An integrated circuit may be evaluated by its tolerance to noise or jitter in a received signal.  An integrated circuit's, and or system's, performance may be measured by measuring a number of erroneous bits (or erroneous data values) that occur during the transfer of a particular number or bits.  This performance metric is known as a Bit-Error-Ratio (“BER”) value. 
An integrated circuit's (or system's) BER value may be measured by an expensive specialized test system.  The cost of the test system and the time required in testing performance of an integrated circuit under a variety of test conditions may significantly contribute to the overall cost of manufacturing the integrated circuit. 
FIG.  1 illustrates a test system 100 for testing a device under test (“DUT”) 140, such as a semiconductor integrated circuit (“IC”).  In particular, test system 100 may be used to obtain a BER value for DUT 140 when particular jitter signals are introduced.  Test system 100 includes a BER test equipment 120, a signal generator 110, a random jitter (“RJ”) source 108, a sinusoidal jitter (“SJ”) source 109, a sum circuit 111 and a backplane 130.  Signal generator 110, source 108 and source 109 may be included in BER test equipment 120. 
In a test mode, DUT 140 is coupled to BER test equipment 120.  One or more receivers 142 of DUT 140 is coupled to one or more transmitters 120A of BER test equipment 120 by way of backplane 130.  One or more transmitters 144 of DUT 140 are coupled to one or more receivers 120B of BERT 120 by way of an interconnect (such as a cable).  Backplane 130 may provide a known deterministic jitter (“DJ”) or noise to data signals transferred from BER test equipment 120 to DUT 140.  Backplane 130 may introduce inter-symbol-interference (“ISI”) which DUT 140 may encounter in a system when receiving and/or transferring data signals. 
Sum circuit 111 sums random noise or an RJ signal and a sinusoidal signal or SJ signal from sources 108 and 109 and outputs a delay control signal.  Signal generator 110 outputs a noisy clock signal (or transmit clock/frequency) to transmitter 120A that outputs a data signal in response to the data value provided by pseudo random bit sequence (“PRBS”) generator 120C.
A “noisy” clock signal is provided to transmitter 120A (or a clock signal that has been modulated with one or more jitter signals) to observe the tolerance of the receivers 142 to jitter (RX JTOL) or BER performance of DUT 140.  For example, data signals are transmitted from BER test equipment 120 to DUT 140 in response to the noisy clock signal.  DUT 140 receives the data and then retransmits the data values (the data values may be first stored in a storage circuit of DUT 140) back to the receiver 120B. A compare circuit 120D then outputs an error signal when the data value from receiver 120B does not match or equal the original transmitted data from PRBS generator 120C (PRBS generator 120C may also include a storage circuit to store data values that were output by transmitter 120A).  A number of bit (data value) errors or error signals per number of data values transmitted/received by BER test equipment 120 equals a BER value corresponding to the RJ, SJ, and DJ that corrupt the data signal. 
It is desirable to measure an integrated circuit's noise tolerance without the use of expensive specialized test equipment.  The elimination and/or reduction of the expensive specialized test equipment then may reduce the cost and time in manufacturing/testing an integrated circuit.