1.  Field of the Invention
The present invention generally relates to a memory controller and a decoder, in particular, to a circuit that may reduce a gate-induced drain leakage (GIDL) current. 
2.  Description of Related Art
A memory is a storage device having advantages such as a fast access speed, and small volume.  Currently, memories have already been widely applied in various electronic devices.  During data read/write processes of a memory, a decoder is required for addressing.  A conventional address decoder is illustrated in the following. 
FIG.  1 is a circuit diagram of a conventional address decoder.  An address decoder 10 is formed of transistors 11-13.  A control signal bMWL may be used to control the ON/OFF of the transistors 11, 12.  A control signal WLRST may be used to control the ON/OFF of the transistor 13.  Thereby, a signal WL is controlled. 
It should be noted that a gate-induced drain leakage current (GIDL) often occurs in the transistor 11.  The GIDL current causes memory chip stand-by current larger.