Digital system architectures commonly include a master processor that delivers commands to a multiplicity of slave processors.  In such architectures, the master processor typically takes charge of the slave processors by delivering high-level commands to those processors.  The slave processors typically enact lower-level control over a system or environment.  For example, in the context of communication equipment, a computer (master processor) may be used to communicate with a plurality of central processing unit (CPU) cards or other devices (slave processors).  The cards or other devices may be held in a chassis or other frame or panel.  A chassis is a structural unit of functional cards or other devices, including a CPU card and a plurality of other cards, such as a media converter card, an alarm card, etc.  A CPU card is used to control the other cards in a chassis. 
To enable the computer to command the plurality of CPU cards, a variety of communication schemes may be employed.  According to one such scheme, the computer may be connected to a first CPU card by a set of serial data communication lines.  The first CPU card is, in turn, connected to a second CPU card by a set of serial data communication lines.  Each of the serial data communication lines connecting the computer to the first CPU card is directly coupled to a corresponding serial data line connecting the second CPU card to the first CPU card.  Thus, both the first and second CPU cards effectively share a common set of serial data communication lines with the computer.  Accordingly, a transmission from the computer is received by both the first and second CPU cards.  If the computer is to exert control over a third CPU card, the third CPU card would be attached via a set of serial data lines to the second CPU card, so that the first, second, and third CPU cards effectively share a common set of serial data communication lines with the computer.  A fourth CPU card would be attached to the third CPU card, and so on.  This sort of scheme is referred to as either a serial multidrop communication link or a daisy chain. 
One shortcoming of the above-described scheme is that because each CPU card receives every transmission emanating from the computer, each CPU card will respond to the computer's commands, unless the computer identifies which CPU card a particular instruction is intended for.  Therefore, an identification code is typically assigned to each CPU card.  The computer addresses a particular CPU card by transmitting a command coupled with an identification code pointing out which CPU card the command was intended for.  All other CPU cards ignore the command. 
Heretofore, the process of assigning an identification code to a particular CPU has been cumbersome and subject to error.  To assign an identification code to a CPU, a set of dip switches must be manually manipulated.  The position of the dip switches determines the identification code.  Manual manipulation of dip switches is time consuming and therefore undesirable.  Further, manual manipulation of dip switches leaves open the possibility of redundant assignment of identification codes, in which case more than one CPU would respond to a particular command.  Such an eventuality could lead to data collisions and other undesirable phenomena on the serial link. 
As is evident from the foregoing discussion, there exists an unmet need for a scheme by which unique identification codes can be assigned to slave processors.  A favorable scheme will require little or no human effort and will ensure that redundant identification code assignment does not occur.