Microelectronic elements often comprise a thin slab of a semiconductor material, such as silicon or gallium arsenide, commonly called a semiconductor wafer.  A wafer can be formed to include multiple integrated chips or dies on a surface of the wafer and/or partly embedded within the wafer.  Dies that are separated from a wafer are commonly provided as individual, prepackaged units.  In some package designs, the die is mounted to a substrate or a chip carrier, which is in turn mounted on a circuit panel, such as a printed circuit board (PCB).  For example, many dies are provided in packages suitable for surface mounting. 
Packaged semiconductor dies can also be provided in “stacked” arrangements, wherein one package is provided, for example, on a circuit board or other carrier, and another package is mounted on top of the first package.  These arrangements can allow a number of different dies to be mounted within a single footprint on a circuit board and can further facilitate high-speed operation by providing a short interconnection between the packages.  Often, this interconnect distance can be only slightly larger than the thickness of the die itself.  For interconnection to be achieved within a stack of die packages, interconnection structures for mechanical and electrical connection may be provided on both sides (e.g., faces) of each die package (except for the topmost package). 
Additionally, dies or wafers may be stacked in a three-dimensional arrangement as part of various microelectronic packaging schemes.  This can include stacking a layer of one or more dies, devices, and/or wafers on a larger base die, device, wafer, substrate, or the like, stacking multiple dies or wafers in a vertical or horizontal arrangement, and various combinations of both.  Dies or wafers may be bonded in a stacked arrangement using various bonding techniques, including direct dielectric bonding, non-adhesive techniques, such as ZiBond® or a hybrid bonding technique, such as DBI®, both available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc.), an Xperi company (see for example, U.S. Pat.  Nos.  6,864,585 and 7,485,968, which are incorporated herein in their entirety). 
There can be a variety of challenges to implementing stacked die and wafer arrangements.  When bonding stacked dies using a direct bonding or hybrid bonding technique, it is usually desirable that the surfaces of the dies to be bonded be extremely flat, smooth, and clean.  For instance, in general, the surfaces should have a very low variance in surface topology and have a low level of impurities, particles, or other residue.  The removal of particles or residues can improve the cleanliness and flatness of the surfaces and the reliability of the bond between the layers, however, the removal of particles and residue can sometimes be problematic.