The invention relates to mobile communications using a selected pair of transmit and receive frequencies and relates to the derivation of transmit and receive frequency steps and digital clock rates from a common crystal reference oscillator. 
It is well known in the art of mobile radiotelephones to employ a receiver for receiving a receive frequency signal while a transmitter simultaneously transmits a transmit frequency signal in the other direction, the transmit frequency being separated from the receive frequency by a constant offset known as the duplex spacing. 
Although the duplex spacing is nominally a constant, it can be a different constant depending on the frequency band in which the mobile phone is operating.  Complications can then arise in constructing mobile phones that operate in more than one frequency band. 
U.S. patent application Ser.  No.  08/795,930 entitled xe2x80x9cTransmit Signal Generation with the Aid of Receiverxe2x80x9d (Dolman) describes the use of the second local oscillator of the receiver as a reference frequency against which a transmit frequency is controlled relative to a receive frequency to achieve either a first or a second duplex spacing.  The Dolman application is hereby incorporated by reference. 
It is also known in the prior art, when packaging two synthesizer PLL circuits into a common integrated circuit, to synchronize or otherwise relate the reference dividers of the two PLLs so that their phase comparators do not mutually interfere.  The Philips UM1005 and 8026 dual synthesizer integrated circuits available on the open market use this technique.  These circuits include the use of fractional-N dividers and programmable loop bandwidth, such as described in U.S. Pat.  Nos.  5,095,288 and 5,180,993 which are hereby incorporated by reference.  Novel ways to employ such synthesizers in dual mode satellite/cellular telephones in order to achieve different tuning step sizes in different frequency bands are described in U.S. Pat.  Nos.  5,535,432 and 5,610,559 which are also hereby incorporated by reference. 
Continuous advances in electronics allow for smaller mobile phones complying with a variety of national and international protocols.  The international mobile phone standard known as GSM in Europe and as PCS 1900 in the USA operates with a transmit/receive duplex spacing of 45 MHz in the European 900 MHz band; 95 MHz in the European 1800 MHz band, and 80 MHz in the U.S. 1900 MHz PCS band.  The channel spacing is 200 KHz (13 MHz/65) and the transmitted symbol rate is 13 MHz/48.  All timing in this standard is related to a 13 MHz clock, as is well known.  The U.S. IS 136 system known as DAMPS operates with a 45 MHz duplex spacing in the US 800 MHz cellular band, and with an 80.4 MHz duplex spacing in the U.S. 1900 MHz PCS band, with a tuning step size of 30 KHz and a transmitted symbol rate of 24.3 Kilosymbols/sec.  In IS 136, as is well known, the tuning step sizes and symbol rates and internal timing are all derivable from a 19.44 MHz clock.  Yet another U.S. standard known as IS95 uses Code Division Multiple Access at a transmitted chip rate of 1228.8 MHz, with a duplex spacing of 45 MHz combined with tuning steps of 30 KHz in the 800 MHz band, alternatively 50 KHz steps combined with 80 MHz duplex spacing in the 1900 MHz band.  In IS95, the chip rate and frequency step sizes are not easily derivable from the same crystal oscillator.  It may be easily understood that combining two or more of the abovementioned protocols in the same handheld unit is hindered by the variety of tuning step sizes, duplex spacings and symbol rates that must be synthesized.  Consequently, there exists a need for an improved radio architecture to facilitate such combination. 
A mobile phone receiver according to the invention comprises a first superheterodyne downconversion means using a first local oscillator frequency which can be tuned in frequency steps by a programmable digital frequency synthesizer phase lock loop (PLL).  The first downconversion means converts received signals to a first intermediate frequency (IF) for filtering.  A second downconversion means using a second local oscillator converts first IF signals to a second IF or to the complex baseband for further filtering and processing.  The second local oscillator is generated using a second digital frequency synthesizer PLL which locks the second oscillator to a crystal reference oscillator.  The crystal reference oscillator provides a buffered clock output signal from which digital logic derives transmit symbol rates and receiver processing sampling rates. 
According to a first aspect of the invention, the second local oscillator provides a buffered output signal at the second local oscillator frequency.  The buffered output signal is used as the reference frequency for the first local oscillator""s synthesizer PLL, thus eliminating the need to distribute the crystal oscillator signal to the first oscillator""s PLL circuit.  According to a second aspect of the invention, the first oscillator PLL comprises a phase comparator to compare the divided down first local oscillator signal with the divided down reference frequency signal from the second local oscillator, the divided down frequencies being equal to the desired receiver frequency tuning steps or a multiple thereof.  It should be appreciated that this frequency would not have been available by dividing down the crystal frequency in an integral ratio without practicing this aspect of the invention. 
According to a third aspect of the invention, a third digital frequency synthesizer PLL controls the transmitter frequency to be equal to the first local oscillator frequency plus or minus a transmit offset frequency.  The transmit frequency can for example be heterodyned with the first local oscillator frequency to produce a transmit offset frequency signal; the transmit offset frequency signal is then divided down in a digital divider and compared with a phase reference frequency which is also derived by dividing the second local oscillator frequency by an integer factor. 
Since according to the third aspect of the invention, the transmit offset synthesizer PLL and the first local oscillator PLL both utilize the second local oscillator as a common frequency reference, they can furthermore be packaged in a common integrated circuit and can share at least part of the reference divider which divides the second local oscillator frequency to produce a first and second phase comparator reference frequency signal for the two PLLs respectively.  The two PLLs"" respective phase comparators are arranged to respond to opposite polarities of a signal at a lowest common multiple frequency of their respective first and second phase comparator reference signals in order to minimize mutual interference between the two PLLs.