The present invention relates to a technique for fabricating a semiconductor device and, more particularly, to a technique effectively applied to a method for forming an insulator, which constitutes the semiconductor device. 
Some semiconductor devices include a MISFET (Metal Insulator Semiconductor Field Effect Transistor) in which two or more gate insulators different in thickness are formed on the same semiconductor substrate.  In general, the MISFET with a relatively thick gate insulator is used as a high breakdown voltage MISFET to which a relatively high voltage is applied. 
In a non-volatile memory such as a flash memory or the like, data is recorded by storing electric charges in an isolated electrode (floating electrode) during the operation of the data writing and deleting.  Therefore, high voltage of, for example, about 20 to 26 V is necessary to introduce the electric charges into the floating electrode.  For this reason, the gate insulator around the MISFET, to which the high voltage is applied, is required to have the thickness capable of withstanding the application of the above high voltage, for example, a thickness of about 20 to 30 nm. 
Note that the technique for forming the gate insulator by the chemical vapor deposition (CVD) method has been described in the gazette of Japanese Patent Laid-Open No.  11-177047 which was filed on Jul. 2, 1999 by the present applicant.  Additionally, the technique described below and examined by the inventors discloses that, by exposing an insulator formed by the CVD method to atomic oxygen (O*) at 400° C., the etching rate of the insulator in a hydrofluoric acid solution can be made equal to that of a thermal oxide. 
The above-mentioned technique is shown in: pp.  42 to 51 (particularly, see FIG.  74 on page 49) in the papers of UCS closing memorial symposium titled “toward the new century led by semiconductor” held on Sep. 24 (Sun) and 25 (Mon), 2000 at Hotel East 21 Tokyo hosted by USC (Ultra Clean Society) Semiconductor Substrate Technology laboratory.