There have been known various technologies for higher memory access efficiency.  For instance, there has been known a memory access device for realizing high transfer efficiency by concealing overhead in memory access, wherein memory access order per memory access request is not rearranged but command generation order per bank unit is rearranged.  Further, there has also been known a data processing device for improving transfer efficiency and realizing higher speed data access, wherein, when an address stored in one buffer and an address stored in another buffer adjoining to the one buffer are compared and the comparison result indicates that successive transfer is possible, addresses and data stored in these buffers are sequentially transmitted to a destination device.  Further, there has also been known a bus arbitration method for executing optimum bus arbitration depending on a use environment, wherein DMA request signals are rearranged in accordance with unique identification numbers, each associated with an order of priority and a DMA request signal highest in the priority of all the rearranged DMA request signals is selected. 
Related technology is disclosed in Japanese Laid-Open Patent Publications Nos.  2006-260472, 2002-304365 and 2005-71186. 
In the above-mentioned memory access device, priority control does not make any sense in case memory access order is rearranged in accordance to transfer address per bank unit, etc. 
Further, as illustrated through image data transfers and the like from a digital still camera, in case of a DMA channel signal with fluctuations in the data transfer amount due to a mixture of periods with many memory access requests and periods with a few memory access requests, system failures could be caused by disruptions in data transfers associated with the DMA channel signal due to the relationship with data transfers associated with the other DMA channel signal.