Charge pumps are used in a variety of signal processing applications, e.g., for converting a DC voltage from one value to another.  Charge pumps may be implemented in various ways.  For example, one approach for doubling a voltage with a charge pump is to connect a voltage across a capacitor to charge the capacitor in a first stage.  Then, using switching circuitry, the capacitor is disconnected from the original charging voltage and reconnected in a second stage, e.g., with its negative terminal coupled to the original positive charging voltage.  Because the capacitor retains the previously stored voltage from the first stage, the effect in the second stage may be to double the voltage.  In this manner, the voltage may be pumped up at each stage.  Other approaches are available for fractionally multiplying or scaling voltage, for inverting voltages, and for multiplying voltages by various integer factors, for example. 
One application of charge pumps is in the context of memory circuits, e.g., dynamic random access memory (DRAM).  In memory circuits, a voltage is applied to a word line that is used to access a circuit component storing memory, e.g., as a bit.  FIG.  1 is a block diagram of a known circuit 100 having a charge pump.  In FIG.  1, a charge pump 110 provides a programmable voltage VPP.  A level detector 120 monitors VPP and detects variation in VPP.  A memory word line may consume energy and cause VPP to decrease, and charge pump 110 may charge to increase VPP.  Level detector 120 also receives a reference voltage VREF, a power supply voltage VDD, and an input signal TRIM that may be used to indicate a target value for VPP, e.g., relative to a power supply voltage VDD.  For example, a target value for VPP may be VDD+0.55 volts.  The particular implementation details of level detector 120 and how TRIM is provided may vary.  Level detector 120 provides an output signal ENABLE that is received by an oscillator 130, which in turn provides a clock signal OSC to charge pump 110 to charge the charge pump. 
Referring to FIG.  2, the operation of known circuit 100 may be understood.  The signal VPP provided by charge pump varies, e.g., increases as charge pump 110 charges and decreases at other times.  Circuit 100 operates to maintain VPP near a target voltage VTARGET.  At time 210, level detector 120 detects that VPP is too low relative to VTARGET and sets ENABLE to logic high (‘1’).  ENABLE may be referred to as a level detector enable signal.  As a result, oscillator 130 provides clock pulses OSC to charge pump 110 to cause the latter to charge, thereby increasing VPP.  At time 220, level detector 120 detects that VPP has reached a high enough value relative to VTARGET and changes ENABLE to logic low (‘0’).  As a result, oscillator 130 stops sending clock pulses OSC to charge pump 110, causing the latter to stop charging, thereby causing VPP to decrease.  At time 230, VPP is again too low, so ENABLE is asserted high by level detector 120, and clock pulses OSC are again provided to charge pump 110.  In the example of FIG.  2, when ENABLE is cut off at time 240 (because level detector 120 determines that VPP is high enough to stop charging), a cycle of OSC is only partially completed.  As used herein, a “cycle” or “pulse cycle” of OSC refers to a high cycle of a pulse OSC, i.e., the portion of a full duty cycle of a pulse that is at high (‘ON’) voltage.  A “full” pulse cycle (or “fully completed” pulse or clock cycle), as opposed to a “partially completed” pulse cycle, refers to a pulse that is not terminated (transitioned to low voltage) prematurely, i.e., before a normal transition time, but rather is transitioned to low after a normal pulse width.  Cutting off OSC before the end of the cycle is reached immediately turns off the charge pump, i.e., causes it to stop charging.