The invention pertains to semiconductor capacitor constructions and to methods of forming semiconductor capacitor constructions.  The invention is thought to have particular significance in application to methods of forming dynamic random access memory (DRAM) cell structures, to DRAM cell structures, and to integrated circuitry incorporating DRAM cell structures. 
A commonly used semiconductor memory device is a DRAM cell.  A DRAM cell generally consists of a capacitor coupled through a transistor to a1 a bitline.  A semiconductor wafer fragment 10 is illustrated in FIG.  1 showing a prior art DRAM array 83.  Wafer fragment 10 comprises a semiconductive material 12, field oxide regions 14, and wordlines 24 and 26.  Wordlines 24 and 26 comprise a gate oxide layer 16, a polysilicon layer 18, a silicide layer 20 and a silicon oxide layer 22.  Silicide layer 20 comprises a refractory metal silicide, such as tungsten silicide, and polysilicon layer 18 typically comprises polysilicon doped with a conductivity enhancing dopant.  Nitride spacers 30 are laterally adjacent wordlines 24 and 26. 
Electrical node locations 25, 27 and 29 are between wordlines 24 and 26 and are electrically connected by transistor gates comprised by wordlines 24 and 26.  Node locations 25, 27 and 29 are diffusion regions formed within semiconductive material 12. 
A borophosphosilicate glass (BPSG) layer 34 is over semiconductive material 12 and wordlines 24 and 26.  An oxide layer 32 is provided between BPSG layer 34 and material 12.  Oxide layer 32 inhibits diffusion of phosphorus from BPSG layer 34 into underlying materials. 
Conductive pedestals 54, 55 and 56 extend through BPSG layer 34 to node locations 25, 27 and 29, respectively.  Capacitor constructions 62 and 64 contact upper surfaces of pedestals 54 and 56, respectively.  Capacitor constructions 62 and 64 comprise a storage node layer 66, a dielectric layer 68, and a cell plate layer 70.  Dielectric layer 68 comprises an electrically insulative layer, such as silicon nitride.  Cell plate layer 70 comprises conductively doped polysilicon, and may alternatively be referred to as a cell layer 70.  Storage node layer 66 comprises conductively doped hemispherical grain (HSG) polysilicon. 
A conductive bitline plug 75 contacts an upper surface of pedestal 55.  Bitline plug 75 may comprise, for example, tungsten.  Together, bitline plug 75 and pedestal 55 comprise a bitline contact 77. 
A bitline 76 extends over capacitors 62 and 64 and in electrical connection with bitline contact 77.  Bitline 76 may comprise, for example, aluminum. 
The capacitors 62 and 64 are electrically connected to bitline contact 77 through transistor gates comprised by wordlines 26.  A first DRAM cell 79 comprises capacitor 62 electrically connected to bitline 76 through a wordline 26 and bitline contact 77.  A second DRAM cell 81 comprises capacitor 64 electrically connected to bitline 76 through wordline a 26 and bitline contact 77.  DRAM array 83 comprises first and second DRAM cells 79 and 81. 
If capacitors 62 and 64 are inadvertently shorted together, a so-called xe2x80x9cdouble bit failurexe2x80x9d will occur.  Such double bit failures can occur if a stray piece of polysilicon, or HSG polysilicon, breaks off during formation of DRAM array 83 and disadvantageously electrically connects capacitors 62 and 64.  Prior art capacitor fabrication methods employ chemical-mechanical polishing (CMP) of HSG polysilicon.  HSG polysilicon pieces can break off during such CMP processes and cause double bit failures.  It would be desirable to develop alternative DRAM constructions which could be formed by methods avoiding double bit failures. 
The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and integrated circuitry For instance, the invention encompasses a method of forming a capacitor wherein a mass of silicon material is formed over a node location, and wherein the mass comprises exposed doped silicon and exposed undoped silicon.  The method can further include substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon.  Also, the method can include forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. 
As another example, the invention encompasses a capacitor having a capacitor dielectric layer intermediate a first capacitor plate and a second capacitor plate, wherein at least one of the first and second capacitor plates has a surface against the capacitor dielectric layer, and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.