1.  Field of the Invention
This invention pertains in general to a semiconductor device and, more particularly, to a silicon bipolar junction transistor for electrostatic discharge protection and methods thereof. 
2.  Background of the Invention
A semiconductor integrated circuit (IC) is generally susceptible an electrostatic discharge (ESD) event, which may damage or destroy the IC.  An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration in which a large amount of current is provided to the IC.  The high current may be built-up from a variety of sources, such as the human body.  Many schemes have been implemented to protect an IC from an ESD event, such as diodes or diode-coupled transistors in radio-frequency (RF) applications. 
In RF applications, an on-chip ESD circuit should provide robust ESD protection, while exhibiting minimum parasitic input capacitance and low voltage-dependency.  In a deep-submicron complementary metal-oxide semiconductor (CMOS) process with shallow-trench isolations (STIs), a diode has been used for ESD protection.  The diode is formed contiguous with either an N+ or P+ diffusion region in a semiconductor substrate.  FIG.  1A shows a cross-sectional view of a known diode ESD protection structure formed in an IC.  Referring to FIG.  1A, a P+ diffusion region is bound by STIs on either side, and therefore the diode is also known as an STI-bound diode.  However, an STI-bound diode has been found to have significant leakage current due to an interference between a silicide layer (not shown) of the P+ diffusion region and the STIs around the P+ region. 
FIG.  1B shows a cross-sectional view of a known polysilicon-bound diode introduced to address the leakage current problem associated with an STI-bound diode.  The P+ diffusion region in the polysilicon-bound diode is defined by a polysilicon gate, and therefore the leakage current from the edges of STIs is eliminated.  However, the total parasitic capacitance of the polysilicon-bound diode is larger than that of the STI-bound diode because of the additional sidewall junction capacitance. 
FIG.  2 is a circuit diagram showing a known ESD protection scheme using a dual-diode structure.  Referring to FIG.  2, the combination of the dual-diode structure and VDD-to-VSS ESD clamp circuit provides a path for an ESD current 2 to discharge to ground, preventing the ESD current 2 from passing through internal circuits.  When the ESD current 2 is provided to a signal pad PAD1, and with a signal pad PAD2 coupled to relative ground, the ESD current 2 is conducted to VDD through a diode Dp1.  The ESD current 2 is discharged to VSS through the VDD-to-VSS ESD clamp circuit and flows out of the IC from the diode Dn2 to the pad PAD2.  Diode Dp1 has a capacitance of Cp1 and diode Dn1 has a capacitance of Cn1.  The total input capacitance Cin of the circuit shown in FIG.  2 primarily comes from the parasitic junction capacitance of the diodes, and is calculated as follows:
Cin=Cp1+Cn1
wherein Cp1 and Cn1 are parasitic junction capacitances of diodes Dp1 and Dn1, respectively. 
In addition, a silicon-controlled rectifier (SCR) has also been implemented for on-chip ESD protection.  A feature of an SCR is its voltage-holding ability, at approximately 1 volt, in a non-epitaxial bulk CMOS process.  In addition, an SCR can sustain high current and hold the voltage across the SCR at a low level, and may be implemented to bypass high current discharges associated with an ESD event.  However, a conventional SCR device has a switching voltage of more than 30 volts in sub-micron CMOS processes, and therefore is not suitable to protect gate oxides in a sub-micron CMOS technology. 
FIG.  3 is a reproduction of FIG.  3 of U.S. Pat.  No.  5,012,317 to Rountre, entitled xe2x80x9cElectrostatic Discharge Protection Circuit.xe2x80x9d Rountre describes a lateral SCR structure made up of a P+ type region 48, an N-type well 46, a P-type layer 44, and an N+ region 52.  According to Rountre, a positive current associated with an ESD event flows through the region 48 to avalanche a PN junction between the well 46 and layer 44.  The current flows from the layer 44 to the region 52 across the PN junction and ultimately to ground to protect an IC from the ESD event.  However, a disadvantage of this known SCR structure is its susceptibility to being accidentally triggered by substrate noise. 
In addition, the p-n-p-n path of an SCR device, such as the device shown in FIG.  3, is blocked by the insulator layer and shallow trench isolations (STIs) in an IC formed with a silicon-on-insulator (SOI) CMOS technology.  Accordingly, SCR devices have been proposed in an integrated circuit based on the SOI CMOS technology.  FIG.  4 is a reproduction of FIG.  4 of U.S. Pat.  No.  6,015,992 to Chatterjee, entitled xe2x80x9cBistable SCR-like switch for ESD protection of silicon-on-insulator integrated circuits.xe2x80x9d Chatterjee describes an xe2x80x9cSCR-like switchxe2x80x9d provided by a first transistor 42 and a second transistor 44, separated from each other by an insulation region 60.  The bistable SCR-like device has two additional lines 62, 64 to electrically connect the separate transistors. 
FIG.  5 is a reproduction of FIG.  8B of U.S. Pat.  No.  5,754,381 (the ""381 patent) to Ker, one of the inventors of the present invention.  The ""381 patent is entitled xe2x80x9cOutput ESD Protection with High-Current-Triggered Lateral SCRxe2x80x9d and describes a modified PMOS-trigger lateral SCR (PTLSCR) structure and NMOS-trigger lateral SCR (NTLSCR) structure.  The ""381 patent describes an NTLSCR 44 modified by an addition of a parasitic junction diode Dp2.  The ""381 patent describes that the modified PTLSCR or NTLSCR structure prevents an SCR from being triggered by a substrate noise current, thereby preventing device latch-up. 
In accordance with the invention, there is provided An integrated circuit device that includes a substrate, a dielectric layer disposed over the substrate, and a layer of silicon, formed over the dielectric layer, including a first portion, a second portion, and a third portion disposed between the first and second portions, wherein the first and second portions are doped with the same type of impurity, and the third portion is doped with a different type of impurity from the first and second portions, and wherein the first, second and third portions form a silicon bipolar junction transistor, the first and second portions being one of collector and emitter, and the third portion being a base of the silicon bipolar junction transistor, to provide electrostatic discharge protection to the integrated circuit device. 
In one aspect, the integrated circuit device further includes an insulating layer disposed between the substrate and the dielectric layer, wherein the integrated circuit device is a silicon-on-insulator device. 
In another aspect, the silicon layer includes a fourth portion disposed between the second and third portions of the silicon layer. 
In yet another aspect, the silicon bipolar junction transistor includes a back-gate adapted to receive a bias voltage to control the silicon bipolar junction transistor in providing electrostatic discharge protection. 
Also in accordance with the present invention, there is provided an integrated circuit device that includes a substrate having a first insulator spaced-apart from a second insulator, and a biasing region disposed between the first and second insulating regions, a dielectric layer disposed over the substrate, and a layer of silicon, formed over the dielectric layer, including a first portion, a second portion, and a third portion disposed between the first and second portions, wherein the first and second portions are doped with the same type of impurity, and the third portion is doped with a different type of impurity from the first and second portions, and wherein the first, second and third portions form a silicon bipolar junction transistor, the first and second portions being one of collector and emitter, and the third portion being a base of the silicon bipolar junction transistor, to provide electrostatic discharge protection to the integrated circuit device. 
In one aspect, the third portion of the silicon layer is disposed above the biasing region of the substrate to receive a bias voltage coupled from the biasing region. 
In another aspect, the substrate includes a biasing pad for receiving a biasing voltage to bias the biasing region, wherein the biasing pad is contiguous with one of the first and second insulators. 
In yet another aspect, the third and fourth portions of the silicon layer are disposed above the biasing region of the substrate for receiving a bias voltage coupled from the biasing region. 
Further in accordance with the present invention, there is provided an integrated circuit device receiving signals from a signal pad that includes at least one silicon bipolar junction transistor responsive to the signals from the signal pad for providing electrostatic discharge protection, and a detection circuit for detecting the signals from the signal pad and providing a bias voltage to the at least one silicon bipolar junction transistor, wherein the at least one silicon bipolar junction transistor includes an emitter, collector and base formed in a single silicon layer and isolated from a substrate of the integrated circuit device, and wherein the base is coupled to the detection circuit to receive the bias voltage. 
In one aspect, the at least one silicon bipolar junction transistor further comprises a back-gate, wherein the back-gate is coupled to the detection circuit to receive the bias voltage. 
In another aspect, the detection circuit comprises a resistor-capacitor circuit having a delay constant shorter than the duration of the signals from the signal pad. 
Additionally in accordance with the present invention, there is provided a method for protecting a semiconductor device from electrostatic discharge that includes providing a substrate, providing a dielectric layer disposed over the substrate, providing a silicon bipolar junction transistor formed in a layer of silicon over the dielectric layer, biasing the silicon bipolar junction transistor to provide electrostatic discharge protection. 
In one aspect, the method also includes providing a back-gate in the silicon bipolar junction transistor to receive a bias voltage to control the silicon bipolar junction transistor in providing electrostatic discharge protection. 
Additional objects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.  The objects and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims. 
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed. 
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description, serve to explain the principles of the invention.