1.  Field of the Disclosure
The present disclosure generally relates to electronic circuits having an analog comparator and also relates to integrated circuit devices and designs including an analog comparator circuit. 
2.  Description of the Related Art
In electronic designs and circuits, the amplitude of a signal level frequently has to be determined with a specified degree of accuracy.  For this purpose, a plurality of techniques have been developed, wherein many of these techniques include the comparison of a first signal level with a second signal level in order to decide whether the first signal level is higher or lower compared to the second signal level.  Thus, a respective electronic circuit may provide a digital response to the question of which of two signals has a higher signal level.  Corresponding electronic circuits may typically be referred to as a comparator or as an analog comparator, when at least one of the two signal levels may vary continuously.  For instance, such comparator circuits may be significantly used in situations in which a signal is to be compared with a reference signal, which may represent a substantially constant reference or a varying reference, so as to indicate by a digital response when the signal crosses the threshold defined by the reference signal.  A comparator circuit typically comprises an appropriately designed input stage, including a pair of input transistors, which may receive the respective input signals.  Furthermore, a resistive load may be connected to each of the input transistors to obtain a differential voltage, depending on the difference of input signals.  The differential voltage may be supplied to an output stage, which is typically designed to provide two predefined output signal levels depending on the voltage across the differential input stage.  Consequently, for sophisticated applications, the characteristics of the circuit elements, in particular of the input transistors and the respective resistive loads, may have to be matched to each other to obtain a change of the output signal at a desired minimum value of the difference of the two input signals.  Moreover, the response of the comparator circuit to input signal should typically be as stable as possible for varying operational conditions, such as different temperatures, varying supply voltages, aging of the circuit components, and any other environmental influences, such as humidity, pressure and the like.  Consequently, complex compensation techniques have been proposed, which in turn may itself require sophisticated and complex analog circuitry, which may contribute to overall design complexity and production costs. 
With reference to FIGS.  1a-1b, a typical conventional comparator circuit will now be described so as to more clearly discuss any problems caused by an inefficient offset compensation. 
FIG.  1a schematically illustrates a circuit diagram of a comparator circuit 100 according to a conventional basic circuit configuration.  As illustrated, the comparator circuit 100 comprises an input stage 110 for receiving a first input signal V− and a second input signal V+.  The signal V− may be received by a first input transistor 111A, while the second input signal V+ may be received by a second input transistor 111B. In the example shown in FIG.  1a, the first and second input transistors 111A, 111B may be represented by a P-channel transistor or by a PNP transistor, if a bipolar transistor configuration is considered.  It should be appreciated that transistors of a different conductivity type may be used, if desired.  Furthermore, the input stage 110 comprises a first resistive load 112A connected in series to the first transistor input 111A and also comprises a second resistive load 112B connected in series to the second transistor input 111B. Additionally, the input stage 110 may comprise a constant current source 113 connected to both branches comprised of the first input transistor 111A and the first resistive load 112A and the second input transistor 111B and the second resistive load 112B, respectively.  Moreover, the voltage across one of the resistive loads 112A, 112B may be used as an intermediate output signal 114 that is supplied to an output stage 120.  In the example shown, the intermediate output signal 114 of the input stage 110 may be obtained across the resistive load 112B. Furthermore, the output stage 120 is typically appropriately configured so as to settle in one of two output voltage levels, for instance near the positive supply voltage or the negative supply voltage, depending on the intermediate signal 114.  For convenience, the output stage 120 is illustrated as an inverting amplifier with a very high gain so as to saturate at one of the voltage levels, depending on the intermediate signal 114, thereby providing the digital response to the input signals V− and V+.  In this case, the second input transistor 111B may be referred to as a non-inverting input transistor, while the first input transistor 111A may be referred to as an inverted input, since a higher signal level at the input transistor 111A may result in a swing of the output 121 to the negative level. 
During operation of the comparator circuit 100, the constant current source 113 supplies a constant current to the node 113A, which may result in a current flow through the transistors 111A and the load 112A on the one hand and through the transistor 111B and the load 112B on the other hand.  Consequently, if the respective components 111A, 111B, 112A, 112B and 113 are provided as substantially ideal components, a small difference, indicated as ΔV may result in a corresponding variation of the output voltage 114, since, in this case, the conductivity of one branch may be reduced or increased, thereby creating respective different currents in both branches, since the current supplied to the node 113A is maintained constant.  As a consequence, the intermediate output voltage 114 may vary in accordance with the difference of the supplied input voltage so that the output stage 120 may go into positive saturation or negative saturation, depending on the sign of the difference of the input voltages V−, V+. 
FIG.  1b schematically illustrates the diagram in which the output voltage 121 of the output stage 120 is qualitatively plotted against the difference of the input voltages V+, V−. It may be assumed that the difference ΔV may vary between −500 millivolts and +500 millivolts, while the output stage 120 may saturate at +3 volts and −3 volts.  It should be appreciated, however, that any other voltage ranges for the input voltage and the output voltage may be selected, depending on the device requirements, wherein typically at least the output voltage range may be substantially determined by the supply voltage of the comparator 100.  As illustrated for a negative value of the difference ΔV, i.e., where V− is greater than V+, the output voltage 121 may be approximately −3 volts.  When reducing the absolute amount of V− or by increasing the amount of V+, the difference ΔV may be less negative and may finally result in a change of polarity of the output voltage 121, while, in the example shown, the difference ΔV may still be negative.  The value of the threshold level T, at which the output voltage 121 changes, may depend on the overall configuration of the comparator 100 and in particular may depend on the characteristics of the input stage 110.  Thus, depending on non-uniformities, which may be caused during the fabrication of the device 100 or which may be caused by varying conditions during the operation, such as a change in temperature and the like, the value of T may also vary, thereby resulting in a non-stable response of the comparator circuit 100 with respect to the input voltage difference ΔV.  The amount of change in T from its ideal value is called offset voltage.  Consequently, for obtaining a substantially stable response of the comparator 100, compensation techniques are frequently used to reduce the offset voltage of the input stage 110 to achieve the ideal value of the threshold T, wherein the corresponding compensation techniques require more or less effort, depending on the degree of uniformity or stability desired.  In other cases, the circuitry of the input stage 110 itself may be configured such that an increased level of stability may be accomplished, which may typically require significant effort in terms of additional analog circuit components and/or process techniques and calibration procedures. 
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.