1.  Field of the Invention
This invention relates to a semiconductor memory device having at least one memory cell including a trench capacitor and a surrounding gate transistor acting as a switching transistor of the trench capacitor. 
2.  Description of the Related Art
Recently, an SGT cell (Surrounding Gate Transistor Cell) having a capacitor and a transistor stacked in a vertical direction along a silicon column is proposed.  The cell structure has an advantage that the element area of the memory cell can be set within one bit line contact. 
However, if this type of cell structure is made with the dimensions (0.15 to 0.20 .mu.m) of 1-Gbit DRAM, the aspect ratio (height/width) of the silicon column is set to 50 to 60 (for example, the height is 9 .mu.m and the width is 0.15 .mu.m).  Therefore, there occurs a possibility that the silicon column falls down and is destroyed by the stress generated in the process.  Further, if the height is reduced with the width kept unchanged in order to reduce the aspect ratio, a sufficiently large capacitance cannot be obtained, and on the other hand, if the width is increased with the height kept unchanged, a sufficiently large capacitance can be obtained, but the cell area is increased. 
As another structure, a memory cell structure as shown in Japanese Patent Disclosure (KOKAI) No.  63-29571 is known.  In this structure, a vertical MOS transistor is formed on a trench capacitor.  With this cell structure, it is possible to simultaneously attain reduction in the aspect ratio of the silicon column and formation of a capacitor of sufficiently large capacitance.  However, in order to form the above cell structure, it is necessary to use the laminating technique using a laminated substrate, it is difficult to align the capacitor and the transistor with each other, and the manufacturing cost rises.  Further, in this cell structure, since the channel portion of the transfer gate is set in an electrically floating state, generated holes have no place to escape, making it impossible to cut off the transistor.