The exemplary embodiments of the invention relate to a lock-less buffer management scheme for multi-cell support on a single modem board using a multi-core processor.  While the invention is particularly directed to the art of wireless telecommunications, and will be thus described with specific reference thereto, it will be appreciated that the invention may have usefulness in other fields and applications. 
By way of background, LTE (Long Term Evolution) is a rapidly evolving 3GPP project that aims to improve the UMTS (Universal Mobile Telecommunications System) mobile phone standard to cope with future communication network demands.  LTE improves wireless network efficiency and bandwidth, lower costs and enhance services experience.  Specifically, LTE makes use of new spectrum opportunities and offer better integration with other open standards.  LTE generally includes an LTE RAN (Radio Access Network) (also known as E-UTRAN) along with an EPS (Evolved Packet System, also called Evolved Packet Core). 
Communication systems are generally split into two primary functions: data plane functions and control plane functions.  In previous LTE products, at least two processors were used on the modem board: one to support the control plane functions (non-real time, e.g., Operations, Administration, and Management (or OA&M), and call processing management-related functionalities), and another to terminate and support the data plane functions (real time, e.g., LTE Layer 2 processing).  Both the control and data planes used different operating system (OS) instances, such as Linux for the control plane and a real-time OS such as vXWorks (made and sold by Wind River Systems of Alameda, Calif.) for the data plane core.  Typically, one modem board supports one sector or cell.  So to support multi-cell (e.g., 3-cells or 6-cells) configurations, it would be necessary to provide as many modem boards as the number of cells. 
A multi-core processor may be used in an LTE wireless base station on a modem board.  An operating system such as SMP Linux with PREEMPT_RT patch running on one SMP partition that contains all eight cores.  In this configuration the control plane (non-real time threads/processes) and the data plane (real time threads/processes) share the same operating system instances even though they are bound to run on different cores. 
Thus, there is a need for a buffer management scheme that is lock-less, otherwise unbounded latency spikes may result.  Such a situation could seriously jeopardize or break down the LTE Layer 2 real-time processing needs.  In an SMP environment, a lock taken by a non-real-time process or thread on one core may cause a latency spike for a real time thread or process waiting for that lock to be released on a different core.