Programmable logic devices (“PLDs”) are a well-known-type of integrated circuit that can be programmed to perform specified logic functions.  One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles.  These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAM”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth.  Notably, as used herein, “include” and “including” mean including without limitation. 
One such FPGA, the Xilinx Virtex® FPGA, is described in detail in pages 3–75 through 3–96 of the Xilinx 2000 Data Book entitled “The Programmable Logic Data Book 2000” (hereinafter referred to as “the Xilinx Data Book”), published April, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.  Young et al.  further describe the interconnect structure of the Virtex FPGA in U.S. Pat.  No.  5,914,616 B1, issued Jun. 22, 1999 and entitled “FPGA Repeatable Interconnect Structure with Hierarchical Interconnect Lines”. 
Another such FPGA, the Xilinx Virtex®-II FPGA, is described in detail in pages 33–75 of the “Virtex-II Platform FPGA Handbook”, published December, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124.  And yet another such FPGA, the Xilinx Virtex-II Pro™ FPGA, is described in detail in pages 19–71 of the “Virtex-II Pro Platform FPGA Handbook”, published Oct. 14, 2002 and available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. 
Another type of PLD is the Complex Programmable Logic Device, or CPLD.  A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix.  Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices.  Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device.  These PLDs are known as mask programmable devices.  PLDs can also be implemented in other ways, for example, using fuse or antifuse technology.  The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.  For purposes of clarity, FPGAs are described below though other types of PLDs may be used. 
Heretofore, unidirectional segmented data busing was employed in FPGAs.  However, this meant that two separate buses for reading and writing were used.  This consumes a significant amount of semiconductor area.  Accordingly, it would be desirable and useful to provide segmented data busing that uses less busing resources.