The present invention relates to the fabrication of heterostructures formed by bonding a first wafer or substrate to a second wafer or substrate, the first wafer having a thermal expansion coefficient that is lower than the thermal expansion coefficient of the second wafer.  Such heterostructures are particularly used in microelectronics or optoelectronics.  The invention is particularly applicable to the fabrication of SOS heterostructures, where SOS stands for silicon-on-sapphire (Al2O3). 
During the assembly of two wafers having different thermal expansion coefficients, for example different by at least 10% or 20% at room temperature (20° C.), or during any subsequent processing of the two assembled wafers, there may be times when the assembly is subjected to increased temperatures, for example, during heat treatments such as those conventionally conducted to strengthen the bond interface in the case of a bond-strengthening anneal. 
FIG.  1 illustrates the behaviour of a heterostructure during a bond-strengthening anneal carried out at a temperature of about 160° C., the heterostructure being formed by bonding a first wafer or substrate 10 corresponding to an SOI (silicon-on-insulator) structure to a sapphire second wafer or substrate 20.  As shown in FIG.  1, the difference between the thermal expansion coefficient (TEC) of silicon, the principal component of the SOI structure, and that of sapphire (Si TEC<Al2O3 TEC) leads, during a heat treatment, to a deformation of the assembly such that high debonding stresses Cd are applied in regions Zd located at the edges of the heterostructure. 
Because of these stresses there is insufficient transfer at the edge of the wafers, leading to the appearance of a ring (a region in which the first wafer has not transferred onto the second wafer) that is too large and irregularly shaped and that can, in particular, lead to the wafer edges peeling off. 
In the case of heterostructures such as SOS heterostructures, the latter are fabricated by assembling a structure, for example an SOI structure, onto a support wafer or substrate such as a sapphire substrate.  In this case, the fabrication of the SOS heterostructure comprises the direct wafer bonding or a fusion bonding of the SOI structure to the sapphire wafer, a bond-stabilizing or bond-strengthening anneal and a thinning of the SOI structure to form a silicon layer transferred onto the sapphire wafer.  The thinning is typically carried out in two steps, namely a first, grinding step of removing most of the support substrate of the SOI structure followed by a second step of chemically etching as far as the oxide layer of the SOI structure, the oxide layer playing the role of stop layer.  The chemical etch is typically carried out using a TMAH (tetramethylammonium hydroxide). 
The generation of debonding stresses at the edge of substrates, as explained above, may lead to debonding at the edges of the silicon layer and the sapphire substrate allowing the wet etchant to infiltrate into the bond interface during thinning.  This infiltration further weakens the bond and can lead to delamination of the structure as shown in FIG.  2 where a delamination of the silicon surface layer from the underlying sapphire substrate or wafer is observed when a shear stress is applied to the silicon layer. 
Finally, as shown in FIG.  3, edge loss, i.e., the enlargement of the ring due to delamination, is already present after grinding.  Edge loss is due to delamination during the bond-strengthening anneal and is all the larger because, during the bond-strengthening anneal, the silicon is relatively thick. 
Accordingly, improvements in the fabrication of heterostructures are needed to avoid these problems, and the present invention now provides such improved processes.