The present invention relates to integrated circuit devices and more particularly to integrated circuit devices including test circuits and methods for testing the same. 
Integrated circuit (semiconductor) memory devices, such as dynamic random access memories (DRAMs) and/or application specific integrated circuit (ASIC) are generally tested before being shipped to customers.  Such devices are generated first through a design process followed by manufacturing based on the design and then testing of the device during manufacture and/or after the manufacturing process is completed.  Such testing operations prior to shipment may include integrated circuit chip testing and/or package testing.  The testing process may include a test of macro block(s) of the device in various test modes.  A macro block may be a programmable intellectual property (IP) core.  Examples of such IP cores include a micro controller unit (MCU), a digital signal processor (DSP) and/or other cores used for a particular function. 
Methods of testing a programmable IP core can be classified as one of two types.  One type of such testing is a conventional dynamic simulation test method in which fault coverage is heightened by operating a functional vector using fault simulation software, such as Verifault™ available from Cadence Software Inc. A second type of such testing is a serial test method, such as a full scan test method, that uses a scan test circuit included in the integrated circuit device. 
One advantage of the conventional dynamic simulation test method is that, as a scan test circuit is not required on the device, a smaller sized chip may be used for the device.  However, the fault coverage of the dynamic simulation test method is generally lower than the serial test method.  In addition, if the programmable IP core is tested using the conventional dynamic simulation test method, a common test vector usable for any integrated circuit device including the programmable IP core is needed rather than a test vector for only a particular integrated circuit device.  As different integrated circuit devices typically have different methods for generating an input/output (IO) address, memory maps, pads, and/or peripheral interfaces, defining a common test vector may be difficult and may be limited in the conditions tested using the common test vector on a particular integrated circuit device.  Therefore, programmable IP cores are generally configured to include a scan test circuit for performing the full scan test method. 
If the integrated circuit device including the programmable IP core is designed to support the full scan test method of the device, it may be tested using the scan test circuit included in the programmable IP core.  If the integrated circuit device including the programmable IP core is not designed to support the full scan test of the device, the device may still be tested using the conventional dynamic simulation test method without needing to use the scan test circuit of the IP core. 
If an integrated circuit device including the programmable IP core is not designed to be generally adaptable for full scan testing as a whole, but only the programmable IP core or elements except for the programmable IP core are designed to be adaptable for full scan testing, all input and output signals of the programmable IP core typically have to be output to an external pin of the integrated circuit device.  However, such a signal routing may be difficult as the number of input and output signals of the programmable IP core may be greater than the number of external pins of the device.  In such a design, a chain-shaped scan test circuit may be added to input and output terminals of the programmable IP core.  Test vectors are loaded to the chain-shaped scan test circuit in series or output signals to the output terminal are captured in the chain-shaped scan test circuit in series. 
FIG.  1 is a block diagram of a conventional integrated circuit device.  As shown in FIG.  1, an integrated circuit device having a conventional scan test circuit generally includes a first sub logic circuit unit 110, a core block 130, and a second sub logic circuit unit 150.  The first sub logic circuit unit 110 receives and processes input data MDI and the core block 130 receives and processes data SL1 through SLN output from the first sub logic circuit unit 110.  The second sub logic circuit unit 150 receives and processes data CD1 through CDN output from the core block 130 and outputs output data MDO. 
FIG.  2 shows an example of each port included in a peripheral scan test circuit (not shown in FIG.  1) around the core block 130 when the first and second sub logic circuit units 110 and 150 of FIG.  1 are designed to be adaptable for a scan test method.  As shown in FIG.  2, if the first and second logic circuit units 110 and 150, but not the core block 130, are designed to be adaptable for the full scan test method, two multiplexers (MUX) 213 and 217 and one flip-flop 215 are generally required for each port of the scan test circuit near output and input terminals of the core block 130.  The two multiplexers 213, 217 and flip-flop 215 may operate to determine observability for normal operations of the core block 130 and the first and second sub logic circuit units 110 and 150 by using serial output data TDO.  They may also operate to determine controllability for the core block 130 by using data SD input to the core block 130 or the second sub logic circuit unit 150 responsive to serial input data TDI.  The flip-flop 215 operates in synchronization with a system clock signal SCLK. 
For the circuit of FIG.  2, if the number of input and output ports of the core block 130 is 100 each, 400 MUXes and 200 flip-flops are required.  The MUX control signal TM is activated or deactivated depending on whether a scan test is being performed.  The MUX control signal TM is also activated or deactivated depending on whether serial input data TDI used as a serial test vector is being input to the scan test circuit or whether an output of the first sub logic circuit unit 110 or the core block 130 is being input to scan test circuit. 
FIG.  3 shows an example of each port included in the scan test circuit, near the input terminal of the core block 130, when only the core block 130 is designed to be adaptable for the scan test method.  A shown in FIG.  3, if only the core block 130 is designed to be adaptable for full scan testing, it is generally only required for the scan test circuit to determine controllability for the core block 130 by using data S1D output to the core block 130 responsive to the serial input data TDI.  Thus, one MUX 315 and one flip-flop 313 are typically required for each port included in the scan test circuit, near the input terminal of the core block 130.  The flip-flop 313 operates in synchronization with the system clock signal SCLK.  Thus, if the number of input and output ports is 100 each, 100 MUXes and 100 flip-flops are needed when using the circuit of FIG.  3. 
FIG.  4 shows another example of each port included in the scan test circuit, near the output terminal of the core block 130, when only the core block 130 is designed to be adaptable for the scan test method.  FIG.  4 is similar to FIG.  3.  However, for the circuit of FIG.  4, the scan test circuit is required to determine only observability for a normal operation of the core block 130 by using serial output data TDO.  Therefore, one MUX 413 and one flip-flop 415 are typically required for each port in the scan test circuit in the output terminal of the core block 130.  The flip-flop 415 operates in synchronization with the system clock signal SCLK and the output data S2D for each port is input to the second sub logic circuit unit 150.  If the number of input ports is 100 and is the same as the number of output ports, 100 MUXes and 100 flip-flops are needed using the circuit of FIG.  4. 
As discussed above, if the integrated circuit device as a whole is not designed to be adaptable for the full scan test method, the device may be tested using only the conventional dynamic simulation test method.  If only the programmable IP core is designed to be adaptable for the scan test method, or only other elements and not the core block are designed to be adaptable for the scan test method, a scan test circuit may be provided for each input port or output port around the programmable IP core. 
As also described above, it may be difficult to create a common test vector that can be used by any device including the programmable IP core, rather than a vector designed for a particular integrated circuit device including the programmable IP core, to compensate for a low fault coverage.  In addition, as a scan test circuit may need to be provided for each input port and/or output port around the programmable IP core, the integrated circuit device, in addition to common features like a data bus, an address bus, and the like, may have to include hundreds of MUXes and flip-flops of the scan test circuits.  As a result, the size of the integrated circuit device may be undesirably increased.