1.  Field of the Invention
The invention relates in general to a method of fabricating a self-aligned silicide (salicide), and more particularly, to a method of fabricating a spacer without causing bridging effect between salicide. 
2.  Description of the Related Art
Due to the higher and higher device integration of semiconductors, the linewidth and patterned of devices are formed smaller and smaller.  The shrinkage of the linewidth causes the resistance of a polysilicon gate (poly-gate) of a metal-oxide semiconductor (MOS) and the conductive wires of a device or a circuit increases greatly.  An RC-delay is thus induced.  To adjust the resistance, methods such as the formation of a salicide has been widely applied in VLSI or ULSI circuit.  In the convention method of forming a salicide layer one or more than one metal layer is formed on a silicon surface.  By performing a thermal process, the metal layer reacts with the silicon to form a silicide layer.  Or alternatively, a silicide layer is formed to cover a silicon surface directly.  The metal silicide has a better conductivity than silicon.  Therefore, an improved electric operation is obtained for the poly-gate and the conductive wires formed by the conductive layer comprising silicon and metal silicide. 
FIG.  1A and FIG.  1B are cross sectional views showing a conventional method for fabricating a salicide laver on a silicon or polysilicon surface to reduce the device resistance. 
In FIG.  1A, a substrate 10 having a MOS device is provided.  The MOS device comprises a source/drain region 19 in the substrate and a gate 12 on the substrate 10.  The gate 12 and the substrate 10 are isolated with each other by a gate oxide layer 11.  The gate 12 further comprises a side wall covered by a spacer 16.  A metal layer 20 is formed on the MOS device. 
In FIG.  1B using rapid thermal process, the metal layer 20 reacts with the silicon of the poly-gate 12 and the source/drain region 19 to form a metal silicide layer 22 on both the poly-gate 12 and the source/drain region 19.  The metal layer 20 which did not react with silicon completely is then removed by wet etching. 
In the above method silicon atom of the substrate 10 is very likely to diffuse onto the spacer 16 during the rapid thermal process to form a metal silicide on the spacer 16.  Therefore, a bridging effect between the substrate 10 or the source/drain region 19 and the poly-gate 12 is caused.  The bridging effect leads to an unexpected electric connection to cause a short circuit.