1.  Field of the Invention
The invention relates generally to the field of Static Random Access Memories (SRAM's).  The invention relates more specifically to multi-port SRAM arrays. 
2b.  Cross Reference to Related Applications
The following copending U.S. patent applications are owned by the owner of the present application and their disclosures are incorporated herein by reference:
(A) Ser.  No.  08/996,049 filed Dec. 22, 1997 by Om P. Agrawal et al and originally entitled, DUAL PORT SRAM MEMORY FOR RUN-TIME USE IN FPGA INTEGRATED CIRCUITS. 
3.  Description of the Related Art
Static Random Access Memory cells (SRAM cells) have bi-stable storage loops that can store data without need for periodic refresh.  Because of this, SRAM cells can be used for outputting stored data at relatively high speed.  In contrast, Dynamic Random Access Memory cells (DRAM cells) require periodic refreshing of their capacitively-stored data.  This need for periodic refreshing may prevent DRAM systems from providing read information immediately upon request. 
As such, SRAM cell arrays are often used for servicing high-speed, digital storage functions.  Even though comparative DRAM arrays generally have lower per-bit cost and lower per-per-cell size as compared to that of SRAM cell arrays, the refresh-free aspect of SRAM cell arrays makes the latter more attractive for certain applications. 
There is a subset of applications wherein the data of an SRAM array is simultaneously shared by a plurality of data-requesting circuits.  Each such data-requesting circuit may need rapid and independent, data-reading access to a respectively addressed part of the data stored in the shared array.  Multiple-port systems have therefore been developed to allow each of plural, data-accessing circuits to independently supply a read address to a shared SRAM cell array for the purpose of quickly retrieving its desired data. 
It is desirable to be able to also write initial and revised data into the shared SRAM array.  However, the multi-port nature of a shared SRAM array raises special problems because contention may occur if multiple ports simultaneously try to write to a same memory area.  Another problem with multi-port SRAM systems is that the paths for multiple and independent write circuits may consume excessive circuit space.  A particular arrangement is disclosed herein that allows for multiple and independent write circuits without consuming excessive amounts of additional circuit space.