A loop-back test has been used to evaluate operation of input and output (I/O) terminal operation of large scale integrated (LSI) circuits.  Executing a loop-back test for memory in some forms is difficult, however.  For example, such testing is difficult for memory in non-component form applied to devices combined into a system-in-package (SIP), a memory having a large number of I/Os, or a high speed memory, as it is difficult to configure on an externa, test equipment or an external test board.  When the memory is configured for SIP, a number of memory I/Os cannot be subjected to direct testing via external test equipment because of accessibility and because the large number and the density of the external I/O connections.  To provide test equipment that could configure a loop-back test would require undesirable enlargement of the SIP system and significant cost.  Such enlargement would result from providing reliable physical connectivity to the I/O terminals or from accommodating additional terminals or special circuitry for generating and gathering test data of the I/O circuits under test. 
For multiple memory systems such as high bandwidth memory (HBM), where naked DRAMs are stacked and mounted with a memory controller together on a substrate, such as a silicon (Si) interposer, it is difficult and resource expensive to reliably configure and carry out a probe test of, for example, an 8-channel, stacked memory subsystem, when the test interface to the I/Os can include 1280 or more micro-bumps (μ-bumps) of 25 μm diameter.