1.  Field of the Invention
The present invention relates to semiconductor memory, and more particularly to a memory device structure for a virtual ground memory array. 
2.  Description of the Related Art
Nonvolatile memory retains stored data when power is removed, which is required or at least highly desirable in many different types of computers and other electronic devices.  Nonvolatile semiconductor memory devices are generally divided into two main classes.  The first class is based on the storage of charge in discrete trapping centers of a dielectric layer of the structure.  The second class is based on the storage of charge on a conducting or semiconducting layer that is completely surrounded by a dielectric, typically an oxide. 
A common type of stored charge device is the stacked gate transistor, also known as a floating gate transistor, in which cell programming is performed through channel hot-electron injection (“CHE”).  An illustrative self-aligned double-polysilicon stacked gate structure 1 is shown in FIG.  1.  A floating gate 14, typically a doped polysilicon layer, is sandwiched between two insulator layers 12 and 16, typically oxide.  The top layer of the stack is a control gate electrode 10, typically a doped polysilicon layer.  The stacked gate structure is shown symmetrically overlying a heavily doped n+ source region 20 and a heavily doped n+ drain region 22, as well as a channel region between the source region 20 and the drain region 22.  The channel region is part of a p-well 28, which also contains the source region 20, the drain region 22, and a heavily p+ doped contact region 24.  The p-well 28 is contained within an n-well 30, which also contains a heavily n+ doped contact region 26.  The n-well 30 is in turn contained in the p-type substrate 32.  When high voltages are applied simultaneously to the both the drain 22 and the gate 10 of cell of FIG.  1, the high voltage across the drain-to-source produces a high channel current and channel field that generate hot electrons in a pinch off region near the drain 22 (as indicated by wedge-shaped region and the notation e−).  The high voltage on the control gate 10 couples a voltage to the floating gate 14 that attracts the hot electrons, effectively injecting them into the floating gate (as indicated by the upward-turned arrows adjacent the e− notation). 
The self-aligned double-polysilicon stacked gate structure 1 shown in FIG.  1 has been used in a contactless configuration to achieve high memory density levels.  FIG.  2 is a schematic diagram showing a basic virtual ground array architecture 100 that uses a cross-point array configuration defined by continuous buried n+ diffusions that form the bitlines or columns, illustratively C+2, C+1, C0 and C−1 in FIG.  2, and WSi2/Poly control gate wordlines or rows, illustratively R+1, R0 and R−1 in FIG.  2.  Metal is used to contact the bit line periodically, for example every sixteenth word line, to reduce bit line resistance.  Due to elimination of the common ground line and the drain contact in each memory cell, extremely small cell size is realized.  Programming, erasing and reading of the memory cells is obtained by the use of asymmetrical floating gate transistors or on suitable source and drain decoding.  A great many virtual ground array architectures and nonvolatile semiconductor memory devices have been developed, as exemplified by the following patents: U.S. Pat.  No.  6,175,519, issued Jan. 16, 2001 to Liu et al.;  U.S. Pat.  No.  5,959,892, issued Sep. 28, 1999 to Lin et al.;  U.S. Pat.  No.  5,646,886, issued Jul. 8, 1997 to Brahmbhatt; and U.S. Pat.  No.  5,060,195, issued Oct. 22, 1991 to Gill et al. 
Examples of one type of asymmetrical floating gate transistor and of a virtual ground memory array incorporating it are disclosed in U.S. Pat.  No.  5,418,741, issued May 23, 1995 to Gill.  Each shared column line has two junctions for each pair of memory transistors that share the column line.  One junction is graded for source regions and the other is graded for drain regions.  The deep source regions are graded, i.e. gradually sloped, to minimize programming at the source junction region, while the relatively shallow drain regions are abrupt, i.e. steeply sloped, to improve the injection efficiency of the device.  The bit line is formed by the shallow drain region implant, which is an n+ implant.  Due to the different junction characteristics of adjacent cells, the programming of one cell is said not to disturb the state of the immediately adjacent cell. 
Even with the use of asymmetrical floating gate transistors, the programming of cells in the array using CHE requires careful biasing schemes on the bit lines to reduce the disturb voltage on an adjacent cell sharing the same bit line.  Generally, CHE programming of a floating gate transistor is achieved by applying high positive voltages on both the control gate and the drain, so that both the vertical and lateral components of the electric field are high enough to make efficient CHE injection.  The use of an abrupt drain junction and the higher drain voltage improved the efficiency of electron injection, and the use of thin tunnel oxide and high control gate bias is effective for attracting hot electrons to the floating gate.  Nonetheless, further improvements in asymmetrical floating gate transistor structure is desirable so that schemes for counter-biasing the bit lines may be simplified.