Q:

How do MIPS exceptions and interrupts work? 

I am working on a MIPS32 like CPU and I am wondering how the MIPS32 exception and interrupt handling works exactly.  The MIPS32 Privileged Resource Architecture guide doesn't give much information.  I am wondering about several things which are:

What happens if there is an exception or interrupt in an exception or interrupt handler? 
MIPS32 has 5 hardware interrupts and 2 software interrupts in the cause register.  Are the software interrupts exceptions or are exceptions just shown in the exception code value? 
Is there a different interrupt and exception vector? 
What happens if there are 2 exceptions that go off in the pipeline before it clears itself for the exception?  For example there is an overflow exception followed by another exception, and an interrupt.  What happens? 

Links to any useful resources will be appreciated. 

A:

Exception handlers should not re-enable exceptions until after they have saved EPC, SR etc. 
The software interrupts are exceptions. 
Some MIPS CPUs have been built with different interrupt and exception vectors, but this turns out not to be very useful. 
MIPS has precise exceptions: i.e. exceptions appear in instruction sequence and only the first exception in the pipeline will be architecturally visible. 

See MIPS Run Linux is the best and most readable reference for MIPS exceptions and the MIPS PRA. 