Not Applicable
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The present invention relates to circuits for providing electrical isolation and more particularly, to optical isolation circuits (hereinafter referred to as xe2x80x9copto-isolatorxe2x80x9d circuits), that are compatible with the Inter-Integrated Circuit (referred to hereinafter as xe2x80x9cI2Cxe2x80x9d) communication protocol.  The I2C bus is a bidirectional, two-wire communication architecture that was developed to provide communications among integrated circuit (xe2x80x9cICxe2x80x9d) devices, and is well known to those in the art.  The I2C protocol is essentially a master/slave system, where a master station broadcasts a request for information, addressed to a particular slave, over a single physical wire.  Slave stations continuously monitor the wire for such broadcasts directed to them; when a slave detects that it is being addressed, the slave responds to the request at a predetermined time after the master as finished transmitting.  In this way, only one transmitter is using the wire at a time, all under the control and direction of the master station.  The standard data rate is 100,000 bits per second, which can be escalated to 400,000 bits per second in the fast mode.  There is no particular limit to the number of devices that can be connected to the I2C bus, as long as the maximum bus capacitance of 400 pF is not exceeded. 
FIG.  1 shows a battery monitoring application in which the I2C bus may be used.  In this application, a large number of individual cell modules 20 (e.g., 30 or more modules) are connected in series to form a high voltage battery 10.  Each of the cell modules 20 includes a voltage cell 22, along with a power monitor module 24 associated with the cell 22.  In one embodiment, the cell includes a NiMH cell, although other technologies for generating voltage known to those in the art may also be used. 
The power monitor module 24 determines various parameters of the associated cell 22 and reports those parameters via an I2C bus 30.  Each module provides a data input/output (xe2x80x9cI/Oxe2x80x9d) port 32, a clock I/O port 34, and a local ground 36.  The data I/O 32 and the clock I/O 34 are referenced to the local ground 36.  Thus, in the embodiment shown in FIG.  1, a large number of individual cell modules 20, all connected at different voltage levels, provide information about the constituent cells.  Because the cell modules 20 are stacked, i.e., connected in series, a differential voltage exists between the output signals of the modules.  As an example, assume that each cell 22 produces 10.8 VDC, and the battery 10 includes 30 such cells.  Thus, the voltage differential between the cell module 20 at the top of the series and the cell module 20 at the bottom of the series is 324 volts. 
A battery monitor module 40 communicates with the individual modules 20 via an I2C bus 42.  However, since the individual modules 20 all operate at different voltage levels, the data 32 and clock 34 outputs cannot be commonly connected.  Accordingly, the data 32 and clock 34 outputs can only be tied to a common bus after they have been isolated from one another via an isolation device 50 as shown in FIG.  1.  One prior art device used to provide isolation between circuits that operate at different voltage levels is an opto-isolator.  However, prior-art opto-isolator circuits can not accommodate the unique characteristics of the I2C communications protocol. 
It is an object of the present invention to substantially overcome the above-identified disadvantages and drawbacks of the prior art. 
The foregoing and other objects are achieved by the invention which in one aspect comprises an opto-isolator circuit for providing isolation between a bidirectional, I2C transmission line and a pair of single-direction transmission lines.  The opto-isolator circuit includes a bi-directional port for receiving data from, and providing data to, the bi-directional transmission line.  The circuit further includes an output path that has (i) a first buffer for receiving outgoing data from the bi-directional port, (ii) a first opto-isolator for receiving the outgoing data from an output of the first buffer, and (iii) a second buffer for receiving the outgoing data from an output of the first opto-isolator and providing the outgoing data to an output port.  The circuit also includes an input path, that has (i) a third buffer for receiving incoming data from an input port, (ii) a second opto-isolator for receiving the incoming data from an output of the third buffer, and (iii) a fourth buffer for receiving the incoming data from an output of the second opto-isolator.  The fourth buffer provides the incoming data to the bi-directional port such that characteristics of the incoming data are compatible with I2C characteristics. 
In another embodiment of the invention, the bidirectional port is at a voltage level corresponding to a logic high when a voltage level corresponding to a logic high is applied to the input port, and the bi-directional port is at a voltage level corresponding to a logic low when a voltage level corresponding to a logic low is applied to the input port. 
In another embodiment of the invention, the output port is at a voltage level corresponding to a logic high when a voltage level corresponding to a logic high is applied to the bi-directional port, and the output port is at a voltage level corresponding to a logic low when a voltage level corresponding to a logic low is applied to the bi-directional port. 
In another embodiment of the invention, the first buffer includes a tri-state buffer having (i) a high-impedance enable input electrically coupled to the bi-directional port, (ii) an output electrically coupled to the first opto-isolator, and (iii) an input electrically coupled to a reference voltage corresponding to a logic high state. 
In another embodiment of the invention, the second buffer includes a tri-state buffer constructed and arranged such that the output of the tri-state buffer is in a high-impedance state when the first opto-isolator presents a voltage corresponding to a logic high state to the input of the second buffer.  The output of the tri-state buffer is at a voltage level corresponding to a logic low state when the first opto-isolator presents a high impedance state to the input of the second buffer, and the output of the tri-state buffer is electrically coupled to the output port. 
In another embodiment of the invention, the third buffer includes a tri-state buffer having (i) a high-impedance enable input electrically coupled to the input port, (ii) an output electrically coupled to the second opto-isolator, and (iii) an input electrically coupled to a reference voltage corresponding to a logic high state. 
In another embodiment of the invention, the fourth buffer includes a tri-state buffer constructed and arranged such that its output is at a voltage level corresponding to a logic high when the second opto-isolator presents a voltage corresponding to a logic high state to the input of the fourth buffer.  The output of the tri-state buffer is at a voltage level corresponding to a logic low state when the first opto-isolator presents a high impedance state to the input of the fourth buffer, and the output of the tri-state buffer is electrically coupled to the bi-directional port. 
In another aspect, the invention includes a method of providing isolation between a bi-directional, I2C transmission line and a pair of single-direction transmission lines.  The method includes providing a bidirectional port for receiving data from, and providing data to, the bi-directional transmission line.  The method further includes providing an output path, including (i) a first buffer for receiving outgoing data from the bi-directional port, (ii) a first opto-isolator for receiving the outgoing data from an output of the first buffer, and (iii) a second buffer for receiving the outgoing data from an output of the first opto-isolator and providing the outgoing data to an output port.  The method also includes providing an input path, including (i) a third buffer for receiving incoming data from an input port, (ii) a second opto-isolator for receiving the incoming data from an output of the third buffer, and (iii) a fourth buffer for receiving the incoming data from an output of the second opto-isolator.  The fourth buffer provides the incoming data to the bi-directional port such that characteristics of the incoming data are compatible with I2C characteristics.