The present invention relates to the manufacture of integrated circuits. 
Lithography is a means by which the surface geometry of integrated circuit components is defined photographically.  The surface of a substrate is coated with a photosensitive layer of photoresist.  When exposed to light through a master pattern on a photographic plate, or mask, the photoresist undergoes chemical changes.  The exposed layer can then be removed using a chemical developer, causing the pattern in the mask to appear on the substrate. 
During the set-up of photoresist processes, two parameters are commonly taken into account.  The first of these is ES, the so-called xe2x80x9cexposure to sizexe2x80x9d.  This is the exposure, or total energy of light, required to define a feature at its target size.  In other words, for light of any given intensity, ES is proportional to the length of time required to expose enough resist to light that when the resist is developed the mask pattern is exactly reproduced at the substrate. 
The second parameter is EO, which is the exposure required to just clear an xe2x80x9copen fieldxe2x80x9d area, i.e., an area without any critical patterns and thus one which would not be affected by diminishing aerial image intensity as pattern size approaches the imaging wavelength.  In other words, EO is the exposure required so that the chemical change in the resist only just penetrates down to the substrate when light is shone on a large area. 
A commonly used metric in the set-up of photoresist processes in integrated circuit manufacture is the ratio ES/EO, and a safe margin typically quoted for ES/EO is 1.4.  The drawback with this metric is that when the developer is working with very small features, particularly holes or gaps, the exposure EO ceases to be a useful parameter. 
The present invention recognizes the importance of a different metric in the definition of patterns, particularly holes or gaps.  This metric is ES/EC, where EC is the exposure needed to just clear a critical feature at high resolution, in other words, the exposure required so that the chemical change in the resist only just penetrates down to the substrate when light is shone on the area of a small feature only.  Typically, for contemporary lithography at 365 nm exposure in integrated circuit manufacture, EO will diverge from EC at pattern sizes below 0.5 xcexcm. 
According to the invention there is provided a method for manufacturing integrated circuits, comprising the steps of coating a substrate with resist, exposing the resist to light through a pattern in a mask so as to define apertures in the resist corresponding to the pattern in the mask, chemically developing the resist after exposure to light, and choosing the thickness of the resist so as to achieve the desired profile of the apertures defined in the resist. 
Preferably, the thickness of the resist is chosen so as to maximize the ratio between the exposure needed to define a feature at its target size (ES) and the exposure needed to just clear said feature (EC). 
At least one of the features in the pattern in the mask may have a width of 0.5 xcexcm or less. 
The light may have a wavelength of the order of 365 nm. 
The resist is preferably photoactive. 
The substrate is preferably transparent, and may be formed from silicon nitride or an oxide of silicon. 
In practice most lithography is performed on transparent substrates, and if this is the case, then the xe2x80x9cswing curvexe2x80x9d of the substrate and the resist layer are important.  Swing curves arise from interference effects from reflections at boundaries, and result in the profile of the slot etched in the resist varying sinusoidally with resist thickness or substrate thickness.  Preferably, therefore, the thickness of the resist is chosen such that the lithography process operating point is insensitive to substrate thickness changes.  This may be achieved by the thickness of the resist being chosen near the turning point of the substrate swing curve which corresponds to minimum reflectivity during the development process. 
The technique is particularly applicable to those critical features which form xe2x80x9cgapsxe2x80x9d or xe2x80x9cholesxe2x80x9d as opposed to xe2x80x9clinesxe2x80x9d in patterns.  Several critical layers processed in advanced processes are of this type and include active area, contacts and holes in complementary metal oxide semiconductor (CMOS) processes and emitters in bipolar processes.