1.  Field of the Invention
The present invention concerns memory apparatus, and more particularly, the invention relates to memory apparatus using semiconductors. 
2.  Related Background Art
With the development of information and video industries, media and apparatus for storing information have vigorously been developed these last years.  Among others, memory apparatus utilizing semiconductors, such as DRAM (Dynamic Random Access read/write Memory) and SRAM (Static Random Access read/write Memory), are applied to devices in many fields, because they have large memory capacities though compact in size, light in weight, and low in operation power and because they permit high-accuracy memory and can be read at high speed. 
Further, attention has recently been drawn to a type of programmable and information-retainable memory apparatus popularly called "flash memory".  It is pointed out that this memory apparatus can be improved more in respect of degree of integration than the above DRAM. 
Further, OT-PROM (one time PROM (Programmable Read-Only Memory)), which permits only one writing, different from the flash memory, is proposed in Japanese Laid-Open Patent Application No.  62-188260 and Japanese Laid-Open Patent Application No.  62-49651 corresponding to U.S. Ser.  No.  749,082 filed Jun. 25, 1985).  In the structures disclosed in these applications, a wiring metal is connected in series with the main electrode (the source or the drain in the case of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or the emitter in the case of a bipolar transistor) of a transistor through a Si region the crystal structure of which is destroyed, or through an a-Si layer.  Storage operation Is carried out by changing the Si region or the a-Si layer from a high-resistance state into a low-resistance state. 
However, the memory apparatus using semiconductors, such as DRAM, has the following matters desired to be improved. 
1.  The semiconductor memory apparatus represented by DRAM and SRAM increases an increase rate of chip cost with an increase in memory capacity and has a higher bit cost than floppy disks, magnetic tapes, and CD-ROM.  Therefore, the semiconductor memory apparatus is not available for practical and easy use as a memory medium yet. 
2.  The current level of memory capacity under research and development is the 256 M-bit level, which is an insufficient information amount to actually handle images. 
3.  For storing information in DRAM or SRAM, a power supply is necessary, and thus, for example, applications to portable devices include a difficult aspect, considering the need to secure the power supply.  At present a built-in battery is used in such applications in addition to a battery for driving device. 
As for the flash memory, superior in respect of the degree of integration to the above DRAM, etc.,  the following matters are desired to be improved:
1.  Since the FN tunnel current or hot electron injection, etc.,  is used for writing or erasing a charge in a floating gate, reliability of an insulating layer for input and output of charge will be degraded with an increase of the number of usage times. 
2.  FN tunnel current density J is expressed by the following equation when an electric field applied to the above insulating layer is E: EQU J=.alpha. E.sup.2 exp(-.beta./E) (1)
In the equation, a and B are constants. 
From Eq. ( 1), a large current flows when the intensity of the electric field is high.  The electric current exponentially decreases with a change of the potential of the floating gate described above.  Thus, writing period and erasing period per bit are long, about 100 .mu.s to 10 ms, thus degrading operability of the memory apparatus. 
3.  The above FN tunnel current strongly depends upon the quality and the thickness of the above insulating layer, and thus, there is the problem of variations in suitable writing periods and erasing periods between samples or between bits.  For this reason, actual practice is to classify memory chips into a plurality of groups at a checking step after fabrication of the chips and to operate the memories at suitable timings for the respective groups.  This results in a great deal of extra work in the checking step, which tends to increase the cost. 
4.  The area of the above floating gate decreases with an increase of the capacity.  This decreases the capacitance of the floating gate in proportion, so that even a little leakage current may cause a great change in the floating gate potential.  Therefore, there is a limit on the permissible decrease in the area of the floating gate in order to ensure a desired capacitance, which is a governing factor in increasing the storage capacity. 
Further, the above OT-PROM permitting only one-time writing is excellent in properties of keeping states after writing permanently unchanged and stabilized, but it requires, for example, an a-Si layer and a contact region between the a-Si layer and wiring for every bit.  In the semiconductor process formation of contact holes is more difficult than formation of linear patterns.  The contact size, if using the 0.8 .mu.m rule process, is in the level of 1 .mu.m.sup.2 (1 .mu.m.times.1 .mu.m), up to about 20 percent more than.  Since the wiring width needs to be increased more as compared with the contact holes, the desired decrease in the area per bit cannot be achieved.  It thus becomes difficult to increase the memory capacity with these memories which have been proposed.  Further, because a large current flows in the above a-Si layer in writing operation, dissipation power is high and applications to portable devices are difficult, which were the points desired to be improved.