Peripheral Component Interconnect (PCI) is a parallel bus architecture developed in 1992 which as become the predominant local bus for personal computers and similar platforms.  The implementation of this technology has come close to its practical limits of performance and can not easily be scaled up in frequency or down in voltage.  A new architecture utilizing point-to-point transmission, having a higher speed, and which is scalable for future improvements, is known as PCI Express. 
In accordance with PCI bus specifications, WRITE commands take precedence over READ commands.  This is summarized in Table 2-23: Ordering Rules Summary Table of the PCI Express Base Specification, Rev. 1.0.  Thus, if a READ command is held up in a queue because the device to be read is busy, for example, a WRITE command made subsequently will be processed before the READ command.  Given the fact that a bridge coupled to a PCI bus does not know which device generated the data, if one PCI device coupled to the bus is actively sending out WRITE commands, it can block the READ commands of another PCI device on the bus, thereby increasing its latency. 
PCI Express provides a way to overcome this limitation by providing for traffic classes.  The classes consist of 3 bits located in the header of a packet being sent over a PCI Express fabric.  READ and WRITE commands for each traffic class are treated independent of these commands for other classes.  Section 2.5 of the PCI Express Base Specification, Rev. 1.0 discusses a PCI Express Virtual Channel (VC) mechanism which provides support for carrying throughout the PCI Express fabric traffic that is differentiated using TC (traffic class) labels.  In order to provide flexibility in the design of equipment, the PCI Express standard sets up rules for the implementation of traffic classes, but makes support for traffic classes beyond TC0 optional.  The standard allows user to decide how the TCs will be utilized. 
A PCI Express to PCI bridge will allow PCI devices to be connected to a PCI bus in a PCI Express architecture.  FIG.  1 shows a block diagram of a computer system 100 implementing a standard PCI Express to PCI bridge 112.  The bridge is coupled by lines 108 to a PCI Express switch 106, which is coupled by lines 104 to CPU 102.  The PCI Express switch is also coupled via lines 110 to other devices (not shown).  The PCI bus 114 is connected to the bridge and to two PCI applications 116, 120 respectively.  Each of the applications has request/grant lines 118 and 122 respectively.  Assume that PCI application (device) 120 generates a READ command which is stored in a PCI FIFO queue (not shown) in bridge 112.  The device to be read is busy so the command is held to be retried (a common situation).  Later, PCI application 116 generates a WRITE command which enters the queue, while the READ command for application 120 is still pending.  The bridge will process the WRITE command before the READ command even if the device to be read now becomes available and even if application 120 has been waiting a long time for a response whereas application 116 has just generated its WRITE command.  Thus, the latency for application 120 will suffer.