Q:

In FSMs does one State last one clock cycle or more? 

Need to design a simple one for school.  
More specifically a Moore FSM.  Im not sure how state transitions happen, is it next state each clock? 
I need to know because im wondering if i can shift a register and add a value to it, all in the same state... Could use wave edges? 
EDIT:
I have to design the ALU part with registers as a schematic from gate-level, so no target CPU. 
I made the algorith diagram, then put states to function blocks according Moore FSM rules.  each block of operations gets one state.  
For instance in a state S1, i have the following operations: y0 = shift Reg1 left; y1 = Reg1 = Reg1 + Reg2.  So the microcommand that the control part of Moore FSM outputs would be 0000011 (yn...y1,y0).  this microcommand should be the input to the ALU part which i need to design.  Now i realized y1,y0 will conflict eachother, since both are using Reg1.  
Its problematic since I dont actually have the Control part, I have to imagine the core FSM and design only the ALU with registers.  This is why i was wondering if i get more than one clock cycle, so i can sequence y0,y1 or do i have to complete the entire operation in one clock? 
I plan on making parallel-in, parallel-out non-shift registers, obviously i cant do the two operations of the microcommand at the same time.  So what can i do: 
1.  make extra states?  which i really dont want to do
2.use edges of a single clock? ( might cause problems?) 
3.Assume i get a preset amount of ticks from the clock to complete the microcommand ? 
This would make the most sense, but i dont know if its the case. 
The control unit does "know" the algorithm and thus how many operations need to be performed

I have to note again, that the control part is totally abstract and i have no idea how this is handled in practice.  

A:

A FSM itself has no inherent notion of time (although it can be defined).  A Moore machine is simplified model and lacks the ability to even formally represent an ever progressing "time" (without, of course, implementing the counting entirely with states); remember, there is only a finite set of states. 
In any case, time can be introduced in an implementation detail of a particular FSM and the amount of time might required to change between particular states might not be constant. ( A particular FSM might also map differently to different implementations.)  In the case of a clocked system it would require looking into how each "clock" is defined in the implementation; it might be leading edge, trailing edge, both, or something entirely different. 
Instead of looking at the FSM here for guidance (it is just the logical progression of states), look at the opcodes (or whatever the implementation is) that the FSM represents, and how the CPU (or whatever the implementation is) in question "executes" them. 
(What do the books say? ;-)