Integrated circuits in general, and CMOS devices in particular, have continued to gain wide spread usage as user demands for increased functionality and enhanced benefits continues to increase.  In order to meet this demand, the integrated circuit industry continues to decrease the size of circuit structures in order to place more circuits in the same size integrated circuit area thereby continuously increasing the packing density for a given chip size.  Over the last several years, structures have gone from 1.2 micron gate areas (1 Meg capacity) in the past, down to gate structure areas of 0.25 microns (256 Meg capacity) currently and promise to become even smaller in the near future. 
The ever increasing demand for computer memory to facilitate calculations and data storage have fostered intense development efforts in the area of Dynamic Random Access Memory (DRAM).  The DRAM is generally a collection of transistor devices with each having an integrated circuit capacitor typically connected to its source electrode thereby forming a memory cell.  This collection of memory cells is then arranged into a memory structure using a word line and a bit line to address each memory cell.  This integrated capacitor may store an electrical charge to represent a logical "1" or store no electrical charge for a logical "0" as instructed by the word and bit control lines. 
Construction of these memory capacitors consists of using typically a tungsten (W) plug structure for 0.25 micron technology connected to the source of the transistor, which then supports a barrier layer, a bottom electrode, a dielectric material, such as tantalum pentoxide and then a top electrode in sequence. 
As the size technology of CMOS devices continues to shrink, the structure for a given memory size or circuit capability also shrinks as noted above.  However, the bond pads which allow the integrated circuit to connect to external circuitry cannot continue to shrink indefinitely.  Currently, an integrated circuit package may have about 200 bond pads that are 50 microns by 50 microns in size.  Shrinking topology coupled with this bond pad lower limitation results in an excess of empty space around the bond pads.  This allows for the inclusion of additional embedded memory around the bond pads. 
In an attempt to add the above-mentioned memory in certain conventional CMOS technologies, some manufacturers have used titanium (Ti) to form a barrier layer with a titanium nitride (TiN) lower electrode in conjunction with the use of tantalum pentoxide (Ta.sub.2 O.sub.5) as the dielectric layer of the capacitor.  Unfortunately, however, in these cases, the edges of the Ti/TiN is exposed and in contact with the Ta.sub.2 O.sub.5 which causes the Ti to chemically reduce the Ta.sub.2 O.sub.5 creating electrical leakage paths or shorts.  This results in general circuit performance degradation or failure. 
Accordingly, what is needed in the art is a CMOS structure and a process of fabrication therefore in which embedded memory can be added without substantial changes in the fabrication processes typically used to manufacture CMOS technologies.