1.  Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to dielectric materials that have reduced dielectric constants. 
2.  Description of the Related Art
Interconnect structures of integrated circuits (ICs) generally take the form of patterned metallization lines that are used to electrically interconnect devices and to provide interconnection with external circuitry.  By way of example, IC devices may include metal oxide semiconductor ("MOS") devices having diffused source and drain regions separated l)y channel regions, and gates located over the channel regions.  In practice, an IC chip may include thousands or millions of devices such as MOS transistors. 
Conventionally, a dielectric layer is deposited over the devices and via holes are formed through the dielectric layer to the devices below.  After the via holes are etched through the dielectric layer, a metallization layer is deposited over the dielectric surface filling the via holes to define metal filled contacts.  After the first metallization layer has been deposited, it is patterned to form interconnect metallization lines.  As is well known in the art, "patterning" may be accomplished by depositing a photoresist layer, selectively exposing the photoresist to light, developing the photoresist to form an etch mask, etching the exposed metallization to pattern the metallization layer, and removing the etch mask.  This process may then be repeated if additional layers of metallization lines are desired. 
As the demand for faster, more complex and compact IC chips increases, the performance of the interconnects has become increasingly important.  Although individual transistor speeds have continued to improve by implementing shorter gate lengths and less resistive gate electrodes, improvements in interconnect structure speed has lagged. 
As is well known in the art, the speed of interconnect structures is generally characterized in terms of RC delays (i.e., resistance/capacitance timing delays).  Therefore, efforts at reducing RC delays in interconnect structures have involved experimentation with dielectric materials to reduce capacitance and with metals to reduce resistance.  As is well known in the art, different metals have different resistivities, and each have different IC fabrication benefits and drawbacks.  By way of example, the resistance of copper (Cu) and silver (Ag) are relatively lower than aluminum (Al), but these metals are known to be more susceptible to corrosion.  In addition, lowering the resistance of metal interconnect lines typically does not result in as great a benefit as reducing interconnect capacitance since all metals have relatively low resistance. 
As is well known in the art, the capacitance associated with an interconnect structure is directly proportional to the dielectric constant (.di-elect cons..sub.o) of the dielectric layer lying between the "plates" of the capacitor, i.e., adjacent metallization layers (i.e., C.alpha..di-elect cons..sub.o).  Therefore, interconnect capacitance may be reduced by lowering the dielectric constant of the material lying between metallization lines.  Conventionally, silicon dioxide having a dielectric constant of about 4.1 or greater is used to isolate the various interconnect metallization lines in IC chips.  However, there have been various unsuccessful attempts at reducing capacitance by developing low dielectric materials.  Such materials include organic-type dielectrics which have dielectric constants between about 2.0 and 4.0. 
Unfortunately, the use of organic-type dielectrics present various fabrication difficulties.  By way of example, fabrication difficulties may include excessive moisture uptake, increased susceptibility to sodium contamination, and a lack of global planarization schemes available to planarize organic-type dielectric materials.  As a result, many IC manufacturers avoid excessive cost and time consuming fabrication processes associated with organic-type dielectrics. 
In addition, as device dimensions continue to decrease, fabrication engineers have been implementing high density plasma (HDP) oxide deposition techniques.  HDP oxide is used because of its good ability to fill-in high aspect ratio regions between, for example, adjacent metallization lines.  FIG.  1A is a cross-sectional view of a semiconductor device that implements an HDP oxide 14.  For example, a substrate 10 is shown having patterned metallization lines 12, which define high aspect ratio regions.  The HDP oxide 14 thus fills these regions without causing well known voids in between the lines.  The process of depositing the HDP oxide 14 requires a special HDP chamber and is relatively slower than other oxide deposition techniques.  In addition, the HDP oxide 14 leaves pyramids 14 over the metallization lines 12.  Accordingly, fabrication engineers typically prefer to deposit another layer of oxide 16 over the HDP oxide 14.  Oxide layer 16 is typically formed using a plasma enhanced chemical vapor deposition (PECVD) process, which is configured to deposit the oxide at a faster rate than the HDP oxide 14. 
A known problem with the device structure having the oxide layer 16 is that mobile ions easily migrate through the oxide layer 16 and HDP oxide 14 and end up trapped in the gate oxides (not shown) of transistor devices.  The most common mobile ions are sodium and potassium ions, and once they migrate to and contaminate the gate oxides, the transistor devices fail to operate at their optimum design levels.  Once the oxide layer 16 is deposited, a chemical mechanical polishing (CMP) operation is performed to substantially planarize the top surface of the oxide layer 16 as shown in FIG.  1B.
As the need for faster integrated circuit devices continues to increase, fabrication engineers will also continue to push for new ways of decreasing the dielectric constant of the oxide materials.  To this end, the HDP oxide 14 is now being deposited in the form of a fluorinated silica glass (FSG) layer, which has a lower dielectric constant of about 3.5.  Although the FSG layer absorbs very little moisture from the atmosphere, when the material is subjected to the CMP process as shown in FIG.  1B, the moisture in the exposed and unexposed FSG layer reacts with the fluorine, which results in the formation of hydrofluoric acid (HF).  As is well known, the presence of HF can be very detrimental because it can migrate to metallization interconnect lines and cause corrosion.  If the metallization lines become corroded, the electrical performance of the entire semiconductor device can suffer greatly, and in fact, it may fail to operate within specification and thus will result in substantial yield loss.  In addition, moisture in the FSG layer also has the possibility of causing metal delamination. 
In the past, techniques used to remove moisture in the FSG layer included, for example, performing nitrogen plasma treatments.  Nitrogen plasma treatments are typically done in expensive HDP chambers and the typical duration of the treatment lasts approximately one minute.  This, of course, presents a significant impact on throughput as wells as increases fabrication costs.  Nitrogen plasma treatments also result in some incorporation of nitrogen into the FSG layer, which may increase the dielectric constant.  Another attempted solution included depositing a silane oxide (stochiometric or silicon rich) layer on top of the FSG layer in an effort to prevent moisture penetration into the FSG layer.  However, stochiometric oxide does not have good moisture barrier properties.  In addition, if the oxide is silicon rich, the dielectric constant of the combined oxide dielectric will also increase, thus raising the over all capacitance. 
In view of the foregoing, there is a need for semiconductor fabrication techniques that enable the implementation of low dielectric constant dielectrics, while avoiding the possibility of device failures induced by CMP operations.