1.  Technical Field
The present invention relates generally to integrated circuits and, in particular, to the configuration of connections in a 3D stack of integrated circuits. 
2.  Description of the Related Art
Three-dimensional (3D) stacked chips include two or more electronic integrated circuit chips stacked one on top of the other.  The chips are connected to each other with chip-to-chip interconnects that could use C4 or other technology, and the chips could include through-Silicon vias (TSVs) to connect from the one side of the chip to active electronics on the opposite side of the chip.  The active electronics can be located on the front side or the back side.