1.  Field of the Invention
The present invention relates to semiconductor memory devices and, specifically, to a clock synchronized type semiconductor memory device which operates in synchronization with externally applied clock signals.  More specifically, the present invention relates to a structure of a semiconductor memory device containing a cache, in which a dynamic random access memory (DRAM) having a large storage capacity serving as a main memory, and a static random access memory (SRAM) having small storage capacity serving as a cache memory are integrated on the same semiconductor chip. 
2.  Description of the Background Art
Historical Review on Memory Environment in a Conventional Data Processing System
(i) Usage of Standard DRAM as a Main Memory
Operation speed of recent 16-bit or 32-bit microprocessing unit (MPU) has been so much increased as to have operation clock frequency as high as 25 MHz or higher.  In a data processing system, a standard DRAM (Dynamic Random Access Memory) is often used as a main memory having large storage capacity, since cost per bit is low.  Although access time in the standard DRAM has been reduced, the speed of operation of the MPU has been increased much faster than that of the standard DRAM.  Consequently, in a data processing system using the standard DRAM as a main memory, increase of wait state is inevitable.  The gap in speed of operation between MPU and the standard DRAM is inevitable because the standard DRAM has the following characteristics. 
(1) A row address and a column address are time divisionally multiplexed and applied to the same address pin terminals.  The row address is taken in the device at a falling edge of a row address strobe signal/RAS.  The column address is taken in the device at a falling edge of a column address strobe signal/CAS.  The row address strobe signal/RAS defines start of a memory cycle and activates row selecting circuitry.  The column address strobe signal/CAS activates column selecting circuitry.  Since a prescribed time period called xe2x80x9cRAS-CAS delay time (tRCD)xe2x80x9d is necessary from the time the signal/RAS is set to an active state to the time the signal/CAS is set to the active state, there is a limit in reducing the access time, namely, there is a limit derived from address multiplexing. 
(2) When the row address strobe signal/RAS is once raised to set the DRAM to a standby state, the row address strobe signal/RAS cannot fall to xe2x80x9cLxe2x80x9d again until a time period called a RAS precharge time (tRP) has lapsed.  The RAS precharge time is necessary for surely precharging various signal lines in the DRAM to predetermined potentials.  Due to the RAS precharge time TRP, the cycle time of DRAM cannot be reduced.  In addition, when the cycle time of the DRAM is reduced, the number of charging/discharging of signal lines in the DRAM is increased, which increases current consumption. 
(3) The higher speed of operation of the DRAM can be realized by circuit technique such as improvement of layout, increase of degree of integration of circuits, development in process technique and by applicational improvement such as improvement in the method of driving.  However, the speed of operation of the MPU is increased at much faster rate than DRAM.  The speed of operation of semiconductor memories is hierarchical.  For example, there are high speed bipolar RAMs using bipolar transistors such as ECLRAMs (Emitter Coupled RAM) and Static RAM, and relatively low speed DRAMs using MOS transistors (insulated gate type field effect transistors).  It is very difficult to expect the operation speed (cycle time) as fast as several tens ns (nano seconds) in a standard DRAM formed of MOS transistors. 
There have been various applicational improvements to stop the gap between speed of operations of the MPU and the standard DRAM.  Such improvements mainly comprise the following two approaches. ( 1) Use of high speed mode of the DRAM and interleave method (2) External provision of a high speed cache memory (SRAM). 
The first approach (1) includes a method of using a high speed mode such as a static column mode or a page mode, and a method of combining the high speed mode and the interleave method.  in the static column mode, one word line (one row) is selected, and thereafter only the column address is changed successively, to successively access memory cells of this row.  In the page mode, one word line is selected, and then column addresses are successively taken by toggling the signal/CAS to successively access memory cells connected to the selected one word line.  In either of these modes, memory cells can be accessed without toggling the signal/RAS, enabling higher speed accessing than the normal access using the signals/RAS and/CAS. 
In the interleave method, a plurality of memories are provided in parallel to a data bus, and by alternately or successively accessing the plurality of memories, the access time is reduced in effect.  The use of high speed mode of the DRAM and combination of the high speed mode and the interleave method have been known as a method of using the standard DRAM as a high speed DRAM in a simple and relatively effective manner. 
The second approach (2) has been widely used in a main frame art.  A high speed cache memory is expensive.  However, in the field of personal computers in which high performance as well as low cost are desired, this approach is employed in some parts of the field with a sacrifice of cost.  There are three possible ways to provide the high speed cache memory.  Namely,
(a) the high speed cache memory is contained in the MPU itself;
(b) the high speed cache memory is provided outside the MPU; and
(c) the high speed cache memory is not separately provided but the high speed mode contained in the standard DRAM is used as a cache (the high speed mode is used as a pseudo cache memory).  When a cache hit occurs, the standard DRAM is accessed in the high speed mode, and at the time of a cache miss, the standard DRAM is accessed in the normal mode. 
The above mentioned three ways (a) to (c) have been employed in the data processing systems in some way or other.  In most MPU systems, the memories are organized in a bank structure and interleaving is carried out on bank by bank basis in order to conceal the RAS precharge time (TRP) which is inevitable in the DRAM, in view of cost.  By this method, the cycle time of the DRAM can be substantially one half that of the specification value. 
The method of interleave is effective only when memories are sequentially accessed.  When the same memory bank is to be continuously accessed, it is ineffective.  Further, substantial improvement of the access time of the DRAM itself cannot be realized.  The minimum unit of the memory must be at least 2 banks. 
When the high speed mode such as the page mode or the static column mode is used, the access time can be reduced effectively only when the MPU successively accesses a certain page (data of a designated one row).  This method is effective to some extent when the number of banks is comparatively large, for example 2 to 4, since different rows can be accessed in different banks.  When the data of the memory requested by the MPU does not exist in the given page, it is called a xe2x80x9cmiss hitxe2x80x9d (cache miss).  Normally, a group of data are stored in adjacent addresses or sequential addresses.  In the high speed mode, a row address, which is one half of the addresses, has been already designated, and therefore possibility of xe2x80x9cmiss hitxe2x80x9d is high. 
When the number of banks becomes as large as 30 to 40, data of different pages can be stored in different banks, and therefore the xe2x80x9cmiss hitxe2x80x9d rate is remarkably reduced.  However, it is not practical to provide 30 to 40 banks in a data processing system.  In addition, if a xe2x80x9cmiss hitxe2x80x9d occurs, the signal/RAS is raised and the DRAM must be returned to the precharge cycle in order to re-select the row address, which sacrifices the characteristic of the bank structure. 
In the above described second method (2), a high speed cache memory is provided between the MPU and the standard DRAM.  In this case, the standard DRAM may have relatively low speed of operation.  Standard DRAMs having storage capacities as large as 4M bits or 16M bits have come to be used.  In a small system such as a personal computer, the main memory thereof can be formed by one or several chips of standard DRAMs.  External provision of the high speed cache memory is not so effective in such a small system in which the main memory can be formed of one standard DRAM.  If the standard DRAM is used as the main memory, the data transfer speed between the high speed cache memory and the main memory is limited by the number of data input/output terminals of the standard DRAM, which constitutes a bottleneck in increasing the speed of the system. 
When the high speed mode is used as a pseudo cache memory, the speed of operation thereof is slower than the high speed cache memory, and it is difficult to realize the desired system performance. 
(ii) Consideration on a Conventional Cache Containing DRAM
Provision of the high speed cache memory (SRAM) in the DRAM is proposed as a method of forming a relatively inexpensive and small system, which can solve the problem of sacrifice of system performance when the interleave method or the high speed operation mode is used.  More specifically, a single chip memory having a hierarchical structure of a DRAM serving as a main memory and a SRAM serving as a cache memory has been conceived.  The one-chip memory having such a hierarchical structure is called a cache DRAM (CDRAM).  The CDRAM will be described with reference to FIGS.  1 through 4. 
FIG.  1 shows a structure of a main portion of a conventional standard 1 megabit DRAM.  As shown in FIG.  1, the DRAM comprises a memory cell array 500 including a plurality of memory cells MC arranged in a matrix of rows and columns.  A row of memory cells are connected to one word line WL.  A column of memory cells MC are connected to one column line CL.  Normally, the column line CL is formed by a pair of bit lines.  A memory cell MC is positioned at a crossing of one of the pair of bit lines and one word line WL.  In a 1M DRAM, the memory cells MC are arranged in a matrix of 1024 rowsxc3x971024 columns.  Namely, the memory cell array 500 includes 1024 word lines WLs and 1024 column lines CLs (1024 pairs of bit lines). 
The DRAM further comprises a row decoder 502 which decodes an externally applied row address (not shown) for selecting a corresponding row of the memory cell array 500; a sense amplifier which detects and amplifies data of the memory cell connected to the word line selected by the row decoder 502; and a column decoder which decodes an externally applied column address (not shown) for selecting a corresponding column of the memory cell array 502.  In FIG.  1, the sense amplifier and the column decoder are denoted by one block 504.  If the DRAM has axc3x971 bit structure in which input/output of data is effected bit by bit, one column line CL (a bit line pair) is selected by the column decoder. 
If the DRAM has axc3x974 bit structure in which input/output of data is effected 4 bits by 4 bits, 4 column lines CL are selected by the column decoder.  One sense amplifier is provided for each column line (bit line pair) CL in the block 504. 
In memory access for writing data to or reading data from the memory cell MC in the DRAM, the following operation is carried out.  First, a row address is applied to the row decoder 502.  The row decoder 502 decodes the row address and raises the potential of one word line WL in the memory cell array 500 to xe2x80x9cHxe2x80x9d.  Data of the 1024 bits of memory cells MC connected to the selected word line WL are transmitted to corresponding column lines CL.  The data on the column lines CL are amplified by sense amplifiers included in the block 504.  Selection of a memory cell to which the data is written or from which the data is read out of the memory cells connected to the selected word line WL is carried out by a column selection signal from the column decoder included in the block 504.  The column decoder decodes column address signals (more accurately, internal column address signals), and generates a column selecting signal for selecting the corresponding column in the memory cell array 500. 
In the above described high speed mode, column addresses are successively applied to the column decoder included in the block 504.  In the static column mode operation, column addresses applied at predetermined time intervals are decoded as new column addresses by the column decoder, and the corresponding memory cell out of the memory cells connected to the selected word line WL is selected by the column line CL.  In the page mode, new column address is applied at every toggling of the signal /CAS, and the column decoder decodes the column address to select the corresponding column line.  In this manner, one row of memory cells MC connected to the selected word line WL can be accessed at high speed by setting one word line WL at a selected state and by changing the column addresses only. 
FIG.  2 shows a general structure of a conventional 1M bit CDRAM.  Referring to FIG.  2, the conventional CDRAM comprises, in addition to the components of the standard DRAM shown in FIG.  1, SRAM 506 and a transfer gate 508 for transferring data between one row of the memory cell array 500 of the DRAM and the SRAM 506.  The SRAM includes a cache register provided corresponding to each column line CL of the memory cell array 500 so as to enable simultaneous storage of data of one row of the DRAM memory cell array 500.  Therefore, 1024 cache registers are provided.  The cache register is formed by a static memory cell (SRAM cell). 
In the structure of the CDRAM shown in FIG.  2, when a signal representing a cache hit is externally applied, the SRAM 506 is accessed, enabling access to the memory at high speed.  At the time of a cache miss (miss hit), the DRAM portion is accessed. 
A CDRAM as described above having a DRAM of a large storage capacity and a high speed SRAM integrated on the same chip is disclosed in, for example, Japanese Patent Laying-Open Nos.  60-7690 and 62-38590. 
In the above described conventional CDRAM structure, column lines (bit line pairs) CL of the DRAM memory cell array 500 and column lines (bit line pairs) of the SRAM (cache memory) 506 are connected in one to one correspondence through a transfer gate 508.  More specifically, in the above described conventional CDRAM structure, data of the memory cells connected to one word line WL in the DRAM memory cell array 500 and the data of the same number of SRAM cells as memory cells of one row of the memory cell array 500 are transferred bi-directionally and simultaneously, through the transfer gate 508.  In this structure, the SRAM 506 is used as a cache memory and the DRAM is used as a main memory. 
The so called block size of the cache is considered to be the number of bits (memory cells) the contents of which are rewritten in one data transfer in SRAM 506.  Therefore, the block size is the same as the number of memory cells which are physically coupled to one word line WL of DRAM memory cell array 500.  As shown in FIGS.  1 and 2, when 1024 memory cells are physically connected to one word line WL, the block size is 1024. 
Generally, when the block size becomes larger, the hit rate is increased.  However, if the cache memory has the same size, the number of sets is reduced in inverse proportion to the block size, and therefore the hit rate is decreased.  For example, when the cache size is 4K bits and the block size 1024, the number of sets is 4.  However, if the block size is 32, the number of sets is 128.  Therefore, in the conventional CDRAM structure, the block size is made too large, and the cache hit rate cannot be very much improved. 
A structure enabling reduction in block size is disclosed in, for example, Japanese Patent Laying-Open No.  1-146187.  In this prior art, column lines (bit line pairs) of the DRAM array and the SRAM array are arranged in one to one correspondence, but they are divided into a plurality of blocks in the column direction.  Selection of the block is carried out by a block decoder.  At the time of a cache miss (miss hit), one block is selected by the block decoder.  Data are transferred only between the selected DRAM block and the associated SRAM block.  By this structure, the block size of the cache memory can be reduced to an appropriate size.  However, there remains the following problem unsolved. 
FIG.  3 shows a standard array structure of a 1M bit DRAM array.  In FIG.  3, the DRAM array is divided into 8 memory blocks DMB1 to DMB8.  A row decoder 502 is commonly provided for the memory blocks DMB1 to DMB8 on one side in the longitudinal direction of the memory array.  For each of the memory blocks DMB1 to DMB8, (sense amplifier+column decoder) blocks 504-1 to 504-8 are provided. 
Each of the memory blocks DMB1 to DMB8 has the capacity of 128K bits.  In FIG.  3, one memory block DMB is shown to have 128 rows and 1024 columns, as an example.  One column line CL includes a pair of bit lines BL, /BL. 
As shown in FIG.  3, when the DRAM memory cell array is divided into a plurality of blocks, one bit line BL (and/BL) becomes shorter.  In data reading, charges stored in a capacitor (memory cell capacitor) in the memory cell are transmitted to a corresponding bit line BL (or/BL).  At this time the amount of potential change generated on the bit line BL (or/BL) is proportional to the ratio Cs/Cb of the capacitance Cs of the memory cell capacitor to the capacitance Cb of the bit line BL (or/BL).  If the bit line BL (or/BL) is made shorter, the bit line capacitance Cb can be reduced.  Therefore, the amount of potential change generated on the bit line can be increased. 
In operation, sensing operation in the memory block (memory block DMB2 in FIG.  3) including the word line WL selected by the row decoder 502 is carried out only, and other blocks are kept in a standby state.  Consequently, power consumption associated with charging/discharging of the bit lines during sensing operation can be reduced. 
When the above described partial activation type CDRAM is applied to the DRAM shown in FIG.  3, a SRAM register and a block decoder must be provided for each of the memory blocks DMB1 to DMB8, which significantly increases the chip area. 
In this structure, only SRAM cache registers corresponding to the selected block operate, and therefore, efficiency in using the SRAM cache registers is low. 
Further, the bit lines of the DRAM array and of the SRAM array are in one to one correspondence, as described above.  When direct mapping method is employed as the method of mapping memories between the main memory and the cache memory, then the SRAM 506 is formed by 1024 cache registers arranged in one row, as shown in FIG.  2.  In this case, the capacity of the SRAM cache is 1K bits. 
When 4 way set associative method is employed as the mapping method, the SRAM array 506 includes 4 rows of cache registers 506a to 506d as shown in FIG.  4.  One of the 4 rows of cache registers 506a to 506d is selected by the selector 510 in accordance with a way address.  In this case, the capacity of the SRAM cache is 4K bits. 
As described above, the method of memory cell mapping between the DRAM array and the cache memory is determined dependent on the internal structure on the chip.  When the mapping method is to be changed, the cache size also must be changed. 
In both of the CDRAM structures described above, the bit lines of the DRAM array and the SRAM array are in one to one correspondence.  Therefore, the column address of the DRAM array is inevitably the same as the column address of the SRAM array.  Therefore, full associative method in which memory cells of the DRAM array are mapped to an arbitrary position of the SRAM array is impossible in principle. 
Another structure of a semiconductor memory device in which the DRAM and the SRAM are integrated on the same chip is disclosed in Japanese Patent Laying-Open No.  2-87392.  In this prior art, the DRAM array and the SRAM array are connected through an internal common data bus.  The internal common data bus is connected to an input/output buffer for inputting/outputting data to and from the outside of the device.  Selected memory cells of the DRAM array and the SRAM array can be designated by separate addresses. 
However, in this structure of the prior art, data transfer between the DRAM array and the SRM array is carried out by an internal common data bus, and therefore the number of bits which can be transferred at one time is limited by the number of internal data bus lines, which prevents high speed rewriting of the contents of the cache memory.  Therefore, as in the above described structure in which the SRAM cache is provided outside the standard DRAM, the speed of data transfer between the DRAM array and the SRAM array becomes a bottleneck, preventing provision of a high speed cache memory system. 
(iii) Consideration on a General Clock Synchronized Type Semiconductor Device For the Problems of Which the Present Invention Includes the Solution
A semiconductor memory device of an application specific IC (ASIC) or for pipe line usage operates in synchronization with an external clock signal such as a system clock.  Operation mode of a semiconductor memory device is determined dependent on states of external control signals at rising or falling edge of the external clock signal.  The external clock signal is applied to the semiconductor memory device no matter whether the semiconductor memory device is being accessed or not.  In this structure, in response to the external clock signal, input buffers or the like receiving the external control signals, address signals and data operate.  In view of power consumption, it is preferred not to apply the external clock signal to the semiconductor memory device when the semiconductor memory device is not accessed, or to elongate period of the external clock signal. 
Generally, a row address signal and the column address signal are applied multiplexed time divisionally to the DRAM.  The row address signal and the column address signal are taken in the device in synchronization with the external clock signal.  Therefore, when the conventional DRAM is operated in synchronization with the external clock signal, it takes long time to take the row address signal and the column address signal.  Therefore, if low power consumption is given priority, the DRAM can not be operated at high speed. 
If the conventional semiconductor memory device is operated in synchronization with the external clock signal, the speed of operation is determined solely by the external clock signal.  If the semiconductor memory device is to be used where low power consumption is given priority over the high speed operation with the speed defined by the external clock signal, the conventional clock synchronized type semiconductor memory device can not be used for such application. 
In a clock synchronized type semiconductor memory device, control signals and address signals are taken inside in synchronization with the clock signal.  The control signals and address signals are taken inside by buffer circuits.  Each buffer circuit is activated in sychronization with the clock signal and generates an internal signal corresponding to the applied external signal.  In a standby state or the like, valid control signals and valid address signals are not applied.  However, external clock signals are continuously applied, causing unnecessary operations of the buffer circuits.  This prevents reduction in power consumption during standby state.  If the cycle period of the external clock signal becomes shorter, the number of operations of the buffer circuits is increased, causing increase of power consumption during standby period.  This is a serious problem in realizing low power consumption. 
(iv) Consideration on the Problems in Refreshing Operation in a Conventional RAM
If the semiconductor memory device includes dynamic memory cells (DRAM cells), the DRAM cells must be periodically refreshed.  The refresh mode of a DRAM generally includes an auto refresh mode and a self refresh mode, as shown in FIGS.  5 and 6. 
FIG.  5 shows waveforms in the auto refresh operation.  In the auto refresh mode, a chip select signal *CE is set to xe2x80x9cHxe2x80x9d and an external refresh designating signal *REF is set to xe2x80x9cLxe2x80x9d.  In response to a fall of the external refresh designating signal *REF, an internal control signal int. * RAS for driving row selecting circuitry falls to xe2x80x9cLxe2x80x9d.  In response to the internal control signal int. * RAS, a word line is selected in accordance with a refresh address generated from a built-in address counter, and memory cells connected to the selected word line are refreshed.  In the auto refresh mode, the timing of refreshing the semiconductor memory device is determined by the externally applied refresh designating signal *REF.  Therefore, whether or not refreshing is being carried out in the semiconductor memory device can be known outside the memory device. 
FIG.  6 shows waveforms in the self refresh operation.  In the self refresh mode, the chip select signal *CE is set to xe2x80x9cHxe2x80x9d and the external refresh designating signal *REF is set to xe2x80x9cLxe2x80x9d.  When the external refresh designating signal *REF falls to xe2x80x9cLxe2x80x9d, the external control signal int. * RAS is generated, and a word line is selected in accordance with the refresh address from the built-in address counter.  Thereafter, sensing operation and rewriting of the memory cells connected to the selected word line are carried out, and the memory cells connected to the word line WL are refreshed. 
The first cycle of self refreshing is the same as that of auto refreshing.  When the chip select signal *CE is at xe2x80x9cHxe2x80x9d and the refresh designating signal *REF is kept at xe2x80x9cLxe2x80x9d for a predetermined time period TF or longer, a refresh request signal is generated from a built-in timer.  In response, the internal control signal int. * RAS is generated, the word line is selected and the memory cells connected to the selected word line are refreshed.  This operation is repeated while the refresh designating signal *REF is at xe2x80x9cLxe2x80x9d.  In the refreshing operation in the self refresh mode, the timings of refreshing are determined by a timer contained in the semiconductor memory device.  Therefore, timings of refreshing can not be known from the outside.  Normally, data can not be externally accessed in the self refresh mode.  Therefore, in the normal mode, sell refreshing is not carried out.  The self refresh mode is generally carried out at a standby for retaining the data. 
Different semiconductor chips have different upper limits of refresh period necessary for retaining data (see NIKKEI ELECTRONICS, Apr. 6, 1987, p. 170, for example).  Generally, a guaranteed value for retaining data is measured by testing the semiconductor memory device, and period of a timer defining the self refresh cycle is programmed in accordance with the guaranteed value, for carrying out self refreshing.  When auto refresh mode and self refresh mode are selectively used, the guaranteed value for retaining data must be measured in order to determine the self refresh cycle.  As shown in FIG.  6, in the self refresh mode, an operation similar to that in the auto refreshing is carried out in response to the external refresh designating signal *REF, and then refreshing operation in accordance with the timer is carried out.  Therefore, in an accurate sense, the self refresh cycle means a cycle carried out after a lapse of a prescribed time period TF successive to the auto refreshing.  In the self refresh cycle, the refresh timing is determined by the contained timer, as described above, and the timings of refreshing can not be known from the outside.  Therefore, the self refresh cycle can not be used as a method of hidden refreshing, for example, in a normal operation mode. 
(v) Consideration on Array Arrangement in CDRAM and Data Transfer Between CDRAM and MPU (Burst Mode)
In a semiconductor memory device containing a DRAM array and a SRAM array, it is preferred to transfer data at high speed from the DRAM array to the SRAM array, so as to enable high speed operation.  When data are transferred from the DRAM array to the SRAM array, a row (word line) is selected, data of the memory cells connected to the selected word line are detected and amplified, and then a column is selected in the DRAM array. 
Generally, a row address signal and a column address signal are applied multiplexed to the DRAM.  Therefore, increase of the speed of data transfer from the DRAM array to the SRAM array is limited by this address multiplexing.  In this case, it is possible to apply the row address and the column address simply in accordance with a non-multiplex method to the DRAM.  However, in that case, the number of terminals for inputting DRAM addresses are increased significantly.  When the number of terminals is increased, the chip size and the package size are increased, which is not preferable. 
In addition, data transfer from the DRAM array to the SRAM array must be done after detection and amplification of the memory cell data by the sense amplifiers.  Therefore, data transfer from the DRAM array to the SRAM array can not be carried out at high speed. 
Further, some external operational processing units such as a CPU (Central Processing Unit) include a data transfer mode called a burst mode for carrying out data transfer at high speed.  In the burst mode, a group of data blocks are transferred successively.  A block of data is stored at successively adjacent address positions.  Since the burst mode is a high speed data transfer mode, the data blocks are stored in the cache memory in the semiconductor memory device containing a cache.  A semiconductor memory device containing a cache which can be easily connected to an operational processing unit having burst mode function has not yet been provided. 
In order to implement a CDRAM, DRAM array and SRAM array are integrated on the same semiconductor chip.  The semiconductor chip is housed in a package.  The layout of DRAM array and SRAM array as well as the geometrical figures thereof on the chip are determined by the geometrical figure and the physical dimensions of the housing package. 
DRAM array and its associated circuitry occupy a major area of a chip in CDRAM because DRAM is employed as a large storage capacity memory.  Thus, the size and figure of DRAM array are substantially determined by the size and shape of the housing package. 
In order to efficiently use the chip area, SRAM array should be arranged or laid out on the chip efficiently.  However, no consideration has made on the configuration of SRAM array for implementing efficient chip area utilization and for housing CDRAM in a package of an arbitrary shape and size. 
An object of the present invention is to provide a novel CDRAM with various operational functions and efficient chip layout. 
Another object of the present invention is to provide a semiconductor memory device in which self refreshing can be carried out in the normal mode. 
A further object of the present invention is to provide a semiconductor memory device allowing data transfer between DRAM array and a SRAM array at a high speed and with less power consumption. 
A further another object of the present invention is to provide a clock synchronized type semiconductor memory device in which power consumption at standby mode can be significantly reduced. 
A still further object of the present invention is to provide a semiconductor memory device which can be accessed at high speed even at a cache miss (miss hit). 
A still further object of the present invention is to provide a semiconductor memory device containing a cache which can be easily connected to an arithmetic operation unit having burst mode function. 
A still further object of the present invention is to provide a semiconductor memory device which operates at high speed even if the period of external clock signals is made longer. 
A still further object of the present invention is to provide a clock synchronized type semiconductor memory device which surely operates even if the period of the external clock signal is made longer or even if the external clock signal is generated intermittently. 
A still further object of the present invention is to provide a semiconductor memory device containing a cache which operates at high speed without malfunction with low power consumption. 
A still further object of the present invention is to provide a semiconductor memory device containing a cache which operates in synchronization with clocks, and operates at high speed without malfunction under low power consumption. 
A still further object of the present invention is to provide a semiconductor memory device which can be readily applied to use where high speed operation is given priority and to use where low power consumption is given priority. 
A still further object of the present invention is to provide a semiconductor memory device containing a cache which easily realizes high speed operation and low power consumption dependent on the intended use. 
A still further object of the present invention is to provide a semiconductor memory device containing a cache operating in synchronization with clocks which easily realizes both high speed operation and low power consumption dependent on intended use. 
A still further another object of the present invention is to provide an array arrangement which allows effective use of chip area. 
Yet another object of the present invention is to provide an SRAM array arrangement having a flexible array structure which can easily correspond to an arbitrary shape of the DRAM array. 
A yet further object of the present invention is to provide a semiconductor memory device containing a cache having an array arrangement having high density and suitable for high degree of integration. 
The present invention includes various aspects each of which is recited independently of others in the following. 
A semiconductor memory device in accordance with a first aspect of the present invention includes a DRAM array having dynamic memory cells; means for generating a refresh address; an automatic refresh means for refreshing the DRAM array in response to an external refresh designation; timer means measuring time for outputting a refresh request every prescribed timing; refresh means for refreshing the DRAM array in response to the refresh request from the timer means; refresh mode setting means for setting the refresh mode to either the auto refresh or self refresh mode; and input/output switching means for setting one pin terminal to a refresh designating input terminal or to a self refresh execution designating output terminal, in accordance with the refresh mode set by refresh mode setting means.  The timer means is activated when self refresh mode is set by the refresh mode setting means. 
In accordance with a second aspect of the present invention, the semiconductor memory device comprises first and second memory cell arrays each including a plurality of memory cells arranged in rows and columns; a first row address input terminal for receiving a first row address for designating a row of the first memory cell array; a first column address input terminal for receiving a first column address for designating a column of the first memory cell array; a second row address input terminal for receiving a second row address for designating a row of the second memory cell array; and a second column address input terminal for receiving a second column address for designating a column of the second memory cell array.  The first row address input terminal and the first column address input terminal include input terminals different from each other.  The second row address input terminal and the second column address input terminal include input terminals which are different from each other.  The first column address input terminal includes a pin arrangement which is shared with at least one of the second row address input terminal and the second column address input terminal. 
In accordance with the third aspect of the present invention, the semiconductor memory device includes first and second memory cell arrays each including a plurality of memory cells arranged in rows and columns; first address means for generating a first internal row address signal and a first internal column address signal for designating a row and a column of the first memory cell array in accordance with an external address; and second address means for generating a second internal row address and a second internal column address for designating a row and a column of the second memory cell array in accordance with the external address.  The first and second address means are activated in synchronization with an external clock signal, and simultaneously generates the first internal row address signal, the first internal column address signal, the second internal row address signal and the second internal column address signal in accordance with the timing determined by the clock signal. 
The semiconductor memory device in accordance with the fourth aspect of the present invention includes a DRAM array including a plurality of dynamic memory cells arranged in rows and columns; an SRAM array including a plurality of static memory cells arranged in rows and columns; data transfer means provided separate from an internal data transmitting line for transferring data between the DRAM array and the SRAM array; sense amplifier means for detecting and amplifying information of the selected memory cells of the DRAM array; and control means responsive to a transfer designation from the DRAM array to the SRAM array for activating the transferring means at a timing earlier than the timing of activating the sense amplifier means.  Bit line data of the DRAM array are transmitted directly to the transfer means, not through the internal data line. 
The semiconductor memory device in accordance with the fifth aspect of the present invention includes a DRAM array including a plurality of dynamic memory cells arranged in rows and columns; an SRAM array including a plurality of static memory cells arranged in rows and columns; amplifying means provided for each column of the DRAM array for amplifying signals on the corresponding column; sense amplifier means for amplifying and latching signals on the corresponding column; data transfer means provided separate from an internal data transmitting line for transferring data between the DRAM array and the SRAM array; means responsive to an address signal for selectively transmitting outputs from the amplifying means to the data transferring means; and control means responsive to a data transfer designation for activating the data transferring means before the activation of the sense amplifier means.  The transfer mean includes means for forming a current mirror amplifying means by supplying current to the amplifying means. 
In accordance with a sixth aspect of the present invention, the semiconductor memory device includes address input means for receiving address signals; address generating means responsive to a burst mode designation for successively generating address signals at prescribed timings; address selecting means receiving an output from address input means and an output from address generating means, responsive to the burst mode designation for selectively passing the output of the address generating means; and memory cell selecting means for selecting a corresponding memory cell out of a plurality of memory cells in accordance with the output from the address selecting means. 
In accordance with a seventh aspect of the present invention, the semiconductor memory device includes address input means for receiving addresses applied from an external arithmetic processing unit; address generating means responsive to a burst mode designation from the external arithmetic processing unit for generating addresses in synchronization with external clock signals; address selecting means for selectively passing an output from address input means or an output from address generating means; and memory cell selecting means for selecting a corresponding memory cell from the memory cell array in accordance with the output from the address selecting means.  The address selecting means selectively passes the output from the address generating means in response to the burst mode designation. 
In accordance with the eighth aspect of the present invention, the memory device includes internal clock generating means responsive to an external clock signal for generating an internal clock signal, and setting means for setting the internal clock generating means to operation inhibited state in response to a standby state designating signal.  The externally applied signal is taken in response to the internal clock signal generated from the internal clock generating means. 
In accordance with a ninth aspect of the present invention, the semiconductor device includes, in addition to those provided in the eighth aspect, refreshing means responsive to the inhibition of the internal clock generation by the setting means for refreshing dynamic memory cells. 
A semiconductor memory device in accordance with a tenth aspect of the present invention includes a memory cell array having a plurality of memory cells arranged in rows and columns, and internal address generating means receiving an external address signal for generating an internal address signal.  The external address signal includes an external row address signal for designating a row of the memory cell array, and an external column address signal for designating a column of the memory cell array.  The internal address generating means generates internal row address signal and internal column address signal corresponding to the external row address signal and the external column address signal, respectively. 
The internal address generating means of the semiconductor memory device in accordance with the tenth aspect of the present invention includes first address generating means which takes one of the above mentioned external row address signal and the external column address signal at a first timing of an externally applied clock signal for generating a first internal address signal corresponding to the taken external address signal, and second address generating means which takes the other one of the external row address signal and the external column address signal at a second timing of the externally applied clock signal for generating a second internal address corresponding to the taken external address signal. 
The first timing is determined by one of the rise and fall of the externally applied clock signal, and the second timing is determined by the other one of the rise and fall of the externally applied clock signal. 
The semiconductor memory device in accordance with an eleventh aspect of the present invention includes a memory cell array including a plurality of memory cells, and address generating means receiving externally applied external address signal for generating an internal address signal corresponding to the received external address signal.  The external address signal designates a memory cell in the memory cell array. 
The semiconductor memory device in accordance with the eleventh aspect of the present invention further includes setting means responsive to an externally applied timing designating signal for taking an address for setting the timing for the address generating means to take the externally applied address signal. 
The address generating means takes the applied external address signal in accordance with the timing set by the setting means and generates the internal address signal. 
The semiconductor memory device in accordance with the twelfth aspect of the present invention includes a DRAM array including a plurality of dynamic memory cells arranged in rows and columns, an SRAM array including a plurality of static memory cells arranged in a matrix of rows and columns, and data transferring means provided between the DRAM array and the SRAM array for transferring data between a selected memory cell of the DRAM array and a selected memory cell in the SRAM array. 
Each row of the matrix of the SRAM array includes memory cells divided into n groups.  The SRAM array further includes a plurality of word lines each connected to memory cells of different group, n word lines being arranged for each row in parallel to the row direction of the matrix. 
A semiconductor memory device in accordance with a thirteenth aspect of the invention includes a high speed memory array having a plurality of static type memory cells, a large storage capacity memory array having a plurality of memory cells, and data transfer means for transferring data between a selected static type memory cell and a selected dynamic type memory cell. 
The semiconductor memory device of the thirteenth aspect further includes a data transfer bus for coupling the selected memory cell of the large storage capacity memory array with the data transfer means, clamping means for clamping the potential on the data transfer bus, and control means responsive to an indication of data transfer from the high speed memory array to the large storage capacity memory array for inhibiting a clamping operation of the clamping means. 
A semiconductor memory device in accordance with a fourteenth aspect of the invention includes a high speed memory array having a plurality of static type memory cells arranged in rows and columns, a large storage capacity memory array having a plurality of dynamic type memory cells, and data transfer means for transfer data between a selected static type and a selected dynamic type memory cell. 
The semiconductor memory device in accordance with the fourteenth aspect further includes clamping means provided for each column of the high speed memory array for clamping the potential of an associated column, and control means responsive to an indication of data transfer from the large storage capacity memory array to the high speed memory array for inhibiting a clamping operation by the clamping means. 
According to the first aspect of the present invention, setting of the self refresh mode or the auto refresh mode is done by refresh mode setting means and one terminal is switched by the input/output switching means to be a refresh designating input terminal in the auto refresh mode, and the self refresh execution designating output terminal in the self refresh mode.  Therefore, even in the self refresh mode, refresh timing can be known from the outside of the memory device, and self refresh mode can be utilized even in the normal mode. 
In accordance with the second aspect of the present invention, since the row and column designating input terminals of the first and second memory cell array are provided separately for inputting the row address signals and the column address signals, the row address signals and the column address signals to the first and second memory cell arrays can be applied in the non-multiplexed manner.  Part of the address signals to the first memory cell array and address signals to the second memory cell array is applied to the same input terminal.  Therefore, address non-multiplex method can be realized without increasing the number of input terminals. 
According to the third aspect of the present invention, the first and second address means generate internal address signals by simultaneously taking address signals in synchronization with the external clock signal, and therefore the clock synchronized type semiconductor memory device can be operated at high speed employing address non-multiplex method. 
According to the fourth aspect of the present invention, data transfer means is activated at an earlier timing than the activation of the sense amplifier in the DRAM array, and therefore data can be transferred from the DRAM array to the SRAM array at high speed. 
According to the fifth aspect of the present invention, an output from a current mirror type amplifier is transmitted through the data transfer means, and therefore the data transfer means can be activated without waiting for the activation of the latch type sense amplifier, which enables high speed data transfer from the DRAM array to the SRAM array. 
According to the sixth aspect of the present invention, an internal counter is activated in response to a burst mode designation from an external arithmetic processing unit, an output from the address counter is selected by a multiplexer to be utilized as an address signal, and the multiplexer selects external address signals in a mode other than the burst mode.  Therefore, a semiconductor memory device which can be easily connected to an external arithmetic processing unit having burst mode function can be provided. 
According to the seventh aspect of the present invention, a counter as a built-in address generator effects counting operation in synchronization with the external clock signal, the output from the counter is used as an address in the burst mode, and external address signals are taken and utilized in synchronization with an external clock signal in operation modes other than the burst mode, therefore, a clock synchronized type semiconductor memory device which can be easily connected to an external operational processing unit having burst mode function can be realized. 
According to the eighth aspect of the present invention, when generation of the internal clock signal is stopped at the standby state of the clock synchronized type semiconductor memory device, operations of external signal input buffer and the like are stopped, so that power consumption in the standby state can be reduced. 
According to the ninth aspect of the present invention, self refresh mode is activated when generation of the internal clock signal is stopped in the invention in accordance with the eighth aspect, and therefore data of the DRAM array can be surely retained in the standby state. 
According to the tenth aspect of the present invention, since the external row address signals and the external column address signals are taken at timings determined by the rise and fall of the external clock signals, the external row address signal and the external column address signal can be taken by a single pulse of the external clock signal.  Therefore, compared with a structure in which the external row address signal and the external column address signal are taken time divisionally at timings determined by the rise of the external clock signal, the external row address signal and the external column address signal can be taken sooner.  Generally, operation of a clock synchronized type semiconductor memory device starts after the external address signals are taken.  Therefore, the semiconductor memory device can be operated at higher speed. 
According to the eleventh aspect of the present invention, the timing for taking the external address signals is determined by timing information set by setting means.  Therefore, time required for taking the external address signals can be set to an optimal value dependent on the period of the external clock signals, and therefore higher speed of operation and lower power consumption can be flexibly realized. 
In the SRAM array according to the twelfth aspect memory cells arranged in one row is divided into a plurality of groups.  Memory cells of each group is connected to a word line provided corresponding to each group.  Therefore, memory cells of one row of the SRAM array are connected to a plurality of word lines.  By adjusting the number n of the groups of the memory cells of one row, an SRAM array having an arbitrary shape can be provided without changing the number of memory cells connected to one word line. 
In the semiconductor memory device according to the thirteenth and fourteenth aspects, the control means is operable to inhibit the clamping operation of the clamping means provided at the data receiving side.  Consequently, a current flow is prevented from flowing into the data transfer means from the clamping means, resulting in reduced current consumption. 
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.