It is desirable to design an electronic chip that is difficult to reverse engineer to protect the circuit design.  Known reverse engineering techniques include methods for tearing down layers of the chip to expose the logic devices. 
Semiconductor teardown techniques typically involve imaging a device layer, removing the layer, imaging the next layer, removing the layer, and so on until a complete representation of the semiconductor device is realized.  Layer imaging is usually accomplished using an optical or electron microscope.  Layer removal can be done by using physical means such as lapping or polishing, by chemical means by etching specific compounds, by using a laser or a focused ion beam technique (FIB), or by any other known method capable of removing the layers.  FIG.  1 shows some of the semiconductor layers and regions that are imaged by the teardown reverse engineering technique. 
Once the semiconductor device teardown is complete and the imaging information is gathered, the logic function of the device can be re-constructed by using diffusion, polysilicon, and well areas to define the MOS devices used to create logic gates, and the metal layers to define how the logic gates are interconnected.  FIG.  2 shows how the semiconductor layers define the MOS device. 
U.S. Pat.  No.  7,711,964 discloses one method of protecting logic configuration data.  The configuration data for the logic device is encrypted and a decryption key is encrypted using a silicon key.  The encrypted decryption key and configuration are transferred to the logic device.  The silicon key is used to decrypt the decryption key which is then used to decrypt the configuration data.  One problem with this method is that the chip is not protected against physical reverse engineering as described above. 
Many other cryptography techniques are known.  But, all cryptographic techniques are vulnerable to the conventional teardown techniques. 
Disclosed is a method for designing a semiconductor device that is resistant to these techniques.  The semiconductor device includes a physical geometry which is not clearly indicative of the device's function.  For example, the semiconductor device is designed where two or more types of logic devices have the same physical geometry.  When the teardown method is performed two or more devices will show the same physical geometry, but, these two or more devices have different logic functions.  This prevents the person performing the reverse engineering to determine the logic functions by the known methods of observing the geometry of the devices. 
Employing the disclosed method and device will force the reverse engineer to employ more difficult techniques.  These techniques are more time consuming, more expensive, and more likely to have errors.