1.  Field of the Invention
The present invention relates to techniques for communicating between integrated circuits.  More specifically, the present invention relates to a method and an apparatus for using capacitively coupled communication techniques to communicate between stacked assemblies of laminated integrated circuit (IC) chips. 
2.  Related Art
Advances in semiconductor technology have made it possible to fabricate a single IC (Integrated Circuit) chip that contains hundreds of millions of transistors.  One of the advantages of integrating systems onto a single IC chip is that it increases the operating speed of the overall system.  This is because in an alternative design of multiple chips, the signals between system components have to cross chip boundaries, which typically reduces the system's operating speed due to the lengthy chip-to-chip propagation delays and limited number of chip-to-chip wires.  In contrast, in a single-chip solution, the signals between system components no longer have to cross chip boundaries, thereby significantly increasing the overall system speed.  Moreover, integrating systems onto a single IC chip significantly reduces overall costs because fewer chips are required to perform a given computational task. 
However, some systems cannot be integrated into a single chip due to their high complexity and large size.  Note that multiple IC chips are typically integrated onto a printed circuit board that contains multiple layers of signal lines for inter-chip communication.  Furthermore, signal lines on an IC chip are about 100 times more densely packed than signal lines on a printed circuit board.  Consequently, only a tiny fraction of the signal lines on a chip can be routed across the printed circuit board to other chips.  For this reason, in such systems, inter-chip communication becomes the bottleneck for increasing the operating speed.  Moreover, increases in IC integration densities are expected to exacerbate this bottleneck. 
To overcome this inter-chip communication bottleneck, researchers have recently developed an alternate technique, known as “Proximity Communication,” for communicating between semiconductor chips.  Proximity Communication in an I/O technology that allows two face-to-face chips to communicate without wires.  It involves integrating arrays of capacitive transmitters and receivers onto active surfaces of IC chips to facilitate inter-chip communication.  If a first chip is situated face-to-face with a second chip so that transmitter regions on the first chip are capacitively coupled with receiver regions on the second chip, it is possible to transmit signals directly from the first chip to the second chip without having to route the signal through intervening signal lines within a printed circuit board. 
Although Proximity Communication promises much higher I/O density and lower power, it requires accurate alignment between the two communicating chips.  Mechanical misalignment degrades performance by reducing signal and augmenting crosstalk noise; if the chips are sufficiently misaligned, noise may dominate the desired signal, and communication may fail.  There are two main types of misalignment: in-plane misalignment and chip separation.  Tilt and rotation manifest as aberrations of these two effects. 
Several techniques have been developed to mitigate in-plane misalignment in the horizontal (x, y) plane.  It can be corrected by adjusting the spatial placement of data on the sending or transmitting (Tx) chip, depending on the relative position of the receiving (Rx) chip.  However, the data steering circuitry is complex, costly in power, and works only over a small spatial range—typically two pad pitches.  Also, the electronic alignment scheme proposed by Drost et al.  in “Electronic Alignment for Proximity Communication,” IEEE International Solid-State Circuits Conference, 15-19 Feb. 2004, vol.  1, 2004 only works for capacitively-coupled Proximity Communication.  No analogous method has yet been developed for inductively coupled communication; in fact, crosstalk noise is a major limitation of such an inductively coupled scheme even in the absence of misalignment, because magnetic fields must have closed return paths, and these loops are often unconfined and large.  Recent demonstrations of inductively-coupled data links showed that in the absence of active crosstalk reduction schemes, noise limits the achievable bit-error-rate (BER) to greater than 10−4 even for a large channel pitch of 60 microns, as described by Miura et al.  in “A 1Tb/s 3 W Inductive-coupling Transceiver for Inter-Chip Clock and Data Link,” ISSC Digest Technical Papers, pp.  142-143, February 2006. 
Chip separation also degrades performance by reducing signal level and augmenting crosstalk noise.  Unfortunately, it cannot be easily corrected by electronic means.  Although in theory it is possible to adapt signaling levels and pad sizes to mitigate the degradation introduced by chip separation, these schemes are overly complex and infeasible to implement in practice.  Reliable communication therefore mainly relies on tight tolerances in packaging technologies that can ensure an adequately-small and well-controlled separation between the two communicating chips. 
Multiple access schemes are well established in modern wireless telecommunication systems using electromagnetic (radio) waves propagating over large distances.  Multiple devices in a cellular network, for example, can communicate simultaneously with a base station over the same space because each device is assigned a different time slot, frequency band, or code.  The multiple access schemes used in wireless communication systems are effective at allowing multiple channels to operate across the same space over long distances with minimal interference.