The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory having a fast access time. 
Computers such as microcomputers have developed together with the advance of semiconductor technology.  There is a demand for higher processing speed of computers, and hence for more fast access time of semiconductor memories.  A great amount of data is often read out from a memory under control of a CPU or the like.  In this case, fast access time is preferred. 
In order to achive fast access time, a conventional semiconductor memory shown in FIG.  1 is proposed.  The semiconductor memory in FIG.  1 is a modified type of semiconductor memory shown in FIG.  1 of U.S. Pat.  No.  4,344,156.  In order to read data from the memory shown in FIG.  1 of this specification, row and column address signals are entered, and a specific memory cell is designated by these signals.  A row decoder 1 decodes the row address signals and sets a corresponding word line to the active level.  Output signals from memory cells 5 of the selected row are read out by sense amplifiers 7 through bit lines.  Output signals from the sense amplifiers 7 are latched by latches 9.  A column decoder 3 causes a transistor 11 corresponding to the column address signal to turn on.  The contents of the memory cell selected by the row and column address signals are read out through an output buffer 13.  The column address signal is sequentially updated to read out the contents of the other of the memory cells 5 in the row selected by row address signals.  After the contents of all the memory cells of one row are read out, the row address signal is updated.  Thereafter, the contents of the memory cells of the row selected in the same manner as described above are read out. 
In the semiconductor memory device of FIG.  1, the word and bit lines have larger stray capacitance than other nodes.  As a result, with the memory as shown in FIG.  1, a great deal of time passes forom when the row address is updated, (thus setting the word line at an active level) to when data from the memory cells reaches the latches 9 through the bit lines.  Therefore, T1 (shown in FIG.  2B), which is the time necessary to read first data after every updating of the row address (shown in FIGS.  2A) in relatively long.  Until the row address is again updated, however, the contents of any memory cell of the same row can be read within a short time T2 since those contents are already stored in the latches 9.  The memory of FIG.  1 can thus read data faster than the known memory items of data serially read from the cells of the same row through the bit lines. 
As stated in the preceding paragraphs, the memory of FIG.  1 is disadvantageous because long time T1 is required to read the first data after each updating of the row address.  To reduce the time required to read data from the memory, it has been proposed that more memory cells be arranged in a row and that more latches be provided to latch the contents of these cells.  These arrangements, however, do not reduce the time T1 required to read the first data every time the row address is updated.  Moreover, the use of more latches inevitably increases the chip size and the cost of the memory.