Reliability is a key concern in the design of electronic circuits.  One of the most common sources of problems is the damage to a circuit or device from electrostatic discharge (ESD).  A measure of ESD performance is the ability of a circuit or device to withstand a relatively short exposure to high voltage or current without lasting damage.  ESD can be caused by the human body, by poorly grounded machinery such as test equipment, or in noisy environments such as in automotive applications or in consumer applications like computers. 
In testing circuits and devices for ESD performance, the circuit or device is typically placed in a tester so that each of the terminals or pins of the device may be stressed relative to the other pins.  The pin under test can be stressed with a positive voltage or a negative voltage relative to the other pins.  The three main ESD test models are the human body model, the machine model, and the charged device model.  The models differ in the voltage and current stress applied, as well as in the duration of the applied stress.  For example, the human body model relies on a high voltage (as high as 4000 Volts), high current pulse relatively long in duration, while the machine model provides a short duration, high voltage pulse similar to that which would occur if a terminal or pin of the device touched a grounded conductor. 
Pins or terminals of circuits that are driven by output buffer drivers, such as are used on the output pins of memory circuits for example, are particularly susceptible to damage from ESD stress.  An example of an output buffer driver 100 is shown in FIG.  1 and comprises a pull-up n-channel metal-oxide-semiconductor field effect transistor (MOSFET) 102 and a pull-down n-channel transistor 104.  True and complementary data are presented at nodes 106 and 108.  Data is taken out of the circuit at the DQ terminal pad 110.  An ESD protection circuit provides a discharge shunting path for the ESD current.  In the circuit of FIG.  1, the output driver transistors provide the shunting path, not by operating as MOS transistors, but by operating as bipolar transistors.  Field effect transistors comprise doped source and drain regions that form parasitic bipolar transistors with the substrate on which the transistor is fabricated.  These parasitic bipolar devices can be used advantageously in an ESD event to dissipate the current into the substrate and across the source and drain of the transistors. 
The use of the parasitic bipolar transistors inherent in the circuit of FIG.  1 as the ESD discharge path has been shown to be unreliable when stressed negatively with respect to VDD.  Specifically, when VDD is held at 0 Volts and the output pad or pin 110 is stressed negatively to a voltage in the human body model range of 2000 to 4000 Volts, the output buffer shows signs of permanent damage manifested by current leakage when the pad 110 is driven to ground potential.  In addition, standby current leakage also occurs because of silicon melt filaments forming across the gate to source/drain regions of the transistors 102 and 104.  Testing has shown that these problems are probably the result of the pull-up and pull-down transistors activating during the ESD event.  In other words, the transistors operate in the MOS mode instead of in the parasitic bipolar mode.  The high voltages and currents generated in an ESD event cannot be properly dissipated by the transistors in the MOS mode, so that permanent damage to the output buffer transistors results.  Aspects of the invention are intended to address these problems.