Most present implementations of synaptic function are based on multiple devices in CMOS (complementary metal oxide semiconductor) platform.  The area taken by the large number of such devices is one of the limitations on these implementations for neuromorphic computing.  Single devices based on charge trapping in architectures similar to flash memory have also been used to implement synaptic devices.  Electrons are stored in an insulator using CTF (charge trap flash) technology.  Device architectures based on charge trapping, such as flash memories, may be used to implement synaptic devices.  However, the voltage and/or current required for operation is generally too high for some applications such as neuromorphic computing.  This problem arises due to the energy required for electrons to tunnel over a barrier before becoming trapped in, for example, a floating gate.  Such a barrier is needed to provide sufficient retention time.