The invention relates to an information processing system of a high reliability in which a plurality of, for example, three processors constructing a multiplex unit are connected by a bus and the same process is simultaneously executed, thereby detecting a failure and executing a necessary process and, more particularly, to an information processing system of a high reliability in which one of the processors in the multiplex unit is set to a master processor and the remaining processors are set to slave processors and a failure is detected. 
In recent years, in association with that the information processing system has widely been used in various fields, in the case where the information processing system fails, a possibility such that a large social and economical influence is exerted is considered. 
Therefore, there is demanded an information processing system of a high reliability such that a failure hardly occurs as little as possible and even if a failure occurs, the failure can be certainly detected and, further, processes can be continued while keeping a consistency of the processing contents without stopping the operation of the processor. 
Hitherto, as an information processing system of a high reliability, an information processing system having a multiplex construction comprising three or more processors has been provided.  As a method of realizing such a multiplex processor, the following methods are considered.  Processors such as three or more processors or the like and a majority decision logic circuit are prepared in one unit.  The majority decision logic circuit uses a method whereby an arithmetic operation based on a majority decision logic is executed for output signals of three or more processors which are synchronously operating by the same clock and the result is transmitted to another processor such as a main memory unit or the like.  In the multiplex processor using the majority decision logic, however, although the number of cycles which are executed by each processor doesn't increase, the number of execution cycles increases by only the number corresponding to the execution of the majority decision logic, so that a processing time is delayed.  A hardware amount of the exclusive-use majority decision logic circuit itself is large.  A number of signal lines are also needed between the processors and the majority decision logic circuit.  A circuit construction becomes complicated and the costs are also high.