Clock recovery circuits are used in high-speed receivers to recover timing information from an incoming data signal.  A basic clock recovery circuit 101 implemented as part of an integrated circuit (IC) is illustrated in FIG.  1.  Digital information in the incoming data signal arrives at a signaling pin 103 of the IC.  The digital information is often encoded to ensure a minimum transition density needed for clock recovery.  The clock recovery circuit 101 generates a recovered clock from the incoming data signal, which is then fed over a feedback path 105 to an input of the clock recovery circuit.  Both the feedback path and the incoming data signal are compared by a phase detector 109, which determines whether the recovered clock signal is early or late relative to the incoming data signal.  Phase difference information from the phase detector is passed through a filter 113 and accumulated to control a charge pump 115.  In turn, the charge pump 115 generates a control signal for a variable frequency oscillator (VFO) 117, which advances or delays frequency and phase of the recovered clock in order to align its edges with the incoming data signal.  This structure implements a phase-locked loop (PLL) that, over time, closely aligns the recovered clock with phase and frequency of the incoming data signal.  An offset circuit 106 creates a phase-shifted copy of the recovered clock to generate a sampling clock, used to align a data sampler 107 to the midpoint of a data interval.  In some cases the offset circuit 106 is an integral part of VFO 117.  As indicated by reference numeral 111, the data sampler 107 can itself be a part of the phase detector 109, with a single circuit 111 used for both clock and data recovery. 
Conventional clock recovery designs such as depicted in FIG.  1A are often rooted in a form of binary phase detector known as a “bang-bang” or Alexander phase detector.  Comprised of relatively simple logic, a bang-bang phase detector identifies logic state transition between successive digital symbols and takes an “edge sample” exactly at the expected transition time.  If the recovered clock is precisely aligned with the transition edges of the data signal (discounting intersymbol interference), the edge sample should be exactly at the voltage midpoint between logic states.  However, depending on direction of transition, an edge sample offset from the midpoint means the edge sampling clock is early or late relative to the data signal.  This early and late information is used to incrementally advance or retard the recovered clock to align it with the transitions in the incoming data signal. 
Binary phase detectors are advantageous in that they typically use simple logic and are well suited for power-efficient digital clock recovery designs.  However, designs based on these circuits are often characterized by large steady state dithering and low bandwidth, due to high-loop latency attributable to filtering of up and down binary signals and converting these signals into a VFO control signal. 
By contrast, linear phase detection techniques result in a phase-error signal proportional to the difference between an incoming data signal and a recovered clock, and these techniques therefore promise significantly lower steady state dither jitter at higher loop bandwidth.  However, linear phase detection techniques often suffer from large static phase error and unreliable operation at high frequencies; they are also difficult to combine with digital filtering techniques.  To elaborate, conventional linear phase detection techniques generate variable-width pulse signals that gate pull-up and pull-down of a signal line to generate a VFO control signal.  Manufacturing variations, capacitive effects, and other issues make it difficult to match precisely these impedances so as to reliably avoid unintended static phase offset.  In addition, as the data rates increase, it becomes correspondingly difficult to generate suitable variable-width pulses, i.e., these pulse-widths and associated processing should be of high precision and should be relatively short when compared to a unit interval (which is difficult at higher speeds).  As implied earlier, processing typically requires (a) only generating clock recovery updates when there is a transition in the incoming data signal, (b) correctly correlating early or late transitions with a leading or lagging recovered clock, and (c) applying low pass filtering so as to minimize the effects of random noise.  Specific filtering requirements become more complex for non-conventional signaling techniques, such 4-PAM signaling. 
What is needed is an improved high-bandwidth clock recovery architecture that is area and power efficient and that provides reduced static phase error and dither jitter.  Such an architecture would be well-suited to increasingly-small digital designs and digital designs that are power sensitive.  Ideally, such an architecture would combine benefits of conventional binary phase detection and linear phase detection techniques while omitting their respective disadvantages.  Further still, such an architecture ideally would accommodate non-traditional signaling techniques, such as multi-PAM (MPAM) signaling.  The present invention addresses these needs and provides further, related advantages. 
The subject matter defined by the enumerated claims may be better understood by referring to the following detailed description, which should be read in conjunction with the accompanying drawings.  This description of one or more particular embodiments, set out below to enable one to build and use various implementations of the technology set forth by the claims, is not intended to limit the enumerated claims, but to exemplify their application to certain methods and devices.  The description set out below exemplifies (i) a clock recovery circuit that uses two-point control of a phase-locked loop (PLL), (ii) an integrated circuit having one or more such clock recovery circuits, and (iii) related methods, systems and devices.  While the specific examples are presented, the principles described herein may also be applied to other methods and devices as well.