1.  Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device having an opening and a method of fabricating the same. 
2.  Description of the Prior Art
Following recent improvement of the degree of integration of semiconductor devices, refinement of semiconductor elements loaded on semiconductor devices gets more and more important.  Such refinement of the semiconductor elements results in a new problem of electric resistance of each element electrode and dispersion of the resistance.  In a MOS transistor, for example, each of gate, source and drain electrodes itself has high wiring resistance and high parasitic resistance.  Following the aforementioned refinement, unignorable wiring delay and conductance deterioration result from the electric resistance of each electrode. 
In general, therefore, a technique of bringing the surfaces of gate, source and drain electrodes into a silicide structure obtained by combining the electrode material (silicon) with a metal element thereby reducing wiring delay and conductance deterioration is put into practice.  Further, the so-called salicide (self-aligned silicide) structure selectively forming silicide layers on the surfaces of the gate, source and drain electrodes in a self-aligned manner is also frequently employed in recent years. 
In a general fabrication process for the salicide structure, spacers of silicon (SiO2) are first formed on the side surfaces of the gate electrode of polycrystalline silicon.  Thereafter a metal is deposited on the overall surface of the element and thereafter heat-treated for silicifying the surfaces of the gate, source and drain electrodes in a self-aligned manner.  Then, the remaining unreacted metal part is removed.  Thus, the salicide structure is formed. 
The aforementioned problem of electric resistance can be avoided by employing the salicide structure.  When a contact hole (opening) is formed in an interlayer isolation film for connecting each electrode of the aforementioned salicide structure with a wire, however, the following problem arises:
Following the aforementioned refinement of the element, the contact hole is required to have a high aspect ratio.  In generally employed etching with CHF3 gas or CF4 gas through a low-concentration plasma device, however, it is difficult to suppress a microloading effect (irregular etching) as the aspect ratio of the contact hole is increased.  In etching with CHF3 gas or CF4 gas through a high-concentration plasma device, on the other hand, the microloading effect (irregular etching) can be suppressed. 
In the etching through a high-concentration plasma device, however, it is difficult to set the concentration of CF2 or CF3, which is a polymer precursor in the plasma of the etching gas, to a value capable of ensuring a high etching selection ratio of the base salicide structure.  Therefore, the surfaces of the electrodes of the salicide structure are disadvantageously scraped off by the etching. 
FIG.  7 is a sectional view for illustrating the problem caused when forming contact holes by conventional etching with CHF3 gas or CF4 gas through a high-concentration plasma device.  Referring to FIG.  7, an element isolation film 112 is formed on a prescribed region of the surface of a semiconductor substrate 101 in a conventional semiconductor device.  A source electrode 102 and a drain electrode 103 serving as impurity active regions are formed on an active region (element forming region) enclosed with the element isolation film 112 at a prescribed interval to hold a channel region 104 therebetween.  A gate electrode 106 is formed on the channel region 104 through a gate insulator film 105.  Salicide layers 102s, 103s and 106s are formed on the surfaces of the source electrode 102, the drain electrode 103 and the gate electrode 106 respectively.  Further, an interlayer isolation film 109 of silicon oxide (SiO2) is formed to cover the overall surface.  The interlayer isolation film 109 is formed with contact holes 110 reaching the source electrode 102, the drain electrode 103 and the gate electrode 106 respectively. 
When the contact holes 110 are formed in the interlayer isolation film 109 by etching with CHF3 gas or CF4 gas through a high-concentration plasma device in order to suppress a microloading effect (irregular etching) in this structure, the surfaces of the electrodes 102, 103 and 106 having the salicide structure are also etched.  This is because it is difficult to set the concentration of CF2 or CF3, which is a polymer precursor in the plasma of the etching gas, to a value capable of ensuring a high etching selection ratio of the base salicide layers 102s, 103s and 106s, as hereinabove described. 
As described above, it is generally difficult to compatibly suppress the microloading effect (irregular etching) and over-etching in formation of the contact holes 110 requiring a high aspect ratio.  This problem is not restricted to the case of forming contact holes on a salicide structure but similarly arises also in formation of contact holes provided in an insulator film for attaining electrical contact between a lower conductive part and an upper conductive part.