Q:

How to simulate memory on VHDL test bench? 

I'm writing a universal test bench for my design that communicates with a RAM via a pretty standard bus.  I consulted some examples and wrote it like this:
signal memory: mem_array;
signal mem_address: std_logic_vector(31 downto 0);
signal mem_data: std_logic_vector(31 downto 0);
signal mem_read: std_logic;
signal mem_write: std_logic;

cpu_mem_data <= transport memory(to_integer(unsigned(mem_address))) after DELAY when mem_read = '1' else (others => 'Z');

always : PROCESS
    file in_file: text open read_mode is "in.txt";
    variable line_str: line;
    variable address: std_logic_vector(31 downto 0);
    variable data: std_logic_vector(31 downto 0);
BEGIN
    reset <= '1';

    readline(in_file, line_str);
    hread(line_str, address);
    starting_pc <= address;
    while not endfile(in_file) loop
        readline(in_file, line_str);
        hread(line_str, address);
        read(line_str, data);
        memory(to_integer(unsigned(address))) <= data;
        report "Initialized " & integer'image(to_integer(unsigned(address))) & " to " & integer'image(to_integer(unsigned(data)));
    end loop;

    wait for 30 ns;

    reset <= '0';
WAIT;                                                        
END PROCESS always; 

process (mem_write)
begin
    if (rising_edge(mem_write)) then
        memory(to_integer(unsigned(mem_address))) <= transport mem_data after DELAY;
        report "Will write " & integer'image(to_integer(unsigned(mem_data))) & " to " & integer'image(to_integer(unsigned(mem_address)));
    end if;
end process;

I'm encountering two problems. 
When compiled and simulated in ModelSim Altera SE, memory is showing all X for all locations.  Reports are showing that correct values are read from the in.txt file, but nothing is getting written into the memory.  I also try initializing all locations or just a single location to all '0' and it doesn't work either.  On the contrary, the signal starting_pc is being set to correct value. 
The other problem is that delayed assignments do not seem to work.  My design attempts to read from the memory and mem_read and mem_address are correctly set, but after DELAY time mem_data remains at high impedance. 
What am I doing wrong? 

A:

You have multiple drivers on the signal memory.   It is being written by the process labeled "always" and the unlabeled process.   Instead use a single process structured as follows:
process
    file in_file: text open read_mode is "in.txt";
    variable line_str: line;
    variable address: std_logic_vector(31 downto 0);
    variable data: std_logic_vector(31 downto 0);
begin
    -- Initialize memory by reading file
    reset <= '1';

    readline(in_file, line_str);
    hread(line_str, address);
    starting_pc <= address;
    while not endfile(in_file) loop
        readline(in_file, line_str);
        hread(line_str, address);
        read(line_str, data);
        memory(to_integer(unsigned(address))) <= data;
        report "Initialized " & integer'image(to_integer(unsigned(address))) & " to " & 
              integer'image(to_integer(unsigned(data)));
    end loop;

    wait for 30 ns;

    reset <= '0';

    -- Write to Memory
    Write_loop : loop 
        wait until rising_edge(mem_write) ;
        memory(to_integer(unsigned(mem_address))) <= transport mem_data after DELAY;
    end loop ;
end process ; 

Note it would be appropriate to code reset in a separate process, however, not necessary. 
Are you using the whole memory?   If you are implementing 2**32 storage locations of memory, using a signal as the storage element and std_logic_vector as the data type, you are going to consume lots of memory and cause your simulator to run real slow. 
For some ideas, see the memory models on http://www.freemodelfoundry.com/
Also in our VHDL testbench class, http://www.synthworks.com/vhdl_testbench_verification.htm, we provide a package that implements sparse memory data structures to simplify the coding.   One of the benefits of these packages is that they use shared variables which allow multiple processes to access the data structure as you tried to do with a signal. 