1.  Technical Field
The present invention relates to an analog-digital converter which converts analog signals into digital signals, and to an image sensor including the analog-digital converter. 
2.  Related Art
A CMOS-type image sensor (hereinafter abbreviated as CMOS sensor) is an image sensor operated based on application of logic process, and characterized by the structure containing peripheral driving circuit, analog-digital (AD) converter, signal processing circuit, and other components as well as the image sensor mounted on the same chip.  The CMOS sensor including the AD converter currently draws particular attention, because the necessity for containing analog circuit structure which requires high SN ratio for camera design is eliminated in this CMOS sensor. 
Examples of the AD converter involve integration type AD converter and sequential comparison type AD converter.  The integration type AD converter produces less variation between analog signals and digital signals and thus secures preferable linearity.  However, the conversion speed achievable by the integration type AD converter is low.  The sequential comparison type AD converter achieves greater reduction of power consumption and higher conversion speed.  However, the area occupied by capacitor elements expands when the number of gradations (bit number) increases. 
For overcoming these drawbacks, a method disclosed in Japan Patent No.  3,507,800 uses a dual integration type AD circuit structure which makes separation between upper bit group and lower bit group and quantizes each of the groups by corresponding integration type AD circuits. 
The method shown in JP Patent No.  3,507,800 achieves high accuracy and reduces variation between analog signals and digital signals.  However, this method is difficult to sufficiently increase the speed of AD conversion since an integration type AD circuit is used twice in series. 
FIGS.  5 and 6 illustrate a method developed for overcoming this problem.  According to this method, upper m bit (m: 1 or larger natural number, m=2 in FIG.  5) is converted by sequential comparison type, and lower n bit (n: 1 or larger natural number, n=3 in FIG.  5) is converted by integration type, for AD conversion of an analog signal Vs. 
However, as illustrated in FIG.  7, the waveform of ramp voltage Vramp is slightly shifted upward or downward from the ideal waveform when a DA conversion circuit (3-bit DAC) 107 has offset or when a comparison circuit (comparator) 120 has delay for the integration type AD conversion of the lower bit.  In this case, AD conversion cannot be appropriately performed on the boundary between the upper bit and lower bit.