1.  Field of the Invention
This invention relates to a semiconductor memory integrated circuit made up of a cell array with an arrangement of electrically erasable and programmable nonvolatile memory cells and a transistor circuit disposed around the cell array (peripheral circuit), and a manufacturing method of the semiconductor memory integrated circuit. 
2.  Description of the Related Art
Memory cells of EEPROM flash memory has a transistor structure including stacked floating gates and control gates.  The floating gate of such a memory cell is commonly made of a polycrystalline silicon film doped with phosphorus to an adequate concentration.  Phosphorus concentration of the floating gate affects the quality of an underlying tunnel insulating film and the configuration of the floating gate itself by post thermal oxidation.  Since the quality of the tunnel insulating film and the floating gate configuration significantly influence the property and reliability of the memory cell, they need be properly controlled independently from other parameters. 
On the other hand, the transistor circuit disposed around the cell array (hereinbelow simply called peripheral circuit) is made by using a CMOS structure at least in a logic circuit.  To ensure that transistors of the peripheral circuit exert their performance required as surface channel type transistors, it is necessary to dope a p-type impurity {typically boron) into gate electrodes in case of MOS transistors or an n-type impurity (typically arsenic) into gate electrodes in case of NMOS transistors.  Additionally, to prevent depletion of gates, a doped amount not less than a predetermined concentration and activation of the impurity are indispensable. 
Taking account of these requirements for such a cell array and its peripheral circuit, for conventional flash memory, the following manufacturing process is used.  FIGS.  35(a) through 35(d) show major steps noticing the cell array region.  As shown in FIG.  35(a), a silicon substrate 1, having formed a tunnel oxide layer 2 thereon and a polycrystalline silicon film 3a on the tunnel oxide layer 2, is separated into respective device regions by STI (shallow trench isolation) technology.  That is, device isolation grooves 4 are made by RIE, and they are buried with a device isolation insulation film 5 as shown in FIG.  35.  The polycrystalline silicon film 3a will serve as a base layer of floating gates. 
This method of first stacking the polycrystalline Si film as a part of the floating gates and thereafter making a groove-like device isolation regions into the Si substrate is a technique very effective for miniaturizing memory cells while alleviating variance of electrical properties of the memory cells.  The method of making floating gates after making the device isolation regions is liable to be affected by concentration of an electric field near the device isolation regions, and also liable to invite variance in the amount of capacitance coupling between the floating gates and the Si substrate.  To prevent these problems, the use of a process unsuitable for miniaturizing memory cells is compelled. 
Next stacked is a polycrystalline silicon film 3b which will form an upper layer of the floating gates.  Let the polycrystalline silicon film 3b be doped with phosphorus.  As a result, in a later thermal step, phosphorus diffuses from the polycrystalline silicon film 3b into the underlying polycrystalline silicon film 3a, and it results in uniformly doping the impurity into the floating gates in form of a multi-layered film.  At that time, doping of a proper concentration of phosphorus will round corners of the floating concentration of the electric field to edges of the floating gates during write and erase operations. 
Excessively high phosphorus concentration of the floating gates will adversely affect the tunnel oxide film 2 under the floating gates.  Excessively low phosphorus concentration will leave lower corners of the floating gates square, and will invite concentration of the electric field.  This will cause variance and deterioration in reliability of write, erase and other properties of the memory cells.  Therefore, proper control of the phosphorus concentration in the floating gates is important for flash memory.  If arsenic is used as the impurity of the floating gates, corner rounding by thermal oxidation is not expected unlike the use of phosphorus, and phosphorus is used preferably. 
After the step of FIG.  35(C), the polycrystalline silicon film 3b is selectively etched to separate the film of the floating gates into cell regions, and thereafter, a gate insulation film 6 is formed and a polycrystalline silicon film 7 is stacked to form control gates.  Commonly used as the gate insulating film 6 is a composite film (ONO film) of oxide/nitride/oxide layers. 
Next directing to the peripheral circuit, in the status where the gate insulating film 6 is formed in the cell array region, in the peripheral circuit region, the gate insulating film is removed by etching, the polycrystalline silicon films 3a, 3b are also removed, and the tunnel oxide film is removed as well.  Then, after an appropriate gate oxide film is formed to comply with a resistance to pressure necessary for the respective transistor regions, a polycrystalline silicon film 7 used as control gates in the cell array region will be stacked.  That is, by patterning the polycrystalline silicon film 7, control gates in the cell array region and gated electrodes of transistors in the peripheral circuit are formed simultaneously. 
After the control gates of the cell array and gate electrodes of the peripheral circuit are made, an n-type impurity is ion-implanted into the cell array region and the NMOS transistor regions of the peripheral circuit, and a p-type impurity is additionally ion-implanted into the PMOS transistor regions of the peripheral circuit.  As a result, source and drain diffusion layers of the cell array region and the peripheral circuit region are formed, the n-type impurity is doped into the control gates of the cell array region and the gate electrodes of the NMOS transistor in the peripheral circuit, and the p-type impurity is doped into the gate electrodes of the PMOS transistor in the peripheral circuit. 
In the conventional process reviewed above, in the peripheral circuit region needs removing the tunnel oxide film formed over both the peripheral circuit region-and the cell array region, newly forming a gate oxide film for high-voltage circuit transistors, then selectively removing the gate oxide film by etching and thereafter forming a gate oxide film for low-voltage circuit transistors.  Repeating such etching steps of oxide films several times causes, in the peripheral circuit region, retraction of the device isolation insulating film already buried.  FIG.  36(a) shows an aspect of such retraction.  If the gate oxide film 8 is formed as shown in FIG.  36(b) on the structure shown in FIG.  36(a) to make gate electrodes 9, edge portions of the gate electrodes 9 enter into the concave portions of the device isolation insulating film in contact with side surfaces of device regions as shown by the broken line A.
Configuration as shown in FIG.  36(b) invites a short-channel effect opposite to a normal short-channel effect (opposite short-channel effect), in which the threshold value lowers when the peripheral circuit transistors are short-channeled.  Also invited are an increase of the leak current of the peripheral circuit transistors, deterioration of their sub-threshold characteristics and, hence, increase of the standby current in the peripheral circuit.  Further, deterioration of the reliability of the gate insulating film at end portions of the gate electrodes is also invited.