1.  Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device having a plurality of semiconductor chips installed on a support substrate. 
2.  Description of the Background Art
A multi-chip module (MCM) systemized by packaging a plurality of semiconductor chips having different functions on an insulating substrate in high density to function as a single semiconductor device has recently been developed.  Such a multi-chip module is disclosed in Japanese Patent Laying-Open No.  9-232505 (1997), for example. 
FIG.  22 is a schematic diagram showing a conventional semiconductor device (multi-chip module).  Referring to FIG.  22, a DRAM chip 201, a logic chip 202 and other functional chips 205 and 206 are installed on a support substrate 203 consisting of an insulating substrate in the conventional semiconductor device.  A plurality of input/output terminals 203a are provided on the outer periphery of the surface of the support substrate 203 at prescribed intervals. 
A plurality of input/output terminals 201a, 202a, 205a and 206a are provided on the upper surfaces of the DRAM chip 201, the logic chip 202 and the chips 205 and 206 respectively.  The DRAM chip 201 and the logic chip 202 are directly connected with each other by connecting the input/output terminals 201a and 202a with each other by a plurality of wires 207. 
The DRAM chip 201 is connected with the support substrate 203 by a plurality of wires 208, and the logic chip 202 is also connected with the support substrate 203 by a plurality of wires 209.  The chip 205 is connected with the DRAM chip 201 by a plurality of wires 210, and the chip 206 is connected with the logic chip 202 and the support substrate 203 by a plurality of wires 211 and 212 respectively. 
FIG.  23 is a circuit diagram showing the structure of an input/output circuit of each semiconductor chip in the conventional semiconductor device (multi-chip module) shown in FIG.  22.  Referring to FIG.  23, a circuit against static damage consisting of static damage preventive transistors 301 and 302 is connected to every input/output terminal 201a (202a) of the DRAM chip 201 and the logic chip 202.  The input/output terminal 201a (202a) is connected to an integrated circuit (not shown) in the chip through a resistor 303. 
However, the aforementioned conventional semiconductor device (multi-chip module) may not function as a semiconductor device due to mismatched timing of signal transmission between the chips 201, 202, 205 and 206 even if operations of these chips are individually tested and recognized as non-defective.  In this case, the design of any of the chips must be changed for re-forming the chip.  In this case, high-priced masks of not more than 1 μm in precision must be re-formed, to result in a fabrication period of several weeks.  Consequently, a long fabrication period is required for re-forming the chip, disadvantageously leading to a high fabrication cost. 
In the aforementioned conventional semiconductor device, further, the static damage preventive transistors 301 and 302 are connected to every input/output terminal 201a (202a) of the DRAM chip 201 and the logic chip 202 as shown in FIG.  23, and a signal transmission rate between the chips is disadvantageously reduced due to parasitic capacitances of the static damage preventive transistors 301 and 302. 
Further, the areas of the DRAM chip 201 and the logic chip 202 are disadvantageously increased due to the static damage preventive transistors 301 and 302 connected to every input/output terminal 201a (202a) of the DRAM chip 201 and the logic chip 202.