#NEWLINE# def test( ) : #NEWLINE# #INDENT# datawid = vast . Parameter ( 'DATAWID' , vast . Rvalue ( vast . IntConst ( '32' ) ) ) #NEWLINE# params = vast . Paramlist ( [ datawid ] ) #NEWLINE# clk = vast . Ioport ( vast . Input ( 'CLK' ) ) #NEWLINE# rst = vast . Ioport ( vast . Input ( 'RST' ) ) #NEWLINE# width = vast . Width ( vast . IntConst ( '7' ) , vast . IntConst ( '0' ) ) #NEWLINE# led = vast . Ioport ( vast . Output ( 'led' , width = width ) ) #NEWLINE# ports = vast . Portlist ( [ clk , rst , led ] ) #NEWLINE# width = vast . Width ( vast . Minus ( vast . Identifier ( 'DATAWID' ) , vast . IntConst ( '1' ) ) , vast . IntConst ( '0' ) ) #NEWLINE# count = vast . Reg ( 'count' , width = width ) #NEWLINE# assign = vast . Assign ( vast . Lvalue ( vast . Identifier ( 'led' ) ) , vast . Rvalue ( vast . Partselect ( vast . Identifier ( 'count' ) , vast . Minus ( vast . Identifier ( 'DATAWID' ) , vast . IntConst ( '1' ) ) , vast . Minus ( vast . Identifier ( 'DATAWID' ) , vast . IntConst ( '8' ) ) ) ) ) #NEWLINE# sens = vast . Sens ( vast . Identifier ( 'CLK' ) , type = 'posedge' ) #NEWLINE# senslist = vast . SensList ( [ sens ] ) #NEWLINE# assign_count_true = vast . NonblockingSubstitution ( vast . Lvalue ( vast . Identifier ( 'count' ) ) , vast . Rvalue ( vast . IntConst ( '0' ) ) ) #NEWLINE# if0_true = vast . Block ( [ if0_true ] ) #NEWLINE# count_plus_1 = vast . Plus ( vast . Identifier ( 'count' ) , vast . IntConst ( '1' ) ) #NEWLINE# cp1_times_2 = vast . Times ( count_plus_1 , vast . IntConst ( '2' ) ) #NEWLINE# cp1t2_plus_1 = vast . Plus ( cp1_times_2 , vast . IntConst ( '1' ) ) #NEWLINE# assign_count_false = vast . NonblockingSubstitution ( vast . Lvalue ( vast . Identifier ( 'count' ) ) , vast . Rvalue ( cp1t2_plus_1 ) ) #NEWLINE# if0_false = vast . Block ( [ assign_count_false ] ) #NEWLINE# if0 = vast . IfStatement ( vast . Identifier ( 'RST' ) , if0_true , if0_false ) #NEWLINE# statement = vast . Block ( [ if0 ] ) #NEWLINE# always = vast . Always ( senslist , statement ) #NEWLINE# items = [ ] #NEWLINE# items . append ( count ) #NEWLINE# items . append ( assign ) #NEWLINE# items . append ( always ) #NEWLINE# ast = vast . ModuleDef ( 'top' , params , ports , items ) #NEWLINE# codegen = ASTCodeGenerator ( ) #NEWLINE# rslt = codegen . visit ( ast ) #NEWLINE# print ( rslt ) #NEWLINE# assert ( expected == rslt )