#NEWLINE# def mkTest( length = 1024 ) : #NEWLINE# #INDENT# m = Module ( 'test' ) #NEWLINE# main = mkChatterClear ( length ) #NEWLINE# params = m . copy_params ( main ) #NEWLINE# ports = m . copy_sim_ports ( main ) #NEWLINE# clk = ports [ 'CLK' ] #NEWLINE# rst = ports [ 'RST' ] #NEWLINE# din = ports [ 'din' ] #NEWLINE# dout = ports [ 'dout' ] #NEWLINE# fsm = FSM ( m , 'fsm' , clk , rst ) #NEWLINE# count = m . TmpReg ( 32 , initval = 0 ) #NEWLINE# fsm . add ( din ( 0 ) ) #NEWLINE# fsm . add ( count . inc ( ) ) #NEWLINE# fsm . add ( count ( 0 ) , cond = ( count == 2000 ) ) #NEWLINE# fsm . goto_next ( ( count == 2000 ) ) #NEWLINE# fsm . add ( din ( 1 ) ) #NEWLINE# fsm . add ( count . inc ( ) ) #NEWLINE# fsm . add ( count ( 0 ) , cond = ( count == 10 ) ) #NEWLINE# fsm . goto_next ( ( count == 10 ) ) #NEWLINE# fsm . add ( din ( 0 ) ) #NEWLINE# fsm . add ( count . inc ( ) ) #NEWLINE# fsm . add ( count ( 0 ) , cond = ( clk == 10 ) ) #NEWLINE# fsm . goto_next ( ( count == 10 ) ) #NEWLINE# fsm . add ( din ( 1 ) ) #NEWLINE# fsm . add ( count . inc ( ) ) #NEWLINE# fsm . add ( count ( 0 ) , cond = ( count == 2000 ) ) #NEWLINE# fsm . goto_next ( ( count == 2000 ) ) #NEWLINE# fsm . add ( din ( 0 ) ) #NEWLINE# fsm . add ( count . inc ( ) ) #NEWLINE# fsm . add ( count ( 0 ) , cond = ( count == 10 ) ) #NEWLINE# fsm . goto_next ( ( count == 10 ) ) #NEWLINE# fsm . add ( din ( 1 ) ) #NEWLINE# fsm . add ( count . inc ( ) ) #NEWLINE# fsm . add ( count ( 0 ) , cond = ( count == 10 ) ) #NEWLINE# fsm . goto_next ( ( count == 10 ) ) #NEWLINE# fsm . add ( din ( 0 ) ) #NEWLINE# fsm . add ( count . inc ( ) ) #NEWLINE# fsm . add ( count ( 0 ) , cond = ( count == 2000 ) ) #NEWLINE# fsm . goto_next ( ( count == 2000 ) ) #NEWLINE# fsm . make_always ( ) #NEWLINE# uut = m . Instance ( main , 'uut' , params = m . connect_params ( main ) , ports = m . connect_ports ( main ) ) #NEWLINE# simulation . setup_waveform ( m , uut , m . get_vars ( ) ) #NEWLINE# simulation . setup_clock ( m , clk , hperiod = 5 ) #NEWLINE# init = simulation . setup_reset ( m , rst , m . make_reset ( ) , period = 100 ) #NEWLINE# nclk = simulation . next_clock #NEWLINE# init . add ( Delay ( ( 1000 * 100 ) ) , Systask ( 'finish' ) ) #NEWLINE# return m