#NEWLINE# @ qpu #NEWLINE# def sgemm_gpu_code( asm , n_threads ) : #NEWLINE# #INDENT# B_CUR_IDX = 0 #NEWLINE# K_IDX = 1 #NEWLINE# I_IDX = 2 #NEWLINE# J_IDX = 3 #NEWLINE# P_IDX = 4 #NEWLINE# Q_IDX = 5 #NEWLINE# R_IDX = 6 #NEWLINE# A_CUR_IDX = 7 #NEWLINE# C_CUR_IDX = 8 #NEWLINE# A_BASE_IDX = 9 #NEWLINE# B_BASE_IDX = 10 #NEWLINE# C_BASE_IDX = 11 #NEWLINE# A_STRIDE_IDX = 12 #NEWLINE# B_STRIDE_IDX = 13 #NEWLINE# C_STRIDE_IDX = 14 #NEWLINE# COEF_ADDR_IDX = 15 #NEWLINE# COMPLETED = 0 #NEWLINE# mov ( r0 , uniform ) #NEWLINE# mov ( r2 , 1 ) #NEWLINE# ldi ( null , mask ( P_IDX ) , set_flags = True ) #NEWLINE# mov ( r2 , uniform , cond = 'zs' ) #NEWLINE# ldi ( null , mask ( Q_IDX ) , set_flags = True ) #NEWLINE# mov ( r2 , uniform , cond = 'zs' ) #NEWLINE# ldi ( null , mask ( R_IDX ) , set_flags = True ) #NEWLINE# mov ( r2 , uniform , cond = 'zs' ) #NEWLINE# ldi ( null , mask ( A_BASE_IDX ) , set_flags = True ) #NEWLINE# mov ( r2 , uniform , cond = 'zs' ) #NEWLINE# ldi ( null , mask ( B_BASE_IDX ) , set_flags = True ) #NEWLINE# mov ( r2 , uniform , cond = 'zs' ) #NEWLINE# ldi ( null , mask ( C_BASE_IDX ) , set_flags = True ) #NEWLINE# mov ( r2 , uniform , cond = 'zs' ) #NEWLINE# ldi ( null , mask ( A_STRIDE_IDX ) , set_flags = True ) #NEWLINE# mov ( r2 , uniform , cond = 'zs' ) #NEWLINE# ldi ( null , mask ( B_STRIDE_IDX ) , set_flags = True ) #NEWLINE# mov ( r2 , uniform , cond = 'zs' ) #NEWLINE# ldi ( null , mask ( C_STRIDE_IDX ) , set_flags = True ) #NEWLINE# mov ( r2 , uniform , cond = 'zs' ) #NEWLINE# ldi ( null , mask ( COEF_ADDR_IDX ) , set_flags = True ) #NEWLINE# ldi ( r1 , ( 4 * 10 ) ) #NEWLINE# iadd ( r2 , r0 , r1 , cond = 'zs' ) #NEWLINE# nop ( ) #NEWLINE# rotate ( broadcast , r2 , ( - COEF_ADDR_IDX ) ) #NEWLINE# mov ( uniforms_address , r5 ) #NEWLINE# nop ( ) #NEWLINE# nop ( ) #NEWLINE# mov ( null , uniform ) #NEWLINE# mov ( null , uniform ) #NEWLINE# mov ( null , uniform , set_flags = True ) #NEWLINE# jzc ( L . skip_init ) #NEWLINE# nop ( ) #NEWLINE# nop ( ) #NEWLINE# nop ( ) #NEWLINE# L . skip_init #NEWLINE# rotate ( broadcast , r2 , ( - P_IDX ) ) #NEWLINE# shl ( r0 , r5 , 4 ) #NEWLINE# rotate ( broadcast , r2 , ( - R_IDX ) ) #NEWLINE# shl ( r1 , r5 , 8 ) #NEWLINE# rotate ( broadcast , r2 , ( - A_STRIDE_IDX ) ) #NEWLINE# imul24 ( r3 , r5 , r0 ) #NEWLINE# ldi ( null , mask ( A_BASE_IDX ) , set_flags = True ) #NEWLINE# iadd ( r2 , r2 , r3 , cond = 'zs' ) #NEWLINE# ldi ( null , mask ( B_BASE_IDX ) , set_flags = True ) #NEWLINE# iadd ( r2 , r2 , r1 , cond = 'zs' ) #NEWLINE# rotate ( broadcast , r2 , ( - C_STRIDE_IDX ) ) #NEWLINE# imul24 ( r3 , r5 , r0 ) #NEWLINE# ldi ( null , mask ( C_BASE_IDX ) , set_flags = True ) #NEWLINE# iadd ( r2 , r2 , r3 , cond = 'zs' , set_flags = False ) #NEWLINE# iadd ( r2 , r2 , r1 , cond = 'zs' ) #NEWLINE# mov ( tmu_noswap , 1 ) #NEWLINE# mov ( ra0 , 0.0 ) . mov ( rb0 , 0.0 ) #NEWLINE# mov ( ra1 , 0.0 ) . mov ( rb1 , 0.0 ) #NEWLINE# mov ( ra2 , 0.0 ) . mov ( rb2 , 0.0 ) #NEWLINE# mov ( ra3 , 0.0 ) . mov ( rb3 , 0.0 ) #NEWLINE# mov ( ra4 , 0.0 ) . mov ( rb4 , 0.0 ) #NEWLINE# mov ( ra5 , 0.0 ) . mov ( rb5 , 0.0 ) #NEWLINE# mov ( ra6 , 0.0 ) . mov ( rb6 , 0.0 ) #NEWLINE# mov ( ra7 , 0.0 ) . mov ( rb7 , 0.0 ) #NEWLINE# mov ( ra8 , 0.0 ) . mov ( rb8 , 0.0 ) #NEWLINE# mov ( ra9 , 0.0 ) . mov ( rb9 , 0.0 ) #NEWLINE# mov ( ra10 , 0.0 ) . mov ( rb10 , 0.0 ) #NEWLINE# mov ( ra11 , 0.0 ) . mov ( rb11 , 0.0 ) #NEWLINE# mov ( ra12 , 0.0 ) . mov ( rb12 , 0.0 ) #NEWLINE# mov ( ra13 , 0.0 ) . mov ( rb13 , 0.0 ) #NEWLINE# mov ( ra14 , 0.0 ) . mov ( rb14 , 0.0 ) #NEWLINE# mov ( ra15 , 0.0 ) . mov ( rb15 , 0.0 ) #NEWLINE# mov ( ra16 , 0.0 ) . mov ( rb16 , 0.0 ) #NEWLINE# mov ( ra17 , 0.0 ) . mov ( rb17 , 0.0 ) #NEWLINE# mov ( ra18 , 0.0 ) . mov ( rb18 , 0.0 ) #NEWLINE# mov ( ra19 , 0.0 ) . mov ( rb19 , 0.0 ) #NEWLINE# mov ( ra20 , 0.0 ) . mov ( rb20 , 0.0 ) #NEWLINE# mov ( ra21 , 0.0 ) . mov ( rb21 , 0.0 ) #NEWLINE# mov ( ra22 , 0.0 ) . mov ( rb22 , 0.0 ) #NEWLINE# mov ( ra23 , 0.0 ) . mov ( rb23 , 0.0 ) #NEWLINE# mov ( ra24 , 0.0 ) . mov ( rb24 , 0.0 ) #NEWLINE# mov ( ra25 , 0.0 ) . mov ( rb25 , 0.0 ) #NEWLINE# mov ( ra26 , 0.0 ) . mov ( rb26 , 0.0 ) #NEWLINE# mov ( ra27 , 0.0 ) . mov ( rb27 , 0.0 ) #NEWLINE# mov ( ra28 , 0.0 ) . mov ( rb28 , 0.0 ) #NEWLINE# mov ( ra29 , 0.0 ) . mov ( rb29 , 0.0 ) #NEWLINE# mov ( ra30 , 0.0 ) . mov ( rb30 , 0.0 ) #NEWLINE# mov ( ra31 , 0.0 ) . mov ( rb31 , 0.0 ) #NEWLINE# rotate ( broadcast , r2 , ( - P_IDX ) ) #NEWLINE# ldi ( null , mask ( I_IDX ) , set_flags = True ) #NEWLINE# mov ( r2 , r5 , cond = 'zs' ) #NEWLINE# L . i_loop #NEWLINE# rotate ( broadcast , r2 , ( - R_IDX ) ) #NEWLINE# ldi ( null , mask ( J_IDX ) , set_flags = True ) #NEWLINE# mov ( r2 , r5 , cond = 'zs' ) #NEWLINE# rotate ( broadcast , r2 , ( - I_IDX ) ) #NEWLINE# shl ( r0 , r5 , 4 ) #NEWLINE# rotate ( broadcast , r2 , ( - A_STRIDE_IDX ) ) #NEWLINE# imul24 ( r0 , r0 , r5 ) #NEWLINE# rotate ( broadcast , r2 , ( - A_BASE_IDX ) ) #NEWLINE# ldi ( null , mask ( A_CUR_IDX ) , set_flags = True ) #NEWLINE# isub ( r2 , r5 , r0 , cond = 'zs' ) #NEWLINE# L . j_loop #NEWLINE# rotate ( broadcast , r2 , ( - I_IDX ) ) #NEWLINE# shl ( r0 , r5 , 4 ) #NEWLINE# rotate ( broadcast , r2 , ( - C_STRIDE_IDX ) ) #NEWLINE# imul24 ( r0 , r0 , r5 ) #NEWLINE# rotate ( broadcast , r2 , ( - J_IDX ) ) #NEWLINE# shl ( r1 , r5 , 8 ) #NEWLINE# rotate ( broadcast , r2 , ( - C_BASE_IDX ) ) #NEWLINE# ldi ( null , mask ( C_CUR_IDX ) , set_flags = True ) #NEWLINE# isub ( r2 , r5 , r0 , cond = 'zs' , set_flags = False ) #NEWLINE# isub ( r2 , r2 , r1 , cond = 'zs' ) #NEWLINE# rotate ( broadcast , r2 , ( - B_BASE_IDX ) ) #NEWLINE# ldi ( null , mask ( B_CUR_IDX ) , set_flags = True ) #NEWLINE# isub ( r2 , r5 , r1 , cond = 'zs' ) #NEWLINE# nop ( ) #NEWLINE# rotate ( broadcast , r2 , ( - A_STRIDE_IDX ) ) #NEWLINE# imul24 ( r0 , element_number , r5 ) #NEWLINE# rotate ( broadcast , r2 , ( - A_CUR_IDX ) ) #NEWLINE# iadd ( r1 , r0 , r5 ) #NEWLINE# mov ( r3 , 0 ) #NEWLINE# rotate ( broadcast , r2 , ( - B_STRIDE_IDX ) ) #NEWLINE# ldi ( null , mask ( B_CUR_IDX ) , set_flags = True ) #NEWLINE# mov ( r3 , r5 , cond = 'zs' ) #NEWLINE# ldi ( null , mask ( K_IDX ) , set_flags = True ) #NEWLINE# mov ( r3 , ( - 1 ) , cond = 'zs' ) #NEWLINE# nop ( ) #NEWLINE# rotate ( broadcast , r2 , ( - Q_IDX ) ) #NEWLINE# ldi ( null , mask ( K_IDX ) , set_flags = True ) #NEWLINE# mov ( r2 , r5 , cond = 'zs' ) #NEWLINE# mov ( uniforms_address , r2 ) #NEWLINE# mov ( tmu0_s , r1 ) #NEWLINE# iadd ( r1 , r1 , 4 ) #NEWLINE# nop ( sig = 'load tmu0' ) #NEWLINE# iadd ( r2 , r2 , r3 ) . mov ( tmu0_s , r1 ) #NEWLINE# iadd ( r1 , r1 , 4 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra0 , ra0 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb0 , rb0 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# L . k_loop #NEWLINE# fadd ( ra1 , ra1 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb1 , rb1 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra2 , ra2 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb2 , rb2 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra3 , ra3 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb3 , rb3 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra4 , ra4 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb4 , rb4 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra5 , ra5 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb5 , rb5 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra6 , ra6 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb6 , rb6 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra7 , ra7 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb7 , rb7 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra8 , ra8 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb8 , rb8 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra9 , ra9 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb9 , rb9 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra10 , ra10 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb10 , rb10 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra11 , ra11 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb11 , rb11 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra12 , ra12 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb12 , rb12 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra13 , ra13 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb13 , rb13 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra14 , ra14 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb14 , rb14 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra15 , ra15 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb15 , rb15 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra16 , ra16 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb16 , rb16 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra17 , ra17 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb17 , rb17 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra18 , ra18 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb18 , rb18 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra19 , ra19 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb19 , rb19 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra20 , ra20 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb20 , rb20 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra21 , ra21 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb21 , rb21 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra22 , ra22 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb22 , rb22 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra23 , ra23 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb23 , rb23 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra24 , ra24 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb24 , rb24 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra25 , ra25 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb25 , rb25 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra26 , ra26 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb26 , rb26 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra27 , ra27 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb27 , rb27 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra28 , ra28 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb28 , rb28 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra29 , ra29 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb29 , rb29 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra30 , ra30 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb30 , rb30 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra31 , ra31 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb31 , rb31 , r0 , sig = 'load tmu0' ) . mov ( uniforms_address , r2 ) #NEWLINE# iadd ( r2 , r2 , r3 ) . mov ( tmu0_s , r1 ) #NEWLINE# jzc ( L . k_loop ) #NEWLINE# iadd ( r1 , r1 , 4 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( ra0 , ra0 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# fadd ( rb0 , rb0 , r0 ) . fmul ( r0 , r4 , uniform ) #NEWLINE# mov ( r1 , r4 , sig = 'load tmu0' ) #NEWLINE# fadd ( ra1 , ra1 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb1 , rb1 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra2 , ra2 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb2 , rb2 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra3 , ra3 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb3 , rb3 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra4 , ra4 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb4 , rb4 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra5 , ra5 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb5 , rb5 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra6 , ra6 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb6 , rb6 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra7 , ra7 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb7 , rb7 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra8 , ra8 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb8 , rb8 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra9 , ra9 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb9 , rb9 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra10 , ra10 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb10 , rb10 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra11 , ra11 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb11 , rb11 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra12 , ra12 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb12 , rb12 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra13 , ra13 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb13 , rb13 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra14 , ra14 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb14 , rb14 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra15 , ra15 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb15 , rb15 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra16 , ra16 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb16 , rb16 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra17 , ra17 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb17 , rb17 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra18 , ra18 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb18 , rb18 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra19 , ra19 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb19 , rb19 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra20 , ra20 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb20 , rb20 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra21 , ra21 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb21 , rb21 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra22 , ra22 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb22 , rb22 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra23 , ra23 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb23 , rb23 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra24 , ra24 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb24 , rb24 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra25 , ra25 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb25 , rb25 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra26 , ra26 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb26 , rb26 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra27 , ra27 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb27 , rb27 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra28 , ra28 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb28 , rb28 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra29 , ra29 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb29 , rb29 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra30 , ra30 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb30 , rb30 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( ra31 , ra31 , r0 ) . fmul ( r0 , r1 , uniform ) #NEWLINE# fadd ( rb31 , rb31 , r0 ) #NEWLINE# mutex_acquire ( ) #NEWLINE# rotate ( broadcast , r2 , ( - C_STRIDE_IDX ) ) #NEWLINE# setup_dma_load_stride ( r5 , tmp_reg = r3 ) #NEWLINE# rotate ( broadcast , r2 , ( - C_STRIDE_IDX ) ) #NEWLINE# ldi ( r3 , ( 4 * 16 ) ) #NEWLINE# isub ( broadcast , r5 , r3 ) #NEWLINE# setup_dma_store_stride ( r5 , tmp_reg = r3 ) #NEWLINE# setup_dma_load ( mode = '32bit horizontal' , Y = 0 , nrows = 16 , mpitch = 0 ) #NEWLINE# rotate ( broadcast , r2 , ( - C_CUR_IDX ) ) #NEWLINE# start_dma_load ( r5 ) #NEWLINE# mov ( r3 , r5 ) #NEWLINE# setup_dma_load ( mode = '32bit horizontal' , Y = 16 , X = 0 , nrows = 16 , mpitch = 0 ) #NEWLINE# ldi ( broadcast , ( 4 * 16 ) ) #NEWLINE# iadd ( vpm_ld_addr , r3 , r5 ) #NEWLINE# setup_dma_load ( mode = '32bit horizontal' , Y = 32 , X = 0 , nrows = 16 , mpitch = 0 ) #NEWLINE# ldi ( r0 , ( ( 4 * 16 ) * 2 ) ) #NEWLINE# iadd ( vpm_ld_addr , r3 , r0 ) #NEWLINE# setup_dma_load ( mode = '32bit horizontal' , Y = 48 , X = 0 , nrows = 16 , mpitch = 0 ) #NEWLINE# ldi ( r0 , ( ( 4 * 16 ) * 3 ) ) #NEWLINE# iadd ( vpm_ld_addr , r3 , r0 ) #NEWLINE# rotate ( r0 , r2 , ( - COEF_ADDR_IDX ) ) #NEWLINE# mov ( uniforms_address , r0 ) #NEWLINE# setup_vpm_read ( mode = '32bit vertical' , Y = 0 , X = 0 , nrows = 16 ) #NEWLINE# setup_vpm_write ( mode = '32bit vertical' , Y = 0 , X = 0 ) #NEWLINE# mov ( r1 , uniform ) #NEWLINE# mov ( broadcast , uniform ) #NEWLINE# fmul ( ra0 , ra0 , r1 ) #NEWLINE# fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra0 , r0 ) . fmul ( rb0 , rb0 , r1 ) #NEWLINE# mov ( ra0 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb0 , r0 ) . fmul ( ra1 , ra1 , r1 ) #NEWLINE# mov ( rb0 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra1 , r0 ) . fmul ( rb1 , rb1 , r1 ) #NEWLINE# mov ( ra1 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb1 , r0 ) . fmul ( ra2 , ra2 , r1 ) #NEWLINE# mov ( rb1 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra2 , r0 ) . fmul ( rb2 , rb2 , r1 ) #NEWLINE# mov ( ra2 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb2 , r0 ) . fmul ( ra3 , ra3 , r1 ) #NEWLINE# mov ( rb2 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra3 , r0 ) . fmul ( rb3 , rb3 , r1 ) #NEWLINE# mov ( ra3 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb3 , r0 ) . fmul ( ra4 , ra4 , r1 ) #NEWLINE# mov ( rb3 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra4 , r0 ) . fmul ( rb4 , rb4 , r1 ) #NEWLINE# mov ( ra4 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb4 , r0 ) . fmul ( ra5 , ra5 , r1 ) #NEWLINE# mov ( rb4 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra5 , r0 ) . fmul ( rb5 , rb5 , r1 ) #NEWLINE# mov ( ra5 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb5 , r0 ) . fmul ( ra6 , ra6 , r1 ) #NEWLINE# mov ( rb5 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra6 , r0 ) . fmul ( rb6 , rb6 , r1 ) #NEWLINE# mov ( ra6 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb6 , r0 ) . fmul ( ra7 , ra7 , r1 ) #NEWLINE# mov ( rb6 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra7 , r0 ) . fmul ( rb7 , rb7 , r1 ) #NEWLINE# mov ( ra7 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb7 , r0 ) #NEWLINE# mov ( rb7 , 0.0 ) #NEWLINE# setup_dma_store ( mode = '32bit horizontal' , Y = 0 , nrows = 16 ) #NEWLINE# start_dma_store ( r3 ) #NEWLINE# setup_vpm_read ( mode = '32bit vertical' , Y = 16 , X = 0 , nrows = 16 ) #NEWLINE# setup_vpm_write ( mode = '32bit vertical' , Y = 16 , X = 0 ) #NEWLINE# fmul ( ra8 , ra8 , r1 ) #NEWLINE# fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra8 , r0 ) . fmul ( rb8 , rb8 , r1 ) #NEWLINE# mov ( ra8 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb8 , r0 ) . fmul ( ra9 , ra9 , r1 ) #NEWLINE# mov ( rb8 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra9 , r0 ) . fmul ( rb9 , rb9 , r1 ) #NEWLINE# mov ( ra9 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb9 , r0 ) . fmul ( ra10 , ra10 , r1 ) #NEWLINE# mov ( rb9 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra10 , r0 ) . fmul ( rb10 , rb10 , r1 ) #NEWLINE# mov ( ra10 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb10 , r0 ) . fmul ( ra11 , ra11 , r1 ) #NEWLINE# mov ( rb10 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra11 , r0 ) . fmul ( rb11 , rb11 , r1 ) #NEWLINE# mov ( ra11 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb11 , r0 ) . fmul ( ra12 , ra12 , r1 ) #NEWLINE# mov ( rb11 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra12 , r0 ) . fmul ( rb12 , rb12 , r1 ) #NEWLINE# mov ( ra12 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb12 , r0 ) . fmul ( ra13 , ra13 , r1 ) #NEWLINE# mov ( rb12 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra13 , r0 ) . fmul ( rb13 , rb13 , r1 ) #NEWLINE# mov ( ra13 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb13 , r0 ) . fmul ( ra14 , ra14 , r1 ) #NEWLINE# mov ( rb13 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra14 , r0 ) . fmul ( rb14 , rb14 , r1 ) #NEWLINE# mov ( ra14 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb14 , r0 ) . fmul ( ra15 , ra15 , r1 ) #NEWLINE# mov ( rb14 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra15 , r0 ) . fmul ( rb15 , rb15 , r1 ) #NEWLINE# mov ( ra15 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb15 , r0 ) #NEWLINE# mov ( rb15 , 0.0 ) #NEWLINE# setup_dma_store ( mode = '32bit horizontal' , Y = 16 , nrows = 16 ) #NEWLINE# ldi ( r0 , ( 4 * 16 ) ) #NEWLINE# iadd ( vpm_st_addr , r3 , r0 ) #NEWLINE# wait_dma_load ( ) #NEWLINE# setup_vpm_read ( mode = '32bit vertical' , X = 0 , Y = 32 , nrows = 16 ) #NEWLINE# setup_vpm_write ( mode = '32bit vertical' , X = 0 , Y = 32 ) #NEWLINE# fmul ( ra16 , ra16 , r1 ) #NEWLINE# fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra16 , r0 ) . fmul ( rb16 , rb16 , r1 ) #NEWLINE# mov ( ra16 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb16 , r0 ) . fmul ( ra17 , ra17 , r1 ) #NEWLINE# mov ( rb16 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra17 , r0 ) . fmul ( rb17 , rb17 , r1 ) #NEWLINE# mov ( ra17 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb17 , r0 ) . fmul ( ra18 , ra18 , r1 ) #NEWLINE# mov ( rb17 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra18 , r0 ) . fmul ( rb18 , rb18 , r1 ) #NEWLINE# mov ( ra18 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb18 , r0 ) . fmul ( ra19 , ra19 , r1 ) #NEWLINE# mov ( rb18 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra19 , r0 ) . fmul ( rb19 , rb19 , r1 ) #NEWLINE# mov ( ra19 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb19 , r0 ) . fmul ( ra20 , ra20 , r1 ) #NEWLINE# mov ( rb19 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra20 , r0 ) . fmul ( rb20 , rb20 , r1 ) #NEWLINE# mov ( ra20 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb20 , r0 ) . fmul ( ra21 , ra21 , r1 ) #NEWLINE# mov ( rb20 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra21 , r0 ) . fmul ( rb21 , rb21 , r1 ) #NEWLINE# mov ( ra21 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb21 , r0 ) . fmul ( ra22 , ra22 , r1 ) #NEWLINE# mov ( rb21 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra22 , r0 ) . fmul ( rb22 , rb22 , r1 ) #NEWLINE# mov ( ra22 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb22 , r0 ) . fmul ( ra23 , ra23 , r1 ) #NEWLINE# mov ( rb22 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra23 , r0 ) . fmul ( rb23 , rb23 , r1 ) #NEWLINE# mov ( ra23 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb23 , r0 ) #NEWLINE# mov ( rb23 , 0.0 ) #NEWLINE# setup_dma_store ( mode = '32bit horizontal' , Y = 32 , nrows = 16 ) #NEWLINE# ldi ( r0 , ( ( 4 * 16 ) * 2 ) ) #NEWLINE# iadd ( vpm_st_addr , r3 , r0 ) #NEWLINE# setup_vpm_read ( mode = '32bit vertical' , X = 0 , Y = 48 , nrows = 16 ) #NEWLINE# setup_vpm_write ( mode = '32bit vertical' , X = 0 , Y = 48 ) #NEWLINE# fmul ( ra24 , ra24 , r1 ) #NEWLINE# fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra24 , r0 ) . fmul ( rb24 , rb24 , r1 ) #NEWLINE# mov ( ra24 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb24 , r0 ) . fmul ( ra25 , ra25 , r1 ) #NEWLINE# mov ( rb24 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra25 , r0 ) . fmul ( rb25 , rb25 , r1 ) #NEWLINE# mov ( ra25 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb25 , r0 ) . fmul ( ra26 , ra26 , r1 ) #NEWLINE# mov ( rb25 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra26 , r0 ) . fmul ( rb26 , rb26 , r1 ) #NEWLINE# mov ( ra26 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb26 , r0 ) . fmul ( ra27 , ra27 , r1 ) #NEWLINE# mov ( rb26 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra27 , r0 ) . fmul ( rb27 , rb27 , r1 ) #NEWLINE# mov ( ra27 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb27 , r0 ) . fmul ( ra28 , ra28 , r1 ) #NEWLINE# mov ( rb27 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra28 , r0 ) . fmul ( rb28 , rb28 , r1 ) #NEWLINE# mov ( ra28 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb28 , r0 ) . fmul ( ra29 , ra29 , r1 ) #NEWLINE# mov ( rb28 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra29 , r0 ) . fmul ( rb29 , rb29 , r1 ) #NEWLINE# mov ( ra29 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb29 , r0 ) . fmul ( ra30 , ra30 , r1 ) #NEWLINE# mov ( rb29 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra30 , r0 ) . fmul ( rb30 , rb30 , r1 ) #NEWLINE# mov ( ra30 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb30 , r0 ) . fmul ( ra31 , ra31 , r1 ) #NEWLINE# mov ( rb30 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , ra31 , r0 ) . fmul ( rb31 , rb31 , r1 ) #NEWLINE# mov ( ra31 , 0.0 ) . fmul ( r0 , vpm , r5 ) #NEWLINE# fadd ( vpm , rb31 , r0 ) #NEWLINE# mov ( rb31 , 0.0 ) #NEWLINE# setup_dma_store ( mode = '32bit horizontal' , Y = 48 , nrows = 16 ) #NEWLINE# ldi ( r0 , ( ( 4 * 16 ) * 3 ) ) #NEWLINE# iadd ( vpm_st_addr , r3 , r0 ) #NEWLINE# wait_dma_store ( ) #NEWLINE# mutex_release ( ) #NEWLINE# rotate ( broadcast , r2 , ( - J_IDX ) ) #NEWLINE# isub ( r0 , r5 , 1 ) #NEWLINE# jzc ( L . j_loop ) #NEWLINE# ldi ( null , mask ( J_IDX ) , set_flags = True ) #NEWLINE# mov ( r2 , r0 , cond = 'zs' ) #NEWLINE# nop ( ) #NEWLINE# rotate ( broadcast , r2 , ( - C_BASE_IDX ) ) #NEWLINE# isub ( r0 , r5 , 1 ) #NEWLINE# jzc ( L . i_loop ) #NEWLINE# ldi ( null , mask ( I_IDX ) , set_flags = True ) #NEWLINE# mov ( r2 , r0 , cond = 'zs' ) #NEWLINE# nop ( ) #NEWLINE# sema_up ( COMPLETED ) #NEWLINE# rotate ( broadcast , r2 , ( - COEF_ADDR_IDX ) ) #NEWLINE# mov ( uniforms_address , r5 ) #NEWLINE# nop ( ) #NEWLINE# nop ( ) #NEWLINE# mov ( null , uniform ) #NEWLINE# mov ( null , uniform ) #NEWLINE# mov ( null , uniform , set_flags = True ) #NEWLINE# jzc ( L . skip_fin ) #NEWLINE# nop ( ) #NEWLINE# nop ( ) #NEWLINE# nop ( ) #NEWLINE# for i in range ( n_threads ) : #NEWLINE# #INDENT# sema_down ( COMPLETED ) #NEWLINE# #UNINDENT# interrupt ( ) #NEWLINE# L . skip_fin #NEWLINE# exit ( interrupt = False )