Datasets:

davide221

/

hdl-raw-35k

like 0

malkadi/FGPU

RTL/floating_point/fmul.vhd

-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.1 -- IP Revision: 2 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_1_2; USE floating_point_v7_1_2.floating_point_v7_1_2; ENTITY fmul IS PORT ( aclk : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END fmul; ARCHITECTURE fmul_arch OF fmul IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF fmul_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_1_2 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER; C_FIXED_DATA_UNSIGNED : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_1_2; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_1_2 GENERIC MAP ( C_XDEVICEFAMILY => "zynq", C_HAS_ADD => 0, C_HAS_SUBTRACT => 0, C_HAS_MULTIPLY => 1, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 24, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 24, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 24, C_RESULT_WIDTH => 32, C_RESULT_FRACTION_WIDTH => 24, C_COMPARE_OPERATION => 8, C_LATENCY => 8, C_OPTIMIZATION => 1, C_MULT_USAGE => 2, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 0, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 1, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 32, C_RESULT_TUSER_WIDTH => 1, C_FIXED_DATA_UNSIGNED => 0 ) PORT MAP ( aclk => aclk, aclken => '1', aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => s_axis_b_tvalid, s_axis_b_tdata => s_axis_b_tdata, s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END fmul_arch;

gpl-3.0

51eadc17385f1b2f8c673bdac989a84e

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_float_8ALUs_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FSQRT_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

4bf42eec09d2799d79016980c8054233

Kinxil/VHDL_Projects

Mandelbrot/cpt_iter.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use work.CONSTANTS.all; use work.CONFIG_MANDELBROT.all; entity cpt_iter is Port ( clock : in STD_LOGIC; reset : in STD_LOGIC; inib : in std_logic; endcalcul : in STD_LOGIC; maxiter : in STD_LOGIC; iter : out STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0)); end cpt_iter; architecture Behavioral of cpt_iter is Signal iterS : unsigned(ITER_RANGE-1 downto 0); begin process(reset,clock) begin if reset='1' then iterS<=to_unsigned(5,ITER_RANGE); elsif rising_edge(clock) then if maxiter = '1' then iterS <= to_unsigned(ITER_MAX,ITER_RANGE); elsif inib = '1' then if endcalcul ='1' then if iterS < (ITER_MAX-10) then iterS<=iterS+1; else iterS<=to_unsigned(10,ITER_RANGE); end if; end if; end if; end if; end process; iter<=std_logic_vector(iterS); end Behavioral;

gpl-3.0

47e1e04b1d0e8c2f67d10dec8ff46bed

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_fsqrt_uitofp.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 3; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

20fde2ec2a04026663c15c3fa01642d6

malkadi/FGPU

RTL/CU_instruction_dispatcher.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity CU_instruction_dispatcher is --{{{ port( clk, nrst : in std_logic; cram_rqst : out std_logic := '0'; cram_rdAddr : out unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); cram_rdAddr_conf : in unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); cram_rdData : in std_logic_vector(DATA_W-1 downto 0); -- cram_rdData is delayed by 1 clock cycle to cram_rdAddr_conf PC_indx : in integer range 0 to N_WF_CU-1; --response in two clk cycles wf_active : in std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); pc_updated : in std_logic_vector(N_WF_CU-1 downto 0); PCs : in CRAM_ADDR_ARRAY(N_WF_CU-1 downto 0); pc_rdy : out std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); instr : out std_logic_vector(DATA_W-1 downto 0) := (others => '0'); -- 1 clock cycle delayed after pc_rdy instr_gmem_op : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); instr_scratchpad_ld : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); instr_gmem_read : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); instr_branch : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); instr_jump : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); instr_fpu : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); branch_distance : out branch_distance_vec(0 to N_WF_CU-1) := (others=>(others=>'0')); wf_retired : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0') ); end CU_instruction_dispatcher; -- }}} architecture Behavioral of CU_instruction_dispatcher is -- internal signals definitions {{{ signal cram_rdAddr_i : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal pc_rdy_i : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_retired_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_gmem_op_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_scratchpad_ld_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_branch_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_jump_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_fpu_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_gmem_read_i : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal branch_distance_i : branch_distance_vec(0 to N_WF_CU-1) := (others=>(others=>'0')); -- }}} -- signals definitions {{{ type st_cram_type is (request, wait_resp, check); type instr_vec_type is array (N_WF_CU-1 downto 0) of std_logic_vector(DATA_W-1 downto 0); -- global FSM signals signal instr_vec, instr_vec_n : instr_vec_type := (others=>(others=>'0')); signal st_cram, st_cram_n : st_cram_type := check; signal cram_ack : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); -- next signals signal cram_rdAddr_n : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal pc_rdy_n : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal cram_rdData_gmem_op : std_logic := '0'; signal instr_gmem_op_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_scratchpad_ld_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_branch_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_jump_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_fpu_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_gmem_read_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_retired_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal branch_distance_n : branch_distance_vec(0 to N_WF_CU-1) := (others=>(others=>'0')); -- }}} begin -- internal signals -------------------------------------------------------------------------------------{{{ cram_rdAddr <= cram_rdAddr_i; pc_rdy <= pc_rdy_i; wf_retired <= wf_retired_i; instr_gmem_op <= instr_gmem_op_i; instr_scratchpad_ld <= instr_scratchpad_ld_i; instr_gmem_read <= instr_gmem_read_i; instr_branch <= instr_branch_i; instr_jump <= instr_jump_i; instr_fpu <= instr_fpu_i; branch_distance <= branch_distance_i; ---------------------------------------------------------------------------------------------------------}}} -- cram FSM ----------------------------------------------------------------------------------- {{{ process(clk) begin if rising_edge(clk) then if nrst = '0' then st_cram <= check; instr_gmem_op_i <= (others=>'0'); instr_scratchpad_ld_i <= (others=>'0'); instr_branch_i <= (others=>'0'); instr_jump_i <= (others=>'0'); instr_fpu_i <= (others=>'0'); branch_distance_i <= (others=>(others=>'0')); instr_gmem_read_i <= (others=>'0'); wf_retired_i <= (others=>'0'); pc_rdy_i <= (others=>'0'); cram_rdAddr_i <= (others=>'0'); instr_vec <= (others=>(others=>'0')); instr <= (others=>'0'); else st_cram <= st_cram_n; pc_rdy_i <= pc_rdy_n; cram_rdAddr_i <= cram_rdAddr_n; instr_vec <= instr_vec_n; instr <= instr_vec(PC_indx); instr_gmem_op_i <= instr_gmem_op_n; instr_scratchpad_ld_i <= instr_scratchpad_ld_n; branch_distance_i <= branch_distance_n; instr_branch_i <= instr_branch_n; instr_jump_i <= instr_jump_n; instr_fpu_i <= instr_fpu_n; instr_gmem_read_i <= instr_gmem_read_n; wf_retired_i <= wf_retired_n; cram_ack <= (others=>'0'); for i in 0 to N_WF_CU-1 loop if pc_rdy_i(i) = '0' and pc_updated(i) = '0' and PCs(i) = cram_rdAddr_conf and wf_active(i) = '1' then cram_ack(i) <= '1'; end if; end loop; -- for i in 0 to N_WF_CU-1 loop -- if wf_activate(i) = '1' then -- wf_active(i) <= '1'; -- elsif wf_retired_i(i) = '1' then -- wf_active(i) <= '0'; -- end if; -- end loop; end if; end if; end process; WFs_bufs: for i in 0 to N_WF_CU-1 generate begin WF_buf: process(pc_updated(i), pc_rdy_i(i), cram_rdData, instr_vec(i), wf_retired_i(i), instr_gmem_op_i(i), instr_branch_i(i), instr_gmem_read_i(i), branch_distance_i(i), cram_ack(i), instr_jump_i(i), instr_fpu_i(i), instr_scratchpad_ld_i(i)) begin pc_rdy_n(i) <= pc_rdy_i(i); instr_vec_n(i) <= instr_vec(i); wf_retired_n(i) <= wf_retired_i(i); instr_gmem_op_n(i) <= instr_gmem_op_i(i); instr_scratchpad_ld_n(i) <= instr_scratchpad_ld_i(i); branch_distance_n(i) <= branch_distance_i(i); instr_branch_n(i) <= instr_branch_i(i); instr_jump_n(i) <= instr_jump_i(i); instr_fpu_n(i) <= instr_fpu_i(i); instr_gmem_read_n(i) <= instr_gmem_read_i(i); -- if wf_active(i) = '0' then -- wf_retired_n(i) <= '0'; -- end if; if pc_updated(i) = '1' then pc_rdy_n(i) <= '0'; elsif cram_ack(i) = '1' then instr_vec_n(i) <= cram_rdData; instr_gmem_op_n(i) <= '0'; instr_gmem_read_n(i) <= '0'; instr_branch_n(i) <= '0'; instr_jump_n(i) <= '0'; instr_fpu_n(i) <= '0'; pc_rdy_n(i) <= '1'; wf_retired_n(i) <= '0'; instr_scratchpad_ld_n(i) <= '0'; case cram_rdData(FAMILY_POS+FAMILY_W-1 downto FAMILY_POS) is when GLS_FAMILY => instr_gmem_op_n(i) <= '1'; instr_gmem_read_n(i) <= not cram_rdData(CODE_POS+CODE_W-1); when ATO_FAMILY => instr_gmem_op_n(i) <= '1'; instr_gmem_read_n(i) <= '1'; when BRA_FAMILY => if cram_rdData(CODE_POS+CODE_W-1 downto CODE_POS) = JSUB then instr_jump_n(i) <= '1'; else instr_branch_n(i) <= '1'; end if; branch_distance_n(i) <= unsigned(cram_rdData(BRANCH_ADDR_POS+BRANCH_ADDR_W-1 downto BRANCH_ADDR_POS)); when CTL_FAMILY => if cram_rdData(CODE_POS+CODE_W-1 downto CODE_POS) = RET then wf_retired_n(i) <= '1'; end if; when LSI_FAMILY => instr_scratchpad_ld_n(i) <= not cram_rdData(CODE_POS+CODE_W-1); when FLT_FAMILY => instr_fpu_n(i) <= '1'; when others => end case; end if; end process; end generate; process(st_cram, cram_rdAddr_i, cram_rdAddr_conf, pc_rdy_i, wf_active, PCs) begin cram_rdAddr_n <= cram_rdAddr_i; cram_rqst <= '0'; st_cram_n <= st_cram; case st_cram is when check => for i in 0 to N_WF_CU-1 loop if wf_active(i)='1' and pc_rdy_i(i)='0' then st_cram_n <= request; cram_rdAddr_n <= PCs(i); end if; end loop; when request => cram_rqst <= '1'; st_cram_n <= wait_resp; when wait_resp => cram_rqst <= '1'; if cram_rdAddr_conf = cram_rdAddr_i then st_cram_n <= check; cram_rqst <= '0'; end if; end case; end process; ---------------------------------------------------------------------------------------------------------}}} end Behavioral;

gpl-3.0

a9a2f45df88b09bf35c95c9cee5bb24b

preusser/q27

src/vhdl/PoC/xilinx/xil_SystemMonitor_Virtex6.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Patrick Lehmann -- -- Module: System Monitor wrapper for temperature supervision applications -- -- Description: -- ------------------------------------ -- This module wraps a Virtex-6 System Monitor primitive to report if preconfigured -- temperature values are overrun. -- -- Temperature curve: -- ------------------ -- -- | /-----\ -- Temp_ov on=80 | - - - - - - /-------/ \ -- | / | \ -- Temp_ov off=60 | - - - - - / - - - - | - - - - \----\ -- | / | \ -- | / | | \ -- Temp_us on=35 | - /---/ | | \ -- Temp_us off=30 | - / - -|- - - - - - | - - - - - - -|- \------\ -- | / | | | \ -- ----------------|--------|------------|--------------|----------|--------- -- pwm = | min | medium | max | medium | min -- -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.NUMERIC_STD.all; LIBRARY UniSim; USE UniSim.vComponents.ALL; entity xil_SystemMonitor_Virtex6 is port ( Reset : in STD_LOGIC; -- Reset signal for the System Monitor control logic Alarm_UserTemp : out STD_LOGIC; -- Temperature-sensor alarm output Alarm_OverTemp : out STD_LOGIC; -- Over-Temperature alarm output Alarm : out STD_LOGIC; -- OR'ed output of all the Alarms VP : in STD_LOGIC; -- Dedicated Analog Input Pair VN : in STD_LOGIC ); end; architecture xilinx of xil_SystemMonitor_Virtex6 is signal FLOAT_VCCAUX_ALARM : STD_LOGIC; signal FLOAT_VCCINT_ALARM : STD_LOGIC; signal aux_channel_p : STD_LOGIC_VECTOR(15 downto 0); signal aux_channel_n : STD_LOGIC_VECTOR(15 downto 0); signal SysMonitor_Alarm : STD_LOGIC_VECTOR(2 downto 0); signal SysMonitor_OverTemp : STD_LOGIC; begin genAUXChannel : for i in 0 to 15 generate aux_channel_p(i) <= '0'; aux_channel_n(i) <= '0'; end generate; SysMonitor : SYSMON generic map ( INIT_40 => x"0000", -- config reg 0 INIT_41 => x"300c", -- config reg 1 INIT_42 => x"0a00", -- config reg 2 INIT_48 => x"0100", -- Sequencer channel selection INIT_49 => x"0000", -- Sequencer channel selection INIT_4A => x"0000", -- Sequencer Average selection INIT_4B => x"0000", -- Sequencer Average selection INIT_4C => x"0000", -- Sequencer Bipolar selection INIT_4D => x"0000", -- Sequencer Bipolar selection INIT_4E => x"0000", -- Sequencer Acq time selection INIT_4F => x"0000", -- Sequencer Acq time selection INIT_50 => x"a418", -- Temp alarm trigger INIT_51 => x"5999", -- Vccint upper alarm limit INIT_52 => x"e000", -- Vccaux upper alarm limit INIT_53 => x"b363", -- Temp alarm OT upper INIT_54 => x"9c87", -- Temp alarm reset INIT_55 => x"5111", -- Vccint lower alarm limit INIT_56 => x"caaa", -- Vccaux lower alarm limit INIT_57 => x"a425", -- Temp alarm OT reset SIM_DEVICE => "VIRTEX6", SIM_MONITOR_FILE => "SystemMonitor_sim.txt" ) port map ( -- Control and Clock RESET => Reset, CONVSTCLK => '0', CONVST => '0', -- DRP port DCLK => '0', DEN => '0', DADDR => "0000000", DWE => '0', DI => x"0000", DO => open, DRDY => open, -- External analog inputs VAUXN => aux_channel_n(15 downto 0), VAUXP => aux_channel_p(15 downto 0), VN => VN, VP => VP, -- Alarms OT => SysMonitor_OverTemp, ALM => SysMonitor_Alarm, -- Status CHANNEL => open, BUSY => open, EOC => open, EOS => open, JTAGBUSY => open, JTAGLOCKED => open, JTAGMODIFIED => open ); Alarm_UserTemp <= SysMonitor_Alarm(0); Alarm_OverTemp <= SysMonitor_OverTemp; Alarm <= SysMonitor_Alarm(0) or SysMonitor_OverTemp; end;

agpl-3.0

d1eef6130d2fe5c57ac20109d57f6d82

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_2CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

1426be4e6fdf5b9c0d6fe9b113384af1

jpidancet/mips

rtl/mips_defs.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; package mips_defs is subtype mips_opcode_type is std_logic_vector(5 downto 0); subtype mips_func_type is std_logic_vector(5 downto 0); constant OP_SPECIAL : std_logic_vector(5 downto 0) := "000000"; constant OP_J : std_logic_vector(5 downto 0) := "000010"; constant OP_JAL : std_logic_vector(5 downto 0) := "000011"; constant OP_BEQ : std_logic_vector(5 downto 0) := "000100"; constant OP_BNE : std_logic_vector(5 downto 0) := "000101"; constant OP_ADDI : std_logic_vector(5 downto 0) := "001000"; constant OP_ADDIU : std_logic_vector(5 downto 0) := "001001"; constant OP_SLTI : std_logic_vector(5 downto 0) := "001010"; -- Not implemented constant OP_SLTIU : std_logic_vector(5 downto 0) := "001011"; -- Not implemented constant OP_ANDI : std_logic_vector(5 downto 0) := "001100"; constant OP_ORI : std_logic_vector(5 downto 0) := "001101"; constant OP_LUI : std_logic_vector(5 downto 0) := "001111"; constant OP_LB : std_logic_vector(5 downto 0) := "100000"; -- Not implemented constant OP_LW : std_logic_vector(5 downto 0) := "100011"; constant OP_LBU : std_logic_vector(5 downto 0) := "100100"; -- Not implemented constant OP_LHU : std_logic_vector(5 downto 0) := "100101"; -- Not implemented constant OP_SB : std_logic_vector(5 downto 0) := "101000"; -- Not implemented constant OP_SH : std_logic_vector(5 downto 0) := "101001"; -- Not implemented constant OP_SW : std_logic_vector(5 downto 0) := "101011"; constant OP_LL : std_logic_vector(5 downto 0) := "110000"; -- Not implemented constant OP_SC : std_logic_vector(5 downto 0) := "111000"; -- Not implemented constant FUNC_SLL : std_logic_vector(5 downto 0) := "000000"; constant FUNC_SRL : std_logic_vector(5 downto 0) := "000010"; constant FUNC_JR : std_logic_vector(5 downto 0) := "001000"; constant FUNC_JALR : std_logic_vector(5 downto 0) := "001001"; constant FUNC_ADD : std_logic_vector(5 downto 0) := "100000"; constant FUNC_ADDU : std_logic_vector(5 downto 0) := "100001"; constant FUNC_SUB : std_logic_vector(5 downto 0) := "100010"; constant FUNC_SUBU : std_logic_vector(5 downto 0) := "100011"; constant FUNC_AND : std_logic_vector(5 downto 0) := "100100"; constant FUNC_OR : std_logic_vector(5 downto 0) := "100101"; constant FUNC_XOR : std_logic_vector(5 downto 0) := "100110"; constant FUNC_NOR : std_logic_vector(5 downto 0) := "100111"; constant FUNC_SLT : std_logic_vector(5 downto 0) := "101010"; constant FUNC_SLTU : std_logic_vector(5 downto 0) := "101011"; type branch_type is (NO_BRANCH, BRANCH_COND, JUMP_IMM, JUMP_REG); type extend_type is (ZERO_EXTEND, SIGN_EXTEND, SHIFT16_EXTEND); type compare_type is (CMP_EQUAL, CMP_NOT_EQUAL, CMP_GREATER, CMP_GREATER_OR_EQUAL, CMP_LESS, CMP_LESS_OR_EQUAL); type alucontrol_type is (ALU_SLL, ALU_SRL, ALU_AND, ALU_XOR, ALU_NOR, ALU_OR, ALU_ADD, ALU_SUB, ALU_SLT, ALU_SLTU, ALU_BPLUS4); end package mips_defs; package body mips_defs is end package body;

isc

aa8023f06d541d6a8209ed69329f0d49

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_generic_cstr.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block EIETZ7UK7lfplDojE4n5WPNAryn8z5Wc+1BTkcg69ivZMCRGBEfqKjKHJvs30LurLDIebMZGGHcU tEjXTQIrgw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bliHcf+gORUPPdEOE6rjelOdtaoTDhkNBJUOhkpslrhO6f6fDW1wZaGnqTS0dbTm/QdTTbbE5bRZ Bh003AVXLhtg1Wx0P0E38fmm4P53hLTvBhsXMnqRhLWlqadGEo+Q6ndqz8kqtCsLYBxFN+eu7pH0 XyqyfpvTp809sOH7/fo= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block D+VuRj9jaC8AiPi8Sd3qOIoBoxKORaT/umCd8xcQOycWfsefjCwX5SQ8i5fZsX7DgbP3xdolpmVS VL4DZcI9u3CiI2zdMklVsa5DJCFZ7qEp4BzinYK27TFKWhO3Ed/Mw6mLx0ow9Pat5PUsSvHPcuc2 0++ZeMNNGt4Z4LxtOOrZxi8Ay3Tr4Or4H7KKXUgXbJ+DHGxFK9khj7f8gqevodil7OXSE8xKreRh XooweCViPOysSBFiprn6H2dGOkRr7Qnf2tjbfc7+oSsyDIyE0/XIsshTyEYLDUdNn92IyH6fZjoI kmMp+LQPKsoVzpL2FPZU9j9Bb/9fbIUFzHUHPg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block TO0GJA6Kj0jscSfgpS0eKy0wVhSYrOg2z8wAbCKOH2UXjmBtYOiqhC5Q11FVWEzGrk51O3tKndHm fz1egOTPQEdtz++uURrMdc5m3K84dbif7qqEr8v4htZP4/SzFOP5LQwcz4GURvHDKgoDJ0oxSYhI DOsMiv6o+6JUcp6rxdU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block F3nCjmvjKXhHEv1EgYNA28jt1eEpJAP7AVVkTb9WWB7z8f4/W/SF0tyvejkOWZ8eLD7jOqzqp5ay ZocThw3RZuF9PCAnUmwjFI21TC2bVbXrHDGpV21k42IGkY/lo9nKXkKMycFQ6kW8rc6zkJJugJ6U 8afgCfujFv8gA2HTilb/pcSDLTBbtqdDLFtB0TDYyLKZ7VCn/kFoE8iKENZGA5LDL1PfSsSDFycV 5o4Cp6sw9VFg2z66UY8caZ9v+kirY6+mK0wcEgD9pexDObZIJrQMhFbzmFIlYqUeRRJEbGJcwZyo 1ZUuD8/TyG3bAbtWpB+5E/sdTGmNaBTpq4pBQA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 99168) `protect data_block E0z4uQiW6OKQNQ+nz/PRqkfhDZnqUjQISVeh3D4Yu4seQNwnncEL7pskkdXIVZR+abtQ58h2NbCu aQc2GiaoDkzpubZ2vMHfrA1ByzDrfipGUDE/MLzDpTJ9M/0O2NAyksHXTceTCsebzCBclqaVk0XC 9UkprjhKJeWjoMWBw5scDjRC8Y8iqMZ51LEPBjzGJol1u/kGGycHh7/mkeyWXUVPOpSphDk9MzVv PMuE5QlAU6q6f1kuyfKpfEJiOXescJr7QT1V2ZCg9GYebY/kO3Hzz7OcPFsBWHrPTMXHKmUHEYTT JFOOpkEJL+cgI97sooAg3cqIqasUytLXBMZDxuBQC3eciD4aI3NQuy1IU0HNbHfDYz5r7bDxDg/1 Cekt8vIMFFX5RFfsvtPx/nOJaQioWrQqOet0a7CY4WGD7yUvbHfzCu77sDKWadBlF0YjN5px6j9O YtgqhJ76SEw5zF+hBm9am9yI7LurrJbhliU/yE2TxTyD53pWkH/EmlX/Oyf2ssuYIfecF9MGO3Py nqIZ7kL9wAGmB0EZU0FMfHHoLmMbyodx5jN1sKewBEofKNIsht0tlOuqbwypPxFIIJ/x9Q4hANtI wy7YMEJwlWZxZhRlPamdPPJ4H+F8DVqCy+YIrW9Tv99mKBbfr6k30Dpm38SGdcP+0xy++ZIrhNHL /LjoLglnvFv9vADxvQqb23IdhGvT8BfSJs3V1++SxuC2gXulOsB+6/LTHSre7xjLdzcy7zXD4oXM 7p9L1eWf8YtGerfaPGAhk1emRIphPvjmGuX8fufElVSXjrUpiQUExRcunyD+XkOAQzZJF+a+Fs9B WVXtsPtcpFzm3+DjVEVi6LMbwyGla2IwaGlbiDU/5anIYiY5avRA+XQfvKDsn+TvXYGup3YX0R47 butSHS9KQ1uLSV7EG5iW8shHvAz/QEB29TfL4hUMtB2xUOiZn9/pYSOQ4EWqdcKBayGa28DpmxgU j5axK0WCLwJT8djD/BsfDpTd4moMkbDjmPVetWdgP5xniHgDaVM0b3IYsh/Gm68XUVrbYfCKZRdG XRRWKvySo5PLYvFeayvNPsKoa/XhE6M7egQTUNEypE68fF+C8eAUjr8rFrAyUERz1XnI1QDbI1e7 7VEg6grJ6XKNlJSx6Mdv819yraIZEr5HmtgBQKVATXBryKtB1P6IOWmGjuswBQ8qXlzdnXfdTCw+ Ill1pjpZ+Hx0t8CwlNSUzwWWGk80lovjW8U7lhK6bzySVcxDetPzqMLRVtGGdE/78TDVGAPVxwKN MKUIFylXkLtLeSyo6gIT+MA1IhHmtGbQ8ieG09NwbS2p3rJAt8hTQkcDjVFDf17cep/LCqiR+otP DiNjlGNPogU+J6T8yuWgTJ1D1l7q1KVsOrW94M8jqEcN34q+xrttVDfoZ2yUmUrsY/QzXKtN5JFQ 9+xYMTh5vj9pn+jk+Pfwe+O4Yn1qDw1n7e/DFBaDQamHJn2B5CeG0XlYCL4gpCOMqHRnIrmswPvT k42kt9ohj+1ch6ai/90Nk2zjPR+0oDeQRXSsb7pj6X5yimHuLqfXNpW3HsQevTLjsULqi2eIlFME mKOVCZZHUWU9Zb+IPLMV0zKjlBKMuC1+rjInHhtpd22ULiYUD3QtJVkAUIC5PdGhcd2nVNKQhC4j +l4KcJFtDBQ9Sgcprwu0h2njuMMjv1siKKSEXfdpRohIDnK1mRTJ7BKIIG+9NHqTDRFi3T8wuvgb lFvlMoTn7FPMA7muWWBOgNdjS6hDhHaBXnLr1qAT5WKSE6/ad8ZZWNsUSpeXCKxjgjFuAMIWITlJ UMaju8w9n+GWXLRZhd1063UVPV4QaXWBe7hGclXgPdifMfJipL/JPWdaV3Akb1NK3aSX7/+aNyYU /R+4syqzlTAllyIjj5gKF3mJKk3n99/NSIiNnPAwe2eLdPjucEXl8rpGeLDw901cxrGDYuXY+mSo uoK75gNfI2mPTHTnJ2UXZwgGYQzEfuYRben4GzNtm/jSWZpAd6ZQ5iMri+KYdzRznhQCNLmY+bm0 lXHjWntZvJonpu0pB9zXCPd+QEF2V/lpUonFSW3lDunAQu5gCL18atCuNaXypGU3bWIyiJ+Za0EH YYkjWdwtlSCAlQyabHFCsDmxShmBb/T08/NGVOZuSLo3wSAw7oEgDwkFxt1tQ5FcUKLGC1smQdeP slKT0AcnbgSfEG2drdLCr4VbpFydJpKU65y/92y2HNUIP9rkkSXYYKeXlDEJT0tmDaOdmKf4ge1+ RKKEMbdfykJK9RSKOTh+9v1758qSz9UEw24i6PZT+nJ/p9O5nPsyEF1Qye7hJY34oQ8lA5lwrb3V wfU5NnCklmPYb3ZkZOKAGftY+q2DZO26iCqAcqCix9aA+M9E/NY4tChc93a3hLzEHxaZB46FPmeX JSwT4vKMUDXfq1rCJU1DW8EqKGqcBbcSk5RrJnfNm9eh0wHgOLpXd8s3vXAgNQpeAkGlonexgspH LL07PDWhjGkWwLAjzfDAp9k77cNhsfJFOOI1xR71OAN7lYsJ7B1/mVGdTporRsHcpVR+FC/ZgSBM mr00Sh80S/+bbnHezSLn3MQBApL6xXbndbv+wo3shUQZ7y4mbAr77bOIYNp2bxSj7dh1ygE/x0g4 5hP5GcaYqLUEihkq1YSaIHxyPec7p79Fx2G54I1IzWc5RVXi13b41/WOIvNSREI5JjohK8NSRjF5 nFzgItEDm2ENTVdxcR1pdECZXCaI2C204Y9Mmi9X1rx+daBiIq5U14lFR+GxTiUXdqiRMGQY+BEQ SKC2yW8Fj5BaEzV+AELOcvEFUUMR8gH5x/86hKTFMxYuOhghSyYWbViyz+ik8e2f0Fp33mLZiiWt sQm+DP8RHMX/4zVbeiI5Or3TPOMCE2Muv3kejXkpldt7pzmHOSNR4JexnOoR7aXN9fLg35OlKVA6 ntAbnntBCATbMIPJAFGliPK8cKavT9AU7SLN6I25guD6jmQxHprC2ps/BOZEW64erHFp8l91/Qds mah46cE0pM9D0HmEbIIzTLG0WrhcPuDhwjnTyv8n4rW4+0d9WXITnnclG0ZpiXPx/TF+63PwK632 DJHRKvtlP1nc5wQFCtD9nVz+uTWcGbbCyF5kpKcXgniQOTJFPtCVWrPHm217TnS5ekq0p4iQUdL1 fo1idNs2LBZ6WTTmJvnJPpdj+Ne+c1tCMyiUI8oAUUJSHQwB3aNM6NNuYNEo5PWAiw53c5+3V+9W gft/AEMWpS+zORXCixLLGjI46dUuiQl1qrKfqBKzp6gzeWZ89cGgaLHd1RLl8JijyBfZqa+Bwtd6 e35UopdeLfILolLTeWFKtX0VMBrXGu4nta5BjWGW+j3sKEn+lwDW7dmg5dRSJW5xCVeC7+iiJKtS CdMiySnNKYZzGKBTGTeiNMZBm7HRwH2aPuLHF3KAfQriVSbndqYn3Sdm5HwCLFvYh0QUGH/Lqydz 36Vec5fhciwNTYP/noCHjBXaCX0to4FEIjeNPqqAnYJj333ApLLeaMpmZ3daAg+LlT/RW+PWK63I kFrVQ9wbjzSxyPXbuOp++N7c5LkcOEgGjTJiTR78SjQkgcXjZUxCta/3KI+DBtUXrijueeFpPAc/ 9K9pUOMDD22SPK1t0f/tiSULp8+yQ6htdTXIO3q/n0DMXBBRql5SCEMs9aPR63JNDSm/H3aqJB2Y GmVfW0xYtE8/0XvHmBW/TAv+t5/mmP3759TPrqr0iuSB0/oGFSR3Hm2HByuTMSmhpZ9eXi/lyHiT vjc0krJZVSRXjk7fB9d4Dg8JOVGz6/8pevUTHT98Fn2gu8zd5tEzb5xX6nMQ3u/p/g95K17ieTsd dEVoVaZFOSi9NpvQhyg6RXDdfxqRe6JTjwpI1oQhF79cSOVKJwyGuyIqRu284hQxf4w84L5JUTC2 4mXNIc+bLMpwL3QQRxAIYFpmJ1cUzJupUfWPDyCvFuvQT++Q6+pXIgnqi64dgo4eJk2L37biLyJp 8QGbEnIo70aEhZ7D9JUGPuK6SJMOto51PF3gDap55/Y50lvP673ULER4bww0Fq5xPJhTUcRm6cEH m4pXnrtWeKn1Nokc2jw6BZd/8jUrVBGq7sIxlnT6HNLVhKipD/NlGkm5v5VNBcQfsGiLLMsaHJxR UPyGfGACiukp72+a+090zEU3wXiAP9bpaOAxD2qQ0oxYu/zdfjOwWTTCxW/oI629ub0/C39cuL4I m10EIK+BeEe1IX0kDFTA7CrS7ZcSPdM3eDlGn0RaWt8+MAnBV2rc/i+HMctBLFuhHpkihnZoBAZy QwJ8CZH6nmfCuyZm4Yrjz5UFauKOYiUoR2iB4xbYYAZj79A+Dtdt3W8EuIfanhXmPY1KBfcnzoB+ hPJQKMYLGiPLr4Gnlgl3pDT0IaWAHY5hxBiSMVsAej7jHGL9gD/VpCcuE37mIin+8egtx/LPmqv1 0k4ac4cq3pQK0RtHNhIk3m2Mna4i9K48Q9W+778kP6FO6tGvQkORUBK0i+sDx0SVbxJ69irwXrE4 LbVKDCXXObPDvW4bPW74xnjz7fDNVihFLu8cVY9DQTI/hjcvy8Vza50Mn7vFDM0/RMkxkNn1+sO/ hRoQuUHZqK5NMLP6naOiNYw+5AwiIKC/fOm5BqHrHgpqW//Fh+6Hb2267ubC0AdMR4eZUoF+pxNH ZIVMB2ONp8zzpn6F3ZsPG6Ou5oqEVkwEekQvkkkN5Yu99TM5hYqoazkDtI4D0Ks5FeSydbimBWo8 u1OKBez1/MGQ1knXhgypwMsbS5OoN/ig8Y4//CgXQKiys9Tvx4+6ofPZrJpqlxwYEtXA6KUkhLuv QTWc1YVr9Ek2f+RawqhHjMmYemmMYNTwojzLWLu+bwfiQhzreucpYnVOfDkEOMI/rruQ5eKgn+6a Xu3Nj8EpohMPvg+nyL5E0TIsxTcAWbVFxIRLWH0P3AO1gupJxbU/QJkLfe2ac/K0iHgg88ZvuxNG rJp2aYz+ERwV3DjToU9ZF/YRFbiMNkIUre2lRT0szE3QPCYKss0M2YXCTt+0JxtoxYhjAfdEPguQ nHU5vpfm4Iux4Xasc+nOZI5WJQ5XelLU1kFu4Aw8fvx9srKw6U/wHMPJ5CpAhAWElLDbOPg84OVn Sd8k/xmoYONhY8ItBKv/z7zTicvBLwrXLQ92SIQoGytzCBkgUJgvJR5Q35z85bpyhPK4WgbHv4+b Mhh7/9oku85qFpvcAjk92O4PEB8EE2KXiToahkyKgZfRLqLEk6mSBzSumQh9SM1q660/TIdz3X7J kQQjPJ+u1QX7TgdP31zO/3jE8C9rGVtNm9VuzhSIQRyUO5y7H6BiVFdeudLinf6MYyHsTsNE7poZ yBcl8V4FeI4SyifDUoYuLpLKHpWLVPME0Q9JdVu3cAz1LWJVt6aj2oxtCZalCAdd/imxcyZh/ZPJ WJXpe1DPn3ol6vfE7ZZpCk19VD886KF76Z4ICbRK6iqKyI7Mw+WCL0DpI6meRBWqgQtHBcT3KQ6V sIz70jSPibEldxISiSCXJ/8RQTh+dArG7HgJOfuWnZdo9Jg57yYIo2REvWWBB2QI3EoGzXSoT2W8 YnbOl0dqYSKlKRhCOBgFmH+SyUX2P1ZhrfWlKLSVG9QInDakK4NbmeAPSLbIbuHlxs1aRn/ev4+N hYtw7co/QVYSj4RexBRGjmp8zDcueaWVDzVxmX+NxU7jzUImSrkywYczTtOISXFfdAaBA3VKC7Lz fz+35ZsZ3RMl2hhCw4bQdn1jVS6Fvud4T07NT+z8DQVTzbo/LEY351kngibdbFOTl03TvyiExoTF HpeZRPSr0XKkhel9Xz0uOF4LH0ZRo0K1l3q4eSIPEM3oWBgsAvUAncbf/WezXtpEf8JZXJdRaL2v 2vEcryfSddkd+jhM1iQZVHA6Wnr88ClUOdLZ1UtUGXiyOsLvl/CJUZ5OSwhHSOIfH9k961vEpDtD 73qNymaM69Dydsh8lF9aQ86RN6vHTYEoCWUaY89Q42JzOZe8XUWCXYIwbAPZF25LEn8nkMXJ/Uh5 CCYMn1/+3JnLhbxR6FB8ZdFnw4KoD67bIDx7sE3Hvv8Cq9EUvL4LREokbqBZKHXTXOdkFdBZfpfA P2gIjgaZsPXDJJ9lj/Ca7j+dBbz6ZiHR3fZZS1gIvIxhx1clVw4e3u6rUAM03/SKTsvOAfqM01oK fJNSxRofcsivfrtC2oPYlW1ZGsbR1Mqdrw5xHZ1uLsYBw7EI5ibE8Qb+PTyH6anHBvIRcU98pKaU HsW/qykWfwHhOcbKCpYsqzmJcoJ7IwGb2sJNI1lAzYsCv7nvBatymi2IGxdkrFLhDaVrdgu2d64G GFLbw2mjOMFp37Csb1UY/qr+rRbyAho1aeXCqfhGVYUfDxv6EvB+jBr7qQgSxciA/KW4n+KDF0E8 xDvhgh7Qh29vqL3fh+AvvAL/bYpcXqTjo7lRpFrHFsun9PLZsqXChe6IwPGui3wFyOw6Hv+lQGzn clOF0qE7n4nFXcvsQlLUuCJoEoPlg+2cfXNCKgMoY5q0BnZZ/oaOSSdDPzIdiwx1k+5DF7choL1q EFN4wPBruF1r4GE6HAqDQbkrjCQ4PtpVyBSOsUoh2jNvX/XLLtkX1P+LPF66EjxBNEB04BOisZAZ M7P1SzpKq2gqF89spdDGOf8ET3d7gUgUUVMtFXP4wQJLBrOTwep7Zk8qAismS5Q4Ta65fJfj01u9 FaLd0q/lN6f2AYEkB9nCxAN1/2QmMQasahpRR7ydb1a1vs+uoWB8Bbqp9OBF7/aXoWN5Vx4KjYE7 prTNWF2WWKI2GdY8QIoyKdKgsqC4Zd7Rft0Fb/pgmUShC8EedLEzxqerD0CR0MyMedgv14x9F1w0 z7cHHCjjCUFMnvXRG/MY8KTQc3T/Oki9G3w/e8l27sw4LX41OPAcQ3865oclOvOW+M3vf0FoHjpY 60SqfzC+SY/9+eydQoGCh8fjX8aCH0t9Q7Bl86g9InYkyRxcOBuFXVBDNMxE/WWSC6NxPa4B890I iIQv4x+bQO68pKTLTwuboo4AM8ndok89wtirriTSdMbqmNB5yyXA/sTlJ/+xwQSC2JmQqHrHWvWc lyoRxjruJVRdlM0K0HIKo0IsOZA2hcQMFHSdUuqPmV4geyWmU6Rj05cQu0moF2O/BZPoBSM6kiu9 wDZv0ZcyjfDsaPv6xglqsS/Aa4ExGCJ5WIs4ZH8/ytjxHDdTpT4AzJ6Toc8LgOXxqL4x5QPB3Ndr EGMW9xrJLpoWVe4tUf7rRNpGe5EanqE48n46f3upbotKy3QPJd+lVIlLH6i2KmbMbBn79G72jD80 l1WDlXGVdDZtEA0oSskxIgx+BNs5ii1ViQACm05jfBaBtieUITAIh5VJrOA1yXVwt2ZbrL4Lo6oS 3RPm3horK/8n5gRplEyG7kleHYC9i9BjxJJcItdmMPnI2lc2i2SLJ3njXPK+5yvlE+J1ocM9a1vP GhLP6TFSQAKagiEOfmPKiIVzmCycahDRmKZVLJf8D8Ob5ozDOoI735fhFBZuLjofOABfNL2x7cg3 VoWflPmQyBtQ7n/bXsZf3b2rfDjC5/RNFD8XsNxAmT9uT6MkXuJHa5ox5fDglKH2ppXwd4fvnXfp Qn5acZjhEBG85bY37hiO+GRpSKSsPIt87bP+2C4/6DYtqNOPDq8RMzVrR6ZTFgejfsjuk5sCcPh+ fxTsz1+HOwm+8u2hqexnFPZtULzuzN4wuJWHomiotxNEZeS6Te75r1eQoCZyFiWRaGvqzAOmob0J VYYMMpT8aepyYmexyt+/AQJgc8pG3H27cK6QcOkIUyUQsK9muFtLAe6IclWr5nWZlXsTARMx/b9L pX52JVv2QJWnLk7DLQU6AzuxJdK9dy7GdIGw7qaZbsiiZDyoWNTo2+f3GJPKLDkMGmwnu1udZRUA dFIvu7IB2XJDeeTu9UgxmrvaxdbM6Q7bli3BGiMZRv21aj/2mZSqGHPAmcrTdhirh4VApoDR9wev gC0LIZY2YoSmb9FKOkA2BKfUYKj5AWtxKUAkuaEH8n87EbSAOWpXa+3uVpmRIeYYmZSngDuY9y8b HKF9nFG8yaEaEE748YxdPgummbrMspPc/FdpDYKDhNDV+geXyUQbcdSPCyrnzw98PxnpvX75YG/z cbgeYJWGu2xuKUYECE+sO0jereRXj02HBB0oRl3IqULvIvuSBd2f3NTpCYLDbaUOy0jXXNddzXKO kCwnbhuL8B/dJcy6OAgXdTVVdcsNAcoBQonzAoosK49nNeGNV6t+nVgZq807m50i3YQRpeJWJyeJ oy6QJriXHJ56uhPshULJN74FHW0VrrUTeRrHKzEVfzwPNK+JKpGag9AhfZkm2gi45ptxO0gMhhw2 qqglG8ble01W8nm597DGUCra8nOoN/fjVsqyboL4cndX3EBmDtqlprN9nYcCtpWQeSODGMb460PB kKx4g8UMuZASeuirQr3JYG0uaUzoW7X8pCCnhbeaLpTNiPZBQy2NGqG1oSVbJZwra+Lxu0CE1xtW 8w+soe1Nv7eN+2/qAnRLEPWhvCWdPwMyqcKvQ9Fim1yK27jQdICtQAory7LkH3t5sywKuKar75DH 18XaF7dpmJ63bxg2iSfH+xNdtOmLnOAUK6QWQsuwsDJpRsgBupbaqB5beZgDvMrw1EQtCLss3BT3 mVITRRRZDW9Kr+8QkAgPyX46QMTMXF530BBG8pk0jjuBFY0Mjzggz5rjaZ48IlO0Q9IbQySNnGDP lI88Wp58NMh9GzUqTUso4ROrD3Vq5q3cBRNwV22MvcfiKflwP5isAHh197PCxK8zTcaUAgdbWNJF Af50Xn0O7mF2ve+CA8tFpQflwGgQa5BjgX7J/hKvtptc/gsZCPoWdkWfvrE1nj9D2ay36aRsuRdx LRiJDoSYBDghJF3PB4GdlHL7QieuiEy9ymdQtF0Nx6nExP7C7VwCtjGOyMA2MWj1P7uHdLCrHOW4 5XQ4nFtc3ezthW8XfhWe3EPaK8laEq8+mp+QPPDnVVjrYdWK6oGc33ZtE7BbldVU5TYz4gBPeBT1 CCpY5wrPdIFRx4Rnt5kkI1zbtn/b2PAS5u8oa5MU1NLwvSQh9kauxuR/4ZrWegmujrTwBJ+2Bf1k kBRF2SsLEPY1vuCKphRtdqLGeyTsUHIxkrg4M45uLy3DkOvXybfMDQb5OQkeGfMnVxXpbFpL9AP4 m6Ebc7dTv5YN7DSNVcdzd7JbS+1+5irzOlgiHnznJMtMuom/34V2h4JNHVO7AMOLhvMmIzXiUkcl J4Qrzex42oi0W1ccCFQ/57ncwh6vJJqGU+W2jJr33qHd7caaB3A/9lncRDB+AQUXqr56SJvGJlvg Ifz7yBo/1Y138NXJrxjGdKimdDqKgS5mmQeUHT+0i+lk9RaR7bA+jbd1Rwlqb/A5LIqF3PsoBOKT xxHM++GWPnw9CJzsRL1sevDcfGhkdqfcri/Wd1d3k4c6vOzOO6y9u2z6foHmaEn6Ec6io9g/9pnl lRCfZFfko10ROCRXaBXfIjTZ2l2ylG0DcKi5pdQt1Nge3rac0N7gO7dmdDg5Y3wH5qWC6mEuJOzs lw2Sxz+u0UqarWJgOH8Jhvcim3nJ305mTDEAv+nHnpgzCZy/Ivo4sLWvsAl+dZg0iME/8DdcY3DS rkrDrXNnScQxvxrxqwi+Cm00XQ/9UbTods02Bz0vWV9R/a5PCIiHuc+4xa+kx0rF0j8tioC/F/fy pSB6M5BEQcv2RprAni1XbsuDIj2+MH7bERo0xqdaPAnqPJ5VZJU3bbyXYQp6j3tTiVxPgDYD0vC8 Go9EcnglCEqRfFqDUFzlGEUn64TaACVg/ReZILgcQwkQrLGCaMDioK1kqGh2JPC3MAMEo2JYoJ88 bk0yMyq4LU4iQ1+QBChhcLVuKiiGhraJdA0ThzW5oVXx3xowLaXe5+JaBLN4ZgLHZMRxxeruxL+z VGFUZ5n81RUm0/s8BAPKhJ0BQyVpA9i0SE9820+WnSjgT9Bb/dNq6S0lX/2NA1W95MaMAQs8a9Vy 8E9NV44AKbQLhTjOB4xNs4lvXYcMfYxdZHfMYv9ezUKvba2s0CSy+q3SRE8XQTlo6y9SE9grX/AC 2Xig+jszABu9DdtQ43T4rxlX9YwYEB3baZrlNEljIfxyKnKM7Sxu58rhI6Vj7nPSXU2dOYmLGoho zcsZnN1Yxez+OJjjPx9L0+S1sGtZP7WzgPKXZPl79iAninUP4FLli8wubukFgL0VjsqNm3pEBYfz n4++fpWHV9ovTBNzCv9MKZD4PriBTZeT8Kll8iB8JaR8cOY++dXmz1e9gdPfmp62mrLHgHU/7BNr s7smYZ/521fUYZXm+BoWEASJB1ddkCaM2NnAveYn80krYZsEdB+pm27n0OegiHkSgY/cWXwYnVyH XvCobMQqeRiQmv9iTjqAyQte7GJXdrS9FMsdtQuRvKDdYTw4pUSCTurEFjq4N/+XAdaTklWZGyuc gWF94VOO9wJ0QpqNELNRMytB4HwBF5OY8cZJnzTZR5zbv20moJC3OnAJfvwZXFreOvI3FDzJPENj 0UWWLjImxN0cekge2zbK2p9+Mmudl6PHQGSugpzkoZRgnmxLOCEEU2lL/SGbeVUu/cGipfQl2UaV eZFGrXdOOJxL2MToK+cFRsYpoXibRgzPyArCayJJ4ftiGYcZl2mDGTPRJRWVdxxjtajRIR3Nf9Jg 6+MQX51buFK4F0sVO7XUO5OYhfZNvhF4hL22eE2IqE7SxmJhRYUcFnNCqERbaL4n56LSJd0dZVj6 G3APBmbKjlrFtMLf/Wghh5msgaDMkocdRXnipjWIzHKBYQTc3IZXS3nC7ulBLrPHM4sAmWitGrd/ k9SIQn0UbKK4EjH+TSitD9w+rw2bLz2VF8Tpz1RtWFA4ZAxy7qJpVdof6U9iWB+TKAHKvZ9on3Cu 1K1hMAOYGs0mVMHlRiclIERUGx9aOEcH0HosjxDER+gDmvItu7DrxY0nMMSvwOh8tNUieGXhq03F 8D7Rl68CcuT2sO5aRaH5F6C9aYTZgXO3YUWsAkODjJsq7bSOqTmmFTKfJ8blpgXHYXew8d0Kz6TR AjxEE0TX8BkN9MqJG9wP8dKd66HN4TLKLTZPMrxfd1lPqX+/SHjddzwWqu8jLH+eCogcVflKtCED zsh7wuVuxNyLpglPv2pzgSHXb7vkWRIKagkRnSrH06Gl+PbBh3WJDOsa3HtFI3J5lgu5L13o6GJG FjPjrg8n7qiBAKwUX4eG9B65dGwxsIy9QKvXCQoJpEtwjrYiamF8Pda3iDciVIm+aQW2s3I/9cQK KXzlskRy9vgzRnQzFYbTcLxxIrsPH30xOmShmXLzECAvp19hg3KHuXuFy4mKJ52OXIjdFgrTXQeA CUET0l0/j757fquIhbIkTd3OdbAoqOXUUpcc8k5HTYE+36WTkjKy3KqIQt8g44DwUmvieH55inYt Vdzdj0G5ywzFlojcdZ3UIIhJmyVFOECy+pqfHVW+qmFLkM0Nrine0yWolLYhoHivTIR+QrPP4lYb /LVV1WAl4O0e5uTnLycomFtI4Je7FOmY39men8q5/GEJHr1x+6i+COgzq1KFyMmuksZS2wyaQb2b 3kitz3boVo55NBozmoC9E+lLtMo2MAHqAGEPQRz5oK8qptl+YkQQ0/CuyU5OP60lQRxuCs6jR00f J5cwzYcJLtBDKsOLlwFxueO9AQiPqmCAqQCBJbKK4Ge9FAdwD101kgeWkDr4tNVljkGA0ithQWiF KG9Vvw7f69UEqhIkXT2SVvcEsYGUtV55SCtOXewt2Zb7kjOKZKgoRIc1zjvT8ZBerCX/d9XdT7Mh 0IlJ/e2b0AV+/9v9a7eXmScD/hsG9b6lu04PCP6ezQK1xG6cDHkJifFAQ+d9BX2w6tEoILSqT4lL /+cWijFhFsLYf/wvZByRARKl0N/qI7e+Aof03kjput1FfvdPpsaj3RiYrZvfl6MXvlIHSx7ZcoNu PQ4oRtpt7POAZFeXqS40sp/Q3/d/KMjW7QIIJAs3BxD1EUoq9pUp+74arKV3oE4FzJIsH5xHHN9n Rhs31J/Mktr6TUpws8lyUTTbzqxCjqllUb6YNoCSA6VIVDk5l9yP0J11EwKExB7AKsSA03OZZL0N ttpQchrIwk4IAvR0T6HJsVRb4EXWDSfUykbFQnlhhJWfc8yhaMHxDUBAJLIsJKhOD0/tFMuaNewA nUXCuZ2pGieYoyUnWx/kGW677ElOUOuoyFjoc72+E1Tik0HR70R7n4dEasQm2xRAzXNptEK4pFCI HuCnQGs0ns7fzfruO4bqXy7XZyL7fTInA/ItjmF2ei4K+Iz1PUCkD+NvxWDyqDj3OdQGOK2nq3+f EYLb4BkCbx8QRq74ow1VD0C8f3qlHSAdkLsNBJIpNK9+5diBch6Q1AcsqUQGbwQPTIOOT+RKrFDa jVeWDVRGMevwganxLwKrmam7mQYOcYdxQm0bXi/F+v3uqpsbR64NQ5frTwvCkAHCWtGIiHorhL+f pSYKpJ/gmu+9sFanvt2HHxkq26DCQCseJ0WlfwDanBWMy4lx0G3nnWGLyG4HnBtAss+4acw1I2cE JeZNoi5ELpoZRFzv3mhBpipbMHjcvMo7ckYmVeU+JMenAefIb8Nd+u7NFF/A6HQ7C8NMQKJyRFEI jvQDmR97xIHnJZ3BCESxVVphjrrZSsdFZfj/M5ax/LH+ocSNHF6LF/dQMdpN6BJYulaEIFmcZL7L +ZLLEQ4wQDP/kkroJ+C6O2aPDzOHVa7LKPrpYPmCziXkyioDoUcIvEWDF2oczDcBuiIcGsWniWHt 4WV6Aa2DpEz07Y032DZrbXcAPIr4nhFtG/Gf4QGghYIu8oezqs4pxQKqomYQwO7lHiAMjzkhYFNf 7a4tQL2uy0dJKAUyAMnH5LimZIegX9Bed/1otX1/kUpdli9dhw3h3owJtVZRbCJL3jWqgL1oskLB mMkPdo/jEoR85HQKv+UuWUyIgpjADSOIElnui01mYLtK1QNmSYG/U4Im/qiOcbL4KcIapKdUrtqD 7n9rW/wbu0Ipjp8iOJPDXXAo9VDetTXi/F/xECZ21pY8HBdBvjV3LndW/bdFiEWOM80/5O4pF0Rm 7ta4TwypVexR9mRSHatxEYKuU2+e1tbU+QQzUbUpxGrqttClk4KM9pORQO8hOgOFJNq2Ge7C/r/l 2cc9Gx412ps3v/35ibv+bz23XzwI6rBYYpR7WjyBWNBlDHllRwMPuOaTSv9T/ETLRiGIEQY7wYE8 UgMX7L+Qn3kdcgmFXpVWZaFu1Ud4/k/b4KMx+pbg+V4yaycmypTwdoJmnrSw16PEJtX+dHcF/8uq j1AW70NN14pmdiNUNniVku2oO37t7HuEAo8HwAvqk+fMdmuq/RfOl+I24k3cp6d0xikYVkYbHVdd DqpMmwARwrfWDXw8yX5/pvm3ryG71dxN7iGjmJ2HPZTUqayvCBEZ3a/v5/E8anN0HBYN7G00lJBn GgCV5JzREnZJE4Cz2nE9G0y11XJmqqHyhtDki1Zq2ZIUH2J+YaTMp6PMh6FkdClUJMLdSoxywVjB V1oH4l4RhoJEB7tuaaORQkos1fMAmLLUrh38DJkSyQuwvEy/iEOh4PYNxVZCcob29ZnNsskkzT8V avKsTHDgievz6598UrmrMpM4LNDbrNIQR6zhAuJzuRQBlpdGCGFtwstf/aGe2Yx9MLjovRExSww0 Ez9GutPW/eQAZ9uPbKbMln3EIlXKD2TK/WLpcc1y/2nK3Web5HMnai4k0xvRwZOWRCMQi6w8151K sz8UflbHq8gqE9HyZ1XI7n4kiNLOQ1jc9kXuU0/Su56oFyEWBQLvKF6xbARaSeoP8IrWgg3XjZ4F VgaXFdijROxpPMjMxHgwTJ/lOnq0a1XpZs2iGDij6W5bOdD2iLE1DYAH5ID7pmfBTEKFMkYkYYgD Qz5hMn7lNaygUcpY6XPT2HUzsiGNdM4sCY+EJFiFtBp7cwuZ4ibZ1Dpi96diVhVTYyy3eSTiT5pT WJN7E/ybz0xwugVp2vO01+0DAzOG2c2P5k07xf0xjdFyum+e/ilf7Bl98rP0GPbWRDweMi4m7So7 T+/HclBhFtbCqWh1B2K+bbgDomjE5YZruXXXrWIvgEEdf1wIRdZJMXBWZHQ1X8ECqULcYYPb+ufW ySRhi6R3kAjNZLAI4SOjlSZVjZS8Ng5qlZiG2Nsah0YN9k+bDNZKCBKMCMhkaB+XT40wXM/NMJ4j EGRqRiKq8n1QnZgPkA5jKkEI2yyRbpQ8jL5P8dgaEwfW/YFBYePmE2el8iWkLLro9fg+OFAwSpc/ Z9hN+eOxRJSARXxFkDljpnDvU4hNG122y19ufnU/vXPa9VKqsFtcLLmBfAw3xqUlAdeq+ZdVnQp1 o2H5O4iAaU2ZBy8BrTL6GfDPOz8YZE7dfzMOH3nt4UzETH8oQzXwTuOqFjTkzpbMi25zH64mkZUY YV21D69FL5PrBLwIYuDG9WSoGkfQt/UU/tjgAbziO9W6MSimwGHt+/6YfYpO7bxepEURHrAb1xi5 dUx7fGaex5PBQQ0vb4dMCwes33Y+LjeFvQEpotup6dJ6OHZt0zBUasvVgSvlK6dtbPW99GGPQE+9 NIw/yXJyXclI19mqWrDLtfodmUlLuH6Vws4p8XFpWAqTxfO8BfBxfjt6WcXb5aITKQbymmOHTskb 4dx+nvwty9v3/uNfu3grHcxavDbElXL3G+t3I2MoFz8/d5Rrb9OHFdcS8IH9rzoE6l5DqIzx59W+ 4ZQilKiwhE0KhR2gIcJtuNC9pzK1IK87Jqz3ESrZD/lDljkUh/4pPBL1o2kgmQ+m8oTqV2C6SVY/ +FMqFqDMaktGlXMSRQrGMuXrftBYPJDgMjnntKuWcr87KoCVzNVciM6EnX1RICjRKNIvDkWT+pb3 euMyhF7NwTDu5KbbnzYxdQysIfLOU2g5bM8dphg3suHdwxPQcwHXImKWaB3hWlgiRlvfW3VpbHDm arbrtkDZb4yy9RPxHKmuY5i6yHvPf46QGCqLCpf8wpIFUYqKunhuM5pbZzlUfEsAifTlyN0YooDL 876NiDouwy+b8uJkTDTlH3PQruzFmY4mszdiP6r1+4cU7oF6povlZXOZTwvN6jaXqa+iPEpnkxwr CZ3xY23ExyBWO+wPob64H4ws7Hk4aUt6CP08oTNaRF9dapYb9EgCLaQlUlMvs7bRH8HBwJ+EDK7b n9rgYYuFbtvShCCIsrBusE44v6jZGiE4sbcddK6TZhkK6ZEGbFfnWMwAjRRXYlTRNVbdXBscn3DF xUdql0XY7/t+zpKGv4kdLIXZtzKsxFrivNOjbnYxnGXzhfbKdPPhV/8gorXwlS2neXtXuCW1LlOk Hjl4GKqg1qhgCRALwvq2rneLr2SKXpOpDTAZUM/sxD6xLU279kHFjJ0j4FT3g3nnnqQxUJBehsAQ 7xs2kYtUCHdy9GN5Pv97bi64zSgunhO4ZvfIsVH5gapiu4cav1aEPdcO9+hxoyOxzB2FmtzColhI wiW/+r8bzgQH7cTW3xQ4fA8dFL5aoahyvhkw8yfGXa2Kyzse+KRvFPinrOAIZxNLrKRV9FhD8v/e lkNFeP2ctP+O6AI4NWS6UYhmKTO1CyMDtiFBit4XRtTZczH/l/EkrxizATlUowqbJNsz2FwY0UJq 9ol6CNKDJB0uLGkipeAm3vnyQGtXXxIGhP66/QxpFsolYrDK1ZK1QrBE5H74p/TTRb2te3EFfZ/G ssD83v+yC+Uo9TfnLyz3/vHgRqnS1FHgy9oGcwyuJiXGznosy3t1bfbLw9NmonizYW/VMIYT9XfI HboXbcCAdDPugJhGChLYgo4gbQ2y2P8gFHGcgYmdoHuQfSSkiOWNWq4UA/ukJipy+8ptXlMGloZg wyOTkHyxZ4oSMpjqJaYB6xcRtWAs7ZSeXb8c27wE1ZOjCDTgrVR8rlC5xYO+L0fRQMGrJ2j+CBd1 nS9mH/rrTMBya2SzOTUAA9yv+L41Z9h+jA3oAvRC6D3WmbJJPzycsw5LQtK6NE+sRTJ0MQftJkH5 uY9clvvm+edOVxmG8rCA60IZbEdiYCay0LuX7pO2yoTibQeM/Vy0ZvOEUU/DzIbVwXcQmQJ0q44B SRa8ynSMYN2bNP3nZGSXL39pItvjkrzdkVDzJsIvoJX51PKHDyYgwzGkK8N8jVG2TuH9IP9WBlof MUU3Yj2kjDL9QXu2MUANfmvh6vM8kNZkwEQ0dboAP/kPRpq8imXFjlS6l7dtF9DZVuD1wGmfVgLx GGq6hBVRzCFywHZ6B3qRgDHiCjpRy49ePPXzfQtVY156HQH1nJ/U4TR7gd5v/Y8oLXYYunsTdCL3 ir7nsr2HMZ+3OSK1zOjrDNIET7uljfeGsXbNZHWXttHUOkbVCiCsykP825auKQZiNEUZSyv8OATv 0HHCpVLwHr//kAWidf4YsUPD+dSOLX2UZ15bguSPLE0knPJDLiQyEQE85EAZLk8IaSgyIqH0sxeJ Ro8r0/ySiPGNxNNJe282OuSiH/2t93gKkJJcWRbhT/X5c91gMh54HSeGEFbuqjwrHNdUIhXOkPP3 RC2SVt8yb8sMDaPDL9COmeblUZvIQf0v6wWg7xsBLzVngjM2aoFCu1owS0UxwXC5+EePuKT02qgw 20enGv4GA7yN/m6VXpWPJPU0IzFJis3QHZt/AZKmr38z1ZFFwpRvhQF784RAl/NgalOxPPVvf0gz U1GklXabphJ/yYi7h0r/ASBYA0AG9LWy+p9SmjB/JIzp46RIed8R5GL3+pajkAd0IYknJ/vtloMM 0qDxzMcgA/Hlgcg9CzekacncdyCnEJm0nr5N+hR4+HnsZnzInZNKnesrt7mdm6x68zvL5f/vbtdk 58lX1egi5MQPh56g86LX+A/P2DRu4t9VioXTANPc5Mc2K+YrcK1j3V62yRSG4tinrMTT4Wc+hJNT ID5q2KC6eM+gqyqUodcQs50kbMwurQyD6ocDcXmYVJw2OMz3M5v+OqmbbCiIq01B3yxDU09AFZ1+ vFqruMg6rAe/JuwhcFm7Yh3NGyGFiZ2B4yiuHCC+nU36UKy3VIBSoB+nY2OyrASfIKSILM553PNx e6rd0QIle8vT3U74PSKMm1w8xRe13fqRJM1K6O3WxMElu0ymNhPM+iAThQ9+l1DF+Y9ZtpsyVUrU B/wa+n8XXL2XQ7K+hfrcJBs03995fAM5FHRfYbZMbG306lkaPXovcWLQA2NOEX0d/890eOCnA6dP KnEduQfPj+sUB4mpxoYPUSlM6B6soMiRGJD7FTMFVIyvu5X1VttNNpH64bwXqn03JxCQYl0IK1OD D3p14ec3OTH7XCQJHvkgFr8rkks2Oqtyej4nNNgBt8tQeR5rgJRDlmmIAvpFqeFqvycmeL0OuEGw Xnprjkq4xSgWTs67LMp0RiY5SqnbFB+rPVk2kNultCodPakqOgM7H5hs+gifJyDTshj3STQQKdzv ieaVpYNLO+RGYtvFU5bnbgXvhnyl8ciAUrk2nBEbMsz5GRdaA7NV/FqHYppZkqQwergLS7dUF3bz DNcoQGJmwWNEeufWXZ1MNLgWeg7yWcqUMXYjyjqQXTFB72e+3lspfSp7HIm4uSSJPGgNDsMoW48/ PB+OZInOLATcFVEYo9Cq3b58m4E5qHj/Uy8MgNAyLZAYER1MA2e/fSs2Cz+aJwCOVJC7PZVLyrhC TNS9IAmBRx2besBLZRJqkNbriXkNWLZgzzUWOWxjzTTA7FpFY+9Tm9wH/OhacyfX0Ff44H40GLvM jDu0+pywaAGW1ckYrA+NYJI8S082YIg/SI3yJWR9GLGfh9ElBg/C1t49iSAUQWIy9zuqvhoO63c0 GyF0Hxlr6Yec+3ZDP7Np+pFi1NN+oAC4GnFlTiVQ/T1b2SdQlVFGQh9k6aezcHxygbAQLHrPNrQV P9P8JXvASTG7MVp5kckgxCNwQEsoZ1DESMrPjyi530ZiGhatMCKnWfHUcF1hpTL0Qdk0DtNsjJ/1 IELtFoMe9HyHeYhbJ2H5pu69U4Tzk4rjc8qaFxcNxklM7jXtzY9FH7FHzrzEcZmw5ABOpRqgGBBH 3g14ZWmfUZX92FW5yNtKBHOX0vtCIK9yza03StJnb9E9cIh6DqXWs2ItMncyp6T4gxewva+Z6rMj 2uHlSRHlBa5UqIbThnRbf+XD1vl3lI3rLBps6pw/OuRXRCivAd0Ojqw500+IEdc9Z1pjq9e4V0+G e4EPXwsNAuO5Q5rO1wiR03HiGNQsBqbvv7zx3OJR3XqqveNT058ofZKqJtNCVfTseROFscr0bEMG kZ4uxEPJls2YNDwlT5D4INVVEGhu2IykHDxjjXGCWZf/P/9t+BkGLoxNoWs01vRRHRYFsZr0C3SI b/dT3SsZTnumSypLJeiXTRZnlxntMa2ZYfclQ0QhKjc5iPMJeLvIuTAz59tOvwCa+kw3j5UsP78s wPtoY6rLIml//DFtXmf3dd8YMbo8xIOTV/SEEJhnroQcmnxvff0yxuZ7wM4FLl60MFCm5Ccd/9YU 1SnNH5qAbbkTm8DSCwd3s3qwFL/kZKrE+7qAInE9EcWQ4i/i5L+/L/PX8qs9ziGuepcScfnzMIwy 5UJhchqG4vnltivR1xhO9B0gNsOw6yd9pVmeH0rBbjZrDsvi0Olz51neqpvXj7xZlcsXHtV9dYv5 jQz5FltsYXylF2uZhAL9tvlcccmmmjr0Zp8712ayNy2R1FrU3fjQrBMCw2G/DjZLgZDqiWTHakxu /TL4bE2JMUPMqJHTprPFIZM/sihiz9bA+i45F9J3wdms7Lk5mmvnpw/rm0BoHVZGdK54Wf+yhMO4 dvpUsm6nhFNbmjykanETrUZiHd9uSzPFqANTElpLUHjAsElFhIjrYUWQ09WgbMM0CX8K1JLOWAbl KRFZ1lMiZIuv17V80O1BY4RTEavw0e99kjN4wNRZ9Kw+rXUGOW8OhiBW9T1ouVrJtkHD25wv96wE cS2PX0JaZUtotNyK4/f8cLLDHwCN1YvXygPyCg1gBlvRUy1RoRYpIlikZI8IwrN7HfLzSvuyMveI MpqC9uKu4vtvEUDFgq0rcsZM5cyMAfGW7KifjvlzJgCr0Xa2d6Rxgw//4rXP3/ZlAibm6RYMFDAs Q0IqQFmo3SlnLSSlyRjU8gbnDpicebzEnEzh/wJEljAxCt5lGktdEzurQkYMDF56zwmBM+PN2X1K LB1NzNe/4ZZrB+K4H2f+cj9BWPeW6TI6uMIYGwkuLT6el9rVZMuMqYMGqS7QLLcOpqvmcWy+mxvS gQhlEzgc2aZeGYB8cHvLIbnNcKwjPhS7a4ma3gNQZgFrt39OLo7wAcPn1ICrmEFon3KnAcg+RaOa AJDbeSLwlMD9w+bomNa/sxYVQ8h0+y8cIji935TIzNa5dokCmew5qwanYJ0crFPPhYHjcyqBWajB yQB2WATYjxrXzZY5yjGbhNTMQeZX0ztlZk72PEeEFJLlmkPcl5Ca2Eb6N90/TNyOdtFLcBItJkkc YRE8uDP4KoYK0eCpvmOFYfl05736vMgL/JPrNwTRJtEEaTEQuISFdy4+0jJf393nY7oCg4iD3j09 bPOS2CWDLGpU/Ihuu9JbDV8hfOjv67BnrZcYzjSllQ3NVkbO00LA39p/rII656l3AP1xxIXo6+zF QKVUOlk3YL6NDmCi7CIWbJvSRvb4ZKipCARZMA5q/vqt08+YOh67O09V9bjkCVcabNIzRHa+baFk Fi7piZa3S9LCvL/K6cHoml6tik0g+AXnwYKM/ia8usmL+JvF2LagtaIqVdczrSPYegcs/Kp6Rlnc r3MSFhZPAdKmXuMGe4sLK4/hVSFenYvwSZ3NHy4FsbR+PqVbDzt3fLTJxfAdb5DhsU3X8Gc9DuY8 OReDoWbKpN94InVvd8Cf2LFjnGrror2DDmJdqepMDj7VuAupJldr2hZHUuT8PFAEG6uBEkE/T6kh gcOE1lGQhJVLexxXxWA5fHpsd/URAr9v7zmhRMYYMkLasgHZqGzXJYeE7NtEmS0tPOlREsyI62Yz 9a5zUatA+CUEFQ/X4P1GkkHYGS60QcG5gDfTogFvbO0i8t7NuUHI1pt6sFwUJaaKyM1Oh0e+WeJ4 LO7VIXaepz9SP0Elp+eitsJZZQ6xNskQSuOy7B5UJSNgTf2IIYUTfiyqxU1dMqF6l27yVFjXXe0B ulFbRCH3XdN+J6/ZgoZhmyfUn6jOzX67SQ2FhxHwD7ADr32clzm+DM/7kJNFqVNjjLXswMTK+aLg OasvgKZkbQDj0lBukHEoWCztHFc8SOj/hoAKxR2Qf5iT8PUJWRJWdg7l2gDKAudosDqSBLoDtSc1 ukMRBPrCVgLYlhpgwLw+6RDou73WOQ+SYb6+ChcyszV8dlDyw49bh2ebofR4l1X0wNX0lRVZxJZN W4W5cAMCsPSSLW6iBG7LWzP9Mj/U7WIKRSwSqMo7lWXemYZUHJdL4GC3XTU4VezJ5PMXHwqFuJmP cXGg4iZu6ofl/Qur8vTcPxwe73hkhNUF0CyyYmlttNQxGwh6On/uptJ0g20IeMSwYMx9Wr4NQaIv DTQuJxd69s6NLmKrFLGKpuocxaZPsF9M4Qx9Eqt7qPU2dKh2+HeVpmbmWF8E1cor1MBiVvNKhiVC fSP7HVGOdtI9tMEu+4KaP/sX8AkOxX52oheqEgkOVd6uuq2URpvv5GUjTrOzRxhsOLw7op0Jj4Yx YgGzIIQ0gNMyeX8dD1Yz0fofQYMdsI8TgNuxrgqjs0wRjEs/5oNfk+5CtW1y/z3PYM6ptYKAttgL 6mj7qzpvqYxDb4O948qUD0mvKomDQNkDBexHqd/AKS7wEz0fLkSdoyHSdAhX2EopEFnW1wYPvimi Lu3KzlVWYxw/ESunJ/hKqNyn4Z/G/CuWb/x75p9IluxlP5NSosyNvHgSFmFSD5KeFpbnoTTAq2Fx xh73nW8goI5MJlBJns2XDYbVNekEz3IyyUATOIQiYnzjxNUh4WtNWoqfchWyDM9/9Iifm14+Qtab NxASB2oCIPOTc++7uVfH8eBniKDPRqAXXcThhYRoakqAL+DWdPuP3xnzIXLYxny0zKTyE4zVyw9P w3w7VW+cuWeGcJcVHfwPvHSmIpHMNU++9xukPHy6jOTdRhoh5+oQFG91+5jNL4ArJBk+E//zm4cO HWmbru5K0tNsIG97WpDtTK56JCgBZ25CLSSIfMJpBp4A5AqUomumpG+zDaJ3SkJWY5/qUWj9IPDu L5Af1f2VdY8XINl8oF1CETFkDt6cZ2T9dz6Yr2qev9suiox5Wqoy3ti3k+8Ss69JxdDsdMz21PSt xQB4Pzw94jBaFm3CES8Ii0SEvk3rIupwQPfi3QQ1kdyUgmqrVrzKK9SWXP2dDWe764U7rPOwpwsc dVcwGHtbboc5sWGQnt0Rlu8yU6B7GINnMe3vnRsS9WKWZ+0s5c5uGBoXeK/2UfZtwh1I8S9YOXGG zaqdC/IFqQDZI5QAJ1HX6vf4pOk3XHsb6oOY/6NXKjiDLpYfqdkEmqcWBf0hKrVc8yTYCFcWxiFf lw6ZZmy+MchAqLM4FCAXufDP3DALKfNBalhci0yIuFtLT8lObZejuuLIWTmWF/+k49AgbQ4YzQGx g36Re11bY28Qaxbm2qlitStrKRT5QDgmtPdBgm78XXZgDMXlI2yG5qN8LoletCsZAmwAvW0L6qmf ilRetWqHZ11RB/VSueXTNZaRRlPMhM5lZkenx0ayjKgDZ+koXvCvabyJekR7bwpOMQIPlo2dKEY8 d43TR6Uq2poU7iSX1M6xOE3pd2tY/PBr5UeuNbjPLeZeSIUMQhc8uSoY65HDYDHLq3A7BQuVeaap Uz06L79+TawCMyvvmxcpsdhPElGyQqthbzTtLyO3zwauu3pya/FwSKiiuSNWnQCzn0FxlMRjR6P6 MZbLOisoUBx660JsINPoaLH0gWaAPMo6GyYLtq+gJ1zjNc+8aUWehEVy7wNLZS9ZzFJKA6RZJpny xettP1xa/UX73wlDDD0n52qX1bju6JnJ+M62VCjIoGudh8HCDd9FRFypxTl8Y95N+nghcYhxKzWn TPoiIFnujDtvWYGA150fx2l+y2qdG4HtUR3PffzZnuCCSM7Ic95YvcxQSE1RQC4L3Pvrl2M9HBdW Y3bhl4hrCkFFnwgWvkl1lmIZLiNcpbXdo46hea34fwoplLuT+Rc5sI7uddAOyut1B1JE6WiKBlOQ H/wx6zIhp6A3kXNY3hrWOq/Yy1Jjv8S9dy4lz/rw72FReHRvxvcU9RE3eWAsWmOqLMFC8I7fnOx8 HUt5Pyk874yA6gcH5Hw08BbhFFiaYcAvvDa/zcqxATT+9fsrdSjzyIKpbQ72tEnhBdUOAAqsYhB7 RGuo/9mrjzra9DGwNZ6uko2cWy1qZzFyRkg+p+otAwxMCiOE5PqbRU0O2fScEmMG15VP/HUODwqb M1P92xf6xO/ZEM7y7ACceAoJz3IwrBkh+IDB8pZ0N4wcWXXj64vpQUP9NXGfBVgMj6Jjp/wDbtfI 70GR+RNcZhI6POwqs836+jP2TQ/X/eN/pFQ0Qx05CzaALNhruzKWE0HyWdMjBEWG2s8FeRiyzKHc mVtf3sxOjAjP9rvQodVp2p3d2tIDHsx1gfpI1f0uRzt6hZ/fGplkA70TiKcHOLyJR0H9DAC7bPKL vTV6xu7oLz+Jho71oZ+UU699XFHPNWJdMtARTyM0aGVxWragvXq4t0jbX8uzq6rhoRpI27XNgYCb nfzlwubVE+iMjz6/8+hJHUhKulPRw+ZdBNp1DbzEll6xMFFhGwUKglEdf8RJ2x5u7TgABKa0lyav tQRgX8nOd9v5pdbBZMAkTms2mSYxmGpTYbi0rI8Zux9zrVBRYADpultPdrcWkbcw2ePpB10I47EI 2yBoZkZnZo2R4jCD0e5T94LGScORx5P7tcueAbafg/QCbb1YxjH8kU1eJrjaCCOKyCsmpz1fyNPw 6Ha3Qmbw5HSjsJ1ysoNVvG+jOBLGHJcwbT9nSYuWkmkZ/xFw3buTUACKeck/cHsaHwlHb5JiGKt4 NNKKrFXcDcA/+fJwOaWZ+s+24n5F/blBdyqeImqABkpfRtZ+mj9dXjuUVz3ZWD5oOganipwOWJ6w HbG0wXiK4SxxMZLA8lJcI/f/VEr+DtPXc9zOJvOg6iE6claE6s3x8yrGL3i3wMBjuex2+7KirXoE /LOhF0y+029rsByfwIPx2NzhveL7cvg/42RrcnCASekMQWmb32AKiynYdyoBN3BiY4oeG6+BNaYw Jx7LNkRsfxb+QX0dSVK8a1YLhpM1W+93sxrkpB3AUMfCM8AP6y1hH4hQJJrFH9RDGG9qWfTnv6UL mmZm3MQs0NoLd57YPXiwBSHoJClPaLY3aj4z3S9heWVP2BqfUXF+plIIpmIz+HwkcvAaX/GdaJt/ GmIcQx8duFK7qE0iEs/d57L9tIX49M1yhwCP7uqg/Os3AHQ220Z1HZlEPOyE3fKBrTS96cO28TXk IymYPz4M9GBBvvZKi8qSxDpdbsPiVAO0xED5zSn4wcHLKf5PRUiB5aAqdlMdzW9AziIeZSFomXk0 3tpWZ42akbmaEPC0sVAqEd2I0AAyGpq2nb88qQTDv7SjzW0rULaMcHc/9l1Dd1FTe0LoJLed+z6N ZHTJRjpiNiZCuUdDL0hjZ37cin+JIWiKh29cpHZp7e4Vn7tL7k8c7/Y8TWt6xMcsfxVzWdfsZeaU 5a2vkRq3MhkKMSGc4qvwddSHYWhtvaAkY75jF1J2iHKXwRDMG8OoX8skxzduQtBXzhtthYgm47mb hbYY+g4YflPRnpeBYkboBWOYjqgiVeEfrQT4CaX2lWhqT8LC086tKCYyAZUY+b6oYLWXedrc+6uY o60i3pUXhWfhz6xrynkNlawuwvdsHiRylkBEk5YguxUOHT0qqwX7hg9uzz4J167DpnQDDDZrLx9z 109S96QlazhH0/rsaSU/+P1S85MA9XiPAgWL1vFGRSJU0/Ym/f8yFJ9xwT891fm0O/oTUGflF1uj AVBbuQKsgzFZMotczudhDaoNqQ2yWYg4Yof2sVQCvl7jcbluiITUcvUdRSLeTwR/akCfpdJQR/xb M5PEP8ihOREY0VsUI1GBJQH8zryicLgqpAAdZp0rIBp6WXw60/BD853H5cAKyPPgaa3IbXa9Z/jf 67Ll4Ipb7zUup9CVhgl+YFgz5ahvkChaMzeHKLZSCpuhIY0FQxKPdRo8hSCZldofMhJCxjg+HNvI 9JAZlHtEXew+sjOnECF+8JDz327CBoe5aAf4S6+ZCfhbm6fjPrRmXfJNLirMZqMH6RXRB1ijrQXk AhFAwrLKXSLa/fFS7J8MpugdAbKL2n+rJoty5lM+WwcmjzFwhKohZe6G+xmNItsRag3RQ++wTa1y KrNzkCU3ei13PaTf74ey7ScRFZlWFKjes7DR21+3vXJ8GBuVuOuVi4trCvZfft9zU3smdtdQYIKs y1/CqD3nJmQlFlVYllgbbhqk2gf9syGhLkKOnsTDJj7g4w1BJ0dOP0gTE/BCe7572YQCmeYYXYGS NbZGrJOZ8ZpzXJ4G9y2U3thhMyV+wj5Zt/ttbmf6VHgpAJBuM8fsOL7V40vaOiAxGvMoiZ1U0aNE NgMLCUaB/uSu11spwXZUPwMiFrKMbfZHZ8tHm+y+VUJWxr9RPCuIJN42aWEOWoMD9SYKErKJfeFJ Y49W128eIoihb7fsNSG0rtMoQDcVkeQelot3eub+ZzTA9NknYx+EWeGI3fb/ofh4zpA1oGoxtbCh qAlynL/AOKef9eD5/WV+NBaLUcQ9lL9eDkAESZ5FHzGUwkFbBMgwkKPJNGf5l7hyeTKed3oNOSMZ eCVeHaHadnUd0Z946qzAcYlKDAM5ibnXijTxiuL4aCe++HB+H/49v9fNURQLO0cvqnKz2LRFh6bc Z6kz30IDmKb4fHK5dULtJf1ox4PjNgA+03r7hdQf/dHqphea7isMhgCyzqcKGGtUQ+3ttqh+osWU sqNqHO629axH1fDr3Maq1g781mGbtbqVd6rg5Dbkzr4i1DXLRyfHMRannSMLAvkrsganqQI0doba WSfe1xZIh+f+D0gjJNQsB0C8w3jRPz4ygaiwdKfMgqHhRAgL7rwCsnEcWbF6QAEJV1EuNZtZCYQs iTWq4sluunqO5daCmAWk+CJbLSRAylzYEV33jepdPwDwFVhkRwMrLrDn/jWRW7G6nQXL6mUGPELT IPK+OOEXtvr5SavjcgNjwrk0ABialNMBiWXJeluMlC4x5EmpD3Zhw0VbWopzV8lb8qB3dHxRg9St vb1bdyD/GWUlO5YymHfoGY15iQLjkatw5Kb0c5v4lhJ5ZHrmUlNnVtWUB41gulpqh/YvtSFiWDL9 squfvdoKsTjAh+RoNZaimPGgNItkt4irsP4gppsn3I4fqWVgiA28QVMmtPzFmZHZrkeHGKOq1Iz8 GiFwftycHPXKtkonmbLip4J5fOM/PES4Plxfw9YchvEyWVpwQd6MRLQwOsqH0TNVenNDCln2gg5P DeSniG/faHx1LSDYp+ZCUGWamdBwW8XQVf3W8+fxYvp9iMrPq5IuyMgOoVdTqZp4MltRavxbcW18 r+9KT2CJYgEa2vuUpb9ouLRsoTRp5Lhfiv8tvXJWYTX6ayfmVKrnaUOYGz906gHb1jVgXV79tC6l XMu9xhbPsukLn7ZTQxgdFNEKt04ZVTJZOkyZJQ0t6of1zETCySRMo4osuT1J6o14a87jooKdfQEZ v3z37sUzJZ4BZ8GbjvXSTCS7oNU9qeSPd4SUpxnEitSAZVsKjNO2ZqPNUOFoNVhEqgKXQIP8opx/ +zXfmY4xExz5PLDDg6zivfTNcbypU1xxXKch1fkNVxVByaAboIi2/mCvopQQmsH0Eh6r0GpRJkkp 1O7T8ktZ0x9uqww7O4HTVwrww+ouj8xoPXDGqCfq8+Z3coiJj/OqhJlS7X2kXVMVt+FpB4DlepIz OdjscTnwoyWmDE2eJ77a5DWgaVNT23QjhYOla3jr75MNnz4B8CIYMiT2qR1V+2M/LuMswV+rC3fi QUbITw2NdLy5JGexEVKHhzZgk+Sl7so5mRIaVtPvqwEXfMapKw9sIWSUD7/uyatcsvAZsm8FoA3s Bido2zYw8caXINP/p1rVwMmYK3baJLxI+k2NUSJUIDwGVQTN2I/H0ZxrAm3ciSDkI7je5YtOoZOn 3aW7LCj/w0+C1lzZRQo1D85rH2Z9ZxU7c14N5SElQhAAQLXhdQVFK3fftqlSjVfFyz8ExXZs9vU7 HGmFlTdyHge286fl5z+EzuMJGSVR6r7YU1UlweZdh+XxvM/s9zN3iYafpX9Bzp0sF4FpVviiv0wr aRok2muzfJT/yhhymlyYY8oo9mWGTkGG6ZAiIb5ZTz7bAfk19Ao190ULITLN3aMOhLevWTN6R8SP +ltIX03iPSYkjfP5pEvuEyEU7yqJI05E6G6ksR1OZK45JFU0h1b7OMt9R1BzonDjfqE4UPkf0W9h PpQXzAf/63xM+PFjrdb2//kTjrTbqgzODiMGh/3PlEUpOi7a+aBBNPGE9zsrx+ZmXf/dQ52yrX4Q nSa34t840bFkFx0eExQwru4qUGg5m+FDuS5S+2lI+K/2vIlcgu6ZABHzCYaZAzZKBMJF7gWHvLW4 dXp13RCnFkeQZmynNVx9UQmF9AnIqrZQlR6DPEr1RECWoUUfqbTXl7Li9CCPBkGO7H39KU5ryF/6 Jxa5ahI8GZEGnf35wvIpB3NBobJ3cHdeN5YrOlZeQwETMW0CWSaVbzMixqY/Owl/yd6J8GnqXkK7 bOjZZwODxeFI+eVpymWtOMqjQfZ/v3ioK25eg1mX4F9zYLZBgh8nbvkoAIZWTWgykhlbc8t/KP+/ hDt+kEepHPpaAJh3wVTXLOXkd2C7Ip7cg24L9kri87nB0JRcxM6op2bhZRCxmu4P9zI/Z2E7WOh1 aqe8I7coI/QoplQfhFqTirTwBWi64bwuGBAgivFo1l7PgTT7Q6nqfQ0ZHVsOT6twQXbJ4G5lgwAZ qAb42DtD2CRYOblN6woTaPfv6srBS/vvl212yvKlefefWEtmSN+JBVNHclMbgxnMojnjb0WvIxdk QFA++fZZx92bqd0J/IROnJhf4KtKuLDsQNxwY+H6UaMUHVAdgs7dtQS6Og9/22WVjCMj5AtBBn0m WtnZKBbtKPsU61cGq7UzFdCnVXhkTruRE4O29lEVbeYPNZ4HLnBukvRSEKoyy4kLiACc7vJZvdLX ukKCpDC7chr9l7v9fmasmFAQ0LRkLwLF5hH/3aEl+6/pYLFUrtirhkLR/SNLKRkL/DnyZPP9LjED +/FaY/I40EwUDMP139sPMGnulZ0YmSZjdbfC0M+XFkuZvM3clt2l7dfHxTnDzbH3h8OkPuSB1zv0 E37/odom56qbF1iW55jzscdPjykMWlbVqo2siqZCpDtRe962SJF3xq2BrsHAgxDStFRj5MDGRerH rakVxplYUEHsaRJ4YpVsbbZBguw6LPRJyfwSyo8DCNQE+eN27Em78ceDjNXS6efLI80Bp2YZE49B u1j0yG7FmviQp0klHDxkSuIdsJC1peJ0WQyK7wtU91MLGrGSUGJ9CVe0U9Ff8/4ku12YEpBBSWvm Z4zdgxtqUoyi2IRB/2vUZSuvrqIR8bvZKP2kXMdd4IXjHX/glDYsD+ptE69EFcBM7UhClpUjw17p d73xa8+oigIOjhI28LnwstucsHvpxlFAQLoV61PO/CgKaXUcEU/Nqh+zxlr2osp4w5dmfzAfPwKL 36fYItjCdsVEHifUu+9Fi2l8pOounyjdPyqRbCkvyym2IcX1zwWSwdFuMW8r7jsRs8Aqn+wRv9JG A6NTRsTTtvymqVW1d1xzYEvRkRz003EgdOcs/oRYYzMOj4IRxSOurENcO6fJvhWU9RJAb0PrcGAf O2t5ryU+hi0g+9ePqfBKyG5lYk+lIZm/hWhjX7Z1OjOBZZ2T9t8vVfonwk5bOPf/RM3U0STnXvAx WNySIUtqm55kI6vTp+fJ1Xud6tLOzDgNcdxvOz7rSwDzSg5vRrVtX7BXdFtckt7n9+wZGsLmKsno m9IihSSU/PAc+EROrnPL4/fra4DBkuO7h1UVbQQdFW9nNJIziObNcUJ163o5zrKGeWS1dED+sLlc GnSmMwb+qyrtSl0/n5U0bXMXY3fju/IEnvBTlWWVF2YtV8ZVinTSLJnIhWDH4ZHRupRlaCOL9LAY pRcFisby7uHP/fkh8XLLIYqCIa6KZtkpQinRX0SNGtIabYj+plYKLn2EAr81IOuhh+HBjWqCAcM+ zfv3INCLO+i0zP4nxR2CdjLuZx7Mgi9Tb4LoWM//GtGV4DcpQ3qgaZ1XT3U3qYRxe2vypFBffdY0 KQC193hNw0UDl5JZ+ZcGMJCSLt9d7XCPMlCj1NmLXtlDWPAyiJYhyAtkHjftcKltITiIP3dp1SO7 ZjET+vNoG5J6xp+NtUAFTZICLL0Y0sjh6DwHbUkp7c6hjfACYJQJ27c/5wp2f4BoaomytGNuHsdj bIU8cYfgk3MjJsopoHWk+KexnOrSX7DixpiEAcpJCBsWRQ8KRCCi1xRup7su7weekg53UpapP03V uoQRhA86qqXLpV/MMbXUpL26aj1GDHVfErdk70+nGj/aHi35eLnSuDeC9X9SB0Bw1pbrl36qHYxk T1+08I1u2KsBDzkdwsSLf+JdMQqbNSgGqWoZh3NZvBzyNZQXydMWC/DmviZu1WHEc4ycXlBVrdki qaRYHXC4v3UkGp6vsA4Con4ncLcuV5MladbElgzzG8rM4cq6w/750CZ1zITSceuU0XKWxLu5k+nO dxlGs9N5y4VyzNPaE1Q7X/omHt6oQLwIXxMDGxFlPeBN+zkNR+MtaWsptPYuUNhHH+KtDyYSORtp zZ19qtndK1zMQxu/bYb4JMFDa9SebMeXpjNDSD6tmXJgOrLNyCpnG3Z9IOWilfdu69M5FzHz+mKq DEvCRXx3YYuKE3zKLfZmRNS2bbVjFVVz4At8eifvAKTa7crSpWarRsX+GeA4bOQmonSZZMb94QiV SVbsE1Lk65ZyYnVMX7i3JXjeE/okd4hD58TNSjMdsb79BOwnTE+EHGG4v20WE6wXVGAzv8HTP2tp SDY9rMZXqBy0ZHtfKW4/XxG8RdrS9NYKaipELcw/exT19HGiT2WOQ137EZ8IqQxuQhNiJgqJ8WOk 9JkW83Ni/jndexYi5p97xt4C8o1xlHUgXTQmhQ2JQceqPbiCoMWn7jxg1PyNzmVq3uF1fTiFS9l1 BR91jU92Brr7sN0mC29Yc5qac3jPr/8PFcdh98vFi8PtgeNUNFPqWFvXj7ZlsBMAs1lfxcY+p2re FzrBy1uQNwhPSqU4c6qPjK/BqqI/YnLss/C3RE82n1imlJuyCoanz+rak7YTkWNbIxJzDkUKHY0B fWM12U76fjgGQzqdaVjVSBrMo76+ui9Qj+xQWglBDsPy4XoiC4Ptqo6C9IcBsj/0fZU/+fyjc4Ny 4UsJG4YpTq/1JIr+7y2ZkuNERAK5vPbCu4wQHZLPCzFiIgLnVUqfW/exBvvr+ivgf7f1PbmhU6tL zCRLKXY4hb/Q8qs6EBVWLCXWRE0TZASi3jcz70trjXQUDhDb1pNAVlQYaFWdxrv33reH4cSCJ3nX Va4W7yVRz5ckMmNcInghpelnRqHzxjboOcvhfU5cTa/PGsY/YRKMXgNfpHJG80HiCQZ6a7RHopwf 1CDRrEolmk4SKecaaFAhtBWu0R62WyRzeqgeIRWhoK9JFSe1ngsRnKP2I/JE+OlMkprlR4j+iGSD RvU5oBm6ZOfXR+r77/gE5X77nB6kzdJsoOlWGy6yz1WKCsJt32u055okPFBblAAHdauUTA8ZDAjK 7yRrFn7q8rEfxEsQ13iHnG7NwZVPvM1EWFUtCIOoOwkJEHfvhTTzwV3HW/ttj7qCnI4nP/3U+xsd uhEtANiIn9Zr0ubI/2wXSG/t3clIeIBN5tgYFOhcS30+XbPSBi90N8B8Vt0nMQ+XpFHHHvAm32ka YUp+mSwE63JUJ3GX2t+Wmb6dznjjgK1bZuPPC9jRiEeS9fLuv1wpZxFIieONDsDo+95lFsSRbPiN RbxU0TUsRNfMCIWY9HNZgNxZICHViLZvqg9xqx0jI9+mmugrrgAwDqLkMyNB2Ij+jB88vrAOiXO8 ggKvz0MNQICi/Iw7vC0Z5oSpXuhBdBkzYLBq/hg1IFkUGIGHGG6rFGOUQL29PnM6lPuuQduc6kh4 jRfIGawZ6mnmFid3dyaXY7SBEK6pq3jc7gVUu0nJC2+qTnNKD39FrN+NcmumMqhBzUa98xeSRYPx XUvnFuQQQqKj+6uSCHmhKnuhkfiGQisJZSv9LaiLMXlcSZnDqCMR9mh+OuOsbKfxfYG9OworQpsp UwKlMftwfAgHifxB/C8pNpjSrtcQv81IXZw5N2Vxe4DB340cTl35QMerbHeqxFsVi3WgEiRiGj8m ZCePucbfXZSw/yZmg+my3WLnybRC4zLRVAm8s3fPigD64Fqm4yL70V4Z/EYg17MTnOznm1Z4A8LC t6u0w/IsBOgNiX8MOXjwBPRt2Imw510UQ618JqzXlpPbozfHelzHXYuV118A6lMM29aOD/mwzLzU gBYRit4FKtq8f4Bl6MnuHq/ummLQDGQuYvieaukzLC2RdsHN4AGGUESZqMCOiYdFCfhA/L9jiJwO ZxlWHhp6F4stfes+fCXS/uvJEFcm1Aez6ecy/Xy8NZwQGA37PsYyyNaHKIxvyIIXkxq+w6Y7JwNA 2VvQKzmvb1wYAlLvBkHIvayXFr1V8Xk4+TTnPCdK/l2N7b/9vUBu0JwR7UYkEMtNgsfQT+jR1DXp 1zjb9VV49vk4EMSoCkUVy/LiB5PSRD1uiql+Gvtuey8Nb3nXTkYskL6YaCrmGoYzNXH72wo/Y4sA /rmDzdq8zwpXGb6iBSns6DkXpbmmoSwgWhg6AjaIR8kBDl5eNSKURTQ4jCAR/fcAAHY0vFZtmjR9 GatMvS/VpQuXzauAn1uzvQAwbXfXHOlYz9PINpmuJkw7E+SmeyMWBJQPLmrbN5Akowv3HcsmEqXM oVgyvpLawGUt+eDkHzWFfuIDip2DA8ShV2wVjC2Ls3Wg1iuNR7tRZsibs9duG9c2mAnNhdmVfjGT 4fUCyJNRQebHaQpbGRTtIttWZQHhP9UpQ03mT2/HdR1LbFaEym+Q8kj93uLEk9gdMp4q4PBDgRbh BkU954uxKWWyO0lXhCscihxpqZ0CKJKcT18sXbtMhhka6rpGFmW4yM+8Mx8D/iHoB5+bgwJitTk8 FeWQFJ9CwfBt4oYwy1swSkP099IUccnpaDQIzSotBibYS2R0F3j0suoK9mhLmACDfQwtoxCcWCda GKN5GuE8dNqL2RS8JGFNsQQFSazP102HUkSA7j2HKCx25JPKNQgabRr6Xtr9hnppRkDYmq0xX26V qoCPak3ptJxwZpVJlRM4flAcd7CdQNgF+NtLUnVQ4Kl17bmyX73fCZKTMRM0smphLLia4CNhU4jw /gYJk2ZpnbhVBKhpC7iGiTNjPTc+822chYC63/9LPfVt52MAyRrcYkDAdcgvdQfrDOb1ZcMyHxC1 H0umyy6fSXbdP13JzYg2e+AwrtElEjfvXmO+Tm0/ZtjhSuX/qssTGynuf3szQyedAe2wsj56fFLJ GZOF2MknvmXb30dzeMOqHtT8S0XsJ46MV4Z+egFphTfyviWYsUVfVQLWiHp6wV2Fq/U2HYSM6MeD d2d4wGgG7Al4C6NYp1I8QhodQG4XkAW98InStGgfDrmIB91bY34Q8k4C7Ce8KyuLugWuNLIvh/XO DRI8WMz5TPI8McnpHTP0IeOhtV/oigx5M30YAZ/2kTvG6W7tA1cVgCw5VnEI4heN6Q4VsaMMKL7D 4ZziNfPwUvJ/UUVtZbU7+VNE9Zamljl1u4jFlmOqQTBFdAJIw2Z3SV8B78vT61ydiJroDwwL9N+u ZEyFLrvgLafsr/CILcVbVMNk75zEw8Y/F/jmKsMnsseGlVks4ryPgLPdQgyD335WAZqrpiutlMKd YlJaeGOGzpAVWFNVxnUP2PRyRIKZWAkjblD4S9pga7sOnSpN90rld//pnIe6ZL3gt3hmf8GF/AJA prOzdXjZIzFsfZnhC2nnoa7NlFj/i0PaSfuO4d4iJa+DZxRdQUVvsOlOxTlr5zNAfWdsmEy00JqF Qa/ma0KN1K4+4gD6+Ray0Q0ms0ntmO2fNLdbfC1CB5+6hL3MOO/PCS27ZyN8YOfLHRRX0p2/ugCa nMnEeON3lpZG8aUYOVOLd9IxP0v0ifxwcnooRw2XeIFIxEkjSaeIDIgdYm8SycJbbX4p61eXSJCo cspSyr5/iq/lEzHEXl9zF5ry2DBBaWyV1/51z4JXC3VrJask/7LbWe06I1d7PmoENNYxYC1aqOe4 xFMmGiCBWxgz8UReuJf1Nw0KpICAiO2L95ubBQRk425WPIZgo/0KDyJhJcQ5EvzgMHCuM9PQtT5v O1DC00KfqKllERvrt6ZYC5LjWGt/ilfDuZbhnF+hFa4uJ8MWWoJXHzEzkKcJTgBHh4abDBER5SWQ NfZr1ajbA5qbBpKL1xRiqh6F9HuK8VIS05HSD55kz2Gnjk9+jPdmF6WAfY3cQRWt/45UorerncqZ +3ydir08fbcdrGOfeIu1rK+/cTV6XqMHv1kUTQtRMc4m0Q47+245h6wNGy2M2bSHkj7gnH9so9Zn CqaBd0KsUMUWDjUczApiIUE9UVDm26lotahnjITjtk3VZbzHbBXMUncRXcuqJfJysA3JNLUJVLBk 9zYN1zoYqIzsry6N+6oUlWGpxAxw9N+a4IoUoOlhE/QGcsrPl1SVFp2DH0PKZgZ4AZnP345Q1/RJ QeGaO6192AipYAAVTL9J7GSE/CaRYY15JJ7cpHtMb53MKo9WFTAUkklWzAJP3PNqb5h4UtofB0wm 1z/2p3VXYCBCY7XPDeHB960ljeMiMJ5P6kXMpMd715SOz5q1Puc7N8iBAR1z4b0Vf0DqsomvD8Nm TuqGN/8pe0/5LfrIXDfpCOHwEO0vlksUdvEX6LeFBjG1gYakBB0hkbNNUBS3iVfM/V0dR2pUPdib 5vQaRMC1mC00cJLOXL5UGMT7rQvGEh3lbJL8KXSvrnXw9FgJr1zmejX9WByfLLrmmIag0dTldCxr ZH0+Q6jlpC3ERyDqcvYZHxMRyoBvM6ALONbma159vpT+OEG9NR65hAheX4J/H6o0pB0JBhiHY5LV 1utQjCh1H6HI5BlXx5XWImYseAfT+FkedwGsg1epmujUxyyjLfgjj4GmZoBEn4YQ5NUOlFNiGD26 BEd/wMUJWhrEcEHevhaTiI7BQwwiicEAHnL/iGUz3Z0CAzwamX5FhsnJtko/PVa00KuyWHLY77aM hwd25KDaogoGSsNhtccfCAWWiqlByPK9PRYfmfoHsXpLqprqMR92WjVZdFgXrc31c3+8z8SesjTo lVivMAm+9UDW7S3wyDwovt9GoE6+B05CiZz/iW4dPn2nrg2ANLRhqf2fXPwFODNGIVw7HWy4klTO ny++UEKrzhqwb0pwAdXA260OA2Lca1TE1dFjZmKLGSqlIj/GxGjoxt83ewCMiFpAPxFzf+J9QT73 4ccuFXRw3NAHJxnK9or3CFHAeCI88PYtzJbiwyFXCbCMEYOJzNhujhyKJ/U2DMb1IXWduLmyxOR2 pSMQBYsY20tPf68dyvTGWpLbZzPu1HpRNI9p/UUWahzLvfos25gmI+fB1V5/8NUFp0hiWAFiQowQ b6vZveRkQDRFF9/XuskIujY+Z4yPdqyaqaoYWTl9wgoemFpgoF5UMLHSPbTLpVkf9r/BBLUkzXSc O5YfPHVpnqT5at2GXY9w6PRJO6JZz0byPOu5EqBAR1RdJi4gRkBTN8ZQ/FYQZR77rXyvskSXzJVV eKEXjaQuM5pr78J4l5n0GtZZFNGQYXh/4+n2EtVGrOhhaZrcE9wSsUIMdfecIiVJBVGjepMEk7hH etFmwSUnPBxf0H6Hi9ubsDcO8ZEFNbSdWlWHq0RoYU4ZFOoTl2QxhOUthY6zTTiMatFtImwhW9ig aGEjujRcRfSyLZrvoqzWKzfMV3sj8w6CJ48w1H6ObfX3mntB5XrgNoQdLtY/4zfXVfGCEN7shSAr Wdu6Wif0nurwDBbE7Osx58yIknOXABbvIRyjKUHOqa485oPbtYd/0foDhhxeCbkPnlO/+ndWykKa RKdYQU4ecqYHV60YbCos86uDoENGXnUeCgRMDCICvfAr1S/3SlE0NgFt3fE4j2I1Ek+kFvYBffgU ykInckd086mOv7LWyex5B3kol4aEuxaYg12xFfPsuA7E9dwCkI96lhiU+KN13Hblax9wEwI3A9O3 8khPQ6kJo2BeOep7Z+gVVJWpPR7/DQEafoeyYhYtWi+8A1N/VmmXf8xDQP36eHitCb2hJ++2xIpv IukMGDSyHn5XzeI8iFjntdnqCs9rvvbF4BL6xi8dcsnfXIQQSpVrMWjRQkdbaWw27OqdPuUr+fi3 OQXuPH1Df49mgqefVvCjDEhmX0pnMmVao7GtrXHBIKq4smEPHyzElJSx1Q2QuoqYy9xt8OjpAGEn WWSGq4QtwqGxIn+m5w27M7kWPBV0l0696GVZobxZ7DpqXRvc+30LcQiizYgnx7MC3UCq43bvjrF5 26cgIcFkmS+ggupI8cQi5zi8h9mHD0ZfzxdTuB4JK1Pj4OX7Sc+E0Ezw9COHw+iRmDpVYcqgWl/g X9f35v5mGQ7rZutKZKuN9fttgHWXB0wQ8oAqk9uC9aiBYa1cIP0wBF3uFDC750yqv7pUcGmkoN2z 6GRb2hZ/xOtAoF6BoDUWpX0//T6mN9XkBM31J3Bjtnw2zD42f28xtzJJOom1l88dcvOOp1H9cNo0 kZyZIe9LSXiswHgYeQqI8pbmbcQkGRgtIza4ZHHLq+zwRmZtDF3zOSCzz6lnhJgdetEbgUWs3Z8Y OcxN1l4ZzlfrI62X9EsCVStaS+ASlsR27HLamrXwAxOJ51pv28Po0V6E5tE4fbbqQNnRCuYo0RmN qriUUBbvy1dNgErTObHBuc4JUATq9C3orG7391oaNiTITyn2YUJTanFqKnefKRJaSrAwbAqNuEyN IVppDV1q8n9BwQh+pT+3WzECpSMBaji4T2xTFzCLDt6zX2f4sNPP/zJs6SwqmVNv1TO5iEkgJ7HR Hlt0ey/FeFVrnE/upi/omSwoMOXg4AO2Mu77zd/bQyh2vAGuNz73fkSlpGdF9nvZgDjIQTo6xH8r jdBPqbhnge5JKeu/oalQLQ0jAmE4RQYrXYT3ok68c9/pDH7vY8W82CiUrUBdsYoeFzEP3eFvzNiy s3PgXT2+WN/TkSCxRrVvAMslF2yRNbzbmlaQIqFS+AEU9YopgKnfmxEwi3DPorb5E7fFmRTRmdx3 sRS2dyxz/rTjlJ8fIsxmUPPNiaZrfrzzZNBooH4aYWKHFbBG89n3MTByb4GO70zobkhT6NdxzrAW wIY3A23tYz6ofY9Wo5S6N/NIq7OYXgx4gOW1ydTKC31IHqeLq7jyEq0YWXiETGWWEY1VEUJ6c2pX amFtWeKdOQ4HKMBwlYSzkcuqF06AqVM79roIXstfZ4Lz54OZoY0EBGEZbOmmJi7KfZKgwgk7topG j2y58pQg4awB5l5cdnUoBcunJtCJRlrWz+LeAM1Zzw3g3bYksLyA91sa2DCmN/SZkiJdn+RZju1+ IwJMyovUJ0uIKNJfwU4Wig7lAmOwcNzSEXnxCcWGcLnhUAgrX4fbyjAAxYr3FNSStjRVw9mUCYeo wxPjmKuEzXLo2aPjlPp2W7vBS6GOc7n+62U+ycLuligomUo+ZjOv+KbD+S2lczpZOo3VpZr2Evuc CziVnyrFlDyw9pnU/XssRsF5zDudOSbkVuFgt9vf3cDKOubMpUeEaaszelBEJuGS/N0lau7Jo/N7 JZ0z0wyPzai0jKhvGvHL7vS2q1EqD5IZpGYjygjLNWWGa6QOlh/9eG8rV7dUaxCCDVyURnFO50pt JLflL2q6ARS9+5v+z+nBIY4zIy6d00N6yvcia56qYMAFkqAZM7Dn8YnUe9FCex9ada7Tt4mK2QaT bBPJUlYtBibz6GIkUrm/6sby9ZZI3yIAH8pvNPTri5Xp1VTKp8TKF+y3Gvx+UK5OeoA3XFMBYOZW h2+lqDnnnWwPISoM0muiidy8NGxp5qNnR+EpyTbuDMNlv6hxEYJvF5yMr6FbTkcC9ZShWGvJ5biC dM5oHOcZ5R4lbEVNYAzcSfFCLDxy/TjteC0sU6czeekkz2Q+R20o3MNIzc8lG5B3R1HBurBckqZg mX1KROi7jvFbqIvSacrWgbOXJMOza7sGRqkZ/0WEE5GduPMEg9blQxsZwOG++t0bnTsqmPnCdMsC otjpHXAMBQxKvs+JYN0As8LIFsjVDrm1VaTp7I7JrCaiDI1CnzYlX7IfhDMFXHm0YOMlzr2NO/Hs I64jKaBV5ZUynDXUXun5YvwMtySVLDWokelC0RzNZT2OYgV06jW3XtUDcK68ninWuC0kGrEtsM+C F1NgyiaOFmF2GazJs4y7Z7LevM5hPN4/3JLtN4fuTtKyI/nP2O5QQMK3QG0gYgpW7FCUV+5tNRmJ lA3pGF5tcs25N2JgYNKOjkpxWZ78pbbYMggIXdUBF1BhSrhGeOu1og/2e7nCNVkA54Y5xnEMkFQS Yxjm63zf/guLX63Xz2VIrFPQSa0JNn4dg+GhVKWQuRbj1LR8sRK1LNADaagB8HMMBXLhpop72dMp a1w97hhBm6HNzXb8HbIYDwBYWajLWCBQj9kvw8ynpdHMndMDufipPQd6xOr+BK9KkRHseViK27gX XQM5YqelNX7mMv4bL2aLCGAc+2X91fI+/H9JDX0/zxR8icbkqFyo1XzaKkI+s50R2uillMm+wz87 VT1Wq80E8pw1IAR/J40VzaVeQJ2IZOvKrMtCsg0vvd1ifHISebmdhCSRDek5L8yUlOjWLJYBAOSz LEooGD1NQ907CSWNLTsr4fkYZJF/VqJqUimrxKQ8Kbziex4ix1gE/VmGLAJ2iXpNlT91z/x8U6B3 /JpsUYCisBSVoxaOE0XnQWa+8dLvkmEEB2Nq3wArM0OH2iEri6jyNoDcTqLuWoAc2P3mDTBZKXR+ TnKDjGttT0V5migTjsGGsQOD0BoXbDkBUEp8DUPEkjdtJAPjlzwhW1h1dxZnpnjwUyuN73t4GXbX 9vOY5rleOek7BmRAo6NDsdOYDoSZYe+SSv90jWPlwKKjZBQo5ps4EmOElzypbc9xvGmToEp33i/L FU42lSdvzX0MBRAHRLs03iRpOmablJWW+gOP+r5ThgPBtXYBiZLyDRHPH9SLnJLDm1B5SqbpFhXx bM72w+5OpPreRFjmYiLqhX6NXgEriQycwxDxMlhIBQA+fx/vR7iH4oWSx/6aY8m/VE6v3z2EQhI6 l3vTH8QtQqi+Bl4OS8Cfl5KEoQwtcOg/k/pVEoQwHFO5auUI6WYClbVCQsei3W5Aa9EWb/65hL+W mvmcfrQzkRYFOLxQHr5fi5CWIOfj5dQfPqeMB4X4OZkSuUxUpqCZBql4WCD7EJYW1v/ZpXrftxTe kSzuhGATVvBnapm6T6JZDKlfU993cB7ElEsUCVARQQJ9+V/DrD0U2wmVHmUYWfBx4fatNlRk2A0Y qry4lIVUGzOv256wzRvtLFPkcQm1xxO4u/xBU22NCqqXf9uv6oHPJdfExt6f/pNtecv/8Ziwv4RE GlSkuW2YW4+F6naHT97oSWwOnc+U/kYItqxm2eLvTGclz2wKex5onc6C4TsAE3Jz/Xh790LNZaK8 UcCJCEg1O4lumwmGoiRI4OfiverDgvoz3yCUsHDuwx9+mhoIVFe0iRVA58dxlyxz6G34DlB6U/Y3 0amevGDTqbW8QqRl2G4t4aclBnYJ55RF9kK3kp15pQWxuIoa6lzyWRAwT59U9N2bMdzNXo6bt1Rl ZiXB7ozQEaf9SUVQyKB3vK2QOM5mwbEKJzq2H7giqfg5nqysdJhhCOefM7UJbdt/Am15gsrOy++Z 2Fi+APp9bwxZfpAY6aqeEmulN6Bzu+fvYgJ0H35XpbZmRBZhXJcRnVsAw6/XnBuo5uKUANxBa+hH 7YLjgDQaNUpgP/3A0K7NFl6/5RbM7N7njoWg5fxQPXW/shs1XbK5Re8ZCMQM0Tj+dIzFauoEid+U zfsXZ0aQ12Xc35c+MPYEfE6oYHyoE+xvWtxR95xoiLRWwu3dKWpmZaipfT2677vjMsQtOCnOXrBo eHdLYBi/siWtJFS2AKeyAi8zuYq5NViP68F19Yp9XPf4G4LdOOO9h5gOdrwl+axy4VzvtiH2VwrZ owcNCaQVp6TcpthlT66s0nuD824EkxUofX4ZLYFOFFmqZOs+6QtPqlhrNhvIyjE0mMaEwJ//cOsk cDn8Ot8kFxUgqqu9CRrcgUauZvr54a1RSL94S/wJIUfrYmNmgWTLcsy8imbSdcDjSzjRsq1fIwae HOGSfrdxVTVFrKR+cDSku/0T8BAMj5sK3+Y2DvXFRB+gaqY6VnK6gjIlOk0k/xpnS6ARtTxs5wlW swAD//dLPflZ/J0u9CY6nsMncJa92ksEVfEoPTVhNCSA7Uo82p3qQ/Fhq38LCZ09FYHphwEv84Lz xDWlJ/gN3Z5JCNw6ItJWjSBfnwaIiIBKKuRcFy5FEBLOxSwQhppllL5ngajiwGD2JI2LuirPtzPO QobfYS2k1M8e8hD8o+4CfUFoukcrNe+6jfqnwU8NW4XzfrPcuEBlN8U9lQvc6PLnj8qcZCQTtNZm bTbjEksLdzPp0zaXrtidxf4YO+10h29fe0IbEijQJb158zZblws9xYkTroVqR31SSKn+YTxG1Ljx xhoa3/DpqlndcZ+oqLhVMfe0qlmPOUY93envSa99ENwwc3GFhTrkQYnbyu/BOlmLxpBBHplFB9IJ aVGIgDr9LYz33PXNIgiDx1/m2cd5bBoHpa8UyH3hJQ+jALHMzX7MqZW68K8vxzPnrK84sxYZDs8m JhhF1AUVYZpcQSQuGxc66OVAEPH1ZJqiWwpWh1P6AstzGFLCdOH6uXAxCCxYRMBNtO/2SKESeQyw PF3z7VvXVZIx8F3uUsoR82wafeeksuy2jxGfuLoGdfxxQ/02PnsTQ58gs47HkY0Ql78E2INDpxQK G85/bR+Sid1WCTyZIvHjjpAkyPOP4+bh4YCFiTppcpFrur9Qw8A0xfmXvQFbj7mJXryyPL457n+t TcRygPEiavfEinKs5nWy8FV6BEfcgC4NZ58qWmuf4ApIYYvg8+bX+WCBfvC6SDtv7GEtNGEeMY7x flhi7CIwiA9SzGCiUhNHqEVEtsff2q/oztefSqtnfoLNItSxlbOLpnLV+0gr6U/N6B4KI6l7Jla/ O8FuCYI4HliGTrkvFbAutZfL1RPyriSZzTmVfiFbyYuMMvp6Rdoa2z/EMXc6vWQPW5C9i67U9z4S UhL7NRnplTGKFyjl7PUwFS1JmbPntrJlgRKeVoshny4QgyWlW6hxZKMUWlW+pp8UeQ+6Gw+mQlxv j0yNtglVjoXuNCqkoWuLs/Wl5WGTzDmdgXkUphS7WA5kqhJvoBZvhuSHDoYDwdenUwAOa4C9BLpx nI5vZSQJxJO2yiO7J/YNH+JnY8uEu44y3HiTaLGcdV4iOH9I7gTl4ga2eNZ2FVIn48iJfWKjW8Nt fXp44r98Uy9RKmYRehTE4ofCLTOS45j7KuXiLkw/k1t1vBBRhrK98Jl6ZPOhCYm2juG0pC96sON6 QFk0Vli2Kj0mTfJ3RfZg/C02y2CwyfgD+yrox247ihzi1RqqUWSnCW4/RAwRYGVDNptuU6fKif5N zZ/ibrjlzIMfyBujTRTwc2K1DbM67Sb33Ir1pqut342NdLF00NkgHOhu9x27Td8i+aVQrYI2nN+v LtIDm1pdKsPmnggH6fEin04+UPZzDxDdYoUmaAxTbKxg56h9mtUANHHvQJbm8d/it8BM2EyrbLTg zqy6oqd89O3UrHO8s95pysjuPKCkcm/08Z26psOBTA2b71Cth4PKiTvf2gEEOSKc7YTOn5XwLa4T 9qy9zzcPWcBajPCXILlNh+KC7Hhk5ejSszPRJjeSAtgxrEtDvDmPe+bfxtG0hCXSaMYL3vahgfuU 7JDYXdJmz67dyPzfU1d6+Mk3wPc7to4GZP4kKRimZOH+lKL/iffi00VuDJzwJGP2+9dn/lwI6x71 AZlfes9hKLzhcr0T3766Mm+/Owc5eyjvs67pEznKTJ0Xq1ohwWrPgUtt0ZsNDxrMdm3ryOpQ+RUr NLz5qbYXrKYVkw2jsqQH67kRisxq77kjitEEeAOV8T1wJs5DsHPt0c2RUbVLVyQ1zIMZgcVExtHP DT+1sIU1CMB+i5Uq5cGgzCjjfOz9rz+FTg0SoFDwQiteXskt7tErEyZedZYiMkjgOrEcOz6gOz2N do3BUjTP9Jb7AfvzuH30GA0KpNtasCu/7JtJoC33veQg7a3nWNkzXlaPyTbq3fOes1mvycPJZrMb pXbTByXbSyPFFKAcmrCGNxUe6VDA1G3GLs9zFSPi1sYAQ4pUmF29GEOqMmgWYCkA0k4qY0O3XZgN TBm9v6nevApGMFgU56deF6Lg1sa0K9oMyysGdrp8BhbG0rg+i8MhXlMLJeMZ1Rdv5wJtXnUbnvCx axz3W9nCCchVg0g7vSDGgrufohRKShYOKB06YGGt9vME+2FF+mJvOsi8yY5Crw+inqkP1Q9RDxV2 ZdCBHV9nYLcIdGFr5t2YYHezZrxEqfTLzgf6gxf7jHtRSe2OFzHr4EKWP7yCPb40SCGv5/Vskznc vcvjz6yXLCXihDd2ZWR8kBb4aGA/m7Ybl2Nm8o9gTqzEY//DBoZw5GQt1vnEKVpgnFPq6l3EKMa6 DrVIIf4blwE2hCl+SnZDWm0HsnAMD1kxWILjLNID1HRX2d7HngDKbsQrrpx1DywE6zhFN6omSrwI kDswSaPQk+ZmgtV8VE60Ef+S09bY2SCOo9G51YBgp2EBnY7UrttSDjgoHgq8TELL/jjg6saPfdge MwgkoIaCo3hvolR6xrQYr6EfzeytFZ4O+G2jP2RRDAsB9ZbtpMGFiB5QDzDF6Hfe89oEbkDxiC2H GzKnAzyQJ54raz1/13JbSw+sKlKbZXjdnbkcQGKynxQH848WiSqu0ClskL5KqG35hRHG30Vps7An kJ360rR3cBqp1wlZyEJp8dDnNb2KedV/ldRJbJDsfHVVEHWM4m+Rldlolwax1Dll4/LZSAEdQpI7 jZFLQZ2kAUn/J959QlYH9srizq7wrzL8MuWOKHfWq4BAqGF3DdMsKmtY1T4KMceGIwhO+nNMOn7R HkWxBn62UEsE4aWmF75WMSj9tZmuJsdCH72opIjnJ6fJRHWcwyJj0uX2wGJhYrfcpzWX9CSCcrf6 czKCp+U/8zoXiHdUe/3hDF91Rx/9PGXMJvcVj2UAQ3vIFgUYT9pR2CoTq0+2bsisSTB4cNfnBOjC BIQEUZUmT3XD6SwhDOJRfPFAKHb2Aze/ubw/zZOuPBtpLRJ5dyYePyDqGF9jm/uvmut5bIdgVhYL JFzhXmb+jpD5m9AvgIgMPvo/HMdom+F3NxCI+JlRKoh1P3mbwBIIVO4x9+53/yMDbv6NPRIS1Vch y1tURLnYh0VnaJtCU64mLdvBwikMVHI9bixaN0kDqd0hrO4/lFrOXCSKmVa1Cu4W/efTzMPQVpRd Q5ZCBzPc9MSQK+6eafwOQTJSMx1gtgLivtt5dX3fON+fLt15qMpuslDlz6LhFXRM78/6NpwRp3gn nH7nzdmLCBoHTdvMJ0GS00fnxzaor6/9fJSJWrMMHKApGuZYRmvJeUD8ysGeBmqsbye+5JWX1zmQ fgjJgQoNlhJmyVpkKGjO+FB6hOd3P+tf7v+RcDSe6dj9HTLgr8TVF9TYclCz5xD6nodutcGcalaa 3aaHnJQ5plNTZ0v04cft2RodYy8DtAlTUz6yXmMzO9p/9EqmeTb7i/d7c/DtdVTmaNIXIi0eV10n R007aFriUp43Ezu6CVcICPkfGnWetRvITvkb38dzX3iCAtrRHSH9T+gGaWMd3yUFOwEG3cXx6kwX PEivPVxpQCCHhuHeuQXcWrodXuEiedVk3OFc8psB3HAh5xhKqISHDR05KhaXPEs+fN6ZpBYmlh8Y 2mTPmPR8vBKjz3uoXTREWL2krMWJpY9uY5OWHZg7NZgEQK3QvLBKtTVYxUWeZfnhDRANGMDYED/A VkuDvvHwJKpMEeSfQwRx7HMlaouy7mwPLbkFaFc6afa2+R9zx/YVs2WWgOV+lTdf+xqOVQjzSQy6 qYoFQ4o5cHaW96IitxTYzSuXbejgFT5JadHGvOqc8CO+DxoyAjZgY2voHqUmXgVlxJ9MYe+xm/HJ gs3rtVynIsazA3L0KsBw91+pFTCQZky2mhOT+wy1nhO4bSkEsmARJoTILv2sc+PfkPboSE0EwiVs 3V2HVuZIexLMiKTTdKe0YW0UxjwBFGGV6GUZCmuYXj/wFJ6Q1N2d0lJrlDDPrvBJGVmuWlw6Ae4u q4sk1JDNI+k6UKy7F/dPS9NsssK345lTsSPZZNveGU8ihw8NWb2KRRpBfaHYAcQjc2MSQf5JwRUm kCVWcOp9Xq//dtzD9cSudUMEtjr3UyBXDr9Eu0a7xZyz9zp28HbdZYNb3V2cTuhgUcESAymdN7II hG/SAajD5/mOpTpN25mygZAneG89FRSrildv1/KmFyRWb+Okb8eOmo4CyEz0dK9YMniZcqKKAerc UsALIf5E0FkQcEaSRShdLFeur4Rylpta9SSck2senrNBPG/eJCNuTO3kITUmcbg1jhzbKzBqljP7 /KtdVGylu7Lc5pOYEA5CP37KiNtfTrZVUb08E6VTKet3kp/aka/SieGhoOeguvIvRUgZFHTM+s6j +7LbDTjWW7UgCUPg3fctcSv7YMsyFSrtr9erWfcSmFXMn3bxsVchF20i5qhekoRV38uOLwl8gNjn NKeDvl1Kk9io6aMGtkfRNNOrq3+Qmu9BGYvCwMYwn+bOEy0t+Xs8Kai2hnzjcTY8NPYxiLYRqUPh REqc8L9chWj73g1fJ1qkcwIYibytwsMGAHUIKjURIgjZMX4bOB3ZwFIWqIQWtaZXN9HrYwYCPeS4 WNjgyXV0TVch4PP8RfEOcGdO7aDYHj5ms13G++TqOn646q2PJ7e5yLroq21ra3NQs5GMVNkIoPIZ 8ZQJN/b9LEyuYgLQvoGD+/GeAV5aqArA/GfFDYn7eimuxjijZrj32sz+69EdpA6Oel14pkNLW5yM av9xYHQifsqCF5MUKGXBZb+qVMKn9uZczyKM4B8QnWNxtqdaGMid6Wc7kHrGZL7OijvMGXw1gZbW 0+VDyMu0t48RQI+6K0JvQwL8gSAtzH1LIs1mL0eB22Rtt5XITYJZdel29eDwNeA+i8gaY4JSNVmm CT2WXgUUzn804OdKgixBo6m3eaC6OOEQTw1BnOj6F5Q831pHoeR1AjwkKCvUJdfMQIZGOVNFQgc5 9vraiMarG1BqbSaO5ES+4bf6f1flPQSeGqOLWsHfNmtnvlQYMg5AdFrANArk7nisVEpIKhYWIc8j 12CCa1KrHlCBOdOeRHwsR6bGzQopHxsSweZzqD8aHq9mZ+kULPE1Gsa07jQvNLrOuK2d+008aRmE n7Vr5xvRVeAcUEweSGPI6BBFGTJjMQ0eG8kCZ3nbuA+LLgjh/L1l50h/ubO8sR5nVODBYE6dDNSA 0u+xyh+fvuj+mmlE9qPht9EL3FX75XSCVGghPPAyWXyRzotNWWrrxrIpNufZE/HUlDRVsyrQFW3x J0umuZKxSw4eNhtE1Ak4cojMutlFoNByoF8U64yjntwo8s6XJGlJ08NfTbrQV1D27jqjXD4ebNTG w6O2zBH2Zgd1WEZJIorzR0P0m0mHjpGOk+k2tpo8UHC3ZWI8boNwSwvzNjoC9aLJ/EfSc6+fDO14 EZOC0SxHe0DUlQFex75JVSgaCBecxkxXDbD/rmv6gYABV3lfP8GvyQSADAo/lG/jZo8yogbDPNvo 48r14Vm5L0Vl1XvhipvjJSyHt0O8TfUVq+0WYYgXnI5y7QEccGGm73Y2Hv4jRujAvwnTOEXoQDpn +oEDDcWXgOaDIv/xBGgN5woH9lz+LI6VoeEAJtp+JIxVftcvJAawdtvF9bN9ywDm4Q8nBZxY/aSv n0aB5eAWp1q1BacIX5KRJU4gkCMrp/RDGlw3JPLsqTo1aPX/Ij/2LVe5SFKgKti4XIiG1kvod74o jLuEaH3LCyoOz4tNpPdB+2nUjBzVJKbgSt8vU5LmjZQNdD6pTxbnL+p5rZjSXC8Em2sK2IPUsRsd c1BcgMkCiuINDD9aVWumHgcQnbgpHCL7JUSKJpXWUBzOSDAkGdXB9j6py9ILm1yhLUfMyCNLpt+2 3iNCdznb3r1v9c6n1Q7bjil1fVPB24ao5k4l3VuSoE5nYE9C/6LxLpCqkH22km+NlFpaO4nDL2OF hOJmW81rpueC0VhYIR34cPzZXwttULDEd7pS/pf4VjoeKla4PzDMZTQ/lkO32hQh1cP1x88p5N1T zbFrq/JyS5h7TgOGKG0N/wAhU1zfsrwR0RoyReGINSm9MO52iy3Rg5p1Dpq5h8iz4/Lk4EGG5CPB N+M7TL+/ZWB1JLP9eeLCxQSmtQrUaPhPv4zc3JOxaYnnV8r5/8rK9N7OMqlzT0dAkRT5LKMX5cPJ ctHhzHJ4MWzeFVLy3hVVBVt8RhLczSdbFvZpU59/0648w66hTfDNA2ElXMkZfe64AyWfpQoebggZ szXw6wt6DAMfzWGvRRUccQ/Bgli/j+P8xXFTymCUbuOqwwQV0ogO6s05vqPh/hPe3rLvMeOg3qwH ezAuXygarUmZjiY4fjCr1qwZSmFpIDSTaY8IO0qUlOrV6NSXZwdkKqvVYKQbksCO/PA+xNLcUkgF z9KJaVjXUtGluXCESXVX6DZino9Ful/RwCz2uLi0VnB0CXwrgN/dJcj43Grlbb0xaBunXrWdzs0f ZWbphK9tzjF6rUMfyXKx5S6PUcXtr4lZMrhXfmDDqmK0LaYCgVQCCzUIeOrNBgzWrzSs82XHTxN+ WQnnMpKB7keAD1kFS/LMlFDA2UJ4VS1Axf31+42MsxKjWpQtjCUFMYfMWZWdKkZ+CrivtuZOqHoQ 5w4UtfG7YxfJvD33KoT33oTDr7gaiCArIungu/uwj1QcJQ5t2x+WwikCuJOWI/iK+2JtkjpWSsgd PluySYXYR5xq0NhA2HTH8goYpLPXIPQuBfhLAPDnKxZWFBS3Y56Prv0QiGaTldWCVyfitYqqqJlO uXLlpgsmJkNGWi88XWrQSvcviKA4Wqypx4Vu098mX1ilyV5IwH+2mpCqhHVW6fz20DXjnFX79xXy bZA7PsEtiE0qeGm+btxUDVEt3XZYsRrFKaeDcmp1080+XDKGLlwlxaCsS6dDht+4E5miHvcIhVFy Z0R2CYLEM7fGl6Mx9K8dUt3QwzlkfUq4zwK99OqQrI6GUv5bKeQREB29Vrt1gPAfpfW43+VHeLCt gfoUUJPfBAVB0mm/9UqmEa8sA0bk3W2JnnAxocFqRk5V3jg/cNUjRI+/V8HXlDsoYTL3CzlmIjYf jpx8kx8FXNsbNqvSmklCMdTlV8xhvmForINVyUq2tMk+LhyGCIK4hKWrpxxqmw8wq5F6sph1dNtk DboewQLYGSVOiyIxB8J9NDEU2ydoOBCnJCRjaCyjMo4iQrcQ3fW3Fftzkf8WDckY5koIODEADUTX TGbwdqW+rzmgHFaga20j5Mjld75QPPESd1EG5lD4L7s2x42QwLTVjiL/AYepWDcxWt0t0+4h543l +U0zCt0mllAzPXBsW9iO/DaQrHxElZcHFu4uRopewDf7vzuSRHziJPz2qcDPriWDfligc5+bL4ET mwdkqT0nmi6k0Qj93KRxI9yL1j2fhW78G2jEbLAuaR4EjU7yFruAARO8AB8XbppTRsAxhyvW0mZk IZ6+wDExujVQc/MTbDdVgjtRyYFt3g/nkPZYFg8QQVFbvT2RaOjwdFgnIgcLBMqLWaPS3wVWY5bb yNQRu/Cse994dytGxHUvK8Sx0QAEZ/zjLSoUNRzM7NBxy8MaQSl8D0++EQAMtew5T1hGFql3vDst tPQ9qEgdqlxm0nm5s+c9GZa0KyDpBmNkUygV8/pn04wF+S4uGDqIJSiRF4GWqOg4z8j6XNQaBvfB jvvcIlsefDPOHONDWgYqEPGbY3eAoFv43oGqjEbJ69f1HMJbTRPTY6Ych1usMUgvwDeAdvnkN8w6 lhlnQLEKMq4/Z58An7MoFLGbUWXfVwvXoIaiooYla81cPFVazJq3kAAr/thicdn2i/WKDmOjiMLV Q8mfn/kQ4H2NpGiEF47ea9H62atK2Ab4/xWEqZYuZX/+BqPTXMwGUv9AS7jESi3QhSg1LuQj1V5j 7Y7b/j9Z03bbpNqY5AxGxHhMc0HvrAdA82nksrcbpedRM7+DKQVyq2JIlPoSuMRajISGVbP+NMjQ 0alES6GFxc55NRnDlHGS41rqhoCSReE1Nk1yJM+UgMe7TgZeTROUaxGs++Thdbo6Ak2f4FoO+kv9 3ZIGIEfOjDQFvNXE1oJedKc13+QvPFmURiCYiecK1kEpOyTasyYLxl05DLKx0BD/gfO3HsTs2jFK AgDa++191L8TfwZOcF8eMkLpbitZ/lULwlgHbCA6zOnMwTYlRPs+jj9MESLcjiYdXGHdc1bvIuQD fMxk5AtXEPg1J6We6+E2ugqV8UB49TTzPLpOe/xc/AYHwLqMvhBslQnp+6pI+M8b8qI7cWUGstVm NrZL7eS2i1zdTJxsrn/CMtvD+Bt0vwpq1yqoMNZg8D1HqZEd1peYlQCFFe4u8vm9Ymf1ZEtZDqyM LmUXXEcnWtZlnrKj/7IpLCjDmzr1QInnuANCbnKeERaik3XwxKWyMdONucuo2Wvbbr/ZhqgUEbzO 5IkL78L21dKqlFG3mBke6i5cOacVnYn2X/ADzBrIg/KaPCi5dOWwgTrXIIKfQgFtpw2JtWcQpouf DP/jVGnfVvYBg7KznbHgMVefzFZh/icXm2/wMW+/o+bD9lTzG1UmtxqRbTu1th8cGyosy1oxEL0L kPEdG3rVmBf6d0UFA8Y8Qa2hSVqaAIStqAt2a4Cpro7YnEPQFa2VhFM2hyE5o1/WGvnAkBMyVDZN BsF4p+ChwP4Kcn2yZRD8tLNmqEaTBt/6uW8p62JdcHzdgI9lO23HcqzCHNinyIy8FrPk8l7NQlAd i29F1ZKQZoAM85QS4nl9cRcr+sOZKoycvC0RQikNOfTB9kYTXMZ82rFT1yEw0HQtbw74laQ7M2DG CM+AR0y8TvZnINMi3rCIokSJkuBjZkYAPjs0L83txEs5NB0MLSbewvKpunD37nh/KcigwDmGDEwV nbdTcLSBafqJlERXFBKK996KkL0gWgElqjhTIEci+wsf0cMNQeBv0JvTIFkhHtZEY9OmEuHCzkVj 5fbURZ6vvdCpNflqHPm1B+6lO5bTfP4vAnnd7BvZQOYdKRAJeQHR7a4XRSWyjKVglo5ewOgMYXsJ GyFFw/I6AL9HKfnC0pp9mLDyRb6XYoQbp9U8zuoqcL5IJXyKzfgSlHOlEkSSY4T7iGqug77dxBFS FPmKveZWQViS+gFJ117agKSyl+R79qaLgjZcBusvS7x3r14+MOO/omBWWUJbYUyDVd+CuGxFG4W1 EC/bM6xNAsfC1di/XHxxNJkMZaAWH5XUmf7LvzY0VJ/YHhFUVgsDpnLFalGPUvbrJaT0MRtWnO2X qniP3CG3YK/SZGbqLpUO6dROWbs0jjdSvSbcav9vLV+1ni11WPoUO4Kh0aK11WeWlPDynjbU3eWj QkV/NoGl8hKtzcslZc/xZc1a0BttLJVFOPxOJfXGuV+TmdcR9CUBZ+Xu+FcfM9YmNBHMYpDfdQeb iciz1/TEIgsyGFfINmgEbYT3MLSHpGdYRqVIXmRkm9sKzCtmodXXdLXmw0P8Rw842Whap8PeReBY X8JQB8OuQYVjzQIon+Dn4jZj1ZXTn7cKJxZa/rXNt3BfLfBwSZ+V1xMNGZJGubjguIVDpDyqxWYR MoFUxfQhnlwMZOaY/01vpnRpfH0whCvIy12ERLgh0wLldI88d6ZhC02Gh75o7yKQYn9WEl1iQpaL m5EW16tCtAbD35DiPxYkeEnWvbNu3FHKiAnp5SQ+tRa+oL6qAQQuUb81sUkZEfn5VNiUQ1XqHQvY 2XZcasSDuBNsnq27Bw7S9DgkscU/3oJSODQthGL/4ARpIYfuuYcvEveiytOrHSAitKtCyMtmJhYD baP4btFH/THuS8WG5fNNftOd7hhl1ChoHIs61IAxKjE0JStHgpRE/X/nWbeHozcG7SnhbhAkh95b V5hNic7sOM2WkCxI5ro/KIAKkuDoh8vvYURSJ/os75pI9/V86zYdc76gbe+NgWfnS5nDQMZ7M1ze 1JYiq8k4LKMcKhuisFl2liuss3p2ASPOXPKdBxd8eaHUa4ldjATJvHqpIn/hGzU8mtCLDdMZ7x/G f0hcAZr07QTvlXF3rAC1rgDyTYQ0HfnufSHX2Zi/petXEaInHiGKceOdw2+2jRqVHW1ZoluGsHBm IjRhGWY69R1pjS3xBHo0pQNrQi06aer5iWTdSxH+rRUBMnNjQMz3t9TdUHdSAGotCHBSVcOUJV8G 4qb3DZ3RlPC9USHJobus4DtLEmhCR8zFWjJjiNrCyBcemHU+krQ+cX5P1o63IFfMKBCHYI6ghCCz W00T44KX1OBbnVyiUmZ2glnpwmoVbVcoOPaY3HBW9bJFUeqrBs1w8M99OQsCfZ80jhHtDh7k3Rkc BzCGABWVZDNNUYJzng6Uw1aO50s0hPbRAmAxhIsKKqSMQ0tDZPiLLyrWsYLTcX4QqEnNvCQEi/Pe TiOEndylEHBPpW0tJRs6BbHE4uYB4DKqCd5OWj3WhOVkzuNIvjrWZ2mva4bpjVaAo+KmJs3T6/nU Pna9l5xyy+cEgonJNQTVR2PHfHjBozY7UV2XdNl0bg5b4xK7E/KNyAjFVsm4xU9k+B5EEy2rpA2X uMKfcbKpWW+EXCJ2MfgLjyB6gJ8zWiyh7pL6uEQ44vPoNh7d4w5ibQfMrNyC4nKijZ8MA+sboU1/ HBDKuLxt83K6VoOyPN0gY88yxvmp2ikUBRnMBpiPzHFZh5ZD+KP9feTtWcAM7zruIvqinN/y8pVD 2WFJM7QB4x0k2tPepvkCt9yPHyZQwNlLSh463SGdMLJyPCiUYf8l7JyxxR6miCu5UKSqDAtnbNkB JRu969wZIrb0EY/ELhdFVmiZk7v6zqB5xYz3XbXBecNSUtPtRSRzlAaFwlsdcMyvbHMXqKtMNSFM RSVn1kZQmuHuI0IZXbnFwvziybnd8tsTsOPcB5k3yx3+/ph2C+QwU0bSLJanceHN8DCyAEOSCMm9 QVzQgb3lgmO2AQoCzf+2l3dRMZOPVrZ5oYskSmpyBl9W4B2kJ6T6vmsp7792ZwUaU71z1iwuYNGZ HOeZRtAAN3Syd9HFXUAMJXjBWL3eie4OHtQMCvWpMpKO07naRfYdKCaUD/N4ScCFPwmFNfkCsZVA 0rtpITnjYH3FIcQDK+nMBO4IzAvtcD75xZu8W5Lo/g839Pfbvxx7nQa6jqgJRgo0LIHi2DvziwVU qdk19sxA643xAB6dxrS3UYLnudGHOVRNhepxWEe8hA+MV9tDmG3auPLShxfREemVknPozfODfp3j DobELm2qKLdlcwL/JNDaDlia2QjSWBZ2HhLZsmWXA3aXYZS0mV3O+gjUIPdXCDNsUXujZNA3XfnX PPCIs4JKN5ft7qHHkmzNgGTX0AWcQVD9tKIraJNpDASl/6Vz1zsd/0lmh9+RZEsin/Mvojt2QaoN Rfi7114c/05b3a2l/yvLKl8QugU01au+pqzrM2yvjOjpoQ98hfKG3ger4W3yKVLaFA8sBgSOQU25 sFkklba/OiVKF55VKeW8yVbfz8zJrZFUEWHuvF6/JettV2Aowm1NLOlChAIWB+sP5vKH2CwpuWO1 H3mzE5QdZfHkqdHyrptqI7KXyL6vr/eIfFZprXqC6h+LXd3RbNzOAdl1NimDBwNdMjmZeFmzqfwM ylWgXWOFOqyoiWAPDI/A3b1UGKERkrdr4Ikn06ttkuZNrv2sYzZQptzJUD7oZ/k1ISpACzxvLfTN 84ZkTFppUJxJm/lnroQuMXnlUAtMy/ta4UP8FIOvCyeGIqqGk08VWqxjCoCxtgDWOc6BmriC+b4W s0a3byjdnw8RszfHiecVDblQfnoOkJjXvS6FWl3ra2aPzD2QRpU7M6N+ew9nH882ncgKAkIyG+/g cGlh0M7iNndOT/ZgGE8I7QIppTSia5eEC9ULbUzQjiiDcQ1nf6cXQUrxH3liBZrqf58IH3nZhL3S IJDNCIfhCtQL+CETwGQd21X09uApI8GTJdO+OepcCk/OAOJ1fFhUkT6R4CoA5I7Xp0AgAkfNs3p/ 2q7zTwwEPMXrmJmQ8N+KqrGM2nKj4i5f+UyUvBfM2oCn7XF7uhQTKGIfelQqAa1xsPfZS9EORtTf iF202D3XF8EtjANrig38v0ZF4X5ti6Emsxfn04TsG4oKANga10huYC+U6us+L5fzgqPjbn+eNObK 4kXsdSoY2qA6V6SpcPAeZyK2Q3/3GPVwjz/8lSR8nUJouIuaIRVyrULny/GLtA2nSRp1rfnd6o0S TvNU1EdTQ5c1Ugxy7fO7d2i5rG4v3aq0R8Px63w0hINQ3+FjRx/VGlc51WEw/9XLcLpyhVGPULPZ 3JigpEeUwS7RMZMIKPx4d5eLN3IcCUMlzr0HaxbR7OV77r0ZINg67/S6R5A5QKp1b8ShBmAjJeca KMx9tOlz4XRnnvz1aNK/VoLny61tC08+gdSh4mICpNe0tAvK02Kh0N9KAqnjiXBikaxn+bMMbqoJ +GSq5c69cVfCuRpnNRuUCBwx3524l/Zzc7tdz0R9LeqOy8TJgKDAecatH1sFWLiagAHECFqBd0Ti pld+ck8g9xXJ79kOX0Rf8LB1qMI15GPy7iTL7kq9r7jHJmfcVrlkwY1ueQOjlWsxWvE8y1WW0HxG OM5QTPsUeWTxHsGaL+ZFP6ZzGOop6ezYohqDn4szLhKcrcswJQaCZxUlq6Rz7CY9LObuGz7W7zw0 D8FTxm25FwX0z56KJdDzREbgKy3FDBHxoeX2KyNgRs9UiyBf6SNTTIbw85pX7r2YnAQWhK1PL5DQ lHMJZwe2qYWBCz3vyhkW5XtkZKq8gP/1Xkfl7Yo7PJ9vYcvPsYfHhKO4QllKzdEB5ie1G9tp2aOS Rq1XDGW4FbaTX+3rWDd6Eq0HqOVoGn7YiTtIi2S1iwAF04noPn9KwcqSfjFcBV0MwqTqmnXyOucd j/5cgrSMv1qFYI0oMdOhrSdYCDdUaalL34q4/ZUJqXZinq5Hlha9yibYBZoY+sVdQ4fPhgyXaM5K vp4pNhrzHIgvpcLTSsFjQHr5z9b783TK/e/z1ttXFT1STxKGTiGjWnyOy4GtFxLhgArFO23D5Sky 1mlMG5xI0u65Hs0b/eWrYf8OS/H5f1xg0P1AxzRd+zC7zVIKd0jZxqPswvW4PlHgWbOuNFcWRJOn wjqwMyy7slyu43T0M1GdO44A9qSlu18RKTkdSXKmcrffwO9htLrwQ7hYQpxeK3T+1waMFt0mZuRy Gq66+P6QnozoX6PteD5LCOlQ4ltLPEtCqL1nJX8tdUGePISc8qBaON81VSvIsEHueb8zuVFMwKcH CPTCaMO7cPOw+SVPUd9vGxhBPFQgcsbN/GeHqpH9qJL78g8TUhmXzinKlrkFuMpA8GeT80tmV0xG ejbdE6dEKwY44loVcZK/SARqgs3zqhZcTYfgSD4fz+Ht4UYtw8ILGzk7cKgeZBp/+9MiRjYHK3Nc x+JmYDvj/A64RMJVSvnEV4XyjOxAMGqtVeh29CKfjYt69smIwmnq+nl41wB8GxgC3/iiRZ6Y0l9B bBhOWfSlJaK/nUw6hMUPocio03nF9/sEifOnoWNiLR+xn/EmQeRgQMuPkH4B70vXhYbIB4jd2H1c BNJKYg3zk+R9dgjfGvTUWkR80zOOyHEaN/MjaDv83Yn4+c1higA2+nwlp33eOoKSciU3YcWBzRxo H4H7CfoOpAxnyizOPCjIL7jyCMLuQBGMJXsxitKi8LEVb7G1ej64kL1SkVYyfb4Zg+TieH8Mdr6Q eSZ5OB00RMxJPW0SdD1bytxze/jZ1bCzAHOhp3ESedlaLTE/Pwcs5xjybgYRheHJJp/X7mMl/V+w hw9Gxauzud5XHNRQVBfX1AueclSbZWcL/h5w2Ybl+ZUtO7QsW+wjCrGstWH2uRejwhmokWsBlM1j GarLUmS1ngUgtfRH8dicbdhR0GZrSNZHfNS53zJYggt5Kj7pwuw8HzM2+jPwMBxDVC74tGlDh9bX CePyF2gCrepXOfbZOYFLPl47cDn59AW3Jfm3vjrG5qZ6A0ONS0pZTYQbL3lAIiAgRPYlao0gpc55 bRgjOHSpkiELxW51qQsdd5Hf7W8yG0ub1NJFy0Lt2Sknwbf5WdDwbHCRilScQEJmYRGGwUEqR7Bx Suds/JlHVK1kyHyHwHrZGT8GWphJq/JwbMayqgH7qC9QC6PthKBfzgatipfH37Nve7bOmC2OuoTD 1fWaTQPpe+Wda4NCLKDHhoT1cUxH5cCePCr54+Hagu3fkf+AAW6PQfSvp0JUH0d5o0FH4V1vgOb8 SKvmQ/910ITon94CrezMZMjVYvOpI3IApjSB3bY6hEtIqBOwIaB4RmwnZLUKuK1uY1Qzj5UMkdZd A4ZY+n88PruupxZDQSdlMLhbcBs6eQgiXG4AekWw9i7sdsheafzTFDNST+H4ODcCTkeJfGNgVbAK penTChlk956rI9uIZuCbLo22H/Mf3vNuTaf3zlvsHucl7UGk/uIecdoTI1u28aVjWJHvB+RmqVhk vTeA3yn3qkLXXpbfVuRWq/fXgyQCDhWrGTtCbAJk7n61G72QUBKWy8bFw0HWtEWcrx2GXVp/FpYS vYbC9X11iF0UBqN23Jx2DxHdbWoXCF40vWhB32M52w/xXXA5q1ao8y453ayqWlsmQjmvBDvduD3c FhIXy+2iyMEDsa0ATEIPZbasRGUZO14QIY1B6wMonZ8iYfGgrPuQPUsvfX1NqvoakSPBs2FF/TeE ZmHLQ21vUvJRqRc4lcopgVA4x+QL8TJ0fFco9Jgx2YcTXGBMBai7zuegZ7KWL80nRE3tJmrn9OzH eESLlCZ2PZOIgIq9XCA4ZumrDQU1a5NcsiI+ZHwFNLYHpVRetwec7cxaia16KYbZKPNaFIClWA9Q mN5g2YR3PmDblOThmIRvwi97VVdvuSLLe7vmiJBvnwGRAMIn/0gMRPr04224bRUz32tcPUmjf7wm 2MYu6xJLhKuC0LCQXpint4J6UY7IMHaPM1DOMlCHUF9Hk8Eg5W9YyRAddm0tDQtmczh3bARyY+v6 rl8odUEQhYag+7jIp90+4+C00qWTMsJXntqqUhs3ejX7xYqqWYEapa7aBQICPvpbMjDfzVwmaAT2 vb3MIVq5AN94LY5aYgJyZfFSBtBuwd5tBhBE+KSgKXEmx91zeQ0WaG1vDFasi6XyuMjMbQUqxKEV SKf5U/W/CyLTS2KRuPrw2EKvmnDyqNeGe8nCKboU+RPHPe8uqK5SmG+lafl/DaimSJZ3UCEgiWCC vu5HO+GGMnPqJDDhVlgC6+y+SG9pfDu7RTQxwTZAFlhUEsA/uNLdQcxv7iuuG67rxdlTuXGcJnFq QE45QS0XYCCBmDepe3NIPiUD9P5vNiKTXCmQkZYh/Al0m5s2XXDLLLhnGCGT0OZvQ1Mj6LQpzPVQ VexKVDDqeaYM4TtAnqYm92e+BY/vxKHjm0ARkcjT02c1stLvzYLnztTdnKeq3f28BV8ZeUKjylZV /U67LeON5Ts2aX5euaUCbAWci85ajmIGASVd7sGocELnQ4yQ4+yd8iZAiC6hAbP73kvfQJYlGapY zOyCKVcjC+Y/2ARbMw2t3iNtE0jwrI/JIWse2bqMubOukS/CaUTlpKFlNaXLYryOqZUzz6BHT5sq r19yzUXtgDXdSlODC2XT4lB7WksE1UHMbrqSV/IOPl7DAXKvc8/bjjROXmfVwq4KuPbGKVpqttlq V0GfUweTaWlKrHQFeCl5nbOlBj4qnRNfKynAaC5oV0qSXb1KFQX9Fz9Xvw8omk4WSpGyQVpPdQbP +i/hRbr2gcZBpMag8bXQHFMq0e0i8ggP8a3sXCQ2SXGvofHn4lBrrV2dYSWAFqxvvcCTbuWQDONW kMcQ+9HDeCcceZjZj+CyBzz5DDhVJTjxOyEa7ThjRF+psoHDDYPruJl5+FXh7AY3Nv7JhENc85eg dnbgds4dc09Q+L4VhMAm9idzV9BDfkW5tgqtYHjPxhLNeB0043BN1sFEZ6BodmS7aMy6UvMDLe0M PpQNkIzMmxvrb0zYpe1LHKOc4UFueB/gWuwGbN9WEWqscObMhVFaNUkk+bvAM/1FqN606K+RbAPD 0IJDmw5Gmz9p1E9V8zyUQfwhwz1JUp9gd/WHDqeg+STlRR7ftL6xCBCMFYGR+mWhQqQyFvrDAnnh iZEwX7XkZEHjWapqdlSKY/uK0fNZ7HWByOfMQNjBvTCoOuTO1uavvluXgkdjziH4g4Xl2p0UlDVx 3w6Z2AmrHjIgSPaKDfRH1TSW57zC7dAhX2Sp/tmyAPCzjmJ8QMsfjhX6u8X/CoWNfRmyNE6GXcrZ YTx23yEyWyRIMXb8Ihd4pFN8sfuNDaqH5pSzmCytpTK8th87s/3o036KgKu3glDdKroEJk5eT+tw Cph+pSH5snQY3RDCLlXaiOOOJdXGKYDZ7LXm5Jf8kUCM+foZ9xEzzfJgrA3rt5BjjV5ImkKZLaiT 1cgvAxyWjsLM20vW9VbACfKLm7gw0fgzT8KdmW77bETaLR5TIwCDpgfDixIES0rUtLQ+Z2xtou+s 7BKreTNpEba0bhNARAGFgkL5u82VZT29wVY7trf4khrfiXSjB9xwFgXeadH6GD78Mt5/aR35Zntr Ck+J6GefCymKO4tPAXo5Pc2aYMVQbSkk9B7TR57TDxr0srfA7jWbNHaElcdidZnWzCF2hfFrZU+M 6l/6bFBLTifZ8sJJo+vDAlH6B6xp4PsGB38OMJa3cUB56ggdX6fY4cviyhS1dpjoS6KFW+obA9oa +RQ36jY7Z7aIM9l3kJw6y8IDptKZQE9rxQou+f2tzRCE0RnLgf1zLB38VybKF+Biz7Q/V904G499 FyPyjHSdUo3PWNdWvQxjckJ91zDGdeu6WGHZ14RWwios8DT3K54Gcc8bFL3y78Fcl9Iuw1YTYfgy 17PLtYgNwrxzogjLiWkeWnXvei5baffZskPSCRLdRsHbgwsi+jHxM9wTX9najb5L0RrNwp+W9Sae HoLstGc+4t7MYhra8mJ4qM//JgJNGZaZL0/Jjto0wzbCXjFCvCWJcQWUvhq3pMWSCZiRYtqG9SyT ejsvERyBu/hFFZcM4H3YraSqGvXUww8B5SKJBVdPRecmCMi5E8RIrJfimo6stc3pc9PY5aIUEAJM G8+fZSKgYovxGdByFSNdCjgX/oWzNCMpFCEEEM1JTVQlB2bets8SIusnxMwPDcT4v1DpCxduGBmC kVidrS6h17ie8pjIep+32eKm8cdnFuxYEpCVoAwDS5J2Hy4JMfxkbdRj488oZ25/kbjxRkseMJ5V glsV3/CNb1vy3XqNtbPOIMZN7CG5BoZdz1wBuK29vRvCQoltmoiJHd8M76iWYWpR2M4xYMxsf6AD aY0K9ULot2F0zpRf7+N+LkV5/926NZVOahKFNiyw+x8yKxBtwHzRmqkNr/pEo0BqwA6yNEtZNLuf 38M6TEIaAZvX2Exj8I8GuoT+iAzqvv5hJbYgWiZFuILlcnDFfvoy9EhIX3tcOCN6xgICYDveNBhW jO1iywq+t47gvnEQu2Fv7p4nRLfLAU32Y1Y4InWBqgakX9NnzQaQO7c2VoO4EeMtn5ulS1nJ/u31 nVc6AO3EqBZ199P4huZgtyzzGsbJLsDdK1IzbozgNrZnjcQd2SzzrnAStaCsBt1HgwxO6eMC3B9B qdWO4kg7jVVnAuOTJn6SyYBQmHuSzTK2Dtx9ObdSAwDSwa2MZITGmjn3TSw+vnagmNWlAUNJ4waJ MDXd+/J55ljpCwr+RqezGph0SVOOTpjAEW7hpS4ZZZ3+rBxu+1uXZzncrFwlFHSHDRGO23myAnEt QPAap2sAQMh1CGcI6tgcCW8uBy/4kRt6GghtM6yTRyl70wSd4pZciKGM4p0Cw2H0R4GJYqu3kRvx yhGOnW4z7tZoNjyQR2L5sLYrnMVYhUn242hB0NLQxm/JPCWB372JETDMETsL0Jin0xMQrvFjFEh0 2crZhNv0KZflb2wvLNM9L/IRA+FqyYIKCiyCdv//Xg3HAVeSRDrvRvp6ULbztiTNUOlCseyslOAo bFvMHoZXM2AenhiZnmZuzqVSG7FsTKk+bWj/mJvAAwaN1A88bRVquxvOvss7ey649ianP8AFG6AD ffbqDxRnQMvtMO7pkOTY8a/op+OpuLylIr8z2xBTW7+RzqXZxnCZpeC3td/YlhELalk8KFmnQJKz so99TFx9BkPwttbazlruv23/u0qrIPC2A13rTKhkUz9/m8+2QONF6IQA2lqtoBgv8T8JW/vmg6od MOaOsSMy69ESgLAmLJ5vWHbqnzJDm+0vAvALTsVpDZxRdvaV8tMAWgNPQreD4ZVrXAHwL02eH/oi 3723d6GHw+mFxBHuuZ65V6/x9GhUMFjDZiFLUGDbxzcHRX6EQg9WzJ/XsebsAoWQuQSO2GlKs70T Ed16z0CNp6RGx0BmCo97vo58MpnYW95uyWbaqAvH6A8idd3GZyAFHUjBDzXxcAJ1Y2RMETK62/K9 16vu42+4eLRpeNEiy7E8FO/wD5OqUZ+zH1vGaPNvSbsDfpR365po71JRuxz1wqGzzitHEVFbBFt9 2neOd+riwvvB++7gLFele08SePydtKfo3vtUmc+hPk6oeu5ms8/5jtHYtLRfQS0WUt4Re5m8lQ82 J+E3rCz4XYLkLEOuXC7pJAMnzCHYo5+4K0UAobVjw0mIw53+z7Fae8RZ5vt/tiQ+KKYDfz550q6q VCq9umBty9DZybi9kGA5j3NgHKY5y0PHshMyt8n6Ki1UNjYROFHWmny6ok+cuiCSsX++mAr+DAUo D11gE4suhQh7wVyCVXK0qfWarxQkerurgbUMfEtq6YLrAkglXLUXoTWb5griPm8rDjUvY7AdHkc+ 179B4cix0DFY0Mqi05UdYz+phQCdGHHXjRuRyBlmJaXn9TLwWx8hI/98RH1LmmDALrgqOMj1tFQ7 qWkpY0qNzJmPlhRRaRq+LUJMSbZ90FUdnFMKX4ZXLKRsw93FT3eyJyqLacB6fwKg4ZJ2BCwntcWL S0m6zWG3ZW+et/VByz4vco45DBzmk1sUJY3XviKL6RidyhYJk9R8nyggIaWWHKRNq9KEcXuqJeKu 0FoXZW7PwG+v6qS9nJiwzoFh2FE80SREvU7Z9yN6bZV4vj27m2CBKXU8WBzDjHD9GeP2UKTX3cqV zrRxyEMhbAOfRCkqkx2fP3YhXdUSOKVHV9cs5QeG1RPKYrxhb5qB3+ZZN/S+o3cNrTKJTE6Pcdx5 uu/sHXffqDQFWCv1DSvXM5E5WMdQBlnRuxp/DWTLpJHf07E6WpYFbW9QLlI6omw6xPVQegLKqaWv nf5rKNo8z7DCBZcESq6AqE8n2s0OZnmt848p39B8vr5HH6otilnrDFUAILSIVenHNuA57GRmEkcr bXTvzQBpd4pLpw7w5xjZ5N9bdjWYs+dfR6/oUq5z9wcAoix7uK70x7v2TQ11nKuwKHVo8A23kKum vHyepxBlciNc/4/PbIuwE7A6eYgD5eu0EB5ck921VbIsa7gbrubqlauHY/5Fz6eXecevun9b3Kie J25A2giWqjW25Qw+CpAddxP11bBy8ky/rvMSaeq4EqQfyXRMqmHL0Fkr6WWXgn3A9ME/P/gNW9Mg mib54D+QGsjLXZY3c5/Cby+Pdd8+sqyfpcUxI/gWY+iTmYcY+FfSmBGqRcYX7w9RZpvWrK5D5iby N+Qao3YghOjtKup56xzCg92gmsXG+U3yqde3cyMPznyW3JA7em47/HPGnBmmovvMOn/ZckHfhU0l agU+GAVLkPafpbjFW+osbvijcz95E8qHSJOZ/BWVK0KjHCZR1XC4LdHX/wbT13KT3EwT2VwjjP0K Ya6AQJr8fh0SP/hKsNzZefoobugbrEDUpmtP8Vprd4MTQ+JWpvtfsXwdzgAEcTljtOLEg31gYrBe q2cTPYwraXiua6rqeBAZ/pPfVKcpQcKIhr3lde+AhHM+XcHuAo50MLFpYXDYxXKhaZW4YzPOvrbH W/P8s+6EPC2NV9jZs36GwbitNquQtDUCsQr68DqpALNcJVwnZdgt8vll91wr55lhOU94oafFbI4Z 01vBslVEslQdMtPzBlUtd4gOt2YTehxcWN0jCAkx2/vhOaSRCXm/P/XgVu6PWJYlYoh6pgrua71l wK1ytnRLFA5vPmLneO/LQ7J3jt8J2AENTiBQg2xNDd9gTbuBOF8GSo1uuYuCmdqhhuWiV3ktwwwo g3UQGCWtilH5vnOoKtdrzwCLedbZppEOLmcAeUiIg4wWFtQZ7K5nPx3Zk9TV31fl6eD7ApX4ilIb YNalgxpP7GkSAobkIV3D5VsGnWWXnMTeJrX+Pq9SKC40QXsApapyIOBDPJ6+P0JMmQXsdajLq0y7 OoKZlmsPlE89hQFQuAoSC6mjEyj+TqXri3NVAp0geh4bVl3TTFq9c3MkUXo0orncu7QgkpDBSLRA Qhn3RwWKgzpFrVCe2FgY7zuEhJCPoOmXIRHCoEXcjuqXoCQbGJNQDlIWz+cYe2OPndq8bUF9ZBvw Vs7XGzIwANaoKS8UC7NYMknVjJZpJ1Min8HncXIFIdBZgW3S5lmHn0IvLOoetTByUMbhiZXRVFgw YUoaHxzhrZ6KLdVaPNeBBKpBn2i/pra9L8pAHOMGUVftd0WYbXZPf/pRjjGNulJicE5/NnRjIBHU 5I58k5D6DcTuPYK+am7vkxmCzGNmdXr9gAkGz3xIshKlzEGEAUL1xV24jpHGzctFYZpjnzA6hsky 8X/yHZjnfU6kS3yOs7zR6mGqvp5zbLTPufAK8R/K+BCkpWa+5kIllJ+dNp4xQJYc02ukFW/n1k08 DtDZISvMJ5HzmRQp9qrU5HqaIA56bOD9Em9qHZZDk2l72fxfL9Mw4H92MTJCYdVL4oLqIrx69Ecd t4dypcVYulQLVMvCH+HL3+vx00xCsvA9S1gsA/8Up7gxzosguWXXsMtAhzxXA81K9zDM0g0ertmv nl1lMYE33n4J+87IdU2PVHM9JPsD69VpiNm5KQmfzhihTXqZoNcM+APGUGYOwTJcLfZ+XZzi7fCf B7LUMyS8m/ASo6pkh+tXDjxvtxjevI0yw4gLGHdYRTUcC5rxTNmNuocpeQSf/caHLSJ4Hi/mL3ny AmNOpk7SXWnyv6HI+04Op0qzuwyNKc/l4oIPlG5yRKJPKMZKmiy+Q8xX7Eh07VjmGMLB0Mnp463P LpDk2kgXbYiqMZ4jH9mWXvHiqa922qQbXgyh/ZZ926d9u/c+1zH/MnYkbG9NW5J4ODq76xsW285b covDlBvqE1BAAJfoZg74GF/a9NJFzfjvwXN+mhG+tipIRpr44SdbbJYxQbHJtsWWSiZ3MzURR2Oq xUJ9fvLqfymubSqLdBtJYTyEKyx5Iw7Xy9XApm7poaUSE0wDVd1yk7dvGwUZBK0sXICZTU3NdOzR M57/fhGFECDS9oFQvHDenii89V896smOyqluRvW0Mms0kgNPvD/uuM28zwCDgNL6XqXlKQGv9Gtc xBDFrz/vu0P6auDheb+uDd6dJG8NwmLIngD5VPn7zAqox8ZVOtv55IFhJzpRIaLIwEnUNwkWAFpR r640Uum4+1iM4f47OcuVBYui20uAlmQYaf+oHTVPf850XqvX2n+T/IV+Qg04vZbRas6uPnLPScJL jkxyyxI2zQuj3wYxasbc9Xg2zuWeZI62MI1c/S+Bb/tz1/6UUS4eY6iM/bPubCkzX+cTc2/YDksP wC4QEzUe/2h9lD6pg1u53lYI5rSsucv3UEz0XWnVuqAgL7Nm9jOcUATofkYhQKjdekJ5fR1sg9Cs krh3N5ucYsIX3sorHUqcwH/dsQ4gtWbY27AVwLE5AdBla7D3OUc0gdmqBS0YYC9paK2cC0mnWwVm mhmV+CGHPq4HOLkDMc51/iEC3nzBMSKTcnzXLh/o51hh0fLUu9e+ehgwGrLEIOUdcXqn22n2d67B 7elJIOtTHpogLgO5Uv0M4G5WtY24iZW5oybnZmJ/jXu5dFw3EPmQw6zSFbn1J/tqGnCJuIeGr/Ew rNlgR3om3HUKdF4hPnNcuzRQn+UUGuUqjwjyg9XF0pbih3UYUK57Wlv5K9MtnIcUn33wltg54XcN ocQ14aYD44s+lzqeU7Nho7P9vdF5KA63ZUH9A/Ag37mImimtHATWZXnIDvNYvpzW0kFXEQo+OIyf A0Le3xX9MTFcNM48/PMyz/aI+9p58SzwSGkpP4hSOFfgArFdxFlWVHboJhS8ggOO6z1M9DFyPMf+ SgT5hU7l1kh1pszfBZvYmT7cmXmKtqNrOF7+RYxdyBAhx2ZZ7R7fEwAElvo13LhLb5ZeI/SKKDdm VdT/roMFcsLAKW1tFXFAlWoK0K+6BbG8M1sVOtyjSEToJfwSIMjDWvI1lG9kwJEOuRbixXnaSp2U Q2obv9dLkkWgubH0SIj0h8KcRF69aAPb6m8L0CEqTP1TYWPROQuIRjTPk/JXkNqc3YxUMQBMzHjr rpCzsrDOPtnB5wVJkrphBKjuzTs73ihYy7um1/GZEDT10N5SZjXHli8KPdToLgEPue1IrqVIRh80 uE6L7w/Nm74IwMJXEQSCgo+s+cxtE0BKbqRHYKVFrisqfvCxPQrYrcIoZwk6vWL/J5Jwm7F0KWV0 YFW/JREjIrVu5SNxNe5fjl+zFaLPtP13Fbg1pHCVFhmmYgC934gfbs666dIHUiPt2/1TxGg7m03j GMhuSoQrDaDWbGMqd1McnQcFzxE2NEAhjGvVN6tZGyZbplza3eiuphDbeSreNNuZyAqtzd1E4kED AEr09AvPfUd5tgHRkbLHnCslemxrNsWALSi7+h2hhu15y3sscsbD2wtVlratOgCB7DUWkxZHXn+Q BrD1mC8OHKjBLcERtZbmjDBszoAakxp22jna28R2l9fUVKG42XGzQRhYkNrAm+xaIo2fmpvdf17u ik37xQ1+B7UykGqqCzmcgzlDBmvxC6TqqlHT6dm00PuVRND8wLtnRZBHdgqMhtNxw4xprrHZxsoH 9mAf8fy9jeNI8NdPO/JSirbDDF6t7URejgRlCY0IIMftaJUypZA/t9ecph9QJdMveZNKVH47j72x LvzpP7L6Bzi0gjgZI7XdTimLUrXzn2Ft3gbZ/Nvw7b9nbMUFrM+p2I7GJ1nYB91AOk1+55FvAuZS w4m6dzPYZPJ4gIgLenoG0n9s/kZJxyMi6T+uhXAIe6d7T3tvRnaro7NW1GlOHSSLeQ+ayc0f0yBs MT1LWepQdbu1154j6dwKDjK4b1ijCnsxkKInc5qnfTg09MR96M2IACrgY+LsFluWCfuUWRQ6RavE 17/HDPf010wTr0CNDNyr02279uHAwdM5L3UYNZUyhnHzsIOkizG45yRutwVrKeS23uVPBXJk5Y7Z KNyLrz9Y4q+T+b90HQVldLxqoUcL0YB3M6tUlKz4kmsl6lG85SciWDldAYaFkt3CuvydDFysLEKh kvYnM2pbnqL3W4VqbxTS7l4fvhl+TK6sl0PnBFIsP4r6p31v8PlIkk+K2IyrdI1Y0LS5RZXv1WMh K4q96WThGO/ej8td2N5E/+RYvZbEq9BhXdLPer4D07lF874krLzZzhSJg04LRf4h02mMPHyZBYpv yUOROY/R/oWFPqpAp6jxw4EA5uHCOmOse7n1wlzJbzoc/TwNShQRSM/ri8rCLFK9xZnbEIoyJVln wcts7Rf3hPEk0Vnuc78js7cZfwfrdv3G22My6S+nBdf+k26WPWcyiCteiwYD322Yxvu3DrLOTxRG ovUn+pgWZ0aBKIxF4FoLppGTxi6LqCo4pB0uUskr+t2DDkucAc4o4e/aWKRYaCIp8CrTx/efXKBW lgF/GODWUFyKNkb+sjTsNDv1mCqJ6sk99qitESPzbe0BspInNlROAo8Hc14G6JKmfT1+1EiJ0snp w8k+f6mwYYvmtCI0TzfGcmNIpf20hnUnx0J0v7ml7l118CluqRt76bxwWuI5QMuDLhU5duXRtFni IA781kvvg/EIFg92s2ltjtqHj/IwUVquxSpqEo70eZ00ulwlFyWvGC3vRmzqLGSY1/2v577H4JQw eE/pIxO1ZeeiSZ3ayimjgyGFexkl4cnQjM20CCbD5txKaL702AkXGswWcD3/A4GXfEFSI9H792X4 yQYOeeR8cry3wJBNl6D5ouwNnSrRpVJa8QcpDW3l/6pful5Z1T+BGD0oHJhZFERkJ40gXQjyjCmi eYRgiYFvds0A5cq3j0E6DHr+TiOrWzlbsDje0t1Z7rC5MbtC6NSqR7DdVbK2BnaoumTrGV08WiK8 ORTVWe9JOqdKDZoZUvuhdg0mhkjQbIkmtF6zm6UMGI9Yt8wwSRph91mIT7vdf7a/GvQrOM+3lyTb EHzbHPUjGH6ZPni/bF0FqJeRh3DKenQrz8tPcQpbhtqj/IylggPVMVfkzIxsPikRYM3tGHAHo4BC 4ocA033wo2z69QCdgzc6FtQNkCRWdMvj/H1D38xes3KXNRNiB2U7ANvDNOoDtfeReyr0vPf9a9nf wXCivbrKaze1IYtreIgpZZmIdPubOJd8Tow/b0UxBekCPyeTtjw9nSTOdgpKJN4PlrWJ3XB6+goN xgcdSw/mXjSu8lz41pzm73dWCwQlDySQLC/5VhM6CM27pw7UVwaPNCQaHUTUHLnVmdm5duRtm5aO W4OP/uba91vj55WgNNlDJnZcR0pBu/Okw9lpCsUWCSLuGTeJ0aLCgYX0TVBE6vK0qAdZHj5m5QOy UrrsY7XX6p+yo157bhu8ZzDf7/bfXVZG4hCxo5anfvwdnrJRTVxvgqMoyPFE/Sy3G0sFykdkc2wj PYehDTOlwN1YTS+BA/f2Yyj0mUSTyzOwWXpIJDc/IRjvmA+lJHbXW/2Rvw8YaF4aRFcJMha/MZND 0nKNTQV5Z5TlNXf1x8OmcWeEhcNv2HXwnBTb/E7oHeSw49St533KItBmr+ZrDdvq4qyGbtrFfB3o M2njEOAoBgXpes3zXfVv3u7QrfV3ihpG06tos3D3b+czA0YXHWYU3LdL9s2N1XKDv7XCFzr98Dyp ac9ym1QH1MJv0MlU+l+sI9gfVpNZKVPr13hwz2CW5S/c7tkH3RL66XCH2dTa7B6wpcRUsiq6BNCo GrfGDMrWs09E5SXAEqvKoY/+WasZBBLP2dpa7I5bHU6SEKW8ptrv/ofGXPtXZqLaSThzkAsxjTSj 1rp5nMwSSMf45zDA38rpCFTrfZlUMLenAwdn7lKHt3QMXunRaP1AIaE5/Ef+EJvSmZafVPpm1j6+ 8EHkOGZhE31dXlnlwwcayERwDH5meJVy7gzDe9SbPKqQqlHU78MhqUugEtEiM7QjD/tCsVMBRn/m yWPnm9/zhPyO/SQhTAC262sCMKAZB0V5FbDjZHk1+W7z+lYpo5b0Uh5C/Y/rLBh82lI4lTt2jZAi vGcnYRAZD5efGmEPu8i9A1ds1IPLtVFFTRGrLjNn8iuF/Hs8GwG7Nme+lfkroF94HFu/IMnLmSPu h8a68u1qmSnCMdhu3d249TofBCTG60ZTPs+yFtAJtQHilGU02u4+tJlWYM5RTQ67sarlnycsTjdb gIjNKgmAxZuJ7l9jcX8alEUWEaGHGq2FX+MeeO+JkuBwBRPH4EBYJhc4l9RiTeCvW+41puF8aLML bjv2ylbbGGrdpm5PWxqPaTPIVpzKD1IOCTg8199BKnoBgPLFzMgFMjdA+Hs7zxv/mq5YNbRr+VOj D5h1qN454S80eujkCdJikIaeSo9J/Py1jhOWmAlIq8cxjmSWCEDK/KEPX4tFLR2zruPcACKZGdCK agp5UM1Ef/la0vVGZPOhxvpuhV+8V9gXoCvXDzTvLo9JtqQDd1x9QZ8OVouBiaS+jCT4dCweNbLU PM/2xKUgnRAl/Ze8rhlADjDXEQ2XRWXucW41PAht9IenOWMNlE0YNFOirdBH68HIDSXfsEvqXk/+ 2EpJv5ZDFZgRDJwcY2wjy9bLeAM66Oz+YzbcR2g8B0gZ89lOOeW9zIvRu3l+8GvX4tZ9W0VoUBhs Xbu6AAVyGNHlHZBGFgPmEtpfbo7hPup/3eunVMXEtNlI5zFt16w5ha6U3pu4chOsRh+UVQzJI3E3 svt0s2pErmFWfs5W1naAvx+AB+mQi48gbqYsVO51J6fV5AluAv03Ahpcy9NrHF+SvTdxjoinMaq4 5RiqtgcLZwUMYOjtNdlxbJcoOstk9uaZoLKQvMYe4tEtk2jwU6XsxljJYEXlxiuEXgbKmbA8i84L jxtumN57ShJFbqufwmbsVu4eDrcgnqTCAwTIWKJcxb5//5QVd6P8tuTplcsm7jg/SNwmhSf3HGK1 36GLXsPlltbMkAYxIKGqyuO9wmsGw3S3F27vkVQ3+q3NbrwqDWSwHcQnlm5aWYpjSOSo7E4J3Y6R n0n6aP9gJVVrSGNyRkXd+2htESEBz9VbikdzY2Prs+iJ4Oe2o0PgrY2fznvCB6RcokKHve2gh6++ NyHAubAlvIyfVMUUgl3SVzbHpLgu/vW4o0TTJxSlCMMWRXjreIHVX1djFUuaewKA4kYUdsn5j50a ZRhwVlV5ilvFG44kCIwFTcaRm0/DYpZM5lj+1R9SiHfrCZePj0QW34KigFOaIJLAKd73d0hApavO +4EbvbytUUrhVnKAl5Ptl1msiMll4IiwQay+sCnxGj8diGm+R2n/5lxvfyEQ425ITTpMCxyv6Xud eg+CUMg+1WrtSYonQPPRJ5G2c7B7RiFst/3jjm0L5janYZozIdeATZlh7xEgJvBywfPkR+EaHyzA GQuGK8nD25BgKkU9cISUXtkNlwecwDJPzalfc7b6N3kE6Yx2EALYFIlhWp60bzUZcifTffmLaU7a NLvk6PuiA/vrNbUUJbJsctOKdU8MB5J4+vO32PKFVfKaqUuNwmcDHrR8kuHV7QGrmVlzVlRfYc/6 /t+IrkPMjYCHFqLwYg26cDaO+t6YyzGKZ3vQMyHVqHo3Zp2s9lxO6nT7KTTQbDANZCrpt16Y3d5i PlQ52ka3x1Cnw16Dj+CoyKUHTbNCjvmtAR3pQia5K0a9S0l1lvB8TDEd0YNgvJxPRD+puIDV+uQJ ZtIdAKMeqJjVvaGybcQQWh+VIegWQs1V6oVWTbzLTmWlo0nwsUrxCM3yWlI9aCK2Q3ZeuoirpvCA T1CLsUw7ZtmVenfAWhHBhp4qLCVFLW9+rWczm87RLpeMcK5pap67lrf7Tp5pG7gEPFORrA04rd/y 1nN4rHaJNnk9c9oAhpuusZ1K0GYV20fMtpiXbcdPz6VelCkhOIIyYwKwu72DS1fIYjb07XdOZJxB cCD2GqLVYDFU7W1s6IRzDWgbCG5szG5AIjwyEe0kGOf5nufbbvJ7lIyqT/i6j7l4u6qWBgBullau hChim7T0xDTHQ6zp+KD+wZJE03rwQeBm5ZYzrOKuZAjrZuhH3xtsLy9CYQKzRtJJbCOLW0uXJdPm 6MVIqjRm/cb9wS3/J9Z08cYTEh6eAIQJcfZ9rzjU2HXZtL2DXeA9CZ5EXlS9007t/eUVZi5HXieA yZuQ70ITtccaxDcz9LOl6+TyWjQrK9RSVIxK/GioFzG3nlbHo/M6nm0IJeE2jK0xtaPlJFwKAYmB sasisZhTshUY3rLcc3XHs2cQeSyO1BbOkevxp34P2stNBY8H1JVAOvU8HX4SMmbkAjZOc2M7FBf5 JSxkfbu4Vzy1rJsMg0akcOLg/pTrp5pxWU3s4bUtVHTpuNZ0Q1BF4hEzpU0gsHeYx6BPX/m29xyG ff78v0RnQoJ9Pq74sVjWWjiP4w95zlCvkOV9iUFFwm3QVa/p/pMCIMcJk5QpzP5pcuYBmmhl3fLC htNsh6Ts9yVk3ziHX1lXQv+uZr8eTpx4mw+V9VHS4pLiw1S95j7ub1ik3Gbx1ciwCQ7roVadOhUm kpcvfbwMwpRaBqBcxJt0SpofnolP9Nj/Ldd3W4ywrrk1AjENIqbZ/FgBmYfMsN6PKNUu4c9rLc7H ml0NUuEefTBRFBp0r4IFFYZQaZJ5KNsPIbp8jc/zKp1uvhxWmN6aPmCq+3QXlGemXATnuHm9y9DP wRtROIQfFxT6c4A6wZgOo+8ohBm83cpw/tIPjyf4tVjOmBWSk2BW0+WDeLM+69eQnfktpm66iBg3 orwh+aNTYIzbRxTLZNX+uMOPuP1XItX7KTa3o5KJlY4kSwhuttjeTGWGp6m3vmeBevlCGxtEjS4G 1YQ82LyVYMt8BX0dxEBDqYdhKD6jvd0B37gWHviatXwMQopX5qOjzUvI5apv7zcePGtPsQsW8mEx Zkust799QgY/iwCXi0Fdfevc1KDwvKm7vS772JAUyq7Gqnuc91+Ibx8BrbTEJ417OEgORIatJbnU mZ5uBqsSS9X/9N9rjrHdTe8lh3Q/KlkZxgJKctu0NwhKH/lcecNLD33PBK5NB8a9AcI5+lF/kc8t bPKvv+z14WbMZJ9Y9cWxkkoiBYAzxdXgpcidwpiU+5pYpvZ/xzHnMPcJVx+cxZaM057Qn8zRiVkt ojRF1VHq5OQ66GhFz70N8qt0V7DBTgeYSs14KFXtiBcCyjw/cCMOIcJMSQo4YZHpIwe+bTQjR+ev Ny+rRXDa5B8GVBC7mosQKhPa/9habJCvQgg2DDoCYPd9cdIRUD3Dg/y011jMR3B0K9VWEteNpESo Bkjp96GAm0kuznhMsAzN4aM4iY7hOVwN7RZZf9DQuj5lmhWLAADcAMkNl4UzJfq9ovjvpIuCQOpy 29Qp3U63n7FyCTRdzo5hG730acGEF5V/AtzmIzn2P2xGJAM+hDBqKxxXX2MkL5gkTYs8NySs+crv Ec6/K7LVuwdQdbaPq6PcgtYUtA+HbfpllWYfTIIbXTN+J4+tv7FzKrSpW4zn5W18trbaugznW+DL 1ONCLpIco/KEOTmK2XAQPHSmHdl0ryUVZSbcyxC9MH19mI09sIZQhQpbt7NA9OOZ5vhMii/xoK71 HBA8DoFRrHP1E0FaGIyYD35Yp8jE8RCi09IReLYwyEiTU91vABsnPGKKl67zskaRSVQNmZGsn/5U Hasi69XXBb66EK1yWd2neyoMZ/N8G1T8M8Ct5JmiXfR5d1db+hkr4m4gzXKsEayOJzpSKJkWKNna fOR/pwmN86rvMIDNICX4mUf8d9CUowEZX49BasGmFwFgf1MWI7UWq0RAIQgDUHlnd7MUnCAKTfms +j1zekEphFGn2MZnIvpMo6uZyUkeZZmLLyB6aCPZfIJ5KxvwUDO3nL6QKEgFjnhmRYL2rdGMjWek JduvHvun0YjN0WZFKp3mOQlfKQDDm2SIrfeiRRRGVTLPYyj0NWmVi0mcdWKpQ5dCGtrznx/fb938 XTk8GxcNYyK7tFV7CXJgRK9E7DoY07D8TOEfZeR8sZ2JMurUoSHYBZv0u4SupjwaMgMBDSqHh7ov urqXWbnDbGpLrlxVOi0FudQ0x8Gq29trjOWxZLELn6kRrTGWf2Gu+mNv9q1MF4rQbpCqBHi1OYsS jXH+jPFK5u1X+nlspAtwBz4UhaJFmYYLS+CzSqAkxvrFJxNS1vKEbfR3Wh88imIqPc2eSQOeBjbt gfic+9PWQM8G5bT2rKdKu0TfkrgCX2IefAcJUfk3h+vgxw2nLihhDpX1WXDJaaRAKATf3DBbAcI6 Xz1zeqo4STo0MGqybk94GYQbZpta8/eBi7obg++o2/Qqtw8/RMihK1TnjFpS8ZYF2hHYFJBVzIxh Cu5hiE8AzzWGw/rUcylPxOEzW/rNkd9SEGuWYUBtSjbv0s1L72RutwZIAXssvwOVEwW4H/ta0CR8 ahKrAfub3YKmsaNCASQ7C4joUQhxxkoDEY52AlWs/LGDsibE+U+yRK1gxkTsINT1gYIYqUxPZOBL ACf4sHPdY5Dg9qiDtCD8M+Pgoe/uceufesv/7+Rk/6mEWHaPRzU5IUMxcSnP41QTVw5adijzAieF DH88mfBDrYzZ2kiOIdWjhfWQVeMiczaWz+bGE65tULulQ/ZK+ZXxeQGjB3mwoytCVt/mjW8meIU7 uxLeSAlyCIUNhgin6cMTJHv6o/H6acRaJy6x1dKPeUpLRtWrB3rbOkLpldR3VU/4mKMYQ8ww37zp //GCiLV3UaXl1GqS9uTpm84dzjlDtDvHxXlEoEydfvft9CSNRWzNsGBFrU+pXwm3ppVnvrd/+Pcz /AG6YikaXbPKDeoitdNwIVsuwY4UxmFohkycahlk84UzwHiXUmbzUZBwtNUR+S7Uk0V/FHxpNVNL 8kSuLbmc8+QSgJXKtclS7GxHlEkQi9AL0DNrR12tjn+f+bDBDEAfdWj9M9e/Z7QNk5FRICtqigvg 9E09CiCyN29L2cYR7l8B/Hay+vjeyQ4kGNq1lWyC9WlpSteYBP9yprFF3v1gAULlF4pXIcsAcGzU TILYIAGYPxtFPNPnCAD8nGIaWX09PbZJK9faEgREaX9xiNtmvHwc+RbcC2Q6UOnx3MaL3r2FTjej 0UlyiAyfiY2S7tw120fiBha5vkX4wyH5bJ1w016HOg4ylltstrwUVfVs3WpmH53thlp4uKz1SOYD Lg93ctNkrrinii4LHyaWpz9HaWc85OjOV8NPegSX7jQnitP273WQFX96nvCbAraJJqBXsnC5MW9D ZJ95vaMi3/Go/076usfQQ1OOTB+E3W3FzUqJXk5k55rL2kcSSvqXHvNYimVXnW1AKDRV6/r9appS izKOEwFp5mKN9sQwYqpCcnCdOH8GHMdypegKWM6x4RawdNIsXjjCDaPbgF+Nvu/qtFpHk+yQIG/E BpfbrOW+tN5r17gt3biI2MZNfoHQXHMXaU+M4fE++WD0FnCWGMWFezBr0av1aixuc0cTlQR1ckmM 13+SaVqj/9ADGA9/33s9PtkwA76o9cKEPQHpcha8NOARYznMvA44N+rAk2j9EuFlHDDNaXK/cyoz O5gfXWlHHfR6zRM4KTWrQ1a55u7wuIO+Ed3zwWEW95r23nTQBGgCsZFBOK/IZZrbdBm9XF94W+60 LinK375Uy5V6UggcDJRnt8WyuTtbHjoN3ktvqVVXvWeY18m1LDzX9qQQaQ+Gz+jelPrVOzxs1E9C cix5Y1s8LLFJJe+pPEiKkuK6+kMjB2W/KmcKynzVijlAPTksV3JX2ZBpGyadsjHWqYBIloPs+eRB eInlbZoNG6tdWbzmFcyGLf5OEQMgZ03MfUPRK+VNhu7L+RQuElwdENGCUVEUV+HnqSOK7CjB2IC4 JzXtXIIuT+OfdWmVhgsl80krtxzHOLtOAJKUvCFIEAO+DNrfmLJvB6FCB26HzDg4QIADLhiRRKR+ NGR2aZiEGqpBz9tbCCUDR3dLqHxmWhdIyEA9ZDeWDRf9RJYAuZVuLkq4J5yJoHRyDb8O4dpmo6vX fstHtHMfFaNZdOE/2YQXddFzS7vLBUB0xaQNdiXZ2yZm9hPW+4HqLp6I8tajBixNRXrIof1TpN3Z TY2HoHMwMBQSAC4LuBvMlXCPbQm+Mrs9Ib5f8uh94qsscKPR33rkokPmw1MJ97vOV5WkWtXFShgj Q9eFegHrCFpyICmmEPzVX2RiCNqjiuL0kkNmrqNYhXNIpVNWfi4h7V+E21Iz64F6al7Br+I/PeUv V9VZKqaoLKNOmBw/zVQq8me5JemMga23wrKq8dd9IlkZv2JSMXzndl7ldZs+xAI9HvNljQui4cUp HpZip5uqou9sxUxBhwtvhHQE4n4U56i4BgSLtYWfTTtz3NbIJyPQcoogQqSwfiAnhAD1igGpr+7c VNTfsAGxgTdYmDl/Df54UfZQ8zMa4nCBPHZWesaK0NZ4/uWzBSADhy9FizIFU6FPGHbfOGNfm9Mw WeJIly6ehFbB+WGXM3bhX9Twk2GnmQm7u4d+P6k8YP/SUEjTmsb0qwMypt7G4Dq0wCF9llH5DMFN B63SN2ciejHj71U/JWkyRqu00aBqoMtQZCsOgGT/R6zJRNj2Da7VsYGQxzWPfQyk5c2qWQtNYVMg uPzeqz4UxU2IJf3QyoZyYML6EkPQ+LmwF9P+S2L0FXD5QW5G/HCgSBnvLTJY469q7bvHSylluPyr fmLikug1H6o7m+0Tqvxj5WlBNkBt1IEClmOXcR5nChtPPLdEuphIW7XNi470B19rBfb38pVlxlyL 8SnO7kdhnvI/5hWag/zcLwclwcfl7ILrx6CTpab8xwfu6pYVSIvzFa2nAcTEb/J02uBdsUBUGNkV b+aEPpbO2m84SKKOh8ZuqF9q6JgeiZEAE1w9Z5KkvpZxoLrgC2g6sE6v0Z/U0See8Tygi1LG+hjU eBtnws6NvPaflDjDE2tK0l66dM30dX7Te7Qk5CBPSscEzUUNS9bA19WX21w4EfQLJuZk8cKzw4zw yEhwrz2A2yA3bhmKcgA5zXzCeIwbcjqUkA0xFrCxh5PKtLWIVXWRNZD+3UyeX6vRlJaxahBAt1bk na8FZFayOX7v99xSUwuKtRQ1PS+9BeLcbpXZNRrNrSMF/uzKioVWETz3m+MTTHteeuREzCbswS7C ep9eqpsnvp8frFbWZtAtVvUAk6i6DQEYAvZ/naK+jvzAlLwFUxgxZ0DfOk6peUVnKWEZJVk5n+79 25M+WmDGs+CoRwALEVxIUIzJtcwMqjN4I0B8P+J7MX8ldqFXU101AlmQYroJvlIprJ4UohQSkE1G DTxej+eXXLWGm7koY0zaxCHm6+t7H0x5rHy1R3NAMymgm5sWhX5P34/JcOjInuJu+lQOI4Iz+4HM SOiMpXOVMf7SQh+kuh9UDRYZtu0Aaln3c490oolKVvFOY2JBhCDQzT6wweV6Fz6UeZx52J/KtkBH QUWkoneDpwZbcNuzusSgh67Kmja/GVJdvB0N62zQ7jJWwtToTkkF0n52EqwQOnNebM4K0oM5PC1D akBZQ2wY1V9c6RhvSjeG9QrXVGKe1CKs/q48YK8GZRfnd9vWSzMGklJABgwq2CVgWNbrdeTiEn06 FDWfPlKFshD8DXJ89KCyLJ8e6+r4JORkWMb1PiL80o6kVOMBuHfeAPZP0iGS9Lj+xQWARfWrGIOI O4mv/z+YoVnZzYDC0Xfrw7bK6Zzw10MZFdHvMfOOAyTlE7sqfAA5kCkQCMElYbrQ9gFqkk8JjSXd aEvzk9yOb16qbooUEXZoBe7j43VAq/bp3vcJF15u3bfzRCR9+wKtCPgl4lBEKjaZ55HDRAVrBp0f iZnSnM1LjBh+tb2Wj5++k5tRJXRytQUTa1M4+OS8v/O2OBhyT2wq+b0DoAdSwNxf4RHZW8GnNKjN cAB0/nERHQjRp5JvPKomLQyC7EWqPZAcjADdy7Lgy9QIStN4ILpFu5xV6mYZ3UVKtrJ4VD/6/D81 utn8V/d9aCmX11IeaFVbkVbZaB0WXMOFVJTOEt4HLBUfHyGPx3W6LDnGrX1k5Dl8oLdA798kuSYv RPF1Fs6Gb1Fp+AXXiqkEvMO2UwILIluUPe83mxN1wnkzaajMGekhPEoIyQAXO0dHT8DOuc9NWqs5 Rjqm+uhaS/y/epbu+tvQHQhWN0HuiPs7jARdLBhHUCPculgx3IigaUmKTku/bVMX161xlKPaOuQT GQLEVjm5hY72Kd/PD45HpQMVw8k+s8k6+iRVTB/J9E296D0YOYA7SPxypAuP+UEmI86qeHhb8Bo5 O8boTcEOnRGxRs736fPXEuqipLHlWLTX5MrLOXFR9MvC+lDaBZM+79fpF4uZaalSteeYA+9fI6Yw J8f2/hcgdHQgqI4Z/q3msj5Yqbo3dV/bfzvguEJQSU2Xfeey3XxjctuuvUgdDUYDah8gQxizUWuP b+ctTI8pMrPLlDTJhgN0fAxX+e5pEOP3w8mrh1IB+pP0MHPK53B/ULBJA9Gy9+eKSJfI61zChPWT cjRj6rcipT/DJ+b+g4KxgoA5WnQFlBfjHq38JqBxOrvOgnKvnZssb/CtyZbqe4gcEbyXCM905GqZ 17xZGH1VyIumyb5uAHIoLM+qYGy3loKj6rr5GI2CKfiVD3k86TfMKTZPSRjfOcnP/0njM74GCA00 pCyk0PqsNWt2cdFOdzJUpYFVLnGvh9L2ntOOKPe8VmO1eeWZ2/osRL0SSI8dKmZloR/tLmAOVxDY hsVWmRBEmIlg85vDGzJdFxj1o4G+taxd0oeys8uGm+mQ7Z6xYk2fknPoClUesPsDqzLa+hcc1OG8 KdtH3/Wo55c2jb0GALvC7mLwaxAiB0Cmx+e7eznR0KsZKgG+4wRjv89FiDYgAx27fNQxC9fVwiRJ /uouYjGygU2pBOImjdEwvUJdFCmLaCxpFB8qoP24UE82CTkRScKZqCvlA3lvy1A88TBFuAWurrdD YuDcAdJNj9H+Y1tFdOLtA7XscHPMLTzXRVvo8EZxogqNwA1F1cp8QspmW8JQHBiI4NbjlefMiW0k ezvw9iBCZHW6A8yhWekIhpnEK1v3BE3ewEqDKbOlw9PfRaRQWI1Usz+BEm3FvZKTXV57O+EA7JLF GThBvbkYZsgIj7dVunSeFCFZ3ebJY1HT7MsS1X9COEqmDqHx5vlI2b+ADNa/s/AcqcQjbgSys4LP Epxp+8IhP1DkYNeQ7bZ5Frqn5OeRBcOHr2H64s8S+a4Rrop6d5A83a5bz/jzJXQdY0K56jUDY6y/ bbvCuNU386cZ8l+DO3S8kH7eDNjgp/BobPZTa/OxD9JlOmO68yxDurkBWyH5OdIAsduLmvqAvxyK QbQ/+mFKCwnPJgT+fkSDTJYZq6kLT/7oYYs4+cUa9rfFZtMQTimltbgXf+1Zd2SS3IRbKBzudsDD IEeIwXlN4fgCJoZdU2gWOuZH0i8opH3uMc5sIlgsCzStg9X5P6VtN7ihClwRZWymZRSYFlG3HJ6b JTJSCmS3rS4aEY0TOH9xzGucZtpJ6Gkn7zpnHZGZ8iqgCZk5vWoB8eck3ChbmgpNManYsAcPITA2 FwFQiYpvEp1JlYDmNS+n9BHxbtoFHkek1r+qgQ3hnJeV18mHuZG4BwuMFrl1AKqK7wo/A3ZhGJOE H+NeGrjUocwKkdnf4FNG87uzTxHvd7j/tSxa4Wv0AUaIUngfqD73ONcqr5QjZ6ZOm4KFegG+dYEF j1f/I4Pzlhebintezukwy4x1JmBs1Vyn3FPxrpMZ1t8bt+TYsNBbMyzSHqPoIpafK5/j7tKoxgv5 Cppg1UaKErCb2uJivKEZLoboZ8yKv8gKqdIoP0LPDY1r+6IGhlZZQnsFeUPKO9jWlvHG+maPuyfP LII4SLEf/Bmd9hK0IwPKfpgfkzaLrWypiMIfgPqlQU9RtSqwLOHQbryELs6i/M3CPGdnVx7j8Ccl DP22zjoburXI9GaGAgh6nFkWEGkvUhJyJ2GCvMHor9OhYC0DIMUYxN3v+wrCmlu2CZzoKwlnz5vX SVPaLuKrcTI9NhUmO/aBmHC6bLzWyFSy05g6VdTvgIQHcAcTU5BIQdklEhPtJeqa0AFNjpsoDtVX xRoYtOcp18AbUVWFNb2aJZzMKw/Mc0+EdJKv0L+QBhwTqJ60bcgcoVc2TrFfemZ3raqus5kjq4ye p8waPbkDHTPaW8vPhX0WPdQlQWndYVWhzTPAH/cUfkVOB2GKEuh3i6EEFdHI8c2ZpFtKzdZxTSVj FFWjSkDZS6mvVEH3bnLfPJCiPMjqAfdX1BG+yBlUcbZ7e83YOS/FsM0W38zj+AU+Sld2Pga9HAzg HDraSXBhBaP8eEDKHFS/ygua90sEl5BvMeB/mF0y2BKmgIa1CDmpWwYR5kBT6EWclkxjY/6kYq+i jVnU/N6qLVEz5gl+2AtdmcDqMplQyFry6F8D9af3ZtRcrIaGrXXdzuAuo1cVcJDvGm+m47iXXzRH raSM/piBn2GwpUubtyJh/jkmX+l0Gx8fd3X0XlhBwaFcxlWb5eV0dK1Mu105YRxLWdXfamJWDECr wcchokLWRt9d0ticBo8Ac4OqALoSr/BNx8sHEK0ZsM5BK+BNYmHKAaKCs4ZP/HR7fAGekVe07vew P484Q9isyyqaMkhX7CSpDvccinyjwvST7TMFe0TXAUdw6sw8mJ4OwApbAD4wCtUpRXEzGz1ZtZfo ApwGStJobEm2I3qhl9H46SWf1k2HYmB5ek4xxjgsbfo4ZjhTvyRpJHTmgZMJizoeXufRnLfSuUWA JSlc2FCmtoNj7gewqEbwc24CvdChvgddEpK5/pFrY1bdX2Hh2CNgwoKosI0EiVmxdpOvrN0eh3jI cjLfgQVZ9FNElbjy20YqRpCxfI7/97DX7Bf4OvBOa4QHV+bfuPalmDcSIpQ+qLj5Bhl/kRD3m7Rd AJsJ8os2gvoCir7Fg1BkYRSzGqqnfoFCOCwdArRRvS+Qg+IufoXN+1kT/h13VZpn8fO5DKT6/XZZ j6SAbDXp95mIpm/EKZA5JoSvWYG8vTi7b/EJzBQVeFIbcXnVYOSmrt3yZ1Z2zt/4UC3KLA+7RM0X e9c6NrAAa1WUkiA8OzT2m0Ffie4gkdQKurE0s54fPEvQDJ7tBGYcQh3MxC7QEa10t2AEwC/kHaB/ qbA92uClFlcWD563z6X1HpFcPqd8RIg84jhmfE/sB5BKOi6+rqk2+L4kiwh9tYnGkz5YnynP7Ady kS4W18YXBCvzmGCDlndOPnFCxNNFDqAkrxJKFeiebNgKthPDkO3v0YS201WdFyBAiDUwWubqyi3Q BvPaKouGGVvqnDDM6fSi4dBE1IoL6MbIvLDbaUo4FhzPiy3oMXasdV7mq61CeLr6/V4Ky2lfqliY z8Ef6xvkBGSEl8mutOk4+V4ezmZBbxxr9FQpiGsFAqDQtU/+vgFvZPw1GaV5Lu2BJ/ZocyKXXErZ kzMDyZjz2MYGiiJTFp6w/JFJDt8Qd+HwxbMb9TpM3Rb9fAqqiM9UF6TASCB4QMyriToPC3dL5kp5 zZK8BehObw+hhtdHXl7idn5ELfnTteRShxaWqt4LzoeaDZuuy6nGQ5/VnxVhf48nwA9LheXgA9RL Wz2HGsvKP6YitmiQYSTBfP1BD59kdaNXs3lKcRDmr5nRNSAU+QC8LECxdu7jZsOxK+kM+FI4BN/w km6RzsK5likTQTJRthgUKxsZMWRDTdzpNt0U0Tj2qIT4/4eU9OweWYux0ftJP2e42mC/umiLZSHf Fj5K38YyCmJi2TbmtydV3Vbs0P29X5VSl+f5SCg095dRiqPyEhmVvlEWjv7SQO5mofcda0gmj//K TEQKxCB6uvbi8yKfFC8CHC5l7NAr3NeUnnPiSADscwtJ2+fO5EVObzeLzL2AFF2uuheQ2t52IQhI yhuUapeobAQejCGg6j+wReInQGzV3/dG7lfyrHkpX1d1OMoKnJ/yH3mf/LcKrAoEAsaDy2oSXVx3 xBFUW7C0VrGMpLulYBuQ2lc76yiJIK37tx78QAE4zZdwj8cfd+sy2+vvb0Do7713LBhGI7ghCcdY EZaMBbRh9MVgfMTWqJclxEFXQtAMZLUHCSymqHPgVzlwzdfv8yYsN/S0IUySZSloYi+Pg1jESXr5 kL5pkHWYABFqdjp2V+0Rd4HP3iJ9wsaHPWxfReCJib6Sljyao9i4IM1Xebd/Yu0b1o4WHH1nJBur EtpOb+lbFVNqmzsbouhI8NrGddQV7H4xZVabfStkrg42spwILyfCcF8ukTOH5Audch0QbOMeNddJ 7IjhXt98jh4o4HvghjyOttrJ4MGDXwdG3qnw8DNyiqF4O+oNRu3s58AXRouKU2DQ8m8QqykKhRWS sPrYn/rOTQlp35GX8V0+0Aoih/C4Nxc4udv0jpdxP1mkX8lVoWqr8fx5dS5HpNrnp3glb1IWJAu5 lGp0gTJ3nmP+1e6MgP42+6ELP+2HpfzuP5/dRbiSx9YFybT57LvRRyjJW0ii2OHZ2jVVHRSgrY9k DXiHiFCkNQX5FqWNnnIMfdX4+hSpGWqPzqHIePg6LT7QYVkPbMYRUiwilEXx8WlA/efqxINOJGOc 9ALeFUS4aVpWF/dqntOOC5CbSl79OH9IqeMZtDiv4tsOwjaqlQA9PBahaxG/387F39b17wILLCE4 wX9fRWPtvVHCjNoG1MQo6rp8doDQRTwvH7FknRQOlfVuz4ZysLdLxDWFSALWw05LZJIj2olNP6BM ciKdBpFw30KA0Zntfzr7XkKCARoYEvHFtXsreRl6E8+WHvt9DW21VITILBZM6EsnCJRUJ2lwobBU MV+12gLYGrv2PgdgZO1zZUquIRHZvXqlkc80TKU3kPzOAuSbw79nhCsmhISeHgvvFivMyhLPDscS S+C3avdCl3WT4ZAAVxsvrU5GQZCtBowvIlQjbT8Ti4tS5JLfP4V9BL+/6IJeuSwaeojyGk4/WOA7 jdWuH8gsbfwlXjD9cbAgVv7NsdVPxiZ7iL0QR8V6Ud+cG20OXscsfjvbp9bW7xjk3mMGTu47czP5 2xyT7WY0dMJXD8VetbAuJnmAQlDbcbFqIa5WWNLZ3UHSbXGm43pZnI22HbDfWs87Js1+1jdT/5ym VKvJcwnwqbcKQvN0H5lOv5Xghe995oq1w+1+La9RaF0JJvzojRQegRMohAFfYLR9IYOePC0yFIK2 dOAmOIIA5xOMQg3EGCxe4Yi3cj7STWPoLFExh8q7VSK3E6cNrULwKf3Q/HN2gJG5ccjT27+W4aAH nNcntY/v5TnSRqC3LnW27SNgwZWY03GjRhshtVPcGlsQGlZKfN/4FOqpWOBUNbgIKruMS+gAKSLe ebeXT5FEh7tMY3ezdJCtJpHDhDIxbGmFdzFENgfGidOaO/y31JCvMF6Jswy/nXmqHvtdGpDr6j2b QYUGP1jwS0xPGHNdymD6hhLdTbgoM+zpLk6BdeavfwKCR+fvUk5LvuS1N9YdG2eLEjqir0OB+QVp lDTBal6W32mbII2EbJxeP39knkiIZmHiPhbBgbtWHh21uLdraXXohD6DDHZedhg0Lq4QHUFqwGve AWvENM73qtKBt6XI4zPy6IB5hEhpBN8B9WKBp1Ui0G7y2WFLuUFC5Tp/df13gqnGbR51xPEmqRWO iBaSfs8DbSYVuD9MrO4ARhW+rbIMTF/o+beOdnCOD6HNbxNZcNC81JkoIOtjQBGTljQHMFZCu470 gQup3pZYgx2uJLtaCmWU7SO6TH4TFhaOpIddO1TRXmbYcvuXniOkcZn68rWD1JIvET8cawWCb8Fq D+4brwHiqosXs77yR+FJW2U7u0iBwtni4C0+HSXSqdBsxH8P6fYuxlxiksjG5nEUi5QspcIXQ7N5 HhJ784KP7C1NuM6T8AR/nZFWaNHniIg0Ip+ws3p/SFrdt2SUv/xRQyl8+u2n3yl7bkyUh2dQBWxr ldAu/2B8Q2YP0LG1idMA+tlPVbGMFIJ02XVqGzA1+024DyUBN9hfi6iJUz7zlSCq8WjLtivVFY3z HhtiC9/tzD/zdg/6f1SXWVw9/JdkhdcokWh051IpXlZ7sbDa0/j2okaSzmCFQwJRP9cO4Dl4/F7U g9qvK0GdNTSkfKO/gq1er5WzXtFQtt7DZKh/8lfIvogMGnxaZlEQZgYiPQ7rRriAndBSsJnwqWf8 jHF8WnnoTS6fw/71oRfPQlNN9zSzvFrHsRAFOP0Nfj9W/ZJM4wt8hLKuKYJJqMM6moZ7BiLYsJh4 0fDsOJWf6ver/sH4NGbkLJsBKh/lH8YbW+bitAoDAOrkGXpzRP7vEs+bvBqTZIv0fk4JPgZjXZqZ XnSz6Xui1H8htrKhpjnB+epKl7LEANcpTsuuKaxPU/Pyjqs9ruO7EXT3KnlvXyWBOdJyL+MX9UaZ T23uUfg5SplOu5Yed4PNLn31a1O5aig1RUBPPn2iB5WCejHG+2V7kz6YFOt7jOdJLu/epSWrS86E VK5GOSPmKp1xvo8MkWoZ927AOtBeqVVkFPBtKdRyVHeAfNqEPcWWsirUtgjVqDb9877VZW1tE7ov n/RtFc22cHLPxz2vE33HUxcU4w2SBtXJVvhSadot1U7MR3H/fWcYkW5K0m9hT9zLpKSnnRLthgzW xcMzphOVF6cGvJwRuQFX1AWpZjvO7Ec+u8s9bDiNfL/3+c7iUBu+PpcTuuV7blVdg5Ue5KgAa2ZI PT3o10K8eFzAp7cdZfrEF23Colr67nkrI7Z9BQxolUyEO7my1sp/8QqOZmUeKgBiEZjjeNxVUmbx J7vrfRHL+aRXk91Aqe3tTvdF5WCk4R5y2h2uDalMsJgiH9OIxOnQh8au5tqacM2wZB7DrWAN86aZ illUQQkdmjLqmJ7lx8YXdrSLIlE7UpVZOAhc/G44I4siljHSCbu7kwgPFKfJiI7bQHo2/lrF1FcT t2mUbYuuzDKEdpyDlcCQ+niXh+4V6UJUIGrQdWksa2gkpn5ObX8yTyAs8Q4F7/pa+YgaKnYGbN4U E7l0+xGy2bsGLgKZfjttMCdzvDC3s98pgOub7cniEuaiN3QxX99KeMtzjDTxdxl1Iu0RV9zLg09r +SDsfxMUEW4tcPGfQ7K1S0JVsYnY9wbNbCySjuIz3FhrUuK5guVdIwFZbdIFN5jbSAFZigP87y/n Uvsob2/Jvyv95X+FHWsflATaBxDgjO2QbT0HDsWqJRQ9Uo2XUvl92ej1ZGB7vie6lVdfM4gNjpFJ 2cNhEte3mfX7M24wt63WzfJKMgI8cnxivt+nuvyNv7ssGbc0MNKnF+OaKyEn2N+UdCmXaEZjnubL SMckRppDeeeJR2r2a8eerEnFSuiLwwDjyuyK+agKNnE3F6UC94cMdIhWfX5+QFhPuCPDWW1D761J VRjyEMBPyFQn8xwqagxCmF9JsXzebF4AxbB3fudi77W9JS6BfiaSdm9Bgj1I+Y/bky7TgQGXUX9H r3yFpwZnUDBtZEKm1sswDUAiU4t5pmGAZGlW7mkmWQ2gPB4DOPaAt5XM+6LRXf8yFU/I50MSPtoO wIWlI/KU51CBvy0mBFdE5/QHcpLCtC26wsUNCAtUtkqhJIv9rdYMTMc2xoOLBA+BKs4WNNptv9km X04rI6LCLgDw47+z7iqDM03sCfalrVh2d3r8S9Me+hlMJ17S0A0zLLOl4J/q1iJuB6uc6Cl45QyF Lo20up4Jr6AKG0cj0xocILDuefNlh7hozC0Xqlb+9QihSeqdsxDUxUgCB4VUzOZ03WLDD181yngE tlpGpk2IqbzgGEasKGs5e4/H4UlNqvbaq+S89krtt0oHW1XV5GI5l2kFQt/ziFJaT5DgjKRS9YA0 bczLljArHiaxY+W7trvBeLaO4yLkA/EOBkbWHQGgm1/IdCwQWNfg6rnMGrZsK1bjUwgjr9G5n1ao Hrqo7HQ40lk/mf1Z5z0FJ2e7PeqSiXdfBnomZoTxcwyRPFtrQdnovoJEGXF8IKsWOvshFL8Hwzx6 0EPPGbvbGh4a2EgmeY0Xx9vQsi0KVB215DtGKrLe0ZQM5Nxxr9aRPrrQADQeWuCxqE88zVpDzfRL MNIUh6t/7r6Jn5xfyCkS9AESFEaRs9KgOAgx569t8jOlmtBA9MEvHGsr6jFpoQcEElhS2Rdgcmuq fBoBatx04dUC9XsHXn7na4aQL//3FGdIgsn7gM0+r3giYxP/3LlY8Lyha1bvJzwJd7a6KdE3fm6J meFUsjp1PU3XwlN5lZAspYeVv/1nuwWa81OnTrqnrByGFW10DuqKNahKFsooOvLRs9PpKbP8blCF hKRHm4LZEX/CiFPKDa7TCd15vTnUchmJKW9H+1kmybqp7VSvxRZKqXixdyfAhXZPWNeptMToJCy7 3vBHwT9To5iFPpKq/U9gk1xM1pwhTgKxpg+GxGkmUE6LXi9yqcFjbGRV5mKZUyL6dpG0YPdmDTPt +6zJM39wQGU6KhCXFYk//xxqB9FTGF6G+5Uf9q8Jp18d4jTlznYzwd+0f3C97d8YghfGbAgM6KsG ynYBh+BzmFXtXOnemUNxQm2DB4NIFHdvjSl6wp3Jw2oq+HElDSU88a2R0/aEer4HfrTuealQWW83 Phh7iNKjjzjHgPLOMEXoE/IyPJbE291V2g5IrGzH3vxw52OuCJfF4Vwo63d0QYCf2jdKpDvHX57C IPyH7UxlvDJQ0L4c5X86AYEOQAEnjtQ2l7O/hw61eJzF4bUAkC+SmTda4CMLoC9nqjJt3Hg0ugGn qAsqMZugYVjQcMhLXU+9jpVdbpF3qmRXnsrxYnW39Tf3Dq46ZaE1hWCFe6y8ZAGwRkZ3gcTDndWE pMJbhdP7IJ3uqtyVmxl7K6ZAdDkVi6ynBrtJR6KI3zLR64mT0cQrK7VZp3Qr6DbEi15+8VSYWMPm ro/s3bXMjGz6NqQxhz3AbykCyhfkfN5ew3G/zo0HkL9fty0Rlh1sfeuW+YzhNHb0CRs7iepwmaa0 S2TltuPtdKefeUhNr3xi3Txlyrw+Pukh4GE+2tWF44xnZB7vQfX8u/xod/0Io1mO30MApfJQSvPC 9sjDI+nc3LeVta9HWjzeOpFQhR47Q+cT29RV6lmkMdwd1L9Ae7m1OBAfo1m8IjfjCgivFa2NXR3F NonOQpaFO6kLJLLPSd9d7QtJ5hU/h1m1ctK0Y04DtgMXpl+xRalpaoTUfZ/zBaDpu2i2QDPaN2iy /ucKZpm4cPw8fYZkD1KpkFJxHK5FLqyOJAkghaVqxH2fwsILfwZjqr7wlQxI9TqVefHOJ65RPEw5 n+ZKgm+L5+jOiuG1nb42C/nb6vwJdtbTEfCoDaoYu+JwMwp03IOPXQzWQ+QycwDkV5hEZYeOqZTI Cx6Ktp1MASgHxEKBfeGw/iY5+q1oJscsa0XtCg50qMGWqUnZCOq+adIE6I/hhFhzu32OZAbVt8ri +km3dtr+yhZ7RFTgpOPkKUuFc6rP6pDmawtsUwb+dQPowo5h2/FK+Wi717an0IogVvucudwyDwxJ q02P7q7+C50UMe32ujkHWWvwtXDxjeVOmDh8bh0LLwUwSURKtav0xxowtWiJPG3OmHSf1HkXUt/+ ZYCEZ7CgtW9Ut/aiTUFhz9jE830YaCqaKFnXqXA0bgg/vJy/o7xIqXrgn0U8dyiIpXLZ1BDQHdgY +rLl84gIpXk/F2oTgoZJlcL8rK3kioEbCa0nWf2GxDvrrqoMqqffLe/RWrzn0HiPlczRsbEizh/Y 5YDoI+vO1EwOugIdmH+wDqZlAcp/3K/SqbzJyV9qxPr6x7CrYvtKUSJhVYHNo5Rc5em2UDYSATJe RuRfxyx5XLSh0aG6uBAjBeIioz0YsFwDsMilqgFXVWTLTnVXj5skHsMo2JelFWccKww1bfC1ylkZ miVM/41El0pGPzxyb27KeJpry3cOm2Z+b/+TepnwVUcaqyvcG6KX5dUN8FqKGhlJpG7rINrZf43e 5ZAkSGdlPo8H8OT1hc2iryrsPHcdcK5+i/WQsmmcybvQTahJcUZVSJkip2jbiucZdMqFw30KoAVY HsCdVEBr/KDx4SOYYQCjNkujMG9mt+zYqC9yROT0Du5UJVdo+8IsUKgu4xBfWiEQQMMwLfezRnIu rF6W/uxT6WxMn/Qinszv15PzT7aDjYnKYXpVM2U+TvYc9PST3wq0RmwGzRPhYNfblBrxlDQ5yyqL 6eK6tkfC0Ms2vJVabG6mwma6E0o39/vAvHXiIXOGZ3k8LYEYGVORPKJ7S7h4jygaSSE7ZDht9UZn d1fFgBpVy6G3zDEoMraWzT0b3roT/yDRvMI7hdmilwliySTqjM5O3Jc94DUEbFee94wwQ80XOQmv EaOv4tvq7YxlY11wzCHvB2VrfrKHUUL013LiGT2aooFyrgEPh2o1aTqOV9pUdKs2heFcA9MLg11+ yCsMFOVTo1e71LlGN+NMVGE4Xpm4awe0XdQ6A893G4HlKZPvnmgxj9OA0s+/8aHGYxlrKnhtKmTI DudHvAz7fwVcAecZA2lZksAzxcEhkN6DN2g28Gatg0gpHxbo526IA9cfQKlbRPd0N9Am8E1tzBTk aika7USmI4LvZgG4P7803NNZjwvKGIsHpRduIR3J4Mo+NfiNFA81WwU7yo1GqTNR+T7ESXJuAXEy FQk7JWjaWbwk0ciRia2EfNcWz180x33hQW/SfV9Y59FERu9VqqP1eyc37+Lt0dguusrgCvrB7vNW S1TZVkUhpLlAFHa1MD1T7TUZUzpMAMt9n2snOkclq+GNkaS4+FD1tbODihw5rjuzjf0Wj36z0o3Q WnWTwMh8RUBYynEwESK2z8k2MsWCv53laHSN3auoE53+imN8NtDj5ut6c1rXr5k5tspnvE5DOlnQ M0jsC39M7Qnf2wtHHxWG21pd2oAad0jtYF0zVjvZHAazamQt9svHocA/TZW9hTDJ90EiKk9tn3cU QkScDYwvpkyNjI55xya9+e0CPqxoNdDmYALuJjuyOLPs0h/ji4K8GF71M1cZjoxkJIsjWtaOxfnt clzrNuHLCRVWyO/2yY7/SWWvUe3ASLKVxA5R/23vFC32kdl/Mz2b2Ym5cTDw1ZJ7SSFp7ul5TLd1 I/9tshiZKiITa9iKSECgGehdWXH+h/ZHX20zVMDmrpw819gsOE9JgSUv4QZEIACsbPTtcgTVGtEb OGnmOy6DnT1yMLOjuAEvRL3MNy52hetDHTyKqYx1Grgolo8kWefFcSnTTyZEC7Jo5oOfYNiCtEQb Dyh7sBmAGpc75UfsqI8zX9xMAaq9JxnMlhfj6iMd4OxkmFPW6pIQOZxFfNGK5PdjLW8GBLQkR5MT UMTVW8Izk7YzAw+Pfnvw24hyb1mpUnRJqvSaNVSLH0KAOMx8rLXz3/tUwxgGgzbksky5ur7o4dzY LGp/QH3IkSYK24kIY8DxERDiFC31eTCKqWoNDQiZYWUg9bGjO7W6GtwcNgnswB3Df2k4XkDKhFnb DWgrH/Z82i5a7U1MFzPrL0kTgEtSvpULeDZsugnp+yGktJkxcLvjyiRCwyAgiPUX1ZCBaafVB5sx w80XhLRE6IgZfBAvBQdnosxntlp5F9OESzKtu/INBD9wBn2kFbsYhu5HVcvnzfwvv+oNqrWCeEuW BIPwMVXfEVNTrQ0r/bU/wjwtf3IPYqvEEQRDCTVasbagKC2ely629r8u6HUQ8H64PdrSa6vw825u OImD97nOsKtg00UeJAR1VKja1oGbHipmUeB+oPzer0kem7nFgvZZBZDgTtRJAKin8qSL3z9PaksD KJr2mnUq2yaD0eX826ml3RyXF9oGNBdSnmUi1kH1cK366MKrGx/3XfzUbQf3cXSIBxbRJlLuTRqD GZ8XCcsjOAio2LKmOWjdkp6RIPMIbqN1LAeDBSYzJ009p2dKkd1vc231FW5sk8MOlOs0WcTS/dPS qzQA1d6UAtTIplgaInrHOTFJBGNIzewoTz1t//O0HArifxmUTaAyiBDY+QLNwF5kGCDv7C0L4sj0 dxHPTtI9zaKoy3aEIMKteFSK1nQCc23RitJ4+kRz5aLbXaLDsoDArKDtw4qJBVvO2T8SASE2zji9 FBr2mxg7SXTUQIkDFr5zpZlGtKVhT6O6Y5l3nkxx3HLMUbN0g/u6f90Q6VluR/LRBU79/jhIJZ4H KIIFIR25qnQp2A+NzDxW7yjiknDvbM+5oBENTXXEnlm5t7lgv9PMTsrBXx9CQ/QSCv0poecsfozj Ta4oUNUVxX0hs8F4OdnmjAbVFbK7OxZhbzjNF7GWZLbNz7O24lQF/WW9fl99QW8OW8otTfl9G9Tq Ur/ZokJuESela7gWLhIV5tOFEkPHu9o6SuFKpfnDPqWxKlP1eXZKSdTA0D5I0H8LCNrAZzDfUob3 +MQ8c6v+S5yT9rkWMmFHhqF4eU//k8ickewRGGSWNwnmLdyPUKyZ4G4P2x5T/aIVndzrY4SwtQ6Y +GCAprAntIXoe0xKH4FYBBYXB5/9pag36W7VX2RjWiGuFlzsHcG4LKVTZ9erW4hrF3j7jBZNPKB+ DXP8IQTzAFWs/eVKL9C6QxK7e8TdFAvSm66GLTv+q3pGya8NG6/symHqQ6s1jcdOXQ2azKqSlgmX tfm6rfojTmiCD++RUUWp8XF/2kWfH24FGZG12UicpoJ/O6jXlDi873NLdLO1HgDXC4L28cshSSxH PeFSWc8IAM/zqCZussvSAevISiIvR8W5HxDztYLhsyIMfRp3U654ZtrVaS3plilB9JhprBT4MN9/ uR+OcjtrkeYwCoCvmL3cdbovSjscTQDE9b+CwS4CosfsZUQ7QllZmZAuW/9/FgqwsC7KCKNd+jPs TRqNrrMFP0zEHOSZ+qwf1w+bC+oaiGKB3N4+tOJn1RKPyn+Z1FFq5ciEMkipwI/oE0t8WUEIVofB +WCdsv5J76jvSdsP8t556vTe5hxgwPzk6QFUkA4/Mw9+GsSLzh9N2jVxqDoKFZBpAVWO+ErtV6el xrAy14AvpSRxeH/d12vxYDDGumb/ylQ5Zyc8L7PKMusXrlLg4LR3NU381S8oF9ttUrKfOkEBgBR0 11ZnjjpuIbnxDWyv3WKBCCZppoLH6/HZrU/X314/y4bsVtgdRB6dBdG1JEAYWiMmPPfP9HTJvGXa T55qFqDTA2ud6/JAJ9cHXeP0W2he27l1a/5QcsyTwK9Mbo6+9DA0JsEY3PryQSb/SHqNH2Ya3aAC iz7orgVwA1Lhkb89uF/A7VnkebqGw2UK9ttjPbL+S0OCTCxO0az36G9oLD/Gavgfvj4MvZinpP6O cqgpH0Pcj0ExG/VlPHPsZLAuT0QWOyrrBgI63GBaECEmkOAG6Gk+U8dHFSD/WHJjhFWa2SgdJV4o VqrUnUcBUYbudAEpOwCnM4mDOeKe0DwaROGBtjXhx4PXGRkxsKGPgb64LulRLvl4b6WYhjGqfFXs 2n0UVQPU63NfKzJlRERvTB3Y5pEoyog1Z5LpUM4UB626WRzUD085VuniS9BxpBA8SoJphaLR1zPN L+X5JxnCTtwjBS21mC1mI8Jl592oJggW6VyPBY59/DguZejCJEplQZEu6AgNvE++uDeum6s77vfc eX9TgJB2rFtSNy5Vd8Lpxd9LQX4YHoj+Qa+IWgeOAwxQ4InFBNK8IYftbgCxunwMlVXT+ef+y1ne rcZ5jQQpqrwuomsrcHhRPtsXlO6R8b0rpykeyg0oo0lHr3ZgaI0oE3u/6sLQEE03PtW0L9GmxhjD BzJFVImkj+UnaYdKtAHZmyEud3COEYO20gV8AG5quVbxH6cbJELmz0c1f8awvuWGv0L8LHjyaMLB XDqMNVVkgNt3OgQLnQ4n1cfLe76umEzD6wh2rSmxo82nkArV12Q6Vw1ooBfWkd+sRWbYBrNr4h43 d+MTvZrfn8ccTIPELlJBkc/XzIgpaqBoOwzyy6ebyQe/gyS9i1UoMiJ85oxeFqJJEd2En2TQBNwr TQW40mb6lk7UjLmIdLc3ExSHOuawXwpAxJhdmpe3N/3rC96DTWy8m2f3cebillppRBmOzWw9rKJN 0ZUrNLdACZzU+eelXC8tgtM87uAq5Arhdbrh50EA1SIps1PV1ek59nAfc5t+HaG8lb0axxPQM+s5 SRT4gNQWMyJ7uxseFZEaTbYgCTlfUIQi6XZiQGNSo2VoL+Ld9s/Eq5EY0i1wnm8bxzeDh9Aw/rAQ 53Xlil7XVsVIGqLSh3Eg0DHkoBscM3wMDyjunBlBF8yaGxgzc0Tj/6opr72E/U7iuAcL7LGaXBSt kMEHHxCWOOAtn89B08TZkPpYdoTmDwLP8Sq5k7JvvtJyLAGKCqNsG+VRNYzXgBXvM7FbrCp55s1i K8EUbmk4Z0o9ssR32HTVH5htepigSi3QQ5iuIGO5ahZmWuxP7agH2/iozHj64R1BRTEZJ60GUAYi CkXJFY+GZTlM/9gVBOoXndcS5axh+Pkgxk0qP1TqQL7wrKkxBwgzPl9hNytGe/yDk+sOpuqx7Z4a BhokDfgSBrjFDaQRJUE4hT3VZUn6sxsdZHkZqYV1CrwJ06ISGPKc8ceOZCY5StYdojkU5iAdTFtY n8WdFxFolEwHrBR+XC+74JxRT1u8XSzaX/nIN0nLsz3EebMLZssljFfg+ZKrJe1FnpmEfk7ViXub HjpPvRnLL1dRsq3uMN1UU6Yj0qfVsXsq01LTvs3l4V0rVGWCzQmt7wSAU9LUIwPEhO4C1J4USi2T xx/1kkS2TQW6+RfkgO96AssD8YcIaXYjQCQei20sd3EnMyiOUy0zEUxvoPgHZ1YhfnRtvHqmmV8A 00E+5plT4/AobWWbm9QblnlpzBhn1wAvowQruRDlztzV7rdrbe+SyYd1mUPCepe8thCMy2tQDd3g PVoUF+HpjIAU8HFcMDT1x+DCeyNibgluOcoJ6qjrt+eOmMp5ZVYcpiumvc3Y6u0a1yHNVLTN8sfO ZjYKY9R8ufUWAmU/z5GewkvOZsxB9zYSOE0TwKdeg2EVCkeOPbggiXdxvx7YeItsUMWTTAaLp9WV wPxakhkB0T0vb0NZd1AZNmx8au1sOAGSw6gSf5ZLPrVSh84spcPBTWAwBRx0ksuObK69mUx9WAo1 P+4Heb3OOBEax2IJileHNPUvdVIE4ASp4zbM8pOR72dIOkcsxxwtbD5AYUskqjVDNKLHYYzzsncN Qt+SYadGHXCsoKC4jlq2eBE5kUptPuj1g/OpAPxrlHkHJ6NYEsJiWgM7AYTh0dKcUxUKOXkbZ6GD 8b0fo3qFpr+x7/ncNa0ZtvlcZYxIjIdTalNN3hnsr5zyt2OY1EyQx9RKk/DDzJ+vDQSVKAKpvZ+e ot9rV2mFBZbc3p+w4tJu97GYkiRe4saCx7e4i63QFUc9u40P0MFzC6ka2C7Qb89y9LZsBCwyXqs1 VZS61eA9Bv950Ss3Ay/ZsQS0lQK45jx0mObkeaXYh0WI9e0w381lIUwoVgAyt2gMSGT/t7T/Qc92 6LK3r0WnMayMs/wgICeEYcFPK+sFuoi2+EXkLO8eWS2lCz98JzNTFHFLegtnqHLUI/XwvlGk6MxE KIXe8SOV9OPVNe5TlWJyK+4ua1hEl9GPEAEzEyxvozLdFIbqlQ6cVAA7Oiu/3HZt7lQ+gT5OFOci apcp+v0qw/5APQs2VdRY0YH3QfYBUK/JzOQDRPzScQKXI5nk0QkmQ5/R27t38rm8mH93DDEyF+Bo 0rEVHJSIZeGAYM64RjRLkfRND+ofHc9R5yn9jQP8aJKtGUFFXRNXo0BsLaEWxVMjImnz2/T94FSI Wv6CWwMvVPVx3jCjlMUOETktdUkoc6yUABIdhEQy75r3gHF8nyE5u1t0zozoKVlLFHwwZ3L9VRm1 ZDWzDxaBNKA8u8umUhlB+1JcO3FtMGg7Kelzxy1cEVIaggcTZVfBE/M/O2pSMSuJJPfgE773UUSL zgtWpbjWGEsxgEJEc0LUBV2fKJBzbKk2TlnjBG0v1yOIfG7gqSAmFaZT3I067M3uUjxA8it0QWCs NKZkm4tYQmsy0BvfBoc7AEkvjMLKm/p57ju79pCi6JIFy28fhP00plSz99rWLypEBaeVTIfx7ufq dREiRX7G/aXjD7lLJuyLk7o9RNP95Hr3BhkE9RQ/iXJ/OHKwYqZUu+X/+NxW0HWcw8HBJwA20UoA lYsQGa2wYl8s7D60nVoC5HRK0cMdNfGabySb2CjI4CabheILFwDTyikdgTRFT60xWfdO7vslhT2Q lJ+aMSWc7sVZYlx8LY7xZ8sdPESBV+e2CeAMVk6omrq69S5+40F0i0VdCgVcQkmBjtG7OvIpx3cr t8al7eE0ZgVzXh8cCmyanIo7XrfDOomdH+NUN7L4UY8FTDJJirtG/HJcRfDt3RQL51U9sTu4FMXt 1yehAv0aWluzksVHtxJ32KrgbGliXaOlEGlheErtHdp9j9qACZWEi6IZYTI5RjG5UPTMXLP1YXoD GUtw4a/FGCfv+KOEfd/jvFLdca33DtvNHDzVgV4F66FU6Lv53YX5t0gX8C4seIenNkXMm5Yz2C8m wdbxfbV9m2JSu5ozu/Nd8+SvSkD38Rb17cx7Ow/Mtz4D4nIOZ1M40xRe0XI/mC9WiTzd6XXgHzd5 2oL1Rx/LLnZ+yRodrbF1doggps2Zkc4NJiERSDzQiznWIbFjTDTdp9GRoXFMDxp1KN4FU9iv9zDU xSM5R8KRNJT04iIZuJAc+ZERa+zGYOuVYfeoiwiCYBpvjhCGEuM/x+pjghaQ8RfSmIZIg3ujVZ57 aOUd789a99YeCrUHRd2K3IXnxBHfxLnWb7OLBqEBX26Xkb/YYuGCdY1g+IsN0wRBjTDaqxVwYHje FfM7I3uaxpzEPGlmODufnmrw8NLdM1GEcFaIJ73HiOHvgvt1ZCdzSo3PBKhBAps+JLDS64v2RBDO B0HGn6XaxO5inBzbF8+83qS8daYhgL8c97TIFfCU/hNIrulnIgKAzQz7phUAIVas+3EsK1BmNczC 0CcInNtBFxKiDI1baPzyKjTxnDI6dQa/dv03ob/adCJaIOQiUmx7/csUC0vrSc5LM3qGQihwQI51 FWBmo1oPjikuoAIIsA7jQCUxI9cs+pYy69lF6KlkVLgGRDWlBCXivfGITZzZczoiJ2ZO4dUhrC9I +SoVmtQ+55N6uoP4LoqTNYcu4oMy3+VrNQ03SW1eyF03l1sz4ag3TxZtavGO28wL2VxWD2lZouHn LArvagOzrqrz1s/MgNO4VndZBTl8Y2ob4tNE10+L5+Jfvu0PZWHYjzEjcClO39NhBjMLr5ZdbKom B4DYMijH3oxxLIiZcNLsIaUP3H26tqCySBjLn4cXEOrR1SzE5ArHNjncZ1v2x41ohwcqD2z6BrY6 NynmrCqnqGnoH6mWO2JlrbTcAxb29lLakwqveNgERBjEa+wYgAgVs7GPxzRWczYPuQTZb3j3Yguo wb/oqmCCt9eZ1vAr9S+1ILvpjgIrIjBthQL1boEEHHJSV32pXUrgWf4cRl2Sbg4ZOFxFaBd0Pj56 s8y/MBV18yCFTJ3XRyPSjARg19q04BmOLKYHXuEvcfQ/iH2X5ZbIgK2siDIGp02ML6IWM1ZYZBft vlY1qIs5hWYyJbz8ovVbpcXjubnzxQiNEtStDBB2TS6rXu20SVcLlfxZRYSLUf2ZxZQiwGlUIFou mCdl/20Mr/TTizv+I6AsTlKC8F92Bhfwk+YtWkX3X0C8A4Pv73bl41BnRPHb2jxfehnwlc01kKpT njmrrfCJ2Dk8pUNbsWkeZ5SBjDslRDengDeSjOiuc1EyI/B0bjFbqeQBaxOJhoG1LdqC6tFVBz6n XA1isElzzTFPv1GNgOtYyAOmUQoOCWEnW1gNg+euSgPWJr5qxUYdr6S94YZbijZ4Pu/73OjsLZ2s h5GnWfCGD0keLxgiFzUAn1Xv4o4/p0epQxqC8dy1dY6/yUndTkOuIk/ji6O0oxDXI16vBLpR6e7V Pl/DqsomggzpMjZ2bZfRbSSvRGhyrKXjkfanai+ahCsKAZ/EOpyFs3OQJmCo5MV37qD33CfzwxO3 0aQkggLVqRm7nqtQ3gxs3WIB9bC0scnsEaYsBOQ5z/vJ73kqIGHOb4vvXgwE1GoojEFqJfcEZlwR qrXFiPsNGnYkNBx2eOwiWtgVkBd4MBP1xWU15gLxIREjtuQ0YNAJwF05tqKFmKQU8jsssS9d3Zh8 T+CPojwHwXaGcN1hngSSAUlpHXaEp9h1YHVsKGGmNV/7fIZcOl53pHYn9wu4Qu7zNvfaXPQfEMqL hijxqLSdVc+aGJsUVRrbjjlND0wuXlxhD5yTVUqCIRqfqJIQmKOMd/lgi6w10H01fGph+UWnn3i2 PTK7+Zom07CvdWP75VP5BwIU9Btvq32F/xHIPXY+IHaa6O8jKFf8CAjyG6kPp1nQTVEFtF4SNZF8 oaU4E321YopZmC9zmyMcIWvhVxLGsKYcIU346KgxloDiAbZBnm2W/ofGn24fAuLQMbmh6b9y68pA aoTGK9XSOhkmvWXaXCyYn+ap/AYty6EcVH4LR7CwVYdLbzLRyDSQxnpbJuMZkuOJ4p2UWvnOy+Uf qhcVRQr5cAfHgNfqw56d5nUJhcnUXDeiraZtsQIvkZjWZvj4yR0CDXWsXsdpkzpjuhYRIKRE5VnB Yeg31JT6MN9miF+43cTM2C5stNJM3m2INe4fGOEqrUZ8QdVPeCA6YQMv/53KBQSLJX0cJuU3jy1X ecnGJcpsuTn6BkCo1/GMictWkFhRwhCuDMX/RdGOsO8e+8tQ2tURBFIrXmtf0BuO3z+ThxQEt5Tv lOlXhJK3Ht/+VzWTZzZWvucPpjVMazzowWK7YjtdsQB7eKz7uTno5pXSoD8c6CVmPQhIhEOecPII 96sI5/OYtgT4AbUXqe/lCHpf+2zNxEUamGKO1wabZNBJWL5BsnLlmNXR9NsG01LrkxcSNnkbhV4h 3ZR5uFNfO9mZhGf/lmGMfCe+lb32spLWulXHHHBmJCKUFPZDsBiNd2bwdFIsTm6DMnUHtBoodnzB XyqlADn9XmL+J4Z0GVogKILxe6iDCnbENKnHv1c5GdhC6l8L8ez25O0RKzndPsSJm6ZPg30Xbxce agOgD4QWw0uwFk4gz5Ilh2Sj5Svd73Xq5DLm2SuplLOlmtzsfn3kd4bLPmNSfYkQjHEYcDldcCvH vZR3GeFUjRaVffsaHETZ0w2Coz7lqvz/OOZJsnSnsfsU+DMolL7DjDXKMPF37zF/+UNHq5PwVDo4 lMmIlIKZKlJoCQrW4XXJrwav6gmeA0FwZ8iB+6qI7e0N8shVrxTEUoMUV8amtbyEm12bvdUhZMpr 1KcC2KP1fRLPQYI3hJfYkQ5CGjgDm8xof9pPpe5QF34AfBeqH7Ep9uNyX/EyZJ7ainlv22FDKSvW UBGxzJTDogz7B3gHQK7Fqj8ZVcyg/Vrx2ToA1NBYzfR/+xAoL7JG9JjF4XjwjY/ol81Q2FYq2ai7 hy/HmY+GEE0d3mHJufOQP2X0nyANhrMHv08OrdaRSc4F9GAU+5p41hBhx6H/MoUSi2kpl0LeKjq8 dcS4mgGM9K7MTtRWfbqiT+op8QHGwqUFemwbFVjB47VFpJXVdBIRTpM0cl4KfSJwrOjnwsfmnuUi lqqoez5M8qnrDRMIU0+fYB2Lx5/PqAJCw4/l7JhghYn7rEc4+NKsUAQ7JGuoweVxi5oEz+C9AvWK FWQA/1REmb1fa2gx0Gp+eNOKgtGouU7ndgPkaXL41/oO2WIkY+srfIeqyvjQpZGYqW7hQ9znmjNl uAup4s63jm4qQoVYZCDpIIPD55Isav9M2LtcJO4nksQw9z7HrUgk3MHH727AEy8cSZEI+IXGfrdl vmp5xKL2FqCjhz83xxfbIDvqKyaPkoI2Jf1pbpSwj4ziLWJH4NS9yaQWWVPUjo+h9b2F+zGc2N0Y Y/EMb8NQSjRmw3wbmsCjM53KA5zTQMeD9t+YTApZ+7vixe2jOKrmda6TVuu71J1mN/OG037Z/lII iRV9uaje/3lExnMoZThaiO0oJZzIFPCv4175TAUrDdYmrs8wxfTp8yFtUtc7N/mDp2fz0AHbJFkI a9AK0s1/I+4vec+zheJhGCol21uJZAbdGdhPAe4VSZon65OlWU5rCa74497xbsL8LMz5i3ant+NG MPNzVLFItpL+ljYLzkD3DVvgmmNzsQZuDH56E+RlBG75rt2zrwQQftxVXc46ii4RjtOZosRPMbMA LnK9s3JgJOW2MS097x6yAaktv+5MO5bxIFol7Sh2O8esoPQfgU2XLAnoD7Jfd+/QzgkyCA2PvKVG 6LSAVhQQg4a8dBEbemWzxDu+ScQYBkc4uGSv+mcTCAfPkaq8VCQaBFUg0Bu5S/f0NVW83uwTXv2E cI6704kWvm5Cu9IY/LofovLwIXRDmm2lKiqUiRTinfvhctji1imWd81HcrtPgIWxZff/tvoHuLPM Wa2A5odZzLAKfXbl5paLswGGJBPLZ0pHc7RHY3SmBNfkG6PairD1MIrsF02m+kOcrwu6whQjcOIB T3nqu/N0Umjt1zzMYUVAnLAtLTlDx6aByq1Yq9X4CtSe1uEVbj2b7yYKSooXPH324Le2b0SzocrE weG0Q6Pcb5p+pLeJyv7xoXLaAs0aK25Di7/N9uR2Yg34wqtPgsITKVws33Ns9qAG7xRURkIp+I60 NNaplrlwJVOX6GLvjnlemBrBdNtzOnEV8vzmftNTU6YXXcfDjdvwZUYyv+dfTiA6MIc/hz2fh6Pn oqB0+j16Lz3AnuEO6MHGdljneQO8p79k/QtUnL71LNPrS2cnJpyLJY7GzTXa1A37beRGQrWPtims e6wdFD8YQM8lZ5uE6xFJWoD5t0OcgtDP2kZkHWqGmS5xNpk5nuDI2Ovp2wy55z80cPIcdUGJKUEL dBDNZxNADz8lafVSXTHcVaMXrCpLmxivSBwukF14UsQWj59UIIczclRJCTPNfqeDdtYOsFs0d2p6 gjVTD7CZsZGZX1+S41Z2NleyscMnHvvehfRcDCKwhKScrzIzKRUAH6bSQzL17MeLwVsIOTlt4U0s TK1eEZnYZce6Ud0gpGNQnyxTYS12i/vMCcUuQ/n3jE4ZblZG3iOQIY/54SQwln+1lZgkXEzgI4Rn SZH8mVSRlxSygB+sBWYChW5roQPXOB3lM33t8KKco2Mbvaoe37H46XTjSanFO2I1Wis+P/MRIwtt PtwHX2lD3kJ+CwWqDjLoNrAQsThhtTVacx7iK1c4jjp87+yp5UeuYBm5C9+zkF7gwz3CbucbQp72 wnNcWvX3Z2iXuT+dshHOY1xkjYXYRhwvvtJ3CDVczuXl5BCUmvNb0IdH4Fta4ueoU4pKSeoo+rcM cToY7PKxWG/mJkyx0sDQL2owkhyYyfvS3eZ+SaWkC/er5kMygH5NcyHXrDgnIsZ7BWD/gjwiT6ft GE4a957/3EQxY4igbeKvC6KhrSJOmDppzq2Ii05DHVHAvxyZllXdHhwt1kPWNwcduAv0LpgfKcHW RSnlqdQDaZN7FvfU/IxX9CgGOlutnrfN/4Pg1o1CVJtmqbgA/hli/ESW444J/Mzc01cTIbIe+TfL tkWdMC//TU1dUhQKvZV7lFWxc5TXUfLljiFAHbbScLgw4FuyRoBO4FCAp/2LuFUSBKf/BP0FoBK1 M52v7NbmCLJ2wP4qKakmCbnRvEcuCy0jnS7VfOiRhEZA4q9Bw2fhjfrr2EauOGnMyUIXEP7ohPTY vsykZi7yq9DWsdEoyl+VkBHJe7+IhzoMS3/f3PyluRKnSIvbm3XWV67D6Gxge7T5EmIHcq20KuI4 oZCrnaK5WL0lScXYV7kLjNgvgxtq2Z00arPl5xLFWV5hjO+sJTdyH/Np8BnqzJQJKqhilWrShpcj kzHl0GAreOhgGSEWT6L7MZ/7mZXvvMF/nHeFakJQ+TuHbrWEtDNzP0zU+m1/35ZXWz35OJtIVV2Z UWjAGR9n007JDslpDB8GOcJT82E1jLf2wa9L2NiC36naQjCItx52I94GoaFcYMRKPOzwI3+Ddcwb euisg78f98cjI3OXWCPtf1DXyyoXFfTxOPXWd4OhWoD4l/kDY0JfN8FiKXW17gsX+oBb8eOWEhSn sOdLjuOM+YNLWijP1XmLLPN8gdLbIgiidKts+I+14uD5p6LvMmJvttUSspqXOl5qGx/if1mlcbK6 xx75GhjPIfm+I4DIHVMNuig+eiQvtoWtzr+vtbwtfk3zfaxBFS6n9EiTYo6KKgN8o+s1CWIci1sN U0atpzMfPYP8flW6C8NnJlZ1YldkqjPZZJHptc+D5hKmm/8NvW1t1RcAEucUAxY6P79xr6JUCk9m hWXfuOSA4G5HK8THScD3/3BWe9+UtD+DBsj2U2u+ctmg0lOIcRNcoyaERPZJvxYwAUTPNhQ8RJXu nWdPuMF6RIhASP0Jh+bNm6vU1F/l5NdUWRl9kyQRRgK+jODLlGPFdgJTWiF2aaxDdQVrUzLuyTrj iRxSLFdypcI/XVns0fyDWZOdxz30L/wGTIGAk8yCQ+m7Y7vG0Qt21szY/ELUzgFrncMwxfcgQVwE uoPaZy7afI4+27eDdAJnFbGNop97rwBBanOW1rDPjL1wb+NGCQ1Ra+IxwnZKjz7RLIVy0Lb1nQd0 TkI/9lN0I0j9WEjsmjxSTCSuozgmSDjr1bt942+iDGyYfUyvUA9ARUILXB5TT5AT77mn/NmF9KAs lJjgO+pXmOmWN1hE8ck2a/1J3Wwq7AL+IrF0m5gPCqe9rpTTI38Vbu8AtTxcRDNaVAsGjDJr5OTE BCtPGlMElMbkHYo6oGaogKq4/D88sygXy1p73JEu93VyJ+meX4qqp5YQSNP/r+Jo5qlfxqFfH2SP PxQokKgPlL92d22pd1vwGahFnaCT6ch6ATBlG+Rf1gCPtTrepIhf2Xfe0sXOkpw9gvaW9qXUhMED 4UGaaHkcl17UxKGurPU2iaQt3TJxSJ5dYAQjZzfpU39X6qKlatVB1aDKr21OhTs6hG8VCALHbbAG vRz0Xr9r5TAJQ89x4FyZbWGkxft91J0zUPYnvNr9zAK12v00AuQKRh+rkghohyj4FFy81QChA0r+ ZU2egrW1HGWz1y2d0k+c4UaucQhPzXFF+N4ZKtDGT/m2oLlosdnPJv31I7GwasGSBQl5C5TrLyev MJwhyxTCiLvt+5W8Yqt1HBX942LleLhvZD2eGCJYeKbQBcYlAFONKrRyMXsNLP9vDT3BEIl9s5eT 5fxSEza5Jy9ftt2oNYY08osLxghKT2P9pE6d6MFP4Ji51M7Jh6DB229ydNKHrWrNpA6dmRAg/dYt THdAcnApQ11AKhzdp/IBx/EIugkufiiEnX6J0udQfcn9bFxebQ1s8rMB/YHpHn+OhyVPOX7oHwap S33N51NVs064Bi8zqYYdpBjmv1AeyXRBX7Ere/rjDURJo2mvGJ5OoeHLOfp7oOvFe5Da0qleAd93 ksMqE53xKWZ2f2u3oKGVf9U+4eJ6aGjWNYKUaGznH6NfNTNG7CEvGkwI58suPd6J6NW4IeFT28gk eAjbNrQog8dXJaahvGFVHMD6txUINP4fMAPKfAhUUjZQJ+R0cOdwm8cnd/BPDfoT2l1xW4AsyE2G +aIDaUGEIxTQSxhPhWEHcD4c63K6gdCxHhJwlUUrHXDITLIKQ9RR20Z2q0OzBahYZ+8zC8e0HB04 2F5rcKh1V75roa60L67ZfHXI4/bjS4EHk6pCOM9DbQ1snkVQfc9JlwgSMYXwJr/0k9Wj20uZzx9D VoihZ3pUtzyhgNChlD9L+XNt3p2vkCLAPPRjdOi4qrCyCdmm6HKCMKFQ2R8QlhMgxwTIdYcNt2Lz Ovay3MSF6qmyne1ND8JPyR5Ih0wnOeovcTb6Ixzz2P1poG4cDuFHWnFo8YNuQpBHLMmNGO6s6Ml+ PsiXpPGqAjHGtHEQLBQmgXd3UdpkSHdxRuPcI05NyYaUae7TMrWSfG6QYe1Wsis8Q1NivK/1yrxS G7c28sAs6A9H6m7HPdYtVYmWUrWJ+fH/eihcxpZgOsOwBDroLLokz/bmQVht7hjcWSaqGY00JiC1 XVu4hoUgsxw9y9frDPBeOaX2Do2bRSDIj8fieb48Le7unKJoMHgOMFeQqqrC8GfN9OzD5SZedkij djpRY9BGYqAqLamp6CbEjdAY3gXmUCEVmcoCP4Cq6efrG4I/sRe5HYU+qd+4hE6CPYxCwhVPtJ0C exY51Q2ia3lGL2ErQ0/dTYHiNoH0tnafYNuLx1f+5oNjqFWprfHY4GsWsPr/ZPENEUfszeqPdpKT 99cy+GCl0/3MRMdm6B9fE3V+neVNM3eqW0D9PFgmFgD3J2/EWr/MNmDPjf29HiS1F24KkJTI1Mp7 dfqZ5CpVdOipzE/fkHsawSv+3k2p61WU9O7yDmSSRSnMUeWZiy4aH18H/ESU72yuTbYhcqFOScnO U6iORUjxBvwcox0fGe0iPyUR6LFFK1itB3jr6lviQcpBwX2/C82L6jOx2TP5ekONOIMUnsMUrM1W sLmoVk12Rp/yd98b+7xT0M3jTxrUVJ3JJbwR7iUHL/CjkbOSdbB4i/DgfpODr6lM1kPF6f68rC11 dt56UawCYiPVWDgv/97DpZqCm9iQ+2JGgHAP97Dk8A8egUez9WRRSgwHV+HXxoeoJrFpAsa9COvl V/qVLdOuDFBp8zkWvSDcE/h9NkScaGQSO0axgpsOhOddyvFF6cEw7sBowYXD8HJLAmAWFPvALN/b f4o+xtpsf/iof0cuVcsEb+ZECE7cFcO5DpkVXxGBXbl3HDH0nA8qab9hiz5dbS536PH/xrI//EuN 9VadCqEGPlJDVtiIrLgNf0F8+PeBvTNWFvEdJL4Dp1/HY1DrAqzxJjdhxGTFZwDSYsNUseciq2In j1waNLKuC3ZuhKud8om52Wep7Iknh3w9ICtPt/yyfzstvLJaAfYnR4qsJEVToDA0AqHoFqNbOfi/ 78GclIeVEX4cdIPZIhA90QTZMZHcJC7R18lAmW/KzsAjmBhFDUUmLk8xWMTrsgw/SmhJJw2NM2r8 uG8evnFUaiauL9QDQoZAJZqWKXIsi59nmJLc5MX7xENr2lY+fvAnmrDZRKLS0w+6PrYvOQwwpHWf 2/cZz93DoTylU57tSVTjsACtOfILeJ1J2iQ6pSBYCO8ILvrVnzSOHYx+4AImszH52KmtxF76Nx9K aqzBynnauxIQFecXZpuOG5elTPXQMqm7MXOcnIP2RfIwyYWzejU7Jmr6+cpNkpRrGo7IbhWlLKpE mu5AA/urCf/34S6bcPNteSMmp0y45Fp0iU82ZU7KgGfQKb6HT6lCyArVPTxz4gH66p1Ize0J9J6z 8bOO+bmoZ3SzizItWL8VdRxJK+Z/9JcKVi8rs6oq4lfWE+dqcQNBpam5KBb6B/Uws5FZaPnswzEl v3WwtmuWDQNMK2XkvZTOfLy22EcBISzhqE+Rs5fKkidZj9OvsCgY0TMpcRWfXe49U6bhh7RkyBPT CSwjcDQQKX54Zq4/XCsjhVw9sBuichc2k6q2PBFl3v2gWYbjxT5KMqT7vlbYHzriULEbNK4rxWEs 935je02LpmANLzN8Buj2GZsUMIXFEf+rI/eGszUovUbYZKLbfrRUaxwMn2xLdqy3vElwGKFYwE1v 3AMSGDuD9i8hDBmMZccNLTCaIyjS9E2QaglofkEl7eNJ/rBMajyCfVXGgEZtzTogXDDna5lvbWUb nxLpV7Y/EeCd6fLicOaKxF7/1i1XeBzXE9LYbGDoKc3N3oW08+sqlwMHPxG8fBfM3Pc5rWS/m32z NbiwsZdE5UnFf+slJkrDK9zWixD4DcTpub+9P2bc9CXle0++8J+AC8YnF6v+/gSreSfdw3eK33K8 +NF14reLveA3GG/MOOI7NtAjSXVKc4vcyHLow/NNrXND/ifWoWHI3djRL8zrZfH4mQ0FZ4exyv80 eEQDL8V9lBLdyW394P7i3dYZgyAC6cqSw3D6+UAUXfr/RtAuC3kSiR5T+CCcYdYOp0WWPkEtGfEL XIQ2IPlJMyKVOSzfNFAlvFnxky+dr/7PrTNrIfShtoPB4QADVWR0YRhvqm5iKH1zbqddCGRXjtS+ fIMAc8vp30jz4a3HjqdEJN5oFzFH2x1NnL2KayLvZo4DXj8wWD1qfrKmi5Qc928fhjQc40Z20MK1 f7cVdmxMtOq342AAUBTTvKd8DcbZ1DOwWaqL3IwDoa8UGFTlb7KvkAmtBVtS8HmE6IRxCiQaO/31 aNX+0JsNpQtjJqm1yVU5o338a680N9SlhtzgwhxrtbHwVF4SxsNkONCOti7xYYSpXrPz7TlbyYRK BJJbR+dZzEJj0Dl/0lwjNzZw1QZqhBde0sD+NQKl8u9Yp2aEgnR+Og1ix/xFE4O9TVGIgRjf275Q sZbZxDYihrSttHRlN26zuyaWPGdTxIVGM1yHlBsRtbj0BgualHfHNr5YVDEhJaOwpod8X5Mz9XHb w1yBncSzS+c7cZBp5qDewWQHDdxTttApob9vZXSIZhHx/v4Fl/YM9yXfDx21VXShRZRgoGTTpLu+ UmJ3eUTyRONBIqjg042hu2uLFDXVkShzsXNdcvX46Is+gV0HaEIi1+jSGcHdpXF4P1VpnZr9TQv/ OihsvPczOXhfn8S11CXolwbQYMt+VfcstLme4OGYfZUmRXiZIMvCxQeVQsDofV+AXPcY7vbAy3CM SCgjUz7OVLejxu7oGMJntP/zP/puDLwvtysv+COl9UEwGa4L1GvfHApwt0cMRduzW7fgv+M6hJWU ArifDeLD4KNlLEdYnHEy/E20kYX842cfrKGI5d0hdOqTvgCtqWzapdbxDJZAVoZ63QXOM3yrOzz6 uuKOg2tDeZtWaNIVFW1sRaNYqrU8DjxxG0m89SZYXSSTk0Pjsie/Fx/TxygNyA637E5HAFtJTx3Y 3vqAaEgGnb3OG66dLAW0sq3ugZOTsyXYfQ8aKop8GWJo3HCn0sedQR+b2tGCQo5USRSIGNFciskN wEYQDQz5lfOG1Pna1CRrOm4Qiqsaa1Mjw0cqnvxTWQuZ15DwI/x3VAi9gAV91EfInTxap3ipD5N4 cjVoCuCiOCoSQnTRNM07xJ+AhjN4TXYBVvDwKxdGLyR03XBfOzYOZz0Sypp8S8+/OkA2aU9G9GLk PFcMZO0/+9QB3STm9YuUmk0tO9IEJWfBh8uwk5vpr8crRXXe1WCfIQAstnB6Q6JWxT1D6V4ZR44+ riMj/1SK+N8QYQFskCFLBLoL3b6i4VvYUN7h/vOb5ffmRKHDFDuOsI39pspYEcwMzCVg4i7dpsO/ DhxExMHDCUGGXeGM5nTwZuKL0VV1zdUVRPvqGfE/aEZP/vz9JVDeU8iJp78uP/a7xcnkP9WrkF2a 6k56RA1P+G28U/AlHfpEPpVje5vyU90PHg92J2lMJPjICpVppI72vbzzMJTnrmgaODYDoF226Ih2 4+ve16QlR/hFTQoUOqyMV4lCmC4K0J6JjgodorAHsOoG7jM2FYroZg2oVfwKAUlMUEYctjq9mefW cbwkW+nDDTCl5LaWdJu7Pg0lx5I4d8PeACvQzykUlAVyRhurX/WiM5iZBlI8xBfAnOcF7wV+C/I9 UxaNE9U6DYZgGgn7I+cgo6RSA2VHYewYsdkvgRvxf8wHLSb8BFEA3rHaqmm0ccYKzfjP2rxBti9m vQKllDVyi/7tHi7lKOOgzlun8+cu+tgld6hcJnabLGMM8slHi3Il1RG7GwfIlehAm9kYgBFG0uc9 XFGOzd9EQzAANPNiLbvvxHl+xzGbLZISC0omJyJEty8lKvxCPAdqnA06Xnd2KTpZXDIOscAsKq/h tMPK7xEJjW7MF9zAcIx9ELBsakESmFVJMgc1tInTc+f1VQ3teXk3kw6Mdz1rEdKnrCy7kqQNBQi1 EuwDT8YedGXUocRF6SyVJdoNod5EobgSLxOeAQlbgacl7Dzc6xvKPL5wE4ADEADFLkom+3qNgcKd N9S+1Ppy9M+dfDDfYaLI+u9N5VgCK6fOQsPDvSfwuXXZI9+9k9vHgmYt4FfD+vQtSGhr3zJ3WtY+ bCkvtBHraM8j4XHMMO+eiQNJ89BgdBODRyJ5G2tfLAC0lrfydCnegGTDxnPwgeyBgW4SlJKcYuci 2o+BWnHBNYk4KXPu52mN8sfzNZ+LfCCPxylpXoGmZZ0dR4BNNcyG0UtqqOTkLvxhL5ZtTELv11Bv VHDRipUpSuO7suXtijXd778KGjGHGSkrO6AbQB6/yLy1woim2+I41sSq97uSeZoGoAk9jvyC9dyB 59lfset2BkOFrL9SIsIYNLw4rC8fUOdcW8r5q7tXiAto0KXJtHQ+VUKAd3iJ9A7GcCuhPQGYZ+9E jr92dBDCdKOoOpERSEvi1QHkOVUhEjAR9SOSzcI9Aot//L8JNDDZLFwIG1OukxhdvRlqcQ/chMMJ qJv1O0wtO3a2ei2CixWRxCO50uUp5ygYbKMg2InoX2cByR/191aPlMAO2kI/+QfS/CKBc808+el8 /T/lQ93mtfafoAhyLd1yr+cQ+WnaDus5JFLmGcsf+qras7LG67z4IXe8+j/7sPKbh6dot8JGRMRi 0nUJrLa+5l0KHdoTKVSlL7oDg51A6xhsSSPOE355GbOZuW2+jfKeURjQ8y0eh3gs5X+U+6imaK7n XiYCh/8/AA5mhiFainZ1E8RJPj2HHvhp2gkGXtPOSQTRu0NRjUFG2O2SNMuFpDBMYcWhHpPpBjIO Wlym+hn5wuDm5Qbd+EeGsJvPIqUqIIujUWYzmCQGE6ZtQiYdMp2p3U6uGruNagmV61PVNDUB38Di weSY74QJuQB4ZARTOwnFuPL9pJXJGn5CzaIrgrTQm6EoGMr2bzojJhRrDtpBgnc3pitzcs3iOzqt 4/01EtDbcOIHGkPudrGe7w341jFMHaRy/d+n64RIXchDB8ehN5sojamQcFnJGOd014+MGosyCrHX 0T476AyRpTBnpeTGvDUB6zEqaZleG1eE30rx4bIUBPLus1XhwXTa5KQvDjk7vPePturL4IGEHfpW X3nzCk2ehtrHcMSJGVXVG1YAWs90AFudYbmiGumDC5n0+/J/bhe+Wn8aWgd+Bf3Py0sSjz6gsXDG YEcdFIJwyqa4LuQSMQqSMRDwxzKqMPn8GDshNRA8bFXPO867Om+GvvvKB1kOed7tDxzT+ASkT8Jb wj8On3lvF0nBiR3FdqbLtuPlzCMraay3RDDLVTx21KkNfwUfIeNyw6xVvYWohrt/8J7NAWNo1yNA Osl+RimzWcwyjM9DV2hUFrOS88CU79yqH6eykkBF+zU/JG0y7DUVX3mlcoqaOEG9cLRf+Jgi1FE0 yC0SBU36J9fWmtVEdXZ96n3t6hBk4kxTNWw4bwAVK1TiNCplWULGYJs5svkTkFYB3TO7XVvlK8qB VPYGDyi5TZ0Z0C8vWqvdE9IHDe8EUC1czEVMagB5dTPuym9rMp9l9ocvC7mNp/USv6VXAljUYohO CIVyNQzz8ducYBJLGGVq5QLQnQuGrn168ClsdafnW9IKApY5NUqcrh90p9WfGD9wxA+OOA1MWBN6 YH+9ZEeDf7m5aNWFjK4+7PBB8mePOhmSjowelN9+iiTC60LekHTWofSDqphpkJP6Y7F5/+6X7Tj4 RddJW33ND1zynGXvONNk7vd+Ig5C7UHTePA+MIOS5hnhK9e8gM2odVE38PR9FraxMFFAadJKFGzU /3F8574mstLBHmnF7ZwUZl6714Db0y+sEdY/OgUDg0JAp7pDKhoRceKDpctM8xYc2vBeT4dbC4Xw O1Wdfp24XkQDKHm891CFNVa4nPnG8CRQE9XgGFOEd2E+T9FAWuhBJSf458QcWg5HtdHJJQFLLrIe cYceP8lHAl96fcLYH5GaoBoAIo+/SPRYUrS3f8J9VvH9eYM/sVHPsty5MCFqlk04MvOdqbicpeJd n7SaDA0AE0eLGliy6/ki6fZ6PM7Our2O2gxOFuOKcg2u1BEiwO/wfjIp0TpFHsXmtFFnG43KHiiI CWGhpZsxjx3i0oCtL6QRXoRDSPn48Dlq/qa1y3yFVJH/KMfjp8gxmUIap92Fcz5INTyj51FFrS1l fSVvbJE3LTVEwzrC5JGhQ4C0s2VQyh4jdUInRfckpD2RTnbKgw2TW0+bVmNOSpD1q2MK0Zd3/ogD NXcXE1MLM38WNqx4QSitx+gS4m1wwwovDvmAHZFV6Dqr4YvqTfbme3rZB2UvI3yS/Iufw5I3xsLX 4XOg4t3Uj58iHdfxunN/musu5JuCr3/C+o3nxQW5lBgeSq/Yxb/qMRfsD/2BHiDMj6SgR6AVNMg2 9lcEXMpOr1FmGfi+EiE7IJ4fyMYYCIrb6ztj0Hc9/06lggxoBNvU+ipckxkrFAmUTM1fn2RBBx3k /md4qpvyCrO48GyfOiYpDVWonhzwWRaTmmxB6M1UQhzYhH16hrxY6JKks3VeqN+y7a7k/LoU6xVa wnP597JcGGHv74EVDSNSai7+K8hCO5nya9Y1i2QoLP9IHkBZgn5JNj1F4FHdGuhVTnt7fIHFm7rN V3WGPHvVMKq+7fjPwEOKy9ZVJnNYxmRJkdCJsgVTZtHuo6oxgPrL1qmT/XKcKkITjddXAT/z+jKR MdKEaLC75ktqaiqCOc99QPB+AdLnEVbluTs0YTadi8ppw2jJgaOJzm9OcSeeSAmN7kgNHdEIGdT9 byF0ANVovZbpoLTfWcqkTpGoIJk0SyVo7vWFH0Sk885nAbjChM9opPdcCwXm9xY4KsuhUKT202DW im41XN1hbYYBUWcrWvYnZknFzW7q39Wiy+k9N5KeioYxJNkrmnNASSm2jMQ0gXdXkULL8Dwn6Uqm eybZ+ntcXSMc2EvGiqIy5KHlGP+CpKPi9gw7BGmWc386Z/hirwAdUrhxQDMKnZqY0soqfm6KIqXF fmJ3UN2CUwXj1JrI7SJyq52QST3GcudhW99JpFNQ+1D+ilUypMck4rdsHcW2s3FYbVPIunh3/YKf UE18y6RcZc1c24k0NNyZKDamS+PGQt3GDRLh73RD21+QHix6ZMMRJoBk2eVg9HLQSx1952JlwezV VhbvJ+IAFgXIhVMMYPNL/Q7y+Sox5oD1NB1Pua4lp1CaZVpajoX66v6yAnDynu1l3WEzrCYWHt8/ 38Yg8JJD/rna7s3RQAMThN0DCRPnhb0X7z394g24MtVIcnDSbLCDE31yrEg4sQRJ0pDloglfNUX9 MoY45NzNPDlyK4wC7+aU0beI2EWv5KbKkj6ThGSxWIQMxLgQ6lN7bu8fUL0iwXpGOiALzJ85jIUh arUGA2mYGXCJmCiWQ7AKURjyDEgAEjQ5GGAMUI1anVyMMUn93Og0khs8jJ2XJnmHUT3G2FT9K4Gq 8sTz+GjPQtnnUS6kvn3OrSvUIaAX5mq6U1wsxQfQywteEyHdcRop5KVJMwbqMtd+U1DET+3I1nch UstQ2eXEA9lYLvXCGl/T9xpwdac+JKXW8gljyf/xZTb+ef8ydk9/W3ztXMUd/hw720JDDtRe3Kgj pXhQuRZS6auO6O+qupJWEkgsnnYOocW29KOv4y2Ck2VnlWBWeeYKblELmPCzU1ncb9c9XXtu9vLw NphWCYga3enKr0Ev1e3PbpYhwKdO7vSy2ub/HHF/wqi3AK4I4M2i+aOnsgY1XUwUTwKjspUWAkZt 8YfQMkb8LsBA2IbYoU1XrFBDivKHUw8JEIE2Hs267HoX56lhdvpyq7/mbMeQis3Eji9M/1ELBWlr FElFwV6/HZF01QZMiVk7qYGmV77Rrx4iZBVkPf87pPYELhjemUmgJyLlnesQgVMEO7nx5eVRrbxx L5diaQCsQWZm6eTiPyjv3+/8BTY+dYELYFKUWrLXyBSqK8W57l4B9hv2xtUrLWCF58WzB3ZE5/ET Y+HfV3ZEbKeVBd2ziDMkQENVKFm4liC9qERUDNFR+E8UiRTmf0cpLi5J7QXs821w2xQ1OiIJQeKq ECeRXmB4Gt0YvFP6wSJmLJHYG+PKqBiI4ID6OkFTHDwTqY85nDTA7sQzYlxdVivQj9e1kmkiCnLE d3RncAkC7TKioOouz43hDodA4Sp2RpRcJ51Bmlbn72DBQf4AkNS6A75Kpt4khDkSRo0V/rZdCSOP /H1pXdVjuosa8OP++GccvFue01NiBC68oIIt4z9xv2rT3Ng5EuNxHki2SWqnuaLw/FPvmCxiANBG 6ZHqUU5QsUVbgWOUJSVPMX6hxJNPyeYDQ0cpYZtIwsC9hhS6Pj7jkv02PLNdjJIuTEqFHKJYzuiQ 3xP6Jz6AC39GMLRsTAmtmW1KPASV6qoEWnv5ZQqB27d8COiUET9drrBH7NrKjlt5Qkfei95QZuBC /5i9DTqdLY+AScH5q4A8IC+tBzYqXxy8aP9gITTPwInjnVN+CE6YalSeNAbJAZGkTUdQ+YH5q8yT jbewwCjXB0JirsPk+rPHu8hZnXHHbwZTCQlmpUUhqAmproI+y6mcqq/kq5HGxPLzzh+C9XmZD8Ws y1o1YYwO5Snhog4hmjaOaSYh5vIN+NC0XatYS9XsLpv48gPB4fcKuePcQnCpGyttOXqkKdCfkMQM PktR1ldxEOKHOtEgOudmCfydKVmkL4HahvZuTgsMAtpMiOH5u1raSrYTkKZMWAP0328MyM+P/8eR sNdlDofxLcalblEfbre4mTGdiT49g34UmYgfozNvj4ls/9Q1ZYmHSgBqaibDJFQiiUkdvdjlVF6Q 7bU/9Q1Jz4MosxAZL28m5tDyQsip97IGAz+rqwOLPbD5JC7O8RXLLXXvgaNrnwB1ZFhOyQo8/AK6 5RjNA6CSM2E5/yGv7p+DnnS7mPXCRGZ80qbqkM++vwmT8Kz47wCNTaDtyOIBVPsapAZv0EvA68oC CgjAWU9qd8Sk8NARtSZTy+M6IzWT3+3+z/zhYit3nljY6irMrE4ch+hTLPBNHCX0I1NJoLqjR++B PAhyvLGrNMA9qzf31qswDEiNfq3KV+Fqkv5QtsNAvcM8IwSaRp5fWXwoLfyT4KA/lZ6tgdIAKzbq pipjndI3SULl1J3AiXYfEQe/G1OuQxZGzBnsrZqDhU9VNluj7lZ/kMMD+vYAgLDFyzV0MgylFDFw ROP3UIfphxViSQxxSomlvY8Y5KiYirPWCKjuHE/74GgZrSJQ7+6CbD3kf3sSCVEragt60QQRfvB4 i77v8AsiwjL2YwWDULCJ/9OQH3IF6HiKnLzMu9/RezGnC8X49RKu3G8WJ36/38lr97MNEKkG4oqW Q0V2qwu2unRjc9HRTxssQ5WW+qLEf3KDFvFxG2Chl1IbWu0MQlmfxh3UJcK1J8Rmd/+ywzKIWAFK Ovgx6LCNL/jFm79EAL2nV4mSTvPBcUDJJcrJelXcNZyXolqzoqMHmApU2fRKZBR2lw2e1JsgaCr1 +lk7nqs1a9CnrnE/Jp28OMPclNA7YY847MlZEOG1x08TCskE5D2TOQQuMuQD4JJn6YL4i3TBloXm iGUaGUU1fmEcAIDFxFFi4PZjEWobTXsUkj2MYX12x21RZQFYHVcJJZ8uFx9V4D/mtUv+rS3i69Pg cUzzEPKSuTjDHCDwvwi2qqxzD+1wc4niIME84ptiHDZp/xEdKcR+YvuJ+iAPcpt1wkUSHeMFSjc5 tuhiPeom7N26daZDd2llHYycfERIzCxlMSELr+XuX+T/cfuqqblMVplSN1yWYGRIu5X2ABheCR6Z H+lYCQI7yYHIMfGN5w8heWFXxHatkEwNZ087JRkPy8ZItmqH3YLmK+RCsUO/Of91VyBIS+1cole4 OsLfdxCafZrGtg8r+KlycqzQ7SspQ2aC/nKhbxC6ICzm3hgiLJRDfRQ3k6p00pcNHzyvYHj+nkEU xyDY/8q3ljlcoP6uGWTuOlLYaSvCgpv3Ld1TWfA/nDYOOW7EuRY3UzP918YVh1WYJQw3EN9QPUXC siR1jveHoJ+hLa+mee2ikw9liCPkI8RYeo97re/wJkD56n1viDAJDDy0qP384opF2/bUbOw2XLND bdLmgZtehYv/8yhA9PLq2YXUXpFF8SgkSzlfg9WVAskkeXDfG/eUsMnsG+hiDRatwSES/BXGRP1y WBbrzcYuvT1TH9LcyZj/kbPxEOWP3FKeFKj/zNMMvqeNhjOdnptUg9U3UgHyJKa3umbmjQi6lbmP fV5MhGbVcsBg7bz8IR/xRMzZmBU6meWr2GCaoJHvaPZodhBB03oYlentxTeX2DOjJn9StQVNUcul Tj46WDwCxBlW2WCbzVa/GKp4skBzByvC5O63+K3sM1FWvYg2nqeqeaLCQgKjXKVYtGPnbzy5/DOb fzKggWGW6oo1apGhBTUhYCm2otWPFFzzINsxbRF36oEP/b1s8JIWB0O6BP4PQNkTvI3ruRM45nG1 8Q5L6+chorZAFit1impvaBZCmHoQN+pzTY0mwvBvt+2Cl8Gq3Exl7VIyNQ9OBL1oxNz7sF+p/Auu gVyNG4zMLh/7hNScN+exnmqpdoh0OOzwB61tFVFSFK3NKbj71r0eIg1RifMawcB6t5A7ckheXuqR au0zsetT7tJsE956P9uLteuE6MEjzfdUf03DSWK5xlSbjinE5tNDSB4qseqxC1u7+tT9KWLarE/V zMlNsXPKhp6/MpHVJn657wXg0rQiywXw0fC+j1+chdC0hXZhyWHtFw655xgtXqi8hemaRQqh1wUj d+raYr7DxrRiOvIfGzTkV1barGexkUQgHtI9ElZcYlD7mBHy7RCye9llyC8fKoLMavUAuY/EIfdd B985Y42JSh3damw9g6vaOWINFcaS2+Xwavz6VXn0UMF8+r2K3T17ZPhNtL41b0oaZXcJ5jjVx3r5 zbSCOKTfFRIAW3KsOcLcRLLbsz2wCo40g0tUvMoGoT8+VEvkKqtfx85uVdr29/fozlUkY3Si+l8b g7zn16QEIWjCFSjm2gvjQukgqs9Ebn7WPHCD+atZhMLZCOBJ/nIrmoXr0JHUmcA8V/sOrrnTjV3G 2lM46jAZP9o8Ht9Mk+nVAJLnZxjM4MJoQBWaP8fBF4ZA6uCip2QTOzLlbUPqRSIvVIzggEvYQuoi FOj3vbpq28kK6Y0GCXjhHyhdwJT1gd+TSN0dytKTKEGPE+IrTthw67CqYaETveurAEGQ+SXaoEpt 92hNksmSjlTOOfO+uY7dS98te9KWIQ/BxVlOY0gLZvnQYu36/zvq0dsq6KzjCHrFiHYQkIsJORer qhrhNsUMeDEpZSSakk3roff0EY/MnqYYHFkkglHsdrng2kX+4YN8h9PjvrpUi+ekWoUXmcuHBZQK EspyZfTFUz+1sAYMXzdnik/YCreNtm2yXIcQdoVwN2XDDeXJv3TkLQzy5p+Yhe4N5mWPGeBwA0c+ Ph/DFBsJgkzNT0CnS5CFxWtynnxEa4lWSjgsMVDfbFbAiiSlSs41BP6dZsmnQk/nQPHflMFa9nSR 6uydKFq8umLDtyYvksfl3uGhOM8OkBg1I4FeNQcY71uYcMxldYZ1jyocHR8jS9CitSAGy7SyQHZk Z4mKglgftsZSX458zfVGq2XvjyR76MfSDXHg2WWhP8gEIZIaoejST8W+6DGKDmMKGyfzikrW4+Vw Ki67+umLBzdLaT0B2frrsmyzGiuB4521yr0z5v3eeA93cfysJCz1eHkLaZr9IwGDrc3JynnmBRpa xYlFEh1Zl34pMma5r2ioJYFpdHoCQvw0t22aLBSdcJPMZS36iBouVRM2SqrJbvUDFgk/fWkUMBEf 2TWJ9bO9ElarQ+oT+Uk+O8k9Op8jTKZym+jB9SEaXIFykYMLlYv7jZiaLGDycCOF2rZXRhUv+PMq M9e1MZlvXIgE4N6jK/YNbV0Vgne+SOXOBM4Z3mmWj9SBHQARv40vwg8uZyzvQGehxoB+4sOrT39+ Nn+gGf3R3TkY96PhO8RIW+fjGVAlSyhM3xr4N1m3D9pQau55NK2yv9r1DhwhTsykpYJloeEhHLHl cExtG+t1vlWxv+DkdYZkvdqVF/vwNj5y3BtK1/su53XaRey4AQH+WWjNudPophluUzk5yT2dggrR q1sCPn/OLnc9paHjS2lEnDb5ab/z+16TFNvwSsOV10pGJL0j3UHCgsmG3NTAX0aXq6zmqSSo0j3K 9UVvJF5O1kJaCmMSsyWsuZffq80L5qKMPS8oeZT5KL7LoVZtaNy5SUQqc0res8VvYFR2cSznGutA McYtgnvnzTgxWO5btovc900lD4qewNY9HdMFC5zh2L/IPuD+8feDTXersR8nc0aTHYb+wcBQJyqY XJ5iULwq2+CispSbuxxTayHxefZ05KFbyios4c3p/fMFLub6UL8HGqTyAWorCY3S2M8qYp02iC55 nmopXBd1b6K4zBs4fjYQXcGAuIuceA3VGAeYZQ0mFCyfZ0wrjnt4kdx12zWyIOFA/ppEmJZQzy4T qz/Vgu+OOh2klmWj9ho0xkcYwyvVmuHdz9rycx0fgD8WeSJBb7BgvaBgokA9Ke4oVP1DmsmtGui3 mzHPaEsC98/SE79sRPnUsmmr1D7TLLmFKPFpJ86tcT1PCqp3f0lNJLr52jXp7J4EDHLyv8n1U70h FiMQfitzLTCGYGdS/6/0yJoc/jwGKMEli+TRax/53ehqtHyfQl4psZP1m8iQ+jOCUjsBlm2NgBU9 a2QN1cjQPYpnzT9AlIiV0HFn6WMQaGlek5pS2xWbvyvpcEC72pu5B6aDwycZqhsIEvNca3HIaTYX lksw4RJagiHyEeX/n+yrwa/mJzTC4lvDoc3g/M4teCFzjiI64Vr7pAV0bVUrelZRXgJCcz5YP01n UU5wN6vAE1gW3U5kkXsrRWtg2tYVVl2KKQGMbWvA5tngPCenyFdc1ImZr1XrSlVfMLIWl0zsMyRE 3wdFVLZGC6Q30yLb0BM69U/Tyy4w4JDjlvzRroy8ak2F6Jka4G6hVG3JTi22dc8EDsx2h09AWAUx o0DpnTFCxHw0VkLeFwJgx/XQddzbkaL8s8VKvDCONyvUqhxV8OUSFwpU1IpqX4Eq+zBWzV+L2CCF ymDyi+kXD9mydvQKs31c3bxbc63FxCgjG3m19COJegnFIbGGX+Ms3URFCHUqkX3Lbtubpzh/Xne4 5UcM0WuSMQTqp+mF5+olILuAe6GD5wQ7+TYwK9zM8/bq9Lt/JO1Sms4GTlfiIRX8zsZgxZ4fYxYI zkdmxuLkkzceoLQdmSlsa6O5TSKMxFE3z4vZGE0gA/G7NpWca3oa019fZg1AeY6Ak/XltWqyoZi/ TbyR9c/5o0/xSs4FbpaqM99mpf+Y672zU/wEkcTguOTby/EbBktaKjkccs4WBLGIqUGSAWHmQ7sG 7EmmzoUIXhgHJ2Es2ZMc7Z+CdB3uYFBiO930TX9vcKhmJXYHHV5HYZLjsosS/qP802RfXH0JfUfU ub+DIE+XSx56mm79xZhuquR/K8IvrAoapQbALd/PSyLJthFnv8GMN6zrht8ki2zMabGbzemmdQRY 1RqKixyH8gI3EoRrHy5xLSJLHxUCpVgKZ/MXOobK72rOhGXEsgljU3Sg2pCqrm+uYiqGAS17/IFe zioC0OH42ykLO16fCvgTv8y0u1llYDkv5YYM6Lh8qZnQmtfLuVi+F6oDNwkunZ5mom0XPalyP/fJ Jf2B2GrslN17hrB1qV9pSCTNzZzJLc3C8iGjhsbgOQsyRhGDjgjFyyjzmxr4/DhZUhR3dreSTxQt QfzmxJJhkDBiwpZGhTfDYIWGqEq+oKmhru4PBewg0EWx8wP+bWHPpl3/kd286IvoTF5RM82zPfxL HDaHLzqMO9kO3gPrk6IbW1bpfvDRue1B/MUI5SVEBhUA6U3KQLdpPUwHr+zrTo2Yu+iXrePUrLpf KvjmXiUatu9kYOnKXw7CAppNSihyMClUleqFiofDycZ+HT6pdEi+lb/ki8vANq+O5VJ65znaujSU kbLrN6g2LIC704SRGJDm7P9nIoQ7tDxa0qCxthJftcGMtv1EV6s3FIJ4ksNdSdsW2cjpgnNvHU63 b2UndcycNPLrwkFIfCXXR26DcTYVQUX3Oba9tMpI9ridxft8AXNUvhsdO9Fv+k6YLoZekNVFHras LJdLKdtCVgo27awfE8QYRtc8J9j2Cg+JZChAXB0P5UJF51UVDteuf12Wlprm6SHCent+vNvzQ7CR fs2fgiYQefwIDq+1Axrg1HMJEik8qnI+9EV/ee3FY99E3+giu3IPTYmnMk6UeqBfokKlYqK5po9Z 0Ky4mwuwbeip59V1AKDI9/OyFNChqGEK1BUskzPBjlvBnmrDW4Ln/xZSwOhJgGjOOrjqFCYTL7as wz5IA0BrLnM2e6W9GILW47X+uCbWfScYQpuGP2BnNHVcpCpXw0i4P9rt36TmWJRe/Z/RlP0/zxYi NZL244ZzwEkU59YHr99wBN3QH96I22cAoXMVm85bMDSluI3GqiNgBcUShCcFTuZU4PJSFussF3ro UiAR3zhNhGur32VxVG9L9+viNMxT0RFfo1BQ/ljPSY5+kQvGo3mimoEPfbkpbO2/OWqHIzr94GN6 qzz6BwOz+7T2WdLLcSRwMPLsy3/awhCtwRuDwMd+pooAzXOSsLa9BtBx9zKNPVl7zwXjN2QSpT5T 4XaLAz3lfZ3S0Ijq7d8xNxHk4J4Aw7wyxbi6ALEQb2QSutZ30cmmM9j8dVkOMBvjBiI3Zt/WLcpK wZi8Grq9ON1C951An7c2rVm9ByNhTe+Wu2jbEDv9z2k+LXu5jDZmvG3vE9b5D4X5qY3NIyxFkvr7 W/j65gz1HZ4THWgI3j0rwiNHjidZ+xOnQYAbnnA1NzOskd91wGy8kXYtIkPJ7aMWSIN1fkvF8DqL 36SEZTfV16LE5NkZvNFtsB6R9AkuGgCU/sMVPwbUXGIja5UoBzgJwWnmQGnbgiX1S+PYyV71aSs0 JV1PmxkAmF/CoOrwxSr2sX8nyIknWVaqtfCs1jdlJrpBeu6ub/wW590rwvA56XBOa1kwL3teb/kl JFVsBvkXQ3Bf7KhnNt7EyLOdEXgo0fzwLe18rYbuXXxWPJKbTrjrbHJDfzX0Hnv8lPeljCSmdHpU x4ikqOwUMJDNcbcy69p4xjKabgq7iYWEoOyWaQhpX0vcRp+QbUweI3P4oqUvIC3l+DFH0HZIUKR9 +cf818sDKi7JcPfzv1GfBQmbDtJ3RIKMbDL3dhFKEOLvHG1MwmTTHK+CLtLoDCcTUHjDnwjONf+k b9cbQwSY/nHyUqwW7Wvt2VvyAJ4eOQiU2FQBLU4FamB85CEuj9ADfeJu7XcnaUgyCx2DQWwo20AC JiDh9FzFci/mFXdo4NHrpoxv3Yelg51/j5QNm5OyuPGmiJg9GooFREhq5zGTEWdwxZiV44+0z3lW uwOjJX1Epv9SBs73Mjh+CU3c0E93GPiOCnqtWSdJQVvV9j4DlwcrFm15Reox9naFu8KU6bz2jUf9 7GK/W2APPG1e4wQR6sjK5AP4goAbusgGuMKTLY5GQQsYMtpaXhfa2jE7lsQzjdQXoN1z7Hi93L/R 4oVb4l1OcDUcd4xvSdN43qs6/jDHWjROX9Wi1VsaFzAzCK8yXq8f81s6ULvkBwHuq23EXU5QwErt ACZvwVIbVSplNECos/3g8Q7rfMOUi/Os4zUWKVj9frSF+eIT0ZSs1K8h76nNZsqDtEZQRZaVbdrU NngRaV3Fhk+POylaexGBs2rKITj3FoV2OhHM+iSTnNxxH7FlaLDsugW+R30W8KntvCg04kTDrz8k 3iqHhojCLn57hpsKaz1alKsuqUvz0MAOvjt2Lvahzgza9KHWOcKYKNYaIsBSk0M2LJ7Euimwb78+ Fv6aHkF8KnYxFaX97jpQkzEGpozaOjVBDO1sNmnnGJZyVytkrDkAswLCZJshyAGQUT6ejJa8FP/4 421ni0dt0ZTpkie5hr2wuQIvQvzLFEdGN/pxH1GtkYa7fHMJuk5Cz8kY0WOSAg837BWbXpYSBhaB Dtr9fAJrWJU5uOnVqGWrGwClvcUM1OCch7ASABHFK0F1unuXD0WVfQeZlkTWbUHwVXXvyyU02rJD BwtJ4gO2z06OCJoMXODr7noUrWuCt97+Ul+reMLoAIpO75DSPxe/yjkTwL+rr82m6X/sQB4RvAiF NGe/nP91CeQ3mAqRPQ90LGAWJ2ZMAAf7wvLJxp1r+EatWxPA7rj22mk9ey4OV9Wob4fBoGIDgFWw TULSx3gKBwqmv1MkMxlFIsud7BE4rl7kpc4ee0qO6EVaEPtIvx9A5HvUjQFd6fNf6b4LErn+kIdG J+s4OPvlEgitxpdicNNNcSNu4w8AmNnmCUAAaCYlUAfIRqHx7R+rkVz/T8K6x/68spNGhddhWdtH NBxxhFKykJN8DYxH3WdAk2yc1z5dj3NBOg1Aihbe/AcUL/7/Z2Vi7wV0m95a49J3p9/46RlhNiAt nlc+QOxxOSN9Dl6JmTnXrbFrh7oCKkQri8rYOPnQHMWwl7x+7ggUmz+/cpKqiEmhgJk6nDZIx+Zr /EUDDGItJrTy3aVjRPKB8rUdJ4pqwS3rY0JSpNPP0I0ON46f3DyS2DPCimAezWRAyG9yxe+XFaB3 utNF4OXQARyU+jKomXVvUlyB7s1JgAOdteWiaGd+lXsxIQtJjoCCpUFitQi113u2VEoWz7ptP1lI rNPs4fQB3LE9yQVOe/cFjOp7zA8jSmV2KHxd4vt7AZPtwvd8puh1xX981/8qhIw0Acnf8GX4puRA QxmSdMjvRoZAzM+V+wj+1mfRIf78eIyeFJYkvQKGHtucOG3YsN4OItrKsTnf0TaroCA/5lIKPwPG INyZpQ7WlSMjn1ghHQ12lIjzu12SA9F1uT0wcFXp9sootqoZAI9AWMZEmYgnbP9Bu4ys7G0bR/cC AOrJpU/EXIaUNCvzlap8XfnmAP4M2QkPlks+MtyzSrdSTCO8j22O7FquiLPfCzDVNCDVWnchSbH2 5GVYUpqIt8NfU9ii1g7VCBCqDQ2ujJDUnDZEZIKhD0nFFJK++BMk2WfW2genveH569us7XbLcyEF ThtavfsztTOorzsuhXJ2Llh/SJo7FDnlf61QKkVoeRaVlY3kvkMwYHMp6wCQxC3IJFN2ZetB5/bj wBmnve/Q3t7AKN4oiHVjSla+dhSxkgLiIMPWEkKuF0F9rdRF6Wp3wBc1MMIzGWagU9zhfOgenh8s bf6a/UaD8ZtA248khK7s8IMYYi+YDHLvFwyYDFZJXT4/GU8b0ZXoJzG5beRchzrMmBsXjwckZr7H EtkN9OeU80rjDjaI6Rt3dYg5a+dbW/2KWhXK+xV+2k4jZgG0V5VcxDGG4tlEorKbqFMHNClSUHwZ FfW8FLNufasS9SU80WXeqG2bocnKDHyJBQoiSx8z5t5mRuRWg323E7N+BWs2P8VTteo+PLMRKuCS YdHM+0vpI7tIGB0GszNIaCjxWC6ByTHpeypd1eZGLAQVAqxqBLM/42vGEF/RBy+ZqGANL15U2a9I zyRWKKnUWWMQ8xxBaisYjPKVy4PIvo30lXhcs0zVkwYCjHPbLDFKkyafxehbfp+vAxLorTpIJvo7 LQF3WkrIFO1NYCGVxBszDxR2mFEYaieEBRsFZy+3KpBoWPwoeHL6YTtyJpSLKRAadJkUMBkClL3P laSraPlXJkmyQ6cM29fX1P1ELkjhyppX0F/31HEaoxrNYlDytmHpycTMYwtrTCfTxWLuzShVK/oe +4/Fohp78IYcmsEgA0kps+SAS6Ie0L41M9SD+k3u3VZb3+ZpokttHKydzRfR9Z4WXjjmSHbzLHss O7yJbnapGq28U/A96xZQehBJX+2Vo5WiGaGPF1oVtj6+PcQnpaQIWgAxL0GqrESRXM8oHHoxgAgA b43fS+LErc8nhMwMwDAto31/O1s2l6Bk2NIV1d9QKsmzcD4S9T4HFEHM2hiMZ5SI97phk//shXtf Ukudled66G/6d9y3WjmGOL2fmlSP8nPG+mK+OR1TxvnxujF5VTIHGG33UVf/mHPOSU9togLVrOQS JrPS6YxO809v7ZSgWlQM8/jRceKvv5lfcVgOxtXdPICm6n5y46XLu8wcODcAjypcheDmRgCjXuoV whhg2qjEzVGPzjUDr0Dln+0tQwKFbiiPepKxyYmOkNKcEbuLC1ikfkEMu2qoCmxlGoJ9pB3oyP7v BYsqTUxvb/e0GtlIM0Ww+dH/q/S0E1bz0A1/VF6Xtg7VXnxpaDC0qovqX16wGwQwvnnrF+qcrH06 lLZK6cJS1aau7YwCp9cvP6y2vi1OhWT674/BhvJelHw5GOuxDuXn0T5Wac1lUsRs+FTswSzCAC5V lceMy4oZqjl/K9zQ9CAWPVdEyni6ppT0EtOGwERoIkSPYoR59QxdFlmS9s9Ja4ujizeDJHxI6mXd eJGgBHN49zXO8ms91BR/bLL4/FkoAHV+3edIDCMTV4bP8Z+V8AoNAwEY0f51O5QIpqZ5++ft05ip UcyGQR9u+Nf/oz1yb4j+KKz+vXRh56C55/+sYBb5nGPcW7v+Yusoj3vOjotRE5NRzTTDYC+D480x 26mcxRKwpiaLNfovnwsMd3mVILJCI5khd4jWJNfPXZFiBvgzCO7tKBs1hnmnVya4HPhNYenaa6GI EK4IPdUSDAZbJHHqYwM3dOkHGiFw8NUj7yNSzW7B5qs3Emcr6wYV5OPM3lVgabPpBalaAvHxUzNB 2bvs5to90v7TH3dXUXclZ/mMki3RyXsbqJok6rFfTjkHRsLuAr37d7sus7160E5GFaUGKs/4f3i3 4bPIfDKzTGfYEH9fUpEcwI4F+lJBJV8zBs85FsJxY8/Z8baL1/7we1CQzfBwb3NH7coEJs5NsTHC bbR8nTgnYeYHSaksYfPxLSgLAPyAKgONjzQnviOGxIJ++X9/sWli7oqmJZdqKmMb3JsCz7buQaF6 0kfKnoPwTBirccby0UPQITqNRiekWf0XEn8ZqwFFKeOCEhgHirtMCyckMnIMzTnKRjWZMycUuM+F 56sOm3lHtkw2ruBNSAzqdIaF718Ad595vZjJSoEPHErnpDysnK5sn/LSLoxRdFyyYovmZwQMmpJ0 FjDqgSQHxOUreBGx+nKzix9Nktkq6Hvr3A0dgAdhMLQSf+m/i0EGtAMAURR5Qh3INAbasFBX5qnB ScnFbOFD7ZY/0ulf9hDNupkKtGS5vPMkntED1mu19LdVa4L8FdQK294J/mR0ui7NnppDxgfXrH4+ yNS+APF24XgJqH2/sjGCcc+ym2COaaCHgza9vyopklEhhUWIslvTwfTltdIF5GqPT9DS83S98fW1 fX+bhKi2YjYzbMl8ZL13wgWDA8fZ2LKe5lM9+Z2JPgl+8Vfnk5f8s1qj7Hiwe77Vn92DnaEOwfd+ t3lbfyNjhGzgSVO1mf95v0caljj2RUiXBI6jBdScWyn2ZAf6k39Cimsky3gJIC1SHbNrcBRHJyVJ PkaxRCCEbyZNsK8y7B6bbkZGixgTcjyxC3vfr+xrikS160N26bWwmTds+TCVPOqZYy9wEoE4dg5f 1xNkfXIgb1fSuUoag5lQJkupsOSFQIz4VyDp+c9iGaU2olXrUhqm0w9GA3mG2u5BZK7d79RivkdP JhjrSWylTQ7v5VMdZzIzWx4Jw+vvhOKp+D7UQdsi15eggY6fZW7QWJ8JmbAjSOz3e7IAkO98UHNT gb2+8fk3WBlPNB3SUp3w/XUUeaI+0y86kXb0T3syztHEw0goTklHDWIgm5sreFyjbS7DqyZ7xZlb DNrwGSyh7dQLK0ccwKKcbXJXWmkF5ijmJXMD+wAniHTA66hBlFUxoGLJLues+o9JSlmGpeNkcaIz XnmE6vC+ZqRvY7eBgf8lLfpdF/jiczZayxETFacAEDPAAb8JaY3XNZrvnuJDQm9L8OS/0LM/uuKt aBWvO+Y0Qx35N8uXK18IQ3AkyEZG7zUwC1p8zxnIX08pReeKb4CM508KQrHA4/WxnZ4Reaf5xkco P4teVSW4MJAxYRLwkTA557k5KUNj47r7N434MLWdJGFNugyaNfVzZxZ+H4vAbvY22JzIdgrvttFK 8ZtO9revbdDu0uGzwHSI0KUedHAURy36Sl8tOXabrmGsoGkRQM8L4Ilk1QpMi40O74oqvp0DxjW7 rdArymNUH3PLIXdXAG0wZ42pZxPGk1sOVouRkc1e9ZzWp4rvEoG4j2slanTFubPQDqI6yYfZpuSv R5afM+JJPu7lm4OymMrZ/iazIH3CQIDstvgV8GYVZwnIn5AtUy4zQJ9Pg8f29MXyHRnfxKMufeam JtHPmFwvYDTwOrQMlj0S6cev30oiZptpLCDgvFFKDAEcjUDvaG7y5wYJ1Gcz5ESr2MU64hBKjK9s lwEskPhUgiPEVzDcUpZ0vols5TURG/08pQJdYiJJ/CyQ5plb7YpiV3fXPIbHWdGIaHI2VGqPd8TS IwWcHvnu7OmFTGpgcQ5XSxF9prGOjiXhxy4I+Ilhfnmbr6Wgcc7kmuIJ2LjYyTLb9BXNiOAFhEKB /324c/zDdg/gVkBaWz7tNiM7AbEih6PeY2X43RlXmWd/51qsXjL4mX7+OL0jtfxGlMlQQv95XlN6 wF1OIYnovvHSujB7zfHlG9Ew+OoZ98ZbszGsybAVtkIRPUBmYQh5LeJnlprEVmn3/LJn3tGEuU39 jNl1wrhwO4hi9fj8RNwYPEMx4/DhRsZqv3jHDq7+BqE8vdTIsbFgsAfZqRBeF3S+hV2GQ/sBjF6R Zcv2eT6BG6VtyZJ4hvrct1gDyRI1Cmr5JFJAXsPsogcN5Zdg/KnO9jI0KQ2rSrOEvUctX5lXp7iN uTMl9yjzHnnQA5IKN3LiQ4R9T/DjRUry7rg6oPB4dGCAvZLeChJRVJH5iphmnXPoi4KvvYJmOuGa UAPePJ/BIwxNu6oYup5IggwCsOWc0sgY3ZHjQvdGEjlRDytWEq49KBQqe6SxSzgAiUmMf8CdStsc 4VzkslU9zr+1pjXwscoeto3m79Ya8N6enagkaUctO83pbDvbvS3gETEw6ebFSZp/j8g8v7m2N//x eeNvfv9A5bOdMdW+dFBG/tHrJCy9UFm5y+GZYLT7YVEvwIaHtVjIVdCSksr/hy/y+YG3tJst5MvR /s93X5gHtsZYacCC8jzZbTb94G9Rb4YXUb2fbB2sVhTIBLS1TIIn9CH/FkbIcRnZbPk9eVlRn4Mz VKF4DnZhg12kd5Nm31yqM5pPu3eM0jRRaBbZB7zMWhK0T/HlAuiNWaLoog4k4othY9iRnDqOnJtK C5JG9hzCUrIb06QhQn/w0kx/5bCnUTqeGDEJsZCn6cjHz89e/kpLCpe+fGWuxlcoVu5uBigmx5ab 9qH4zZbJUVMD7dgcnq8rO38OvC0DAbE1zoP4UnoG0vizr3ArABn/qyMsc29plqKSiygHa/dd1YUe bTMNZgxJD5ojNIq+OlxTQFlKpDVtD9vTnFPmPw6h7qIiy1IkDd63509uOgYKi3G9nwwlGC4vt63p oxgYCwnyl7/zhyKNRLMJD88Hs8vG9qaG4qB0DrBTMka4R6MHKWqHdFDAc9dcIIiLpLqExbDg4lJm PyURq4MUqaTwqxUMWQqXfRMUXItlfBvTpIh0jjUzNuRtyJb7ZtHGkdNk5NqX81WAddo2WDNCLYwC 7tSAl3v1Y/1aoLIkUMqSz8b32kTgo3hm/A2WwrWy9mXYzCaj6VEuU4LlOX62kUULUiPzjyOEuhBD YlZuIyRU0mUMWkYclPATNtgNcuAfAMp02KuTHZhYVLNQ4D4aOTphCsNcIlgx/iAuAAILbEngSPvy sS3faORpKsKEKm59l7SchVP5R0EZVyqNC2qyATKUsrsiwB2mWpoUJmsK9kBNZx45mYc/kr4KH/lq Hx3oXVlv2+V3+FW/UoABFWmU+I7p8QIVkHZG1N5PmVWHlnHk9zfw4cMuHF7N6KG1dn6qEQm6JIFY 9Jw1AjcBHK+Cv+X2EIyTbTrnCVRVREnv1viv2wHGjkXZPqJ6uXXYjEeGBJl0dSA3YI0txJpk2Qmh FOkneyZlGlizpgfWlM28dYhtLIDdn+K/L3LIeVhxjlOhu/ju2P8S2z2hFNmxy1Q9RPcXEf6gjONL iFI0e8wBDMITLAgFC833GHYSz8iokD6uzWx1hSB3hZ9zp7dR8fBHVfuMfZ3zQcJSPihnv9nGDyd7 NaZQHyXjykXya8BbodyjJUOkf9nPjbHaRDfkwTdvLbAIfdu6w1BaCdYRBp6ncGl6asNtwPZ0EQOM kizzz7Oi3hGm9xFVTrkjYNhr7N6R5my9pBqNIqbl6OSR5o08z4wS1hhb63X1w4RLKNHt+ySQd4Fm SYCF5AFvWJyFtUTTnUcOux/3rdbj19RWN884FQZ4cQTZ75fgXicfo7vPOVuDTHKddYps3nfdG231 wQAEjOaYuMK2RnkuxXhQDHRR5nAanOWKYdNpUcEWczv3LD6zFXKpnMe0fqyJF/RlZk6AlCeta2Vy ZPuJtRx23MHF7/Txw1JWHz73CNlfKkzatklnhIb7q7d5sZww+PFzWeOhyzSAxkCHARk3DIB+/zYa xQ2Hk4kgzonGcUHrNcrpBCUkRwbZyRKxkGOwRo2ziQphyyCNDZLGvFG5b7aXH45ng3UR2/mlfxOp ooHcPLmj/u94JFz6VD416xnsmsipfM47VCyAsNs9+8w0vvzMEfIRXfwMccmHQgJXHvxxDmuIlOb+ qaXl2dKDteIGTDoAIYN3iOUU/lJib1B4XSnXM0tRS65rag97blVCWXuBx/jl6nCCwIXPycPiHhGV UeiSxFgJeOBG9zVKnYsu5PKm7/rWbNGq9hbk4xlWGKI+iKvwLbOtfflf7TAaG2UAF5uT/M5+1AKP OGKcLiQWtUdak4gL7cGAUqGqWjqi7/AG3r3/wYaLYW2rn8bhLqvmnhotms3Uv4qK43PijdSw0X/2 KEPgZQUIWW6XHZeqcG9fYh1GaWjwgjJuHNZVRXmehZAK6i4XBqeHHgiZGucBEnvFvYeDnoROsljT 9MVHZpSOez4iqMmJumUKtOH0k+t7aCyOk994CsVsnbB2Y90n1vJ1ZHguPSMfdd3/8Zd7suajYbWN vXCN9cIXMhl8jBZWCbJxGnOBrcPl8aZXSerbCOFA2WSNCyXzn7PgfUYxrzKKQqF8fXyjViQHhamR +UUA02Y7udXOoyu83yfAkUL4pwG/TEUw/6o9VLXyAy0AMrTwt6yuoiW5Bkc1QxhZJCl8pT+2fnmJ xbkGhrT7g/jaSBxxmwqxQm98inkUQQKhKWYOxmNKczsMPRJxag+EkwJBhRqj47W1ToW12LAkIIlZ TPKaP+LA665zNHdCKvu0DRL0AzFkhvrNuc/Vakp8zfjRvT5wP22lqndpa7nmr2bqvqB8MPIbiSjF l8AOtalznFFfV8vexxAuREBb2yqRhmPg+Cc8n/XNIdvj/OMW195MOrjDeQkZTlT1j3fB1ISdRK5Y U9fm7xkFZrqPKkX/7pVjOt9+7jzc2DWZFY2wLHj5SKlp2NQhee8gMYSfZx2JVC7Fx9o50qRYvPhb gjB9k7K2BVOGkoVcyjz3sz1dPqJa09bJn9W0uyMKxeJR0HC/ZByMXlUpwX428NoGie5PCAzs6u+e vt3qxmInrovot5CnhkH29mY12kF0ASh6VqO4LKvUgkKptDr95nhICx6zwqzXxs7r956oSL3XU04a jMpD3MKmLVNnft8HGiQn2bZ+jLcud/6nt75K1mdbZSQEPSfawR0cvmc6RbCjvmYztfBqTo9CLZmw AXrFNU6KcBZofQlkNXWgG6zenfwiZSWPEI7ehU1gJ5dbBilgCWOXLdhFFH3c37yC9bF4ipjYhvfI IuXAdM+qjduJ3tJu/WAoi0V+3qkFZMMhITK4mTCv0JvXvv55SFtCzWO0bTGtWIStFVsWHRZjM4HI r7YM3VX2/ctczSTZHOukoEfosiPDT6tLkwAMyOMzlfI4jtwZ1j8/6YESWno8JT67+gsEqcnJiC10 4oKAJV9ZhIvPHA40rRdtZzwULTndleTzaz/Vw5aUgvJQvvveu3JNb8vjdsEn+rQTEpci36211QzK fk6DrbVzdRSiolRikCdqey+9+DQBgd/Qjx4ezzm4AAQ2xiqKuhW597U7fUsGdMudDp84H4unY/ls RTSzMYsZKPFOdKL4tmZgx894QvZvf9SpGJ4gqMEYRyqBbbfBKtzUFO955bdEfbKrf0JbFCJPwxbp 2Nf58RZ8KrXjO5jUJutM1e8C35vCZul+DutbDMMc5OFp6hJaai870TnS8TGd3w3LqbFWunHX7bm0 0JipfF2aTaLK+rEchjh/bBWEh8gIjeOwZmBkV2tEMxY6/i5tANYurNZPh3PfBiHR4uu5TMa3rXJK iiK8Pq+JGOnXW8Rkr5s3sdeDbZZciVY/IXGTQLgHzv5VVrJSOFWBDxewf0Xd3wQb7sMWu7RS4vD/ OQV7S4/J/aZtwQfVevMZuD4jDMj51+L1NepVVUFml4i6pnEc2wR+xiZhtqjAk5m2spqgiEihLUDI wat2kR39gJllzCehik+rf4pv1vM06VI/q72Eh69W8+qzKSTGshKuaTeBTRjDYS41oFJLpZsM0LcO +VceHA1cepJu/RKlzDvZm3uXtGQilH7lrCFvWQDPY6Iuldi//AroMRmFM2Tdnl8HhtDu8cgkvFtZ 9208QQETYLZNkFV9A6++ioxq6I+gcQXU9cMOjj+8yaA3u+p0zCz9xt+19dypL/tsZAT561zGcU9/ UC85WYgloE786Cwmjz9nxGwPgZqkuGPir73Mt1a68io5Ko1Xj8zraMils07GY+n3gLYBFW93th65 qPLJ8ByWBNUw16MUpZYxYuw2BaBMV4U6DodVKjus1K4fwwK+zZkm3kL4tC3thVoJ5sxC/K9XE0A+ KOB5ewqTVZvQJf2KY940/wocYvXe5ZkizR+0yTq+rvNLQDOTAxLaJnYKihWGBlLYGHMm0B7rIwQ6 srbkqf2R48h0kW9Ax+Ob5idUlhbazZM4GjFjrm621WyN0EmmLQOsGEgRxU67ur7xmdMOnXnJ6ivr pAt53L2YgaXsv6L7q0lpFkOMdDnZLEIENgMSJ5PUqMvO+8V06WEbTpCl82oJ4JCDN/XvL9mrTQLx 1VXmK0NwFy/GKO4jz7s/t1xeCJ6+vjBE0RdMSoFGUlsFTxcIe+m0p4AUeKrqI0cuP+0icaDitrSO lEMtTYKwwCh1XUsn5Pzrb70XGTxZeuQW57pzy+cQ3s/hFyH8j35opEgu1cCt95Hl5SO6Zvkiqa2z 2tzAYIzEJuq5JnOjnCPbNJ+rOZxrib6UaEfviUIj7xfAsM+2CZ6VBT3Ya+Q1mfBxlRc45mvpggax f7hlx1yqnAkZMdNeuitmNHaOu1xazw/ePPE1tswiHQcRlYjT57g5Xqu/njlrZQAKSnraPxpYSiNL TwsbolKmPKv92NHx5qHJi7WKXWZj5u7MHcXiLF1h0bERTfkeDs6nMpg0cothT1xYrvR+tW4nDY7l ZvQGQzbvOLAqs02mhXL7yLEOL2dPPYADUz7p5YGGHlbrMOe/Vf4VbcROpUSVYqRABDAktTO0LVT5 bbFYKIYTU+d8LIEbsHDDH8c74fTDeCqtiT4NrO017/mrtaBkl8s+Z+Gv5Cy6SAEt1Wl9w496sN81 Qz81lp8j4JXLEggtNiRu8mAcPtn7T6bpacgP3bFfOogN948CXE4pLaTNOWWZLVqS+O4IV7EJvzw8 AGoE9ykr/QcA2R42nAiaspqUySzkmVf8zuY5kGqc3hHNRLbo24BeUuzg6o+2oQA7d4Ys+4JkkWlD /7Q5+z7USPW2gS4gLu9oZmy0LQzTTO73GNsqkb1IdEI7HA1++stnpOiR1HfeqYpEqOQP86idtome wei6FXDXkZX8aclsLwT+sbdSPKvmdzCoOGuvkMXp6ejPHeKzdGXlZ/ldzlBUS3Rz6N+yuEEUMXa5 7hLBgJTw/fM82X5W8n0GbKohZrhhd7k8jyDyNOyebDdvQ9JwIB2lSCwCWdco6n6U4d/ohUpfGDB2 GLRLl/niYo0LsdIodaeD9QrVoy3EZTVofZDRZdvJkNYhrp91tdelrOK0KEBPAP17gA9Ak7VWZekE tYojUJAUOr6YpziK/6xGT9gezS+wHCMlbKmnPIrFtROVqXHPCze1lgxLCELRexBG7jSyZJwsKVPn nk5nTk1bsnKT3i2vLtf+ytITc83LvBsVlEyGY0BCHCdBWqL4vWO5ihHkNNVtocseImXayUWKjkBu x69IUj1pMuTc4aeF7XyHTVvhM0rxWiEGEW3iLbZLLlqukWvuu8iREn5d6T1ZN782i69s6QyBzyAs a5/8o8p7htupBiEGTwxKdxrSR6WyxKNG9QFugOfuRgYM95AMF0XFmZ9jjXIaV8vBF8woU9JTEU9a qg934M0/FTU3GwUyTT7a7zLg0SyeQb6D18iMYoZL9OxEXbYYl9K2Yjruk0vAdlPxJg9OdddSGbke UBHk1DTprU+YpL0N5X6unzTzRsGTdEXHJ7QnFTT+lXZhHCBHBuHc7I2LnDnahBs6f4inOMrFHdQq dBYImy2lqbNNGoeoMt2vGZNiRWFmZvhi7/BLKJpfML8qpOqkLFJCtylIpkDQmrz/zciZQemTN3Nx skZH0+EzbJFriEzv7+pF8pe9F+b3/MGLGYRnsxu9YwH4XFruTS/LADJQhezzJR3slP1SNlXyGw2+ 0P+M1lgHUPyJbJU5YOSCiQtco2ZrH8Lx/4ez9HrETzD8OArsZ9WZtgqMsi4ZccPATVypLpr+EFN4 GDPRYA0t7hkon/yKyWjIx/6HLonRXTu2j4lUZu2Ry4GeHO8CFe9ofXrPPRfkzkDFeZ4/k8K0IIWO 6cHDdOduuOMw2CQRZSOLqnVy5rHA252FOHw8NWFDCrzafVuo0lra5piGosxOdxo2sq515SqAORKW HBTTkFmrNuEAi7FIx7tRiInPrN3M3cMbFBLQF2xVAb8R+2NGwq8b6daCCu/ennI9soJs1AjIoky0 9pZYVnWkPQ9asck0MrpBb5wXADC3PjOPCa2cc5Jgou/zaPHVq9R4i3JttH39T/ImfDUzd3mTHgd2 VQQSBniBa4tHg1DVy98uT2n54NO94VHr4WIE4DBon2qqz2Ep3ubhnKD5IsEAUuhyyRjWlOUjsf6o 9MDHMp4GeFSKPa4xXp/fp1MsOl2ca41rQ5p7ONzeAKCaSX0rHKBrVZOLGljZG4I1c/8BDrI+c1yC EBr9VYzDvgSgD6dfB5LLJPHo414S4Rm73Y7xl08VjMINc4maHGiC+OT3JdAuevKyyKgligQh5RfQ cjvMI8iF1VmqF0aD4XjfiUZwk2Ky5lUz/IILfJN0Gl/JPZyKy+9PM9pUz4MpWormURmXgXikKauT tT8qTKIbIUZgkvhhIUdTctCSeGJRfSMZ+tLPEqiFXoDIZxX2a2TtR46Yr4tF+j33meHSnK4rnPcG W32jYsa9CUOqvkN13kfye5ypMyv0+SfPVI5o/ax21w4QBg8Wb5GmX6JXveR1DbvZC+PG13667AIC rzmF25E4WHJQGJOAXkM3M8pMUz7z7dTsBz776HVmZjOYkGBiEMzqbWl+RVEjixLwQKY5iE5syc86 Zj9uUBcVi41Ajv6/Xe4KHfrcPhl4qUq07Erl5LPs5dyURtXIJBPYnuAeamhSQug3Tx5+ruI3oJJr LzD4xjm+F8YN0brrs1Ek6J2z7vi0uMc8JWhy5k/msZOlqdZtsh3ZfehTc5sow3K2EtMAx+kkosVY p9xci9QxbY5N9MWNxRips0b36qhplLSTpo3yQmwutblynQg9VWUjs2+xnoV34oOpVyX7C85l8fx6 MULJheTzr5UXcViSSCOYuToa4uV76jD8plP8vLYwz6QyDwkeCjm5skDFkMwe9tf6k60MFQi3dGEu 89AEnplfnMnpgBMZkvrXbYR09FFMIAiyvY+xFhr9cC+EQYQVk9+vFWu2SpzWZRB5ljoCOFeHMUkn Azw2O8bJWKwyFi6/bb6p2gPVW/seBHiuGG0OvbRHZ3eR4ZV9HO3JzWHpWRsQaBUeGTzhs7AxA25f FX+JNSkiJ7wwiyjNI0psqRyPyJ5pZXbOtQ+P4MJfVTG+JZOvjG2FmtmsoY6YahD7MIp3oyzDo+eQ Zb7q5OyYR6J7lvvJzZO7Zfh9cnOYEdT3eKil6iRzO1NNFvkmUN7JhXEknceL+cVu3tAWphk2tKM4 GvQ2NQgoG1x4OWjQcvq9eYGFiuMYgs3z3/+IUgfDlSQmxyi0Wyfksbw3bGTSqWKqpIwjFXBF7a5k zAu7Ep1t8J6HB07J0HiV6rPVXU1KTqGtLoOUk4kAo/waE4htcZi8NFUmbNOGuFt0YKn78SIGQbpN 7KlE2tYXlZeWg/blRJNG/eg0Vm13jRVrqiF0hq5MsxFxKJMEb4W0NyyXXPannPErISVoYNNmkpCF RmsILfKhpgj7a9W2kxx6uRHm0BUd0D7bUfb50sSjI/H+UI+ijIVbBkr5NtX4h/OFI9rxxt1a7aHH FIZCqSybDAKMMqH/bNysy8buhfVOYTN61RTG2lqKbo4/Uo1XgzGwMW4oRF8UUimWTD7vIB0i0pQP JEwBxq3mtpVDCG/65IhF0JRllMJ6QEDcNYjP5cvbdKnoz9Q0hvKSEgKkuo+tDfuSI9CE5eDGk3PF HWmOP7vbR+ZeTGFX/ITWkRRqwPoYwAeKmIpSreUV6Nqo9csBwZ1mEtraL0+UqzL5N/7TDQLE0hZh 3qd8c++CKg6NsfpWue/ydEjyFp6Qyxfildxi3UoNffC4M1M74FDFn8YVfjJSnmZDY5VWosxV4BjR DEVaXJENwHm5iRRumErKVne/OxkUnWzPH/dhrE2n+t+/2ix2cUFFe/WVvMet8KY7WaOdSkk2u60n GHtFekkVywv4RAvNsqoEhpFfZqRyzSP4Na3bbcLxnrXPXVHyzuvf5kOk01kKm1u3mC59EOuhWOnD RhUg04dx1wc6BcdeRyVHZ5e0Q9hkfYtNiyDYfJ6CHy5AMmBFpCm0cSsYeQ69jG8sraTrE5blfTp4 Kqw89qJWiI2WtFChSrBqu7CndV91P6/SQHnBOrvAj2CO63tEfJ6kMwH2eVQ/FwkULRxArzpQT0vZ 5WgL8l4pz4IoxdWsEjoQVWIIjY6of32DG/iINIoWmvO8uFB7Q57z1Z/So0R6d+Zq3iYpZH84vNLi 24miL9kdDRSWmLIx85w0hSAcN1wJdj4cy8jI8ycG/mIxyPXBiwa2kq4g1wfBL2cCT7m9Aq/jLXKF jNFakDOu0gTp+HGifqcBoIqGxSkq1gQMZLO+sO0h8GKylJZj8P5zUShhyfX+HbaDeM/9parNZOsj Ku6COPkGB+L4XWRhVjiL84JttIOFdoUMDLAhbjeoymhAfA9PvxFEM1YEdqkxCXfuEGRLfSVZJHZ2 UnY7xg/0Ytyekf7i+TETWJlpyjScGYrcNIx6yqWzUPDlN6hhDus+ftQjxunuG/gkeaW8eBGxFwJA kD6gu/E8q7ciio3/F02A8/bikc9U8OiDrmZ2w0ZsuVOSa/53jorvAcBWR9ACRAyajsCmF1GE4HeZ zdJi99Bcn+xcfPWbl8jYQ7e0BQmkN2yvymKRvWOgOYBjZ1qUJTnMnE5MO1pr2QjBpUAMMHFkZr9W YvwFkZfeW3A2u5bQN38BGcvyInJIrHIBZwyyCokqhRv0vzlqBA7PkzPA5succcOsaxOFCWhz3gzb OEPAmvc5V1ofHhO9vJ/Fg9yDy0CDsNDiit8d9HyjbOmE2610qmC0NaBdswtPh5ubk3qCG5dvreYk T7beGlkIfuFNdzGzUHMH7lyq5Y9y345T9iNcC1rj2DVKlxVB0/RayzITjb9R7Qt7ML8o9Oltsiv8 UIn+rCzWbOg8HnoBpg0QSLbBOW1ckrSGFmRQdAbNlbI73yTUobmpIznz6ozFya8qI+mTyx6Z60KV CDRoL9BBQEv5+0YRXS3kHjb04h2g9/73nmkj9NfAFkvqR7anqIcP8Mj8aAFyu5CK4WhKfeeoS36E nm3CtgMF2XyIB/zVLWWwV+qVrdriEwebHtVjS7zdNf2/AO7p0gre1fZ5LLomWE6X3F4BQK+wBKpv QQEp89InprGLc33o6cCozIEsEDuGocv/IuzwhWNU4eWgK3zHi/L8T6Y5SOatxRshfukKtpjLNle/ LiovHFOWnlF+WcRplOb9lmaCJJ6WWTOKdt0Sfjxz4RdSb0q/AOUpVrIB/6mT/3PD8l1ZVv8mcMMM sK+J6f2Ex2fh1BNhpIQn0H8Nl9MzQSu5WQaGlQ/IEHFoJJfujFUMuxZg3mcktm1T7hAqOcTFfHil Z2ySuWDEnK1P+0kKFNfwLjCmE+hGubT5nipjETWvKod0USKfgou85sjpWVZ8xjyeVyBNrkgnZFyz C2wNclA5BmNFua7p1Buh9+Zl23o4v9TmTGIE0IelkJyU20EVLTxBInAQQuwlFG5xxeGV8FYELwmJ Njk8ebnG4pYkwtLupo1PjOsXtwq+svGx5opzl4EkoYBYy2AuZZac6CkbaIJT5gFqSy1sD76Ex/GM QtlDwPUxXzjky+lJH9KJMhuglBLSuGODHkJ6aq/9NJJ0I0UYHizlxLeY+214mqvvW9PUlC9BhsDf pZJCrD1F4mX3VvUopk4CnQV56NzMA3aJlhH5dzMxIG+ALmRLCaHotshKPp80JNZ2lEK51q+7YU3o ZwhNaERQ4Kebwd0agthBXsmVtJ0y3mA+7ur3/RXhhHPVvHzaAo4FsYuKeWwwEkqifaSb6jW3LYfd 40STYh/QC965Nar4SLQzbLnGTyXZSpcULDpN0DO4mle1FVHqQQ9rrbxYh2MumkdJJ9viJezUw7kl WqUXQTx6ZGxS64I8rvRGItRWeU3/sHMo4VTRTg1I0tYRYqRtF04jQV3YHvLzVTB/GxaZoSdQPu5s VeiFkmVcU9HHgpeEz1p6EhPpS/RdmRKgB9c2fxgUNjBi2qQ2P1+a3AADmxwKyBz7WX13A/K+q181 i4bso47UkamSCeGLFEP0hGQJPEdcCtif2jtf7eM+a8T1yTCXnxXDboH9wE3xi6/uSMOk307hMih4 rJzjwOYjI5nMByyCR/F7oYmuFFyIbmFFv12PoIqr41o43CPHgy0G3ybYtGZ1knQq+Tjcz6ET9KE6 tVLlUwbdQMCeHTnSfkHf9KQRKC5PzQ2bh6gOKPsMw5xoiMgqB42aopp0Xvsz4pg0yWimmu02tHDW JvYBznmJXecmyV+ecxHFzGhNnvdt6FWBcwq2QpxZq3N3RrCdC/plEgmgsMf07NIqxkcE3/pVE7LE pjXfJvnZuNJQyEMYZtTrb8zxi/XWLZ4NK/P+uXIoPNjVEdU7wg8TRvxQcPL/Hr7JtzS8hWQvk60U KXanuXwX/ZLjUiptFgjrHi5PHW6WbilC2TB5S3FlRvW59Q3b61KKMXH+fPVKf60kpup5GPYiabJH antCApCnKFcn+EEgk10n3XSsssvi///tYC2Z+sfjOg/YG91SrhCAq+/bzNyOe3F+HxtFUqcRjWyh z5cGCJPL5LoNsL01hJtLSa6z1HeLWvCJC6h/qqT3PuujWlsXSQNJyMojJbvcRtp3dL6ZMpKPDs5A 7FjQsOFTYhooH0TCqiEjjN6IJbAjvjQpiFIw5FLihm8vulJSNgDO4TU2urWogokAx5K3s9DG3/sn 49BOS4KPHLEyKcphfOjula6GynAHYlNynxgbUaVqU0CDJAr3Dw0hIFyphMAhvzLPZRxgkaiJJMF7 TWXwX3/bPWHnDhFESup7PHQTiw0TEroTyFjs+3z6BNB95SOyp1szV9S8J4aZVcHv/TmpdfZ6Wska r7eMOXxruJlwIiXnjtpTFYooXDlIC0a6NI2NwsTYevKwtQogny+zrcZnuvtGsOVW5KPaVyE8Fz9g 0VBQVe9zqy/WoVVTr/e8ORraMRS5U+Fckt/VxUbv8F/6cUzYlzqFneZvnhazNqFwwvc5yPjo56wq afJhGKMnVzk6sgoEFJfdfxEr99s+Ilg67TRXFUeOM3hPc9huhExhPx0e4crHh8WTK7bISI4l/662 g3dcNqfZVw+M3oHg8iN311GkwJke+/zMrglY5yYpNwKNq98Q1w2Mt0+YqzMcruaxO6El3E6BxS9a qZv0q4/dUJGi6EzgSNm9ylVtdm4s0P1mqUZwKnMsPVDzaSID1mg05MGDifOAFHB9p6pursLIG9rR US75j9QAIhRNaXdnCLJNNyrhTjn0IywsUSWyo6IeN40k4UF9LVm1N1W5IL489hORTaQZ8m3RyyM7 4jzTbDaK8ORwf6sKgJvxc9Iglz6+Jk0tAQoALILmz/omg6gv3obOazcuqwpCsf1lpf9WPr51j02B N2Ty78SWmaU1RfONEklEjTrqzqtaaTGKxCfiwTFgCY6F1GgnJmLV+rfaL3ObYOvuDHPOgtHyv9pB iMSdbSJ2JtOT3MJzLpNL6Hd83jzUnmGgtvP0fBdci2MB01gnaQqjFxdXadIiQD3QPDAGPNf5N0zN f9Dk/U+wpCW+EI5cIuBKC1LS1PInyDBfNq+s7IYNgsVrwkrCectHRJXcRNEpIxDPll1bd1koAz/t qDEkZzzDeubNWGgzHicuyr7LXyBogR8PhGj/UoKR1fhYpg+JY+8UKv16GHhxJKvq4A9qU4Gf8UwL r4Dc9PR5rV8Yue9SY8BXtYPPfurjKmZdY31ADjDNz2n7SfQSMvJ3GqvBLEJ0OqNxxsKrSwld6Fjp 9EiGgHFzdc1nQB9sAl21nslkx7azw1rF4RZydT+KmyeNM5gjz2k0l9T0U1TYUeO+31trc28iMUP4 GYO1PPy8DvGBMWCZdYp4WOHCrvbEbC736d2SX7rdUnUIFIdviLpaibcyr7IbLcLy9QMtBf9Y8LzZ YX9Ivh9qsZ7XH/tprjxIhhpsSQ70U+bh2fHwODETVyBBWi1Pl7Aku68MrGRCDnr4Pkuk46RDgH6F Z/Hxwbr4S8/8X7vcMy7GqmnhesOp5oZwN1h9ObtMVdyreCzp/ovG74GHYul5x/p322V0/W8BJOgp 0+t85yL27xpaLf/81Y2lVyOXbQLT1Kr9J+e5ttyTXwkbQlm/WXtJqnrMddvGKA596IoIwy0IsMWt 8MnIRuQVzS56KkosYoM/Ffh+WeH/kRw4oOCc/jojWebfUb7ach5kn2Dy25qhDhUrnkrggd62Pc/Y uNW07CLpd4Q8r0bc6va1lKEHhInSnGqhypMxoNe5uj8A6G8uwKF19H0X2aBU+By9aS8aHDJl+GjX gQOpMsPQR+6pbT7jA95GDv+waie3Dwysp6Krw0JIR4V8Nx1nqCx7GPXeXjmjkChPcDmz5g8Gjolb Qg0u86Cv6Zj53PVMXdyJQTsRBMYwOzKTE0Ero6/MHnNzu+s+qoGjD0UIMYnQfa3TeHMMM8uqjvj6 i3KVvwYcD8YDzG0nBTOTryU1CKuOamOUE+UQ6LtxQeNUGSx5QcgB3K1vuf2NJKYu/okYjFSVxH5J W/DnX9qF+R7WEUYxzh8lq2PU8DxwHIqxpv8tHILkHn6F7D7EH43MrtOd/meMdsde1USTl127N2zj 8OkEtjbLO8u2xliwgJz8Ih1fdMpZ1Qkm3JF41Nja+8ukNQ4hyblCM+CGoic0YVaF95jGi+tTaf9i d19pMXIm4SwU6SRNFMe/8iRADgKYrNhg0B1a7sUIG9ygzNdV/49kPRYRjwcLx+0oLQueaQPz0Otb ZNg9ytGet90+F48KDpgbfvCyeguPmPtFelC/5vXWwnTvLo4OBU/KXpFoYAZXfO8lAd3g9WFXV97x CKeW6EJGjqisx828TdXnvTSdmFPxtw8CrpNcQ9byzvfTN7PNAu31Q/lh8QiJGDiW0DHPdI3SMNi6 roIX4NITCHpcUM2X5UO74UwywIzmDsIalDTtmu8HIqLC53bEJgc65QV2YaGR6O5zSB0YuJ4sL0J3 s4Xj4C0V0WDRnwAK/IGeIlKcbSsYSel5HFUK8KibT0oDNskf76RMQdcKqhiMfGzmuGwWNZzLWLfE a/5vrY7uSoYONT2WP2rk/S9eumYso5BVKNFoH4I1akhwUihvy3nWZqG8N35pOujovFNFl6h2EUPy p3ahA+D0k35xy74qnmemRFmpXCGuOXySD/0G4ec5c2hT8mkOjJCkNS9gL35AxcfgmzqCdUTYpOvE vdiZehkYqRcq9aL3Lpos4AewLVOvMghqaX6+8DjUqvWbBZpLAATbp3mk2KLbsMGjgqTipIWTpSMD ODMvJ6sk7S0LWJpbuEawxeUP7w9kvj2EkY4ujqZuGzS+1Ar6Rv0TA/BC3jwcuuYoEHaFECF+W4rl EbG/ej59mFlj+KgDvPk5SopfIv+90rBsC1jkOnJZWxUni0YNSrElLRB9X/6zj8UUBzUOHN48Hwe0 dO2ZZTCbeFN0doUXQnJc1uFYERAL6wtjUJL0dLdX1Ul4Sqxxdm0UJGyGhIFjqdzp3ZlrNEekdmt0 LyKILvB5Terc2nPAFCjFbXhx++kkS2eR0zm0zU0K7X0d8caxiWNt2L3ePBvAU+6EXxg29rcT9ua3 ly9LWxIVZGDETXuWm8tBfh3oRB0UrY5WdAtr1LN9CbNk4d/T2/v31Q5aS6XY7ZDQ9XDAMmaV7Qxh wlupQBkB38J1dDntuspfYBKxMdj9qHxHGHrkyxONS4+XdKTzj+KE7lJwvByAQqpCdiBAC0B2rsCu rqC5tJhQ+aZchf1aCvyMYuYL/O8thTA6nuclq2VHWoq910frFCUa7fIQi8ZrE82aaE0wBB799v9T sd+G9EBf5g0R67bPvDhcl9Dpf+dogkWbqVSPe/Hx2Wb0GkhZveTTSVGrIM5gxoZqxZ93WPnid8cl 1rcOjVTGjktlZBAMhZhggV4U4KCQ5GFe6CbnwwpRCMwLI5GF4I3M1J/y2mbb+2cG2ytSQ33Qn8dD 45gc7HcVhnJN63WPTJqZxc23WsR3gh7nMu3P4o8tu72OknQCliUTw5tVeVpMutzXFH0OVg0Vh6QR r36T7PRtkdPsCNAEh+OooD1N/JgIp4gUvooLDYR70iI6cDVr3fR9d6P/+qmIenkOSX08GNkxPqZy UiLGzRZfZnm42W93hpK5mkLEt0RzXhzGIfWQTTj/KflpNsIrvOYEGCaO4EiW3wl2c36viHHd7D31 mtyUUz7Y2MHY64t/R4nRrLg0FCVPpQOgKWQUZa7uB06XKUtoYR4evmkZ5gDN `protect end_protected

mit

6c7a32c885f78d562f59ef0102b884af

wltr/cern-fgclite

critical_fpga/src/rtl/cf/nf/nf_transmitter.vhd

------------------------------------------------------------------------------- --! @file nf_transmitter.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-07-23 --! @brief NanoFIP transmitter. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.nf_pkg.all; --! @brief Entity declaration of nf_transmitter --! @details --! All critical registers and the paged memory are concatenated and --! transmitted to the gateway. entity nf_transmitter is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Control signals --! @{ --! Start transmission start_i : in std_ulogic; --! @} --! @name Transmitter --! @{ --! Address tx_addr_o : out std_ulogic_vector(6 downto 0); --! Data tx_data_o : out std_ulogic_vector(7 downto 0); --! Data enable tx_data_en_o : out std_ulogic; --! Busy flag tx_busy_i : in std_ulogic; --! Done flag tx_done_i : in std_ulogic; --! @} --! @name Memory --! @{ --! Read enable mem_rd_en_o : out std_ulogic; --! Address mem_addr_o : out std_ulogic_vector(6 downto 0); --! Data mem_data_i : in std_ulogic_vector(7 downto 0); --! Data enable mem_data_en_i : in std_ulogic); --! @} end entity nf_transmitter; --! RTL implementation of nf_transmitter architecture rtl of nf_transmitter is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ constant nf_addr_offset_c : natural := 2; constant num_bytes_c : natural := 124; --! @} --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal addr : unsigned(tx_addr_o'range); signal rd_en : std_ulogic; signal busy : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- tx_addr_o <= std_ulogic_vector(addr + nf_addr_offset_c); tx_data_o <= mem_data_i; tx_data_en_o <= mem_data_en_i; mem_rd_en_o <= rd_en; mem_addr_o <= std_ulogic_vector(addr); --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin addr <= to_unsigned(0, addr'length); rd_en <= '0'; busy <= '0'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else -- Defaults rd_en <= '0'; if busy = '0' and tx_busy_i = '0' and start_i = '1' then rd_en <= '1'; busy <= '1'; elsif busy = '1' and tx_done_i = '1' then busy <= '0'; if to_integer(addr) < num_bytes_c - 1 then rd_en <= '1'; busy <= '1'; end if; end if; if start_i = '1' then addr <= to_unsigned(0, addr'length); elsif tx_done_i = '1' then addr <= addr + 1; end if; end if; end if; end process regs; end architecture rtl;

mit

0496a48fdbd4ed236824656e758d6b3b

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fmul_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

722b2b97158fd9d1354d6d49ccae1ef7

Ttl/fsm_uart

examples/echo_tb.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY echo_tb IS END echo_tb; ARCHITECTURE behavior OF echo_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT echo PORT( rx : IN std_logic; tx : OUT std_logic; clk : IN std_logic ); END COMPONENT; component uart is generic ( CLK_FREQ : integer := 32; -- Main frequency (MHz) SER_FREQ : integer := 115200 -- Baud rate (bps) ); port ( -- Control clk : in std_logic; -- Main clock rst : in std_logic; -- Main reset -- External Interface rx : in std_logic; -- RS232 received serial data tx : out std_logic; -- RS232 transmitted serial data -- uPC Interface tx_req : in std_logic; -- Request SEND of data tx_end : out std_logic; -- Data SENDED tx_data : in std_logic_vector(7 downto 0); -- Data to transmit rx_ready : out std_logic; -- Received data ready to uPC read rx_data : out std_logic_vector(7 downto 0) -- Received data ); end component; --Inputs signal rx : std_logic := '0'; signal clk : std_logic := '0'; --Outputs signal tx : std_logic; -- UART signals signal uart_tx_req : std_logic := '0'; signal uart_tx_end : std_logic := '0'; signal uart_tx_data : std_logic_vector(7 downto 0) := (others => '0'); signal uart_rx_ready : std_logic := '0'; signal uart_rx_data : std_logic_vector(7 downto 0) := (others => '0'); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: echo PORT MAP ( rx => rx, tx => tx, clk => clk ); u1: uart generic map( CLK_FREQ => 32, SER_FREQ => 115200 ) port map( clk => clk, rst => '0', rx => '1', tx => rx, tx_req => uart_tx_req, tx_end => uart_tx_end, tx_data => uart_tx_data, rx_ready => uart_rx_ready, rx_data => uart_rx_data ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; tx_proc : process begin wait for 1000us; uart_tx_data <= "01100101"; wait for 10us; uart_tx_req <= '1'; wait for 10us; uart_tx_req <= '0'; wait for 1000us; uart_tx_data <= "00000000"; wait for 10us; uart_tx_req <= '1'; wait for 10us; uart_tx_req <= '0'; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 100 ns; wait for clk_period*10; -- insert stimulus here wait; end process; END;

lgpl-3.0

ee7e4efd33d50dc750c73f24b5769962

malkadi/FGPU

bitstreams/settings_and_utilization/V2_1CU_min_area.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 0; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

e774854ff2b9448a104943e4341ac93c

Ttl/fsm_uart

uart.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity uart is generic ( CLK_FREQ : integer := 32; -- Main frequency (MHz) SER_FREQ : integer := 9600; -- Baud rate (bps) PARITY_BIT : boolean := true -- Parity bit enable/disable ); port ( -- Control clk : in std_logic; -- Main clock rst : in std_logic; -- Main reset -- External Interface rx : in std_logic; -- RS232 received serial data tx : out std_logic; -- RS232 transmitted serial data -- uPC Interface tx_req : in std_logic; -- Request SEND of data tx_end : out std_logic; -- Data SENDED tx_data : in std_logic_vector(7 downto 0); -- Data to transmit rx_ready : out std_logic; -- Received data ready to uPC read rx_data : out std_logic_vector(7 downto 0) -- Received data ); end uart; architecture Behavioral of uart is -- Constants constant UART_IDLE : std_logic := '1'; constant UART_START : std_logic := '0'; constant RST_LVL : std_logic := '1'; -- Types type state_tx is (idle,data,parity,stop1,stop2); -- Stop1 and Stop2 are inter frame gap signals type state_rx is (idle,data,parity); -- RX Signals signal rx_fsm : state_rx; -- Control of reception signal rx_clk_en : std_logic; -- Received clock enable signal rx_rcv_init : std_logic; -- Start of reception signal rx_par_bit : std_logic; -- Calculated Parity bit signal rx_data_deb : std_logic; -- Debounce RX data signal rx_data_tmp : std_logic_vector(6 downto 0); -- Serial to parallel converter signal rx_data_cnt : std_logic_vector(2 downto 0); -- Count received bits -- TX Signals signal tx_fsm : state_tx; -- Control of transmission signal tx_init : std_logic; -- Resets tx_clk when tx_req is asserted signal tx_start : std_logic; -- TX start signal for FSM signal tx_clk_en : std_logic; -- Transmited clock enable signal tx_par_bit : std_logic; -- Calculated Parity bit signal tx_data_tmp : std_logic_vector(7 downto 0); -- Parallel to serial converter signal tx_data_cnt : std_logic_vector(2 downto 0); -- Count transmited bits -- Return a counter value that minimizes the error between real and wanted baud rate. function counts(clk_freq, ser_freq : integer) return integer is variable tmp : integer := (clk_freq*1_000_000)/ser_freq; begin if abs(Real(clk_freq*1_000_000)/Real(tmp)-Real(ser_freq)) < abs(Real(clk_freq*1_000_000)/Real(tmp-1)-Real(ser_freq)) then return tmp; else return tmp - 1; end if; end counts; begin tx_start_detect:process(clk) variable tx_req_old, tx_init_old : std_logic; begin if clk'event and clk = '1' then if tx_init_old = '0' and tx_req = '1' and tx_fsm = idle then tx_init <= '1'; else tx_init <= '0'; tx_start <= tx_req_old; end if; -- Default assignments tx_req_old := tx_req; tx_init_old := tx_init; -- Reset condition if rst = RST_LVL then tx_req_old := '0'; tx_start <= '0'; tx_init <= '0'; end if; end if; end process; tx_clk_gen:process(clk) variable counter : integer range 0 to conv_integer(counts(CLK_FREQ, SER_FREQ)); begin if clk'event and clk = '1' then -- Normal Operation if counter = counts(CLK_FREQ, SER_FREQ) or tx_init = '1' then tx_clk_en <= '1'; counter := 0; else tx_clk_en <= '0'; counter := counter + 1; end if; -- Reset condition if rst = RST_LVL then tx_clk_en <= '0'; counter := 0; end if; end if; end process; tx_proc:process(clk) variable data_cnt : std_logic_vector(2 downto 0); begin if clk'event and clk = '1' then tx_end <= '0'; if tx_clk_en = '1' then -- Default values tx <= UART_IDLE; -- FSM description case tx_fsm is -- Wait to transfer data when idle => -- Send Init Bit if tx_start = '1' then tx <= UART_START; tx_data_tmp <= tx_data; tx_fsm <= data; tx_data_cnt <= (others=>'1'); tx_par_bit <= '0'; end if; -- Data receive when data => tx <= tx_data_tmp(0); tx_par_bit <= tx_par_bit xor tx_data_tmp(0); if tx_data_cnt = 0 then if PARITY_BIT then tx_fsm <= parity; else tx_fsm <= stop1; end if; tx_data_cnt <= (others=>'1'); else tx_data_tmp <= '0' & tx_data_tmp(7 downto 1); tx_data_cnt <= tx_data_cnt - 1; end if; when parity => tx <= tx_par_bit; tx_fsm <= stop1; -- End of communication when stop1 => -- Send Stop Bit tx <= UART_IDLE; tx_fsm <= stop2; when stop2 => -- Send Stop Bit tx_end <= '1'; tx <= UART_IDLE; tx_fsm <= idle; -- Invalid States when others => null; end case; -- Reset condition if rst = RST_LVL then tx_fsm <= idle; tx_par_bit <= '0'; tx_data_tmp <= (others=>'0'); tx_data_cnt <= (others=>'0'); end if; end if; end if; end process; rx_debounceer:process(clk) variable deb_buf : std_logic_vector(3 downto 0); begin if clk'event and clk = '1' then -- Debounce logic if deb_buf = "0000" then rx_data_deb <= '0'; elsif deb_buf = "1111" then rx_data_deb <= '1'; end if; -- Data storage to debounce deb_buf := deb_buf(2 downto 0) & rx; end if; end process; rx_start_detect:process(clk) variable rx_data_old : std_logic; begin if clk'event and clk = '1' then -- Falling edge detection if rx_data_old = '1' and rx_data_deb = '0' and rx_fsm = idle then rx_rcv_init <= '1'; else rx_rcv_init <= '0'; end if; -- Default assignments rx_data_old := rx_data_deb; -- Reset condition if rst = RST_LVL then rx_data_old := '0'; rx_rcv_init <= '0'; end if; end if; end process; rx_clk_gen:process(clk) variable counter : integer range 0 to conv_integer(counts(CLK_FREQ, SER_FREQ)); begin if clk'event and clk = '1' then -- Normal Operation if counter = counts(CLK_FREQ, SER_FREQ) or rx_rcv_init = '1' then rx_clk_en <= '1'; counter := 0; else rx_clk_en <= '0'; counter := counter + 1; end if; -- Reset condition if rst = RST_LVL then rx_clk_en <= '0'; counter := 0; end if; end if; end process; rx_proc:process(clk) begin if clk'event and clk = '1' then -- Default values rx_ready <= '0'; -- Enable on UART rate if rx_clk_en = '1' then -- FSM description case rx_fsm is -- Wait to transfer data when idle => if rx_data_deb = UART_START then rx_fsm <= data; end if; rx_par_bit <= '0'; rx_data_cnt <= (others=>'0'); -- Data receive when data => -- Check data to generate parity if PARITY_BIT then rx_par_bit <= rx_par_bit xor rx; end if; if rx_data_cnt = 7 then -- Data path rx_data(7) <= rx; for i in 0 to 6 loop rx_data(i) <= rx_data_tmp(6-i); end loop; -- With parity verification if PARITY_BIT then rx_fsm <= parity; -- Without parity verification else rx_ready <= '1'; rx_fsm <= idle; end if; else rx_data_tmp <= rx_data_tmp(5 downto 0) & rx; rx_data_cnt <= rx_data_cnt + 1; end if; when parity => -- Check received parity rx_fsm <= idle; if rx_par_bit = rx then rx_ready <= '1'; end if; when others => null; end case; -- Reset condition if rst = RST_LVL then rx_fsm <= idle; rx_ready <= '0'; rx_data <= (others=>'0'); rx_data_tmp <= (others=>'0'); rx_data_cnt <= (others=>'0'); end if; end if; end if; end process; end Behavioral;

lgpl-3.0

02bbacdb7bdb41ba664a0c53692a59a3

jcowgill/cs-dacs-robot

Robot/DecoderTB.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY Decoder_Decoder_sch_tb IS END Decoder_Decoder_sch_tb; ARCHITECTURE behavioral OF Decoder_Decoder_sch_tb IS COMPONENT Decoder PORT ( RF : OUT STD_LOGIC; RR : OUT STD_LOGIC; LF : OUT STD_LOGIC; LR : OUT STD_LOGIC; SCLK : IN STD_LOGIC; I : IN STD_LOGIC_VECTOR(5 DOWNTO 0)); END COMPONENT; SIGNAL RF : STD_LOGIC; SIGNAL RR : STD_LOGIC; SIGNAL LF : STD_LOGIC; SIGNAL LR : STD_LOGIC; SIGNAL SCLK : STD_LOGIC; SIGNAL I : STD_LOGIC_VECTOR(5 DOWNTO 0); BEGIN UUT: Decoder PORT MAP( RF => RF, RR => RR, LF => LF, LR => LR, SCLK => SCLK, I => I ); tb_clock : PROCESS BEGIN -- Clock Process SCLK <= '0'; WAIT FOR 100ns; SCLK <= '1'; WAIT FOR 100ns; END PROCESS; tb_process : PROCESS BEGIN -- Instruction 0 I <= "000000"; WAIT FOR 1000ns; -- Instruction 1 I <= "000001"; WAIT FOR 1000ns; -- Instruction 2 I <= "000010"; WAIT FOR 1000ns; -- Instruction 3 I <= "000011"; WAIT FOR 1000ns; -- Instruction 4 I <= "000100"; WAIT FOR 1000ns; -- Instruction 5 I <= "000101"; WAIT FOR 1000ns; -- Instruction 6 I <= "000110"; WAIT FOR 1000ns; -- Instruction 7 I <= "000111"; WAIT; END PROCESS; END;

apache-2.0

c3f91044781e9a8336a5e37408280b58

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_8Banks.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

0be3fc6835d9c4a1bf0e60fca3523011

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_4AXI_2TAGM.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 0; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 2; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 0; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

cb834c4f72b1f9d0f09bd62df4ce65c2

jpidancet/mips

rtl/register_file.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; entity register_file is port (clk : in std_logic; rst : in std_logic; a1 : in std_logic_vector(4 downto 0); a2 : in std_logic_vector(4 downto 0); a3 : in std_logic_vector(4 downto 0); wd3 : in std_logic_vector(31 downto 0); we3 : in std_logic; rd1 : out std_logic_vector(31 downto 0); rd2 : out std_logic_vector(31 downto 0)); end entity register_file; architecture rtl of register_file is type reg_array is array (1 to 31) of std_logic_vector(31 downto 0); signal regs: reg_array; signal addr1, addr2, addr3: integer range 0 to 31; begin addr1 <= to_integer(unsigned(a1)); addr2 <= to_integer(unsigned(a2)); addr3 <= to_integer(unsigned(a3)); process (addr1, addr3, we3, wd3, regs) begin if addr1 = 0 then rd1 <= (others => '0'); elsif we3 = '1' and addr1 = addr3 then rd1 <= wd3; else rd1 <= regs(addr1); end if; end process; process (addr2, addr3, we3, wd3, regs) begin if addr2 = 0 then rd2 <= (others => '0'); elsif we3 = '1' and addr2 = addr3 then rd2 <= wd3; else rd2 <= regs(addr2); end if; end process; process (clk, rst) begin if rst = '1' then for i in 1 to 31 loop regs(i) <= (others => '0'); end loop; elsif rising_edge(clk) then if we3 = '1' and addr3 /= 0 then regs(addr3) <= wd3; end if; end if; end process; end architecture rtl;

isc

3442883408312c96b292fcae26b3e35b

preusser/q27

src/vhdl/PoC/io/io_TimingCounter.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Patrick Lehmann -- -- Module: optimized down-counter to control timings for low speed signals -- -- Description: -- ------------------------------------ -- This down-counter can be configured with a TIMING_TABLE (a ROM), from which -- the initial counter value is loaded. The table index can be selected by -- 'Slot'. 'Timeout' is a registered output. Up to 16 values fit into one ROM -- consisting of 'log2ceilnz(imax(TIMING_TABLE)) + 1' 6-input LUTs. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library PoC; use PoC.my_config.all; use PoC.utils.all; entity io_TimingCounter is generic ( TIMING_TABLE : T_NATVEC -- timing table ); port ( Clock : in STD_LOGIC; -- clock Enable : in STD_LOGIC; -- enable counter Load : in STD_LOGIC; -- load Timing Value from TIMING_TABLE selected by slot Slot : in NATURAL range 0 to (TIMING_TABLE'length - 1); -- Timeout : out STD_LOGIC -- timing reached ); end; architecture rtl of io_TimingCounter is function transform(vec : T_NATVEC) return T_INTVEC is variable Result : T_INTVEC(vec'range); begin assert (not MY_VERBOSE) report "TIMING_TABLE (transformed):" severity NOTE; for i in vec'range loop Result(I) := vec(I) - 1; assert (not MY_VERBOSE) report " " & INTEGER'image(I) & " - " & INTEGER'image(Result(I)) severity NOTE; end loop; return Result; end; constant TIMING_TABLE2 : T_INTVEC := transform(TIMING_TABLE); constant TIMING_MAX : NATURAL := imax(TIMING_TABLE2); constant COUNTER_BITS : NATURAL := log2ceilnz(TIMING_MAX + 1); signal Counter_s : SIGNED(COUNTER_BITS downto 0) := to_signed(TIMING_TABLE2(0), COUNTER_BITS + 1); begin process(Clock) begin if rising_edge(Clock) then if (Load = '1') then Counter_s <= to_signed(TIMING_TABLE2(Slot), Counter_s'length); elsif ((Enable = '1') and (Counter_s(Counter_s'high) = '0')) then Counter_s <= Counter_s - 1; end if; end if; end process; timeout <= Counter_s(Counter_s'high); end;

agpl-3.0

51a84f8048fd9a5d31d98a0c9be7b9c8

malkadi/FGPU

RTL/gmem_cntrl_tag.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity gmem_cntrl_tag is -- {{{ port( -- axi signals wr_fifo_free : in std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); --free ports have to respond to go ports immediately (in one clock cycle) wr_fifo_go : out std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); wr_fifo_cache_ack : in std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); axi_rdAddr : out gmem_addr_array_no_bank(N_WR_FIFOS-1 downto 0) := (others=>(others=>'0')); axi_writer_go : out std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_wrAddr : out gmem_addr_array_no_bank(N_AXI-1 downto 0) := (others=>(others=>'0')); axi_writer_free : in std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); axi_rd_fifo_filled : in std_logic_vector(N_AXI-1 downto 0); axi_wvalid : in std_logic_vector(N_AXI-1 downto 0); axi_writer_ack : in std_logic_vector(N_TAG_MANAGERS-1 downto 0); axi_writer_id : out std_logic_vector(N_TAG_MANAGERS_W-1 downto 0) := (others=>'0'); --receivers signals rcv_alloc_tag : in std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); -- rcv_alloc_tag need to be set whether it is a tag to be allocated or a page to be validate -- rcv_validate_page : in std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); rcv_gmem_addr : in gmem_word_addr_array(N_RECEIVERS-1 downto 0) := (others=>(others=>'0')); rcv_rnw : in std_logic_vector(N_RECEIVERS-1 downto 0); rcv_tag_written : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); rcv_tag_updated : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); rcv_page_validated : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); rcv_read_tag : in std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); rcv_read_tag_ack : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); rdData_page_v : out std_logic_vector(N_RD_PORTS-1 downto 0) := (others=>'0'); rdData_tag_v : out std_logic_vector(N_RD_PORTS-1 downto 0) := (others=>'0'); rdData_tag : out tag_array(N_RD_PORTS-1 downto 0) := (others=>(others=>'0')); -- cache port a signals cache_we : in std_logic := '0'; cache_addra : in unsigned(M+L-1 downto 0) := (others=>'0'); cache_wea : in std_logic_vector((2**N)*DATA_W/8-1 downto 0) := (others=>'0'); -- finish WGsDispatched : in std_logic; CUs_gmem_idle : in std_logic; rcv_all_idle : in std_logic := '0'; rcv_idle : in std_logic_vector(N_RECEIVERS-1 downto 0); finish_exec : out std_logic := '0'; start_kernel : in std_logic; clean_cache : in std_logic; atomic_can_finish : in std_logic := '0'; -- write pipeline write_pipe_active : in std_logic_vector(4 downto 0) := (others=>'0'); write_pipe_wrTag : in tag_addr_array(4 downto 0); clk, nrst : in std_logic ); end entity; -- }}} architecture basic of gmem_cntrl_tag is -- internal signals definitions {{{ signal axi_wrAddr_i : gmem_addr_array_no_bank(N_AXI-1 downto 0) := (others=>(others=>'0')); signal rdData_tag_i : tag_array(N_RD_PORTS-1 downto 0) := (others=>(others=>'0')); -- on a critical path -- }}} -- axi signals {{{ signal wr_fifo_go_n : std_logic_vector(N_WR_FIFOS-1 downto 0) := (others=>'0'); signal axi_writer_go_n : std_logic_vector(N_AXI-1 downto 0) := (others=>'0'); signal axi_writer_id_n : std_logic_vector(N_TAG_MANAGERS_W-1 downto 0) := (others=>'0'); --}}} -- functions & constants {{{ function map_rd_fifo_to_axis(n_rd_fifos : natural; n_axis: natural) return nat_array is variable res : nat_array(n_rd_fifos-1 downto 0) := (others=>0); begin for i in 0 to n_rd_fifos-1 loop res(i) := i mod n_axis; end loop; return res; end function; constant c_rd_fifo_axi : nat_array(N_TAG_MANAGERS-1 downto 0) := map_rd_fifo_to_axis(N_TAG_MANAGERS, N_AXI); -- }}} -- mem signals {{{ signal tag : tag_array(0 to 2**M-1) := (others=>(others=>'0')); signal wrAddr_tag, wrAddr_tag_n : unsigned(M-1 downto 0) := (others=>'0'); signal wrData_tag, wrData_tag_n : unsigned(TAG_W-1 downto 0) := (others=>'0'); signal rdAddr_tag, rdAddr_tag_n : tag_addr_array(N_RD_PORTS-1 downto 0) := (others=>(others=>'0')); signal we_tag, we_tag_n : std_logic := '0'; signal tag_v : std_logic_vector(0 to 2**M-1) := (others=>'0'); signal we_tag_v, we_tag_v_n : std_logic := '0'; signal wrAddr_tag_v, wrAddr_tag_v_n : unsigned(M-1 downto 0) := (others=>'0'); signal wrData_tag_v, wrData_tag_v_n : std_logic := '0'; signal clear_tag, clear_tag_n : std_logic := '0'; signal page_v : std_logic_vector(0 to 2**M-1) := (others=>'0'); signal we_page_v, we_page_v_n : std_logic := '0'; signal wrAddr_page_v, wrAddr_page_v_n : unsigned(M-1 downto 0) := (others=>'0'); signal wrData_page_v, wrData_page_v_n : std_logic := '0'; -- }}} -- receivers signals {{{ signal rcv_tag_written_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_tag_updated_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); signal rcv_page_validated_n : std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); -- }}} -- Tag managers signals {{{ type st_tmanager_type is (idle, define_rcv_indx, check_tag_being_processed, invalidate_tag_v, invalidate_page_v, clear_tag_st, clear_dirty, check_dirty, validate_new_tag, issue_write, read_tag, wait_write_finish, issue_read, wait_read_finish, validate_new_page, wait_page_v, wait_a_little, wait_bid); type st_tmanager_array is array (N_TAG_MANAGERS-1 downto 0) of st_tmanager_type; type rcv_alloc_for_tmanager_type is array(N_TAG_MANAGERS-1 downto 0) of std_logic_vector(N_RECEIVERS/N_TAG_MANAGERS-1 downto 0); signal st_tmanager, st_tmanager_n : st_tmanager_array := (others=>idle); -- attribute mark_debug of st_tmanager : signal is "true"; signal tmanager_free, tmanager_free_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal rcv_alloc_tag_ltchd, rcv_alloc_tag_ltchd_n : rcv_alloc_for_tmanager_type := (others=>(others=>'0')); signal tmanager_gmem_addr : gmem_addr_array_no_bank(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); signal tmanager_gmem_addr_n : gmem_addr_array_no_bank(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); -- attribute mark_debug of tmanager_gmem_addr : signal is "true"; type rcv_indx_tmanager_type is array (0 to N_TAG_MANAGERS-1) of natural range 0 to N_RECEIVERS-1; signal rcv_indx_tmanager : rcv_indx_tmanager_type := (others=>0); signal rcv_indx_tmanager_n : rcv_indx_tmanager_type := (others=>0); signal tmanager_rcv_served : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_rcv_served_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal invalidate_tag, invalidate_tag_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of invalidate_tag : signal is "true"; signal invalidate_tag_ack : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal invalidate_page : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal invalidate_page_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of invalidate_page : signal is "true"; signal validate_page, validate_page_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of validate_page : signal is "true"; signal page_v_tmanager_ack : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal clear_tag_tmanager : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal clear_tag_tmanager_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of clear_tag_tmanager : signal is "true"; signal alloc_tag, alloc_tag_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of alloc_tag : signal is "true"; signal alloc_tag_ack : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_issue_write : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of tmanager_issue_write : signal is "true"; signal tmanager_issue_write_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal wr_issued_tmanager : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal wr_issued_tmanager_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_busy, tmanager_busy_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of tmanager_busy : signal is "true"; constant TAG_PROTECT_LEN : natural := 7; -- # of clock cycles before a processed tag from a tag manager can be processed by another one type tmanager_tag_protect_vec_type is array(natural range<>) of std_logic_vector(TAG_PROTECT_LEN-1 downto 0); signal tmanager_tag_protect_vec : tmanager_tag_protect_vec_type(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); -- helps a tag manager to clear the protection of tag signal tmanager_tag_protect_vec_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_tag_protect_v : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_tag_protect_v_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of tmanager_tag_protect_v : signal is "true"; signal tmanager_tag_protect : tag_addr_array(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); -- attribute mark_debug of tmanager_tag_protect : signal is "true"; -- after a tag has been processed by a tag manager, it will be stored with this signal. -- It is not allowed to process the tag again before TAG_PROTECT_LEN clock cycles -- It helps to avoid frequent allocation/deallocation of the same tag (not necessary but improve the performance) -- It helps to insure data consistency by using the B axi channel response to clear it (necessary if the kernel reads/writes the same address region) signal tmanager_tag_protect_n : tag_addr_array(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); signal tmanager_gmem_addr_protected : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); constant RCV_SERVED_WIAT_LEN : natural := 2**(WRITE_PHASE_W+1); type tmanager_rcv_served_wait_vec_type is array(natural range<>) of std_logic_vector(RCV_SERVED_WIAT_LEN-1 downto 0); signal tmanager_rcv_served_wait_vec : tmanager_rcv_served_wait_vec_type(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); -- helps a tag manager to wait for some time before issuing a receiver that its write requested has been executed signal tmanager_rcv_served_wait_vec_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_get_busy : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of tmanager_get_busy : signal is "true"; signal tmanager_get_busy_ack : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of tmanager_get_busy_ack : signal is "true"; constant wait_len : natural := 4; type wait_vec_type is array (natural range <>) of std_logic_vector(wait_len-1 downto 0); type wait_vec_invalidate_tag_type is array (natural range <>) of std_logic_vector(wait_len downto 0); signal wait_vec : wait_vec_type(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); signal wait_vec_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal wait_vec_invalidate_tag : wait_vec_invalidate_tag_type(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); signal wait_vec_invalidate_tag_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal wait_done, wait_done_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of wait_done : signal is "true"; signal tmanager_read_tag : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of tmanager_read_tag : signal is "true"; signal tmanager_read_tag_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_read_tag_ack_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_read_tag_ack : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_read_tag_ack_d0 : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_tag_to_write : tag_array(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); signal tmanager_clear_dirty : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of tmanager_clear_dirty : signal is "true"; signal tmanager_clear_dirty_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_clear_dirty_ack_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_clear_dirty_ack : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_wait_for_fifo_empty : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_wait_for_fifo_empty_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); --}}} -- dirty signals {{{ signal dirty : std_logic_vector(2**M-1 downto 0) := (others=>'0'); signal we_dirty, we_dirty_n : std_logic := '0'; signal wrData_dirty, wrData_dirty_n : std_logic := '0'; signal wrAddr_dirty, wrAddr_dirty_n : unsigned(M-1 downto 0) := (others=>'0'); signal rdAddr_dirty, rdAddr_dirty_n : tag_addr_array(N_TAG_MANAGERS-1 downto 0) := (others=>(others=>'0')); signal rdData_dirty : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- }}} -- axi signals {{{ type axi_intefrace is (find_free_fifo, issue_order); type wr_fifo_indx_array is array (0 to N_TAG_MANAGERS-1) of natural range 0 to N_WR_FIFOS-1; type axi_wr_channel_indx is array (0 to N_TAG_MANAGERS-1) of natural range 0 to N_AXI-1; signal st_axi_wr, st_axi_wr_n : axi_intefrace := find_free_fifo; signal axi_wrAddr_n : gmem_addr_array_no_bank(N_AXI-1 downto 0) := (others=>(others=>'0')); signal axi_wr_indx_tmanager, axi_wr_indx_tmanager_n : axi_wr_channel_indx := (others=>0); --}}} -- final cache clean signals {{{ signal rcv_all_idle_vec : std_logic_vector(2 downto 0) := (others=>'0'); -- It is necessary to make sure that rcv_all_idle is stable for 3 clock cycles before cache cleaning at the end signal finish_active, finish_active_n : std_logic := '0'; signal finish_tag_addr : unsigned(M-1 downto 0) := (others=>'0'); signal finish_tag_addr_n : unsigned(M-1 downto 0) := (others=>'0'); signal finish_tag_addr_d0 : unsigned(M-1 downto 0) := (others=>'0'); signal finish_tag_addr_d1 : unsigned(M-1 downto 0) := (others=>'0'); signal finish_we, finish_we_n : std_logic := '0'; signal rdData_tag_d0 : unsigned(TAG_W-1 downto 0) := (others=>'0'); signal finish_issue_write : std_logic := '0'; signal finish_issue_write_n : std_logic := '0'; signal finish_exec_masked : std_logic := '0'; signal finish_exec_masked_n : std_logic := '0'; type finish_fifo_type is array(natural range <>) of unsigned(TAG_W+M-1 downto 0); signal finish_fifo : finish_fifo_type(2**FINISH_FIFO_ADDR_W-1 downto 0) := (others=>(others=>'0')); signal finish_fifo_rdAddr : unsigned(FINISH_FIFO_ADDR_W-1 downto 0) := (others=>'0'); signal finish_fifo_wrAddr : unsigned(FINISH_FIFO_ADDR_W-1 downto 0) := (others=>'0'); signal finish_fifo_dout : unsigned(TAG_W+M-1 downto 0) := (others=>'0'); signal finish_fifo_pop, finish_fifo_push_n : std_logic := '0'; signal finish_fifo_push : std_logic_vector(1 downto 0) := (others=>'0'); type st_fill_finish_fifo_type is (idle1, idle2, pre_active, active, finish); signal st_fill_finish_fifo, st_fill_finish_fifo_n : st_fill_finish_fifo_type := idle1; signal finish_fifo_n_rqsts, finish_fifo_n_rqsts_n : integer range 0 to 2**FINISH_FIFO_ADDR_W := 0; -- }}} -- write pipeline signals {{{ signal write_pipe_contains_gmem_addr : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_waited_for_write_pipe : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal tmanager_waited_for_write_pipe_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); -- attribute mark_debug of tmanager_waited_for_write_pipe : signal is "true"; type st_finish_writer_type is (idle, issue, wait_fifo_dout); signal st_finish_writer : st_finish_writer_type := idle; signal st_finish_writer_n : st_finish_writer_type := idle; --}}} -- bvalid processing ------------------------------------------------------------------------------------{{{ signal write_response_rcvd : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal wait_for_write_response : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); signal wait_for_write_response_n : std_logic_vector(N_TAG_MANAGERS-1 downto 0) := (others=>'0'); ---------------------------------------------------------------------------------------------------------}}} begin -- internal signals assignments -------------------------------------------------------------------------{{{ axi_wrAddr <= axi_wrAddr_i; assert N_RD_FIFOS_TAG_MANAGER_W = 0 report "There must be a single rd fifo (from cache) for each tag manager. Otherwise b channel communcation fails!" severity failure; rdData_tag <= rdData_tag_i; ---------------------------------------------------------------------------------------------------------}}} -- error handling-------------------------------------------------------------------------------------------{{{ assert(N_TAG_MANAGERS = N_WR_FIFOS); assert(N_RD_PORTS > 1); -- assert(addra(7 downto 0) /= X"B7" or addra(8) /= '0' or wea(7 downto 4) /= "F"); ---------------------------------------------------------------------------------------------------------}}} -- finish FSM -------------------------------------------------------------------------------------------{{{ rcv_all_idle_vec(rcv_all_idle_vec'high) <= rcv_all_idle; process(clk) begin if rising_edge(clk) then -- pipes {{{ rcv_all_idle_vec(rcv_all_idle_vec'high-1 downto 0) <= rcv_all_idle_vec(rcv_all_idle_vec'high downto 1); finish_tag_addr <= finish_tag_addr_n; finish_tag_addr_d0 <= finish_tag_addr; finish_tag_addr_d1 <= finish_tag_addr_d0; -- }}} -- set final finish signal {{{ finish_exec_masked <= finish_exec_masked_n; finish_exec <= '0'; if finish_exec_masked = '1' then if clean_cache = '1' then if axi_writer_free = (axi_writer_free'reverse_range => '1') and axi_wvalid = (0 to N_AXI-1 =>'0') then finish_exec <= '1'; end if; else finish_exec <= '1'; end if; end if; if start_kernel = '1' then finish_exec <= '0'; end if; -- }}} finish_we <= finish_we_n; finish_fifo_dout <= finish_fifo(to_integer(finish_fifo_rdAddr)); if finish_fifo_push(0) = '1' and rdData_dirty(0) = '1' then finish_fifo(to_integer(finish_fifo_wrAddr)) <= rdData_tag_i(N_RD_PORTS-1) & finish_tag_addr_d1; end if; if nrst = '0' then finish_active <= '0'; finish_issue_write <= '0'; st_fill_finish_fifo <= idle1; finish_fifo_push <= (others=>'0'); finish_fifo_wrAddr <= (others=>'0'); finish_fifo_n_rqsts <= 0; st_finish_writer <= idle; finish_fifo_rdAddr <= (others=>'0'); else finish_active <= finish_active_n; finish_issue_write <= finish_issue_write_n; st_fill_finish_fifo <= st_fill_finish_fifo_n; finish_fifo_push(finish_fifo_push'high-1 downto 0) <= finish_fifo_push(finish_fifo_push'high downto 1); finish_fifo_push(finish_fifo_push'high) <= finish_fifo_push_n; if finish_fifo_push(0) = '1' and rdData_dirty(0) = '1' then finish_fifo_wrAddr <= finish_fifo_wrAddr + 1; end if; st_finish_writer <= st_finish_writer_n; if finish_fifo_pop = '1' then finish_fifo_rdAddr <= finish_fifo_rdAddr + 1; end if; if finish_fifo_push(0) = '1' and rdData_dirty(0) = '1' and finish_fifo_pop = '0' then finish_fifo_n_rqsts <= finish_fifo_n_rqsts + 1; elsif (finish_fifo_push(0) = '0' or rdData_dirty(0) = '0') and finish_fifo_pop = '1' then finish_fifo_n_rqsts <= finish_fifo_n_rqsts - 1; end if; end if; end if; end process; process(st_finish_writer, finish_fifo_n_rqsts, finish_issue_write) begin st_finish_writer_n <= st_finish_writer; finish_issue_write_n <= finish_issue_write; case st_finish_writer is when idle => if finish_fifo_n_rqsts /= 0 then finish_issue_write_n <= '1'; st_finish_writer_n <= issue; end if; when issue => finish_issue_write_n <= '0'; st_finish_writer_n <= wait_fifo_dout; when wait_fifo_dout => st_finish_writer_n <= idle; end case; end process; process(st_fill_finish_fifo, finish_tag_addr, WGsDispatched, start_kernel, CUs_gmem_idle, rcv_all_idle_vec, finish_active, finish_fifo_n_rqsts, clean_cache, atomic_can_finish) begin st_fill_finish_fifo_n <= st_fill_finish_fifo; finish_tag_addr_n <= finish_tag_addr; finish_active_n <= finish_active; finish_fifo_push_n <= '0'; finish_we_n <= '0'; finish_exec_masked_n <= '0'; case st_fill_finish_fifo is when idle1 => finish_tag_addr_n <= (others=>'0'); if WGsDispatched = '1' then st_fill_finish_fifo_n <= idle2; end if; when idle2 => if CUs_gmem_idle = '1' and rcv_all_idle_vec = (rcv_all_idle_vec'reverse_range =>'1') and (ATOMIC_IMPLEMENT = 0 or atomic_can_finish = '1') then if clean_cache = '0' then st_fill_finish_fifo_n <= finish; else finish_active_n <= '1'; end if; end if; if finish_active = '1' then st_fill_finish_fifo_n <= pre_active; if STAT = 1 then -- if kernel_name /= sum_half then -- report "Finish begins"; -- end if; end if; end if; when pre_active => finish_tag_addr_n <= finish_tag_addr + 1; finish_fifo_push_n <= '1'; finish_we_n <= '1'; st_fill_finish_fifo_n <= active; when active => if finish_fifo_n_rqsts < 2**FINISH_FIFO_ADDR_W-2 then finish_tag_addr_n <= finish_tag_addr + 1; finish_fifo_push_n <= '1'; finish_we_n <= '1'; end if; if finish_tag_addr = (finish_tag_addr'reverse_range => '0') then st_fill_finish_fifo_n <= finish; end if; when finish => finish_exec_masked_n <= '1'; if start_kernel = '1' then st_fill_finish_fifo_n <= idle1; finish_active_n <= '0'; finish_exec_masked_n <= '0'; end if; end case; end process; ---------------------------------------------------------------------------------------------------------}}} -- write pipeline check --------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then write_pipe_contains_gmem_addr <= (others=>'0'); for i in 0 to N_TAG_MANAGERS-1 loop for j in 0 to 4 loop if (tmanager_gmem_addr(i)(M+L-1 downto L) = write_pipe_wrTag(j)) and (write_pipe_active(j) = '1') then write_pipe_contains_gmem_addr(i) <= '1'; end if; end loop; end loop; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- tag managers -------------------------------------------------------------------------------------------{{{ trans: process(clk) -- {{{ begin if rising_edge(clk) then rcv_alloc_tag_ltchd <= rcv_alloc_tag_ltchd_n; tmanager_gmem_addr <= tmanager_gmem_addr_n; rcv_indx_tmanager <= rcv_indx_tmanager_n; if WRITE_PHASE_W > 1 then tmanager_rcv_served <= tmanager_rcv_served_n; end if; tmanager_get_busy_ack <= (others=>'0'); for i in 0 to N_TAG_MANAGERS-1 loop if tmanager_get_busy(i) = '1' then tmanager_get_busy_ack(i) <= '1'; exit; end if; end loop; wr_fifo_go <= wr_fifo_go_n; tmanager_tag_protect <= tmanager_tag_protect_n; for i in 0 to N_TAG_MANAGERS-1 loop tmanager_tag_protect_vec(i)(TAG_PROTECT_LEN-2 downto 0) <= tmanager_tag_protect_vec(i)(TAG_PROTECT_LEN-1 downto 1); tmanager_tag_protect_vec(i)(TAG_PROTECT_LEN-1) <= tmanager_tag_protect_vec_n(i); tmanager_rcv_served_wait_vec(i)(RCV_SERVED_WIAT_LEN-2 downto 0) <= tmanager_rcv_served_wait_vec(i)(RCV_SERVED_WIAT_LEN-1 downto 1); tmanager_rcv_served_wait_vec(i)(RCV_SERVED_WIAT_LEN-1) <= tmanager_rcv_served_wait_vec_n(i); end loop; tmanager_gmem_addr_protected <= (others=>'0'); for i in 0 to N_TAG_MANAGERS-1 loop for j in 0 to N_TAG_MANAGERS-1 loop if j /= i then if tmanager_tag_protect_v(j) = '1' and tmanager_gmem_addr(i)(M+L-1 downto L) = tmanager_tag_protect(j) then tmanager_gmem_addr_protected(i) <= '1'; end if; end if; end loop; end loop; tmanager_tag_protect_v <= tmanager_tag_protect_v_n; for i in N_TAG_MANAGERS-1 downto 0 loop wait_vec(i)(wait_len-2 downto 0) <= wait_vec(i)(wait_len-1 downto 1); wait_vec(i)(wait_len-1) <= wait_vec_n(i); wait_vec_invalidate_tag(i)(wait_len-1 downto 0) <= wait_vec_invalidate_tag(i)(wait_len downto 1); wait_vec_invalidate_tag(i)(wait_len) <= wait_vec_invalidate_tag_n(i); if tmanager_read_tag_ack_d0(i) = '1' then tmanager_tag_to_write(i) <= rdData_tag_i(N_RD_PORTS-1); end if; end loop; if nrst = '0' then st_tmanager <= (others=>idle); tmanager_free <= (others=>'0'); invalidate_tag <= (others=>'0'); invalidate_page <= (others=>'0'); validate_page <= (others=>'0'); clear_tag_tmanager <= (others=>'0'); tmanager_issue_write <= (others=>'0'); tmanager_busy <= (others=>'0'); alloc_tag <= (others=>'0'); tmanager_read_tag <= (others=>'0'); tmanager_clear_dirty <= (others=>'0'); wait_done <= (others=>'0'); tmanager_wait_for_fifo_empty <= (others=>'0'); tmanager_waited_for_write_pipe <= (others=>'0'); else st_tmanager <= st_tmanager_n; tmanager_free <= tmanager_free_n; invalidate_tag <= invalidate_tag_n; invalidate_page <= invalidate_page_n; validate_page <= validate_page_n; clear_tag_tmanager <= clear_tag_tmanager_n; tmanager_issue_write <= tmanager_issue_write_n; tmanager_busy <= tmanager_busy_n; alloc_tag <= alloc_tag_n; tmanager_read_tag <= tmanager_read_tag_n; tmanager_clear_dirty <= tmanager_clear_dirty_n; wait_done <= wait_done_n; tmanager_wait_for_fifo_empty <= tmanager_wait_for_fifo_empty_n; tmanager_waited_for_write_pipe <= tmanager_waited_for_write_pipe_n; end if; end if; end process; --}}} tmanagers: for i in 0 to N_TAG_MANAGERS-1 generate process(st_tmanager(i), tmanager_free(i), rcv_alloc_tag, tmanager_gmem_addr, rcv_alloc_tag_ltchd, rcv_indx_tmanager(i), rcv_gmem_addr, -- {{{ tmanager_tag_protect_v, invalidate_tag(i), invalidate_tag_ack(i), clear_tag_tmanager(i), rdData_dirty(i), tmanager_issue_write(i), tmanager_tag_protect, rcv_idle, axi_wr_indx_tmanager(i), wr_issued_tmanager(i), wr_fifo_free(i), wait_done(i), tmanager_waited_for_write_pipe(i), tmanager_rcv_served(i), tmanager_rcv_served_wait_vec(i)(0), page_v_tmanager_ack(i), invalidate_page(i), alloc_tag_ack(i), validate_page(i), tmanager_busy(i), tmanager_get_busy_ack(i), tmanager_tag_protect_vec(i), rcv_rnw, wait_vec(i)(0), wait_vec_invalidate_tag(i)(0), tmanager_read_tag(i), tmanager_read_tag_ack_d0(i), axi_rd_fifo_filled, tmanager_clear_dirty(i), alloc_tag(i), tmanager_read_tag_ack_n(i), tmanager_clear_dirty_ack(i), write_pipe_contains_gmem_addr(i), tmanager_wait_for_fifo_empty(i), tmanager_gmem_addr_protected(i), tmanager_tag_to_write(i), wait_for_write_response(i)) -- }}} begin -- next initialization {{{ st_tmanager_n(i) <= st_tmanager(i); tmanager_free_n(i) <= tmanager_free(i); rcv_alloc_tag_ltchd_n(i) <= rcv_alloc_tag_ltchd(i); tmanager_gmem_addr_n(i) <= tmanager_gmem_addr(i); rcv_indx_tmanager_n(i) <= rcv_indx_tmanager(i); invalidate_tag_n(i) <= invalidate_tag(i); invalidate_page_n(i) <= invalidate_page(i); validate_page_n(i) <= validate_page(i); clear_tag_tmanager_n(i) <= clear_tag_tmanager(i); tmanager_issue_write_n(i) <= tmanager_issue_write(i); tmanager_busy_n(i) <= tmanager_busy(i); tmanager_get_busy(i) <= '0'; alloc_tag_n(i) <= alloc_tag(i); wait_vec_n(i) <= '0'; wait_vec_invalidate_tag_n(i) <= '0'; tmanager_read_tag_n(i) <= tmanager_read_tag(i); tmanager_clear_dirty_n(i) <= tmanager_clear_dirty(i); wait_done_n(i) <= wait_done(i); tmanager_wait_for_fifo_empty_n(i) <= tmanager_wait_for_fifo_empty(i); tmanager_waited_for_write_pipe_n(i) <= tmanager_waited_for_write_pipe(i); if tmanager_tag_protect_vec(i)(0) = '1' then tmanager_tag_protect_v_n(i) <= '0'; else tmanager_tag_protect_v_n(i) <= tmanager_tag_protect_v(i); end if; if WRITE_PHASE_W > 1 then tmanager_rcv_served_n(i) <= tmanager_rcv_served(i); if rcv_idle(rcv_indx_tmanager(i)) = '1' or tmanager_rcv_served_wait_vec(i)(0) = '1' then tmanager_rcv_served_n(i) <= '1'; end if; end if; tmanager_tag_protect_n(i) <= tmanager_tag_protect(i); tmanager_tag_protect_vec_n(i) <= '0'; tmanager_rcv_served_wait_vec_n(i) <= '0'; wr_fifo_go_n(i) <= '0'; -- }}} case st_tmanager(i) is when idle => -- {{{ tmanager_waited_for_write_pipe_n(i) <= '0'; rcv_alloc_tag_ltchd_n(i) <= rcv_alloc_tag((i+1)*N_RECEIVERS/N_TAG_MANAGERS-1 downto i*N_RECEIVERS/N_TAG_MANAGERS); if tmanager_rcv_served(i) = '1' or WRITE_PHASE_W = 1 then if rcv_alloc_tag((i+1)*N_RECEIVERS/N_TAG_MANAGERS-1 downto i*N_RECEIVERS/N_TAG_MANAGERS) /= (0 to N_RECEIVERS/N_TAG_MANAGERS-1 =>'0') then st_tmanager_n(i) <= define_rcv_indx; end if; end if; -- }}} when define_rcv_indx => -- {{{ st_tmanager_n(i) <= idle; -- in case rcv_alloc_tag_ltchd are all zeros for j in 0 to N_RECEIVERS/N_TAG_MANAGERS-1 loop if rcv_alloc_tag_ltchd(i)(j) = '1' and rcv_alloc_tag(i*N_RECEIVERS/N_TAG_MANAGERS+j) = '1' then -- rcv_alloc_tag must be checked because it may be deasserted while rcv_alloc_tag_latched is still asserted rcv_indx_tmanager_n(i) <= j+ i*N_RECEIVERS/N_TAG_MANAGERS; rcv_alloc_tag_ltchd_n(i)(j) <= '0'; tmanager_gmem_addr_n(i) <= rcv_gmem_addr(j+ i*N_RECEIVERS/N_TAG_MANAGERS)(GMEM_WORD_ADDR_W-1 downto N); st_tmanager_n(i) <= check_tag_being_processed; exit; end if; end loop; -- }}} when check_tag_being_processed => --check if the corresponding cache addr is being processed by another tmanager {{{ -- if an address of the requested tag is already in the write pipeline; the FSM should go and try to pick up a new alloc request -- Otherwise it may stay in this state, as long as no anther tmanager is processing the tag and the alloc request deasserted, e.g. another tmanager allocated the tag -- Processing a no more requested tag may lead to the following problem: -- a rcv wants to write, a tmanager thinks wrongly that somebody wants to read the address, -- as soon as the tag is allocated, the rcv may write and the data may be overwritten! tmanager_get_busy(i) <= '1'; if tmanager_get_busy_ack(i) = '1' then if write_pipe_contains_gmem_addr(i) = '0' and tmanager_gmem_addr_protected(i) = '0' then -- tmanager_gmem_addr_protected has a delay of 1 clock cycle invalidate_tag_n(i) <= '1'; st_tmanager_n(i) <= invalidate_tag_v; tmanager_busy_n(i) <= '1'; tmanager_tag_protect_v_n(i) <= '1'; tmanager_tag_protect_n(i) <= tmanager_gmem_addr(i)(M+L-1 downto L); else st_tmanager_n(i) <= define_rcv_indx; tmanager_get_busy(i) <= '0'; end if; end if; for j in 0 to N_TAG_MANAGERS-1 loop if j /= i then if (tmanager_busy(j) = '1' and tmanager_gmem_addr(i)(M+L-1 downto L) = tmanager_gmem_addr(j)(M+L-1 downto L)) then -- (tmanager_gmem_addr_protected(i) = '1' and tmanager_get_busy_ack(i) = '1') then -- (tmanager_tag_protect_v(j) = '1' and tmanager_gmem_addr(i)(M+N+L-1 downto L+N) = tmanager_tag_protect(j)) then tmanager_get_busy(i) <= '0'; tmanager_busy_n(i) <= '0'; tmanager_tag_protect_v_n(i) <= '0'; invalidate_tag_n(i) <= '0'; st_tmanager_n(i) <= define_rcv_indx; end if; end if; end loop; -- }}} when invalidate_tag_v => -- {{{ -- if tmanager_tag_protect_vec(i)(0) = '1' then -- report "heeeere" severity failure; -- end if; -- tmanager_tag_protect_v_n(i) <= '1'; -- tmanager_tag_protect_n(i) <= tmanager_gmem_addr(i)(M+N+L-1 downto N+L); if WRITE_PHASE_W > 1 then tmanager_rcv_served_n(i) <= '0'; end if; if invalidate_tag_ack(i) = '1' then invalidate_tag_n(i) <= '0'; st_tmanager_n(i) <= clear_tag_st; clear_tag_tmanager_n(i) <= '1'; alloc_tag_n(i) <= '1'; end if; -- }}} when clear_tag_st => -- {{{ if alloc_tag_ack(i) = '1' then clear_tag_tmanager_n(i) <= '0'; alloc_tag_n(i) <= '0'; st_tmanager_n(i) <= invalidate_page_v; invalidate_page_n(i) <= '1'; end if; -- }}} when invalidate_page_v => -- {{{ if page_v_tmanager_ack(i) = '1' then invalidate_page_n(i) <= '0'; st_tmanager_n(i) <= check_dirty; wait_vec_invalidate_tag_n(i) <= '1'; if write_pipe_contains_gmem_addr(i) = '1' then tmanager_waited_for_write_pipe_n(i) <= '1'; end if; end if; -- }}} when check_dirty => -- {{{ if write_pipe_contains_gmem_addr(i) = '1' then tmanager_waited_for_write_pipe_n(i) <= '1'; if wait_vec_invalidate_tag(i)(0) = '1' then wait_done_n(i) <= '1'; end if; else wait_done_n(i) <= '0'; if wait_vec_invalidate_tag(i)(0) = '1' or wait_done(i) = '1' then if tmanager_waited_for_write_pipe(i) = '1' or rdData_dirty(i) = '1' then st_tmanager_n(i) <= read_tag; tmanager_read_tag_n(i) <= '1'; tmanager_clear_dirty_n(i) <= '1'; else -- - -- st_tmanager_n(i) <= validate_new_tag; -- alloc_tag_n(i) <= '1'; -- - -- + -- Populating the cache line with the new content should be done before validating the new tag -- Otherwise, some receivers may write the cache directly after tag validation and the written data will -- be overwritten by the one from the global memory -- Therefore, issue_read -> validate_tag -> validate_page if rcv_rnw(rcv_indx_tmanager(i)) = '1' then st_tmanager_n(i) <= issue_read; wr_fifo_go_n(i) <= '1'; else st_tmanager_n(i) <= validate_new_tag; alloc_tag_n(i) <= '1'; end if; -- + end if; end if; end if; -- }}} when validate_new_tag => -- {{{ if alloc_tag_ack(i) = '1' then alloc_tag_n(i) <= '0'; -- - -- if rcv_rnw(rcv_indx_tmanager(i)) = '1' then -- st_tmanager_n(i) <= issue_read; -- wr_fifo_go_n(i) <= '1'; -- else -- st_tmanager_n(i) <= wait_a_little; -- wait_vec_n(i) <= '1'; -- end if; -- - -- + if rcv_rnw(rcv_indx_tmanager(i)) = '1' then st_tmanager_n(i) <= validate_new_page; validate_page_n(i) <= '1'; else st_tmanager_n(i) <= wait_a_little; wait_vec_n(i) <= '1'; end if; -- + end if; -- }}} when wait_a_little => --necessary because rcv_alloc_tag does not react immediately in case of validating a tag for a write {{{ -- tmanager_tag_protect_v_n(i) <= '1'; -- setting tag protect should be done 2 cycles before going to idle -- tmanager_tag_protect_n(i) <= tmanager_gmem_addr(i)(M+N+L-1 downto N+L); if wait_vec(i)(0) = '1' then st_tmanager_n(i) <= idle; tmanager_busy_n(i) <= '0'; tmanager_tag_protect_vec_n(i) <= '1'; tmanager_rcv_served_wait_vec_n(i) <= '1'; end if; -- }}} when read_tag => -- {{{ -- report "tag read by tmanager"; tmanager_waited_for_write_pipe_n(i) <= '0'; if tmanager_read_tag_ack_d0(i) = '1' then st_tmanager_n(i) <= issue_write; tmanager_issue_write_n(i) <= '1'; end if; -- }}} when issue_write => -- {{{ -- report "write issued"; if wr_issued_tmanager(i) = '1' then st_tmanager_n(i) <= wait_write_finish; tmanager_issue_write_n(i) <= '0'; end if; -- }}} when wait_write_finish => -- {{{ if axi_rd_fifo_filled(axi_wr_indx_tmanager(i)) = '1' then if tmanager_tag_to_write(i) = tmanager_gmem_addr(i)(TAG_W+M+L-1 downto M+L) then -- the tag to read is the same dirty one! -- the tmanager should wait until the write transaction is completely finished -- otherwise data may become inconsistent st_tmanager_n(i) <= wait_bid; -- report "match"; elsif tmanager_clear_dirty(i) = '1' then st_tmanager_n(i) <= clear_dirty; else -- - -- st_tmanager_n(i) <= validate_new_tag; -- alloc_tag_n(i) <= '1'; -- - -- + if rcv_rnw(rcv_indx_tmanager(i)) = '1' then st_tmanager_n(i) <= issue_read; wr_fifo_go_n(i) <= '1'; else st_tmanager_n(i) <= validate_new_tag; alloc_tag_n(i) <= '1'; end if; -- + end if; end if; -- }}} when wait_bid => -- {{{ if wait_for_write_response(i) = '0' then if tmanager_clear_dirty(i) = '1' then st_tmanager_n(i) <= clear_dirty; else -- - -- st_tmanager_n(i) <= validate_new_tag; -- alloc_tag_n(i) <= '1'; -- - -- + if rcv_rnw(rcv_indx_tmanager(i)) = '1' then st_tmanager_n(i) <= issue_read; wr_fifo_go_n(i) <= '1'; else st_tmanager_n(i) <= validate_new_tag; alloc_tag_n(i) <= '1'; end if; -- + end if; end if; -- }}} when clear_dirty => -- {{{ if tmanager_clear_dirty(i) = '0' then -- - -- st_tmanager_n(i) <= validate_new_tag; -- alloc_tag_n(i) <= '1'; -- - -- + if rcv_rnw(rcv_indx_tmanager(i)) = '1' then st_tmanager_n(i) <= issue_read; wr_fifo_go_n(i) <= '1'; else st_tmanager_n(i) <= validate_new_tag; alloc_tag_n(i) <= '1'; end if; -- + end if; -- }}} when issue_read => -- {{{ st_tmanager_n(i) <= wait_read_finish; -- }}} when wait_read_finish => -- {{{ if wr_fifo_free(i) = '1' then -- - -- st_tmanager_n(i) <= validate_new_page; -- validate_page_n(i) <= '1'; -- - -- + st_tmanager_n(i) <= validate_new_tag; alloc_tag_n(i) <= '1'; -- + end if; --}}} when validate_new_page => -- {{{ -- tmanager_wait_for_fifo_empty_n(i) <= '0'; -- tmanager_tag_protect_v_n(i) <= '1'; -- setting tag protect should be done 2 cycles before going to idle -- tmanager_tag_protect_n(i) <= tmanager_gmem_addr(i)(M+L-1 downto L); if page_v_tmanager_ack(i) = '1' then validate_page_n(i) <= '0'; st_tmanager_n(i) <= wait_page_v; end if; -- }}} when wait_page_v => -- {{{ st_tmanager_n(i) <= idle; tmanager_busy_n(i) <= '0'; tmanager_tag_protect_vec_n(i) <= '1'; tmanager_rcv_served_wait_vec_n(i) <= '1'; -- }}} end case; if tmanager_read_tag_ack_n(i) = '1' then tmanager_read_tag_n(i) <= '0'; end if; if tmanager_clear_dirty_ack(i) = '1' then tmanager_clear_dirty_n(i) <= '0'; end if; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- tag mem -------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then clear_tag <= clear_tag_n; we_tag <= we_tag_n; tmanager_read_tag_ack <= tmanager_read_tag_ack_n; tmanager_read_tag_ack_d0 <= tmanager_read_tag_ack; wrData_tag <= wrData_tag_n; wrAddr_tag <= wrAddr_tag_n; rdAddr_tag <= rdAddr_tag_n; rdData_tag_d0 <= rdData_tag_i(N_RD_PORTS-1); end if; end process; process(clk) begin if rising_edge(clk) then if we_tag = '1' then tag(to_integer(wrAddr_tag)) <= wrData_tag; end if; for i in 0 to N_RD_PORTS-1 loop rdData_tag_i(i) <= tag(to_integer(rdAddr_tag(i))); end loop; end if; end process; process(tmanager_gmem_addr, alloc_tag, clear_tag_tmanager, rcv_read_tag, rcv_gmem_addr, tmanager_read_tag, finish_active, finish_tag_addr) begin -- write tag alloc_tag_ack <= (others=>'0'); we_tag_n <= '0'; wrData_tag_n <= tmanager_gmem_addr(0)(GMEM_WORD_ADDR_W-N-1 downto L+M); wrAddr_tag_n <= tmanager_gmem_addr(0)(M+L-1 downto L); clear_tag_n <= '0'; for i in 0 to N_TAG_MANAGERS-1 loop -- linked with we_tag_v, don't change the order of the loop if alloc_tag(i) = '1' then alloc_tag_ack(i) <= '1'; we_tag_n <= not clear_tag_tmanager(i); clear_tag_n <= clear_tag_tmanager(i); wrData_tag_n <= tmanager_gmem_addr(i)(GMEM_WORD_ADDR_W-N-1 downto L+M); wrAddr_tag_n <= tmanager_gmem_addr(i)(M+L-1 downto L); exit; end if; end loop; -- read tag rcv_read_tag_ack <= (others=>'0'); -- first ports (default 3) serve the receivers for i in 0 to N_RD_PORTS-2 loop rdAddr_tag_n(i) <= rcv_gmem_addr(0)(L+M+N-1 downto L+N); for j in 0 to (N_RECEIVERS/N_RD_PORTS)-1 loop if rcv_read_tag(i + j*N_RD_PORTS) = '1' then rdAddr_tag_n(i) <= rcv_gmem_addr(i + j*N_RD_PORTS)(L+M+N-1 downto L+N); rcv_read_tag_ack(i + j*N_RD_PORTS) <= '1'; exit; end if; end loop; end loop; -- the last read port serves the tmanagers in addition to the receivers rdAddr_tag_n(N_RD_PORTS-1) <= rcv_gmem_addr(0)(L+M+N-1 downto L+N); tmanager_read_tag_ack_n <= (others=>'0'); if finish_active = '1' then rdAddr_tag_n(N_RD_PORTS-1) <= finish_tag_addr; elsif tmanager_read_tag /= (tmanager_read_tag'reverse_range=>'0') then for j in 0 to N_TAG_MANAGERS-1 loop if tmanager_read_tag(j) = '1' then rdAddr_tag_n(N_RD_PORTS-1) <= tmanager_gmem_addr(j)(L+M-1 downto L); tmanager_read_tag_ack_n(j) <= '1'; exit; end if; end loop; else for j in 0 to (N_RECEIVERS/N_RD_PORTS)-1 loop if rcv_read_tag(N_RD_PORTS-1 + j*N_RD_PORTS) = '1' then rdAddr_tag_n(N_RD_PORTS-1) <= rcv_gmem_addr(N_RD_PORTS-1 + j*N_RD_PORTS)(L+M+N-1 downto L+N); rcv_read_tag_ack(N_RD_PORTS-1 + j*N_RD_PORTS) <= '1'; exit; end if; end loop; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- tag_valid -------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then we_tag_v <= we_tag_v_n; wrAddr_tag_v <= wrAddr_tag_v_n; wrData_tag_v <= wrData_tag_v_n; end if; end process; process(clk) begin if rising_edge(clk) then for i in 0 to N_RD_PORTS-1 loop rdData_tag_v(i) <= tag_v(to_integer(rdAddr_tag(i))); end loop; if we_tag_v = '1' then tag_v(to_integer(wrAddr_tag_v)) <= wrData_tag_v; end if; end if; end process; process(invalidate_tag, tmanager_gmem_addr, alloc_tag, clear_tag_tmanager, finish_active, finish_tag_addr_d0, finish_we) begin invalidate_tag_ack <= (others=>'0'); we_tag_v_n <= '0'; wrData_tag_v_n <= '0'; wrAddr_tag_v_n <= tmanager_gmem_addr(0)(M+L-1 downto L); if finish_active = '0' then if (alloc_tag and not clear_tag_tmanager) = (alloc_tag'reverse_range=>'0') then for i in 0 to N_TAG_MANAGERS-1 loop if invalidate_tag(i) = '1' then invalidate_tag_ack(i) <= '1'; we_tag_v_n <= '1'; wrData_tag_v_n <= '0'; wrAddr_tag_v_n <= tmanager_gmem_addr(i)(M+L-1 downto L); exit; end if; end loop; else -- this write has priority and it happes at the same time a tag is written for i in 0 to N_TAG_MANAGERS-1 loop if alloc_tag(i) = '1' then if clear_tag_tmanager(i) = '0' then we_tag_v_n <= '1'; wrAddr_tag_v_n <= tmanager_gmem_addr(i)(M+L-1 downto L); wrData_tag_v_n <= '1'; end if; exit; end if; end loop; end if; else we_tag_v_n <= finish_we; wrAddr_tag_v_n <= finish_tag_addr_d0; wrData_tag_v_n <= '0'; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- dirty mem -------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then -- dirty memory for i in 0 to N_TAG_MANAGERS-1 loop rdData_dirty(i) <= dirty(to_integer(rdAddr_dirty(i))); end loop; if we_dirty = '1' then dirty(to_integer(wrAddr_dirty)) <= wrData_dirty; end if; end if; end process; process(clk) begin if rising_edge(clk) then we_dirty <= we_dirty_n; tmanager_clear_dirty_ack <= tmanager_clear_dirty_ack_n; if finish_active = '0' then rdAddr_dirty(0) <= tmanager_gmem_addr(0)(M+L-1 downto L); else rdAddr_dirty(0) <= finish_tag_addr; end if; if N_TAG_MANAGERS > 1 then for i in 1 to max(N_TAG_MANAGERS-1,1) loop rdAddr_dirty(i) <= tmanager_gmem_addr(i)(M+L-1 downto L); end loop; end if; wrData_dirty <= wrData_dirty_n; wrAddr_dirty <= wrAddr_dirty_n; end if; end process; process(cache_we, cache_addra, finish_active, finish_we, tmanager_clear_dirty, tmanager_gmem_addr, finish_tag_addr_d0) begin wrAddr_dirty_n <= cache_addra(M+L-1 downto L); tmanager_clear_dirty_ack_n <= (others=>'0'); if cache_we = '1' then wrData_dirty_n <= '1'; we_dirty_n <= '1'; elsif finish_active = '0' then wrData_dirty_n <= '0'; we_dirty_n <= '0'; for i in 0 to N_TAG_MANAGERS-1 loop if tmanager_clear_dirty(i) = '1' then tmanager_clear_dirty_ack_n(i) <= '1'; we_dirty_n <= '1'; wrAddr_dirty_n <= tmanager_gmem_addr(i)(M+L-1 downto L); exit; end if; end loop; else wrData_dirty_n <= '0'; we_dirty_n <= finish_we; wrAddr_dirty_n <= finish_tag_addr_d0; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- axi channels control -------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then axi_wr_indx_tmanager <= axi_wr_indx_tmanager_n; wr_issued_tmanager <= wr_issued_tmanager_n; axi_wrAddr_i <= axi_wrAddr_n; axi_writer_go <= axi_writer_go_n; axi_writer_id <= axi_writer_id_n; for j in 0 to N_WR_FIFOS-1 loop axi_rdAddr(j)(L-1 downto 0) <= (others=>'0'); axi_rdAddr(j)(GMEM_WORD_ADDR_W-N-1 downto L) <= tmanager_gmem_addr(j)(GMEM_WORD_ADDR_W-N-1 downto L); end loop; if nrst = '0' then st_axi_wr <= find_free_fifo; wait_for_write_response <= (others=>'0'); else st_axi_wr <= st_axi_wr_n; wait_for_write_response <= wait_for_write_response_n; end if; end if; end process; issue_wr_axi: process(st_axi_wr, tmanager_issue_write, axi_writer_free, axi_wrAddr_i, tmanager_gmem_addr, tmanager_tag_to_write, finish_issue_write, axi_wr_indx_tmanager, finish_fifo_dout, wait_for_write_response, axi_writer_ack) begin axi_wr_indx_tmanager_n <= axi_wr_indx_tmanager; wr_issued_tmanager_n <= (others=>'0'); st_axi_wr_n <= st_axi_wr; for j in 0 to N_AXI-1 loop axi_wrAddr_n(j) <= axi_wrAddr_i(j); end loop; axi_writer_go_n <= (others=>'0'); axi_writer_id_n <= (others=>'0'); finish_fifo_pop <= '0'; for i in 0 to N_TAG_MANAGERS-1 loop if axi_writer_ack(i) = '1' then wait_for_write_response_n(i) <= '0'; else wait_for_write_response_n(i) <= wait_for_write_response(i); end if; end loop; case st_axi_wr is when find_free_fifo => for i in 0 to N_TAG_MANAGERS-1 loop if tmanager_issue_write(i) = '1' and axi_writer_free(c_rd_fifo_axi(i)) = '1' and wait_for_write_response(i) = '0' then axi_wr_indx_tmanager_n(i) <= c_rd_fifo_axi(i); wr_issued_tmanager_n(i) <= '1'; wait_for_write_response_n(i) <= '1'; axi_wrAddr_n(c_rd_fifo_axi(i))(GMEM_WORD_ADDR_W-N-1 downto L) <= tmanager_tag_to_write(i) & tmanager_gmem_addr(i)(M+L-1 downto L); -- if tmanager_tag_to_write(i) = tmanager_gmem_addr(i)(TAG_W+M+L-1 downto M+L) then -- report "match"; -- end if; axi_writer_go_n(c_rd_fifo_axi(i)) <= '1'; axi_writer_id_n <= std_logic_vector(to_unsigned(i, N_TAG_MANAGERS_W)); st_axi_wr_n <= issue_order; exit; end if; end loop; if finish_issue_write = '1' then for j in 0 to N_AXI-1 loop if axi_writer_free(j) = '1' then finish_fifo_pop <= '1'; axi_wrAddr_n(j)(GMEM_WORD_ADDR_W-N-1 downto L) <= finish_fifo_dout; axi_writer_go_n(j) <= '1'; st_axi_wr_n <= issue_order; exit; end if; end loop; end if; when issue_order => -- just a wait state st_axi_wr_n <= find_free_fifo; end case; end process; ---------------------------------------------------------------------------------------------------------}}} -- page_valid ------------------------------------------------------------------------------------------- {{{ process(clk) begin if rising_edge(clk) then wrAddr_page_v <= wrAddr_page_v_n; wrData_page_v <= wrData_page_v_n; we_page_v <= we_page_v_n; end if; end process; process(clk) begin if rising_edge(clk) then if we_page_v = '1' then page_v(to_integer(wrAddr_page_v)) <= wrData_page_v; end if; for i in 0 to N_RD_PORTS-1 loop rdData_page_v(i) <= page_v(to_integer(rdAddr_tag(i))); end loop; end if; end process; process(invalidate_page, validate_page, tmanager_gmem_addr, finish_active, finish_tag_addr_d0, finish_we) begin page_v_tmanager_ack <= (others=>'0'); we_page_v_n <= '0'; wrData_page_v_n <= '0'; wrAddr_page_v_n <= tmanager_gmem_addr(0)(M+L-1 downto L); for i in 0 to N_TAG_MANAGERS-1 loop if invalidate_page(i) = '1' then page_v_tmanager_ack(i) <= '1'; we_page_v_n <= '1'; wrData_page_v_n <= '0'; wrAddr_page_v_n <= tmanager_gmem_addr(i)(M+L-1 downto L); exit; end if; if validate_page(i) = '1' then page_v_tmanager_ack(i) <= '1'; we_page_v_n <= '1'; wrData_page_v_n <= '1'; wrAddr_page_v_n <= tmanager_gmem_addr(i)(M+L-1 downto L); exit; end if; end loop; if finish_active = '1' then we_page_v_n <= finish_we; wrData_page_v_n <= '0'; wrAddr_page_v_n <= finish_tag_addr_d0; end if; end process; --------------------------------------------------------------------------------------------------------- }}} -- rcv status eraly update -----------------------------------------------------------------------------------{{{ tag_trans: process(clk) begin if rising_edge(clk) then rcv_tag_written <= rcv_tag_written_n; rcv_tag_updated <= rcv_tag_updated_n; rcv_page_validated <= rcv_page_validated_n; end if; end process; process(we_page_v, rcv_gmem_addr, wrAddr_page_v, wrData_page_v) begin rcv_page_validated_n <= (others=>'0'); if we_page_v = '1' and wrData_page_v = '1' then for i in 0 to N_RECEIVERS-1 loop if rcv_gmem_addr(i)(M+L+N-1 downto N+L) = wrAddr_page_v then rcv_page_validated_n(i) <= '1'; end if; end loop; end if; -- for i in 0 to N_TAG_MANAGERS-1 loop -- if validate_page(i) = '1' then -- rcv_page_validated_n((i+1)*N_RECEIVERS/N_TAG_MANAGERS-1 downto i*N_RECEIVERS/N_TAG_MANAGERS) <= (others=>'1'); -- end if; -- end loop; end process; process(rcv_gmem_addr, wrAddr_tag, we_tag, wrData_tag, clear_tag) variable wrData_compared: std_logic := '0'; begin for i in 0 to N_RECEIVERS-1 loop if rcv_gmem_addr(i)(GMEM_WORD_ADDR_W-1 downto L+M+N) = wrData_tag then wrData_compared := '1'; else wrData_compared := '0'; end if; rcv_tag_written_n(i) <= '0'; rcv_tag_updated_n(i) <= '0'; if rcv_gmem_addr(i)(L+M+N-1 downto L+N) = wrAddr_tag then if we_tag = '1' and wrData_compared = '1' then rcv_tag_written_n(i) <= '1'; end if; if clear_tag = '1' or (we_tag = '1' and wrData_compared = '0') then rcv_tag_updated_n(i) <= '1'; end if; end if; end loop; end process; ---------------------------------------------------------------------------------------------------------}}} end architecture;

gpl-3.0

d7ad03f8bc1b5e86c207f04514c00d70

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fslt_2AXI_4CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 2; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

d5730168d4285270a67fec42f00dcb43

malkadi/FGPU

RTL/floating_point/fsqrt.vhd

-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.1 -- IP Revision: 2 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_1_2; USE floating_point_v7_1_2.floating_point_v7_1_2; ENTITY fsqrt IS PORT ( aclk : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END fsqrt; ARCHITECTURE fsqrt_arch OF fsqrt IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF fsqrt_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_1_2 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER; C_FIXED_DATA_UNSIGNED : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_1_2; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_1_2 GENERIC MAP ( C_XDEVICEFAMILY => "zynq", C_HAS_ADD => 0, C_HAS_SUBTRACT => 0, C_HAS_MULTIPLY => 0, C_HAS_DIVIDE => 0, C_HAS_SQRT => 1, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 24, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 24, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 24, C_RESULT_WIDTH => 32, C_RESULT_FRACTION_WIDTH => 24, C_COMPARE_OPERATION => 8, C_LATENCY => 28, C_OPTIMIZATION => 1, C_MULT_USAGE => 0, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 0, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 0, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 32, C_RESULT_TUSER_WIDTH => 1, C_FIXED_DATA_UNSIGNED => 0 ) PORT MAP ( aclk => aclk, aclken => '1', aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => '0', s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END fsqrt_arch;

gpl-3.0

461b8c766e2b18b936eeb20fc880566e

preusser/q27

src/vhdl/queens/msg_tap.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.utils.all; entity msg_tap is generic ( D : positive -- Message Buffer Depth (Size) ); port ( -- Global Control clk : in std_logic; rst : in std_logic; -- Tap Input iful : out std_logic; idat : in byte; ieof : in std_logic; iput : in std_logic; -- Tap Forward oful : in std_logic; odat : out byte; oeof : out std_logic; oput : out std_logic; -- Tap tful : in std_logic; tdat : out std_logic_vector(0 to 8*D-1); tput : out std_logic ); end msg_tap; library IEEE; use IEEE.numeric_std.all; architecture rtl of msg_tap is type tState is (Receive, Hold, Transmit); signal State : tState := Receive; signal Buf : byte_vector(0 to D-1) := (others => (others => '-')); signal Cnt : signed(log2ceil(imax(D-1, 1)) downto 0) := (others => '-'); begin process(clk) begin if rising_edge(clk) then if rst = '1' then State <= Receive; Buf <= (others => (others => '-')); Cnt <= (others => '-'); else case State is when Receive => Cnt <= (others => '-'); if iput = '1' then Buf <= Buf(1 to D-1) & idat; if ieof = '1' then State <= Hold; end if; end if; when Hold => Cnt <= (others => '-'); if tful = '0' then State <= Receive; elsif oful = '0' then Cnt <= to_signed(D-2, Cnt'length); State <= Transmit; end if; when Transmit => if oful = '0' then Buf <= Buf(1 to D-1) & byte'(7 downto 0 => '-'); Cnt <= Cnt - 1; if Cnt(Cnt'left) = '1' then State <= Receive; end if; end if; end case; end if; end if; end process; iful <= '0' when State = Receive else '1'; genParOut: for i in Buf'range generate tdat(8*i to 8*i+7) <= Buf(i); end generate genParOut; tput <= not tful when State = Hold else '0'; odat <= Buf(0); oeof <= Cnt(Cnt'left); oput <= '0' when State /= Transmit else '0' when oful = '1' else '1'; end rtl;

agpl-3.0

07724aea8e5ffb90d37be67eed5a4db8

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_8Stations.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

b6136fdfb9d6774cf3b47bc091e8d20c

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_6Stations_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 6; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

2c026ddbdfc513ba5fa5198546e4fa19

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_pkg.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block P+DoZGbwQYNTfamCkaX4eNyoapbAz7CBycAO7nXMXBv2n7txtzq5Pj3Gw4MqZKLQ37wOxgpqLG4s J07nNOyh9A== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block degCxfvopyg6qX2tNc77hRfXQJiBDRJkYl1TlU6X4bPgmPo111fUzXF3RnGCkBUBV9bwAZIPqxDl dpLCw4NrT5A4K5+FQWz0Miz3Yv9znqMV60M7/AmYMs/1frH2w2/OjV7DnVKGULEVthmz3s1bII5a /pZA4ht7hYQ2PTOuNoQ= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block lxSDwuB6RhthDOlKX9B4Lfx6Zxl8rPNhtammZtBLixE09MfuVWfJJuax85PHiCAcg7h8NQOVWgzQ WN6e0ykge1o6DTI2QJecTPVZlGtGguGh8Tes+yh0OFpSG3EMvUW1BMD5VMlkCz1sx/D6wngfFwBD JNIsZbG9bI4HHYETUWPof9v6tCwWlSv3PbBMU5l7uLaRoyQJOXaAVG8xFRMBT2genQy0F7onxgYc HoBNaVpLrkzR9Zv4UYHs9Efdng6OiILG5I/zOUXY9sbpUHBbPigDpOQpaOKH3kEkNufCZ/YMYInm JOtbRS6tcdH65jIJBqo2uiWPqTYkV5UFIswGKA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block k1Igbghb9tnE1hKZAFS6F3dCAodTQKznJOHcHYzXbrXcz5FYowGEwK1qw4nTRtb/3aky8o+ky66o /e+ZpwDi0UnEN84b1rLhmgaoAgAvrqTxID6DdNMlMyIQeO5aM9qI5sQtII9dQ0+JTgwTEbnex3CR RY6rFPWNZjj38odZJes= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block BBD40RKOZHIcxNddQXxF+m+4EXEch/XpqXBvDj9hU7hbLgpkKnc7mhoJBDLLDa1jtsIg9o2XAUZy nomklCKRS70XIkjkS+CoyMgyjCJ2kZ+nDcvf2wePElTE5XIaJqujHMr7+lf2eNS2E09KepOMBlCD l8k7/gYTOrc5NJeL6PMGBNik2OZEEBKUyTcVNhUbXngRE2/KQYUi31Qq9nTxCkWfmgIlXgdGmkFc WX371L4MN5EfFs/gDXKt/y9vxpqARZVa2S0y/rwpMjN2Ge2hOu68+3VEWJ7OAdvDpimYXabU0uUT zJmn9DGWQzl9MHlIV4NhB7S1nLPtilbd+kf7xg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 90000) `protect data_block LYoE+O9Z96el/BBD6NBzQcsbXWrDHju4zX6hRPz6J00q9aJWryA5jf65IXkzenhc5Z35/10GNMWb m8DaL//rSdBHC0SZpb/obpGZCOcSq1XK6Xwc2+HAqNYuHNmUxsvTwhO9yPAuv8zRJYP6N2KQDwZw k/txnTHUu8Mmk8sW1MDEf3WSBY6/mS6Sf/xO0mNG1UB1jVeKRNv5LMP6/v86PftBNw8KbumAImko NAikr8YhwkjTxWuCVhiKw+ncyj9pYRBUULpfJQZV3yAM1sVdwi1ihyZrMK69zKvh2s4FXF42d7AY H9HoPT8QrIlu3Bx443hlQRuF0KOmP4VVuCm8ZF8Newd5w0nGaGCnhI4/ywQuDBQa/fFe0gS3IAkp 2NQ5GhNCcjVEyQMsFl4pfoRQ8Hi9ebj/QlhsNjIEd1WpjCufL1GCz6f6gxKxvBNXp3VES24VBDzj 0MpvKNqfNqPr4aDUJsAyVeDIT2D1JC6CnrsAzWKHg86VjqbIDP1X7AawJYURGem8qvuXBWbvfR5o ob3tDH8LQVOG3tcBL3gvEXvDjV83nmXC3fbUFu6eJDh/eEoYzArhtOhFYIMtQcENWMFDHkWW5Zoz PKt0cjwSkjfPkqOR/G6xa/Se52R6YwM0oF38ZmCKpGps0SoRJY+dmHlepHcKigEXRVz26SCpEt7q mz/MJniZOVz66hunjGvk3RIPcUb1RBKcYtjq9a+QKyu0f1MDrQh//LJi48yG5nzz2l7OHGy+jtF3 XInUa+KwVZQcgFFLq6rbGljiS+4XD7dcKB3x6tJnBca2CtNQ6y0kAncbFCoiBXBHz97bVSbr91UQ RCxR3nJm3lw5gVRKg0owAvy91cPm+nvlh/1r3zpHK034s7g7Or0U4Q7cH2Rl1DCj/8gU84YJ24m7 b7FkBaYzRPnL1xp4syZoJtjDqjlg6tZYbRhgEE3TgywpBFrtWGa7We/e5ALhBCShRMkc9sUbRSqM qKSaWsxPWF/4Xr7ir/hKVjZOCciQI9AIeusumcGbV36LZjnqOCex0t3yVSFTtvH+/+oP2QVtNUTg vewtblIszVnKWstlMxPrbn9tZ5+rDiqkLGU6mDV7I06v38gKq3pBqGqhPTjmZf8if/1I8T+gw4Va 6HoK5CQyxqvosdHC8pezY8OeulDLZNIKqL1AizDD2xIy4W+sFXD7QS3Ivl4R4Zwe1zAVUwLjyViB bM2OS7YB9ci0l0DEVl3muVBKgPnj4QQqUl+uZEdtz5boBpULeANIlpEU23RzY7yMfYracjIiLGuZ S4XYgPvebJyM4rTTqGABBb9Vi2n6U/92RBktQIL/Pe0qUCD266JdG7KDqVI3FphvqZxXTIuPj+7X BAG/v6/X689lZGmxxICdAMggXAJYPdFd8E/8AKTFM+RLERIZ2oPq8+xX/iid2kOEEn1D/FE+/2Vm MpsGTWq53MXnsin89H+/RIm4mTkkfLnUKG/aaWxR/U5/vihh1J5g1pj2SqXSDnZ7AkwABV5shhsn pKwA3mEJLF15tQcbyMoQS6H7tAaotJgtDjY2p5ZlsQGGgHjAORvcuXVsQkfPAUaAmik39Lck4iEr Z9sNNeUqgI3IaO0pTTW/dQyjH342nhTacGVXDdijn+TrzVke4kb//+35u7PO+Cz6KMZTgY9KXrbs RsKYFMkrwaPq+x3bimjMPNdVaPtggsIHRoZlw0QssmDZEVdh0znC/Nh/Epny3jhPHtg6PJaidi3R 75Cp27Tb+1V5hbCeGzpFhFYUUHmflEPz40Gi9G7Bndb4S9x2R2G85PgRldoxLMuX7tuxipuLi/bR lXkLlgcctErexsC144HDsReZ6VBGq4HH8iPv9Kn5b44vsHsWomDD2GEFrjN/pkKFnB58K0505WzU MT7Faia+973GUfSUASfLYAvCRVlVYBI1D8QPUkNxBw8oBV7oVl5YRgUeK6lMEQY9e55iPF0leXQ0 8rSBg33d9/Rh3S1IY/AEM4tOW2siKGP0P6m9JMNGC0j+FLoWe9poYKjU6sTQWfs74YkqO8AimpCv jfwnu6uzqB3SThYKRsxL4s/1zHJ8Ab2qvJhJ1JngB80AanfTU0FN5sw6R5yztjS1ziMVTjCvMFWz gQMMSLS4+mGeS2RpJ1UXRddSdbzROk/T4gKJfDX0q+sKSuE9Flz3yv2VHOiba/2mbhPwVfnvZbBQ ZUhDm9YT/VbxPdvyP97HZWjEbuNY7LNV6hit+qXqgohtBylUqfFthgrL0v0e33bwhNORi3+ipYTW /HkExok4bwp3XSeRoavmpjR+74C0ddz7dL3/uchQWygDktFSDZHJHrtVEfLn9xoRE9fn+d/T3n27 iyxgi7pqzibFHXuPs+ElIjntQk17n8b2Y1Z9yf7F0ANQ/HU7MaFOpbij1pF73sgk+sPo0hxlC/8e E9BBTws1Ym/yUsUxJlKcQTw9+yq5gVgzWDmXWMNEqo1wDPNXJPSJVR1S2Zrt+R9ra6t+DX0SnPx6 073K0mx+2DZz0fw0Z5j29qBPxwzGhPL52JIBSFcl5uUjc4+mAHvSUu8nf9e3tuqg6wQMCTTbjO4p FgzGQBO5lQT3zVLY4jx6hkZpQ3udkjTXPOF1+8R0Oc84ikxI6dmnQmAzK8xQcCXz/C0MUtHOcw4D 0boM40MWMrLkJFy/5S1wOiQboRUhlURBCXeUAr2TDrBkevwIE84r98YCKMLZXuxUtj+AoVxaH3Eh 3DQl/jUzgU2vpuMOnE7Ml33BAJT0KZXkekvrgN26nkn/5Y1VT6jKTJc/xWBDezqr44VM+gs07hHT EpLJl6IZjo0zdy3HpoucOhJp14FUhGX0qTip7gm6To7MeCX6iUHV0NCL0MtOZDvTJXd8dk6mRb5u hKbfGxQqG/tL7GttY3Y928rTvVfEz9BQRl8lAPA8JaX7CFXbrAQa6XGIi4q8qfYEDx2ilCaoTf4L aH7rmATcRbGzHhkBUPaVL2b0s4KbvoXS6+BML8+cmKhxy96k9l8uahdNbVBDU9zPXBW6f3q/GFOP FkRxEttV15sAm2g2aWnaBSWhlrr0ycDX2Jnw9zLMJ/gGbkH/B4dVCpBursdCZ1GoPIWkSDTUZ1ZD NaJbToKKQDtZZGUbNWkGo/65T4eiO490qi30d7MlFP5wq/8cDqObDI5sh5R5dQqv9Zycwj6f+gA0 Yj++ht4mljZl3+IEopFauqWlHvbJdaZFV3gsP1oHgcoDAl86EBv4B1+RpiG0C2ljBWH7dii7s0mg UOAb/NqlSEjYaTINxF1n04h5HPjDjlzE2oMIxTOsK3/AG0xRr65U5IgUDC9gMRovhk2+G9N75uQm +kseMoOSKJ1SLLbKpI69hkzy6TDLGOP2k7tBJAuZnKueWuEAZt/c7/1Bos4vanne8SoqVMoin3qL hQQpC0eIKJku3On1LKzH58MqTHqBAeQBVY7QWGTmL8tSe3/JaiuiZUCDo5DHzuSs9f6qF+5Mg9gV v7wPgYa80q26hR5MtmhgCN2SbBkGmokZTdC7Ud4sGCgOmoBtHTLxWgClOvq/AQG1EELZhiVWGzyt uKuMNLO6Oltqit9Xs72vZcykpc8337MT3efq5qCY48KUGQgZAZ3JcLDxGUgh5/Kc+nLmQv8mRZto rZrgOlZkXRStXWQxeJq9+bWAOJ/ndEqdYqRFHm+4of65+cUSIDX8T9mHUJWxSZLEGC2Haj8fpxwN J72PQqutwkJcwbg+0dgEPQm2+cstPyyIp1SJzCRV+vgNMZ95HjFe3AweehUAZttqo8bV3wphOXya BrNlNJ0fncEECNW6g5cU70+RrOMADv/eZWRs1KyUFQMi1d2kseydH3W0RvMXeTkG02bLRWbw6Y4W iiW0fI0tgsP3wo6rBdLjKHyOWKbf1rG/M1fm/12Czf/QLDg5eahqoLCotmCnrtef1ibd1M3rv3WS yex9JeYiqXfP98Wjjvz+LErlZGUgVEg7WLgW4YPnoCt4IeSwMuCdStCzxg17nkyYem23yN5smEcG 3WOox0k02joe8kLjy+loGwEXjcz23H4/PfzuaSrKdA6tVA5J7fKMyW756Y53svxqClIMJ9WkQ9zs NdXZAhggDRkzmqOg7Z67vg1LtMpZ8PmA3O0Yj9kxH4C0ctlvJ8SYEz3ayx1Ja270VpWcvmKMAKHS /0+x1+UKCVTZL5wpx70bnGAN40+GuJParGjvgvqwdgMxO41hCwFR+5D1BSQ5MA1ZbjkZaG0VKeSH 9jHuhkVBA+LaOmVzKp64zw+a+1SiLTaEAch4KcOGg8Q8hmVKG+D3V0Bn6Is5G5d8WvXxnOE2JDJr Qji3c1/ZZx1y8c6+qRCEX47Z8EfwXIXssEb+eTVnrnoQBVhMd7Izc5OY70X+H3ea9UfJXgts+/m3 nScYifMUqSPgnwzamgpuAYaIpASKJtSN2f+2pZD7K/Yh1gI6TprX9cbd9w/ceYFY9+Ys7dy/1jDd LnLSByqCzCr72X1vfc1ePU5ds5XqOsxjWXNHhbtq354thWZ4Z0s99ngn1bW79Ccobjx4SHWNOsTU 7Iasf7/vfs+Wdf3Z7tgbt8ZgDgdZF/IwfZML6SbcA8W7c5YUa9hx1mNVwun4cVhXJYH9CA5u7wEN BKyvZ4O19wMv31u7gSSeihqVnlQngBzAIGSuxfy3tFX0h97Z0dqBVHiQFVU2tLL26Cx7Mm6v3qZr rinCKnjKUT86BS6eHSg4EDw1znV9pNMyWhfkV9IuEac+BNLyXxRIXMHGg1t3NDCHc5JoMonuDBYg hDlWRorL4Gg0sgT+Gh+0XO7hBaNRgX65D4J5iXoJjnNcLMeDLLdkHBv2Z9LklAT8vyuPTHLcwAqX Jda5nM95H/aWfIH4RoRHyxC2+7fzgNYU4JN6UH6mZsjDQi7QMrSVcNAeVge9G+9e108FzZKJLQcv WUUIVBRL+3d7SRqgKU8LkUeZZfacdnalzUj6yb4bTHvOGu3wapQK20jcQA5z90oJdEPzOevNB7aJ 9bbRNdk1aZglrRTmLgxLj15q4zrGTGyyxLFzG4dS/RGugeT5e9UCbc2qE6NxP7Z5Pa3N5/mqGOFL R67Vcp3CJ1SoQIlNex94xnhta8jIui6rmwiTIFO6vc18I0hY4aDik/RDgastYRmxUdKvQLC11aXg /k/jMchzZ1owqknC3wJd+wbvqBY5ITsNtX9K2/o4XlXbx5YObIo9T/nzzP5S93J8UrjeCPJ5CfUS f2w05hqWbCzquZsKY5bX4/sqhf/toBD0h5TrhBgqRHTC7j7UoA57NDw/c7fwMNgQLSAk/xpWg3Ke fQqHVpj2UlM2Pk1ejjhoGsX0jYWLhUvUZDc2kFbcSRvWIKtUfxHUu7lmA0Ma3ApD5RpcajUxmj/0 S2LF7RtMaKknqMXSgOa7Q0fLAimHhucZ8nvWkv/nnGfdcfRxVziTOA1HYa8HUmgvrx1pEF3U3CyC bJAxnwCZbx4JITcvitaUy1GUDL6UqrplegvZmV3Dix4dfU0Qo0I3TX3VRpHDu2p6A0kCQueC3WH1 Et59l829gSm+NkhPRvs6v8rWkZIdZ1Dovobd2ddM7dIz1cmzPZQtStNBe8i4G+pSMdmgmN5ANjZa sRbQl0PTTCDCMDTZ9w3Ba2splAbw6z3RGg5SfMFCzk53+WxWluqxwxxwnC6pkcZspAKsYUvxbJU6 OrD//vQ+iP+24Nb1QLRacrtS1mbcGgvT4li9rPcDS7614Uc+uQTCWxQbYUBTV+TFAEa06bjIp5MZ bJ3i1ItM6pGh8tvvQ7cyoaASg7Qba/VXd/z1Rl+yaCZBlidprOJym75kUolKJODo28lxQhPjDgBF rCEnknZOjkX+Z3JwqFSMPJDSoSssqipXF0u1/0zNLjntDfR7gAHEet9SoMdOoRod47R46b4bbg7B K79wNQeD+aUGUbZbTzHYt6KgP3I+yJY2YZTPJimgLwrRaI5hrnZB5cJ3z/bD+nK0NrjgFELf8soi VC2d6lX5MRHV1fpcL1eXYBq2GEA2PTexRf1tFNu6Ok1kjSQ64x69plR74cImCIPs7Lmit2dKSoYu 8n7wZU3GWOForGPC2lRNpegb4ks5bLXe4BvrbdMVUg/EOwKN5XRMnzRnZMbGsXadyvZ0amNZqbrT Fq3FdIY7tsiO2cWh/O+ac8lJs6XLYgvqX5VQrWCd7w3cH8CM3MzvJrSbXjj9Nu74pYqGR5FIhvvV 5is+vXVSZYWvSPWXvK1P/uy60dSZEmM8pO3e3rYoHGwGpJhkuNC9UJ2o+u07jLwlAEE2dTzwdm+Z nBUP7S5LtQEHF7E+hprlmaeuGG7Q3/detUdy2qNXZqUpMhrBof/6vYPP0pZWamPjnEGiuJZxFvgo cPIvRGyuG28rrRjkq85+co5svaM62cjP+nYAqYp+fhBd7wOBPwdESJ78SDMSokMaCEk6lUWV3Dn4 Ir40ihoWlJHyJMQknONiQVzjULYWVa4wtxpjqY9AOEYDe4njj2rJOJaFQmV/6FqDKeL/BhGbTWja 2mbOJ+AlD56wnMaOB49TxnAAGi9yaU9cMs3XkMOxGJXB5rjwC7l+/2rov6P1dWVOC0sFvnPkwlA1 mbYt95K9yay7UzNziIaME2Jd6KB6CnlWFDau/7prMOvY127iDfIc7Tg2DlicXqRhH060biANZNht lIDBQxBzHyXMsqY18ipgJ7tyA6dKhqb40j8S6oxW52Q8zYvAAaieh61Q7qyQZMbBl+5l5FZPrnT0 HtrGFZ5/uN3PuGNtPYlMQCg1tyPX8Q0n3qo6zHnc5+F5PTTkbyc6dExj3mkEyeayy4IToKhXgD1s IKktZ8BxrR+wt4MfBnsn+abwuxDbqasTE8T2ma5t+53ymEEErnZcOVbZge0+Bu5rE+A1vuKKmUw2 YseS+qNs3xYqi/g/+1BS4jRMAwDjioA5vVqnnKamDp9KZqROeTvt/+WelbYKOuMoQAGgyYDDrlHo IXM4OL8+oe9pdYchWjrkDmVcrsNTWVBI28APiFYbT0EfJMvj+jurRu/jwTqFYolk05ACwiLZR4Q4 GiRnKsxGsWw1C0MAw8rPZ4WvpE1q2kk/RKkTqmFUfbnvvwBziS4iVEkXzFMy0znSQjFVoniA/koL 9CCBm9vGomY3MixVvAnDpd3xi2oA1iim2jI3DqoqJhEXrx59wxmmsD6ruL9j4qMjyi2t9eYYwrn0 iANRqNTSFbUUnD91UtPvV35DzVMDavhn93vFvt6BuAAVKajnbG5GMzZ+q0WIg/ARCKSBmsa7Uj7q i0dA4+K+06pmMTIYH9h2IrJsZ5dCoAGOwh5v8jx06K4uax7VwsaLYnp5MyaW89Vq8AVkPRXB8Ae8 9u1I31hmuGKdg+IhVVlDGWSHtlD99I6b5bLlKs81v+cnO/wOxvMTOtm0eI/A/SvgEU0gxpUJmt8e zmuRw0du2XlsjwhEP3DEN0AHw4xd6sCsHH+u5YWxtSSAmlQ1sqQEWZ83WIXKiLDrmekvTPAN66+H NdYAsipzzMCUkY8Ze/2OxFfiI18QxDYnFT90XNJZ8WfXXcoD/AYia57KY14ozvWxR4hESdRhscVs 0WCH3uFS7PIDGZP/LWTnbcXFytiZUknVBPFcMnukjY/6pKKUcLY9GDdfF0ETbmcJqV+CO25YJYhQ +UIZsQoAtAQ5Cna9jKSrF105slR5suw4lJJvd0mj6Y9s4b88oIjAt8S6tw0fIdYNJU3DjkfXywGs auUUpbx1OXLrvkAGeyAiM/jsLT6T73k0mkJ0olsXN11hwPBY1W3orljvTqJlgDl6st63FTggWl3X EQaHj6xOTuO1wXpuWHHkDhrTl5c2P9hrQBo5vF+OZjGe17HeYhLVqjgGGA6GOkxMuvYOcGEq3XDv rHqw+Uh7dL/fcTfDaObGASeYYLTAoHn53a5M3/WZh6ahyc4V/mHYt3CrgZvZKEQPjQH/7tT6Z8W+ t3sJ28xaKJXx7aezU2o0tGYoNxW7nWc63+FACiGBe5aaqm3jgaF0NO1dxyVsYWV3KR26qp5OWf6X 4rUU5OSkEkbLHqUHcvlsG/Xz2NEkdq15QOW5ZiExif3p7ne5tVHoLC3/2SYo5mmbew5X+GZnA3VD 7iDIw2tQjM4yJ3wgGgZI0h/OveMGCuiBv+gJhnQ7HGKmGtq4r2iTdzJ7SxvN9Jg8SxUjVN2mXNHV MmBFkV9iAQaFU82LqeVEOb1nrJ4xyPqFRtEManmAjS67SMkBLke6zrlrWJ3ieS+85fsXuDocLrR0 2wusHWjVFTLoxwl8LzifDMLyMxdPqpvuBtWPNdJTjaEX8yyd31hV0u3P/4k/bEUEyKuqNt0gT48U E9NFrO5WFtCmZSJuGN0ie6oMnJ/qB5jfEFebmEiT7/I+bCGSVfGCgaCwV6zI6pcuzAQpV5azaffK OABGjFYYrjFniC1+uh2aem4fQoSZ1PRmgwDSNW6dmjOr+FnFRi/rRshZ6lZxAWdVZmVWyhgRI7jQ 6TXEj8o5pG6hZ122/nhPeYxq5oSIjupdCKlUQsiVRo64E3x9EFyXV2Xi9IPmKtuxrAa4PJ/Cgb19 lnpQe4pYXrhnv9nZ0iCvk1b+PV2lQIyFlAveEduvN/bXOKywyWxzGgunYGYKL8yhySyGCvrs+6fl kllSfq7Q0Yk93jrrUdlPr7QNRbEmBChY+Urkii5TTv+NYrn6BUg4FeBc/QqsMnw33N/JYapUeeGK ++UcEa/eJM5hGAeQIYVTXPGYxRaRCXZrh9WeAG8Pey94U3Z04H8UxzkGUB0+1m3jekhHdeRuLmVc Kp8cBXQSAomfLMlLLCJK1XxFCBIbPckUWDFaBtRT8mzKFv6SaAJscVvrhwFur23Dzba5GjWZe9xY gV9cb0HKqTUwoGl5fkuV0A92daLDvG9/B2BknfAD1tcjDa50za+PBJgHOXkYNYP6RuBr+IchuJd1 fpJAV8xBveOvchQvFuHK9zm465JdpEOg28Iv6LtMcg7fXNz/LuHk/VEn1ZQ4cLXclunGVn/T7rj7 hifpG14/ExtRpZIkYr7NkDGjaLk1bDaQ2RoG5UTpOodCDkM14iYpWIPtHWsW9M84IuSX/7rjAtg5 E3Er3h8clzjslxd0VVJrA2hdIeRzs/66x0ynYfPoNgoZvWJ30Ye39p407UeKLjVbI1/1IGS2dUZP /7YWwqDmhsO7BR37zKDVnGJPyYIhvO5b5WXQjaFVBzKvWzMwEWBBksHcwBg0EFmSbjY+67omWFvJ vzDuVL6m7xuXRRSPUUqt1mgDLCvlO6000BUihUDobXUmfMh2p9xcG0f6oUF3CdBdAk8QxzTg6B3p n4MN1NMtw6RxgYg9m2b5oo7fBfuiJrbk2K9pj7c2IYwMNUD8BqSglB93WsHZEG7lFMFmlGVzJWPW xoZBGw0HOgED1wLK5gz8IIVZhPnPg0Jr6Lsh30jkk4wbyzPO3XVqY7VhQjB68FcQerzBRxz6kzP7 UgsM9J4qFqN2FUyFueeHn5XmhtZB5ZQCSw5S2zOP3EBmsBdJ6d4R1WSfkBxO5SdrAZR5vQf3vQIe sjNuefVB9MGpZceEX5vA7KpcsvIShzoaQR22Uh4kZWx+mD8gYOTlZ1HwBZ0dd87oscRduJz4cHoy bMij1OEN4sN16X9860sf8UlPlr1egxSpvhm3q7zafQg3MKx/9HoWMSTckGwQfJer3QkRZH5re1qU 4GDGKs10clziZEq3i1VcnWdVhc4cgaLmUn07Qf/Nk59k1mImYxDY+bN82almaNnmgQCcOIoChroX voDhos6ejeILr6enB2mGnX8p7KHS6Aw4I6EJ5ersWll5UDRwsy3NOriTvrhrn/ZSQW7FrBkWN8W1 i049rBdnHiPo6FYG7IfVbHWKhTtVTVZ2qBG+JHq5ZSsHYoaomv4TTGbMntFyA2wFVYrFom+jX1xz oCwdwJa+xJ+HXWiFdU5YeV6M6gF/JCmVEbq044My810+h3pO72yKIo4AcOiRTIM83unL8n+cKvQB YVkUjSItAXV36+5PDvFw7oKsLfGrKwxkyvOOcs6YAPpdKynUdKFF+2CZHpusJaGZxF7auULJFxxZ SOOysWd1/x1tF767rg3jXLn4mfta3MEkR6+NcUcqlZVTt2xWou6skFyuib0AWnran+0p+QrtcBLd oCuKlTA4clYhFNP2ViO/mxwR57LldEKAFTjIkYbG4mfYW6PQov93bAXm/5xmHORbDfNOOTlTvz6a nNygl26CU6qZHwY0XHwdLHEY5K2p12/YDvv7prIdVMhYet7j2Cru3OqoKLfbhiesGKxDmO7km8gm gxGOb8EP3hrFP7MWDiD6bZykJuIyRBOxfK5Tsm1uVDH2iFKCFnBtketjEjGaAncWshcTHBE21a3B q92s0zvViiTBcxewgKxxCFs95m3BKL5wfofL7qqhiXZCLWLejOV+K27FQSnxM3M9//4zHwdMBknx qLuyx7pT3R+xF0FFqP/nAbG8r7JRuPN75zMxKq52Zd8P1zyBr8XDoO1HZn+AzZL2W5UpUeOH6Mkn qVhNxfddiK+fiFrGmX7FPXa/sXOCf4jKHJoNU4ff2lCyfJYOYRGsF+gmA0tINDMM2pWI4cmqYSDC aDDwS+hp/ChrOePGUv837D9HRxXkPdWh2epuAkxgeSfLioFHW2MZgMP1fFJCOSK8KcnFHggWEuTE K9/JOt8aQpcF9dm4aMlrHn0V5j4Mw4RwgRTGtbTdKCdU09Lx5bN1Lk2MtpC69LVo6Ms2jgbxvk94 EHcG0S+/QOGRG5THMQSGnxMNyWJXYjuL7EAtfhSLecZxmevxGwBIVkbaaECVAfHPdyuBd3tNgT2+ ST4f7yKFJvnb9Xdt6coh9BCvIjBBHg6kMyC6TBQiLkfwEnuIqrNpzNVi+nTk9noRz0HFmU5PiAyt +635FuZwV84b/pKkxTNIY3vtSGMEn1h0ZrlT7O2lk60XwZX+WbD6EMOkrMk28C2H7mloM32IzAFt 7AEjznUCXQu1z2HMURxDWznnnrbuFGRmpg/hbbmRcP5Z7evfpRqTmYi7qZZTu7EZHdMvDyq9t0DT u+cPzefGIx7zMzrp8bq/yaQXIkdTsj4/DeLC+RnR/5YuR3+42fgMs7T5mJr9ObtNa0IAo8G42bSj XnUN0eJEuCSO/LOniA/CKcePHyjupJduXQFXeyit9dPvsLjatyMToKuL+kt1ODm5kbCZYoam7ISA K9hh2kqwg3EqeMsqfcSGAqOBojxqeR/TAi/1ER6LWwrE/wxPisyctmWXAoBsiUFSZIzNZg5pD/tm Xa65HzRDW/KFLfxGynUFd4A09nXwth4i0VqKp8j5TpE/TVuwdcSbJ5Ill3mx21UfVKMvSRVnqVw0 BQOqPIeZmCuDsAsiFIzep5Hn8Uazq+TAisUF5PEliwOf9avbi18exB8xReM4ZQ2xp3UcIOjd54MC VxAw+tG8tX2FVKrV08LpyU+rMYhDxdhxd88YK/t5OFe39w3eSNBkc/2r+YuMy+cIj6grSuh+ypuc 0cKuPpPmGjRzYqjUFA4YR66vkXGdGmIJPHsleN69fEZTHf6G07xb0g+Eb7RUQ5Lx9XxomQGn5jYh gIDalR+ZD/PFd3Cq4Uj+d0a4diY8/ib6a1tVq3t/DL58cVJprOF4IhqCNrd7iaHUqceQ8f4GX9Oz As8HBtRwrXCXONPlMydlz/bNshqGT8gkkfL3deCkc1GkTWQ4ors1U64aRvZIc0fqOB7drmh2UggU Bgmf7h46eDgG4sPeiT8FWfv+IXodnhRSkRnarxA3kTKXvCLugTCI7Lig5RD90p4Zn3kjSSJHKszY 2TvfrOTN/qx5JEs1TdclSGhps5E8CoEQx0yXCmgrqdjY5Qj3VGwfZ/wc2ETeY/w4emZIS8Y7pCzL EohzGMmg+9//hqQOz8dAXE45y2Uw6/8LmQJQUVC66Pngqj6dEafMNnpWidAfO4eGbsN7ObWywHOp ET0YFAqt0EhR4QW3p8SIhPaeDpSJY2A2VJo4HAciGDomjuh4r1w5ZXjYSXxOfIu0IGy0quIwRk19 PwujRZ2d+eotjaN0yzqdWPaUytpkVL8nctn0P0vl1l4IxJAyUMhPOrneWvwvW6CA4jhbIBtRvZwc rpdT9q40hRRxY9cAS6IEHtebnahf5EOo+5GYbLWzyV/2GFUhdhLKMPZkv8omy680fQHAafdfO3UZ Opur2TuxRzB6xFB/vLrjU588+hRojBXl4Ft9ofA/nM7LIQTiZy824dWkm1xsHh+lmHR8nqtS//Xw P7cXuAye39skS5UMVXEFx5Oj6oFJIsgU0pxKnARKFCbXiIBDYs08/KOA8zBJ1YO32BfUma2Q7NrB 5epUjsrRLVxHo+DD+gNOsdM7AF1mmKkiRELuelk8waZcMlYNrId792C+E9b4MiUKs7Foe4xryqCR ApS5KyEr7Hafc//FQA8CWlq0MZClB9JVKZWtZVjhNTIK7p4XyjYrsoiIGHZA4BOMin5OaN37VAUB HmjrtH8UPdG1tn4NHcNGEVXd6HnuD94yNeDUhStcbB/tXLgXqRftqunR3VU19uolwXB5nQ8vkvE+ 4VnIzkvb7BOlnJIrNRBw8D0ejkFlQRc0Nr78eqEN27pHly80ltpSXchgNwyyjT1YOt/iPaQRyoPU UakCXoOwlfDiQKLHonZRTnNK+AE4NvfZ4Ci6aMuUsKGxzdhckzmoZD92WHYO3uDe//VVaroMm9NG 7qKxLp14c0WoW7ChbFMAlz+vS/gSlru69iK3JT0YvGqHeFl1Giqi2N14UnsKlp18xjKxQB/dnEja eIrK2z/2B3DtigVrWT7tHi/inQ/OaSPLO/feJH1H2LOxGZfE/GPc/9bnr2/GVxwObBmKiXg5g2gC 6bTLR11+CD8/dXJVZ0R+lUUXhUkDIAYKiGeTFYI1g3R3OlSppLRWfnUqkxnxceAiqrDNHa9lRhZH wpFdYw73jHyijCdJG7ge9g0mjkUMrEoth3r3iunv8h4WyZzdo2/mEun0yvs0ZpHRDG+cawNQz15M f5/Mw1nhx88lMh+DXJYr4d5/DWOyvg2kNGIruxyfMZ5FJa8SaqNH8tuNakBTLlAToxfbn7YL9muY fVJSDHJH1qQ1DKABn472d3TfanAAx+flTMWDInKMTTV+X6qy2qsN8Ns2AYVsZT78RcjG2qYQiX0v fTk3C950vzitBIyTJ5d4UYpcbfc5/fD+j6qsqGc+wZFy16ICUsl/RaIDJN1zXPXLMS7/3XKqhGMW /gH83dBWOzF8ywelzs+bgLBhCurPPteD7xvIy86bNFTWhB2fNtqcCmtRNQRMZbFvRB7wtaADyzoD V++zGM5vQcT3SBKoJNKhuki+RcG1KTm3Ub8Do68wgs4Z4I0GUO3X3YyAYTR7Z9o2rM0lkrlFW7MP oYV9oMLesFGJ60zh0KAlSgSzVUzutYiiq8sMOnGTu/imagiqxAmQACXx1O/ALCkwpENcysm/y9ye pGBZtDaMFHOgNEmnMhhiNmMS0rzYbkSMgeL9eziYz+8yQ01GHFy+tQYLow6n1RDue4gYjiVSYn4S mUloFn/Ov+nwbPm7yUcP0fF//LQiFDJJyOzvaBWqt902yfajFmJ8TMD2ogOJ1sZOX1QgtbEl9sQm cRiXY2+DMuEzn4KxPwPqhDKnIdi1uaG/sgYAUFWwQsMtlm4vhXKdMRZMbSpCPzq4lfurpTjspdQB 1Ur3kuokTf18pvZuFYM4TvsaqULyEpnMiq00j9WNOCV1sJhieqyjYk9QDyeq7oS+TFD4u42MPnuN XThzrVegtAqbK1mj/aDoozqy8KLfT4I4fWoFsRlGgR1SvGNpN4D1c7oV8gfIHfjAIKdwT4TlzQbd ooxPk6R6+VSmgoAKZpvtB6VbN8e8MxH+BluwqLRaFE7oOIilSqlO5zQxPyeYOVTVBodaFT/z48zW 8adG/H+Tw5dvWZmNXuPTUcdLudex+FkvdaH+9uZLudAwSkSM61VKpLtaYJvPKhVDM0IOkexl1/yz 37KuVJnvr+qVV/cJEv95BL7meoFg2DKnEODvt+G4Ys+NmYQIam9div1zCCyJlBwb1VmiwQb6sXMy 7hhGhBNuzYmiExaD28jIWUug4+aRUzswiB193I+rElcs4BcPjPBR0mfDJJZEBHxYUnDbswMjGKm9 xU04f0Ej12quPiVC2TGrddccz2F57qHGI5SuCI4iPzZRSHNIZZxikMCBTsMIp5GvyDLTi1L8BXVM RM69+RRNAzuCOfiCTwvhdCRv/2E8LEkwb2cwoqG0PE79HM1bWnHkC30dXrhRsz6qLmimMQd+hT/d mL5sx1WkJHvRhZgrlEaipCEQ1Fbcl5h/eBiM+Mk71kow+AkcC05JcKmZWVBsG5Im8AMidiEDKA5+ CCxQ5ur34e2HrL7GakpNSEuo09Z9oN4mocmpZt9LV/lH3Z4MUvl5jEZZJwe6A2dSHVIcROuWv2+A Axljtsw3mSYuX7VQK/wAPzS1toj30HJr8lQVPXwqnqzeUVD0c6OtjFBiRQcCwcdjVdXabo7vzhgr MsExOrz0m49qiP/yHbbhOD9Yk1RXtWDShtHswIcFSI6PZLsYNY0n/a0UDIIeYenvHXqPzwXfs/qN SNERhJx/LMjlLfCbgHo5MqZEzEUNqsMT0ApJiy2wB8Ht2Mt6DFQ80oVDV1qgp/lGjGCXKtNaMUaP oU8JcwV3jY6q7wgesnGRj8fWbSQ27O59JM0RDRo4Z4RJheBVUt3Yz0P0voDZby78v+tprdNAVqVr BS1d7FhLDrTwmA7pR0Es6X/YmKYn7s8wK8DKzRAFw9DIvsTFOyhchOTzVXwYJJChzrraEdHiggrT LgMr+ea1tZfVwYY6LKozfC3xnFH+VjvikHtblOY6L1CyogKmNhvxMsTayIKtmj4vLL6323m1UHXE G0FQO+Ncj0YDfhwv62OxHWGX5kgJYg7NvD6XFt8LYcWhK9t+OzkRd0aJLsXcIoufPfMOhghG1PxM 8TffqkUq7i+R3EpjhusC+RJGpgYy/PuVf/gjd+SzeKVVbFF9tw8LmUgK7FTduOJCS8D7uEqk0Cdw m9yaDsWKlYKqck0ptmb5fhW8kuYm1QbVC2vbEeHc+vYV29b4Kf5RghDlmWDbim9rl5zcjAE2UEUT QBCO2mmjkfgoT1R1AxgLht1CmP9r7WRgEtTFzvoTtOqZmGAGDMFDrWeGp/1zxLqXar/45yL9Fzyl jt6owLXWb9fWazMA/BXAOInE78slEMxQvZ0z5PrZEn6GyxZv5ayiGqboDFIuJ+eKm1zRoy7GqaQA bEYXlCz71uilZ1QcFwa/tusWLA32mCBnWRIjGCguRqI2Jd5m8kKr1A90ZOXByd6XYiiKGezTkTDA nkTwCC458XtjHS1Hm3BddIPub5rTptZsSvsaS6bJfGyE99VkjVk1jkCnRbKY8yv3No5hqONId9cP h4lrjOL/v4sIO5aVABks/cNibV5aB739af7hdeadxGo5wawrPLSIMrT4xz4u1C3A4AyjSSgzLkNc ECh3zLnvFc1BbYBBP6JEIO8G5tvngyZmAA4IylHS5fAFrn+Gm18+fhMwSqrmtKg/s8dg3Xw4thnI sx7YY0HS56xyqZy980FyapPykTLgDh7WNksk/zyjUau6NBns6aSeLA/pb4uP4BmTJDLWIlbHOHhy ZhS6Jf3k/+UJsmeIBBn7ff1h2TwyyKXyAhzPqnOYXtv5Fou6YO909u/GmlSLbsPAweOOybwpZ+Km tDMQlmX1xfGDfVYNv9QIcQc0YNFSszuQfWMI5eX2OphQqI0BfSu70TJqsApqXPDRxAJd4jbRHii1 /04bglnUS7/i70LUZfIuF1DIPoWKWN7U80MTKlWD5FF4N+UrsA6ll6MPjwvg+P+6DUHSjeHHw5mr E6z9CHrBTDbwNsHoZXbIz0JofRZ3FBiID/kTD1ICkhj7c7bhQqS90BpLbKMLutTZxSmRl126dvoh yn44gGogbziZDhCDwi/gqj0Z66ehnvRb1oSn71rldvNfZUTpG20RESB7SXI2rGqAc/dMs/wlJwlI ka3adipkwYlhOhAavkDHyCRlqfZUtOjVLO5yjU8Z0XRwiruEyOYcS1vN1QBVJuGdpzngaiS6wmiK X28GtOtdAX2TVfw1btwRpAH56GxtMYTODjKbnO6lf/6tpSOkVwzD1V46Km9/+Aa94suSU65rItHM PvSffcUFZ/tD+zSFpXWfcshYjcIKz6txJMWyF4CWo0S8HYhqg4OWPEDwc2FlQKQoGeE3WAndgejH MXZP0S55ZcyeussqmKeQaQSJHeP4zUjEDPzQb54Yy8pB/iZma1YyjBGsMCFneUc6nXub04RKgu2e GN3Wo0g/nSpUUwLkHsi71D0+SBG3uwQXEk/GsjSQDwfikZv4bn9ZDJOgnMuhSKU6TENanoGkORbI yLeJ1zAlIFDmFj48x6DUTfrU2+u+E9DbtraBWA6kMhohLLFjUIUxH86pnHAwbFF2Al1WN/zl1gqO iMW9YnGnqUn87XvRaBbGxQkFMWdkbRCghmfZ+STL3/Jms2JE9oA8qHCnDUW6IR80B+nm9YAYTVe5 rDxvwQiKf9TihS3Lu2WwUehsNZDGd7D+gxH0e2VaYCgXzQBs+QOu7CJs2dLm6g7EwCGIH5Ry9qff FBGDU25qhNGFTmd835F43azxUp9m+Sm1udEJ9SdHgPT2cvQ46JHfgoavMi+SMvVKapHJzo183mOU Tbk/hU9hX/TR0iS3SESxt5o8hazbSK/vLjCqmFaWKfAAuGkd7r6CzL6/qfVWpBoDr3FlRWGzH6lM wJpOhzj0GClyGkxyKnW2VL6Nj09oDgnh6bNH0megoJo5d5QSBjJXnRweInJHUBCE8K2NE3WN/i7v YUBhjp9GQ25mTPI926NRYb8ZdA/jahEz5Pjd2/wvlsJRNM/k04uW4X1FTxMilQ+vqe7+00Pr8Pkt 3y8T7KlS2NRnObyCzLTqsUA0+xFCPWuN7XdxoVH+K5in09F6DD8HaAsf26RZfw2rKc1v2EqzOr0i Ubo1wouMJFcK1F0nrw7KLZ/HYY4x++IWuRioqFSAeLDgHN3uJF9JBzKEcgjkJ8PamkprBhLNXMNn mWrq6BbgVyvL+fmZDfcDI6reTtMPu95fLI0VtBj8zhcFvrap9Q3RK6SrErFnDENNUzYyGlLZT9VK WVy/a/zrive0k5HwqO3G/zVq/wVkmV3FnT1hBVvMnHAoBT/z25oVJfW90VJTurIjWEgog5cJeOE9 2JPjuRVyayYDB8u3mPqPJjMQ6xBZ14ajuUAz/dr5D4t6Hn6RvUi9L8k2NknXLgiHoOPXXXV9QWyX Qn/v93DAw8L22a8lr3YmtjJD+47CbR3msLUo5/7uToBs0e0C8c1HlkgRGQpr6+XZTRY/Xcry9SeZ +/NgLE386W7xYMTJSWZ25v4OiGZL4PKphtuxEGp7EHksHCtxMj1VmUx/Z1vqGEgs9eglBtqSt7hH /DTtTSdMxKob0Ns/PNYJCM1maoFngFBqNaY+O8jUM6MaRZrq4VWnzT0adkRbA1MlaiplAzqEhrOi EHrUOPLkRe3WjPzOARic8nIWyvk8eMs/OItw4P2upqCLresi9e/r3SP6kKuC9ZE1E4S5cHyz6vom XrgbqQZ/S3Q2NWhOdzJu6eCrqcHF4QlvpyT9kvmGyH8BCX5od7D1ymJci7mX0IiyPrE1DaDi+lYe 6lh4F7CZl91GVz9oCdvAR2PnzIu2PznvSD4JZFNFu/so4XT5wakaCb2/7BgiBjOWAbIkL8hAoNsG ONAKdoKpV2qZZUFgfyQGcKtcVtM1I2cysTTgIYA1gdxA0OZXUS2BF9aWbuosbNTI6/wsERLgb/hU cSwR3Ei7MltIA+L5Q8HK4lwLwL/bsardNO/t5FZKyAHahAN/kRqFiyewzflG4IfmnT66vT3K16Bs gRS/loPpvVSyxc6oU+eCGOpv+nWpiVhcv2MDDlD0dsn4pO8qgU+mVS5n6cqpXojRCKDWWffck/P7 +Zq+ISMC/BhGLTq4wOkIUk984QBcTSoDPjDQQ+wI+FFFogSRYtnlUZ5I/+XLx5RiSpMnobxEQn4N eKixGZ6ciG0VAsnXONSJQNy9uY+mc61wzgP7ES77G+3UEHDZ1yPGvq4CfuHXaETxs6foeNymjnsW 5bTmdyZF93NAiOIpw1zAAnXk9aHc+KbBJChTqVl239IRGQhcLd9hZ/T+n7d6mxFKaMqPWbDYELpq q5BvQ2BrSqT0zkvkypkHUpadh72jk3wHdmsiYm5D1F5EQsUMmnru91Ik4CTVRPy5CSoVqDs3zewe POXxOXKaWhkjxJ2YEiDlmwR7c+KWx8zf0ZZWErQqVmRF8c1UAwqfkI4aoGWcnI+Mp94GPgnmGpTj 46DpiZ79OfwCH4d77I+XYZYdHuL6lAx45SuQv02Y0IaVm2nvFhQTUMzhGqasA6uW4AK78r8tzCcs ClfCJBrFCMex3pCnb3al4wDXvHNq9D0tnS9oXMqcpUdWjIIXJqNHomuKiU32/PcRCSDUxo7I5FyD J/DMZTaaCgmBgNyazld/gUBGTqFVHMIJ6QmGsxUFxsS98n9cNEog+Cb68QS46BPtiZttPlkMQ6On EtqsV/lrneqAr4t0aYRCy7ZEmoM5HsnRfqqFzScdJgYrSCFoRaXm8Bx+xF2Cq2+kvBqhrvIHaxIo YEeczI8Bq+owt+SDTDlCtiQeYaU91IK/u/YHSnEBS8KV5bbJ4b656qLPFWngBqGkX4IKsVVshIr9 BiNjqf2N8oK86SOzobotjtH5zlAgjD6houftDaEeebKuM8B8gXobJtartf6ZiM9hBV+F0Hb/NLAn 76VliVHbNrH7dAiMNv4NbRPCuZ+bq/aobK3601BkJ4eInwTieUMdIAEmuviGY2zu0B0zHQUH7Zu3 6+H37PhR19R81FInhQM7PaTvuPxTRgUZvJArK1EUk6FRzjwacrBN5rIsqBVqNRxdLpZuWvvjY9wc dYR5CsJHIxk1/AVX2Ca9M9Vp4M1vtMrqowBOrqHOb/EKjsfQEYqv9CesaiYxBtjFKa5/VNpfzisE 52XupD7RaE4jlUpFltXMLzHN/atqyLUQl9VU692ZNZgYtofPQvP7ldaQ/9EG2CMiLavTsFmGvO1L UUUS9lz5W5wuG1GqGPMDp4uKhcDl+Zq/iF23n99IAtM6iIuc44Yq5A/ROzFYw+/qeogIqNHR+ueK dMJCH+8CaOf11oPGRDaV1R5Wcj6YYiZ8/zdKYKTziwhY5LAUraQn9W3sOoQ0OU6QzmdEyz7qCo86 J986/zZkdRdZm+DImM5C/ng2V4rw504aRdVd9/Qp/o/pBsjcqYDh0jmFmJLTUGgY5yRE4qT7616t Zt+BfVDR+JjY4iEIq4e+dEjj9YjBC53EVQ511xpYzEZHJur24c0Kj30AnBPFo73JhPQk0fMKtqgf 61NiyJWhjPLIG2xMH6TsDh6ppk8zYxFn50P6B+fiGXFOvao/QWe8u/4rYL983u+1NpZGxuTn2fGw uiQYrE0xRA9LB9L8aJ/A6rE9D7SJPV1zR8X24jUGhapGdNEUXn9auMvEyGDU9Ws6W7zChD1zc5AQ /INzSr965gNs4DNe0JOV7c/ujA+4pRUDh4g0/t2mQMTJgHFHYn/zA9xWRHeKXHnTVAj95Ui1R47R eWwf4NQafDNJdT3tcwXIzIchZGK5U7zQ6NstC3mcG6H0wdYkRslwKGV0NPjN766R6cLsQW0bemMJ L+ClPlq9l4R6HyMVWBgepcRbLT0gyJTRwPbEmpOcVGisU5L8/S3M+MjwY75Ptl5IJBReh3llG0TI /VW4P6VgKsFPFyi0i/6cEWA8CQGH4Foo5c2UFy6yN685t959anXPrfmEXe5OZuHpyE0tLYnUrj8+ Ljks32i8sK+Pvx+0okEv4aMF3GWJH7UqO8wTn7ImzuUT4jjzd49sR+gFkvATH3E80qliE/YOcvK4 L0nNdODSO0GNUPl511nLdNoR4d6hsb/SQ601POz13Y2th2+BmtCsyrhXZQ/ZsiaQzxQzSsJIeIPX dIsYDBOCk6b5kOuh7VRMy+IrQv2TV58o7Cp2C4yVBZgb4uortca0xtVXTL4oqTlt5rWt29XWjn7T n8lSxoi1h2+LVQDP2tgnvlEPYuVicn0Nqy69O6BXZF2dPynotzx2OUK+A1Xv5/qJEx8QGpvBI0xu M0UaVYE/fjSGrkscSVqgPIHxgmZR+iXv3uJqiFqCQzxZGywJr4w7UC5pvbODGE4Q4W4FVnlRfUIp EkyIR8EmLBI23x8PwGL8rs5Dzd4gYWR7te4uyXmztt+dKczeJSfDs80x9vjoXDbgmNDCmUgnCTCX YJecfXfoICHvypiL3Ng3Xg0lKfEI2dvrrfQPFT6y4yH5u38uqysGBKadFmzvpPu8bwcLrUEtGRAX AhyscwFgCtkWcV3229Mvnr7RzcXxtKcz4nimBl8KpCCkjz0w9s64gcmXtrbsc8/jHv8rQG+CHksu c6ozFFaNMC7rVH7sSbtoAfO2PAXOVQ+eXo80sJqgOOowRulL+a97K7jsk7wVxZXx+u5mbygHVBBV SUhbuyZgCBZ67vjsloGuLo7fuSPah8JUeCFW29yRDfpppczl/GSTUJQYHRifyNSsZpsLdTOY45Kv i2xJllf5uALAKFd7BMzEl2+UynzklKnA3jw+9/FhfC2fVFcwJh56EFiTU5K53giDqx07szYVrEzr +jB0sbq4qZ4ak3P2jELpGfzwmRwJk7PdpvcBV0TnzH3tRdBNDd5RtTtxv0AN57VkqhxWz4AfO9pS SLLq22NwZ15XHcNyqf/1g2lzw3SwkGM1CHDs5LLgDFEODfuw154RaIxNx2M1aB348DA3az/rdtDo dBwn4GFXOOOcjZAcl3FWuaDQiPbvdNZgEN6SlUYpZAD7aecUzDYjKO6dLffWvoL5DjimjguDh+A7 nRhrcCj/+KAElxc/3IH56sGBYRyHvup2XfvnKfx8nqL9F03rC+bPfnuFWJwd8AmgmJ+0M24W5XM7 XAGvkCs0NZAG9N95hsPLMXMUSUWYU+h1XX8XLAIJClD9AAsnC8+tPuVRo0v8fAmVafJPhs/UtFCr sY6wuOS5FIFl9YwDAqV7k9igKrk6Apd+wElOcUjHj8J38GefRn6OPHHjmZSTL7jkutHl2uelKcsV 3wd8J0eGCJYRgjGyxqLEUTycJIG7PbUbtdkZBuyCePLj9tesQ62hxIHRx7Nsxpi2AHpbEHiFeFYT luCMrWzhlD+o+AbESFZoth/EWMnluNrOtAlt+jdYtAqe8dblnS3AUmbz1mwbR0jYfvzFXNcy5sq4 Z8rQczYHS6xLjhNsD8uGj1SgLbLoW7Q+W0ws5lX/K21Rro4qzOqhdbTZmuKG8cLWYPIEBUyNcDyW LGmkN7VQjuWMjbwcxHPoXUnqwX2my+c/2HelcxzTMoYRG38U/dCBbJN6H5wZYj/LpLLMK0xJLANu bc5loIlGLnlXFNqSOEecY3P2dgQzPXJs5jCLGYL6/KMGaFNFZgi8vczbEKCngMH/2Usrk2s6o/YO B92lArWBHJ7ZBqm4sXepIGGOSkd68+Z9s7zgdEc/oYo6bIoyuKYsGbH8bLxNFocijbiSCscYm4tk l2hJ4T8QOp43NEacXDv+dcZP3CZ+z/o4NQ7t/DlWvPOMJwrwHidP+Bh3ACrJPXhu83e4ZJnJeEvE sTOYhdt/xCMfhbncKcJ8pY21jifpexSivQG61bxiZhAlb8h4WUPk0oa3dEcXQzhMLXgrpuP4sSHj 0ZxO1x3plrmcRBI8BKSo24PvOBg1WQtjTdsV5uZN75Gk83sdtsdqVX+VXfwDHUI6QqcvTGJmQ2cn lzhyCy0e9/nmuTpOPLEZNOxdlCeHg71U9tOeC1DuW3bfirVO+80PSWNCcOM/qU1aeK8rNf2zRKtj /UUKbTX1cQh9R1wgu5uVaW70f2LsqV9p4BYy+UmutS5Fm1535N0sBcc6HX0rE3RGlD9Latnx8jLL d0Iajv/y41Sjma0yEwusztx2M3D2+FoMISVEbWfoRzHeYz8MT56yQZtjcOBCiKxSNC7LYYENCmw9 1Ji2ueGEGTQPMQENocZmITqp14FQ30EFtGORDVN2KfvMQdqQ7p3Q/QoaE9wN7Ivb/MCKNe6489LQ RWnW5RV3xF6aAFNPe+dgkual50AL3o7E0gTxJ+4oKngNBQpGd1+7O7vkI0veTrLBAEyD0MQiWWTM YzuFoF+V5NLMwd57zKRTVc487Z+rr9E2LNM4hefsLVryUDNmi4qKAM6MmTc4I5GHTMK2yvr1Gv1A icMmsYENos92bDdx4ri4uHxZui7Ek6XqFKNvTtNbPfaEb+6hYqR65JuNgZuwAWR8qGkt7eu5t3/q 5i5+ulxW7hy7ZsCISlEu88az0+LhTtxmE14rdtDRLTNY1TvlUCY6BfGsHGb+66XpgVNtX8sawnsC X7BfxKj+SUVHJnIWMAA6WU4yLjB5zDheFEACex5gEb4jXoaZIawn29X8PkKrGh/cse9Q1hdonWN0 /n4ciOIgWuCagNYtQRhT1pVR8YMHsyNllVqpQPtQS3CKkkIirLGbsn6cSpmxlNDkZ/ZVeXwRK9hg wzXEHXthfY3eOfAskPzHl4RjVXuuwvu+/DCDL7YTIJAX6f9jI8mmkmYs9FSnzfeBPCMXN35PUMZe GIxREvPafmuI/b0BhPU5pZZhQJ3S69iEoOLX4Aq0CTsCpR4BVMnedEXvlApn5CSPLFtR4OHrQAmX as9Z92ywXElWUMEtxadYAfn/pxs5iAW2xliFbS9EqjiSQEEJLbYoOEpSwYJcHJWHy2GJdQh1p0CF 6LQGsMWa1qc4lejoa0TVXWzVSOL5NZrLAW9bjmy4pcHAmcWkH5u/ExuBYYRY+g1h7rK5BBDjnXqK mDkMTS33Bs8oQlDnHFtbawTC3+tkfBbvV+h3TR+1B25vc9CyeIkpNf8yWaO9NnSv8YSsvRJIny/j xaOyFitWqVIAbxiRlH4GSbIKCsoum5zGoGh01lYVN/E2aWqIBG305GlaasK7OJ5+AdwVJwTG8ItY Yrvu1ol6Xq/eFq7fzqHKhnsMahvQ8z6yxAtf9eJDF808Qd8wqml0kEemag3kA1fj1kE0AloZIKDx f8aQyKVtjBPk0U4kgILkLb9bVW9iujnxlXFiPMhWfjiFbl5yLTug/5n07CIFOxg4DYBXWTGdLefI du8JUS3JDjdXqjH0GIIE0HIA5pRdD9otb6iGJ9LdFC11W8RdwD85U2BiccGXiCZ+LiNJmEYCWwDB M6JdW5l8ABw7m0hpFmXycjXINCRtvUxKdpk2mWH7dHnBqrYCzrk4TfamWx0i1RUd/LsNIQCd4HQL BjHHlCvD/lK784HeL4IwKr1biilUR2op/K7NzhJIHD97zoGGrffoFMO0iiikrk93Vo9TxhD1PLWJ LaaLSrd3Uk62jSb1F5rsFJVvbUHk3xGzRHd9TWcNGAypYLJnMyRvvWLiCN6gGjGslyL9ZxFx/+7a T+sKlJ7d9MNhK45Ilv8e45f+YpCYfYKioyPLbU8u1Y0r4rC9ej6oB8mtQIOrjeak5TqsQtJMMs64 HmyfiW2DdNJ0Q0hZC+A8JCahJ6wepsnX2NDW0GYlnGqLZ/lPKbT0yEE6v27Up2b77oBxgZ8fEu+N vdsiHgvc70hbDA1o2M0ToSTOYuIb8wGGA7EBNIGg+/hXnB3XAknvQYX7waadrnxlUaUw0ZidSVy1 eRYlglSS6+ATalRyWM2k/oi8VqchpxwvYL5LWiXcRHWRBB2HsMzf8NPcNbl9a8CQKEySW7EwYphR nht8M73NueLax0xWB4334KO4f8C596Ye5/TpFArXn65AFS9txy3ahPqLHVy7axTlD2X2kdsHrNds F5YmX43OffMozp8JWHnhoswprTcUMoG/37IG5377F+4OviUyN+CEJdkpuUYZUCvWdxm9zEXeVdVz anDpzLnuIRYsFV5RRLXci6SXKDZTNi+1bZ58hVXjTkuYelHXwg8u3odZvbX62vM/mg/5C8FdrJiu cxTUboFUqlFAOfCLHDnHHhv8xWrrAYKYJpaAmX6C20bwFgk5Cm9NvyVmmhxDvCqITZopXyK2T9ez EmLbxJ6uqivTzyhvLoiiunJyw0EWSJUR68m08A29lkmdL0XNKpVnjf1wkgj2IySC5zYAjox53V55 mG+9ekIfISSD6P6GhPVSNr7vsVoBL6ZmT+gGm2Synq8wzXb7L+hV69ZVHxM5MBErIWd/Bd4aF8A5 nu+1a5U4zKpDFw3z54t0niuburrO6c+8V/xwT1mPgoVHA2eW9I1XVUJGQICI0cPfc3oYPGwWTE45 uRNQlvzin/h9TYZUSYZayJRBt0mVOXH1+aOmqMF59EpoRuPPY0R9u5u1Z7BD+hMhfkZuiv9UP+gf ZEwgKNDkQxtXZy8urH3fDAbe/hoVijRE7kWUpOTuxAmwOAMh1K6A7bT7w3/0VKOiWQJHMz3yhPoW iG2v3BTSr1Jb+9iLg0XyM6TxdjGMyLkswzuI4eKVK9YtgJhn0YIrG96kbl1CL6ckma63BYgVug/s TzTyIG2GpklkQHoEeCBiGdyBD5F/k4Zqwd4zr4UI/be9PZm/Ig3CpihG/Ylid8TZBYNnZm4Z2IAL MhxwAzLbEV5gpQyix7Nvre8OVvCnqOJnFM4JR94vI17bTiYq5zh0FqlHyrKwrCaVkx7aedCH/YXT IZL0kK6PrI2xg5tzKZXdY0jD/Nb1WCUZYvrIQGGrAWHZfNa16SyX6pdfY4sYWqqUbswwtyVkugzL inYzm3Gt3bHI05M2vuMc6zREfZTc6KsLB13Lf3fFJq3jC/gAkpjDD9ow0yg2S2rlHzJkEtb4zpAe YobYeNi2mq68YcWfii5xT3nCcTMgw6TLnZXk7AT498apm4PrXLZymHTz6+F7PMFZeous6TqzwKms rV4tljzjh6Y1X5rDDshIoz/ACUU5Le1hVZ7pq1Kt/dZt890wXbK01xfClCtjeiNrv2zxLMfjmYD/ N2pECY3PoOOflP3TC/0/2eY3du+g+IQ1qrZu+SdiCGu6ky5A+PmuXyXv2uN5o3kAwpqIvrVDpUAX T/1ITBh2TLmr0Us5uifjHNC+Ik727ObHsKmb1suzuGOoePvhzaeeKbVQu0UsQeNSkIHIsmXdZjxA 9/eNPg7buQGYkmtLj2w+mTkskFv/dkEExuOHuso9sv5Zg+HnnkDq2KCRTWCRapaoZOIS5Km8UJ/n YkmuN5koagPZW1o2eCe7VGqObsA5GXiC8sg5Hk9Dqj9Zgfn5vm02NxA6uj9zsHRWbtx0bsy9qixZ k+gUDjWORJL6S2yx2NG7+0bv9WCvznGT6ST24xWXMEb24jDVVjkOzI4GVJO6Cnks455bCAccJFbH 2u22W0tEkMwk9GRmUAHsL/7AdoYMVPpC2MWACTcAlG24Y5ce+zdTAu9vqamMuiFK1eHcmlmJ3eo8 c1ddcnfEz7OHcctcFceYrFcudg/1rmx7A0mU0A1WReJ5l2MPFu4y55ekilfPU75nZ2QvMszdkcYg E/bHpoglOtrUfh29VArldwoiAw/fQ92XzgqnluGq0ShhYPwZSCYJPZa9igNdF3Q197irDGtWhsQd Gj71ayG743KuJ0CP12+naYJk9KzUo81JEz+hJ6LoNi9x5shJdxFP0JRG+lMX0O752chXd19b16g5 ezszeQ/3MlbAp6RkEmvvzfcRUNMNsoKprjaObiRpQHrAYkKwpwcMytxriTtiNkaMDNB4lArwHZun X/YKy7eKxyvpyiPokpZE4Xa9e3NLrF+zeqKoy50Ax7zIAZA9brrIbESCXviJoZpH4Mf1XMiNfKC9 doKYIW0s7vXJPSt62JQs6ur/bRBS26EEBdoatm7+fXO1GWlO+uYMCbTSPAQo2KbS783ospMgZmP7 b8yP9m9xYBEKlsTHtJa9DgH6HlSLwS6QCjvZCPhqWK1IH93wvTsuDRnBdD0saCfSrh1b36EvN1k7 XtJi4WQflefUpwEF0EDUczNDa5gTjJRy4XcQ66x8VVuvRpxPhpTOshp24y7gwe++K46TRWap6WER z7LwB2iSvj1gsCiOd2t5uu6/xZYhSutTAbOc/+3ginXbdk5hPMR0ptuABwCR6EnR6Wbz/1nn+qct u2jrF+QW0Lxq9jrQWmXP+a8ua3TOCksT+oAgxegXxHkVjYeglaWZHIUUorreMnKSG1zb35yopaxh KsHGyAgMVWNSf7qCUpcoF/W5ESsBhUlS9tFa9eE7SHe9fvWWkKpdzHaZdyeyIDAOXL2YQYI0xm7u ClpqwpMjiQBbUw2crZ4qntkvHASqS8R6fIrRsS5GnO1WCltTImNU7mzXRanCkWEeAN2ko6f4FxF4 fSno76dlCZ3VORZbnT7R/B8Fb1b1ArP3x+8z0flgUT5+P3P1v0fRp4I10fT+KEqP3mMTX3VbVz66 RJNk5ZgJHBtJFSPKW6f1MxXHxm8JCdrgE+Kb37o3/Ino3USr5QKtlwl6sY2bOwhMKyOjQ5/VUqsT CTWJ9WrPE/j7jVoVo2/OnF3LbcRKPicj7e3PVMDA2t235A84/8cTZ3f6tCeT1KSsDsEXaJH9Yr84 P2062EdDzRqprOXq5RgduCu5r85Ac4vY75V1zxJcBc4FWzno0M3T4MdV/nHCYbAuD2JXN5/Is7ci IB55MLfmWJjwhCjw1Lln7f2wcsdbw55kz0Dswndptk/MU4JZKtWPP5mOeF9mBLP4tAds9eyU0nMi 9Xe+w8gVVn0QLwJo8chwxaR5AUlC3WqIB5+/B1kJSsuWN7O8RCg9E5ZL+XfgSH+FGBzNiwWvFrta ifPLya0asZrUFMfbqwhmsmLbvkNLKw5/mnXYZVr+FP7dup/vTLphtRwCVPgtT77CDhD8HSqTFnWT mpABXtrfJIwyW+J/oeDcbFT2ZGiIu+yiNabO5CXLPBiYoC/Pf/9DlFQSfvGyYOfLHL/peI7YwgBw tBhEjNmg1NHk0emlYiqiOwuP50Z8tTUtMhuV9iD9vHP1fyp+sHr8cEhtMwCdz2nUraPXxhjDbZtK WmEdAfl+k7reu4WYW7BFmQNmMwDQLmPtGwt4UUDaaehGfHga++1XHRkuvOTxXc19PEeMpO2htqpZ 2EPUEDTertsypwT9whMW9KhpU36Fg0mSGqA3N+n5KPSgF1bQvBhi0yCwa+VsOkx91PA/9PIxUWPT A76mjcArFeXaELityYQXio22u4GKTwVn7PN/ZpfizWuPGKC8WWtROAVrukbZtRzWoJDHGnizLyI2 oIFRNz3pkXfUPAhhxTKDPcwXLpkvbsux3aCSbsM3J4W+k+MG9g6G/u1GySRVbrz11bc1uOrJ1w6t mEXuC36FMvK/9EWiyxX0kHgB5PN0Sf3JQUOWSKF0Wivn+MqGaEMNUuJKroPtvMQvBFdvvhi9Naki y+nt2rCPIFE+mui+fzbyiKQybsri0wecjXgvq6GOvbXWd3juCpRDA/iMqT0mLIAlrfqNCEc9tvJL ubEKHu1UK6WfwrWDTU9N0zzQNk8ft4gIUzLSY9zEOQA6NozIc+0vUUAzswYcznpVvcQu9c8QvMfc ElPwZAMbwn2rzQBb28o46dcEsBQgm1e/Pq9ps86tCWv9ew3Tn1Jw71OywLqsJtTc1X4Bauz47y8F DssDBeL0EQc4+mDKenxRVnGl/Z/qLD/O3xDw/CAgqJrtEokk8VnD2DG6Mc9XWuS6KKfUFTIi234e 2Za/NPBCP0NYRc42ijMHXhodm4+2tFqwVgXz1eZug3oHbj9bdXeo/vw1Csws8UUlN/B7exy4tRYy ZUASp50InmDSXkWfMvbk4WE50oBRqr0gAPwxQKVZFy/kvR1fpEY1iv0SNX0FyGlSm/UHwoL/yrfl uAtyaui0kn8Y8adfLrn4czIsF4IpLhDrlkTebeJCua8FIK4SJ3g/oW/gwGNIrAIgEBhpc4ANAoAg /wz3VEcecZrg2hPYEyk5ldRf4imIzuqA6Yt9S4BDlSpFDyadtK/06j4HCvD4csr7wbKVwQPP3UXA f9SOmKk8Yw/3J3IPsLrA8UJ0C5s6hSwoab//Mf0iUvIPLJfQLew5Qe6CKwFC8qjdaJr8Rr0NCHLU h5dklkpk0XjRD+9lpTGSIpRRRFl3dPYU4zIpjkxYwZJf9eJZnxU8LBKUuAwQWqu7VH6Z09ZhlxPk O3FevxVJIJ9fPRPDzAh/KKDIVEJukGJkG6bko347SYie2TxLLmep7vFdz1B1ASSrEa7yzj5Tm2Gq waVjjlWgnlz8ub7ksJA0Jv9SLGFwDKS+dwKVG8nHxF1NRMTCipGIAWXNHhIGOsBR8wKIvgqnkiwt fyyxUekwSxbjs+kLXeJTHAoFBhoSazw6Q7aiihUQn3OcrA9tNH2tNHXxNhpV9FpadSsBiuZs7l4T n7PKuoySKLYDIK7MDMlpjLQGhzv2q8PHepYZ14B6JmlTq1Ww8AJo6UOvgQPUMidd0rwoV2tA/6AU T5uC4K2lllnHpo4DJ3NwEPjEIk9EjKycXBYQCsD7ayq1A8ZqeQmEMf2jJutd1uVkYDptV8EdCWtd tVwKuYnnQSEvXe2hNzXPgPTO+T6Yr+zi+h2q/RFr73XLoBenzkbAtgJD/6Ap50gn0TMrEXC2163X /hjtvF0+CjaqTR6klCmAKTEKg+eZ+XBZ2yXU4rI/1duZkdmage9Z3s/ceyYC3U+ejTmqVdYlb5dm cTyO43FTrqt2w/IODSAB9iy4xHgrLDK/ePDHUFf5/ffC0jOXbz92KhqOdl8CSBZhkaIkTDQ0dIK0 u5GuOADLaNlIJih2kq+PIE+TAtWYKEOCql7WvT5LGGqZMwond++3+h5p6ICcmGFkBtcN09R5wfE5 VvhXN88CeYwgT+suUAD5HJsgJjaBJtkEohDa63FRChzcJK+f16uBwaS+xxDho9XJr1GPnY2MmA9Y ECovWqqsjiCeYmgT2orsgxdwG6OOdckZcciu5F9bDhRZuIorUPCovbKBZovKaHSEGy+/mxhXEC1p RQ5qqczGwnoX5mhSG8V3KO/wsK/B1+k6oMiyVJLBZrouJRiNSDR4N6yFXPdd9xSC2dp/znGrn1IP TUfrWtVCy6JpVwzpJ1r2aID5IwZaNIVz14/E94Ay+rovSF99qdxyS2j/XF3waZ1+WZ5JyQLrx1XR 4YCB/AzZxfFq9gJmMH7Gv6bqiiG5tnxPVtN4kVEQSLa0rqMYJwBqZAiFEXH5FSjen1pZnwJFZnJU Vm2PCpyL51iT8RkxTBtRTkXNbYjZwC2JqXAV6EEkJe0TaNFODB9Fh0r8sfaZlHNEP9wXU9YkhZHD kX3hBrvA+GnbzpNLrVLOpqqFyE1w9my+y+KyOI4VOLUZmzhMgAyAZX8LZFkk2iYQgnq4aWo9vrWZ OkQn6WcxZxAk8F9uFvnzSIniOuDB40bLwmeny0CTje2AkciteXvdsZu9r4gFfYHHq5F2igZPPTbg oQKca32sytvqqEdpJAPOe57uCt5u6g67BgJmj5WtKRUUJO6591vmTeDvN0T38PssjohShPFaulbf 2vVrfVhPKXy7i41TKOd6fIE4VVPXRwJvUnNtCgOtxmO+srYw4wLH8SBx6YKwq1MOffcl1Zg7TQbu jJpLvMJPBT7KWraYMOXWhHDiRvx1yAODDz06xd0P86sGCX5sdRzdmoeQbMoNh/27qrgdviAbx09N d/mk/fAPLYBv/iy9lenM8/nZiB0jieu31IiH6M3Sv+kC88Kh7GSXrlrzRb5koiAhsaZMPjymWv84 DYdNbXQJ2sznC51+SY+WxwdYwV46+6OeCFEIulxZv+F2dyTpgsxI/FesWrX1HH58C1zawX/b/J6Q n+skLWdgjJx03RVRMmVgW9FLQbXQTheZG+WGnxVXKYVO9Qox0uCrMlv8dGyUsJwKDoEMHwbbffLc yoARKPIKHBmgw9TbcMqXk+Ehe+E1+m3nKRHxYoVXV/Z7C6XucGKOPsWcJ1krZK22dfjCzuxR10jt YAkpldERynZK8NI0q3kHorUyA34tqpMadeODUA3CwzMLE7RPxdrUrlwEOJPylyY6uFIwXAEBKQo/ wZVs92pGyPZovGbuRynHYXTJj+/3X+3flOVxq3QqPKrs/tFFcWcSoF52j7wGzH95mU7l5YsMDPAy 9iiNigJQ3QzIvKhdM3wqCU3cxMtN+8xNIo6Co0/J3HqJ6KC0tMRnVjiNdt3Jn90ypgmxPYjgZa7M Kk0EoWcZdLu+ZDpPk3KuSiPh+0cMcWnyLoaqjc7wRDgCBJac1gjtMgmhhEnJoEzxpD48ewG+qTvn JDwxbxPPf10MNMpndpbRnOv2BNuSExZHzJa+HRXljj9lGY0E1tC0nQzfgmeKoC4LOE8fI8UB1+Ms ZOWeJDcPd9CpuhtwAytQ0dx3m9rMdPJuHfuK6yOVjcuAKZ66d5FuTyF2RQMcaVJUTlPEsZg78Koj Cvkwd+EcDkBYRY17K+OMPbCjUgqPg53d/i5++HPh+MAT129mI+tmGAqts75MdlxVSWJOF1OpBChs kQhRllLWS68fzMCGgx+vsDiTltSQr1MVYZBfbAZkBY77sJiKWJ9w8HI2ofuAqxPHrZAkQQzyxmwt /+fPCOu4Jid9j7686zdmY+fJ7qf5GR8+5Fjg7rwJ2Lj95kwqoNUzhQv93Kb0vTVtPF3tHa+6ODPZ CUzVYJi1VJPMUEd8f2zm3RpUsCzW5rZX+lt+vaapq6TS18fMK8q6zU1BITHnyB+MSq0veAl5lFxE N9BoXv7wOiPpJxo88g1onvD2CHoTjDXEXWIemO49Y+U6LD7WlXdxbSbtX4gUKpaIFrEFvAe5FMWX Wq/jN+8SblgRFA+7DAxXicoyc3h/fGsrMZjmyskc3HSxG0YPSmcjCjZCc+qgg7Pp6oeA0vJM+OkZ BkQ478tZmaJ0GQu4hohbywCfPIcqojuLwQI2yK6O1eVpKMhzBCk1qP9qnA4OlbJadT5GZvDvpEJx wo9FMm9b8je8gA97asZSnkWGE9OmhNw1hjmF6e+NR7NJtLSDogeyhlzgzOtsQSiii5u3fR7i8PLJ ROysiqXb2n+q27f2dQLlfPN4vOkeh/v2NI39MlhiFF7l1ytFi4UU7LIqrFHUcJq7qgStFHwywC7+ oErVx3SNKaozltV6wKjmA3qVuG8VLCMBXiCrh4HYQWH+uozW7Vw/SPQuJBKAmoaSt9DzAxwjklG1 8LqzTAtFvW8IX8Ml1yWOlBeaiV3oGbkrnq66in+1BPP1QjqNDISnfJDrGTwz8fmRmdUKitJiDj69 XeTkxYiejU9F1zSllLZ4NAVT3MDPLFLvWf+gBPq0Vtt17B7vmTwA7Fr4N1WcS7ZUzhUuSGjs0sge DL/we9l1jLKh/FAz+6B1HjVL6bnkzWy3ydG9cqmExw8YF5nBUSiMtsIakd5rSh6J8VwPZcBVW24n vSKz6ZI9MhyvkiDU3OM+NZrRKmsBblp9aFKM4NLMj0jCW9pvYpojQ/b9GT+mLpZv74mE01bQEk1A pUkOChAzuj81tunr4rjsTv+DVv6JEEo2X9GcM54Mn8e+vvccjxab63NKj4UQDahBqLTxIC8pTFsH umHlZaO1c8sFI4EWUMylrm4ebQMj3ga1Qg6FdPCTHhcAQNpnFllHpGxe5q76wmdNs6ApYU+JB9oZ aqU7MjnGk0KScHyWPW1lsg0wj85l8tc7RrIq7ZDT4wHB7Wi4BvabKF8n9vKya37zC+T6p/jLviZR Okh4Z4VHszSeplJwRU9gggQWswrRbCklAppa47qdJFosME+BilNzMdqaJ5C0EumIzfiiRfwmNp/e SWZtDAq1C4ZkPHJX6LkYS2HA84ca/8ns6K2+YS3ljTtIzH+ARURqd56nJaQNEBvJivCipfxnCKna VEfl/qvHoZpo1NiOOiJWfA9aHjPa+EhnzW+aHwJ4h7mTguYRtZVQUr65zckVdBAJk6tULeTXG6wT X9iGKI3olUpY/nNonahpOaID1Jc5Z3MGCf6MSk4GbRw/hDE6XCGfqiTqezGyjKiDnkoCq7La+m4n Hbx2hnkfEhVLbcR2T69F3ay1SLwqLG7QSnaUY6swn5xGgNfLJgwGp1LPzjB3xBFHAIAdcDHniyeF +NqcGEzRYRhAN4SceRcR4p42uXPo0gXcyVE5Vvq4IBVcqOoarS2qhPd2qch+k8ze+Vfk3jW+xNWt WFtrMeXbMQ3KbnumX3rY7CWrRBS0fU8fjbGR2Ibpb/0d/V6smNpUYHseG1bhCd6S+y6zhEG+aPx8 jA1vevXGYrxuFN/P2yTL/DzkPOMJ4qzGbt30by32zDgZ+5I3GgkfLEL44neYoX1peeZpPP4Bt1mX +7PyD8sT6tkdHen2HGtcl/47X5qRJv+Uz6+nQG8VG90JxTdp0ZOl1F/3MubSX/E5DTrYDDc4R+dH qeTncEaJuPc+jcI+vrYP+VM76DF4Xsd0pFeylNuddTrmAXgBOw97eds2R6wvI0allWb21UZO8/FG 1kMr1BH/CUllHdD4e2u916wDJ/Kv/h76ZQPz/4OVZL24eLplt3XE3YcTuJvO/+MGSxzJ826/Xs6g gBWRMLqk9dtf6TgVgViBZSyA4DEk1FxTH578HXbnJryxNzoTSvN+FyweHQ6p15lVOxnEYdWedKYJ bDempqBFy4oat/vwTCQnxzRf38J0GH1Mxxj5qKcU6v/5gFlbcQcRWTE2eOVxSS8+khekaXGHep7Z 4u90aj+KZ7jXBBVS6xmD3YQjlTyBWRQxvm+Ixx7351xRUefLl8ptChfhJWZJkT0nZdkxMAK8mm5b QJl9IlFYyf03At08dCkWphaKqhFWPWGy9kWgeeYsfPryonRYk4VvGHMqPZaTn6ZEHy80613xprAt xq1L4Pjm5S7UkG9/SuoVaHrhE+XHHICsCDdR/lD3s+690KoV4qChgtGWy0AmdTOkk0J2DImnGFke J64hjZbV+qfMhznsWzCLBj1rWxTvMRzCkh+B45jq2FGW6RPX1aySqmPsty58psgqZ/hzNiCMVGPi QgoU/d2taLLC+L8ybQ8+N7LluTTa6cf8YK/x/cz4d1eGTKkXsKyq21m4Yxj2IniN3KApSRxBI4K+ JfNpTi0gbQ2mqIU6VC4Ts5Th64YR192beRpdz56Uv2nGwGOI8DWYDMQV7MJw9O66W0pwAloLv17a jXvoeh54S+felyLFQRS5AXHRZxB5HyEaXiU7Y8b+DCI5y2ZOam6ZnZHWe7kjQlnf2z2JK81yPluQ dqHoYZYqkABLtyVpUULmUxzBO4vjDy/N8o8Luhne5ZtDb8fXIam1U9A6kE17YHuQwvVbNFprenuH TCA0vRuGwMLxdFj16AYy+jk4/ERS+oJ0ZEhxZH5baR6gGc7g3shwq+nar9GYhW69ZXd1MkFqcN5T xI2+mSC5dE/paWpES1QX8oFwN4QFSvXyj6ez4B3h/a1qfkqQbW5x0Ds2CmLvLKHqVUUGI+iy2EnR 5jFGXwCc8h/Zyto2EqUe5le6YrAgdGBGEtNmfpjLUGAL8vl53YhEveh1sDPWPc5YYIihTRh3uTUj oQPA+ycpzpU5StOFXZhQCCcnUHsfXltHc8pUscAZOZLBJcWsdReRs5lQMMFbuqtBjktsAUdg7Kxv ezPeFJjVyF3iXYY1hy6z6G1q1otyZDrMHen3A5fGXcJDNEP9Ji7QBNaTPDBGEWH05M2RWzKOyfNV Zlt2EegLU4nOPB5SjHChOoJQiJ/IUk+tEzoQLge5jKJBqY3qoGYnixXM9JmdNLq6YlE4EDhvnptC Xv+WNZk9z8Rr8mZqXFrNfa75C1gecUZswDuQM+RoCvJ/0aF63LqPHJZlPTXBuJeZtXq7IMPb0jve xPAW/C0eWet2ZYq1vk5BFWMyN5+ISK/Zg1q+4f99ocrEK/2+HSm10XMZUpoUyCMYyC0Nru1tACMi PvTNua0wdJ3/zh0GvuiDmuGmvmvR+hMLBoY/lippjeiVRhC/22wUB2OyGtup3FrRJiqsCCQMqZCE c2J/WJcJhOPix9Wu1fcSG7NSIR3KtxJoCZ1AEZ28qOFAWGz+7yPTZo3I+Gs3bLcKRUv1s77ec/p0 LxWkdfvD+45Iall1BmyqxhzYPut0xmDXqjTeLauoiXOoR+OkAXPnMOCHh7QneZ0Z1xW0ZxLnJExF NfVsovxhwO7JEsbbytAjO9fO13I7UkcgtcPhqFF7p8ZNNX+2O86FOETPfKPhicAgv+1/QBnAtLxS rRByhWJ1VAzHB+DF13l0kPJt4yifE5sMW3eSrUtS0U4SUqruNzu9n/NAIXcBLXa3b2WowxVvYXWe vD+uP3RaOJ1ue2LA1tmRzpqUvW1V5m7qVx5RpgnjSWN7qJSgkIfj3+l3wKyHf0XudBdjzsEt0guY MYT41f++/p9hcXIrk3x3DjGTXoNWXVSfZ7PEidpCq+u3Pd+TvkVZQhYJfsLD+w0GxM1WUr1qAxZw 4aXKiFmVxTkZ91wY2GQPvGKRWerVD/YYKAWqcDjKZP97IRJ1Z8HyUi3SLAqK+sjIp7kkQiVOEE4U CAmhGJGOJAYiClncjRbp5QhkbAS0utgvhjQ0s6ni8dm3NFBwxxngL6Tdp8eCm5RRadTsFR20ER1s TMPLs/YIehQ6SUxd+qTMjNLKor/3yy9XkmWrBV7c7vb6JZPhMvDUdDDKbyeYzkI6uq6gatijwm4h Tyn3b1FlGRmvRR4+YDamjXY0ZI2zBE18VdF/78dmwTdVpVE7PuU5JdVsrbM5c4kJq7Pgb6oqQ/ql 9il02wrF0lJPdudNvjtVvbskAauRZKXy4q87Cz2CAJ72Hq5+T85WEL69z6dBJKjDY9qfqTd2CzUO drid+CsjGOOz+4MqeEMCRc+geQBL08anZE0MgxUifk3z3gFhuClk4AUo9KSiX4kK4BMtkkLto7D9 I1RPQ+1P6rbvIYHGYaokgT7vGh6mq4Ji1euF9tgvu/3YfAnv+TzNQhxP6ibo/n/ZYCWKulV89SCF /u/qr/qdSgRspOi9A6sE42rGSlDLEzBKkib3USeFHMjyl+nBoyJ+chMZo4p+iIs+5f3n7xuuLc1F U8oIujlHuNIfzeH+HbB5SKLLX8G2dT0qlZsHxqngPw2ZtdbvFqALMB6sq9wO6MADvtsWLn8WLONO wAzQC41UGf/dDlQlPRkh78BLR39w+bHrXxDdcsAEmlavlwMSX8bYDt8pA91YHbvbgyqYFvoKQSYF dtPUMnf1Mq2cCTZg9VoU0/Uk7VfpFvEA46doJ3B8QoqxJDD0M5HwfGqXTPFoD7GJos9kEuzp3hvh Qv8lYg9VxujaUcK+M3qVgvMCZ/j+JBpdUpNAagOHcGtGzokG3bjw0x2rfTOqYIUbBET+DrKZkWUa 1D0TC/pxsUVNa3R5nBBLuUObfX7u5TzKvTuWj4ndYNHWw+y44u0YRZoeqwRfVBlAwdLJRxnSWFX3 NkuV28Rm6rC1YYYIeYcnge/eKH0x3IKoUK0o890ThgHZzc/r6lmxyaa5AMiZ7BYYMtO9e6FuoZwI rz3MjkmoHAbO1HFBISxCqFvKJnjyL2Zwinl7/SxxuCRFLskvVmIvvVszNIJWRioMvOya4cyEOkqF n659TCU1z9uQr73EdiK1VJ4sZJGqj2uDosBgaUTeORtYp9iSh6YI6/Yq5lDouyHDvAALdidbXGLk zLlY3etxBryIXnC+5DljuIXXCLf/x8hqGqcnJ9FN4lJrdBWGuD/BuVs19RCCFEjqTwiBJ4mzzYtY hhRqXvQNGKkyKaChE3fPWRDmnQg3grkQXJdZ+WJOZlAD6AbM736jmN0Z0gq83ayc0VxwIEU6tQxY N56zkP6tS27vNx/a7HDLfRdeivEd+4r44HfzmjPHpk1xRupmD1/B8lWFjW7qmUt0DIWG6MyjXiHx FPSU8YEI6f6/0QEhjbk8W/dLs56qJzMYQ1IdAfGQSDmO1NAnYCsjL+eceGzo98+O97PA2ckqjFRT NfVp6JqNUTVxmzCPnZmCUx4naR4BKRWyVqpnF6QEVibIMctt+hsvE8XJh5YaztVfkUc/QYFsHsBN q57qoU7Fm3o33aaZ0TwxVS0+TSZYk+YZ6vsPEA6Xag6WPvL//vQSqHXhC6N01xs40u4HdD/o28je ZjReMLTjrkF3h2zcA7+Ay7pIKD2+wnOiVjvz1mbnmpDR7w9hd0U21Co5BV2pCcC9B5LliKarft5k ZDetbNcvQPYebeVinkt/K/GNufNadwX3Ahq5BYYL0KABxL4obCFGPNPdkd+b6Ir9YEupR/fHco8s J+QYu5zXk71hz4woJwkz2ccNXHWRLDaaM3QfxBoyiEMwczuHY0U5fF5bZsfaJJmkTQstV+nmMBXn sUtnzqq7OxsScXZaLj9b7uliTD1PoARPfOQH9HvhnWGnuo9pcCbMQNYk0TB8s5blqhKydi9SuyfL 3jPqUo8pirvCS2hX8Er/I2gUSC0m0BIGnT1X8r/pKGU4Axee4AMbt6s/8hpjsExl66k1F6NECUjm BBDt52/F/y6mxVMuuJkHArr35vG7T+MuoJNJe+uIMQRjzmPYGgnhybq8F8hyogJRhIsg4Z3HmvgU UgWshz1BIPsmeNKPEx1ZF6TStPgpE1cH7pPM6uhpw0pAri/9+H/wxzbgJOuNlrN2Smmf6DITUMNB NQ4IjGooSv7G0+4czYIix1BZufavlTHOXLsr8mWhERUrFuu3ujsZ8uQgy6j1E0lsIdhDn2VfwCOH ZFNGK54g5iUqV3NrD2kOG93AICKbcSAAgqTbTA5SPzRuCnu02a/OZ8PUeqviUYtx4QGZpHEYrQfg f3PXZVNuX30U3hixeHQdveI0NtAC51mp7EqXtYqadQOutlBj3jfHgMkGUmi0AF4zkAe5RZOeGUwS OR7X5xqO668ESneKEYf2BEO4AAUAaUulQpLLqhvJOsSb1VBnBWZkP2iirDGmUiWS5KWu/NNedtln 8OANDYhixY4ExquJpGYxdzvcIcT41/bxEogigEQlU9rafTJRyTPfz0vNAggocrCcwJLUY0QnvktS FL1ijKZNSke/3XvtQ6kNG2/Wewk6mwh8UFfLgUO9RmdCa8i6h2hsk4yz3B6qjdUZnQ+O3XUnSFUS At6poVBWICZ1bYTKJOE3Oi01zhqK79QmDdylBOG0iXSCE2srUY62yoFv2O8A1PRhp7ttTAaj26s4 aDdqFqhJGW8p1Dx/awIMhr2pY3mjAktp+GbkobbLicZMh/L1gtL5H7h+5WgZMj5DYg/o82TfkoD2 ZknoyU7U+OJQ2wFTyHCX+XdLkHwcHe3fuvFfzGbAs9p7PI/rCjIZ3OpEkR/zfgvSht/qn/mWKD/8 0zm2LqQ2tQjqhJrPNegvLOXQwloJofrozoG0APWLXBfOx6p5zxHWiWieDe/YUdmT/gUrMzQDijcK lujzDkS0NZ5jirlZesxDzf6306+L6QV4gAwtvWlBk0lXVj5ZCAtReQkYFUtpEru1rDvw2YqFr7YG lGpXOnb83Mqj3LfH3J77byiU938d1eRusa2ojFzWGfYP6vnOMRj8hoiix57HbXT/mQfJZjcCX69G 5/v2XlgGRxAt7bYPwEHuxnN64xpn47sO5sLPxvlOLlSYzcnnR2wTnXg7XvIIVNUnyShPOf3RDV0x Yg0Cjh9HEDPjzw+a13W8p0tn8XAxhT8ZAyeGzjHwIj545jpoiK8hREhVRK+mccy2po7Bj0deST24 E+jHy5HOE1A7Lxztzkjo9WBLL2zXoq6mZIHYrxWugXRbkscPmnWTJIdR/F9I0A+vbZGyVX7o1z8P JAFMxjySM402PulgX7ebbgIJgI+8H/DKQfnKJKw3PuvR6XDUwD+cVva4nuMEMnkW+tt+lrjOdS8m zh8fkfxaMhxsWSgOyDZpJ+ib13+gZ0ep+nnuHIQIkYq7JfbSNzib3f3atm2sjf3V8b4wNXjtlYAw ynxMXGTwaKV2Bc21EshbpfbGK8SUdDEWfxtyL5tdur0rNbVBnbM2nzAh8yGjrJcfMxem8tU8QzMB /R6NXytPf0X1wWEda+dO/zX4yTvseLOkiee4MfyhalZ7EW4ZeNEse7CNQYE3nUFfNl7ch0HqnW57 /7NB4BpMHSVsQH67Tv0Hli6QWuj2HH+hMQTkBZ/VOwNz/AyiHzMsWrrSfWBWQvDwJ0O6THAPVaZi tXLONiWwjuoZnSbF9wJQwGurOfTZ4zrLsPXisq3sQ5UneqZJXJbXRp4u9ED5oQtTAoF+tw5iyicy d1iFhekmarubUu+DTMw3qwqUOahQ7aBMCHJuI7/saHwV06ZcMR3jVzOlEUKtovZPdPYaZkUH5pM+ hcYl7daLdrqasiRHPhuwy2Q5ku0FEgVqkrcT8puYirBRWxNWE8+h7kKphPC3ne4MBGMNFbL+iHHz LsjLL8W2D01CReY/A3gpCey/G8NeDAocP5E5aMDgsMsd147MH/Nro40DCDs+XEfFQtEUSEdisHFc se+JT+UKJ5ljEHZVCFAus8C+5PEarr/4/BUWgveNr2PVtvWQRQ+LSIISEcE2xATl1dHH2W2d1Dsq MvBVs19Yp4UFHbl8jagNU8rDysKS0TiGn831ByAgQqJsziiq9vpKJdwRwesDDJ0unMIHDY+MNuhL STOZvIlI3sG8nYTL0Lf4ToiyATEa6X0jktiXmIkRbu8jXIv507vs3srfQj18pCPBIs5nf9oDOVs5 h45Ew/i6iApwbbISppx+xbX0tGdvWDlrQXOgibL+3hrH34aGK01XyrwcRDBssAIoLb42fmlMWLX9 MfsKcxaLTXmrhfkotmso1LPGMLWhoWuSCY4IEcdxRavYWHzj1dr6gFVWz5X02KDo6WWS2rPfCIc7 9V7GdaN1hXxDQc4P6Jh7C8/8zFbU7hEdsGCDZp54m+U5ICJm2N8B7hY1WiJckCyBNR+1d9+04Ray hm0vXoXRCJxAj9pR010qdR/wUd+nl09xbYp8bEACzT3oJJCJWD0jPEAmKFSIhQHSaHui+LOn2c1M Vl2z43E1HyKfouoVMKgeV98ovi5u1o1AplD0b/FOBoHHJK5uVbkieN6Eh7V0njfR7Ia4HQREU/Cb gb5Wn9wDC+W0ejGmdNsUDXsVtlwvk8EdwK1f3SvRi+wezf/4psq8JS4KIhKA6/J19lmmH3lwM9yA nJyjklshJRV6FH9qn4IsruO6qTvPfp8l6zpVkpIebkkQAlPgsmgAtXEZXcQd/U5h5meWcL5t+ayt gmgeyJifVBc1axmVNvTbY8IfHQ9YxTd5Ql+T1EGmXMOorGq6aGH2eV1REoGQIrsQjwa8GUa06jpe keHGX/7XoKbBQ83FRRTxoXjOsZmm01y3zW1mipLyXvHltLHWyp2U8Xehl1f6qB8/PlUOC+Je1gbP t9+chxGO8HHhGlCtddH+POkvrx9dNjDykOBRp2Owzf9nEjC1PrCjdsXO0p+kZTnRT1ryubALFvGl f7aznfLhN/87fqRjKdqHA1WJD/2POC38KwVHHpZJFdesKKj5RgpiC5JJywVgedjCOaYr9F9B5XCv ZeEXfoU4xRDo0Wuv0MxLCMs+kklwdY/bCyK8X1JI+LWtM3+6rgy8fZcrsMFT/cViBepbiSsOmRbq vcUzxjOyMlasq4Zs8bi5TDcYHLAAgzDxoJNnL/r8bXQVz8HESfkwxqXQ0MvZEm8zrwayc39JxtHS aJYtZ//loihnCEXukxqgdi45RFuZk76ct1TSd0NCcPl6TkwkK7S3A5L3yeOYiRz2QhZO8CiOE8HK vF0z5ydJjGsJpZYyaPlXD0CuQxNZS8w3Ql/gxib7qpTEOy5vF6soRzvW1NKp3n35TD7wqMBc+ySa QxdM+a3A+KWqQ79jo9gYcpdSxthakTLCZ1SiTgSm0eRh37KKue8HFqeL3HbrVAKvu4/LcWQfEOCj i7oXlTyJhCKQnus7eYeDmkYJ7BABsmMvzB3oCjsRdqDhsORvkxhroW8NWLCXpjTUF43DDI/nlEL7 gr+ySJmgVYlyjomcAhM3KzoZjDC9ZyG0sTnYwPfmSmt+ojiC6t0WqeemzQEz4Vzl3g1PYd/EicNV kX7W8wByuIG9XmsEMg0BSZZngDm/6Gg0m6BLzmYlbt4mDR6e6Z9Y336Ns8PFt7oN1KECcxsPj7U0 i4mrJiSOaOw/hJo60Exzqvtjxq+C9Vi4PqThJqn2LHOzSy3sQPGJpyHlIe2hzahZ82/hvmuvNU0r 9YPP2Uapay/JZVQnnQihmW0mo+n2QSk86L8pNSwG++yFRxoy+jCFmIN9tWXcKRAP1cvcjFmRujbf yZHJyazlBCTHch2eutHl7yO/HluUoy5ZlMY1fZupafbe/IzpLuNObPL3AsmHVseaySl3NPFAvP6V ouTJ5ZywE0Kdf0qTj5eA/Th7K9YmzX3x+z20NMY8lHARnAQWI+9Ltk4jtn81ioRkuZuULUHg4ro1 9rhb9eTuQ/KBZN8gKVYJQZOSi4waS5N235aJ7YRs+400GgZ5IOkLhZAGLAeGs6C2e8RcBuLAszrn KXblJTOHSrDscrF7EZ5htuDSPYDgqxcp6fTGqbB1oC31OnA+u+g96OxUuoFsz4ZInikgVi0ty9hQ Hc7uamXgulabL0jbY3GszzT6xvtQfEGV9w7h9+WK+9hTsyEku36OzprCNH3FziTb9hD88AVymyBd Gt5S6CaGPeHpP+maG351liHJIISTlvLJwIfoGMDWcJ4PdMlLjD38GJuN/nT4zwWSD2AqfhsF/YNg 5IHXUN47Kr6pOx1zZjdetFmX933RXG0GI4CRc0+VNFspP68xBMXgNeybul1r8TCi9pu4f3687+Ht EoYSHk8MsvvWL5y55OS61EBn0hNBTDDCBcrj424BPhTiuX9UlI5xJGhXh9IGC2FPUUjjlfOmY8TY 84CHMAvnZNFuGHrs8W2rys70P05LPX2Ii7qfbdM4nhLcXMTq/ktDn1OL/K4bQQJNajWpEi1nMWlF HP83TRAd0GeNFIAJGdQAYh3kqMtBIJQw1TcC6HGzlBIiyCsAU0mxalsJkZppZ+LPkKWO71tCFA+S 1Dr5mK8gs9/ggWYaL3b6saoM4s/mmSf9qFSsoXV26JGgkyF3+CFrsj9uq4nUqCQrlui9hdhkKsFW sinGS2hBrQ/T17/ue3EX7CskpS5zOTCRh0dCmMchoP2uy4IvVuO1k+9duaXj2ww3Z/wsfuWh3OK4 tJtbyEe35QpisSWzPRenUq53mA2RehILBbsZtGRPVC6gCngT51HspzhCHroebzlgw7QbYUTViomd lrCBZuN6JUTzZLl5zQ3/s+qrTIUSxxWcmU7Qukhg6kfU0JUHyBpmKlaNK0jnuecY5pYKqknWzqK8 6auWf6ObGasFB/rglwrh0sYkJZeaygg4P4sri8sTqq6Mq9RXaslrwpaC6H/EK0sH9MM3FCMpBEBc gma4qLmddQXZIi3yNmQc17MJQC/Z0aHfFDcpbCacCjgDLfVCMa7Tazpv1XhlQffrs3NI13iPZ6VJ XQtduu/+/ygICnMwGJqJ9b52j0myApi8xloZw575lOMyWFE1MTLLYvqtxzGRgbu8rQepZyLlj4D/ ITn8ZXcsZ70ia3/Nn8W8EqBUkSOAphzdXWNWi5ezkvJlz8Q1nDs1RvCltj/6eYdTpya6Q0MuSVvM SbxoTq0MzX6y5UzlX4PWuQu97uBD1sMlukver26PjE/IOY4lXDqTnyAuehdQYfohIaxxwdS4Xec1 2mMxy1kXGD/3Z7rHItuEs93C4JERwlOmPl2cO568DIj97nM2HC+U9nNKepBinai4U+gLRbqoqO3X PJEKMua4yZB4pJ4drwkFzGhXNMPMzZlngdn47grBxU4CtUszpfpVlTYVPub97Mky/tZsgRJHCuEo tIf8grCw0dqImClhYd0YMWZiLfDei1Y543mcfjMfu9NvYjUW8gIiZfgWUYBu7eJ5JiTkvqXX8wHi I7dwDd9FjlOCqwm8nj3ciTTA9RohkYNIx8O2SvJ4ttG80XenMUS10TJhCZbVdcjzoWXZxdMFg0qO Eh6lMFnkGAsSQdwzdvl+KxgqG4rk28CcJNIgJnqXJRHnJ8A3n72N+DZ4hWFYtPvX90mShDuj2n7H Bk1CqXte6Ygb0/TlV55IxtMZ618cO9DNodyaiC/RsoteykYeq5BQlcj55HZeY6B1GZ5+VNnNa4KS 49nPfcpKrewUpVGJriFMhHmCIqjF9Y9zFkQZdDo/LqU6pSskysWYxSE5gwbjYXCyTFqCpHlnwEC6 0WdKF4NBDrHWzO97uM+EoKfchAYnfviqhLPaxDhdFe4Ayx5r8j/h5ULmYE8hDEdfvGj9Dt0vYqj5 8XyXTDFCqCMehOjn1OOJCdJuyNt7QX5NtjNI/qlt6aGoBYxa2nnlBQcogwgNGQKT1+mylvPvbKhY hE5ZJSXB6c6/IjQh9OM/3ggGLikS41a7MUrSu5eEhDqzM+Zg2Htjd5av9lwaSkpzLoOib9L8nm5q JonHWexNAfx4RejPVxhCn+fD9LJnMFSrnAulHKSFlygOQ7cRC9nL5QgRXLIFpWL1SST1FA7UTNWj d5/qqROPNLMmZiTk3k/gwYjXVtx9k1PelxlFm/xPeAw2P4mliHuILEwKl9arrVD+MTRx8Rs5axhX 8GTa65JnhuDqs4KX2Ghw74fXiidAr5YGeTt30aRaw3n1B3vR1cmipLXLYZArsh3VA5K2inrEFfTT Rl4DqKMXqWr5JLZFF5svUBwtfNMnWAQfPI4kB1DhXHu+ydnZfm1aY3i2zRZMB3Y1SkCksKCOtSRT yx8dygGeAOyEV3jDcMRpFPRUL4Ysb2Jh+GJyrKOcCtZr9Ky9+FYcViIsZuJSzM0NO1QAtyvHSJSS P50hGoMwbpySyt8mDzkVCjwKdvPFqk2NVkyKt7D+14P0Ld7lybIl6O1FEZ73/QG8UwgVHg+PWKuW iWqII9WDtBLzHGDt5WZ++YeGQZ7ycmRJKO8eWdmfMo/tBah85FT7SgePETDdNtzLz4kfTnKeD1Sj CS32rEHJwBvM2Xdhy9IRaSLcTobA1DUJ3Kad4XHiQPyfBAX00FN/lMe74yP9XSPmdAm6KM0Zijxt JI80wa+gx68PUJdpntLSAOpzGneQydNaBNRGScHq1DG/caPE3s8XjHM9CMl7ZExUSVX3eR5w8+Hh 1qJBLyCHk8/4PAkuGn5PWGNa7Z9S79eSHORlqQg3m9o05grdbEfka6RkVpcYrGmtB3urZZ1Of9CA Cd+wm0Hy5R4ewKX4DMfuTRqmaJv7fUoX7/8zww3xojsanjo6mjFQw2oWCd6zaFctEMdbXcg0Gnri tZ69nIh5gkCItF56s5AZVL0jcQHzd6RXWohiamNMafIAcj8ZV6kkdBqXdyREJjxJnqMvmlG0mcN8 vp4M8dQMtoNSynBiVPyIYmvmbn/hh3IxpttlJMXFRcO1+4eLAcbXWCt1qh8MbMpZldGjwUlV2DI9 UB6JB2P4HOvqDIkFoBpNh8J6ayQH4dY8EN8CyCBb9frh5BU0TzsDO4mfB6FEiL/QBPSg4SlKVfge eTW9ZFUp/MZ0xU14RIX61B0a+BaXLO/VwC9PDOj73iJ5vy6WFIZwx3saRoc89z+Co4EdG5q2p21A 5F+G8kliF9sD1joEbd6tduTLahbGHLR52NCROGNBnLUzIInldhSf0lMGhSOC8POA5vwKUBKwcro7 44zbFiOXrIpl34XlFdBH5HZssjThzPetVZlvoiilANtHitYglfs1Hbgz3VLIK4UP3O6Y5lIij0wp E8gtiltCeGLG0ZUyryr61bsLrcOkpPuIHAxwRoJbHSVpZrZTIVgaExdW6nJClHD3MrEzgLGxJXS3 j4reLK9MLnndhnWk8b22OMVau4vZjRwzSGOahI6ymn8tgduYfCsEOmBF9nIAAVpZkQaoWJ32xnuB m1tFUjak0tjpUWPcMeu5e9gVMXzlaKW1Hin+r3T93gti70LA0uGB4h1C1QtbXNimCam5qr66DGB4 otGZ7yJMGgIuh83nXzmLKitiE2b6M8iOqBDOW6iKnsg0WCfNcB8DlJNz/j9EHCJSqJ1dUIeBdkPu ccmJY9ckWHw6oVjMxAbRWo7pZVMuuW9M6EmZmDzsB4E2AoClf5vPtNrGlaDI57IBJsla6ofypUAE OzKbFzAZ3dXVptQ9r3956RQ7+pMb3snUy/yRbVjZr3AKuIjjw7AS5nV+CzyqkCzDJcZDtIfdLRHx +/f2YnWzN7QSymUI9lNpg1J+f4PQhDzYKOpsU+UfklUGc6+SbfjKewl7EihqOJDRtcC5TdA8s/sB g4fQGKTWUOd/ZYCK4T+REv9Ubq2tZQ6pB0qGnxIXeicuVFFAVggRezS4becBgsac93piOd5h4uLN yqXLFEtFfLXaEK2jXS3ufG0xHArFyYdiibuEbp1pO/dyqwGeXjV341iOjEbrkvOanoYa4x0Wlsm/ 4PFX66L8odc1OYDjeOqOvsja0mgihx8WQmOTR2mV9xPhdQnytY2wNEobZamDcp4WFD0rk5bdcFTo EdO9DJadnBdb4ST1hiduz78iS4crGTZBPkM8/oqjmtelyalgwrDYa1UB+k7ElRe/arhTCu/ghbbK QHKTS3tjGgrBbm+rbOb98gtN+PqIUsEx3rQZ09AAUbNATrVP19d0+YJlzOSUbMrrOAdEuAesXOJA wjFSWddvD4ZQOFT3RtDHZ2EgE74tZZqXpmLKSakwGnXK61qegRYhvYT/TjcyRdKSFrieGsx5epCn ik9AcaLl/MdVsHY3KnU6G0dDAXgEmnVBB1dzQUHmKqd87mxB5SNWbJuM9qx77tPpOrmFOSXrquM3 x6hs11SjEbIZYZ/e80dJKHxEiMlnpyL2j2teH+/2Tu1qU4CpRQB4sbg4elvB7bb8H3eNYBNdWna2 FXlIlvzYtrPS60Vv7Yn+hx9hXs4vrnZnMPx8GaN2dvuLDxAD08Z48QCwxwAkuvIHpVMJRYG4H//J VpvZsg/FQUCqNR8ACRRjJzG+vJshl8vpdpgDGsI+0KElstQd4ELfxubTxo8FaWiM0LzGUA0zy1pu nlk+xtyFSbhi8tCtBlAxexP2/yTqu9rm/Xra0do0Wir8FL22Pwr+HbBeXJZR+KjRvkxjsv9F4T1i B9EvAPWOIGc2v5ECH0VvA1Ms6eJ8p+n2/pxoiwWCHDlLKb0vN9MR1b6k6/K+7vbjmLDv8I4ExS/e r7HXKl0X/sKGv9nGgvaNQRAxic+BAY892iSYgS9xfaerp91sNBEOw4hJfnxbjbO/zBGurqyBMswf deQsHAJlAHYFWS8ZAXfhFDyC8iizBwkzrCU76e+6vtyFqThafMtJR2MexFnXSAYJ7zfljZjOqw4h ZobyuHK0hP2ORwZ6NyJV2CBxN1uE/wG7SRBJjA5q069ohRGoR0dxelNgTqp2gBqVPQV3G8JwLFdd m6o55Lvig2j7pdhPTJerUVlel/D5ofg141D1ye5bEtF/ij1UN9tzd2WFLCq684CoqggoaW/KZAjT WxI/rUrXQez0hy0LQj07r/jxvB0MnwFL7F3SO8R7tKI6otR8zxTD+n6bW2hqtay3j8P25uhX+q7e XDrqYhsF8DUXacRD3ggPKDSKpMI/unOElEPC2NTt8zms1NAOfrntQJt1h1c24VQv9wFHk2mG7QXv CZqYmUQ+Utw/KTS3lKLWKwwp5PrsePqAGHuIRaD3l8EnOvYwrrZaNZXwzNJ2s0PmBKRPHOFxVWcJ XJmxF7o2Yxj+8b/TrbWXZNznTE/DvyMm4u00+gPs6JIivMIo1x0LCB7Jxo+zwWQcWAIdd4M/Ds7Z J4aHi93oOlSI9p/YF+Qg6CcBtwsHe21cD/JQ6rZQaw/N+AfSXXpq1AxkmnxVY9K8NatsEnfgGQkz a50d7cn+QJmhiue1MsROjeZolQItrhtEyIymvzt4OFBwa4r4ci9C2rNiodqgYZk1AUZabVylZN86 voGroK82//NaPxcicjQoVcgl19vthtmreEFZRELqxQ0t8jhq4KxvQUt+StHPVY2F7pnzrlmKLKdR XfSqVWvfOBsqPZRw9xgiLL+vXpYm3Z3BqJAaBVuDQCEDHC15sdeD+NexBww+9pynKo3ZGF6eU9uh 3Da9omF22O0jIbk8hko+forLlXohXiRSNKEK/MsL34WoY06qui8Uq88pKRUo7T9PfkZaeEkFcUlq wNQiI1ueU6VHKPA4vUYi5zBfBujXi9+eSIHh3RlWJ6Yf3ZfAQ5Ovzodkm9B0z+VnokwoB4HTRJKh zEvLR6DMZoKYxJQhMEg6sJsKXVq0i25oOaKwDyBCeKoNNMSnLlt05PGy9FrhIWLrvJZqIunKkEi1 MP4sUYql7Q9nf5UFG2DpSZrycYLvfwM/WcJHFuXwKsrTKpbovGrpcBn7rRSPujVAVkuLn4Zn/+YQ 6LHK3+Lyf7u4iO58OgwLOjoD8EGT8KdsVm2ihGqdQJtM7ZHLrMdN1gJmkWEhranh1VMzff95qDug DD0oyZOR1EUgkFjR3SlsUUMcjGqz/qxYte2HjupdH9h3FrVKaTTZKT5f+HLaS3cReK2+HrF05k8/ yIZAmSLgn8eSk9OKaZWUpeoZ1K5T2EphzHp7J1aPJqr+rnsr0QChEgZPW9Sjq7nxlQYXDtAfX334 g9qtsGY33jRHAW54dpIvwAe4gO9hoscqWFNSskDQhVKv1MtdVY9hvMDTZenLL2S4rHr0udNqicLS fUBQMcbvZp+ulSIE7NCy9KDGQ6joTuo/JT3HmlPKQsUo8QwJ5wItr12ZzplVfTaj95hlLCgcR8Xd D1cbpAeu1YnlcyBfHrKGFjFSjoNkCGyj8tgJt4o/T0eHrlYquDzi6Byn2cWw5Wjxq4WJxb9hIc5O YKecqoXkzL72gA/do6tXDe7A4BhsYscDVIlxL51iQ+cl19Di0tiHwS8EUbsPBGl8WTZn3LYARTfJ R+uUoFs3V/qhCRbVyMrl11Sy/lQuqbvsQ/ZoxeqRSHsVUiVnD2UmRAffpACkpjfYoIczTNuvcncN 55fiYBnp056qCflGklqCKzzi2I7nF8LCbNfpD2GxIyV+9DZGQS1ZffxLE2pqJW7r6oszt6mLvLS3 sN/DrrIzgKNVqd0RpkbtLDeoCDkx8dpEoC5FaI7zyfJ95/bWkhFpcWxMqlblLIbeJv+SxP3JScni vUcS7YxwrKC+/rKObvtmcODvYujmhXTqKcuSF7J2HYHz90mX4ycBipGVJuDEEMJ1NWk1jVtta7hc E2tpOTsVCrIiHEIVlCJHtWfNdJkMQIVTkKGPot+GVRLyMGXJfoqReedWZs5Z7qoODvkunUMbYgvA lp0npHIBpG1fpn0Dou9iAPmaZFxSuHcrPRaIDlJZvVGjhO601wcmqvsVi7syXjfgB7x5ndFiG/rG NLPll63JW/EGbDucGsEr1jS+IFt3I7GIzzuIeI5tcibqpw4fd6lXN9QoZm9IYokvTGPapnBGbNKj u3+zt200G/36mtY0XLgLaZpLbF71MENw53Z8NxbmmKJw2+BMBHLtwlgsDAGrJ0wTmJeLxS5mNzRT 8qTMpuSHskXbSjPNfYNAf+wkVdFcwFH3Nf9SVWlmVqVOH7h7oUmM2k980VgOWQdKBc0kC6tgNPtL S0FAnfThNZGZWXC0BBmfAZ0vZ72uhobt4VP+lBGJcpmKusNwPhqMWWQ9zJPJCZFUXDHgWnhpZg7m bwc0D8FpV+UCJ3PGotzrLb2IepfHDH5ch5UH1pjYSdHS04Fsn1yVSJf8kfn7J9h6TzDNxROvPQ0c 9bAKy12tft3Vz1pkJKXwb0iCRfW1hjZzu7IeEuXJYj6W/LSEkAf9GnpnN+mnzZk40ibyk04NDall Ac0Gy/GDDzngzXVSdSAKZTbGfm6u6Uj8KjkTS6rjjOc+PBgFmuEp5EihBOOGadPnIRC5MkInUv/9 knovttHPuZh7qjP+Ss0NU7pIvhpvoF1jb63F86Xg4w5ZGWHc0Pwix5Jo5n/fZ+ARLsapHkpE6hod KIB5suFAAVJAVb4KkBbGp6LPuCEwE/pyH2IHDPWrh1E7LubyaEBIjXp19FMQ3Bib1yuJEONrjfu4 VXtO8gzvjuENTi7ZFE2kZtdtNNnD05IyXR1381yULnAZ/c8k2A87RWGDS2N3QTbbCwnpk/Es6EbK bmwDmBQiJE69UKHifLMXs/jbUv75A4OvLwPdI2sEjpBKLnh6tQolGiuzYX+cEFakIubggdKBTARv JmkfcLkDeUblLd3YbMCwowHZUp4oPvLTFGk88mTscMtfKaKtYhbV8mJ6O1jGdkWHXzqZNXGsb5oA WRGl3J9nA4ErY0yB+nkhOph8ieQbRn+bu46l7mwzPPNPUZkk4B34zJ1aoiCtwsDyOAD5ioRy4Hjo fogM8RD0c5XRZSQWwn3qv3cGP14ky6Eaes+DIO1mX35wLy2ldHyiT1hjoiQASsKlwOIAe1sVZ3cj tAHt+flLRoju/Pai7RVC4mru6Iue6V9FG6IHhTeKeF9bLU+V77vQdHMFy1cEOUD2Lyz/4G2sG0Vz lFzU5CJYdxLxhlgynb7lPv2koF9+3SPGLhqa5PEqsgedVS9TF9nIYkHXLKcKooEV0t+E8HpdMr70 r5ontxt8hOuP97mqMlBzLmCE097M7fSWjwRQz2vr+yubM1RE+xL6I46d2R89rHZHy2qczvPgzhCQ 1EbdHnj5OgnrERy+etSt0khwRVd/iVXA3ZbAZyyLLSLOtnJNibkl3W2epvR92pPcFgfCUozb/jkv 7WgfAaZtvHZO1Y+1GRN6k+ZIr40Q3m9UmsmCmmRNDFp6Kmq3dMKcNJQ+/ZYT6aoPb/EQmGVrVQaQ QUxK9KP9Fk7v0ICuvsIeWqdjsXWrpqqe6UL7JVQFm+UTgf1TpXZzHc6/isYC7BuMdOySkpN7v6Qb GzJ7Pu/NcB7Q4vUpGgCf1CY66wbZnkfnh0v2XiqU7Igu8+H1FfZ66e7QC46GIxGCBGsamAckLdK8 fbg1bE+OosQrJ/6UAtQ5UCe21Sk+UmgJu2hXBcm5yXURlTQGako+GRoUu88tJ+WtyHibzuuxNkXR xsNgOP/iER/Pzhp34GHWT36tuAzYD16Hk+UVUmW/qIJS8TfKAU164S3FQbxTp8HNnsXGzORKYeyV JyObU3nutW/OK+RNa9mzYgjHhDP6rYP20Kco2V6NIvkiJtB3XsOnhSUzfDEXSeOm9mDtaGvf24Hp yS1MvUjESi8lw/e09SM2GzltQ0tnpM/Pc/VVhIqfQ49ibaoM1o4br9ULRq+Ell3o8OSfX7WesbDQ kWDcVkebdwTPhxQi0DDrc3iK4QKkCDATr6l/dVTqsYnc8U/Au4O8E3b4AUn6hKcp3JZA4jqwtWjR AJgtJTTHLofrAoJigs1hIZuaFZcRxtRAoUlK4DbjsxOxSxO5O22T8CInP+1u0izgj56xkPhmY6S0 NpT+cfIxtou16kmy6MEUqyIRjHA1rAfziHWX83YNLssYpOy50flxwYg5Gsahldy2bSgwDUhzphrO PHtAX0M4tYRNt5ZTwlBh+t4Z5VrLlcL9O+1dUjL1IEVE9VJw3aNGSYLkdklqXLCUsBOdnYUoYmzz WUSCNowjTVS+8cEP+te6E81+QvQUIEi4udXeL0MqkCzHiwbnLAxDCz3YCgincP/3doUkbChNdWhN 6iO6XGyVRW2bFbzqfyKmUeSw0spbU8N4ejhNdpeaQuxUYc+V2JpL66A8P1NVH6lQsBX8JRUDR4Tv ELItiXU48OMB9ysHjJ8HmvuEVB1BU3qKWOCRgx6QUKCIl4OdhFKE2QaoBRRqU/zik+YM+8y/7ON9 6xyrCT39xU2EzGAUYjkAXrfqa+a1vEiFtJcsYt7MHN2G+//CEMCBwAt+2ssV/zbh5HImDpi/ZE0l huniV78e5kJym2Iz+PJFZ/CXiSwezEdvohA6II3Np3XuAclVMCw2SR1YfySomiSxwoziBXyupp3v QQlNHVK6hMSWhx7rNhDzsjASyldwXiIZzN8l5+oxOuwKLVIuYJKts4xzmTt3drv9raUzCwPxItNG AXOUjgy9PB0NYMCYKGQTpq7ZqWP6+W0MRU/CSNiCxMozsaabfetdlxx5ursNXPIJpkndLW8ziSQn jpStoEkTOFiEO8Meljz2F4dmhfbtb9rPwpPiPv4ACmY8B3Hyv3kQJXF4Dd0d2JAGq6Ez0eOUnQEC 0jO3gkpNjarnp7fGIJ+S2WcQnxoMBJoUNyYsO623ZrNXIpj8LEjAyG9baGpGjTCiZ12mUT2eBZX3 MIHXuZLfTLPazd0r8ukSTYPQyFeMdrP3pmES3sA73oMfPYpF7r1aP4dFMFSmFUpcdYZjJpZicYQY rEkobeCMNlH74qFWsy3auUToJPYOtNj05oryXC+ag+2A/M1JYN1WltG70OnbtFazEKNuF9bw5pQN 6SFH9J1aTV8JEbn6C92wB0F3iE8j6yIT9hzrCQQxaZe4Zf7T3tuUhlobDktpOcTIWi94kNjGLhS9 Uad+gRaoKpn2AJ3eEs2+HgfB+brV7x/+w/DXJaM0deprihTDLBr12OwvsH1FRaR89arTmadHaPg4 fEzA9aDrDSu3td44L4supEoeCLqptKv38IBITJReonAvK0FWQ2hQ1qfSGGBkmGi8j3qfaU7y/Xrq t7xOHbrkAyPzcvf8RwTAbFDgpMLkj/0FVoU3CWg8sptG3hnFXA7nbRHXFqBxJVbE/z9F9m8jhG3g tjdA7tBOWwwQ5HQM6OZD3DLYghLWnPZmF9KWLCiFfU1nes3imIHJ2GmvORiMXCHYd2rzUtWhV3V3 N8kIpPucWb+ZSCZwNxT/rvd/l8hI1i4eSioW8QoeIW/Ts3sf+jSqomI2N43paaNFeP4WQBR4dcM9 ydOk3/7zeBIptIbkTZGu/pM4O4GkOaX1OerGFtNoXC1H2PwrJq4h5PrfsGuZYm6NK03Ush7+B6Ea YA5Jx7CGLpWWaaClUiqySV4QJFWAlZQtAsH4Oy4SXQaijXXqUWFr1Ziol4Bqcz88ogmTVrg9CUD2 c6uC3OPE0jb7nbIpVWZzsh3+Wp/2L1XcNfcqrgkIPQfkwUtwsnyNgtk1F1vBL/MQppMBT1gV+aHn vEFsKmWOFxFFNyAQyl58dqksBjAqmmhP5N7NYP0BsF0qADTahwqtpWDBkqHdjSCesb8qCjl5lp7/ sTil4upnfC7jvBIE4bZm6zIKwdo7fBQukOJUr8FBi6tnti7ecCj+fF6+KhzBaHWDqGLGpDPjyT2q jWs6o0fJkgFULE2w+NNeTEaFeRBVEhg3M6Yu73n2xHFlNfIW9a0JOUYicHPLkit4hhWtBU0tkfog l1sOM+KItXqFSXKiIjKpWIvouaUy6TTh2OV0Fuy2JYFPzUmk42YA9FnXszCEzJCXOLtzJVWt3dlR IfCuFf3kw9vgxJXDs6Mp2LehMuptIf5aja03tdP1MQcObsZdPS+RunolDp6e8OF3XqnNYW0mnEMP PLdTTk0wsGB8eXUf5V6gaG7TyCCOyh4OYDFQKM3Yd7T5Tcv/PTNhGT02KekK8xqYvVhj+b+zxASg 2Bso5N2zkwybURfwmLGVZQHeYWoiuK1sketc3Q1/MwD+r2xEt5sCrI3VJMQN3R/X+WHPOrxPqEG5 fOk0Ssj1qm63qXJBB9J5TbPZ4pfWOzKZT61j3I9yijxpb1Jb2Kz5GlYWwypSagpTcAmXKFiYuA59 0Jpu+mLGRVDiHpm0FmBSmQVPCIpiRWUoeVLXvzUwEXU2GmA6pjuqH0g7ZdRRpWAmyZOJCDYewPnv jZaXLZgUNnjJId34pIux3M6MZVrJaBgUyqrfU7QGVGdngN6eBV6pi4wannSfukCRpYmD5BxGCIaC N5wzrzJIA33jV/3Y+85YDIhYZRWYjrIXMoeU82H530KyjQ3wnKVSQ5mYdNI2wxrV/Sw2WFTrtywH J/qPJXnqNyclHvkZn0XNtHDfuWWqNoMHGREYpW8ZeAvlqnXAodR8pRLcVF063OxjcE2YCb+gX3kM E4UtoN9hTeC7DvJmghMIhZ/zK+ScpUSqJiK8T+RbGhco8Q61LyOHnG4TnjA+xAYO6J9Gzs24b6Lp rHbj2siyxzwdZjFxcJj3CrRh5074GFrfkVP0BgvR2opaUL6Ukq112JFGYHd0osST9DcpkBbNpVXa AafGDVoMvjrqh+J6cOJQfcVNBX+0Ekce1t+kI5n3XHez6emiNaJvZGKT2XVV5jSsyTuIBjfufJPK 3rfwaQV2UzKOOXepreFY924Q6yYYNB5YYI4tjK3Pm+tqa7fbH6zY6lX5ozr6p1TAeEFNuYTZTxSK rHYvOmR10gOtS1CnJnDYn1lY1jJzX646OBBeu2F2sST4Z/qUQtE1ecYo61AnQfSsDdkiGF/3Sxj4 Aeedn/Wa+HZ8kscdFqFvJ2dNQzIIkiygTXZFBMVapSA57/0oMAB14ONf1Ovv1nMABLGmUlI4Z+qB 0Ry74s8obIvYS2SgMGNzmHpP7e/07lAXyiq/HnjIxY0VnzZgDHn9fPga1c3rI23XZDfmr3lD/YzS tw8gtVawXRziau6ZP8d5vbfdykq1AtrVcn1K4oaTdT+/7Hn+u4hrAzM+Yw5SqF/QL91NRfQ2VmgT meAc5Xn6jBvOMw8VHH7HZe2j5knbTKzY4uC3yYswBcqtjLnkUJR/W9QqP8yBRDqVWMU/Vo40ra99 eO+caZ0s6iTRodrgoZ3i1H9U12rYCtI2XEvO5eYWkrKFS2CiR3oWE8/2jAhQ5KNOM4DX4x6iAgDA vu+u9os8JCyZ3FcKB15fxQVsye7/nQn/DsnXt5JYP6cNNzduqGW3v+c83zeWohmzJmweqGJD3anx vPdK5i7LGCA8OyGnLQTnYIJn+LRDXpX91XVmXlflegyb5m8WQs/lmCRpo+GTT4+eLSoDIF9ShpVJ Hc0FKvxBDtDXYMBHfkZU4sbgYAUZv0rvza7qypSZCyo5qKWQJiAnGC/Wi49ShtsrxgchC03xeYV5 wt2auXD13jjVroU1tW3AjRd68RHpFpynu0H/Ye1GVofB5LMpPTRCGbwT+geDVZKpP3mdvyK9khDq FZS5HHfaGmYPIrQccwdQg4+WfjUpe/s1x4tU15BepVWKR5Wol19LOY9urUFsDhitzZIFp/s+GmSn m2h0NPFj77t+bCoifrZnF72S2ND/nMjYq++7fq8UWcsxrv3cg19Ju6+k/4GC7O6eDfhUdc/HfCwV VeBmKAVCM97z7OJzWZJgr58VGaISsmdZ0JKvAavrJ9IvuovUyIqQ134eXvQX35cestSQBBs1UvoY W+CY/hNIh98L9b+W9y9MAS7kFmNRwx3MS/o9yWNNMC0YN3VAHCSOZ9Aek6PIvW86r2kdgTMH9e3c 6OPiZDr5Oxj2IY6AXnqBxObUNF3pfWCYgYbSz7usJbvAYGi3LpL4yGFu+91mrWbf+rkXM6cvliDm bqmjnw8+IhfHMnSDnqfVZ9EGWDuF/iVM0VtROyuikmbwNqKBSuQSj+9MiMbD4oAVzQrPPVST3qVC pETK1SST+dB4VGFSAsH9TRt0ahQI+WKKaKjl4+87A5fBSjxOwf+vkxBovMRmD5leznVu8vOOO3To 9CTHvvQqBdWYM5L5LcIAB/FCQjOGPgLvEGUAvvKhJo0tBdihkVSZxd8BEoKoBumNH0b0gd2rRTWh c+WG9YF2by3tMCfcFDwlDSKlDOzYVkKPxnIROb1H/sodkv5exDpNHfhfMY91XPxByMtzrcvOMWii 6EloBKncz5PNC4Q4kGzxMdGelJXQ0PDh8IquSlMRun2JNzGc9xYeQcteruulDND6Ixn55gsEvshQ tk9BubPpgH8Thy6ONMsC3PWz1xn9pYrtIE3mPuE8gHC7cx4zMhLu9GicLV9a/pyNnF4DQXsSx8K+ TN97blzQgIRCS3Y1RCYkFvs2cwBxqG1KjNTCpTVEy/h6k5iqzzkxOw8wRJfMWcM5lrdiKJ4IJggb iq+D0Zy0h79ynmvutyfFGlUqPFE/DNigeX0YYm6Y5mTgAwTFCKLFI92xyiGbdYqfs2uOUMBNyXUB RjAFnTF2yliIoq/vcLLzBK0p5k0vZ+tgQkXM4iykNS4/AJDOR5FlD+yjb5Q6+RMq5OaidDu1QAmy AiZvGfDsK/hNI+ZoDG26IQs9hg2X47dibLn2ZXLkiSibIWnmxtielcsQOwQCf/A4neaN3yfkE7oY UqIBW5X0Nz4m06fkJf8KY+ZgXejHIckr+lQeSSNWu2KjQzqAYH1+D55kaVL6HhTI5l/UqgdXjHkP Zk6gG+ZcHfkw8lQW/PSTtuTQYKf6bWy6df1p+KLeG5tYuI7pxED6pZv8gHKHXGnnWX3GXh8IVf9F Z++xeABy2x8Vt3i/b/4mOoNCYpVLIBRDtyN8p15x2/qztW1q/tUHB8U7XN9P/ghMhXnOZ/QvkXjQ ekSK+SX/tTOvOgGL/4BJHnoicKCgsd3odNUi+zpgOMWcHpgVmjszv4S9xcsCxlAiqqtvJ63ZoxXm SObfO1J1tNAdxSosLIAbtsGVtqadhoup+AEwqXu24b+Mi2E3S2ZzoUomtcQQHTsfV9pxvDuUX0gl cwfp4a0OID24LqOG5XuWb/wKsnIG5xUJSXHffmuasCRqwrXUCiRwBLtPZ7zBPNNlyPEdhAgumBVZ 744Gdv7wTalgbnXZfn+/tNTCyDu0GBOfCFjMerRxRl3Q7TEbYVazGN2LJD3chrrwl+/L1Ps34qA/ gfnjomr1Ku4uw0CK9PVNQIAHSFXyEwIIkZuiht45gNUVFPYnkWgdAu27j+Nvd+Xwu/iu4um2nX1X 6nbRHomv1lRH9bnccv7wuAyhs0wjMxuDPYjc2qH2LUP3nlFFnky5uLpQzZcDRwOgjNP6JR+BBOep OERpG+9rGF5CDcJh62O2csr1ko7KW06M+1IXbyfFjLfP6y2sDZoA0sYHysgnoK0IJg4DHcIcxHzM 1m3pGhfaNIsj2hNdl7FFZ73Nv+VISl/gCtRTtL1dwclwF5dOwcNrRxzvpjr7cszU/cTWP3iJuQS6 LTGXMvVKeyRbP+DYkB7tFLG6tN6hvtYaDhZwKrX0chR+gTM7c7u36QkebseJogrmxr7Ij8C6Bvrl 4i3VYC75ozq3ruV9YbiVeVDG75myrfRJXDS+27xe8fUfxuhvXV59sHjx3i8pj5MLRMmHkkDd7wc2 hY1kUpAPRc/lw7YpAHJpsXNg2GqFofQzAg2ITo55qvDgtdvoPW24XnIzM2fmRb9bGOmgViAeW3hh 1bhslXmMT6uUY5y3iSdIjXN72EiWvTEirLBaiU7tcJ9GTKXonn8KbeJPuEp+8sIN2t8a0vj/qWMp yTSW60eCT2A6GEyOJITh73oqyTyUpd8cBz3bjpiRzr8P8cH9e/AhyxZVHVx2Ew8rGSxRTGaAai5c yp112oZJo6pmsgQNNyjWlAefqn9E8NWfOvn4bchHxaSvDllnlWzgfW8XVdJCVjebfe7MgVM7WOjZ xllswN1/T13Fz8yFKFriBWMUWuqsICJSLbfAURhuUpd7Kcw2L54wqqflJM40i/LFzQqlnPD5DZQQ VRQbx7M39e1DeS9HxgiOh9gkkRLt0DkyR9toMjttwwgQnGsjEJzfQjk6lRnfJe+x2BVeuaMAYw7n 7Gk0oNqa9ejHj7sZkTJkiPJWKVNOUm+Opdbi8Z2EUKDVOviukXEengtV1T19w6//A33W22BdqfG+ oKXFdNivVlUoQfRKyUSl1kjb69tYql4+RlFpSExsBaBiBd82hETEvrsb1cxOAp2Wiq9GqtL6CHNx KqW2PYOi5jxrEsdGRQkNFOaVZZ5o5I0k382zxnXT3iU/SmB7CfsJVPs+XDzOi8k1DB2+p+FIaCQm prZn+EitmVuB9U+FLQ4bR45vyAR3j3kO5LdDvdn2i1erJyCEetd71cRbxNahPw8f7gVKj4JzFaSZ 46y1JIs4MSgn4beQIo7N67tfjKkon8xPXKmmOAWmT0iNS35vN7k2S7lC4eUFy5sijWtmHuXyHfSL EqDpt3aY2OjaUaDgbqyvT22bP7zGErUxuaGm5yO0gPd/QVISc8zY5ZQOYeBU/HIPFoAgKBvhqxbG 5b34lCP1Xp5oey0JYYSx2kjITubPLX2yGUF8P8W8YZA1qyJ2f4n8IhpZ3O+hgmHOn6lo3/sn7ABn y2P2m1JAAyB5fOoJ2c08mUkS/zMVzfP4IPBGuQroMDQ2mo5GX2/RWcpf3dwxDnWYjT42S373k9Vc AhJWQ72WgctxGr95fQhpfyRrvGPKUsb69j0lkaZJD3/GSuj98TJSNnAWBP6Hn5TKFJNynGvnGywG bcDSPpvo85u1WwKSeBgiL9r3+YqFu7e8UdTUcfHSgqO++z8S28gpJbISgabOCRoVA4MBBNBXCsbs 0G2C1f+rFUCsxBHQWT4fscgF44CWb4reXmsG8aKx47mxo5iPgjn/Eo4ARK+Qz60sTQEz3oD2uIcu rihDylUtGPcpvDe0KaokXnjXYAqaqQFsBt+FfAned4T5ndkQK7YDYNN17G/SBAvyic5nVHRjzCPb 9XeKv6oqk5qj2kV0IzPSHMwqXemZCzHj3g/pW2t/GkPXZ8++Pv1bI/SD9ENV/3/IdDnQduzwO/at Z3QjMjc4v1NGbcInP7lxf7M8SFN1GsDzs1ChZCKd8sd/Le1blCL1Ml6QhfJd1HE4IcBWzzWkOROL 2XlhYmd2a9BCEhn+pCHQUDDqBsOLhHlF9ZaadgIn8GrwQCxnE41C1b7ZjSoHcrw2O4hwq8KgFk+c 6oZcYUqbjpkgE4QDxzYuAhMtv+4pwUtqnjbW9GYea/OvYuvO79ukM8KtoSUiXw7iPLIC9NGMlloQ y8aan5h3GLinSPlxkU/5s86ixUZaYhrr4ABf+/P0eTV8poowa7SrczCR/tKgjYBdneWK1Y7gUvaU vKFJ7+bWkmttgYllTc1G9gRDQGBXHWyUHiwEHfliaCve60La/4Uy3ycTA22APnNPTp26QFnqr/Cd qyxPB97Yy2Ra4oNuNry9+TddvCwFSMbLSSN2xDCw3kqtGjNpJOHLks9U5bMwPuaO88yJ2h6ZmltY eSQIE9TuAcSgqgq14A3eODUTgcduzHWsw14ptBmrASLg4ySSxoYjhngD6p+YB42CDrY80CBgyoFp mzdsWS41+B35ovrGYzFavVvjBwcNyU5Lmh7e/v2qHOSmq+f51siER4O+hN4u7mYx+FmQc1YBMD1E vxe5vm6mA9/vAZvqtOGdhrvYcfiEOH3pJF+SI5NSbSXj34vX8gCV+xFF3FYKTfbIeVZy038bkUDv u/WvWqWRMuWyAXz3Rpo6qvLFMSwuKpOM01uyoh9ii+sX59xgscqVQ5UWTGQfZ34NUodnLa8e8v9P 5YnZFaMNwgiuliF3rTs9Li9NLJ3MNsiHuVVs8VPnsoMuroTuH76ciGi+5LSl3AbQZp3hVkUYCeDT J64Qm1PS7Z2ZeOLRB0h/HCNRgu3z7amn2xG/vIif992DZm2lSF5C1A814GCMWkNu8fW1huuZDOE6 WKSDye258G/VQlcm7Cn49jYii7yBDhHyzkFKwrmJl9gsJx0L75gmMTItWMp9KX/HyY2cNnDdEWyQ xlouGV3pWiMuGxzxTPKkdsWuxL7kg1pSLQOzlOKMeH3gAaNypcZB6k8L54fwLN6+ThvADgGklv4U q1he9MsDDolkilIUqCYNmeaGdjo+zHMyMRg2/fvYoKaSXzCGy1wg7if5r4JYDwHoknHyMQ9z66Ue maTRAOBsDtd1+5IHzUCJt0f/iELLeT/5dPZrCAzazfgXqsBuq+uyRU8B2YXF1vlrNm6MqSqQWhmG NXQSSe2ul3MNlG3A+eIQOvvy2ivY1CvdG8VM5bfpXS5VyCPuw7hfKTpT/UquUfGARuTvl2UJ72Xx 62jeJ5hr2nMqtIVtFArpNRmu2udhX0W5Z2xQ5CSvPxcW2LSJmWp6aU6osCv/ceerG63pMCg3jmbb JYwHsyMV5CmhF4kVoMRh484Sod/8alNAnGKIShJjlhAe1UaaME9/0oAXnwu8/3Eg82xI8lO1sfA9 EeK8A4qmd6G2zFTniVkpYOQjdgm8hDJhj7I4vcaz0CIE3Ur8wJ+lR45NFia6gfNZMT/QuZVvEwga U+w8laDxy9HIqLNFMIyy7NsaB3mugHx8q4SwXzmcHk2b2LsoV4KMabNlHLJZkfmQOufEO7RsIrBq gxRkTqOipgwRH9SKilBS+gwD3cBYHGx1o8n+gGqtHkLcylpT24WHqkjbYFq5eEzrJuug2xrcbruw sX8Tk4rAOgAVmNketiZpo2nQimf4ESsRdTFzDXNedtX1OUgaYy8rmonuUhlNkexkQFf1NkQCeTNy cmMvb6zr5SMJkacFKqy3PlDA+bXzjnncO6ABH9TpeTXS9iFYjzF9fofrfSOijhUOZ2YnkSfBG9bf KwBINuwE8yvKv4vHgAL0YBSCyo7pPZglvB30GBsa9l7JOstBHqmJKMG5jFi3DdOO+eknR0Yu4zEr 5MgamzVKnwYBp7Baqzv7AicefXo9Ha5v/RSLfAMBOaVmkckSmtRGAzQLjPjlx5bZVckxXaVPrOeg waWT8Mp2xtTDlpSjYjnyMM1ucb8A/ttic6kPD3hV4hLqapenNvLmjjBnmHA5BJyyFn7Z9lZ7Q4hw PCbK7oUzPxxgftBQPDHFAPY0cnXRf1GwtCQWNXZui10+IJ0n9gGifcu9s8yqnvLUcShjKvedJvdU 30YgpgUPSyEFxzF+lqA5MXHZGl3hRMisAnW/xrqrHTa3RhDki5owavZDL05TXlbPJ5mQTaXmECwg qY7qPsGpvNa3iQllgBqw4tUvQRNI4UmukKXl3MeZijH8I3QB5hXpbjhZDtHaNPkb/FP2juL+Np/4 HZb3y/GYkXq7HdQ0wrfV3N27KaPg7CxIp9fh5ijp+wTVBj8no225ScZFF/os8dStEjFwv6pO3bug 4EeRA67T199BfSrBw81P91HtM8HFNixap3dyi/eVQsLauP5kQAYfAzabXH9vTgI4HYsm/ndfICrw jxaZtWYqyJ36ajHqmch/Vagx72Tls9JY0RQx7T7hcpab0qkU/QC9Ri1czWPfArCCwuAshNxeGdaD 4S1Y7aWL480eJDYXWrZJEVnr2xBRxe0x9CtCxcAe3/E9RADV5eDh+d3l/B4ccoEyaOFgKBrJfqvp yy0RotPvdBNQC3OFf/GCyewd3b/WEweWY9FEmOedpYpKgkRehIoe0ktqMCFGS2YDF0LI8gzswWb0 wbXZvCzkugezh6TBsnPUQhCAWJZCJSOZEQkbK3Nc6jvk0mQjFgtovZeXnn4XWhVeo0gYg6VwMWGp G+ncc5nTIJ0EBHsfQlb7MQ8qXeU5HS4ueKv1q2MduJudL+MyJG8VW6spip6uYU3M6MnlXCFaR4mN 3N+iZ0F/kaGdgh2xU6wu5C8+8b+xkME40YcKtEJjvHewYhNxFVKz/fKXkZjmoUy1shXr1XOhbxBU +yxor5W+QJl4tD/ovfJkEnCuSybBXKgVB0UGuwPPQQAyIZu7muPPmIkdlTxGQi6paRIPc9fAMX/T 5hcnh6oRPXFOAomNNHg6KNI4cVGZhDLemM72weB8J2Vmfe+GfknJCco19FNPVs5VZAu5YawiLw0Y +ny2Kcq784PasUTbDYdRPf1NSxGbjxsKVTpgeEwBC4fsEejgdZFE1TC/7fgtnfchGKXzXcKGHjmk ct59mQfhyHCY/LuA/XAist7uUNmZEzVirwe/MOVXOx1HPXowE7Xb8YuO9cFWc00gI39/a31T+dJ0 iqu49D+4ZF9pWpQvAjg3yWconXoRNN+PpR4or4LQj8CBn5eRdWcqpCUDYrLOpazcwujleEeuDLOG p9R+Fh/DKvbHXq/lBoIi3yddsNOFDW8JgDR9hLictmNL+L77qnvE7XQmHZmQDD0F0HoUnQfiN/zk 3ZU9jqNtaBgyyFUjp/1Gs+qiHJGZVf8W9h6RfhCai+Ha7+Z0xoIdV1KQjiCq88ulw1TZbMLncAdI xEVrkvAZHFlizym+kM2H0YmHdXk3ZZTIOImLNOvhUFhNCawM4dl0/IyeqVa9zh5kuL4ZxSE/wC/5 zEyUpM61Bec0oymrVKtr29dh4kYHTbjt0PsCZFhseaMrcCNG819ARtGgxUMDdTxvmpD+Y7t9kx8d COE7n3PYqGG0wTryvB2DtJO/RyE+JDHCyMsah/n6LArxIgPrJOl/sLKPAEUzX3Rs0yO4PczR0SQd fwiCIIrIeoDl8GPs/NedI3oc8EawszxJhsatj5P+IlzvXPF4FYRFPXYWeYIfqHOio/BXhZRYK1kj sJuwqP2G7C6wFKM2alrNO0cZxFZ+aB81U/6U8d/geKNjLSMWKXzsIoQaZGzmbFncna1Pp5itcV+7 WeFXlp/eWw5VGNSGjp+hfCeY7ru93Vfr1bC7K/l3hNciZkAosQvhrTnF87EH9macwZ2CEfpqUsjA mDsDuFIO/59kAS0ZL/U3Zo8nBaVPQ/JvJsNvMYVR2HgET7keFnCk+CIeGwdA4CNfGHtmItcJIgPq TLE5/WNiA16Xz95vyx/5hmqm/oyTPDQofuS5DiPCmA/FWD6+mEXQ+l7301/jDQ26pLSrkO8K1g6t wyV1iz49nSn3zf2WFdl2fx9e8w410eyK0NI6csUooxYx8Zv8AWxtTH8VYmUMznCoOPuSDwWjsYcQ iSq7VdxzxeovJq5sausBacO9YdK+RQ7uDHmdBIRBCr/hw2b+BBTUEjT93WwRr20Ytc8w2Ho5bSEB fSuUurrqaEn8p5LBxvQR1LEfXVSt6gDQv9J5RbA9BeuNY/ho52H91ag9cTaad4DLFVSrwiywlHh6 1PlLf/DsEcr2PkzqC/sR5el1uhgwaCky3WCWnwVwyeQ889XL58xhRJxw0YLD/XswZY9uhAds7rWf 7F11R06m1NNNd8X2AMZL/wAw91jtI0kzsRvZhw/4p/5j5UmWtCycc4PLpVBG0OOedklVTy3bbTtj XbrQYZlI5AraGaxbUH3mswcnLDl/AyaguN+xX+n1WzA28K8Vg4QTon6msLuAkn5z20DohMvJMGku JyWarmxJ5GzZiPYifWjF2Ktpb6wlMUC4AeDKKzVztCV8OY4m6SwzKH58Or0yDNmdys4xW22HKn0Y 7GMwf+RaUiWoTdX/IsbRJf+mq2I0pnPruH+KH63ZBAHRziialSJymyb7hzCEsILEEdKc9QfQcZ81 oo/8POTD8Q0I8XBpxGmhl8Pv0i0AmFM3vWClyjGEdVlVYCFQ/KpdgYOLQs/j7VNSkNj5rqnNbhQl hdjV7HxM36e+wEphrSnPRefLkPHcyzeFC3q4xzNrAbvJMMjlkSZuzzkA5eRZ0h72h0/qL/rbtW5c sMIgNEJp5VYi2ffEpULp1PtEUnUeyJYVSRspavXqFaiHIsFmYLj8SfqsyJuF/qdukAUqvQ49ke5N McHL9bQWHJxbSaT9O60rgp8xUPJ47drK+1ZxSkHAuUSRwmxltyiMAWFQxXlg5e6A2YA/eND9WzbC wVc23DkAe0G6qphIw5nUs9J9eHYNPRHODOP6lo4H7r1TY+5gMoegPJeQkgQBkDWccyXdWxT7sCHL DrRkVDrNCiYhvq0qdugdI395Rp0rkz99/0hYBGKrqPJJm/d8fPrrk7Lz/PDcDV7LE7hUlvKQhRo1 12QsYzpkjqTwWH5IV7rpWzqmLMud65Pu6S1Hoty4bJY7rex2HX0lU9yS9z8dBkxtXtY3WYLPcbk8 LlsIfLSJNAEQjuW7y3yPmz0NylmMfB47GA4k8EVYRW75kQKNpF3jiaH3U3oSyItgA2eJaGyFHbhj 4njCeG32LlpLrfyjI+WufVYVPxwXRqwKEEpY9qPKYLp1rw6k7xJMYa3vPAIAsi2eP4Q9v9S2vnBj 6DnO7wgbzXOR2xpHy2EpMudixsTX+YP6RHqWKjPA2qS28/C004eyt6TzKqwkw4aJo9SVQlinRhXR p1WwpMdE2BxCyD9tHAfcw26vMYak+1A9CJLCldf2w33e5ZRUR+LeyFjG8Fq+R19D3I5TLkxqYKi0 Bu/yuG3vTQWgPfOYBMXBp3Ljd0vncxnC5cLnkSplafvxSKmODABqFYg1dFr38HkRS64YUtf+Wpug 5xz/BJnJTCg6X4D648/EjcFO7Aex9vOLCokJKmfI7kQFs0vttFpmmBEiWP9rlisBnnlNQCA4W2kS dJmhFox2CSUaSAL6dvj39goMweOJSYeB0ox1hlDKPuKi6mGmee3U5uM7UcrUS3SUyIUZi6pPohtF bVDDjBQBtAMAoc8m0zr4xxZAUOz5lPVaECbbVz+RWq97Ym9xzU3E4QD3d6zE/TcRpuOIdqNgBN+u vWb1xBJZJo7GHml0YN++VjAdk3LWx7KpNTo1YMNE6yGnypiAYaS75iiZ2GTDd1sX6t2kj8Q9fScH iqF89wL3rcIa1nnkIJyBodwXVyRZWDu5IJvhWZAACjxF+/RsKAXQPZwSPK2lB3Tp25vBS0TV2wCA WF+oLodPpQH5GRV6b7x3Pv3HlsOrsJGSIV1sBnYckJIHdZAYcyOsAZYD8s/gCJEc9Xx3DJiaSErP TM0cioBSmz6aKb0aa0DeFm8Ofzw9NVipEizdV5l8tx/ZGiGdmhfg3mw3JwhTkZ3Fb5znbT7sFdDf xrtXBNskKaLMvAmMs+5bXX7MlvB2ooLwFVM6Duaoqx9LuAe5dghQXs5UD19zRhZi6nVjTJ2NcrAR LWXCalF5NA93hyAXDimbhFOwN+Tc90u5vG1QWRCqCY3rrVHCXL+x7iF45dW14tKy8h+2aonubChk GeMTituL3KMiuBu2XlXLLBFvxtHmIVqfjt+O1CRIsHifUdfS0kR+PNWCrFMtWW0IcICE3DujSWFF Jo9h5YpfDI1Pa2NSaE7kE7PZwWqHEMRMAgaxX181/KxFvVqA3Zg3R8PYkW9n/UNrsUoNXAVCmR74 xVl7xWravivfzwgGUJvTVZfgzQ/B7mkhesGw3hxbrEwerXWr8kaU21/KlnwSiA8u5M/LwcE0XhED z7bi4VquMUXuTZ0KASTlpGOfnCLVvKQXd/tMnfYPm4AAUnA9aQra+a1wxRJr0q1hHhIpZfFdvyX2 LB4Cet5+tC7FfKAY5u31T/DgZv93yEypJKSSRX2KROYdhi0fB45h8y/F1k0e+2kuplAgnPOBrLEf ZyHSmPkQugmMGpEea4x6VUfw/HguacGOGQqJtL4+WWsKeTAUIy8JtYOe1FmYN6kTvMswxQszpqmp piSn8nbZhZOgS0jqnTTPTAvSgSLSySn7/UoaTSDLentIMfXtv8+84E/+aMytaB2Hh3t6ysLW3HbN elUlotkwM7napnalRSdBUe7jC4sC8cCeyZiJJOP6vq0Rn+rKXSUJMf//Kx1w0/q2S1KtfUUxwybU MCUbAdzfUtoTwPUtA0Rz4DlOdZd06M/9HzpDi7TKOWOi5fVPtquy2hxwnDBuIeO1pGn3OHfobS2z /Pmc4lswQvEujWBSvViy8IVPub2U9H4jhIgvJDaI/q6zbLeqo3DjDbEQd7XdsTb6wAfVYxdujo1f MevwOIVwljPetVmHQ2v4lToCBiB8K0/oRubCBiAl4cX3flT6VIbYj8mdO86DDJYtC1Fh91ZW3Mgk kraxZnG7aiFdMn3e1FxrpCcHAXUU2BYrunKFbWGjGuyta60UvOyktOzNgjeVbz5/ZcrP4XuhE7Mp 6/vXB6QFzXO9Xyg995LvdcIEcZRdzHCVNrDtUyzYwq0XhPEpBOewOeZJ6zkILUVu8iC8R0Sd8I/n QMHfeV12VWQyi26n59CR3d4yGMSXl+7Qwvf4GS1j4mAgkfkMfEKjcjmLlZsK/3GYXBHb0duoJLcr uERqD7JvFjAVb6DM2UHAOuQgCfTFtJtT4FK9qZbM4sPrdO+EVBlMSASrbw63gRxV67V8kNTnmEAO /4gHbyXEb7gN7mio/5F2wpocioiCv3iPH6tURb7DJN66cPwHyBNeDGab+O3ytCCnJTiWy260B4fd LLTAfAjmrVwi7hcegraaVj0YPFr8OMzRGYJHm/BpFTWwrhaXLoPNCxGfcy2BpFS7/8BpSPdCaOiN JXxcKH9OF57+mRw7nVzDnMI7wm3D/VGj4Fu47tmHZ2yqdSbDUW2ey7PkpYVz43JGuE0vaSSTWEGc IF22q8YEPqeXnHgC++w7UyjgnZhkIj+6upYRh7p1zKeMTYSISEq3jld0bIDm75IpR7gDuOrTLuQJ QktD7LqiYnIkpWEB/5H3Np0ZxS4tvoTVCHAqB0gMDbtVcP+WWx3nSP9oN9LNcHrURAGYdeX/hzem E/M4sU0d0TMGxCBUPhXd6ZtZ6+hLIjRd0Nld7gS2bTPin+/7lE/KbMndokac1T3hsKJpx3ajhrbf BHYk+atnXj+9HEhEeIxJYBg8zH9uztpkpSUiUip2nNJASHLnRA5DWvXsFykvEEVDBj8gRMc9LS0N Bk4Fe3yMw3ENBTuR6Mnj35J7wxjEuuP1T+iUZV76e+9B8xIw4d8VIYRhhJi8K45kZfcYvzTqYxQX aSj9Uod5xUhffWiromfRwiMERmtg12K7tBCM/2R7dbpAWOt4GVSXYRg+l7K7pizDwgdMPqMg6L8I xgnyP2HAu+ArPZ4fdWzlMsOPQ6flubA83SHEPbYONmYSgb1wT6EcD9qn6D916GCZfje8z3DD37Nz ULPnqYCMEMHJWmAI9mYlhBgzePQhFaMCGrzMm8EfYxAnfLmzBnZMUnMfzfrnzrnGPjl13njEgh1v ddvS4ZilveLBg6UerF8dH7m9/mL7uxih7q4wafmln2Xf2TEjr+hnVzhphbxdsSDxxbA4MYMMZB3S 9MdXw4lEdylFQNAu/HczS0MFVYuITR4KDe0owzVRaX8GdxSaD2r0Umxk0jm450uaTbWQrViMh53u klB7irIP5ONSwYweDOS3HWufralV9gAuQgtqa1myEvTT6pwKYHgsShtlwPC18zygGxDcsdsB1bCc NeP/rY2m4lzQ/jGP+m30bVQdAVDM2kp/LSCylosZz5aFYqEXGVCzQ4zfUHAkv7AcU1URI30nPoAq H8LF2mKIDWwim8fU9BGmdazRz5fgwBrn4/kMmxRbE9kH8MhbZr1w68sl6IQwz6nuletTAFWo+/Qy cOm/U+YurpPqIQ+K4BnSsCY8xyLcuB+zQqkHCI1B0XTj9V8Iu6TMUhSn+30kRnsRcSzK04FNRxkX Azrn6ORnJp3KDICOOWEDmhjfLcH7b1In0MDkQXRM5U5Ds3OSoJh86iwJv26i4qoeFeUy2/pErB6M wj/VWsHdb+Xr9RbhH68SGvAZJSCl6em4kbsX4wMCrzi7vL9zX+1zr2NfLFYMxn4mduamkdU90gWk FKIGg06LvkFBHnaJLtYEQepqP5TM9Jn4IEIU6a4DMObxiba75tla2RESLEbT1ZzrA1GgKD+jZ82F Ae/dMxfsaL7Toojo7FwXgYgwUjRGpOGOvqdwEM6w45o9JTTDp0t/PFOGx8zdfbx9WVZJajt0lqXv GFc/b6o3SkCRV5JHyvaevsVOsv8A2o38gAIVZ91xw9xLN4HBW+6WNWcG0j0FvZw6ygW5AXWdkTqf NsB186QL90Ks7zW5xZsvUktzlZlus4TqzEktnyAklASqWHY13btXj6KoxpgYWvGt+/IY6/bak+Zn 1WQei4lavn7C2AAnJT1EHll6OAfwmVTJhNhOxreyGQTCVNCMXqDpMbeIohiCCJFebuDwjEw++vKJ RE+gsG+no5mZ68ILG7yUxGAYg52bLSV96KlIDeqz1ToNpBVMAZ5lyob06ZdOoYroeUVsdRdznafF JhUkRvdeAoXIeHzKKwW5ayoy2ho1KFfUkWUyamCGkmaj8vZnfXO04nNfFOYWUkYwp7luADwxxs+5 8UlB6Iht2tfH+bwDIXdyG0QeDgmTYkzyFSytF2DyWXG9IYmSDdwRzm92DEQVYuJiBv9ILBVPMS5w 9OJVQaMsB2Lq8dVj8bZfOVszvIWZOCK6LStF2x4PATke5Bazgltn/67ZY5sQdRVAqAxgGQiCF9iJ nqeYS7ntLAALbQWNnfEDj6asTFouPTNkoMb3QfiMy4bWY2vyug9hdY7ZeYkIpMvgH9o/wwHzN4Co HaSg2l6tG5gR7//bv+suqPlrXJG7452Hfk6/MedR0Qg7H9SoCoUVLzNvBOEgYqQpZTpKYdmQMk8J OR5ERjHox/ooCGRA41h4RMOGRZNHmGGnZxGAgGpT6EHOPQXiFnDC2mzEDUD8cm0KsoI8zWxrnjL3 l3NCUrx5e/j3Kpf4Dw1/tncLnyMw67hkNS96D4FrFDLDBnZ07f3ANS69ap57vzhR6kbk7iCELwji tnQe80wO71D5XOahbPicmARzF7tD5bVKAj+bm7/73PRam5EZ2jvpCKRn24iQKKgBS7WL/oXIVSVE HeTOyWpPBBKhJSEveljfmNikHm0PB/SdtKDSexllsa8YJQteloZEbztEDEunQaZAgHfv6kaPl1OM wQ96BZaapaZHT27pvT6T8NnscFgQbVH1FP2iIZ/swmzwBg/X6iPYwgl68O8gHeDsXp/vu9O1mB5N BrLIXcn71Rwz1rrsf8ds0dJYjgvIvflR9P+VMmPAOcAfYQfJxUgCD203LnQB2Bg3/hwsFkH5QFph DIM+G4C9qAZVGMVYMNNxfDV+raJRM50YnXOE7BUz+dKtSQOgCe2Rr2siCpJEgGCcCqw8JnyH+mvu IzVDePVdhWSfCfq9cuUfp+lCfrgGdOL6we3MU0i0/1/0Ov8zXZ9h+ROdMw3lIip6aIIOv4HrqA/M M5vz+XzOzdYhZS/JkVg2Y8CD9/b9TVMuHpznEebgi9p+4yHwNB/lHL80dhQZEqDTTeyGESy3XJJY DMTBb2EVh7kslY+PngWyKvhpF0vDpATx7RNQUII7j0HvkgWkSLKbJxPZWuPvi8bzyURLu06UYjz4 m6FWS5/00cpCPQ/HzDqjq0T7pGcZcukffDgOarpvYnM4CNDK2nS/Xnl4jJkOV1qHzncxwazySA3z DrYMIvwIubc+ur5AwbHzByGOrhQRIL/GsfI+upLAqwavkKI2lAz9fsKzLdtTyVBBCDujAGeJnxJi jkxFWBr+ewTZBxGUuNvvMXoV0Y8qZYafoJcrcWF2N3ghx4zraFJmZVOiGuuUTEjYRvbVS0XKnIQw VTdLZlhVGu9g/+8AV6QDioRQbNNmtM1xTWY0/NE4eQFifiJPrWbT93HSIhvXWFGhQUwv7DiGg/DX hIUvZDxjoK01q6DWpR2KeIZaKnJ6dZuLmlGINyXn6EIU3Wnnrgg2yhQ0+0PssyiV2/XNFkU4Ichh PR6HbZDjjxR6zOCxpGcs3zy0cYvBdInVr49Ew+H2KU1UaQVVXnGw0/iEiNSMVN7mJRvWJp4nGFgP Sk8yScSuyllrZeD2CpsCMEJUssRG6ndRExoumLykOyFN9Yz/8JWlyL7s2bXIi55wVF7Wd60/BUSC c1pDkdAgwJcTTPShKKbUqhmi+1QEz8tdwgtufckFHkz6qslEJupd/CXFK1ZBe+8Qo6yUuazJ9Mg9 VDtAZUJthRJzGsaHN9jUeSw6Y/lNhV5dRBslj9DOGmiAZUTsugCmVzZ/EchltE8SK5MV3xmldrun jWI0od4jzb/x9AnNmHu5rVV5xht90kB9ObR9uaXU/mbH4hNp1BXVRlKN+R9v0XV1mk1y7h4xxYLW Pu7WoJ7MaCR01TAOsciuyr+M9QEAAnIj8AVceVOq797kpBXJZFIXCWFH4MYp9K+WJcBvHIacEvii aNfAxYx3NuSszmMDY1N8Q+kwZ6533g4rbwXuJ9oPZ4Drk+IqhZOau2p6HPdaXuBHQNb67M5dtqiA 4zyVcdQRRWANeZ/9Ia+cvq5xL28dItSVpCa+r0TYHt9aotZscnqSLhQowMWwZ90t+UMdfLQtaTaf C90VASlQZDi4oRF/TeYKergJZKxP3A0aAsMelF/CmJwjT48TaNEdwnfoU8BLGRAGTlpOmFibqcoG gr1+wQLniUFc+uHlkLQ3wUVk69AWZw7mqiP5g9BasXc+clIKdH3FND35eMHq7GvWlJ9OKg1higQs GwWYn6n9VGbmg34TwDBxmUUPMMW1VmwVnVHWb+JUZQY0jdNCZcqyjS+cST0HH9vd7044Zo08C7wo ihq49jt1KPgGNhFf9TLSJu6elto3KB6XBmuBvo4pA9Ngx89WdKPam3wlk6DiohxO0U5nzxYeBLjm E/WKGQE3E22RRCiK2xRkKVR+BnRO+WDIbNj5e3KVKRC2Z97+mYN1wvSF/eLqbNEobCgqo8ypz2y7 2RCUho6UhRSKZWHS1iFQpfTedpM69+qe+VPn6nNOpEIs3NuYk6FD2EIzXblE5mtWqtjB7WokEW1O 675eJsxGxE0aq0pzMP8g03Kys3CzXDR40WBllZJdxZ/tJXJf0l0m4jnypwftoK4Kh3iLJFhSNkbc 10nQIdK4dAWQtDTWRV0P9zEg5O4ECP+YRbdD2uutqpiWbJNuUSnKiQitZ3yxmxpmy7qsPArgqRDP DRkRCqNDWe9ZIqiLRurLuUV5KTYwpSqkZOd1LfKIhFe9WryqmNtvEfaEZ5KQP6z0CgMn2mplvDYX NnZaVacsCy5zD6CUm5KaqrdQ4EMaslJwr8J0D7mM3Vf5n7FJm11yjNbeVEXL7H3sterR39jKZ2Hx TcAi4jW6tJDg48mjI9TWJFaO7NfwIsuxPIYiBe53uaFkppGQBr2OqQx96V/y+4tp0H54qh3J5LV8 vaDiDIWg1jphMWg7lMyh2j90yQEjYPQznZKe99r6y/cduDKJwHgGHwJhJCNOgwEqF8v67euS3/FD BWBildMUJD1wetbQvltp5KrTNTx86elkb8i73SOwxgJN0god+sRckEKlN0Srz8Ma8AaFlTHJA6IV 8ceiy03GNhczNLsa+hC3MzeIfCqSjY07cHU3o/DZ4//aLogwI3leff1MtuvKhl9AH/DHkU9Y6rN2 1YrNDP6Pr/kSIWY2OLe4G17idvbXAC16WPJ8YSNSiY04owg5ItHv/OURuGZDA5q73mVonM53WtB7 53XTTKOItj+r0GNxZKhp4zkW62XLSaKl1UqTp0/vFA4tSZmwp/ATp+dTlzuaeiX14d1JTbrbyOdy 9pRsH0gB7iioE+C8BfUEz+2aIaqpDTQhufMreuApCiVNeyz1Vzsu9ZkKByGutmdWK78LeyP/Tnco t6z1QHxdUDQkaknzc6kib8raJfYcXDCAgyski2wUxnN07WMjyoQXjIT2EVgM8vUkCyhm2apHQQVI /KsRt8YMz72fUbfHOxLyAjJ3qSf64nWu1MaijwZpJXiC17Boe6o79HBlREzL3Sy9MntpJKrDXI2c +O/hLB6h84QsC72TWxECMouPQAhdmQsgeuGIF43EQV5tqhhwl3hNMZUHFQJCt/p16IJCCaEB9Eyc bOFo3c26IVY3E3TkT/8l/eQ5US6TJbJ6jv3ErN19xdWRHcmld6LYgCoI2KgfOdqVcpsEanM2Q46K hh3gjv5XIaLju+3WZry/JIICGXF5eQzzOziM8/cG1p8TEqSM0Oxf+2XaMI1JfRcvRilqlwdDkL2E +z9FkQ4y4/JqZWFQibzOgYOSpqGh8+Tv+/tS8rtMqioKxNbjAdCo23/fq4bqeOckWxuSEW90RDTH XVb3Er3Nl0bOlVny35IfwbCE5YjABof3kKaLqQBQnX71lUSL/pK/v/oWNzqwA+Kmqi2a9cwkTQ0J j1fC9Giv+kqDTKQMov5R3r6sdvnhjx3t6MOmFn9Zi54P1eGgEhHKTvp0AmL0G0kiHQA+5Dsiwkqq oluRYSSI+DIOiqmRFUfdVGqMBqUslSYPkp1tLRpwkWPildFiZOAwEnYwJ7SEjtLX8B9rMMeshrTW F25o7SZBLI2KVysKERDipvWUkYpbAheY9lZxMq3JTLapJmZvAsa8TqvNYMU25mRQ9v5RTGAi3C/k JBk0a2lE2GXRv+XYA+ZajEWDWvJrCDSXqCNX0Plc/8rGPBhyOhXrEKp7ySqKVf20cp8CJa70fLbI 2WwxqzrXNFUQcDkBmUkj4kptA//bMAWiIW5JxwIgEnOTE6TbNM5uO+/yfV+KwDRNgwZspu6f4mUf JE3D5Gz2/H8pgyctb9vfACR+iqDEaBLCTc7VNsR5W2p278kbAI9ZSvAuI+qKfudlqT2lTv8w3gun IBeMfHfOq/5WIE8Gsu5juHnKw+kE0H4gCmo14QF2D2+ZVUG0BFZUUpjbAJFt6uCmqF68hsNJdXP3 vyQBxSAjGr3BtZVOiL7LIHuEyr6J8BUO/neCcntR93I3uGNf1l1ND4Cj9wvOQfxlr50PMvTvr0NQ 9CachvqRmS8v3CMdlw49Boxo+BG+X1HJtcQkpYPDfb44692kdVVUjaYyip9ESkUnT5UGEVkUkAEK aJ+TrGoXRLbbtNnF10amJYaohl2oVvDVsx2jx0EX96mo/lEdJxY7Ko+HIZLFiZMoJOaczK4Tdcty eNbt3m2tw603XNyz//qc+cTM4MFXgcjsX9bDT7CEOTTXWvDFdPp+ZYMCao+eOHlQkLxhU2t53uV7 eferAmwU6Im8Qptd+HaJgt7mqmOsPkvNTEgY9pwffyY8aB+oPD8tctgf5Tr9aVZjiA+2b6wG1y4s CAUB8hTgSA/qikco23s3ANNzdki2zwDv+wPJ1l/C8DFKa982Sv8vP/g2Is0sLRD9pMSgxZJ72hHc AYYWxH5QviRrunGeglE/iaC/15diP6EX0t79jVhVr5nblinyJYflb9PCUbmIQuTWLDmt09kdrRq8 /13aOin5BCeHflMYjUdEXpgu/rDiLWty3q+yvroYohxqaeaR3ysksqyREDsWGI/B4X/Sj6dwPjwv znzjcL4/Jdv2B9ivqLlpNMPITuCehMQCZVtxcH2R2//+kHLOOKqRBS8KaM3l/J0hynd75CmlJUdi GFXsCKWr7Bc0YM2iw0Jo2tGD2phx7deBTA+GmTXO1NsRsoeTLOKJknAVnckvMoYdTlM/s66YNG6K 3Zmi/Orvu8Zr0NauoZ64tF741pIAw1r/jeEs1bhMhT3loQGG94TBk31lzsjepDc+UtJyXx32LQM9 IzfszdyjfJzoHxRNOqOxZO41qBHwIXQukObGvoH6eWKa1+Eoc43p/6nAfxa2BWVvmt8nWt8IOdT3 GiSZYh/S1r8WbtmFd8wF5zglUPAmDajjLrzGblSUFq7FjOkiXZ5Ke0XyGlivwzzH6MfcbMx7PPi2 K9BzSjpXms8QnwdYmYmvH3MPQWSU0b56QkHbLYt+PQ03xkHGmwoDMUbj3zCrev3gWSnT8sFg/PWF Y4BCmPfw2Cz6Xs07a4wwHVnXSAmHgZ98fvAxuKIg1uOr25C2qtMugIk6Xia2eTGSkUUU3aV6wrlH ceavxoN2IxGjtnecwxchGLi5n9HNhHIApjVenbvYJLjtyW9KBaPMqktdZYCGwYJQyD4r8iUxauYb egx/mem5MZxT0nlFA3yKEc1yBeI0NNIcX1IFLVvojIx7enU0fi9BWmgOufEhuDurto7M4wG5ROza 6U7UuBkjCnMvxZYa+pn9BqVE0PhrsMTk9vT/wQ3eKlGT+DhdIL+O2MAneg/DQgEZ8K5lrwJ7srs8 aHJQ+hV1Ly3Cp62SSLeZrWXsxiQFgqcOz0xdrQsLxTUt77udi3eOztFUPfImmWQuqIBaAx/B776/ X0IlgUQq3UXRGCuyJb122xtao/lzOrHblGfLcQHW6p19bs0332TH36dHIrRU+Im2HTRFmVVdDTaD fsgno6m1cZ40bx6mTcdE2rndemKyn2pHnz5KukKNVBJZnaxCexQnSmVnJfALCyN5BRcwQ6gqld6L auRLWaAXSb7RxkMV/fjZChDDZtWJ7TEUQHEdPA1DlOhU28sgFX7155LGTpNQ4GOWKY07EpEU0PdE 2FbQla5msVFERomvaRfHI4HpK4OKXnqBXdp/ZsA1pCJN3brVjbrn4aoPDf9ZgUS8Z2CIHrHMu2qw eORN64V5RHagd3n33x4a3qovQHQRzlY2IwGuMYiO7T9s1v8C5g8JQmAAECcLmqtznzT1A1VEpt0Z EXZRCcm2wBpTNZXzJOkCSpsDD9GHDiwvlWztHjYHlarrXEGQsYaApLyqlS1KhONOhS2gF+8EJAq5 /gppAC5Vc9WA+9SaE+YfV1z2BGfDjGXjmTQz/0GY/l3qj7EKsHZYVeTP2/ABtFlkZ2R+YoNQu+Qf edvDJ6J+dCUZsiXH485mbA2Dlz3uuoDwmRANLJVFINHGxX+KOdj5YMOoqDCdLDZ+hJnbL5HGKK7f qiSJHShkmQEAvyd3rdeAd+j43hHCNsmvmA760RcANzt+CF+Mjp60A2+FPIo5NVWAltk5qz9bxAmq c6DQzHagk0wC8YhAdpDJy4WChNIrGmvivWSPm0p4IVbgTrE+K8v/QTvAu/EjK8fMZ4ylNqzN3Lxg TrDACabFL3KbkhAWsctaGZlQRdGztf7pY4PgIgwxN/ADWMz+bz/cjGJ9nRlyeUg2wAyLCCxynD7Z XPiB9WIx2GnnLfCbt/KLyRLfviUn6xyTlcL5bx8fDjXeo8iBEw7mQzrefJEUDFL1pWMil0iHA13f K9+U7uaBmYnTpN7KN7ETB9iFxwybIhGS9ezIWdOgsCzNpPn/GKxdtIiIz+koVGpz1EUtaWJtljAK jbT/z+XiYZx6yYAoeO938tF5X/CKi2q5S5vRpWAe7V7czAKKvTYc/MRK+XpG3pJ2L3+G6QvKJD5E ZTwHdtlHOH0umexFc/qrbB+2U8Iq6gkP+rgwRsG3g/semp8sFW8kh2WintsCqViXcSODQxfbLPrf JTUsuo0YjhqA8TGNJhRspgKpWa/h+J0bxluAo0LLWjf3fwNU37L96TITS5OH+Mt7HRFLgxAlmwna 4uOXqdmuvrM4jV+mknEMG6CybUPJCFQ0sjH0jjaOtqs54na/ixehFZq5CtkqOJPi9fNYW9x9e6v3 jQaPllc2NRXFwLj51ZLDDU1EDl/ssWA+12QQRlV8neizCMFDkDKjtILzSKxOhvk7vaK9NczkgPiR cdeJ6mSTnf9xl86XlYaVYX9HSsGKaWjJimXjy1IdUeU7r4uZD7xtMK2Lvpw9KlfWnO9jIam7oZS4 k5OC7pSZ9qusM65XjIPF/Glydqk+++wRx9DzvdYBa8BuDsAi1aCP3PPUZhXtCXVXClvRtSVbqzVh IzG2GYbU6T+0rMAazxVjgmjqS5BfgHaVv/NJlJxGQUwgQh7/ktkQpnwXsRl3FThwsfgp6LDfoQR+ Z565+X/B3Pl9/s0l2uOXX5dv72RAJTP0S7/iokUz3vPq1vkDUtNAnDOI/d42yhU9bzXYUpFQe/0d vxBj2Rr5p2l/7RqbWMF6Hnn2TSy5f7qjfV1PxHsuafugLUIdCWMXeAG7vFiTzvbdyM/Tms+2qBKQ Fl7sWhdyvdFHghBCMcUYc9QAqZhjZIPU9T4iVZqgexnrEc+gspAc/LNd0R/hFtU6qd8wXTRm8zKl bu59t+W7qKipyZrIBB5hbesNt22EDEgkbYOsS6/HBSXJWKxP679/SwKHZXr1O0EmO5lgJamOTW0+ vzF2ymuRpzYTZsI46KQghGF6OdDXF5/w+cgPbicVlQaxEuAaRcIm8Sr9tEoOybM4rA4hxg/TZObo xQDPWEFGh101MXZPdrdUbPeY+ZvVaV22ai24BZMH9HZsNLsvoqok7LAIZ6PTUgsFhd9ZYkXvHBOV KbP74kRbD0+/NRCw+SIV1aCxF1qagPtLOshCnyg6ujeL5t8qE8qOd3SPtzA8SU6Z/76Ft897Y42G Upl4JHvluP89d8XCd8RhVnG6Osnub7FaiS6aCRFkr8MZtlHOgTN8fnTHAnQOpyAgDyzAdVxkohhr 8Foy3QstEWB0Jxe+Ztx0qlKRzFIRcdoTHLudrlS5WTos0Qi6P6eOT+WRU6fA3l3NpavnYai3/OP4 wkdJ/SkhbY+M/qjtZ2fRAin+DLUIrb+O9UvjTKSqP+SvsEv/7Mt94KFGtisOoa+fa6DvHxG6HTsk R7M+XcEFNC3Jl+3htipkEmOkoi2WAjZGycyXuJXsm4RydNmtMBfJe0gqbSnRLoqsbCsEMxSKNdYZ BF8xwgVANSlWYY0qV8J9f2C+ggA1hUxp8M5D55h/Kqxh/H0HUBYMV7N2u+WpaJZNB4xl/DFijLjG luBwNHyF0iQ/o6Jg6IUFVFPBcBVoxAFT4/tIlBk6S7Ns0y/1lD2sOamavhCT8vRkk0JLeF7aAFTH bx7b+DGGgW9N3TOMKLKn/BdNVkke9Zx0npaRvG5vlEatIBQK7yqDL2BZf9HtVcan4xSKIk6/xvPO itvA79JhpkOXm9UDgylirEv1HLJVa6XEAaovikqIAytFBeVtCX5TDOD5z0LW+HwFMGY8gFE2TVHE 2WDk2kxHjCWCik6Ey1TgefhsMCuvY4fP6xZxxyZlJBSlG+3ePKONgWXh+Cz8SEZsTep5qwE3CxcT cZ8UXKlizEfBowumJnJ8q6t6291vGNRiNeinYbRUPfmRxi2JgQyWtGlaZgqUS4a7Rh2F7sukI+EU hlL/P3sz3SbWOQv3h0MHik09hW7593jUiyf33gZ9/Ygy2LReROFBqK3yiI7XRiP+6XFkdN+/MpgY VBgtZDiDrH9bU+IxBBgJwKwzWfjK2yDTi2mxqRfAML68F/qd+B/HSkkuF1OOp1373a4W6A6odd34 4Q44SPHJrTbB2wlS2tt14r/7bvt1Jblk5GBNjHY2I7/Oi9hbZEo5KBo5S0jpu2DJQnbeIoGPr+ol 0j7RtRfic29Y1MLxl2UMT/3e3mK8Xxof9a/KqjApg9KTabGiBchAPzAe0+231VZBL74YaN4u0JeZ bNbzFb/4FlTKXTc1ZWwXKFUJQwyOoQK+u9HWpFZkc/NGNZelhtfQVvMhTLio/y0bU+fKqlnVwH2M HkUDQiYn/d2gM1XNXe7lXDVHJwMadWnJxsyd8so8C4f0YoXFiUr5m6n8Lgll8PHnvIA8iMJqugrl hNuApVDS2FVesemfWfd8xXY3ANub+TfMOm5EoFBxtOgdp9kqD6tzUqZBCsBspsA/Oj/weqtCR/3f WiK/G6tcbwWyZbK8cA/uvI6yUf6lepTxvtsmRZf9nLndqtf0E/j1Y2SSuBa1Ba/umZTuIHfBJhOq 5CzEUXML7FNcCuJO8tMSRoiuS4KFKnvafFpc0+TSGdh4ch8ltvniQV8jf4m6R7Ns+eTzY/7iauO1 SoIx7yFWQccYHK/kiW3Zc5aQRLMmHrTIeVqV2FoShuadqyRxRwb80Abck5YEiiSAdoy2UNdlKEYW ek30HikJJkopa5IjoiaIjkfrNZMJUK8pgtHqpx+IVIzb3kPnjANaRLWlbr+SYKxEpL/IzbzVaL8N HnjZUXiMyaJEGw8xKWw1Sr348gTNKSqxrC0F3QgppmW8TVg6dKbov7HLln/iN/EYSIwNY8ptjyyj Kb5qopYFd6OSHBhn+jgzpBJBXo0mOU6JrAhCS5UJCm9KVhDa5rcLwSMt/beqbHbSzdhj5Va/kcuS GIQOr/x51qlYmQTI/v4klLPrTaLvGRzU9lpdEgVht+K1gpmUHIrXuo5Wd6b5Z8N4OZ3M4FDaUz+L dOyUSH2I9zx1vg0zvhC38Ov/MFrXAopx5ghMYWj56GCCiwLX1Zia62nVzcQN420hrc2a5KPTU48y IVcYViBvJXzbSldh7WbxsyexRSrSbJ06K/dMpuuhFbGbEaJWxZtcOlx92y9/l8oz6UFgcF0VYwZA e+t8+hKSabxtkUffCEV7v+0t86Zsqh9rEUcTT9ewzpjacHjkJ1ovQGZ/y2sSbm68JPw+Br0Wm2nq DTIfZoq/wpUdFl3aLN1QbF5HPvhwFKnwG3ublc+fcZ6fPs1coPaCkaIaGAUZ/ZuHpdHLsHK6aNMt J/oy020WnpdcxAtidBpDPSf17yx2/2ewhofk9IJfep/vZOAfE/SwwRkQHjQmTTpfKv7pyPte82fm 4YrRNVW2+P8wZsVDbP3LtQb19UPJOvpw93kJ0U70H6pWmbyGkr9xNwMQ3cQQD/fCnyxnEv49c6br 1z5JB94DET92rkPady5RZAEyi11xD9v8gzdcoW/z/aYpTRrPYlDc39pdQ5BqTuy5B3rN3i48q+uv Uv2hj6mGtKiVodhEh2whhEBZXeWnYIAfmfwjLb5JgDaTAM9Y0O8xfZJXS1hO8Y+K8IVUaIrDHVeO pmPR3FU1PIjXvqs0W0EoBA67GB2Aop9V159mAZTJrC20dVZyuY4PdwjQ73i3K37b8hAiLE9ITq/s oKPDu2k12Jah4FDpJ41hSdWi3bxsOyOIKVcvokuuIHcxTZ+7tPyCzEB4VVnRyHahcOIX9+bk8G5+ GQHP1MPy/x/zg7HbaNo4o4NBEckYBvjFkEy1McW+s0mVsT3kFFaixjk0lA/qVqkZvfi74u5IFyyf /zMgP1s+DpRs/RJk3i1wU8NXqbAsw1scY7DerCJjbkSUzPFnZzuxCndyHog7B3tSigb0yI8mLFZe n8HD9xkq5KaAeenE+0GYmusJm9fQU4P2I/F9HPKiCGtJUIzZC3rDj+/OJKIS8bqY6msRwtC1AeIG j/ZhLEqeL0GkA7+DPndShggHfMRCb7+D2WTp0NtkTTgl27q0XEPcz9txQyeR1/pvddxHRm1FkkQM LNG9BqOqItHI/ApkdFJp1oQ7NG0ppQApfnf54miP5juIdMdwtd9LyChC5tLD2jz5QG/5jyASLoo/ odnSVLwO0kPZFM+c18NpEZ91rGqB4OWlOhtQ4OO2E2CNADPVZUbhqhHPvGjGgyxeAs3Ss1+my32o Hf5+dD1yHIUF8q1xgr0jODGrbur9NinA/CEwb400y7FEwra20mQNmHVZ0yUEZQEjGpt6kfSyKEU/ UAZd7BAf6bhZKAQuH/PRGii4wnHDNAUjclSrZGaUArvMPhj02ezic+RDGHbd5HrV5ulXV7B/Okpc 7X5y2IJDpQSKympHCDROwT89QNvKTdxBR4SSjUndH4sVQzYTaNMtGhTU3BR9DdQgQ0LTHd01CpCQ m/f1KfzARUN9kx+2GygctdQ5otjXnzUG+aiFBLS6hX8Glxlz/rmFvaUVuiliMir//iFTQ83glgxv cad/rQyn4aH6zQCD7022W56Pz/7wb5cyvNiaPorbhpuG7fiK2dOKDEL1k5nSVB7hB06Uh+h0WqW7 SQF98+Zg2DRcSIRoPE0FBuDmqkzZP3j8c5tR940iIBeyHWMa80rnNya649p1nBNi5PrP/GZ4L7Iq BthlUPFLZ+lkTgOQnH9loI9sVjWlD5mte9BPnCPkAUX6Pl+1MVHo/SyKfmq8U+A4LdsA97846j2Q UlUSRgDXczb/lGLOOFa74ZtlVXanH4iXC0Ry4IiYB9egBXrROurH1bxgoxo0/TEk2lmM38fCgLRN nZzcCXI2H91ZddxYttEEh5l16oWY/r55vE3+LICL/nxtcxln0M8HLf5Ipkknd8BC3QSMIe/PLV1P m1OKmxN4vUHKtszZMbY30vK4z0OicJVRb/fKmGQLXQA49HMjKIa3b5le+YlbZkWTuwu9IYPb2yAy rM95vnrJ2vgzufWFnxnXXLY2Is3KS/xQ1QXZU1G2iGqWWOeA0HzncwzipzsnsNOjqFipD6uG06R3 Vkr7euACW37eIWzkGTR0bYDvNxyqvYvVMKj6VkZS7U5lZizfyIcJXA0vGXbPkDgY16UtWikJRVcj oG4FCGwtJxCngpOQ3mzpoaRt6V6IYwKvcaJIOcn8FWmjTUXQU21Of8tMD5tP9C7yBigVl9NYTbmK wFLE22gqvSoQ5dKqDhY4QY6s/mDFjIlfODiv/JxydHY5s5X5mh9KZ6x5iTklwsy1r3TeHKZ8jy+G PZnVY0ScZot27CuUYGXp0klrp39Ek0+UFsix24jFYqpfbg2WLmvn8fPm31VAhW/bWwvMJpVDAZaI MdfHbpcg1G72OxxC+kBhANYXzQ5pH1LLldamONSOufH8lk+dexyjYqSoDH2RS+o/nXhxoUgMLuaY 1EaJxBzcd6VcPGaHn99H5ofsk1w6qBh454SZubklW3knUF2y5MW+FkZlNdPZ+GrfJ/eyJpLrWl2T /S4MuaPshZDdqG4pU+Z1UKdcfhOD0VCU4IGC/RoN3me81SpvEUAuyOWIbgTDaFsShjgqJ+8Jnb5a u34GE4r3suCTMW8Wtuwwb+uaEgvpy4MNFRctgiVh9qak+QQAqnQxcrABp5pLpF/ySNo9sXywFLMb A7slMmQILpXlGOiWEdsRIBs/nctH9gxn40f2GrmHuJ2KYVxRY8+1qJodRyagzAyR0RCvb42yyRvl C85avld2HR/ZJYHAPwkWbA5oKlfHDpu5lGdnZUAw50PAHnPz0wFHuOHJLNJDHAA8VFzNDK/U+dv8 sFk3xoZiH8v3d8CAod1HBWnrdHVxTuL8vXAsLBY7VuVfmj9MCoL7PzvVghH7V7yx9YohOQi+SM8l A5r2EYs8PfC417OLij1dVvTFgsVbJmInRQp/5fPa2QAfttXpy15IdSTgd00wVdSPK5gWP8l9z4nh dPNwlHvOsWXLRatW85QEjxXEy8m9xWXTQhxKDBOZwDT2gXEIj1nf+kf+tb7oL8eOWTazgZfYaYTu Hf2nXt/Txd8hEqqldlbrK/YcUbOGEnjGBl8Mfi+hljX7V5AIEPFtLFWAeCQrQrOfrn9+qw4PzJbq LYfKluEG/VhH4ZwUrnlzgdPJlxTFFeAQWZGhr5LaAs7EbsC6KxfqOMewb7rUF/A8ltQq2cAUZIqa CF+y1sZui3gdijPPXdpBKc6le2H8Gg6gPVVGIqvUmyqE5Ui7PI1AKy4IVNNI6N3XW4K/tW5TxHwE QsKdR3Vl6F65LrGOEPwm0zv5JV3ROJLTNsaKy4v8IRpxPkux33BO6MUwryqlSX/lrsY/Fxv8e3qF +hVfF0C1AahqvLxOl6yVCbSl6vI1sWuKFn2nHEzATmiiKsjUoX5JD27WTpS9D6Kg3aLcoVnpNXir otgcIgsImMWp8dM/xjCPX7dpYXlbZuMXQJvPxTAGQ3b+4OSYb7ygTb04xAXMfFwG0F0Y6iDZlnHI UYrjrP2pU19kBCIVl8pHcHi0PHXmRUtqk2Yri7sOgAiTQRu8Zs/dgbynXMOsK/YiJhRIdDFeecL5 3cctvQYQfqSs2TSJ3V76LRLDF4kAuPnYGTRnSOYxmav+DhDC3LGtTUBQgE9WJSHz7OoePwLFjI6l U+A7wViCDk3dUVJXT2GXFLIpDS3GQKDMSV4Hdd2cn0Jrkgp92w0SUaTrhRw7mZ69r/vFifRKVk9z FlsyX3rqbvwUNDdJ32Nfzza6AvsbTBC/KWNl44XvQSrpqAmvNBI3EEbdZ/ZppUi2GBE13PWRaKT7 aiObgJqIluz9i9gw2pEEgDIGu6lqaOpUN/aWbJrGYP3KlDFNor1xMz+1T1kT9imc2FmfSWdAXsje faAR0ZMG5tjTfM28cnhUrk59NdLQln1qhCX3uyEGrANQx8gGyC/Cu7OzppxVPILUDFuDVrHf/JYa VAw3KBJmD2up8Yvt5MhtdzxeN9vkVmFxMrA/EkcoK2TonPUOU2178hoKLZNYS+qNtrP0ux+ZmbYH PKrgPQcOqpnGai7mCaTOTDyM134JjvkFGLYf+Me/1Pe5d1Bo0FfYjamsBEpBWOr0+8yCPrb+PHHU gvpzDZoNN558NG79LbHUJw+6N37Yt0YUtrUvACqnwe/MqGz3761vpscV25fxI4Wf+kKjC3mX1xxd 3S7UbdVBVrFZSn4v10GQ3NuCqpEepHrbqt68KZlup6TM4zprp6ZuCA6HKf0GgrhV5L0bl8WA9EtV XpfGh6L/v0DvIZN9TZASf1jEoUBBH7Vmx0guHeCdJGRMYRVxbT33IY1tT5csaEtt4idY0Zlu0bjI 7XQ5xnvDr9aEl3y5VTfkWdw++BZ9OUaFKXd91rbDCEIOLlJDjwwVvzSj0DueGnSdWkKTbrK5jfLR 1qzhdygMM/WiOJXzDvyC0N2XcZtVT1KBgubTGNGQDYHv1D1fdQi8QKqaibTkN1bmOJ7NvESPbGtb lLvNyq/Xdji3Bl/1DEx81JoG3XixMPAkVTXZzAdNugo2eDd3a0X71kS4L0AnoCV5B+CHOU4F+8FV ee445O5adBYnvTQYRVDGyAjo8wLbk2Jw4hjGliUkfodTL9w2ltnF6z4sg2j9Qlqf2VuIJqdZarMU FW9Royjy+/35RtDkVW6Hk+6y+g9ZXy0S3kHWt8dzNLHkpl0/lrd1D56DQ+onMq2hQVKqZc2CBQ2L qDftfl+klflm5PCyjofE0OFpYwt5Mer1OLtFCZx/wwZXIeRN/+B0zNYNtFJ6wcdV2lZjUz4LJTs7 KHzDxfP8RNYqh7AURTIy2ZtWhiW0MU/HLUnHeZMFnoQAi+bMG9P5xc/8RED3Z2XQgW105WpgI1CT y+BRdHI8Fmgy2MdUGX1K98Q/52/Hp0cYSspzyIYjDxhRNfPtnQF46CinFOdHUi2Rjn45ixKND6fo dG5SK1vg9ekjo3faOclh+zacNzXUvRV5cB1uRBjN9QPk+rmDteD2arv7rUJ/JAQuZDkvWSIBNDN0 IvSL7p71XCSK0vzbHlruvK5SKFdvOqtikFQvfiJ1aw/llHIAjWw4qn+QHaNmFvPHzNGFawrcepDE KcV3ROshriIvt9bRCqs2kgOCbcZh11FKrxdDr72nYQwtbEv50tqNlH0MpadhmnXdhXvskbI8Ogkt CYMFWyqvhwTm+VdrAq0lCwd3vY0yzVIhC+7AKgJmKhoFgoMx++EkjseDSp6LQsl2NiOsnkb95tWi DwhYiR6fEm+Xu3F5R2hg1hjPho3QO6KbpBcsMIgJccQnaJdIAAUEbswqCKeoc02SwmHEgpgRwp0T dO2qokYRuFzvwObkUQYDvTQJ20wvXrjlL8UfOuYILntLbPMPxYfH7xxYDEybrqxzHzxLOK13+/5i ieZNmGefVLWng7RBs3jQoY3KtePR8LENkUZqbB3GbJqbnuSdmvpxF6f/K5SeLRbM/v0Xwz4w4F62 pnX/iYAYSxl8oPN00FbM05rOFw9v7igVCdmv4iLnDHZobPPK0b8AYGzEYBT7HNhba3wrPYumaKcL urwGNdt7raGUKyZDvBKrx1siTjJzHIctMDQEkhlp/RxGeqtx/acM3YBDR2663FqRPupapvhsnKpR /HLRi+E0DADOZOKoAop6Lmsm5x6xAm9ppo6DLdkTNW9IVhVzTdnUyc1AK2aLjoNo/gdK9xo4rDt3 T0rFNxo3SvHs1HUdHxpqxJObNSAABs2hnLPoG7LlKpgwEi5pyx+SCt7LUyhtHzacMFBDQfnDAI7Z lJhisbNGgjWGv/Kk7ynicI+bwsTzoNnkJjM50FAqyFuc2K/gI8FHI4b1kmWsidy+9WDVYNexnJn4 D0RuVujCizZ1R2lkCm3deSIlRen1msigvydjJ82cUkrkCf21UiOtbCSsw8GYCbev+DbSYLdW6SZR +3nZIMayWMgMkGC9Zat/a4enjQihvWO4aUGN3EpnVPJuH81eH0C89tv03F1Dt5thV96pAzHJSTl3 lvRf6PUWjeUogO1QEIrMmxR0U4zGFp4q7tAHa+BOznFr1EmTh/TtlcCu4MxTWX37hYqUYvghdn2l nvLkD/eM1GHtUO3AsBm4pHKP9Ubn5kHpwwuR23Ec5jJFzTBraxR0HtVIR+29sjCMvv0U/yoJxzOZ g9F8BoWg6/DTB34hN5YQH/IU8EcH6M3rPjcLtRvz0nNVozIMx0fVnZ21bGACxAZrQ5Gc77hg4HMT 1fzxNKg9u0X+UFDk9OWOHQY0WPLiCCK+K1sGYrDQtZxhi2SkVas4wRx7Zt6XRFqvd+lF1JjBkMQV f14SeX5BLzuGWVcn1dchyt4o/sF/g3DViQJEltx+W+bMURKBQllOTfHZY3ISs+4RiPAcnQwNwgGC ObiaEcmAImlGEyo7oRZbeZyJLhxx7TLtip4odL/yyBdMxO2qH92dElPuWoeDMCyVRQuvYnBaUUj4 DJa3ub2FUO6hhgO89Q/1iE0M0VQ4Bz+q62VqFTGZ9aBXlay7WPlJS83BeHvrWbwcXNKTEF/XdUTl YuIWo6YbGO3cYv2E8evWrwcsNNEwVI0DZ8E4pSMU6ko81VXve7bi5bLKQ5ZI5/oJfRkG5HXWr1hM 9rVEPaoTp/GmxMMIsQuiLzC+zET5fUgIAvesmEamwQFJdgMusR8ZPoEQ/PCTk/ScV6At5NivZsbu IRQmcVJBRZJSnZHI8EWhaOeg87NDxp49UbPZdbReC6oxuA0DoeO49/EV7bQIvd6CSW1k72VluELz mF4OGMV0vN0OOs/d3j1S8xVJRq9Tjopd57XWQS6pC3LST0cJbnbApN/+UBva6bJE59z1PziAe9ms ysWTenK9xtKCF+AYwOliB+TLaeAOaacrYJWSqiEsR2RtbjhdyFVXBADlmHY3beQ6D179GPK/4q/P svI+BxKXEWQn091ADfDYJXtWPkfJmHJnLkhRnGgFPjaUGIbhDmTrUbX6s7D6OpVTz2iACMudn3od BErqRUU05NL0wjtWVOVNEjcH+udoTxNDbCmgNsG4odkuF8/irpi6M+n30ItQ7HH7Si7MmiWzjHN4 aVvq8rIBZw74R2yYdFNBo2E13MUsWyN0MLPcPak8/IdGKDJ/5OStMWUGf3YyVm5zK49PDQXEBC3N pUcDjoWIbkNZrWEKnjKE3QgdBTbzHopnCG8V0+u+2uO5F6RzwWTM/AT6VgHlx1DVCO+/aq0u1Y8x j+uafnwGi3QYFQMaNknikaitTmhfXa7vH73j2UeiRjEE3kBRyvXLlrxlm8NjowxqnLeF6zZsV3P0 BSTxwzRMSDsl1VJVTH/j+01SU1Q/VolKPubX+DZWL0C09GSX7Orv49gqGnqCYExJhgB8rpCbav/g WAGcNcu38I3t1xSEWx9eNVxgzQQXArTRcoMcV1J+EXjbQP7LOiU/3rJBfxSCaVX1BusXTWXK+2Ho bJcdQa0dhmJOMAso0eqhzb/3it8zgN2kwMx7jzkEpsSyXr/2+QOdqIOfLY1iE7+tkq8Wr5+M1v5e MHal+qAROCswQU79oPPv4MQDIrapgJwCczgtb9EGiKIkDqm95eadDhl5pVf5sUVd+JuY5QN9+oTH GOSbCamsgsuPbVr5HubO2UgrOQkdthBGrZD3EXWqI0E68SgLP5OOvuOe40EXcO4sajyMJRgmhrWd 3O2yPHtusbWnGqNXBiAmOUEFisdSgGaMW95zKUkUwSuNqIubJlWgxtZFfDUNcMhKSQb85A2I9fP6 uTWuN4xeR/BcL/p4CbWfSsI+/5w+NRt/suJUVDlda9FDKh8rXnnrkT8RpOxuRNgkCW+wrluAt1wj tnsq4liAp4OfszLiUZLsmwibMsBBe/nfKTHVUwgejYj6h1eUMLiXGJ+cxzMFTsuXA7EG04VnGY0y iKVubsuda5BY1ub6JFl1nzc5g3ljyC8hohR3KVEe5mZdGr4YQX5zpGJlGXHmCO62JfeXYs9PE8dz KPDpCo/57QOnI5qzZ6ibYE3mEaKtIplS9Wi/HHTu7yhBPCMcsljDPy3CeQktqxmQonYdLcIlgUmF 1GI0iCLxQobJQ7B6SEGjF07kVGRMM7nCOJUKmMLoaxQQIdUt3eTsD0zftf0cfp2wFT7qYsGaviHx VdsUjiHgOtG4+vKslbWRiC0kn2mVE289fyS+mOjUnH43Nz8ijDbNblbmUZnVmLomygpDc3AJ6ifB 2S6b+evJCGXVFRBWQZwqJCyUcCPDIVsDfdcrDqupjlFx+/rv0pHupLZ3CbLOp7Xl5+dJ6Zq1OHzU Rp2X1ZXWkLDW9iGqP6gk3adTooeOG8ZrLe0Dd6MaPLZZoPpBfYCel2/ymIvcdwPkDhauRyWOrFHz JRH+j4m5kGxlwnLmU5pK5/sxpsJAArFAKP3oFrzK1h65Iq6HkXuj0HHFV/3FxIe/VzE8hojjsBC1 z1zKQLseVc0Nh66GQ7JdOS6fwPmPVGWrFEKCe063KqiP6jTJ4QWyyFn20j1qmYtbi88ggEWlOBJ3 M8W4qPGhlWKBAXTA6h8PQJxaNfZBgLRWir06cnnx35OjXJYsXD7A5GmqZmSTjs5y0gFDBKCIgP9U 6U9kjX9EivPYEKztaAjw0PcPuZb9FWYmoS+ZaMbjMs8eBlm2++pOT5ZKq7CI/cXz8JcLA5CTyKlT VB4iPJSPOuYJtDHrXzT0NR6lenoDeh6VWj7gJ/yEzUWn/6+lG00CyzBEm8mzeKX7qMiSNTAFGw69 7hM/zKe+TbmMVVq3BQ4V9wGH497XRbL9MUZJaGZ3w7WTEmEHJJnJuS3ESJm9EFmiyH1EYvWMgX1p g0umI48VhaRaIu1bYHkS1mK57N94sayHPAZ7/fH0wMX/9zdQu2rPTo5joxoP54VDW9TkiCeUwkxE NvvP7MGQsjErBmx+9o6ziQ/RJFI3nQU5rOXNPxj7Kk2oOH0qzYkeZot3xAQUJLeZHcBOFuJf657e Oda+gD0MM+96Y/dWkxb4n7DPBClNVwoZSHvCVS/DA9cC7y0XZ0XO88wh0AryTanJsSbAAHTB8Ugm DMzHezHQQXAQ6SBUyOwM3DkMiMaz0/NqV2Uy/+FHK5wc+3hOJlc4lC0ojmgltofl7a78cuAzgEgc SFFAqseGg4Eq+nrLwcYrguqE8z344lR27ldX7iQPXc+/1KBHyjbmSn4pRtryePNePlf87TDx8pl9 yb4gCuPJLDRnxF5k4Zd4ooB1nJj8Q9Le02z+1r8KxM3RSwJIxg2l/kTThe2/EDwpe0MBwfwCBf6v WrGlA7Y9VlxkvEugBvMXjfB4xmAp5f5EbjtB8TKGl8jfObbv/UDjsdIU/jSKWwDShr1HhqmXLWjs gbWX3Tyl5/P3vh397fF9m50jTaDOmSnleFDKTIOf2cu2+uKBPRlZD+iRf48qnF0eb68JjxfXZAB3 f7jp68YCtO13pz8O+ZyDlXaenZG8fowoqccvH+7uro59n/zwHurQyHCzHOe7dJ9Ex0GxILAppI2U gWSzZddJ/1fm5luko4S5knZYRNRZOMDCDosnEgMj8j+7bd3GSYPMJ3o46woOlnbd/l8KLazoa8bQ o2a1oqfjck3uMVs3Pzn5gRxldjiqG/Wy16HCSg92LHdToKIAa+B1Oisbeht/b5D8aPAYrIQUd2W5 qyclNQqlmy23fONoBl4eVEh+3uTnpFiLkaOZL9BTyKPsU7N4Gs0KHTp9ecrqbJlMeQvYgEdOLXbn suEUk7hJaAxtGcrOqmGWUR312bphazp4C5eOeH1ZRdDvoYJFV8HY+M+bsS9efQjzsi36Pzlj9gbi jA9D9F1e4c/oK6JA6JZkbDeIynw66FLMeIrGcBN8qpfyFg6XVPlYt4lFU7KlnSFZGgLkDAp+axr6 ISpWrIc7vcpin4kGyXxC9nE8Vvmf5GGt2jmye5QMYxfDDTkX3qe/bExn7ZvMr/nDC7wPlWC+VgV9 Bg5doNW/Umj2yIBEmpQ/eylOan8mTAW+5OJ6ilWiZOJ1slg1kG5WCvYG0nqmVVtwZKNu96W23Vnz iQ0NjJRegweU0G4IITkY7jyZfnruCAM1FUUNBuSgRoDy6LZpOwoByKbzJqMa7o+JpHqkS1YdCuU0 ljeI4xtfldXdExwRnMhHhJRZnhymmoM9BA//wE8lH/0pk44u17zMSZb2kRrkP9PTsG2Hs1xDAPGQ e852fPWbpmaBTe1sgLkHKtTxLuXsWUS9Vbb/ujt6t0RBqfTVBCFKgh2KJnMp3DUVMwZJ3h2hlrzT imGKQ0SSPsQhV78pFghswrxF4ddj2SfGMeBAiICr9LYpBUheLcRha8NRF/bQeJ5rvqHSoKUaHOgi nqoqDNo+vXtQXd3uNYlbsMAhHTkxt13MpMtMulIM+N8eFQzkzbMa7bRharfa7tKkZtdBUN+vTBSP qVPcaDoTKa11D7JNGO80JKA0+8zNIJXt5N7DN59cry3M7LiNSmSKQI9GyF5EKlQf4p4/YrTR1szL jDL8jML0Oa4MRoUWBsFUSIDJiAMTvaBkUiSOs4FXq+PZaANcBMdRyQCXmi5TkRqlYmlioYb7an7H Q6+T4tGhBrMDNmE3+0OgLtD+Z015QMp7BQ/w7VdgiydF5gDNbEBznYJ3efl7sKLcHbYiHbW0AUfb tGnBEQ9aTO4WAjWiz8EBF2vVdPW87bBMdczMF6VRiuZ+aJ6uxv14xusyIPwZn1heI1dWD8B+9j7x vpQpMQLUtmKgaqkNK3fo6I9QI2CbaQEoVR/mhXzqPpKk5BMOzzrHJHyBagQNKDjww0CqOULZmgjH ZgiFI9oXfC6XlFGQWo4+UNSpKNvwczinuMWcZunHlgeMjEypxmr8STDk993zPgNpgnjzaa2kibE6 2otW4oxiYtTGVIBno1rkWNaI/8L61uwrBPGj33QAJlJlyWSTKozR8zAaxfHjn0bxzthAsYDIgUYX BWLmfYHe7BZYVF7XtYfRyTPKv3r16y2yskJ8aE33utPH6RhL5K6icmPJwE8rmMXuTXZA3uNNS2xk dKpNz0zuj5SR+ZaUIHdMDeUC/J6WS4v55r2Xw30dWRKeWvV94gzTPw6YyYhiWhW83H3r4KxXwlYN uZ+8HaoGGeKY8vsYlgQoBiXyMcaWjp7yukBUrHIbf5BhLkae+oGWOv0jOeHgJHUp//pGt+dl/vk6 vokRljvZBtI5nEiGo5Tnafnx7mI5viQZEl9jvgGjgznjcX+EjmqKluvNbMEQA0ZTfCN1lJHpmQ07 BPRBLXQr94mZ2pryEyxKfpFzxQasOfK0HzZUUrkf0iJ63SxHZT3GntVakkU77kffpL0nEqVsXcDN 4lRODmjfIUDTSbFqFuX3N5iNqab+LCO3S7aWQsp1A29DLFWKSC/GUcVNPRvx2O1/2xv5/GQQdNq/ LTBqNad1QKlYMlvDeX1J8OIRCKTSR4Y3dKlWnyA8DUONwDARQQRdvCl58jdW7eqvfJ2OaQapuLQu MSHylwIXLEE4ah/D0ARBmSveuUlVA+q75+CStKV9V/A1niWjy8+Fp7wnMyzYZVt3h87tLEINutnp 82rxO9k16NIPFwaD8lc9khLbI2GaB8kG2dpDS7Q2GPJwjYUKACsqxp/KhoapwEYuLnjwglf9k0jp hFUXbCJnphfrr1CBCim3l4NKcH2s5Lis3oxmzuMHYJwG1Tgyl+ttNuzohgeiqrlajknBM/h9jMKX lajSKq1ZaZVV3ndj59AYAST9LEZ0WzYKgecsmLeqpRV2o1Le4FRR+RIP5KbhEg1bShohY6+pf1cr DvFel1oRu8WQzBU5vonSdwyCQabdSv6G0va5Fi12EPEPLVuLziqkysYezlARzDiPwYw2t+pkDPTE TfZrnu3rKyLRXWuckep0AOMnrB3a0H4V5mJ/Wza+2bq/FKpO+c3rG27ClxDX1LQe9HcgOJMQlY2Y O2ICDFlQzK7AdmXh4XF3ORvSqUb5TE7QU/IVKl/oPPTqHBkwGBJ5YdtPzG7OdTrYI6Tcil/x1J0p oqrWqC4Xcl8C8Plt5jL4v2qP/0di7kVYg0UdPK2IFGIpMlTQro7pHK1EAmysHxT29CFbk/3rwDAF 15TB17Q3/g2Gz/eHZbP1LxeIb5RWYjeMeh+ytUUS3q0e4xCKC1J0ACe2A3DvJZEYGlIkUKrDLxFB OcdX2vo1dC4mIIlA4upom1msOuJ0ESMs2Sm4lEFVLI14hf7t/mgLQ4FTNco8IeqeIYzVTzipAQPU DqacJsnHuLPCXXBJZTVi6OwMnnTqT0Rq05Dj4u81MnFWgdarebKgipp9o1/AfJCdzXUPA4t53tTv Dk66MMu9fKWhMfpxSxiqSv57nLEY2faQvGICnOHCAcdJni4Xw70at2LdX+vf+OTVhRYV1TQFzG6n CCALWQjk0IbtQDOFezIWGB5/00Frrw1foRWayylwm0E46NjdC9N3HTx3Pz3pXIkUYiVLACyxcled DI7I/kS+FnXO27Png3vjXduztxQgvG+AYAU2Gn3czf++m2s63jHhg3DmiNr/nAHvpKGuBpv+/eky bKcNTyYswCCSvoh2Zg30clC/fW/RIqmElDHdhBTywMqbqqsCv3O2egw0dGDMtWKlYbrJU6NWE/UZ JUgBKR0b+m/95XSVNWyy8s8HuEiX9kAccvdVGCoEnVuyCGF9biYb2Uw5rW5bx5pcMqQyJ/iPM9dO EMD3NuTKa0wdRfd4LY4w975XrxEJcXgBw2zM3lBM9DPZzUzerOCAmBkBbcxtKnGucF4F8GbFH3BK P8k/pmOogJaVjeMTXTX5qszVoiml3iltzgQzj+ePE4eXS9p0Qbkbn1EYcAr9MR1xeonsZtNt8z9f tfornVLkrIOEvXJS/cOsC6I7N6OzJsk8IHalbyIaofn+eSrYT3th9v/qityqVoqhAGyfKCvCtkU7 lU4muwy9nxWc6saz75lbETFuTYDgPSlXaOvHLTsvz1i96XRigvVUG+U8eRoWz6BPHhi67CQSxVI8 5j0f3CxKFfdw0pJlMbXXok+0WIeaoWTDs2HrIGs6VK8fnClIsZsDE5tpRScE3iNgeyBNyM5qxLnc 6pC9jMH/V169wvbbJxY9xMqm7HjlGzuvNCae0xLuwmxMrKvwTp3dkiPGQfFjll+fonl5EWDshTbI e7fnTx7sJ+2WJ2rrqEcoTUHEq8v6GpOOZL/myU9d6cNQFckGMQI2ATiyI/xFZHXDzKJRMScsWPO0 E5/0unp/3apSKC2xMbg3drPgwh4hCsdNo563TdYEwFxC07wlI1QM7epnhx6s/rOKHGShKqZQCkWS fjhA9JrI7lDTv1pn+2BalFLi0JY+DtlIFZ/9mOaEoTWHfthvuM5nCR2i9r0O3EpbakGtvwYaU+ck 7vpj/q8g7fY4wTfmt9sEmp4kjAa6txWJbT1hD6T0zSh/3q9y19TlQ6iPfDkNloK4hCLErMdrSvt3 TnPeD0OPq6nVb8UVXcfKaOaoEUisD/Oju5GLhLgtshJiNynQhp0FUinkHn6zW62wyVrmX8dziPuh ZpRWvF5/8Ct7PExhPFQoKWRv8zuWFcITZbaTTmLX5Akjnv1d7mRYt6rwQfM45i3rWJZtgMa6Vu2i FZ4erilmW/3/tc4/CNMbSM+w2g/ZTL279nVgaKOQ4DWMihK4x5XbmV6O9BoHGlzI2ruBvdfl9q1e Qfz7FhyeihilhfULH5XmAbNTvuOo0sXMK6QWp14kNPEOl8VL51Ui2p1cosnlpmQBZr95HqCqgaI5 qgkzK/SNZgC0Ca4cR/oFZD3ZbL33b/ENg2oTsrgBEbziVTpMZH8rbBugC2ghCZBisw8nA5v5TKxC S/+wWKPtvNj5/mHaiJ1ZFc37n1g4xlLbG+Mj1ckCg31ssWDOCvqMyIrWeMb44a64bRWD0tCeTyOd Hdhf5hH54ayXBMTMrNUTxUUGb7ToCJM/M36sWZBLG89J4HcLKCow7gQ607bwMZGt5WaUuwAzUIwr G9GyWVY9SdGd0KEoVsjk7rnl+ieUhfEjFDmAgS4Gc5PPCIJkICwd64uGZeI8OU/XIO+NUOo4jcUd yOd4/ezRq4mRPPGWPOd3N2b636s0cBSFeBwr5pt8v/elmaNon28NMeBFvp/Sq51QN5BOXuYajG2k ljrxJRwxa/xXVu/P+vQEVxGLc14zrGuhbd4xK65GVP2D+HGBEdvbL/jqx5Xf4mMb0UPCllESQddk S3vEzzbJM3dBRnIKbL1p3nxedh8NtI/PsDsrJvVkQ/lLDzMNpoOfKzDWKvimKDhePCXwRhW0C7pa 0UfjRvWAV3EYEH+Rc63xHG4eoEzRkWrlh4XTHf0zlfCXf76eIGPAtJDi7al1HfJCbmkagFb6mzrF Vsa/5btOQ7RhKQ1e4YiP8SZCWiIVg5oDT4OZ2ADQnY/y249qadeLdxa3yN1N3a/OeiH2g32NeZXZ UPsY8zwk+fSygVUvnIj+N0zEjeaL24CwRPVBVAtCrJOXs9eKW6QWIzTTYoWA0vcZGl6+TvQy4uEH u7q5p95Cp6R03tlHJLhBPX8u03gUP34U206Wx/3GZvlihxYGv0g+1nmkkxkzCE71vRWR0nGvFZEI eTCiViaVIpCAX1EJMWzh79664qcQ0Gwwj1MQAl9fNWg+ViJdL+7ck93jKpdA8e++8vtUoK4WhvLe 25h3sHZG08aDsNwAdnnwYnvVLpu0ssJBjgJGZF7ASqj2fFowWoiDDGlfR9ZldvRBAXs2nNDOD51x bRWwJNKHvm38blIClEMHR5pv504GkaGgG4VSg/yLKGUqkp7yo2UYdo2aLBP5TKEkR8s6sbphkha3 QZtCSLUs22XfdQos/K8Kas6taxsS+90zZ9CRQRyOl5ORQASAmxQvFOMMQMI0KEkW9ng/BboHyCJB smyolVFdSDV0hrxmB4lavVsNReu+QdvzUBAg5sORuzShqxGNd3gxrz+qRLB/qatPJ/8pJlZKRUDR 39Eh9BXgUntC5e75T2cUTs3NCqBoHSQLA9mj9hSpFpy2uxwkDjueuRUPBU3DUigH+n8aYVDS4a2t JjfkbJuMcw7iYi343yXaZI2Vw8wsEmL02ADQVCVjyju3dOHknHkcJ8EL0O5Iisjb59DzCNASzs0M s8Nr7A+r6/hF9O0SUAPfYwfK1PopLFNSFNTreMU7uu3Iv3aYxh+/w4jIvZ6v+fH/IlmQ85O/Hy9u KsAc+jCeFVtlLSYluZ5kKq6g/nldefXeAgVjBLekekT0TxIy00tGiPzfcBUgR7MtdBLfBHzwy63J a8836L2oMIJATlY2yY+TIo+5tfdQRSfrp6A49FlpKRgMt8D4aBiKK09MUOtFz9iPkUC1+UR/p/7b r7AFs1aoPMDsxT46G9+/t0TN00FDEBGmHGTObal4q59ktWCnj/EAKVzBeIYSLhphi9/AW2/rff9E mbABrM/Htn+VUpqYgVrHbLwO6RNcNcw+fAbsznQNzau18v7ka1/4kT/CTBETFeIbdDVpzMvyjjMF I0th4bMN4qUUiE2wakcQdP32Uzkbj677geZtSOOtc5YD29JNBNYjYvmgLaOSLbjyDrHOG/E7NlDU QcdSkDu+kOt9CUzcG6Z/rliCp51+8JV5/wCD0NKQLZF5cDucnBIbkmJBlY8AAW01S+0IeMtVnx8y oE2hmp9yMNK2JTTiX7KUBkObVSqCNq+sbt22JqTLw8B7w2BhnHoKfWQf6eJ4VoB2aTpz7AlH82Bg Uu/fAuFv+8+pkdiy9Q2+koCbXQYljkmeFA8tjMQCQi/8FfxomxHwrylvnMvOyPbSeNV5Vhrvc5Y5 qPcF415OJOnjoRMwJb7d+xFDWhduNLRSyi5ypOZCBI+pap6XvJrUOHOCtUAzp3XUVkviPtxf9C4Z tuu4YOXpP7Yswd8YIEvQwCSRJyZxEoloEg53feOojSUJS/D3p6Ke+fIoUNAOB12jFxN/AfZL71Zp E3BfGfMokrPoNocL8gsfcM4bsHzhri4LgkOg632MF+Re5TrrOug8zBvVvnv30/3eD07SIpcj8VMc FNDPyKqCFs/sW1kSyHjo0yKtdcYN6mhN7RmYJfmZbxrR3QFU6VZYXGv6R2d7wN4MSD+KKWzbuq4z b2CIxua3KSZ1Q0VLRO8PDjIJkJY6lFA3p7f6RteLnImV+q0LAHDiUr3pBpoWzeMQHsDmwA95CpDV CQZNR7AELFWZ0CsI+A98pxe1w9lnBu2uAddA2HgLRwsdYLastRpNUNL3zI/YUTgajE7qc4PGGQw5 JmI+6AI01aJxB3N/5joiA3Np0f0FvpR2gRoC+yMZdyVyAHFAEprgMklYBDmCzOdrHS01oAKePCZu NDz7/H7+J1Oxesn02GpAOGUNtTVgaMFNLW5Jt0EUX+oRFLFTmD7JCaWgn/DLZCdudt5XWsAs45Gl Gt4zt6H03iXH5zmxYjN7cn6ApnCofdUJ8aSCnCZyxdKHAjJ5GAxCh7tL6CWZlJgZ4/oiwkh1Y76q 9HSr3CXNnX/qwqZiTm68alF2wK+u1H29bDjTQJEzaeKgUaT8jINyt8fRvlwpKHTzkhXMGL+jJ3K6 U/x7Ro/xBeER7rjr1We6N95WvFIEnlc4znWEYakSGpPxrdNXZufacEzgHWH2hAwTwApUhpghPD7/ CT7OrvEBynwa9N5a9qac8QACJos00knpAlmyOcg5ONzVRlRRGtGBLYsnmwAmnR3jW65nv2Bf6XxY qYAlKfDod92eO5poTu1xNAleyOOIXqXbbR6K8xBSIHzbBEl4IQ2wH//e3wrLjxT/hOgFlRchMPox EQe2UiBHotn7eH5odYM9oENDXZAvqLieQ6QKQWdg78RmQ7hZ8qFLSqUCf26fAlOsn6VRp3Qn0sMB +B9Y9+F5ebAC4ct7W3PmhfNep47U+tZFhx5AZwL/h+hJwEBgYhlbkDkp4uB066uDTNvwi8x64HXI jzKh/d0FTcRM9WmvkaaQPEHred9oCRUa/cAcHmBvOankbjDhfMalvLVKdkuzdXEVekqvCVJZwu8T UfsfNWh3o87nxhh+hJoG5dlswIIULDgRjPnIBTCS211nSgPSH93uA5lrXywyzc7MoRKuOy4Pi4Yw EZtzK/je0+46OHYvtBn7W9tEYH7NT8zRj8hkhFv28ajI58GnT+FUr8PtLPjqnxwPViRaGqvmx2uk OX/Lxm0oa5qj7nYE8vxzk66hrykkTXQRgw+45CdfKI5Q6ZJ+UnQZd0Pf0jE5gHGvmJfiUJ0Vct9w 3kXRE5QxLrJnlQhuEMYGVGB1QO5Of/1QDTRSAnvW2cp0m7RWhvgwIFa6/YVQFiUR7R3BflZQCVl8 k3xyEMrVUDDGSMyy7tOd+4G5Xs98tWqBQ3W37uL9D/AdmQFCEJeadmQ59lAFyxfQ2AzFDYahmdwA 3ZLCcm5afraZliXmQfM9oLzqK+X103y4w1x6YOTaH8qoaNDpo0PSiRMt21WrCAeN4cNOLjeEl/Zc nO8FMGi4meeAnRId4mp52q4qWFtJDPhbSS0jx8TQiaJ4GH3UMYthG4j2ekOJAJKmH7e7a/3RyfSr pdMSE8ViBtq0SwPjIyKMvUXbVcd0Ha0TWOFpJK6b74q/SvAlEEMYZbsWUbXBVQrMWwAb5s5tCxET 8hsrzzBCqG2rTW+YLVT2E7mx7+msTg7xlst8HlIlvoJTegfclYUGHx+Sq6FvzY9HCoxIXvx/+Qsu +sEFRy90o9YVQtUNHF3bv1hX/U9v4MREWSjQhSQKweI3nHdl9Ikq/eBy8fAUQuNJQNzWVi2pgNsZ G9MPqYavG6DDdRoG/GvQjToBjBMrohUH3SM91nNonr4/cMoTZDCPTglDs8GiD2HnjqB6N9SjUExT eB0ePnNkclP6WJwWrhhU35PWvreQVfrQd64fAFwewf0hc/u2gYkCWZm2cx30yfHfRvDtD3J3l9+B FGw5sgE/oh92RVkn64qWxQxypXFRMVFz4Wh8nSxtxQhIZLnGYjeipqIwlemHfuPJ/F1pWbs1n3ej jyqFKf/igIkGmxQlX4wf/upSWDVHwKNFVy24uYo43dVKTv1zTtZJAw80Sq8yoSgTuFzibr5EOE21 GabT4XTVOzLxsHZ6Etswew65+4h/mLOb1m1lVRGApdexOIGHb+D5bjLhvtyAbfZRg/r7geCU82OO AxC4ZfF+d0hA5o7yIQyKRJh3F5c1rRwHb6ChcsQHTq/ztuG/vVxklDtFyfe73y9EkPfOx+aTiIfi 4OK+8V8WvijGuFLGP3vxh5blcNvPdLTZLSJ4tgjtlZ28xNsaH2PMpEnZAIKowPIeh+hK/vCcH+ir nFqg8d+GlHmUEX8dj+Qq1wn9l4MACTIWZY9hMJsZN4wL31l530VC/gPHXaRULeCN6u2ZKN1oQDxn GenxNdxQyNVoHVBkAIEPkZsynzQAlPEwpk0ti/ZNB5/XKykzx8XGEakcq7K2Sb2qRKawx6B8bI68 uR6JaTiLld54bZeGiMwgW82cVbCT27EOHDdtvz3cgXDZ223Q4gfqUW44fp16ulV3v2Kgl/y59dxp ZWUU0IwfKXYbCnxwgo+kQNeE5Bgt4sG0OJpQyju2ECc37y8GWzBT1gWJ0baB2f9QFMhddp871fE0 EHrZHGqT+bo5tBgcPP6qMzf78s4ZNCmn/bp+oR/KxTdEXtiDvasvGOW8swvHfTy2qRfIUjFgv1n9 uyJpm70R+Tk3IIaJQ27ouSBVNiINsuqXFGMHPxZmjRg6XxSozSIAU/NjeR0CvTZzas67a7BMP852 Xh5up1YfbV6VWeHcANh46OShJmZD1XeDnm29QuDCeNXEaA2oT7+i7QQ9H82ayX0bqEaSsTX2vKmR 9U4/lQYdzrC9T8X2Ej1hOGGZZy09oBPpisPZVsPDavbbiHkAM1W/HeIRhOBIG8PHyWemorB2LqKr dGnF0ao/4sODgCUKACadDcSf04MdKknTuVNjyCU98C/8qTmmiQAz51Jfit/nJzjFzRHpl1REFzt7 s/uHdiHi9QFC38VDB1U6jSoO9kDoh7P/SOQfWsht139j1oewszDysS5RlXR98nczukQp+RYcIYYk QoXEtAMwGF4PibXU8CjmmTe2Sv7T/O401d2zTdCwN6kwBjlsh8HyHGehd4FdWoqKGf3owtVFtEFa kHWn3JxE3LAl2tVnLKkMrjAFsZzk2c+DhTsBr/lIwhG0wMAPnpVpzH498gEjFTazOg2ijluHIOzu PjtTcCZ4KYtDOoS/64DhbjPxT/3QtsXZQ8ZQAN65e3qzTTLRsnt09SA4CMO7E1pMOWxi4RT3WK9l YQYSSPmkcVaG49lisKyIZj05K4N0QhrPr14vpvQgclV0wsXNjdLmNme9pAf/W7ljJ4v9emyY9+7A nV9QRLWG0dnYSzers3hfc2FuPvMJkkDlWzXZh76+UC1UyUT+BiK4tnTUYIdoC2jOxVNxJTY1Y0y3 hk8qIs3fRVOR2TzjAYPzeTFxkdEbiIFA0zlbX3KnS0VpN0CJSV7JkLgnAzH5Xur8sixC6c4oSep9 fNFdymAZksHle+WLNJxERVqJ5aw5HkIKL1tVX7Wd/etdmE68mfotXsNB5/HbYO7Yz/kNX249U9Ni 3WePok4tuBunKdzbq9xR8Ms6HINt+9G/tYvmv7bXe5VCYLZQa1kdTbsYcrAcmf62iuPxcPwGPtgI VQx6vNujlZI/61+9kxBoF6cmWfhCs9kQhE70eh4WIk8Edg3DIOBs0dPOtq0MRKdp3wWyGEdbT7XY X2BEq5/roQODv88RD6QpTIMhAyNKWB6/KJFwxqgYTm5m6W5WRf+yh1+9seUDjjXfX981buGXZ1tN dXjLHAgX12geq+Ki2U/GDfzz/on6MtRRqtyfeBcJA9G9TDVWwJoPt2n4Ih+3QsQaOcbd5gBrxSdS UMt0ukwcr1IzFGcSfDY3+K9W18owjIKTqYmhup5XPmO43FifJVjPY7wLOc6xfPwqZgQvg0Ldbsyg KSTZOzNO2mAF0fsxPOGlMgTA2gfPMjLCGMm378OUZUpj1LbQIp/lW4pSfHzc5oM4ADHJiHIzAYDA oVd4N5KmCYj6aFkjmrvJ+4artJnCN8EGhfLm3CHchwJRt6uLeI/Gy4i9FXtEm/ChSmcpOCsmSKSy 4IDmqdltgax4atGI9erVM6P3703WpQ1S/zITo0ofBvc5TScqWiugXrTlPBIbwM7HGpP8211UMXgD EVnYHEtTC0N/7k/KWOj2FWmXFfYmOzgxCmg1dHWF3GrZdP+gsxhzI1K/9aIk5jDeosQZxHu/ARda e4usKUWCqRz7RvLraF6/B90OErNG4dqJZ79sD9Gr2+Jj0Kt6m8gaSLc0acEEpmK3F299hQKJtEpr oN4rLMr6rX9QA40CPfhZ0LP2YwCVbm1GKPCMfEPWZTYm26HW5s/R2n+xC7EI8Kn6lZk4CbMH8Pf+ WqsnmSlZHY0iI/qrYGULJwBGuP69ReFy5+zf+iSlESJZNB31K1VF9lvUqFpkvQjIJxuT217A29WZ aOD4ipdG4KJOLywEEwQJCiS1zKgQSF9LWNkM7CDTiYij6uudtEfCyyeVlOS6P/FFTsebFyi8XdES Z48fXZtsei9Ub5Ap2Vk4BbZDfghSV/K5e4nPH80tZ0hD8/c0YaB1Wklt8R3MtP13EyoiRh8XNjye ri3rJUArLVmIO1xNFgRsou/Ng9/gE3d6pMHLPvJ45iO/xOgfWo/lCzqGatm7l8eOt+8UzfA+iIod efbzg7huoVhlfWc3x7O7NGZRrbuZkx6dMtTJ/GqmUsKXgUQ3gJt8iw62zcgJm8xSgR1ter01OmS/ Ca8uGHZABkSqMNNafJlkDpefJcLkZPQl6Jl/PRk2xFT14Wn2e60cmKdE5AmRRr/HpPG7TMNZ257+ J4fbIbAGN7DgGHOoGotkU+j2Pg8EhlJjkvLT48XxG7leByLoOBnyZs2CqtJ0LEf3PVfNVDaka2pe Ta7Ojvvly8XG/VjiReR3QBny9KSvK+iGeTAiIhzFEKU8buNfXUNhjQXStV//3gniCtLCZPmLbtMr 9mkZTLQKhM8pwBRDDPF354ElsPxVDYc/up0GRitsCRwcfhKry7sXC3HpgKmeYdecNfCG61cNBTdH dnQz3/dBZopTeC9rCzvUQpC+Z12dpZ0lqZP5TwXWazLL2HK+CH/mvntSy7xFFjSZxcZznCSBjCBm 2tYNv+sA2qmkIhDTxiT+BzlFGmIXsnDNVYaIBUQmItMQsm8FaZSx4Pr4ccSqYhxgE5cx0P55W+gx x6a5CEJaJ1bnuyefdLUqijztLf8qBPZkXeG8FJvcJ2FOtZ+IIFLrR8utXplmvuSu793Labgt+neE GVni4Vrt+nvpubMJzIcd9qxaD3/xhRRMVZZUQ4I6+p3MiVxZ1uzQp35SSQfmJrAx5BLGXfdRtqW0 IUXr2RdKz70HUyO+hbLDnQAOduCyy7kccPLzmiF254ESYtIzp5+DhNaiB6wJGIl7RIFI/Q2XHRNM 1ZcLHae7XCU8QkUnqufyDOIZn7iYq1XBjkPhWxxW93OBHzETOaD85WGlA92zUVX0zQBBVVBftXdu 2e1Fctxp0tWjPslD68qwJvLED1UFYeDgbC8ALJgUq4gEfHCZCvZb4P/TB4YjJCipLwxEqm63cRWN zccEgv4f6pWfvAroU5YMawSdEZqZqYxW+lu8NlewHfJrBlLA6kjdjUCsoO/Fkr58utt7Yexv3jDy UWUUD1Ucw/ZJo2dvuExZ96rgdeTCgrGSqxKq5TLJQPdWQ+V11uDlPa7gxStTOoAYkhjzuU/25j6c sCbSj613m20Zqu1jJHN+HcvTWlhnZ9PzHqpCFAvNkAS68byT4Lq8KPwKpmWTsVZGgChqK5VgygmH GdBJwKNQAp7dqlG2l6x/5924e9n/Xqxd6d/65r7x3NXOIqt8trnoZQ+JFy1k6UsRJ8YWSHdr1Em2 pDPa29Cq/XDudotOmlfloD36CnnC3dm/hASZmgxIR4JMW1zoof2veXLOvrrZUSLxsUy+6jvywujt qRsfqsnhhDyqJ2qMFV0Hp35drVEBOHNlg7uxMtIt1XJ1LNCy/tHxBxkn3dvzp1x0WUBknM3Df39p PcnIf6hSaUlGThZ1y+Sgmdj4JSOLO7KzDx3E6cbaZCMB0aPD5xp8Ut6mawO4aUUpZVzcCtxniAaj IqfLYRxs5fsWR3nYpxKRFPy1ZkPgwNdXr8UIGJfQFveArzGbtvQpW55vx0I2cXha+FH9nPTuiu/0 sM2EUdsG9sc6esSd+E4+Iu7DL8QTS0ul0ydaxjDZsO0MGTG22cN4xT0R0DkQl19z0qmijZ2XPofW CgrhDNI+nYfCIMePJHs9V+Td9m61EZxYpwGs6UQUhN8JQZpq2QDavO+sr+aEHrgUuysu6/yGfPas Fj7h3Ctsa790CGD9Ri2T3J+ptSGUao1pFMBCtnpuVfR9Jk+PjG1ZGPGLG33E6h/dz6A3FXDyiJIE e3XttDD971++KGm7hci4gtOcXfvLGxPEGTmPcE5vb5Aemk2mY4SqDL95PSObpPlOD7ynZ7/X+ED8 OiFyn+vfEBS0dRsIqRvoxCsbuFU5AsN6TXg4DVB1GY/sTPyCra9Pwg1EVxF/S+bxT3KDolgYaO4u Ea5tY7Eb92fpvsnpEeVDuFTimm4bAPr7Q2QHRUY1fWF5cLBqwI0Xly7XaU9na0ma9W9VqXvOSvfT PLumracs/phbqucr6gUUOOHCeJ+KfydRIPh3T8zk4FkxeX7EmYA8uJCGfSmv5h+s5jMctrT6gxgk SCEIAIowFBXwub6Ccqp2CDO6icSpoHOKDp5dtsAYD8Oriqa45g1/AAwmy9cidfbuEgIrceuULRjE wIWy7uN+UoXTDnT5u/sE2iiJsC65lFEcJb5I/YXopios0XgUVXN7X5Vtq3tH1l7gYWh9+rOvP+le IIcccvCrNi9yLLCad8nZWNB6ctSz2QjbrKCd/RNoxRcPicLLBocJ42RAP1spjmF29K/5aeO5H0cr I+xSHnhVvh3NGTTd0Xry3qoWhTpmCMzT1zEPULuvb8Azfx4h8SERXAl9umoU2qu8XzpZIocNP7QA ohvMzeDc+s/r/OIG0cH5fir4rf6Wihipj4pRurqwLhxl0gGRcn9GDHb3FKRdpjqyv2TyyZ4tDAMT C6Fst21Zv/lo/7mQnHGRnjqq27+HU+aOcMhAqonIeJlcY/o/f4ngmyEyQe9Dp4wR/SNFen3VH8y/ 2bzh97eHupglw5CaCy+MoJ7eUw6T7EbFW2XhGdmd0YR7P8S6K8d2uZeeNYOwVXJd0arhIDDbEuaW /Hoomu8EM0RssPxLJqVBjJnjOGVPq79hrdsij6weJdvTSBwV57lDs/LsjuidFmfTY/kE1WFN6dra sC9aC78ggCwyBHrA1yPXRCkdGpZ8nan1A1Qf9Vk9j0La1+YT/o0+/sKpUIK2p82hxGgYwMBE1jcZ 678NGvlHniuYrj/EHXxuqXp+yvo2AmBCFVJr2wDQDoiisCEREEWdQepz4K1DCD14ODenaXYwkuDb aiHtmHnKqSfcVHLZ0SQuxwY+7I/QhFas1WWE1yod3wlP41jPe4SUxagTG/BuYXRYES6R4kyIgPQ2 Jk2yDZwrXwGHj4TAyrpxd8tdd6A66H0MCbTvJYEkiV6b8w+uz/nZOjkb5wc4nKE2WjYmFWnr3Z5E Ypxx2tHyr7+K57nyuMOMLrfsvEUcqaNm+CvM9uRJPDrhTfkAxv2ZK6Mp0gIvec8kmU/uWXKjHOJt J7jVoRYnXNpahbQcncxlI3R51BY9PQQNr5aQCSyq+ORcbbrjRq5I0lJx6AuVgxwwiknhh1V1zj7W 1mwaBKYq1PEVZYhLrQWaoGjagSwQonuoXmJS3Bz2eoBk0xPKsZQQqFbSoXoip7LBuGx8dI7U+p7W wmVgqHhBbgdO3WHIEaL0kmsIWJoGJXa2cQ+L4sV6GOs07CcYqBBLk8mW5cdlWx6k5xOHxD7iP5YH rvYJzSY1N95KKbbMryX0NkWw1u8xwLXxi8RzHQxmFYgbnIqFV6nux1BCPQTFyciO32O6nXIZMrMm jrTzj9ZClk1pUVFqvuI6UQf84ZuW9iMOT3B9R6jnQwib4HF0YbXuRPba/kmNVRV7d0v5Mj9EGoWX ihzGU2naC2MzwX58pGuXkk8s4Ly9QH6P5AQhujJoaPOVb+sMFYIznTKHc4E2Q8a0zRSTn9hA93tD dd/2MUugZmbtOWSqlaOSALAX8SGaeRGuUdXqaPfePgSx2kTWE2zsIG6HLA4Cx196aEgEDxjucu9Y CN8LfahMzvPuPuBxAgguju4jwtnU4GBA3cCOZBPgOPdSRzuRdUY9agxoi18FySGwRgItbVRnTAY0 k+6HZdoLCjzZxfeiixubthR02jWCWofHxcSj9mXawyb0GcTWRFZlnQCxU5OrYC17AMA6+Hd7PyT+ +HFVQUoT3y0KhCTmefptL1GUAECK8Vcy5/qlKbU5wEEY+27Vn52HFdZejhgWrRvRDY/xhmyPHyvc F4RQVqGbiYyDUlQehhXSlUXS4+MRRs7scwNAbKp3QsZctseLxvlvrEtNu+kzYGRRp4A91qgDpTy3 IoE83kD8lyTPYql/dqOMSm2dCouNCuUZWonZlHgDL6C8jwa7n9muRK1LxorlrWMWnqAPLBCb/3nR UWptOdjg4QMiNK1UIECC/+nyOhVCxNvNWuo8jUOaliW0V28E6OKw38sshKG34aRPXFM169X6pRDf 3iKdq/yMd1Vu+/WCwJ9jfgrk5g2aZ/iUM7Y8SgRmTC0EaMLyP3fpYUyy+FlUX8dE+gF/1dQSaxXV TmliYS9H6smOUfjfS0nE/k6PVyCxgpLs8yYmI8sdMIs09W/1e+qwGy953OQ4nQ+PDo+1bsoqMQA7 12lVQAmT7k+Rf44a1yeybs1bntkAG6YdvJRR4oPfjRO6pYFBcBN0D/XbCp51K1fhQfkBfcqHQGk4 j786xad6oPN7cjJdbq8TEJ6qwoKweUaHszEimh+QMy6L5BxeeBWX2/sZd9yjIcJthDlhceMiv8ZH BfYKv/qxFEDjggaM4E202vBnWLoV6A90bjsEMQc0s87L4wJ6TDYFB0yZD1rzYd0tzY2S5lI00rB8 pvMmGIadBQwdpZgr1r5QcotPNcuOL99YmVmmBEZ7IEQ17qmpN88QB6hL21uNp8hsrUqoST0yy4Ho JDwiZqFv+WKZgt31pIG1McgaV8E+RpGWa2bNRKLgFG4gEVtfX7SW7NuLg/KJPdwKtqcqIQGTl/5U NCRPoqRckRt9JFKa9T+l5XAncVtIWSEe78g4y1LJiAtMHCCUpso8pWpVCmmvatRNwc06RJkFafMo RdNZz/u1cXV0ICC4yzfCuQ/ttiWdv0uvzQCOXL8ag4+Sk20JosYo8T5uqm9cWY/2QyOdeRfhQoYw CZeLiKb98GhvqSfwNNLAcZB8bDh9uODiiIV/Oa80eIeGxrk9ehYxBgGkwWiAhLpJJcRIcak/FL8X s7WgYRgpsq8oWmJhADfdw5eIyBns+K7aEvBeuN/QW41SOAcar5IiCNrnJzzWn/kuBqCs7OZBPUrR qOaWy9A261QPe96ED3opuFD5zpXem4J6ZgANZsgSc3HgaBv0EyDIY66y20sRF4ch2Kizlui8d8Ga yBT8OYl1WzWuCuK/H2rwjW6dJRWtZf6myAaoy8TkhzbOqCuRdp+j5HAEJreu2XwOJ3S9dheKZ/CG L34ba2gp6DCcUKwE6hXPQAJmErbIZ91/onZ3G/CytjX+GZXwzFAY3gYStIHAAR86nUHWnOhLUvfx EMqj0kXLb/XEEuFzOStEL9FmjysnQTwsLicA1wqT3tvyXKYpoFBPO6EoFV192YE9SPYXzjqp5768 u2owos0sdo0g+pHJFQIyc5LYiNHWojoJu4o4EN7DU5VNWeK5UVnPrBDSTjZtTo1yMwYfc6nkJxGK 1h9EAME2ZTcKCkab6yfoLiWHJLYx/DoHHSe6s6L+1XhGN30cBs7amQhxSbPtjNXRwe9NzYDX3deO 0sWIFFswwgkM8Cc2n4aNIWyC75fh2N8AZ4eNPCz5If2Tp+VTL/w5+pNPCsz0FGFaFXXKw40bpbEo HXOiF54LG8eTMExupyJJyzaADCvHZIEXGgdII/zt9h5SjicipSBJdTSD3b/psvfcZ8NrtKvzi4z0 EOge/shFIErpfvxn/q/yg473vzb/exDkonnS05ZA9MiSxmzrDCC9o1zzh7yDcxXkMB/rlJQF4rFT Z/sWONejIwbsuMSgAhhKZW/lY+wGnPWj4Bh2mT7p76+jzOwU3O9LFvFD53NVXgEFbkxdDHc9da5D m0v/aTWPizfFE7KL1LkfJR2NlhZ/ODlCIKfqriiYdCkI9bZXPoBETTL8WVlyvL0ljlAu/HdUVFSe jtGfqK8G/IWvp7wi5naWmwKEocBpS/mv6Fb2HTXpawknbYOlqOhkayQLe93qWFXEmIQcjB/8maqe I077t0RO64e+7dQ9tUiPB8KuCIvp3Qks9sdgDSFx3XywyDDt6vvMjdupg14eNbQUdz0QikywISu/ QdlbM9hRdz1luJuAMBVDgM3zL0yinOtUeR+Au53utA27fqKu3BfJhQnYPMLKR9kUW6pCHususfSD 7a8FmR8xPWi8Uf3yR9B2kvD0rk59A4Y3ZLM98nFsk8dUjJKpcptlLrlkghBRTv3lvLNCuIAYzhLZ n1NZHqa5dOVogGbI1QHz45vBRv5ZVE6NfAjlUh/ZPeWex9PQXP5D8ZPmNPu1xrpNGZR0v0Ya+aGF 9STHH8OO+pR7uN7y7wnJFjqmSH62wiu4/urOHlg8A7wTkSbL3GRADkvj/1XsKo1v+ix/nWdgXKsy WCG9AZdTyh62/Q+rc0Zy23c6nxbIZb++pLvAY3gN4LIqKQ9EinZpS5hn1MA8GqGv9+eHM/HN5Xdq LxKZ2i3YsvsZvXmvEBuzqOB5f6JXq6tCGyUKIDrRrnfTzXVEV/4zyZO5eTDnFxXs/yxZ9cEaFmtw e+ClR1B6A9ixRWpj9c7FnT3FSjBnXGLO2fcqSAfH9EVAKHVTAbLYWYl6vI2IiOlXaxruDoJoKYua uUfVTDVpXIBlWtcA9rCr0177DE5yF/m/GpI3Xp7DyF5q62vBzoKNs8iRi91QHSjI8QKYJKxpD2sw zHPC7csfmHtkt2rzIL4JlBO02XvtKGelR3NchHBaVFVi7ZNoFV5yPX/rYUj00h1UEwjlXHVuxlj3 vieSnL7oP16Lzgudt3IBnQvWqFJmGnf+q68pi8sTcJ44DX3xL31BmP65bfq8CemQte0wS7BHpaOh 0EGOC/u+9cj/UGnioAhZ8DywLBFkaaZGSx5AU9IyUFDVjm8x2oEJ4jFnVrGH2K9YuLF/aWhFsWUw kEBmvAxA6bfybmhEEhMDJT1sFRcS95cstq+7t193ahed2DsFFJg4PV5hbcjk2YvscHOsP7r9EyoO SbnBEyWfPN4/Y4vXH53hgroAdUVifw+7BmkB5IeKUM+P24kIrBsp28MUgS53LgoAVfyV34/HjO78 6LtHJDPNAqsVHcvLO89I8mvQN2bDIJvl3RmzE2KuSRJQLFh4FPeuHwMbSCedBVKqO+JOECcBX1z2 kFh3RvI2IiUIccbWcQOzWjFc5TFMDeqtakRwVZgfYiYPurpBmwsOQ3wvfZZeDZta7XVH3fJaC4gB 9CjfD4pUldrjiXzPf2OGmXcVybLAGEFm5rVRJXM1dXvZbGGGCqIdMxvzROcmPa+mVuxLVZ/Jgl9X QA8jbqWCaVpQi1+of1q7VcVBFETcGXvBL2GcOMIbQ/GVI/hnvE5a8isNkPnpBQo3tWb7ykvvw3pW 04GQLEjjmxZ+xfytaMHJbQUQBGINweUdZbw/qVbfo9ldudAHf8VQdwgSzaH7trDShzxFXnhwhon/ Wh4cb/NuFuqjdhPfsMnz/xghBPZIlqFBLsrzi2Eg0WvR9h/93gSk50OEWKOSyIJ5Anf0GVNBE7Wj hoUZS/QyJurezBjzMJP/rZ8ORWudAXzzCBcKyVv46SYEH4G8HxgBl91Xt6nFydsznuTK6kOlC+vA Ba2vk0/EoT3SE7eQR+2e+xEzg3t/82Wv4FCiHAeM+9GKlTeSn3w4IlHI8EpjTCnezheZn7r9bfEz qa29Ol8q5BtbBnFIlDcsENwCRzUu3DZL91ozpEIZQ8eO+aLr5p0NCR6IFAjZ7Y9bDE9/0sK5sBC7 z4lZwV75e0Ccu3J1frgShGPzFQ0R8ZSubFIZHEHvOQbJEs+kxzcpuJ0IrZ1qnIs4TPE70f6uiPxW PRNPTyVBPBLjIKGtB7l/Z3iHlpInv/tLYpnar/eoX8XevYFyPgGMlEUvvc+k1LoIdSRTmoBvDwin aRcekrIlPOkIUUud4NzjjSHAdjGzGSl374HObktUvr/RT3UvG2DIv4XycwJfjhJ4Py7Dh1JUMu8k 1FTS1igim0bxrZ5+1oOIPbVxzfaFn4UNyhF7+CLCrYKBzAbhGDsHyAq2KveUHaxZ0GjH4eqk4zXU FTq/HUyGOoFeqP/+TuONZRFcll4YnOb5Nq9F26DkP5KGz4ZQwdQQskbEdQDdDmckr0Muf+A4NVvZ oV7R6U8WSP6KSYg+1603CdP/lcnLb2cwniPp1d3KN/j6qZyXigVymcDRCg8UuDgjL0naNsdk8i0B QiNhaDW8grPIqM5poH6AgtOUdxZ1HTbx6ewq1LREC+s0sB1lKCbeFlZr8xllduTDsDihbZcLJ0gl 2ikKDz1Dce0HM0lN9R3d92b3XhaEOAtr4whLC9iFVK2xQca8t+7oYuKkZi1MILpqdMa6o5+2auJK 8s0a3sTLCx4F+QimzaK4JlcngrzRprFoBnSgZ/B+mEOHp2TCCJ6+tcLJkcXZTh6pcWp9DHtcZf+3 6WEGTYYsd+ySuTlRKigfgXkfxh9whllVe6OfkPzR1xWljguFbF+5VesJZ1yRu/LD2Y/+EoSe2sQL vL5KFuc8eKvKlvnP1PBfVoY8MUvADY4uy9cIJHtQqfAbxc79dhLHXLDf8W/RRnq7EO9/w8PUtShi CL1lRn9v8Fi1o40bA3ZjlGeeGbOi4Xdp+j1NYQVj9MVCJQhvLZulIRXz/8GYXyLN/tVrANxv+KHo j7VEZmyJn9EQwA6wIW1axbi4qdMQWtz+ZcNwR+7gYIV2s6AXP3Z97ZtIebUHQGo/oVaFZE2TQ+81 kZxCpeAm219XPv6umYxL1Wi8RGCcFVVNVwj8WMtOThd5Ek7msDD1dDUJ8D8f+D2RT8XiHF/n+f8H Y2o73GMZEUsQZcmyfg6OPheFR07KF9bC1ys1SLYEGtBmyh8zxV/rGiUICY41POuRN1ruw09iPqQ/ N2OF0XGlX7hicGnRGVBD1S1FUBH05aDaG7PsgRFixT77bUDz/TOTFKkegFgGA5+W3VuLinhmH9eM STC8VC1GuxQ/OXd0zkBZ4EfgcqRS8JLcUh4XQVyYz3i7wAYWjCQ4XzrSOwnJIlz7xna6lhSsu5Iq vufSL0EpHD5kklS2zndb1IiC5tzOqFN9DqGZxwY8NvcoeMtm6+Z/KCOQeTiA68QCijpjRh41pj3U VHimwFl0qTZ6h30SqDBSmIZeq8EiKAmxbCbX2fDVnacZoaY1aRuELVIBsOwcCGZLdysewXIb0HmS so3Rc+OVdc5RHxuqYiLNzGEcEkq4cDeJX7hQN9iQOat4ShSfYaC4ZHIj9lqgi2xEQLHEDRDqXITr vnE3J0o6MPDnRZAHgwwZ/RmJmKzy13fR/hXSUbeoEOjdymS8tCW7nXWknCGzx8ZCEfsKt9LOVRF6 d3c5dorSmeHOIpBiSIs3bn1H/CF6I3S5CTMtDO3IzKGtuDR7ls7tVvBwW4OTdOASi1sZV80OquHS o6VGVIPczS7bFJkF7KD6B3Un+2XtrXDOfFg/CHe4VS9VkTjemaVlaM9XRXZkC/3hIzp4rWRojFWx WgHpc3gLlrwFIgeLyCOV66XRdgbOhPJN26OtHPbT4k7mGJIzZwsxtuuOxYDH7P1C6cEHvgzLDiYU sDFFAWwvb30inrez/rRKgFqjeydGQ2Fi94OL3caYXfPJWIV9XnEAgDP6u4RDi08/+HEG85vWZrUb 0dYqiAwh7cz1SNjBOMd+F0MTBXoY4Uz1HLsoOdbARK22oYxtJ0QS/xeC8ayFAiL3MMabqMfZta2J 1kUUPaT2tQbVZm2f/RJ2ayuAZ9lw8M/msNDrsVyEpAg9D5g2NR89WfPLEfLLXSIAkulXMt5uVymf YhGcDUQJM5mZgqp0BaZk/VpYXyYYKwkLlGeWnycTbT0zs+KXBAu7c7HZG7lNtQTpehE+Oexa1FlX UyuAJY5OCF2ZMXXOs13vf0AkKErqX4Z1csQZge4oZyznDmZNZ3GoC4cB7qCQcPjW5FP3MWdoG+Ju Nz3NF8sCCDDMAEMFlGd8E9HAWLdHwlQj9Ry1vgwl3FMf2/FLbSD6jQ42ClaExJsjKLDF7Cr/lbmm jiiGk6da/KLwRyeinDhHaJc9aOPxBvkHK1gK7U/r7rEooeUBuAd4Aqz8IrLRTM9Eq7iN/8ztGwwG HGcE8LvoWBrx98rjeQoLUAel8kZxaVIsj7Et7Qb93t3Ju5lArx4Y1OzVk9+UGCHMHgi9ORDE6hju 6usGng/Uxb08XOkR4Zw/SU+tjJx+G+Kp0/ZK4cPyaiJABAUHTu6J2Y6FPsE5kTE0fg2Z+fWT5XVI mqSd2AaYfF0wZXbxkEbiaUTK1zc1iMctrw/gIUf3IvVMKIdoULCL6gPBn1T+HBLtgEpk0mjBMTCA 4YIZqRqL8krOStZLef/RmBPPP1Q6PdApvJGLsyE5tDUR42+jCWtgDr5jiX3OTsjKSia0kD0gshrr M/puQSBlJ4DqmMTq8IVShCOmQXntsfiEGRTcKhHhmlYCw9gk9+PfAayRwHAN+AW9lRxMP8luiXtR +Pxra+C0YfBOvBy4qBp1gOHqAE13pd+gJPjxlA7V0Nesmu/61jQ1lBCtzm+BvXFyq1nWTKerafer 3BN8Hm5LlDrBo99Joz35TBPzjar0V3tOVQh7QnvVP9pVl3lS2IwzZDxwq6bepuXKtdIp/+NmjGHX jg1OwM2f8iUZlTP7gYcg+n4FpS0uVq/CRzZNi/D/mIQJyuzcdb+01EPLDGBRn+M5kXVm6WbnStMM 9rw7+PMNjih4Cn4M9bvjxkWgU2NFJk5RBqT9Xqk8wZYGHfNufQFbzRHT0OGL440uIJHvBAFUd5+/ jtziRRZrb2Gg0MzDtLoOdlkT+BuVXv9Q+Z9OvN46UdnXsUgfcDJTnIY/Qssxw0QbnJ7p6N43bd6S ThmD55tzNbq++ea30yaGxJpo7xGsTqMsahbk4LALFndZK9kgSfj6uPYpDJMllHVxUBokkLpAnn5j ZCkMH7/WJnzQ/sKdJuZV7iFHT3MCf38Mz1pCRM5xBggyJsGHeqR21/AleT2sZ1a4ektDAihKeac1 v2dCQX02OHN5Esbpd2pUnPSzhAAfivUFSUpMJfE+71HZi9sjGu5rMD0+UwveBMYlYbrbZD/YdIk2 sawWz4lwD9sv3Ftpp7hmTBlwqikyy0271BM6zQFdcgpUXSaadnbiJGqOiXNZlkV92JRbSkNcgDca NzWzKlvtDr7o0AOMnbc8cqQNneshymJf6gcX/VyXpbC1dqUAOOKuQJKH5+XeNoN0M4C0q5LVR9r6 e7g7z4VgpryqGsWzQBMPPmGXkGmiD5rV8/aFn3M0DRVuE9W68LqXmpxZjOLRdHt5lzWPMLlwPGsw dEli58F0VKC7JW3tzAuA8KslokWo3aIsvpDjs64mc0IKq/PgzrPh6IwK0SgJ2fZONGc2X2E5wJ9N wks7AGlzAX7JA/1bQPVQGebufOPVk/HE9gMoRF51PoO3Ur+eKpywhrmYile7JlwbFcin3Mpgcb+L SEMIZwQO40weL31ooJX6UXS8ffsce6HNoBiPTqgLsO1aosM+F+v6gsDdAYYCZpjE4KPmkJtGC9pG L3NJEObp2un4YT8TjaVG/xdOQiFrUn52c1x2Buo5/SfgB4txD7OUWNttyCqfIC4AN7deN/Rn9Owb T1Xl+OeIv2J3lcui/wu5C30GhVm/5OvDNKsamuIBmEvRJsmjHNHc2gZdN5+HI4CsjqMqTj+a3FCY r/h1Mk0TITMKyAbnXVuIgo58bE3woVvXXio+xKj9OR5D+WzsoHz8Ax7i8q7nKvYXDiUkvEk0Y/Bk QHRodTKcWjwWr5vMZFZtPFCl/bnLqKI0bsEAVuNznM/JEHvG7MGNuyH0M827VqMzLAhN4sE2gHZ6 06n001A4RGr8xFa7KEwgz0L6lUE4NnfVbPfgeC9btYfNAdNWtVoUv+aNd+fyeF4qVyKsH4ydjx81 lS9v9EWdvVmiCYe52dr72pdpa7QJSi7rkA/27drHMUidSoCRGhTnFF1C0tM25gTqaOW4k2vEGRB+ o5UedZx92G6yKwLx1WBGIQAgKAsjYVDEGebLX7/gIZyRH/4w+bVmgef7ExsPqvuHGTo7XQw2Tn2C OjiobIDSLUjX1sTWo/GF+d2gns4TzWq4DuUclY74nZBG5IRrwi47agQ2ppwQtI3H2ciH7LiNxt8M BrSo/W4Ncs2QeXGGk1t/Xm54V+/mgyTSbrV4XgTOwnSmarMnd7pElsxt2bolTPaV6UdD03lgS6no Yr95zNKRVxxLhtl5BQLn7lmEoj3VGwIaZOHGPd5xGOKviVrSJxneXeij60dZ2VKBPC0vAjEyykYs 3nn/QqBmpYGW5QVFciC2Wp8Y3ZH97nCza1zlYhTk/cTSRp6n6yzxsNHChjLoaP99TZs0nnEydhET umaQy4x5waKN0L8UwRHwtETxa+MoVvA770us5kIkr2L9JmWTYehucOLlON1IwCzQKHw/qhuQH11u jgQi2R70HTx3bDFypCRFCgKyXQCPRpmwAMFBrnjmLkRdOiTVSGHdZfBIJN4ETFmoyARET+bjfmyV iZd9kyqOdI2iBLFlaL3fWOjz5kfh4FST6Ka5VXUz5W+7dh30kQwntD2B9mbVZRFn3PeZl2dKJnAz j824/oFBG35uNBeO9sNtUAOMIzZ/UfHGju7PIDM9x+sz6kTTtzdAoQAaHrQyTkiP48rHmCBJVRba QA/f87O4E2N0Gnao7k0amPGb/QIN4r4ePDj+4Y5x9zsuldKemRvbCgAw4Ji2UL1l8YxLJu6uHtZY op4emm5Pura/39r6UhCged0i3AO26XqoJwEkgIURYe8c/MRcrQhget87yNV81rwgUDayr5h8Dg5B U83BoHI+Z44CqwLP7I2yP8IniF6rmvBPK3iCnpvUJ1lkVBL6756i7khEDX6a43K4+4r9ztXXSyUi JDXuTMb4cnTCUrJ6+ULCT7y4XDUAOa57GdDzIZIo/JiGinOE5aq24r74avmMdi6lju7Zp+kDqQHg 0JC01Ni+rtOZNKpYYs6zUvYEyNYuDgxnOdxlrPYPdTaDizfQfV8JQfwPrBUoVXhvbesG74DZ+yoN RPJh9ELfg76cL3kcdgfZoHL82qSx5tOMmDHAHXeQlQaCDd8Dibz2Cuir5KSmZXgtXgQN+OIL9hB6 9Z0JB+T1dLzT4baCyQ34nYXKzV+RopyUrk03k4VspK9q1jnoNnlRm0QsjRTcinOI5i+75xmgCHRz RAU5MF+eiNDltobBcL4NqAA1ysGquL3IdOB0Knnga8xVv2SiRfFJdZDqzCQviB+fjjHElEeSv+A5 b1cztBH/c4WjC2rAu+CP97vJizqawu3DDPpcT2Pa488DjiWP+KgnY5I16oUGNS3wCe/ndzrmszcv tAMcUwZgxahhU6kW5ZEN+FIJxKcgU9YcgRcGlJ3yE1uDW9wE75p0baNL0mQ/ZARYrkpv7nuNK14E 71tY/ECothhuf9HJsaiA0P0XetBHKUCdtxSvkhzzumyZkSRbMug6IPNilxBXSgbegAT6HKo0lQQN +yVDKgEs/dRpRnIuahS7AqwJiTSHPE3+93O5IqLWBSPJz+eiER60RL81T5C21gQB9Kwm0CA7Hw+v 7FgcyJP/K6OA/jg51bkNGAaLdY7Hn3WZt0BTLkT/Yl6Lo2ilDw1JX8a2uj0/D0uGj5TH3s9+Gm5c 8Od8SRGHnDGoxM5Wq4hRuM65OtfL7COtQEOzN2L0FKlafpCxF4ZbiHGSjf0zx255CxJJWFXEcTie oejBr+9YSgYnGXrFHjBdr4Q2OhY1J8MwAF2Jz4h+RI5fWzn4KmLcdaEQDjHfZrJtSLhILvHJv2Bx CaXSAdGV8Ys2UcBSNkREq4agcj5/7D6Vdr6MIuQU1lkG7H0S4Vo5ap1IRMjOtXS33ZEorPScJmKj IxgmNWkARUZFcaWgPFKkqCcahHwMgKLEbYrfNzjBHyJrzCsTVHU5hdmit9pizxR16LnKcy+/5put a4st80JI+KZhf8DgUMFq9Uu0FBurYP7XhHbMtmMMQgeaxS4AjFRoDHav4FuyRdD7OUkUryLtEycv e++c83djrzwJI57UMv3NDcmIVotPbBdjgvTWKlJo0kD5ApBh7RVLgkM3xOYEJ9xuiHzyDoKAyoIi O67Nc1j2PP7riOqgQeqfxl4TyWmpQOWhMvF/UDPneZ+3PVXMt/jcAJPLJJJeH7+uVcHSOAvxhtQD G+/CnZc0CpZW2e1Rsi8JKgROidObnSmapTCyPYImcqtWBNoABfgM/pK+YXCF77KhS6ioy1DZlRhy Scm+XQ79f3A81A0jEW+e4MIHrNfLRAK8horIE4IV5S53bbTcBGNe3GBQVaid2Vdzdbbsj7n+nRYR BL7mfz2pspOTk/o+Ux0ISk/NTLw0VFZVH0KfpSDECCfwPIz6/ol2nBjtT12eQHIikKcVZ3luqAoC UDynM69ZvTPw7hHucCH2WhdPUK5rw9ZFnv10Mz59ghJq8U1wVCc8pvj5x2cUXKevb0PPvXN9l1Rg u9bDpw7Tv0p+J5KYxS40IXFB2aVbYhuqjilwV8cj5g0BrdI0+LNNCCrLoRu5DKG3y5fPVDffR95x ZuIVhl2qROn9YrYwpBuBEQF588NlI5+kjLHLd7iEOS33KNFwjIfPiumHP5+RnUEk+WqfWHhUzVvR o8gRr+x6gDGjlrhVC2K3yiOO+VFNxnluEtz7YPgEdd/HxLlVrMUznDa2tvHPI6JzkhFO4mnwiBS8 EZWCZh+hr5YXYIU3l0T/yzSSsT/OdY0ZKk0QELIfKbFGXWk9DX2YwKi8cmC70zC8GcuZFK0d9gcu 2y7TL0quH5ZhUGyWIczdoF2AjnnQyNrbYk9KWcA6GGBoZR2akShvJvqLU+zRHysKvm7sst0d+8r/ wDGvgiNj+S7ADCwTIFYT0DsSjVATlsfcB5iuEZ8cwGaBcm+cn7TDHMwouYhmW3vV5EC07Ih3YKRm FUVk+v8dCAH5vOY4bG4gw3GLJa1BYaxpQ//84R7nlhxk694Y47Y4nsx25S0Da/FKeELny2A2h3kq 8MeYs52lolMZhcHREG/cmOxkFFVYgyve8LQkUmPJvWwOedk5H8wjBqvEB2PUt9mRyrYH7u84G5K4 jimInpypMW0KAsN1m58JhvQ3rijYkAZ1ur8ZtP9trCcv2Mvt9TuL56iPa1ePxIh14vir64gcFXN4 jPRwKoGFHxJDVEfGKKkxwjXN02hAm04q30ZZlsAlIsVwQlHp2JQrB8paSb/sl3xTSMajIsPR4oyI BP0/cVrV4LyHupkBX+gODBHtp88OyLIpTdWowjvXM776tONT9x5Tp/dnTakVgGsEirwQ7kHKKvsO pOQ2v9Cci9VF6s48NRO4W/uARcBqmVbRWs5vTS+5iGm0tEbxNG17vrLPq8Bnrs3aBC1Gh42YKDI+ w1ZIXtaqnJRf67fw8OPWDkj8TwXuhz+OapR1kV/7In5YyxK+5oUvxHqUm438ixsxNZezLA/w0lnj iilmLRVr6tj27abJ/DMH727deYS26Tzb8tMgehu3do2hqTwI+HUVkoDdx13BeVMHhVzra6VfgYtr 43beuG+Vb+GQQS3IMGWB4BWL9cAZN23YfdMThQ3iUxEvGHmPqqXpOG0KIC2PZVnhxpsZYNtEpB1F UlVQUPIZPTtM4PnqZyaJPxpWuMFfRa8ut0pNSlcidNNBU9cZ1KgHwC9rUexoMEsM0uWKlIEfQHeX 1ewBHhv9QRkSkiY6HbKnpGBtNNry6Px/jhfeaLYVV8YPbmNo1XFM/1ovaesBEeiIsTnql18FEjPS r6JEcIZzdkmTOz4hT0zcNzoAnVGMT9KNegNp+hmodeVzFh1XS4EcMHUqQoPREkkaVjdOQ+cfcBVi xCWkzdmlC9gtmCm1+c2DZLDkdssvrnfYYU3lm7Vd+/V8Upx0jqp686otMM5w/ZvxpNQJPj9CTUjl B+96S1vsdyEZQtUJkbOhtqOQrhE1dlRQdG6mMpD6S9vyhQi+uV5BSILlxsT5KTShwq9fpD2ViKmc kKeTjEmxgnLM60Z710uXd4ZWVjlK2r0YlbYXwXwSbPYnWjttyJid9nv6DP1t02vCzMP7d+dEjAa4 3m3LUfOr2mVqA1PfwbAWE8ku1ZEBy3I5v104Z9mSu1mBXWrgBpQnO0cp7sGs+lyUei+BROQpyIF5 yJSWglcBS1IyKQhAnRq4IcfILPbf63D7XKYjHr3qsp7mMlnDKeqksfpopub8NN/tJyhJvuxpJcdN u9WRSjVns1NktdCSVmdKr4qOnDAMF5Bo40mp3E0jHR5ILId6KZshCkAS6+oxpOe/G/8Mk0HvcjSB 2wrT7gSu5UmKHFW8OPd2cVMDGeK10vUd80vjhfku+rpn97rx4gJjRWazb7O8z26fFXSdg48pjrH+ jWFgBED/+cStwVTQz48maW1WrkyqG5ZCEFYeL7E25FiwhUmGywqAb3Uyd+5EzcPANmA76WlBFnrI YtaGGj6Il8z/sm1nNwJrQEiR+j7kMQFxzgQVf0SbIIHOMbhE1uW2XhUG/VOJb3h2j3gfkJcqRRAG FRXGeiVdnW+D50jBHUMnGTqf00VhlOk0QWwubiN0RdNobWhVYpldXhBr6BqrxMBCave4bz2cLH/l uk1IQYYLr5xktng0Z6kUGgMZOY7vkNWEYeBPIoHDPnCO1LeIh0MS6vckxh2rdRF80O3iIvQ0T5lH QrtlVwfhby54Z0z/zz1efYLm85dFllSuhd02eP/8uJY/VpN8HbP74h8qspiVjHOdXL4QuyBA3um1 CBrGS6cId9bLR1/xcWe51xjxVBeiJUMurdkL+x6JXe+ioDhTZOh/r6/TV3X25rTZ+r1ygLdVXyPr zEgma8prkSAegmHvvqWP/lKKF19JbfzQfl3KrfvI4X+jLfokBw1bxUSIEzBL9mPk2pWh1WSmS63T RyKmAYSzuZecilIhOns6rtNWO9unJNuzuPis8kSGYApnNPuVZpZYtPqb0sI3e+aocznabdlXgmLF 6SSwiMTHlNn6E1lq4wOJ+n6NGTVAVsM1tj7VbC5GW5UTasAh6TJsxWJtSWYMm2cFLpSkvE5GZc5V 3J+cheDD7bwijgBiq2hL5Gc1b+ww5Ctl22VR8mdnT76CPsKbSv1t5rj5HhI9nko7nBtJprI4Upj4 ZP7lUdOjaAj5uAbgq50T5Yi2aZW7ykBjlW/NP3ZVEbFYtGPnxtjwkzV6k6sE7SL/9cHrWRFiaFvX os9pAFYoNAl2PiecbwCGNKakIGrfVs2L+fR5fEdMjvKcVm/QkCX9+pVFT3IKMjPzo0CAzdTN5T44 79ymaCFuq5ctVh8PZvjwM6b+5+QGzWoGpZQ6kVv1Z90+ov5lSXDnkWTp9nff4QPkkfWiR+9/dKZq PzyCLx4sqOGsKpeIE78R4eGqHF9XJu2FTRYxYBR3VsSyC1wzU18xSOE9CrL/jjVtmwpNudH7h5mc yzTfxrEFO+lFxdzi4vHcdqTcOjY8DjcTj2NI/ZUKeIk6yomRWF3alfJr7f8jdK0V0UVjsTwNlJqe oxasB3SG0DDa614IOa3Rvh0enEw0OEGR33FM2AVPXI4p7n0CeJumWFTzxlBzox25l3X1hELwX87R wsSnH8KJ69+bBrR2vQcs1hiCyIlE2CMbYj3B3KrUjVa7EgHDxdO8G9eQdlgUjbPWojN70xxzRyER AH6vSCAVqM379SmGPVyUmEh9BdbLh0TaVKuFVLrKlicwyq+gpXGefcJI7c7C6miYvcf8d+EttZgD SJ3qsOXHT4erEC13hpEmICN7GlgbahW2I3uz89O9T10pBe1WAw10JeyFUIQSTwkAIqaMIeMvp1YP zaRnos4m+KVAEUXg8XRFjzQ+kCNhfI1LoS136xUYJCtU+O+YA+Wu9/VVKk0DpC+dvua8OniAJCPi p1DfavRR22YNBfmaMK3A7PGg5yuzwnHd9lPV2mQdaUQOllAXhZdTimkt2Yx/MdAGxjEfpbkSptg8 ckvT6uRbEzcXENptJ1qh1bKgoRztFZi+63yPbJ5itrmFskqT3s8lhIJYTQEohxRl8HMrYxNMkTga BWh05YxgrBjlf8Yms0twkCErNCErYDrmPzbRErJVHcIYRrfWXl+qLfUpcm7dgW+ybZD1Zj0R4/Tq KzS0ARECVsY1Y8dmTHpbTU9h7Dc1b5MnSM2UHqD5RuFpUl1sDuysC2EXzajxpOYT40ESXe60oeSo pmZZjmDW7S7zw2vDpDPI+KYy2gP7QlryMdo8mW2m4dqmpZjAGZ+RdJkoIZ1IqRgHj0aJ1XVzSeDP Gtib+kFlINXfebEN5OUHOaaDEEvA+RgL4Vnx2xM3eltW8dSQ4AAFO+BYlTU+4Kl4SceS6G80Z3aX k/drFQoldBO8f3M2/Qff/HbHSzA2erYxlOkz01mXIQ2LQQoahftFMT2BIyRhif2cxJkWVarkdKPi IiNAJum2dQPD3dMscUVYOGx0sUWWQwWzZ+yPWvRGttVLtrFZSKGv7fTzAg6jNgFdPo+Hvp8kTQ+n dJoC/3WUt4edB0Kq3ZaBuDFKWxbxEjwj4ktHbn8MTPo3fz9uvQ8aRF3kwcKsWDjX3o1WnLTPiTzM Cl4dqxp25JozQIUNPu9zoe6NYYmYt8oOo8Zlx9KmQ+bzagP2YsvKnCsNNYdLObxFJzY+T7DqxRqo lhau2kZbmZogNCLvHnlLE/SMtJRFSiTIFBWai7YIwxQLNLr/QG2LqTO0eQZi5k3xPvUminilyMF3 IAX6E0Obj+dkUCvTx9nIgPCKEZ8vyeXUYDxLyDRx4MHOuaMstz3B725LJyeRTr/nvy+0gozWyWkD gY5BzOXHDlpA3KgAeSel3cl3RRReEdgMBi4BmCUiomTRcFyqVnCQkbsPbuoOoop/0PJDcVOy2ajW 3nUZhf5FRYyOfOp+Axla9ROXe03z5LENYiitoLj/DjAJ6SmN4SRlUnTKaGpUz5kKfTr3m6jCrODq gi2JigrTBCh19Qd+UboXt0ZIeCq5/Qhpa8dd2xKqYmyI4BAMkeViwbNJgSeRsjiKjR4JZ768A0v+ VUfdctR+j5VDjKWhzFId7dVXsjdxHT42r1HPqflmndz/r1LpOnTzweinM/4di7Wkr+dZ+Rq3JMQI vrwmSPbK21lfLhAiwwJjpnd2ZTO61Fzo6griavE8WsjykGfjEt9hNR1XkJGlC8ja4LGjrWxoxpY5 sAqKtyVnlGiAi9Sn2a5F16omjk2WGCfeu3jg81TJin+U9rYTKfRJf2CLyvF+4AJahrK6XnL32D5Y xHg3ZfiqY0TFJQcZfF3FcmHXZ+NZNSvtgh40MTEUQ+y0jo6eZxftxgjWtJgNJafauvNCPpxJP0Sn aVUzloAypEAMQ9mJi2irwSeqZMDo3WCwgPoqC6qYPGXpxWzQbziM6BHOau0DwxOI2ZjWSnPqZ3SQ xFRUPg+sLXfLNwiGLkRpaRO/om69byp0dR9iIUKAJ0n9wQUn/5hfhZy37ne+3lvG/+kit51c3RJ3 rh2qAhzNQHwWGhsy63Ptsc90tgN7RFIcqvVjFRWEtfrK0QkFSx9ORmmpKtGJGWm7eExOPYdvJGfq 8zcXCS0WC/nBZJwYS4AnaqJP8ZMbENCfrqes56NrQotQKc68X+lUrYEQYic2bVV8QuWh0WWwytAY 3+lz9Uj5D5xrZA9RoAAubpFRzm2CI5+NWuUHjbJ7rEFb2JvoRzmxmftXQAGxBubYIQKxMjlUd3i4 jr4m/KKirs+sRQEIRQYxIPvy7NCPB8kAl+ArjTKiCzEcE5lw25c9z7dxgPAA4J1yXoz0jQpis1a4 dqau0rsldCz8VhwpV5C9vemzZXK9yH8DlTwB3K6c+pRFDsZf1PgqxWnrd5+eXqhyGEIFKcjhIB0G x+PM2DI4HIy471DoA3WH0q7uPyZkGFvFw5/Wz1QJL8mh/hJ0kix9XZXG/kEAPAVvOdTjWIoWdw2h W5hOXAjh5Pijq1j83uDZRC4flBxbPGSwkZlyQZeNJrvglpY0PRxk57KgRBVsvDEHYeuj0oWmFWVz WYj8NNVDE7+UiO2OLr8rujAqtGgzbO4d9WmyUsmguSkXMyLICbyDF3ZaVmiV2nlmfOPt1qjO2g27 KbUEZBv/fETkx/62BH7gV5mgVq1KotxpjqObU3jtlrD8z/Pia9NuZVdgYCqhSfwr6fukrWKJiHIm tOHMeFWpKl0AZzF3PiFVZ3i//+fr4btX3H64mmitmf6VIAx8CzIuNjH8we2FORUdfxEPpbEHZ96x pqS3Hr0XoPBYHK/lsWTwfQ2U5R0IYDs0YKGRyr1mzJdjLpMrmvIbZWJ2qrBluC8hvB2YVfu3i9Ap 2Lz2+Fzq9zsqyKQVre/6IzuBcL3HX2eI9wEprlx6cpt/LH/3IeUzTYbTzYggZIxx3x3bcLo7FSCf gmkC/hPp/CLVIKmHnndtEVfcGBXPAFIg3A+BSqO8boyxifU8hApfBwgOi+MT+cHPkPEZJ57kJ2+i Zr3hXSUNSmd/7Th5Vur0Jk//fYW6hXq6vs4hANRgo33Mn4rY0tDAG4Z3ELqDvqf/QsHkmadk5Yxq 5Zwuds59VxUyTYa8fP5vQRDxwo+rozBfOvmazdlvXSMrHQBS6VcCwO1Rd9nqR1JARcpTXztJN3V4 j1spZZv/JabHchaW4M4+jIAPqGqkLy/KaOXlLN0E0MJmg6hGhL57DxFTnukUQq7bdwplug9fOzTi Y6s8HDhsgSAadqI0rJTe/IZe63+8hya6mqxhm1wTXZmxBBeMH5kJ58BFRX4YEMQ8bsegfCrWQw5W WYajcMOirtW4JfAVoYQ68UVfQJN/f/G5Jkwq0KQx5RtkSzUCSkEIDrc0wwL3ZfZDw4yidJaZPMXP PEqvsh3MdZWtR3DH7BcE4TzdFJlrW/8LH7IJrn5DZbxtLZGCkdPwKeRg+CJXA8PuWIiLE9MC11fB ISIIIvE7d66i2cN+9OnspxY/j513doPXlspn3QRfthiW4rSIVWmz/X1ocOhmHPE5flUNwD7hQCnp G3ZjMKnhLfT+bdqpFWrBsVvRzXcQTQyPqTQf/4IlUlZ2uhnMeEQDQyNIUo3F6uTRnuwi0VF68RT5 YlPP8pvuWkbcU73r/GRPfk8TEmlVBFZSfhd9nMKfGyjm+DR3rA4P4bQEKbxV/6YyyWLPkF+oRWLT Da/I3n+DiboxgPIbKibWKSdvDvEWRCWVgj7VaYZOc066U1kWKuXN3iCilxXtBOy2Vk39niGorpHT ptJLlqpy031fONMPWEZvDHx5504i37cwTm5aH0fJqfGU1BsOMbRST64qJTwfqq/EEbGT91qRRgHc s9QTpmaviqjEK/xu+HW7epiDnVckheK3HOMZSd6v/KTgIZfyhGFq7tINzKvgWArOrHE4tDmg+Q0G 87T9WmFdhVYwBnR+6+mR224AeiN3TJezMyf6f4SPs4jsLb2jNZ92q/dgrkLhtS7GURXmw9fwD0EM Zf5lOlEDMWJ1TWd9ouvmovW2jcGj8I6Po0dDLDtyf1K7rzBP1L7SjaB0sX1xwhRFL0DUtgOVkghG 5dzpNLzaa8iMpkpFMRbpGJb35FZM1sYNMUvkO/tkiHkl4SjLbya9VP1RfW9SvLyZEkMo8OLyPStj UWa8gU8EFq9CV6VBiQBNXvYzsaCJ8Ex/eBqUuNXHyuKmbWkjpMo3i5SQyPHVv0SM694XROJUrWz4 FfCdqSMKWlQv+p0URQkoC2H51obUt7Y+xZXUOpJtB54fARJV4/nmuD5ry2Ec99WP6U0vBhTMNb9E J9hIksiSuadjhOOzlLq0efU5OMHpw5NzLc0y8i4AaVpoxREkxW2FlAj4UuZGKsavpBgdGXNxB1pp ZYUSEk0wz96MEGcShpJBiabt3ClxoIj0qC8BuzX7UuV5y66lPGiNJ73+npFWKeg0O7mO4MNLvG7u yT15s0/caDxpqNR2k9lrxYCniZ8dkyL9j+Bq+HB1Q79F+U0rfwODw2DZyB67Ud7MvejS3MGTld5K f2iyQrznAzOGSlnIL4FdhRvvcpk+M150V8hLZyr85J9b0wIoKwzy+Zug4pDRO+16w52KvM2p2HOZ tM2nU/52SJPdc09xgwY32b1oxTXgQlvXV9V8OPZ7VuAlATLNU7id/Nrqb3DMGdoMK6OcFJrS2lyi DMS4Sb4Eztyf3wOZCatr/Va2TjxUYQZs/r+xyzuyiSynBQMDjIWgO1sCL8+d/+pCa9VMpGe8fgP8 KUKc+d6IOyJgwiQhVOL4iSYZnSKShIVbSHlRHFGlUP1sjujxrRXpL0DTbBNsPzl9Hp6Kv8vt/oPR D4doRDC3c+P+VJ7GGvImIwfLh30tznY/5lJ6KwofxGuMsnAIWM0oFxZXeiA15QlTEBYSjAoQSecD v6uq3MWftzJORELrKpsuxhtrAulnyc0aSzMF7scoctlyHgA4r4WAawH8sKIlrOqmAR4DPsw87a69 l4vI593Pc8jNL0ER6sT5d1xShZ2yrWeu0iqI+bGWk8Xd0DQkOlD5/GscZAuRaKagoFVrAk0xa2wG D07tjlIPBZ2klK473ZQrMBvWLU10xY+utPfJPSl98jWDHHBqSRWpOVkFW2zyUiojIWscGjYkHJe1 UmGx1fFai5esGyvQ8bJnmuhXP6EeudwRWMA58+zMaZmlxrGJLoIEtR3MImOlgncFGZRySKW+wOI0 ztrRv/eShX4Y5t83Tim5ncqUeEtAM2JZo+M7BMFgL0D0BdF346OCF0vAHjv7V0YbKPit0ayLUWdC MSCEH8zOTyY6ZQTpacnPVND4nATSJki3LaovTh85Zd9Azm6RL1B7a/+IW/qOgFalYLXt3MIUgKSq /X00iqcStk82wjKYlRkwJPDAI92+R8mM+GJMLoiSxRM2FG6oclkAop+d177XcANczeERHjCUHRZK OX9KlcB7+Galr9Xss6waWY70CdvywqCp6hN/lNZKk5X1g5m76ZNltQpmCPJDPUYdsLVGk/UhRrUx xFWAQopiAM6aGZlpe6egfLf+60ydM5P7Ql8VNLWT0aKcmYQXXCHwoyb+wmMPb98gqWGUck1D2pNO ksju+obZR7K1zTJQDc07/KLpxpXxe3swzFrdQReKXgCUDGKettDzAaH8B1sLF5ZyJp9RghNRDLAG Lo5LgIZor4W8Pqc0NGnB6zJYvgF+2ahlRpnHZrM58P6cMzuduSeOyMqhgg2CkvtXln0N05Mc0HSA 5No3fWywactl1G5nHOYFVH4xHEzRQ+ZGnnnZ2pBSFNejLJE7sKs45ySj0BC3R7Mf2JQbdmTvD304 rr1a7FwNtVi5y1FzzlElO5QWeRzo6znJ3Cs4fmXa9MriRY70B5OrgyT62IaZhgbjMt71lGHU `protect end_protected

mit

71790a5e36c1d3a7a83955d86649eab8

joalcava/sparcv8-monocicle

DM.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DataMemory is Port ( enableMem : in STD_LOGIC; reset : in STD_LOGIC; cRD : in STD_LOGIC_VECTOR (31 downto 0); address : in STD_LOGIC_VECTOR (31 downto 0); wrEnMem : in STD_LOGIC; datoToWr : out STD_LOGIC_VECTOR (31 downto 0) ); end DataMemory; architecture arqDataMemory of DataMemory is type ram_type is array (0 to 63) of std_logic_vector (31 downto 0); signal ramMemory : ram_type:=(others => x"00000000"); begin process(enableMem,reset,cRD,address,wrEnMem) begin if(enableMem = '1') then if(reset = '1')then datoToWr <= (others => '0'); ramMemory <= (others => x"00000000"); else if(wrEnMem = '0')then datoToWr <= ramMemory(conv_integer(address(5 downto 0))); else ramMemory(conv_integer(address(5 downto 0))) <= cRD; end if; end if; end if; end process; end arqDataMemory;

gpl-3.0

791f6fe907e0ee0109301231942cbf63

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_Atomic_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant ATOMIC_IMPLEMENT : natural := 1; constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

3399b5be760eb0668a77ebe0bac91ba3

joalcava/sparcv8-monocicle

Sparcv8Monocicle.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Sparcv8Monocicle is Port ( CLK : in STD_LOGIC; RST: in STD_LOGIC; R : out STD_LOGIC_VECTOR(31 downto 0) ); end Sparcv8Monocicle; architecture Behavioral of Sparcv8Monocicle is ---Componentes COMPONENT windows_manager PORT( cwp : IN std_logic; rs1 : IN std_logic_vector(4 downto 0); rs2 : IN std_logic_vector(4 downto 0); rd : IN std_logic_vector(4 downto 0); op : IN std_logic_vector(1 downto 0); op3 : IN std_logic_vector(5 downto 0); nrs1 : OUT std_logic_vector(5 downto 0); nrs2 : OUT std_logic_vector(5 downto 0); nrd : OUT std_logic_vector(5 downto 0); ncwp : OUT std_logic ); END COMPONENT; COMPONENT psr PORT( clk : IN std_logic; reset : IN std_logic; nzvc : IN std_logic_vector(3 downto 0); ncwp : IN std_logic; carry : OUT std_logic; cwp : OUT std_logic ); END COMPONENT; COMPONENT psr_modifier PORT( crs1 : IN std_logic; ope2 : IN std_logic; alur : IN std_logic_vector(31 downto 0); aluop : IN std_logic_vector(5 downto 0); nzvc : OUT std_logic_vector(3 downto 0) ); END COMPONENT; COMPONENT sum32b PORT( Op1 : IN std_logic_vector(31 downto 0); Op2 : IN std_logic_vector(31 downto 0); R : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT alu PORT( carry : IN std_logic; aluop : IN std_logic_vector(5 downto 0); crs1 : IN std_logic_vector(31 downto 0); crs2 : IN std_logic_vector(31 downto 0); r : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT control_unit PORT( op : IN std_logic_vector(1 downto 0); op2 : IN std_logic_vector(2 downto 0); op3 : IN std_logic_vector(5 downto 0); icc : IN std_logic_vector(3 downto 0); cond : IN std_logic_vector(3 downto 0); Aluop : OUT std_logic_vector(5 downto 0); wrenDM : OUT std_logic; RFSource : OUT std_logic_vector(1 downto 0); PCSource : OUT std_logic_vector(1 downto 0); RFdest : OUT std_logic; write_enable : OUT std_logic ); END COMPONENT; COMPONENT instructionMemory PORT( address : IN std_logic_vector(31 downto 0); reset : IN std_logic; outInstruction : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT mux32b PORT( A : IN std_logic_vector(31 downto 0); B : IN std_logic_vector(31 downto 0); Sel : IN std_logic; O : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT pc PORT( clk : IN std_logic; rst : IN std_logic; address : IN std_logic_vector(31 downto 0); sig : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT register_file PORT( Wren : IN std_logic; rst : IN std_logic; rs1 : IN std_logic_vector(5 downto 0); rs2 : IN std_logic_vector(5 downto 0); rd : IN std_logic_vector(5 downto 0); data : IN std_logic_vector(31 downto 0); crs1 : OUT std_logic_vector(31 downto 0); crs2 : OUT std_logic_vector(31 downto 0); crd : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT sign_ext_unit PORT( entrada : IN std_logic_vector(12 downto 0); salida : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT SEUDisp30 PORT( Disp30 : IN std_logic_vector(29 downto 0); S : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT SEUDisp22 PORT( Disp22 : IN std_logic_vector(21 downto 0); S : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT MuxPC PORT( PCdisp30 : IN std_logic_vector(31 downto 0); PCdisp22 : IN std_logic_vector(31 downto 0); PC : IN std_logic_vector(31 downto 0); PCplus1 : IN std_logic_vector(31 downto 0); PCSource : IN std_logic_vector(1 downto 0); nPC : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT MuxNextRD PORT( RD : IN std_logic_vector(5 downto 0); O7 : IN std_logic_vector(5 downto 0); RfDest : IN std_logic; NRd : OUT std_logic_vector(5 downto 0) ); END COMPONENT; COMPONENT MuxDWR PORT( DM : IN std_logic_vector(31 downto 0); AluR : IN std_logic_vector(31 downto 0); PC : IN std_logic_vector(31 downto 0); RFSource : IN std_logic_vector(1 downto 0); DTRF : OUT std_logic_vector(31 downto 0) ); END COMPONENT; COMPONENT DataMemory PORT( enableMem : IN std_logic; reset : IN std_logic; cRD : IN std_logic_vector(31 downto 0); address : IN std_logic_vector(31 downto 0); wrEnMem : IN std_logic; datoToWr : OUT std_logic_vector(31 downto 0) ); END COMPONENT; signal aux1,aux2,aux3,aux4,aux6,aux7,aux9,aux10,aux11,aux20,aux21,aux22,aux23,aux25,aux29,aux30,aux32:std_logic_vector(31 downto 0); signal aux5,aux14,aux15,aux16,aux27:std_logic_vector(5 downto 0); signal aux12,aux17,aux18,aux26,aux28,aux31: std_logic; signal aux24,aux34,aux33: std_logic_vector(1 downto 0); signal aux13:std_logic_vector(3 downto 0); begin ---Instancia de los componentes Inst_SEUDisp30: SEUDisp30 PORT MAP( Disp30 => aux4(29 downto 0), S => aux20 ); Inst_SEUDisp22: SEUDisp22 PORT MAP( Disp22 => aux4(21 downto 0), S => aux21 ); Inst_MuxPC: MuxPC PORT MAP( PCdisp30 => aux23, PCdisp22 => aux22, PC => aux3, PCplus1 => aux2, PCSource => aux24, nPC => aux25 ); Inst_MuxNextRD: MuxNextRD PORT MAP( RD => aux16, O7 => "001111", RfDest => aux26, NRd => aux27 ); Inst_MuxDWR: MuxDWR PORT MAP( DM => aux32, AluR => aux30, PC => aux3, RFSource => aux33, DTRF => aux10 ); Inst_DataMemory: DataMemory PORT MAP( enableMem => '1', reset => RST, cRD => aux29, address => aux30, wrEnMem => aux31, datoToWr => aux32 ); Inst_windows_manager: windows_manager PORT MAP( cwp => aux18, rs1 => aux4(18 downto 14), rs2 => aux4(4 downto 0), rd => aux4(29 downto 25), op => aux4(31 downto 30), op3 => aux4(24 downto 19), nrs1 => aux14, nrs2 => aux15, nrd => aux16, ncwp => aux17 ); Inst_psr: psr PORT MAP( clk => CLK, reset => RST, nzvc => aux13, ncwp => aux17, carry => aux12, cwp => aux18 ); Inst_psr_modifier: psr_modifier PORT MAP( crs1 => aux6(31), ope2 => aux9(31), alur => aux30, aluop => aux5, nzvc => aux13 ); Inst_sumPC: sum32b PORT MAP( Op1 => x"00000001", Op2 => aux1, R => aux2 ); Inst_sumDisp22: sum32b PORT MAP( Op1 => aux21, Op2 => aux3, R => aux22 ); Inst_sumDisp30: sum32b PORT MAP( Op1 => aux20, Op2 => aux3, R => aux23 ); Inst_alu: alu PORT MAP( carry => aux12, aluop => aux5, crs1 => aux6, crs2 => aux9, r => aux30 ); Inst_control_unit: control_unit PORT MAP( op => aux4(31 downto 30), op2 => aux4(24 downto 22), op3 => aux4(24 downto 19), icc => aux13, cond => aux4(28 downto 25), Aluop => aux5, wrenDM => aux31, RFSource => aux33, PCSource => aux24, RFdest => aux26, write_enable => aux28 ); Inst_instructionMemory: instructionMemory PORT MAP( address => aux3, reset => RST, outInstruction => aux4 ); Inst_mux32b: mux32b PORT MAP( A => aux7, B => aux11, Sel => aux4(13), O => aux9 ); Inst_pc: pc PORT MAP( clk => CLK, rst => RST, address => aux1, sig => aux3 ); Inst_npc: pc PORT MAP( clk => CLK, rst => RST, address => aux25, sig => aux1 ); Inst_register_file: register_file PORT MAP( Wren => aux28, rst => RST, rs1 => aux14, rs2 => aux15, rd => aux27, data => aux10, crs1 => aux6, crs2 => aux7, crd => aux29 ); Inst_sign_ext_unit: sign_ext_unit PORT MAP( entrada => aux4(12 downto 0), salida => aux11 ); R<=aux30; end Behavioral;

gpl-3.0

655d9ed71284db31feb668f2b6b5ba44

malkadi/FGPU

HW/sources/IPs/FGPU_2.1/hdl/FGPU_v2_1.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; library xil_defaultlib; use xil_defaultlib.all; ------------------------------------------------------------------------------------------------- }}} entity FGPU_v2_1 is -- generics {{{ generic ( -- Users to add parameters here -- User parameters ends -- Do not modify the parameters beyond this line -- Parameters of Axi Slave Bus Interface S0 C_S0_DATA_WIDTH : integer := 32; C_S0_ADDR_WIDTH : integer := 16; -- Parameters of Axi Master Bus Interface M0 C_M0_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000"; C_M0_BURST_LEN : integer := 8; C_M0_ID_WIDTH : integer := 6; C_M0_ADDR_WIDTH : integer := 32; C_M0_DATA_WIDTH : integer := 64; C_M0_AWUSER_WIDTH : integer := 0; C_M0_ARUSER_WIDTH : integer := 0; C_M0_WUSER_WIDTH : integer := 0; C_M0_RUSER_WIDTH : integer := 0; C_M0_BUSER_WIDTH : integer := 0; -- Parameters of Axi Master Bus Interface M1 C_M1_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000"; C_M1_BURST_LEN : integer := 8; C_M1_ID_WIDTH : integer := 6; C_M1_ADDR_WIDTH : integer := 32; C_M1_DATA_WIDTH : integer := 64; C_M1_AWUSER_WIDTH : integer := 0; C_M1_ARUSER_WIDTH : integer := 0; C_M1_WUSER_WIDTH : integer := 0; C_M1_RUSER_WIDTH : integer := 0; C_M1_BUSER_WIDTH : integer := 0; -- Parameters of Axi Master Bus Interface M2 C_M2_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000"; C_M2_BURST_LEN : integer := 8; C_M2_ID_WIDTH : integer := 6; C_M2_ADDR_WIDTH : integer := 32; C_M2_DATA_WIDTH : integer := 64; C_M2_AWUSER_WIDTH : integer := 0; C_M2_ARUSER_WIDTH : integer := 0; C_M2_WUSER_WIDTH : integer := 0; C_M2_RUSER_WIDTH : integer := 0; C_M2_BUSER_WIDTH : integer := 0; -- Parameters of Axi Master Bus Interface M3 C_M3_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000"; C_M3_BURST_LEN : integer := 8; C_M3_ID_WIDTH : integer := 6; C_M3_ADDR_WIDTH : integer := 32; C_M3_DATA_WIDTH : integer := 64; C_M3_AWUSER_WIDTH : integer := 0; C_M3_ARUSER_WIDTH : integer := 0; C_M3_WUSER_WIDTH : integer := 0; C_M3_RUSER_WIDTH : integer := 0; C_M3_BUSER_WIDTH : integer := 0 ); --}}} -- ports {{{ port ( -- Users to add ports here -- User ports ends -- Do not modify the ports beyond this line -- Ports of Axi Slave Bus Interface S0 {{{ s0_aclk : in std_logic; s0_aresetn : in std_logic; s0_awaddr : in std_logic_vector(C_S0_ADDR_WIDTH-1 downto 0); s0_awprot : in std_logic_vector(2 downto 0); s0_awvalid : in std_logic; s0_awready : out std_logic; s0_wdata : in std_logic_vector(C_S0_DATA_WIDTH-1 downto 0); s0_wstrb : in std_logic_vector((C_S0_DATA_WIDTH/8)-1 downto 0); s0_wvalid : in std_logic; s0_wready : out std_logic; s0_bresp : out std_logic_vector(1 downto 0); s0_bvalid : out std_logic; s0_bready : in std_logic; s0_araddr : in std_logic_vector(C_S0_ADDR_WIDTH-1 downto 0); s0_arprot : in std_logic_vector(2 downto 0); s0_arvalid : in std_logic; s0_arready : out std_logic; s0_rdata : out std_logic_vector(C_S0_DATA_WIDTH-1 downto 0); s0_rresp : out std_logic_vector(1 downto 0); s0_rvalid : out std_logic; s0_rready : in std_logic; -- }}} -- Ports of Axi Master Bus Interface M0 {{{ m0_aclk : in std_logic; m0_aresetn : in std_logic; m0_awid : out std_logic_vector(C_M0_ID_WIDTH-1 downto 0); m0_awaddr : out std_logic_vector(C_M0_ADDR_WIDTH-1 downto 0); m0_awlen : out std_logic_vector(7 downto 0); m0_awsize : out std_logic_vector(2 downto 0); m0_awburst : out std_logic_vector(1 downto 0); m0_awlock : out std_logic; m0_awcache : out std_logic_vector(3 downto 0); m0_awprot : out std_logic_vector(2 downto 0); m0_awqos : out std_logic_vector(3 downto 0); m0_awuser : out std_logic_vector(C_M0_AWUSER_WIDTH-1 downto 0); m0_awvalid : out std_logic; m0_awready : in std_logic; m0_wdata : out std_logic_vector(C_M0_DATA_WIDTH-1 downto 0); m0_wstrb : out std_logic_vector(C_M0_DATA_WIDTH/8-1 downto 0); m0_wlast : out std_logic; m0_wuser : out std_logic_vector(C_M0_WUSER_WIDTH-1 downto 0); m0_wvalid : out std_logic; m0_wready : in std_logic; m0_bid : in std_logic_vector(C_M0_ID_WIDTH-1 downto 0); m0_bresp : in std_logic_vector(1 downto 0); m0_buser : in std_logic_vector(C_M0_BUSER_WIDTH-1 downto 0); m0_bvalid : in std_logic; m0_bready : out std_logic; m0_arid : out std_logic_vector(C_M0_ID_WIDTH-1 downto 0); m0_araddr : out std_logic_vector(C_M0_ADDR_WIDTH-1 downto 0); m0_arlen : out std_logic_vector(7 downto 0); m0_arsize : out std_logic_vector(2 downto 0); m0_arburst : out std_logic_vector(1 downto 0); m0_arlock : out std_logic; m0_arcache : out std_logic_vector(3 downto 0); m0_arprot : out std_logic_vector(2 downto 0); m0_arqos : out std_logic_vector(3 downto 0); m0_aruser : out std_logic_vector(C_M0_ARUSER_WIDTH-1 downto 0); m0_arvalid : out std_logic; m0_arready : in std_logic; m0_rid : in std_logic_vector(C_M0_ID_WIDTH-1 downto 0); m0_rdata : in std_logic_vector(C_M0_DATA_WIDTH-1 downto 0); m0_rresp : in std_logic_vector(1 downto 0); m0_rlast : in std_logic; m0_ruser : in std_logic_vector(C_M0_RUSER_WIDTH-1 downto 0); m0_rvalid : in std_logic; m0_rready : out std_logic; --}}} -- Ports of Axi Master Bus Interface M1 {{{ m1_aclk : in std_logic; m1_aresetn : in std_logic; m1_awid : out std_logic_vector(C_M1_ID_WIDTH-1 downto 0); m1_awaddr : out std_logic_vector(C_M1_ADDR_WIDTH-1 downto 0); m1_awlen : out std_logic_vector(7 downto 0); m1_awsize : out std_logic_vector(2 downto 0); m1_awburst : out std_logic_vector(1 downto 0); m1_awlock : out std_logic; m1_awcache : out std_logic_vector(3 downto 0); m1_awprot : out std_logic_vector(2 downto 0); m1_awqos : out std_logic_vector(3 downto 0); m1_awuser : out std_logic_vector(C_M1_AWUSER_WIDTH-1 downto 0); m1_awvalid : out std_logic; m1_awready : in std_logic; m1_wdata : out std_logic_vector(C_M1_DATA_WIDTH-1 downto 0); m1_wstrb : out std_logic_vector(C_M1_DATA_WIDTH/8-1 downto 0); m1_wlast : out std_logic; m1_wuser : out std_logic_vector(C_M1_WUSER_WIDTH-1 downto 0); m1_wvalid : out std_logic; m1_wready : in std_logic; m1_bid : in std_logic_vector(C_M1_ID_WIDTH-1 downto 0); m1_bresp : in std_logic_vector(1 downto 0); m1_buser : in std_logic_vector(C_M1_BUSER_WIDTH-1 downto 0); m1_bvalid : in std_logic; m1_bready : out std_logic; m1_arid : out std_logic_vector(C_M1_ID_WIDTH-1 downto 0); m1_araddr : out std_logic_vector(C_M1_ADDR_WIDTH-1 downto 0); m1_arlen : out std_logic_vector(7 downto 0); m1_arsize : out std_logic_vector(2 downto 0); m1_arburst : out std_logic_vector(1 downto 0); m1_arlock : out std_logic; m1_arcache : out std_logic_vector(3 downto 0); m1_arprot : out std_logic_vector(2 downto 0); m1_arqos : out std_logic_vector(3 downto 0); m1_aruser : out std_logic_vector(C_M1_ARUSER_WIDTH-1 downto 0); m1_arvalid : out std_logic; m1_arready : in std_logic; m1_rid : in std_logic_vector(C_M1_ID_WIDTH-1 downto 0); m1_rdata : in std_logic_vector(C_M1_DATA_WIDTH-1 downto 0); m1_rresp : in std_logic_vector(1 downto 0); m1_rlast : in std_logic; m1_ruser : in std_logic_vector(C_M1_RUSER_WIDTH-1 downto 0); m1_rvalid : in std_logic; m1_rready : out std_logic; -- }}} -- Ports of Axi Master Bus Interface M2 {{{ m2_aclk : in std_logic; m2_aresetn : in std_logic; m2_awid : out std_logic_vector(C_M2_ID_WIDTH-1 downto 0); m2_awaddr : out std_logic_vector(C_M2_ADDR_WIDTH-1 downto 0); m2_awlen : out std_logic_vector(7 downto 0); m2_awsize : out std_logic_vector(2 downto 0); m2_awburst : out std_logic_vector(1 downto 0); m2_awlock : out std_logic; m2_awcache : out std_logic_vector(3 downto 0); m2_awprot : out std_logic_vector(2 downto 0); m2_awqos : out std_logic_vector(3 downto 0); m2_awuser : out std_logic_vector(C_M2_AWUSER_WIDTH-1 downto 0); m2_awvalid : out std_logic; m2_awready : in std_logic; m2_wdata : out std_logic_vector(C_M2_DATA_WIDTH-1 downto 0); m2_wstrb : out std_logic_vector(C_M2_DATA_WIDTH/8-1 downto 0); m2_wlast : out std_logic; m2_wuser : out std_logic_vector(C_M2_WUSER_WIDTH-1 downto 0); m2_wvalid : out std_logic; m2_wready : in std_logic; m2_bid : in std_logic_vector(C_M2_ID_WIDTH-1 downto 0); m2_bresp : in std_logic_vector(1 downto 0); m2_buser : in std_logic_vector(C_M2_BUSER_WIDTH-1 downto 0); m2_bvalid : in std_logic; m2_bready : out std_logic; m2_arid : out std_logic_vector(C_M2_ID_WIDTH-1 downto 0); m2_araddr : out std_logic_vector(C_M2_ADDR_WIDTH-1 downto 0); m2_arlen : out std_logic_vector(7 downto 0); m2_arsize : out std_logic_vector(2 downto 0); m2_arburst : out std_logic_vector(1 downto 0); m2_arlock : out std_logic; m2_arcache : out std_logic_vector(3 downto 0); m2_arprot : out std_logic_vector(2 downto 0); m2_arqos : out std_logic_vector(3 downto 0); m2_aruser : out std_logic_vector(C_M2_ARUSER_WIDTH-1 downto 0); m2_arvalid : out std_logic; m2_arready : in std_logic; m2_rid : in std_logic_vector(C_M2_ID_WIDTH-1 downto 0); m2_rdata : in std_logic_vector(C_M2_DATA_WIDTH-1 downto 0); m2_rresp : in std_logic_vector(1 downto 0); m2_rlast : in std_logic; m2_ruser : in std_logic_vector(C_M2_RUSER_WIDTH-1 downto 0); m2_rvalid : in std_logic; m2_rready : out std_logic; -- }}} -- Ports of Axi Master Bus Interface M3 {{{ m3_aclk : in std_logic; m3_aresetn : in std_logic; m3_awid : out std_logic_vector(C_M3_ID_WIDTH-1 downto 0); m3_awaddr : out std_logic_vector(C_M3_ADDR_WIDTH-1 downto 0); m3_awlen : out std_logic_vector(7 downto 0); m3_awsize : out std_logic_vector(2 downto 0); m3_awburst : out std_logic_vector(1 downto 0); m3_awlock : out std_logic; m3_awcache : out std_logic_vector(3 downto 0); m3_awprot : out std_logic_vector(2 downto 0); m3_awqos : out std_logic_vector(3 downto 0); m3_awuser : out std_logic_vector(C_M3_AWUSER_WIDTH-1 downto 0); m3_awvalid : out std_logic; m3_awready : in std_logic; m3_wdata : out std_logic_vector(C_M3_DATA_WIDTH-1 downto 0); m3_wstrb : out std_logic_vector(C_M3_DATA_WIDTH/8-1 downto 0); m3_wlast : out std_logic; m3_wuser : out std_logic_vector(C_M3_WUSER_WIDTH-1 downto 0); m3_wvalid : out std_logic; m3_wready : in std_logic; m3_bid : in std_logic_vector(C_M3_ID_WIDTH-1 downto 0); m3_bresp : in std_logic_vector(1 downto 0); m3_buser : in std_logic_vector(C_M3_BUSER_WIDTH-1 downto 0); m3_bvalid : in std_logic; m3_bready : out std_logic; m3_arid : out std_logic_vector(C_M3_ID_WIDTH-1 downto 0); m3_araddr : out std_logic_vector(C_M3_ADDR_WIDTH-1 downto 0); m3_arlen : out std_logic_vector(7 downto 0); m3_arsize : out std_logic_vector(2 downto 0); m3_arburst : out std_logic_vector(1 downto 0); m3_arlock : out std_logic; m3_arcache : out std_logic_vector(3 downto 0); m3_arprot : out std_logic_vector(2 downto 0); m3_arqos : out std_logic_vector(3 downto 0); m3_aruser : out std_logic_vector(C_M3_ARUSER_WIDTH-1 downto 0); m3_arvalid : out std_logic; m3_arready : in std_logic; m3_rid : in std_logic_vector(C_M3_ID_WIDTH-1 downto 0); m3_rdata : in std_logic_vector(C_M3_DATA_WIDTH-1 downto 0); m3_rresp : in std_logic_vector(1 downto 0); m3_rlast : in std_logic; m3_ruser : in std_logic_vector(C_M3_RUSER_WIDTH-1 downto 0); m3_rvalid : in std_logic; m3_rready : out std_logic -- }}} ); --}}} end FGPU_v2_1; architecture arch_imp of FGPU_v2_1 is signal nrst : std_logic := '0'; begin -- fixed signals ------------------------------------------------------------------------------------{{{ -- m0 {{{ m0_awlock <= '0'; --Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache. m0_awcache <= "0010"; m0_awprot <= "000"; m0_awqos <= X"0"; m0_arlock <= '0'; m0_arcache <= "0010"; m0_arprot <= "000"; m0_arqos <= X"0"; -- }}} -- m1 {{{ m1_awlock <= '0'; --Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache. m1_awcache <= "0010"; m1_awprot <= "000"; m1_awqos <= X"0"; m1_arlock <= '0'; m1_arcache <= "0010"; m1_arprot <= "000"; m1_arqos <= X"0"; --}}} -- m2 {{{ m2_awlock <= '0'; --Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache. m2_awcache <= "0010"; m2_awprot <= "000"; m2_awqos <= X"0"; m2_arlock <= '0'; m2_arcache <= "0010"; m2_arprot <= "000"; m2_arqos <= X"0"; -- }}} -- m3 {{{ m3_awlock <= '0'; --Update value to 4'b0011 if coherent accesses to be used via the Zynq ACP port. Not Allocated, Modifiable, not Bufferable. Not Bufferable since this example is meant to test memory, not intermediate cache. m3_awcache <= "0010"; m3_awprot <= "000"; m3_awqos <= X"0"; m3_arlock <= '0'; m3_arcache <= "0010"; m3_arprot <= "000"; m3_arqos <= X"0"; -- }}} ---------------------------------------------------------------------------------------------------------}}} process(s0_aclk) begin if rising_edge(s0_aclk) then nrst <= s0_aresetn and m0_aresetn and m1_aresetn and m2_aresetn and m3_aresetn; end if; end process; uut: entity FGPU PORT MAP ( clk => s0_aclk, -- slave axi {{{ s0_awaddr => s0_awaddr(C_S0_ADDR_WIDTH-1 downto 2), s0_awprot => s0_awprot, s0_awvalid => s0_awvalid, s0_awready => s0_awready, s0_wdata => s0_wdata, s0_wstrb => s0_wstrb, s0_wvalid => s0_wvalid, s0_wready => s0_wready, s0_bresp => s0_bresp, s0_bvalid => s0_bvalid, s0_bready => s0_bready, s0_araddr => s0_araddr(C_S0_ADDR_WIDTH-1 downto 2), s0_arprot => s0_arprot, s0_arvalid => s0_arvalid, s0_arready => s0_arready, s0_rdata => s0_rdata, s0_rresp => s0_rresp, s0_rvalid => s0_rvalid, s0_rready => s0_rready, -- }}} -- axi master 0 connections {{{ -- ar channel m0_araddr => m0_araddr, m0_arlen => m0_arlen, m0_arsize => m0_arsize, m0_arburst => m0_arburst, m0_arvalid => m0_arvalid, m0_arready => m0_arready, m0_arid => m0_arid, -- r channel m0_rdata => m0_rdata, m0_rresp => m0_rresp, m0_rlast => m0_rlast, m0_rvalid => m0_rvalid, m0_rready => m0_rready, m0_rid => m0_rid, -- aw channel m0_awvalid => m0_awvalid, m0_awaddr => m0_awaddr, m0_awready => m0_awready, m0_awlen => m0_awlen, m0_awsize => m0_awsize, m0_awburst => m0_awburst, m0_awid => m0_awid, -- w channel m0_wdata => m0_wdata, m0_wstrb => m0_wstrb, m0_wlast => m0_wlast, m0_wvalid => m0_wvalid, m0_wready => m0_wready, -- b channel m0_bvalid => m0_bvalid, m0_bready => m0_bready, m0_bid => m0_bid, -- }}} -- axi master 1 connections {{{ -- ar channel m1_araddr => m2_araddr, m1_arlen => m2_arlen, m1_arsize => m2_arsize, m1_arburst => m2_arburst, m1_arvalid => m2_arvalid, m1_arready => m2_arready, m1_arid => m2_arid, -- r channel m1_rdata => m2_rdata, m1_rresp => m2_rresp, m1_rlast => m2_rlast, m1_rvalid => m2_rvalid, m1_rready => m2_rready, m1_rid => m2_rid, -- aw channel m1_awvalid => m2_awvalid, m1_awaddr => m2_awaddr, m1_awready => m2_awready, m1_awlen => m2_awlen, m1_awsize => m2_awsize, m1_awburst => m2_awburst, m1_awid => m2_awid, -- w channel m1_wdata => m2_wdata, m1_wstrb => m2_wstrb, m1_wlast => m2_wlast, m1_wvalid => m2_wvalid, m1_wready => m2_wready, -- b channel m1_bvalid => m2_bvalid, m1_bready => m2_bready, m1_bid => m2_bid, -- }}} -- axi master 2 connections {{{ -- ar channel m2_araddr => m1_araddr, m2_arlen => m1_arlen, m2_arsize => m1_arsize, m2_arburst => m1_arburst, m2_arvalid => m1_arvalid, m2_arready => m1_arready, m2_arid => m1_arid, -- r channel m2_rdata => m1_rdata, m2_rresp => m1_rresp, m2_rlast => m1_rlast, m2_rvalid => m1_rvalid, m2_rready => m1_rready, m2_rid => m1_rid, -- aw channel m2_awvalid => m1_awvalid, m2_awaddr => m1_awaddr, m2_awready => m1_awready, m2_awlen => m1_awlen, m2_awsize => m1_awsize, m2_awburst => m1_awburst, m2_awid => m1_awid, -- w channel m2_wdata => m1_wdata, m2_wstrb => m1_wstrb, m2_wlast => m1_wlast, m2_wvalid => m1_wvalid, m2_wready => m1_wready, -- b channel m2_bvalid => m1_bvalid, m2_bready => m1_bready, m2_bid => m1_bid, -- }}} -- axi master 3 connections {{{ -- ar channel m3_araddr => m3_araddr, m3_arlen => m3_arlen, m3_arsize => m3_arsize, m3_arburst => m3_arburst, m3_arvalid => m3_arvalid, m3_arready => m3_arready, m3_arid => m3_arid, -- r channel m3_rdata => m3_rdata, m3_rresp => m3_rresp, m3_rlast => m3_rlast, m3_rvalid => m3_rvalid, m3_rready => m3_rready, m3_rid => m3_rid, -- aw channel m3_awvalid => m3_awvalid, m3_awaddr => m3_awaddr, m3_awready => m3_awready, m3_awlen => m3_awlen, m3_awsize => m3_awsize, m3_awburst => m3_awburst, m3_awid => m3_awid, -- w channel m3_wdata => m3_wdata, m3_wstrb => m3_wstrb, m3_wlast => m3_wlast, m3_wvalid => m3_wvalid, m3_wready => m3_wready, -- b channel m3_bvalid => m3_bvalid, m3_bready => m3_bready, m3_bid => m3_bid, -- }}} nrst => nrst ); end arch_imp;

gpl-3.0

82be568a0f583d9fafc3942274b061b9

preusser/q27

src/vhdl/queens/queens_slice0_tb.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2016 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This testbench is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- entity queens_slice0_tb is generic ( N : positive := 16 -- Choose your board size ); end queens_slice0_tb; library IEEE; use IEEE.std_logic_1164.all; architecture tb of queens_slice0_tb is component queens_slice generic ( N : positive; -- size of field L : natural -- number of preplaced columns ); port ( clk : in std_logic; rst : in std_logic; start : in std_logic; BH_l : in std_logic_vector(0 to N-2*L-1); BU_l : in std_logic_vector(0 to 2*N-4*L-2); BD_l : in std_logic_vector(0 to 2*N-4*L-2); BV_l : in std_logic_vector(0 to N-2*L-1); sol : out std_logic; done : out std_logic ); end component; --Inputs signal clk : std_logic; signal rst : std_logic; signal start : std_logic; --Outputs signal sol : std_logic; signal done : std_logic; begin dut: queens_slice generic map ( N => N, L => 0 ) port map ( clk => clk, rst => rst, start => start, BH_l => (others => '0'), BV_l => (others => '0'), BU_l => (others => '0'), BD_l => (others => '0'), sol => sol, done => done ); -- Driver process procedure cycle is begin clk <= '0'; wait for 5 ns; clk <= '1'; wait for 5 ns; end; begin rst <= '1'; cycle; rst <= '0'; start <= '0'; cycle; start <= '1'; cycle; start <= '0'; while done = '0' loop cycle; end loop; cycle; wait; -- forever end process; -- Log and Report process variable cycs : natural; variable sols : natural; begin cycs := 0; sols := 0; wait until rising_edge(clk) and start = '1'; loop wait until rising_edge(clk); cycs := cycs + 1; if sol = '1' then sols := sols + 1; end if; exit when done = '1'; end loop; report "Found "&integer'image(sols)& " solutions in "&integer'image(cycs)&" clock cycles."; end process; end tb;

agpl-3.0

e97808ced03b3916b71330b31e9a4891

jpidancet/mips

rtl/cpu_execute.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; library work; use work.mips_defs.ALL; entity cpu_execute is port (rt : in std_logic_vector(4 downto 0); rd : in std_logic_vector(4 downto 0); shamt : in std_logic_vector(4 downto 0); imm : in std_logic_vector(31 downto 0); alusrc : in std_logic; regdst : in std_logic; alucontrol : in alucontrol_type; ovf_en : in std_logic; rd1 : in std_logic_vector(31 downto 0); rd2 : in std_logic_vector(31 downto 0); regwrite : in std_logic; memtoreg : in std_logic; memread : in std_logic; memwrite : in std_logic; regwrite_n : out std_logic; memtoreg_n : out std_logic; memread_n : out std_logic; memwrite_n : out std_logic; aluout_n : out std_logic_vector(31 downto 0); writedata_n : out std_logic_vector(31 downto 0); writereg_n : out std_logic_vector(4 downto 0); -- Forward forward_a : in std_logic_vector(1 downto 0); forward_b : in std_logic_vector(1 downto 0); aluout_fwd : in std_logic_vector(31 downto 0); result_fwd : in std_logic_vector(31 downto 0)); end entity cpu_execute; architecture rtl of cpu_execute is component alu is port (op : in alucontrol_type; a : in std_logic_vector(31 downto 0); b : in std_logic_vector(31 downto 0); shift : in std_logic_vector(5 downto 0); result : out std_logic_vector(31 downto 0); overflow : out std_logic); end component alu; signal writedata : std_logic_vector(31 downto 0); signal srca : std_logic_vector(31 downto 0); signal srcb : std_logic_vector(31 downto 0); signal overflow : std_logic; signal interrupt : std_logic; begin srca <= aluout_fwd when forward_a = "10" else result_fwd when forward_a = "01" else rd1; writedata <= aluout_fwd when forward_b = "10" else result_fwd when forward_b = "01" else rd2; srcb <= imm when alusrc = '1' else writedata; regwrite_n <= regwrite; memtoreg_n <= memtoreg; memread_n <= memread; memwrite_n <= memwrite; writedata_n <= writedata; writereg_n <= rd when regdst = '1' else rt; alu0: alu port map (op => alucontrol, a => srca, b => srcb, shift => shamt, result => aluout_n, overflow => overflow); interrupt <= ovf_en and overflow; end architecture rtl;

isc

c9d1b9ba3debdab59f955e6e95bef9eb

preusser/q27

src/vhdl/top/dnk7_f5/dnk7_queens0.vhdl

library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.physical.all; entity dnk7_queens0 is generic ( -- Design Parameters N : positive := 27; L : positive := 2; SOLVERS : positive := 240; COUNT_CYCLES : boolean := false; SENTINEL : std_logic_vector(7 downto 0) := x"FA"; -- Start Byte -- Local Clock Parameters CLK_FREQ : FREQ := 50 MHz; CLK_DIV : positive := 1; -- CLK_FREQ / CLK_DIV * CLK_MUL: CLK_MUL : positive := 22; -- as fast as possible but not above 1200 MHz -- Output Clocks CLK_DIV_COMP : positive := 5; -- fast computation clock CLK_DIV_SLOW : positive := 15 -- slower communication clock ); port ( --------------------------------------------------------------------------- -- 50-MHz Input Clock CLK_MBCLK : in std_logic; --------------------------------------------------------------------------- -- FPGA0: PCIe Interface BUS_PCIE_CLK_IN_P : in std_logic; BUS_PCIE_CLK_IN_N : in std_logic; BUS_PCIE_CLK_OUT_P : out std_logic; BUS_PCIE_CLK_OUT_N : out std_logic; BUS_PCIE_TO_HOST : out std_logic_vector(38 downto 0); BUS_PCIE_FROM_HOST : in std_logic_vector(77 downto 39); --------------------------------------------------------------------------- -- Ring Bus -- Output BUS_OUT_CLKP : out std_logic; BUS_OUT_CLKN : out std_logic; BUS_OUT_PRE_DAT : out std_logic_vector(8 downto 0); BUS_OUT_PRE_PUT : out std_logic; BUS_OUT_PRE_STALL : in std_logic; BUS_OUT_SOL_DAT : out std_logic_vector(8 downto 0); BUS_OUT_SOL_PUT : out std_logic; BUS_OUT_SOL_STALL : in std_logic; -- Input BUS_IN_CLKP : in std_logic; BUS_IN_CLKN : in std_logic; BUS_IN_PRE_DAT : in std_logic_vector(8 downto 0); BUS_IN_PRE_PUT : in std_logic; BUS_IN_PRE_STALL : out std_logic; BUS_IN_SOL_DAT : in std_logic_vector(8 downto 0); BUS_IN_SOL_PUT : in std_logic; BUS_IN_SOL_STALL : out std_logic ); end entity dnk7_queens0; library IEEE; use IEEE.numeric_std.all; library PoC; use PoC.utils.all; use PoC.fifo.all; library UNISIM; use UNISIM.vcomponents.all; architecture rtl of dnk7_queens0 is ---------------------------------------------------------------------------- -- Communication Addresses -- Word Address: Read Write ----------------------------------------------------------------------------- -- 0x0000 <byte capacity:32> <-:30><enable:2> input interrupt -- 0x0004 <bytes available:32> <-:30><enable:2> output interrupt -- 0x0008 <!vld:1><0:23><data_out:8> <-:24><data_in:8> -- -- A data read (@ 0x8) implicitly clears an output interrupt. -- A data write (@ 0x8) implicitly clears an input interrupt. -- constant ADDR_STATUS : natural := 16#00#; -- status word, interrupt clearance constant ADDR_STREAM : natural := 16#08#; -- data stream in- and output constant ADDR_BITS : positive := 4; -- relevant address bits (at least 4) -- Bit Length of Pre-Placement constant PRE_BITS : positive := 4*L*log2ceil(N)-1; constant PRE_BYTES : positive := (PRE_BITS+7)/8; -- FIFO Dimensioning constant FIFO_DEPTH : positive := 5*(SOLVERS+5); constant STATE_BITS : natural := log2ceil(FIFO_DEPTH); ---------------------------------------------------------------------------- component reset_resync is generic ( VALUE_DURING_RESET : natural := 1 ); port ( rst_in : in std_logic; clk_in : in std_logic; clk_out : in std_logic; rst_out : out std_logic ); end component; component pcie_ddr_user_interface is generic ( DCM_PHASE_SHIFT : natural := 30; DCM_PERIOD : natural := 10; DMA_ENGINE_ENABLES : natural := 7 ); port ( reset : in std_logic; reset_out : out std_logic; user_clk : in std_logic; clk_out : out std_logic; dcm_psdone : out std_logic; dcm_psval : out std_logic_vector(16 downto 0); dcm_psclk : in std_logic; dcm_psen : in std_logic; dcm_psincdec : in std_logic; target_address : out std_logic_vector(63 downto 0); target_write_data : out std_logic_vector(63 downto 0); target_write_be : out std_logic_vector(7 downto 0); target_address_valid : out std_logic; target_write_enable : out std_logic; target_write_accept : in std_logic; target_read_enable : out std_logic; target_request_tag : out std_logic_vector(3 downto 0); target_read_data : in std_logic_vector(63 downto 0); target_read_accept : in std_logic; target_read_data_tag : in std_logic_vector(3 downto 0); target_read_data_valid : in std_logic; target_read_ctrl : out std_logic_vector(7 downto 0); target_read_data_ctrl : in std_logic_vector(7 downto 0); dma0_from_host_data : out std_logic_vector(63 downto 0); dma0_from_host_ctrl : out std_logic_vector(7 downto 0); dma0_from_host_valid : out std_logic; dma0_from_host_advance : in std_logic; dma1_from_host_data : out std_logic_vector(63 downto 0); dma1_from_host_ctrl : out std_logic_vector(7 downto 0); dma1_from_host_valid : out std_logic; dma1_from_host_advance : in std_logic; dma2_from_host_data : out std_logic_vector(63 downto 0); dma2_from_host_ctrl : out std_logic_vector(7 downto 0); dma2_from_host_valid : out std_logic; dma2_from_host_advance : in std_logic; dma0_to_host_data : in std_logic_vector(63 downto 0); dma0_to_host_ctrl : in std_logic_vector(7 downto 0); dma0_to_host_valid : in std_logic; dma0_to_host_almost_full : out std_logic; dma1_to_host_data : in std_logic_vector(63 downto 0); dma1_to_host_ctrl : in std_logic_vector(7 downto 0); dma1_to_host_valid : in std_logic; dma1_to_host_almost_full : out std_logic; dma2_to_host_data : in std_logic_vector(63 downto 0); dma2_to_host_ctrl : in std_logic_vector(7 downto 0); dma2_to_host_valid : in std_logic; dma2_to_host_almost_full : out std_logic; user_interrupts : in std_logic; pcie_fromhost_counter : out std_logic_vector(31 downto 0); PCIE_TO_HOST_DDR : out std_logic_vector(38 downto 0); PCIE_TO_HOST_CLK_P : out std_logic; PCIE_TO_HOST_CLK_N : out std_logic; PCIE_FROM_HOST_DDR : in std_logic_vector(37 downto 0); PCIE_FROM_HOST_CLK_P : in std_logic; PCIE_FROM_HOST_CLK_N : in std_logic ); end component; ---------------------------------------------------------------------------- -- Global Control signal clk_comp : std_logic; signal rst_comp : std_logic; signal clk_slow : std_logic; signal rst_slow : std_logic; ----------------------------------------------------------------------------- -- Communication FIFOs signal acap : std_logic_vector(STATE_BITS-1 downto 0); signal avld : std_logic; signal aful : std_logic; signal adin : std_logic_vector(7 downto 0); signal aput : std_logic; signal bavl : std_logic_vector(STATE_BITS-1 downto 0); signal bvld : std_logic; signal bful : std_logic; signal bdout : std_logic_vector(7 downto 0); signal bgot : std_logic; begin ---------------------------------------------------------------------------- -- Clock Generation blkClock : block signal clk50 : std_logic; signal clkfb : std_logic; signal clk_compu : std_logic; signal clk_slowu : std_logic; begin clk_i : BUFG port map ( I => CLK_MBCLK, O => clk50 ); pll : PLLE2_BASE generic map ( CLKIN1_PERIOD => to_real(to_time(CLK_FREQ), 1 ns), DIVCLK_DIVIDE => CLK_DIV, CLKFBOUT_MULT => CLK_MUL, CLKOUT0_DIVIDE => CLK_DIV_COMP, CLKOUT1_DIVIDE => CLK_DIV_SLOW, STARTUP_WAIT => "true" ) port map ( RST => '0', CLKIN1 => clk50, CLKFBOUT => clkfb, CLKFBIN => clkfb, CLKOUT0 => clk_compu, CLKOUT1 => clk_slowu, CLKOUT2 => open, CLKOUT3 => open, CLKOUT4 => open, CLKOUT5 => open, LOCKED => open, PWRDWN => '0' ); clk_compo : BUFG port map ( I => clk_compu, O => clk_comp ); clk_slowo : BUFG port map ( I => clk_slowu, O => clk_slow ); end block; ---------------------------------------------------------------------------- -- PCIe -> Target Interface blkPcie: block -- Local Clock signal pcie_clk : std_logic; signal pcie_rst : std_logic; -- Target Interface -- Address signal target_address : std_logic_vector(63 downto 0); signal target_address_valid : std_logic; -- Writing signal target_write_enable : std_logic; signal target_write_accept : std_logic; signal target_write_data : std_logic_vector(63 downto 0); signal target_write_be : std_logic_vector( 7 downto 0); -- Reading signal target_read_enable : std_logic; signal target_read_accept : std_logic; signal target_request_tag : std_logic_vector(3 downto 0); signal target_read_ctrl : std_logic_vector(7 downto 0); signal target_read_data_valid : std_logic; signal target_read_data : std_logic_vector(63 downto 0); signal target_read_data_tag : std_logic_vector(3 downto 0); signal target_read_data_ctrl : std_logic_vector(7 downto 0); -- Interrupt signal user_interrupt : std_logic; begin -- Reset Recovery resync_comp: reset_resync port map ( rst_in => pcie_rst, clk_in => pcie_clk, clk_out => clk_comp, rst_out => rst_comp ); resync_slow: reset_resync port map ( rst_in => pcie_rst, clk_in => pcie_clk, clk_out => clk_slow, rst_out => rst_slow ); --------------------------------------------------------------------------- -- PCIE <-> Target Interface pcie: pcie_ddr_user_interface generic map ( DCM_PERIOD => 6, DCM_PHASE_SHIFT => 198 ) port map ( reset => '0', reset_out => pcie_rst, clk_out => pcie_clk, user_clk => clk_slow, PCIE_TO_HOST_DDR => bus_pcie_to_host, PCIE_TO_HOST_CLK_P => bus_pcie_clk_out_p, PCIE_TO_HOST_CLK_N => bus_pcie_clk_out_n, PCIE_FROM_HOST_DDR => bus_pcie_from_host(76 downto 39), PCIE_FROM_HOST_CLK_P => bus_pcie_clk_in_p, PCIE_FROM_HOST_CLK_N => bus_pcie_clk_in_n, pcie_fromhost_counter => open, user_interrupts => user_interrupt, target_address => target_address, target_address_valid => target_address_valid, target_write_enable => target_write_enable, target_write_accept => target_write_accept, target_write_data => target_write_data, target_write_be => target_write_be, target_read_enable => target_read_enable, target_read_accept => target_read_accept, target_request_tag => target_request_tag, target_read_ctrl => target_read_ctrl, target_read_data_valid => target_read_data_valid, target_read_data => target_read_data, target_read_data_tag => target_read_data_tag, target_read_data_ctrl => target_read_data_ctrl, dma0_from_host_data => open, dma0_from_host_ctrl => open, dma0_from_host_valid => open, dma0_from_host_advance => '1', dma0_to_host_data => (others => '-'), dma0_to_host_ctrl => (others => '0'), dma0_to_host_valid => '0', dma0_to_host_almost_full => open, dma1_from_host_data => open, dma1_from_host_ctrl => open, dma1_from_host_valid => open, dma1_from_host_advance => '1', dma1_to_host_data => (others => '-'), dma1_to_host_ctrl => (others => '0'), dma1_to_host_valid => '0', dma1_to_host_almost_full => open, dma2_from_host_data => open, dma2_from_host_ctrl => open, dma2_from_host_valid => open, dma2_from_host_advance => '1', dma2_to_host_data => (others => '-'), dma2_to_host_ctrl => (others => '0'), dma2_to_host_valid => '0', dma2_to_host_almost_full => open, dcm_psdone => open, dcm_psval => open, dcm_psclk => clk_slow, dcm_psen => '0', dcm_psincdec => '0' ); --------------------------------------------------------------------------- -- Writing target_write_accept <= '1'; aput <= target_write_enable and target_write_be(0) when to_integer(unsigned(target_address(ADDR_BITS-1 downto 0))) = ADDR_STREAM else '0'; adin <= target_write_data(7 downto 0); --------------------------------------------------------------------------- -- Reading bgot <= '0' when to_integer(unsigned(target_address(ADDR_BITS-1 downto 0))) /= ADDR_STREAM else target_read_enable; blkRead: block signal rdVld : std_logic := '0'; signal rdTag : std_logic_vector( 3 downto 0) := (others => '-'); signal rdCtl : std_logic_vector( 7 downto 0) := (others => '-'); signal rdDat : std_logic_vector(63 downto 0) := (others => '-'); begin process(clk_slow) begin if rising_edge(clk_slow) then rdVld <= '0'; rdTag <= (others => '-'); rdCtl <= (others => '-'); rdDat <= (others => '-'); if rst_slow = '0' then -- Only accept word-align addresses if target_read_enable = '1' and target_address(1 downto 0) = "00" then rdVld <= '1'; rdTag <= target_request_tag; rdCtl <= target_read_ctrl; rdDat <= (others => '0'); if to_integer(unsigned(target_address(ADDR_BITS-1 downto 3))) = ADDR_STATUS/8 then -- Query FIFO States rdDat(STATE_BITS+31 downto 32) <= bavl; -- @4 rdDat(STATE_BITS- 1 downto 0) <= acap; -- @0 elsif bgot = '1' then -- Read Output rdDat(31) <= not bvld; -- @8 rdDat(7 downto 0) <= bdout; end if; end if; end if; end if; end process; target_read_accept <= '1'; target_read_data_valid <= rdVld; target_read_data <= rdDat; target_read_data_tag <= rdTag; target_read_data_ctrl <= rdCtl; end block blkRead; --------------------------------------------------------------------------- -- Interrupts blkInterrupt: block -- Delayed FIFO Status signal Zavld : std_logic := '0'; signal Zaful : std_logic := '0'; signal Zbvld : std_logic := '0'; signal Zbful : std_logic := '0'; -- Interrupt State signal EnaIn : std_logic := '0'; -- Enable signal EnaOut : std_logic := '0'; signal IrqIn : std_logic := '0'; -- Pending signal IrqOut : std_logic := '0'; begin process(clk_slow) begin if rising_edge(clk_slow) then if rst_slow = '1' then Zavld <= '0'; Zaful <= '0'; Zbvld <= '0'; Zbful <= '0'; EnaIn <= '0'; EnaOut <= '0'; IrqIn <= '0'; IrqOut <= '0'; else -- Delayed Status for Edge Detection Zavld <= avld; Zaful <= aful; Zbvld <= bvld; Zbful <= bful; -- Input IRQ: space has become available | FIFO drained if target_write_enable = '1' and target_write_be(0) = '1' and to_integer(unsigned(target_address(ADDR_BITS-1 downto 0))) = ADDR_STATUS then if target_write_data(1) = '1' then EnaIn <= '1'; elsif target_write_data(0) = '0' then EnaIn <= '0'; end if; if target_write_data(1) = '0' then IrqIn <= '0'; elsif target_write_data(0) = '1' then IrqIn <= not aful; end if; elsif aput = '1' then IrqIn <= '0'; elsif aful = '0' and Zaful = '1' then IrqIn <= EnaIn; elsif avld = '0' and Zavld = '1' then IrqIn <= EnaIn; end if; -- Output IRQ: data has become available | FIFO full if target_write_enable = '1' and target_write_be(4) = '1' and to_integer(unsigned(target_address(ADDR_BITS-1 downto 0))) = ADDR_STATUS+4 then if target_write_data(33) = '1' then EnaOut <= '1'; elsif target_write_data(32) = '0' then EnaOut <= '0'; end if; if target_write_data(33) = '0' then IrqOut <= '0'; elsif target_write_data(32) = '1' then IrqOut <= bvld; end if; elsif bvld = '1' and bgot = '1' then IrqOut <= '0'; elsif bvld = '1' and Zbvld = '0' then IrqOut <= EnaOut; elsif bful = '1' and Zbful = '0' then IrqOut <= EnaOut; end if; end if; end if; end process; user_interrupt <= IrqIn or IrqOut; end block blkInterrupt; end block blkPcie; ---------------------------------------------------------------------------- -- Input FIFO to Ring Bus blkFeed: block -- Byte FIFO -> Unframe signal glue_vld : std_logic; signal glue_dat : byte; signal glue_got : std_logic; -- Unframe -> Stream FIFO signal oful : std_logic; signal odat : byte; signal oeof : std_logic; signal oput : std_logic; signal ocommit : std_logic; signal orollback : std_logic; -- Stream -> Ring Bus signal pigot : std_logic; signal pidat : byte; signal pieof : std_logic; begin -- Raw Byte Interface: no real buffer glue: fifo_glue generic map ( D_BITS => 8 ) port map ( clk => clk_slow, rst => rst_slow, put => aput, di => adin, ful => aful, vld => glue_vld, do => glue_dat, got => glue_got ); -- Frame Extraction unframe_i: entity work.unframe generic map ( SENTINEL => SENTINEL, PAY_LEN => PRE_BYTES ) port map ( clk => clk_slow, rst => rst_slow, rx_dat => glue_dat, rx_vld => glue_vld, rx_got => glue_got, odat => odat, oeof => oeof, oful => oful, oput => oput, ocommit => ocommit, orollback => orollback ); buf: fifo_cc_got_tempput generic map ( D_BITS => 9, MIN_DEPTH => FIFO_DEPTH, ESTATE_WR_BITS => STATE_BITS ) port map ( clk => clk_slow, rst => rst_slow, put => oput, din(8) => oeof, din(7 downto 0) => odat, full => oful, commit => ocommit, rollback => orollback, estate_wr => acap, got => pigot, dout(8) => pieof, dout(7 downto 0) => pidat, valid => avld ); blkBus: block -- Syncing the stall input signal stall_s : std_logic_vector(1 downto 0) := (others => '1'); -- Outgoing Output Registers signal OutDat : std_logic_vector(7 downto 0) := (others => '0'); signal OutEof : std_logic := '0'; signal OutPut : std_logic := '0'; -- Inverted Output Clock signal clk_inv : std_logic; begin ------------------------------------------------------------------------- -- Output Inverted Clock blkClock : block signal clk_inv : std_logic; begin invert : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '1', SRTYPE => "SYNC" ) port map ( Q => clk_inv, -- 1-bit DDR output C => clk_slow, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D1 => '0', -- 1-bit data input (positive edge) D2 => '1', -- 1-bit data input (negative edge) R => rst_slow, -- 1-bit reset input S => '0' -- 1-bit set input ); OBUFDS_inst : OBUFDS generic map ( IOSTANDARD => "DEFAULT", SLEW => "FAST" ) port map ( O => BUS_OUT_CLKP, OB => BUS_OUT_CLKN, I => clk_inv ); end block blkClock; ------------------------------------------------------------------------- -- Pre-placement Output -- Syncing stall input process(clk_slow) begin if rising_edge(clk_slow) then if rst_slow = '1' then stall_s <= (others => '1'); else stall_s <= BUS_OUT_PRE_STALL & stall_s(stall_s'left downto 1); end if; end if; end process; pigot <= avld and not stall_s(0); -- Output Registers process(clk_slow) begin if rising_edge(clk_slow) then if rst_slow = '1' then OutDat <= (others => '0'); OutEof <= '0'; OutPut <= '0'; else OutDat <= pidat; OutEof <= pieof; OutPut <= pigot; end if; end if; end process; BUS_OUT_PRE_DAT <= OutEof & OutDat; BUS_OUT_PRE_PUT <= OutPut; ------------------------------------------------------------------------- -- Start of Result Chain BUS_OUT_SOL_DAT <= (others => '0'); BUS_OUT_SOL_PUT <= '0'; end block blkBus; end block blkFeed; blkDrain: block -- Source synchronous clock domain signal clk_in : std_logic; signal rst_in : std_logic; -- Incoming Bus Data Capture Registers signal InPreDat : std_logic_vector(8 downto 0) := (others => '-'); signal InPrePut : std_logic := '0'; signal InPreCap : std_logic_vector(1 downto 0); signal InSolDat : std_logic_vector(8 downto 0) := (others => '-'); signal InSolPut : std_logic := '0'; signal InSolCap : std_logic_vector(1 downto 0); -- Solver Chain Connectivity signal pivld : std_logic; signal piful : std_logic; signal pidat : byte; signal pieof : std_logic; signal piput : std_logic; signal sivld : std_logic; signal sidat : byte; signal sieof : std_logic; signal sigot : std_logic; signal sovld : std_logic; signal sodat : byte; signal soeof : std_logic; signal sogot : std_logic; -- Solution Stream -> Frames signal tx_dat : std_logic_vector(7 downto 0); signal tx_ful : std_logic; signal tx_put : std_logic; begin --------------------------------------------------------------------------- -- Reading the Bus -- Clock Reconstruction blkClock: block signal clk_in0 : std_logic; begin IBUFGDS_inst : IBUFGDS port map ( O => clk_in0, I => BUS_IN_CLKP, IB => BUS_IN_CLKN ); BUFG_inst : BUFG port map ( O => clk_in, I => clk_in0 ); rst_in <= '0'; end block blkClock; -- Bus Input Capture process(clk_in) begin if rising_edge(clk_in) then if rst_in = '1' then InPreDat <= (others => '-'); InPrePut <= '0'; InSolDat <= (others => '-'); InSolPut <= '0'; else InPreDat <= BUS_IN_PRE_DAT; InPrePut <= BUS_IN_PRE_PUT; InSolDat <= BUS_IN_SOL_DAT; InSolPut <= BUS_IN_SOL_PUT; end if; end if; end process; -- Input FIFO (ic): Pre-Placements buf_pre : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64, ESTATE_WR_BITS => InPreCap'length ) port map ( clk_wr => clk_in, rst_wr => rst_in, put => InPrePut, din => InPreDat, full => open, estate_wr => InPreCap, clk_rd => clk_comp, rst_rd => rst_comp, got => piput, dout(8) => pieof, dout(7 downto 0) => pidat, valid => pivld ); piput <= pivld and not piful; BUS_IN_PRE_STALL <= '1' when InPreCap = (InPreCap'range => '0') else '0'; -- Input FIFO (ic): Solutions buf_sol : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64, ESTATE_WR_BITS => InSolCap'length ) port map ( clk_wr => clk_in, rst_wr => rst_in, put => InSolPut, din => InSolDat, full => open, estate_wr => InSolCap, clk_rd => clk_comp, rst_rd => rst_comp, got => sigot, dout(8) => sieof, dout(7 downto 0) => sidat, valid => sivld ); BUS_IN_SOL_STALL <= '1' when InSolCap = (InSolCap'range => '0') else '0'; --------------------------------------------------------------------------- -- Solver Chain chain: entity work.queens_chain generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES ) port map ( clk => clk_comp, rst => rst_comp, piful => piful, pidat => pidat, pieof => pieof, piput => piput, sivld => sivld, sidat => sidat, sieof => sieof, sigot => sigot, poful => '1', podat => open, poeof => open, poput => open, sovld => sovld, sodat => sodat, soeof => soeof, sogot => sogot ); enframe_i: entity work.enframe generic map ( SENTINEL => SENTINEL ) port map ( clk => clk_comp, rst => rst_comp, ivld => sovld, idat => sodat, ieof => soeof, igot => sogot, tx_ful => tx_ful, tx_put => tx_put, tx_dat => tx_dat ); -- Output FIFO (ic): Solutions fifob : fifo_ic_got generic map ( D_BITS => 8, MIN_DEPTH => FIFO_DEPTH, FSTATE_RD_BITS => STATE_BITS ) port map ( clk_wr => clk_comp, rst_wr => rst_comp, put => tx_put, din => tx_dat, full => tx_ful, clk_rd => clk_slow, rst_rd => rst_slow, got => bgot, dout => bdout, valid => bvld, fstate_rd => bavl ); end block blkDrain; end rtl;

agpl-3.0

e0bbd69eccd385ca2a3cbf7d58d548dd

viccuad/fpga-thingies

cronometer/debouncer.vhd

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY debouncer IS PORT ( rst: IN std_logic; clk: IN std_logic; x: IN std_logic; xDeb: OUT std_logic; xDebFallingEdge: OUT std_logic; xDebRisingEdge: OUT std_logic ); END debouncer; ARCHITECTURE debouncerArch of debouncer is SIGNAL xSync: std_logic; SIGNAL startTimer, timerEnd: std_logic; BEGIN synchronizer: PROCESS (rst, clk) VARIABLE aux1: std_logic; BEGIN IF (rst='0') THEN aux1 := '1'; xSync <= '1'; ELSIF (clk'EVENT AND clk='1') THEN xSync <= aux1; aux1 := x; END IF; END PROCESS synchronizer; timer: -- espera 50 ms para un reloj a 12.5 MHz PROCESS (rst, clk) CONSTANT timeOut: std_logic_vector (21 DOWNTO 0) := "1001100010010110100000"; VARIABLE count: std_logic_vector (21 DOWNTO 0); BEGIN IF (count=timeOut) THEN timerEnd <= '1'; ELSE timerEnd <= '0'; END IF; IF (rst='0') THEN count := timeOut; ELSIF (clk'EVENT AND clk='1') THEN IF (startTimer='1') THEN count := (OTHERS=>'0'); ELSIF (timerEnd='0') THEN count := count + 1; END IF; END IF; END PROCESS timer; controller: PROCESS (xSync, rst, clk) TYPE states IS (waitingPression, pressionDebouncing, waitingDepression, depressionDebouncing); VARIABLE state: states; BEGIN xDeb <= '1'; xDebFallingEdge <= '0'; xDebRisingEdge <= '0'; startTimer <= '0'; CASE state IS WHEN waitingPression => IF (xSync='0') THEN xDebFallingEdge <= '1'; startTimer <= '1'; END IF; WHEN pressionDebouncing => xDeb <= '0'; WHEN waitingDepression => xDeb <= '0'; IF (xSync='1') THEN xDebRisingEdge <= '1'; startTimer <= '1'; END IF; WHEN depressionDebouncing => NULL; END CASE; IF (rst='0') THEN state := waitingPression; ELSIF (clk'EVENT AND clk='1') THEN CASE state IS WHEN waitingPression => IF (xSync='0') THEN state := pressionDebouncing; END IF; WHEN pressionDebouncing => IF (timerEnd='1') THEN state := waitingDepression; END IF; WHEN waitingDepression => IF (xSync='1') THEN state := depressionDebouncing; END IF; WHEN depressionDebouncing => IF (timerEnd='1') THEN state := waitingPression; END IF; END CASE; END IF; END PROCESS controller; END debouncerArch;

gpl-3.0

5e3cca487ce1f6ec82745d503eb9aa13

preusser/q27

src/vhdl/top/xilinx/xupv5_queens_uart.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity xupv5_queens_uart is generic ( N : positive := 27; L : positive := 2; SOLVERS : positive := 52; COUNT_CYCLES : boolean := false; CLK_FREQ : positive := 100000000; CLK_MUL : positive := 25; CLK_DIV : positive := 14; BAUDRATE : positive := 115200; SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte ); port ( clkx : in std_logic; rstx : in std_logic; rx : in std_logic; tx : out std_logic; leds : out std_logic_vector(0 to 7) ); end xupv5_queens_uart; library IEEE; use IEEE.numeric_std.all; library UNISIM; use UNISIM.vcomponents.all; architecture rtl of xupv5_queens_uart is -- Global Control signal clk : std_logic; signal rst : std_logic; -- Solver Status signal avail : std_logic; begin ----------------------------------------------------------------------------- -- Generate Global Controls blkGlobal: block is signal clk_u : std_logic; -- Unbuffered Synthesized Clock signal rst_s : std_logic_vector(1 downto 0) := (others => '0'); begin DCM0 : DCM_BASE generic map ( CLKIN_PERIOD => 1000000000.0/real(CLK_FREQ), CLKIN_DIVIDE_BY_2 => FALSE, PHASE_SHIFT => 0, CLKFX_MULTIPLY => CLK_MUL, CLKFX_DIVIDE => CLK_DIV, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "NONE", -- only using clkfx DLL_FREQUENCY_MODE => "HIGH", DFS_FREQUENCY_MODE => "HIGH", DUTY_CYCLE_CORRECTION => TRUE, STARTUP_WAIT => TRUE -- Delay until DCM LOCK ) port map ( CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => clk_u, CLKFX180 => open, LOCKED => open, CLKFB => '0', CLKIN => clkx, RST => '0' ); clk_buf : BUFG port map ( I => clk_u, O => clk ); -- Reset Synchronization process(clk) begin if rising_edge(clk) then rst_s <= (not rstx) & rst_s(rst_s'left downto 1); end if; end process; rst <= rst_s(0); end block blkGlobal; ---------------------------------------------------------------------------- -- Solver Chain chain: entity work.queens_uart generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES, CLK_FREQ => integer((real(CLK_MUL)*real(CLK_FREQ))/real(CLK_DIV)), BAUDRATE => BAUDRATE, SENTINEL => SENTINEL ) port map ( clk => clk, rst => rst, rx => rx, tx => tx, avail => avail ); ---------------------------------------------------------------------------- -- Basic Status Output leds <= std_logic_vector(to_unsigned((SOLVERS mod (2**(leds'length-1)-1))+1, leds'length-1)) & avail; end rtl;

agpl-3.0

0a51b1c82c035509d28ad574df0f87aa

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fdiv_fadd.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 3; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

7eac373ccecc914faa048086d4747c18

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_bindec.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block GfmYVDVu+TEIqolgenDas9izt6SZXSU0VONt8FpAkwrqolWZ2fyqu1Pdo+dOJ+7bHIOZ6JnqEjUF t0t4l8DRVA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block D2e2FXItpsMtjUQwtkNa8rD4XaUHEroTyJC4NG/HmrPmPV3Y0GSyHNeWtwLriV5NxUf7UpSh3KxD mn8q+FrtJ2Xrz46tywRIki2qceC8IV0jyNzkoCnwqHbN1JhmUN3yXCTqZEQsoqGKPybX8leFq48Z kQNh2C5bvkfhK3mvR4c= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block K+YoSNA4ANwrRuEZypFUo9I3X7RpCUbSM8+7npKE3uVeZmSoQIlTzPEm4v2sSfNr3X8kGwEFaLND 1XzCqSTF5dwQ7SzwjazeqnzZ/dGbvDjy1DpcPyZWW2S9XM420sGTU18gTiAp0Mzb+jsPXOm6cS1i GbnYwmhW6pMMcsyQusYLpho10o3U/o9j0+zVgbzuAfFuQ7q8QQeA1zKssEGGsxWKx+peReG84OtL ZGSzdgAELFCU9Ykp7F/zzEI3/AzzbiCNr1FgFyBDWFNJZACkOlSqFEHYXlUeU3o21Zyu5fER0/Wf jf6S/UW+sd6/XlGbmHgLQzYeDB5jXI4s2YUIhw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KkNT8RuVGt3I7JUmgj0YwG+3oG2ZRLmKuczPPnFzmaCx26/EzTLSZZz7ZFhTWnWsFZ6OV5bu5daO uyMZch5a6pE0CaiT/L7YZuZ+eh4iWpQ6RNwIEZMwQZa6kQgxy0klXmq7vtNB7sivq2opZD+K0e90 soamvZ8mU9Ixfhwye34= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block J39BUIyWPx9yZZF7CYU3QEzEnPd4Bo61BVoW5mk+11wyUEsW/ZTwpeFiXBEw2nV+tJXcVm8I8rnk KbFp3gl2SHdHT+99VOrwK6w8e8V+CHqgEnxeVmG2dBkDMK+FAcd9ZWqZjSz0F7pR41yY1vnwW8fK VA7P3QvChAk1pomkWw/C0PKJ3wLzvLND7+Yl9dt8vYsdrBSeUrk06lGzpa0Z1KORbC6iPtVxJ/p4 Mik958n0RkNhosSM5aGoACD1VToX8vio9r8Jhb5RyZhChC9Z5yh8sY/zfHf3+WGQ1u+lzyBZ0V1d 1fch8FxL+7Utjr16tkwDBJgWBkkNN1/mSzglug== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5824) `protect data_block VF+905Z07ZvA14IX+Ic7yoLfQeVFV2BtBvfwGHrl6SlgMT/c4C9Jdu7d3fFG2XdOTAGYUUPloimz mVf4aKKB38Tqbsix0rdPjWp3ox56TLCdyeBGEJFssTfgeKZ2BpVLOcf5KrdwdeRs2L6ka6eAhggl /t0IOkfd6tJRu9uMIBuFIA2iEIA2JDlbhMOCX52RfCp7SV3q9NvQdQv85w/6Vh0kniH8DtMZn0FO L1YgqAJkQYWrTGkLyvseoePpgi7McclT+zH/iNrwKRK1IBpmbekaVbh75qYqupTpONr3JF8doksT vBcABzMVq3tW83TclfT1hty+/iCX0SoSw4z1Zlz1KQ2TMNpjv239DwB4YhEnM3AWasGhyBPVSz9e x/FiH6iYGP7LtoZnlnEQxnzPudKrUP4W9saqqJRQT3AXGSoZApBu2kQYaNxV7sNU+bByerbRBzD9 ry7do4dcvRt0r7fj0kyzUatSgYPBOBaGODPmp6kY88P9ZaMEwShwliFAxFu2HGSW5hPPoQGVkBA9 qPechmvgUYUtjfArznMkAYvfhwbDvBfKknkLt1ZiubLnepaCyLOpfy7ibbEh20vx9OpGMx8Jn/xS H/rMYf4SzzlTs5p7M09Dna93fRd6USPtzYA6cxjFPmGTa6ODSPsaMRi8tnhsiWEiR50ms4rM3PNI 67A02hG7pIHuVqNYrkcOlAxqDHXwsH+n94D6TW3hssHnYQw8hi6qTR2+ahlv6Y/xnyG8Ep2vWbW7 aGv0adZmgYWYSUg7N1HpYbipWQ4L9Q9VjSl30XrMGE6mpnM5hWzdjRdcLcg5Biv5ZM6ME4PCZqKP BCqIKsD2U6a71cGkVGg3XLFNNWJFiLHl+20e0qrNRVKgRJRzUMdPB2GOFVQoqxqEonpTDLRZW38T XwN1yQ4C6+kuOe4P4eRbTXXD9UxwrLEMMRMobbRo+nX6b7QXfYlnrX0J44AmTKCywTzBjXpME1Ca KhOHmvFqecRiTBlmuypmlyL3gK1MEO9Qfliysh2KXzXaSIjppwwNr9tdx0ZlEfUJNaQVvy+Yweiz 1Ytq5tgKsq0/5eyLDpN7cs1oQWPaVyyXM72/NRWrVaTiBkRgbrftARkgI2U/XZHBT0gkg1khRBpi bTmoi8VNaknjH5TFq6Tni66V4DsiQJ7fQ9xZNtGuf9O6dQ/pFsFgv2W7xgPxfY8DIYU8e9XyeT8j hUjn9fX4LMrgHewz4dBBldYni2KCar+b+dyF2qYTCw5nD7zAFRRz8gDLgbGwJIZaw277HteVZTkc Q6cnjHjYN36jJj/GeJmNV49V40g7SfxLE6ktEb2coM6nrts6h1Eda0H2H3FsnXItJ1egp0TBN35v vhPAhgl2aDUjwZQSloQh8f4GvgauQh/U+oGZ4F7GZDix85RSWoN9m1TOZbzJA7hYrDk6p79pQon5 Ggkc+jfN8RuXOV055ekdGRfEck0Brt5xfCDBx5IS+r1I4+yMvsK+pYJJkbJJ/VdtZKVNgITJs1Cn nvVy7jrFGP8TRmFTbZcBcwWUP8aMlwC80zPnv7MtKvGal6C2o5VoEE+0aYOaY1AQ+u+5ftT5ZQmo lFSf6ZFTzkAqqNrO3vsobiooupmapkzrd70bMp29wTAGLSM1wv+w+qYWkcxBzX9zJpzjY4RGZJaX 49mCkvb29ozqtjTzwHAWGMsYpy4LF0LPcND2dUG0W2ebgjCcd7p6R0YGWB3yDZEhkU2dxh1UA/uN 1BIFgHXV49+fkYeCNP2ohuCZrTTV2gkuFJq6qM+IblY+cLU0WH9sWDAb1LXnxvYB0QgqmsuAh/jO KuRU7d3NjDLT8xspoC2FYP/QjR7yn5e3H/qrpvRIFD/XWYLZbXzQlmtuBN4wUGRcVUoUFpV5yReh a8CLZEt6bFPIku99LO+yxmiR0xype6BGPyAsT0Rn9sTZLle//TlLs0mf4NwuXsjXH14/ROhhR20w X98bQtA5gm+upChcXlqqh7x0dc/GcyPfBLvVqmTawQP65GEKjqUzmByaYlVPPd385EDGaDUP8SjO fT4CYtHbgUSNNQe2f1fX1/hVD245Vbc09icCdKZ33trkll8GEMg3FK0ngopEqQEMIym3aqRidLfJ 0U7luItgdB08oOy24P+/UNpc6hyrrpgGp9Izz9vd0l29WNXg4cQ7ptM79RAJZN+kQF4Y62x8PIL1 k7iqahhx34sL6OVEIqgd4R9iJT8s68Dh0oz0OEgoOP1pGNlFNWWUWTv5lmjfWzAmcJLY9xCLQ52s t7nV9p6NpTQcQAlfZ77LIX3Sbdx78U582k/3lQ13b+2IzK5k4ii+R6CT4fyapmB0MEpofrESn2zf tNrc+FJ6aPbLYP6M2t9Oma4a9F0n+JO4dPjts2+bKKlI+1FTC8HILpPB/KxbGjvQwpPGi5WEI6Db koAYlnU0s5a5xZgWtAyKmKk+sCgVLBr2V4fqY7aBan+kc1cm7WQBYF0iXOdhH2R3Ael9p3s398nB Dn1V9pvor3PMx0CzfGSmwMKnt+HXBvdkqAWyzKBtYVj5y91CVOvyeSQMWAiHqFvXpM7dkl22HcD5 ikQaGvp4zhYJD4ah+0ZXGYied4/tTFvXPUL+oLkUFP4l9a8/4VxaaGdovsCy5UWAoO3CCyem8paV sMbnG1vrgZoA7Csht2p4TmZiT/i6VGAWN9heArO02aXYTpr+C6z9rxHFZYKhvyLkgeZ0TwvCz1hD qjAW+5e8ixbbbs49sc6X9rryvQY2thb/tm+VIA3YCqVGTjOwlBs0CfPsIXdLA//He3fsDMpgBZSy s8mfMZAWri2JxL3d/dhSW9k/Nf7PUFy1stGbXXPSbwS8VKiooyEiZl6TMxX2MPc35v1FiHtBJvE0 5T7/+2MxlRHsX2Vbgyi14oDMlm5Ytz0I8Qc0+gsADd0WU77vJTJ4vFZQs0MGFN4pE7+SGrM07ndP WJyyEOZBDIRNuz/YD3pUXSGDrWr6yxHAtGBv3w2F1dEaMwzosPpd2Anb55z4J0S6NpGmtB0/0dUq kepQs3OYqWgAkrWfFT6CUktSoW0W3l37R7ZAGfzkP2Vr3wsUnOpQ99mHeqQo+8oxUkgrGvWfHaK6 3t+tSEnt4Dh5bf67Hem6jqDz1EQ7ijEZhXoPq/J7v662pfCxF2wPK8Ii1NbfS2HxcB+981RuzJgE WUUfY/mMTNnr3dJBhStVFK6NYu/GAOdaDypqXYkifHmCA0J0Ay8ERks4/kIXYYu3yAeXzOsWaNMi Pjm9x77Ueap5n9zyah6I69Eb2TJwB9fZjbWfKxaUOqOyfXn50JXaqaV1sL4Ho+uRD6mJqASkwyVD 2xqpzazwxiYFhz4pNxELP95lodTZLPFSA3jWRt56QLnRSx2QLT1xze85WIH5FuyoHisb8ij/3zKz UglerTo9umvsFy4OgcGHIinA4NSW/MD2UkGPJvWVnBGHAzFgixk/3Hy4ieOpPqvtHA1gpfvmO9i/ cp7blE4jGnYogb+3NL+ROlevsLL6Ogpxku16zlWxFdlQdxiXnLRqU8wYg8fAVwZGqXuGS9FGqnk0 d8RokD93YXPu4KRSOmWu9G8dd5iO+ggRhk6h22x1jKx5ycjENMV9ja4KRNRHtZdmweUoUrJxVFAs c63VJ5qrCbv/EhUrHLQnFTcyfeOVifuLWZfszQxjW5Hmqq76tft05KLiLJ5aRGvZb2M10Astl6hm rDszrTUj+IRfE7LKN+R8gS6giB7GgRVUTLYi5ZxZoWBaxStL0P604Sa5NtmHNoBV7bimRRq/PpP3 Kd+uXSCVejMFkClEiartmZm27OpHGyDcpXjy3zBr9m8OsA6SNrIUovKQivIEg9SBnDv6LgTy4iAr OewwJhhqS0NrOHZ/z8GoE1Ai0mbzg+axAo1I5sqVU9mgCXRpt7msssAgZSHy/CZM7dSW5/BgHsKO uTBLi2gTpTVyHIXW3RN3p1sQHgPBM4K665hO8wpOWSkfCh7pavIFFkX1DbXa3c15y7Wk0tMNiDuO JXnK8mPxKDGci2AZM/67XqZ8TpSSoN+IovJs/zFoQ/Xh7YkWPoGA7BJMoFOJAz1mE1qsj+G4yPrf Qv/SauT6YFmIE1yZk6i2B1f1uYPIahQihFMlSq+B98BCyX506/nF826uksnVBj2050MK08gfzuYi 1P8jWd0DZT8ZZPeAfyiiYAc92LLvj1vCQdFuPVldbqoFTN7S0dRQbW/DlNsoCvKOW3c9TCODQp52 UyQuxmNhuxYltmwDdlFwgnPBuJwShkL2BTCFv+aje+YTnkZTmw3QWYXMYXiNEym1i7V5/6HTGBFb /KRU9r6cWXW1jcsGLJ/UCIX+JWKAa/YKAFdk6JaQIVwbpWTV4bQsa8/G5cAUCnAYv7uFsT8k6k4x LcToKgWy47W464Co7NtXHTQHIiY7/rbEsDg7z9Mfr50qFwoYYOWPFd/5hGbNTB/x8NfnVjYxZc9u +ii5bArfV2ZpdyUQiI6brPbdjcotLI58cVF0h9rRUgQrUs9cfylT/eUNMUEDISN/Fwo3X8sS55CB +zSa4HEmNAQERBqimBEpyi9WqvJuusqN7rHd3gepgJf+K2LLYs+o6O28Yp6t3S79gJYa7WbK4F9I v7iI13nySe/NJICkqQampqIKdv5muNhrx+pupvdpXDN67rS9W85vQBkxn/jHkuqjqGkCTuLPK5PH rdfSHlyj6pxelcGj95uFVA2MzXec/nhDCs+KqMfnYIAYP0ATbvpjxyVJlmxX7A1tgxlOryC/ijIe Kwr3uYMiSrzAKS5062EmFzchNoOnruFEbOfyBHrRlV5tBNOW0wMHaLG+WJ2JV7sgXYIm2BsJDDUJ uQEwzJWpLjrWTRHYXZoMTtnrZO09e4FczkFjexWfEUGSyDCt5auoumAePFcCw7fEDtbrnjbIgJW7 TO+dvsEbSjjfdD9d98Fcry7Wkmb9zXavCdCNly1PW/O/1Zns8u3sJgbEa+85J6MPY2vqnZnlqu6H Uzr4b/oJiorz66O3cXZrRaLEzxevX8+ynJMtTaEJR+FMJfo5tyDGqs+1i1urCIW3U3omHu2BDgKu EWtllhx5h9qLnQZ6yS6sEgonDhXcxZ1qKO5ZABYctj/vVbA8IrVT7x/ryK7ZoPOMGxS5XfMu8ron lM9MwuFm1u8BlO0bwposh523V+utduTAiP27lRvU4/cHve+lq0ZP1a7V/tT9J8JzJF1ddEOSE1no EgfjevDwisA8xcAGYjPiyDLuS9lAthq7cYyXmOqJ6hR8Fyj2mIVeP/yWzkDet0srYQ60ZTBA1sak zGdGA0ojwSHJRoS7ZWbdMlNloK3iPIdMTfVcxde/9aaNjSmdZk2FlKud35bSFaGiPjX5GcgFgr6d 1aL+ylcRxDUYyz+j17KR2pwFwkQC+61nqyB7a+XqW7bN6MaHRtdfLrp/k7aVp+Y/pDG497nQslsC yx9ruCGyjlmZmDY2AG8wVsM/Bt7wtxaFFsPwKuJ9QJriHIoq9Pg2s2SZZBdgJRte2ylE9S0bMwNU IOYpd2LC1IPAH3eNsFDCWXYdpOpQjMQGoca7RbNSjHF4B55PjMZW6U4rjAhOf5ZOpl3wU98zG/J4 xFUWoxZT92iR1UDyr/NxtgA7vJvkq8VNwIbcfCVx25LnLYKIKEgqCfPLvyztgcZIf8dl/bMVy8XV dDDBNhQMaL7gRcj/ThPosMFns59IEtNFvd1hk2DMT/3F8CK6L8W/fc+mt1Xuk2fi5bXDIXqaK58a a4o3CZGKPjbgp/8jUKRXEQyrAITeGMCOvu6MuRjYsXvs2hq1uWL84J8QwwssdQKDI/8kTSmi8zIo QwX57ozwgaII8gHJ0hYKTIyglKeJSc59BbZ/mdtDvOrZw7Kw99+An8vDONIYBv/wFIw7kFo4OMDs C6DoAIKcxG+r6RUTR+nGe1cWUFXn1feR4uibsQCdYhUXtjbQFWUXc5+mpr5pe8CFZ/w0FdvT7lge Ox2XgG1atVIocDqISrOKOTX75G+SySgI8r4PKWycwdcqNXkW8YP2Ucy6RaGLHpYRkTQihgtZPjzM biX/4kBpWZ+vv1TlVNq6sUhVnp2tq8qkgSJQVvQ7b43i8VgvRkh57EaEt4njcF9oqRXcN19YYSkQ NFMZxJiOUbfWyzQMcNw/estVmqNtRpcA8JdK1xoE4CHkWRQxlk4Yy8RCTcx5tM8wh0ay+QoGVw86 kUTuN/hnR2WU24MLRWVub1e+KC05ATSgZa6Yutfox4zRuvqcw1sAh+HBULJWBeAY08GHfpSBd3lo Nt6LHxA9ajS3nVM7h1VzaAcjF4Eio+PaGk9leFT/B3AwNN5PQ74N6vQAIbq/lKxh4PzT+N7+xbyw Wrinp9VVm76Len69KmrOskdyZtP9FmDxZtUqgqljBzTVJ8F7DmwjEnvg3uL1J9HMaQAFe6P1ROZ7 DcE5lZS5dw0QuHuQVtlf+gvHirKLhbRQ7GeqQEG8SAy1V6/G4oxtSozrhM592Bn8RYNkypCS85Pc YhcSuVm5lJQuyekv6j49qP1Xt/FXollsA3TJfbb0wvm2f6+D2pqd39H4CIZbXgQoXVmjjeWxxyRy RmvWGwP/5BzaBWlPmXnkWL38MxgM1QOQcymaQSpoFPsGgwKdv4P4J4P5UgME5NUb1UKF68V1znUL fxB0B4dzJ9U/tjkEBDKI+d9cd9iz1KzKpk5sFcVzv504Rms9UcoQYZAEkNWcmvDauiIY5uBDTqmm 606d85/Zk6HaOb7xxX+Vq9nCy9mODnswhsPyYVk3LfRljHkBK55E1LwX2k0a45ybP9j5RfogPxTv 9aWNBreKVByaA8zNby2LezgrY+tIoRqULGainT540WloXck7WS2qslLjO8rkcusUfS7bLXGEdqgL es9aYSzJSQTzYUXxPBAp6g37au/naerGTPKmyofq9s0kctv2325LFwUeqQa1eVuZIJch7ufLrzPb xud11qZoORuMNOcRVAKL8PpsGdZS8N6rODn9hhhabGXI+ewP9+4yizyKSFdz3Zl/EnuA+Gxu7iWK X8XGz1JZe8V3IgE6VQ89+qpJMVDiosoOwALcIScFE3BWf31iG7HADRKMYHejrkpjZhX3qTrQRBH1 s/Z4c72+q6o9q8A6rBU+dieCnpHuVMXBBvTOmAbaF2xNC+NnrQ8/KDjk/8vLnLyJXUuJGFosmmWv 8uRr/zRqcScY2wwci/1/HraluU/XE1fd6FO3Cc3mm9r/hndkGiW/UrFLkAXfQKQWO9d/L4qP1OJr 5F/v40IF/+CvYL3jt8gLfF/ZOIvaApLTnwji3LQ5TjYAGpVaRspnkR3bORk7Q0J4rz1MDSWxEik+ REcXlKmKc7XYgDNfurYgNdUpTLe5cIwJ6Zl2+YK0ZdiHyDAQppc/wccIcV6u7Z4NmvODH1iYwFYm PhwtnhC5muVlXQ/P0DAkehM/JaBzKdWV9W62Q4P4CFbYCeV3OY8DNb5DdHA8cfCQacDm6jmXdi1r BTCkVEkXn0olQOa69BG3nhii08avzsPL9uzgrHQKBJwJBNpPyGvlUni4VavTtXPuYHZQ7cX8MITn WJLLNi7xjoL9BB0en1xKfh73mPFLkzaOUiyC4lqd+UR4cAcA+PrEerPSTzmO90VY7jIeZxbOOoFS HEfw05FH/hbUB2Me1jd4oCWSwO/dBYRfrV/qrE4NhYxVPBX8jBGamqdt19QN7hYDbQf2h41TB5/r 4v6+fz9LZDF0Ag== `protect end_protected

mit

755aafd6055cb72c60fdc99e097ce1a8

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_tx_osc.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_tx_osc | -- | --------------------------------------------------------------------------------------------------- -- File wf_tx_osc.vhd | -- | -- Description Generation of the clock signals needed for the FIELDRIVE transmission. | -- | -- The unit generates the nanoFIP FIELDRIVE output FD_TXCK (line driver half bit | -- clock) and the nanoFIP internal signal tx_sched_p_buff: | -- | -- uclk : _|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-| | -- FD_TXCK : _____|--------...--------|________...________|--------...--- | -- tx_sched_p_buff(3): 0 0 0 1 0 0 0 1 | -- tx_sched_p_buff(2): 0 0 1 0 0 0 1 0 | -- tx_sched_p_buff(1): 0 1 0 0 0 1 0 0 | -- tx_sched_p_buff(0): 1 0 0 0 1 0 0 0 | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 14/02/2011 | -- Version v0.04 | -- Depends on wf_reset_unit | ---------------- | -- Last changes | -- 08/2009 v0.01 PS Entity Ports added, start of architecture content | -- 07/2010 v0.02 EG tx counter changed from 20 bits signed, to 11 bits unsigned; | -- c_TX_SCHED_BUFF_LGTH got 1 bit more | -- 12/2010 v0.03 EG code cleaned-up | -- 01/2011 v0.04 EG wf_tx_osc as different unit; use of wf_incr_counter;added tx_osc_rst_p_i --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_tx_osc --================================================================================================= entity wf_tx_osc is port ( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- Signals from the wf_engine_control tx_osc_rst_p_i : in std_logic; -- transmitter timeout -- OUTPUTS -- nanoFIP FIELDRIVE output tx_clk_o : out std_logic; -- line driver half bit clock -- Signal to the wf_tx_serializer unit tx_sched_p_buff_o : out std_logic_vector (c_TX_SCHED_BUFF_LGTH -1 downto 0)); -- buffer of pulses used for the scheduling -- of the actions of the wf_tx_serializer end entity wf_tx_osc; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_tx_osc is -- transmission periods counter signal s_period_c, s_period : unsigned (c_PERIODS_COUNTER_LGTH -1 downto 0); signal s_one_forth_period : unsigned (c_PERIODS_COUNTER_LGTH -1 downto 0); signal s_period_c_is_full, s_period_c_reinit : std_logic; -- clocks signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p : std_logic; signal s_tx_sched_p_buff : std_logic_vector (c_TX_SCHED_BUFF_LGTH-1 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Periods Counter -- --------------------------------------------------------------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));-- # uclk ticks for a -- transmission period s_one_forth_period <= s_period srl 2; -- 1/4 s_period s_period_c_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Instantiation of a wf_incr_counter counting transmission periods. tx_periods_count: wf_incr_counter generic map(g_counter_lgth => c_PERIODS_COUNTER_LGTH) port map( uclk_i => uclk_i, counter_reinit_i => s_period_c_reinit, counter_incr_i => '1', counter_is_full_o => open, ------------------------------------------ counter_o => s_period_c); ------------------------------------------ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- counter reinitialized : if the nfip_rst_i is active or -- if the tx_osc_rst_p_i is active or -- if it fills up s_period_c_reinit <= nfip_rst_i or tx_osc_rst_p_i or s_period_c_is_full; --------------------------------------------------------------------------------------------------- -- Clocks Construction -- --------------------------------------------------------------------------------------------------- -- Concurrent signals assignments and a synchronous process that use -- the s_period_c to construct the tx_clk_o clock and the buffer of pulses tx_sched_p_buff_o. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Creation of the clock for the transmitter with period: 1/2 transmission period s_tx_clk <= '1' when ((s_period_c < s_one_forth_period) or ((s_period_c > (2*s_one_forth_period)-1) and (s_period_c < 3*s_one_forth_period))) else '0'; -- transm. period : _|-----------|___________|-- -- tx_counter : 0 1/4 1/2 3/4 1 -- s_tx_clk : _|-----|_____|-----|_____|-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Edge detector for s_tx_clk s_tx_clk_p <= s_tx_clk and (not s_tx_clk_d1); -- s_tx_clk : _|-----|_____|-----|_____ -- tx_clk_o/ s_tx_clk_d1: ___|-----|_____|-----|___ -- not s_tx_clk_d1 : ---|_____|-----|_____|--- -- s_tx_clk_p : _|-|___|-|___|-|___|-|___ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- clk_Signals_Construction: process (uclk_i) begin if rising_edge (uclk_i) then if (nfip_rst_i = '1') or (tx_osc_rst_p_i = '1') then s_tx_sched_p_buff <= (others => '0'); s_tx_clk_d1 <= '0'; else s_tx_clk_d1 <= s_tx_clk; s_tx_sched_p_buff <= s_tx_sched_p_buff (s_tx_sched_p_buff'left-1 downto 0) & s_tx_clk_p; -- buffering of the s_tx_clk_p pulses end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Output signals tx_clk_o <= s_tx_clk_d1; tx_sched_p_buff_o <= s_tx_sched_p_buff; end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

f5446c81c184739860128388445b44d6

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_LMEM.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

14de120d09595a397e92ed0aa2747f78

kennethlyn/fpga-image-example

hdl_nodes/adder/adder.srcs/sources_1/dyplo_user_logic_adder.vhd

-- File: dyplo_user_logic_stub.vhd -- -- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED. -- -- This file contains confidential and proprietary information of -- Topic Embedded Products B.V. and is protected under Dutch and -- International copyright and other international intellectual property laws. -- -- Disclaimer -- -- This disclaimer is not a license and does not grant any rights to the -- materials distributed herewith. Except as otherwise provided in a valid -- license issued to you by Topic Embedded Products B.V., and to the maximum -- extend permitted by applicable law: -- -- 1. Dyplo is furnished on an �as is�, as available basis. Topic makes no -- warranty, express or implied, with respect to the capability of Dyplo. All -- warranties of any type, express or implied, including the warranties of -- merchantability, fitness for a particular purpose and non-infringement of -- third party rights are expressly disclaimed. -- -- 2. Topic�s maximum total liability shall be limited to general money -- damages in an amount not to exceed the total amount paid for in the year -- in which the damages have occurred. Under no circumstances including -- negligence shall Topic be liable for direct, indirect, incidental, special, -- consequential or punitive damages, or for loss of profits, revenue, or data, -- that are directly or indirectly related to the use of, or the inability to -- access and use Dyplo and related services, whether in an action in contract, -- tort, product liability, strict liability, statute or otherwise even if -- Topic has been advised of the possibility of those damages. -- -- This copyright notice and disclaimer must be retained as part of this file at all times. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library dyplo_hdl_node_lib; use dyplo_hdl_node_lib.hdl_node_package.all; use dyplo_hdl_node_lib.hdl_node_user_params.all; entity dyplo_user_logic_adder is generic( INPUT_STREAMS : integer := 4; OUTPUT_STREAMS : integer := 4 ); port( -- Processor bus interface dab_clk : in std_logic; dab_rst : in std_logic; dab_addr : in std_logic_vector(15 DOWNTO 0); dab_sel : in std_logic; dab_wvalid : in std_logic; dab_rvalid : in std_logic; dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); -- Streaming input interfaces cin_tdata : in cin_tdata_ul_type; cin_tvalid : in std_logic_vector(INPUT_STREAMS - 1 downto 0); cin_tready : out std_logic_vector(INPUT_STREAMS - 1 downto 0); cin_tlevel : in cin_tlevel_ul_type; -- Streaming output interfaces cout_tdata : out cout_tdata_ul_type; cout_tvalid : out std_logic_vector(OUTPUT_STREAMS - 1 downto 0); cout_tready : in std_logic_vector(OUTPUT_STREAMS - 1 downto 0); -- Clock signals user_clocks : in std_logic_vector(3 downto 0) ); end dyplo_user_logic_adder; architecture rtl of dyplo_user_logic_adder is type signed_matrix_4x32 is array (0 to INPUT_STREAMS - 1) of signed(31 downto 0); signal value_to_add : signed_matrix_4x32; signal cout_tdata_i : signed_matrix_4x32 := (others => (others => '0')); signal cout_tvalid_i : std_logic_vector(OUTPUT_STREAMS - 1 downto 0) := (others => '0'); signal cin_tready_i : std_logic_vector(INPUT_STREAMS - 1 downto 0) := (others => '0'); begin config_reg : process (dab_clk) variable index : integer; begin if rising_edge(dab_clk) then if (dab_rst = '1') then value_to_add <= (others => (others => '0')); else index := to_integer(unsigned(dab_addr(3 downto 2))); if (dab_sel = '1') and (dab_wvalid = '1') then value_to_add(index) <= signed(dab_wdata); end if; dab_rdata <= std_logic_vector(value_to_add(index)); end if; end if; end process config_reg; adders : for i in 0 to 3 generate type sm_calc_states is (S_FETCH, S_CALC, S_SEND, S_FINISH); signal sm_calc : sm_calc_states := S_FETCH; signal tdata : signed(31 downto 0) := (others => '0'); begin calc_data : process (dab_clk) begin if rising_edge(dab_clk) then if (dab_rst = '1') then cin_tready_i(i) <= '0'; tdata <= (others => '0'); sm_calc <= S_FETCH; cout_tvalid_i(i) <= '0'; else case sm_calc is when S_FETCH => if (cin_tvalid(i) = '1') then cin_tready_i(i) <= '1'; tdata <= signed(cin_tdata(i)); sm_calc <= S_CALC; end if; when S_CALC => cin_tready_i(i) <= '0'; cout_tdata_i(i) <= tdata + value_to_add(i); cout_tvalid_i(i) <= '1'; sm_calc <= S_SEND; when S_SEND => if (cout_tready(i) = '1') then cout_tvalid_i(i) <= '0'; sm_calc <= S_FINISH; end if; when S_FINISH => sm_calc <= S_FETCH; end case; end if; end if; end process calc_data; end generate adders; cout_tvalid <= cout_tvalid_i; cin_tready <= cin_tready_i; cout_tdata(0) <= std_logic_vector(cout_tdata_i(0)); cout_tdata(1) <= std_logic_vector(cout_tdata_i(1)); cout_tdata(2) <= std_logic_vector(cout_tdata_i(2)); cout_tdata(3) <= std_logic_vector(cout_tdata_i(3)); end rtl;

gpl-2.0

9686c6a74fcedd114484c1dc2b6506cf

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_prim_width.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block cqJciZd04oy/xqN/teer9KNKZIZIVlnG7ajgn8OzB5FAas7j2XRIV6Yyd10dDw1rd7NHoaBTTp9o nw798sfS2w== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block NqH+8VdO2PwfJrVZDuDtAhaTdX/Uv41nro4huTCFkpH9AhLnG8N+Rg0M5GHCNqXCY3/mZqa49FbQ OxtJc0xNztbN2IHchIRyAYyJ0yRFxhHcPfD8ucTRJmZVoo9i4Mp24JUkwNV/EQL9WuV69E2+BnvI 3G9yQPYYqFSwrr5KUlE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block fQjnREVyzaDiAoh6Eu33/7x2ljlAJt2BcpFhDbsRPwfGQ3u9jKhJUz2artRgOulGQ512qjCTdwOE YnZbqNsPUptM0myHlJBf8VeVCv2DuqjGj3SUadvgS5/GZfOvCA7BoPh3Jj7Vz6XqSPukkiBGQ3mX Vk86Sd0lzajYmpmLROlqk9dN8O7YzxtjJBD4WC1h3zMpUWNWUfKd0vjpB7I12Q/UKkHlkd+uBczH 4kB+r/xO3MZ/JpJVo/j9R12IPbDITtldKJL4h+YqNFHn3XvvsYZfcABrEUkaEpdo7U1VNqM+gcwK geGq62l+Lm/hk7CAIio8Wb5k5weg2+Pg9THkxA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Iq1tnz4SgK5jwxP9m5pg9IpL7DylAjKt2VwX4nav172vBA7kJK04ZRIn8vXKrvb+V0/9rHtFa9ve FjUsr92sGXlzcNcinK6ZzMcEU3l8jDuGPvRnnuOLq355pXCuKAEkhJ1AH/5x5boo+LDBbDYFygHX dwFI4CyLhrbaMJYXt/4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block hdvgbNGerqs2TVl8wuRe/ql9nsm7xb306R/2izZZFQE6oiPjSdo35a8pgFirVEofOBvc4H86rLDG qwsD0pk0RJhJwZZe3TWOjzZuTClB1E9tViln6H1/VUa55r9ztglhNMK0ZRHUyHFtT9r45/ipIXaf 9bHO/KUcwpOrVYi6Ajz24uUFEE5YypdW2sFxx8w1CYDPXVUWtq67tKSi5P18UjG80Gys0178H4as V2Y2SKcZx+Ze/kSgLrn66J1GFPX7u+3HamwvT9fgP10w6K9RCnj/cgx+KWDq/+nFEND+DdkXUhDm +txuM8Z448q/u/jjqm9olYfT6+vX2ibMJt8leA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 51456) `protect data_block flWFhEsCaLXA1tzHYhctP9wtkWkcMIVfpxtGo4rYf3PDNkFAgAr8Csk0Y2l4CPgn+y/5GWjO2RcO lU1AfUXYf1go4/p9lsz1iIAXRswdwBYmYViSlFJzx11UrACDNIZhtoMNo+HAeNiO50KF6ihTFk60 eX0gGtyeOXID658NIrZb5xR+CRMF1IhmQR02hG6eyEudPeaNUTsSWzEaCB3hVD8J7EvPZ3TXqMCz FV+Jin8as/qKfqHxQsNoGzR8X1qe7F91je50MG/Alvt3uySziiac78xrE1Y1n4oCS1f9GaawAbOr 05gthyV+smEpUH99D/zqorVTEU+of2ykd4Xtk8sqhgUa+Zur8Gbzq6c3GKb1kYmF8HuKIvggmf0v pM8MVGK1hmqw75GcVv7IGWaWpLYLFykt+DHCqtjtRw/0ODYQLIWx8mc7yvWQJMEhJGYi+WciJGWY x5gMcTx/y194+bciB7dtoeHkkkyvHzv+CevRM5XqTvDKCTg+ui/Q+4VKlDz9R9WyRsb69V/Emg84 HX4j1vlZ69fgPEQL4QqGBiZwE011/QqYoaQ6AYDT5tXNcvTguUZiJaS5Be6334nqHHP29Pm1yCZ+ nVrIE0ALy0qv80jf+c3qAtxdhcKgLLaPvDoDjf+RKywm6NWgL59fpp9gPjG8xM8rtIjb90cikdAp V7V/kcL95jLrpomBCHnOVnXIGTqsTu254lqIOGgaoeOZh5p6GpFiWBpeRQaLSsYZsPLVr5GvflX/ cTETIMWtS5s5O/hxIb+L58SpmKYpbU9faFChorxK30iZ/lj/P1eXnqD72I+ae7qP2x/oWL3HkuE6 uwTNiSsa88EOu6QWYZU+KL++ueLu6NQkCSsK1FQcKlZ9u+9CD1rm3rFr5VctMcTSzxYZJb0eYUxg /3yTLtQbloYuOnKqfO4srPFuXtPFIPg+bnjKSbz/Uhm9mbPYcyvraAwxkZMVRKf9CSRa9V0/16uo Py008NeCY7DnhN9No0oCpcQFZhzd7K30dwFjXLEKWv/Km0Aj1D8DHonBNa6MI8p07kS+czKJ9zS9 LMjDotrCIIZYv2PAsxmoMOIszfhv/A7KiOBCVWHzfEs2FeGsLBXWHl71tUFIfcJ8Dw3idoUM8VRe SsgzWHlrty4ZXLauRBgOKpVo+1BY6WKAbCt+62c8eVEMS8EElp3aGQYNtf2WNtIxW26FagJeaEGD Vi/kmi/DULzNp1726FerYCDq6xnpbl6s69m4/GlbZ0jlbFfT5uWKrsmkCpmnubK0nTpUGAC/bwQr smmFr+6/Z3IpG/jo6m4Eek02i/1WIwzoQ6GeU58sGcQGRmn5vRGAN1OBdDRCLjyDPDELerShZ3Vl NkU/3i2opvkgyUHptN6n7dD6x0qahmM3E4Rm6Q7yNpcNhicABu31Z9RahyJjFBIj8uNg80qAx6XF URsrZdcc7ZOJ+mCS5Gh9vDCqDBkdDEP4HIMT7qi0V0ry2DRxXAn3UnnNN1fAF431Kzoq4c7fKWp6 FZU6tMTj6z25Mg5dvpT/+r0ndrOUZe+BXy7p+Ge4uGfDgsSD2mNX5VhU7n/OQ3YSe35IntqmjgJz pYo8xev6+VHQ3QLrHMgUvGnetCOux5qkSlFUdd8J/YSensHMArsxfqxS1Wes7mDhGpX1THdeji5Y kDPiAk1yhCDlvefN5nu64GvrpXBEvLoKX6i9dAcyF+A4nDJMxGTgpA8RjTRxRwCZS+gOUvRKcHAY u7jfHnyzTvElGxRpstg+e7qu/ofPjHJig0/rtYlAsWhQSY8qrwwE8cLxZkBn4zvPTHYpeYc4nce6 83yWIWxA7gXCZe3tUblz5sBFEH6OA9xV5VWxLBsReuk6VZfnciavs7COGQf4u2eApgTg4JMpzgmD hZFrz3UQtq3eGZIzI0SafMKhRXsvAqZiTVkC8uug3eFNV39NE7h9kJATpSAmSIYYSPXIt+UigGnf /KNVtV5HJHX1aMXaByVW9FKQ+k6WAFIPnu5kJOthpR5cQ9gT/H6Mmy5OVexx+f8zWIXFOHahYav5 ED6nDhGBTC5kjjHIlbW0BKGRXCtsUPlAdLGGRPwq+aHGyXuHFZEMwpg29EylOLb0l+eCAIJMgFar FUPM5Lqx5Bk/9OeYwa6y4ii7GAP7EBbdkqmTDNy0lJvRryMa8kTczI7/DVd90BnxfaOYqfBq1+qE 9zRPdSVCdwjLWrLQ6NcYfwn58kRx1rEu9hqv5sfPuODn6WAzqsAcCKia4vRbPE8T4GTUq43jTRJD WWPp58uOn0A8JF9yOwYJHD9mWnTh/eiDvp5sCqszu5VC9ZzR7RfpBpVlHonACWXz7DtVGzlOS9Py BU2MYXuRmWr+YfFh6tFf8p4vdVEn02B2kMrEhj+zKex5Ae88b07WRPA/zRykbYPO1OQ7SU75zLzD caWIUeqkauYUdqxXduQ4hPZf3qcYTsNZzf3zc7POZzcCClCsK6YhlPBs9t9j4ZrJ/S3W0rJHVyW5 nbSPgbFso8K20F04kMEgxS9IkW1riJuctoCp6oqGL6xA7dJt/towO7Rc3ZWxqxpYulV2ye90iGA9 QufF5SZcOg0iqMHpgeXtR17L08GMXlW1yE8tgDA+6ak2GwLXgMu45LJnespZ6Vbrt6A1gYHFscvl UCh4QhyHroEpljzraARbxG3uwWxiy/Cv4LkWd7XIXvYtwvmFvwlGz8fHXlQJfui9GS08ID4csBSA 3OIO23KpaUAyEJC/WGQItV8lOUxM7HHK5zJgly5SOdJ3e3VitPSFm9yiFxvbmyBOT1s4zOR41Eq/ shi2ZstRMlgODvYE8PTnwE1MfrX47yxY6dLz2GkUgeQ9lkElKq2UOW/TdTd+DbLPmAmkhPxPQvSn g2RUKFEsmnGDgH55Y0oFkKnLTrd5CAcpCU1MGxIWWncGR3p3jbs3TDaEoqq74khIcw53l+BaZcO6 2XFdXVUOgl4GxG238NKWwPMG2Bzu/VQwP2XgsbJDSKeOJw7d9ezsvsF1VtUnM1acodjSSjrqr/0Y vuFpxhQeVlELlQadQ7VR3vWFjy9PBuXuyMrlZpURTxiMAd8fxKiQU87vbKLFc16bb99gPESbmy0Q 4QPkisa7ksPaodIYLTsA+xgu1Ta7xFvKw/W9dX05Rtspky/Ul8RUa1Mub+6jM1gRR7Os6WR7U7+C TiPMINeVEIRhfFBWSo7PZr3tw9LFfvNMJCgNF0wfWyiCnwFGOwMBRwp47FVghqdNDae46iQKQDmk qXn1Eob+fhR5Up4QWEKwQjfT3LR6t+TXftCxYNIqy+kmmcARSgOB3RNLwDVbH9PMtC56CHcf8jWZ 1FOMhZS2vFsODiCGndV/r3k2q/C2TJm+NIEVMeyeyphAURp2OBkQcDXN2bSwgpYfbvDUgZB8BKvM v4B3HJp5tn4XPK1pGn7Na3SzsgXBi/399tIFyJKOcHqaXIf+TNHTJDarEhQBpVFM7m5HubCPy+62 A8fMS7A2vbAJ0jw/9Pyf10vdqt+D+s33nNKHJiaatNWNG1UYYKDr/VLEM8gpcFBZwSda07tLobK4 wP3w1b87lVY4KkRkuvs5AJqtFhjt3p/ZcWO4UdvDgtOQODEf5bl59aVQTq5BzJ012CKOUan2kiSx tpn6/yNU7MKawaBsnmNHaPzjGPVzbswbiGozvBTbBtXHQ8YYXHX9apdDW/4s+5gKqXVKAR1nnUo4 l3uRJ75GQCq22duZ4z8jNYPZqkQDX+JeB+OWlt7I9t+JFtdhSjyFRd9jucgLXxIQbcRibbDj1sP5 oGdfRU51JB+yhGeX5cwm/cuitVInlZXxmDvwbFMHwQwdlnI84bEhft8/UlmdjrhIZc6tn6q8ZKZ5 A0Qj2rQk015WGps3EzNIG4heVC7JubssaZhczVCop00Y6e9hLbOwAbZ4/m1q8sWza8C+PDRsMY9Y YGlJQSp+3ln/2o/G0PrOjexwszeDLoym0Uhlhc8c5s6yEUPgd8kbNadvxSJ/eXHKCLVmnnA7J95b HV3JCOTlgNDM1iXhb50sJ4cDsOAPFy8JQgtXfwaBJ65K3DEVnHp7vmRKLQSBVbKk6ub7I2jgMzve Msmfv0e6x2URqSDhdpxOciBEqdPr33RSP4oitI9qBMUEjMrdNdmrNm9/z7WRJP3lYDrrCuuOfr8C EOr6c5dTrL2dhFxyjoffRF8bKz0eM+boQ7WThZMzxCR5GO971xzLXJ45M1B8n4pfJEWISk43G62Y YJAeoyouAIBUHi1uWRVP9Zeb9KUSVAMlWC1nZxaxsSSAuz222FARvQ6GnWY6FhVWi84SEUgACuaw MHfNiH2Fy/tah1PYPicJrWrQhGyNH7mgIfXLnO5VdGeANp5gr4cYwaPLdmtMDLNu9t6KX/SjqAZ/ t1iCP6FoOYHgsEvVpjC5dCPEOTYS6EFSgoNxatej9p8jER4lJM7SJw5QgRN5yMDbjsBurqy++wtF hcErcWU8TnrcvEEHmhsg4Cesv+oLMOkyd6cSUZTXeR5ZguBUcEtnKHSGJn7semyRNgxqZH7TmHAq c9FMYYE12CA4YlPlrUuWATlihFhv6vwzywFb5e77kl4GNA5u3XUjTdOwqbah/lBIGolygyEOLg5M n10rrGfGwzE2bL+h3yWNGipSc+rZEpQrbhBcHvXTKUKib4Z/jdGKTYiebfiJt/wJufmP020ZWqlW 1NQvi4DfGPre3esFVXyUSCCOo2Qp3cPK/0G/Tjcy51aibtJKStam6xfFCpUnpP+6yMOHCT99cnCA anj03r0lf57xX8x81MGpP2z0VbqtPr3bAf3J7xbmZpAK4nxJgu3uYyk62JH/v9tbF0VgvTJfRaMk uuMEZ6c8N/xfD+kXIqol/sSW65GIkxv+KRTcouUvaUo+m73qGNfIWO1U9GLnrPzW8oXVaZjlEkxP dNzGPyjRdV1L3O4Vyz8OJg6cTZIuny9EjGKIOZZcMilzu3GgTRe5CD5HZtPTWv96+s0uKS19xLrT 4CJCZ6iCZZETEPoez4S3MT8tfpzZ66Rsjfaq95xyw6eXCU85DdctJmrl26GOkzOh33fUBUuL1zHY TUMifgSytJkIP3WfdT3FAScwfUSqKh1iG+UdxfeSAJvipx3Ja4joVokXFOjPQn7cvB4BvR6dd6Ia XdUcUw6+Zg8gLabEvHwWErerp370MBJK6BS5cnvXd7OOM2iN0s/NLZU9alSIJry6ztOGBuZEK53Z w8nA8XCzDEsxUJDqC2VLqYHZ9SpyCw2FV2RmTRP7tCmkB4/LIhzk/8AVxHkJjuOVWSrDYc81B+hY B+J9bQsj351LEIlAZ2spbID2x4hRf/yn9LdP6tSziNRz5raczao03VIas8zKUlFjBfeXCABr/uT7 pzo7sL70KN5VTJcfDOGjiXokT7F3Y9Rb0Mbey/eToK+RBs4GKy3o9E/x4dXwGGm7MDV2Q9PtcWrl 3Qldy5H+8yAnXaDt42rxQ11T9jLoiK7Fz0C+6eDiVpVw7EMUeOhTONF/NIl1ZppgmHcugWrNcXIb 73Bof9y568ZnuKaZCpLPwR9pwhPBvFn8jrZ+IywXPyHjLYoXqCSLWPXNWa/Qm1kHiebKcc6NTwbp uugLk71I97e/1pibcWP0floQDkH7BRyrqIkpU+OtXnbGZJZ/t0ZqIz0yDK3tjHd3zp3KM4+gT5iZ ffxl9yMuWXSbbBPjrxHqI7IDerxiMjxxje6sHEsl0nQJlT/4/jK4nwxgdFK0cgtVEkAsNlcMZEbf 3CgVuRztGslF90j8+aQdhbQod6BqrXmxODJjvZaXUqPxyFwYD6M46pYvhw8o54uTcxzXlZctVPfq aOxNM4pzeKmfeNDEw89RMD7CoiUzf29NBSY2xjdUARyTLjoD/Xvc+LO9qcx3twC13rwB0HPb9SyM 7HpU035k1g1h1Vy+n7yGV+N2r/Hu94MXI30tKO5lnb3fUsEc46lT8VatXyAHLWvoJXbMIHgWJWJg ncNJlo0kTM2nBR84peOyKs3QjQ7E8C6kHd7/CBatymfTpD49DHgcedgObHayba0qSFN1J1eHdk86 ML4UJnwMsXHnN24mis9prbxn1v98iGc+xQhmEAHGy3nm74oDCYWnRHhW7CdeEXesWX1Nu6W+mEU8 2fwKSqCHb2hznF+BHPxm+n8lN7hSy/8l8th/DCyrdg++cJyW/VQ3Pw7Nbgum2XLisrK5GvjzooRv DgppdZxWrsDK6Fm2gXSMbfXyPfQA7iQICHojcOYm5b5Ah+pkSsybJ8Kc3TwiReiTe90PhGt/BUiK ziBOUvOpJGCf5wtJhChwNWtwYXROsDed4F3M+8bcCk5vIp39Qeo4bYOieXtCgUGlVFsQY/cJs7vn GM+pJnw71noIl54iNWDQatV5KAF9oF3Tz49Vax2PJxcR1vBavwSq1OGExD9c8Xh8jdRWBi+7iVpE KxvAOYNVai8+E47Jpm71eLKFtBqjdfRqmHiLvNW2nGSSuY1JAxlvTB+/mLPHC4Wd/oVlxEOckbem Iuqf/OIDG7rWNKNF8laW91GSOezYN2OYZxfdW/TFgUEgrIckVVd1Mbo89VI/QALQLPGEIC05u+Rb xPU+J8o8j3kYaQSwkfYEaiY3LcTbYiuorIbSFv3UCHNLBzEfHMT+oLKa61Kkqj/timWHyw/ZDecK A807i2+FgvlxHPsXOkKW4LTiQyctURuplPXg7fUABjn6Edx9wa9uzmwzYBH1m+iSiOQFBQoyxXdM kv3NPFql0o/IxORbGCmA2Hvy/BPk/PYtHzlWiN6I4eXNeyRK1KgILeG1QUslWbW3fa+zOvZVgvZi xKyPFNbbhtg9d82GTLjUXN4f4xBe0mGcYdXBqNHOeZQSKKNB1HbggT5Aa2Sanvw2KJKxtO9D2Uv2 JwlYliohmM4oHhTydtVzGBE8hIATym3zVvNNQUdxQ6Bas7LPq7lL2d/s5MvVqoIX0KUgrgRtaMLo JjAlZrsbyY06W7JeNpD/sC6KBHeCpn59RPBpA/O1eYl+/B8rwW6PpP864aU7GgXLtDN/Q+ImeDvq k1Ocg3wjPm00tzjqiLRrN7/ZFU7RMRJYyRvQSEO/yhsGdi9grMSEhMdjQFF+Sdp6zgay5CXFr2z8 gp2MZqBHSyxd/X1d7iBr0Ov0W4Qz1dW6KgTDKW0dlkLCVoiy+MTQzyyOv5ACMPopAIrWbl8PqYqB 5pdTG4pDiddFL3vQKYnkyEqUrvuNCNdqCNxyUY0/R660lrtSroqP5/kEDN9VvXed9I08HjdqKL9W ea/AGvunmiqBpaifboJjPHk0NZ2sOFqwZuBaqwo2D7w7Ub+m4xV300kC4c4Dk/0PWi/o4ZhbfOs+ e3Z4yOIMoCABPhaRKkRVkuDIhlHV25Yfd6QItZ+SATjjf+CNcazf0bLzwPscF87UEFcoInAHRUsA B+wKJdT4pdNf6dkz4rUc5EF0W1QHZkeBi5m6Fr8HT6G92aqlVjU7TYax9TetjCe5ps0pjDPYI/Uk eJQ/sL+wNh23bz1lMgfH3f3tBKsSDvnPHB2F5FYJvgV33nTYJyJKPU1/jz3dKh7sUe2utSTkxQHk FlHn/VZpw5ln7gNRTxtRUadgHROQNgVKokbeSBn2J6EFR+1Bu8emOtxxZRvasGfxUr8H7cBsF3yL eXtoM2vhGIJTp7Zii/BmiktaSLjnCxms8xSHn7rhDi3nY+GahiJGOePZLugsHtvV4fD5E+fZKTkr 1jeHHd/6eNhWrf4OGcjfs6onJOpYYIgJVtIuivuCJRilSd6nS2VNbHs1G0C1bGU3y1ULSdzy4t/p N0FQ6dpHOF7RAFkoD+G+MDQad0EUig3LRh7w8MPzWGGCoFSdhoPuj23KBkZ0QqMK08Ms04OBwsIo jsw4KwoUzKfbmrR/UAzYMMQXC3L+D8ri6Ya3Kk+kg7ksLkKBVwr4vHTuPwLajCDYvc4NabHzeHWM 3lfhoHNaXhpZXNufAvMd0Fv2X9uK0yJnySgWkQWRT1THsv/dJTi6gUo8PLDGpzqO2TItVSoNCyQ+ h9xjIGPKuBvVXRiyUsVI4eg+lUOr3kN+qj4n5FZTy9VJyBrw5DTUsnck2VMAEC0kv6XaDoSrCf1j goEK0AKnDHupwXFCtej1rxNTUuFcxSGRTY/fh/Tu2q+gpXtF1u5xCBHpkkj0e7h5r6yAeiyRM/c/ XO2paJOdQPvh6CYtdo7jHDSemiyZU/LxDD2hmWdVNJisUkxMJFmADRP7gDbhNmnc/rvLuctbQoiY K4SZzEkI5+UwofJkBiVm0X7HrVPwIqjuFr518ArOH5aNwDRKL9b+9aJRvbistmMEDPhyXD3684u9 vcGVdhNg8j1xsp1BHFd7HiSTq8YAyh6dF7PY9490NysRHwc6+fTQKg4ONQUTo8oQz6XB7gERJyjk y8YR1cCmSseY+UgzobOd0l275wNdAopCLoJ1fon21MPuD9jwiUEEnvWMRTZ10HRy6l74nHpkX8u0 3Yhle7ZItRCbYCDz663Wl7gAvkH1yHbEBZPxKWFRCEzCyH/t2kP8MRMLLH8vjMevZDIM7A4R+jBP wzuSnPnQiBJuMepIDp3ItM1Do94Dnlhjfsp+9wV6ybCwuR7hqk/EnGHIBciCtlxOOstDlAH2rkEW kW0BT2uQLvGZJfVO8x76Lax2hU5Cm5JMlRGdyAETuw0wmi7Z8NQIProl2nhqMSPa1I/IILbUZQ6C BnxaGjtd/gG8JzgFDLYks4Ry17WfI2V0ydRjqVOEqkD7n5GvjrhBprCq+ivjc6ztUkiK0v3dN3dU L00AmCTxTkLpC/DnK8c5mVLtc7zeKVHxoYu6tGzPJaCNrvaWRLwNkiC0twW7SpTxGlRFRRw9QNim jxYnWGi0zWEJAC6RpQTpkRSYFLXSqDDYvUhjMk3hHkD909TO9k7wy4eILzsxg+bZIoYJc/EenoLF O7CWZGxRdykompLkllrqfRvddntc+AYZvyMDWyT5vv1ohTdWG9Fr06/moiWoVEWbW+Q/02OiY+De YQISCx0t/Tqc/SUNdTF0SJ25EszxsOoKNjWDoWHYlpfz/Eq1yMiIYEa6WcLupOYGoqfEXKr3gBFI eocxI0CDdgg8Q5JHixO7UqM7q9sYyo3Yp/j3/q0nmawvwu4tlKiOod5xEguOydVJ+44Q8qmz4MF0 pQXNQPXPmUzutOcfZ6vaHMe/tfrWFB4R7MDQKjlhe535f0xM6nLUaK4r0E+8E8rTllNyS742aCrh eX1YA1auXSLiTCqUr4jI69FFXm2cgJbWe/6Jlfw06Y6CoN6uPUDbc82IJlIi7unsDEsK0mPY2NDj 3ppPz+vlajjh4hBVopfESGwwu8kJr6aZEaYPml9tH3/1KBfm7CL3+SxZd7CrlPSy7CLWwWWylLaT YxSgwmyx7JiYHOYA7dN7W4wD4WmBmApCZ4HdtAokER8GP0GAh6uYSqtP0Ataj4n2djCFtSieafri glcl/zKWbAUS1gcHJ+8lgyIBC//zoyviL0a5jreBsN9fl0oYkNLd0DF1vgVetSHo1/WQ9s1XPRQP 9kF8M/HZXzQHCQS2RBDzp1vKfF5b9zg2ENMTTHf8lFp+iPBq+txzVkCsqQyMh79Xwbbjir2ofbB5 +IEcf+RL/i/AZ66R1d01x4sLUCm/oQNbGAlT+TTl02kQ1T0s9iQLJAaJpmslJDIrnSzc0kG6l2j1 5sYpucioU+Gbbv+kLMxEAC6xl1K4cgRELBLv1Za8aqVxJ62q8ZtiyhO0rC9WV8XyImK4amWnFXOD bugIYtJ8v4Uf+HAC2arxPkegUQZ5pwG7R3r82fx4oq2HbDMsjZWS+RLU4r7778UlDk6npb98GMOn AQDrulCXp/JgIkab29zB+E4E4tTyg3VwLIg/gMvNaXeQmjd73sRpCg0CXd32JvKqv4cPHxTPZJL7 knphhq+ZRGT993Byaz8nviJkHG/FVZmut/ZWQmXorsOTkRQosu61x+VY21dds1gWZKab+MAD/HRi vF22SkBs/K1PN4b2DBn+MNlAlMrdzS4QzcjmdSE7ejS3plCAnP07qhxRb5cn4MU6hWmm3G54DLni iauvtYW0X720+VKiQBvdMsPcTMBIFj+3XqFnLVMKabJoPkowiFz5/j+qumr6mwTIg1aKtAZsKG9D azbz52zuc5Q2EH8f+mPL4T0skKTgbfjMdCmxZmgzqDYoch6lvo6cwDk3niuacCv+KlXlTpCFunJN qB9DLL1NJf0RFvXskkpmrycwZB+oBQ5ukH3xFYt3SSO+UW2nb0SA8oK8eJ8h1kbJdFwchqzEcrcH anU6mkIHo7rxfgoQvOJXGcANRWumjxulVfEH1kdZCS/HWaFthuUIOYuoTGlcBP9r3hYMGlv4Dc4c 5tBqwsKUoD9P0/XUTQPF0Mo10eRQkZ5YP/POJpX4B+Mpk8tOSLwKgJnhYFGdFjvg6SfEirldM9D0 wJHEIl2HMlfz7lrd9M3ykmQ8eyviH4ZvQL1wz3jVquFyIuerwbqBuk7+RQAJh/LasMBCybQC03/R yFEL+A8ayY0P5AE0sSnHZm3ofHTnBylkL7Y4jRR0uyIjaV/A5UGwIIs3Ar61K/mxE2PHi8aM4mkh dxuoF3ARiT3LUMqP+5RUWvoAAiJU+HwpIWBbKsjz4hMMhZYLlyEduRgugeSvhBdx/QSRxwf9r8XM Omr4D8dlrb1KtFoAqAo61ZO3hZOQaNFmicDHOBx5E4zWdZ6+cogOqUGq8pYP5D1811vJnu4ajiVU Mg5/h98o362JTNifoG0fNhnAwiuvxCNyWZ02X7PDBdyqLbzcA8RQW+ZiECUi2vxIuxUAF+p/Rg5+ eWfv4jF8x5M/OAiIroR3SgmlOKFsiKQcnZiUTSNm9tzuWR3FG27aH0ZyslRk8DBDJ5gN7L3WhkQL EqC6sgQM0M967izECK98o/EAAYNU+t8OdRiV0ahPrF8ikHvCR9h2jFh881EPSh6BvVgB1JQEPGSV hXSEcnRhwJURBADVkFpn2dzSinJ8aflc8AKXVdgCahvtRngCd17HXIzJY0DgWxyGv70XRh+WQIn9 2eKE72bBbVZGpVi503VkFsynqulN1QB6xemYKjqrADtPgAUJ2KKLpKXt5jofAiP0KHSQKuptlvb+ oFrZ0S4giPlMicii8IMYVsqjLupmw7ELcoJd0JYXCOpbr3nakkovaYURJ3SqD6kW24+8m3LZxTmG kaCmrpWE+v/DhD5AYFHOGMISnLtaTOV+8oPppEFHTU3n+4CMHTCdUDJeEHFy4+Q5h0JWJ/U42WYh o/83omyBqYNS3Hs0leI/L6KGGmFLfAxi8IcbKeM5vA8gA2VSpMPU528vwNSvU0iLNViJ+8vHtkVt bhzDBtSsVAovnX8I0gcn31tLoelZNn+2rW1LFUHKTsYOrAQq0d3Vu9s176dIIA9CbqOPsanjjOTO 2NwbRLjQsPn85Mn1M1Hr5GdLkJ5OzNmAF3EFXhSFGLf3RlbkQdRaZDkbloC4F7Nb8NiknEPJK5RP tguSEcop0BJlyefo8cNmImgnUkqKJ8ddbKgNRsDyw/O6p/TnXvUfHIffO7zm15QDxwh5QexDBAOM 6M5RSXhFNgLiCfDYNPQczBHXGowxt3NxbxUuFd/ZcEEqxqS4IXgfhBhmMR3bwh4CNAeDYupsSKAz X4KULGM5+wELN/S3ckNbXX41RjIhNrb3jYsGmrFaaAWyuW9e1fS9f7o+WNVl6isOcYGKA2jCz2W9 ViytRN1Smm0rIuVZXl2g+ps4J6Jnu+LPP48GY63+yDGQbqMMxgRsfOHvEVNoIFeZSOvo7XehY587 gC1rBTuu3DX/XhTkHGayF+IJxYERzQ6oNhV3m2xdlZJeJSq4BL2XXq6/KdX39gXZilALqeGHSYVE 6CzkaiodEG8kVL6NFdzqlJwG68sIRHygNaJy72dDwqTc5hIFz8lwN9691+od4KyewDy1rhgvYj6I uSLkhGx82hgKxGIzOosNZxj8wg6Bs1jcb6In7S3enG8x77QEgasKCYSXPWbLxGJmgB9jJTbMZZLo irRynhXRYoL1k3rBuk6R1XCRTrxLkUVgAHkY2jRJ6BwdQJ2W3WFC69FvaxNXj1zKwnYwkdydgtEQ zQE7XUwTeI/xttcNHx83WHCYt6sosT/yJzYTLhFnxl1bspkz5SnCa6SLeIJOP4m79Pccf/h8bwZs rIkzxAa3Ng6fZtnMFRU/5QZOpGGuJPwVXuj0t5DyCqVZakY+7R6ox21+qVpv5xp/X78sMWMa048i xr9fhwTwN+JVhHiCDqQ25NN7F35Rfyt3P6mH5znXJ7CG/U8bXKVQgO+9h3upX87GyCEimusN/7ka wytcghIGKJytfuWaM78JYcls6b0KXq5fLeAuKwKEOLJXXqo/INZgQVsUr2JafKhWyIl4SyZ5L3Di bnBTSEZTfB79P4QhyCjqEFBn70k0YtbDkc5MYxCUep+JlghwyHQE9jmC3uhP2MiNrCf5j3uhWuQe Za+KTU9SOml1qm00nhhioEgMnrCpAQ+PEVI45FjBmi5HR8no+hFpaKnIDip9DUeBfJ2TwevG0s+C 2xhY6LwPVZULf1Y9xoPQPHD3s5T81Igy6QptJ1eg9d3Er/ikVbKAn2a1KS1SZzA+p2KaDNDle8DF reiLChPQahsdddPi+M/gqLxcCi0R573AiUathDWb8MGlPudTSReVQGMg+cbipywSmZwn/smGO4/S lAbvI83324IQRuU0FLCeADTWp/GwtArHAmbya2WooKjicRivNuxUddbG7nlg3TRaW5FKD9wSaGne OO7X6arBct6pjslhOdbI1kmRag9WFDKiy6n6jfurAWjjci/9BIF5KqilOmLdVhUQOVnKnOgt3Qb1 zj5SgOI6bNpl8098DX57E4OvseqFuNDWEk/pk9ef89RQp5ExeBkBen6KAOFjkcgRb6xuYoh4qwx6 8hUvsyufLTeBWYv3G/+JxAJdc0+lSX285UhF4MtlDRSmlXpJ7zM7LzinjqTcI8Vbx41RelD133gr YG4fWgvQjEu/u3tLCoiNGiZ9+McUCySIoRegtixPggLgsFGgi6oQkBOlIW4JEAPwhGyyQvzgfPZW KrOVpILgr82dlxxHPObvh5nAvlPqhDpYjZzP7TlViTynsJ/4lOs7vbBkSOTmnBCPtDLiCwGZjQux i4oYRcT/JPXYUDqsn/joliChwV3XGxXnqWk5BLS4C6cpct9gvUKYrc3026lACcampRtqgGHWFD6d G2Tyyiak8fh3lbF/uxGEWatAPvkr2xdqS4S4NXTyWyKVXWCTpuxVZR1wpcgP9PRiBiGkktLrrD5s qi2BQ1f/H/1svrB0trVFsIvss1yT89clD+ozWTCpwkonQrQcaxBDKVoIgiaVG2yvaBNLPCU5Q2vC DTl170/pp2+TfnhrnCiggkXtJmc9UMDyxdMYRQv49slZ+z8gbtzEmYR6t3mt5c3HjuqU27/iRtMG fixyNEUXrLMtHWJJtTGPmQ8IQNLwKl1AEvSUMcdGBstQCFbNgID6selTbI/thUBVmfdQvxzfsJRh XvS20WehqMotdpyU1vu8L2keQb9Mqyq0hXvlnLG9SVaDf+BxCjusAwyvFgbt/yxYQ5xKsmKn8nRP umyHvOyAQu9x5mv+zl4VOUiW+mCl/55zkTicF0nw8TkCXg6vRuBmZysxyIQa2KqnBGE/Hco3al/t LaPsdUe5VUUxN+cU2+ABJEB0yNYgfWw75KdyoBSwFkONRr80wUe2UCaPHlmBYjfAYcFffoGhrWuF C6gMNSELBMH5rm/kn83U1m+oO93xlCMwQ5k5GyW1fOHr+AuuEpwgGTS2ZjajYFdY2kXb+YOWZYQM +EcNJJaIWDM4hHCfznPOXWcyMM/59GVg2+B4Vjwuio1kgdIeVrR0KC5z7VzUen9bABJQLdJ0Ikmz 8agtwwq/kmXhMb7+raTdNkCGIUcDk0VyXswwqq/oCLbEDXDJ2iAVGxlxwIPrzyOSuoaGPP2ij9zb M2w7X4xGicVjlwGm/ri7YkeMfB/69ulIGsl1jeT1eM4EyeCdtXqe9c6TxMNPUatQ7FCarJ/zJ2hT +U0+r0a1RdAto1Yvz36kQWb2lnZtp1TaqpX7hesukT31HsmrQRtc4sn0KxKurzYwhfGQAe5iZmNR FvljqHF9ESqGZ+2/0GYs0hXWwC834iIjqYN61AMtg9WWkThiySMt+RN+DO88pLIZrwwBTiEFcVJh cCYn35F8jOUbjvh3VNLdOrDn6NAyQEyFg5I+Sb8lkXkiNzwi+yU1vxTPPTItnGNJTXkDAuGvurgd yymoUN4zsrIHJrvVQP8hadoeS1TB6EaaCbOayEtU3LphxnUlE/VnHqfDpFhgjSX//qDkj+k6ZF/P 5U9jxG7QEtqiZ+Y5WEDRtpamj2pyr3/U2nBIpBbmOol/WfS3g9Rqdh5fdX56kMH6UZQC4O6SmLxV eA30mWWBzA+UREjDwU6sgFgAyMtvFqiXl7TExCWlGgE8ojkBI5OwezaLjreHfRGhc1rN08TtOvRc EnBOAYBiBN+bDmoi9gx9RX4ggO2608pNt/pm38qS8oyzmQ8DH0YtZuRO+6i+VQ7XZyMDksXcG7L8 +vwjGbOtQCNNkncqBwaU2o2bW27yhrS7P88OIQAh73+VUsfPozyMEDRK/pmGlARZNkAJYkYO0ow/ Kez9AqJmhLzMGXRcQTBCq7YwwO//216e7PIdTywruBBvp8KBLLiwQPO5h1/y6UAyQSuQduu7oSqS uDm9CUi89ZkUvC9HXZDIOzxCLsU6FgLHYP2iu0SbCG1rvnD+t8COQ42wlZ217c4rr02XnEDn7omc Lpdh4oWNmAKHD/l2YA72eAzTLjHbe36zsiuIiq76Wb6PZGmiEf4HpqEoBrJrmheMHFI02mQOP7/U KxjYbBXd5fAGuzD1d/d14086gceWbcEzWmODSjn8KAj6j9GyPdKVlzDFYA8sFTKXjtVtF3UvXYaH Cq0nk2/gWR/l3EUJptR5otTmEiCocOKhWuA3T3PvAVT4lCL4UFg+huA/NMIizgalmiUkPXeX1b+a BhOWrQRDVxQH8lIFstIPsSnWTtEDyu6PgkcqONxsxMYZ4yUDAM2l4+/f2vBvmHFbh+BRe0I0A8/7 /R30oTlK6sXXYl5Ekm+5p8aa9hbV46uErxi3wuHev+u4j46J5tX6QORCNgADn6jBIlBl41UXQkYC gAGEI5LCUI8xq7yCNkIVon00v1K/abz7NoHu4n6dzmlLS9q5e45ldpre+5/fQ/JS633t1O1o/Dsh 6PF9oGUro5+dkq2tkA7UUg3lEGjydwq/M3LDpsU2sab1EKavhaX1yZHwFpWSX4415+GvI5+LjNJz 9pCwRDRZ+2DK3H5x5ZkVf2/gnkEnwmgwShJtXmQLSMsliNNd8ZdA4TlPCd8RlRoc7/yo4TNBmg6n 8o5kkKJpexYdyjSNIRj1EtNVKbnoLA6gjE8KNGKMC65+gmj+dTEKDjAPmWG4UJSK7FdIKKzD4Z25 ikCYVu2cEI0+BoQKblZ41l6YT3WF5lG5xlg4AufUsCk+NhQVswNchG85TWNT3cqOxT0oljZv3toO 0WSUoht4kL7NKGmITZZf5Bj4AwpGOJRxl/FoaUN/5e0rtoeSc0U5QZY15lb9C/qQnGx/wHutJMGs 02FvImLHiYH7iadlE3ZCtojmD3EXGjplXsNJdikqoWHxcdeVz0kzzQDpdrHjEov1BSadAfdGMNio 7Fe6ezWzBAUblnw3qWFLMg25AA4teWe3IeJqUV9ASs1D0jKo1kaawY8q7axVGrROn5dPVbuzLFow CPLfUrnju5SaVPnDUwK4pS1HzSgGHm4EdyCO8Rkfl/WVszXYRu49IxoRwMpzwiBV8awuCtHVk3Ww Y0ypUflEvwEp6YZZsRkjuc4D9oGnnnDCaLTMtXjEhWKyOeDNPudmPSjnAmkuFQSuaQpopJIl8m3w 2p2Pqr5K6X8n0YlMHa+nBmcAZafO0T5tyCAu3k3Y5sp6UF/ofT2/BVRowpqHjfa4BQqIxPb+Tut6 edrPkA79O4jyUwN1Vg/FdJ2pCFE11eSnQhb89a0FbbLH/Xt9vjqdyZKgqWDvVYLT/xUa7V7Xaw48 RHfrrjBjpf4bRKPSCUOrtrrTB2s3mj0DfRZNyvjamjH27kav2PCUtgzGgtsB3BEPf79VQlhh01TQ cAP+M6bTFWp5tmqIo3LOLORkkf/60YGtxoPPhfwAx48o0mQj2TLIFLX8gYXaSy1Zr4i3Tmf3ei0G 6ZFPlJwM3jvBwuYRtvP8gNjh/YXXzfsLrrFhfy63CWIvEvVfeZtfJNu0dLV2ZzYUejEtYDePk06S HaefTqKqWld9IufV/n0c+Wu0H81UoefwlfznQw1F0a6hlfTeazkuVNi4d3C3Vi0iLZvbazxnyzb0 29ez36+YbnhqvpjHXj/gNsTQiIky34MRiC4kDCw2vF1f0usyevXHxGVe6BwvOM0DodtXIxaCJqZ6 Yim5K40k/M3y1waPvgENJi4ZxL+4mPdFLG6ACkxm7ZZ3WO1+ExpTvhoZByF5vI/bALepPD4/JgFW SBL80CXBMSzl4PP9MHmqkMa8R9s0Ih7JqPGYrdsLI5FYbpEX6WZc/sdr15hKzNe9yo1UNMRtNyDF f9yk0PjvjCypBl1DUAy3LDl+3LHmhfu3PVZTzdDtTVUW2wWEJyyDXfvNl3ynpH/fDHRgpKr/7VmT lTParK7sF1hfm4ewYlgqfvtwKzyDBE74v9bt9/6sq8TXOGlJX7P+iDWANH+dcvCe4g67EvelWFnw vPfOF40l9cTYehkapfhiUBZrk6VnMP+3KH/+tK8PZqAnA+bX+IQkNxP3LRHhXrWK3edc66Sf90sG IjfW70qz961hrtTzhv/L7AHWlsmaWV3YIWEUChQUhoO1nk134zKrjUK7udhcxqOvyJ01YDIoXGze KOjblmqwpMtTdWG1GWCrH1Q9UvaF5aBNsVtgYnZpkGif+006ulLnst3vbMAGfFmXxz64XMqhsjt7 0FM391yIKZSYvdRC/ddFgJgmxg52Nq7RKB/myU0WnQtQRBakNPXwIcb8i99xgHadGYxfwpT7qhn0 MW03I50ezcs3+pi2ZRBPR6uqX/EubdRYJyZuTCxVQNuKmXJzSunj54vtKWwoIf7rNixIcHT5TLUm S/4XHoGng+wiKiwlLlJ09Vx/ZktAXXixNpZUQZ3L+fy9EMZ5+aSmqGF4GfwgpNc9Qkkdv3ac3iLl KhyH6/t25EPKFds0L1BT6jtwzuVoNwxNQrvQpqZFTQbn8RSMWh6TP+WWD6+BDc0mUQGZ/j+HlxBx jd7xFVyb6Ole6s/x21uaaDCc5IHMVBkVU4WEsD7bZjuevGZaDuTU/ZtOYctluHTBC9SDxVXcUuyQ /xeBqr/0C05XWdN5GFho6qiyOQK6Ua7otGG2T2qkJecfPebMcPIEDlNE+Hy/0EcqeV/UcCsIegex GywuXXItjQk+Bg/1zyjPidQnvDRh60rxnD0ex3HGTmgK1CSYLqQIMiDB4n9c4oMKp9w/fG72PKIJ LLUWpjNZZv9WIhdnAKxcLARYUQJSbFqJXx9BgLs9/f9JIM+Qr0aJbLoyK6iASUdqCrUlhaKE8516 2vIgbOhomJwQx6z0evR/4dQZRvTGrp+KafN7ea+X6J+ZZUnqNOvTp/orBadvrysHvILfvur+pMiB fSmuSNlC+Hm7yNHBOe7ombXLN72j0zje89tZ+L2ms2/KOMKRtCFSfA/u01ctdMfdkp3WrHPoK6rU AUIArr3wCFr0FiWTtV0O1htiNhXXRbUFm/9LE4br0WXXl6l0QCqAxLIylMNqGIP7mWxRa0YuvpOp SzIDtGIyYmBzrXO1/6PKNHokxoPfAnYFOkyTEVfMiwfx/hccJvtrQf+BGD7h48cBb0O6H1pWa3oo dLANxcju75HcECZEH0L4x8bPqr/7DoT/41WK6uZu7e5tO2fsRc0KuBzoDIDEc+ThgfsUpZuAQyLB bY8769w5cjlINgdWUJCqhaWnecZVphicxzRQf3IbVZzt84avGN58kBDBhaYk8XHpsyEUFRYC9dF1 4QiJl4SnAnwprP/ru8hcJRec1pfzdBkKQXJDbayrOXeYdkEfzUcMzCbxOirp3w5o/J8neTPoG5g0 RdXMEZ/SoIs1ae9id7vVY47Thli/kw9gdz0In6BSKbguuoD2O4dxRVxSe9SLql2DrmlJ8ub3PITc 7D/NRqQRBwVLmTPvTgWVj0AbS82DYhdlOWe6X+SDB7z8kbMBuK3Z1Car+4Hv9Qz2+9mIYZQ6h1bY 94367cKSnPOmqlilfV1njTSZ6KMwXKizeJgRBMk2qQo9di2kudCiI0Hvrt5OyusXApXiBaJ7uCr/ 7oOX4rbkmD3yIc3VAGo90EfPylSG+ZrEB9xPA6v1xvMbgA9OevgU6VEuQ9rmR0Bix18sRRKT8i+o +cDKcASBUuyREI4SHFeSdfZTc8dBUCbvcXSp6Z0fai+a4hKHsDFqbPHeKbE88lJjy6SWVYW7zlRb wWUrXf6EQAAx+qG7gOioU8Adn+SS9woQ/G1DWEQICA1lFvcz/6051NXBycmcZ7787zKjB5rRpLwB rzccMVlyvDmpSDnh+x+GH0X56iWT2A/8CRvjrfZvNwAkqnzvW5g9x81teAnTDm0lVrXOJlyNWZvx ynMeYtyrYtf1o3l1fhI5JiB77S8OEhMa+1Fk0ntc2gSfu+quS60vQfFt3du52SDzRdigF/m1HdG0 L4j+7oKJALfZHAuOyQPjaVuVBSaVYCviHy9YangPj8aJA29QjpLhbKRv3UzNAqlBtoSKLqewTETb twKmIR2nn3Xfb4xSPDeAfFBPDwFhzKMIERyly4oPlb8OuD7d92EJU6bVNpS5/ZfPnqi8eXRrHQrq MmVQx1TctrTY5NIdZIwX4UtK9kmQyBqwJ+ebgviFMlorbgtwASBCTTYmjQ9N5In+7XujiD0tuHqP qa+4Fzfj2RAiL70eBVGZn+eBJJDmPVTKxbrZd33G+9ijvrJfhqXuoGStdLHv2VmZUYBCxvLtvC5L RKGuallf96aUz7fq5VmU6423bWKcJk0gPgO1YSW6nxwFfbl2JuKk8ZjHJUCYyZ5JCTBD1uS9acP/ lfiHW6vnBgxA3XlkSAlow47bOwWL+W5OFmTosXBxlx1FjY53nl8+oosxOBccJCgR8c4/CUH84kgs 3u3PSwVncxfgP6uRtRAgoln8yikIdoNrc4RHJS+MQxefuZq1Uy4KaC1jhR/OlLyJ6iIOHKPaGYXL DVB/wFfXLmlg0rZ7OCWaAkIFVzbfAesbE1F5gcb/i+tD+i4nAdjOYAgRGUHbkV/28aPz3XDd4nNQ 3JCXr293AoyvxGR9K4VE8n9y3ZyR3vfShkC42XW0tliharLc+tsqVj/5T8CS43DVHV7Uc95sV084 STZdoBS+4tJ7Ozcm+U3DCFP8CS3EsKoS15Tv4fttLjoCEgGx0kbIHcV4BmV26loOfqJCS+dRObVv M0XH0aW75i9mPY8qFqmSMHxH2z7y7Jmd2aBISpiHgFHNv32kkuFC3fwykfZI4w4bmThijDgCVpwA hX7MXrLQWhSk/wj+vBxf8yEJgKypH6+elYmzQMUYphUTNaxySWoR8L9KVFgW6Q9tOzYob7Mcjc9P mFyfxJt6QNtguHtYcF8vYh5AMFp/VOUhfX7dnTetD3xlCZnrwpjtaqubRi18vx3cwPD/cVqaFJpN c7EtQFSPw4IZ9WV4C5gsBKHWpcvGa2qnONjz1EBSsScvOF60Ek+OTHig1oNYS9nn+hSuf/SQ1Mor 8Ezum0XYs47xUZ3drefx57UrNnGPslIi64YTZTNOdBGY8RR9siZ5CfxgEFu/54vRIChydLzLBHzF 2KQiHsVhQvaCagB2N7bbcNbOTLLXjkt1Sdm7Kq1+z8X00mn3EeANFOFGPQoDpLufRv9XM/xDOtaA SjtV+U1G5hb+FZ1VXlqDvQfXiWvGSUasYZEfnw+ncmOmvlBvwRwjIdCS+twat1g8HT441Sr2oIe8 Z9s78yd1UqnPBQkcoW+lnIpQBQjf+Hg3uI4AcliWFmyP5s0PU32mBRdBon3RWbUf3yD5an8uxihS 6/WtAV4Q4jTbH0kfChVe8hCtXC9JH0YAQU8W6o7l0mGJIgFDaElyD6hhIkWnskmf8DEJDFNjKeX1 TXQqWfWZWvlZ4AcL8iDoUSRvPVUOvQ37qeXrImnEf3eqOrTi7yhJwk0BjzpBZUD0qwaoKXzMZ59F yVC4QWxqAAG/wj12J3H/dJr6+S5u7h1XtgAFzrqNvIwwNv8gM6wHJXQcDM4mMQ2tv/gYicuFHL0m nJnOCrWHLc4df0ZMJwShLPxMJ+TMHVJZ0e/3k7NJ4fKX4XvfVkM3vyL+SGORP+i4aYKuHVJLXkB5 0TGXv+CdbhGmyJ/TkDeLVNlByR8VFugBsIL1KvNsdXs54TiKkfu2h9rUflKfLz6LKfbSpniSKAi6 NLA+zXc6NsgBLQaBY8BygXSgdQBeTW7Kx+znvKnPmonfi1Rl/g7XJBX4HEf0k2WbtzZbwZZLVLpW pTjWGKMyzTe8u3iGdl5ZiB7LAczHcQYNFCSaYeDjaogGdyrA6JosvLXm7kf9jZA4i2U6egnGxsp2 JxYaJZQzt1lU8XRWg9jCjKzn3eCh0wMpm0RFOuNtRP6y3NKBWTJb+Sp2hqYTZfxPi9V6LKzKg4mQ WzQ6GVlFMzHw//pYsTrF5l5sJ6XVlDNya1GiagZx9wWOG/zxtqZcyoagTqGu31AoR40hdTbVLrzJ NIeDjf+fC9qlH6hkAd7pIGXAGaOUz4kwK7Qm+qOAgqRsKrBjJSyIc99IHvpMKb5xD2uPN6NKGwX6 iSkduNe6yde54JlbLaRqgVsQIL48znpSvruiVLlrf3yxqGa4eMuScK5BaYwiIG5+216dXa08bK/y g5VDyH/uzg8yKE46XiFDxf1BsdPJU+dv+Vm0egq4sgcaAPYUdDB5pMYj/pEZiE9NJomY8pvH+84z LtaPCoYSXzfdL4GxUXzPtQ60LXG5CivY+ojeZwzjYNxdliDvZAvpRP2LDljzQu6vGTAYh9i1Z9IU wY/4uOJvew9MWfa/i4JeO/mSe3Il2f6k4IDzbLrmDNn1cBBqVjErWa1PgkRZ08fNKCHmVV+WRRfo R42fU3ER5XzRYq6iKVL0Q0rKJaq97t5cpF1NJ6OBTMyG2R4f8lR/j9DxG0mCvpxirAshzJKBTtRp syTf09S/qbKtGAMIOQpBqBXUCZw+J3/kAUdRGSuoz0lIbpxQDFo5A3aDktMY6TaysWaijbZe7ZX9 Iwk7rBVMvSfN9UIhlmD5gQYtUsl30FTYDkqMQH3RJnl7gwEDFQcRhicT04pWUBMbGlcOuqK3uMyO LQAug+HLUERxS2seWhh7xDGcY0NAbWbZlUGgX+Qly3VpFi7NTK1qIeDqNYscEvAmZKBSimqvWQGS xlK6EmHfpntJRyUDojuJFBqiLgge2MaO+iTzxC1txgy///02J1ZQ/sLITrVdRkmjyBa+oXLeoDqu t/EO+ED/tertCnJudDl+s8GDJs/hvc9GHWYNCrYodL6B36vkZvhHIZ3nTKuuXhTd/5HLWCAbfy0u e0klOjEBvQFy7UsK/U+s4SUBoIoyzNROkcNPq3/vz+V8uM4xh14KQSUXPAas0JhimVu4N5tZw+tC jO7na1Rx4BG23C9oRhgXCfUQXF6jEl4koM0oDNEyBw/asjGeAlVM9m5dhK27//OTJtVvGFF2rXX7 CSXusZoF9om7+7zGPq4nrsMqXHpLA81spF2UQc5hUdRZF8jhydCIU/wPTK9jnI6uutvTIbPJ/c2d 8KJxroz0XZxtT854hu2WDkatdTQog7CrRba/bFVUHlvkiik1Yxleom3HKyREEUMGDlkA3bUWcVKy qrIztgZf52Ug7mJkKkZfFa+NCMQws3LuSz1diRfe/8JCvo/vlINIuPxjM0/s8udvTOBBE+1mPp4C +5ect6cDqKqp7A2cYqb1jriYWsWlTpM/7/DBeu2P1PXEOSjx+9fMz136HcfNJD/FavFQowfJJ+3q TAJMEAktxRRyClp3+yrdBUZh15AoszDdpc86+719fquhOK6G0+8QbP8BjbbBM16tn+vP4IrXP07t 3IuYS5ZPFBpf/Xa/1+WtEg8Dt2nmfUmNnJILNuITaR/rBupupsCI/9JPNiFNJR/P0M3NMEKADTqJ 3WpLYPdx3UoMuHtHYbitjQ1Iu4kH9o9zhfhj95W86i9YXZLkkgDSf5IBnSHLbewH7LDBzGXuFetL egRuTMwsnCiJyDHQz/yN8Kzr7iQiuGP0Qww6mHU3WEkSgxsqDCEw07BIxEBq+B8hC0JDPv0KT+hJ nmieWhxextpMDYNuulWokGloYUUxOCtMyibFOyIJdFYKuGM7rmf8qnO3/bo/YDzddL32V71ZK8Iv ogXAhmynvNr3Jgo+kED6ba/TRnUWMPmBxhzhe/HUgg/17GeUJnXSN+6EFm816uDo2N5Pv4F2oTVb IGhaTZdBw/ZXaJQewFpz/uokQz/poSy7LsZwDP/PWWVv1k8RRDOZ7M0xLP5n320XFuWgHqL8cv10 I1apjLgEyy1hB42p+d4YfasuDmgviphid6cSN8/3VGFXaWjeetb0uydwo9HuE4jJcA2s1JCSRM/S LZmopG6ca3NUwjZxhwUErvwwlILeodbd0hChgVMo+m0YIh1UtvK8C58llxp1zKDRuU2EUQs1ZC+N M9xhJAgWhQevBGdMOVyl/foT1NluHt6BTZ5XUk+dURUwJzKyEJCnqFd3JsicW8mhOT9hEI7tacVm 8nzOWutrJHvFh0BBqe6lcd7NfN1bd92FdWSfj+4iLKJM8OTKMYyNphuRIZ5tbwN2s0L0O9GcCd5Q XfKjDRx8Dwwhy9mttEC3dzpigaVTvNasttat6lCw895TOSHcTi+w+c1Bkjd2Eg3qnVr0LBY1sNtX dizTbehLRxb7BQJ3DWZjOB93Lxkes/b0Lm9TmsK/56Jq5n0Y/hk3wp1ms/ilGGAzr/+wYWE9AvES ZZJL4n7FBgLd8nZNb7TV9LKBq3YujXMmr/k33/zega3Oj2Q5l8WdrIGwXkHvJgtASi1a+UBZA9kM 7JqFHnAs5DWVY+ntvG6nu8q0B+nyFNztsQoxM/TP2Edx5MEYA+/qAja/0+A0DZ5gF6EhP8Pskj7F HPyYMZEY0St3QsA59mYNsBm3WkIAp53nHgN/8ufbFHj7A5ry2Lio6q3qF6bzQXsIFuglk+d7CrxS UtOXfn0LyqOQ8Uky4oL1wfcBOE64mVzjAB3cSxzEPCXO28SUFE4bNWgM6QijZaHh8GCxZLnGcNdC 15I+co9TaE+AEP6rnnOMDRTx6rUY92JY/fcscZDzoJWE7sXTYiIHDl8OGbrQjmS7kuLAsbArOr9Q tMzlprLm/jPzeAl112VSbkyHV7NYDuqJTRjc8Rj6UiMffhCyaJxq/lMl5mR4wzN3qA3+kapueaF/ qZfEtuBUt5cR0PpOQBEMkqyo61zjXKuTkAclDEo/HsrVWgYDDqKnTp/RIL4lxBoxIbl42VHegCKV IDQhs8umwo5uZtNrMe1Q5OMuY2CoP1ScK6iFo4usE21MuPeTZl2FQLGNI5vSczbpojiHjdxFohUM DFjqfhNmoocXMg/qZTIIDzIBOgeRIfvtjUVzAtnhOg9QcLfrh0NPYC++ZRx4V5NQWS2XR5BZCmZl idM7dSrRn7H/9R88Ep47lMhJIGqsxzba+meo4sQaUkY8Yc57/OunFUpbaOOS/b1SrcxwnWH8vK9U AsTHz9Jbozd7I45cBCwBCgVHsBu6lh6Ty2IwBiuzVcENICjN+4UAWWTI0NdXEmDmeBX9+rrfiAI0 Lau9N+lV7iROz3gwNGC5ceuzdxUiselrBBqTGT1wb9OrToDVLNcZPQw3RvyNfugr0LGnoOVmqPc/ XZHPGQmda82Rml2nbL6nGc3SUzI6O9J8mCgKRU/AT8SXzOvc0M3JUVNG5+BDDcn2MReyn1M1KNWi hpyZYgFac1CysqXqROYFTxTLgpyTairPB3a3PJe/ouOGdfm61mWWChHI1fjRLsgWfLKNgum8DEUV Fx8zxwj8CZMmdx3QWR1AJ8biciuNe4aKtxtc6Dl2L1s7EIgtfA7in2x3mVM/iV7jE6uyY5PIXQY/ uDneRfif9l/pVCdgRBkYa8zHDwovtqGNgcwO1C0so/h+TVNI1LfwU7syPwu4MYXjIjZw2qQqQwkn KTGerSecf/Ud1nqs1QG4IunwegCdWFOkKD8V5gSvQ0hPR/BViPYYb971XsQLxxyIUNgyEdmsthZ+ Lcigant5CXJm11lK1M/L11WPl9Qo7P8Q7j2b83maZ67Q5UqnYgVj0KdQjGSgx0QzWKhAL270p+Iq nh42TBnUQ4QwP6T/7qcnfrdWESYBhihobufBTlCKSTbW0DZDcmvB0jsXQ2cqghZu1LKdK+iGAJIp XPrxiAets4+6h8L/70IuEiniceKFXTHH2POsrFsv3S9rEmb83TnrrRlGnifal605avyGVxyWjaZ3 NRfoqo1KV1pwsi6u0hWL0Hs57rUP9aqPab8Uwg3wLHgHO0lPVZSGioBVy6fBGeVA9YcrXFJI1wmk fYGT6LBTZb4OZcZSAHInndasraSmlncbKCU5DeBz0ODj/vLET4f0SLw2Y4CsyxV1QtumzVURRtqd pqtbP7p8tyGwK++hW8hpi7epVKyIYYQg59i4hmJlFONo3CJP8lkSHPLlRgIE5Lc5aboqzWwtRwmO bjhHb/Lw9W2aF1vWYeiuxmd/2bKHBU1BI9isaImzvAAvirp3kq0Tjw26oVgUsqAz0Hq1Vx+owttZ ZN8HFZtVDkpW+wijyAypJuIIM/KMjozjVdzoBZ5O8ov0KFwPhoaQWad5UPUkCCjZWyYXi+njJlQA Da3O7wfsSsTByPE8pHG5NpGosqYUE4ljijNiXgaMw1mkCXB7IXaGdT/NcWB+cYpgdEHeqkN7XRO8 NGfoJs6KyPJDKT3hrHCuDg7LGsUeO6Qmr8BbzC2kbAss5oiR6+AGsBF/lLioL0XDZUkXzuTTJqas iiEQZr9IOziaPIcGGv3jB86bBFP7Z4fOrd116Aqeicra4bVWv+qwGt7/MiTE5or1+GTnOrgc7Fur lR2ioUUS7eEn97/+T2CWw4glBtTMTdGcZyjNoAjmKTf+02Qb930j57lWHwllNYB1iXw8BgaEcyPi RGJH/OEfFEFK/Y7Woppf3LYidAiWokY7TeEx4co1vB2NPXygC9avfaCstPQIRI6iUbkgpYRcNlha YzMA1SsPe8Tqkdp1U7O4cs56aiM1olahpRVoKpTyw9dp7neWcHM/1ivmrbkoQPNljytiyNABlYnC GHAUMg1L2MoxoeIS6ho5x0Id63YeZDsTEDxzR2BnJtWqNxMMlFLvIOLYeuZwWt/HywBPNQc6q1HC KoC7gO/Lps2PfWtuLSwVNMqTORA9NAvBw2xPEQiDKvDxYIdIO18JmTnB2liALdO5I8a+dJVbSh4W svbq45dYTWHNDLMLj0dcQdkV3KAFyZmZPALYu6gR/V4AeSDm345lkkBEzF8eSWkaSsMoOqk498zs S513lHJjFDqG2ObU8QBc6TzvuTmpXnDQY8P4SePvZCwAtHz34OuavU8emU8bxxm4F7maPWoPTvIx ebQ+bwxmGV2TP58MJmMXC/x3rFE4bPAxBuG2Ss7YqcBIGEEd9HpWfxXAUYHA2lAVOhw7OMNI5BwV yy0nQItw/D8Qq1TTnIjUbZjjZRx+qqTYFIIvF1Epq4OelqR+1VNyj0GEbsmuEHv0MuFKcvX1Cu5F v3tD6rDuhnetJvyxZzWRJDl+c/t4FcAH8ZcHVmoVtQheqyTgeJqav3ib/MZ6HrL2P7Xcsw7HIiZI 2/n6wOKvuCWTFn7B77KkTfNIbUaYlJwPE8mNpzOJqVFb7rIamhmB/hJWbTiRksrWh1jGY4V+Z103 GDYMzfuxRRD7obcv9sHuQJo/TZDNw3rrp81F4Lt+j2NJw818c1581VMTQjuBGauYAIfuSYLkefMR dWkZDh7UoyRt5NlRbula6N5snlbKlH7eFh9WhWH7jc7aAjn5+iXy3UXqiy2v+DFAw5othKkxvSc4 kjLfjHoRR8diIAX0uJVpQF8GzNQs5hiJwmheiZNxBwFSVVjX0J7ed+J07vhHzhWEOyvRuVXChZMd 8frYayg64SHjMqXGUh0kZTENnqwq6u6o/gTqw0FAecyjFxgQLVr6sKELgf77E08pziBw0JNDyFqj 33Ucs3yXFq3PMOdpiAGmZZKUzLqpbSRpzZ+N3x5ZgDJHM2G0MfWwZAJ9iX2SzKuBpBak20a27D4I kxRFUxVTrXE/EdEH0JyvmPp8dSOXWiL2LkauaZt3BneBX58uNVpZ0YLIVcm+Gg30GlnTr5dvdFye y8hHtid+jgHoAgM+aOrVM0md1/8v5WR/BQEVcO0xC6MVMliZg0uqCwINGjmDzhCFfhi2ZR18oVa1 NZGXda6bxHjMVaN/4/ZUkY2n/8Ui9Fn9hXCl15lIBVW4HRL0j831l6QFbj0WldJi2GdBNj6f/n1L 79aT+1seD03NVfRmzHXiBGjC4rL3B96wa728okzC+E6T+R0u/Q/rC5GpFCetd0XUoOM/ZchFdezP 2f1+riNINiOG6tjSl9FvlYPEXsz6x9JPoViMKStKGNWvGVtGmFl4YNtxv1SGkTJrqNgId2oi7kKA JmIQIBiRs2xDqIyDgizXEwqWeGMmzARkByJBijXWYqSWPh5ztBh5JP+ukDDtIwcY9O/SWMpUdekK mRgWEKGhG9NvAYawVieHItDOL/JTWy52kfrereSZ0QNFOIsIiA5KDC3TMfB4eoHaEO8+k0Og2kHO DY3xIEnahdo5BXNfUb6uaqj31X4DH2j5bThlZh7jRnqDpxWbwFe/xSp7DB4FfwyF1EoD7SzqJ7ML dNUFXz5R3fFAimbEH6r+Xgf3F/nHCL2ehfxhhV0CJWFG5gZKZfn0qc3hBtcjE+DSQHPyy7x+IrjL LOJOWufENVzhKSZbjua28m3iHzUSYqmzW+L95SpkFghp5z+1Can4sJjzeWifPuj4+xOjMBbDKG1W H0hDFXaaRkHPZmUpbIe9VWs/kFsEJgs+wGZzn9mApChOT1pkjoPIcvNpdoC8GWebkDSTVL+3Cri+ ckMAMwDgfQh0iYF/s4MsXBr8SfPD6m/JPC0gC9BD4VSGB3iP2PQVpsuhYPQ9s2Bo6kbGhlDYiQ4h HgvgPK/cgSBxxAE4KQkMkuFRWhl17XAwci66Pb39x7twA+JY4VSSbgW5W2CTlubyUMnZJP4cOpnD FaRL5jTEooA2r0mJPmlRmsZ0gipwxa2UPz4MpagYXDUQqGobqiWmIZvhKs9Yj0tc+eKyW6w77aqj y9xIbqgKDjWpjlk4B3/hba8IAxoMEfh7Ad/F3Zyfg28s9OjDQ5Lia52yOJXX9KsvpMM6r8df1KCY tPnMSf9b9hD6fec2PdCBYL3gscB0bDS8teSP6vsCgLpcNft2K4A8z44up8m8GvRAVXytib+hHdE6 pYJY9NiQ9wQoy5Y1+gItk4XNHWq+UzWB9vRn1VDmKqwT1VvCZJwqHMcrVS6tb2mwgHga3vURYziK jU2hDLCx/TABIdCtbMJkNm3WolIA1YhJdk5KGLOld2fKkxPa6gjAS+McVOiBxBC+v+r711FvYW6q e40Xmh6BDlZKZY1TP3gHfd/Jlf4BDXbaQag9ky2gF0dL9Gs99VwbMk+K77nv5gYSM8ZuIC+xW66E Q3ZEpSqQ3dY/1c75cjqE6B215sNppAYAJYDebhwnt9bTlzoxWogEa/Z7eZkHQRhen/61GG+8IrMu INHKTzrkXMbu3NuSsCPFVsQDujroUqknN1OcoHmU0DKqge2hy2074Yzk1kooHqE+nfs0BLwo6nvD tCDf9sPYnR3VHvL1zdi2gT/vO/z7FpMeVzqTvFMKTF1gqffxyA3QRzZ6fn2fnAAeDFVz/YTbyF/f IZ3eJEAGXEFgCjRg9zAnVpNRirbVG3/tNAPZB7ojmdKodVKT9t7nHHprS+lGYlC9i6+qFt4VUyyx LtkitSb/vYxQ5rb3IUfTi5Xo94BjAYtSdqCZMS7/B9jjHBfix1WY+y3tOLY8rImYhxCKJ8tIOGa3 DSJoLY6qNg+FB5/8CGtCPgUsfMCetoViK4DW2WI8SIzEM2QSdgouzxlDAuPQXkMHiV5tsbSJFxS5 qTgRw0dWwjbCZQ6j7wM18j3StfHpDolDwkysX6MG0xxpPy/jnQd+MFDo+IuV08G7Xh8EQ3AMpqYN 8L/iBUfUdYKML6pZKvBov4jZ96pjsRYfHeRoJjSi/IJduoKzis4UxM3k0tTIwwOxgVuJ+i2YYcjp Bj99Iib4cO/4aDbcrGQBMGXyq/A/KvS5onowGEXvJjGlOEXFRBlv3kuE7ZtkA4e2sPo7PcHHdpaj UFXy5nG9eTtR5jSev8bfPSYuhpf8kG2pPrzoGiJQ6W/DnWm3MlKuTRZ93aCtdmunId6NvvNFmMKK QnQQa/mPiT3EbOOaw8G05zgpcYQHJtfCUDBLFXqlERTrLs4CLcc9bAq/D6PQ5vJp7HZIS1REkzTb H/7Mwpw8Ou2quo6JY1uyh9GQvyyWXE0ae5aTp5Rb0+Sz2shQjJT2voawsGmnbJ3HKgS0uDaS85gi k25+u+9HQNI7zwcCQE98kzMDIhu5UyTI5PxddYzxUrg2iP75x2LEIr06Yt5w4pWqEImsB46EEaRN T+pOadv/C9xGGS5+i5zNpvGeiwB12vhDAPC4NQ4a1e+uqxif/9bX6cbi85VqYY/CWRZPx1XXUlbl N+Q5UTKfVQeSfFDMf8ZdE/mbNdl6sK5Dg2WYgO/hmZFmdNiHFvEOrINxd8E8gXAcJDyKYPJ0XV9K Kp081EbTwzzoxEtDimeeeNlqtTzT2wvxoWCaA0pthh5RJzyBBiOEBmHv0lmaQraaz0OcvWrSOmo1 wlgh9j1SZuYnjLhKpjSoKkjAN5zHWPVEOCOrGHnuwCTI3x1UmN5zASYuCAaqR15RLSfTSdwb4opp jaOIh9mbAY8sxEECpZQQ8eK8Yoy53PVgN5Xml7OXyq/rDn5PHl0jdO8YeSJ5GZRXsQ7PdIwb/w7B tnXWDkXC2C0yiQctJs7SiPQbJrJ6YC5fq8NnGP6JKzUp39c9FQNcijoM0jYa0RL6Wy0kn9UXUElm LYKD14sdbeHK8GWHYtQk0ewkIH00jYXCzEDOeThZ2D3eb5EctXxDJAGAoTjutruaVEYnL50KY0Gd 9lhuMyHvpxqj6wCBGMqamWuAT8+4uxtS7BkTgQJON2xlDGsx24C5X+3e1xrgGQ9Zdclo0sQ+jeqJ GVo0fOR+ogwJRHX/22cn5gSO6EHLGLwAHXhUJGqw96ByK/h24VekfkGvFPEIYIKyB8C82E/6YgYb AzI86KFpnkonWgyidia51NtPHH0B05W2VeASo4mcI6t1AL+o9rqq+dwi9kp/82j50c57Xc0RGruh 6V16wDcQPPxE3TBuaojpRImTskBnzt4ijprRHHo87aslxGeJ3uSKFUTGFt0ityDaIqh6/s9GfCVk Od/+QFeaLkj4YBBCBQbhGGhkCgXbMV2edlfy3W2OefP4PXaI14FYvRZqu3K+5NuJdwntIoODFmE2 J84oYImtpmgYSjEqCE9Q3AA3eGUpK5lPPWMSh21vFed9FaBjhM+0+yjtWm3CjCcQjDzCJm8Ubwh1 K04iELtoAC8H/54CFUqXN8lmdT5CwY7wWemWzFaDmOiRvwDfhF9f9iRQytDXQO/Zs6go38P372ks M7QzNpHNPbDlBlWP+8Q8HTASPpWTyKwtJMl+E4dm58/g7rAvxdUFXu28zT+WPZGM0sYjRyV8pJfH izBDSa5h/OPHOzndkjxtBVSRtSOpW21ZPvBihK8DrWuJnOKr1NLppR1Td87T2MPKo2r/VzDds++C GzD49HdgBkaRprfA4qunSTYNmxGXE3b0b7V+HF9q9RjQsycMf9/p5XO2VKz+NNAYsh8LneL6xszE vHzbzXHlRUdFHUN1lIHarROlsgv6gosCOrITX7WDWbavwgWk2uXEZbDdV3sntZFK3oEhLGnb7hmj 8Nnn+0PEUwvkL58oBxhxIHKjD0mn3XC+jHF9NQxXex6z9r4gYRTvFmShN15ELjdvlHSgYGNvHlpZ sQ4+vEdv8h46JldnI9aPKLrh0GtjawspNZbU8e0Bz+sIbWiwNKWZbCVVI9W9o/gTsABsFVpC/6kn 9YM7ZT4y3ezEomCn94RARxKud/UQiAlIDmPkWwIR4o+nILtIPIOIs4eaRxP9oD9Eg8AU+rG331cA lexo0ifIeuG+8fKLaO5qjxsrOLmOpx5KHLp30FWV2/EQxuTRdObAsOUUHUvG1o+Zuf4TXma+cVAW x9kZBeClLXIQOLpcTM+ovTqupZ1SuPE2Y6zf7QTcbTl3oev20DIzPYWi+GLoRo7Vu8UCyh7DOSPk HBCZGlM+Fp1pGtrAgurzoD+ySf6VAJWHE6VXd73V+xMFwS8KunkVIF25yd7cc3fcFj25BqUOWD2K mZCHv2krxAviMI0pFm/kvsnZg8NLXfH8MVeMdVjpLXPOp+J5MxJfsFTwlMxsQ3RSNKtA0mSnISqg zQEyEzThtuEG6eTS18lCX3LIK4XYL29r3sAUSJqSxfAq3cOvjPvWMLilRbbunAWJwc+aohW8C70k UT5x1Im67J+Zmes+h5QpkaKxr2Kde1QcWsmMiGT2suR0y464bxAl2duLxtcjn6fNSmceDnU5tPgc EM+im+4rNgEPSrBZeRivu4WNN4JiG3ui4a76lBguCiRnTWOb/9Kg9p3QPIJnEUgIxv3Wfh0nL5sC e6r/R815HxErapHvd2r10Z9LMeTEWhUjpWWkLn24wMVlwWXesuSwzDrJDawJXDtsHmq7P+F+X5Mn 3WzhJuyKvYXNdXALiwsb05eIngn94IqGh/j5VcXyxa1SiphJN6ZZyK3fmiJq/2C92wgkFkC/r4w9 czMN+eVUXvHiK3SV4uIEGpjmolrlx4exISF6jfa/QQen5/8j2GoN49o/MC5tWsQ+2rIFsgQapElL Mycymr2Y4jUEzoFn9HXcSAXMlrJPi5ImRM9RnPvIHNoAnpa1ThNeWYpNj4OZTXl18b5kGp1/mAV7 lT6bL/NirJ2OICKujxwzFVmwuYXHngifuWlgAy4/aJVefcjqBxJauQmMTm7cLNR2dPXRUhMuwIcP K/QrERoZpfOaHSvdbq8onqxGQFYtZMN1ybeb2S91X8mhtqL22Yyo/FWUQZuVUGYGhaUZdU2qJpHD +hBFPsM3c4ApPe7meN+E69JOsmGkx32lZQExlifnGDvb21XwC/j3xw6iTSuDcctgHq4UbbFgJjjr B6kTv3vlTMltWJxc0CTAaIA7DHNruI1F/eT2WHeY/lbBO5xNgB1YjKJ22DRYPwwbJjFRmOQ2xma+ 9xGryHbDtmr1zFU54FGQTvBeOFxc6tLOh0+J3GlhvuD5WleHUXcwm2nSqWIkfXVTMtD/7aDF/ukp Le+8zPoUjWcrPsIxPdN/B89eux2PgtEMG4zByLZEi50AJKD9qfjAw/33DQCU78ewgjBRWGZRwa1o sHumACrfoMsRvaNdp0/uucV/3vQ/nn9Oysme4zohVqFUJu+KQWfT9y5bZeqPuehZumn98e1yqHzf VqWIMtmCeB8TdKRXvFhgeUfIPOwgwzJftdm40KTPMkBekYxj76kIzGWilpFD34ot7UoKNf6HEYIm Kkr1A1H9tcyWuMxtPiAD7MWV/X1p6HEzHGwhzutjH9HUzzTvpG8TJqz08/c/HHT1NevG6/C77iHo S9mZ7Z2n0x/ovbZfihbkWns/LEG0s9X1SyeCtqrV5y2UhmPAbcPW6jjfJp2AuExgRGA9aqYe7/XM RyQ5o1CGpMITXzNoY8Dlbq474Qs1Xl8W5WtStol6/83Mvyra0H1iRBwFsdIeXFHqceneEgnN3JB0 SnD0rCRmr8H9W6GSFUrJo+VEn+XkVKOLYxYwrtKOu6oXdbLTFTaIzXp2swiDH9BM6EwoFXKzv3ic XVo++cznfQa4vCmUmjQAhnYssjyDli+jSZzuPntDgufDir1xzxp8FKYJMWm2YNjn9LSeQV04Mxfx OAeZ0DE1+ZjOhlmoJaoBl1FaYGMsNYEIb06ES1QSATEXgySNlX51oQ8qgJQ7KpFpmlzKmUdALhaN AHnbRxdGmjCgflaI0oqIIz8/UWDCLos4RTTeJaa3a6qAp7VZ6vMSOcgLxSuM+c3U4er7wSkKplGx 7DcRL4xK4oyRmgA78V/nIYXNdkoS87WaKw/GZFyggomlbuTW0E1Qdqq4GM6RihGf7SHvVFlQf+mj 3r2LCUkqfQl2ZgSAyHzvX5rj1eAvkbOs7ZGI2D1EZfu/yg6oFZz2UsOJF9QCe4p2rZQngInH5RDX LOd4rOVFiYbZSxdTmQY/J46/XE7kJh7ruwPx7DVcRBlbv2Kor7d1jl3KPfAJ+ZlGOZSImlNwikgp ZROZ5nHEsVQ2T5RUSCxEligOoUIWrxsF6K3aF33jKdGdedHBgaQECZ4PMWMKnFBATKB7UwiJ/fzL e1m9cNoIKBjvkJqPMf6NyhDdKO4q8eDy8CprH5aFvOs36kFDYr38dHLL/u+CpOOn32PbINW4TtIK 5VF5BT2gl5evhn9yeJc6SXiP0bSVfoa++z0NeLyIleEOE1yRbqrFM2JhUYeBLeFmMwCIPoO9B3cn U4wclqjH2CtWy/AkqM6iYFvwhiAHexeRc3jEdVAgJ+3WLEkoczqB+eYxoKmHIn3dtLqjzdl7dvUk 7I9XJMuPz036mF19bkt5oKLrXpYILGTSVAknFiUor1dDlHp44Dnj5e75a5aFuQhNK43AeNLhSj4J 3xM6NJPPLYmYJZLay7glRhodkhoPu3dGhM7tWtMdQi0muK1aTEqJtgHxNMs4HYF7Qk6Q+/gBlrwG djvfyu+QJVnqy15On5FkxFDK2IlEZGtIf+KwdLdh4G7Dr9Z1lCO6p7yMj+7YQ4jzCeDvyIVNkJBb XiS/ORA2C8TUHgIECnksyJe5PAw1JZuZwpqjQcWFcS6tXbhuJXmEfyeS22lhpv1x8J2jp7Z9QMw9 xwXvvsif7yqu0vcNpuGpi6pePC+B56rG65VXqbWEN7+FN0yqmlfGErAJbbzNgLCXmGZQASj5QYDt XQ398I20msT2wd23ZbklYX5x/Ql+iGOdV9OBO+XNnladKXKtUFCfge6QulZ7N33yx6b0zx6uXBMY bXGPu8JMkuPbi5AkY+ibSyi3Bp2RsmezMUojVEuKeWBaYRhNRrrlx0EtcIXzkolZ3KBd1rpWfpJ1 zryCZZUxvU6gdg6hO41YpOxST9WaachceCxRrC0sxfkhWTnZI0ETydpGClxp0/cw5jCddBqRNSRL RZO/12cof8gwAVSF4Oyt0e/nzR7Xhon7DC8aamWdsDFOQPCBYJUueLPC2JuYWY7FIl2oeVLSdATr ENrIUhzZ1gOyc7hMwwH7h1fJnmtwyTljwMn99pQ3EHoJ946BP9dFS/o8wY3heBaCz0L3fUAVyXXB EEOnP7AjZu82JiLvUD9TP12NkO1d9FCkILe6NZEZXMGYZmVnp85pElexhvHzqo9mLxLftBHt2nLQ roeZVdUIse7mvSofy1iVWcAlsW6oZSAq3Nntr+SO3RThWUf1d6WYuG2kdaMETVH24JnUA/mJOs/J mdglYu+XmTVO9KGwD4BqV79AV7i0EJLBvs5axlR8bjBHKM+68xHEphHrbo6JfNR5MyExqkZMKrgL Ab3REEDO34t+01fKz9BU8rervJ8n25wPtjSV5b/pkynQqxvF3rJhfrwQ5J7EupUalHcAdQe4U2AA Jdogg5TrkKAeTKmifopyV35NQqo90or9Wq+2aZ7TDkImy96Q/9PI4mW8rfNhPsix5jyjLajPfppq tuEJ+gluMAvjQt+nTGrGAJZWJUdotQ3m/8426BxrSTBKJee4SYDRqYW84YEDEOVqeb9kZH253N1Q UVxRHUbN0Blgt8kpn31aNZ8QchAJnHYmFeR+OPmy0ifa2kL2YTq5ShHtdf8djwv3Tkqp/zV+ooXH NNh8itEi8lJm7fYOEdXaQ8kxFWqf3qjDShLxIIpvKjhTvl6iOW9DMVthJI/5dwDWIqdGoY9kA2g5 wE4KHshZW+ZfN8j/7V7QY0Y1BTym7cyuCWpFkePxtEWtdrZ5Biguur/HercUx6Q1ALL1CNDptYk+ L/4XQdQOabz+LlxBniIImbVXwfWkgARosfX53cM/Wm0uySzbwnbwAW9zqaBjxWTb2nebdBwzwkk6 YSQYaTW2exbjNvJ8iUr473QLrz/23VR59+aepn0edN8QtR5XXy2gipSe49KRCb9FHxuxQVA9XljX Hrt+qr3K92Oa52OQS4gd0sK/CCgpvstA4cTgsI2+zJPCBqgyR3jcJzsGUXc5AHbBo16DxRZLzAn3 kD14fn2Dedujt2KKWoaU0V01qOZiVXTwHMjKOC7aicu3euOPCmOfGHDcnfsPdrwGTyYBJKojuqI4 5fkNKhAv641UHhNUnG6oygOAlv4A5thXTo8SAyuJxT3N0wU3pLc4AMP5/aC7QvG2p742pofpn5OI PUycFLZugUhpx7Ko29D7D4ru9P8czcjAwb11oHkrcFsN+7y50/sruj0+ffv6v8hD9HsK3fnkyYLp 16rRs3qQ3MN2Z+isRvxA1kag0yj9WyTHSWUCyjpicbzYldMEKCrB0UOdBgS4uSa1Uv+IUbgVeg43 hHCsbHsmsuBcHvdRpoKNx3O6FgOGmAgjHIi7haCeAR9Ds9PFCcQ3B2dEZImq2UB3F/xZf736fuDe T4Eo6ojc18DNIkN/VkqaScOLETBkxZEz6DQ45xbbdLQOS7l4a4JYVZGMD/6zo3J1D6PgGlAwX1DM c141nIIjisPcU1hCVcJUwPJ9G7uEL/VRNWXMoWLfbe69Ax/ne+7H06pVH4fdF79AgPQwAldWJOje CN8PxNsHIo/EZ87L6GoUW+N9p0s/GyUsjUWCQwhZ4xCnYv8POT2ZlCRKFlju1z86v11Rk4tK+NI+ f0qMXXkz2ZRb/aIzNvLmUPXPnbbgMbeMQNNqP4rJ/MJ+SXGKw9jlcngk2MtF1KPfeBXJFvPuyJms sztecfF6jna2PJYBYf6JfuZeOeNLMdCwCJlTRF1Lj5c3xvax8xl7jDLL88jWvPGcsXBzcFqCJXHv ihC+kY4/o6QOXwzk1gRstPeUGABpMxph41BWuQlUjKwY+8WYX9JgDT35FhtDEecLah634NVrT1xn VK1zBE0t3xP1SqwOu0wbcffuilgv6Yc4N2If+4zMMazNn+iTq6/bmgHpQtmF/R6M2Rguwapgtgkb NsOogCy07efW7PvUvMTROarhT1Pn4zHcQbwDBz3V4c03JuMVR+gIq8J+f3OZzF5VcqFDWg2dML27 YGYuLIwA2pXoCbYoNMxMUfXvoPKYodEw7R8tr7p1mjgQjXQ6vgP/F+1R+XaFl+ABzAwouhC/TVet 2oS8Uo0zVqTrO24+HxG+HMT6FtXT+GrTuUzcB92aiQKnf1/R8Rdqux6mhXg92scpOm2HaF9q98jK 3OiDR99M2J9ESLfr+a1JXneBe+jernfCKUNMnwlpaTbHEu3Z8cC4XOVdvR9m7qvvmdRUVz8Q10/V a2XsCFJDNkDXD5YoGynVJ4TvL8MK1hvAvOGJp/wNPf0gPCQIA3cA+sTBav4tBmz+zTgYRGO9bcQD RkZ6/kj7pU+CgOhZj0AcyZQP96C3RFks9F30othNnzoLeKYt6tTT+Bt+7Vz7N702J+CAr1c1FAhy bEV5Qin4SRkQH+Y+uRtPL4KiG+I3aQ+FO6OOlBrwewRC23DsTcKtZFV+iCXIFPysQZnSibs/EDvT SgtbZUp2Tj0c3tUROXoK9+TIulduNXdnsSoY2JRgjA3SpzXn1F75r7C1fAg62RWzKxBinYfrHIxN tz8AUXNkbAowApYGOxBDSg1wlf1RJipsrH1fO0NMXNYUEJ90vPufBMS1713Hmkz9j33vpaCAzAXf qISlCbr966iDuDSilL3FzZ6DD6lG+OTHfQbEkxxMqj+c9hWzhBcixYL+lh5bH0k8nq8jtCamepD6 KpdY0qhxuhn7fvKTMB2bh/++GKfhM9XRDKDzCyAfzGOM12P9y+mviHePVvTpaFiH3I+gEtLh6TX1 vZvxeqjnLVag6HEccTh/uawARp+znE5EU5XHSAQfgUx6kufbHcNy0cfnlkoH0X4HhSwPDiKUHQSI Jb0N8ngNvLD1klDIUTScRcPlbm13EboX8Y/JsTsq45mA/ktc9fdxtoL0G103OmYE6k8lJNnKvcBE Jyt46o3I72OwGc1HAxyWejrktk9c0b0gdMPLqMgxwjpvAwzl38sLbBMrXQCgyrMumrpQISCrnqSL 08LHc/etpUlxKH+JByvgtCR9eCJUBs99eXKNV7VC/rOUuW09Z1tKHiRw8afqPbgzOmUEtN/bjFms Pc7zLi/8DOdrGQ8EVphCZiINUEWvlcvcR0TD1QLBVVB9AsSlMxCMVvk/hNYrRkwVel1uNUX1YnhU SSdmDoSawloQnU5BUKdYi2HG1BawJakN+cixs9fXa4JY12qlJjER/b2q62vpRpMa7ZvUV+GSUjbB gSnCH9P5hlQCMqzj8NlTtyhxOa+dFVOy1nT7G9BfKF5dxmZv51Ttfrm2gm207ZBa8UaUV8nnPIaA BFVnbgjbQPrWQdLuXu3oR6sPREnpQpkASXvemWtWEZVPebSmdiYvZwuVcGRZcJCBlNdzkGHa5Jpx s4yTfelrRh8zbCj9MLUvta5yfATR0xrXMavsrNGXKKZQwjiO5s40/2J32JmrEv7Uhe86ZKrTpp/f rPz8nITmTrqNffLrF8cUP/hB0m3TKuZb7a7H3RoMXveS6kSX7fGfTBnU6AEsSBkZJJR0lJdLCWBM 3XBlUJvc7gXlW5jIan0i47wVcLE2/hZVGrJ5xI+e4TkIOAfDgzx1lGQDxHlS5Dvk74KyStUl1RmB dLZVgQ8RaQGzqL4CjwA+I4Wqvfq3iqYinVVgamSuDxeaVLKY1p9y5tWWSK0BZ4kWP8g6Lzv1gtTg nsgtcCKzO+lxP/VnWtps0EatJP28BfoO+N7GXW38RnTQDQJAV/Ml7hssepxTwpDxuDaOHUFuL/Us gwIRYAcVnKhs6MxWr+DhRQbL0i/7o7lImpk9KiPWRgllqh/SIMK259OeJnUzgFAiFL4RPSOwfrjG tHfUXEHxg45tlVljY4XT64D/iU97bmXKCfAq6OeyF/2k9TxMWlhHdy+BojSYbIAZ1ysx+v+Z3MbD tsoIdJWaVlD804FyLj/egvAiXcuorlC41b/O7QoyZaNF1550tbK147pDgBYcC9k5kqB9t44kQx7F c5+eej+R8LKk0rUXecTl2ENtoYwcgCHfGhOe2gMpxhcXw+83huTGLyrzaaE5DqSa4tTinfz4Rhqn m7Ji7gZknt/mZkvrUAjjFrFfB8Gt3VtiHB8A723Ahf+ri9ohCUXjPYLa86dIjPImgP9JJMcG5i8B ZY+hW5J1OVsPSuXfperJuGwU/zCuLBPCp2PuoZcYnBGzHas+SkHcit6EAew3X26PJEWk3mr+YafM xVCJPYSTaNI/rcqEp0QSpz6cjS5pwrD1p0wyIqkp+w+JfArPAIEmKGpz2AzgTJ3ZFgGc143pwBwb cFhegmfg0rVwfQGlhRUbpyi7qcuunYgzdipZwfq0tVi8xvryS2lWOF6ckHYhimehXEBS+Ybd7Fbx 87JGpTCxSASrNo9JEaZvoXJKImZ1gX0M47lK898Sfjf9t4GxW1BIERCh+Yz2R7Wd1Ym+Wibg17mB b3QUvGf1frkX3C8a/qQLg9pNis7ja3heqlyviVu5ZjUpg6hl62yX19c2U7zaO+O0ka0CBXI9CSOf vXHAsSsqU8AFl6yGTxwONtjG2Ym5oYBJb8uH6UprRn1ZsTpQiFyM5T1xOBILXPjSi+w+oaAqOqJb JK/cyL9IXsSzu7xsfR/1ztcHKoMIVYOgqCUv1yXHCgbgOYNXjprt857t1FCpZCqozwRqieg6yMPS 3thbmX0s720AZmCism30+09oQhpfJ89N4+0Up0xm/sl0XC5oxo8iK4cQSkGWEZAprLMRm6U88oWY zpw0TTSlK0yJDIFrncNRIeuK/sUkRavbNB54sX/C6YDMaAfqg+sClvcb0mgURzM0Sk25zzt0GVid HXa1yM5hYt44TTCZe8a2VfHqh8ubOv+urzvaa6eX8NZ7ZFhhibW6yqFairDbPx4p5dROUY04izds gIXrc3PlB1qtR5n3boZHyWlFHkimeWixBeElQA6E9B6dHdmKEHISmmRmJkjWMi8jcDJE3yUi69OE R4voqcbWWSvsnbZtLv4Dsmexcn3/m7IQ5vGtGJ26v84weoWHSmlqAtArDeEcD5FNwa1nC+7ki8DG BZeot67iEyRZCXQcNW7orFkXeEnS65ktv0NNMQnaiW15egYy63Td7qYFsHJ4GjY5/hYfrXcAtpsF 12S/fJiZOOu2Zb48N892GzyHcd6Em8eCHmQAwG8cvjMlzS5FL/Qq6YGM7II2vZ+BIcSjeyg/XlXP bvAbRQWPu9bxy3oTjcVq2UyThEvrujeCNyMHI8pAOOywNOX65ih3QrgsuU7DcHdTbb50qXEhha5u MWNlefZQ9CHpxhIGLYOwdV6JsHRqpWt1/tuuf3dpaAHfMhVYEyCw4lEm0bjOr9CgIAP3L9X8/bOE e8CRWjyQG3nuE5SXgOdbH0CLivfAPwND2sgEeRHwggUJOKTBpDI1x74IOqaRsx86wVvNvjgLXz/Y GKMsGXvGCAElKUME0BnIMqD030ehCMPqFeJIoIPNqfOREvJ9QSJlyR9TbpAkdi3HSJND90fS8y0i rd9ST0gYMwn2/EXXKJsyvt/MRw4BTyu4uPdzsfFfJyttA0EO77x4KrV6bWbthdhG9iDaGJMoszfB wZVtkiZ0t8WOJGTqsdbLjAD+HkjLxmrfO2JmREgAbJg6vD5Blgvaq17zWnQWxMr6I2r6BdDllZBc 6abMSBz0+q1VOiv8wEz/0iduAw8XqCqX8L1uv24cHz6XFxIpvsA4IJxHw6yCASogKR1a0QN3Op94 /Z6rbernr7lfGMEs6eRJDDfW5v2uEsIUiDLmo2DvlQocKr7yVElXEMl+lAFndeAwbfsdCxAsXPlB 5PAzzVPz92CaaO59EPwEaMPt43k55eIX0mZ/w4ubEBRZNqkgJlNZ/ty+Ac3mZ1T+o6ED7WQgoOJt jRahaWG8SPWR1l68qsdbTIsokEc9yje0KTOSCRHHwt4wC+08WrFHQsrROLgAyZI1JJjBhd8DyUsm IOI5LcUThFWhVpjR9X4gT1S8CvIAmggqRHpBKiBv6wRQ7DgC2TI6+f1v/AlIPxPqtYIZVOOVWoYx sxTBggSC2YUR1HpmjTPl7LBjIdRBm9BNIix2JWUD9y1JYBPc3V0VeixCU6AmlXrRodjTLWJclg2f VKDTRzpO1nstSqf83h9ICPfAUfQObJgFTjmpcY61lVrNKvTA+vnKiYkrKCc7BYZi714oK3peVw0U bzpmnDBG/9kV1FqFkBGiP6hSuQOhguF/bZxPC3KvaVuXx6ag4w5FJfFqUl3Pl4g9ZbFvakqcs1ET yxrXXAgofnQ3Lu6/bFJq7dlQAqHu7ffMWQcPnL6JThtjisCuyMQIgKvShQtLBktv6n7w1w8FTa3t vxPIAnct2daLhVt9/e5qsu9jdwK+Aw58D5Hc07rQf1dVEyOQUg+SNR9L6ThklmG5d4ytHtsYqbwl s3rOQgUldvoJTCRSqAD0pvl2Pl/yGWJdLkkb6XCkx2uQE0wFCUeO3kiTwzVfS70qsXqvkpro/Plb 4fpoTnmGbwyxfpZZP6c2SOsl9ZMVoZ1fDgHnrPyD0nwSF8eOK9zT4Wau2Chd64i2/uydkokRTF0e I4NnGhZz2hosLGMxrN368zKQYrTEsTx9VqejhBQZzVT3Z9QF21VM9ERk5HHzieOs8lbKbsu0thTT OLMHVSAnJvVwxGaIeXkoXVgOduc6uEOBCao3QMtWbIg7ZTTCAHdNrln3RjQRBeCbPkysFmn8rnGk GFrEtmGWTC14dLUvzeCvxcJTJciFZbPCEyAUj7WEFKR8PQKx7F/w/WJny1xe61YoS21UazWSzhbc Zeqc/OJB+7QcgXDStErLBnbNg5jH8+k6QX2joeM7VhIpRq2+2I5nNJHjA+CPCyw/BZf9aXyLdEiE QKSF3r3E9erh31SPOy6I1JH1sVa7eX+EAIQiMdzok7P5k9wPiupTmxQgpneDg7Db5HpVMqNfWJDe OryxPeNqV/6g5RogTOPBnzcB3n6IdjQl6HvJ96FEM2Ai+YYMA2LwkPW2JfCIsffqKwqd8Ftt0IWB ITDRxwJdlBvpomQRsqdlC8yaRaf/d/um/9JgHS5aKyVCi4XBP+48RvE9fjTosfMWwBTpO4tzBZpe z/136lgSwAeBZBGkZ1y6K7C4OiJ85B7y33/wChH9igD0FVNfSmiJZv0PsPfnzO9P937TJ/orTw3M l3Tulxhdvn/dW/oPZq76euIAcxO38IgJE8ydFRaPHFOYj55zFK26z2zTRODIzT/4mDwInpHlt5PG JpZwUarVvIJHnkRgeVu4Ygb9G4YW4l68kc36ao5hulo0NkhGsgyzQ9QD+9pHu+A/NyXuxvmTfHMt eGbl3a5soeIAY5qri2aHzHQ5IBcr/foXERZPhgublRYXJEAW39v03HIKAO5mJii3qdTY+EhcHSne 9anKl06moHrtsoKntfZzxeoROAyoDTaBeIhro07xI55BxtXb1QRi7AmDZdDCsdoHsz2UpLS1nJRm Ccf3+VNIgYA5Rd7fLS25MSbBHNg4/bVjE7cVo/2WEUzgqZ53Dfm3c0b0P65Nd8IiYWerHOL7FFJx fXsnPw47VQ2z8/PpVHti7QBYSHYlYDp1aw+7GU9/ErTBfsxPcn1a88PeRXHg8+UzBdNoJra2KMq8 piu/GfpsHPWX3cBvWQC7lMxxKkxm0kc2JIGE+kxDU7FPMNH5cxVmtioqUuHZAWEZ4UMpOQBiafik daLm74p7hoCGgW1SyAgmdsCL9J7Ams0IlqiI0lnFLSIm42w3Ay1gtSDXitkGskn9oos8jktytnW+ ADQ+zpzac4dYW4wfTlT8onnnaNesY3W2vKQjc5IBj6EFW4JVYx40pKAFvU3Gv1Nw0U7KznxUSStT ngJmxxdIwOfu3wcbr+Z/NJ2GzG3dKZqAOUpN7AxMt19dZsxmUyHH9YF5XgfyLF07RylS3uShlEWJ VEnxObfYNXP5Ai1OSjxtcDw7sOJU+GP2oXJaMK+c/J84NQeQJXnN2fMPRVAaozXKTw4NOdyc7EfO IwitK19tqruQbNamq6pfWXurFLMC4Vi8NbSUe/5a84hvprxXUGb/q1bYN5Wjcp/tcpoLqi0I5dEh OYy36iTcAhvXSIscwxTbtdQew19e+2IZu5gSiQ1AdbX2MGovkMm2VYJqhEATGSnNwR4VaB678PDy MGzx2G9AtZqs7j7cQK2a2H1n3kRD+GIiryYk32zuUwtx9dTf0eFmD11IG9WtWWIkFC+3GYXnCe4+ WYYVw5sZu9zL74up3LBBHHwYXdnum6JkVCjnKm45tl57mpudsyxFG4FuzkjT+2bntIMkfJ5N8hTA WWvoaZSPlbE6YfgKmv4ArCGG9VXZqIzjzR8JIXywJO6cn5TiaHaJYiL3Inmdpl+3kk8xGcuhfTLc dbBGr2bjEpAi1omJyWDa3DOMY8qW2eAlh1zvM2iKZjYiQudSLgyYaLRrGo91wjPjGRBOZnnZ3QUw Ua8251YexEhLk1762fVit73DotTdqTQ4G/W9fINxZEWscrqIIRquBTeW4b8+dmWc9iYKFeOsduLN KxBpig/EwAGi0EgxgaabjlPr3ahRDqFtIl6RhooQ9GK6gsioSr0ekZexZ1C9pCi5pTcXme+Fg8RY 0/ryK/ZF2kuSPC9DifThfaPxZfLZDkvTH207McACB9eWigS1yzZlZK66P8Cl0fywEhv++zbSFa83 n6YeRnEOacU5a9mgeVGmnbhWnlZII+rNHj4PfSU+hbNcDACIx+CinBavjRuxdPxEXZaZgHQxw61Z M86Ut9QYu1Vt2peaE/Qn3IikgiCKuW2Tn7Kn4/qHOmpAt8db4Gcth6CTnWAmMB8UckHufldedFhZ ovzDvKmsI6TVzgpqaND39n1SqRNfpS0J3cVtPiV94qsSnp+UaRW71zfmleWwQUtN5IsKQMHNhE3i U4qSPxMSO94nJ3vGmJuL4Q6LfaXHUkNgMprgQe/h34Yz7NMHye5HhFbEIjY1QWSZdLY2dmt4/67O 4ReCtM1+bpIKRGXJCF3bp2x7Izi4C5BRfDhQXzPFadmcRx5paw+8Bk1LgMrYr5OQybqZhapo2MVZ sT5BWNS5HRlOdAmhICxop1MJLprGvbmeFFNWqmaaKC3J+SbyxSn1z0BBayS9pLZJE+ZGzGPZbtIu NhKEmCMnFeVCpO8EirokUrK/eF7FXV2Bd6BXXE2QoTaSFiY2maer8a5OGmhQ8cBw3N0000cm6uLB DTobiZDt2mVSAtXnSCt+Rv4K7kdtzAN/6ivlxhvCKJ/odwvETAMFGKgFyRLdURdBlJSM08saPj26 GrbhW2GNeXkp6HrFm6bxbmcJKS9yBM/r3pip2KlyVpPuwQRKcsThMhjaJBRT+J0lvPQ0eSpEDO3V AsQctm1B4oPpkW+rmqtiK000+FRXHh+vuhOphY0K/8BTHKja5SJcr3sfFlqXzjo3/O0pTzisIxRd PJYYnvB3ny3/d33gugzEW8MSYyFrMOd9mmgF3m2UNwCr7Arg4kDXR+8mjVo3/a1Ghx4Dy2IVqeY3 odcBy+vk0j+Lp71xQVRcOGQA2A7DJbnNu7Guqm7dIylZGWJWCaa2NL8pf2qQVRHMgswBOQvgPnQc OqAJZFvXv9eaIszjRaH+nrE2l2/50TdrnLFIqN6J2lbeaok0N3aC1L1hBPKWKyMJgzYu7IQcq6eP XJMj/3RoV6mw71wstFLOFF+qpN9LOqOlsn6Eq5pXPe7TiRuWA2KR2CVaJAlYt6OBzZIcXCbfysze UlWTnOBAi1khPT5Qmigj7INVmhylSsRf4E2HgKwPYWdrztFlGSITykrrf2YD0a+uRpvWWDMt0EeT 5QKh0KRO7Cm4f2v8tCcxG7aU0e6LcXanD3nDW1lJS6FsPVp4PEo0c/HrFB6lWJ40J3fjqY59Ejp/ jH1No6OprJZ0AA6ABSfd9bneyQ/KG/U68EqYWjW1iYAcYEuhr93ovgvCBKUnZ5pk0Dxrhl/YP2vV g+htKcs8suQfYlD5iV+QGprrCTzAfDQgwK3B0Vv3YTm5RZAWBg7DGN0Ks1PaDtj702zMIeF8Dw8c N2T7WXPGOVx2vCnAUFiKB30V+6MQJ8i26au1LGa4jOU+nWJbChWMVqWBhU1V47HLsixsUiAi1h6/ JOLeWYpMYXF9kwJzPrlys5cziyKOe6imUE0QK3bmMJ3sa0N3ZUJHK3HGaTRLQaF0QlrF8A6X1O2p E98a/n9hvhnn9lR11InhAhm5mYJsvRE4EUC7OMVCsFHEgYJO2Nt+fi2NEMm5aI2LuiItXHf2WKvm QS/5e7BqUAvzr+ut0y+W9oBnNLzXUKT4b7wXzKD2mdukqF1mMFGjyS4R41ePug8AkCnAL6h1SAwd RS6hfTTz0UGK9XBbHyA/RzHeh1v383l17g+AtC/22hDSEBwVdbvTsdxnuQGYCV8uwjLK7MqI3lbH woSjF/f0cD5XpRxTFGVM5hCTZWP8TMJoMe6wet4AhaZzFHrh3CSHF28JhQmHnKmyNLBLT4xvDj7F R0w0v90fwFBbgHt+C5wLVHZlQTKK+S4ScfwoovdWAU6sfn2tNdB1jA6J7Z3cRgQn5O6hbt5s8Qmy KxE3D7bqnh6q77p3N/Czm90F179y2/TnhJpME95T4dFHQFbjdPRV6zaOFWO7KUaH4rLwnNFziVHI dUFOL1/IKuY50d+Kjwp54knW7j48f8WCoSGcJb/Bbfm1HtglOSYiFXhblQ8VhHQzhRcWl7IiX0wm oTah1UTRgaJVP7I2j3kheCp79w8JmDq7QGiz964JoMQgIqufLOAAQzpD9Kk5MjYgpZs2dDfs173/ 9E0jYIjr7EtF0o/9NUoGoT7pusXlVjKWE+gkx/Mc7hL6ZGR6Nufxmezmm6aaBRZqu3a5moTMvJvw sX1V5Zn925ODk2TkvlnKiuBVnFXBvPjCnPQrF9xpfs6azY0f7I+cQ81ojhybydXZwwXxOrR27WFf fQYUA07pIw7eTybzhVzBeaUmsJCqLbBfhmDvPaUgLEaJYO1HW6N5GDmaC25p0BYzi7FP6rWgBU53 aEGHjo6dA1ZwEbmkHrPFEqLxNfl8xEz/t1BqMXipGTFIZO4ToXnVvI7Uiq9Ciu0ajdZUVNkxcwx0 fA1zDrZj8F2e2brLnDXUI9+d4Rg3o9PBvEo83Sn2RZkrQCm5y2RJo+FBovTip64gZfDFgrGtkoFA 4zhzSzFJzDlxnFt55Q/7uZpZnD8p2gE+SWaCsJc9tfmlN/SybHCSxMnZTWN5xJOBnRx661LovQst 3ojw/IJGLyHkT+3rUZm+/CSl8Ad5kQpNRJMhIsJ8gY/giY1MLZFmUmDQFdGyd0/6/rLh3oW07WW5 bJ6xspw40V+/cCmilmK9y1JhhW44VVYuMbsnkwipfjHmwlNPt3s170JKUDNmw5o2105R3CfAr4Ir O0LCN8orn3LSWjzHeS7dFNCUgtu8K2a6muafdssHvuTE4hAMnImGLAkNfP/qK7gXYLlme/0rGQvD Hg76t56uQ8r0hip7KrY7H8mMz2KTlalGwpjUwpsHU+KAd5XT9kPkTPJumsTvNVCZ9b7zy7usbgBg puAzzGwQKb8xlelQNVB6GcVYrHYlhkOpWKiux54q9FbZAWKDtu9iRUqRe8ARHjWludh6MldDXp7v pMGevXUgxq8ya+/o7ooCFBVM4vPV8kKsyL0sAZB0KfC827G7vECMDhNyjdhzoAda97YwpJsfM15q jlo3aStasC87LZ2BplcjS6RlFvg6y1pPpHaVbox0shgRlovbgG93MUdA4K5/V6aVY7h63QUFIaNx /2czEmCT0szvjQtFLm0Cu3hDjIpFsGpVmyPgo/enHTMhTMbsac17KAEv+1jrrO7Si0V0WCCnbb9A AKMMAt5hRRxt6EP+VDu1Fmp6Q4XfgY4d4gIUKewEWLQ+wISYdJZQAJRGifsu9e1cmAPfiRVhBJky DOlpgINnlBwVD58Gy5JKryvyQNLmuNWdUpDT4S1K00QmzgRZGHd26hiQtOQ4waN9sJYWWOpI7AU6 qFoNrttgeuOlrEVI+C9MC7U4qtV6cEn2/T1a0RiX9z+IzHC05ustLHeMjVw4fAp1d9yoWIYzEoLH TnGBhzIl2VESLaaMq8tQ0dtuaUYWWETpixQqc8IKjTfDNKl6Dtaj6j9ODnRYCtP3sGL99b3XPO+8 7ftWSc14piEtxUJvmO+DUFsMjmnbEZ5Hs5a2kc8/BcMuoEqy+94tdijppARXZClH/bIOJTysGybc Gstngdy49qfFfjed59IfKa0Xl0b9Lh2QYXpsElBEWfKt06M3iSYSNBXJjsdmIOIYM2H55QgvYHd1 yWkF37of9jRREjpLXjaXo4428jWllWcGBwUvQVNo+kqpB6ZtI5H50SrvGohiiAEmZghGeKOAUFAI L3VAzhMC0dLQQiEiDzPjkykdYmEXe6/CO18p/Wh9WUMaUyXP/PKRdCp1GgpwAf00mWWdY/usdr2+ 4xB6HxnHk/NLyB/LsjkStEWbDSezLcDDym1EqrgSwv+Nd1bDCHlpWXCIJ3P6/6D8rigI5+Tyg3TH WegKOqIWGA81Lv97A8NIeDrHE1UZGI/Xo6reNsw2TixR0crtPupZgk19hvgQvCYNwjhOP6zTLiet Jamd7hYeRyF1lwuKQnfVFg33jyhhc5oSotai6wV5lf7hmQigGnKJl5D6zIn9Gpgv8NnGfsGfYilb WIpB5Aa0FBJHSBN6ydO9Tz0ZnAHSPiB7FUzmt6ZI8wKB1Kp89tIMfrDgrXFiSD+bLRxFDCLrjtw0 mehMHd2JHCWBnn/AnlpRueivVEsWlKLPFUzQvSjvS+XCbvokjHBXH0IFrltLiJoFlPRJEiGen/Ps GqRYAT4p5GogqErsFupW/j4Qs6YI2IWV3HDrvQsP2cDd6NR7j7PHmwop3KNFMo9+//J8usvQWXGk yWQ6UMcy6pX4Yxotn01PkqNJh6AuU+LAU6qqbfR1/DlMDajHkTt9nv88rXzF8kAZb/3EK7QaXkDH 52hcX9pr1apX86NT/zbm6Xea0A/+QD+ElagYRJb6QzTZbglImxkrnFl2D3AxbsHG0/Y1/yBAgDyi GHF6iMT6OrAjcUwt3JIb/93bQ/K65EfOVSCYHo+1tBVKccfNc36YGtvaj3KlzyXAuteSxiq9/cWt w9GLkiVu64Y01iIvtIuEK2kRL80cUvx58nqn1NHXY5NSYEQjoE1iz5UI8WO0CIB26+8PN3nJkzRQ G5JCfOMa0S+4u6a+oD0NRHlpR6lXh43Zd9ubMdDHiLHKGyw3SzDatxYGVLS5hqn/aYW18mYwFA+y okOfI2XzCFmHq3OG7n9Td560hSy2OLF1k2EJjX5mXrCYoaViuFMXsWlaNKn+WIORI5Y/XO0TZi5f kZVknDAfEmimUsggdkgBr4WP4jWHUzWwvnQ5e+uCE2H+BeU1JpwyryPM71vi6+LtETkgrT3CFMdp bSQosRGFEfFFD3F4JHH91X8eZq/OZ9XsAn8il+TfuUpuMKger+MdZwBq/AQ/tflo0/Oqcz/xGOa+ Bzs8yd/GYIsis2xJtf1UcVLiEJE5XmtkBoHV5w7Gr8gK/IITtEOmfTHBXLtfsjOm+8E3w42Lkzc4 hDDL2tdvasOxJWg6QVEr0x9Z9n3AM5tBbOPtJre5b/UyOrdeyj9vhC9Fskxx0iaAnsf+6yiUx/bU wkOnDWxsKm8slzP0eGQGyRl2ANgIZOICRWAJ5SFLmWEe7M87e/2HYpOQeoEh5XaM/kevX6UqkTt6 IChPxOkrrFephUg9Ld7tNVONRye3XS9ikCyS/x0WYeO9PfCsdwA4satsde1WjOwqXPzFZVSSUE7m NCu2KDHovwOn66rPbEPIH4usPxykpQIOvWCwLHTRscj9ctTl/b7be3yQiH12cbCrO7ryMAqvQvQN ZZcWE8wQgL85+r/NRQhXuXlIZz1/sVwjLg6B7Jdf4anug+IvCa4QhRKOIEUANiGwCfcWhQOf6MSt i8fnQ5lY2vtLify+/+CMaY7VEiI6xbYEdurdsio9mmdw2ElTYFRUbSOtk390eO8dj6oWwauWsxra Nd7Q6Mu+B/2QDcxbYX8NhCV+1C0p6lqCiplQvD8t1r/klr1nVV68sgUNLz/uNQPKSZKpyKYvKXKC XlL0t/fyFWmhPqCUXAwTceYeWr2kfT6IkIdGIywPIPFau/V1vLj1H6laz6HqSnTlQaMTXhJmRxd+ IeZxSWOXZl+kka6vOLQCnQkDvAPmMt21WPQrrs+kNh5DmTU9QGAc7wKI3tD4RWc7nF6pDlii/ZdU 8xUuZutZ+2G7+SKs/6eW5nHIZnq5X/Jhx6lZvMg8XsXQBofTPKGu5jfdLvdUWKbxDnXoLo756HLg LP0Ns6HTkk6JViliVarAU0OFh9rW/LEKeW1tN201vv+gByf9AhUshrU1Jqpy+YYevK/fpxuMv6FZ XaHibD71CxjBurtiiGlamuSvbHTt5xkM7RQGFqOfYK+Yvd3SHw30UsN/4izPepnHpJ9JhxZvW+lt tH7dVaP6YPn55ditcKQqmKnLLheDXuVYC8Io3vNKfkuYIjb7Jt4ti2pPlhSyozjA3LiR0+oDWS34 izB3fgEdAHWf9uv3oMFveyCrhkQds5CosTtDk8SFqQbDazIbPMIYQOaYN6DcJrp4Ps13TxytfNmk dCC+esy9SNhuH0jHtxbPLgjCDBgnlS7eTLo2b0XkdiGqITSuJr2kXT9mDN/ZWDrfSS2mUpyZ0smw JaMgHsqYA1Gtrk8YhyqdKjF4qAINLyrQVAFE6HU75fUMj0mHSm6oXm0Kb4ed+Qz3nBf9owf44e6e EqLT5ywcPDqp33rNTds+zAgsGcMvNyDtCh6wx5HUR2l1sLb0yvUgvtYMXJiGeo8quzY/NFIKYF3P 9ESKcHrzTqd/3Ri7h2QApQPLWpO998Fc0p+dWGXvG90FA6vhKEGQtU0/SRXuYrnPDqRN1XSpUawT p0xF+fo8bjqk7LXtTV227RWH9OHjAvYLvcZcFxY1yjKY5+goIXiz+VnOBaUdwnk1ppL7WZEyFurC kXBKQ3tG5J+KXBhb9uFAexGcudI8Qe0XWP/FClmIaBMZ59dgV2ZVVxZddLpGQ1ehxv7JYrcFDTB8 d5UeZG3Ms3ibQybs77u1NK6fktL1ccFrrcEtMmb36AcIgpc9qx9UbzZfosMOz4Qz/MqCh/+z+N9/ 5EukdwOFv/wGFfob690sqObdjtjq7ZibAT2wCChlM6TZ3LlSuBLoezzNNmWTRsR/lVyPugFpS68y WqMOAWfk0P+cAHxtpg8hQV4MXf4PRDkbYCaByYUHQVfuXau9Yjt1mNRfvH1yA97UZGxV7NT3QcAX vJle6lnEd/518pfjDl84tA8fXEgYFiXRxEqpXFJB956sE/CcdN2yomE9107QwNAw08p8zSixNL7f QSHKaHN5qZ0pKeinPoemFYIooqxfkLXfB81r5BoCOzKs+8iIHqwsqVmME5uEFq6fhtjcAnGuLzaF Zn7k1iHLWBZYkkejhZXzTXKZfFmiLCTioeTpi/moEYpRLd0P9bCt6NU/Wq2Uzjt65U7qpD30PtqB pmo+3KJTqAXQDDNpU70PV4FVMBsfWzGvlIT9GA7S27Cg3cCrMX13vuw5y3VDPG9QHRUa6qFuS25+ m4Va+nr24b9y8E5w5If/Bka5aTKrJ1QUEOsT0x3F1WYD4NL2Dw+tEScrZ3xdWWQBIFnft/ceM+O8 IUwCKf7r7Pvd0K3AKiszeXfSrYJ2gHOiSyqmF7kh9KMP4UACFBdP1/iW9BZJJ8zOfJBQdeLQp+1u CWgDjF8kVxvAQoVy9PaM28dOyCOG17dWmfjdhirnoFA/RAxd0X8B0a9+G1dkWwYUOBRlVidSaBtT y/z/zTxcGgABW3JhCFA+/2AAlOv7sr+dgzmMHBO34u/IrQUFZw92pKDGR3NoptD3qYFsco7/6xDD FnRbTbVKtPgFCfYNU/J49VfzeFKGFqLl/OMONrxCHDRAhtrNP3SrxDfo2tSrpn25AugEfDr/c0/5 6dz7KG8WxUmd2pLH5BBFOMMEK4ho4e2thHESCUBmivhv7NvcIUTSvJl3G/QW0NrHE+9ge5CttWwq sjPqQKgWl89e7KatOGevG0lpXDzPqJD1wLh3ueAti62I4c3lO9d9S4y48WbcvA7JnM3xx2jvXVfI aBDXETqE4uQ8+qY3eggTlU2vrY8YM3JsN2B67oCmhUeRZ4xz6wzwm/p3yKTHeBaAPUVpcJ3eprmk 89gydi5Rv6B1jIBkpZxAm2CqXAob+sFyvS8HTTowF7wABVRvpl7OxybsIpkkQ32elmeYv9vG2dud CS+t9eZrG6ZuQgZ73IKnTBEqueEym1ig579jVFyNBfsiNTSF+zU6ry5R5eSf3wuehqBDfT45mXGa zw6LQWjPhvcgo+ymooaci9+Xy7LZ1hP3WGDvj21f1D2z6CLzyrg+m6StEFkfEghYXZ5WGh0SErZI Pv8HOBcdstsc0HfZ8Em+Mc9D6y47K/jcSnauWgFfcUGTVag5g9XvJZxol7Xs886PfYlfggEnUMXD gaKlBdu73Y7wgtk8n5PRixi2br16MLesFXBcCrQaL+DkyQ5K56qKhX15eS+KeW7lqf34Y7A5iruW UIXPADeRSroH8nPWYmrKVcbTbxHSvMPfpPuWoOlNQe9m19dGNrmQwo7QoTo4bvdzE9vskz81gulA rftTG3IQiINC4SYIj6YeLNLBhAaSiyJ16qaXBXs0009aAD6sniApMkQFYdubrrWfBT3z1F3q5o+F KLHzu4RkVidWXmMdAQZhfheZw6xdLcoIS/l78iIgiBEdK6aqInAjMnllBm70BQWhSbE8vI8f3X1j UiXAV1HhOwcDr/2ZlRSrVXxHxjuC8+lu+O3nHWXgiiuEjwaf4QuVFbUjD/SWiwkzkTdWv1ZB6PiU 8rhkuZzyCILKuTdVWugyzbpzeJgLjsnefT3umXuRSz1JdjHV3cTVq+5mzKCxlAGWX2BnACvKIC9H E9N1ab8tI8lBnh+KZdPTZoP0vCANeMvbnRh3ny5ckI4Edn+6EpB991slDtztF4Alps7b5JPBSyFm 0vrKYRUF5yGXYe32TcrkTsqJ+AkCrDOaTuCb3hwVvtXKoTM4Zj9w1aAw5iQ9wCj5gFuJPq8kbrUX nPZT6paAc4CiU2iD2EnXcTiBCHGEDgD3lyz5RCu9sovQ4puMZNQsHO30N+phiR1YQpt3DIRDZ9xt W2mSE0Lcv1zsJIxAej/BJIAofuc1vp8VqT504hHqnBxngANS980l9uQDppJ9uwoyS5ZNOXSZ59fP AImzLnaARBtqAfXb388tCw62m3I4HApzCMFYuqQm1SvP3Iv9oYpKMUqYunvM6C7PUOwwpxUqFZoT NW4hKLPHzSl8deoY/fxdiRnc+4JxYOE6sY5LCbqOADxf6J0H2z5V11YKn7tVNihdNTS2s7/94QT5 h3a1rhGDA7WSdXK4/RU374CsuufgAPGZ8ITyAifrVAe7cu0qgK0UnopocTDRhmHEaiTjBFawt+OW craznjAkjOXpUV8Q6WEPfaJWb3Nj8MgmZplngGNmPl28uru8B9R7eMtIhBWUxIPDNqEqqhO3kzIC XKGosgNIWG8AALmZMsAvDe2Aci/jYGGPFTDPNMWO+BdXpBIr8+XC+cVyspbSMV+OQi9LxmxRdsVP +NCNh1iaUYSWwMyHI8hkXtMINz1fLO0bdiYKUPGGVCFDiaJ2eWfCpr8Q1y3PuzB+ZaLQ8FlQNnQB zMJoiWbk54mZ33+Jqz8l5ldLj8rHytfcnUFVxGUjrllyIvLhzmu5mThxHW8FLIT6e/oH655Uwyz4 eopsWKiT5EuwBxxWlIBvJ8tfaIKUHXeUhZ410QYgfXhUY92ukpshjbzs6YM6uqt+mmv4+pHDqlB4 9VfvQqCBsrGDTnBPNC0gLAraC2pUHf0vNk/F/LHYrRCONRX7jEsk76/D3FCwGXaEz75eT8e7UHdi pNvVGwPnjgBN7pQP281+FXaEnfy8PskaPe45a+ZYBkcfmiDTocCqVm+4u4eNcNhcxo9qXr5sA/Ni HU2AH2jSrLH9WF4sqhADZfHCkigzExHGQNkR1Eh4ffiSevekgi+VKveZAUttOBuAhnIHoP4OEOQ3 cnxqRPlJ+d+MjgKYNyo65v44QRCr7nBq4mp5ZRlki369XCAPmEw0nVmCbx2jgF/9UBfM7WW7UC9a dKByM1bR33LPorjKyvZnLdMl9D6TrHYRPf7RSc8D3StTZzZNIzXQzvoDCDi/OfrkwwgS3hgK9zeH GtRdiZf/LhNig6c0aQwgZ1QrU3Pu5Mg/7iGbAnxNwMDJ3uQagK+OS0/j972puu81upRwwxJ9wvx1 W1Nsw6FAtGb3iEi6AZ+1n4wGCsjeH1tHU02gWaw+ZkaiGOO9R8a0Q+QTgbjQsnixtO01vCuxMdjx XFqYHhHdXB8X8ShH1hJ+3YkmPHcWKOVprrN56OaE7q9FohN7eRreMyCfkHJA6up8XPp3kZuPX/Ki CuW+FmB1EuywH/qZF5o9jB3hZ0l2IdveunoCTw7dY98H6Uh7ZpMy0x2a2e1Xfno+2mjVL8xYAl7j FmnPXpIjZrPj0QlbNFpIBV/izR0WQ+MzgwSMm/XCktVv3iXJUo/WIzW0YvZhRaYMDL17cT8pW1d+ ri13+Tm34Ej+ILWMmuV4trFvUC/7y9iffHzOiyXR4xUgK9qV3gpRjWX+WFQGkxksoC3aUo/Angrr AafXI5xue/R5IQXCq/FKKNniESeyygSy/9cFx3JniD5EzSBPT4WunTrEaJly/84PRKpSBCkUBULI lhnSGeB8+vCtogDJjYtUWCgBqYNcxTWSpjni0PY0ZbBTiyQ/ypM+aq1/yxmxUtEgG6enaS7C0w4r 5K91iE6+tdffcj+BhyUMCi25BuyyakW4cPA3Eaec7IoucaupfolNjdOitikAWFfwMJxm1XODTwXw XKVlia1dpu1IFQNPSYsw4B2qbocjD3gtEZ9VB+zbmH2Th+U8YSTMYMLL6dxqzDl6Qjo0Za8KoK7Z P9e/w1Tx3g3pNcYcYg1pZ1/RSkTqOxXUSlX8Zlfpvhwp0qZb/Gl9N0FQbxk6v+arcbKFDVxwme1H FrQ4MfXY3Cc1Dp1bKpCuQRH76QsJ4AdbX943rso77sm16fs5ESW0sjFkbpdVIx/js475FN9gtxMW Si+A2Gv9KRijrkhn/GEPl6xmbj624+ycfaCrW0OgksHd7zcwt63j4bxGF2L2UYbu8Xj4lLHbTONQ hx+2sEN/DDa0IiELq+QTOnAkwKpTBAJJLq6DW7F3H63TGDrH+zrA6R8STL9ic/I419RgKu92MMu9 lISa33lxBnvP//5DclPiTajcrs5ALoyp6Bmqh0vk+JWx9QWDoFg8ytC0uy8rZ7Dn1LPHwCE2XwGb GbUvCrye9PM0cc+luQtMj44A/Hw8ahmc7v5CHzqHWnUopoY/rBphZv5hCrsjbGcPunXmdqntYK3w DpP5NJ0eN7JSuWnK5Amahm/BsAYFT0oYpfntfuLRf70u0P9j6FNSFTy1jlj+DXU3lAGepjHCsOXJ P1AxEqEC9w6SwsYjjetGz8wgoH8N1Qa/g+Ye3LKab6P2UombW4az8voq72EBqS7AImexyFXsGCb/ LhsXSusKQsUOLDF6f31WdIUu1YugXOuJB41reeFUidVubHdGQOVh5Esacpc5x7nXtnUd+Zdgr+FW 0RZVsuyLlTh6HxB2LMpk8XM3kqC9CYMLL839Bgj3yDzd7hKN9/Zf/f1Ko2Idovr5EQoV4CQSs7oZ qfmj2ol1AcrzCIoSLzHNsctbniN5k6whR/K4h76Y2+IcHJZicp2D27vdIASmlqCW8K6j2wGDO9uB AgMmRC81LvoqJk73IC/FAMdysOBanpBCnBb6KOy2I/AJSNlF3v2UWkBauTyNvzzBx1SKAjtNRy7q Lfj36TOenvhuhaZA8NqaRzPtyQ5ZQVlb24akmfbJrIv3uXmYWwD8BZ2aAJuxxzaCbrfM8mKovsu8 ErH8NjGaSAuytFGl08pNouLfcGeiihmmwAfxdKBNpFjRCBs2O7DIPlwaRxF/9EgsfXQxU4q2h3Wg 0P0aOT+O1lnn2oCTJ0jnwlq+tNgCiskK0UnW9yVZkmeScLjwD9bs3TDTsiNKcOhrwNHbMUHV4ydR yMqCyTlhXPkOYmUkZpE1uqDZ5pBiyDLzJitqys8LItyJgsZRysKk76O6LAVM6/Z6zMNgtDcaJ/p2 SWOkp/H6jUtYbBgn+xRtM108EiBcamnWoDRP5chDg/DDnpzU9eupENwasj1cMtqrXuzBwrJHKASF gsx18Kn6icI+rYwjKd65D7Vg8l/Ein/Aj9Hev0yVFneIC9J0r2kesgVl6UthycN1Gy+Cz6ekcwNN ec5dH2NSH7BPvvEnmKfIcJMDtV0HQGp3rAWFSMczWZukRT8ZY59FT31nH1kn5sAaewlJFuOnzLMj GHyR2c2d5VpjwhYb79h+3zzY4I06ujE6YembxeTEriMGaZ7BzSvDt4IvUlyJSnAjzwqUomEQujGj wQ4JFgXOOVZw58T0xM5XyzcEvV1LXkJl3kVf0I9XhHwnxqGvbntXws86u0ccpAgjgb7yPBsRaUT+ EBOQdO73DEA+OPzx+XDErvi1gUXkNDKmL9nO9rtdA6HeroWjhtS9xisGN759EMg7Db8CFvIVY6Kj JQkgeUNcDOHtI8IeSCIG5TqwbFpsJ7ui4S+TOaznhTuRy9lwpB8ITIXXOJdxnA0RmEgL21jTrqnZ nM8aAokDB4AfQvcCLNV5HNDZ+M093n84jPlHakeeg6UpNjtARITVVU5AIha8BVDPKx+12L68ftsW 3NUacXdljOrX4nAv5IaeXzyCfPrZq8dCCnE9UNtk4PI5fKWx37APXgUKh8AxcdOaM8wCsshso1O9 BZRePhA7CSnaVAr6uwZTPUrJ4nd49tQKGh2tcWk3njuvEzMq9QrPyOZyGGFPVitDp5NQWSX/YjxG muFhImq/bC56NQONQLxxsLfrhmxl4sxJAbu0w/IbsUXEsmxkXOsS1bR1e8H8aa3zeGqNg00hurhR IukkfoIRHNfZUPnTr3KlukXcCmhTr92OgKuXhrTXdJEczv7cKimKEHuuRe9v0ET2wuo6vmIwcUc7 M+5Y4WcYwF7tRtE65NHqMEyyyAV26sD7W1BH3ZYcek2QQ5F18jnovTuDaKG0yI2S85C0I5SnWchW NRP5w7DGz71DmoxuZwf5yYdGtcSNX7FrDhIJV4WLoi7zKk5piBGo84p9EwB5/Dyy0drgVZt5+rhA rYiY8mYPeKsjzZYRoQMeTDJVf2Yf3lo7/UhpqofpBG6NhDP4RCp+xQt9sJus9ajeB/KSAlfm36vw TNZ0NmTRDqRQhB+e2lOIbkIQgAHGzg2cI9+yhks7yVZaxHjNxbIWma+MlAykn1FQXL3b0xYtitTg Qr7St20YidmkEP8DcW5z/KrXFCwr1nyZduPoXu9PZVCuf2N+tfa/GnDbstitYgEMKNqPZt6p9kuz ZXCdrsuxLAvNElC+/twtjHRRfbyu8xGC9OHs2LGBtFKLqowXoDLIG5CoT8HbQBYRmQC7TuheekQb n9PTHeGgEm7Em2QjDfzua8aVa/3DgTLpPTz9TnYPsGFhXFdHxpeX9I91Sk4J8RfreAbQLx/P7ndg /StWSx6gEMIz8azPZ9ppiVpd1YckCY1F1qeUEVs8ZoaVs0YjYja9Tgu36B/AI28lpI0ptZ3uymKC GJ3hkSqBxwl3vdzVTpnoKUOzGFEKEZiQgkKcVgAAde7OIeaDfq0jF2LNhT6yEj5LwsvXfLQqBfpA 5QjXcq6bVpRNBLuxXxN60Vmi8W+cSYDKDxHGswx8MUVbGZW/Q/KC3LewSpw97YEb65PcZ+sgBMHb M8Tpxm/zp334xyU5LZUHAAtuwRN15TLn5OU017zjHB+iXzyv4dsyYTobnw79wG7Cc+UuqOZ7npj7 Myegy+CYkyF5FW9MrVT7z0YK//KESEqZo4rDl+h4MZ6e/dZ7FLN+l6rrsZsPmuxgpr4qk9T7FNsQ rJViu6kXre/uOQR7AID14qsgGD6TSnOICelzIB6Wk2LlaovgNpP4w6t14vPxCb3pqqx/oaVkOKdW oAc3fos4Ziqf3SFFhLgYwyi3k4s08i6y89mA1HNFsEb27MJy3T/fckqdNFw2gTN/540MxK8xWl7F rT5iQqPTlQAVgYYEqy5Kn5odswaqYJL0bta5R3Y00tXx5tXN7L2vFiYBs7XpZrho8TL/sPkPaRoQ Y2m1w8/iI20oX1Xr/1ZyTpoBwRLKnRbCVsF4RGGb4eqW2ZZgnQlovo71qsb5q+a4+E+HLVhsGUoB FprlKyJ7mopM49PW/4WVxPPZKs6a7D4WsxIzE/IDP/vFjJRSoI+eLSld/I3rl6ymWZQbh8z32+f3 jFNaXcjaqoqSbM7i+YpK+em1J8NSl6ba70itAShiEu6uLZF7wsF4Zu7GBuRxsL3TbKca3H243R5l JZvPIcVCrnGOPRU7XLmkh2hsv/oGYfNzUxMF14yUE3xQvNXcbhCy0hbaC4NpwQa9RUK9aDXN7ZVL efp+36omBz1xTfGvKdcBYdfkZSr5eyQUHvMVVbMarUlrFbsLVKM8Z49x3tf6WnrQvS+OhghbxRuc Cm9/fyCOKgvzdyO+dyRjYoxGB6yXGqyQEteQNe1XJQqVZxLUKDdh4sG5qh1p8JDW5tBciaXMLnDV 6Bxg3a70NY7zgPAdFgrZDpVPjUwkF4nKZ2xTaWGY6fEKgvHhvxe4DLF7eDwj7tfRWv73dIKWfpR1 VGOmP/+W2XN1gp5DCrqzTsNGPkaSWi2E0mHwEjif2VFS74BcbIF2Yy+lnriqJjVIj06BjEDQJ4Tl fJukAk7X9OgtkTfNUC/NZ0rUhQQ5tdf7wFWkajl/PeBxBloHWfjUPhoL8FOY4dng4WgAillYDENh rLYG9JGS0aJbmoFh87t3vWVfUUZ2gHu6HHCOBDqFcViGTHo7X5ldvmX1uikvKtE/Som911dG5nPW u8uaYL+XOfQh9boIlnBNLlaRi3lAA7JMuxcVsoaNocWWz62mqiQ56WgMqDIiBUId3v2rrEe23I+H Ft9ynaoUzgcsUDXyIlmSuWuhD1fQ/l1ImOiCYTWIuduflM3h6cvueSHp9T8Ec9c8yh5P5iO1ODZS GQlu6TlsNSgS3e47aMl2qs6A+F8LEyWFEaqSxoZuEUeAekK7T4vE8olYjGGoyih3sCk5bMTorv+y ziMpLk7oPxXgoIefLqieXv/S/bj4WM5BYGZT2USr9wqZ2SMlR80bdOt8h1xuHOkTkPpu8rZ6bNvh Jo2UPex6H/FUHudcmDWJl674IKbt+vqqg2qEWIW38piR+M43RkmhkX5F28SlTBIO/LvRZDmyOy9y ev+qNxS9ZS1qMMdjq+YqAkBZtQ/bZlPXEL3SzPb/TlbOkUcg6P+P4Q0fxzdLsnFgr+PzpJdvMfCs 1WzqEDUt9/gP/CmjMCdojjtUz9yu9yRf3MDqiIOvyN43U5KoHnx8dOPqeVe7XYtePXp54RlstTos CVD0c9YEin6faWkRyvtCwTbNgFHiCzq9w0Liywb0hI+/p+IT762cKOtqtKsJA3JOlJYEixQq1QSC N6dQQ/rvL4JCsPCOX/SpjkbaAGVoLnN+3DuU0T6m4/034IeO1a+q2tToklDVJ/aYY1ZO6NBxJe6V T2g8lEXGyaz6+fnHFA193AX2dW8oIOGfIO4yS9wKgGpJQChvYP4JFrHcDkV6hcNzM7JWcDFuy3TT pWI70/4Ok6/3QgLRcva6d8gzrmVEtJcicAGY96SNzrx1hmCM6m5Bd180j6pfCfJw/daom1SEHfLK OS/fuyTA+4af9HhruDDdMAhqp7KG1cMT54of97vIi5bcvHC6hs6m7f9aFTeYWZtDvKaDFCYlft6E 8lP2shU/Sxfw0hWuczlQaVqDmOixo5Fh/R5nlsYoFgO+yXrpR6yB4SiGOv1XDsViS4Prif+TjzoV Ov5tds0c6uGpIjKZFWSlmHwrSqSQcEIdf1kMTGSxrQbNE+3mdasdlWKnpR3pCfGVv1GYwuND9V9j 2WisN7G37Lz7qOtvf8G/M1bkT3HNBx0HiS8ML8x2tHgyzvEBa4gbhzJFFNVc929whxly7fVPDKzV FVpzTWpnn4NjdSL9RscRV2DKXqnRrxroqrxDW5MctYt+tXKGgWxb1AqrbLrM2reUTNM2jMSTrb/Q lRI1jLiOg0ys+luWTn1xX09i8OV2bnDriDgpepAnwO2LQGBHHVKyrnwknpdEcNwkXWZlelXgFByw xegkqmjx7QbXWcUgIlpVlF0CLYUCak5my8/lj7VDXXWphwo6Bv/PqlgZVOiA1O0/HuPYBLqs2cNU jDDvnoSGkATqr5rOBBvEc5HgKX7a4R2uc7aNhhT3Rjj8iiKCA/omZrQACxH67pxiFfco8AoFpVW1 R19UsTZGqAc5PYDXgKZruVfurdJ18I0ctuw5ACRyTEDqu8RWsHQR4UmgNNn1uuMqWSX8lBajKaOB A20C0d69DRlBCpOcq2PJouzfvYKkOk2H2T7KtkSXdhwRzBZrPGIYz0msFKTREb3bIqT5epySU/NB 376pcp2xJZPsaiTo75WiJ7jCaYsuFXKW19AVapOe96Ztd1fyCQsijBWW8Kc1f8Z24/vAacBZfb+k 2pkij+k26NxLbxIY84CIV8Ka/lttVPL9o2No+phKV12LYwIHZg73t8MpECydBHMHVnC5kBfVuvxn cN2aUxfyPnrcwEz2cragwxVYjhJFUe7H1e8n6VSicHpv0RaCCzHcIdV3FF4aNyFonxA2/aafvt5s QcL+oDQmQ0v4rQ0U4TaBOw6VsGPDP9jpKllbAsZvafMLS/rsyLsZMMbUindcJ82kXg1VjntwbyTq lka+fYyApmF7ptvyZ5N/3iAcLLPwwy5ZBq1fgQtyw/iCYOxN/oaq0A19qEgUnUTUQPhPlShpR3ml /eHmp8oHsTUBV3EbLajFqvwXIiRCxfEj0f6YPp4Bw9aip18rYo/lB9g9yCU6Hi/u2QB3o/E35B0O cYEdUx6lcDA95DdRoiVR5AnEdgHaEXUmDrx2PfBiswdazCrKJp6vB6smUERBtHRjHIiMa79Nb3NV 9ie2EpR64woMDfyCQeOTnoA8L8egsPlJrbWf43W+C/QZ+iV/JaUVYQ5bQYr+a3IfdpgoZLHItgro IdHlOiMBvWxdnZ/uNmVZOecabaMUMcXZuMD8wlOsBBk9rqmiMxgHfHBJ5ItYS7G1XGz181aicbI8 myHuKaWTfXfhjKvwhruHTokl7R0/yC4b4KN+SlZbFX5JS5OeiuJufytSjdgdiBYLQKfa6nLEXMv9 XaBSRcn7wUvWDLlRGRf2RC3siWIzysbmuBraXFq9sYg0x1I8pGu1qohEiZ20qKDJn59cJba7tTq6 5rkfN/dLPN+nonc4FYIoddpPVVtz5P8kfcYvvLouvtrceeN7jk3pJIL3IsdyyVxpICtYVARUxtJK FSiPdQuZpEkMffzp99F0LAB0X3QHfIWoeXy6lyB12zxrydSzGPq5zu4E3NZSghFfcLJOz83sFVgU x6Fwe0nVuohWrjeHiE8Wn5jrVAOkuGxWP8GKSEPYhLdJ2YTB9t17rh4W8QhIwppV+3sdC52+mpc4 9qiTFlLYZPlKnMBoeF3YXvgaGxPdso1+lM0FAGdUH8sCAwNy63fBhoYh0j+qe2H/nA0FqqySLcBa HiATH9mtRVYDVY54x+NlIQ8v+/HvmmyY2xkBRUwRev3jjmBrAgX6L4bpvl6yCr0vnRugfPZ/yLBQ nYMMzz7/BECFbWTnuPWh1SKOGqy8d+xaAE5dL40/aI4B2XOBDp0hTZgU0lQbd1g5Du0MWNFP8mi2 I9/8+VFzQ3QvMCYjotLQT0XALRIMRij/8acrNAmUN1IR3C7NzaFNBtexYj9scJOLgm351JWgHG7h CJICI3R1eZvvYrI0n6GAOfjSt7ilWSve9ChVW0QjrNHNSoSuJ40jJZy3HyL4NL8hRrZ5aFCZoIRg xAH1vT7wGBkytVXqL74DELEfFlKZ/QysXLtHm6QcfP+9ALrOvR19RcNk442GctkBVLwXhvlVZZoX 2XIBBIfKEBRYsUDgm0XYdVsJYRZXGvTY/wAo99TYM0ekCjls0dtjSWDLqyBoVj07B6aCzrHF+5d+ EROh2WHM75Fex6OH8eFr4glkhgeTIh67jx5HtWMtrWgkf/X+G2fzd6EjI6zeyKf+pkzrQC+6P0z5 XWcfiOawVHDLGwGASpn4kMmREASnaKe/2mT7DXmLWuUNgqb5Kq2FIUWcYX0a3/J5870jws3hPpvY SSUvodRxHWC6GEa7Bm9hfdS/4oecZoQjxAghIFfZGO2bHziPjD5e+pbhnEp28Pmxuu2uSqWzK10m /XAVeU/jOiCfk6WTrshwOGHSkUMHtdLM+A0my28RnuANO3zATSQ4+U77K1SAPNWQsRtMk+aECDjr 1qPXQbLetJ8brAMlGZYH32ShXJCgJD8/qCsNTqLYAqlvuByprl/anTFek/sXBivKADcPTeVIeE6D 770fd7AwWOKyreZPGLDheLFZkm+5/Inn32meK1av4fDLvqTM7yHjV+ThngkcLyzUnB8rpq5s3SB+ J/F4dP/bwWtFISw5QEBVqOsMVutfWSXfAw6mUNAMchWJ9B/Gpjr92FL2rGrkJh3HCK82m4jCDXxA TBGtpTsOa4K7oenZ3wOlg4rJyyVRoR/nlHbsXtiVRgPojBL7XlIYtzka5gq99mmjOlkdjiywfk13 Em5aks/9qELihze4H9KA/bosftP0J+Xdb/Ae7yqrzawGgQuJy0/vsMLHdd+tJ7bhjoBknmATe6SI ys3vybcTtBOqJCCsk3Q0kRvWTp7XmZht7pIOsYNrpxttrI/UB+FCTFjzPcuNYK6vBxrDQDD6iW/d QBVyjByoR0xd4U4nkq6wCf9oqEkaicnbT5QzAdISxJDkNLo2WSQMSC7TrUcLERa8g+mfTVs7lE7P cahB9EuYr/SQ34gsOEfT4MhkucCYuurhB8v4pT45A6/aIbn2/BaWEDoQ+CgfhIKEFIDTgKVMOhDp OygaBCbxeozVrG2a5I4fsGbdjL7akrmGQfUSZjMY4ZgcEporDdtJGg8Qq0Z1yJQFWO7S9La2WHDw kinVTl6mPJDaoB/Mvr/AzM03HzkAigRvXJppuEVqdn373C1AA6AhFYwtVv4qOPbnNYRrdwsNdn4/ euPpt2O9sjqpyRIu/9BjpagrFUHeZOVGgExAfKhq0zc+pW0S/hQ6oqdlGTpcGBLOPZvZyKA+udIS edc6wW/0o1zSsPv2IY2RSn23z42yinQ8NsxWVksC8D7jtUklAiGxRLjC2bPB7eJuZjphGO9LtsyU SCT83wr9br2PXjkqYv0NxIY4+q1LavG2DnpCpXmjD8rQsZMoQdc2rZG8NNqNhDGdxSfmc0qT1RE9 4G8/2s6d7rcReiPtRdvjVk6B7wHRQWmUX3oMX2yJDo8OhlPCKlgLPNycE11XSitbMaZ3vaCshUqa 376iUVS+W08VGh14in9wNLhMAvEVkWodZ+uBGiLcoraoayd/PN0t5KKga1EWmtqEPevWtgJNvdQv 4sfoyD7YnkdT/AgcD6tZ6CtaACknkrXjNxglhRZx4pgi7EbS6xUvL4WRE0bqcPs5O634tB/Ly8hf 1o9j0Py18smIHI3aO3yEr6UfrFMWESBw+DsQZEpIDsvtLN92/H9mojlHpKc+s8Ba9ps9Qlsf70lf 9dLsi9JUDhS9ATE0M2qcojUjlM/VWXdC/TJEylEPsoWm+uwgkVqykubEhaEO7yvZxowjyreUBMMZ oAThEl+3Cgp1V+mUkjnlkVWGBRokKPHaM7k3pFAoJM5jTN0pnmgorc5rv/AZqE3/Hzj9U69sbUSK Xgcg634GKqdA6116qCiXuOrF33rHBSZsVbqvHZmBg0LlKozm/lQna2E2ts8qeTl3gIlF4wBltReS 20ewFB+koL/VOBo/7uFGnA+kZLHUtUqy5qUxBZkg+78g0DmbR4XEosk+ieVqKIUT+THCDn9bZMlz csILtSNFcnH5pbg6RiZGptUTt9X5Y01Q+zsk/dAaUtqaAOERVdS/FsGOnOYEQKe4mIPREfPDFldJ DLxburJOm13kCbeuTxgt191bbtejxkQZ77oYUL+prSp00WrIrUiXH5VQ6LPrIY1agOUuO6/O9Pw7 R2XUOtUeUQiHkM78ttk26i4yDES4Oy2L9ApwNiVXUYewkVOcP+h2DyDxZRj5hBTJoZ2WUSjS70/w nDh8sR48eqn1wMeRs4cGsMqI3P7d1exL1U5iDfOEXltgHihG/kqM4rbtQSwZxq0u1RkJKK1FacEE Xz+lWFEBEV9HGIFDudM9yBsoQ47bsLsz+QzXu/tVnvS9ljJ6Bisti7CU7e1qsqvy25zhjtby4ZbF C80KIG4/sSFTnB7UuSoi9b1kF1mpSay4uZmebFq7OnCt9V6Cco4f6HQyWl3mpDP8U8RRXWhz2p3a 3+7JDwHHY+DcbiH3e2WTlveTKYUYsE//MtnboUj0vTgf9F1Dh5ekdMC2l1PFaP96uQuEazqEfRsn SKsB1OtzBJzfV7qSy6POOR8d703g4mxOuD5ggN+lAGYFdmCDqjn7132FLBmac7QCjXXqglWYEh/g PzGgi//ahqJ8/L+adSEdeCC55nmD8GyrX0GUGtRqp08ZQzhspOqqVsGx1XNwFE+nW0OXd9PtehOZ Zr6CtFmGPaB2XPClNUdelYQSicH3+heglTIcNWIv7Zeqienla0DhGD/zZ5FkrBIRC5omYluafUFO QM9QRplcx8OKJw4eov8Yu9+DDOBJTO4WbyoaYS0etHtylBJ4jJ6I62iWt5VbrJJ1mDWBuh/6n4bG SDqWhfdQH9QfLXRTVbKdW925qrRp8R+a8bPpSbA/1qz1OMb+Ekt1pEKAda86SlPXUQDaNS7Zqx7G j1kNDuNq/g1QCUj7Rw1f0Wfn7vUblq3o+Etom1SRdiqKpdUUkf8iACGYLX6uQm7WkhEHUwDMW9bT Hk7DwuMDl9+4dY7O1vABGZJykyoZ2TpH4x9UVbyhnF+tdpG4auZnThZrflyLTof+G603FzmjsPOr S1k2Y2CpboRsAGxsXSzzC+0veVMT9NVTaem3wWz700Dx4HJFyPL6fAmpfBMGa286JmasUfp8FTrg c0nLrOiLEHVUhdYx2NkKpx3CdZadslxSC1+RthCG1bSRvXLwjUZVmiCHTqiLCxxGUTYaApcnVDi3 FxjwrgzJhEk42wtvmeSSJWv9i1RL3R89B6KF3EirYYEgrDlTT/fSu7YSPAgZ4R5VCegE56dNAAyp uURs5tlsyYKbgbs5BofJqiVZHtXlgodkcvns4dt3C8prBZWGIyJlCxSdzsn81LRCFDMt57j7jbh8 jx2UUKY+Kb6dJC+bAb4mY6z3EnHPIExOvrh26LYRWtRvESX83tD/Nf6y+n6zmaB/+qPTrGwQQiND yTPrzXzbh8UVJ51CwPlrMnBXsgUDL6g/6oCQL4zrzB1AD+hPrz/hG4v1xG+GkGF4KRKeorL9U5z5 ZBXkg+fFwH3h44Up4jsPfvpkdCeqIxPvpbrAdcRKuPhgUFqy2bjtao1rbwqVUNipP7bmPCYyuYQx em7PJaHA7mgEt84/eTTt4ynoHD+yRg41YBU/px+0s2uO4pUPEjG2Yehqy5MlG3ipDFt1w0glCT9X P+uQaYSFGEYcqTHAuaVgQgIzSYHDaKmhkxjF9afI0OByafCNvW33Bc7Us+GkkyusfTTVVvSgFoVq 4DwbRyhbXsTPrJm9PildRgETdpW2GCH1CMoRY7qKsOBq6x4gG0JyfRnl/94aRBDgmIgsaQckbVVi J8DKWgdMj55Khgu/4tTdBhzrGIERApbKRVXgv2eZOGVPxOR49R2tVTg0rMkICd4MmCyeTHKPfU7C pDRHmHnGd/1b1UUvi8ZE3ENJWmdTK/kGhoEoiaspJ0Nyif04tddV+JBEEVy4jjSNf/n0X/YnV4g3 CQA00JaiM+UB9z8E3UwbKucarh6zcrjsG4Pt8LaeMQk4+rrxveg5fSbalTc3UhWt+gr8r1hy8RTT EX7LFDtX6ZKGPIbasyg6SpfVej8/P26bktvuuSItJoaiwWbwxMdv8DZcnALDCc/wKZZab6ky67kD /M+wl33CSk8YBxrcNiDow4ro7egthfEBFWQT+ZfLOWERvdAOW0LpPEVQfOmut01hju3DgKvB+kSP MIvbEt+jtrz1o2AfTpkomrZfVVZHVHZD16ZbpORGYe/RN72jpq3Et7OKbz/rVRQnboA27hGiGLum 6InrYRVBzSfbY/u88LBvWsiuF7VO/YvBkFr/gPQ8HHmb+id3LvajFwXbcHGQ/CIWgGgAwjpQkchD BAr6UxlXRZNkclkLVpYOOJNG8sE7xYWnlPpFWWVnHuPgFtPPyrfLVDU6TbT0ES80mwycSXgDoTtA S4AkFVyIszyuMVHj5tX+t/ZYqyCgpYJdZ8PmS0paEINRFQEXN36EvI7G6Hs8Q77lCp4HCN7Igckd 1NRAbeuRFW585yZoQYp1SqPc6yn9owwOBXkSZXSkxACYwy72/t8e0iCF5wl59lPSEgSQjx9oOmsE eeY8qtLA+UCrcL9L3e+/WH/CJW6Gem4igtuzqvcMdUC2dGBLauWEw2rwdqs8NSlnU60Xamh9Tj3r a+L2BsLqlFIXUDKt/+a0atyY3sOoO0DvrXsb/lXEctIYGuheN0SlVkB9GWqnRZvCcP5XDLrU62i+ pWzAU3HH8JRR+K8zxwn8cxgbz7LxM4ETEtS3yKb+ExhuZdrD/YK1w5HWrVYgnB/nznIaUqSMt/lK nXgPsYZ98HdUQzaZyIUOGQBCdb449gAgjtvD879nytKYQ2OlxONRKW9bg2TbCxSV+5lfbNlbsA1z fjxHvMxFKgatt27JjSfaIGMRMHwGi9ckD6eKY7GvYZEG+tb2hO3Xr2POMQvjVvHdv6vynwNf/MmK 9hecaYyiWR3doVcKW8WpJA6aWHBhb23cptpnOeUCaCL+gjuX8U3pdVNpgGkc4+Xt2FnexWgmQcMl NsEtV22cAefXmRz4mERBuQfsJcQeWVGq3TAMhP10ujj3BLzDz9o2g6yLLm5B/c++73M22irJzQ6A D97xeuv/vFCsZV4d5zSssT3ByX6hf4cRvRlN2lDZ+0/RePdjZjifrgWQoqGA+Khk3xn1I40DW5Ze RFFor4LJ5xOvaeuCgXhdfvuWt2hHwe5Vlu0a3BdpUpiLNzWacvQMaU/IT+Zs24eGcG0ZnZyeh/Ot f30sMfh3srTmUMXJ0cyowUmhedC90zUCJUI01spQ8vKnYw7hjBOK8ENfLZMNcQUiJQGC0dhE5XFT XvY4LtHcpZBwCSS5GG8oPjMW3HuryIA8MxXa7Sq07ARA/hnTlmhLPe/i0o3wfYKCmsQ6yTdidgmv x572TkfleUbwOnnin+qMxrWcDMNUKdeP0kf8hwa4iBvED+88XVGw+nKvRcC1FrVKQy/rrKM4pb13 4gu0huMti/VAqrEGZZ9JslS+I8DV7ggzA2BMNYTmu1I6+PfMBqWFcG8RBSzvmuTNbTkVcfuy1eT1 PeTjtXYBP0AcTFTNm7Buvz9tvYwLX/a3QYtlzYtQT6r6Q87EgIU5ALurF8aP8PowRuL2kkMVrcW1 Hd44VPFVzYM611fGvG5cH5skE4kMeUw1+5KbBUNDPEp91z6FRQpWxYAs7nmPPxS67XTBIXlqA76B kdfjZJ1boV6FBp8MF5AZ59txQBZuvg9rfZHy2k4wZf7XacLDSun1V/cFnMoZ0CI5NYB61yyj3zFE dRY5TLE1rbg54EAQFWDk2R98n0Pg0XmRHv8TwUKcIVCJ2ccixFEul4cHm/PuDfzAwjH9HHoDKsKo oBtIOwwQEQURDApzHUkimU4HpTXFg7IhkgE9bqOCiinZ+yE7b6zveV0xk4vnnivZwuA7GuOu2hwK gHfltIHnHkFwN5gQdF4pWhEZozf73O4WuwZZM6cflQ8u+y5l+p7ZpUYt/3jTq4fzZQoKlIWdp8Yi p5O2Cg+oWqqcifXW5vwkaCV4pAHictOSa+4mYAqyKQOe5lCJUSUN15JWqZUdVYsRV98bV5Odacm6 SXapa0c54sMVjTJb/6IUbtX1AhwhKEfEdHIrupA2K74Aakij6L1iWBwRGnaGbAIISD5Zuhei4IHn wHb/T9Lmpikt4kf6DqUuFS2wWLBOXi6/bBpnoaYQihpoJWduUzFn8nqqw3zeQIRIH3o8yZ5U4Sm8 9dFc4al/F5FGwHd4d5vLoQbRFAVnSq71RJG2+8QnUNKaHyrC/8YfoDiUxsBJwU9gTTirw69AM+T5 ZjHnBxRNZ//z9aRxfm3zTH25SyOdtomKyNO2CoIgz10I3jbMg+eUYfwm+AsZJxwJ7Y4xU5L1pbmE +zp9ByAlEnrwHjr1h1HiaG2lpirYl6bhzSYrjjXKI7VkJnV8ZtlX7SrUU+WFRxC5LV65/0Emyp7Q 5pims3xtyH54yob1xbDYNF6wAvqEqpfrRU52jHBPgH1Bo2e/rRKY/ObTm5mrk87IlH82W3JnD/Mk ZErbiCFLNI/2vPC3zu6qCUS85GstzjEk/+ORywPyILadf4bC3okhXsj8ij8Am5kX50aGI6N0f6cQ r1LXwEYTWvvDHmT31VSi5MFWG1GEbC7QBL2ibPrLPEo6kMzwAqaAhXJYGxx02MgOP5+pycOOivgM 7LykqZU9X9NPNkIBBd3GIQK5CZIpcAfCaRDM2+cik8C449u++oopdLT8kIDknufGYMdxLz0pW0c5 OWlL3HqXKzi+dQ0eGf3P2mY6F6ha6VlfAJRnbPmDi8brt1U631ENmNoctg2uqrwcVjq05L+GcLCl L8iSZIg7U/sWxto3325dpSMU9blnmFvldnyuU8fmPVvSSTVtqnvZa+Y0qJ56Aytzc3gb/PHYeBAh x37QHaThF+0Adumf12ausC4ysd5IJpztX78pBqT25/xEcdHYCTjn3pf+r0T7rr/Xxb8LNcC9WYAX O+zczGlIkg/4mTjFx7t47ZD+igGhtpe9XmYVpgM9DEYs3AM6GzDHRJng/O1KxNUXHM0QvrcWIaqI Ev8tFu6jNA3a6v7kPA9YeDjiK2C3prdJQENM4A5RFChzuaB2iV90zb/jCkgEiztTmdcifLU3vO3R DLmy6B2NpQqcMQVI5/aKxobMzG3t0qqUCNIHoF8mXcko6NzV1FT3kr2gWnXhFYb+27rry/XxaU07 AkazCxQuUHFn7XlqCvjxDR6XdBvSi0ofeqJdQ1i8ooIN1h7WsK/lgnR4WijyGeeWLl0dKw8AKJn1 sSxZHiNy5DNXvkedd4pXZwKUAtDNsb7A67hdv4iOFcMFBHoddUut1X39RdMDL8yB/qfMvbX4xc4C pIBJ+87WDQqH+laht2722eCah5wwYssml2yoR5k8guBovcf42nrUlkTyvQ0Ox9oLxwSyxkp6NVd2 H+ajKZU7f7yCCFNF6cz3yv5TsVD6/xKjurFxPnbX976dUsTIyj+ZiKNVAzfSi7C5Bqk6Zvltq137 +NbOs5vnS5ZdPa3JtGGqXsrKPfRFIvtrw4iLK91l1HXojzDdej2d74DUk1UK8LBh7K8b3+S09GpM 21wxG3ZLtiT3TD1vSBZpXGTGI0l8IaebJvOusSHY+1M1nJycyg/he2Qh683521Qxw710x33+qOt2 skz/9VGftnVWyYiZpjbGbQCgvvrEyeu/ZtxEvUkkpnKadq0j6ZcE5k1z4NBIRiIPRO6PFRk3EoRv 00KQTpzkq9niE4p3LIOym0q4ameP89XbnPMRZtFZJRQMkxcc0RxmxhtN4L9yflHRhQZyicKKcI6m GSatS6OngqEeYiCjjCCmKpj/cSvQAsdU65nA29UrAbBWxDCqthB2Xg6kNS0B/c4MtVJBxMDCDXL5 rR3D2jxjYw8P84XcRyuoDGmDAYfCgsMUePZyHllqcrjX4jbBwVBQPggwvTxrDlGie7e3Sw62ujgR 3/FDEiAtM5jUaCsmNwxWx3EwxZa+HfRDns6m0cOozNstgEVwmkwuN8nbJeIRem6uz57mXmFhKuDA zHPiRGhTSGF0sFubwsJTXQBrKUwpe8HwhLs6iqkdnXPofIJyqA+ZOCGaxyvESz3htVh8RnzgdTUY BcUbKxRhM4YPR+Kn8ijhlnDvfx+g6OJXNgSOTcXRIW9mmqr/ydGksoLXzLay/3NpebgTHpYNaxHz BwQ1fD5TrRCZn3fAZzGtJL+NMTt17DLlK6rW6EHbrPPk2at3JksGzQtL1+TPBOBAONupaUluzrRs ARsVwGXG9ZcVXsBhrr1EWKk+8zhVBM8pFcp349bT0I+0oxR/AjFi1flQzALbLH4gBy58ST2TOe9U pxLTGWSyyw0agPoMqaH9S3GxVEYTVhz2jbj9VINIvviM6Iyj7cNr60GAguizO/NeykLqGNzn85sn BC8s9s3XR53mV6v7RCPsfy99oNqBX8axL6ExOydH6yR9DUSoPJ7WqW1SjnuLOFtCwnIx3GTqe0hn PqTzsOt5uafexlsgPj+8YArJyhplq2bFqWl2uX9kOEgN5o8XDXHOIVTSZsdqsX/XE7z0oc8n8O9V l2hbwn6NN8Jq+CIUOjwEjvCBGQuhku1wivBhDCJRzopbstLir2OLLX5d `protect end_protected

mit

95f62ef4a2158c73890aec60bd92daa8

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_4_CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 2; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

b1e1ad1e8b6f4cd7100178c94a0b473b

wltr/cern-fgclite

critical_fpga/src/rtl/cf/nf/nf_tx_registers.vhd

------------------------------------------------------------------------------- --! @file nf_tx_registers.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-07-23 --! @brief NanoFIP transmitter registers. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.nf_pkg.all; --! @brief Entity declaration of nf_tx_registers --! @details --! FGClite is sending 60 bytes of status registers as part of it's response --! to the gateway. entity nf_tx_registers is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name NanoFIP read interface --! @{ --! Read enable rd_en_i : in std_ulogic; --! Address addr_i : in std_ulogic_vector(5 downto 0); --! Data data_o : out std_ulogic_vector(7 downto 0); --! Data enable data_en_o : out std_ulogic; --! @} --! @name Registers --! @{ --! FGClite status status_i : in nf_status_t); --! @} end entity nf_tx_registers; --! RTL implementation of nf_tx_registers architecture rtl of nf_tx_registers is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ type reg_t is array (0 to 2**addr_i'length - 1) of std_ulogic_vector(data_o'range); --! @} --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal reg : reg_t; signal data : std_ulogic_vector(data_o'range); signal data_en : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- data_o <= data; data_en_o <= data_en; --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin reg <= (others => (others => '0')); data <= (others => '0'); data_en <= '0'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else --Defaults data_en <= '0'; if rd_en_i = '1' then data <= reg(to_integer(unsigned(addr_i))); data_en <= '1'; end if; if status_i.adc_acc_vs_0_en = '1' then reg(0) <= status_i.adc_acc_vs_0(7 downto 0); reg(1) <= status_i.adc_acc_vs_0(15 downto 8); reg(2) <= status_i.adc_acc_vs_0(23 downto 16); reg(3) <= status_i.adc_acc_vs_0(31 downto 24); end if; if status_i.adc_acc_vs_1_en = '1' then reg(4) <= status_i.adc_acc_vs_1(7 downto 0); reg(5) <= status_i.adc_acc_vs_1(15 downto 8); reg(6) <= status_i.adc_acc_vs_1(23 downto 16); reg(7) <= status_i.adc_acc_vs_1(31 downto 24); end if; if status_i.adc_acc_ia_0_en = '1' then reg(8) <= status_i.adc_acc_ia_0(7 downto 0); reg(9) <= status_i.adc_acc_ia_0(15 downto 8); reg(10) <= status_i.adc_acc_ia_0(23 downto 16); reg(11) <= status_i.adc_acc_ia_0(31 downto 24); end if; if status_i.adc_acc_ia_1_en = '1' then reg(12) <= status_i.adc_acc_ia_1(7 downto 0); reg(13) <= status_i.adc_acc_ia_1(15 downto 8); reg(14) <= status_i.adc_acc_ia_1(23 downto 16); reg(15) <= status_i.adc_acc_ia_1(31 downto 24); end if; if status_i.adc_acc_ib_0_en = '1' then reg(16) <= status_i.adc_acc_ib_0(7 downto 0); reg(17) <= status_i.adc_acc_ib_0(15 downto 8); reg(18) <= status_i.adc_acc_ib_0(23 downto 16); reg(19) <= status_i.adc_acc_ib_0(31 downto 24); end if; if status_i.adc_acc_ib_1_en = '1' then reg(20) <= status_i.adc_acc_ib_1(7 downto 0); reg(21) <= status_i.adc_acc_ib_1(15 downto 8); reg(22) <= status_i.adc_acc_ib_1(23 downto 16); reg(23) <= status_i.adc_acc_ib_1(31 downto 24); end if; if status_i.dim_a_trig_lat_en = '1' then reg(24) <= status_i.dim_a_trig_lat(7 downto 0); reg(25) <= status_i.dim_a_trig_lat(15 downto 8); end if; if status_i.dim_a_trig_unl_en = '1' then reg(26) <= status_i.dim_a_trig_unl(7 downto 0); reg(27) <= status_i.dim_a_trig_unl(15 downto 8); end if; if status_i.dim_a1_ana_0_en = '1' then reg(28) <= status_i.dim_a1_ana_0(7 downto 0); reg(29) <= status_i.dim_a1_ana_0(15 downto 8); end if; if status_i.dim_a1_ana_1_en = '1' then reg(30) <= status_i.dim_a1_ana_1(7 downto 0); reg(31) <= status_i.dim_a1_ana_1(15 downto 8); end if; if status_i.dim_a1_ana_2_en = '1' then reg(32) <= status_i.dim_a1_ana_2(7 downto 0); reg(33) <= status_i.dim_a1_ana_2(15 downto 8); end if; if status_i.dim_a1_ana_3_en = '1' then reg(34) <= status_i.dim_a1_ana_3(7 downto 0); reg(35) <= status_i.dim_a1_ana_3(15 downto 8); end if; if status_i.cycle_period_en = '1' then reg(36) <= status_i.cycle_period(7 downto 0); reg(37) <= status_i.cycle_period(15 downto 8); reg(38) <= status_i.cycle_period(23 downto 16); reg(39) <= status_i.cycle_period(31 downto 24); end if; if status_i.version_cfnf_en = '1' then reg(40) <= status_i.version_cfnf(7 downto 0); end if; if status_i.version_xfpf_en = '1' then reg(41) <= status_i.version_xfpf(7 downto 0); end if; if status_i.adc_log_idx_en = '1' then reg(42) <= status_i.adc_log_idx(7 downto 0); reg(43) <= status_i.adc_log_idx(15 downto 8); end if; if status_i.dim_log_idx_en = '1' then reg(44) <= status_i.dim_log_idx(7 downto 0); reg(45) <= status_i.dim_log_idx(15 downto 8); end if; if status_i.vs_dig_in_en = '1' then reg(46) <= status_i.vs_dig_in(7 downto 0); reg(47) <= status_i.vs_dig_in(15 downto 8); end if; if status_i.vs_dig_out_en = '1' then reg(48) <= status_i.vs_dig_out; end if; if status_i.seu_count_en = '1' then reg(49) <= status_i.seu_count; end if; if status_i.fgc_status_en = '1' then reg(50) <= status_i.fgc_status(7 downto 0); reg(51) <= status_i.fgc_status(15 downto 8); end if; if status_i.backplane_en = '1' then reg(52) <= status_i.backplane; end if; if status_i.serial_data_en = '1' then reg(53 + to_integer(unsigned(status_i.serial_num))) <= status_i.serial_data; end if; end if; end if; end process regs; end architecture rtl;

mit

36bf44d5698aad2a6ccb6b1b404cb241

malkadi/FGPU

RTL/CU_scheduler.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity CU_scheduler is --- {{{ port( clk, nrst : in std_logic; -- output status signals wf_active : out std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); -- for Work-Group Dispatcher sch_rqst : in std_logic; -- high to begin scheduling a new WG sch_ack : out std_logic := '0'; -- high while scheduling a new WG sch_rqst_n_wfs_m1 : in unsigned(N_WF_CU_W-1 downto 0); -- # WFs within a WG wg_info : in unsigned(DATA_W-1 downto 0); -- for instruction fetching cram_rdAddr : out unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); cram_rdAddr_conf : in unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); cram_rdData : in std_logic_vector(DATA_W-1 downto 0); cram_rqst : out std_logic := '0'; start_addr : in unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); -- branch handling wf_is_branching : in std_logic_vector(N_WF_CU-1 downto 0); -- level 18. alu_branch : in std_logic_vector(CV_SIZE-1 downto 0); -- level 18. alu_en : in std_logic_vector(CV_SIZE-1 downto 0); -- level 18. -- for RunTime Memory rtm_wrAddr_cv : out unsigned(N_WF_CU_W+2-1 downto 0) := (others => '0'); rtm_wrData_cv : out unsigned(DATA_W-1 downto 0) := (others => '0'); rtm_we_cv : out std_logic := '0'; gmem_finish : in std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); -- with the Compute Vector instr : out std_logic_vector(DATA_W-1 downto 0) := (others => '0'); -- level -1. wf_indx_in_wg : out natural range 0 to N_WF_CU-1; -- level -1. wf_indx_in_CU : out natural range 0 to N_WF_CU-1; -- level -1. alu_en_divStack : out std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- level 2. phase : out unsigned(PHASE_W-1 downto 0) := (others=>'0') -- level -1. ); attribute max_fanout of wf_indx_in_CU : signal is 10; end CU_scheduler; -- }}} architecture Behavioral of CU_scheduler is -- signal definitions -----------------------------------------------------------------------------------{{{ -- internal signals assignments --------------------------------------------------------------------------{{{ signal wf_active_i : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal sch_ack_i : std_logic := '0'; signal cram_rdAddr_i : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal instr_i : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal phase_i : unsigned(PHASE_W-1 downto 0) := (others=>'0'); signal wf_indx_in_CU_i : natural range 0 to N_WF_CU-1 := 0; attribute max_fanout of phase_i : signal is 10; ---------------------------------------------------------------------------------------------------------}}} -- types & functions {{{ type wf_ctrl_state is ( idle, check_rdy, rdy, wait_for_selecting_PC, wait_pc_rdy, wait_gmem_finish, jumping, branching, read_PC_stack, scratchpad_load); type wf_ctrl_state_vec is array (N_WF_CU-1 downto 0) of wf_ctrl_state; signal st_wf, st_wf_n : wf_ctrl_state_vec := (others => idle); type CV_state_type is (idle, start_exec, select_PC, check_wf_rdy, read_inst, dly1, dly2, dly3 , select_instr); signal st_CV, st_CV_n : CV_state_type := idle; signal new_instr_found_n : std_logic := '0'; signal new_instr_found : std_logic := '0'; -- }}} -- workgroup indices {{{ signal wg_next_id, wg_next_id_n : unsigned(N_WF_CU_W-1 downto 0) := (others=>'0'); signal wg_offset_d0, wg_offset_d0_n : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal wg_offset_d1, wg_offset_d1_n : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal wg_offset_d2, wg_offset_d2_n : unsigned(DATA_W-1 downto 0) := (others=>'0'); type dx_offset_type is (write_d0, write_d1, write_d2); signal dx_offset_state : dx_offset_type := write_d0; signal dx_offset_state_n : dx_offset_type := write_d0; -- }}} -- global signals {{{ constant WF_WAIT_LEN : integer := max(FLOAT_IMPLEMENT*MAX_FPU_DELAY+11, 16); -- 16 is the normal delay for instruction that use the ALU -- 22 for float delay of 11 (fmul) -- 39 for float delay of 28 (fdiv & fsqrt) type wf_wait_vec_type is array (natural range <>) of std_logic_vector(WF_WAIT_LEN-1 downto 0); signal wf_wait_vec : wf_wait_vec_type(N_WF_CU-1 downto 0) := (others=>(others=>'0')); signal wf_wait_vec_alu_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_wait_vec_fpu_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal clear_wf_wait_vec : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_no_wait, wf_no_wait_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal clear_wf_wait_vec_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal sch_rqst_n_wfs_ltchd : integer range 0 to N_WF_CU := 0; signal sch_rqst_n_wfs_ltchd_n : integer range 0 to N_WF_CU := 0; type interface_fsm_stata_type is (free, reserve, write_wg_d0, write_wg_d1, write_wg_d2); signal st_WGD_intr, st_WGD_intr_n : interface_fsm_stata_type := free; signal wf_on_gmem, wf_reads_gmem : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_branches : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_scratchpad_ld : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_jump : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal instr_fpu : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal phase_n : unsigned(PHASE_W-1 downto 0) := (others=>'0'); signal rd_priority, rd_priority_n : std_logic := '0'; signal wf_sel_indx, wf_sel_indx_n : integer range 0 to N_WF_CU-1 := 0; signal pc_indx, pc_indx_n : integer range 0 to N_WF_CU-1 := 0; signal instr_n, instr_buf_out : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal PCs, PCs_n, PC_plus_branch_n : CRAM_ADDR_ARRAY(N_WF_CU-1 downto 0) := (others =>(others=>'0')); signal PC_plus_1_n, PC_plus_1 : CRAM_ADDR_ARRAY(N_WF_CU-1 downto 0) := (others =>(others=>'0')); signal wf_finish, wf_finish_n : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_alloc_indx : unsigned(N_WF_CU_W-1 downto 0) := (others => '0'); signal wf_alloc_indx_n : unsigned(N_WF_CU_W-1 downto 0) := (others => '0'); signal pc_rdy : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_rdy, wf_rdy_n : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_gmem_read_rdy : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_gmem_read_rdy_n : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_gmem_write_rdy : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_gmem_write_rdy_n : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal wf_branch_rdy_n, wf_branch_rdy : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal branch_in_executoin : std_logic := '0'; signal branch_in_executoin_vec : std_logic_vector(19 downto 0) := (others=>'0'); -- this signals prevents scheduling two branches successively signal branch_in_executoin_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal advance_pc, advance_pc_n : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); signal execute_n, execute : std_logic := '0'; signal pc_updated, pc_updated_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_retired : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_activate, wf_activate_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal sch_ack_n : std_logic := '0'; signal wf_active_n : std_logic_vector(N_WF_CU-1 downto 0) := (others => '0'); -- }}} -- coordinates {{{ type wf_indx_type is array (0 to N_WF_CU-1) of natural range 0 to N_WF_CU-1; signal wf_indx, wf_indx_n : wf_indx_type := (others => 0); signal allocated_wfs, allocated_wfs_n : natural range 0 to N_WF_CU := 0; -- }}} -- divergence fifos {{{ constant N_RECORDS_WF_W : integer := 3; signal branch_distance : branch_distance_vec(0 to N_WF_CU-1) := (others=>(others=>'0')); signal divStacks : alu_en_vec_type(0 to 2**(PHASE_W+N_RECORDS_WF_W+N_WF_CU_W)-1) := (others=>(others=>'0')); signal alu_branch_vec : alu_en_vec_type(7 downto 0) := (others=>(others=>'0')); signal alu_en_vec : alu_en_vec_type(7 downto 0) := (others=>(others=>'0')); signal alu_branch_latch : alu_en_vec_type(7 downto 0) := (others=>(others=>'0')); signal alu_en_latch : alu_en_vec_type(7 downto 0) := (others=>(others=>'0')); signal divStack_addrb : unsigned(PHASE_W+N_RECORDS_WF_W+N_WF_CU_W-1 downto 0) := (others=>'0'); signal divStack_addra : unsigned(PHASE_W+N_RECORDS_WF_W+N_WF_CU_W-1 downto 0) := (others=>'0'); signal divStack_addra_p0 : unsigned(PHASE_W+N_RECORDS_WF_W+N_WF_CU_W-1 downto 0) := (others=>'0'); signal divStack_addra_p0_n : unsigned(PHASE_W+N_RECORDS_WF_W+N_WF_CU_W-1 downto 0) := (others=>'0'); signal divStack_dia, divStack_dia_n : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); signal divStack_wea, divStack_wea_n : std_logic := '0'; signal divStack_dob, divStack_dob_n : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); signal phase_branch : unsigned(PHASE_W-1 downto 0) := (others=>'0'); signal n_branching_wfs : integer range 0 to WF_SIZE := 0; signal n_branching_wfs_d0 : integer range 0 to WF_SIZE := 0; signal n_not_branching_wfs : integer range 0 to WF_SIZE := 0; signal n_not_branching_wfs_d0 : integer range 0 to WF_SIZE := 0; signal branching_wf_index : integer range 0 to N_WF_CU-1 := 0; signal evaluate_divergance : std_logic := '0'; signal evaluate_divergance_d0 : std_logic := '0'; signal true_path, false_path : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal true_path_n, false_path_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); type active_record_indx_type is array (natural range <>) of unsigned(N_RECORDS_WF_W-1 downto 0); signal wf_active_record : active_record_indx_type(N_WF_CU-1 downto 0) := (others=>(others=>'0')); signal wf_active_record_inc_n : std_logic := '0'; signal wf_active_record_dec_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal write_two_records : std_logic := '0'; signal write_two_records_n : std_logic := '0'; type st_branch_type is (idle, write_true_path_in_divStack, dly_to_false, write_false_path_in_divStack, dly_to_true); signal st_branch, st_branch_n : st_branch_type := idle; signal go_true_and_false : std_logic := '0'; signal go_true_and_false_n : std_logic := '0'; signal wf_indx_in_CU_d0 : natural range 0 to N_WF_CU-1 := 0; signal active_record_indx : unsigned(N_RECORDS_WF_W-1 downto 0) := (others=>'0'); signal phase_d0 : unsigned(PHASE_W-1 downto 0) := (others=>'0'); -- PC_stack constant N_RECORDS_PC_STACK_W : integer := 4; type PC_stack_addr_type is array(natural range <>) of unsigned(N_RECORDS_PC_STACK_W-1 downto 0); signal PC_stack_addr : PC_stack_addr_type(N_WF_CU-1 downto 0) := (others=>(others=>'0')); signal PC_stack_pop : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal PC_stack_pop_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal PC_stack_pop_ack : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal PC_stack_pop_ack_p0 : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal PC_stack_pop_ack_p1 : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal PC_stack_push_branch : std_logic := '0'; signal PC_stack_push_branch_n : std_logic := '0'; signal PC_stack_push_not_branch : std_logic := '0'; signal PC_stack_push_branch_ack : std_logic := '0'; signal PC_stack_push_not_branch_ack : std_logic := '0'; signal PC_stack_push_not_branch_n : std_logic := '0'; signal PC_stack_push, PC_stack_push_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal PC_stack_push_ack : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal PC_stack : CRAM_ADDR_ARRAY(0 to 2**(N_RECORDS_PC_STACK_W+N_WF_CU_W)-1) := (others =>(others=>'0')); signal PC_stack_jump_entry : std_logic_vector(0 to 2**(N_RECORDS_PC_STACK_W+N_WF_CU_W)-1) := (others=>'0'); -- signal PC_stack_dummy_entry : std_logic_vector(0 to 2**(N_RECORDS_PC_STACK_W+N_WF_CU_W)-1) := (others=>'0'); -- signal PC_stack_dummy_entry_wrData : std_logic := '0'; -- signal PC_stack_dummy_entry_rdData_n : std_logic := '0'; -- signal PC_stack_dummy_entry_rdData : std_logic := '0'; signal PC_stack_jump_entry_wrData : std_logic := '0'; signal PC_stack_wrAddr : unsigned(N_RECORDS_PC_STACK_W+N_WF_CU_W-1 downto 0) := (others=>'0'); signal PC_stack_rdAddr : unsigned(N_RECORDS_PC_STACK_W+N_WF_CU_W-1 downto 0) := (others=>'0'); signal PC_stack_wrData : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal PC_stack_rdData : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal PC_stack_rdData_n : unsigned(CRAM_ADDR_W-1 downto 0) := (others=>'0'); signal PC_stack_jump_entry_rdData_n : std_logic := '0'; signal PC_stack_jump_entry_rdData : std_logic := '0'; signal PC_stack_we : std_logic := '0'; -- }}} ---------------------------------------------------------------------------------------------------------}}} begin -- internal signals assignments -------------------------------------------------------------------------------------------{{{ ---------------------------------------------------------------------------------------------------------{{{ wf_active <= wf_active_i; sch_ack <= sch_ack_i; cram_rdAddr <= cram_rdAddr_i; instr <= instr_i; phase <= phase_i; wf_indx_in_CU <= wf_indx_in_CU_i; assert(2**N_RECORDS_WF_W >= WF_SIZE_W) report "increase the number of records per WF" severity failure; ---------------------------------------------------------------------------------------------------------}}} ---------------------------------------------------------------------------------------------------------}}} -- instruction buffer -----------------------------------------------------------------------------------{{{ CU_instruction_dispatcher_inst: entity CU_instruction_dispatcher port map( clk => clk, nrst => nrst, cram_rdAddr => cram_rdAddr_i, cram_rdData => cram_rdData, cram_rqst => cram_rqst, cram_rdAddr_conf => cram_rdAddr_conf, PC_indx => pc_indx, instr => instr_buf_out, PCs => PCs, pc_rdy => pc_rdy, instr_gmem_op => wf_on_gmem, instr_scratchpad_ld => wf_scratchpad_ld, instr_gmem_read => wf_reads_gmem, instr_branch => wf_branches, instr_jump => instr_jump, instr_fpu => instr_fpu, wf_active => wf_active_i, pc_updated => pc_updated, branch_distance => branch_distance, wf_retired => wf_retired ); ---------------------------------------------------------------------------------------------------------}}} -- WG offset capture ----------------------------------------------------------------------------- {{{ -- trans process ----------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then wg_offset_d0 <= wg_offset_d0_n; wg_offset_d1 <= wg_offset_d1_n; wg_offset_d2 <= wg_offset_d2_n; if nrst = '0' then dx_offset_state <= write_d0; else dx_offset_state <= dx_offset_state_n; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- comb process -----------------------------------------------------------------------------------------{{{ process(dx_offset_state, wg_offset_d0, wg_offset_d1, wg_offset_d2, wg_info, sch_rqst) -- rtm_wrData_wg) begin -- when a sch_rqst for allocating a wg from the WGD; the WGD sends in the first 3 cycles the offsets of the -- corresponding wg. These will be latched here dx_offset_state_n <= dx_offset_state; wg_offset_d0_n <= wg_offset_d0; wg_offset_d1_n <= wg_offset_d1; wg_offset_d2_n <= wg_offset_d2; case dx_offset_state is when write_d0 => if sch_rqst = '1' then -- wg_offset_d0_n <= rtm_wrData_wg(DATA_W-1 downto 0); wg_offset_d0_n <= wg_info; dx_offset_state_n <= write_d1; end if; when write_d1 => -- wg_offset_d1_n <= rtm_wrData_wg(DATA_W-1 downto 0); wg_offset_d1_n <= wg_info; dx_offset_state_n <= write_d2; when write_d2 => -- wg_offset_d2_n <= rtm_wrData_wg(DATA_W-1 downto 0); wg_offset_d2_n <= wg_info; dx_offset_state_n <= write_d0; end case; end process; ---------------------------------------------------------------------------------------------------------}}} ------------------------------------------------------------------------------------------------------}}} -- divergence fifos -------------------------------------------------------------------------------------{{{ -- divStack -------------------------------------------------------------------------------------------{{{ -- A side: WF Scheduler -- B side: CV process(clk) begin if rising_edge(clk) then divStack_dob_n <= divStacks(to_integer(divStack_addrb)); -- @ 1. divStack_dob <= divStack_dob_n; -- @ 2. if divStack_wea = '1' then divStacks(to_integer(divStack_addra)) <= divStack_dia; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- divStack CV side --------------------------------------------------------------------------------------{{{ alu_en_divStack <= divStack_dob; -- level 2. divStack_addrb(PHASE_W-1 downto 0) <= phase_d0; -- level 0. divStack_addrb(PHASE_W+N_RECORDS_WF_W-1 downto PHASE_W) <= active_record_indx; -- level 0. divStack_addrb(PHASE_W+N_WF_CU_W+N_RECORDS_WF_W-1 downto PHASE_W+N_RECORDS_WF_W) <= to_unsigned(wf_indx_in_CU_d0, N_WF_CU_W); -- level 0. process(clk) begin if rising_edge(clk) then wf_indx_in_CU_d0 <= wf_indx_in_CU_i; -- @ 0 -- if phase_i = (phase_i'reverse_range => '0') then if execute = '1' then active_record_indx <= wf_active_record(wf_indx_in_CU_i); -- @ 0 -- the if check is necessary to avoid the case where the wf_adtive_record decrements while executing end if; phase_d0 <= phase_i; -- @ 0 end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- divStack WF Scheduler side ----------------------------------------------------------------------------{{{ -- divStack trnas process --------------------------------------------------------------------------------{{{ process(clk) variable n_not_branching, n_branching : integer range 0 to WF_SIZE := 0; begin if rising_edge(clk) then n_branching := 0; n_not_branching := 0; if wf_is_branching /= (wf_is_branching'reverse_range => '0') then -- level 18.->24. for i in 0 to CV_SIZE-1 loop if alu_en(i) = '1' then -- level 18.->24. if alu_branch(i) = '1' then -- level 18.->24. n_branching := n_branching + 1; else n_not_branching := n_not_branching + 1; end if; end if; end loop; end if; if phase_branch = (phase_branch'reverse_range => '0') then -- true in levels 18. & 26. n_branching_wfs <= n_branching; n_not_branching_wfs <= n_not_branching; else n_branching_wfs <= n_branching_wfs + n_branching; -- @ 26 is ready n_not_branching_wfs <= n_not_branching_wfs + n_not_branching; -- @ 26 is ready end if; evaluate_divergance <= '0'; if phase_branch = (phase_branch'reverse_range => '1') then -- level 25. evaluate_divergance <= '1'; -- @ 26. for i in 0 to N_WF_CU-1 loop if wf_is_branching(i) = '1' then -- level 25. (last clock cycle where wf_is_branching is set) branching_wf_index <= i; -- @ 26 end if; end loop; end if; n_branching_wfs_d0 <= n_branching_wfs; -- @ 27. n_not_branching_wfs_d0 <= n_not_branching_wfs; -- @ 27. evaluate_divergance_d0 <= evaluate_divergance; -- @ 27. alu_branch_vec(alu_branch_vec'high-1 downto 0) <= alu_branch_vec(alu_branch_vec'high downto 1); -- @ 20.->26. alu_branch_vec(alu_branch_vec'high) <= alu_branch; -- @ 19. alu_en_vec(alu_en_vec'high-1 downto 0) <= alu_en_vec(alu_en_vec'high downto 1); -- @ 20.->26. alu_en_vec(alu_en_vec'high) <= alu_en; -- @ 19. if evaluate_divergance = '1' then -- level 26. for i in 0 to PHASE_LEN-1 loop alu_branch_latch(i) <= alu_branch_vec(i); -- @ 27. alu_en_latch(i) <= alu_en_vec(i); -- @ 27. end loop; end if; if nrst = '0' then phase_branch <= (others=>'0'); branch_in_executoin <= '0'; else branch_in_executoin_vec(branch_in_executoin_vec'high) <= '0'; if branch_in_executoin_n /= (branch_in_executoin_n'reverse_range=>'0') then branch_in_executoin <= '1'; branch_in_executoin_vec(branch_in_executoin_vec'high) <= '1'; end if; branch_in_executoin_vec(branch_in_executoin_vec'high-1 downto 0) <= branch_in_executoin_vec(branch_in_executoin_vec'high downto 1); if branch_in_executoin_vec(0) = '1' then -- level 26. branch_in_executoin <= '0'; -- @ 27. end if; if wf_is_branching /= (wf_is_branching'reverse_range => '0') then -- level 18.->25. phase_branch <= phase_branch + 1; -- @ 25. it will be all ones end if; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- divStack trans process --------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then go_true_and_false <= go_true_and_false_n; divStack_wea <= divStack_wea_n; divStack_addra_p0 <= divStack_addra_p0_n; divStack_addra <= divStack_addra_p0; divStack_dia <= divStack_dia_n; false_path <= false_path_n; true_path <= true_path_n; PC_stack_push_branch <= PC_stack_push_branch_n; PC_stack_push_not_branch <= PC_stack_push_not_branch_n; if nrst = '0' then st_branch <= idle; wf_active_record <= (others=>(others=>'0')); write_two_records <= '0'; else st_branch <= st_branch_n; write_two_records <= write_two_records_n; if wf_active_record_inc_n = '1' then -- incrment commands come form the st_branch state machine when filling new requests wf_active_record(branching_wf_index) <= wf_active_record(branching_wf_index) + 1; end if; for i in 0 to N_WF_CU-1 loop if wf_active_record_dec_n(i) = '1' then -- decrment commands come from the st_wf state machines on RET instructions wf_active_record(i) <= wf_active_record(i) - 1; end if; end loop; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- divStack comb -----------------------------------------------------------------------------------------{{{ state_branch: process(st_branch, evaluate_divergance_d0, n_branching_wfs_d0, n_not_branching_wfs_d0, go_true_and_false, divStack_addra_p0, branching_wf_index, wf_active_record, alu_branch_latch, alu_en_latch, PC_stack_push_branch, PC_stack_push_not_branch, PC_stack_push_branch_ack, n_branching_wfs, PC_stack_push_not_branch_ack, write_two_records, evaluate_divergance, n_not_branching_wfs) begin -- {{{ st_branch_n <= st_branch; go_true_and_false_n <= go_true_and_false; divStack_wea_n <= '0'; divStack_addra_p0_n(PHASE_W-1 downto 0) <= (others=>'0'); divStack_addra_p0_n(PHASE_W+N_RECORDS_WF_W-1 downto PHASE_W) <= wf_active_record(branching_wf_index); divStack_addra_p0_n(PHASE_W+N_RECORDS_WF_W+N_WF_CU_W-1 downto PHASE_W+N_RECORDS_WF_W) <= to_unsigned(branching_wf_index, N_WF_CU_W); divStack_dia_n <= alu_branch_latch(to_integer(divStack_addra_p0(PHASE_W-1 downto 0))) or not alu_en_latch(to_integer(divStack_addra_p0(PHASE_W-1 downto 0))); true_path_n <= (others=>'0'); false_path_n <= (others=>'0'); PC_stack_push_branch_n <= PC_stack_push_branch; PC_stack_push_not_branch_n <= PC_stack_push_not_branch; write_two_records_n <= write_two_records; if PC_stack_push_branch_ack = '1' and write_two_records = '0' then PC_stack_push_branch_n <= '0'; end if; if PC_stack_push_not_branch_ack = '1' and write_two_records = '0' then PC_stack_push_not_branch_n <= '0'; end if; if PC_stack_push_branch_ack = '1' or PC_stack_push_not_branch_ack = '1' then write_two_records_n <= '0'; end if; wf_active_record_inc_n <= '0'; if evaluate_divergance = '1' and -- level 26. wf_active_record(branching_wf_index) = (0 to N_RECORDS_WF_W-1 => '0') and -- CHANGE (n_not_branching_wfs /= 0 and n_branching_wfs /= 0) then wf_active_record_inc_n <= '1'; -- increment the reocord if the current one is the first (all entries are zero) & a branch has been evaluated write_two_records_n <= '1'; end if; -- }}} case st_branch is when idle => -- {{{ go_true_and_false_n <= '0'; if evaluate_divergance_d0 = '1' then if n_branching_wfs_d0 /= 0 then if n_not_branching_wfs_d0 /= 0 then go_true_and_false_n <= '1'; if n_branching_wfs_d0 < n_not_branching_wfs_d0 then st_branch_n <= write_false_path_in_divStack; else st_branch_n <= write_true_path_in_divStack; end if; else true_path_n(branching_wf_index) <= '1'; end if; else false_path_n(branching_wf_index) <= '1'; end if; end if; -- }}} when write_true_path_in_divStack => -- {{{ divStack_wea_n <= '1'; divStack_addra_p0_n(PHASE_W-1 downto 0) <= divStack_addra_p0(PHASE_W-1 downto 0) + 1; divStack_dia_n <= not (alu_branch_latch(to_integer(divStack_addra_p0(PHASE_W-1 downto 0))) and alu_en_latch(to_integer(divStack_addra_p0(PHASE_W-1 downto 0)))); if divStack_addra_p0(PHASE_W-1 downto 0) = (0 to PHASE_W-1 => '1') then if go_true_and_false = '1' then wf_active_record_inc_n <= '1'; -- increments the record if another one has to be written st_branch_n <= dly_to_false; go_true_and_false_n <= '0'; PC_stack_push_branch_n <= '1'; else st_branch_n <= idle; true_path_n(branching_wf_index) <= '1'; end if; end if; -- }}} when dly_to_false => -- {{{ divStack_wea_n <= '0'; st_branch_n <= write_false_path_in_divStack; -- }}} when write_false_path_in_divStack => -- {{{ divStack_wea_n <= '1'; divStack_addra_p0_n(PHASE_W-1 downto 0) <= divStack_addra_p0(PHASE_W-1 downto 0) + 1; divStack_dia_n <= alu_branch_latch(to_integer(divStack_addra_p0(PHASE_W-1 downto 0))) or not alu_en_latch(to_integer(divStack_addra_p0(PHASE_W-1 downto 0))); -- control alu_en_latch if divStack_addra_p0(PHASE_W-1 downto 0) = (0 to PHASE_W-1 => '1') then if go_true_and_false = '1' then wf_active_record_inc_n <= '1'; -- increments the record if another one has to be written st_branch_n <= dly_to_true; go_true_and_false_n <= '0'; PC_stack_push_not_branch_n <= '1'; else st_branch_n <= idle; false_path_n(branching_wf_index) <= '1'; end if; end if; -- }}} when dly_to_true => -- {{{ st_branch_n <= write_true_path_in_divStack; divStack_wea_n <= '0'; -- }}} end case; end process; ---------------------------------------------------------------------------------------------------------}}} ---------------------------------------------------------------------------------------------------------}}} -- PC STACK --------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then -- read PC Stack -- stage 0 PC_stack_pop_ack_p1 <= (others=>'0'); for i in 0 to N_WF_CU-1 loop if PC_stack_pop(i) = '1' and PC_stack_pop_ack_p0(i) = '0' and PC_stack_pop_ack_p1(i) = '0' then -- pop commands are issued from the st_wf state machines on RET instructions PC_stack_rdAddr(N_RECORDS_PC_stack_W-1 downto 0) <= PC_stack_addr(i) - 1; PC_stack_addr(i) <= PC_stack_addr(i) - 1; PC_stack_rdAddr(N_RECORDS_PC_stack_W+N_WF_CU_W-1 downto N_RECORDS_PC_stack_W) <= to_unsigned(i, N_WF_CU_W); PC_stack_pop_ack_p1(i) <= '1'; exit; end if; end loop; -- stage 1 PC_stack_rdData_n <= PC_stack(to_integer(PC_stack_rdAddr)); PC_stack_jump_entry_rdData_n <= PC_stack_jump_entry(to_integer(PC_stack_rdAddr)); -- PC_stack_dummy_entry_rdData_n <= PC_stack_dummy_entry(to_integer(PC_stack_rdAddr)); PC_stack_pop_ack_p0 <= PC_stack_pop_ack_p1; -- stage 2 PC_stack_rdData <= PC_stack_rdData_n; PC_stack_jump_entry_rdData <= PC_stack_jump_entry_rdData_n; -- PC_stack_dummy_entry_rdData <= PC_stack_dummy_entry_rdData_n; PC_stack_pop_ack <= PC_stack_pop_ack_p0; -- select push command PC_stack_push_ack <= (others=>'0'); PC_stack_push_branch_ack <= '0'; PC_stack_push_not_branch_ack <= '0'; if PC_stack_push_branch = '1' and PC_stack_push_branch_ack = '0' then PC_stack_push_branch_ack <= '1'; elsif PC_stack_push_not_branch = '1' and PC_stack_push_not_branch_ack = '0' then PC_stack_push_not_branch_ack <= '1'; else for i in 0 to N_WF_CU-1 loop if PC_stack_push(i) = '1' and PC_stack_push_ack(i) = '0' then PC_stack_push_ack(i) <= '1'; exit; end if; end loop; end if; -- write PC Stack -- push commands come from the st_branch state machine when two records have to be written into divStacks PC_stack_we <= '0'; if PC_stack_push_branch_ack = '1' then PC_stack_we <= '1'; PC_stack_addr(branching_wf_index) <= PC_stack_addr(branching_wf_index) + 1; PC_stack_wrAddr(N_RECORDS_PC_STACK_W-1 downto 0) <= PC_stack_addr(branching_wf_index); PC_stack_wrAddr(N_RECORDS_PC_STACK_W+N_WF_CU_W-1 downto N_RECORDS_PC_STACK_W) <= to_unsigned(branching_wf_index, N_WF_CU_W); PC_stack_wrData <= PC_plus_branch_n(branching_wf_index); PC_stack_jump_entry_wrData <= '0'; -- PC_stack_dummy_entry_wrData <= write_two_records; elsif PC_stack_push_not_branch_ack = '1' then PC_stack_we <= '1'; PC_stack_addr(branching_wf_index) <= PC_stack_addr(branching_wf_index) + 1; PC_stack_wrAddr(N_RECORDS_PC_STACK_W-1 downto 0) <= PC_stack_addr(branching_wf_index); PC_stack_wrAddr(N_RECORDS_PC_STACK_W+N_WF_CU_W-1 downto N_RECORDS_PC_STACK_W) <= to_unsigned(branching_wf_index, N_WF_CU_W); PC_stack_wrData <= PCs(branching_wf_index); PC_stack_jump_entry_wrData <= '0'; -- PC_stack_dummy_entry_wrData <= write_two_records; else for i in 0 to N_WF_CU-1 loop if PC_stack_push_ack(i) = '1' then PC_stack_we <= '1'; PC_stack_addr(i) <= PC_stack_addr(i) + 1; PC_stack_wrAddr(N_RECORDS_PC_STACK_W-1 downto 0) <= PC_stack_addr(i); PC_stack_wrAddr(N_RECORDS_PC_STACK_W+N_WF_CU_W-1 downto N_RECORDS_PC_STACK_W) <= to_unsigned(i, N_WF_CU_W); PC_stack_wrData <= PC_plus_1(i); PC_stack_jump_entry_wrData <= '1'; -- PC_stack_dummy_entry_wrData <= '0'; exit; end if; end loop; end if; if PC_stack_we = '1' then PC_stack(to_integer(PC_stack_wrAddr)) <= PC_stack_wrData; PC_stack_jump_entry(to_integer(PC_stack_wrAddr)) <= PC_stack_jump_entry_wrData; -- PC_stack_dummy_entry(to_integer(PC_stack_wrAddr)) <= PC_stack_dummy_entry_wrData; end if; if nrst = '0' then PC_stack_addr <= (others=>(others=>'0')); end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} ---------------------------------------------------------------------------------------------------------}}} -- Interface to WGD ----------------------------------------------------------------------------- {{{ -- trans process ----------------------------------------------------------------------------------------{{{ interface_fsm_trans: process(clk) begin if rising_edge(clk) then wf_alloc_indx <= wf_alloc_indx_n; wf_finish <= wf_finish_n; allocated_wfs <= allocated_wfs_n; wf_indx <= wf_indx_n; sch_rqst_n_wfs_ltchd <= sch_rqst_n_wfs_ltchd_n; wf_activate <= wf_activate_n; if nrst = '0' then st_WGD_intr <= free; wg_next_id <= (others=>'0'); sch_ack_i <= '0'; else st_WGD_intr <= st_WGD_intr_n; wg_next_id <= wg_next_id_n; sch_ack_i <= sch_ack_n; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- comb process -----------------------------------------------------------------------------------------{{{ interface_fsm_comb: process(st_WGD_intr, sch_rqst, sch_rqst_n_wfs_ltchd, wf_alloc_indx, wf_active_i, sch_rqst_n_wfs_m1, allocated_wfs, wf_indx, wg_next_id, -- wg_next_id, wg_offset_d0, wg_offset_d1, wg_offset_d2) begin st_WGD_intr_n <= st_WGD_intr; wf_finish_n <= (others => '0'); wf_alloc_indx_n <= wf_alloc_indx; sch_rqst_n_wfs_ltchd_n <= sch_rqst_n_wfs_ltchd; allocated_wfs_n <= allocated_wfs; wf_indx_n <= wf_indx; wg_next_id_n <= wg_next_id; rtm_we_cv <= '0'; rtm_wrAddr_cv(N_WF_CU_W-1 downto 0) <= wf_alloc_indx; rtm_wrAddr_cv(N_WF_CU_W+1 downto N_WF_CU_W) <= "00"; rtm_wrData_cv <= wg_offset_d0; wf_activate_n <= (others=>'0'); sch_ack_n <= '0'; case st_WGD_intr is when free => -- {{{ if sch_rqst = '1' then st_WGD_intr_n <= reserve; wf_alloc_indx_n <= (others => '0'); sch_rqst_n_wfs_ltchd_n <= to_integer(sch_rqst_n_wfs_m1) + 1; allocated_wfs_n <= 0; wg_next_id_n <= wg_next_id + 1; end if; -- }}} when reserve => -- {{{ if wf_active_i(to_integer(wf_alloc_indx)) = '0' then allocated_wfs_n <= allocated_wfs + 1; wf_activate_n(to_integer(wf_alloc_indx)) <= '1'; wf_indx_n(to_integer(wf_alloc_indx)) <= allocated_wfs; -- wg_ids_n(to_integer(wf_alloc_indx)) <= wg_next_id; st_WGD_intr_n <= write_wg_d0; else wf_alloc_indx_n <= wf_alloc_indx + 1; end if; when write_wg_d0 => rtm_we_cv <= '1'; st_WGD_intr_n <= write_wg_d1; rtm_wrData_cv <= wg_offset_d0; rtm_wrAddr_cv(N_WF_CU_W+1 downto N_WF_CU_W) <= "00"; when write_wg_d1 => rtm_we_cv <= '1'; st_WGD_intr_n <= write_wg_d2; rtm_wrData_cv <= wg_offset_d1; rtm_wrAddr_cv(N_WF_CU_W+1 downto N_WF_CU_W) <= "01"; when write_wg_d2 => rtm_we_cv <= '1'; rtm_wrData_cv <= wg_offset_d2; rtm_wrAddr_cv(N_WF_CU_W+1 downto N_WF_CU_W) <= "10"; wf_alloc_indx_n <= wf_alloc_indx + 1; if allocated_wfs = sch_rqst_n_wfs_ltchd then st_WGD_intr_n <= free; sch_ack_n <= '1'; else st_WGD_intr_n <= reserve; end if; -- }}} end case; end process; ---------------------------------------------------------------------------------------------------------}}} --------------------------------------------------------------------------------------------}}} -- WFs FSMs ----------------------------------------------------------------------------- {{{ -- WFs trans process ------------------------------------------------------------------------------------{{{ WFS_fsms_trans: process(clk) begin if rising_edge(clk) then PCs <= PCs_n; PC_stack_push <= PC_stack_push_n; PC_plus_1 <= PC_plus_1_n; for i in 0 to N_WF_CU-1 loop wf_wait_vec(i)(WF_WAIT_LEN-2 downto 0) <= wf_wait_vec(i)(WF_WAIT_LEN-1 downto 1); if wf_wait_vec_alu_n(i) = '1' then wf_wait_vec(i)(14) <= '1'; end if; wf_wait_vec(i)(WF_WAIT_LEN-1) <= wf_wait_vec_fpu_n(i); if clear_wf_wait_vec(i) = '0' then if wf_wait_vec(i)(0) = '1' then wf_wait_vec(i)(0) <= '1'; end if; else wf_wait_vec(i)(0) <= '0'; end if; end loop; clear_wf_wait_vec <= clear_wf_wait_vec_n; wf_no_wait <= wf_no_wait_n; if nrst = '0' then st_wf <= (others=>idle); wf_active_i <= (others=>'0'); wf_rdy <= (others=>'0'); wf_gmem_read_rdy <= (others=>'0'); wf_gmem_write_rdy <= (others=>'0'); wf_branch_rdy <= (others=>'0'); PC_stack_pop <= (others=>'0'); else st_wf <= st_wf_n; wf_rdy <= wf_rdy_n; wf_gmem_read_rdy <= wf_gmem_read_rdy_n; wf_branch_rdy <= wf_branch_rdy_n; wf_gmem_write_rdy <= wf_gmem_write_rdy_n; wf_active_i <= wf_active_n; PC_stack_pop <= PC_stack_pop_n; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- WFs comb process -------------------------------------------------------------------------------------{{{ WFS_fsms_comb:for i in 0 to N_WF_CU-1 generate -- {{{ wf_rdy_n(i) <= '1' when st_wf_n(i)=rdy else '0'; wf_gmem_read_rdy_n(i) <= '1' when st_wf_n(i) = rdy and wf_reads_gmem(i) = '1' else '0'; wf_gmem_write_rdy_n(i) <= '1' when st_wf_n(i) = rdy and wf_reads_gmem(i) = '0' and wf_on_gmem(i) = '1' else '0'; wf_branch_rdy_n(i) <= '1' when st_wf_n(i) = rdy and wf_branches(i) = '1' else '0'; PC_plus_branch_n(i) <= PCs(i) + resize(branch_distance(i), CRAM_ADDR_W); PC_plus_1_n(i) <= PCs(i) + 1; -- }}} process(st_wf(i), PCs(i), start_addr, wf_active_i(i), advance_pc(i), pc_rdy(i), wf_on_gmem(i), gmem_finish(i), -- {{{ instr_jump(i), instr_fpu(i), true_path(i), false_path(i), PC_plus_branch_n(i), PC_stack_addr(i), wf_activate(i), wf_retired(i), wf_branches(i), PC_stack_pop(i), PC_stack_pop_ack(i), PC_stack_rdData, --PC_stack_dummy_entry_rdData, PC_stack_pop_ack_p1(i), pc_updated(i), PC_stack_push_ack(i), PC_plus_1_n(i), PC_stack_jump_entry_rdData, wf_active_record(i), wf_scratchpad_ld(i), branch_in_executoin, wf_wait_vec(i)(0), wf_no_wait(i)) -- }}} begin st_wf_n(i) <= st_wf(i); -- {{{ PCs_n(i) <= PCs(i); pc_updated_n(i) <= '0'; wf_active_n(i) <= wf_active_i(i); PC_stack_pop_n(i) <= PC_stack_pop(i); wf_active_record_dec_n(i) <= '0'; PC_stack_push_n(i) <= '0'; branch_in_executoin_n(i) <= '0'; wf_wait_vec_alu_n(i) <= '0'; wf_wait_vec_fpu_n(i) <= '0'; clear_wf_wait_vec_n(i) <= '0'; wf_no_wait_n(i) <= wf_no_wait(i); --}}} case st_wf(i) is when idle => -- {{{ wf_no_wait_n(i) <= '1'; if wf_activate(i) = '1' then st_wf_n(i) <= wait_pc_rdy; PCs_n(i) <= start_addr; pc_updated_n(i) <= '1'; wf_active_n(i) <= '1'; end if; -- }}} when check_rdy => -- {{{ if pc_rdy(i) = '1' and (wf_wait_vec(i)(0) = '1' or wf_no_wait(i) = '1') then wf_no_wait_n(i) <= '0'; if wf_retired(i) = '1' then if PC_stack_addr(i) > 0 then st_wf_n(i) <= read_PC_stack; PC_stack_pop_n(i) <= '1'; clear_wf_wait_vec_n(i) <= '1'; else st_wf_n(i) <= idle; wf_active_n(i) <= '0'; clear_wf_wait_vec_n(i) <= '1'; end if; elsif instr_jump(i) = '1' then st_wf_n(i) <= jumping; elsif wf_on_gmem(i) = '1' then st_wf_n(i) <= rdy; clear_wf_wait_vec_n(i) <= '1'; elsif wf_branches(i) = '1' then if branch_in_executoin = '0' then st_wf_n(i) <= rdy; clear_wf_wait_vec_n(i) <= '1'; else wf_no_wait_n(i) <= '1'; end if; else st_wf_n(i) <= rdy; clear_wf_wait_vec_n(i) <= '1'; end if; end if; -- }}} when read_PC_stack => -- {{{ wf_no_wait_n(i) <= '1'; if PC_stack_pop_ack_p1(i) = '1' then PC_stack_pop_n(i) <= '0'; end if; if PC_stack_pop_ack(i) = '1' then PCs_n(i) <= PC_stack_rdData; if PC_stack_jump_entry_rdData = '0' and wf_active_record(i) = to_unsigned(1, N_RECORDS_WF_W) then -- 1. condition: '0' means it is not a jump entry, i.e. it is a branch entry -- 2. condition: it is the last record, i.e. all branches have been processed (there may be jumps) if PC_stack_addr(i) = to_unsigned(0, N_RECORDS_WF_W) then -- nothing to do further, the wavefront has to retire st_wf_n(i) <= idle; wf_active_n(i) <= '0'; clear_wf_wait_vec_n(i) <= '1'; else -- there are still entries to be processed PC_stack_pop_n(i) <= '1'; end if; -- elsif PC_stack_dummy_entry_rdData = '1' then -- PC_stack_pop_n(i) <= '1'; else pc_updated_n(i) <= '1'; end if; if PC_stack_jump_entry_rdData = '0' then wf_active_record_dec_n(i) <= '1'; end if; end if; if pc_updated(i) = '1' then st_wf_n(i) <= check_rdy; end if; -- }}} when rdy => --{{{ -- the order is important if wf_branches(i) = '1' and branch_in_executoin = '1' then st_wf_n(i) <= check_rdy; wf_no_wait_n(i) <= '1'; end if; -- assert wf_branches(i) = '0' or branch_in_executoin = '0' or advance_pc(i) = '0' severity failure; if advance_pc(i) = '1' then PCs_n(i) <= PC_plus_1_n(i); if instr_fpu(i) = '1' then wf_wait_vec_fpu_n(i) <= '1'; else wf_wait_vec_alu_n(i) <= '1'; end if; pc_updated_n(i) <= '1'; if wf_on_gmem(i) = '1' then st_wf_n(i) <= wait_gmem_finish; elsif wf_branches(i) = '1' then st_wf_n(i) <= branching; pc_updated_n(i) <= '0'; branch_in_executoin_n(i) <= '1'; elsif wf_scratchpad_ld(i) = '1' then st_wf_n(i) <= scratchpad_load; else st_wf_n(i) <= wait_for_selecting_PC; end if; end if; -- }}} when wait_for_selecting_PC => -- {{{ st_wf_n(i) <= wait_pc_rdy; -- }}} when wait_pc_rdy => -- {{{ st_wf_n(i) <= check_rdy; -- }}} when wait_gmem_finish => -- {{{ if gmem_finish(i) = '1' then st_wf_n(i) <= check_rdy; end if; -- }}} when jumping => -- {{{ PC_stack_push_n(i) <= '1'; if PC_stack_push_ack(i) = '1' then PC_stack_push_n(i) <= '0'; pc_updated_n(i) <= '1'; st_wf_n(i) <= wait_for_selecting_PC; PCs_n(i) <= PC_plus_branch_n(i); end if; -- }}} when branching => -- {{{ if true_path(i) = '1' then PCs_n(i) <= PC_plus_branch_n(i); pc_updated_n(i) <= '1'; st_wf_n(i) <= wait_for_selecting_PC; elsif false_path(i) = '1' then pc_updated_n(i) <= '1'; st_wf_n(i) <= wait_for_selecting_PC; end if; -- }}} when scratchpad_load => -- {{{ -- it should wait for extra 3 clock cycles if wf_wait_vec(i)(0) = '1' then wf_no_wait_n(i) <= '1'; st_wf_n(i) <= wait_for_selecting_PC; end if; -- }}} end case; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -----------------------------------------------------------------------------------------}}} -- CV-Side FSM ----------------------------------------------------------------------------- {{{ -- trans process ----------------------------------------------------------------------------------------{{{ CV_side_trans: process(clk) begin if rising_edge(clk) then if nrst = '0' then st_CV <= idle; advance_pc <= (others=>'0'); phase_i <= (others=>'0'); new_instr_found <= '0'; -- for timing wf_sel_indx <= 0; pc_indx <= 0; wf_indx_in_wg <= 0; wf_indx_in_CU_i <= 0; instr_i <= (others=>'0'); pc_updated <= (others=>'0'); rd_priority <= '0'; else rd_priority <= rd_priority_n; st_CV <= st_CV_n; wf_sel_indx <= wf_sel_indx_n; advance_pc <= advance_pc_n; phase_i <= phase_n; pc_indx <= pc_indx_n; execute <= execute_n; if execute_n = '1' then wf_indx_in_wg <= wf_indx(wf_sel_indx_n); wf_indx_in_CU_i <= wf_sel_indx_n; end if; instr_i <= instr_n; pc_updated <= pc_updated_n; new_instr_found <= new_instr_found_n; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- comb process ----------------------------------------------------------------------------{{{ CV_side_comb: process(st_CV, wf_sel_indx, wf_rdy, sch_rqst, instr_buf_out, phase_i, pc_indx, pc_indx_n, wf_branch_rdy, new_instr_found, instr_i, wf_gmem_read_rdy, wf_gmem_write_rdy, rd_priority) begin -- {{{ st_CV_n <= st_CV; rd_priority_n <= rd_priority; advance_pc_n <= (others => '0'); wf_sel_indx_n <= wf_sel_indx; execute_n <= '0'; instr_n <= instr_i; phase_n <= phase_i + 1; pc_indx_n <= pc_indx; new_instr_found_n <= new_instr_found; if phase_i = (phase_i'reverse_range => '1') then instr_n <= (others=>'0'); end if; -- }}} case st_CV is when idle => -- {{{ phase_n <= (others=>'0'); if sch_rqst = '1' then st_CV_n <= check_wf_rdy; end if; -- }}} when check_wf_rdy => -- {{{ new_instr_found_n <= '0'; if phase_i(1 downto 0) = "00" then if wf_rdy /= (wf_rdy'reverse_range =>'0') then st_CV_n <= select_PC; pc_indx_n <= pri_enc(wf_rdy); if wf_branch_rdy /= (wf_branch_rdy'reverse_range => '0') then pc_indx_n <= pri_enc(wf_branch_rdy); end if; if rd_priority = '1' then if wf_gmem_read_rdy /= (wf_gmem_read_rdy'reverse_range => '0') then pc_indx_n <= pri_enc(wf_gmem_read_rdy); elsif wf_gmem_write_rdy /= (wf_gmem_write_rdy'reverse_range => '0') then pc_indx_n <= pri_enc(wf_gmem_write_rdy); -- rd_priority_n <= '0'; end if; else if wf_gmem_write_rdy /= (wf_gmem_write_rdy'reverse_range => '0') then pc_indx_n <= pri_enc(wf_gmem_write_rdy); elsif wf_gmem_read_rdy /= (wf_gmem_read_rdy'reverse_range => '0') then pc_indx_n <= pri_enc(wf_gmem_read_rdy); rd_priority_n <= '1'; end if; end if; advance_pc_n <= (others => '0'); advance_pc_n(pc_indx_n) <= '1'; new_instr_found_n <= '1'; end if; end if; -- }}} when select_PC => -- {{{ -- PC is incremented in this clock cycle, st_wf is moving to wait_for_selecting_PC, PC_slctd is being prepared in the buffuer module st_CV_n <= select_instr; when select_instr => -- st_wf is wait_pc_ready, pc_rdy is being calculated in the buffer module if new_instr_found = '1' then st_CV_n <= read_inst; else st_CV_n <= check_wf_rdy; end if; -- }}} when read_inst => -- {{{ -- st_wf is check_rdy, the instruction is at the output of the buffer module, phase(0) = '1' execute_n <= '1'; st_CV_n <= start_exec; wf_sel_indx_n <= pc_indx; phase_n <= (others=>'0'); instr_n <= instr_buf_out; -- }}} when start_exec => -- {{{ st_CV_n <= dly1; -- }}} when dly1 => -- {{{ st_CV_n <= dly2; -- }}} when dly2 => -- {{{ st_CV_n <= dly3; -- }}} when dly3 => -- {{{ st_CV_n <= check_wf_rdy; -- }}} end case; end process; ---------------------------------------------------------------------------------------------------------}}} --------------------------------------------------------------------------------------------------- }}} end Behavioral;

gpl-3.0

8aa9352c2fd2886627bf7b5e26c32574

Kinxil/VHDL_Projects

Mandelbrot/Colorgen.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library WORK; use WORK.CONSTANTS.ALL; use WORK.FUNCTIONS.ALL; entity Colorgen is Port ( iters : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0); itermax : in STD_LOGIC_VECTOR (ITER_RANGE-1 downto 0); color : out STD_LOGIC_VECTOR (bit_per_pixel-1 downto 0)); end Colorgen; architecture Behavioral of Colorgen is -- TODO : Améliorer colorgen (comparaison OpenGL) type rom_type is array (0 to ITER_MAX-1) of std_logic_vector (bit_per_pixel-1 downto 0); constant color_scheme : rom_type := ( "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000000", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000001", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000010", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000011", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000100", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000101", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000110", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000000111", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001000", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001001", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001010", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001011", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001100", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001101", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001110", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000001111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000011111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000101111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000000111111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001001111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001011111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001101111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000001111111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010001111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010011111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010101111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000010111111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011001111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011011111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011101111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111111", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111110", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111101", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111100", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111011", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111010", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111001", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011111000", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110111", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110110", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110101", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110100", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110011", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110010", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110001", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000011110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "000111110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001011110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "001111110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010011110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "010111110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011011110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "011111110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100011110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "100111110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101011110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "101111110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110011110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "110111110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111011110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111110000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111100000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111010000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111111000000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110110000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110100000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110010000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111110000000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101110000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101100000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101010000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111101000000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100110000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100100000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100010000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000000", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000001", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000010", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000011", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000100", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000101", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000110", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100000111", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001000", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001001", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001010", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001011", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001100", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001101", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001110", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111", "111100001111" ); begin process(iters, itermax) begin if (iters = itermax) then color<= (others=>'0'); else color <= not color_scheme(to_integer(unsigned(iters))); end if; end process;end Behavioral; --Cut and paste following lines into Shared.vhd. -- constant ITER_MAX : integer := 4095; -- constant ITER_RANGE : integer := 12;

gpl-3.0

643abb10fc2df6ddca4b091048626b6c

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_6Stations.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 6; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

a4743406565e4ef32af5eff74cc16d9d

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_SubInteger.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 1; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

705bfd499fa826d4c87b4001492ef460

preusser/q27

src/vhdl/top/xilinx/sdrc_queens_master.vhdl

library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.physical.all; entity sdrc_queens_master is generic ( -- Design Parameters N : positive := 27; L : positive := 2; SOLVERS : positive := 90; COUNT_CYCLES : boolean := false; -- Local Clock Parameters CLK_FREQ : FREQ := 16 MHz; -- external clock CLK_MUL : positive := 31; -- computation clock: CLK_DIV : positive := 4; -- CLK_FREQ / CLK_DIV * CLK_MUL -- UART Parameters BAUDRATE : positive := 115200; SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte ); port ( --------------------------------------------------------------------------- -- 16-MHz Input Clock CLK16_U : in std_logic; --------------------------------------------------------------------------- -- Master: UART rx : in std_logic; tx : out std_logic; cts : in std_logic; rts : out std_logic; --------------------------------------------------------------------------- -- Status led : out std_logic_vector(3 downto 0); --------------------------------------------------------------------------- -- Ring Bus -- Output BUS_OUT_CLKP : out std_logic; BUS_OUT_CLKN : out std_logic; BUS_OUT_PRE_DAT : out std_logic_vector(8 downto 0); BUS_OUT_PRE_PUT : out std_logic; BUS_OUT_PRE_GO : in std_logic; BUS_OUT_SOL_DAT : out std_logic_vector(8 downto 0); BUS_OUT_SOL_PUT : out std_logic; BUS_OUT_SOL_GO : in std_logic; -- Input BUS_IN_CLKP : in std_logic; BUS_IN_CLKN : in std_logic; BUS_IN_PRE_DAT : in std_logic_vector(8 downto 0); BUS_IN_PRE_PUT : in std_logic; BUS_IN_PRE_GO : out std_logic; BUS_IN_SOL_DAT : in std_logic_vector(8 downto 0); BUS_IN_SOL_PUT : in std_logic; BUS_IN_SOL_GO : out std_logic ); end sdrc_queens_master; library IEEE; use IEEE.numeric_std.all; library PoC; use PoC.utils.all; use PoC.fifo.all; use PoC.uart.all; library UNISIM; use UNISIM.vcomponents.all; architecture rtl of sdrc_queens_master is -- Bit Length of Pre-Placement constant PRE_BITS : positive := 4*L*log2ceil(N)-1; constant PRE_BYTES : positive := (PRE_BITS+7)/8; -- FIFO Dimensioning constant FIFO_DEPTH : positive := 5*(SOLVERS+5); ---------------------------------------------------------------------------- -- Global Control signal clk_comp : std_logic; -- Computation Clock signal rst_comp : std_logic; signal clk_out : std_logic; -- Communication Clock (Output Side) signal rst_out : std_logic; -- UART Interface signal rx_dat : byte; signal rx_stb : std_logic; signal tx_dat : byte; signal tx_ful : std_logic; signal tx_put : std_logic; -- Frame Interface signal pvld : std_logic; signal pdat : byte; signal peof : std_logic; signal pgot : std_logic; begin ---------------------------------------------------------------------------- -- Clock Generation blkClock: block -- Intermediate Clock Signals signal clk16 : std_logic; -- Buffered Input Clock signal clk_comp_u : std_logic; signal locked_comp : std_logic; begin -- 16 MHz Board Clock -> Computation Clock clk16_buf : IBUFG port map ( I => CLK16_U, O => clk16 ); DCM0 : DCM_BASE generic map ( CLKIN_PERIOD => to_real(1.0/CLK_FREQ, 1 ns), CLKIN_DIVIDE_BY_2 => FALSE, PHASE_SHIFT => 0, CLKFX_MULTIPLY => CLK_MUL, CLKFX_DIVIDE => CLK_DIV, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "NONE", -- only using clkfx DLL_FREQUENCY_MODE => "LOW", DFS_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, STARTUP_WAIT => TRUE, DCM_AUTOCALIBRATION => FALSE ) port map ( CLKIN => clk16, CLKFB => '0', RST => '0', CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => clk_comp_u, CLKFX180 => open, LOCKED => locked_comp ); clk_comp_buf : BUFGCE port map ( CE => locked_comp, I => clk_comp_u, O => clk_comp ); rst_comp <= '0'; clk_out_buf : BUFGCE port map ( CE => locked_comp, I => clk16, O => clk_out ); rst_out <= '0'; led(0) <= locked_comp; end block blkClock; ---------------------------------------------------------------------------- -- UART blkUART: block signal bclk_x8 : std_logic; signal bclk_x1 : std_logic; begin -- Bit Clock Generation bclk_gen_x8: entity PoC.arith_counter_free generic map ( DIVIDER => integer(to_real(CLK_FREQ, 1 Hz))/(8*BAUDRATE) ) port map ( clk => clk_out, rst => '0', inc => '1', stb => bclk_x8 ); bclk_gen_x1: entity PoC.arith_counter_free generic map ( DIVIDER => 8 ) port map ( clk => clk_out, rst => '0', inc => bclk_x8, stb => bclk_x1 ); -- Receive Bytes uart_rx_i : uart_rx port map ( clk => clk_out, rst => rst_out, bclk_x8 => bclk_x8, rx => rx, stb => rx_stb, do => rx_dat ); -- Transmit Bytes uart_tx_i : uart_tx port map ( clk => clk_out, rst => rst_out, bclk => bclk_x1, put => tx_put, di => tx_dat, ful => tx_ful, tx => tx ); rts <= cts; end block blkUART; -- Unframing blkUnframe: block -- Input Glue FIFO -> Unframe signal glue_vld : std_logic; signal glue_dat : byte; signal glue_got : std_logic; -- Unframe -> Input Buffer signal odat : byte; signal oeof : std_logic; signal oful : std_logic; signal oput : std_logic; signal ocommit : std_logic; signal orollback : std_logic; begin glue: fifo_glue generic map ( D_BITS => 8 ) port map ( clk => clk_out, rst => rst_out, put => rx_stb, di => rx_dat, ful => open, vld => glue_vld, do => glue_dat, got => glue_got ); unframe_i: entity work.unframe generic map ( SENTINEL => SENTINEL, PAY_LEN => PRE_BYTES ) port map ( clk => clk_out, rst => rst_out, rx_dat => glue_dat, rx_vld => glue_vld, rx_got => glue_got, odat => odat, oeof => oeof, oful => oful, oput => oput, ocommit => ocommit, orollback => orollback ); buf: fifo_cc_got_tempput generic map ( MIN_DEPTH => 5*(SOLVERS+5), D_BITS => 9 ) port map ( clk => clk_out, rst => rst_out, put => oput, din(8) => oeof, din(7 downto 0) => odat, full => oful, commit => ocommit, rollback => orollback, got => pgot, dout(8) => peof, dout(7 downto 0) => pdat, valid => pvld ); end block blkUnframe; blkFeed: block -- Syncing the stall input signal go_s : std_logic_vector(1 downto 0) := (others => '0'); -- Outgoing Output Registers signal OutDat : std_logic_vector(7 downto 0) := (others => '0'); signal OutEof : std_logic := '0'; signal OutPut : std_logic := '0'; -- Inverted Output Clock signal clk_inv : std_logic; begin ------------------------------------------------------------------------- -- Output Inverted Clock blkClock : block signal clk_inv : std_logic; begin invert : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '1', SRTYPE => "SYNC" ) port map ( Q => clk_inv, -- 1-bit DDR output C => clk_out, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D1 => '0', -- 1-bit data input (positive edge) D2 => '1', -- 1-bit data input (negative edge) R => rst_out, -- 1-bit reset input S => '0' -- 1-bit set input ); OBUFDS_inst : OBUFDS generic map ( IOSTANDARD => "DEFAULT", SLEW => "FAST" ) port map ( O => BUS_OUT_CLKP, OB => BUS_OUT_CLKN, I => clk_inv ); end block blkClock; ------------------------------------------------------------------------- -- Pre-placement Output -- Syncing stall input process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then go_s <= (others => '0'); else go_s <= BUS_OUT_PRE_GO & go_s(go_s'left downto 1); end if; end if; end process; pgot <= pvld and go_s(0); -- Output Registers process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then OutDat <= (others => '0'); OutEof <= '0'; OutPut <= '0'; else OutDat <= pdat; OutEof <= peof; OutPut <= pgot; end if; end if; end process; BUS_OUT_PRE_DAT <= OutEof & OutDat; BUS_OUT_PRE_PUT <= OutPut; ------------------------------------------------------------------------- -- Start of Result Chain BUS_OUT_SOL_DAT <= (others => '0'); BUS_OUT_SOL_PUT <= '0'; end block blkFeed; blkDrain: block -- Source synchronous clock domain signal clk_in : std_logic; signal rst_in : std_logic; -- Incoming Bus Data Capture Registers signal InPreDat : std_logic_vector(8 downto 0) := (others => '-'); signal InPrePut : std_logic := '0'; signal InPreCap : std_logic_vector(1 downto 0); signal InSolDat : std_logic_vector(8 downto 0) := (others => '-'); signal InSolPut : std_logic := '0'; signal InSolCap : std_logic_vector(1 downto 0); -- Solver Chain Connectivity signal pivld : std_logic; signal piful : std_logic; signal pidat : byte; signal pieof : std_logic; signal piput : std_logic; signal sivld : std_logic; signal sidat : byte; signal sieof : std_logic; signal sigot : std_logic; signal sovld : std_logic; signal sodat : byte; signal soeof : std_logic; signal sogot : std_logic; -- Solution Stream -> Frames signal tdat : std_logic_vector(7 downto 0); signal tful : std_logic; signal tput : std_logic; signal tx_vld : std_logic; signal tx_got : std_logic; begin --------------------------------------------------------------------------- -- Reading the Bus -- Clock Reconstruction blkClock : block signal clk_in0 : std_logic; begin IBUFGDS_inst : IBUFGDS port map ( O => clk_in0, I => BUS_IN_CLKP, IB => BUS_IN_CLKN ); BUFG_inst : BUFR port map ( I => clk_in0, CE => '1', CLR => '0', O => clk_in ); rst_in <= '0'; end block blkClock; -- Bus Input Capture process(clk_in) begin if rising_edge(clk_in) then if rst_in = '1' then InPreDat <= (others => '-'); InPrePut <= '0'; InSolDat <= (others => '-'); InSolPut <= '0'; else InPreDat <= BUS_IN_PRE_DAT; InPrePut <= BUS_IN_PRE_PUT; InSolDat <= BUS_IN_SOL_DAT; InSolPut <= BUS_IN_SOL_PUT; end if; end if; end process; -- Input FIFO (ic): Pre-Placements buf_pre : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64, ESTATE_WR_BITS => InPreCap'length ) port map ( clk_wr => clk_in, rst_wr => rst_in, put => InPrePut, din => InPreDat, full => open, estate_wr => InPreCap, clk_rd => clk_comp, rst_rd => rst_comp, got => piput, dout(8) => pieof, dout(7 downto 0) => pidat, valid => pivld ); piput <= pivld and not piful; BUS_IN_PRE_GO <= '0' when InPreCap = (InPreCap'range => '0') else '1'; -- Input FIFO (ic): Solutions buf_sol : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64, ESTATE_WR_BITS => InSolCap'length ) port map ( clk_wr => clk_in, rst_wr => rst_in, put => InSolPut, din => InSolDat, full => open, estate_wr => InSolCap, clk_rd => clk_comp, rst_rd => rst_comp, got => sigot, dout(8) => sieof, dout(7 downto 0) => sidat, valid => sivld ); BUS_IN_SOL_GO <= '0' when InSolCap = (InSolCap'range => '0') else '1'; --------------------------------------------------------------------------- -- Solver Chain chain: entity work.queens_chain generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES ) port map ( clk => clk_comp, rst => rst_comp, piful => piful, pidat => pidat, pieof => pieof, piput => piput, sivld => sivld, sidat => sidat, sieof => sieof, sigot => sigot, poful => '1', podat => open, poeof => open, poput => open, sovld => sovld, sodat => sodat, soeof => soeof, sogot => sogot ); enframe_i: entity work.enframe generic map ( SENTINEL => SENTINEL ) port map ( clk => clk_comp, rst => rst_comp, ivld => sovld, idat => sodat, ieof => soeof, igot => sogot, tx_ful => tful, tx_put => tput, tx_dat => tdat ); -- Output FIFO (ic): Solutions fifob : fifo_ic_got generic map ( D_BITS => 8, MIN_DEPTH => FIFO_DEPTH ) port map ( clk_wr => clk_comp, rst_wr => rst_comp, put => tput, din => tdat, full => tful, clk_rd => clk_out, rst_rd => rst_out, got => tx_got, dout => tx_dat, valid => tx_vld ); tx_put <= tx_vld and not tx_ful; tx_got <= tx_put; end block blkDrain; led(3 downto 1) <= "110"; end rtl;

agpl-3.0

4c5d4802f60c1802fd7309264b042f7e

kennethlyn/fpga-image-example

hdl_nodes/subtractor/subtractor.srcs/sim_1/backplane_simulator.vhd

-- File: backplane_simulator.vhd -- -- � COPYRIGHT 2014 TOPIC EMBEDDED PRODUCTS B.V. ALL RIGHTS RESERVED. -- -- This file contains confidential and proprietary information of -- Topic Embedded Products B.V. and is protected under Dutch and -- International copyright and other international intellectual property laws. -- -- Disclaimer -- -- This disclaimer is not a license and does not grant any rights to the -- materials distributed herewith. Except as otherwise provided in a valid -- license issued to you by Topic Embedded Products B.V., and to the maximum -- extend permitted by applicable law: -- -- 1. Dyplo is furnished on an "as is", as available basis. Topic makes no -- warranty, express or implied, with respect to the capability of Dyplo. All -- warranties of any type, express or implied, including the warranties of -- merchantability, fitness for a particular purpose and non-infringement of -- third party rights are expressly disclaimed. -- -- 2. Topic's maximum total liability shall be limited to general money -- damages in an amount not to exceed the total amount paid for in the year -- in which the damages have occurred. Under no circumstances including -- negligence shall Topic be liable for direct, indirect, incidental, special, -- consequential or punitive damages, or for loss of profits, revenue, or data, -- that are directly or indirectly related to the use of, or the inability to -- access and use Dyplo and related services, whether in an action in contract, -- tort, product liability, strict liability, statute or otherwise even if -- Topic has been advised of the possibility of those damages. -- -- This copyright notice and disclaimer must be retained as part of this file at all times. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; library tb_lib; use tb_lib.tb_env_pkg.all; library std; use std.env.all; use std.textio.all; library dyplo_hdl_node_lib; use dyplo_hdl_node_lib.hdl_node_package.all; use dyplo_hdl_node_lib.hdl_node_user_params.all; library dyplo; use dyplo.all; entity backplane_simulator is end backplane_simulator; architecture rtl of backplane_simulator is -- clock and reset for testbench signal dab_clk : std_logic := '0'; signal dab_rst : std_logic := '1'; --Internal signals for HDL node signal dab_clk_i : std_logic; signal dab_rst_i : std_logic; signal dab_addr_i : std_logic_vector(c_hdl_dab_awidth - 1 downto 0); signal dab_sel_i : std_logic; signal dab_wvalid_i : std_logic; signal dab_rvalid_i : std_logic; signal dab_wdata_i : std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); signal dab_rdata_i : std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); -- Receive data from backplane to FIFO signal b2f_tdata_i : std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0); signal b2f_tstream_id_i : std_logic_vector(c_hdl_stream_id_width - 1 downto 0); signal b2f_tvalid_i : std_logic; signal b2f_tready_i : std_logic; -- Send data from FIFO to backplane signal f2b_tdata_i : std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0); signal f2b_tstream_id_i : std_logic_vector(c_hdl_stream_id_width - 1 downto 0); signal f2b_tvalid_i : std_logic; signal f2b_tready_i : std_logic; -- Clock signals signal dest_fifo_status_i : std_logic_vector(3 downto 0) := (others => '1'); -- Clock signals signal user_clocks_i : std_logic_vector(3 downto 0); --internal signals for stim_reader signal cmd_i : cmd_record; signal cmd_accept_i : std_logic; signal eof_i : std_logic; --stream signals for datain stream processes type streams_in_tdata_type is array (0 to c_input_streams - 1) of std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0); type streams_in_tstream_id_type is array (0 to c_input_streams - 1) of std_logic_vector(c_hdl_stream_id_width - 1 downto 0); signal streams_in_tdata : streams_in_tdata_type; signal streams_in_tstream_id : streams_in_tstream_id_type; signal streams_in_tvalid : std_logic_vector(c_input_streams - 1 downto 0); signal streams_in_tready : std_logic_vector(c_input_streams - 1 downto 0); --tready signals for dataout stream processes signal streams_out_tready : std_logic_vector(c_output_streams - 1 downto 0); --tready signals for dataout combinatoric combined with tstream_id signal streams_out_tready_c : std_logic_vector(c_output_streams - 1 downto 0); --data signal for storing stream parameters for each stream type data_in_streams_type is array (0 to c_input_streams - 1) of data_stream; signal data_in_streams : data_in_streams_type; type data_out_streams_type is array (0 to c_output_streams - 1) of data_stream; signal data_out_streams : data_out_streams_type; --type definition of type for state machine type sm_control_type is (IDLE, PARSE_CMD, DAB_DELAY_WRITE, DAB_DELAY_READ); signal sm_control : sm_control_type := IDLE; signal schedule_in_streams : integer := 0; signal dab_delay_cnt : unsigned(1 downto 0); --delay for dab r/w signal out_streams_enabled : std_logic_vector(c_output_streams - 1 downto 0); signal out_streams_finished : std_logic_vector(c_output_streams - 1 downto 0); signal in_streams_enabled : std_logic_vector(c_input_streams - 1 downto 0); signal in_streams_finished : std_logic_vector(c_input_streams - 1 downto 0); --component declaration stim_reader component tb_stim_reader is generic( STIM_FILE_NAME : string := "" ); port ( cmd_out : out cmd_record; cmd_accept_in : in std_logic; eof : out std_logic ); end component; --component declaration HDL_node component dyplo_hdl_node is port( -- Miscellaneous node_id : in std_logic_vector(c_hdl_node_id_width - 1 downto 0); -- DAB interface dab_clk : in std_logic; dab_rst : in std_logic; dab_addr : in std_logic_vector(c_hdl_dab_awidth - 1 downto 0); dab_sel : in std_logic; dab_wvalid : in std_logic; dab_rvalid : in std_logic; dab_wdata : in std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); dab_rdata : out std_logic_vector(c_hdl_dab_dwidth - 1 downto 0); -- Receive data from backplane to FIFO b2f_tdata : in std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0); b2f_tstream_id : in std_logic_vector(c_hdl_stream_id_width - 1 downto 0); b2f_tvalid : in std_logic; b2f_tready : out std_logic; -- Send data from FIFO to backplane f2b_tdata : out std_logic_vector(c_hdl_backplane_bus_width - 1 downto 0); f2b_tstream_id : out std_logic_vector(c_hdl_stream_id_width - 1 downto 0); f2b_tvalid : out std_logic; f2b_tready : in std_logic; -- Serial fifo status info fifo_status_sync : in std_logic; fifo_status_flag : out std_logic; -- fifo statuses of destination fifo's dest_fifo_status : in std_logic_vector(3 downto 0); -- Clock signals user_clocks : in std_logic_vector(3 downto 0) ); end component; begin hdl_node : dyplo_hdl_node port map( -- Miscellaneous node_id => "00010", -- don't change, because of address range in simulation -- DAB interface dab_clk => dab_clk_i, dab_rst => dab_rst_i, dab_addr => dab_addr_i, dab_sel => dab_sel_i, dab_wvalid => dab_wvalid_i, dab_rvalid => dab_rvalid_i, dab_wdata => dab_wdata_i, dab_rdata => dab_rdata_i, -- Receive data from backplane to FIFO b2f_tdata => b2f_tdata_i, b2f_tstream_id => b2f_tstream_id_i, b2f_tvalid => b2f_tvalid_i, b2f_tready => b2f_tready_i, -- Send data from FIFO to backplane f2b_tdata => f2b_tdata_i, f2b_tstream_id => f2b_tstream_id_i, f2b_tvalid => f2b_tvalid_i, f2b_tready => f2b_tready_i, -- Serial fifo status info fifo_status_sync => '0', fifo_status_flag => open, -- fifo statuses of destination fifo's dest_fifo_status => dest_fifo_status_i, -- Clock signals user_clocks => user_clocks_i ); stim_reader : tb_stim_reader generic map( STIM_FILE_NAME => "../../stimuli/control_stimuli.txt" ) port map( cmd_out => cmd_i, cmd_accept_in => cmd_accept_i, eof => eof_i ); dab_clk <= not dab_clk after 5 ns; -- 100MHz clock dab_rst <= '0' after 50 ns; -- Synchronous, active high reset dab_clk_i <= dab_clk; dab_rst_i <= dab_rst; control : process(dab_clk) variable stream_no : integer := 0; variable v_value_int : integer; variable v_value_slv : std_logic_vector(31 downto 0); variable v_result : boolean; variable v_result_len : integer; variable v_string : string(1 to CMD_WORD_SIZE); begin if(rising_edge(dab_clk)) then if(dab_rst = '1') then dab_addr_i <= (others => '0'); dab_sel_i <= '0'; dab_wvalid_i <= '0'; dab_rvalid_i <= '0'; dab_wdata_i <= (others => '0'); dab_delay_cnt <= "11"; sm_control <= IDLE; data_in_streams <= (others => ((others => NUL), 0, '0')); data_out_streams <= (others => ((others => NUL), 0, '0')); else case(sm_control) is when IDLE => dab_sel_i <= '0'; dab_wvalid_i <= '0'; dab_rvalid_i <= '0'; if(cmd_i.valid = true) then sm_control <= PARSE_CMD; else cmd_accept_i <= '0'; --release command end if; when PARSE_CMD => if (cmd_i.word(0)(1 to 12) = "write_config") then -- dab write_control (hdl_node) command --read arguments for i in 1 to (cmd_i.cnt-1) loop v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i)); proc_get_value ( str => v_string(1 to cmd_i.size(i)), slv => v_value_slv, result => v_result, len => v_result_len ); if not(v_result) then report "ERROR: Unknown value!"; report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i)); report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100" severity failure; end if; if (i=1) then --address dab_addr_i <= "00000" & ( X"1000" + v_value_slv(15 downto 0)); elsif (i=2) then --data dab_wdata_i <= v_value_slv(31 downto 0); end if; end loop; dab_sel_i <= '1'; dab_delay_cnt <= "11"; sm_control <= DAB_DELAY_WRITE; elsif (cmd_i.word(0)(1 to 10) = "write_data") then -- dab write_data (user_logic) command --read arguments for i in 1 to (cmd_i.cnt-1) loop v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i)); proc_get_value ( str => v_string(1 to cmd_i.size(i)), slv => v_value_slv, result => v_result, len => v_result_len ); if not(v_result) then report "ERROR: Unknown value!"; report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i)); report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100" severity failure; end if; if (i=1) then --address dab_addr_i <= "00010" & v_value_slv(15 downto 0); elsif (i=2) then --data dab_wdata_i <= v_value_slv(31 downto 0); end if; end loop; dab_sel_i <= '1'; dab_delay_cnt <= "11"; sm_control <= DAB_DELAY_WRITE; elsif (cmd_i.word(0)(1 to 11) = "read_config") then -- dab read_control (hdl_node) command --read arguments for i in 1 to (cmd_i.cnt-1) loop v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i)); proc_get_value ( str => v_string(1 to cmd_i.size(i)), slv => v_value_slv, result => v_result, len => v_result_len ); if not(v_result) then report "ERROR: Unknown value!"; report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i)); report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100" severity failure; end if; if (i=1) then --address dab_addr_i <= "00000" & ( X"1000" + v_value_slv(15 downto 0)); end if; end loop; dab_sel_i <= '1'; dab_delay_cnt <= "11"; sm_control <= DAB_DELAY_READ; elsif (cmd_i.word(0)(1 to 9) = "read_data") then -- dab read_data (user_logic) command --read arguments for i in 1 to (cmd_i.cnt-1) loop v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i)); proc_get_value ( str => v_string(1 to cmd_i.size(i)), slv => v_value_slv, result => v_result, len => v_result_len ); if not(v_result) then report "ERROR: Unknown value!"; report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i)); report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100" severity failure; end if; if (i=1) then --address dab_addr_i <= "00010" & v_value_slv(15 downto 0); end if; end loop; dab_sel_i <= '1'; dab_delay_cnt <= "11"; sm_control <= DAB_DELAY_READ; elsif (cmd_i.word(0)(1 to 9) = "stream_in") then -- stream settings --read arguments for i in 1 to (cmd_i.cnt-1) loop v_string := (others => NUL); v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i)); if(i /= 3) then proc_str_to_int ( str => v_string(1 to cmd_i.size(i)), int => v_value_int, result => v_result ); if not(v_result) then report "ERROR: Unknown value!"; report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i)); report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100" severity failure; end if; end if; if (i=1) then --stream_no stream_no := v_value_int; if(stream_no >= c_input_streams) then report "ERROR: stream_in command: Stream nr " & integer'image(stream_no) & " invalid, valid stream nrs are 0 to " & integer'image(c_input_streams - 1) severity failure; else data_in_streams(stream_no).enable <= '1'; end if; elsif (i=2) then --length data_in_streams(stream_no).length <= v_value_int; elsif (i=3) then --filename if(v_string(1) /= NUL) then data_in_streams(stream_no).filename <= v_string; else report "ERROR: stream_in command: Filename cannot be empty" severity failure; end if; end if; end loop; sm_control <= IDLE; elsif (cmd_i.word(0)(1 to 10) = "stream_out") then -- stream settings --read arguments for i in 1 to (cmd_i.cnt-1) loop v_string := (others => NUL); v_string(1 to cmd_i.size(i)) := cmd_i.word(i)(1 to cmd_i.size(i)); if(i /= 3) then proc_str_to_int ( str => v_string(1 to cmd_i.size(i)), int => v_value_int, result => v_result ); if not(v_result) then report "ERROR: Unknown value!"; report "Found: " & cmd_i.word(i)(1 to cmd_i.size(i)); report "Expected: hexadecimal or binary value e.g. 0xABCD or 0b1011010000100100 or X1011010000HLL100" severity failure; end if; end if; if (i=1) then --stream_no stream_no := v_value_int; if(stream_no >= c_output_streams) then report "ERROR: stream_out command: Stream nr " & integer'image(stream_no) & " invalid, valid stream nrs are 0 to " & integer'image(c_output_streams - 1) severity failure; else data_out_streams(stream_no).enable <= '1'; end if; elsif (i=2) then --length data_out_streams(stream_no).length <= v_value_int; elsif (i=3) then --filename data_out_streams(stream_no).filename <= v_string; end if; end loop; sm_control <= IDLE; else report "ERROR: Unknown command!"; report "Found: " & cmd_i.word(0) severity failure; end if; cmd_accept_i <= '1'; -- do accept command when DAB_DELAY_WRITE => if (dab_delay_cnt /= 0) then dab_delay_cnt <= dab_delay_cnt - 1; else dab_wvalid_i <= '1'; sm_control <= IDLE; end if; when DAB_DELAY_READ => if (dab_delay_cnt /= 0) then dab_delay_cnt <= dab_delay_cnt - 1; else dab_rvalid_i <= '1'; sm_control <= IDLE; end if; end case; end if; end if; end process; -- Data in streams data_streams_in : for i in 0 to c_input_streams - 1 generate signal words_send : integer := 0; type sm_stream_type is (START_BURST, INTERRUPT_BURST, BURST); signal sm_stream : sm_stream_type := START_BURST; signal burst_cnt : integer := 0; begin stream_x : process(dab_clk) file datafile : text; variable v_file_opened : boolean := false; variable v_data_file_status : file_open_status; variable v_data_line : line; variable v_data_word : string(1 to 10); begin if(rising_edge(dab_clk)) then if(dab_rst = '1') then streams_in_tdata(i) <= (others => '0'); streams_in_tstream_id(i) <= (others => '0'); streams_in_tvalid(i) <= '0'; in_streams_finished(i) <= '0'; sm_stream <= START_BURST; else streams_in_tstream_id(i) <= std_logic_vector(to_unsigned(i,c_hdl_stream_id_width)); if(data_in_streams(i).enable = '1' and words_send < data_in_streams(i).length) then case(sm_stream) is when START_BURST => if(v_file_opened = false) then file_open(v_data_file_status, datafile, (string'("../../data/") & data_in_streams(i).filename), read_mode); if not(v_data_file_status = OPEN_OK) then report "ERROR: Unable to open data file: " & string'(data_in_streams(i).filename) severity failure; else v_file_opened := true; end if; end if; --read line from data file if(not endfile(datafile)) then str_read(datafile, v_data_word); streams_in_tdata(i) <= hstr_to_slv(v_data_word(3 to 10)); streams_in_tvalid(i) <= '1'; else report "ERROR: End of file!" severity failure; end if; burst_cnt <= 0; sm_stream <= BURST; when BURST => if(streams_in_tready(i) = '1' and streams_in_tvalid(i) = '1') then words_send <= words_send + 1; burst_cnt <= burst_cnt + 1; if( (words_send + 1) < data_in_streams(i).length) then --read line from data file if(not endfile(datafile)) then str_read(datafile, v_data_word); streams_in_tdata(i) <= hstr_to_slv(v_data_word(3 to 10)); if(burst_cnt = 63) then streams_in_tvalid(i) <= '0'; burst_cnt <= 0; sm_stream <= INTERRUPT_BURST; else streams_in_tvalid(i) <= '1'; end if; else file_close(datafile); report "ERROR: End of file!" severity failure; end if; else streams_in_tvalid(i) <= '0'; in_streams_finished(i) <= '1'; file_close(datafile); end if; end if; when INTERRUPT_BURST => streams_in_tvalid(i) <= '1'; sm_stream <= BURST; end case; end if; end if; end if; end process; end generate; b2f_tdata_i <= streams_in_tdata(schedule_in_streams); b2f_tstream_id_i <= streams_in_tstream_id(schedule_in_streams); b2f_tvalid_i <= streams_in_tvalid(schedule_in_streams); streams_in_tready <= (schedule_in_streams => b2f_tready_i, others => '0'); -- Data in streams data_streams_out : for i in 0 to c_output_streams - 1 generate signal words_received : integer := 0; type sm_stream_type is (WAITING, BURST, END_BURST); signal sm_stream : sm_stream_type := WAITING; begin stream_x : process(dab_clk) file datafile : text; variable v_file_opened : boolean := false; variable v_data_file_status : file_open_status; variable v_data_line : line; variable v_data_word : string(1 to 10); variable v_expected_data : std_logic_vector(31 downto 0); begin if(rising_edge(dab_clk)) then if(dab_rst = '1') then streams_out_tready(i) <= '0'; out_streams_finished(i) <= '0'; else if(data_out_streams(i).enable = '1' and words_received < data_out_streams(i).length) then streams_out_tready(i) <= '1'; if(data_out_streams(i).filename(1) /= NUL) then if(v_file_opened = false) then file_open(v_data_file_status, datafile, (string'("../../data/") & data_out_streams(i).filename), read_mode); if not(v_data_file_status = OPEN_OK) then report "ERROR: Unable to open data file: " & string'(data_out_streams(i).filename) severity failure; else v_file_opened := true; end if; end if; end if; if(f2b_tvalid_i = '1' and streams_out_tready(i) = '1' and conv_integer(f2b_tstream_id_i) = i) then words_received <= words_received + 1; if(data_out_streams(i).filename(1) /= NUL) then --read line from data file if(not endfile(datafile)) then str_read(datafile, v_data_word); v_expected_data := hstr_to_slv(v_data_word(3 to 10)); else report "ERROR: End of file!" severity failure; end if; assert f2b_tdata_i = v_expected_data report "ERROR: Received data does not match expected data" severity failure; end if; --read from file and data bus and check (assert) if( (words_received + 1) = data_out_streams(i).length) then streams_out_tready(i) <= '0'; out_streams_finished(i) <= '1'; if(data_out_streams(i).filename(1) /= NUL) then file_close(datafile); end if; end if; end if; end if; end if; end if; end process; streams_out_tready_c(i) <= '1' when (streams_out_tready(i) = '1' and conv_integer(f2b_tstream_id_i) = i) else '0'; end generate; f2b_tready_i <= '1' when (streams_out_tready_c /= std_logic_vector(to_unsigned(0,4))) else '0'; schedule : process(dab_clk) variable schedule_in_next : integer := 0; begin if(rising_edge(dab_clk)) then if(dab_rst_i = '1') then schedule_in_streams <= 0; else if(streams_in_tvalid(schedule_in_streams) = '0') then --Schedule, next lane schedule_in_next := schedule_in_streams; for s in 0 to c_input_streams - 1 loop if(schedule_in_next = c_input_streams - 1) then schedule_in_next := 0; else schedule_in_next := schedule_in_next + 1; end if; if(streams_in_tvalid(schedule_in_next) = '1') then exit; end if; end loop; schedule_in_streams <= schedule_in_next; --Schedule, next lane end if; end if; end if; end process; user_clock_0 : process begin user_clocks_i(0) <= '0'; wait for 20 ns; user_clocks_i(0) <= '1'; wait for 20 ns; end process; user_clock_1 : process begin user_clocks_i(1) <= '0'; wait for 15 ns; user_clocks_i(1) <= '1'; wait for 15 ns; end process; user_clock_2 : process begin user_clocks_i(2) <= '0'; wait for 10 ns; user_clocks_i(2) <= '1'; wait for 10 ns; end process; user_clock_3 : process begin user_clocks_i(3) <= '0'; wait for 5 ns; user_clocks_i(3) <= '1'; wait for 5 ns; end process; enabled_in: for i in 0 to c_input_streams - 1 generate begin in_streams_enabled(i) <= data_in_streams(i).enable; end generate enabled_in; enabled_out: for i in 0 to c_output_streams - 1 generate begin out_streams_enabled(i) <= data_out_streams(i).enable; end generate enabled_out; p_finished: process(dab_clk) begin if (rising_edge(dab_clk)) then if dab_rst_i = '0' then if(eof_i = '1' and (out_streams_finished = out_streams_enabled and in_streams_finished = in_streams_enabled) ) then report "*** End of simulation ***"; finish(0); end if; end if; end if; end process p_finished; end rtl;

gpl-2.0

a6334997d2da6a7dfcb4c72555827e87

jpidancet/mips

rtl/alu.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; library work; use work.mips_defs.ALL; entity alu is port (op : in alucontrol_type; a : in std_logic_vector(31 downto 0); b : in std_logic_vector(31 downto 0); shift : in std_logic_vector(4 downto 0); result : out std_logic_vector(31 downto 0); overflow : out std_logic); end entity alu; architecture rtl of alu is begin process (op, a, b) variable tmp : std_logic_vector(31 downto 0); begin case op is when ALU_SLL => result <= std_logic_vector(unsigned(b) sll to_integer(unsigned(shift))); overflow <= '0'; when ALU_SRL => result <= std_logic_vector(unsigned(b) srl to_integer(unsigned(shift))); overflow <= '0'; when ALU_AND => result <= a and b; overflow <= '0'; when ALU_OR => result <= a or b; overflow <= '0'; when ALU_XOR => result <= a xor b; overflow <= '0'; when ALU_NOR => result <= a nor b; overflow <= '0'; when ALU_ADD => tmp := a + b; result <= tmp; overflow <= (not a(31) and not b(31) and tmp(31)) or (a(31) and b(31) and not tmp(31)); when ALU_SUB => tmp := a - b; result <= tmp; overflow <= (not a(31) and b(31) and tmp(31)) or (a(31) and not b(31) and not tmp(31)); when ALU_SLT => if signed(a) < signed(b) then result <= (0 => '1', others => '0'); else result <= (others => '0'); end if; overflow <= '0'; when ALU_SLTU => if unsigned(a) < unsigned(b) then result <= (0 => '1', others => '0'); else result <= (others => '0'); end if; overflow <= '0'; when ALU_BPLUS4 => result <= b + 4; overflow <= '0'; end case; end process; end architecture rtl;

isc

dafe1ca6ead2f7f61ff3dd01e7641e2e

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_output_block.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block fnKWgUaCSOqW4UkV7KTA5KHnkoXkAb2Q6EROHzdT85wRehO7Bp2/qKeiQRmzk4OErZoVhcC/f8kQ w+EPkQ3ogw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block eJKqI8HhFxYftSk0GjwFmXDujn9dJbE4wcwqBdSjZ+EKpDlxN0as76LhbI0XFqbHtE/tcXTbBPhj nnNsDjsQWL/ZAP+l8koPdk9W56Ezy1OCf2LfOkXL7pSgc3m/cUGSj76G+GDuiAr99UJGFcRgmzcM FZ0NkcRsdxUDLlncB0Q= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block R/39QEgL3lQhXNpaZ/bVFCv8YTW7tzoVF9JPRkbopv8OLDCkTfBbDsONiZfacgTvB4EnLoMU7fWU SsTCEBE0Wj204nffuddAr4phNsu/i5vErtUCrFRYPgsLL55TwM9oF+im1cIHr4REaLPkFqrrVWDW XhSm43XpUkqrekcHJVOtMmCp5uCvCJpaSO5RvlW2utNuRUlIUHMRlccAjUSnYV7iBLNVZbNUpRO5 NVcPR1k+Wj6Z8akEI/nOFan+OTDCcm51bXXoE5/CrQ6coTeEmcnHZF4ZOt6O/d/d2ZSsEgVeehpz ygfsS/Xd8V8BC7gxWQnJOyeedqG9J5U0xMaEag== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block EZrXXPwe8Ykj0I7j8dobf/sku+pG5iRw9/bsB2jmZ41ObJ+pOv30287Uk7fKCI3kNXkzemuQMsOF NVWiSKM9rZZKyfHtzkQ94vkiB+FkFIRPVi4ZafpVK4hNWYDSKN348zQ0h53wgua5Ao3HK+hiZq0O T5cLR+YwW3RXHg5VNo4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block s/5aAaqHVD32pMacHasdrv9p8gjO70pwV+7r1OUiW+2tzrWAX2eXWSGnCr4A50uFnWUGmOECfpSC JrIErUBExG20sqfV4iIfW40lHj1Yf1hOISTYfT7yVpH3u4jBwRlPJPoDQ2nkn7Abwjw80Bt40BGY 0gk9YKLwiro+XRNwitLTDWbkk4owNR8CPq0krCUB2NvVXA369JqgtLZtYLLVz7D72JrVBifmAQsc 0w6zTi/xVnR6kFIXKI3sv7DPHBpW868Btz9Fz80HMbwWEpRgEbbDSuwD5RioY+qzM8PcYC3m6acC JcCk+GLYG63k84JSvF0AieOQcBJqzoY2bxXvzQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11024) `protect data_block uLR08VNMPncxxe4s7fv+OTTsoF5Fo206pFoEhY75lUfGHW18V4+RYDM5RWhAM6i/cGlyHlm4zISQ A6bHXFuOnQCvtmXOfn8g07TM4tLfbxT04xbr3vzuqEA4F0Bw3cdL9LmVV/XCObzMkPZeQYZ1c6pk GPzmDSPPSLk55ytj4TBLEHFYWFcz6xBZRP9M0hY4pmfO4nEdBJBageZqLvFCGkS5vHD6jSePQMah /UUiXrmcv9eMODbmdWFVbibuG00eADvF3fKFLuottkqrPyoLTUF2XR+a04gxFHaEVUSE7aX7jHqy Js9hQh1kRvGP8nAB0ADlnzk3u2nqxJbDS1B3W+skIL8aaOT4I6cHbMPn+1yXZTBiAFBHhr6BWOuj ORqnAwCqSW0wTraP4cck53RXoQv1+WBjRCim6dAOcMbwXPVCa3hpef1zdxG9OLH3Jl+6tJKbh7oH yB+89VQ8vF0aZc3hH4otvFf45dzbATKw5EuGFldSZamObwznVZqIH79GefFaqCgBH2c8+2ntjqlF olgc0OmTzufEjmOCUBFoVOga8tMduCF7Bclj/cHkpE1UkDhBahrk/SKoSAi0LVM78kQCmAxQ/ZpZ YR1UsA1/O7c8Eof/IHiDLiafqAuTiHTeyZnOeYsvKaEcFEX4Hm6C5jkZ4dPvoKDeZbe4adDmUlGA 94A0raQKOoBnyQ8W0Roa/nZ7SxHnveC0KE5OmdiHqx7MOWEQiOAubxT5AQWBx0dsX2iGHFwINCx9 H8GirKPbvVSOAOu381p11ssqZuLhsoRQeNzc3krP9A28iv+ZzVIca0It8Q1Txk5PKiqJIjNhRsX6 rfxFTMc9olfqXcEiHedEHctkE/fvK4Xqwc//2TZZ7L3jJFwVat/vINNH88PEPHo6Wv+hkEK4GhhT 4k2T1r7SgtMIUAsI8TCrao3QPl+S4xt0mp9jh01gp72Qz6h7jG1RITVttI55DIZhadwqnJtQakWA ZtBAMRGj5/yjYpbVE7JuAreOsgRaJOXrQ1YYxauu91Q2yxwNT1huBudCpymSNoS/j7l7jXO6jqXI BPoPkOk65WlLIhdsMTNyCHuDUD/ixXDELlU7w+fPWBTdi19FqDvFBzePnMmeGx3Bcc5TPFG1rmZr QL15bZqxuaXh0cBSRdr2C46rcEKhIihPX12G57pk7Jry/2I151uxtTI/tJ12dUryZhFAyeMLFTot 3Tk55CH6ZZVGVEI5HM4FzxO8D3Ehege0lycpwDY1yG4WPoIHEdVhYa+I6NmYjvdrJ7DWOuPGSzBH BXesG/d6LHTq6hFA0PIPXFmkEMKTq14VxPW5sGJv/qItBAmTGSuVkJnRP/rCv3XOx9FFgVb+M70E qcElWM3PaLzC0zemugXZnVypDoCYuFpYLEkzL4BvLRxxBz2yUEtNUhVh+RtFRfhWv9fiJ/MIFAE9 ivEVh46qDFQEOPZog38GHGXS/wHwr60z98MWQdaPt+cBk4QJSx+y+ODH3zp+KdjomuMA7npBgboL APd4n3tO32d3dZfT15U0DYZFaM8vRl+YAtsI7+Dkvek8tiCWI2gUx0WyDFAXNAC2zdvqa97hmHCg ptWbTf4yV+wY4GRjE1ogQ2fr7nO1lIIAq3XRkwyG8Hm39CvaQNbByjh0UAZ8y5DrS8IqZKGSe8wJ 7vNFG52cNtWU06YMPhg6dv5o3XUKqXBE5UYmWRbQeO2yhNqW4wF8LQ4dx/YfPeofMiC0paL4Y13F u5saQVFDwZ8ObD5CQNTFvMtjZtZ3Fvar8KYDNawccgseFxUVhm1wxPi3e4mSRIy5Xuehdy/fRiDs hqGbPePD9DVrkU+VkuT8SW4CGW4UwxrMKj7GYhcxwwpgoBG+0iGc8Xbcb+ClixDLTSNJR9Cxtq6c EIpWjIsl+frd4Mkh8sJCxVpwJzNpinvPIE4nk973HZPUKznvMEhcCgexTc8p6aWtnWWhxDxRvFKA OYTwH9yr1xG6T/dM0VSWnokZFqW7Q7meMOtxSDDJGYkrUD35ZK1FccldDViBZhKXLhlGfXBV6DYb BgvHrfkf4GONrkFZA8XhJXXK8ruEeSkU0H4IBN4RIwvWZpyNjC13+ndxkE/evc9p95I/AZZMLQD9 TmfRjRiZe2X5xATGIWtrh0L8GyeXmqlzQU1ErKdJiZg+VpFWRzIV7FaNCqx4Sw4p3o3Um7y/i3Y7 ez8qslAPxIUJx2JUCJGvq+MsAvkqehV5bigcsOxCDbUTlhUMCEc2OU43nxmT+hWl6T3e5hfYY0gO gqz5kWZzWKUuO9UkebfXhiQ40+nbaEdoLZ5czSm7Ntg+4toQoYZob4RCzRIZxDvHWYxEXaqszf0z rAbSFEdnTuR868XJqF29pGAvGzdGP6wNHtU2uum0UuKEXJIuHM5aQXvshmdj8Gm69+WS2sr1meGz JPYcmE/PpJ2/HuqtOecD8ec8Xc4ou+46luKbEHHsUNvyJsnRoTFanX2cyQI7pcG4D3VKDHwyKcqj rkz/c3IBM3O0v1FmFALZg+2Ahty9Tuaaa0Y/pUIVYzOZLv27k6QMkl8k270+sqm4JG+EOk7P1ntt qgJeeiS9Zh5ByuelgAC/pIskad0YMgNxgsE3DwUyvmS8a+SbaDWnijrmhaYqTr2+biK4wv+1PgAc BHTIFpoZS1/XaFsx+uYMga2q/hFQ96sxubm9/tO/hPyp9tQdMdK9xA9C8zEBYA5S3dFx3lRpmvK2 5M3gbERud9SqMiSPmgrxp4tK262ovLnLutWhueLOgbul7gjOFdc2IvrguCSOJweVwKn0yW5l8G8g JHiHUGQd/qHg3J1Shn3GdvTbiIMqBdbYkmdnJYHuofdZBh6lHwyh9MB1rCkdJF0/vllC6PR5YsOq G83tWZfR+SQcTVFjux/3mBL/eYFTH/1VoYB7STlqm2wa1drVZjUqR6GCSvJoT8mHsa+0mg3P5w1O wUxADLAq/kcafcply0gKIxxlFRvh66e4cmV+sc7SEZgkU+WNMRFLjhp857hsRRjAQ5Jr37VwytLX n2vvMah1BJbTYMrx5elONdVM4/zZOz2hA+78r0CZloTT79zxPzp/pHgMXQD1Jn6LcfObJN4QLm9r UdOz3qf8Hj/Ooi0Wui8AqbuXpcQcFwwAZ8ke3KX0BKXEl5hQe/RSuzwfDwRCPBhgKEW6lP5Q4326 VxxaVgCmH88sa124RWJvo8le/jb4DxkAUvRmp+551e3T1mkkDBb05sCO8tPUQw6tnw9R+OVP+WzG e5qg4NL0isxAoztqblaEOQsJIl/frhYKReokilZTC1lPkNvb6mUY6psBlL2KQ58t+LmErF9YjVpL E1QpHkpZ8BbgyAlIpEMj4kP7g5WqfGFobZEU7tFbP+7hf/JSvsy2zbKbLYetBqBlzO/KQzSmD5Of C2Ebe68oqV0oK/d9N0s6QGkKceBFmpUjqSZN/zL2w2pEf1n7qIX/1OPkOcE3S8OHRPwy4disbJsZ zMmqU4lRh95da7HdE8fXlzT3eb7sgulaAfKV1GZ7xTC37jKuBINBDTqzhXwHaBFXeS8vXBe8g5dl hFP7Sz9S/UEI6XVtvK575hW1UsvE9Lj64HMpBpOEIx4c7P7tfonukZahX4cRuGwnNiZiPo/ptvLI Oyw+OYYdyHlZRvdCT6QVE0DU0+sIOXLYgkMYun+VMX+ShJ8ejkk49rRDRtfBJXe7UNzWYgB768oB dMeZ0RnJYifVTZSOyPwwWwFcixt+TPokkVbuq2J5LmTessMd7RocZDn48vkHElZlM8r3JQSQdqjk /cxCP5Pa9WfUng/VxkFIskxdWTnpbKWfGIKODhybbgSjuQy/OrsHquDx6Np9uTwatLdqUUc33nIi 7bFWc36a7y+xgBnJJF9CoIffUTvEGBfAygEtvRcEvhYqsrimNK0ZsfDGw8olNPu5BiIiWRINhUmr hzWPPLIuKqfIKz4qvlrM2z/bbq86KTYurnv4vf/vtoSevAHt+FiQcjpcdH0PEN3Kk8sFz6RJQ2iQ hbA0b+ebcI97lbrihJjgcNyF4cYnb3dnmDNPxXlk30VpkFkm4YalJKaEC04MRCaZrb0ZB5MtVPbv Kj3yso91D97sSNo3fw3OaWBN7G4ycds6IiAfwUDgCK4btBfGvEgytavne6Fq0FPY/lYa8pGTf7+j 6D8Vay5jORy9F2hju42QwbIpZiOH3f5G3pmV3XPPpzbIZUIUWEdvK6S7K/m15i0tAP6qM56FC6yI llCxYqwxaeccESnyhk6zNOVJA5zDMniMr4L/vvKOXGTRCkS4oXhW/g2/fzR2KeizvxU7wydLhJmV U9Twjio2bzZgwrmVwszbWlrjUqZiexMsIb1k3Zj+YTNNsSRVddoOabLSCYRN/yUfuqT5yyXbBz+1 kmEOWAh5gRj9nhdjWDVLrBRzdq1LKzMDq0Jud27lHuED6NAeREj4KnkKCR1c5dG3+68n3R2Pixzq 8C0vombg7dweAuh0uk8801xeQJfpT03TXDu8CHkXnOrXEoPTrhabAb/1k3TYQAAkalC1xavaCNM6 zurS7tvbYAeZjL9FeHM7c1H8T/b35Cxe8XXszXyaAkjWt78baxwzRMhX+axNUcH1vvw1pTnpVeDt kmUz5e2ZRISGszCKaJoTr9aMRWWpG7bnE58jS5QYQ88+Yz/4f8mj27nVbOxZrsF3fb0CSB5/KQe4 q8N2qn9Zndk/fxalRI5YlXejRaPDsDXnyQNkBPcD6uA/dEQaivNIg/ZtHnt0XVE1/UJ0aFssex0R 8rpWLosO1y/zGFQEXz5qBCARoMLdkCJWyJSAA69kq9pVBKAr1heRdJ4qK5TsU9rJkSJOq8/qQv4u McRVr3K0GkjnSRhThCdg3mOLb5fToy8Os2nTqxhH14WwvqZb7LrhtxB3HJr4zemSthn6f/YbzKq2 Bju3oyraz9EscdAadI1Wk21DHScku0Jjl1OOqSOXgwARGgG444fZQtiUhmwN7tb5mqB7IEONjlAm bh/2Dn9bKFYFNLldSMf1Xmqb1Cqn4dm+7vhhmtUWoUDsGkFhYPVguYPHskCV5DYiFylXOadHbjhr AsolkGImB85ZghyfRQla6rExHXVBfjODKqo5R44NJfTBN3OH5j+5kCMzIyqs0gLXpRQ3Xm3atddL m4vJehWGkNWM3Rvk90mimhUaHPqlo/VFbZ0i71jYTMvyJgLd5gky4zhFYOy02Dy+bMZcQ2zw2OaW mLXpNiLflh2uKOZoGochlFDDicOJgSfUYD5Vy4E2v6mmB0aS6/RzdBENduCF5fwtDaQwt9CKqpyl IIriXUcOrR5VtBrpY2qWqCC0FnCmDz45tKSv0JOCHde2W4QsO0TV912Lbr0+op7gzGqEVKFnTV0s O56ukL9TIhH6gK2uKsrh5kfGCTCy+m/cbwMERQmHzDyd550tZZ80dhsPYWzV8hJmwhCw1AuE8UnP ZeH1WKGENsCja2ylP9pBKc9O0SV9jnZf5W4/re4DCAxVdzgsrGgLLUL85iGr6ptY9T4ojZa6s9ER tNJvofMknaXpjzRgCYQn4JfYC5DPqkbROY4lTOuv6WwYka1xoovTzExtDGkKWBvg5hRl7DNnY3Hj OvB5Cmf8db27zbP8/PVD+du6ZNCyZsr79qZT53tx6xtzugHS0O3G1e34/aKj5yvUPgcRWyENBcnG Zx/YMhvlwqdzh2f9AHGsFAhLLuuVdf0Sa/8eskb+Ny5hwaViWZO5rK3VJdHRimba6l6qdavl1TyY N4kfE42iEfeoFc8r8UJICgaQWSwfmjyVkV3v5tUMSZ9C9SK2NQvHbfzmfejMyIWiT4bagBxg2FQv saH7pwoU8j0YraqE8cGdQYLgmMZDZ8OoDkq14F9qyRwcNhRLhHebVyfs8KiyvfwrUXNOVKvSCKJ8 WAGTSLF2mk4n9auCkeIsK6xXO7ES4kYKh3dOKiYR2chrXPRHfQkp5pg8SKjuO1/jRUb9j/pxWMAJ NNWg/Kx28mOid5Xd5N9sBSWVwUwAfGUchcjTkbP/1BGMje+zv4XanSSXU8su/QVY7gp/hNSGDd5x XVubR+YTAtAD4yf25Y4qtwghr16OeSRuwWgEoBNUaERKHRbEL/ZXZ32v6ackwklqrigdk0g43OIl Y9iZv/XZOakf46F7ELwpNjh3HogrOqqURoiCCBSkcqU/rCbHfTssBpL6zcZ9Bw8PmXP5tOx5o39E u/f70XHVtoNHd4N6/sVirvo3Ce7HFf7AU35TSZ1TWb0HEOuYq/zVZLD7hqWxiu6WubPYCIfp2Le/ tP5dYqypIa1DuJ8cgqUE2QJVoGVkxgpfX/OjsgJa65CFxfp6BdYkbUteDPJ00cACHQk69Wc5Ao5U bfsXUJP67V9XGGHVN40ryTxYFjCBj9VGpylBRkF+TThYcwia6vs+JIlTPWQM2ojgSgUoei7zuIHw mVIb+0jgzeE34kXL/thTXQGdmFUseNg8GlzEUxibFKSaX5QbyKNqYTg2qUETq2lN7UPM5lTFzKmq xFttBJf1ui9O/wcG2+i2YE/ugQOfGw7bolNpFUdkHjmqy8wBMSXfAwRb6EHa4Vns40g+wvKnaePe aYw3wv4MwzxqPoj/hNKA804W1n5zjY07fG0R0H9e5NmV06sJW3QfTaBFHycBbPnxiv6nnd6tBHbO d2ca3oBJRFS9pC9I0sYK/IgD2ADBHeeamsq1XtWq2H9HLRC8rEDyW2v5I3K6QLQUZu//AzUDs2mJ mo9wajFYCDuDzXFGt1+/BIyJAzi+DSFhIikQaysaieUDQ3AxBnF7vTxCUa/6SA6DIq066yI3Pezv /J2BdVGZuKizwm4lVVdZyYrO6SchwTq152tFMiD3AZZTFF4RX+sPC2Iios50iFXudyruq2a9ECrk gPYxoisgZ++mf616yvBnqhfNIofhCpBGNCsNlEkWHN2Q8Pf4H40nBTSgCbldGNbXPnCX7c+vCv/Q vm+b0m4VMfEBGJsp0UT5Euvjy7FiANTf8P3D9r6Z+7rYoI5QqqEa+A3fiCIO61notnMWntL4s25F Jxfr9MO2lvejUz2B0SzW1Qw4+7irA2qWCAfrNDdiKM5QFbc7luBsNAdR5ejB4xKots5cWZt5BiR5 fzGcMkhBXUBn3dWZtlEOH235QZ6vVgud1JQPIYm6twm9fNqmzJwaDSXrCFzE9RKzlqG6l3PKVo7F NtcKMaF8g9me3CCremzjz6XVXCiu9DMWyjFKiF5Pl6HuYglL9I+yQgcLiZtEVUPn5vGnKrSs+AcJ dD7uLK9SHjIbtLYfPrUwPAWxPgTWNNAjAMM3YgM9G6fh4MSWpvPwBfJmcjp9ZEIsyswL2mLRy/Hy Sp7BjXV4P8D5fQ7F12QqzlWEvik46W/dIy09qjguhCuQpQZSJrJK9taa8VSlEBX6RxwFAnw/GRq2 lJ/uqsi6WKnXWYtDjkjCjTVxOeCnxqH7r9WlKzHJeLRhagk9OQjREIa3C98988kVfB6aAEwmwmv+ VkwlVg0LT54SpCETbGV0mBLBJQKBMy7SxE8ium6eYeas6qJIRwc4At6V0v0Q8AhLANwohMg8UWFp gukShji2zqg3Exg5kZmYjZbRKOlyUgi1ksZh/+SyeCD4Wc8cW1an5L+wzjpSE2qHmGGtsvk5Vtub o/6j3L0Z4ipmfj3ngv1UwMf7XURlhXeomyDsjyUsZI28QayGMb7j3byJL7ad7UGW1PnAht02l2ms TQIF/7m7cTVy2XlvpYrPZI7CHE0sk9JqlipuK/r11DocB8Xy2MoMRS9ffnEZch/WU1DGoizrdfGB zJyIsV1FORiscly5BZK0JASrxgBeVqh0gurYsa0GkqQ5UUPd0KgALwG1zY2/y+1tObt6QD0nhko4 jzD+3wryQ+7W47lH2bVchUcWNTh53faiQCTSv0o1HOb+//4pXQFMgy4fsycrmR6cTEwk/rRHi6N7 gknDyoXWgTHb3t5nxzPF3H2CnnxrIW708P/vgDjYfV/OGCQucQEOUw+CCVuct5DRAimr7myU/81q sB2TOjW2yyGucj93lnZEeVzVP4J4CgwB0cCSP+QyNihBty9U47UuaIwEJm4ksTB3/6PK4v7v5jqM XLXNXvLaH2fc//3V/jF2V9lkmL/CBeDpQsze5ljDexMo3sChZEe2AJxaNXxBehi5ij+ZHoYw2/M1 0qOvVzMfm8ZfkVbBhCQQuqaUaqCBdU0SuYxVQnr+5RIJ8gKRNGTbsKJWCsb7t4C+TRd0i2ImLDT9 V1WoD0rx7UtUBVUZXAbq84NZU9ijgS2ypMHbOBJ92ZhtSZ4Hu8Ykl/vgnaW62qsKf3cGe1yIYu4r Wdxap9HQukm35OplBfwJ37wZmYPE3xY9Rrbw10zm5HIwEcm6YKAhBbPLXx1+Rc8HzP7XiWJ1FYU6 /P5l8ZP0OPESFmsjZYLDKDH6VhTVD1CRVzDJ5mzRKWcREtFJnBSJY+/HS74armuI0pvIG/rJVmce Jynci7xbsR89+6ZZyEuhmF9VWqIfRjPc3kWLobFb88EWeZiXfGeKby/w5Ee2bU6MYzvi2dlQR4JF 47tT8zVTub9S2VzmSWVzJ4qPeU6ci3B54CV2O7PXAE/7qvQjtXGXstCZVtRquEc7xqWrTG9TP+0G sn09xjgejRgrWwT6rhC8ePU3p8EKSJsTztiKFBiZMguEIioqbY1vnp0ji+b0yrsQmSx+A/WkmKq5 SNiQes1/k9TIr2nTVNz7TAS4AsGnqV7b6lynsIsto68bU06BKwDUoyWT5vOUeS9NDnBmpKjMjjop MMa8eIuVkZHxO00ICYmCvusS7ErBGfCKUwM7FXK65T/5xW8y8dRH2tT/i3+hqqGIcGSW6ocAgpY6 Ua3KCBzWijXDQYeVLNxd3pAqfB0R2fFDvn9pvEbEzClifpFq4NIAlmvjz9lHgKDhl+rCEhmMPDse lkjOPKRhtKt7bWcDiVfg2RTd5k2AFGWSdvdke9FXaSXw9F/kvFhBmkwS6zoRVUoRAyyB9ORzI4zE wUJS+tNHhiER6YtCRWuKwXym30W0aTgtR5QFKOATYZ+f+ow7obpPGbWjfit3QMxtD1K/bWsSJlJ9 OAnB6edC6YznKIEdVqm6YTgEcQpdB/HoSP7K96bd0E+D6GlvbU5hybDRk0FF0y+9cckHYn/10sFx A0+HV6cwXazb8+boiWgGS5mhzcXml8InbriUsXfXmufjvDH7x+FIlra8gFZ7MFowe1V43BE1j1bB b9z3bWsN03rulbB7HNqYXdzJ9h3lvULCgn8mXEG87Ro72deMruScHBLu9HwlSd1EgovsQ9z1NU0c asp+WjSVtl2MgMf3nxyoHcNu4PdttGiYbSZZaVvPCivLzE7Jo+YAbDDgqyonnC9nabrF+XckOOxh VASe0hsvKsGa90uNu7kbvefSzcELesNunPeNDp1c8i4vhCuzQgLZMUh0gEmiAT4h1gkEpbiGKMYd 05mGC2K52qCCFxQLNtSJSXCFnmluz/k1N6+TaRbkNl2SJbj90o4shaR2q16Sb4i7LBKixxWs29RL YffDDAfPHm50Kbdwbu43EKZljSGo28Btgv8gbi1/wzlIVjNwTnViWu4dXvCgCdErP3PlOAp/TJY5 wGfT+s+OkRF5cuC91OrbQHmresNzYR4wE9PSKM7BG1WHYXNRpB4Zcs5kGLTqM4pwYNbp+ScV3FGx H7Gr6rHFyqPA+gm64QugkUuGIXuWKaErKSdl4bgEDcJtWPJ+htp1U/WWDSNIcH4YlLvvo0NkfspJ +1jDqHOTyunMbIEPJn8DNxgqqVfEQ+dfZCK0PKAix/TLwBPDUhmiTZTbpNCZ0onxLRYTANXzsY7z 5/rSwplbUvg2XB9isdSH+A3rDZPSkdSMh6m7IVn16Pr4aEbS+mFUF6zcMqh8g708Y/Y4ik6U7GDx /ofJ870k/8BQM/comHsq+Ed2Mmcy3AXUqaUazGSgl2zerwfLEwzd5mW2PIo6XiYRlSCmLZjNPJj8 LloP5CwgsTB6OzuHBOMYDGFMttMZMKMLQZS3I4sF+QhLY18jqZ3qZ0STNrGn5xc9+HKP4m5zSI1s rdwCKO0gscUVOAlr803m3yNyyyvqmg9ywjtbPBEn/GaGXKiFf+ThUuRU73PVLt2CpzNgseGu+Ddx 8iBqLaXsT4P+I0LL3alL69WsVAuampC0UF1CKQWPwb4QGrScLMJv8Pp7zw5rdfBKV25TF9+ac3G3 bYoMjAo+Np6/nb8QlZvEXal/zJJC0fee3s3ue1XXacm8z/iRycSdl9eBrGfcS9J/cuDxl/ZeZim4 cempFrEwaxtx+0SwV/MGWS4WDy3sUM2hjYNUHYTx3V11PvGfRwk8pkQBsk4iS+D+BEPseNRT/HwJ F1/HNEN2Gg2fxVrzwZDD+FhdoK6aQuhsIxUpyPWb5bL72hjpIivtXDEx5Qf9J5RPI0S8CMDGUs8Y nnh12Hno2mi/Zr7DW4RVp1nUu25/LFkNeLxpdWAWY+u0dKIhaGJBf5NHwUhpLrUk+RlsS1IZVP3b SY+IhSHZ8Oj50RntQu7/FWVAa1D9AsI9BuNegenwZxXdchcGYGaJsYzRHiKA8eIXtfdopwmcMMCa 8sfOezoUmKU8p1Si7qAgHiNO/OAgQbgI3hABqwbqcnbxDBUzHgSg3GAr0uqhD7Jem2z0tH1BkD2z neSHdC/1BZG6nq163kEVN1WBgTFU+8s6FXK6292SIZGzEjc1hnMt701v9WVByctfuJuPnGD7eso7 FFhS3bFrGRyQD9jOAxP/jQ+BU8fEjumXhGu8kcJK3KE/e+B7cLTy43KUSWLS2lH7xKETkXh3dGnR mdkCArY7EIHUg4gSiNbz+oRv+muC76D7G2g04S8RZRtq07ObEe+BgQs+ZcUm//WcsR6CPwRp1915 xtUpG8XT0VD+WbWRIxXEHvbjYTosLgqKs6WDPF5LgTp81bgW18VeVnsLI5d+lYrdhthlUZKjcxY9 kwxykqsaajvU5Lovc/GRtena/iufr+aJYe+F7hPYnOeeqS+gFM0clBHqh7SdqqvZE7bHpMfApRL3 zEiwhO1sgOzxwzmaZinT2plU+RPio2JnTgjvikw0sw+J6c9HK++7QYABlDxcKVzQatGiTP4QZYSb 5bINhIGnA9VLASHX/DqeLDikBN+z3YeQCq+vahaD9EnKV/by+1MefHhj1uEJO1NDP5lBDlKIFn9H H4KcHwnxdwjey8Tlr6kiXYjux1kNAkdfmZ+e15VNEdonfYowxdq7f2X3WWSBZrSrswQBaD4qb0iO Wpv6DOOjZmopXPjWmaTVBGPbVpgNnynoxOjYnGMmxq40WIZMeBRPG7R16IfNszKnNALX7dE3zxFT CZB/hvCylU8mfObjyOUWxOaEtFSDSahVi2sCi458EvIR4vZQfZYErDZ8gRg/XEu03L5zoUpHiq5t 5xvHiL809DTMCmwhseRMqCFfKj8QqAiC0+Z0pewR1VnZF62pMSOq0m6bBx+YWu8ZHKr1/Yjs7QAf Yc252BUBqYgcvB+xIn2c/DJz7VK4zCjtk6NAsamK+Ft8PcwT4eF3YNxKXVrS+1FYLpzWW2jMiUaY qCU+qH5D0G2pfDJTPCFBQ69KXnc1PrLa+uMGyITlCFO2rBHSdB6eJGWylRZ+m0/kv+DrBw/dENJN jpA6mQVfbpN0c3VvQozR6fsmQ72xyMH4Q7Fbyu5/564LkvZeFs/uTFXvoZL857STjcXaLL/9o1/N ibUbY1jSj6vgHmTjxWZIeN9NCv+q9pAs4NhotxUu3lq8Z6/mxdfCoKTbBiW988k/IyfR3HnT18a0 kmuaMuPidtaExgIJ+06tgNGf4P+qT4mfl7evSLALWwRtmJ/cqaQBVDaBhW7YVqO45wrcTfUy8kHR bvogfwoP5HLv3LF5WnYvB1X40BApB1Kns1JYqxjqi3L7xJZ0hbEWTmRL9hH1g+PBK+Tww9E3fIfz yao9bVOnCKRGnVTsHsUkQeCnSUZI6nZW3AylxCwCLMnMGd/k9eZhU+yx2EnI4B2/2Tr/1+yuGELn C/JnIkfQfcLZ5vwwL1v3OjxAMrmH3u69Wa/zlc+kD2yVs5cF0xybEnCG2G/keFsWCICxm2hvI1zt FH7TZ0pl9Dx0SQvh445IwNPVRKjZw4SpV/z89vdscmXqV24kefNE+HSHZskK2ubceReUVHeSsvvH 8aDA5ekExmE94idU44kFiWFeIE40N6/JOPtYfpBsWg4XdOFnLm2pJCkx0J1t2qtLOU3r2T3SVP2f /xZT38PikHO7948ZXh/SE0B/ipuZ69HWaODu45trjz3qq3WER0GL2XTpJwu2hb6wTErkn5NCDP7F beQtmXIU77sGETHRy8oRX5tPn+h0G8icRUyTsimp6OaNDMk9eWvd3MHJBfdrydP5wRMnVYtARi/q ZbuI2EdBkJ3+sDFtomCp3SmTD+FUgvcRVv2FMM/QjubS6m9KW9n32CPYVRgJhG0bcSdqnzOaZrop oC5DtrGwEdspG4COHK6G/2QAkpkeJL9cIIlv+BlD2LBqulv1pDTBgWh5PZmIAC/gq0C1Tpk6bUQ2 VzCLhivRQa2tVxN4j+7azATd4RTGT9jgv9xILGuUH/BSKUeEBl4HnBwvUkr8WxPf37kSWDOlRtCR DSBH2xObf8zFCOF1gWoqhf7jroAm8nfdPC267aH2aUKvGyvumBJI+ADsdrqNk7vnhtOYPg9R6XfA nDn4Qz6ZWEmCwhp4bZOnv4G8mC96I/zG/XaVFtCzV6r47vd85R4uUbdNzN+PHZZAkr/+diQ71iFK ciRO+IunpK1qsPGMa15fdBdY6yEp5006MoDvNB0AdMxcuRLmf9dTeH+sEW0iwlVtnpnC8pyPTLcV KpnLJKYe+GzFlkQiZLL527ZOO/LC35RCS0OlL0PBv8P9wzFFg5eXXlz7hldx6CaNPu898TY5HrFM LSTBk+yWM/w5SVFueJoJSp6tLmxhUH6Af8jeCJKwwjXBvK18bQjTS3enxie0CX8T07EDYosVeanq guhHWY5BN3/zc4NpQgOFtgpvK1hTXhaotoyMKSCzYDAls0lEnmbDvoDjPxxjGqIwYGZ7dfOjuEce R4pG/stv32HiYDFcS1irlRI/ggaK2D8yV4rgZzVJkfIgRbjjzvdjwKOUfLXZvOhvjNAgfilaCi8H v28hUYV5QTgQgqirLa5s8LTdJct7wxWWu0I57nYPzE66u6A601Py4yE6046JGjiKhm4YBEVZaLSB dZSKKWH41yQCoZRnjnEOiURYCR7BYEn7RaOp+Wl4/CkdlbXNipsM8upRYK76N4YogMYMK0VeJ5uS o28dpzzMoe7VRfYHek5ehRpLZGkA7gYZ08Jp5Vb74+rKX/Hta+l9fyuFIbXJC8swNPXUCGT54R/P tNerW+BxipxJrN6YMOFXknfBODaOxt7+hJsvRY2IJ4panBlot8CEgYFGuGqjXADcbmY10i3UiAVW jfVxs3KodgaLqQYMHXiboFMuBppWpVhLvImWlWG0XFO/6qDYWUgeLtyo33sP8m9TRTalJ+ynRPkr +XHD6elLAEW9ysMkcgG2bgBWT9MJhpf6qM7EGphVSBcdBAaU37CtD014aQR3DC1H/xmOhig1TkhU I7XzvD8q2vV0RvXa9tNGz3lEPb5yEgBv3H9HABqIzzYmkjCmws59v704kmoXl+FPqLxR2qNgHIY7 bmKUqZ3WqkanjPNE3i9qA85r7t4HAD6v0ygb98p0G3aGc2LLN1Je2D7ZLVgm60Po0OrogN5gidEk aEPkNSvkuyjAQWdlHLVxNXDgYbzT/b8JRUu1eHTBvM/Y36xc/WavU4whrOmwLV93MLimYYsL2LI/ X6ArDisZ9WRTDMtJyia0iEGLpe4etJm6IVgJhZDQqcfrBXRYLGoDK5ug6zuodQwoPzAqpENbNE/p z/sp/PrRQjuRzFh6DVeX35jtTCHcSBxlhDP0P/jpMQlS3se8sATomISbEMB9TIT7LuYltEKvuwj9 tq5QrTduj7MiZ4TuU+bCvVO+fnpbCq7I0Trwma6BIoyvFW1Zlsx9zujJX8gg/KfRX2jYWH1abraz DKovbSddClJ6h/nlcxYnlWs4l/5uHpXH8aaJN9HKCpht84HNPHRXPBm4KrA5u+2MG+hjg+pxSMyr oB7pMwpuesOzuAXgfhmmsPscHUYrK3u9mP3wlk2/41/Y0a2z8sI/x4ss5fUem6CJ2KAHzdQgF2yj fOnmjJ0tOljWf4A4quOZvpv+g/SVnBanrZ+6XIWAv+TBz+ieRq/SGrPtUEqLu31mNtU3v/J/Eez4 8HdExEyAlI+/BhphZdf47YBL6uC4O5LRcjKIxcwwfueqzeZQiVu3+OmNnK8VjoudLaLL/fa4m1ag sW6a936sfKhktWgJRVhuUB2KinMRglcDnIJAnHLF7Az+xUQLuQeZZjpezIO6guecxaTcXPLiv/Pm yARExhbpn/XdfEDMhrF8TjyZQeR9MD+vZxoZnev0Qdvw0k6io2d1d3usT6mIYdulkgNpCuNVe2UI 3e4YEVh0mp4uUy0MPcHcqNKJObWzAKUGwgkv3upe8dQ1pSbsx6G+QJMBMm6UENSc4rzsykei7SUG rgJ1zB7l/SCwT+8/PChgQl2NX06jZRo= `protect end_protected

mit

e3cca48a2dc3a1bc405f9708ee4f4ad1

malkadi/FGPU

RTL/CU_mem_cntrl.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity CU_mem_cntrl is --{{{ port( clk : in std_logic; -- from the CV cv_wrData : in SLV32_ARRAY(CV_SIZE-1 downto 0); -- level 17. cv_addr : in GMEM_ADDR_ARRAY; -- level 17. cv_gmem_we : in std_logic; cv_gmem_re : in std_logic; cv_gmem_atomic : in std_logic; cv_lmem_rqst : in std_logic; -- level 17. cv_lmem_we : in std_logic; cv_op_type : in std_logic_vector(2 downto 0); -- level 17. cv_alu_en : in std_logic_vector(CV_SIZE-1 downto 0); cv_alu_en_pri_enc : in integer range 0 to CV_SIZE-1 := 0; cv_rd_addr : in unsigned(REG_FILE_W-1 downto 0); -- to the CV regFile_wrAddr : out unsigned(REG_FILE_W-1 downto 0) := (others=>'0'); -- stage -1 (stable for 3 clock cycles) regFile_we : out std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- stage 0 (stable for 2 clock cycles) (level 20. for loads from lmem) regFile_wrData : out SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- stage 0 (stable for 2 clock cycles) regFile_we_lmem_p0 : out std_logic := '0'; -- level 19. -- interface to the global memory controller cache_rdAck : in std_logic := '0'; cache_rdAddr : in unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); cache_rdData : in std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0); atomic_rdData : in std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); atomic_rdData_v : in std_logic := '0'; atomic_sgntr : in std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0'); gmem_wrData : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); gmem_valid : out std_logic := '0'; gmem_we : out std_logic_vector(DATA_W/8-1 downto 0) := (others=>'0'); gmem_rnw : out std_logic := '0'; gmem_atomic : out std_logic := '0'; gmem_atomic_sgntr : out std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0'); gmem_ready : in std_logic; gmem_rqst_addr : out unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0'); -- to CU scheduler wf_finish : out std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); finish_exec : in std_logic := '0'; cntrl_idle : out std_logic := '0'; nrst : in std_logic ); end entity; --}}} architecture Behavioral of CU_mem_cntrl is -- signals definitions ---------------------------------------------------------------------{{{ -- internal signals definitions {{{ signal gmem_valid_i : std_logic := '0'; signal regFile_wrAddr_i : unsigned(REG_FILE_W-1 downto 0) := (others=>'0'); signal cntrl_idle_i : std_logic := '0'; -- }}} -- constants & functions {{{ constant N_STATIONS : natural := CV_SIZE*N_STATIONS_ALU; type stations_for_alu_array is array(CV_SIZE-1 downto 0) of nat_array(N_STATIONS_ALU-1 downto 0); -- functions ------------------------------------------------------------------ {{{ function distribute_stations_on_ALUs(n_stations: integer; n_alus: integer) return nat_array is variable res: nat_array(n_stations-1 downto 0) := (others=>0); begin for i in 0 to n_stations-1 loop for k in 0 to n_alus-1 loop if i < (k+1)*(n_stations/n_alus) and i >= k*(n_stations/n_alus) then res(i) := k; exit; end if; end loop; end loop; return res; end function; function order_stations_by_priority(n_stations: integer; n_alus: integer) return nat_array is -- variable res: nat_array(n_stations-1 downto 0) := (0=>13, 1=>15, 2=>0, 3=>2, 4=>4, 5=>6, 6=>8, 7=>10, 8=>12, 9=>14, 10=>1, 11=>3, 12=>5, 13=>7, 14=>9, 15=>11); -- variable res: nat_array(n_stations-1 downto 0) := (0=>9, 1=>11, 2=>13, 3=>15, 4=>0, 5=>2, 6=>4, 7=>6, 8=>8, 9=>10, 10=>12, 11=>14, 12=>1, 13=>3, 14=>5, 15=>7); variable res: nat_array(n_stations-1 downto 0) := (others=>0); begin -- if n_stations /= 16 or n_alus /= 8 then for i in 0 to n_alus-1 loop for j in 0 to n_stations/n_alus -1 loop res(i + j*n_alus) := i*n_stations/n_alus + j; end loop; end loop; -- end if; return res; end function; function distribute_alus_on_stations(n_stations: natural; n_alus: natural) return stations_for_alu_array is variable res: stations_for_alu_array := (others=>(others=>0)); begin for k in 0 to n_alus-1 loop for j in 0 to (n_stations/n_alus)-1 loop res(k)(j) := k*n_stations/n_alus + j; end loop; end loop; return res; end function; -------------------------------------------------------------------------------------}}} --station signals constant c_alu_for_stations : nat_array(N_STATIONS-1 downto 0) := distribute_stations_on_ALUs(N_STATIONS, CV_SIZE); constant c_stations_for_alus : stations_for_alu_array := distribute_alus_on_stations(N_STATIONS, CV_SIZE); constant c_stations_ordered_for_priority: nat_array(N_STATIONS-1 downto 0) := order_stations_by_priority(N_STATIONS, CV_SIZE); --- }}} -- finish signals {{{ type st_finish_type is (idle, serving, finished); type st_finish_array_type is array (natural range<>) of st_finish_type; signal st_finish, st_finish_n : st_finish_array_type(N_WF_CU-1 downto 0) := (others=>idle); signal check_finish : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal check_finish_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wf_finish_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal wfs_being_served : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); -- }}} -- stations signals {{{ type st_station_type is (idle, get_ticket, wait_read_done, write_back, wait_atomic); type st_station_array is array(natural range <>) of st_station_type; signal st_stations, st_stations_n : st_station_array(N_STATIONS-1 downto 0) := (others=>idle); signal station_gmem_addr : gmem_addr_array(N_STATIONS-1 downto 0) := (others=>(others=>'0')); signal station_gmem_addr_n : gmem_addr_array(N_STATIONS-1 downto 0) := (others=>(others=>'0')); signal station_rd_addr : reg_addr_array(N_STATIONS-1 downto 0) := (others=>(others=>'0')); signal station_rd_addr_n : reg_addr_array(N_STATIONS-1 downto 0) := (others=>(others=>'0')); signal station_free, station_free_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_wait_atomic : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_wait_atomic_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_go, station_go_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_rnw, station_rnw_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_atomic, station_atomic_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_perfomed : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_perfomed_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_rdData_n, station_rdData : SLV32_ARRAY(N_STATIONS-1 downto 0) := (others=>(others=>'0')); signal station_wrData_n, station_wrData : SLV32_ARRAY(N_STATIONS-1 downto 0) := (others=>(others=>'0')); type op_type_array is array (natural range <>) of std_logic_vector(2 downto 0); signal station_op_type : op_type_array(N_STATIONS-1 downto 0) := (others=>(others=>'0')); signal station_op_type_n : op_type_array(N_STATIONS-1 downto 0) := (others=>(others=>'0')); signal station_written_back : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_written_back_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal regFile_we_latch : std_logic := '0'; signal regFile_we_latch_p0 : std_logic := '0'; signal regFile_we_latch_p0_n : std_logic := '0'; signal ticket_granted : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal stations_prefered : integer range 0 to N_STATIONS_ALU-1 := 0; signal station_read_performed_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_atomic_perormed : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal atomic_rdData_v_d0 : std_logic := '0'; signal atomic_rdData_v_d1 : std_logic := '0'; signal atomic_rdData_d0 : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); signal atomic_rdData_d1 : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); attribute max_fanout of atomic_rdData_d1 : signal is 10; signal atomic_sgntr_d0 : std_logic_vector(N_CU_STATIONS_W-1 downto 0) := (others=>'0'); signal station_last_atomic_serve : integer range 0 to N_STATIONS-1 := 0; signal station_wf_indx : wf_active_array(N_STATIONS-1 downto 0) := (others=>(others=>'0')); signal station_wf_indx_n : wf_active_array(N_STATIONS-1 downto 0) := (others=>(others=>'0')); -- }}} -- memory requests buffer {{{ -- 0..31: DATA, 32:63: ADDR, 64:re, 65:atomic, 66..68: op_type, 69:alu_en, 70..80: rd_addr constant MEM_RQST_W : integer := DATA_W+GMEM_ADDR_W+1+1+3+1+REG_FILE_W; constant MEM_RQST_DATA_LOW : integer := 0; constant MEM_RQST_DATA_HIGH : integer := MEM_RQST_DATA_LOW+DATA_W-1; -- 31 constant MEM_RQST_ADDR_LOW : integer := MEM_RQST_DATA_HIGH+1; -- 32 constant MEM_RQST_ADDR_HIGH : integer := MEM_RQST_ADDR_LOW+GMEM_ADDR_W-1; -- 63 constant MEM_RQST_RE_POS : integer := MEM_RQST_ADDR_HIGH+1; -- 64 constant MEM_RQST_ATOMIC_POS : integer := MEM_RQST_RE_POS+1; -- 65 constant MEM_RQST_OP_TYPE_LOW : integer := MEM_RQST_ATOMIC_POS+1; -- 66 constant MEM_RQST_OP_TYPE_HIGH : integer := MEM_RQST_OP_TYPE_LOW+2; -- 68 constant MEM_RQST_ALU_EN_POS : integer := MEM_RQST_OP_TYPE_HIGH+1; -- 69 constant MEM_RQST_RD_ADDR_LOW : integer := MEM_RQST_ALU_EN_POS+1; -- 70 constant MEM_RQST_RD_ADDR_HIGH : integer := MEM_RQST_RD_ADDR_LOW+REG_FILE_W-1; -- 80 type mem_rqsts_buffer_type is array(natural range <>) of std_logic_vector(CV_SIZE*MEM_RQST_W-1 downto 0); signal mem_rqsts : mem_rqsts_buffer_type(N_WF_CU*2**(PHASE_W)-1 downto 0) := (others=>(others=>'0')); signal mem_rqsts_data : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- alias signal mem_rqsts_addr : gmem_addr_array(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- alias signal mem_rqsts_re : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); --alias signal mem_rqsts_atomic : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); --alias signal mem_rqsts_op_type : op_type_array(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- alias signal mem_rqsts_rd_addr : reg_addr_array(CV_SIZE-1 downto 0) := (others=>(others=>'0')); -- alias signal mem_rqsts_alu_en : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); --alias signal mem_rqsts_rdAddr : unsigned(N_WF_CU_W+PHASE_W-1 downto 0) := (others=>'0'); signal mem_rqsts_rdAddr_inc_n : std_logic := '0'; signal mem_rqsts_wrAddr : unsigned(N_WF_CU_W+PHASE_W-1 downto 0) := (others=>'0'); type mem_rqsts_array is array(natural range <>) of std_logic_vector(MEM_RQST_W-1 downto 0); signal mem_rqsts_rdData_n : std_logic_vector(CV_SIZE*MEM_RQST_W-1 downto 0) := (others=>'0'); signal mem_rqsts_rdData : std_logic_vector(CV_SIZE*MEM_RQST_W-1 downto 0) := (others=>'0'); signal mem_rqsts_rdData_ltchd_n : mem_rqsts_array(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal mem_rqsts_rdData_ltchd : mem_rqsts_array(CV_SIZE-1 downto 0) := (others=>(others=>'0')); attribute max_fanout of mem_rqsts_rdData_ltchd : signal is 300; signal mem_rqsts_phase_ltchd : std_logic_vector(PHASE_W-1 downto 0) := (others=>'0'); signal mem_rqsts_phase_ltchd_n : std_logic_vector(PHASE_W-1 downto 0) := (others=>'0'); signal mem_rqsts_wf_indx_ltchd : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal mem_rqsts_wf_indx_ltchd_n : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); signal mem_rqsts_wrData : std_logic_vector(CV_SIZE*MEM_RQST_W-1 downto 0) := (others=>'0'); signal mem_rqsts_we : std_logic := '0'; signal mem_rqst_waiting : std_logic := '0'; signal mem_rqst_waiting_p0 : std_logic := '0'; signal mem_rqsts_nserved : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); signal mem_rqsts_nserved_n : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- }}} -- CV side signals {{{ type st_cv_side_type is (get_rqst, fill_stations, wait_update); signal st_cv_side, st_cv_side_n : st_cv_side_type := get_rqst; signal latch_rdData, latch_rdData_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); -- }}} -- regFile signals {{{ type regFile_interface_type is (choose_rd_addr, update, wait_1_cycle, wait_scratchpad); signal st_regFile_int, st_regFile_int_n : regFile_interface_type := choose_rd_addr; signal regFile_wrAddr_p0_n : unsigned(REG_FILE_W-1 downto 0) := (others=>'0'); signal regFile_wrAddr_p0 : unsigned(REG_FILE_W-1 downto 0) := (others=>'0'); signal regFile_we_p0_n, regFile_we_p0 : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); -- }}} -- signals of the request waiting to be processed {{{ type st_waiting_type is (free, one_serve_zero_wait, one_serve_one_wait, zero_serve_one_wait); type cv_wrData_waiting_type is array(natural range <>) of SLV32_ARRAY(CV_SIZE-1 downto 0); type cv_addr_waiting_type is array(natural range <>) of GMEM_ADDR_ARRAY(CV_SIZE-1 downto 0); -- }}} -- mem interface {{{ signal station_get_ticket : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); signal station_get_ticket_n : std_logic_vector(N_STATIONS-1 downto 0) := (others=>'0'); -- fifo line -- addr station_sgntr atomic data rnw we -- GMEM_WORD_ADDR_W N_CU_STATIONS_W 1 DATA_W 1 DATA_W/8 type fifo_type is array (natural range <>) of std_logic_vector(DATA_W+1+DATA_W/8+N_CU_STATIONS_W downto 0); type fifo_addr_type is array (natural range <>) of std_logic_vector(GMEM_ADDR_W-1 downto 0); signal fifo : fifo_type(2**FIFO_ADDR_W-1 downto 0) := (others=>(others=>'0')); signal fifo_addr : fifo_addr_type(2**FIFO_ADDR_W-1 downto 0) := (others=>(others=>'0')); signal fifo_wrAddr, fifo_rdAddr : unsigned(FIFO_ADDR_W-1 downto 0) := (others=>'0'); signal fifo_wrAddr_n, fifo_rdAddr_n : unsigned(FIFO_ADDR_W-1 downto 0) := (others=>'0'); signal push, push_d0 : std_logic := '0'; signal push_rqst_fifo_n : std_logic := '0'; signal fifo_full : std_logic := '0'; signal pop : std_logic := '0'; signal din_rqst_fifo, din_rqst_fifo_d0 : std_logic_vector(DATA_W+1+DATA_W/8+N_CU_STATIONS_W downto 0) := (others=>'0'); signal din_rqst_fifo_addr : std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); signal din_rqst_fifo_addr_d0 : std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0'); signal station_slctd_indx, station_slctd_indx_n : natural range 0 to N_STATIONS-1 := 0; attribute max_fanout of station_slctd_indx : signal is 60; --extra constant c_rqst_fifo_addr_valid_len : natural := 3; signal din_rqst_fifo_addr_d0_v : unsigned(c_rqst_fifo_addr_valid_len-1 downto 0) := (others=>'0'); signal fifo_dout : fifo_type(CV_TO_CACHE_SLICE-1 downto 0) := (others=>(others=>'0')); signal fifo_addr_dout : fifo_addr_type(CV_TO_CACHE_SLICE-1 downto 0) := (others=>(others=>'0')); signal gmem_valid_vec : std_logic_vector(CV_TO_CACHE_SLICE-1 downto 0) := (others=>'0'); signal pop_vec : std_logic_vector(CV_TO_CACHE_SLICE-1 downto 0) := (others=>'0'); signal lmem_rdData : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal lmem_rdData_d0 : SLV32_ARRAY(CV_SIZE-1 downto 0) := (others=>(others=>'0')); signal lmem_rdData_v : std_logic := '0'; signal lmem_rdData_alu_en : std_logic_vector(CV_SIZE-1 downto 0) := (others=>'0'); signal lmem_rdData_rd_addr : unsigned(REG_FILE_W-1 downto 0) := (others=>'0'); signal sp : unsigned(LMEM_ADDR_W-N_WF_CU_W-PHASE_W-1 downto 0) := (others=>'0'); -- }}} -- read cache buffer signals ----------------------------------------------------------------------------{{{ signal rd_fifo_data, rd_fifo_data_d0 : std_logic_vector(DATA_W*RD_CACHE_N_WORDS-1 downto 0) := (others=>'0'); attribute max_fanout of rd_fifo_data_d0 : signal is 8; --extra signal rd_fifo_addr : unsigned(GMEM_WORD_ADDR_W-RD_CACHE_N_WORDS_W-1 downto 0) := (others=>'0'); signal rd_fifo_v : std_logic := '0'; ---------------------------------------------------------------------------------------------------------}}} ------------------------------------------------------------------------------------------------}}} begin -- internal signals assignments -------------------------------------------------------------------------{{{ regFile_wrAddr <= regFile_wrAddr_i; assert CV_TO_CACHE_SLICE > 0 severity failure; cntrl_idle <= cntrl_idle_i; ---------------------------------------------------------------------------------------------------------}}} -- CV interface (get requests) -------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then mem_rqsts_rdData_n <= mem_rqsts(to_integer(mem_rqsts_rdAddr)); if mem_rqsts_we = '1' then mem_rqsts(to_integer(mem_rqsts_wrAddr)) <= mem_rqsts_wrData; end if; mem_rqsts_rdData <= mem_rqsts_rdData_n; mem_rqsts_we <= '0'; if cv_gmem_re = '1' or cv_gmem_we = '1' or (ATOMIC_IMPLEMENT /= 0 and cv_gmem_atomic = '1') then mem_rqsts_we <= '1'; end if; for i in 0 to CV_SIZE-1 loop mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_DATA_HIGH downto i*MEM_RQST_W+MEM_RQST_DATA_LOW) <= cv_wrData(i); mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_ADDR_HIGH downto i*MEM_RQST_W+MEM_RQST_ADDR_LOW) <= std_logic_vector(cv_addr(i)); mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_RE_POS) <= cv_gmem_re; if ATOMIC_IMPLEMENT /= 0 then mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_ATOMIC_POS) <= cv_gmem_atomic; end if; mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_OP_TYPE_HIGH downto i*MEM_RQST_W+MEM_RQST_OP_TYPE_LOW) <= cv_op_type; mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_ALU_EN_POS) <= cv_alu_en(i); mem_rqsts_wrData(i*MEM_RQST_W+MEM_RQST_RD_ADDR_HIGH downto i*MEM_RQST_W+MEM_RQST_RD_ADDR_LOW) <= std_logic_vector(cv_rd_addr); end loop; mem_rqst_waiting_p0 <= '0'; if mem_rqsts_wrAddr /= mem_rqsts_rdAddr then mem_rqst_waiting_p0 <= '1'; end if; mem_rqst_waiting <= mem_rqst_waiting_p0; if nrst = '0' then mem_rqsts_wrAddr <= (others=>'0'); mem_rqsts_rdAddr <= (others=>'0'); else if mem_rqsts_we = '1' then mem_rqsts_wrAddr <= mem_rqsts_wrAddr + 1; end if; if mem_rqsts_rdAddr_inc_n = '1' then mem_rqsts_rdAddr <= mem_rqsts_rdAddr + 1; end if; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- CV interface (schedule requests) -------------------------------------------------------------------{{{ cv_side_trans: process(clk) begin if rising_edge(clk) then station_go <= station_go_n; mem_rqsts_rdData_ltchd <= mem_rqsts_rdData_ltchd_n; mem_rqsts_phase_ltchd <= mem_rqsts_phase_ltchd_n; mem_rqsts_wf_indx_ltchd <= mem_rqsts_wf_indx_ltchd_n; mem_rqsts_nserved <= mem_rqsts_nserved_n; check_finish <= check_finish_n; if nrst = '0' then st_cv_side <= get_rqst; else st_cv_side <= st_cv_side_n; end if; end if; end process; cv_side_comb: process(st_cv_side, mem_rqst_waiting, station_free, mem_rqsts_rdData, mem_rqsts_nserved, mem_rqsts_phase_ltchd, mem_rqsts_rdData_ltchd, mem_rqsts_wf_indx_ltchd) begin st_cv_side_n <= st_cv_side; station_go_n <= (others=>'0'); mem_rqsts_rdAddr_inc_n <= '0'; mem_rqsts_nserved_n <= mem_rqsts_nserved; check_finish_n <= (others=>'0'); mem_rqsts_rdData_ltchd_n <= mem_rqsts_rdData_ltchd; mem_rqsts_wf_indx_ltchd_n <= mem_rqsts_wf_indx_ltchd; mem_rqsts_phase_ltchd_n <= mem_rqsts_phase_ltchd; case st_cv_side is when get_rqst => for i in 0 to CV_SIZE-1 loop mem_rqsts_rdData_ltchd_n(i) <= mem_rqsts_rdData((i+1)*MEM_RQST_W-1 downto i*MEM_RQST_W); end loop; -- latch wf_indx and phase from first ALU mem_rqsts_wf_indx_ltchd_n <= (others=>'0'); mem_rqsts_wf_indx_ltchd_n(to_integer(unsigned( mem_rqsts_rdData(MEM_RQST_RD_ADDR_LOW+WI_REG_ADDR_W+N_WF_CU_W-1 downto MEM_RQST_RD_ADDR_LOW+WI_REG_ADDR_W)))) <= '1'; mem_rqsts_phase_ltchd_n(1 downto 0) <= mem_rqsts_rdData(MEM_RQST_RD_ADDR_HIGH downto MEM_RQST_RD_ADDR_HIGH-1); mem_rqsts_phase_ltchd_n(2) <= mem_rqsts_rdData(MEM_RQST_RD_ADDR_HIGH-2); for i in 0 to CV_SIZE-1 loop mem_rqsts_nserved_n(i) <= mem_rqsts_rdData(i*MEM_RQST_W + MEM_RQST_ALU_EN_POS); end loop; if mem_rqst_waiting = '1' then st_cv_side_n <= fill_stations; mem_rqsts_rdAddr_inc_n <= '1'; end if; when fill_stations => for i in 0 to cv_size-1 loop for j in 0 to n_stations_alu-1 loop if station_free(c_stations_for_alus(i)(j)) = '1' and mem_rqsts_nserved(i) = '1' then station_go_n(c_stations_for_alus(i)(j)) <= '1'; mem_rqsts_nserved_n(i) <= '0'; exit; end if; end loop; end loop; if mem_rqsts_nserved = (mem_rqsts_nserved'reverse_range => '0') then st_cv_side_n <= wait_update; end if; when wait_update => -- necessary to wait for mem_rqsts_rdData to be ready in case no alu was enabled st_cv_side_n <= get_rqst; if mem_rqsts_phase_ltchd = (mem_rqsts_phase_ltchd'reverse_range=>'1') then check_finish_n <= mem_rqsts_wf_indx_ltchd; end if; end case; end process; ----------------------------------------------------------------------------------------- }}} -- gmem controller interface -------------------------------------------------------------------------------------------{{{ -- fifo {{{ process(clk) begin if rising_edge(clk) then if nrst = '0' then gmem_valid_vec <= (others=>'0'); else if pop = '1' or gmem_valid_vec /= (gmem_valid_vec'reverse_range=>'1') then gmem_valid_vec(gmem_valid_vec'high) <= gmem_valid_i; end if; for i in CV_TO_CACHE_SLICE-1 downto 1 loop if pop = '1' or gmem_valid_vec(i-1 downto 0) /= (i-1 downto 0=>'1') then gmem_valid_vec(i-1) <= gmem_valid_vec(i); end if; end loop; end if; if push_d0 = '1' then fifo(to_integer(fifo_wrAddr)) <= din_rqst_fifo_d0; fifo_addr(to_integer(fifo_wrAddr)) <= din_rqst_fifo_addr_d0; end if; if pop = '1' or gmem_valid_vec /= (gmem_valid_vec'reverse_range=>'1') then fifo_addr_dout(fifo_addr_dout'high) <= fifo_addr(to_integer(fifo_rdAddr)); fifo_dout(fifo_dout'high) <= fifo(to_integer(fifo_rdAddr)); end if; for i in CV_TO_CACHE_SLICE-1 downto 1 loop if pop = '1' or gmem_valid_vec(i-1 downto 0) /= (i-1 downto 0=>'1') then fifo_addr_dout(i-1) <= fifo_addr_dout(i); fifo_dout(i-1) <= fifo_dout(i); end if; end loop; if pop = '1' or gmem_valid_vec(CV_TO_CACHE_SLICE-2 downto 0) /= (0 to CV_TO_CACHE_SLICE-2 =>'1') then if SUB_INTEGER_IMPLEMENT /= 0 then case fifo_dout(CV_TO_CACHE_SLICE-1)(DATA_W+1+DATA_W/8)&fifo_dout(CV_TO_CACHE_SLICE-1)(2 downto 0) is -- DATA_W+1+DATA_W/8 for atomic bit when "0001" => -- byte case fifo_addr_dout(CV_TO_CACHE_SLICE-1)(1 downto 0) is when "00" => -- 1st byte fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "0001"; when "01" => -- 2nd byte fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "0010"; fifo_dout(CV_TO_CACHE_SLICE-2)(2*8+5-1 downto 5+8) <= fifo_dout(CV_TO_CACHE_SLICE-1)(7+5 downto 5); when "10" => -- 3rd byte fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "0100"; fifo_dout(CV_TO_CACHE_SLICE-2)(3*8+5-1 downto 5+2*8) <= fifo_dout(CV_TO_CACHE_SLICE-1)(7+5 downto 5); when others => -- 4th byte fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "1000"; fifo_dout(CV_TO_CACHE_SLICE-2)(4*8+5-1 downto 5+3*8) <= fifo_dout(CV_TO_CACHE_SLICE-1)(7+5 downto 5); end case; when "0010" => -- half case fifo_addr_dout(CV_TO_CACHE_SLICE-1)(1) is when '0' => -- 1st half fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "0011"; when others => -- 2nd half fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= "1100"; fifo_dout(CV_TO_CACHE_SLICE-2)(4*8+5-1 downto 5+2*8) <= fifo_dout(CV_TO_CACHE_SLICE-1)(2*8+5-1 downto 5); end case; when "0100" => -- word fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= (others=>'1'); when others=> fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= '0'&fifo_dout(CV_TO_CACHE_SLICE-1)(2 downto 0); end case; else case fifo_dout(CV_TO_CACHE_SLICE-1)(DATA_W+1+DATA_W/8)&fifo_dout(CV_TO_CACHE_SLICE-1)(2 downto 0) is -- DATA_W+1+DATA_W/8 for atomic bit when "0100" => -- word fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= (others=>'1'); when others=> fifo_dout(CV_TO_CACHE_SLICE-2)(3 downto 0) <= '0'&fifo_dout(CV_TO_CACHE_SLICE-1)(2 downto 0); end case; end if; end if; end if; end process; -- fifo read port gmem_rqst_addr <= unsigned(fifo_addr_dout(0)(GMEM_ADDR_W-1 downto 2)); gmem_wrData <= fifo_dout(0)(DATA_W+DATA_W/8+1-1 downto DATA_W/8+1); gmem_rnw <= fifo_dout(0)(DATA_W/8); gmem_we <= fifo_dout(0)(DATA_W/8-1 downto 0); -- assert gmem_rqst_addr(GMEM_WORD_ADDR_W-1 downto GMEM_WORD_ADDR_W-4) = X"01" or gmem_we /= X"F" severity failure; atomic_signals: if ATOMIC_IMPLEMENT /= 0 generate gmem_atomic <= fifo_dout(0)(DATA_W+DATA_W/8+1); gmem_atomic_sgntr <= fifo_dout(0)(din_rqst_fifo'high downto din_rqst_fifo'high - N_CU_STATIONS_W+1); end generate; gmem_valid <= gmem_valid_vec(0); pop <= gmem_valid_vec(0) and gmem_ready; -- prepare write data into the fifo din_rqst_fifo_addr <= std_logic_vector(station_gmem_addr(station_slctd_indx)); din_rqst_fifo(din_rqst_fifo'high downto din_rqst_fifo'high-N_CU_STATIONS_W+1) <= std_logic_vector(to_unsigned(station_slctd_indx, N_CU_STATIONS_W)); atomic_din: if ATOMIC_IMPLEMENT /= 0 generate din_rqst_fifo(DATA_W+1+DATA_W/8) <= station_atomic(station_slctd_indx); end generate; din_rqst_fifo(DATA_W+1+DATA_W/8-1 downto 1+DATA_W/8) <= station_wrData(station_slctd_indx); din_rqst_fifo(DATA_W/8) <= station_rnw(station_slctd_indx); din_rqst_fifo(2 downto 0) <= station_op_type(station_slctd_indx); rqst_fifo: process(clk) begin if rising_edge(clk) then push_d0 <= push; if din_rqst_fifo_addr_d0_v /= (din_rqst_fifo_addr_d0_v'reverse_range=>'0') and din_rqst_fifo_addr_d0(GMEM_ADDR_W-1 downto CACHE_N_BANKS_W+2) = din_rqst_fifo_addr(GMEM_ADDR_W-1 downto CACHE_N_BANKS_W+2) and din_rqst_fifo_d0(DATA_W/8) = '1' and din_rqst_fifo(DATA_W/8) = '1' then push_d0 <= '0'; end if; din_rqst_fifo_addr_d0_v(din_rqst_fifo_addr_d0_v'high) <= '0'; din_rqst_fifo_addr_d0_v(din_rqst_fifo_addr_d0_v'high-1 downto 0) <= din_rqst_fifo_addr_d0_v(din_rqst_fifo_addr_d0_v'high downto 1); if push = '1' then din_rqst_fifo_d0 <= din_rqst_fifo; din_rqst_fifo_addr_d0 <= din_rqst_fifo_addr; din_rqst_fifo_addr_d0_v(din_rqst_fifo_addr_d0_v'high) <= '1'; end if; if din_rqst_fifo_addr_d0(GMEM_ADDR_W-1 downto CACHE_N_BANKS_W+2) = std_logic_vector(cache_rdAddr) and cache_rdAck = '1' then din_rqst_fifo_addr_d0_v <= (others=>'0'); -- report "clean happened"; end if; if nrst = '0' then fifo_wrAddr <= (others=>'0'); fifo_rdAddr <= (others=>'0'); fifo_full <= '0'; gmem_valid_i <= '0'; else if push_d0 = '1' then fifo_wrAddr <= fifo_wrAddr +1; end if; if (pop = '1' or gmem_valid_vec(gmem_valid_vec'high downto 0) /= (0 to gmem_valid_vec'high =>'1')) and gmem_valid_i = '1' then fifo_rdAddr <= fifo_rdAddr + 1; end if; if push_d0 = '0' and (pop = '1' or gmem_valid_vec(gmem_valid_vec'high downto 0) /= (0 to gmem_valid_vec'high =>'1')) then if fifo_rdAddr = fifo_wrAddr+2 then fifo_full <= '0'; end if; if fifo_rdAddr+1 = fifo_wrAddr then gmem_valid_i <= '0'; end if; end if; if push_d0 = '1' then gmem_valid_i <= '1'; if fifo_rdAddr = fifo_wrAddr+3 and (pop = '0' and gmem_valid_vec(gmem_valid_vec'high downto 0) = (0 to gmem_valid_vec'high =>'1')) then -- 2 because of extra clock delay (push -> push_d0) fifo_full <= '1'; end if; end if; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} process(clk) begin if rising_edge(clk) then push <= push_rqst_fifo_n; station_slctd_indx <= station_slctd_indx_n; end if; end process; process(station_get_ticket, fifo_full) variable station : natural range 0 to N_STATIONS-1 := 0; begin ticket_granted <= (others=>'0'); push_rqst_fifo_n <= '0'; station_slctd_indx_n <= 0; -- grant ticket if fifo_full = '0' then for i in 0 to N_STATIONS-1 loop station := c_stations_ordered_for_priority(i); -- station := i; if station_get_ticket(station) = '1' then push_rqst_fifo_n <= '1'; station_slctd_indx_n <= station; ticket_granted(station) <= '1'; exit; end if; end loop; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- stations FSMs -------------------------------------------------------------------------------------------{{{ tras_stations: process(clk) -- {{{ begin if rising_edge(clk) then station_free <= station_free_n; rd_fifo_data_d0 <= rd_fifo_data; station_gmem_addr <= station_gmem_addr_n; station_rd_addr <= station_rd_addr_n; station_wf_indx <= station_wf_indx_n; station_rnw <= station_rnw_n; if ATOMIC_IMPLEMENT /= 0 then station_atomic <= station_atomic_n; end if; station_rdData <= station_rdData_n; station_wrData <= station_wrData_n; station_op_type <= station_op_type_n; if nrst = '0' then st_stations <= (others=>idle); station_get_ticket <= (others=>'0'); station_perfomed <= (others=>'0'); if ATOMIC_IMPLEMENT /= 0 then station_wait_atomic <= (others=>'0'); end if; else st_stations <= st_stations_n; station_get_ticket <= station_get_ticket_n; station_perfomed <= station_perfomed_n; if ATOMIC_IMPLEMENT /= 0 then station_wait_atomic <= station_wait_atomic_n; end if; end if; end if; end process; -- }}} stations_read_performed: process(station_gmem_addr, rd_fifo_addr, rd_fifo_v) -- {{{ begin station_read_performed_n <= (others=>'0'); for i in 0 to N_STATIONS-1 loop if station_gmem_addr(i)(GMEM_ADDR_W-1 downto 2+RD_CACHE_N_WORDS_W) = rd_fifo_addr and rd_fifo_v = '1' then station_read_performed_n(i) <= '1'; end if; end loop; end process; -- }}} process(clk) begin if rising_edge(clk) then if ATOMIC_IMPLEMENT /= 0 then atomic_rdData_v_d0 <= atomic_rdData_v; atomic_rdData_v_d1 <= atomic_rdData_v_d0; atomic_sgntr_d0 <= atomic_sgntr; atomic_rdData_d0 <= atomic_rdData; atomic_rdData_d1 <= atomic_rdData_d0; station_atomic_perormed <= (others=>'0'); for i in 0 to N_STATIONS-1 loop -- if station_gmem_addr(i)(GMEM_ADDR_W-1 downto 2) = atomic_rdAddr_d0 and atomic_rdData_v_d0 = '1' and -- station_op_type(i) = atomic_rdData_type_d0 and station_wait_atomic(i) = '1' and -- (station_last_atomic_serve /= i or atomic_rdData_v_d1 = '0')then -- station_last_atomic_serve <= i; if unsigned(atomic_sgntr_d0) = to_unsigned(i, N_CU_STATIONS_W) and atomic_rdData_v_d0 = '1' and station_wait_atomic(i) = '1' then station_atomic_perormed(i) <= '1'; end if; end loop; end if; end if; end process; process(st_stations, station_free, station_go, station_gmem_addr, station_rd_addr, station_rnw, mem_rqsts_wf_indx_ltchd, station_get_ticket, station_op_type, ticket_granted, station_perfomed, station_written_back, station_wrData, station_rdData, rd_fifo_data_d0, station_read_performed_n, latch_rdData, station_atomic, station_wait_atomic, station_atomic_perormed, atomic_rdData_d1, mem_rqsts_rdData_ltchd, station_wf_indx) variable rdIndx : integer range 0 to CACHE_N_BANKS-1 := 0; begin for i in 0 to N_STATIONS-1 loop station_rnw_n(i) <= station_rnw(i); if ATOMIC_IMPLEMENT /= 0 then station_atomic_n(i) <= station_atomic(i); station_wait_atomic_n(i) <= station_wait_atomic(i); end if; station_rd_addr_n(i) <= station_rd_addr(i); station_gmem_addr_n(i) <= station_gmem_addr(i); station_free_n(i) <= station_free(i); st_stations_n(i) <= st_stations(i); station_get_ticket_n(i) <= station_get_ticket(i); station_rdData_n(i) <= station_rdData(i); station_perfomed_n(i) <= station_perfomed(i); station_wrData_n(i) <= station_wrData(i); station_op_type_n(i) <= station_op_type(i); latch_rdData_n(i) <= '0'; station_wf_indx_n(i) <= station_wf_indx(i); case st_stations(i) is when idle => -- {{{ station_free_n(i) <= '1'; station_wf_indx_n(i) <= mem_rqsts_wf_indx_ltchd; if station_go(i) = '1' then st_stations_n(i) <= get_ticket; station_get_ticket_n(i) <= '1'; station_free_n(i) <= '0'; station_gmem_addr_n(i) <= unsigned(mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_ADDR_HIGH downto MEM_RQST_ADDR_LOW)); station_rd_addr_n(i) <= unsigned(mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_RD_ADDR_HIGH downto MEM_RQST_RD_ADDR_LOW)); station_rnw_n(i) <= mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_RE_POS); if ATOMIC_IMPLEMENT /= 0 then station_atomic_n(i) <= mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_ATOMIC_POS); end if; station_wrData_n(i) <= mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_DATA_HIGH downto MEM_RQST_DATA_LOW); station_op_type_n(i) <= mem_rqsts_rdData_ltchd(c_alu_for_stations(i))(MEM_RQST_OP_TYPE_HIGH downto MEM_RQST_OP_TYPE_LOW); end if; -- }}} when get_ticket => -- {{{ -- assert (station_gmem_addr(i)(17 downto 2) = unsigned(station_wrData(i)(15 downto 0))) or station_rnw(i) = '1' -- report integer'image(to_integer(station_gmem_addr(i)(GMEM_ADDR_W-1 downto 2))) & ", data = " & -- integer'image(to_integer(unsigned(station_wrData(i)))) severity failure; if station_rnw(i) = '1' and station_read_performed_n(i) = '1' then station_get_ticket_n(i) <= '0'; station_perfomed_n(i) <= '1'; st_stations_n(i) <= write_back; latch_rdData_n(i) <= '1'; station_get_ticket_n(i) <= '0'; elsif ticket_granted(i) = '1' then if station_rnw(i) = '1' then st_stations_n(i) <= wait_read_done; elsif ATOMIC_IMPLEMENT /= 0 and station_atomic(i) = '1' then st_stations_n(i) <= wait_atomic; station_wait_atomic_n(i) <= '1'; else st_stations_n(i) <= idle; station_free_n(i) <= '1'; end if; station_get_ticket_n(i) <= '0'; end if; -- }}} when wait_atomic => -- {{{ if ATOMIC_IMPLEMENT /= 0 then station_rdData_n(i) <= atomic_rdData_d1; if station_atomic_perormed(i) = '1' then st_stations_n(i) <= write_back; station_perfomed_n(i) <= '1'; station_wait_atomic_n(i) <= '0'; end if; end if; -- }}} when wait_read_done => -- {{{ if station_read_performed_n(i) = '1' then latch_rdData_n(i) <= '1'; st_stations_n(i) <= write_back; station_perfomed_n(i) <= '1'; end if; -- }}} when write_back => -- {{{ if latch_rdData(i) = '1' then if RD_CACHE_N_WORDS_W /= 0 then rdIndx := to_integer(station_gmem_addr(i)(max(RD_CACHE_N_WORDS_W,1)+2-1 downto 2)); else rdIndx := 0; end if; station_rdData_n(i) <= rd_fifo_data_d0((rdIndx+1)*DATA_W-1 downto rdIndx*DATA_W); end if; if station_written_back(i) = '1' then st_stations_n(i) <= idle; station_free_n(i) <= '1'; station_perfomed_n(i) <= '0'; end if; -- }}} end case; end loop; end process; ---------------------------------------------------------------------------------------------------------}}} -- regFile interface ---------------------------------------------------------------------------------------{{{ -- regFile comb process ---------------------------------------------------------------------------------{{{ process(st_regFile_int, station_perfomed, regFile_wrAddr_p0, station_rd_addr, station_written_back, cv_lmem_rqst) begin st_regFile_int_n <= st_regFile_int; regFile_wrAddr_p0_n <= regFile_wrAddr_p0; regFile_we_p0_n <= (others=>'0'); station_written_back_n <= (others=>'0'); regFile_we_latch_p0_n <= '0'; case st_regFile_int is when choose_rd_addr => for i in N_STATIONS-1 downto 0 loop if station_perfomed(i) = '1' and station_written_back(i) = '0' then regFile_wrAddr_p0_n <= station_rd_addr(i); st_regFile_int_n <= update; end if; end loop; if LMEM_IMPLEMENT /= 0 and cv_lmem_rqst = '1' then st_regFile_int_n <= wait_scratchpad; end if; when update => st_regFile_int_n <= wait_1_cycle; if LMEM_IMPLEMENT /= 0 and cv_lmem_rqst = '1' then st_regFile_int_n <= wait_scratchpad; else for i in 0 to CV_SIZE-1 loop for j in N_STATIONS_ALU-1 downto 0 loop if station_perfomed(i*N_STATIONS_ALU+j) = '1' and station_rd_addr(i*N_STATIONS_ALU+j) = regFile_wrAddr_p0 then regFile_we_p0_n(i) <= '1'; station_written_back_n(i*N_STATIONS_ALU+j) <= '1'; regFile_we_latch_p0_n <= '1'; end if; end loop; end loop; end if; when wait_1_cycle => st_regFile_int_n <= choose_rd_addr; when wait_scratchpad => if LMEM_IMPLEMENT /= 0 and cv_lmem_rqst = '0' then st_regFile_int_n <= choose_rd_addr; end if; end case; end process; ---------------------------------------------------------------------------------------------------------}}} -- regFile trans process --------------------------------------------------------------------------------{{{ regFile_we_lmem_p0 <= lmem_rdData_v; -- @ level 19. regFile_side_trans: process(clk) begin if rising_edge(clk) then regFile_we_p0 <= regFile_we_p0_n; latch_rdData <= latch_rdData_n; station_written_back <= station_written_back_n; regFile_we_latch_p0 <= regFile_we_latch_p0_n; regFile_we_latch <= regFile_we_latch_p0; regFile_wrAddr_i <= regFile_wrAddr_p0; if regFile_we_latch = '0' then regFile_we <= regFile_we_p0; end if; regFile_wrAddr_p0 <= regFile_wrAddr_p0_n; lmem_rdData_d0 <= lmem_rdData; -- @ 20. if LMEM_IMPLEMENT /= 0 and lmem_rdData_v = '1' then -- level 19. regFile_we <= lmem_rdData_alu_en; -- @ 20. regFile_wrAddr_i <= lmem_rdData_rd_addr; -- @ 20. end if; if LMEM_IMPLEMENT /= 0 and regFile_we_latch = '0' then regFile_wrData <= lmem_rdData; -- @ 20. end if; for i in 0 to CV_SIZE-1 loop for j in N_STATIONS_ALU-1 downto 0 loop if station_written_back(i*N_STATIONS_ALU+j) = '1' then regFile_wrData(i) <= station_rdData(i*N_STATIONS_ALU+j); end if; end loop; end loop; if nrst = '0' then st_regFile_int <= choose_rd_addr; else st_regFile_int <= st_regFile_int_n; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -----------------------------------------------------------------------------------}}} -- gmem finished -------------------------------------------------------{{{ process(clk) variable wf_busy_indices : std_logic_vector(N_WF_CU-1 downto 0) := (others=>'0'); begin if rising_edge(clk) then wf_finish <= wf_finish_n; if nrst = '0' then st_finish <= (others=>idle); else st_finish <= st_finish_n; end if; wf_busy_indices := (others=>'0'); for i in 0 to N_STATIONS-1 loop if station_free(i) = '0' then wf_busy_indices := wf_busy_indices or station_wf_indx(i); end if; end loop; wfs_being_served <= wf_busy_indices; end if; end process; st_finish_array: for i in 0 to N_WF_CU-1 generate begin process(st_finish(i), check_finish(i), wfs_being_served(i)) begin st_finish_n(i) <= st_finish(i); wf_finish_n(i) <= '0'; case st_finish(i) is when idle => if check_finish(i) = '1' then st_finish_n(i) <= serving; end if; when serving => if wfs_being_served(i) = '0' then st_finish_n(i) <= finished; end if; when finished => wf_finish_n(i) <= '1'; st_finish_n(i) <= idle; end case; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- controller idle -------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then cntrl_idle_i <= '0'; if station_free = (station_free'reverse_range=>'1') and gmem_valid_i = '0' and st_cv_side = get_rqst then cntrl_idle_i <= '1'; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- cache read fifo -------------------------------------------------------------------------------------------{{{ -- cu_mem_cntrl <- port A (myram) port B -> cache cache_rd_buffer_inst: entity rd_cache_fifo generic map ( SIZEA => 2**(RD_CACHE_FIFO_PORTB_ADDR_W+CACHE_N_BANKS_W-RD_CACHE_N_WORDS_W), ADDRWIDTHA => RD_CACHE_FIFO_PORTB_ADDR_W+CACHE_N_BANKS_W-RD_CACHE_N_WORDS_W, SIZEB => 2**RD_CACHE_FIFO_PORTB_ADDR_W, ADDRWIDTHB => RD_CACHE_FIFO_PORTB_ADDR_W ) port map( clk => clk, push => cache_rdAck, cache_rdData => cache_rdData, cache_rdAddr => cache_rdAddr, rdData => rd_fifo_data, rdAddr => rd_fifo_addr, nempty => rd_fifo_v, nrst => nrst ); ---------------------------------------------------------------------------------------------------------}}} -- lmem -------------------------------------------------------------------------------------------------{{{ local_memory_inst: if LMEM_IMPLEMENT /= 0 generate begin sp <= cv_addr(cv_alu_en_pri_enc)(LMEM_ADDR_W-N_WF_CU_W-PHASE_W-1 downto 0); local_memory: entity lmem port map( clk => clk, rqst => cv_lmem_rqst, -- level 17. we => cv_lmem_we, alu_en => cv_alu_en, wrData => cv_wrData, rdData => lmem_rdData, -- level 19. rdData_rd_addr => lmem_rdData_rd_addr, -- level 19. rdData_v => lmem_rdData_v, -- level 19. rdData_alu_en => lmem_rdData_alu_en, -- level 19. -- connect all of cv_addr; you have 8 SPs!! sp => sp, rd_addr => cv_rd_addr, nrst => nrst ); end generate; ---------------------------------------------------------------------------------------------------------}}} end architecture;

gpl-3.0

3f09e7127002a8ea848484ea81a4f72d

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_no_fdiv_area_estimation.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

a44de22ad437649e4d322fd01f514bd2

joalcava/sparcv8-monocicle

register_file.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity register_file is Port( Wren : in STD_LOGIC; rst : in STD_LOGIC; rs1 : in STD_LOGIC_VECTOR (5 downto 0); rs2 : in STD_LOGIC_VECTOR (5 downto 0); rd : in STD_LOGIC_VECTOR (5 downto 0); data : in STD_LOGIC_VECTOR (31 downto 0); crs1 : out STD_LOGIC_VECTOR (31 downto 0); crs2 : out STD_LOGIC_VECTOR (31 downto 0); crd : out STD_LOGIC_VECTOR (31 downto 0) ); end register_file; architecture ArqRegFile of register_file is type ram_type is array (0 to 39) of std_logic_vector (31 downto 0); signal reg : ram_type := (others => x"00000000"); begin process(rst, rs1, rs2, rd,data) begin if (rst = '0') then crs1 <= reg(conv_integer(rs1 )); crs2 <= reg(conv_integer(rs2 )); crd <= reg(conv_integer(rd )); if(rd /= "00000" and Wren ='1') then reg(conv_integer(rd)) <= data; end if; elsif (rst='1') then crs1 <= x"00000000"; crs2 <= x"00000000"; reg <= (others => x"00000000"); end if; end process; end ArqRegFile;

gpl-3.0

74c45b379c857e7e31b66915f8c49de0

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_model_constr_decoder.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_model_constr_decoder | -- | --------------------------------------------------------------------------------------------------- -- File wf_model_constr_decoder.vhd | -- | -- Description Generation of the nanoFIP output S_ID and decoding of the inputs C_ID and M_ID. | -- The output S_ID0 is a clock with period the double of uclk's period and the S_ID1 | -- is the opposite clock (it is '0' when S_ID0 is '1' and '1' when S_ID0 is '0'). | -- Each one of the 4 pins of the M_ID and C_ID can be connected to either Vcc, Gnd, | -- S_ID1 or S_ID0. Like this (after 2 uclk periods) the 8 bits of the Model and | -- Constructor words take a value, according to the table: Gnd 00 | -- S_ID0 01 | -- S_ID1 10 | -- Vcc 11 | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 21/01/2011 | -- Version v0.03 | -- Depends on wf_reset_unit | ---------------- | -- Last changes | -- 11/09/2009 v0.01 PAS First version | -- 20/08/2010 v0.02 EG S_ID corrected so that S_ID0 is always the opposite of S_ID1 | -- "for" loop replaced with signals concatenation; | -- Counter is of c_RELOAD_MID_CID bits; Code cleaned-up | -- 06/10/2010 v0.03 EG generic c_RELOAD_MID_CID removed; | -- counter unit instantiated | -- 01/2011 v0.031 EG loading aftern the 2nd cycle (no need for 3) | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_model_constr_decoder --================================================================================================= entity wf_model_constr_decoder is port( -- INPUTS -- nanoFIP User Interface general signal uclk_i : in std_logic; -- 40 Mhz clock -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- nanoFIP WorldFIP Settings (synchronised with uclk_i) constr_id_i : in std_logic_vector (3 downto 0); -- Constructor identification settings model_id_i : in std_logic_vector (3 downto 0); -- Model identification settings -- OUTPUTS -- nanoFIP WorldFIP Settings output -- MODIFIED -- s_id_o : out std_logic_vector (1 downto 0); -- Identification selection -- Signal to the wf_prod_bytes_retriever unit constr_id_dec_o : out std_logic_vector (7 downto 0); -- Constructor identification decoded model_id_dec_o : out std_logic_vector (7 downto 0));-- Model identification decoded end entity wf_model_constr_decoder; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_model_constr_decoder is signal s_counter : unsigned (1 downto 0); signal s_model_stage2, s_model_stage1 : std_logic_vector (3 downto 0); signal s_constr_stage2, s_constr_stage1 : std_logic_vector (3 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Synchronous process Model_Constructor_Decoder: -- For M_ID and C_ID to be loaded, 2 uclk periods are needed: on the first uclk tick, the values -- of all the odd bits of M_ID & C_ID are loaded on the registers s_model_stage1/ s_constr_stage1 -- and on the second uclk tick, the values of the odd bits move to the registers s_model_stage2/ -- s_constr_stage2, giving place to all the even bits to be loaded to the s_model_stage1/ -- s_constr_stage1. The loaded odd and even values are combined after the 2 periods to give the -- decoded outputs model_id_dec_o & constr_id_dec_o. Model_Constructor_Decoder: process (uclk_i) begin if rising_edge (uclk_i) then -- initializations if nfip_rst_i = '1' then model_id_dec_o <= (others => '0'); constr_id_dec_o <= (others => '0'); s_model_stage1 <= (others => '0'); s_model_stage2 <= (others => '0'); s_constr_stage1 <= (others => '0'); s_constr_stage2 <= (others => '0'); else s_model_stage2 <= s_model_stage1; -- after 2 uclk ticks stage1 keeps the even bits s_model_stage1 <= model_id_i; -- and stage2 the odd ones s_constr_stage2 <= s_constr_stage1; s_constr_stage1 <= constr_id_i; -- same for the constructor if s_counter = "10" then model_id_dec_o <= s_model_stage2(3) & s_model_stage1(3) & -- putting together s_model_stage2(2) & s_model_stage1(2) & -- even and odd bits s_model_stage2(1) & s_model_stage1(1) & s_model_stage2(0) & s_model_stage1(0); constr_id_dec_o <= s_constr_stage2(3) & s_constr_stage1(3) & s_constr_stage2(2) & s_constr_stage1(2) & s_constr_stage2(1) & s_constr_stage1(1) & s_constr_stage2(0) & s_constr_stage1(0); end if; end if; end if; end process; --------------------------------------------------------------------------------------------------- -- Instantiation of a counter wf_incr_counter Free_Counter: wf_incr_counter generic map(g_counter_lgth => 2) port map( uclk_i => uclk_i, counter_reinit_i => nfip_rst_i, counter_incr_i => '1', counter_is_full_o => open, ----------------------------------------- counter_o => s_counter); ----------------------------------------- --------------------------------------------------------------------------------------------------- -- Concurrent signal assignment for the output s_id_o -- MODIFIED -- s_id_o <= ((not s_counter(0)) & s_counter(0)); -- 2 opposite clocks generated using -- the LSB of the counter -- uclk_i: |-|__|-|__|-|__|-|__|-|__|-|_ -- S_ID0 : |----|____|----|____|----|___ -- S_ID1 : |____|----|____|----|____|--- end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

25bb6c227d5d2268b8dfb7865b703268

malkadi/FGPU

RTL/gmem_atomics.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity gmem_atomics is port( -- {{{ rcv_atomic_type : in be_array(N_RECEIVERS-1 downto 0); rcv_atomic_rqst : in std_logic_vector(N_RECEIVERS-1 downto 0); rcv_gmem_addr : in gmem_word_addr_array(N_RECEIVERS-1 downto 0); rcv_gmem_data : in SLV32_ARRAY(N_RECEIVERS-1 downto 0) := (others=>(others=>'0')); rcv_must_read : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); rcv_atomic_ack : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); -- read data path (in) gmem_rdAddr_p0 : in unsigned(GMEM_WORD_ADDR_W-N-1 downto 0); gmem_rdData : in std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0); gmem_rdData_v_p0 : in std_logic := '0'; -- atomic data path (out) atomic_rdData : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); rcv_retire : out std_logic_vector(N_RECEIVERS-1 downto 0) := (others=>'0'); -- this signals implies the validety of atomic_rdData -- it is 2 clock cycles in advance -- atomic flushing flush_v : out std_logic := '0'; flush_gmem_addr : out unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0'); flush_data : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); flush_ack : in std_logic; flush_done : in std_logic; finish : in std_logic; atomic_can_finish : out std_logic := '0'; WGsDispatched : in std_logic; clk, nrst : std_logic ); -- }}} end entity; architecture basic of gmem_atomics is -- general control signals {{{ signal rcv_slctd_indx : integer range 0 to N_RECEIVERS := 0; attribute max_fanout of rcv_slctd_indx : signal is 60; signal rcv_slctd_indx_d0 : integer range 0 to N_RECEIVERS := 0; attribute max_fanout of rcv_slctd_indx_d0 : signal is 40; signal check_rqst, check_rqst_d0 : std_logic := '0'; signal rqst_type : std_logic_vector(2 downto 0) := (others=>'0'); attribute max_fanout of rqst_type : signal is 60; signal rqst_val : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal rqst_gmem_addr : unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0'); type atomic_unit_state is (idle, listening, latch_gmem_data, select_word, functioning); signal rcv_half_select : std_logic := '0'; signal rcv_is_reading : std_logic := '0'; -- }}} -- atomic max signals -----------------------------------------------------------------------------------{{{ signal st_amax, st_amax_n : atomic_unit_state := idle; signal amax_gmem_addr, amax_gmem_addr_n : unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0'); signal amax_data, amax_data_n : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal amax_data_d0 : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal amax_addr_v, amax_addr_v_n : std_logic := '0'; signal amax_addr_v_d0 : std_logic := '0'; signal amax_exec, amax_exec_d0 : std_logic := '0'; signal amax_latch_gmem_rdData : std_logic := '0'; signal amax_latch_gmem_rdData_n : std_logic := '0'; ---------------------------------------------------------------------------------------------------------}}} -- atomic add signals -----------------------------------------------------------------------------------{{{ signal st_aadd, st_aadd_n : atomic_unit_state := idle; signal aadd_gmem_addr, aadd_gmem_addr_n : unsigned(GMEM_WORD_ADDR_W-1 downto 0) := (others=>'0'); signal aadd_data, aadd_data_n : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal aadd_data_d0 : unsigned(DATA_W-1 downto 0) := (others=>'0'); signal gmem_rdData_ltchd : std_logic_vector(DATA_W*CACHE_N_BANKS-1 downto 0); signal aadd_latch_gmem_rdData : std_logic := '0'; signal aadd_latch_gmem_rdData_n : std_logic := '0'; signal aadd_addr_v, aadd_addr_v_n : std_logic := '0'; signal aadd_addr_v_d0 : std_logic := '0'; signal aadd_exec, aadd_exec_d0 : std_logic := '0'; ---------------------------------------------------------------------------------------------------------}}} -- flushing aadd results --------------------------------------------------------------------------------{{{ type flush_state_type is (idle, dirty, flushing, wait_flush_done); signal st_aadd_flush, st_aadd_flush_n : flush_state_type := idle; constant FLUSH_TIMER_W : integer := 3; signal aadd_flush_timer : unsigned(FLUSH_TIMER_W-1 downto 0) := (others=>'0'); signal aadd_flush_timer_n : unsigned(FLUSH_TIMER_W-1 downto 0) := (others=>'0'); signal aadd_flush_rqst : std_logic := '0'; signal aadd_flush_rqst_n : std_logic := '0'; signal aadd_flush_started : std_logic := '0'; signal aadd_flush_done : std_logic := '0'; signal flush_ack_d0 : std_logic := '0'; signal aadd_dirty_content : std_logic := '0'; signal aadd_dirty_content_n : std_logic := '0'; signal WGsDispatched_ltchd : std_logic := '0'; signal aadd_flush_active : std_logic := '0'; ---------------------------------------------------------------------------------------------------------}}} -- flushing amax results --------------------------------------------------------------------------------{{{ signal st_amax_flush, st_amax_flush_n : flush_state_type := idle; signal amax_flush_timer : unsigned(FLUSH_TIMER_W-1 downto 0) := (others=>'0'); signal amax_flush_timer_n : unsigned(FLUSH_TIMER_W-1 downto 0) := (others=>'0'); signal amax_flush_rqst : std_logic := '0'; signal amax_flush_rqst_n : std_logic := '0'; signal amax_flush_started : std_logic := '0'; signal amax_flush_done : std_logic := '0'; signal amax_dirty_content : std_logic := '0'; signal amax_dirty_content_n : std_logic := '0'; signal amax_flush_active : std_logic := '0'; ---------------------------------------------------------------------------------------------------------}}} begin -- TODO: implement atomic address changing. Now only one address can be used by an atomic unit -- TODO: consider the case when two atomic units work on the same global address -- asserts & internals ----------------------------------------------------------------------------------{{{ assert FLUSH_TIMER_W < 4 report "make FLUSH_TIMER_W less than 4 otherwise FGPU will finish while there is dirty data in the atomic units"; ---------------------------------------------------------------------------------------------------------}}} -- receivers interface ----------------------------------------------------------------------------------{{{ RCV_INTERFACE: if AADD_ATOMIC = 1 or AMAX_ATOMIC = 1 generate process(clk) variable rcv_slctd_indx_unsigned : unsigned(N_RECEIVERS_W-1 downto 0) := (others=>'0'); begin if rising_edge(clk) then rcv_half_select <= not rcv_half_select; -- stage 0: -- select requesting receiver check_rqst <= '0'; rcv_atomic_ack <= (others=>'0'); for i in N_RECEIVERS/2-1 downto 0 loop rcv_slctd_indx_unsigned(N_RECEIVERS_W-1 downto 1) := to_unsigned(i, N_RECEIVERS_W-1); rcv_slctd_indx_unsigned(0) := rcv_half_select; if rcv_atomic_rqst(to_integer(rcv_slctd_indx_unsigned)) = '1' then rcv_slctd_indx <= to_integer(rcv_slctd_indx_unsigned); rcv_atomic_ack(to_integer(rcv_slctd_indx_unsigned)) <= '1'; -- assert(rcv_atomic_type(i) = CODE_AADD(2 downto 0)); check_rqst <= '1'; exit; end if; end loop; -- stage 1: -- latch request rqst_type <= rcv_atomic_type(rcv_slctd_indx)(2 downto 0); rqst_gmem_addr <= rcv_gmem_addr(rcv_slctd_indx); check_rqst_d0 <= check_rqst; rcv_slctd_indx_d0 <= rcv_slctd_indx; -- stage 2: -- check validety rcv_must_read <= (others=>'0'); rcv_retire <= (others=>'0'); aadd_exec <= '0'; amax_exec <= '0'; if check_rqst_d0 = '1' then case rqst_type is when CODE_AADD(2 downto 0) => if aadd_addr_v = '0' or aadd_gmem_addr /= rqst_gmem_addr then if rcv_is_reading = '0' then rcv_must_read(rcv_slctd_indx_d0) <= '1'; rcv_is_reading <= '1'; end if; else rcv_retire(rcv_slctd_indx_d0) <= '1'; aadd_exec <= '1'; end if; when CODE_AMAX(2 downto 0) => if amax_addr_v = '0' or amax_gmem_addr /= rqst_gmem_addr then if rcv_is_reading = '0' then rcv_must_read(rcv_slctd_indx_d0) <= '1'; rcv_is_reading <= '1'; end if; else rcv_retire(rcv_slctd_indx_d0) <= '1'; amax_exec <= '1'; end if; when others => assert(false); end case; end if; rqst_val <= unsigned(rcv_gmem_data(rcv_slctd_indx_d0)); -- stage3: -- wait for result aadd_exec_d0 <= aadd_exec; amax_exec_d0 <= amax_exec; --stage 4: -- forward result if aadd_exec_d0 = '1' then atomic_rdData <= std_logic_vector(aadd_data_d0); -- if _d0 is removed then the atomic will giv back the new result instead of the old one else -- if amax_exec_d0 = '1' atomic_rdData <= std_logic_vector(amax_data_d0); end if; -- atomic_rdAddr <= aadd_gmem_addr; -- no need for the performed atomic address; it is included in the signature -- atomic_rdData_type <= CODE_AADD(2 downto 0); -- no need to send the atomic type back; it is included in the signature -- other tasks if (aadd_addr_v = '1' and aadd_addr_v_d0 = '0') or (amax_addr_v = '1' and amax_addr_v_d0 = '0') then rcv_is_reading <= '0'; end if; if aadd_latch_gmem_rdData = '1' or amax_latch_gmem_rdData = '1' then gmem_rdData_ltchd <= gmem_rdData; end if; end if; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- flushing amax ----------------------------------------------------------------------------------------{{{ AMAX_FLUSHING: if AMAX_ATOMIC = 1 generate process(clk) begin if rising_edge(clk) then if nrst = '0' then st_amax_flush <= idle; amax_flush_rqst <= '0'; amax_dirty_content <= '0'; else st_amax_flush <= st_amax_flush_n; amax_flush_rqst <= amax_flush_rqst_n; amax_dirty_content <= amax_dirty_content_n; end if; amax_flush_timer <= amax_flush_timer_n; end if; end process; process(st_amax_flush, amax_exec, amax_flush_timer, amax_flush_rqst, amax_flush_started, flush_done, amax_dirty_content, WGsDispatched_ltchd) begin st_amax_flush_n <= st_amax_flush; amax_flush_timer_n <= amax_flush_timer; amax_flush_rqst_n <= amax_flush_rqst; amax_dirty_content_n <= amax_dirty_content; case st_amax_flush is when idle => amax_flush_timer_n <= (others=>'0'); if amax_exec = '1' or amax_dirty_content = '1' then st_amax_flush_n <= dirty; end if; when dirty => if WGsDispatched_ltchd = '1' then amax_flush_timer_n <= amax_flush_timer + 1; if amax_exec = '1' then amax_flush_timer_n <= (others=>'0'); elsif amax_flush_timer = (amax_flush_timer'reverse_range =>'1') then st_amax_flush_n <= flushing; amax_flush_rqst_n <= '1'; amax_dirty_content_n <= '0'; end if; end if; when flushing => if amax_exec = '1' then amax_dirty_content_n <= '1'; end if; if amax_flush_started = '1' then st_amax_flush_n <= wait_flush_done; amax_flush_rqst_n <= '0'; end if; when wait_flush_done => if flush_done = '1' then st_amax_flush_n <= idle; end if; if amax_exec = '1' then amax_dirty_content_n <= '1'; end if; end case; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- flushing aadd ----------------------------------------------------------------------------------------{{{ AADD_FLUSH: if AADD_ATOMIC = 1 generate process(clk) begin if rising_edge(clk) then if nrst = '0' then st_aadd_flush <= idle; aadd_flush_rqst <= '0'; aadd_dirty_content <= '0'; else st_aadd_flush <= st_aadd_flush_n; aadd_flush_rqst <= aadd_flush_rqst_n; aadd_dirty_content <= aadd_dirty_content_n; end if; aadd_flush_timer <= aadd_flush_timer_n; end if; end process; process(st_aadd_flush, aadd_exec, aadd_flush_timer, aadd_flush_rqst, aadd_flush_started, flush_done, aadd_dirty_content, WGsDispatched_ltchd) begin st_aadd_flush_n <= st_aadd_flush; aadd_flush_timer_n <= aadd_flush_timer; aadd_flush_rqst_n <= aadd_flush_rqst; aadd_dirty_content_n <= aadd_dirty_content; case st_aadd_flush is when idle => aadd_flush_timer_n <= (others=>'0'); if aadd_exec = '1' or aadd_dirty_content = '1' then st_aadd_flush_n <= dirty; end if; when dirty => if WGsDispatched_ltchd = '1' then aadd_flush_timer_n <= aadd_flush_timer + 1; if aadd_exec = '1' then aadd_flush_timer_n <= (others=>'0'); elsif aadd_flush_timer = (aadd_flush_timer'reverse_range =>'1') then st_aadd_flush_n <= flushing; aadd_flush_rqst_n <= '1'; aadd_dirty_content_n <= '0'; end if; end if; when flushing => if aadd_exec = '1' then aadd_dirty_content_n <= '1'; end if; if aadd_flush_started = '1' then st_aadd_flush_n <= wait_flush_done; aadd_flush_rqst_n <= '0'; end if; when wait_flush_done => if flush_done = '1' then st_aadd_flush_n <= idle; end if; if aadd_exec = '1' then aadd_dirty_content_n <= '1'; end if; end case; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- atomic max -------------------------------------------------------------------------------------------{{{ AMAX_BODY: if AMAX_ATOMIC = 1 generate process(clk) begin if rising_edge(clk) then if nrst = '0' then amax_addr_v <= '0'; st_amax <= idle; else st_amax <= st_amax_n; amax_addr_v <= amax_addr_v_n; end if; amax_addr_v_d0 <= amax_addr_v; amax_gmem_addr <= amax_gmem_addr_n; amax_data <= amax_data_n; amax_data_d0 <= amax_data; amax_latch_gmem_rdData <= amax_latch_gmem_rdData_n; end if; end process; process(st_amax, check_rqst_d0, rqst_type, amax_gmem_addr, rqst_gmem_addr, gmem_rdData_v_p0, gmem_rdAddr_p0, amax_data, gmem_rdData_ltchd, amax_addr_v, amax_exec, rqst_val, finish) variable word_indx : integer range 0 to GMEM_N_BANK-1 := 0; -- variable n_amax_exec : integer := 0; -- variable written_vals : std_logic_vector(2047 downto 0) := (others=>'0'); -- variable written_index : integer range 0 to 2047 := 0; begin st_amax_n <= st_amax; amax_gmem_addr_n <= amax_gmem_addr; amax_data_n <= amax_data; amax_addr_v_n <= amax_addr_v; amax_latch_gmem_rdData_n <= '0'; case st_amax is when idle => if check_rqst_d0 = '1' and rqst_type = CODE_AMAX(2 downto 0) then st_amax_n <= listening; amax_gmem_addr_n <= rqst_gmem_addr; end if; when listening => if gmem_rdData_v_p0 = '1' and gmem_rdAddr_p0 = amax_gmem_addr(amax_gmem_addr'high downto N) then st_amax_n <= latch_gmem_data; amax_latch_gmem_rdData_n <= '1'; end if; when latch_gmem_data => st_amax_n <= select_word; when select_word => word_indx := to_integer(amax_gmem_addr(N-1 downto 0)); amax_data_n <= unsigned(gmem_rdData_ltchd(DATA_W*(word_indx+1)-1 downto DATA_W*word_indx)); st_amax_n <= functioning; amax_addr_v_n <= '1'; when functioning => if amax_exec = '1' then -- n_amax_exec := n_amax_exec + 1; if signed(amax_data) < signed(rqst_val) then amax_data_n <= rqst_val; end if; -- written_index := ((to_integer(rqst_val)-6) / 16); -- assert written_index < 2048 severity failure; -- assert written_vals(written_index) = '0' severity failure; -- written_vals(written_index) := '1'; -- assert ((to_integer(rqst_val)-6) mod 16) = 0 severity failure; end if; if finish = '1' then -- assert written_vals = (written_vals'reverse_range=>'1') severity failure; -- written_vals := (others=>'0'); -- report "# of executed atmoic additions (counted inside the atomic unit) is " & integer'image(n_amax_exec); -- n_amax_exec := 0; st_amax_n <= idle; amax_addr_v_n <= '0'; end if; end case; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- atomic add -------------------------------------------------------------------------------------------{{{ AADD_BODY: if AADD_ATOMIC = 1 generate process(clk) begin if rising_edge(clk) then if nrst = '0' then aadd_addr_v <= '0'; st_aadd <= idle; else st_aadd <= st_aadd_n; aadd_addr_v <= aadd_addr_v_n; end if; aadd_addr_v_d0 <= aadd_addr_v; aadd_gmem_addr <= aadd_gmem_addr_n; aadd_data <= aadd_data_n; aadd_data_d0 <= aadd_data; aadd_latch_gmem_rdData <= aadd_latch_gmem_rdData_n; end if; end process; process(st_aadd, check_rqst_d0, rqst_type, aadd_gmem_addr, rqst_gmem_addr, gmem_rdData_v_p0, gmem_rdAddr_p0, aadd_data, gmem_rdData_ltchd, aadd_addr_v, aadd_exec, rqst_val, finish) variable word_indx : integer range 0 to GMEM_N_BANK-1 := 0; -- variable n_aadd_exec : integer := 0; -- variable written_vals : std_logic_vector(2047 downto 0) := (others=>'0'); -- variable written_index : integer range 0 to 2047 := 0; begin st_aadd_n <= st_aadd; aadd_gmem_addr_n <= aadd_gmem_addr; aadd_data_n <= aadd_data; aadd_addr_v_n <= aadd_addr_v; aadd_latch_gmem_rdData_n <= '0'; case st_aadd is when idle => if check_rqst_d0 = '1' and rqst_type = CODE_AADD(2 downto 0) then st_aadd_n <= listening; aadd_gmem_addr_n <= rqst_gmem_addr; end if; when listening => if gmem_rdData_v_p0 = '1' and gmem_rdAddr_p0 = aadd_gmem_addr(aadd_gmem_addr'high downto N) then st_aadd_n <= latch_gmem_data; aadd_latch_gmem_rdData_n <= '1'; end if; when latch_gmem_data => st_aadd_n <= select_word; when select_word => word_indx := to_integer(aadd_gmem_addr(N-1 downto 0)); aadd_data_n <= unsigned(gmem_rdData_ltchd(DATA_W*(word_indx+1)-1 downto DATA_W*word_indx)); st_aadd_n <= functioning; aadd_addr_v_n <= '1'; when functioning => if aadd_exec = '1' then -- n_aadd_exec := n_aadd_exec + 1; aadd_data_n <= aadd_data + rqst_val; -- written_index := ((to_integer(rqst_val)-6) / 16); -- assert written_index < 2048 severity failure; -- assert written_vals(written_index) = '0' severity failure; -- written_vals(written_index) := '1'; -- assert ((to_integer(rqst_val)-6) mod 16) = 0 severity failure; end if; if finish = '1' then -- assert written_vals = (written_vals'reverse_range=>'1') severity failure; -- written_vals := (others=>'0'); -- report "# of executed atmoic additions (counted inside the atomic unit) is " & integer'image(n_aadd_exec); -- n_aadd_exec := 0; st_aadd_n <= idle; aadd_addr_v_n <= '0'; end if; end case; end process; end generate; ---------------------------------------------------------------------------------------------------------}}} -- flushing ---------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then if nrst = '0' then WGsDispatched_ltchd <= '0'; else if finish = '1' then WGsDispatched_ltchd <= '0'; elsif WGsDispatched = '1' then WGsDispatched_ltchd <= '1'; end if; end if; atomic_can_finish <= '0'; if st_aadd_flush = idle and st_amax_flush = idle then atomic_can_finish <= '1'; end if; flush_v <= (aadd_flush_rqst or amax_flush_rqst) and not (flush_ack or flush_ack_d0); flush_ack_d0 <= flush_ack; aadd_flush_started <= '0'; amax_flush_started <= '0'; aadd_flush_active <= '0'; amax_flush_active <= '0'; if flush_ack = '0' then if aadd_flush_rqst = '1' then flush_gmem_addr <= aadd_gmem_addr; flush_data <= std_logic_vector(aadd_data); aadd_flush_active <= '1'; elsif amax_flush_rqst = '1' then flush_gmem_addr <= amax_gmem_addr; flush_data <= std_logic_vector(amax_data); amax_flush_active <= '1'; end if; else if aadd_flush_active = '1' then aadd_flush_started <= '1'; else -- amax_flush_active = '1' amax_flush_started <= '1'; end if; end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} end architecture;

gpl-3.0

4bb6361250f7431a1401f035d1cc5ebe

preusser/q27

src/vhdl/PoC/fifo/fifo_glue.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- =========================================================================== -- Module: minimal FIFO, common clock (cc), -- pipelined interface, first-word-fall-through mode -- -- Authors: Thomas B. Preusser -- -- Description: -- ------------------------------------ -- Its primary use is the decoupling of enable domains in a processing -- pipeline. Data storage is limited to two words only so as to allow both -- the 'ful' and the 'vld' indicators to be driven by registers. -- -- License: -- =========================================================================== -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- =========================================================================== library IEEE; use IEEE.std_logic_1164.all; entity fifo_glue is generic ( D_BITS : positive -- Data Width ); port ( -- Control clk : in std_logic; -- Clock rst : in std_logic; -- Synchronous Reset -- Input put : in std_logic; -- Put Value di : in std_logic_vector(D_BITS-1 downto 0); -- Data Input ful : out std_logic; -- Full -- Output vld : out std_logic; -- Data Available do : out std_logic_vector(D_BITS-1 downto 0); -- Data Output got : in std_logic -- Data Consumed ); end fifo_glue; architecture rtl of fifo_glue is -- Data Buffer Registers signal A, B : std_logic_vector(D_BITS-1 downto 0); -- State Registers signal Full, Avail : std_logic := '0'; begin process(clk) begin if rising_edge(clk) then if rst = '1' then A <= (others => '-'); B <= (others => '-'); Full <= '0'; Avail <= '0'; else if Avail = '0' then if put = '1' then B <= di; Avail <= '1'; end if; elsif Full = '0' then if got = '1' then if put = '1' then B <= di; else Avail <= '0'; end if; else if put = '1' then A <= di; Full <= '1'; end if; end if; else if got = '1' then B <= A; Full <= '0'; end if; end if; end if; end if; end process; ful <= Full; vld <= Avail; do <= B; end rtl;

agpl-3.0

97c54405a3b6af4cddc41377a685fe55

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_axi_write_wrapper.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block eSjNqhAX5dMjiPMlOMRO/4jf2JFhBFmlC8x0Wv6dphH4AYrpCET1ziOzgdxEluKaV3fn6WHUdDrO 1MFrbO3k4A== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block MD9vuE1ZvquyQCWUpVpm0b6A5Bx9YN7WIHyQgH1NJOVfsa+Smjt1+M459msQrCh0jZ+ae47KScpi KLxtapP2G/SUAGFCR35gmVhntFmZvkzM1qmVQLiWdtVv4HKuII/znq+h17pNYoCD/iHqk7ee+EAj QKyWXUDAmxdmpVEbL/Y= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block aO7O587FnK0UlKUcT5hJe/lxzaW+Ab8B4PGLdtV5xqujZdzxiPEAz5J6w2drZKcMnRDD5/EgLml0 3IFdcUGMzMim7LvTg6OnIjexEgEvWxOEF+2UR1xTMZG30LHqn09Xo4SL4nsiWvDy45HfPq2Y2Ln1 xqF/dyJI/mpyKUr+J/aM1Smjz335d3zygzIliBzXdtx0aXXkCMSUzGZZATyrx6hVgUr3qj3jAvCv p3sXO8ri1gZ5TzwjbOs/2pW7BfC8d3lnW6gwb4eNmRsq8FDKAWFJQ7G6mXAebj11Nyu7LQOgeTGz naciP6mNVBKJkZigNLyba9KUjA8Yl4+OUWAPNA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block UM+BLG0rX/liUEb35hqqrsfpGUBU8ynPps3eRUzpCfZ1KPx52fmw+mIrXKiEaR51P0LAAa/djeHk oSC26ioM7mbC9CKvPNK0kXQoklqOkYcFeRV98uPgq/FEoj3QLX6PK+ZvkfnZUPXdBy4/OlTC3i8l +i/G7ysYIPwBBu1sT7g= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block jWotZ+/qnf2UjBkC8cDQ5oqSSE/bVppH85EbM/I/uJpgN3W3ds8ndIPt+Ow7sQbWThGZtGuEIBwq jazXrZUmGgB2ooeMI6WBs6HVXakd+7nhQfVhZSY+DdIMs8fxw0Kcn+pK3Hzr+gphvdsfswP1poMX Q0B136cD4YKjlDjX7s+ILCMkN4b25vTlmNyMf6SVvLYJjHjFSIvLUlE9aE2lA8OtShPK2A/2FipP zUUOqr6Z5V2uMauU1z47uHcMMWP13Y14kwsbuQop4h+7/CJyadsfdVkMzGf88i6PdHx3iSkAebPn lr/2OuzUWz+O/as41hWsLVvDbrmN8h8NrYB6MQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 47328) `protect data_block eyeoEWlD5hn8AxwD/Ydjz7S9TXao54f6tO+i+6EdeOp0HS38fuPTm37j8K6hzbsA+GTG1nKCT0d4 UJLrvBrobnK68VFYGQ1w19rGYHv/sifXG3zMzcjl0+H3ejJiJ9TXxnJc83TC5IuFgyfsXJlwQV89 QMnBolTKJj0GPh4FaXmHmPeIkQ+UmnDGh9hADITf9jeLxIQzzWjWrYAW16n32NgE/jcFnwlFsZgg SeHuPHyiZJO1abLsMD8l5y1fuDl3egJwbQIO6fnemig7perV4IYj24ARNkRSv8Vo/Uyda99K+FgW /3K+fsFo5vPF9yvrbI6oChAdIYXjr3+x6r3kUR11G3LtBwVl59ednVqq+Pgw58vRc6UTpw9ESr0u u3pzTljX9ecHcYZvgauCxjII5iCy2c/mgl7q3aHFIuyvyB6uu5lWRNCX1vSWNxNkZBA1ruMyZ1J2 1xNNnvIyOABG9dLeJACseRax4d2Nk2Dl8if5/8E+IKxn+n/I/R1XWQ0YvBQu223+r88Uav2QwqA1 eR5wB4cmFFEHrXe6XG/cmx2eEoiONjsRTdVfaRJqRjSIDnnROGKm/3Ce6muE391tiytnSpMBwvrq /AAZ8t0L+uzjk5j66RuGstxvQuq6MjAY2wQagifF20kv+BOhLD/QfBcnDW/zxkzl1YFI1YpKDexs VcgCT9E4h9WWIn2WkR+9jGu2JLavxUwCbUqwbc6FNLw4KYvWOQV89xO+XhvajH5CxSr8ha7YZH/s KGBUTIHJR84yxSwB/TmHdmBCjIac+SFfAV2qROmK3DEpQZAQoXPpStJqJsdzgWoJ/9+MPC6uPhRv tO7/jrD28VJwGZ8/ESbxVXTV+4W7+721yFzqIa+wpe2sbQ8IXFjtS6/3goFA1ZzDuSqbGlOegchN JHP3+U7apfynx/8HCH3XdBTF00mi/UKepUsIMmFWJ8o7ft2CDHj/iJ0HGzopQ09BPKMpt9IpCBYi kScXBsuM01OKo0U4jFWLdAXIpnBaOtAcYS6VvlbjgkW440d8uvXfov8im8NK/UC7sUmhKAj9r73z jCkFlnoaOkspnRLOt75dWXZNKcczFPSEmXq2kLh8/8VxEnDFW4xBjKIbrXGIEVVj4BZ6FxEpqQQw zCtXE4/hbH8w8LyGJnOJP6YpHHskss4c4oJ6+62OgmUE8d1YNSgWLOWEsUUGn7QAsLe6rEwd8jKw GHGYOd2/K7M07n8qzi/FhDFLkbblNqjAjOdRR+H7n44wrx67ASm39JzYD7Q9mtQvlfw0tI8Ljal5 RgUTaTuTY+WbtZiUFL5DzpOw2L5plo17vUDyWtALg405cR2Wo1nil2fR0oBJEWAT1ywfJjzyUxL2 78Dk+lzGToO2syptELi2mi+gsfjopsRtIMfEi9ITq79RgTaXCNp01fR5mLZFJXFp9CPI6oy4bQ/E E0A+FvfH23KoVBwhmIb/eVmt28FuRx00zczlOxeQZhUe0yXm1i8j10ibgTMOPwrzB4IeE2kuw7T9 Ihq8ExonYxJhpLWzIhFbJvUaHICMOfL8ZvlWlAFnTNFnJIrRBYHAldPWvLmk0ET4hoQ9DamH8fKk wQ9VWPutZzt0r79QClGHXIgne4P+omizthQa5Hr0LZA7orz30CesoHPFPnIA0QlmfwLHgBbnk+3B qVgI/1u3UTdDqZjkx9l+9Du833TR38hMOQMBRbv4B73K/5Rg82PWkhfS/QZ9qdwmBV7Mt6VlgvQJ fbik9r+c64twpnNRL+hm6m67te+kr+7ZEtpHpfLCnmJ3lDkIRHvwAVUhZmjlkSi8zCSaYBwVJzxN LaUAbst54aQYaKdIUxw5ebXbpPqxFhCIr3Zd30QGA+GXg1LWILKxNK+Sufr0NTA2a2P7zEH0KUiX lnR9K2CUfVSxIOiCEINvy3AhoEeslXizWjRDplMc4K8bfAVmapv96v9Pmb/711LvSneYTso6C7Zq rFLODQ3FRB30mPKv6Y9jn5/uPCKxPJ52RGJqWwKIuLxVHhSydaW/ZLKfgcnUD0Gv2Z/8q4Vo16ad r3+gDSE2idAYW/SKjkmBF4PqMZeBGA9PG38ygfHb1QHofcZ/8n6Uew1I7+0GFJvb+gAYecSSzY6V xSZ7gshH0+QD7p5EhxUyHqHioNbIGjQ3hk5kbLXI1SmIsTXCQ+SmvcsTpQDRBRWEWf/nCbBAkKNt 4gW+YLmoazcA+F7WTn8Br9ny0lKwDvke52KZumbKgDeHFzMZNB1a0xiy7KxKHTtiKUt2/cFfoU5d cDLQLhmLC0l6f2D3RHej4yEr3b3FIs6xC2E1wW0FeMnf1jGldRYnk8AGO4EaN1zZegY3f/eqQQwf RJAl9wEVEuyrI+5aUuecpdFIwQllxKxFEBJjTX+ts4slHpZWO3iGP6ZNAvBx+NDF6BHooxMwV0GK fO9MfzK7Lty1g+A/xBPjikvzy7puZINoS1U0K/35njrbJQKJkpr6OBfIa50Yy2O7XsllXchYqtuQ Tb+Gqa462BEIc9N5zZGlEH0cGaSV2ro7tl6WLJwHKb8aGLDOSQE/R9pFct08KWr/+2gOVPRSP/No BUkTmNGGynKKn9fLrB3XDgMYd98TS9NYfcfcR7pfC+r6CjOXvV9sS0hkCfU02BhUidXVvUo3ohVC cjDmHBdYzhf30HJOHx/t+/sr/mV0K/OsvlyWpfi1exHaHLNYcVMI9Lxc54O7G34Z4S8iWiZYybwH uVmGdChAXF0ycBWGrIU6IfcDXGMbTCoONsdHoJHXcRhn7hqLYJP87cR9J++HFGf+D16A9iMuvmaR /AobBm0AKELx+t91SnGN0kt8cgSP243ux5hPn+G1ZNL3SUyD8EiphkzrWMLmdiWJYp3ERQi+Auhs gf8Lke2lhdlBk4gPsC5pgc//2m2qxWcpubQmRJMxvPDFrVGIxOs8Jx57lnfTmDLHxlXot1uvmbxT 0+soNpS/B11i/9rxqouYR56s8wsL4FoimTlt/qAzFIR6aHBWY9vedWhMJA5gSZrZgKxr3xNpE0pW 2BNVLCveg/5M0fV5r3YL27ijzNjDULk4h8OfGFGaWIujsfMosd0fn1OnzmeBIg7aO+IbPE+1UTmh hiYqsYylvvkpquME8HWtbkEFIT6jU6OO3+bLnqDwJQtUFePIuLOJ+Wk42DEVv5oAgAzkabheQoAf vGf9wFTWemPbaelzu20686s6CM2+SFgtL88gFc9zYzl71uFssof234BwPtBIKtpDND1ipuzQf0ju Y19mLs1JYOPYCHTExEj0+l+7DMmcbFhpdcaybWQd/KWXXDreh0pEJnzBOX2AAhG0k7LxSTBpQQwh xFGIA440fDO9ofuWhcjqqyH3GbuJE9DwB0DD41LlS6nYX/AnOIVdlRqAa8v5T4ABqf8aX5bmAa1+ T7mWIfa5V5A+oMr2f0r6f+rzRHh7IswL8qMJT8oJu1t7oMaxkUMDB6jzTIvAdnIixdVtk1pyvVgv xm0qro98B9PLv6Ac/9diAFrV++PWMuRhfBxFclGtAebEayxWbE1HIb8mAB9D5MCM+Q4mGHQW7Jkc EWRUaN7WOsmIH0WVYcoqQQBlw3EW0tMl5quLoFqeEYIt7SbL6DEcPpM3yXrVvrxDKm+4JJlM1lFH L9cA7Lqq6cofny128DI064BsE0MNHonGSvHaU7GjCgztuaC+VA1P+MxulE1fE3sXXibXupvUwX+D OQ3eMWyeaCyI80IHMqmp6iVIhJmfrSdahI52DSdUmTAVpGdkM8EBgtiFyyc1qDvqzg1xHjj4dT1F lGQNoXUUdkH3hYb7mLigjRmMJdUgxolh6iwO1ZeK6k2yQraQLKIsI0+7BYFLUs8n4Xv0gaz1gktz 97V4zhTyqJuvFepx3PX2Eq5zkKI8lBtNAvvB2sKntEZAxpozeLeOPowfpNeoa7nPBYIYzNZ4w0Ma IkQCGPg/L0Amw+HaKQLm5/3jN5JPvF2JaMGjY/CSzjr7XfvxR51yPcTUy+I7uG9gc6uzrwz0AD66 ACKqTb/rYazIO7YNgsiTUpsKQC2xfpCsuvOdUMTc3GX0RNlcDZf/oJT4E35qWW8+Y+e68hBBKQpj jmU1AY0lmpKVuwH2R8sVaXwCU/oITcSxhxsFjpUOkgaEmX+iSunPYQALnDVcQjk6ucxkjU0l303J hnSgU1p2EDUoCavsRrPEUE8Rf6MZizzkR0gZBqiYMwoJtz7T/hvF1uJXxcnLpMpBvXYs2Kbf0ZC7 YZVzOe0hA/iGJdqZBzAiQzLZDBcW0eRZF6Zqwi2sHnHg/LtLCE6JihD2qbLBZR1W/JI8sGBBMASs IqdKSOepT2m7d0GYdc0joFM2ss+q9iV5gg6fW0Lib8C/qyF4SxT9oZV9Bm8pe7jQFw5jU8Tv7VZu fvT2NSe4mdGDBA4ZEFN4Beyw/VuHUvkQXAVnp9Y4nJLyjA4eYFBZE5zX6cjgLBWpsIC+lH/n+8sY o5j6Gcna2L7bCemYQUlG1sK1s1omrb/dIw2+H0JGzdNtc1Qx3p9AAGczjv37/MOPChPrkIptJtid VThaCR9r1jNwNrhJsxavlsnfWgRdRQErB5F4l4F/G2eW62rG+9jLjU1D8vOYFceHnjeMd8Rff2C2 CT1iNPGzg9UAO2oiPofxJUPjLTJ0FL3oGQaSeQHkl7X48mASVF2BlQcpDAtbohSkwB4DKuNoQfpD O5g1SeE5Mw0Nzddz5zH7ZtWKd5+1Z0tUYUbcWpdp63kkN0pUa7452BTFIxD98/XKmlQbyjC3vZJq HOI4hRDHNBu/n5HcUdEE3Y7PUNoAOwJa/3uTrb67k2xqdrESU9Bei6Sw9+NcDmg84rapopk1fcSY qVNTYOs0b06D+E+RL9e6/wxs2WOvUavWW4ze2ZmAWWtIHup2Mnx1843zAqz0rKUvgJfb4zMtDOwk Zq9eeWkPch6U4KX6tpfcOkK8IReLi9jFeo/MO7Oit3mrSre1d8tK3gmYqdrhqkQWJmDEV8KCUmqb McGuFKwvUYDbtjNA8bSRzx00xpjrfhPOcM+RIUwKT4GktNpbjrJ8uD82CVVSV10TM8w+Gr01ExOC yCseTq30r/XqYyoRC+buiDJO5HXepNaUSl0dgMsNA/Zu028lxrnYfU4lpNiXNNthNEdBgXEyCqEU 52ptTY709KkWnhsaFzql5DQY0SkOXXyuKjUSrgF13lRXqwuLw3OmnuXA7Rr2LPVuC/tsDk7WG/9N FTq+irzaKleV6ewBFAo6FoR383tFBsaJdPxb1eC7MFKJJ5pgDQrfd23BkS6PamGM/48qw06HlR7l 8sKA24cqpvMjcsb1JcvnyOd4ISDef7uUGz/Fp3ynjuj34Dj1F8UiDWdoopk6Z6Emr0QSeU9wXfaM iVghTeVAoYmhD72pjVg4ZVmEQl38CGOT/hXRnuRb+Rc4lAidsrHlDsH7DggCl5nbIGm5csXWOM6Q p95CaX7hrUx5wi8/Hn9zGoHJNfVKIK7CDvGIhgeLydSbvAHprAPX9knjDgDm2bqeLpBbV2shkXZv dcKjvS5z+gqzC1xVAE1NHJT4sclFNRy/jMn8AkuiP5ObjkRt4muA1xMjsTqhI8/mtrcbW/rlhP+q Hdn2SI29Ol8BGxN6hHF0rRLa2zqfuxy0cX3efFelapQsuH5BDtWzTMjQxtSOw5+YlErhGXfeMXp9 puPpDCnWQkLgMk8RMosH1E8WjslZK/59cLi1sDMYouVzIFHvT9yc9b+Aj6tLYwrnWvpk8LDKVSfq 70rVWfU5q8caGlICmMdTmYY/fq6zAxDhaR8HM8ZilQCtnrjex8tMZC29J/zAQd53DolWHMFKObKq 1zFCCzBLzPjKQXhJkHgZjKB8sBL2QoAJ2QKFiw7whK4alHnjGVmwn2gnaCSzJsSpQzNdRrq/9xz9 wTkfBEcppG9mIy7lm9/gpVySs6MVJof4lE+kT3pBEccgiQoCK9FX5mivmCvocBrA9YwXtjC7d2CT r81P+W3eL0/O38j3cipo7rZFKQOmdGkdXMN460l5wUluoUnjCWiwAf1Zrz0BrgNdqIaaIwmcr4XQ PkiNIg1bZrml+yr9WW8Ls1KO3k6JTEfMWBiy+mpKB8QJKdVkScyCG/9Mzb6U7JRIZbiz0XMPJref hYLNSr3sY8tZk9cGKJ4zPSaewPbGSrUi4pS/ek9vP5m8boVCkTJtZorxk4ejbdBUvPcHem5LecUA yUcotWpBzhAvQfAXwgnFsEAM/6VOSpalNKbHJ9sp3R4epEX5s58iG4YSbEJbYdnRK9ojn2K31mKW 6TvQ9d6YaLY4QLxVCjDFkfYuGULbSIFgGF+B3IbMAX9zEADN5i4xY+wbT3WQ4k7wnPtqtUxfiYSK 93f7D7dCb6NW8cRwMJ8FnzInzkmI41KhDk/JGDN2hkP51Epkc73sUSHkI+R6C24AuqAh0mnktHAA oSEeVcIM7X32Vk+okP2u5Giv7vPtlEk0Qq5M7ArfhdtQVuz0CE7uCgUwcwBqFaW1oJieFQqHBuL0 xPG0s4/lt7HN2U7w+3C3mTCyR9moVGC/F2KINQSNPzbvANOwV6oFhBDkblBid0qA1CcEWuH894ol 2P9Yy5UDpaEKFuFrSFXj7dPbLSKUcUX+tm86Px7dLfD02GLIGJF3FCSWTG6YmDF1qWT8HLAW23xR m0ts8lRzcIZSJm3ByO+/5oprmK9Ui7zBLzaEtLtCJoIBRZSrEZD9d4ErJQjYqiSyN6NtVBIQq87T FCkOXjbiSYXbDmAeYETwcLixiIx3RPRbnuo2o3hoMRiGarheHlrSEJNAsdtayrwdJvmIxiPKoKm6 kAGECYBqjFcmbpuRpU9UWCiq9mAYwGEQEGWldfBHS70LPLUBAtknuWVs1ybERobKiPfyFAEXOQna bbruaPlqPX5Yrl/2VB8p3vvm6UBk++DqzfK7ARJCzTQGrbjzlUPFaAxED9SHIb4rXOCKykDkX87S 0oAcGiFtsGroNA1eq0kmCGMt4DxccXCqhe/1HhHFNxPB2HLrhBR/tb7HuANm0TZSIflJjqPHaQXj gWOqG5sub0RZf3kQicTrHRMq7gYiSMrT4B2eR2Sx24Ln9CcgkCuP9PkpdJXjWK7o0yUjaZEL0KTg vy+d/awQurOmoRTY8JrlzU6ptPk04u7sVtwQOFdjhqynBnMLPPfbT1Vr+eA/n8V48gPiaHxRTOo1 B0bWZ201xpVMqjghB2sTlIyh/B/N2zHdcKAuPDHPMOkxRLo+6/Yiujj05yZp5wLjmKMpIwXUpMiJ CIuR8n3rT2eWX9ffRWjoZVbEcPA+W5leh8s4Wt7NuXX0Gtyw/SUpuVdI2rBUi7pvpW2v9YR7ht4n TPP9tGQHPzwhwbtxLroy31nTlIqm+d5hatAL8lQYc8XjcndpkA9LxL+YkWzV9MWuPrnMKnIKUGfk 8+EuJHAX4Mkt7AKsZAcScPdQ2oLxYK1P2Nslig6B2JSF1Gh647iIQncggrjmZdwIn6kaAKu2KJSj QHdVCWHfxWec6bhXzCadOgJSGsYi5Sx0o7TquV4fwP5EL4snD+eYhSzi8M9Sv+lvCdoqF2YOK6Ld j0HMU7Sa7UUzyTx3eE/XRF/ZlLMgbDv7sJSevbrh+3rBvkfbAEY2qvaPDm3j7kuPVPBKkiCObzFI MFhRlxbtaM8JDScY36j5QJGy8/Itrjjrv2FwvvhRZtId5yLWC5jF9QNfcnzv7BpQkNhk1nQya63Y 9cXAyW83qCf6TfBEfuWfpkKg9SaB4pUNskqh3ILnDCIMr6386PlUjHMA2Skr/9RZv0LifXSGtP0D fp2ABts6z/893Jj2/FQ1bNLl0LjcVQ2q40pJZ1/jvUOKqWrP+Mm5fpgnHu5nkDMa4Z2xNTr8SXE1 7AOEAi6LJ8KRiGKryRMABrEO7gQJkX824vnEd+KYnMPTYikp01qokeBqnszMXUwxay8K+b+qHvAB WPXluYbC9o/+7/sFu+yGZ2u4qJvWVPF1TKAzY/letXpLKWo9e15VS+3DAYiNQEMIaPxINIln5UJC efwAfgJeLRF8OIVn/ORvFKRK0ejotEYzhPN+HMsK/UHe8TXpO3lWaIJ8tUol0zem40mJAg7kiHUL jGvpJzaKiYuUh3u203C+wbuJq6YrZ9C6Ukr9+cMq8PJMrPxhfFx0ETLoFUdXKYJD6jypOAw1s90y 470zSbYsSopxzkAjAodz2CP3j1pZ8VLsRaueaqLFnE+WeXV29Fry2xockM/IlxH1/jpAwRkcCy3J feJHy2G5S041rWMWz1FxY8whCXQYpr+QhfXH85615epr8G1WA0bkFzVy7WCIiuvVhtfK16i02vw3 edOcFee/t4SUOxwhFpF/fsGLrm6RsD9oZuCTp3f1Qfq9nBhcS51YN+bN4SmGQdlspZzbZLt3cBeg UYPpwXkfFu3F0VpjgJU/z1ynD6OBVq/j4G1dNtv1dfW9BOQ8Jo+RHYO1wTjPOYrX62jdUKp6orKN ++frmfbEGayAa1c0cOIG22CMogk6fiOiD00OmQFPoo769pvfengGC/8pgkUTLbOuil3NcIvarQGs a8LyPeMC52AJS0LxUgGSADievlWER2aqMjGzy+5Ndm+vFx2SMcRU6WonSCtTYk02xk9B290qz879 plfRv9QnJGWrVUKNTwDqT9RdfTy2/MVwmnjfnNPg5BLEpOgZ4KK52PtKa7T7F1VqJ7jgLTU7TGTj KpV+3bnvk5C77C6H4XJ7fus5dAoEwT6eNDLyS0LniArggrNDKrU2Q0ljElhP4nwg73D0grbLzLbA ObZrX/dMA2nf6mMWpKhVmDpNWH5uzFbpS2h9vLyOv/f9ElF5i/c0ghemZuHsp9oBoL2yaraA4loI AGAANWvkn/Hz3jXjjPK8ENjBNEI15t5F6CdAsSAbvnvH8WlBNIk8I51jO37/x4dmGAPpvhiIKHSf tae+K4gDEiqvKdaaUAfBiXfZqSeZosFQhwBO2HVgZU36XIbF/NyynTecKNpdCRQgXB9Td+7YWaHD L01BEsXr2px7EWcBqYsnAst0jPeBZ/OCtYlo4AwZ9WNdq6SeyvD3I/l9DDwL4BxADYqSHZWjz6FV AvD5kSZEPYeX4JlamdD6lAQxqQHJ+BLQTfqrIpTP7jLbY13qOnLZQXKhGzS5TYhEwy2pXbJ6Plsl D0zdU8zzZdM36wSPCCc07CLOxtD+RSpKWkq2eLOOCX5XvqOwJsAGdoRfPR7e2Ws1pYNVTcFvSRXX DQVrjgBXESk5FSQF0eIm+MhzJcxTTP7DU139t3t/qMKiGFuoVghIqYoXpoI0xS3MWNdgDFORsZpx 8/x5TE0MFPHkGZz7o6muR7RlJXt9GylSpRHSepbcVmwMyJqO2mif5WBfZXfkBYIwRvoL0Gi7nh43 BCbJWf6ybHYtwnUcHE4SIbtjVdxfkIKHJPa1KcsDrHBOBU9E2RewJ+/fQJicYC58VcZtxHPkeDCb 5XT3giOB55N+nyRfIXibd9Tl6tE/6j0GAwc6ULZe7nr0NyaSOUZmKeUQfY1mZo8X9AgRr4jecKsw eAFD4cFsq8QDj2qKrsNgaK4STTvOugzaH4b8pNE9XDnZInIuFgFKU2PopGzU8R7uq2J+W/NIUxrb pwBZWy/7E7IfmPsiYxqyMK/VCHkctNihznu9ebEGwlGF42FCccb60hsz4wcV6UKMxYxhQMAC4Zoi l7VQVAt7LB9wPg/GlYO13zDfWjtEeHm85mMgDfCNpx8FF94o82bm+kfItaMwYBlmVcqcylg9DW5G qc7e7th9CtHvKue7NJPTrws6gM/RfXdZODsUOzEysryPoOWfXfQ1zkPLDQ0ss33pxyS4waWUR5tR 0pbAIdiXMOXuyUzSFC6AaRstAa/WbJaPSlxWDbgv36xQXKk7qHMv04snEONY3x9HjDrOj6BT4uIq W1kVfQ8RIuPI6srjSZJKPx7edh7t+sj4l7m7FP2tLltvpo8Fd9w+vKUmqArZ2jyGUYrBqR3giszv 1dQOj7uKoygMP/K2te1WU9IZGrmgqCNa6MqA+tDBrJ1RP5L02u/EOkySXDaYOcHT8w/Swdx/NsyW gkuo1LQq6605TEgzeCLK74Vt4IIzdggfnk3DazXlGwfF7ib1db7D28cUStCQXLKbtU69ReRMMVSl nAp6RqmlttbWljvD3Kygp0X1x/368yH1hQPVqHu9QN5DXBI3VOsP+gBGoBnJjq+gkwpg+N4XCqiz eJ41+LGOB58cORtu3kMMsOa1uPTK8d3IaeNq5ywWy64eSgoGPXp/gU61mNH0QKQbRCf6fqr4DPes DkerCnNgltzPbUlSfEqidfOVuSBaWO4s0WZR7WJnXlEYkekqeeB7OKttz4LgPeDosIkZwazd/AIi xPJNlLa78Ux5YoqA++oseB4Q7FVF1aILvuabk6r5CqBnCbuXO9mo80v5MNpLfzZO4THN7UO/3d45 UIyPHgb+rkiEp75rYIacuMB9nU3CdQ9zJ6YMSE1TbVAaUU+vKxwNdku5HodonCiXQJZkoMXSFpYE yWlXdHCXq8GyZaQtyb8M4onO3eRQEagW2qPFyXFbw1T9PPxQX5LOQPrwtfROT6nVdRMf7QgxXcsF /Lejt12bkBtG4W/PumJMW5iDc3JTVvNzzaR0+UajiF8A1Gr2Ifcek3o7Sj9GCG1KFvS10FCGPssQ rY/lmBMJKyrwC2nSPzfLNuV/ZgQEyLSmU2sgmr1Qc3MJURPKiMdmdMGBLJ62tcjkjTTMyb1EWb73 7EkfqYhhO+kJLa3CoB/p5oBQe0Lyv+4A+gx9gbeNQBYmN7CPxITIX08odmMn97K8NvcSh8I5AaoB lk8j43DEQXAn3XW/g1n4g08qWF8G71HPlQrhqr5/dGEYjaET9m/RcgdsbppbvP6KkfAJlYOEG/w/ In7dWiWEkZRQ8UKeX5nG5QSYt2vR7fl1cTy5AxOYQh+7Xl+6Tc0JlqTHXodFf7F6vdHGROyNN6PS YYXqU3NTBw7XSPEzB+K0jsybXnbG8WhzaLD7/OdFhVom/5XQQtK5PI+y5kGV5WNgac18AOohGC+v MAPaIrPs8bSmvNjKv4yBUm9/0L78uAibWYO0SQU6fauvvan0z/Z1lPzJiP+MOzpbeTffrzkY3LU+ qTF2zW3EE/XViPvlMXZxxRQtcQfZdBWJ3GtaThWUu9t8tsqpOoAH0f8PTC0BylLiLvZ1d0RrMIpf HwSTGXVwcwCjZZ5rZJtt9HmiM1Ibs82TpSdgiOPnX31hoN4o8UGNOcaaOvgF6ckbEg22bK7vLyKO rjxzuWFAE6zFE9f2EAx5/O40xVi8QUWGXdaDQF8w7YwSMUmJGmGmMgsq+OjK/mzPXnFoh410uWBN ldcGgbJQGqlgDMDc5MtgH392xgJCwUk82GBpEURiDjtvLCBj3yxdArAJwgpZIIWtEaCiNFy62bEh NmYVC0vaCTGM2fXK0mNXAUe/I48qUXYpiHTkpEmGoL7CC5to3vPaepPyvT01scH2cJgZmv7j1IVa 4r2aYazgUyld6PE4pR0/5xzXI42raIbx1LqdFjcHHMOVkX/VxzqeswL+l+BJcNxeKY172mfppOEy I039OtcI3N9QgDWTnRLMPXM+JvNjvZUIV6EUwbTYYD3dl8iNgA0JHXpS29UZnNGOjulgk3dczmID V8XmOFC3OIWMHKeKAUNUvNSSvWt557xU0m9CevWQArylD8DsWu4lo88ZUdRjGSq692110o2gPtzh XK+Cmr6ex439GYWU04GBYasZlBC2IFyrJDxEyFOG2ki7of/YqhBvSIS7bunNkQiyoFwu+CwInwuz f61tFjO8yyY6J+TBZGIHDghdaODq1chBMyCnVTI2Bt/XdUDNhKYGyuplJo4TnzhwLCgzeqJj+dof y3pvTy9E8D0kggT/4FmnVmSuc1kEvMI0Z3BFMBg94vqh8hO9RwlDcnabRLeGjlPdup49t7CohWN5 NWXdoLIE72fKLViuBMy+6V2ZP5fSx0XFgqKcDTWzudG3ANZIN9nX5C8CUN23dY++731AHMx5vHhP Ue4vfaHZ+sE/BKsT+9dXxvjz/cUiuH++J/CrCym3pravUUZtV8BY4r8DsUtEAtBjg7PwDgsvbe/W 8tPR12p6BCGceUzY902P6AHPiPjM8wSk5UngyBMgxKiksxkYTfbMot+BKqUnOwFZYNLDUAOON5WG niLezN94lc9j0Rm6vBqmn+3EZRfXPUKl/OPaF6QhPxkVjLMU6SUlUeVV8TcUYK4BQ2nrZJKwHTrz PWhE1Zu1o227Tqi9begqdqN/mWdsw2ThxMNuiql4W1+T366Q04kbIKm7nOyPdaIyvBp7CxbYhqrD tqZbm1XjBu9vQ4jUhigYf6XpWdbs6leouH11mbvxmAQ4ZVeOatEUT/uY9fXFU/qdVENIXAtNuRNd iJl+/cQl1hw+s6HwmdG47DI2ygStV+rlbU2E2pOA73QnDRWT2DECn4ezUk3xAnXJA63s7JFwBQvS hWoKpcA6fHRmVB6Ae5U4L22OEP+WmNWYZZTQj9lEUS9pBKucY/zqyeR91Cu/wnzH5IotzY7Wjvka CZPXxZ/TmlHzLNll8YGpuxBIzjJDv4962lmRxiqO3yoO55zWDMOxaqEEWk9KJ936rXYmIAFZ52EQ JMjsGtXyeS7pjRrTuKtYtveF47LjzAAGQ8k88Pj3BLoOj5f9u7SRcL3s2ZmjVkrLzEW3rtw0xtGA 2c6VEnq3Xb1TzFKz19HGxlQ9+orZW+Ely4VveSw48n4+Te8wmF11uIIUIV58C15UAWy4ajcjbIi6 a9vFNproJd5b8TK6bIB1Fcd12IEKK90Tj1H97iV/ezAioCYZmHbf3W9P7suxKB5gFmRSniv+Y+Zq 9PErQWBQGfnBoSPyI36iznGI7z/l5ZWk1IAf/tc6KYfdrNpybXiurjizrEDgjXtrvJWs9mw6HE+9 zajGngjc0QMCSyJHe/UiEc2UBfrDSjKzAnRYV3zhnD/EsOEVPOSyJK00JmFNXkRL4W5EpFoRnYKR f5Z18BEpzgptxXBrL+1JDs3EWABAqOzudQuKEDC+WMRfd7JZ9q+WoQmPB3AIfH2rGXv1EjJaNChI t30K2VM5WNEDfO6AvP5ZBDMyRwdDI3FyEfy8I017qCrA8b5ztkuH/BVPhN8tEBUnviIYvOdkrGW+ j9tpZsJsBwd+xLuXZblep1+jQmdcuOyFWC5t3OTCSdYeqykrD0zH7/vYyA2sBxZAB86ZG41DmFN0 Q57UV8XOtDTvq/nr7m4N9AIDdXGQ4HmET6XMNZ/S105QTQ0RtsZwHUr7m4vc3FNiTsojc9AQ2s31 tzG39p7l0hCMSrNr2GgDU5qsVlgndXbfXx3LV6GMMq0X/wPXifV2TbdXAtFx3cd+35tPiIlYJBXO 9KhDQn4Dhmh9Zru7p3YTgz2tFcmCNPD0WFI4yZw/m5jyPC2gyUiIcMRTRdtt83qjKIUI8Igsyg1p GA0dkRn2CtgQV/bZnk8IhrFC6USls3QAzoshEKmw2ebduXcnnsY3NbB7NxSqnP/9XrCYcr2+eGp1 8SfByXhUkFXpWFpD0snIoEDOv8PhAy3hbxoHx917/AF7E4M3+PXUN6ON49jHcL8UY2nGz7gcTBE9 VnjlvQsDGMt7dLOpn3d9OOAdsax/xODXOrm44ubwwgu8A//86whEmSvOjQLmFbguThvvzHqsA9h3 WfwTxIg6shcUggSs3ZmA1x4IamGIOZuyNbgVEH2qCM8C0PCwYzz0LSZKK942KPqSWL2d6Yvzpol1 P+O5+sGo1AXoQ3SfBaroy9lWx0XV/mVnMq4CvX4U0yeTAY1ryPkjlw76EHZuA7u3c6SGS2Xf0o0P P5cU46WBpm99fOrtk1rRhXxZxzqylUpvx8TdwAJbWtzKF8qVeNimilieVRN2uszg6LocVH4KbXqq r3x+DooCHbUVEtrEGJ/mYh4T4dLa53AmPOuzkYyB7PLDhou5TzvjHqCYKl5bn6FOWvr9M9ACU/MP aeme4E1nC4enyYSGL0TwuN0fUSuuNbJrTLn7HoJUyPofp67LxMVk7MbUZaz2Fz0IlvmB0Ts0CgP5 XAIWujaO6FMkUH5xUbufVD9dOfeN8ofrssFfaAFjFpMhYzBD+V5aptuGEiFkIl49aUCysh+kzuuH Y8ik8WwK1VDC1PPXReHMURKW4GR5tSIpX+DHomuABhOkmZt4q4S44+50lQR13Yvv0jRrdGiFF0/q vVXmpNCkJUqxXg0fmhxsXYfR1pmjo+T6G595S53oBITY0439KnNG3u4ru+d9m6I/J4bPlkaob9Q1 avRMdoVL28HmTfosvPxSUTbdWP/Tzp2nkDWVucUFukSRR9HbDaFnmedAx+Pn+J7J9IM+K1CvidJ9 tR9P+pUDNVpxiCHjJyo9Pj2pcVYGPQFyGGlN5AP6i53/5SsqpBVRnSFb9UfUPI+1pN7cND0NGqTL aPY77L6hXIxYazAfCKe9GtfyRoqBRnpzyef+SisNtKKExJHXFmM8qwPMz8+LK2KqjE/FLflaR9cz AQJp7hxZA5fKxT7CDZFrRSlSs4Y6tiYa7MP9T0M89kE7ADNc43JewKufV5U0M5PSJk3MpGS7jYCv 2CUv8i9dX8kZUfTuaUkp/o3kVyLh1k51q0kJk+wGkoAZlZAUs3IEIFqrM1LdjdPDKk3Qfhn68KdA CNzflAy8/hvF4jYK2THVcDzr5UHD7dSwePr5I0gqVVrMjQd9P3Tk3T697jYNahXWd/AtEqSMnpVc vhKVeIMLbi1MN5UfNGZy0vFwaEVb4mJ6aY899AfuljS9nyYA5FtJSn8tHuLf/CsL5zwRnL4BroJv bJkhOnpghtUpRj25HGCHJakheMoWtprffUbdjiqAgT7xX+6jujhMcogAtbEj3DV4DAfX6mrQp97W 4qu7z0a1f/19eGEM1tT161P5W41QSo3dLWWslcyf0kv6P7sGyZLZvGWRbWPGYKCYR9dh7G/HJcOY yj682x1JbBbgwCmMZLmax/LVC4ZrWb92j9DoqbhCzmtFh2Su/DfWrhPLG6HJnowsEGOQsZXJ2IeP hLNTXxn3uW76d5uqdziqDIEhbGD/ZgsKQLSR024e/uYrSctCx6HyoVcnXkvE3ab0DhsxMRvfoHuE dYbAyXXw2u3grIYO/dyFWEbp3SkM0RiUV3fC1QxpFBtB1oYIhxgE+8I05IXk3CrWQ8UNvjC++wx9 NYBoXMWq2K+mdji9UIjFhx77QqwfLUgGYtCvou7iaiRAuXfgJOaBKCZxUVQviuvGqsI+64Kt721N RQL0UCCiyU5+VT3J2kJ8f42Om9swU4ujZdWGf5SYxS2tmkA93s1OrWUE/p5xqBGf4aiEnUekh0QS RoQHaPwoEAQNkdbzpFrIEsZS4qx/BGRFMpzYNfPjHvftsmQh3bLbZVKG6VPX9TQJhsweo5Un3F4y m6RLpvySi8i0i04yasUAgVlRaOaYNmtHZK/EXD/XcE/qs4KkuZvWGGljJdM7X30+DbqNnNu2wBGu izs1pX1cnaaWSBWUEtB3wzpZ7JHHL9Kkjx14k8Q0Gn+w0XQuy5v9PjYCUYVXn2gSktGaar76szzO kjspolTK5ykqV2cOgKoZE8RlCemRSP0GRclke6xdDcAtLU0kqYOQ1neooEqueNc8uxoxGShM6EAh o2ozTaU4HuqEVelkf8zImyxueZdZJbcTj2u/hlHwUMrup8XIUddyxLRqaARq4z4XSkITmKau7tuU +f7m2eKd6HoZ7qrOnriHTDqiq9dAZ+9hjAOjsTvrR4BAef1FDNRy7wzGwktpaqAGwPh6h1etIxB5 7Ncx9wD8wdGhb2qJpPMf82rbJ/VtnLteG4UYkP9MBlvSG9Kvc3gNiHM69krepgbX2qLwRj42aM7D T6dki0Pz4JCNvbbkV3ZWdnj/lEOfLfuM5Pdnc+g95IgnLPBrCADW5bZzhoeQ/pHhezuF2FqyqL2f vV0kEuxKP1O7nZR13ZpxcVFK/6U9dB7487qeGumW2qi01GGkolMrTmetfxPyh2jdYVuoNFs88Y4u QoQyIfF5Ji1TG2/gZC2PB5xviGtNOfdzcCIcnj86Iqw6Q6aqnHH5BoSz+HFGTBAyYvb+mIsdTCM/ 5JmeLsLwjF9MWichJFGiZFalx2lMrb2CmqLA4SEWYg8h2eZpJlbQAeqE/h4qUu4ihdZVlFz4kiUK c3nSIOtSyTIHxDFnZefMma0oVKgfGAKUgO80vEwgPR09MTdQS1gf7gpNfE3izQzvG/JTTcH2BBux gA6tZcO/CCw7gJtWDiV2pFN+iZg0/URi4vOSbLlsG6SHMF9HEjgoGH/iyuKm4lOXb4O0LBgFbb77 65vCb8gnKzour2TSinHgNegkTgeVPFLP0dY4aubKCTzrJlzVNFSQNkaCj0A3PrxmZHwOmdBeHqGz Hn54wEvdc4xIptAM8txYVVds+PJO9HSZf5uqsBuY4EhYlB4V829LH1Nsh3sxgT+10Lc2sjAt7NPw iMMkMLsTaC7pXISlS9y5M4cx97aC6nSv6fknyad8yQ+LDHjQXjPLgPuJJiXrcPtz0r1gMi5u+KQQ hJIsscOvrNWXVF5WLe6zKgrAMqaXlB+wg32Rl5Q/byaslC4yKzykX2Q/9zVmgpxYCeucVR22U+KS BnZ4QshBn7Ic9xXr2/WwlVX3TyZa5foGNYarF8Fsx0K8BxMK3tJs1TshpYweaMLOU3m18jDjYl5p myChaUNocmLjbeMd2OB+lnrekH6Vbu21Xoy7/gL0o9MZX3EUWyiSAUqnQOLQEQj8eiSl38ChRy1g 5QHeti7P+bXa1XjKqMopDVJrw6fdUg1dl6s7pDGZ8x0jTvZij+kL618/C/imX0e2r0S/AIN5u0H3 QZLkWOKZ9QBWYigjX0SCZ5HDfq5Of30yxoTh/uxSoWCsjVrLVd4hnfVpTDzWo+dnNpo+KqJnuNh0 Jt963k6r+xxuA9Jvz6kCg8sq0NdaPe5oSfq+PX5MFa9pBcpyS9KfWVsTjFJW+T9BBxTXHGGEuUoS u4A3XYpi4+MXGZq6vCaHcZfe0LUJdJmdlisbqPVCYibEnJZxoxURoxvXxl7dBDXa8miPHWuj/EEL Y4DkVlhjEax92Lm/wSfdzgKvT0ysV/Hn8c+ckrif3+UnE+Wvr5r7BKb0kOu3UWlS3MF62rQca3WJ lzGfMncH0Fxmh3bFYeL8/uowTX6yD/JsW0eA5efV2i+I5O/4+mxU3dcj18U1zaWDvlp0yCwd00Cl c7IniiFHAMEnRGrKkXYXKHizUWKcyYoPYLpbOtt6zPIDL2fFvskTeu9H9AYyIY14pxOMtQDWEBHx GzKTZo1PNEqzxJNx/t4gKL2Rx3aNFSzbMJioJgO0sl2xrIWQLr9gvD/sPrQ2Rym+EjaiHlnroAyE RI1z4XY/TVF1ozcPZ+2ScP72nd9cSDaXMOTV4NcbjKfhcaGRjdf43ZuBxj7y9MZYSa0J0FOBTRvU vUdn3WdZud/l3Stn/KL9l9Q/PEibw0aSC1HdYH/RT5kbifhQjj+9QX3ZUAWk+UpjGmGs8E3TRMxP SnDXmVlQQgtL4Ow/UuZUl4isLGRxaTsphKmqbRMGAYEcBwvyTrwhuIRRgt5TGMy4CX3I6D47tSMk Kw8yRm1DnuOVfxT3mE+gKG7MfdumvPeoOKoUZ/08oiA/AGeIMcWBttK7yjn0OqyjPBbIeXCc5/TG sMWOQbupvujSSPi/TVHUDx3BVSFPcHIMme5b2hu4+rIuDvO3X/EOprhpMecn0AAZNEbPTNbRbKf7 zc/lqCoSonp+t4P+cwgV1tUWiFLLIdSGJp9PBIk10q8+xGSGCo9xLKj6Ul+h7ioHiRZtXk/85S/p o/TIx3OqEJur6GF0lHzq2V8NAHHoKVUs/B3UldpA4EHEU78oPiB0Pvg471QyQgufrY9qBVpndlln cAkIB61ZzEFhmBlhp2YHhab0lZfw3MV1m0jp/HCfzVUIBpqCUWmaX3pJ8mQ2HWIC51kmGCynHQ7E xzrMO+TOSQrL71Q+dGLTu1fU49GvVghShjZzQab5dEso7trWaYcVVQIavaC7h/1snL/XTZM4m+xW d/8FF+Pu3SES+wLglA60LRQSnRWMzscTojps0tzE4yJwTyxjHpDVbVp9JX1olzT45/ZC6wttSp52 b9jl6ZklAbM6VTv0IFC69er+NpY4eAtoVBKcpysNBrqqFdLI/I9ptLK4gGANlKokiVvm93AiLZLq /UJxD0Hop2mQ+W4pSdXOcBNv+rvLuSzslIEvtNTXEW5ZuII8ctPEIf2LeaoWi6MYmF7znHF4aabx oVMbuZQorX1aofcWa0XKa7yh2MElaMSPNfs8+Ut11wiIYOOxtb08Hy0oMCK0iX6DzNajBTwztQwc rgWxCQHxF9Aep4ca/+N9iNN+WOg96Dhy7smlly0O9uuS8mdh1JGBq8MjTLd8VGWaNXJBaBs0cuET vk78uZUy6DYpSGfTj08An4hsZA4smfivp8Fo+dFGK9tlnsgik+BXY+2zSBS69ghlo5R05qcHe+34 p2wbFEGNnK+RIRJ+Hk7jF9/3JOjCGWoWmL5Oqpn4OaERuXLYPwHi1IyJkzHXJ0h0xmJmQ+0Vp0j2 QPdOigg7+qd5a//koIRd0UzfuxMlDYWM9YWgyY2G33d/rHKIWnb3cgLjlldlGsWoMo4i8QjSvTAh wmNf2PVV1FDsM3AtNr2MqNFlLggxZpgvEwvLXRDbhV7l787NoQ+iF6Kn1Hiv4rP+j6TbfFqZ+uld V2MkSR59Cj0yryQbcSa51SJdM+yraL5UANUNag6OyUF0akt1g9/QXRXSzuq27GAYZdDju7vsSgeD YTMzK9TeG3GIBz37YcBLNpFmdrL1D1WzMZQ3QJwu4h7WrZ4X1kvPRPU0JfBzkAIZlMRPJtz9srkO j/qhdpMhINbBDyGIfXVZ8i4ou1P3UmB9Zqb3vk4Zyx39ohHy8Fcffxcj8+ctWkKWpLM9Lyp1CDRL qxGOapb9tR9rxMWc3Xr6TbbS3BHIIUKISKvJugVPJc/lSHjkuTXq3bNd+jEsK+uc4t9dNG5tF10M W/buDiFm8D1L0MBRrHVto3s7SJubASIgS+BXIP7QOGMyBTjSZmiisLIerlSBT22+NWWKaduNFHyP eL0YQ+C3xcY+mb+rkhVRmLUs6aOS+S855YwGGDON0h1yJhu2CCbsv8weEsKpsNN7dhHWrsOClVGF U9RT44jkG+auJFztolQ/FekmgLcRDySIcOBoerGTfRHXy4KjT8XiSrNNOUV0/ptxdD8PWlaq50F7 OF6UWbBvOH3No4xE+8F76gqJHa8k0+fNIsOeWPtc23gVdvHQMmzN28892xeza9eotBdnSjsNCYV/ +nKvatRNbRKUL75v0IttANPNL0eqjFc3pUp5Vo4e0zO4v0QV8mfL6ISq2d5Q9N7MgXRtPj5uUVLf EoxCd3cSxdRZH6cW6JNyVzd9sqISBIiVfHnm/EBi8qgtJZEIloybn2rYQu9JJvyXbvIuy10bTjoJ hnDnHIVW+d72Io3VGCKs0SlvZ8ftDh7uc1pY73Q4g9IEJJ9/xSd5CQdzYsN1gHpgQ8hXkuHuZsTp bYl5xOJDeZpb36cjFaSgbyLJTRFrfUPG3Upi/zpEqvIA0U+a9NW32BRHDMoGOgb5+ZqXY0Y7HbTP QmrCaAjQ20jVuTP44hdOxEGH9Ic74/maJee1jxBGzVeer/LjXjGkPdCVks/s7/UREB0oYj4iNSZm p4ainpAubX2vfhcpEkjLcRdJVNAEF0j5cFo+Pvhl5gUhQUdtcqt3nJ+aZwRBYvswVDr9KaydwUL4 /IL6NlASN1q1aZVNoijmfFFt4DvgOeZwWr+K4uPrIVncfu3h54MLEBk+OF5boAL3eedCwPI7eoUR 3e5BcoLpxzWTgtdMi/tFjECETGRc/5fkclPkaGUlrpRxPu7C1iBp29sj9VV+1MRMjVxbuyqkcIHi V8Q/JSm9d6xqRNXQcgN/YVjbz6RGzBngBeRArM3tAfcDggzZHV2OC/Edo74oyItAMsKXqT2lEgP/ u5ENRvnFunxv04xecN/UJNL13cfPtSvUrAd+pwjEzZAOZgkyQ911VM3AP6p8PwvzXko+h6xUMDHj QKRiHGLMOHsHul3WUA2NgzGkJLAb9Gsolq3ZB3Td/P2HrDKJNV/iyxoffQG2Jzkyh0QrAiMyhB9H c03SFESwBn6gy/IzruJg2NbIxp5xm8O8X1UX2fDblk1Ny9RAVz0liQW96WnvHmId30xsv5VALAq6 HX81l/r0r7oGWVgPWB2K6p9aunbOAqi26Sj8v2xLgFWOAiR5zQPge1lTdnAsXjD8KbikDuT6M7bu yXGwOXSpgHNvxqtMO5RTzrnAXLWZ6Z5Qkkvy9wbTbwnVJ0NCEV24Et0aIySrQRxOeyHHv9DyWbTi wMPPCxzKDLMoYeOYoD3ZGCfioZMa1XrsjpHclENcA6Q8eQrwZoYSDGNfttE3tSrwVdJEoVEMuUdL nCxRVvMs2uFIDFd1ORTigWSdVkkHQAVHgutnAeI6SyWgEAEmijcUgEmHhftAPA9cEoG7JcOAHKM/ reCUxg2zKYfcARZQytvoUNUWZfENHw/+RJSWbCCQcnRzXQIKvpQgDuEPfM3logiGgyKJkxdVF8Yv 0ThF9wx4yhE0bginIOzyGWLLyNHP+KNvwA43pKo907b7LhpbaoUZ4lYHIIvc5LiQBglUuCAwZRS5 N6u5ixZPrrrTa16teiilOW9h6iezTU2aIXfwAfJfAI7eFaGVfn02F/1XvuitFJKKeTXBmQRrgdk8 UFdJsmPOriDypCpg45/DYYSYRI3sACb8agNy1UxEgJRWVv3qnYxNitIMxlx+vB72b42q8V/9KM80 OjB0J2rMNorUaH8Mchw4LM7aEL3gOSH62AwzWKEH9Ey0lnhAep0znBrkUQ4Hfff6bDosC/FriAN1 cKHw+Cre8NhI1FB/qV7IPrqTUKf/CGU/HwomPpl9tnbYXQ9c5OM9m7sWp091XHDVab1EIVPZnIYg LayxKZJUputV0hg4w5pMAJBvO/3nM8ZwCPZ1c3zIpP92XDNHW4+k4dzSYbEkLA/uCzXsv9J3EezJ kNgb+jEaCunzyeZHD5usjBojzPNzcgB+mgoxRvSU0N2q6XVLHTCBwkixfZyShRBy3pQPnI1jWHHD 47Cs0lqz1Tyjg27NhWt+UK58sV6uRKIAaaVEXzcOJfoANbO5AOId9Bap2OPiO9oWVzYp1VWUm87O zYLDjsYRd0KyWEoYH58HByOoTaomr+s9pEr+Bu091nU+7Vor7sAVYEr7iJxjFdQtqLoWTYUSTLre wgt8SbA21DPtcGwHCPX95p6gi/w2YztmdHrXzHV+f5ipVmUQePtsJkXAEhB0e9AP4u4qRKSkj6sg UByR6+8wXRsRiqr7KlbKLdHhg0hECvX/sscj2fyMEYOKVpDyvYkTQpbphhOGKhx3DJZdGEhgKVAu gsazFt1yBGWCbDGAhR/eCNAB0hKfOeVYONXUjkigFK5QAUMf2Ejgc39ZS1S9wUq8xvKvM7wkYR0/ SnGIkJG8T34O7I26s9nr3JEA6I4jbapVqBg8l/snfqLyxl/KE70nXuV8tINb2bJEzHMJV6gum8qf okJpaqJp3mwehJUucdF/bF+FYs5CnypQdjXcEDjnheKyhhIrof8eKHriWcVLmm8gS+mu5cqKY+tu D5TrS8p9SNaWwIVmF37u0vvTSAGqST9tOcBnSaS+0EuYg8bF3RA/2GuyoOmdWlfXwawuXZYbaAdW H2b5v1JO5+fBtltLg8rkMc2/3H9P3YfRD0xK+MaVH/KwisAZWDW7eHsi7Raaok3WxE7la2KbIsfL j28KVIkL86N0DXGiky2onUwNBnMPXBHucy5ECk3eQnAPrYL6rq4E8gKzIwmwpt3ZkE7Ezogj1r4Z DvMrW1bvilPnMahhInUDV3/gSkCoyaa/Zo5pW3uMRQBiklLfjyJtR7vZdb7knmnSNnJTqhKlh/LR CG7XWtroFXwRNVBPrAOYU4TFydvVxAuoeZWrDy8W5iNcoD8CvQj8LXQLAzp9HAtcz1r4HskGYefY zQvHLvUETG9/xroPfBnWLYT6fShOYiaJ0SKxFv7eeEwujvLlW8txCz2eAvXx4pEpiShRTHD9yjJJ p38AjCj+6sScrrUo3QWI71CotTtj6a1nwEtR26keWfcF4LdSptDwh0vlg+PcTez24EuNANmdcSsP 6lzfs2USTW1a301YCYWIYUEet/zjIstGax/puam001VFwR8MsI5gC43JgM36wmp7SK/JdEswqIeo P4tjFgYAQaBk8bu5BYCeZd3AreT+9g0T0yE9yEVE75hpckbPZ+ONQSfV1a+XnLRREJP+AIPTSRoA 66Tg+1UGYJsJ8kYQSt/m8B3iicdU2IQxNLaDkD/F7tsBTPJuw6KIT2avEND407I4Vl5jHN558vGX Ba6VGnnChRCwTvWVk9yCk6Xq7/jKj9jSAP0ZEgKIXW0Oq5hfmNvWGiMJhyUIi0ru7jRjhFZtHUim AmB41uYyyFCHYURog2tnVt/acRY0CIGPfRFtqk6ICnmP9yK5FEZ29dge75wnUvF0DvLWzQGpyGMR KDq0PUqw+1sS52bdp2aZz6r+anHLV126oBzO/fxMBDoaFpmvuPbGDzbZH/1jjSMLaMafzebV7rqq ht+ssja6ssIcbS/lg+6ZlNtOCwYyahYwMYaJv8HMOTIjbTG3OoY4dnMrHN5Yq9wzgHl9fkBq8pnx w9bwlY/Dsbsv54HrZQIEivpw5VPfFvp/8JdlNr3GGHa+LKJ6m+djq60ZJo4ch3BvjBo56gn0tG81 AE/eqR6Gl5jB/0aB3a97Sx1b1luouXj4auEnrf4OBbna/wdN3DarorO1qKk8hUBbBxqEgtLPr6Ax +2ud5DpzJCpK4rvYh6PQucSug3I2HhRCsonwYVeRtmedHxLPak6v7d4uM+u24j/s6jA7JiPrzRJI GU/eU4vHDd4FtkNVR2vpiSwzCImzUaxaLE0gJ/mXHJLU8sXg/w0PeBH+ti5xAK60ulEX06DMEDx3 5lO/6OLPHKXU5zAOvoL0TDNpwS6ftia+t/gb42GimCPLi3rpmTzKdlKbJrZWTJNSYyivtnTv0dF0 mZ1KZByOPPfhFSkvtqn+QeykjSAW5w1FzqQ43OYzN3BBBgKykPge+PfGMUBlaRiAae07l4peBwM6 XJQz87FUAMgIncn/DFT0QZB8qVC3cjhx1VQVA1CtSkFvmlq06pDOLOMykvOwvoqbfS1R5l30QBTc oVAg+UXMPj1l4EFfqHs/KCzO4VJxEw/B1qTE8ZdEswwXheC12vr8kybmHT3Xfy1cigZf5QBAaTlF 4V6XXq0Mo8uutDPMOIsiVmJrK3FIYR2B1mn7pxcXw/4faz3sO31GKkapZTTDYIAsOSFrFNlSjM3U MJYBxDYv0ddzr2N8TznnK7aZTpHKeiB6Jc+yuEmXib591c5D3CCs7JZR1Plnfg76Jrp5KCpDiRsZ dcU/rQCS4XjLNg9wKs57zX6ynqGQKv4CuIV98vsURIdfA24Dl9WU6wz8Gbkf/yOoATaOHzZ+c8SQ Hpakpr+brKqskgHdAtzgnWEC+QXB8PkmbMj0Qkq7aSnOGHKBC3Z7/sBv3GbbC+OxvNarB7D3/8jY 6Wufmignyi2AuSTy8BPA9wYm56YWEbLbRid6uXWEMcNLpZVaU3vP/An9e8YpTXk3UIKQL8OvqRaa 2pk5esW+DURrDlm9d0V9i36hXaQmtCQIuq9gOPCNXzNV0YdOc8eiOLH24NXE9n14jFF3DWqBcQXj NgZfmDWcJJe3r4mHFOuyqHQ2JztisI6jxp4VkFd4NFhuDp9hxt22X5aLedUhKdhGwwpljz9r+/J7 S04f4dY1sJaa1pp2WEFVjS1gTRqedW6U0lJXRqicbmyv2B2FMZ1biDB1JDJJ1gCqC9Z2rJZ5sYpO IbcgTaQi2p7JHQvptCd1uTcaMf0c0wB36GQ+G6rx/kJOCvkazRIDrdIPy0Lh7S1Qq6t2mcrpIbHn zOLa/2/VEpcEy0Mwlu3IHtiVZ0guorhNlk/yGqOd3EiktIVNPGvaEQv4twOdq9eaGVevLMI9FgJl dq8vi9VEbxdQvsInrtv3N56z5Zqn8/Z4sZs6nN/G8AwTkv5pzu/a2SAP9ysNe7WxHqsykzVNHPP1 s/UA/EbKhhHxdb3kjSvrWQWBeU7xuXQyB9hdr0ScIbDSRwsZ9oONmGiz5PI3QRCN8GHsdMkV2C1W OoIaTuHKLCdBWOzydXHp0WREuy0VZsLD/v7K6Ur897DcFN/bYZxTDfMQOo/E8IGCzkK2FOuwnGYu RpPS5+g4+3bmDwdq1YnOMWzgXhw66s8VbjZ4e2/BeagI3yuZmniO5KWToc3Nfk36iHJm4N659dRN PllAChWUcti69YtY4S1ljKUi3qA4wqvgYHwRqDXAku0ITcKRDGgwDm8NQM65oNSF9mO6TUlQSmPH 4DlQBW78FHNkYS9tWbyMzY/BTn0csVWB36jmnvVn9fQYCHSM1yK8WGT2jGuL2YP6xXDodUVWZLG6 WKrdfjNpWnPmD2X/MxNV/gfmC8Fc9MQqWTe4PgFFzrtGgQHeuqBbxHcyM50ab1rKMgGrPq9DWSFp 1H/tKoObIqsh/0jBq1uuZyCwQ7CdZgp0aD9WETO43mV7fpm0iexMJelKk2lHjEobKErFPPNslZQm WY1NsBbcxCGt9th+ksIG3aQbFZtPQ+vYVb+73zSyXJqjh1DrQLbYrk+hPSRFRYSdE+PfOPb0emWO rsm4qxLGb8Q3hbp/V7B2tDQrqozEgcxcsyUOEzexTSNICH0k/vyvC/OmB6XcBzmGpCvrIm+D0hfC vUk/PIJmzdpuii2QmxphVsydblDk8aYzErbfvBJFcz8j/YlCY6TkQwd3fdbh148MZ8Hdx+2cOQ8e AVPRqz/RWwP5qSfdVF7jTsIAPkv34siO1bQlYlqrV2jBzXCl+3EXTqK2kOMvYffGA1Dt1gAwAkiq y/5Gtujjk+JR+O+Mm/b2/CAdZ4J8DvGhIjmZcok+a+8y10MISeT4dy/sn/DBIQLbWGOhPlHgcAeg qlDuQdsXh/3Av2mYtsjgorKdQv5mHnbcELA9Gfdw84iGAmaLczHpRdXLiT4dqNlAhOOBHIjuaFVG uyxf5ZsGXVkpJGxzzAxCJL+c1y0EMfBsNrqed9DfVLXHf/5NjuZ3e4csUftYxkwI63eV4RR/o+Pw R32Ilb9mmoBnHD78RU5q/NmreWXHJ0lG4Fn+HVqPahs76pI+yQL0y4ZT+ziybhVrCwfNe0lIzCcA EECfLy3x5rhqlGZ2SeDead1JF27MNyEKfloEgKKeBaTJuQqckNY41wELKe3lOBKlC5AQdyidRMp9 MVbO4z5IUqmIhI7Wa+uYuXZbEPbHmhhq/eJM+admeer3KNPNAmV5G1x9eKtheJJ/jQznyk9NJTjk b4ZWoIQrwQK0TNHTAXn2BKazmjDfxwoV+3HORu8QUXLPxtNXjrtBzvq/ByR8eeEzVULvjYRNaVHI oUEi6cJDEpKByAr//FixSvUbiIbP1K3mmFkLPnqwdNugAFOlKzQZCD9n3xeu/ABOGTU6WMEdn5d9 x5pC8G7VmNs9OgCrkuP4fccbEnWqyqaI4M3yrlyeNdDhdDEbYY20cKZWcOdmAd6/lQGGygCZ7Rdl vZFqpHwjYffZbUA4SyTkGHXNDAG3EgV/Mk5mK8iATik0w6Kd9qaRFdMZrJCHi+FwH0IObRmW2/4k ufAmB21gYIYFtsQEFv1N8Ne/kQ6btf/0mEyq0bZcgMY8rNNf0wpR8MFHtUbnaCv8H1u/2rngxEzp nDmBBXfQRIOVBW6lH5PeTwLgcNDXYhkXhiwMMa51IJTohRvP67CDGEV3ndMD2IVH7jgMXitpqI7t NEAy4H4mV9clTRi5TBVGJ3+dqVUGTp24eTbv/7wQUX3UDpfQe1g3CXR6xVHnh8pNjuNQRe3BS5Ub Y4IAZmzIxnSIa0UG8DowNXTDG3sz52P86zeeiux3PybO5DYOPQ3TiT091Nn2B2kbHcmbPdaAbjUx 7ht/67fScAqeX9mC04SSSkDhmK615LtuPrM0i1sIk1B0ENuZdF0EGcvavuwBcafCI9tx8JPC8kgU 2/CEagQJlpUeb/CFMsk52cwkqvyjLu6306xWM2c7Szt3Tg1oxo4ZXUWXMUFXPhTvysIV6mE1FfU4 iBfMI/iyGPxUtGPqGUIa4gNczv2y4eExQ0sZt09L0z+V5MG3oXH0Ynxo5JjlZ7Cat7829LmNLuJk Dhcjy3GpyZsdyilHgRv/HeOIv9PBu+C+vOZ9FQzJXX4EwRiSkkgSJ/d2ql1UQCeEm/0OTUygM4Z3 qCSAWvx8/qirF9vndAg11jgeuUzRaOLQ4mV0YBZnO27evyhtXTUskncqYIUDXktDQgS7QbPMYY5G U4JCjvKeSFKIcX8VLjMTv7s9SKdkTUEKPXCl06I6g40u5kJVX825MuMwIEd4jn9CSOmpRjH4/wzT fVfkeb6C1wj0SP1kXYx9U2meJtl0Ga0o/ohO992piqeAlGn/odI/HVgY4Aqc3z03Hb2L02hDLBqT UUAKSEWtwDQ591iOSe9JmblP/GBWhxoeW7DkM5t92OEtFqSro7sTFvzoPYn1UXDaeVSD+ibeLeUz Oozk/Hcqlj64+YmTyaFcSeEMpAazx6nKMdwS9hgLA8alMzNYcJ1PAfKzGE0zge2y3nVtJSFBhikZ slj2jBlLE1xiaMzZhcmrD5seCn8yD7SD8dJ0Xa+7StchQhGrIk0uV29mNSzX224P1saqe2OsEH9J 1PGpZjeEwEzx6mmhh6AIsuuVr7yozkQ6nY9k+yre2rf4Km5O2CxJ8+TXVQXBGbiiUSJJY6n7kmfe F14oi6QP5JjiCsQscJHag8QDvj0aMt/BJaTsVH/56eK1iRy7/6xUInKQgXLbxevSEooqKVvS3FJg AZG73P5QfLlmAiAappkRHwPp/6H57S7VcptEnDxGyRWwR3kO4WZAWH5p3VXHMaRsRmNhgo/yBqOj K2RzwPbMuwdZM9lWJlfEzQA33I92pTeDnY3BV1tR/2kBYuAouMz+V287W4UisYxH5BpPaX91+5jn IlbpNRr4CV0IyoKkOUDXXPchOQKJhE3SZeSorIErU5Y6d8MFo/MKUom46kzi8qGkvBaoL/Pw+1f5 upTRoIXIUMgeM09ftfoTB44YhQBUZYC+YRPdcyPZ8CgmLeqPJh1WG87tHUzaoLtlVbWxbEhkcn0h JIVhL1TlMSKzNFXqTxRgHY/Xy4fXSeu+W6qMJ2hA1V16abxtDh9VnwSr1lB7l3EmLm8R9ciT3pJ1 XI2xztr2y6S50AUKWveN0sILU2vgHRwEYILX3TcrpqdOhzVrJeiVqMDTOt0BdlKDO/n7ykvwxMel /O7EquqtEGGet0d5Tpb8kkV580iIcsEY8biTt+HSqskqi/oAc+BR9LEl3QnSN2dix1O9FxbAIEQb VxckR5sQ6SoHr4hV+0bPN7JzlNObK40UaCe2XcLQGxrXr2OcPaUoE41Cw+WtrPuGb1vJMFPVQgnp zDOz+NigBzuQpAAxXkniKIa+wvevHumV77ojtcgIYTD6lwgDnwg7ZBU7EIEwZ/BAVCtTw9Ezxp5s PRNJzF19xG+NTo5fajbpUsss0o8guwNdcdIn5YRVAP3vC5vOk/igafkvxSclOzkrBZEBFek2qRi9 hRciOeOWHwlscIjU/z2XxKSevhaGpz8c5Dyq7vbF7vk6ieNFLBf3NO0qEYhKtZC04mvMPGKFy5lz 9lQ2ncV9V3xjgaR21DjUHdKJ05Y+NAStndQSZNl7GyjvhyV8d7xNjddUH+i2d0fsHIPmc94qRC2v EEnjfCupfkkIGOUgbresnjgBNUg62zN6XsGLcqs4BXE81WocjELGmtYrUW2KJrdhb4uZtxwXgliR 6+9orU+tYGosBsQnlRiZRcOnBHjwIZspn03ZQBaeKkt6B58AoKLdD/RymkXm5pAfjGjOAMWwCCRc R/gimJRQuFyIoA8boUz3puZc1e4zneFI6TlTPW7HlmaMMfeyS9B0qsT/EfYvqmuUqUqW7syKasgV O4Wnbo/gwz03H0ed8uzX40VYwbWNN1NBVck6t3RYtOviYVc0DsjOd9i1iiepy05acJlcud2Q9Lvo G7M7/FSF/fiWWlaV3fqVin6z6Qkgii+2s2l81dV25s5sP+KBt5gDSmNjK8r2lTLU1U4GliaWqZO8 WiVaYE/ebhT7ePnBwUWgHjDi7UTzz5RfgIockZHQPUgXakTotkyxL6atZU2ccQQXP6/PAoB5Pwgx utK0Wtep2joewUR2QVLshHQtXunjB7paCKJlV5XUlJfWrXGXogF5GhQmf1ITdgMIRNSSztGbL4H1 +U9fQDt7vzsoOC9hoiDMeGI/Tw/zGCNGZ+SLa5v32ERw4GHRUo8dwzlDie/jZURJt2BeCHmE6gEy 3hm9rHrSIiBX7+go2fkkm6J2ky+TGDAeGZBmlrVbGq5LYrs4txdsu6ue3EMWiI9ZbMiSSzsjUjvg fdT9SdS8RLOo4rPWDMFwSRjzua41ej1WcT6T8OKlHqWV20kk718K72SzXjDiHzXmodlTYsSlYvmm Ph2a0yyDGgIVWnq1zyNoXj7u8PZss4lv7tXX/FbrKIVcsK44OKMI8hzudzDadIJCAkt9sg8oGOkV kFoezd9I93V5ugdxzEsb0dWc6jHnzk/iXjTluN8TnrX8eDI8VtkeFWLcgRY5uottKYZOhpyR1Ac1 k9AScWphocnBGEKq/jakrW9qKWonIM3CwUUVLAmJbIxd4nHEe7V0o7bUrKrIQf/Tiu9vcdBKj1u2 JRFDexlg+WPyMvhrv+r4o74a87z+7kWttNe0g3ZiMwzMKsPRnkCuChQyDdStOqmo3IX+2oKBxmT7 eC9fCL6LiOTKSNsGUAHd5CbPqY6WSbIN8rH5TuQ6p5CH79vlyG0pgLmtfRT2pigRZeUMGBYL4Jbr kk/ImoUfcfkbcV6ofThbCzPCVRLR4OwOytS3SuqkP/1uPidjcMvkdNX7RZUqVZ7lPCLJILRljrZd nb9ueRA8WgwZsZtweAGMOOHeGS0gBJAcm28TUlRoU8iMfeEx6h1H1tE3eHG1oexPuU0bideCymIj K68edTvmKfUN/cTVnNHk7sQxYTcmKM7/DJGvFEo8ChcS7gPXhFWy623IttlZGCm3dkPGI48xtTGp LU9TldD/Fxm4Hi5YCAuiZMMXfWj4AakCPgcSHj7CMANmuWYQ590ITCLd0ZlrVsFjlhLXzNpLSXUz Rqc/9gvhCAQVk9I9V8388jQT/aH/Uz15JkLnVDzY3Uo3LpSJ87DJpWtrFXTf+OURZqnsYYh63TIx aXryafEOIe9wwdxUfTIsf3MkO1Y/zUgrGxmOryfTUHr8697MhrD/Ba+mpNxnVHP3p6UmIXMwEOXE JpOZ8yy5VK2tfUFbnOvFHhOj7QB1wsO/102qCGo9Oq7fGJoTu4F636hdMbfgwH40WC+2kxq8p95c IRXXavBSn8ellnOpiX1bAuLFY+5jUHRFzey/L0HJVBMwkqMExzBP3W1rYMFJw0slkwcotEWwegx2 gwI3KlPj6oIey+bhuKi5YKKKfIB/5YA4D4xTXB3wih2NIDx8kt8qgUB4vnKZ7hfwQsR4eKbpA3dr fWxB887RAG+5Ml/G6ESNw7Uib8f7na3fNkHIhxKwxN/mnIM19qQBwZ0oeXELAT0ZOsZjwPpf1fEi WAUir63FX6F1OtGL6sZYNqxA3MJTvQcmYsE1j/W2GWZ6ds6K20sqTTXG7ZQFkucIPL/kpgDVr6Mp KILe6UEm/ssy7g8Vk0QyiIgq3nQR59n2J3DLh9/GQfRGv0TGBPHCbklfGZb47LlXOdNKVH0HFmMN MPpTAjcTY16tQK/zEyfIvNNoWZc317WwD2gAucHI48//6emfqL8mHp6e35x8ZTDsMFalwGxGi3RD mppJkzp5V7XbJbBb2z36MT/NWG2avDcWyoWeSAaHzmFND5cwGL6wviCcIZkFNF9XPN2B2chMAjJd is/Uvz2W10aWnn5OUj4r43aHd/k7ur2Li316ssz7S48f0MxfXv3qYBG2fVRW4g7UTJpRPh26XEkn 9aNhwVggNhtxvsqsPRATU9aPQ6YyC8GF7kDSpGcpIPe3o21e/MyvC92TG2hwJeAsdn6Ley5abWVG wTLz25sNU9ANKEbA4cNk2tH1b561P7h1pFuXTpdUk58OtQWj8j1WpSB+XRG13jydr0r5sQXzF3t/ dJlAUxevcDEq+mKhlMycJcspHwgUMZOkomBsiEHiFiZf101HMEYAmeJUbCNWgrHbmgJmcI8Yd01b Z/e2J6/ME1PotXdNLf95aGGKAfyt/mSwW0/f6SnjteAZdb6RLg4KD1bwlaRze0LJp+0yd9zl9LHm PmoWJDArzBop9xOJOoxNY75u4tvc5brCmeveZNG3L3pUNj5mkUxcHR2LZoMkol+I2fO87Y1bW8by dwcz7DR60QyxonqjKypjLOMiWEKsIYu7JWzBIoIB2yUDFcLr/Sd8uuNMyPTaXeBBfS1/OxsnsuKu yRegqqALg+xWtqgt4lef4pR7xCpCAAKxvK2+SvHy/5ht5RzaADFKq4rmC3H5iKFu+h03NX/xPDTv plhuLyacnR8jPE/tpLmKYW4QDrSBfSNpH4D30mimZPjHlF45H00EBimu4jY7cdWStop+btkdX2WE 25cUu6sbke0Nk7WOg32bTZy1hepHKXqHQ21a7xidOry7NAUP6uNpQClvR4fJYW2Z5FvgWycQ0crO HrNJuB+LJlZul63ygV3MR3VhSAJ+ORfzC+V0FtTOmeiB5nFSNR4RS+DKhxronGbhFCxG9wY+HSvm ACYvVO7ghZl09xy8lHC4aSovkva96oOmw6MK5gdHKnWzS+U8NNE4AdNcZd6AhV8095VD68cjhl6D D7/WOfe+TWFLlmXrBv0KdzcwS/rSAGIOzCU1UQ7e5D5g5ThdXENuA2rXMEN0EZOMQK5e9R0arnSQ zaK0OktqpU8Gl/ki/+mTkYh9vUUT3H6LKf0WO0yFVFZ8NK/Qxv+k6ng9uxo2cNdmm+Vvm+/uDgSy l66aZ1qwZ9kP+EMfXCCaMvmboX8iDLPNgFgvPaFNNx4XH3DoMNcK6ij4fupVH9nQJVVJLrcsZngZ tNHzyCiFUfhrggiUOVINJHNVmufODCSlja4Gz3o1K7klPjhcgD1GUWs5pLd3pKg0PxNXGOoGw/Ur 5ph6Wp0n4QUfV8nP8tfeiAZ1+JFb4Dy5DVdMsxiqJeBjJzsocjYyuqeX6sXDSJNzvPOYFbT+iOYg 8JwSk6x+03aY2emJEQSoVR2NF2srEc13yjH23CgykRXhTeppKZIfASisrQKdPTXDxaG3wSEzHwRM S9KBe9OCA5otcnhn9NyVhgySw+1+sAIZl0eDUHk7nLxS3jP6giq+IeF5NUH9BDTYzaqj1XFmqspQ C9iqpzxXaUT6Grwi64fcFCZ8Qzbe1H07fOiZCHNx9JliveuduNLa4FrMsBl3XAp4sdfUeQ+CQiAU QIrWHqXT4VcJ6qBbWQB75qosAx+yUQFCE9jidgXXT4w7ff5bIK0Ywj/9w8Fbgff6l5kDIecXIMfc CwC5/YsHAPlqjC/0Wn3CEce4wPVKNMlJGSw+r3/SfTN+pa1GLvATobO1vxJijPiQ+Ngufej2auZI vvMxytG0IVrmPFjutfvRSc73hiU/Npg5r0VhHzMxddTZS2hmEpH2K56XHKjfZs4bnMvM9cHy7PnX 0Bn77gNSwcpcwLDmg2iQ4+Wbv+ILRDteqPD1FlLudtYERYA0Y0V2HCdzAHuOTjSDnIbww/klUudt d5oqkhxq9rQAu4coFkMv7xxXNfiexYSmHTQ2RdQxTuSm+hsQFxzBJnpKWWIcouKrbYQCNszWUr3p CxUDac1odxZqt9qNVnbxrMVgcnAsOMIIeDqBLq5OFZ/h0rPN3uPmim6Cztcv9XSUALZ2676sN4El 0tbA/kQCPNJrDHWqKajjX36hkjNdpriRi7ARKADAZE2TO33DxJ4lJEeYY2xCJ+uq+xmEQjJ9V1/W uxoH4ixOJEzsZZRzaJ8ykiTE9TSqpn9g9KUwHmd4kSmx57jr5uu0CMzJCSNb9FzTrgavRIHk0S6y 9Tm7F/4PKGCKcgkZLTj1Ckes1FbqRgRvmIB/kc/kXSBOJ+qZP0cJFl62L1H4mJbi1GQQ6Y4sp0H1 X5HB/AD+8MM9O7QeMceqJeKy/G3ojIO11FtgTlD3Y1Y7mJa/h866fgEO1R38oK9CNKrpY+474V7h FtY3Y9pfLH6fwDLcp4uAbgIhhE1f4s3YHkzweoj/KMag0eBtS/7FTDKbIFdYkm1YAbI4121Dirus mTuIFC6oWhjXJq7G0OkepXRbUnaPFp8Am/lqNoVdg8t4pyl6gswcUYSMUQ9cT5doDhsMaqH2juQQ 1Wxxy/AYWR4kiBeoOyJy5GXfZn7t+EE9hS5LSLhc8CvbXCzcfAv4MLqUeJluhN4HNbawaawOOOoP Iz3ZQ3YNH5mlGthfogLJHsPRLPFi/egmYCdasQVwAfi3XZ/s1vIi6TrldM7XBzJ+tzHNQQVKk8C3 bJNUdzeuAa3ws+5KbuLT4vMeHzDrDdMZP0eQSLUueVj50Xa+dEylTkyBH/I1siX7/KLe8Wdhr4AD C56daoLgTOqw2bxjOx2WzbnQmlgI/ud/TWat5q1cGmDlgcIz51qP26e1OsHOA5GzREjh52wah9vN T4TS9WmEWsmSjmjnTa/J7eyOB2CqdEXPTatPjP6XrY+cVyVulBZwO0tnSOBmnq47dR0nmuLcJR2v BfXP8+kBg27wHgR0LNGUi+KQkeHfK3ni+LsSLBNhuHAr5xUarzCOB6fqdJYHupf3i1SzA92Rc6/g vUTGMnZOTOGIldfTjDxVExE/7PLiIWi+hQCSydwjxMNdnlUhAXkCkaCdOf+k5eD0ssZGa7HySN6h zysitU7Zp1wFx5PvxFnTy8JRFZoY5VDjdxYsMv+vIa9TKVhIUMwTFKxousZrd3guRXh4Fmxss6mB BCaQEMfUV+Nt/c/GjXJmnc1Dm+ZMWhI0ATArQzGf1Lstgmd9fOQacI8NjUQeCPAyIauYTCpRlkVL S+KF/JEoKSArkbdOpz8AF69QhE9zpBzHk5w39+PLokoSn3J3/t+9mdZd4UcwxBzJ1pYnXuhSKR97 IMV5Qg8DE2l51Cd7weWcTcGfQZiRwgu7o9vOku01GFyBLIg9yJc21xm17Hpra7sjUzZkZ3pkofaL P5U3+Bu5cE3IPmVLkweLPXdbjIDHyyaqGxgX+7erWYiZXeBBRmskQNePjwSmVV6XCCx8JnbH5te+ chxVon3j/dFfUskdPwBneMU//oQCrNOO78pPauKGKm4rwiC5zecDhtJm02XRZzKPfAh/BM5Pk5gI UKWx4Iku/8pxWXSD/t0vfQYXmcwnjQkzSriD/CouWN9x2qq15dekQMBiBUKRlZzyodzO6Zs1zJS/ TG7xvqkYyAUhopd2K7YCj+PGoPQxdx+gyBE8LGdb9U8Pc3cQm0X6yXkeypYyse3SVqQ36cahoumP ga/1/3/hr55c794xDPDMIfVPzTUe45vArXubEtgGjFZcnUV3CboZHeXwG1Eb6n2QkGu+Yt33EyLA OVeFFLuk1MnHzhLWWBGrxutkknYgvptJ3xd8OA5ofsX6/QrrXQc+3oop4B2uWr5g3IP3eBt8f61n 9s4yYNmpjlWEfOjcLv6zlcAcRtMn9OqTxBYjyQTA+oaoHpUF8KTvX8DzLe42la0qHP2AgOPbmvYn Nhv82pGG1FOl0ozSrAmhwjOBsZ5iLfjCgHvlneSaM5PCqhohcbP9/bs6yI0wQXPHM6NPSVNLQwYY vIAL9g/zTuMDR0OBrmL5FBpwAxnQc9ZN0ZZRlOfeaVUNzRewS84Y3epfUJ/qiC8SivxAKCDL4knA y5yrVsxmZlIA1hqL5BpZooMTwT3LwZasxyrXbPzimj0n7uo9hkiLwiYf2txVplYhT2T3ZjAYjsQw 1AisXgoxro/DNNPuzdZFPH7NzdYlcSznmZOEk5oMbzOKW+8zAU7s/D2rzaPkMyNKWN/C1qNkOw0D V3FpQpJJOIGmYm/Aa/bVM1crJuQ950UNbLsfNS7hsRTDuBTOr/dmKYkPOaTn9cC1LW1P5xsFMQoE w+MfVeIbYd93nqKLKoJsAJ7NgaZH8JW8Dl4Qn67vkWHOTLlUfy2TryZ+udFSoZE5kXHz7P5ra2UB AW5MyqhsKjzMf5buKZpxsWV3rrOiE4d99ZfG/5/mPMgw7T8NLsIZooLJdeDhPCCw8jsQOrhySRW4 8Uii2hhsZv1tekZhbb2hSlISukecgM2jLa3RhWsMnn/nwjhaB0sl8aF6ELx6l3GyccduMPrI01It li5szRWMeX89CPBI/TabkXhFETyQrFRhG56eDwIfuH5wvfK5rHwEi/DN/K+WQ0qFfLyk/H/xWIzx EcMmj+Ui53QbQfWqHU5xJ2nxG4RS1hUWnQPb33ALT/iIQkZmrwl18NeSj6YKhY/WLTM48lmp8YfH a1gvzGXfgAEreUhccxue3RGKItAEvdAFUpyRnzaSYR4p9BBbjqP57rji/Is29qw2t+ZKjCq7NLcA es1tjwV5Wen2fyY9WVN+0mgQwshRzq3nkC3BXpNemRCItnlbpZod2/SLI2vWC5KHiVhHGymRCbaG vnjAY+BSXSsvL4lWkH2NGwNgL3hpoYvkNYyHqURpi1bPa4nBRFzapKGPiwvyF0rTg57K1H2ug5nk ITCOAkZhx8i2JDZwXmZjWU3+yAMkwBVnGk8jjLA9j5TzUqQCE18E9rcuBetD1YqCkPq30DCcg5p2 gpDjNYyMwNjicSXyiq24lULvoxD/18SVVMbv1HA3yiaycj2q2TQMtCT1Z9g6e6uCYEadg74MLDSZ OFKgpakqeR/IjBI65shjNQM45WF+Gr0zbWSM114dE3uHe/psZ9eS6NXrDZr7jYT8lMhmkksrW6bC XIjtdV/yRwqtFzWZoVInnt3AfNOZKV4uCkU2ixXaerxwCZVUhoocrgh/rbMFqnNn1IWDzFy6Llvv l4UubTG4HaRBmjzPnaoTnQImwHpoZUqywjeCMjQTYPKvr9JWDahVzw/0X4tDlbj1329+LU9F8SXH UR7milsHV1YrUmCkvrqyyHiajwPc7FN4uHKjfWJV9oqRwC/BJ5t+cGNFUSxg95Vx0Ks926x1tXjO xabK19UY/XUMMEwGktuUd+Y2PMkiZZF87ihMXD1ZlihI3kfexbpOLrRQcsUIuljfNWfX35TxxsDT td2AT7MGEhWl2Vv5oBW8vQ0N4oai6jaxjmUr4ulEQKn9SmX7MH7nUC3JCFeSJXVwXcKV5T22lMW/ aXU0MqPI1TjfmM318OPL7zJ56XvNaBTSBpvtMbHqX9Zu27IdLPi4iTO8zIp3pPrpsgvu5nLBxaEX KvE+1KWGh2xgHdj9tcPyAQhkwPT/+cV65O69vM0qPE7xuGeGPUABrlmRNBXER3zOQU+lJBmqggqj cC8Gxq/LCYyqWGlIQJON2ZGAceS9Ryma1rI1WWa8KtOs6WA1xSGV5CZ2QmQf3I857rmhAu1eGDGy VzJa+2yhU4Lzv4xG7jDtBHPLcw9W0YkYHbBR8GX34GiV52NhIz0RjkOdFEX4b6KrlVcf8JAM45Y5 DfzGt9ax7/ww4y0e0xKmX9uTr1XNCz41kQf9Via76tv/lvSr74fFJCBofKu/3ad4nl0kqGTfzC1b H00ckULKKqbJQi7GL3GGJny6+gZVa2kkEmIo+VeMjTUlRANf42QHYXbYgPo9BUyChdMR1lA79UM6 HHzS1r//0Z4OPkzflqd6GjHM27X2NPMyz815zGAh7wf6x1FSlK6nqp4TRTkoRr4y3LCvvEZ9+ksX 6uABgkM7QhPUgAqdjEfnxTUadUMMMD+C29wHo4QT+gfnhpqP3WOGALTf4h+q6jnG3UU5Hnd9AyQN 4y8Tjw0hQfaKSK1bO5gw+6K/U6afcvC2EGh4H7BxZFT/CGuqCESU64JfenX+Qiu6WJYQatjGN0f8 GUgLKIT1Z6Sz32bBCqQX+rgYZi9qqKI5G/9x0L2AZrUsyIK0JsOL4GPtV8kvvxYokUgslAVWzYKS aT6GYSv/wNEWZdmIOdXIbGbNn2Y69tN/DdwxqEtX1Vu+cMssqAt6pF1pBbVZWwkcHr9OvVgGc+Sa 5FDxaeb6lD11cjXlqwqJ440m5m+uzeZxaOGpxfphdl+Nhn0ey6/WjSfO3VZHbHTygg/TcUspO+jV Ds8v2mGmCKOQvtgOG7KYC76FkahyXWb2512pj9Dk0eZtLzM1EfmOTJX+H1XJORRTUu0I20Rmyxh2 3nKVPs/WUVQZMankIvgauFQ8dYLAeS6ZNxxstGuBbPW57hoRVgeQrhviBzE3j+OKtAcYPmI8Cusk p5MAM79R6sPw5+EumAy6lJjprEQ5UaozUiatQqqc54PWEplr9dBjFQqdrNQsQvYq/C2yh0lAqZaD Y1+TkbLyi5Ruci29ccok/OTUhUL+99QtqV7j/CaY4CyTKaY6/Kfk4lgsOx0YvhDCODFe/aGt9AsX xM0J5tRjEsXKcXwwjBmoGl78bzeQYkGkpjIIU1antoQmLvc3jxtBtiwu/JmTPAUmhW5gDQJIb1CU T8Dr+SENohaDcicHGTmuz9nfpwcOiufzKE9lPpJXjWS6QowZ7J3kQ3IL7aK0Mh7Gtsa2BnMDJy9a i5DsN1kOEGRlhgKJ7iria/+6U7GPaGFajGfS9rUAhA+T2rCE9rqF2M1l7Fl9LshBq6dmgREwT1vw id7Wl8QvI0gBWzILmUH06gLdMKeCVb8h+IjOZmdhE/KD5IfUSSVDSMsJGu1YTFYZsaZF4ZvrM/vh 2IgkEJ1Fwt4zQtmKLuyiyW36nwnDyjQLfXE+hREmdL5vPGeMtGNzzT8jOr9rS5ZlmUn13NHvmeVT y/KzFCzFbiRVhrPhjsg4cBo04/pSHowbn/ZiVdWoOK40xctcd/xp0bMx8JUYlspwFt2OfWOpnGkn UsjUlFZ/UKqZprfJk9MhQZdzRE0m5d/x4jpZPIPzpjTMEKq6GVpIeSAcRgon4bjejT26a6mEwdgh n+pv5+gCQXKd9Bt+hphYf9RTwfCfE9kcietiHSE13t8NRyXsIqjPNcfXfn+Ytw1q6K81ougJKKPx 5EGwtsyBUnyZAHcenm21KitSKy6jMCiSxtHJ5Bd21jvJ9CS74iufDUQja1Af6r8+ofXiSO5nhJnb CxWOcVIyVJeH0cAk4vzSmF0TL7YglyjdXbuLxTo1ocuYObLRmmioKcM2UGspMIDXpYNLXHYS4Ppf PBkz4dve6iXJ35LjVf5S50FV4MVfgpLTNe52FJjqAKPIi6KCVtFWza4WrZhXzcvPNtSBcTZ/ft0x a1QfekuvBKQjI5hy5TcWPHQ8752StZtpDRrkBnjXok9GJ+DIPgL8FWc25f4kR3bOlqOoVkfGL3nr ny2YIaMLHbN+g893fyQx4GYhYmh2+mTBEdJ3VJpWjdDTBN/T6EcTL9Q2nFxyf455nIc/He6JVJld MUCzeN3vPY18PvgbsmBdVSmqlPLDzrc/z/v0UhjRHJ8b8RwPadgZJC3Ca71HcLJrwJvWrOlvgCbH UeJoNJHF24UEP4aiGawaqpc+d3wDfmjwEKkuBwjhI6/L8QB2dDL5f7n81PU+OZjXdTtl+Q/QOTlZ 1TNTNug6d9BFw5Q9GU9MDTi+sLz+JY1aeEaTp+z9+2nu2zELgITkAUUT5RJOU26nuocU0xfoMH7D hh6M6W4uEbLjzTtXzuHunb0Q6Z8jBgNVgWbkz+R9cws2sTy5ioQ7QgKHiObjz6dTEOB8TIIDoOJh Gr8YcMQi59YW9aaoMLh4jOUyjjbdaV5lfBZV1/NPWzH0qnQyyRW/a1RnHO4AatgXsp5ZgS7uZCdM rENn6VNViba6TYmoZOLDX0Dbz0zKKOvhym5rBgL4nGgPAjz5C4dHBssdA/ViYzs51T6eCI6EE5p9 Ne12e1FPaDxyZ53T4w9kj/JJvKWsBkOqGodlvjrv7xXliBw2ltQXONNSPuJMY9/3um+Q6MpP8ByJ XFYsnP6y4X2m8poKZeAbaqZwp4wjiWd41TNoCbjvW3XudBBtXFfPDQ9YPGaURtPQzhqpryp1eXde Ot7928srmpOaC79/vHL6fsEgNMcDReRU1CDj+FMyktd+gjIAarxCHB/YYurZ0t8i/NIscB+J1r3R 74JDnjXUueTFfPKLIfQc1t3Zmf4Kkmy3vNmf5K2OCh/w2J3/HwvQ7Ed6MIwd2jTlIBlHHFLj3XmQ X7vQO160V5yq/rWNJLBghkjsdosp4jGXocBm4jT1xBdCE8ja+nJQhOefej28S2xJqFFsGsEOecnx YfRg/3SiT0TMjwa+EaXqvRwgZ7KJLUCOG+ak81fNB0/Yp/vyLfuWutALqaru+9zE7IV0Y9JWzn0o 3xnb1XfJFz5kh6qjWYnZOheNGR/SpW6hO2Dy8pNHwpegL96iWg8vpHm3IcQI2jKmtA1E1hkB7Kbc 6tjZ2oxt6VeJtfr5IxYa/8kzvVTd7Fg6dhCNTwlz3eYMsrGB10ndbvdJkcjSNIE2i6gQHZASB2z1 rGdPteO88yd6g0Oil4jsiKIgej/Tj/DvbZWnAITIK3iXVcbXkVzC5EuPXxJkqEs4dK7OC/P50Ldi P5Bffkb1SJPyQMEL+6qOePVEdFTl3FFUdHhdjU6MDWmg7rt4Fjbfscp6m0Ww6iO7mCaJchLUvhuk DEUJuVBseziwmHl17ngSoNIry+DaS/Q5/+JuGQulneJtn5BBXsCglRIkuJ67p5vE8skmM+gD0S7J S78aPLvwM5IOTl3xo7JkZM9+DtbZstEZIW776uFAplp4b3SmoEMtkflVsXt5wjfFm2yQijztTgrF LxBgSWXtAl0KTC1FfFql8I4aeS6s+DdEuccsTi2n1qOwZUCZad9uc0R0Tvo8loTFOBLGP6lmz5Ot /QeMo++Sb2Ze6yYhvRes4Gpu31TuwrGtsXAi20BWSAvCsXf7CDLwlzPyqlJzx/X5NDHRFDK5lzqg tDXzcBWpaC+oiIbd/wPZp9tpUi+RCf9abGwaCH5sbQqgAk7tqHnksj93dMeJDGau+GlAe4vNutJN xp4ZjSWNr9CT2tzspAIBeyMSNk857OodpXm6cmUAADcqFdvOOQ3PPljuzDcV7hxpFU0r7ZdqA7P4 Ht78UTMmLFM7EksjAwITKHtqsMLQQ8XsBjvF+d8ZtU5Vp8j2alVGZNT7SZiUz7esMsB+YklBe2tG FK9yQKuImTGG7bPdPbLLmgFCL0UZJ7YxOYfcKDQdGESscP6cYlWpy16SRa2yc8sVnCkmoZ2+kGH7 meAP8Iwe8c+XaHXqAiPfQf0j+vMBdlx7JTJXRMCy6nc8DnZkWm7Eh5PCxqMG1hp6Ko83n7FMYGW1 v+H9GHKRGuLrml2o6xqsfRMTkezvHxTFWfoHHvJytIjMkLxXLq1Sj1PorMRL1+bK7sHP4ZQwh5Sx 8BASQ7fUxnPz9o/oeA1RuohW0G64dMQzVYNnHLdcy8CyhFHjVHTF5XOnDmdFGfdmoV+a6KctSbNJ Nqf0GwTFIMkO7v73TtxFT7AVO4rdn1iWYbxLD2ekZNkEqa+gtR0SNCm2nj3vsTL/u+RwiJjkezv5 Qc/Iok9QhTN28aKWXl7Q+3i2gpInUrMp0HieJISQ9ogtg0ZJdzHgelcShdAILRdTXseBYGvrqkqY G2u3wvcEXwqu888vWs/nWVY4ykQtFzBy/qpNa3s+QbSVw9eERjtRk9VLbSuXUyGNqzWfpfOlUd8/ pg+czR9NrnmHoYQKAbwjjdWj1cK+RwSRo5wTwfJs1XCwoKao+/t9TQWhxvfxw89PBfzB++sBSoB2 INE+riY8PE62AP2xdGz2gjG8ZFd0VmQD0AcQBkom8KMl76uWgDCUjh/OvMNePXIQl0ykPXpPLRei jKsXNOMoUpCPo98VlZaqKvJ/mzko9AgxvTnzoH+7A9Zu7ouvKCZyLXNQClN/rtWW5o6JQtphdJoK Wq7zCP7K+pBI4YN+Jntg6DkCY4RMcEV2N1X/+3mbslf+pNsH8KLRSzxNOcxLJa9+GyyAjUiaIela +FCryV/onVesX2s1Z8KjqhPhpFZqsmsyZJF2j251JRLOnyqihWSURROQlep1vEYNt0igTZwEEeGe n30+F8p7OonCsW0Dtsx/kYzsIcdph14mXRTqyjNJoeLhixlY6F5hoocfgD1owd97FPuRqoER6fEc KOOU4QMBACBKNlafmSruMxwvHGn9tw6+K1UEwmefYXQ8Kg4TSGwEdfU+5X0GsDJlh7L7JEd8NcGA y6tMhmRYnkVHHYvP2AZhsWFdQMPYF+0OnJDnaOYtNBIg6dVQq47vn0oP9mtUIUyWUa9cgt7SCVRZ UZsdQa0Uq0HMQA0o+SPBajbPn/fDEe5a+WBLIp2mK6Oqs+HmBb2ne/tn6xkvAZdyCPkn0MUqjlTr nJdZZ0E7uId4o3BM6C9jC6H26YXzHhqBvtCvHU5PN5Qs4ySa4Es8A1R7Yrnf0xS9tXLHda4C/hC6 N5t630P1F74Vrlk5YEHT28fQOcM5BvKtd7PEmfZJA407HKFffE0E1dbKYGqjc2zBaT3xluOKn/Um 7vR1qm46frSfQnCi548s+OB7WtJkdUus0eifZAq3rh7kP+n6cNA5hGCbP5BJbvwdRowbZO0WLtbm 5byuyAHh3GCibp+pSrV7yGJ7qrasqSYCxnyeT6FlrhK3K2e+G/r54UD0c+YzNk8/szNDYDk0etXS A4aHWNbCUB3RvB+T4cpG966QWQW55h5iY4SUBU7Fn9mZWtdrvLQvCeWPnVlJoqtfpjqMTeNcjo5+ S/E3zefxgdo53FOhlA+kshTWCi1CwpVLxxociLzjEZGQ3/rNwninLYrY0gvBozdOESPaJ2JQTwS5 z7L+5n4SJcy7zLlnAaBMONCOdM2TaJ/84EZWZW8tJ/Lm5+VTf8JFGMQ+uMWrvF86io+4eaaCgzBL hPhf+UnKy5FPaXhigqEqTgX8962SLQHek4TfQxAuJZrwe65wNp/n1mTr3eqfRNoCR0yh0sLZvpKR uS9MSyir9m2S3yQOwfXjQqEcla4nQEuMXd1W6J5IwxHlMeBfneWtGTf+/cH/k/NwwHegYZJ4T7D1 UrFomYadz2iNDM3SWWC+WtSYTA5jtbSG8YhUyRVrgupnSFEhjrPzlenKOoj8JcRD9Ys82e126+L4 PBnDJAMkVgJwklZ7dTsPk/Cg2Yw/84LKqPX+vtKZiuo6a1INnLehsUxLjZ7knNbWez32nqVYAYtn 1pGdBnye3no93gcARev291MHlBXA5XIzIy1Ld+1Iox99HaKNKHkDtkmkG2zdGo9rgXQHnPjab7HX 8/a5DRmrj9Oi4Wz9foPggi1piJuHcJVRBM7+BFR5ENZpraZuco6WRDCyP8PrXsvYDHE70gOIaqtP e3bQ7FjUBbyKTx0TmpJsZVOL/42BMgxuXnY/NSqAsQ0Q2XWxLMlq2x/OJgwg2GsB6VePXUJL1tKJ YuOVoBTmHP4uL2YKsxik+bT8NvL6KwbFvrVr2ga1wvfrDn9SO/mnqKnKPqKHx/CV7WSHfVbLQTRg BdCN9A34AlYKIdNhBbmVeoh45vEViXGv6qIMB2bfN1H/uhUlKZEXdDuO7/1tBVxoAOR4ZDDPlMtm /E3uUXwWNV6jW0qS2lTaAe/SgRei8EAGjDgVSPbj0zm25cSGFDT3iGcs9jQRSALCUE8d1xzSWZnU mZaNOVGGOy2ZxrZTYxtw7eKqdxbf3oJoOALQNKjlvgCwXsXiSWIHOtimyyTwTF5pljTfDeTnBuFF TZZmsgS2n24PggKCJURGEVY03F0aeTaKTgH5Pck+92QyO8eCSTfk4RnkYd3aqouGvUFYAaku69SW D6Ravi9kO+iav60ol1gchOO81yJJvNp1TRaWPwdsmhhly+ors3w24Mp+gklgntpNLawxw4/fHhPn k6Rdzh2G4sXKuQRzUUjh1K0WFAeiVZsbjfaOg7K13sH8Tz0cmH3n65AU8+q1Sa4XP5wuYFabA6Z0 PkPsPoB17bmvUZlXNu9np4tFSzU/umtH41GgQmTcr+fsm/cDStUSN8lXss7P+hZPjNc2Lt0shON8 O/G1Ba5C1BaFgGamO5iYp9jbrnrOPwJG2ovqO724KKhmm/6C9BCqXFl4muH8AX5n5/WWCjLWAj6f eeZmbia9yTZohyVWm54QUD4Ce3gRjr7Q8Z+iVK9nkMTU25WK+WsihV5nMqXTRIhd96YUTRhcha77 IEux+Xkh3F6nRgmuqs/7fFGXcri7mv8ePnxc4nK6Mh18t5QJfUTj3Rp/LUvyB3/o1vi954DTU+VD LFrnBs+vmtTTfCPM4XgO/0oyq5n5NGUbP23qk5Te164ag/JTT9HxCGj/iZ+PZL1UqeOuQxaZxRHW 0VPxxW/43oIfTiLZwo8CjGvumaEKdJqs1j837TYA5xmaKmxTyuEbFviXRY2gkiixaX5Eqlv9Q4o6 d1pZlpjJ3ZAJ8L16DQr8o/Iq7AeuGZHxzI1Hguj+gjFzv2syw54QF0E5kjYOhE8zwmK0z/KjnYvS cOpB1KTowAirNQ5fTpU0Jbo/y87IE/KbZ2+u9Dn/ImWbIq42kK1G7yXUqMp/gnv2e7DOU/4viFIW 4B/kqAPHxzFoF9N/cJGNjBc3+UF676IS4omjjX6bNUSydFHwh5QnwPCxolRMkxkVEZL1fX0/gBk8 svq0cBw2iR8hh59XWnGdcVCqRJUGV9VsxQrzzlalZk7O4hmjx5EtSoF3c00M5kpjQTtZxdkMa0qB /InTFhasjI3CtbV5V91YZv/VFooo/ZfT+YUL8TvojQAsMCzkUYhgPlnf4zRShPK3rFv6Mj0tnrRc o4YestJBcUO5ATzcUNELInuZPTjMJJefa9icInQrlQfCy6dZNTsG2XuJwthKq2XkrmUF5b4lzU1D SUWJM5sq1VWat2+TXQmh1JfKI8u3vk13LEJP/SmeMOzceqtftVjnZgBh3rOnTPOh/p8Bn70cmSMI qTlSNXUKE6BkqcLmAK2/oTxf5ybpFp/MrH//7HQMafppSNj+pMoJX2XMLKMdGH/BeG/GCWJDrKWt CkjVNyTfuA5DiJdAHMJCf6RFMrgW5eBDNSIfGFhNndV1eva+V7iZD8Y0Pg+RJShNC4He2AbbpIWi nCzKjh73Ud5hbp2Z+QZtCbcgPc/5cgPRJTcS7p2D+RMTPv4vZsEwHSulKP2OaP3X6Qq67wlnu+pq dypNlwYNpePjGnQf0QvOLOd/I1F58IsRmFiSYFxrXIA/FNUJUCTdCkA5msyUZuWmSclnzndgfCDY Sr21xiBvwmnRA41d4JBFbNEPgV34ZtAKXkC6nzbamniX+8AVvC1Y+BIC0hU0SM7l5w4bfOBxjm5z OSlojkS+wQ8gjtEuPQFca6GG+iEXWjc3kXfiW3i1fb24RJ6DZ83/Fjct3Nt3G4VZkYS+5sQtGJjo qC2zLBQz/Cv7ad6RPfCwOt4xaGao+PVbK6IK9XQ8XKurcnyyKciWBq5ivgYOZZFRRzCUPD28NaE3 G8RveuClqkx6v8KGv4naqTfNQokOoWRgwXLJ0Z9FnTOFWmlI371A7mW+yQYaMI2xYvi34MoMa1DL 61mK5fHsIsjWRSJrNJrE+1jsrzk2O5t92R0b8cUrMxcel+bWi1K7GNNS9gDEn2x4wP0cyDPXPksZ aV24BuKHBjVjvrbFT2OEbOyDzJJv/djZ0C/LFqXKoRRIIXzOtYGKgkI30kxC5sL9hFm9a46g+dcn dF/DPtX83+T97yNUUpvk2WN1Aloltu8aX943qycXuQo8xLA4BRmsZbxWJ9LAPXGVYOCQ7u2h6prS 5nZoFFneC11MKKk0GJ3QY+Sv+LRq+gT5F1NUMbzXXdel1TmWLqjZp608VJG5xfFHAvrpgfG4Pryb iPFVTLKwfc3ZajE2SEW2SCkTUPwrbOn7u5rbJKpPb2GXk8Hto1EDUfk5aUjJDAZ+jMlx8mWyjri6 GcjkVDxtubmyK5LSExmX9y6aib8PNCORLX1A2udXEvO6X7rDvMYInVd6ED0syXn6ft4w4gR6aEDV mD8WOgOXq1oFIdI6LPYXDFpxFGypv0Snv2HDvjo61mHfvYpPuTE0i1mbHsz5Z211Z/IWSpOEbr/3 z7PSsHVU2wZfy6CGqlbE40fx4k9gGQYIzm69I9BWHW0pWYBGDha5jd5JzVKA+B0qoYbXI6BM14g1 V3R4GkNuUoTQ+hS94fGd/dQDwofJmv5M2Zfh5vVGmyKWKfR1El2eMy7+af4mqH0nqqUh+Cv+4SjX 3Iz/i9+41rGd1zv7u81AryVAFd0bdSHG5Uq6i1wgj7RRZ2edIbmCF/yc4yLp9aiLeQZS1/yYqx+h A4ZpbiFmP587t550Apr8lSyIqcKl3tw91kssmUHiTFY20IjSuFBKWH0h4NdZ7L70EtRqRciZ9cHD Bep5RmTlNsc0EzWvCQ4nxdmpUImWwqaB9NqlDlXKSu05I8TBv6kz0319w/TkAqY/kUafJlRxoWtg lR6Jh+4OAOF2C7AHLz2ToLqkczLYrRaavAvs/SlXLc70siFwg1vISi/s7l8/n3q12PPT2U6Bvsc3 kzzCOk3Ebmt8s4JVW+EV7MvjQzAcWuGw15ule70jaeywSiS4w60bsInJsYIisthCWfkFLIEj9K4n Hstjdcd0ZesNTF/Fekt7+WCjOwhDCgXiYoRQTqWEGqlv1e4ilQ76vYvjjFAdqLs6dr1IBJj9w7fi LqO+6YLyoi03Lr2dvFk7U41GFwPW0wtGScKOJJQpbyL6E+he4LMkXclo6vE5il3BsAbhKWOC5kHU e/oY/REGy/Vs1HSKo9bnXhf4SYa3WfRwIeIeTy+YNAo87soI9MNTI2l7nH8nu5dWojPqfDYPq2XD qQdl0Msi3SrNZvQLCunrQ0AT8KLPDZ1n885iAdsN/pCjBxVzxnvAWyBFw9u990uv4GneSwpJ5Ui4 TOtZboXFTKDx5exM4KjD+VEMIwlsEsHzydHrYsA0ltt40o1U4Pq6+ivC/yZ+XxH740oa6yVvhYjr yX3JjOKkRsEn4w32wqStb8c/81/jWerx5uefuXbtQW5n1c88/A3EOkF2uKyczU5EjEqw2X3aZvSG Ptzy9eXgf3DHZmSvz69HMsfp7fmkr7rTFWB1JSoExliFQF3oPaelOfheVY/DtPCTOuhDQ0gYIHQn m0JfBfrWVxPMEqVsA52vGNuk/3Ecbctmk8WxxMAHlCtfm9j4PtJPp9UIQLHezHP11O9DvQmeaN12 9n0NbgKoYcIdRM0ivwJqSoxOuCOx2e186h+C+6jCoSXpCjcgn3/rWg+8RS2xWDwqvNXPUSz5/xcq ke+Fz1lYnElndQSijIjJFQs0eYtB69gkKqhkOTT+HbvMjcfYRSgodeF2kEtp3zLk7+lIGZuOqVoL vZCnppV24XAVxxBfIxatdqmgVqEmmByG1wfVSeauyxd9z4TZObq11fsNGe/1E9NjtTHc5fXbpbsC YSqA3ZExD1vKg29adQKj2VthsPKEBRMd2keBDmtkRCKRWkILyDa18bm13kIoGA1B6o7beDJmPhP9 UGTuWgPuVQ3SMfm4R9Y8Ype4v37NUSpFiGU5Gwh/qohBJpGlB5DLNL/6GExn/0u85cw7ZPbcFAmg SUqOc8u4sn2HaiDDROMWoBwecu3YCxSE0Mlu3xDhSwD4mRfs0zp2AFP/USCfm2cG4+hTJS0DJ8b/ 4mS+lCbzXCoG4k4vlEmtI0gYZbclGRa9HnRm4fjxmE1w4WG3t4DUyc+iGModTBMXs3Ud6hWSOaa+ qd2xprhLUG82gp/SVg2/M66fZKqRvNg4V/0Jk0qffPluVr8ZPlKy5yD9TdTqlS1p3uPh8n3P7JER MbMjlOVzgxsqFGKa5QmUUYEQsdowtcWTdvVhfrqW5I4CTzYSLlEq4oHYTeZr3Jo2hrRf/HHro7V2 Gm0NAzPfPUIKRtkn12tKEN2lpULUVTD+L863eDfuEGNS4NTPjZBFsjfSSC8X4sNE8SoFgknZY1zq 9eQoI6H6U5dXXZRx95WYNZy+UkhBbp1qzgq+PQk/7/P7vqwD/mmn4+wx/EyCk/fFyoFzPMJ5Zz54 zyAMUkR8tl+QBE8SVgvfpkax9GmDfjxnamqe7pzpQQiJh+vEP5ADa3a3fXz1FuKyCVFe8fseZiZ9 /90mu5ESWeTkA/n6LAr26n2p4vTbJfuWO6B5cer6DFgimcv9Ahsa1V14wj/9MuHIQrf3aLqvMMop wQcnUqkhCcJzTe8Mw4QE79PvtekOr3kNfR5nr84NLhOHLrEk8jJb/xwOo/16xrfhq7rVJZnNy8Ef 02hlWRtNM925pUkU1kWUsFXp43kBOXO1Ts7dLy6Nmpya50EOGDXIHLxQP3If3ifBJloMDchU9GKS SOdTNKHTEgmwvuyFoqUeNUBhzyttw7UClp9+tm4Yrz2RRMaYIFqxAj9W4ATLBFnUKc1pJhw54l6v 70nwEzNeEJEPQ1+KRIif9JiU8yqUrpEJGDyWwuLteDqcCg8VzSH3Cub6HHYKTLHr3N9+qGBvXXe0 zxvlogzUSAPp4l4KI5yOpTAmvcTnzgWplKY5QSl9JjrTBg/N1JqjDBvSKOvmLZv1i9LlKVtWM1dV 0BQ9f/OT3Vtm9TiSkx0XFrlXpwZ+OLeXLjdcnr9+QSl1xduOF+MaS5ZwCohsX10JzvEqZJ/W1230 7zl8z92YvMoK295tCns1PTvmd3x2luYJCNVfkbH1+fseluPFErSr5ZKjvHxmPgZt+ZxdZIuDdgwk EKkc1MxwUjQDo2FhvQ21nzKQuVxzZOugIvaDFyBQk0su57aWnpLRxsDjACMn7t6D7kRyy+uFHeUK DZ8GenZxZt2S1OhfEnCurfk/HpTEbMb6w5NDWK/29ZKEB+8ahFFLF9G0TZ/ZjrnMtPiPzBheNGcn 1XAtFmZ0Oh10oM+/9u40UwfZcBLQUivl3nya2nUojqtxZFDsY8naJ5b3ymxPwXXliWTyqHBoixzz 4YB186v7DzFxtQzkIChPV0eHQcyi5g+fVVyQDm9kq2bJ/VXw2SOXYPzKyBZaRON8ycuHUllY6TTn +XQAEiHM0K8bxMaGci0lhQ+4o2+bGTX08qyF0WdP1TqIg/xBjwsWtUE2GLFqnH6DLbs0fvXQ3a5D fGego9YKpAi+ZtWB0W2QTKgzvur4g7vDHo1NyvcWQu1AAIfT5CUmRErVcl43/3ZECmVaSdJn2kHR RxOvXJ1x1h7qSNuEm7Q5l2OfiIXXpClWBBVM2K1prdUaBqOTsGbxMBjbxye4R7LEiTrVK21Hs0L6 xEQvsIXRrpySDjdvS3/GcjCflc10mbmkPAYrmY9JsoKU9AMnGEG/8zPsetiPJARDILVWU0e1UO1f rDl8YAE88qZtdKjVwxZlMe/nUiCN0h8iUL7iuwEjGwnCnPB2oQq0RQZGKqqMpeEdF3l6dICwc4WJ PbhjV1Urn9x91+LCnToFSBD5//rb9vD1epzB2bUH4Yx/j1vBEltL7VvTDJJPiqYX8u8GLFlND4+E MNV40jTZGWFtXmoTjK/Ysxa+OW7qzM0N62wDlpQSezImK6x+pzSOcqhdIDwBaBiWh0BUD8DaatY5 fPdzALaupJM0Y16KbgfvoweOBTinSkUJgK0p2BJx6fGTwT7WGz+SMJCjiehqEOQ0WRpn4kcFxHQT wz5gacJEskCBv+bW2YFzfK/evjMrKFHtHtF3Urs5/hpC24FTOk9VZKZZbQqctIFKGAQg8C/qPxGt md58sP6shuwgd8QIK9VJqzJY1TK4CoQMb+JWmQFpkyRDmxwrO8u0M5F6eniRGT9P7DdX18h8do53 hVHPeDNSdxc/iFuEx8sqZppybxDjy2Ah4bBr7hnswmeGAkX6ufGGmWAfIZ0dv+CjFfqQYhnXvz8I ggV1OwxuRkpcwzPmQ6cvff9iDobK3nkZV7IF3jA5pZv4AZ4EW06iij2Qolz9SJPVCSYAUSZN9E0V jsCMM3PlxICiGwkmsaF16SAH4J1WlH5/sx6y78rbDGO4g8S3CciXa7CEQMCZT20A9qD/yHPdHPxt ZEdsnarPJXL1ggcppQ8UaOXYN2FjMgrP9sUhz1RIMcPyHRGuHrIvCvrkMzEXYqRx6SQZy1CoAMmN /xugPvA5hALMPg0Rr4trba7mw+BKbaTA5hSBVvAI2SWuJWXm8TREfJlu7qhNO7juAVQj16ga7ZPd /cn7F+j+Sxrg75oIv9GOeKbjmxC+V14FU5BQSe+FZQv0xIA9/sLk1yOyP+Wcru20Xm7xxIec1xyB oyv7WoBo+TYQ/Qdaa5PBRHh0A3fAmn54hEhTbBuVKTguVOY58H1A6f5pyW2elaKXXI1xuDVSYLJ0 fwSR0aFzh68bvkw2yYMUnerNSU5OvgmMD4owrGWNLuun4n6IOZiVusrOfUGLHusG7J4d8lT4s9hn IVyN3C1Gtm9d52AxhzpNCEtTxt6kpR5+LZ4EeFYb8XVORjQH6VJ/PV+p2o1YXml2ir0VgAfTWzLr Kz9PSSfqv3SfGtHbEUFr79eUm1Nk4KcfTI7xqiW7Cza6Hdv1njs7yDXa6ig/PdC2YBZiAOLX9BsY +hhZbRE4vJRfbPCcNNXEo5K2nHyjtSi1eKxmnL8xbUJZgkVAV3WiEfyjElF7Z6WdHY2A5WtT2vn4 ecXKZ6IXmu9e7OBVvH2IsAhqu7YKQHXR0BlIB2z+xmVUsrwRxfjOFrspPww5jGvPSWl/ieLaICYl c2eszQt+EeScrzH+Eu+DXy6QeN45IcIUpIFv1uiu0/8CZMD+YKqpRKa0n57YhEZuT5YCUehgGQ4v ee9VS2XPvFq+dn4+mnTrKeH91VCb45Nh+ySgDAG9JBdc4sbhxxwxAR12Bwplq0R1rpRTxhnsGiYC dzzBLnTOMlorI/iYVv6QS02V7tnlV6cv/6JBjQwQFej0oOwo3WAoy4TR8nqnu37CRrbYwxDvEcJr XBe4cV8IdGy+WN8uEs1w21I5ok9GgCYVKoVzmOlfU+T8TYG8hYnA7y2jcSPnu/nTF9Bw4tlZercZ HFm0FE2mBMLS0zt20Ettl+OUMVtD0AoduP0PoSa/91p5d9ulyoKiUcC7odDQ8lge9A7PnYFvh91t 09CQ3jHbcPunlbaaUtiSZPJMxyYFzKt2EVY6+tOujWuP5heOXdoVQTyZcH5sEWiD4kzlASVUDATR wkk11vluhIegcdOvxle7RDQcuRb+6ZldBGKO7ScDcaSiPgKa/U28zN+KIyByBQitXthvUBpZy1h0 S9hzeCSgJTnSDZS8rQKenJT3yoervdB8xLkVrHrmZ+uL0PrEc0G6mnAN4TjjMfNHY6w22f/1m58o j5XY6gadON6AqA5g0o5kIvDgo3tUPaH0evjzDzqvAz0RCXGQQV80zgvcw6uE7T3OPQkN8u2Pj16y BJnjSAVVdtoQJ81Wq6OjfFW+Bb2JcyKyI9vMhL+vcL0uhP5p3lgyNrs/FNg6VN0eljTCU54uqbVm /M7ddCf+XDlSz/1gW7OrKgVJ0LzU6vM32uyciIoVrLQE+vU0vgD9NP6bTXTple0ZO5CUhGDGo7Q0 mKvaR6wrIlOu4PuVGvmvYnC5qTotkkX40w1fNhTCzcdYey6NAtdqWU4sIxMRD0ao717cHOCnSahp fAcM3n3pEfrCjnkAsVNm0bkKDnsas2/NcyVK9Ao5d8QmTBzs9ZLDbGJQva3+NnnUhR7IkiekFT5b GZJCn8VIRKzPtnO9ISPY0r8fAQY4JHMJ1C1OvQN9lHZ43EmbnhktDZaKyuyZnQB3bH/Zm6oThqG4 dXrF5UDS5u+4+itJQCuXcrNWv3Pv3+K4f3vzBnRNSlDYba/RM4o+RrN/diZv+AIcmF/oGNYjiktY /hDiFdQuDErT4GwGL4XXdw1gPAsLf23eQA2iz1AZCU/82TinWgsAYNSVWw8nd/zONwnn/dY9FySK 2oHSNm3kdBB7QNNcK7KuAqHRf9ZevuumoCRvxUIeOSFRi3IJU0Hly0emluuxQJt/pm4gLWknQk88 KkO/qnL+x5cTMnA3d+ERwBZu/AQUYPXRFUv9ArbMUQMbzWdmOi2sxeSt+6UbYxNBc5/ESaGPrq7/ ctMoanm6K94MlDlLrCXzm7SSzUWqJfpOAWVXtky2VuzxxMk2MJja78aixW/q+9xNtBp+Sm6JacVw nhcFujjGmqv/Ra28As4LvJXKDf589hx+25IvyDZPUl6NVmm4l6r0aB6LQVhsFBgediRNq2ann5pA 1LkdzNfRHtCBwfO+6hlwHfzyDcwCiakwTMvUj9rAehP92SfWZ4AXmmhvYNQxdxxWJuU0Uf6AlFEJ ghbd/uNGOhomKPWcdABxqrQEsQLV0HrOFz7WoXh7KJgoThvitdjqE3jcydWAiq27UKejPd6LqmyE lRDm2TSfi5hKhpMbCOFyi747aX5aeZtWVNwajHEDNyjmJgMVtZmS8RwtDdzHSaHC5Sg4GBVbjVwO vJHvNaJ56+DRQBhaOtK2lu6RZEM0DzbsWOiUw9ATf+XfO0L9yS8JHhCv6x1yGBcL6jalJ310NxYy f5q+gx/W9+SJ3uGTbG6ZjeNZDbGmaWg6Hov5wxBYVY2Nf7l4dGbIYjqdpU1WwlkND8g/XS2qeE1P sOnr6fJRlyUTNmc1sM152WWlRu34meHBgT7SiGcBBYEGZwMvLzLPyB4drDp7jqj6gIM+NWx56phU SUpzV3qwwt8iuhSH6UmAzda3cGI70CAfzqvleT2USt8GvFL9SQ4h2iTP80WO/bPydpF0sGvXyUHg QxF5zny4BZfe2N4cngX6skTXfLcch3Pc/ea/w/ovubzAVbE+0pCQyIOXBYrINlwx5eWD6qQvs0DV hhAmi9ro5cLyj0hOAxDGZbVUzR6KsS8qratiR9DbJ6eMbIn+pzHkERuKXbAEyV0BQS85t8dAICcB pBUTTaq3aXLGMi/VQiNut2qgl6I4+A7d6ViJUeSiYQYBDoxrDiD1kUB5+fw6IRx6MkcL3kLtKvC4 8FwBsLeGNYqUFXxrN/llK8F/NeQsW9400fjdfzCQigTLNjLBv2yX5hq5sUy9xtx62D3HXK1vY+kI mdxhwHti7zDWZhgjNoy6WQ2txUpLyD1cDI2vbASPUoUh9yZyYbak2ar/AzkpVOEsASVwSnClY1yg Tem/ayQDgLJXw57I2sCzTyS5/eC9HzyIvQzWOFD1EXZFovUWmHKsoijrzC0oMEzKrf27ojE01gu0 zi4J2+tXYTEMee+No2WFiGSTLBpKv6XGbXdGvy1Wu+mxPf2orUnZ7fpjIt351SA/CuwlAm+ipRVq 0gxJc62kgvgpYMdl7sa3/vA0NFPj4xqCxSFpxyJzSXI37hP1+CZJzaKaJ7rgWCWPkyuYkovFcRYB fk9GQp9WneIDAEAv63uVMGoNqQuowQv31yaITGweVYxq+uhV9AX4rB2zBBScSRqJTfN+VQvWhHRl rJG1g9N43zEyTdefxNNk3ZYzchNRFJTyVoNcgssqFYUpRLls0xfBVKIgu/x0gFo92Uv2DOAM+XwO 9FHJSZR+aoB7BFqimJYh918T4qLo7+yLwEDFZmpW3WQMU8iO9h9xzqvluKarGYHDDBhaeN6zer7Z U0qaGMOLpd6nz4cfEmCNA4u/tweY01aWXeZaPKEtwmY0H7AQqfw0BTo8j/2zrOs51e7rC5pjgfu3 ZLIoFioTWjD7xIjA+MRaRAHZBMGQvonB7n/jPN24bDCvo1Z4Y52kjowvs60DJoFMmx3J0E5QYJfk zbQ0MCn7Suh2eHPmC6/tidTALK4vI1KlEap7tL+WnpgOe1tUGbnE8dEryjfzDoF6y3aHWg1z61/s ppVAKoMdh6oIRcKgcTW3IBDRwMsxPwI2MTSMdu3PlUfZsZHeiHdpo/QxoA6Id5uwH1ON+H/hGDeK JCkn9UW4ADvQrkFFgxRNbpPHnfI1cSUG8EyXWHLJWAjqIQcSru41kh0HRO0w2cNnDHwXSe6RbeMm VZMKBr0pf+xTAIHX0PAENbmAZPoh2q5Ed31whvQBrG24bxG0RkhpxxmX0SzoLk5ZMoMHiozlvaS9 f6U/a5L4nUr3pV7YkYuXDUn4Zxhp5sR7si4aay9VfN5LNBn3eiTdAZIKUrprxnxSEEw6Z23rrOkU TmjwL/yWLMYmI/OhVHiqucbAWP7DcHbldXsDMIHcUfbBB8jviJv5DG6LmcWtmObCZYLjvfGWsEUV Nnlfqsr/Mv9oQL202Nf03eq5l/uS69RL56fzB9/SU7XTePWhsj1fjKk/OYCvzonCOczakhHdI7xo QnDcKa7wfmnZhvqRCbNR+BDA3A0BT8bgZU+IY/jPun+mi6S6red1/uc90L3wvhXy3xf19gIf/NjV 81+8+d2KP1nq50rGS3QU+KYxng+RHAUyuGOtTpAaVgicu5jMVd1yPC/D4I3ytHWKeayoG+u9eT4v XS2k/oOM1cDMR89w9JR3BpKBs8AaXdVj/13b1+BKFNWQsjhMG6DBjpNH20yIMxWEYYTrBlhJZqWj YMg16O4FM2KDsKv387FCYv5c7cyQByWgpdiY4li+yBkJCiaPus6VAqaCj3ezydGXZsUHkMJ3qNlW +I0kEW8ag94T66l7gPLhBHPix9TbCO9y+McLhhAB8TWMZnyrCd1KYua0nCg/B+qIBd+2YJOxV0Qz W7NnwoDgMVj31LtDndfok16NALm0soET6HpxIc8HSTTFQsSSuEIQSo4KwdW6AoLl/7SJEwM/Kk49 KYpsH+TJmwd4KPw3OwxLs94CdIlnQhEcu1xDn7nJrCBnydIDoUlHS7dP0Y4O3tYcQPMdVjg/L/YM iTBtZ3mN95U6w9asPPvSnTUPhsZMvgcXH72xvlxp0N8U1iowD30XhkhAK05SlI/8M2EChSAxg9sv wtwooX/hI3ezeDpHxSxwqM8DrRQk8rzxZYKpfA80lMptcn3OJj/MsSU7N6K+g4C591sH53v6XEJA TS1mXDuNq4dLDLow2jNfResPQH7C9/nNxT1nEtr5mKnUbR9AqyrVfQVNka/rQRM2O/dfNqXuvpUZ nSaxt9rwtB73OLmJlMd7rONBIQjdiJehEe8Yxrhie9/KyukZNT+2wj3hZGOMnEOyyFHx14E8qzfA ugUilY40lgeSaMXmpId6nkc5anUvVGJUJCQFne8ajTiGHQjMxVV/Aa5PgG8H+grx9jH7WCdv9TL/ nJb+uFhqh4HrhX5xLv4ANFbgLfeHo5pGrm4eUn+Qj72/+wGGOrttbAtzSBCu9Kf+JNOY8NPQRLd9 qUr7nCrZxrQe+ME9Jp7JdYIQfn/igVvSKFkPf3yFnDdulFgZGlfVNO9kcWs1VkPtzI5BXPzRf6FX GfktSdRT7e2EFrFoMUJs0Bm9An9ZeT/nQEX8xhYTCCP1Q7wqq8mUz+FiDTXe4cdwwtiv9LLqDdk3 1xs4XJlnpGahDZzCWLn5WtS9mXykigj1afB2iPL9Rhimy51Nmb2NgDIaqmkQmfFtHTjdkZwZkhJQ S5b1F04eSJITvLvmKLmSWEltJnplKXexHibtfzXozVsKVwHFeDFgCQfDHhegJEU1lXY2BYBOxWHc nCpWxEp3BsWJxJSSj+utnCkt1StgmQJTL4a6ltd1z0OU/JTJJ65rxcvQ75WwB5GIt4VxXl3Uo6up XMC3yjTq3q+WzNR45xvgdgfbgfQzMTDYPZiuWQU4LAfI5nNtg43IA2QRAxW05SHzYAzYHZ51urOE wZR++VW1bwyE9rNeN8M0NxTOugH0p8vcUP3c/R3CjANNmWJHtdEuB1956J8r0fmiFDuJwOlT+UBD Z4lvGKBLZEM04ZZPj90vj3SunTgkaQ4q+eE8gid3NQIJNYO/STzulJCYD+MefLvya7QEkNXA1Ip3 VmqEaLnzVOQltkLxG2hLxZgF2devEVDjtHr+NTlPXdQ/0rubyB4p7zzuwW+beJS7nQaWJWuoFT1F AWfMdfndZUOQlyvhhf3xKkYU0EvHM81t18QbGiacxDbuZMYGiBEhh8+7dmTmNHMZtoqVAvOBK6X8 y/gFfWV3qvvbCPgCx1FELBtH4n+6OaMa6oFeHETON9ROiDmofzBwC/ij5h5c7dG5aV8UT1qXkHbP 0/jZEgbkCAZtf4+teq9G8YnaUcoHhiL1e2ZPDBCnYrgkX9nOAFhzIgtVi9FURQMXgHCvUjRbPTeQ 8FqLE+ycbzcAbCGyIITChuUL98gItUut404XGAucVoZaKf/ra8ciZ6nm/jlAmIxXvEy1Ci1612HX V0NevxYbkqH9fjseVf9x+jlbGl8hFmJliczHmMqkuTy5aRbbNhAZqSMd7cAR4H/VjrxgVhPu6+ya ipq/f3elkWgwRiIlcIeGcRvFyh5nlCGuqzGMoMms2sSE/RSaSMLWs6PWnYi+Q4g9nGjX9GxEvhXg oYsPQrx+uZwLx1U/X+E25R44n2gMh/2bNGQ7UtTIAoamMTyJ5/FFB1PuYPviACDEKALuXC+OK/WW hnpQSCxyvYqRrK45ijF2fL+9yDHieVbBfw00A97fJ8vVEAS9WKJ8NrHGrLWTWBUlaWEzNtn/KZJc Kj5W5Eek+uIlhwMhdRlOuwbTiIuxtGsBNccJZESuqaQrGhDOVFJ2trkkWoSZmCLwCiuFY7g/8y9t /Gbs34D2WUJzq7at9I0l94QhYYFdctWkz1JQMXWUuvBS2hEA66SBwslK/7abo4NdHHNqyIme2Q/N ZKuGLJ2DPfn2ZbCxtnEsHH/Tp2N9/HszBFRRSd7TfpY4tF0MMJrKWfnlzUgK4gpQPmnqfxrDx7r2 /v+S7u/wFzlnIuwuhqcBAJhTqqfq+ch4eanJP9d3wznpTIpeOiuQNyXLHWrubFQEn9amFVrJsrsP He0Cfg4OhczAjyPKskWVDsfPjbH80+arrVuuZ5tAYKCZgqnYycyvgSkFPCFGuy3++ycBXyfWfP2X hApg1RX9m719x+KfgzILraMNYnnJqtOKSkhWQ2yxD7gJfNZdKndgSvwbSCHMVqRqiR3j33R1MIJA 46cQP4fkBs1HwdafK/oLmdZys50ZCt5E90R2p1IutarI1p/TufnKScszLKF89HJSBuPai0Ip18Zw YjwMBxxc3ZZ0wMRse9tCHM8Nwd1+mLstxcXKm5ow97FaCxnvkQV+X6korDtPygdywzg+REt3ozFp gJdaqDMDfnlerhFqHKIK+6PwIxhQYDegU7GbhXMzK5H2wJ0OKlYQGpwXKu1d6X9LGlsoB2JX94ey GT2kUJMIAJzOBDTVJsAqYwspiuenFYenxQEvG8ZWshpHVMgZVHl5HR8A8ruIYbMJF9/PF8ua6oGe nRGqzARjwB8WQA/s++Jo+wQro0jrygv+2YU0wKOloQZTvZwMKCjBlmqjCmHJXbiJAPeXXb8KNNi2 OcNkHrPJR686lDD1bW23InygsXjVgVu4sYX/wTvgKEA2O7Q9hhPjGkZhKYC+9EiLyf/NSQMFXhIO 9qaQxAplXWVQOlShObB1LYoBApcgQ56eYzlYNJmVLEi05RwqfBVKwsNWcXAEsfTpOL+IYvF9Mp+c wvJ6d4f4reBZ2XNa1UHBBHkcB2RJLXPhYzSwOLijcNFtHg0pC/5b+4FlVPiLIBBp5o0fGMgLPM3P k0gon8rzpQSbZbz1EaEg8pix9EvHQs1fK0Wtbe1z3tTk6eCQ1SaiKcx1WHEorMIS6WHf/fveKbvG 1aev01qrGB/TuO/rcnSAq5OHBqBM1ETka9JJDBxDsCHZvqocO9qWL45Mcfx5C9ZHfAROqSPfHuTl 0vDLFK1Mb4GfDLC6WTL2GJfiuCB41M28OdObyRGwsne1uzHCGonF2IuJqplmzVEMh8EoZnlJLE8m 0rSFAMwjSRIgS4p7TFPnNYHrEUNL0GyGm9SlXTFwpcggsrV7/5m+JkIojWfGZTr7FjlZz6cn2Cen lHlydUSWE8ZytRYCjd157rAVS32MTSUki0u55xAOmuZ82e9wYia5z7rnkMH/qzjtXMi6QsUwd5JN GxrHr6VQIPp+M4n/glHLZiMk3Fjq4Pgntm/pWKGhD+e86Cf3E3SeRDj1nL0j5kVOJxpmF4N/s7ey ilMhkSatNzC/8EOvyQoK/XXP/Wil2vCQWgwST+JRWMTQ79ysHMGuADAURy7ckm+9Ku8oghylf2i2 s/OQimUIt1FOYOLjh8RB1PqfVIYO0GO+XJ/58QGyiQwQZ7YMHpwu5qETcZ4xOavCA+7RexzQ6xBA wUysBPHXQCiBoLIR2x76ifRoHmsZeTIBTe0VyoMjMpaUqtt8+uSBsR/w4kVGravtbkOLdkv6Zo1e ql9A8N5FeB5Q7Ye/fgiYzNu0axQP1MG2Xs45y8RVPEkJnEaccUkncoEz9LjsM3qtqpgti1V/7Cr0 Xzj4BTaZPuPNMrg1nuuvDBsBBiRD3n2aK0ZxUIIFFmc8Ntqe2gmyV5aDBEJmhmmPt/PBoOZSRgbN C3r2RYDWRM1Kie/MZpx/dXGCaAmBborx0ED6vaLTfajOxT7oXONzqd07P9GFo0Hli2eoZB26hJjE 6IHCeubvOprfU0ySUyYCqfBrguC5yCbAkPTw/WwKIK76jFmp0ncc5iOF2EEEhK4egrPDKENFHOaA jDocIO0nsnIluC3r4Kj8K6RmnakxrC5N3VGyH/fWsM8nubghS38PCEd3NWoiPxx0M1uPniJLMGnC MQL8E4a7K+tPZT5KRwbl1IepfhKVdvHhHyQQ/ngZPIGl6InznmfYtEOoJkMNVEhGcoKs2UJj4eKh oLrl+sdGi3r6v946pWhlptaftxGuzXuUikiIS5jrttczqm6oEAUodXsRQ81THlYHPyBi4hQL+ok9 R/ufMRA8cY1LXjuKXWXBeAFS9UeQDXGO21SjElNfGGLqVH0trJY9k+9xB4SsWk8laMmUEfXQjmEg x1oZWJJCSilQvf21TMWOjk0T8z+LWuVHuoc8h04S0hgjYT6HEJYYzlmsFIZcayTxu4ZI0xywM2hp FatgeYqUEd3svqIBm9h/5TSBHO9p/MxSsCNqYMDNU81R4dMAPN3QcVndczHvKtQ54qc/C5ORWR62 n9icOkG+DNiZvnrBr+PpqMIPCjV/YXHr2RngyCYy2P6vW+JsyDR3sSmoYElT4o4Zrq1Xe29IK8q/ eQzojh5KhytEJXg4HEt8Vza7eOz5TWOh2awFhQ706T0KLDaYpPi0gd/ErRFsyn0BlA4WgYZxPJ5m 8UMCBFg38y2L6C0FJR6glq1xuItgW59SlMczZ4L56FgtlNuURR5gxOhopHdE/u0Ynr9fQuXg8KWt NyDLqDisfEV/q4KnbiXrQa8oN5CsCcp5Dkc2fU45MfWxdFMh9s102y3oHHy/PfPDRuCS2KLFn+34 /6l53MyidaFgKaWWMPIrIeL+ceBqHFEK46xzWBGc0DzfH6kcKso4upj8QK5Hi/JeJbOnv5kc31M1 S2t33vul1uAQb9V10FgnetJD7vcNzFcMxwTJ+QBNjtVTAHPE5bgebRcHkaBs8pcGwPXk/GFBUzqh mb80JjU14cxn2Cot64zYVDcjbVOfAMFJQlT+Lc7Q4ySgksfgHWBkT1+epDGquLIvwYIRGSf8GUr2 vwZT5riY9N+PYywSuJQepHlQ9XnwuCmPrMn3dmqgm8S3DuddGDIEBZs4QRjhh/msi83RUEGTfjqp ZbX2jS0scT+/qebnkbnKYCVxKtVGqFe+JaG7l9ThAu6yVidZwQThqyf4pzuTTmdGxB1j2p0g32Zv cl7Q8VMY/xezoB4TWNznylFlwi+NLzUmOuf/ev0AdMDPO6Cv2W2EgEg2qp2kyCb4fHMSuTo3FG6f xf5po3uWh1r8BPpksHHCavmcYqZjzm2d42bWjJQuKz95vL4Ahho4f/sYnsatyqFkIIOWOaKmdKdD OorDhKzeQsp7KjYYPvaudMWUrcDjwbtIqbw5UIIUfOCWQ0une3M4Xr3ubP2Lp/jgcdGpFHT40qWx QfTyuXYiiSoAKx6yP2MRF6ZOa/uSwao9wHn/RlHsbv8apVoX/Z93xw2eQ+hWn13OwhLxtN3tSZgl +kOehGvdDvHeoJ0AuhGZysFA32SZTrNZ1UoDjL8eiXOd3eKVq/YKemRva/Nwn5GsNXaoaiKVA3q+ qMsDjR7dTy+mg8H0L4j3E7PElKkgSJwEiHBx789dOriIGTAm20XtIUAB2wsOTCpSwgxobAvBwhZS 7i1J0OzaH8RpoLbyQBcRuQdIDsBZ8hRT3XMj9fcSLenIEIBFMjtpn+DQWuGyWUst+e90Gk48jYvL 4mbYIjg70zAjISyJfXftQNKLcXRKtvZOcc9ATC+LZXH9BBZX603fd6L1vU0m/j33+2jYHCXStfCi Exa4O3zuW1LUc7iBTkEAwRfdW4hlTEm5hi+YpaoxTAHQ29PscLCq1moNhNOSz4jegFb5R23peh1+ 1Mc8sW3oNMrEkm3N87jBmNWnQXi+KpkMg2m3LNVi6nH9rC+rp9PzI4IwAuobcYv1dJWzhKNMSJiH dZeBEZJpnmbvGD0x3wFu7IRuYaKVpyRJYtTNxySb8mRInKXH5rJdx8+c5Cf4hjBaukiW/mYIEwlL DqLFbDb4pErJqeDrR92U8ATL0+tZ52WSnmHuxjQNM4lKCYe+lGX5DlRJpsm+fmjoGXp19d4/GjD/ D8hdGqCR5ho5fgPduCjp+6apoEtYy4UVY9Cgxpegtj40oFPHeuRL/ObrAj2teF5UFpeX6JcGfTfG FAXGDzsMbczRgR55jkG3MYgEjAFWQ5rTc0KeUVHDVjgL3tfilwU1zov6U0O7Fb8RScXt0D6WbBCZ F+mjCmTOph9RaMZkzie9t0cHNLwpt/HL5ayk5CegzAtWAPDfB9LpNJxes0jOtkYPnH3+LcB0GiDR WPsoI0XxK+WvbI76dsFQLREWXZ4zVeb5sgvl96XA7EUSARDWc7BmQJgENExY+3w96X+m4PVGVNlI dA34RKAs9wwdWqS8XvTeUQG/L1sZeSkAKlnXr8IIGAmXivOi3tkBHjm+QO47lpCt4VlBDjuU+lIf GYYijvjEUD3ALpEZ+ijKLMdcn/L3utHfD4tNKFpbCoCmA/JKtriDo5tf2mG/cZSGCxtYr4Ub2LDs VZZ8vSFdSSgsr2utAaVHEa3/QLHyLZL78Ukh3RNQfqHSdJzWHAUYEgXBxL7rf8ir74+Ryb85tjXa 4DYujWcrq++ho3P6tmViaRYN3bz4kT5hZGHdfm0PJfXX6U8cS42SW4Hzc7duqDb4DyQ1x7FT5PlP 4gvj9z3T0TwsNSvUQeu/bD/XhPuPAbBYAdEWpf+dPgjWlaHEoppGiWr9ZUBDwqOiqkE1vbQbnsj2 9KRU0uD1itKy/LWANV/sadZNhE3L1anudWw+lU50EHobreG1PN9lpGuujES0R67vKVX3TtbQee1K aEJMWlWNq4tsZYoWTugAAIPoz/l3DQIrZTNZcwBjsvCsMqOQJBr2BpLU6QEbfWQ+cOjMpt/00sd4 3nP/XuoeMq2WBsAbSI7Zp6JKfDfQkhV/B3DJO68T9XOo9pjz3A6IJWUDv8t7k4D3vpMuHbRXU4U2 UCZNUWOnwZfcp/NsTopDP/BYKsH81FeKYAll5F3FyGG6AI14WWR1ebV+cGR+8WhCGQQ9nffWXFX1 S25N7XsikK2aCsby5+Sw7tEbIf3w7CCdr3Iz8wG2L+sRMmoa/ExcGc122jKOtv7pNrFGQjmiBB6b ODmbgFZ1l2WT/6ua3m/x6gz6hnOLvc+BUuPeGSCjlxKKRecog4618X13pYlBNUoZl1ZW+kNYERb0 B4w4gX/y+IfN8vW1o9tL5ZSp5r3oaeNBQKwobf5U++co+WtkrcO0QlLhFgXjbzlEIIIoImg2IEIz GdDhsI24uZiwOw5vmr8XmpKh6gi3VcGcC0mrdsaLcuWomPRYOuaf3T3y05uaBxD2h6/1w3kk4m4k hI3JdX1XVyHK6+yZizeLOXT0gQIGvHy+TH7RDZX132pIKvehmGoweTRCsBZFtgPk4LoYr0TE+aJh J3qMjeIKCbRgg0uG5w5NKd5qDwRlOM50cQ/kWecGu5cgDTNM111HAm52nXiajwCLOdjBrjCSfyQX PZM69ljcwuOb7B3tCcphs72exGT7ZlKpBRXC7GZEudV0KvRLon6NLWsoo0T2nl/Hi1KpVMKvPlXE ZNj5qA/HV9Fp2kn/0c87piznKbkC/kBNf2do72bkNz5xovSlH32U/eaoUPebNdYezk8jY5BCWcT8 xVNTAblRFhHzD+H3BeoajVHcrnVi/xe8FMOK9aid94spvPQbrH9zZF+bZ6REbwAVjpiVTAXfZOUk 15Dk166m99NaPci3yBiyUrZWRN+dPWgJs02oGh1aWX/oAP2TjxlQQXhbOXXmWFOqfOw7kaCKJy6d ZE71X4ADaOIUSM75nsRWbDQ4xEE2mfokDzoeAmYsk6CIbWyjT3aY4uH3WhGTEVYb9jnj1B0Z0bNg XA4wVOW3Mjb4XKzUnlSGbjkbzaPnIVxyWV1j/zSN0XLOSxWUGd4tY/iMGtcDcfsZoriPN1wGZPbZ 88AKx6KWD6wg2uY4AUsenhKtZ78ax0g1ZjMat0lpWdZK96Ko8n5g4PnDzuwYs11dS8liSChT1XCp tU7fwOFin+OCKgSLXPX3ifWUrl+K2IuI4hlKWDiQsVejXuHP6N55dUTs+UROG2FfFoyY0iKnOw/V Obu02CxMVAiX6IQDn54CVO1HIXByxCc5vmwRqsyOhIcM9LsNpMAX/WQpjGOMqK2ttfUBT73jkEUU hlkAmbk1MTLGl2rRhyoBkzNxBSwXFFNB6+tz37yQbpdffOEcmBE0+JhzZq4Bw6VUo3FtK3wB09o6 Smr/B9KEr4Cd8EhzcqFtMoXyAQiCNsz3hJdLTuFLZy4EyW7/zxv9ojpacKEAFNHkzfpJ1zIuWzvL mhgKxDkihVVaxaU0Mgb6UDsdY7nq6quSWCMLEDBuzAPU615mnH9ESd1UOAmj9RX885okwZO76bJp z8ZITAvTrAHo1nBStOd04sReRhIGJGzAcO4E/tDjZyozccs5pVrs8ll85WsWd5Nw7ZlXqiLOYMNn iPAnX+qQhCQh4oHKokdYWWwJQip/31D7eSt5zJ9MNSNJ8k1qMPqzfjpWEDzwoe+DNowPgtFqJH8+ hB+4gjI6W9Gxg/SSWaPc5pW6McTxbI4QvU7QGe2uUtNBt4dY7w0NS03Oigwc8xNSJY0yX2pBQWko Eszvd/EAskodwoAPjxcl+JQXyE93QfuwHnh61xizcz/xUrV23gzVQ2wdPD92+bQPBAEm3R+3rdYS P/Rtxrl901DSXmGCd3xJdeLrN8dFsoUhCVtmLIDq28eSugk2G55RG23wCsMuU28+Z57ULF/yPatg HnfzbBcBbOf+FJLt9Gh0Oc/OlzXEgUTciD19ks5h3sRp2y9ku60biZ05IYibMhNXIJymcxsuuxZE n5hc6aW+gb+Hrxd3PVxHT+uEXq2ueMrU3gQqAa3Qk5ncshkDwLqyK52bgiEvrw2xGLt4WhvsoMBK 4PVcLBZjQxfIt0ney+lPU0tExKf1CrUFmB1uuY9voQMZ4ai9J41cV75WK+JWBNv/64/PelCzmwPl W9quKwHiB6pytUfzjBDL3iHTFY19Wfs/GKEBOU4xa5zrJulrJF3/z+GcdSDd1oOKBfS6FmMtFyOd l6FfjDY0cHVA2du1zo3jUinYGT4TkhUXZjoiwbxG7/FxvBnE3AFYdvlGcTBf2BNrtTegCp2qsPev 8If1J/6/DYPoBiYSLiHafDW+l2/t4z7HL54IKJH/QQ6HqpJTwlZSbPPEToODnkJUbkDOnIJrCIjB 1B6mT6ieB03qmkM4ZktF9JsuCqDMUXZ3q7DVddpRAf9Edm006FmH4y/ypwyacjFYUivJz/aNleXw u165s7OPlb1stXR8rmHGyWpUz8Q1X3PImWkbtAKEWcXQ346HvF3vouFY6CT14VUo37iwGBGoj8NS jOpJgXCRVpyeMIy08H7BWKoZ58h5EKXFERLsqvlAlSQJiVkZEYfC8S7DjBzKWm0GJ17KN/Zg6PWg 9s8bZjWuMTFWwVMFWqhLS5XaIRG2nVzv0AgVqGRo9yOc6QUe8h91OIuAgMSCNC/wyOMXcuBkHX3r FKkJjoi3d7K0JVb4LcBR6hs99rHNVWebEg9BbBusBSKcYGTkmqo+rP0TLAc8Lm8G/ZwMcbvVZDo1 QOURJqcyRl0Q771LlHpKcMqQRAqSuZB2/X+wrBKCrL72WfSpzuDgu6y9wepavvmOF3aJWMEi6kgq s8yxzOGGL3PNPHViq81ThEmEVxV720n/vtmBUQac6xUkUTfO+xr7VQr16aaaaQCTFgwjNPcGOojT HlEzFO7tlub5cWLqLe5AQ/OpF2tcrCrhalC1O+xFUJk2IstNyuyKhaMa+6AYttq/150RH6gr1m3n bSj8v+Ji7vSMKH4kOEBM6m9ByoMqqda+2JGe1GTKKxypf2DIkLOG72CNUMWhXW1VUIHf0hisw2wq d2YyrPIcEYyZcR7A7+8drqhlPWZkhz+Mz2iK89He+ABgA4s7n8Whzd0kakdVLan2JCGMiiHZUbyB w7NAT6kzBnIyphhAuNHx5qTO `protect end_protected

mit

e3cdccc37a4e7b5225bcb3fe6cc14865

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_8Stations_2AXI_2TAGM.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

391e30b01ba5349a04808465ff7365c7

preusser/q27

src/vhdl/top/xilinx/sdrc_queens_slave.vhdl

library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.physical.all; entity sdrc_queens_slave is generic ( -- Design Parameters N : positive := 27; L : positive := 2; SOLVERS : positive := 90; COUNT_CYCLES : boolean := false; -- Local Clock Parameters CLK_FREQ : FREQ := 16 MHz; -- external clock CLK_MUL : positive := 31; -- computation clock: CLK_DIV : positive := 4 -- CLK_FREQ / CLK_DIV * CLK_MUL ); port ( --------------------------------------------------------------------------- -- 16-MHz Input Clock CLK16_U : in std_logic; --------------------------------------------------------------------------- -- Ring Bus -- Input BUS_IN_CLKP : in std_logic; BUS_IN_CLKN : in std_logic; BUS_IN_PRE_DAT : in std_logic_vector(8 downto 0); BUS_IN_PRE_PUT : in std_logic; BUS_IN_PRE_GO : out std_logic; BUS_IN_SOL_DAT : in std_logic_vector(8 downto 0); BUS_IN_SOL_PUT : in std_logic; BUS_IN_SOL_GO : out std_logic; -- Output BUS_OUT_CLKP : out std_logic; BUS_OUT_CLKN : out std_logic; BUS_OUT_PRE_DAT : out std_logic_vector(8 downto 0); BUS_OUT_PRE_PUT : out std_logic; BUS_OUT_PRE_GO : in std_logic; BUS_OUT_SOL_DAT : out std_logic_vector(8 downto 0); BUS_OUT_SOL_PUT : out std_logic; BUS_OUT_SOL_GO : in std_logic; --------------------------------------------------------------------------- -- State led : out std_logic_vector(3 downto 0) ); end sdrc_queens_slave; library IEEE; use IEEE.numeric_std.all; library PoC; use PoC.utils.all; use PoC.fifo.all; library UNISIM; use UNISIM.vcomponents.all; architecture rtl of sdrc_queens_slave is -- Bit Length of Pre-Placement constant PRE_BITS : positive := 4*L*log2ceil(N)-1; constant PRE_BYTES : positive := (PRE_BITS+7)/8; -- FIFO Dimensioning constant FIFO_DEPTH : positive := 5*(SOLVERS+5); ---------------------------------------------------------------------------- -- Global Control: Clocks and Resets signal clk_comp : std_logic; -- Computation Clock signal rst_comp : std_logic; signal clk_out : std_logic; -- Communication Clock (Output Side) signal rst_out : std_logic; ----------------------------------------------------------------------------- -- Solver Chain Connectivity signal piful : std_logic; signal pidat : byte; signal pieof : std_logic; signal piput : std_logic; signal sivld : std_logic; signal sidat : byte; signal sieof : std_logic; signal sigot : std_logic; signal poful : std_logic; signal podat : byte; signal poeof : std_logic; signal poput : std_logic; signal sovld : std_logic; signal sodat : byte; signal soeof : std_logic; signal sogot : std_logic; begin ---------------------------------------------------------------------------- -- Clock Generation blkClock: block -- Intermediate Clock Signals signal clk16 : std_logic; -- Buffered Input Clock signal clk_comp_u : std_logic; signal locked_comp : std_logic; begin -- 16 MHz Board Clock -> Computation Clock clk16_buf : IBUFG port map ( I => CLK16_U, O => clk16 ); DCM0 : DCM_BASE generic map ( CLKIN_PERIOD => to_real(1.0/CLK_FREQ, 1 ns), CLKIN_DIVIDE_BY_2 => FALSE, PHASE_SHIFT => 0, CLKFX_MULTIPLY => CLK_MUL, CLKFX_DIVIDE => CLK_DIV, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "NONE", -- only using clkfx DLL_FREQUENCY_MODE => "LOW", DFS_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, STARTUP_WAIT => TRUE, DCM_AUTOCALIBRATION => FALSE ) port map ( CLKIN => clk16, CLKFB => '0', RST => '0', CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => clk_comp_u, CLKFX180 => open, LOCKED => locked_comp ); clk_comp_buf : BUFGCE port map ( CE => locked_comp, I => clk_comp_u, O => clk_comp ); rst_comp <= '0'; clk_out_buf : BUFGCE port map ( CE => locked_comp, I => clk16, O => clk_out ); rst_out <= '0'; led(0) <= locked_comp; end block blkClock; --------------------------------------------------------------------------- -- Solver Chain blkChain: block is signal pful : std_logic; signal pdat : byte; signal peof : std_logic; signal pput : std_logic; begin chain: entity work.queens_chain generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES ) port map ( clk => clk_comp, rst => rst_comp, piful => piful, pidat => pidat, pieof => pieof, piput => piput, sivld => '0', sidat => (others => '-'), sieof => '-', sigot => open, poful => pful, podat => pdat, poeof => peof, poput => pput, sovld => sovld, sodat => sodat, soeof => soeof, sogot => sogot ); -- Resync stream so that frames are taken out in one piece sync: entity work.msg_tap generic map ( D => PRE_BYTES ) port map ( clk => clk_comp, rst => rst_comp, iful => pful, idat => pdat, ieof => peof, iput => pput, oful => poful, odat => podat, oeof => poeof, oput => poput, tful => '1', tdat => open, tput => open ); end block blkChain; ----------------------------------------------------------------------------- -- Input Stream -> feeds pi(ful|dat|eof|put) and si(vld|dat|eof|got) blkInput: block -- Source synchronous clock domain signal clk_in : std_logic; signal rst_in : std_logic; -- Incoming Bus Data Capture Registers signal InPreDat : std_logic_vector(8 downto 0) := (others => '-'); signal InPrePut : std_logic := '0'; signal InPreCap : std_logic_vector(1 downto 0); signal InSolDat : std_logic_vector(8 downto 0) := (others => '-'); signal InSolPut : std_logic := '0'; signal InSolCap : std_logic_vector(1 downto 0); signal pivld : std_logic; begin --------------------------------------------------------------------------- -- Reading the Bus -- Clock reconstruction blkClock : block signal clk_in0 : std_logic; begin IBUFGDS_inst : IBUFGDS port map ( O => clk_in0, I => BUS_IN_CLKP, IB => BUS_IN_CLKN ); BUFG_inst : BUFR port map ( I => clk_in0, O => clk_in, CE => '1', CLR => '0' ); rst_in <= '0'; end block blkClock; -- Bus Input Capture process(clk_in) begin if rising_edge(clk_in) then if rst_in = '1' then InPreDat <= (others => '-'); InPrePut <= '0'; InSolDat <= (others => '-'); InSolPut <= '0'; else InPreDat <= BUS_IN_PRE_DAT; InPrePut <= BUS_IN_PRE_PUT; InSolDat <= BUS_IN_SOL_DAT; InSolPut <= BUS_IN_SOL_PUT; end if; end if; end process; -- Input FIFO (ic): Pre-Placements buf_pre : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64, ESTATE_WR_BITS => InPreCap'length ) port map ( clk_wr => clk_in, rst_wr => rst_in, put => InPrePut, din => InPreDat, full => open, estate_wr => InPreCap, clk_rd => clk_comp, rst_rd => rst_comp, got => piput, dout(8) => pieof, dout(7 downto 0) => pidat, valid => pivld ); piput <= pivld and not piful; BUS_IN_PRE_GO <= '0' when InPreCap = (InPreCap'range => '0') else '1'; -- Input FIFO (ic): Solutions buf_sol : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64, ESTATE_WR_BITS => InSolCap'length ) port map ( clk_wr => clk_in, rst_wr => rst_in, put => InSolPut, din => InSolDat, full => open, estate_wr => InSolCap, clk_rd => clk_out, rst_rd => rst_out, got => sigot, dout(8) => sieof, dout(7 downto 0) => sidat, valid => sivld ); BUS_IN_SOL_GO <= '0' when InSolCap = (InSolCap'range => '0') else '1'; end block blkInput; blkOutput : block begin ------------------------------------------------------------------------- -- Output Inverted Clock blkClock : block signal clk_inv : std_logic; begin invert : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '1', SRTYPE => "SYNC" ) port map ( Q => clk_inv, -- 1-bit DDR output C => clk_out, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D1 => '0', -- 1-bit data input (positive edge) D2 => '1', -- 1-bit data input (negative edge) R => rst_out, -- 1-bit reset input S => '0' -- 1-bit set input ); OBUFDS_inst : OBUFDS generic map ( IOSTANDARD => "DEFAULT", SLEW => "FAST" ) port map ( O => BUS_OUT_CLKP, OB => BUS_OUT_CLKN, I => clk_inv ); end block blkClock; blkPre: block -- Syncing the go input signal go_s : std_logic_vector(1 downto 0) := (others => '0'); -- Output FIFO signal pgot : std_logic; signal pdat : std_logic_vector(8 downto 0); signal pvld : std_logic; -- Outgoing Output Registers signal PreOutDat : std_logic_vector(8 downto 0) := (others => '0'); signal PreOutPut : std_logic := '0'; begin -- Syncing go input process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then go_s <= (others => '0'); else go_s <= BUS_OUT_PRE_GO & go_s(go_s'left downto 1); end if; end if; end process; -- Output FIFO (ic): Pre-Placements fifob : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64 ) port map ( clk_wr => clk_comp, rst_wr => rst_comp, put => poput, din(8) => poeof, din(7 downto 0) => podat, full => poful, clk_rd => clk_out, rst_rd => rst_out, got => pgot, dout => pdat, valid => pvld ); pgot <= pvld and go_s(0); -- Output Registers process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then PreOutDat <= (others => '0'); PreOutPut <= '0'; else PreOutDat <= pdat; PreOutPut <= pgot; end if; end if; end process; BUS_OUT_PRE_DAT <= PreOutDat; BUS_OUT_PRE_PUT <= PreOutPut; end block blkPre; blkSol: block -- Syncing the go input signal go_s : std_logic_vector(1 downto 0) := (others => '0'); -- Chain -> fifo_ic [clk_comp->clk_out] signal soful : std_logic; -- fifo_ic -> funnel signal scvld : std_logic; signal scdat : std_logic_vector(8 downto 0); signal scgot : std_logic; -- funnel -> fifo_glue signal sjful : std_logic; signal sjdat : std_logic_vector(8 downto 0); signal sjput : std_logic; -- fifo_glue -> output signal sfvld : std_logic; signal sfdat : std_logic_vector(8 downto 0); signal sfgot : std_logic; -- Outgoing Output Registers signal SolOutDat : std_logic_vector(8 downto 0) := (others => '0'); signal SolOutPut : std_logic := '0'; begin -- Syncing go input process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then go_s <= (others => '0'); else go_s <= BUS_OUT_SOL_GO & go_s(go_s'left downto 1); end if; end if; end process; -- fifo_ic: clk_comp -> clk_out fifob : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64 ) port map ( clk_wr => clk_comp, rst_wr => rst_comp, put => sogot, din(8) => soeof, din(7 downto 0) => sodat, full => soful, clk_rd => clk_out, rst_rd => rst_out, got => scgot, dout => scdat, valid => scvld ); sogot <= sovld and not soful; -- funnel: si* + sc* -> sj* join: entity work.msg_funnel generic map ( N => 2 ) port map ( clk => clk_out, rst => rst_out, ivld(0) => scvld, ivld(1) => sivld, idat(0) => scdat(7 downto 0), idat(1) => sidat, ieof(0) => scdat(8), ieof(1) => sieof, igot(0) => scgot, igot(1) => sigot, oful => sjful, odat => sjdat(7 downto 0), oeof => sjdat(8), oput => sjput ); -- fifo_glue glue: fifo_glue generic map ( D_BITS => 9 ) port map ( clk => clk_out, rst => rst_out, put => sjput, di => sjdat, ful => sjful, vld => sfvld, do => sfdat, got => sfgot ); sfgot <= sfvld and go_s(0); -- Output Registers process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then SolOutDat <= (others => '0'); SolOutPut <= '0'; else SolOutDat <= sfdat; SolOutPut <= sfgot; end if; end if; end process; BUS_OUT_SOL_DAT <= SolOutDat; BUS_OUT_SOL_PUT <= SolOutPut; end block blkSol; end block blkOutput; led(3 downto 1) <= "110"; end rtl;

agpl-3.0

1848736eda8be8885aba133032388745

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_8Stations_2AXI_2TAGM_2CACHE_W.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

25ce6ba1b8a3fd491498cbf78c9f55cb

jpidancet/mips

rtl/cpu_fetch.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; entity cpu_fetch is port (pc : in std_logic_vector(31 downto 0); pcbranch : in std_logic_vector(31 downto 0); pcsrc : in std_logic; instr_n : out std_logic_vector(31 downto 0); pcplus4_n : out std_logic_vector(31 downto 0); pc_n : out std_logic_vector(31 downto 0); imem_addr : out std_logic_vector(31 downto 0); imem_data : in std_logic_vector(31 downto 0)); end entity cpu_fetch; architecture rtl of cpu_fetch is signal pcplus4 : std_logic_vector(31 downto 0); begin pcplus4 <= pc + 4; instr_n <= imem_data; imem_addr <= pc; pcplus4_n <= pcplus4; pc_n <= pcbranch when pcsrc = '1' else pcplus4; end architecture rtl;

isc

5f92024a3d2040be6f70c0612b028cda

wltr/cern-fgclite

critical_fpga/src/rtl/cf/fetch_page/fetch_page_ow.vhd

------------------------------------------------------------------------------- --! @file fetch_page_ow.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-11-19 --! @brief Prepare one-wire page for NanoFIP communication. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; --! @brief Entity declaration of fetch_page_ow --! @details --! This component prepares the one-wire page for the NanoFIP response. entity fetch_page_ow is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Commands --! @{ --! Start flag start_i : in std_ulogic; --! Done flag done_o : out std_ulogic; --! Memory index idx_i : in std_ulogic_vector(14 downto 0); --! @} --! @name Memory page interface --! @{ --! Address page_addr_o : out std_ulogic_vector(5 downto 0); --! Write enable page_wr_en_o : out std_ulogic; --! Data output page_data_o : out std_ulogic_vector(7 downto 0); --! Done flag page_done_i : in std_ulogic; --! @} --! @name One-wire data --! @{ --! Address ow_addr_o : out std_ulogic_vector(5 downto 0); --! Read enable ow_rd_en_o : out std_ulogic; --! Data input ow_data_i : in std_ulogic_vector(79 downto 0); --! Data input enable ow_data_en_i : in std_ulogic); --! @} end entity fetch_page_ow; --! RTL implementation of fetch_page_ow architecture rtl of fetch_page_ow is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ type state_t is (IDLE, STORE, DONE); type reg_t is record state : state_t; addr : unsigned(5 downto 0); data : std_ulogic_vector(79 downto 0); wr_en : std_ulogic; rd_en : std_ulogic; done : std_ulogic; end record; constant init_c : reg_t := ( state => IDLE, addr => (others => '0'), data => (others => '0'), wr_en => '0', rd_en => '0', done => '0'); --! @} --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal reg : reg_t; --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal next_reg : reg_t; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- page_addr_o <= std_ulogic_vector(reg.addr); page_wr_en_o <= reg.wr_en; page_data_o <= reg.data(7 downto 0); ow_addr_o <= idx_i(3 downto 0) & std_ulogic_vector(reg.addr(5 downto 4)); ow_rd_en_o <= reg.rd_en; done_o <= reg.done; --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin reg <= init_c; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else reg <= next_reg; end if; end if; end process regs; --------------------------------------------------------------------------- -- Combinatorics --------------------------------------------------------------------------- comb : process (reg, start_i, page_done_i, ow_data_i, ow_data_en_i) is begin -- comb -- Defaults next_reg <= reg; next_reg.rd_en <= '0'; next_reg.wr_en <= '0'; next_reg.done <= '0'; case reg.state is when IDLE => if start_i = '1' then next_reg.rd_en <= '1'; next_reg.state <= STORE; end if; when STORE => if ow_data_en_i = '1' then next_reg.data <= ow_data_i; next_reg.wr_en <= '1'; next_reg.state <= DONE; end if; when DONE => if page_done_i = '1' then if to_integer(reg.addr) < 63 then next_reg.addr <= reg.addr + 1; if to_integer(reg.addr(3 downto 0)) < 15 then next_reg.wr_en <= '1'; next_reg.data <= x"00" & reg.data(reg.data'high downto reg.data'low + 8); else next_reg.rd_en <= '1'; next_reg.state <= STORE; end if; else next_reg <= init_c; next_reg.done <= '1'; end if; end if; end case; end process comb; end architecture rtl;

mit

b0d1cb7bcf989dbe7556bdb8ffc3afe3

preusser/q27

src/vhdl/PoC/common/strings.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann -- -- Package: String related functions and types -- -- Description: -- ------------------------------------- -- For detailed documentation see below. -- -- License: -- ============================================================================= -- Copyright 2007-2015 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.math_real.all; library PoC; use PoC.config.all; use PoC.utils.all; --use PoC.FileIO.all; package strings is -- default fill and string termination character for fixed size strings -- =========================================================================== -- WORKAROUND: for Altera Quartus-II -- Version: 15.0 -- Issue: -- character 0 (NUL) causes Quartus-II to crash, if uses to pad STRINGs -- characters < 32 (control characters) are not supported in Quartus-II -- characters > 127 are not supported in VHDL files (strict ASCII files) -- character 255 craches ISE log window (created by 'CHARACTER'val(255)') -- Solution: -- PoC uses backtick "`" as a fill and termination symbol, if a Quartus-II -- synthesis environment is detected. constant C_POC_NUL : character := ite((SYNTHESIS_TOOL /= SYNTHESIS_TOOL_ALTERA_QUARTUS2), NUL, '`'); -- Type declarations -- =========================================================================== subtype T_RAWCHAR is std_logic_vector(7 downto 0); type T_RAWSTRING is array (natural range <>) of T_RAWCHAR; -- testing area: -- =========================================================================== function to_IPStyle(str : string) return T_IPSTYLE; -- to_char function to_char(Value : std_logic) return character; function to_char(rawchar : T_RAWCHAR) return character; function to_HexChar(Value : natural) return character; function to_HexChar(Value : unsigned) return character; -- chr_is* function function chr_isDigit(chr : character) return boolean; function chr_isLowerHexDigit(chr : character) return boolean; function chr_isUpperHexDigit(chr : character) return boolean; function chr_isHexDigit(chr : character) return boolean; function chr_isLower(chr : character) return boolean; function chr_isLowerAlpha(chr : character) return boolean; function chr_isUpper(chr : character) return boolean; function chr_isUpperAlpha(chr : character) return boolean; function chr_isAlpha(chr : character) return boolean; -- raw_format_* functions function raw_format_bool_bin(Value : boolean) return string; function raw_format_bool_chr(Value : boolean) return string; function raw_format_bool_str(Value : boolean) return string; function raw_format_slv_bin(slv : std_logic_vector) return string; function raw_format_slv_oct(slv : std_logic_vector) return string; function raw_format_slv_dec(slv : std_logic_vector) return string; function raw_format_slv_hex(slv : std_logic_vector) return string; function raw_format_nat_bin(Value : natural) return string; function raw_format_nat_oct(Value : natural) return string; function raw_format_nat_dec(Value : natural) return string; function raw_format_nat_hex(Value : natural) return string; -- str_format_* functions function str_format(Value : REAL; precision : natural := 3) return string; -- to_string function to_string(Value : boolean) return string; function to_string(Value : integer; base : positive := 10) return string; function to_string(slv : std_logic_vector; format : character; Length : natural := 0; fill : character := '0') return string; function to_string(rawstring : T_RAWSTRING) return string; function to_string(Value : T_BCD_VECTOR) return string; -- to_slv function to_slv(rawstring : T_RAWSTRING) return std_logic_vector; -- digit subtypes incl. error Value (-1) subtype T_DIGIT_BIN is integer range -1 to 1; subtype T_DIGIT_OCT is integer range -1 to 7; subtype T_DIGIT_DEC is integer range -1 to 9; subtype T_DIGIT_HEX is integer range -1 to 15; -- to_digit* function to_digit_bin(chr : character) return T_DIGIT_BIN; function to_digit_oct(chr : character) return T_DIGIT_OCT; function to_digit_dec(chr : character) return T_DIGIT_DEC; function to_digit_hex(chr : character) return T_DIGIT_HEX; function to_digit(chr : character; base : character := 'd') return integer; -- to_natural* function to_natural_bin(str : string) return integer; function to_natural_oct(str : string) return integer; function to_natural_dec(str : string) return integer; function to_natural_hex(str : string) return integer; function to_natural(str : string; base : character := 'd') return integer; -- to_raw* function to_RawChar(char : character) return T_RAWCHAR; function to_RawString(str : string) return T_RAWSTRING; -- resize function resize(str : string; size : positive; FillChar : character := C_POC_NUL) return string; -- function resize(rawstr : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING; -- Character functions function chr_toLower(chr : character) return character; function chr_toUpper(chr : character) return character; -- String functions function str_length(str : string) return natural; function str_equal(str1 : string; str2 : string) return boolean; function str_match(str1 : string; str2 : string) return boolean; function str_imatch(str1 : string; str2 : string) return boolean; function str_pos(str : string; chr : character; start : natural := 0) return integer; function str_pos(str : string; pattern : string; start : natural := 0) return integer; function str_ipos(str : string; chr : character; start : natural := 0) return integer; function str_ipos(str : string; pattern : string; start : natural := 0) return integer; function str_find(str : string; chr : character) return boolean; function str_find(str : string; pattern : string) return boolean; function str_ifind(str : string; chr : character) return boolean; function str_ifind(str : string; pattern : string) return boolean; function str_replace(str : string; pattern : string; replace : string) return string; function str_substr(str : string; start : integer := 0; Length : integer := 0) return string; function str_ltrim(str : string; char : character := ' ') return string; function str_rtrim(str : string; char : character := ' ') return string; function str_trim(str : string) return string; function str_calign(str : string; Length : natural; FillChar : character := ' ') return string; function str_lalign(str : string; Length : natural; FillChar : character := ' ') return string; function str_ralign(str : string; Length : natural; FillChar : character := ' ') return string; function str_toLower(str : string) return string; function str_toUpper(str : string) return string; end package; package body strings is -- function to_IPStyle(str : string) return T_IPSTYLE is begin for i in T_IPSTYLE'pos(T_IPSTYLE'low) to T_IPSTYLE'pos(T_IPSTYLE'high) loop if str_imatch(str, T_IPSTYLE'image(T_IPSTYLE'val(i))) then return T_IPSTYLE'val(i); end if; end loop; report "Unknown IPStyle: '" & str & "'" severity FAILURE; end function; -- to_char -- =========================================================================== function to_char(Value : std_logic) return character is begin case Value is when 'U' => return 'U'; when 'X' => return 'X'; when '0' => return '0'; when '1' => return '1'; when 'Z' => return 'Z'; when 'W' => return 'W'; when 'L' => return 'L'; when 'H' => return 'H'; when '-' => return '-'; when others => return 'X'; end case; end function; function to_char(rawchar : T_RAWCHAR) return character is begin return character'val(to_integer(unsigned(rawchar))); end function; -- function to_HexChar(Value : natural) return character is constant HEX : string := "0123456789ABCDEF"; begin return ite(Value < 16, HEX(Value+1), 'X'); end function; function to_HexChar(Value : unsigned) return character is begin return to_HexChar(to_integer(Value)); end function; -- chr_is* function function chr_isDigit(chr : character) return boolean is begin return (character'pos('0') <= character'pos(chr)) and (character'pos(chr) <= character'pos('9')); end function; function chr_isLowerHexDigit(chr : character) return boolean is begin return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('f')); end function; function chr_isUpperHexDigit(chr : character) return boolean is begin return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('F')); end function; function chr_isHexDigit(chr : character) return boolean is begin return chr_isDigit(chr) or chr_isLowerHexDigit(chr) or chr_isUpperHexDigit(chr); end function; function chr_isLower(chr : character) return boolean is begin return chr_isLowerAlpha(chr); end function; function chr_isLowerAlpha(chr : character) return boolean is begin return (character'pos('a') <= character'pos(chr)) and (character'pos(chr) <= character'pos('z')); end function; function chr_isUpper(chr : character) return boolean is begin return chr_isUpperAlpha(chr); end function; function chr_isUpperAlpha(chr : character) return boolean is begin return (character'pos('A') <= character'pos(chr)) and (character'pos(chr) <= character'pos('Z')); end function; function chr_isAlpha(chr : character) return boolean is begin return chr_isLowerAlpha(chr) or chr_isUpperAlpha(chr); end function; -- raw_format_* functions -- =========================================================================== function raw_format_bool_bin(Value : boolean) return string is begin return ite(Value, "1", "0"); end function; function raw_format_bool_chr(Value : boolean) return string is begin return ite(Value, "T", "F"); end function; function raw_format_bool_str(Value : boolean) return string is begin return str_toUpper(boolean'image(Value)); end function; function raw_format_slv_bin(slv : std_logic_vector) return string is variable Value : std_logic_vector(slv'length - 1 downto 0); variable Result : string(1 to slv'length); variable j : natural; begin -- convert input slv to a downto ranged vector and normalize range to slv'low = 0 Value := movez(ite(slv'ascending, descend(slv), slv)); -- convert each bit to a character j := 0; for i in Result'reverse_range loop Result(i) := to_char(Value(j)); j := j + 1; end loop; return Result; end function; function raw_format_slv_oct(slv : std_logic_vector) return string is variable Value : std_logic_vector(slv'length - 1 downto 0); variable Digit : std_logic_vector(2 downto 0); variable Result : string(1 to div_ceil(slv'length, 3)); variable j : natural; begin -- convert input slv to a downto ranged vector; normalize range to slv'low = 0 and resize it to a multiple of 3 Value := resize(movez(ite(slv'ascending, descend(slv), slv)), (Result'length * 3)); -- convert 3 bit to a character j := 0; for i in Result'reverse_range loop Digit := Value((j * 3) + 2 downto (j * 3)); Result(i) := to_HexChar(unsigned(Digit)); j := j + 1; end loop; return Result; end function; function raw_format_slv_dec(slv : std_logic_vector) return string is variable Value : std_logic_vector(slv'length - 1 downto 0); variable Result : string(1 to div_ceil(slv'length, 3)); subtype TT_BCD is integer range 0 to 31; type TT_BCD_VECTOR is array(natural range <>) of TT_BCD; variable Temp : TT_BCD_VECTOR(div_ceil(slv'length, 3) - 1 downto 0); variable Carry : T_UINT_8; variable Pos : natural; begin Temp := (others => 0); Pos := 0; -- convert input slv to a downto ranged vector Value := ite(slv'ascending, descend(slv), slv); for i in Value'range loop Carry := to_int(Value(i)); for j in Temp'reverse_range loop Temp(j) := Temp(j) * 2 + Carry; Carry := to_int(Temp(j) > 9); Temp(j) := Temp(j) - to_int((Temp(j) > 9), 0, 10); end loop; end loop; for i in Result'range loop Result(i) := to_HexChar(Temp(Temp'high - i + 1)); if ((Result(i) /= '0') and (Pos = 0)) then Pos := i; end if; end loop; -- trim leading zeros, except the last return Result(imin(Pos, Result'high) to Result'high); end function; function raw_format_slv_hex(slv : std_logic_vector) return string is variable Value : std_logic_vector(4*div_ceil(slv'length, 4) - 1 downto 0); variable Digit : std_logic_vector(3 downto 0); variable Result : string(1 to div_ceil(slv'length, 4)); variable j : natural; begin Value := resize(slv, Value'length); j := 0; for i in Result'reverse_range loop Digit := Value((j * 4) + 3 downto (j * 4)); Result(i) := to_HexChar(unsigned(Digit)); j := j + 1; end loop; return Result; end function; function raw_format_nat_bin(Value : natural) return string is begin return raw_format_slv_bin(to_slv(Value, log2ceilnz(Value+1))); end function; function raw_format_nat_oct(Value : natural) return string is begin return raw_format_slv_oct(to_slv(Value, log2ceilnz(Value+1))); end function; function raw_format_nat_dec(Value : natural) return string is begin return integer'image(Value); end function; function raw_format_nat_hex(Value : natural) return string is begin return raw_format_slv_hex(to_slv(Value, log2ceilnz(Value+1))); end function; -- str_format_* functions -- =========================================================================== function str_format(Value : REAL; precision : natural := 3) return string is constant s : REAL := sign(Value); constant val : REAL := Value * s; constant int : integer := integer(floor(val)); constant frac : integer := integer(round((val - real(int)) * 10.0**precision)); constant overflow : boolean := frac >= 10**precision; constant int2 : integer := ite(overflow, int+1, int); constant frac2 : integer := ite(overflow, frac-10**precision, frac); constant frac_str : string := integer'image(frac2); constant res : string := integer'image(int2) & "." & (2 to (precision - frac_str'length + 1) => '0') & frac_str; begin return ite ((s < 0.0), "-" & res, res); end function; -- to_string -- =========================================================================== function to_string(Value : boolean) return string is begin return raw_format_bool_str(Value); end function; -- convert an integer Value to a STRING using an arbitrary base function to_string(Value : integer; base : positive := 10) return string is constant absValue : natural := abs(Value); constant len : positive := log10ceilnz(absValue); variable power : positive; variable Result : string(1 to len); begin power := 1; if (base = 10) then return integer'image(Value); else for i in len downto 1 loop Result(i) := to_HexChar(absValue / power mod base); power := power * base; end loop; if (Value < 0) then return '-' & Result; else return Result; end if; end if; end function; -- QUESTION: rename to slv_format(..) ? function to_string(slv : std_logic_vector; format : character; Length : natural := 0; fill : character := '0') return string is constant int : integer := ite((slv'length <= 31), to_integer(unsigned(resize(slv, 31))), 0); constant str : string := integer'image(int); constant bin_len : positive := slv'length; constant dec_len : positive := str'length;--log10ceilnz(int); constant hex_len : positive := ite(((bin_len mod 4) = 0), (bin_len / 4), (bin_len / 4) + 1); constant len : natural := ite((format = 'b'), bin_len, ite((format = 'd'), dec_len, ite((format = 'h'), hex_len, 0))); variable j : natural; variable Result : string(1 to ite((Length = 0), len, imax(len, Length))); begin j := 0; Result := (others => fill); if (format = 'b') then for i in Result'reverse_range loop Result(i) := to_char(slv(j)); j := j + 1; end loop; elsif (format = 'd') then -- TODO: enable big integer conversion -- if (slv'length < 32) then -- return INTEGER'image(int); -- else -- return raw_format_slv_dec(slv); -- end if; Result(Result'length - str'length + 1 to Result'high) := str; elsif (format = 'h') then for i in Result'reverse_range loop Result(i) := to_HexChar(unsigned(slv((j * 4) + 3 downto (j * 4)))); j := j + 1; end loop; else report "Unknown format character: " & format & "." severity FAILURE; end if; return Result; end function; function to_string(rawstring : T_RAWSTRING) return string is variable Result : string(1 to rawstring'length); begin for i in rawstring'low to rawstring'high loop Result(i - rawstring'low + 1) := to_char(rawstring(i)); end loop; return Result; end function; function to_string(Value : T_BCD_VECTOR) return string is variable Result : string(1 to Value'length); begin for i in Value'range loop Result(Result'high - (i - Value'low)) := to_HexChar(unsigned(Value(i))); end loop; return Result; end function; -- to_slv -- =========================================================================== function to_slv(rawstring : T_RAWSTRING) return std_logic_vector is variable Result : std_logic_vector((rawstring'length * 8) - 1 downto 0); begin for i in rawstring'range loop Result(((i - rawstring'low) * 8) + 7 downto (i - rawstring'low) * 8) := rawstring(i); end loop; return Result; end function; -- to_digit* -- =========================================================================== -- convert a binary digit given as CHARACTER to a digit returned as NATURAL; return -1 on error function to_digit_bin(chr : character) return T_DIGIT_BIN is begin case chr is when '0' => return 0; when '1' => return 1; when others => return -1; end case; end function; -- convert an octal digit given as CHARACTER to a digit returned as NATURAL; return -1 on error function to_digit_oct(chr : character) return T_DIGIT_OCT is variable dec : integer; begin dec := to_digit_dec(chr); return ite((dec < 8), dec, -1); end function; -- convert a adecimal digit given as CHARACTER to a digit returned as NATURAL; return -1 on error function to_digit_dec(chr : character) return T_DIGIT_DEC is begin if chr_isDigit(chr) then return character'pos(chr) - CHARACTER'pos('0'); else return -1; end if; end function; -- convert a hexadecimal digit given as CHARACTER to a digit returned as NATURAL; return -1 on error function to_digit_hex(chr : character) return T_DIGIT_HEX is begin if chr_isDigit(chr) then return character'pos(chr) - CHARACTER'pos('0'); elsif chr_isLowerHexDigit(chr) then return character'pos(chr) - CHARACTER'pos('a') + 10; elsif chr_isUpperHexDigit(chr) then return character'pos(chr) - CHARACTER'pos('A') + 10; else return -1; end if; end function; -- convert a digit given as CHARACTER to a digit returned as NATURAL; return -1 on error function to_digit(chr : character; base : character := 'd') return integer is begin case base is when 'b' => return to_digit_bin(chr); when 'o' => return to_digit_oct(chr); when 'd' => return to_digit_dec(chr); when 'h' => return to_digit_hex(chr); when others => report "Unknown base character: " & base & "." severity FAILURE; end case; -- return statement is explicitly missing otherwise XST won't stop end function; -- to_natural* -- =========================================================================== -- convert a binary number given as STRING to a NATURAL; return -1 on error function to_natural_bin(str : string) return integer is variable Result : natural; variable Digit : integer; begin for i in str'range loop Digit := to_digit_bin(str(i)); if (Digit /= -1) then Result := Result * 2 + Digit; else return -1; end if; end loop; return Result; end function; -- convert an octal number given as STRING to a NATURAL; return -1 on error function to_natural_oct(str : string) return integer is variable Result : natural; variable Digit : integer; begin for i in str'range loop Digit := to_digit_oct(str(i)); if (Digit /= -1) then Result := Result * 8 + Digit; else return -1; end if; end loop; return Result; end function; -- convert a decimal number given as STRING to a NATURAL; return -1 on error function to_natural_dec(str : string) return integer is variable Result : natural; variable Digit : integer; begin -- WORKAROUND: Xilinx Vivado Synth -- Version: 2014.1 -- Issue: -- INTEGER'value(...) is not supported by Vivado Synth -- Solution: -- implement a manual conversion using shift and multiply for i in str'range loop Digit := to_digit_dec(str(i)); if (Digit /= -1) then Result := Result * 10 + Digit; else return -1; end if; end loop; return Result; -- INTEGER'value(str); end function; -- convert a hexadecimal number given as STRING to a NATURAL; return -1 on error function to_natural_hex(str : string) return integer is variable Result : natural; variable Digit : integer; begin for i in str'range loop Digit := to_digit_hex(str(i)); if (Digit /= -1) then Result := Result * 16 + Digit; else return -1; end if; end loop; return Result; end function; -- convert a number given as STRING to a NATURAL; return -1 on error function to_natural(str : string; base : character := 'd') return integer is begin case base is when 'b' => return to_natural_bin(str); when 'o' => return to_natural_oct(str); when 'd' => return to_natural_dec(str); when 'h' => return to_natural_hex(str); when others => report "Unknown base character: " & base & "." severity FAILURE; end case; -- return statement is explicitly missing otherwise XST won't stop end function; -- to_raw* -- =========================================================================== -- convert a CHARACTER to a RAWCHAR function to_RawChar(char : character) return T_RAWCHAR is begin return std_logic_vector(to_unsigned(character'pos(char), T_RAWCHAR'length)); end function; -- convert a STRING to a RAWSTRING function to_RawString(str : string) return T_RAWSTRING is variable Result : T_RAWSTRING(0 to str'length - 1); begin for i in str'low to str'high loop Result(i - str'low) := to_RawChar(str(i)); end loop; return Result; end function; -- resize -- =========================================================================== function resize(str : string; Size : positive; FillChar : character := C_POC_NUL) return string is constant ConstNUL : string(1 to 1) := (others => C_POC_NUL); variable Result : string(1 to Size); begin Result := (others => FillChar); if (str'length > 0) then -- WORKAROUND: for Altera Quartus-II -- Version: 15.0 -- Issue: array bounds are check regardless of the hierarchy and control flow Result(1 to imin(Size, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(Size, str'length)), ConstNUL); end if; return Result; end function; -- function resize(str : T_RAWSTRING; size : POSITIVE; FillChar : T_RAWCHAR := x"00") return T_RAWSTRING is -- constant ConstNUL : T_RAWSTRING(1 to 1) := (others => x"00"); -- variable Result : T_RAWSTRING(1 to size); -- function ifthenelse(cond : BOOLEAN; value1 : T_RAWSTRING; value2 : T_RAWSTRING) return T_RAWSTRING is -- begin -- if cond then -- return value1; -- else -- return value2; -- end if; -- end function; -- begin -- Result := (others => FillChar); -- if (str'length > 0) then -- Result(1 to imin(size, imax(1, str'length))) := ifthenelse((str'length > 0), str(1 to imin(size, str'length)), ConstNUL); -- end if; -- return Result; -- end function; -- Character functions -- =========================================================================== -- convert an upper case CHARACTER into a lower case CHARACTER function chr_toLower(chr : character) return character is begin if chr_isUpperAlpha(chr) then return character'val(character'pos(chr) - character'pos('A') + character'pos('a')); else return chr; end if; end function; -- convert a lower case CHARACTER into an upper case CHARACTER function chr_toUpper(chr : character) return character is begin if chr_isLowerAlpha(chr) then return character'val(character'pos(chr) - character'pos('a') + character'pos('A')); else return chr; end if; end function; -- String functions -- =========================================================================== -- count the length of a POC_NUL terminated STRING function str_length(str : string) return natural is begin for i in str'range loop if (str(i) = C_POC_NUL) then return i - str'low; end if; end loop; return str'length; end function; -- compare two STRINGs for equality -- pre-check the string lengths to suppress warnings for unequal sized string comparisons. -- QUESTION: overload "=" operator? function str_equal(str1 : string; str2 : string) return boolean is begin if str1'length /= str2'length then return FALSE; else return (str1 = str2); end if; end function; -- compare two POC_NUL terminated STRINGs function str_match(str1 : string; str2 : string) return boolean is constant len : natural := imin(str1'length, str2'length); begin -- if both strings are empty if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if; -- compare char by char for i in str1'low to str1'low + len - 1 loop if (str1(i) /= str2(str2'low + (i - str1'low))) then return FALSE; elsif ((str1(i) = C_POC_NUL) xor (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then return FALSE; elsif ((str1(i) = C_POC_NUL) and (str2(str2'low + (i - str1'low)) = C_POC_NUL)) then return TRUE; end if; end loop; -- check special cases, return (((str1'length = len) and (str2'length = len)) or -- both strings are fully consumed and equal ((str1'length > len) and (str1(str1'low + len) = C_POC_NUL)) or -- str1 is longer, but str_length equals len ((str2'length > len) and (str2(str2'low + len) = C_POC_NUL))); -- str2 is longer, but str_length equals len end function; -- compare two POC_NUL terminated STRINGs; case insentitve function str_imatch(str1 : string; str2 : string) return boolean is begin return str_match(str_toLower(str1), str_toLower(str2)); end function; -- search for chr in a STRING and return the position; return -1 on error function str_pos(str : string; chr : character; start : natural := 0) return integer is begin for i in imax(str'low, start) to str'high loop exit when (str(i) = C_POC_NUL); if (str(i) = chr) then return i; end if; end loop; return -1; end function; -- search for pattern in a STRING and return the position; return -1 on error -- QUESTION: implement KMP algorithm? function str_pos(str : string; pattern : string; start : natural := 0) return integer is begin for i in imax(str'low, start) to (str'high - pattern'length + 1) loop exit when (str(i) = C_POC_NUL); if (str(i to i + pattern'length - 1) = pattern) then return i; end if; end loop; return -1; end function; -- search for chr in a STRING and return the position; case insentitve; return -1 on error function str_ipos(str : string; chr : character; start : natural := 0) return integer is begin return str_pos(str_toLower(str), chr_toLower(chr)); end function; -- search for pattern in a STRING and return the position; case insentitve; return -1 on error function str_ipos(str : string; pattern : string; start : natural := 0) return integer is begin return str_pos(str_toLower(str), str_toLower(pattern)); end function; -- function str_pos(str1 : STRING; str2 : STRING) return INTEGER is -- variable PrefixTable : T_INTVEC(0 to str2'length); -- variable j : INTEGER; -- begin -- -- construct prefix table for KMP algorithm -- j := -1; -- PrefixTable(0) := -1; -- for i in str2'range loop -- while ((j >= 0) and str2(j + 1) /= str2(i)) loop -- j := PrefixTable(j); -- end loop; -- -- j := j + 1; -- PrefixTable(i - 1) := j + 1; -- end loop; -- -- -- search pattern str2 in text str1 -- j := 0; -- for i in str1'range loop -- while ((j >= 0) and str1(i) /= str2(j + 1)) loop -- j := PrefixTable(j); -- end loop; -- -- j := j + 1; -- if ((j + 1) = str2'high) then -- return i - str2'length + 1; -- end if; -- end loop; -- -- return -1; -- end function; -- check if chr exists in STRING str function str_find(str : string; chr : character) return boolean is begin return (str_pos(str, chr) > 0); end function; -- check if pattern exists in STRING str function str_find(str : string; pattern : string) return boolean is begin return (str_pos(str, pattern) > 0); end function; -- check if chr exists in STRING str; case insentitve function str_ifind(str : string; chr : character) return boolean is begin return (str_ipos(str, chr) > 0); end function; -- check if pattern exists in STRING str; case insentitve function str_ifind(str : string; pattern : string) return boolean is begin return (str_ipos(str, pattern) > 0); end function; -- replace a pattern in a STRING str by the STRING replace function str_replace(str : string; pattern : string; replace : string) return string is variable pos : integer; begin pos := str_pos(str, pattern); if (pos > 0) then if (pos = 1) then return replace & str(pattern'length + 1 to str'length); elsif (pos = str'length - pattern'length + 1) then return str(1 to str'length - pattern'length) & replace; else return str(1 to pos - 1) & replace & str(pos + pattern'length to str'length); end if; else return str; end if; end function; -- return a sub-string of STRING str -- EXAMPLES: -- 123456789ABC -- input string: "Hello World." -- low=1; high=12; length=12 -- -- str_substr("Hello World.", 0, 0) => "Hello World." - copy all -- str_substr("Hello World.", 7, 0) => "World." - copy from pos 7 to end of string -- str_substr("Hello World.", 7, 5) => "World" - copy from pos 7 for 5 characters -- str_substr("Hello World.", 0, -7) => "Hello World." - copy all until character 8 from right boundary function str_substr(str : string; start : integer := 0; Length : integer := 0) return string is variable StartOfString : positive; variable EndOfString : positive; begin if (start < 0) then -- start is negative -> start substring at right string boundary StartOfString := str'high + start + 1; elsif (start = 0) then -- start is zero -> start substring at left string boundary StartOfString := str'low; else -- start is positive -> start substring at left string boundary + offset StartOfString := start; end if; if (Length < 0) then -- Length is negative -> end substring at length'th character before right string boundary EndOfString := str'high + Length; elsif (Length = 0) then -- Length is zero -> end substring at right string boundary EndOfString := str'high; else -- Length is positive -> end substring at StartOfString + Length EndOfString := StartOfString + Length - 1; end if; if (StartOfString < str'low) then report "StartOfString is out of str's range. (str=" & str & ")" severity FAILURE; end if; if (EndOfString < str'high) then report "EndOfString is out of str's range. (str=" & str & ")" severity FAILURE; end if; return str(StartOfString to EndOfString); end function; -- left-trim the STRING str function str_ltrim(str : string; char : character := ' ') return string is begin for i in str'range loop if (str(i) /= char) then return str(i to str'high); end if; end loop; return ""; end function; -- right-trim the STRING str function str_rtrim(str : string; char : character := ' ') return string is begin for i in str'reverse_range loop if (str(i) /= char) then return str(str'low to i); end if; end loop; return ""; end function; -- remove POC_NUL string termination characters function str_trim(str : string) return string is begin return str(str'low to str'low + str_length(str) - 1); end function; -- center-align a STRING str in a FillChar filled STRING of length Length function str_calign(str : string; Length : natural; FillChar : character := ' ') return string is constant Start : positive := (Length - str'length) / 2; variable Result : string(1 to Length); begin Result := (others => FillChar); Result(Start to (Start + str'length)) := str; return Result; end function; -- left-align a STRING str in a FillChar filled STRING of length Length function str_lalign(str : string; Length : natural; FillChar : character := ' ') return string is variable Result : string(1 to Length); begin Result := (others => FillChar); Result(1 to str'length) := str; return Result; end function; -- right-align a STRING str in a FillChar filled STRING of length Length function str_ralign(str : string; Length : natural; FillChar : character := ' ') return string is variable Result : string(1 to Length); begin Result := (others => FillChar); Result((Length - str'length + 1) to Length) := str; return Result; end function; -- convert an upper case STRING into a lower case STRING function str_toLower(str : string) return string is variable Result : string(str'range); begin for i in str'range loop Result(i) := chr_toLower(str(i)); end loop; return Result; end function; -- convert a lower case STRING into an upper case STRING function str_toUpper(str : string) return string is variable Result : string(str'range); begin for i in str'range loop Result(i) := chr_toUpper(str(i)); end loop; return Result; end function; end package body;

agpl-3.0

b0ea63feea60cf9182a58e5525d3159e

preusser/q27

src/vhdl/PoC/fifo/fifo_cc_got_tempput.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================================================================================================ -- Module: FIFO, common clock (cc), pipelined interface, -- writes only become effective after explicit commit -- -- Authors: Thomas B. Preusser -- Steffen Koehler -- Martin Zabel -- -- Description: -- ------------------------------------ -- The specified depth (MIN_DEPTH) is rounded up to the next suitable value. -- -- As uncommitted writes populate FIFO space that is not yet available for -- reading, an instance of this FIFO can, indeed, report 'full' and 'not vld' -- at the same time. While a 'commit' would eventually make data available for -- reading ('vld'), a 'rollback' would free the space for subsequent writing -- ('not ful'). -- -- 'commit' and 'rollback' are inclusive and apply to all writes ('put') since -- the previous 'commit' or 'rollback' up to and including a potentially -- simultaneous write. -- -- The FIFO state upon a simultaneous assertion of 'commit' and 'rollback' is -- *undefined*! -- -- *STATE_*_BITS defines the granularity of the fill state indicator -- '*state_*'. 'fstate_rd' is associated with the read clock domain and outputs -- the guaranteed number of words available in the FIFO. 'estate_wr' is -- associated with the write clock domain and outputs the number of words that -- is guaranteed to be accepted by the FIFO without a capacity overflow. Note -- that both these indicators cannot replace the 'full' or 'valid' outputs as -- they may be implemented as giving pessimistic bounds that are minimally off -- the true fill state. -- -- If a fill state is not of interest, set *STATE_*_BITS = 0. -- -- 'fstate_rd' and 'estate_wr' are combinatorial outputs and include an address -- comparator (subtractor) in their path. -- -- Examples: -- - FSTATE_RD_BITS = 1: fstate_rd == 0 => 0/2 full -- fstate_rd == 1 => 1/2 full (half full) -- -- - FSTATE_RD_BITS = 2: fstate_rd == 0 => 0/4 full -- fstate_rd == 1 => 1/4 full -- fstate_rd == 2 => 2/4 full -- fstate_rd == 3 => 3/4 full -- -- License: -- ============================================================================================================================================================ -- Copyright 2007-2014 Technische Universitaet Dresden - Germany, Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================================================================================================ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library poc; use poc.config.all; USE poc.utils.all; use poc.ocram.ocram_sdp; entity fifo_cc_got_tempput is generic ( D_BITS : positive; -- Data Width MIN_DEPTH : positive; -- Minimum FIFO Depth DATA_REG : boolean := false; -- Store Data Content in Registers STATE_REG : boolean := false; -- Registered Full/Empty Indicators OUTPUT_REG : boolean := false; -- Registered FIFO Output ESTATE_WR_BITS : natural := 0; -- Empty State Bits FSTATE_RD_BITS : natural := 0 -- Full State Bits ); port ( -- Global Reset and Clock rst, clk : in std_logic; -- Writing Interface put : in std_logic; -- Write Request din : in std_logic_vector(D_BITS-1 downto 0); -- Input Data full : out std_logic; estate_wr : out std_logic_vector(imax(0, ESTATE_WR_BITS-1) downto 0); commit : in std_logic; rollback : in std_logic; -- Reading Interface got : in std_logic; -- Read Completed dout : out std_logic_vector(D_BITS-1 downto 0); -- Output Data valid : out std_logic; fstate_rd : out std_logic_vector(imax(0, FSTATE_RD_BITS-1) downto 0) ); end fifo_cc_got_tempput; architecture rtl of fifo_cc_got_tempput is -- Address Width constant A_BITS : natural := log2ceil(MIN_DEPTH); -- Force Carry-Chain Use for Pointer Increments on Xilinx Architectures constant FORCE_XILCY : boolean := (not SIMULATION) and (VENDOR = VENDOR_XILINX) and STATE_REG and (A_BITS > 4); ----------------------------------------------------------------------------- -- Memory Pointers -- Actual Input and Output Pointers signal IP0 : unsigned(A_BITS-1 downto 0) := (others => '0'); signal OP0 : unsigned(A_BITS-1 downto 0) := (others => '0'); -- Incremented Input and Output Pointers signal IP1 : unsigned(A_BITS-1 downto 0); signal OP1 : unsigned(A_BITS-1 downto 0); -- Committed Write Pointer (Commit Marker) signal IPm : unsigned(A_BITS-1 downto 0) := (others => '0'); ----------------------------------------------------------------------------- -- Backing Memory Connectivity -- Write Port signal wa : unsigned(A_BITS-1 downto 0); signal we : std_logic; -- Read Port signal ra : unsigned(A_BITS-1 downto 0); signal re : std_logic; -- Internal full and empty indicators signal fulli : std_logic; signal empti : std_logic; begin ----------------------------------------------------------------------------- -- Pointer Logic genCCN: if not FORCE_XILCY generate IP1 <= IP0 + 1; OP1 <= OP0 + 1; end generate; genCCY: if FORCE_XILCY generate component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; component XORCY port ( O : out std_ulogic; CI : in std_ulogic; LI : in std_ulogic ); end component; signal ci, co : std_logic_vector(A_BITS downto 0); begin ci(0) <= '1'; genCCI : for i in 0 to A_BITS-1 generate MUXCY_inst : MUXCY port map ( O => ci(i+1), CI => ci(i), DI => '0', S => IP0(i) ); XORCY_inst : XORCY port map ( O => IP1(i), CI => ci(i), LI => IP0(i) ); end generate genCCI; co(0) <= '1'; genCCO: for i in 0 to A_BITS-1 generate MUXCY_inst : MUXCY port map ( O => co(i+1), CI => co(i), DI => '0', S => OP0(i) ); XORCY_inst : XORCY port map ( O => OP1(i), CI => co(i), LI => OP0(i) ); end generate genCCO; end generate; process(clk) begin if rising_edge(clk) then if rst = '1' then IP0 <= (others => '0'); IPm <= (others => '0'); OP0 <= (others => '0'); else -- Update Input Pointer upon Write if rollback = '1' then IP0 <= IPm; elsif we = '1' then IP0 <= IP1; end if; -- Update Commit Marker if commit = '1' then if we = '1' then IPm <= IP1; else IPm <= IP0; end if; end if; -- Update Output Pointer upon Read if re = '1' then OP0 <= OP1; end if; end if; end if; end process; wa <= IP0; ra <= OP0; -- Fill State Computation (soft indicators) process(fulli, IP0, IPm, OP0) variable d : std_logic_vector(A_BITS-1 downto 0); begin -- Available Space if ESTATE_WR_BITS > 0 then -- Compute Pointer Difference if fulli = '1' then d := (others => '1'); -- true number minus one when full else d := std_logic_vector(IP0 - OP0); -- true number of valid entries end if; estate_wr <= not d(d'left downto d'left-ESTATE_WR_BITS+1); else estate_wr <= (others => 'X'); end if; -- Available Content if FSTATE_RD_BITS > 0 then -- Compute Pointer Difference if fulli = '1' then d := (others => '1'); -- true number minus one when full else d := std_logic_vector(IPm - OP0); -- true number of valid entries end if; fstate_rd <= d(d'left downto d'left-FSTATE_RD_BITS+1); else fstate_rd <= (others => 'X'); end if; end process; ----------------------------------------------------------------------------- -- Computation of full and empty indications. -- -- The STATE_REG generic is ignored as two different comparators are -- needed to compare OP with IPm (empty) and IP with OP (full) anyways. -- So the register implementation is always used. blkState: block signal Ful : std_logic := '0'; signal Pnd : std_logic := '0'; signal Avl : std_logic := '0'; begin process(clk) begin if rising_edge(clk) then if rst = '1' then Ful <= '0'; Pnd <= '0'; Avl <= '0'; else -- Pending Indicator for uncommitted Data if commit = '1' or rollback = '1' then Pnd <= '0'; elsif we = '1' then Pnd <= '1'; end if; -- Update Full Indicator if re = '1' or (rollback = '1' and Pnd = '1') then Ful <= '0'; elsif we = '1' and re = '0' and IP1 = OP0 then Ful <= '1'; end if; -- Update Empty Indicator if commit = '1' and (we = '1' or Pnd = '1') then Avl <= '1'; elsif re = '1' and OP1 = IPm then Avl <= '0'; end if; end if; end if; end process; fulli <= Ful; empti <= not Avl; end block; ----------------------------------------------------------------------------- -- Memory Access -- Write Interface => Input full <= fulli; we <= put and not fulli; -- Backing Memory and Read Interface => Output genLarge: if not DATA_REG generate signal do : std_logic_vector(D_BITS-1 downto 0); begin -- Backing Memory ram : ocram_sdp generic map ( A_BITS => A_BITS, D_BITS => D_BITS ) port map ( wclk => clk, rclk => clk, wce => '1', wa => wa, we => we, d => din, ra => ra, rce => re, q => do ); -- Read Interface => Output genOutputCmb : if not OUTPUT_REG generate signal Vld : std_logic := '0'; -- valid output of RAM module begin process(clk) begin if rising_edge(clk) then if rst = '1' then Vld <= '0'; else Vld <= (Vld and not got) or not empti; end if; end if; end process; re <= (not Vld or got) and not empti; dout <= do; valid <= Vld; end generate genOutputCmb; genOutputReg: if OUTPUT_REG generate -- Extra Buffer Register for Output Data signal Buf : std_logic_vector(D_BITS-1 downto 0) := (others => '-'); signal Vld : std_logic_vector(0 to 1) := (others => '0'); -- Vld(0) -- valid output of RAM module -- Vld(1) -- valid word in Buf begin process(clk) begin if rising_edge(clk) then if rst = '1' then Buf <= (others => '-'); Vld <= (others => '0'); else Vld(0) <= (Vld(0) and Vld(1) and not got) or not empti; Vld(1) <= (Vld(1) and not got) or Vld(0); if Vld(1) = '0' or got = '1' then Buf <= do; end if; end if; end if; end process; re <= (not Vld(0) or not Vld(1) or got) and not empti; dout <= Buf; valid <= Vld(1); end generate genOutputReg; end generate genLarge; genSmall: if DATA_REG generate -- Memory modelled as Array type regfile_t is array(0 to 2**A_BITS-1) of std_logic_vector(D_BITS-1 downto 0); signal regfile : regfile_t; attribute ram_style : string; -- XST specific attribute ram_style of regfile : signal is "distributed"; -- Altera Quartus II: Allow automatic RAM type selection. -- For small RAMs, registers are used on Cyclone devices and the M512 type -- is used on Stratix devices. Pass-through logic is automatically added -- if required. (Warning can be ignored.) begin -- Memory State process(clk) begin if rising_edge(clk) then --synthesis translate_off if SIMULATION AND (rst = '1') then regfile <= (others => (others => '-')); else --synthesis translate_on if we = '1' then regfile(to_integer(wa)) <= din; end if; --synthesis translate_off end if; --synthesis translate_on end if; end process; -- Memory Output re <= got and not empti; dout <= (others => 'X') when Is_X(std_logic_vector(ra)) else regfile(to_integer(ra)); valid <= not empti; end generate genSmall; end rtl;

agpl-3.0

ef4f5453d52aca1ac947d91ab3d89851

jcowgill/cs-dacs-robot

Common/AsyncTxTest.vhd

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY AsyncTxTest IS END AsyncTxTest; ARCHITECTURE behavioral OF AsyncTxTest IS COMPONENT AsyncTx PORT ( TX : OUT STD_LOGIC; ACTIVE : OUT STD_LOGIC; SEND : IN STD_LOGIC; CLR : IN STD_LOGIC; CLK : IN STD_LOGIC; DATA : IN STD_LOGIC_VECTOR (5 DOWNTO 0)); END COMPONENT; SIGNAL TX : STD_LOGIC; SIGNAL ACTIVE : STD_LOGIC; SIGNAL SEND : STD_LOGIC; SIGNAL CLR : STD_LOGIC; SIGNAL CLK : STD_LOGIC; SIGNAL DATA : STD_LOGIC_VECTOR (5 DOWNTO 0); BEGIN UUT: AsyncTx PORT MAP( TX => TX, ACTIVE => ACTIVE, SEND => SEND, CLR => CLR, CLK => CLK, DATA => DATA ); clk_process : PROCESS BEGIN -- Clock signal (4 MHz) CLK <= '0'; WAIT FOR 125ns; CLK <= '1'; WAIT FOR 125ns; END PROCESS; tb_process : PROCESS BEGIN -- Reset CLR <= '1'; WAIT FOR 1000ns; CLR <= '0'; -- Send the number 1 DATA <= "001010"; SEND <= '1'; WAIT FOR 1000ns; SEND <= '0'; WAIT; END PROCESS; END;

apache-2.0

7204d74e74dfc00903e03cb6db300eee

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_top.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block qPI3GEpZcWQvIycErMHhDoSKsieE/CU1+Ybm/uQFxbrtkOKyOV3ZWFMB8n6MZ3bT8CRlbUhWEzXR TkxRDQG9yQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block k/t3gWcO/yZ6QHxZLkY4V/YSwTnMWe59zgVXRMqLIqmP5+4sWdcnqrkWJ2pBDLgKPlHOUDO5KHVg XZQouc2gZ8nI9hPwoqlm+ho4rq4zHpnDJQGzRE15JSAxtcXMJjyuVk/MN6Dhv5p2xXr5Mfi10QtO ogsfzAak/7F8gy868xY= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block IEZOOM0P3bqdKRSBhHQs7GnlzR907iHpy1Hk0F6Oc/Ex4QhmnivkW8swyCxiyH/jpHZhAzO8FWmd ftoZsDPJTNKTUjoQwCCbJZpG/atgT4+YNgdnP8nW7sVwOqzR1RvkUd8WlFsDGYMrtkFpB05LSY7Z AktdT41off303OK3Fy/NEq/Lukwp/TqPt5ubMYf8LszAHVEN8jSGaK5fO8rQy/zIugLRWTSw6kdo m/04YgPm2zvmhtPft6FsFinJo87li1IHf3xTxnHHiv4+yTZng+W/GvRo2zq/Fmh/nAgc5LAS9GIw GiPtDzZHju8N4YuZNJ0fScfyQ+ICPYmnLtakzA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block VRMRnp5/uW5brCSAkibQm/+O1+sxO6aRTjgUAWEFsaucwkUI6jStg939ie5BuSBZha29TL27iTE+ 0Ggl20amFaZBsaKlOFdyUKzGYVPdJdsmw/8K8DqgyrPhmkPJhTb5YPVoKPFoDgXIPzQCeS0AJeuJ q4nP+ZGH1psEz++pyLM= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block XzB2GerlDlWqx3wnqh4bkduemFEXzc/NoNxXZ/8GY+dFA6MXUTlTPm/WFI2CI3EHJkqesb4wNiHP FVHvb7xpjlD+X1cbzBAVqICz0rS2J3MyaVzQZkHVlrvVwQegCtFL9nwqbpoBfjINMP0riSrB47ps v3hMEKcl2DUdEtPSacfv0Vgjw0DTxovaOHbK3oNquKzVRrhvoCS8ZAtZYX5UUkPct241DbS44JdG 6VffbfENl2OxkBBurK7wb+dTGoJeqSbp/1JDmqfKA4CnAtFO01sZ4rACeNTybZA9HnQ9JViWo0iV E2CT52EwXLPJ36QSRtSZRhSDesBXAVt29vw9ww== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 52624) `protect data_block O9zKr6GTBhemmUElE1qhWqFv8Dl5Lt/VQ1NGKpbbrgyg1hQRLqqRWKy3K7c5zcPuLaKXS0V5LWqb rlTE3bss7cBQCEjhhvEbYGPpSp+cuxkHRQyW0+FymdBtjuJ/O6DRJPVHezjqRrYl1l+mvnlDRfRZ FL9GVVJPbFf0v4SRJ4iYSeAY5s9vU7m6GxrDBjblVbXg+ZAVSABhZKPtOGFm9lIvUSahTB0BRYTo QAUKiFX+n4NYPYMvTz/TEjDtHEKoLc0xP82h4jp9yCOGdFntVpSPAfQf9Rp3d8vwysWwCQQZGfIp r6vp4dWwnDGtzWwLbfabKMhdQICRST5bV1S86aO8qZhpwPX0sbjUr2p4Q9Mg4c/9Plu1FMxqvh4x YC3QPrq/ifee4W8ISIZQ0BqVtfmrlDCQjdBKgFFtSUxvbU2VaCgeblM8b46k4YbmU/zIItDDh7vD ERYFTNQVL9DdaB6lOz+2ioMeulas07l5xev5XwSeyV9t8rGLcS0ooSYdVF27qdhlsC3xjPZ0zKYK x/R+tTOeUhXoUfxVJQ0ImIdFFYlTV0b0zhDScXx8BhtyptVv7ruIM0cLWLPIq/XeCHou9WtWNxYR glWhUVgLrOwSOoM7TQqUqO/vo53HEsW5fI5zj0QWCy4M5jl/TGE7avcViZfJAsl1EZ5vNX2gGCuL B6XeKzjQwvZcj2oxhIFJN+Sng/3zITvWIy4i67Vmq+lc+/GmEl1PLuyLpHYvqk1ugGrNRyBMm8YA hwEqvlf8uSBJy4nLp14fGNQ5xmNpxOLfvVaCAqZCprjIngMOfgupLdyNCjHaG6N/cL5GzDeejXoW 6bWYbDL4csqyIg/iiqmCGQhR9w67UNm/jhdAyKB4XrK+i/wkVPRkftcyLUVLNnIbh5/Km622icpB iqSKtf04Ao1uRJE7Y7FIPRY/n5NjRuf4WGj5Dn0eQCkTcD9PpwOv4nVrIHyK69nzLT2nyvGzXIC4 gjElbefFffOH0/Z8z/QToB+5O/XFCQFuMDY9vYCdWRTG04Ff5oE3hh3sRAIuwUoW0ofqnFmOUdo8 ynNBxKBLribffEKK2oTqE1mPV2n7dRhUgMqYDRVl21DErAzzlS1mfBi/J4y8M6PC582pZwPzJxQB y4FtwOkjJyXc5rEHs2xgEawfQFCOr69+r33lIJgyc8xGJq7lR1AGTj+mXQEpIMEe4n2NB3xoPcig JGrLYbBhyaOyAkWWw6UqVfnsPPBWK0WsrzMscO527s2LD9/h323Jfsm/PICuETdr5iLuxvvYyW7Y frKNH7IJQov4LTZ2Ndw3P4hcPjuKrTBh21wsSHs+PayZ6bfbFOP6Dmwn9OTMr2p6CeHa2YaR+HFs ePqBfOJrSBT+l1s0poO27ITSPeegHW+7eGpzWaGfPlQ5JfivH9F5VBezQ75NMIJbwSv2KV73bYID HDf2r75aix7bbDPpJJsojm62hTU85nWeSZn3riUvfyRt2KWYeMmdrjF7ecllJG+2UQd3HYVRNDim Iw5UFSHgTSULanLpwl8qivFyRw86EMGW8SI1tpDInut1LNEcItvtWW/xU2k//Yjt3mA0PlpZScr3 sUUjoX5sVgYeXmFFUYbTM2WcWvJoJ72TCQWcGP4UAYwD9wz2nBwtPneeBpxgh2rRat7NLQtUnu8M kGpSs6COVFWjqd1V8G9pb7/StH8RV3CNwXsCnb1iVFtYjeqXtjaIlueHMoAyZndFUttvFivRqweb BTMx1qF8dGHsH23E36y5eGq/LB2Dg5xzXL1ulC8snHdfpZilLDg6R6gp2wemdzbQ2vAhGoy0MdW8 sfUWN77nG/AADQYS8AoSNXvPLw0Mwrnra12U4wED3zBDpg9/Nwt/VIkCoJG1agFnUcgoEh8OF8WD 2KRLX+NZvLF5AKOVxE37S5OKNSCke0CiphzMA+rEIhD5x4STcTQaDjVBhzTBUQVA0+ZIsipr9RBT xeKce2W64gNDfUK+9mvTP2ROIyUIvmeyi5kXGHfv32g1xyiItaMsOTbFFr93z4bWk8fKzt/Zb/3Z YLxNpglIFR1ufYrZE2P/glcabV5+YH+H6/9cKhN7IWUsRBKx4Hl9wyMBJVvePFadAUgUnahP/dsi Krohy7+Hk3xqNV83NE5Hs9ful1uaMAwkHYh+0g764k2wPT/hdDFyWnj/Q2lXIek/TLh3Nh3Or22P 2aGhMb+dhL9f0ZaFU3HmVoKrsAyFYdSqEgYLogaAIHOIJLfbmmsUUwk2KEKr/dyb6L81BTQT+E26 fQgyeJ7374wpNUawmPubodya2I2EEZCpfYFEZtZaXBmQ7eK1EFNTSJfNRFVBmBjle+JwyMioeO29 vNKNIKyUxGiZBwXtJfI+fAxofUOdW/VcJzl0YKYQ1sT7zcMqVRQqtHUEps05a7IJSYBtM+Fw7Rlj Rzj/Dj5qUjsf00MS9s0kjlignk3cArfTr/POOrVgWcl2CfDiiqe9TrJtR5B0cui9E/u/5qFXcf2l jx2ABB/U6zdUyVQWHtBTtbGJd3VprbycszoT/QQ6l/L/R9AhgdT0ieWYY3N4UYhY6z1Q26Uet1KZ ICxSiVwKTDsqGgBwzhdqGYPeBRZ052QK6J5XYSW7126USVoOSlt/7CWhCjXmo1Qw1XIF9TcgB9Sk ziwvpqxH+Ib02vSIIWyGXLY2SBX1a+6qe/opWhne5AzR7xu6zSvBzQ4w0cP2p52a5rQE+mLymjXw 6soj4iRGMQ1/MdijiYxkVeUq9tctbc+rPObfMhyfseIjQuSQMrmpzQAuQH6JIn0XtI9nU92MMGJf nzsnRuwFBH7rEDyl//K6Ryd44GNaMIuOxv41vIgAMBzgc/hs0kG75tahQHDesyTBL1l6mO8S5+nD piFTnsc0WeZtlV/DWa1m9L+YpgDmkHFEMpgHyyYPLIeQ8bHe5PauFHv9v4jDSggIIk02/pmJqurW 97FutmKqbQxB7ru8W9kKaitFBT0E+8dmyJrqSTHP5n9w8s8DMgCk6DpfR8Net7aweoYPfDMu6ftV FKwH0+SBPawCKk0fT6ddDftDKI1brsNOuD2PD9/R2Bm8MtKkOwbYc2mWcXpHE41Mb73jB/qG9o/R JZZZWrZJ7gVosLK8pvxGdPs5+bEH0cqyZLS9m5rITaKw6YmFSE1zHrKYXA8I5rwGVG5M2YxCNfQT Tvx3HZVIdTT6A0DKmrDf7lIkXn0hch9nBCN/HlVlnwAvNz8KrqUBf8RR3o3QhThKDA2bQIRlHctR /A+nt4p01ydZNOScmAA4WUDi/HfetHGHN4FGiRu7rbvtNGVgDpdm2Ycs/wAybvGJXiHh2Fy68Yot myRE6bGerLUAsytK1IT24gJ7ULpUm+oQt2hHUCpf+WGNGVRYV3SDFWqsRpad7c6kb5hAJ4VpGqV6 z4RivfI+Y372eEfrCSqsK8I+pBWdjrpprBGwoxCrrSMpq9WavHkij7JuvYYPxtqaFWD+twlXo+Ku p2wH+/tpEif+LuizKDBMwqZoIjAWbjX4FDjWcMIBAsALsoJon2TZGm0u9GRttpShQEO5wC84pmAN BveJJUfGlG5OXpCxveZpuvpjMYdGFr7WoNybAE+stT9BAZBGLKTShWYcEWZjciSw8SATpPxGTQni ChJt9c0dx9uf6UVVKtIEiX2gCrvJYNnQB/NjIjNrFTFKb4RiiUPjEdPfFESSHWs3D6FJNPb+IUfZ m90J83IS+y26bGSHOTuqFu7+RU5ngmk49GZo7XgvrC3eOz/uOzwAiVfhB4gTvXhCz87hUw05ESWc 7UVLb+w4XN/hOVOjVB98f54DSXxz96fAtU64oRVwSnzk+uwuQ5ktCsMZVQ1ShChLCCycY0shjO9F lUwcDKJrKE2j8KRX84V7lnaEUCimUS9JdILPB6EIQmVoTbr7cxwzgbc/Re0j8wDPucbzEpdMD2E/ 1islAjgo8BoZy0i2lOZCXwtACsWL1bwGLWDrYYLLkG1FZN0w3oGtnKk4FCxXph/KSOxngA+8Q9kT ktEFovaVL2NsKWDdsdCCJ3/pBCyGROC5eYVBjROJpwsHga7T63MixAsq2q73mbMGmPh0gIW9d4/f SAtQHFKTEjnaZ4Wxt0bm/J9usi++tF18Z53AkREKqwhtVIfTu4gTszgnddIicOg26BUJIZbJK/RZ DKVq/PEB/HfYo2SZWMGK/WWf2XTprp3XHkwPAnumP1WcnEjB5N7jwWkNLblHM07G1p50J5DIRF+B /cxmH5DfF83wZsRtGHdG/9fBnn4IW7GYp7vrcVSTEL9bjyJ4D1n1g50qnumqki6U31nl/lWdOxRa Yp2AkeTSq9hqywJYnPqffoSmRftEvkYh56CajxDUoOLisY+aPsQ+Oaj8Q06frYK4Q46Xd5wPkaNt Zfu2JdcI/D5hqGVM+2PwtpimpzNzpEJ/xPiy5kE/vUOj8fCyTbh69hgI9dR3tl9ysiO7PbFYcMme wCkgR/6Fc31t6ZrAETPwOGV3LPiyzYwGmEIicM41/+509YwFGyXHL7aW4eBItEmNzkvMwRrOJZtN Q/6PhtOar56FQvKKINP7zzCbn0X9a3PBCFcw7o8F9Vd1R0KN2lp2fYTys3q72nWg5YbGLKvQXduE Ry2kgUXAYTCssOjkBmrNPS1hWmJ6QbNqUU3iNigL/Wmwu46sIW2AVtZgNC1kyAIiHvuE6up2E+k4 m8GSxKl5wOiRUsAnk3XGH/EzcR16ZiGtdhmAlgWVk2nG902eZaoqfddXNTJoXse5p1ifdH9z/Ruh fPiWsZYvTL1u+6/gTJ2WV1Xb02S2AqrcK9uLkgej4exLb7WL8fhDHPhmlq+BUV50xqMjsh3jmg5i r8rZgCpItsB0C6Q+ONL3Q/N63I2qkcnCnmRUVUImoOqCH5DaEHALZQMdqf0YVZpWaeTFi41oVFPl MLyhHKOLsbJaHaFo/myg/zAQCHOVHublurgjoTCQvFLK9kpkQwh7hbkzjuPrkSRELc8mvMcEpfET pL9it8nQ5xE2V7xKpPo3Zpa80KJmSonEvakDdwaWhyVAHtPqjwHz3FodCsh6W6ses4N/yEQrmOWw izQDhPwU3XLmyOl6lc0+ZEPPF+RdNEZARFVocYCNEE8rM5W7qpoX/vmAl5MG+ctiRt7jJ4IVRBcJ FAMIC4IQ3gippA7LGTh7PBovh2higsTZsuzlFMiCX06r+arBfoWUaqe9jeUcRuTOVFAppMxZ0mV1 RhcEWO2vYygK6VD/24wAugkYZrMyiyyA4KgjDTgaGtMWWrRy8V79V5519NHShSDslHv9Ytw/NYiO y5AMRoxSr9u81B4bIlrLcjAWm69LKWLde85ws2k1IyYsoP/+XyuhehcHwiuwqO+5Iml71AkltxF5 PrjyGb8cWl7MjsfDH8AN2ncL0qe65KmeSnI85dluxKD69dU1J9ONNwk8urtCnPD7tVsWCJ9Zgcza gYza9rfKO9SHYOPf2PV/Oz9o+q3p71Go7K27v+wpvC2MuQrtvfBWkn8hILenLHSETjPUSUc227Ma YINF8IKVPWD9/cchea+ptRwWZO0K/+2oxoVcSkeDeGg2d0JV9HsKbs1Y5tyO/gnXfjIq4Db2cMGK PAS7lEKy3Ef8HdC6nRbP7tTf7f1tghLCszOuPSFPC69r5y20wHWyhjHupfOnJjHC4zhWiVFlCVFA LIbVZfr9rmYPd6AfQ7S5Y1TDW0FKF7h7XuWZdNEwfHUVsKruOBwnWBRsR6MZ7E8K1nywCOycUxhA TiTISe1r3EbPLuPZhT2JWmnIOR9vH7r4ZdRM+45pJUNb44K7Xoqe6T+hchfQ/eHZVKiZvIIfjvf5 DczjCx1MfNl3Tbqn+xk3KjW9i5Y51akDDMJ7gUFLxJRgEkPgSWochzysXrmC8bgo7Bp9cp7bZROy 68YcNzuWszosYhMY5DzHCj5aSAOiiwAQSV9mHJFIM2M5oACescxE3bOwNinC+XQDR06q/gApRHms E6UEV3tLPt62k1X82K+9O6od/Qsw2SCAyJ+tQZNAMy+Sj3A3lHqo9IMYzyXulhfoOzbFKrOKLCRx c1Gvs6DSS3c+kOAgXuOSukDaug0bf3N8JxFG+hyhIttktAsG6LpxZ23uZeItpImYcZ/RP9xJqiLp 9DOsVF5U1lPVZ6jjsMrnNVj69vCy+vc7lpHN1Sb4pLikfxjj2FjSQWGgYgkd8meFqJPVA7jTXFWL 5iZW6w9Vfl0GIXftA7nUm5amXZJp+unBPCW0q5cpmolWxbtY51QwqQcqvncv8T5bhhC4iZS/UvPg QjYAduVkrLHJIMhdkuP4TIZyLvUfm3g+S9R5xOAOPeq69nKPDxcd0/zviogOWDNJTkzJ//LVqcLc DssEXk/umjwjBFDelxL87v9ehHwKbovyya65EgUG5kpPu7Av83l3PyO2kgFZC5C8ZJqo0G+suDHO smTdENXQCf1WDoeUjZXE3v/2aFtdmtSlXxvpdGzE4YcgrIh4e9v7JwCmNVjmbm0iTETzX43Err4p HVlZlndk15Yjy2BuckQlRPK8yLfehXENk3JrcOSGUuFfO0E5bQfwdVXIrD3huaxjqMcJOVpTVHQ3 DGjY31sRCJNvokR5t/yljCTlJcQGm44MMvNyVHaR55Vnk36wc530uzBVZYmQeVac7UOsgAcNJyy9 moPo2qv02+DYIUw8bBcaQEM/cG3EuskKBpZPwcXMLRm+wI3XhiB3U8KhI3DWtSG3A5MMoz2STbUN 4hZKRD4qvgKhDe44DAR98Wwku/lt5GA6iRZl3z7LH9GZp1R3UixoZO4pwE64/5bIT+Rt4tAA8CIw OoTssaDDOFXq6jiH4Sv7LTrM0UGIxLe24aOEgeB/v3xAilf7j+pgvt+MEJaR/tVCMKea7VhQrw3C f0JUpd1jiQJhGiKsRUkRVlcQaZ6hKevZjulUBrcNYbnWUtzfJKk4Pd0iZ1P1yJJ4art5wSds7ph4 fmvH6bQySOpz3BnlCRtsseZFWq+c1IooqaeEn7t0JzuvFtON/MMTTQLfAaAmBkemcaS0oW5Dlc7Y CrjE73gPhKCgfQAl+tct406vg01i9xWoiTJb4nQmd61JaWT/hlBPDFX50mSMXuL/PTlRNOFGHLDw 2084PwZ9lCSjir9ZZl/iZaulY+dripArKYu5YBO3MJ5Tqby43RJiA4t5PPrgHTkRuTzsCVYrUj8f m8iOGxlVktOVleqUGWSXm6kgK6Z8PZxUPAx+dNOW8bqoFMxUBMM/A9h+Z9X1o/Pa85tXm2JovCXg c5B20XFr+m+jw5J24OKiTNa6lZsomqT4pzd/RwFSJxG8fayBz2R0jGLiX2H5UrfpVvvZsJb5NxzS JV6VWg5dj1u5f1GNZ9DMTNZkAWNCWDGl2xKHKg4+37UXGhnWVTcQSVmAhXLsBSXFZkLrbClcny1S nfop36r2Jd++17cIR91o0h9hjcs2W/oABzgfApyEauz1mfBzVOxurhdWD8QZoi9DZiQcL5ynl+fB JHoJxCVCLKaga8GZDWk3sMMsBwqGNE6693xlxrjOAZ9SeZ/Il8XlTyld6AJGvlC/B3L6Ceveg0RG TWZTzpGd9yVqcRFekSNz0EF7P8Pcni/KHqtCL9K0QfteQ6yTDOpry64JrTsmxtLqM2RPiY393Oo7 mZlalQ9qcTCMRlUL31yGkYKIHGdt6fIveUMYWKKWan8VO+tJxhBCSGVMoNFfhOXCLVg/6Jxsg+P8 RdkgpwJrgi9OfFC9bpYQ6ESDz7ELKKJXhkgq5tZRhhLe+c7S9LEc6Cj0Zon+5miAJAilS9d5GOee C51o7EAMpmY8sXaIwEVvPjVVMjqWMZNXJ0dGUo8295WRsyFHeYtPPYhVEBRU3M7MOurUXU2u0P+U ny9GPZ48Hj9k3xpovmnXEUCwLbP94S1ZlQgXTGXGmWDR0WQNL4+mB1ECV8HbdfS8I2JWc1xOl/9W wkWDEzVAJEPp4vTxi8kyHB9lW0CUHtglZURb5r2bihAiuQPgLO4UYHJJqQavxYVY8XyZ5+vr8dhF 8C/mUTZGrxhw1Aa3LwxTkmkZgwDyOjkdGrzgQfkywZRPd6Vu/NyjD0gGfwjlP8Giegwx+uDv+LRx F9tbqm/7smrsRHVQOceh7P8ldch+BMqC2qvXhpCHOVieHyMOBGsoJMMCsVt+ARbGY+l4GarEmLXu +obiD0uRcfBxEAhwzMiO9+HzlDledneiXw/oS5VAp+e6e7FWWBxAaQJjRXIBKXfenIIufs6eprbC Pwnk3iSmKODOEQld6O9qhapOXTBFElR8WzObjLCJ6ZlWiYW+sEC/LU59vyVSPNCzaCBOtPWgo4fF kwVKfO06vXFO1as9YyfHyG+co815EcVlRepgwZQuTJ7pY9xb8dSXgKACR54NGTsEe2T5oayUJxjj UYL622H4YoczMuZitL26EHqnEtxyLSMmYSLoLRhnNSlbxF5A2y7YyUy6sh8lDWmW0QU3SLKRdjRG z9ZgjHr2WIYtQCwZ/9eNKDh4XviePtLDwylL3rH6GxWUl7zIv8X2cr6fNpM3OO/3HeeSm/o9Ov+o hf5bVc1K3OhVBeaPjV4yApczCSnbOui1dSAYqp783Ap1VzJfy2heBOBfgbC55r8D0W+OZgITputX cO5dXOxwr0v7MMn495mFKfFRw5mjmh39ZpQT5k2XFu4v6EZdFgSSe534S1cc2JOJFJH/gOwv3EW9 /xyOAJlHmmpn7AuQwmyH4MvazI+IwXo5k2g39rVEhlWDYQxdU7I4yCY1cHI411yMh2eVvNFJE4lv ipcCSnai21L5iihODAbLQ93nnE2fTXteJC1LMbscKqVt1asRNQRsOviz5xPgLAUd1wOzCwgXYbfp SIZkCKlGlK1HJw1PZ7OO3DSo8Yrk7xy/7LQES7nhMdXnHN3DLDbPz2Ruh1WbNDzEpQlB5cVB50HG xidmvkEEDyY5dwtTdIwdl4oSy+S4MKaXoiuIZ4v9XHWQ5krdg4DTkfYY+VsryaZRmI9Q3rk9MMei 7CdUXHct+PfCMSPDUz+GIiwhIhiNchQ+N2TmmI7wLGHWHxZynNFCs/8muyM2VRxast3Lz2EikOr4 TYlsqv7x60W1092RVS5fPXirlfObQHU78jDdFGYtQIOUr7/R4pyqZBzPHZy5Jd8UIBusNfScc5lB 8h5ZlhAMeQ30uMnE/GYVZ9Y5DrIJTxzLwZ3VKHdT7TlD1kFlJVgtk0lc0qxblplNLV26SzAYIIpu hhtoeS2O1oSDeu5QzqHb07M7w1zabSRRSB/J89uHLwoEiYrX8h17N2WdDrcwxoZFlG3inKHH5E/V XSeKCnFh+1bPQrXhfB6OWhwHzZqkbw9YyZegVU9vqpxeCYY+qafj6s/H1WDEN8AS8aHion5O0liG DN1AEfuSobpRp1HnmjUfLVvn05+KBtyNn0Jl+Jg1SCuJUUGQMpfAQifwBSZ54jLCPHSlCgbcxs9/ v1EtmAGGMAAeUNl6M8A83nzzWeoTuBcIK+B7qXwV640X0GJFanfUpdKE5vdQPvuGcuxxLW13Uw4r 8irDpbQPBVibJw/j2g466s3dCNGNABjuK1swJNm9GI0q7F1WA28DZaZzOfrzdpzBNfvqBSiY6KxI WdMbTWiN/bVKiv8svrVYHcxNy0AyXADQkgNJPV+WT20DlwQWbpd0WsQ9OGCfMagFMqj60pn5jhJE FzqePCG20Ch2kZTmlHb85TPmF4TRqQA0eTq8jx6VmEBKZNXIiZtI7D+Pqp+EOOlcevFeN+lRWu9m HCNuiSVvhSpqI5QsIa4aIhlReZOR5MeONzPdyDA/480RrDmV+OxlYYPytInfLhXFjqgEi2Muy4b/ C7YXD2FkyvYZFn55AjdwbIfRokO7XavdjrQIcW5ajxY1FTPiCoccYcBnQYKYV3O8xKrxn86vVDKW Frl0RkPHOTo3rMRdZ0XRXp1LQzwQ8kfNdO6I0cQnMhzIUnmFYhL2JsTPe/R75E0TJaiLZ0kBn5wZ wkmrUJxR4tkABqmpx+FI/DGg4GIXVONKrFSx035rXwfW25N43TPCuo9GvGYLNRAMRdkwvxFAfkfs vxRonj6b/3HPguwFKYvfSpAWnCni7ddzayrLx7c7qyHLPx0XCS/Jq18j74OXpUEJcLc55bcsvttU gymk3Giz9U0vnuWrvS4cvUUo1GgsrqCi5zl8rmj8Bp8yOrMM4Em5gvaOVHZRj1DPvmXBC4KoqE0o 8g5QagVXL3kFuDzJY7IFpFY5QS3FJxhhM5H3QfQLnZtI+ZGKJSV4BgUIxpkQMloAvRVbg3WLd5cY n2lXSQcfszBTKsOMJ1PKBNHRwkkKlCi6WK+jQ2fHbb9qk4vUmXr8ZCWXvr5HTAHaW3zvVvaXJkYW YdZJc7ohGLH1EYwCFGj3vq1BkHjuq/vTZJseVb6mLN26nVvMEvSzuvt5hiDoLhYCuyED1qOzIzob AqtTb4A0N5Sx5aF9HDF0yfLhcvxj35RxL/lApswHgGHhOdUhf7KWvds5UCNw59+2F+Ioa5gm+xYJ 14rnH8WQTefei6ACbDJyGSyTmUhGLkoOvfirfNEHd1uGNoYLNvKwfEC2YzrnsjA7ez7qcIScPaoM 9Ig1jb2PIr8IO/YDV27ZqgFHCGHfbW1Dc8M3U6IJO1npOljJuCgZ+p/2ypHl3Uxu6ZyGD96O8U0P T0AvdMh/7iET+mU/lewJC6m3V0yNR00EMp7ZWp4/96IPadWMG+17eboMny2Nxzc+vTgxbXL898fw CisdRcxvl1FYYDc448iDR6h9Yk/llBQ8i2Vvd6Stpb4jmyU+WlWiz2mc1rsC28xF8ec5/baN7fD8 h7AHPmIAoHW5MdAcXVTjZ0QoUm9AcRnR8TMIGgcpZpu9S8USmHmlJauG6CeYZ2YGUNXlZxPaVDx0 xiY0bZe0hfEYtERgJxZXrY6zmk8KxbmBJCD3iA1i4Iw6DbfwoslHMLD2Qw4Dhai6+HbeGMolG4tl jCbMnsN5UjqVprnWrdJaVej6YsZ8Wv0EAp76bToe9SbfPsnwyUCJvby5kccJYewWStE0DBl0094r BcoabBEr3TKNFg70mSD5JmNr7FVmoj+9kLs4PVgVHld+QFWpoQwOLEgzPi6Jh23Inoab1sq7BZjV FRsdSKK31xqvBuxRpgkmZC4fSytbE4E1P4JE2Kt1KDOT/VFtd6SegTRDay/GZQ0D+1tF8oBtay99 hnpdnpkhdlOLaSLEhAn+ZJuHayjurNSOS6GSOYSWv5yJvwcbkY0vRWBMKoR6S70ECfKAcqOMlsir VBQmQYpYtmsoN7/KI2p92ddL9XdAaclQkZtSgWq6cSigSvmH+LdmmyyjEP/P2HNNOJeouiDNWiiK /uFG2rPzPuuCeCYsbad8NLmklOyXstoCfO3cK3pjat9Qaendff1wVDHy8xYvnQaZ6VIBkAeVLDHb 1O+tauNzXPbJQHU4etjU5U2RSknBg5CEP2o9rQv15b84mWzEKzOhhYQtRaFZXrfRSlaP62AeUTO2 SXKJTcfJjJqQZ0zFVYEqJWofGTBhUXA5ARCfFXdD0GH5WHYZE9U+OIfKFdllXvlCUkjk7nMzu0st hF5F8YQ5HhopF92TX5BYwCgjkYHU5C4DpGZw16R+LQqApgtWPBhiPX3kr02nKBbTw5D3uzDT2Qo4 owWs8RYX/YA5o2LzvUfvPAfT2HUAorxJJ+eUuhWPAMA6zoUspoZRBTm2qSxfwaENwGMKR2COqqsG OLxF7trt7Cvv1ebQUfwWIAmCid4O9XPjLKm6k+3MCnfoaFwSxqrh5rqMkIigEG+86V19wVEfnBMg LnGJoMKr6fTcejg0wHfgFs8Ac3AONG6fjbqqLVII6rJTSyXdhgBcG/Yb22ohs1AFSD8l90FEzoID WrLQjtjtcKnshPZtmIKWArNDHTNfpfh7faPbsscCHmNthlAHsf2TLMTSFoxbixQZpLOynHqF3ksn xFqVFPGeWbEMMRj0maQh8wMI/fr4JfglYMm4fBvZWuRhyBvrxpaqCmZ5X8iABC4k719I5juevEsJ 7mvYyBY91S7G/YyGn2eP10f7bz1Li7mOtuezIqeTrEOf3L8xrCZ6TkyrFgQZivdZY11Oj7JARDAB 2dK4SR36VSUXk9hf3Y/EvpiT5BodenymzTgtWp8fH+cjvhaKpT9Wa/q2GrcN8zFsr9VATZLuKaPD RCggJSwgsnj1GOerXK2ruP+e9l2Q9TXiSUJyhxSWgjp+vX+th1s+VqI1ZRaLd3UXkE/4bPPvZ9Pj wDPOC6zp9tYOVYiKL5S5arMQ3Crp9avgjDGHyfH6uiwKeDVBNe/iRTyl9vKVu9DD7g0MJm1RbEMN Pph1DLj2auVRyBioLIJTQMA7eH0OAQMOJpLT+00NrUJhEVlh3VzYew6s6g4Zqblxex4olB/GB4W9 Dk5uCG4fVFyfvHxrcSCfvTiCcEyryyD33p2rmrsijBi4z14dyOX+LyLbHAX31Wm6iSwW7YmWgVmA 4fG7AlC0zLT6NkwLVHEMBf9qHpbIvElom5/nxMxn7JF9YfjzebRBZq/SGdjaNDp2iYlQhwUBS8Pf dqQQv4S948EoBOU9evq9C+XdBHxDnECS7C8IAqADDU7bQ6VC6zaj6JbPKg93hN9ccxiTEcleacdC xUgpbJAM38Z1jampoeiOzq0JXDMPTuiB4woClQnWIp6Ae62a1XazYiq2zgS5bd4lgmraB+wPaX77 KsxAMqQ82e0GlgtBVL9veD4gjr3KCgTF7XTKzi6uobI5wPRMYnk9+UMxzjrMZCx5zrYNgt1OuXHX O70WFxmw2KHXS9xo1VyG9YWFNSpW4T/960BbDi33wb0QWcKG9OVIcrym7/RR7NVuGlQJmt4k8RuS eYkuZG16GK3R6y9LjNSdVcT2pTjQRge9x4+MpnoZpYO0GeNuC3MJ0zV7+lec+HZh+bPFIUwPaTFY 5ooQg1cg8tU2KMMzZrc6LpV754wByOH3svbTRqXX4DyIjGpcZQ5RK/5QF/D/X6hQ+L7c5pkeYC1U BFFZhpPyNfZNixi/DhG9EOFZLT8WkZrYMJcACFBDYJh8CueZ7VWG/ieFNGuvu2xwK+1N19xbAANv nzxokWETVz5KWGSQJ1Lw0jKJOdTbOeDuFxzygDSxoHl9TywFEFEWcsAxhjuDpuYpLKLZGGeeBp+N VzFo5cJMCPi3n6BycijxWDXjIfnUrS7R7dpSiXoFV970poiKlhurJPV1vM/+Z572OIyuRsVcMeNC 4TNPrpY+GmiwZOS8wsNKYh6RI8t76UDeWLC3udNrGsIA88stiz7CPOCkfJEqf/OrlwRqEq/h6ZLX yh7l5Rcsf5PyVlyPggYZBjB5okrFBNRAiWmiZx0Uro1fiKfiLH+ZnqeNDu25g736GaYsig2OTPL7 8sH6n/ug2800n6r0tEA5ujgb0zw4rDU1rPUF2hkzU9pcgrrmO4HaVh2bm9CnqMM7NCUUG/ZFPLg5 5dVXbR0Qfr2xqNVpK15v0aG1kyqzlnGH4JAf/TzBllMiggJIsgziHDnRHN12NbE9td06Zb+EiUxZ P+LlzpGO6YXqlB87CxjUw1HyIcbEKRCkz8FG2GK9t8WLZmDG7xYF75dNc43CqddgQPzma4vSpzFb vUuAqNRYdCHG93yPZrblmv0xBhZbAhSL/Q3lQU8Uu1dH+i61j/pIaQ20a3lbvqmOwPn8UVJ45s/D IrbldD8R5pSUe7yWjP50rYd8UGseDMmt2S32wC870E9J5trzq6ZimE0Fc0ieNxYnVw8a6YjrgEr4 COSmWzF0Jd240Ton8JHUfqBnntIN44cQcNKY+tpDcAos2TZlnz4stybBFlZQ61RBJhRPFIoNL9RT ORGBMS1HGutX+d7+5FB2Qg5b783xevFBhbCo8gG54K1tRlwQmyZ4boWhWXF0/QYPAlWtyiGP9ktN TwE4Yf//ekARg+KSdOXwvqR2yYIekkq9TfiTAssC+lxaGU4ZrUq2+oOJOtuSDJDOy5OaxpTreXro Y/0cPBFqBj7L9O3/CmVZpjZl/h1NHKHIyU25/FSvyYTxNib2hcJBsWuQlWyk7VYcNt5/lqk4SsZL BBcRQ1E1fHWCBpOVny214Lj8hmG9U2fSX29mT3QrJ24mI4zwf845SOwZOu/3cDkxQU26ZMHbWPZs kEtBAeNPpTNpg+NeWju6S506w4do6porG38I/TRfwKEFA/jCx3lSNMY0kMbqmH0bzvgOk6Ir8nxW N0AGrTojFb4Mz10x00//qyP/svC85Qslw+d8kHxQ5dNUsT9rucsquxTk/vAR5jADkSMQw9xx36Zf AWSsAbAt2tQCmiZ7MQCIFmtl3tS4H6KAIS951sEH4Mv/BfuovqOFwK7UjG+zK2prFs7E5/Jq7trd YNrBCbIi0rIhg6iNEqMt/oU8hs5XtIO6IjHBti5GG11G+WGrwPLKz54L1SS4N2ZPM+cU7QB+mgBm QoVdZegMmKgBqMCWfnPYFbD/R79KzM0bFr2hXRMhX/IPz0OAgePHAqWLvQ4W6wDuNuliOJP+abzm kte9NzAYj3RmbZqfjilIxLLkNTVXaxEvcKIJu2OGuVhuuRvQ5Oh0he3QxAPVqhP7Zs4cgDVjFz5r 0ntBPZnlR9EjOYubKJznvaQP8EyOdGcS6S1RDnDrwL31C5nNQPezXsJ67lOzaxrK+wVGg+8OrDL5 WzF5byT7cvvC1jymzkpC7lLsMxgWmrCnHe/koRYv4LRmzTWKrgCYdtoPTapmwwVS/cgznmFH+WVa rGoac7sigTKleJA9qC20/DY9jMEWwyCoQWvUMIWAwd7GF8f8NzS+XtCUIvnKgoVDSfNtrl0SPz+g Rc+sz6RCigvj4bZlIWGYixpWBvtBBugPmN0XcXz9l0XdtZbgZG/4QeUHHeTiTHtgh/mA3xoCThG5 YcpVru78RFowc4rngxbupCxhG021jIpHYeWKsMXJCDYAT4sogt5CI9G2nyOekBDkAJ/sEjrAZR4P lGgFDl2eghFHPr8e5+2kzvM7OZHXjMUA+sgzmUVWUqRxzMukd7IYNUoT1Hof/dmZZfp6qrMu9yZ1 Bc0cobZq8lJWX6QCJ6pIPXPewFVHPWlhkmLJVZ4o+M+X35uhG8V3kC45s3UXxRsSxiECC2xOfqI1 +oElUWxZ8ZXfcxdHec4snm8WNGXNmGFaPbxkHIAgcyO6cuouEn50Lhy2zzKmZO9yB0JJgDdFKE5Z 5W9Bi9P4MC9SRZOoeiGzBadGnFeH6Rp+QysxPUDeCFPeuQ2TSaMeoBZCI/inUQhwV7kYRTLCwcwc cJf8KlAgtwhgEjBqN7Fzw8eSsDQGgRrNKJrQWJAILMliSWXuk5vZYmzqHQqbtWkdGO0TEQcC/X1g 99RNU7dSFk0cXvv6gRE8xUCOx6Uyiu+Maw3yAQADzrHYbL1VJkEmchIJHOTu02GE1UXX/yYyybUu 46i0oLdujdJ4WlWfvuffC4YNFpCYPtXbwfHt4KU0ogIgCeriTmXIsGOCImKR7Tynof7eM+CpfzmR 92NnNB+j1h94XINCo0cFYtkTRB6cL2t/p2D+vMCuM01h3p3ceMrMnFvWupk7yuF0a+9vg8N/jqXo PYFHWOdDzOfCqpMU/lXWPkx1l5CIRtQ77rFUl3UE5/2qCUNqSzmW4GGW2K7DVbStX05RI+CgTXh+ as6pwdlLmCViuFbIzQIbchT6aDJAjBTUen9Vrja3YcPYbWbdvpza/vJIAKvWGZF7l7jQSIBPuO+W cABESC42+tcVNjLW+3ys+hIo8/yiXjbelDy6CEmiFzlDw+LYGcuYCP+t9moAcWGeCxFug1XtE/41 sApB8CGURnYIy8CxlITI6YkVKM9snnwydq8obfPaDaiStOm+oHxQ7NN+DpB0cbfYc7eryGbfVixX 0UOXm4sipuS0MJm++sUGJgoqAFZyqAicDpYEL0sb68Hg//6zwnPdZ7d2OrV26U/Vk87I2m+kU31a iXmLWN/ZVVqiAYGWUFN6bhgRyUjR78vrH4V7V6O+g4gcwIx6IUNjIv2ehhPkY9N9l7Wnvraptbyw UHRnrl1eRLTyvM8TfK/N5PbkKlYi4h0ch3Ik5TDD5zVYsf+rvLAYtxLYO2gBR1bb9qpScEUB2Y3w nTdF/Qyx8U25jCo3Jfy/8Bvaz37Ri2f1sRfHcr4YgyLemvN340XR5l3QrmtIFAPSSnMI84ND7GAt iidqLO3mzfY4UhMnDnxf2pMv+qoWDhO2Xt3+ov6My/pxAsdcLDAMWmNNPrrFlPcBOKHLD/g37ZtX VeYHjvCzJW8ZKt5zl0Z8PcNmM4+8wXAygF/UVkhOYBCgXh1Za5N9xDOjIsiBFmRu76r9c1Y8db/c e8+klqC7gSaOpaO1P/fvvNgFHn0S5BuJkxDCH+76syYyJCWcYGpewZL6CEjb7yW05Z5kPnPLQxb7 THlfDC9dec1AnZAFkMuMYWZx5QHkiDY0AZrTOUOik78jy3Lc2XN5AvDfUSud3oCc3DfAp67GUse1 UFPMe3m3VYQEkEt/++oST9YdLJen8vRhnfrxrdzhSdfR8L9v4Bg5GgaDgV5ft7l6OWD6k/oPB/k/ VnkqXtZLnFGj7WeEHRjYVSt2XBR/mETPeqMpKQde38lYDy+Wb7EVehEe+0dpWxPudjCLU/Wuf6X5 XHmfds9rAOnTxatu2s+kuDeCMbNl8Ub6zN5YKmZ6lwdozK6st7KQxW4jRt965pz1/4zUNbnofIzN yLYOHAOAzwtBupzfDpWRgHxngy8jalMpKyiIzXuAPUhI2ZOarbDbzttCY/0c6t7wKQBLl4V92cXd /ISRFIkp32PuNlwjpB3ZY8KCCyvijX2qdbsq7C9pL5zcHCU0Y5xrtaACqo0H92EXSMoAWoMcYBNE hwUpP4tQnBbmQpzfHD609Tc4lJaDZEanox622SHCzz0J75+VkYisH671YEWsodeHy9lkrKHk3fkg rHy6BBPjHyqJwoeFoWbAGcT8z1C9sbSd5j3ELf9AqYI4C9XOjcEmKOSjN3jhF25OCdAtOFEJIbRG YCZCAWqa/sHiwuhfv37dTbIL0jwTI2/Hfqwqz4g28yvdiacFvzmg/bdeoPz++4w4LQOFdGOh9n18 9b2el+KT4CXj6qbne3Yo9LhIgc455hF3wTSOLlHyJ1ffHGEnYtdatmkZyl3F3GbzLP2MaTM0wtZb 3So2xwKodpfVdZ0UmS8Lrq6D1jYnqgnKz/eHtDKO/4bVTDSxfysKo0COLgcLtf4ChZ2sYfxxEiap Pw9wBtVL5CYk9hmt67qvgyTy6GLliduAcPDNQUhU4DZPxhHLZMJvdFmaN/Ifv+f+599shXDL6f1e MxowHHCKW6nL9ECxRLD7J0lcBZUdjRb0XUBj1mGdqRTvYXBCH2rxPpQ288O08irZkHu9mkjXkU12 Udzc02SAfddPX1Qu+wxZwCRiL96RxKbHRuBbiC8IYafc2SGjBWyO39wQvyTe4ccI0ABw/4nQqWic vYOPS+RXhxZhvY4DdMAoIzImOws8RYNW4rOqvqszbYt+fpii4saMdB10haB4MJZYXQFeQlW9gM5k RCHKjy6U6TjxYBX0R4119yFyvmFfQXduY1ylzRICyDuy4zjmbvrfFBpvdcdxI9CDQ7+DmaW0DBNf pZOa75F6qRopxxtWGqsL6A7I7lxJqWr6utU8L2sOe8XaWs6E4/PvSGeDcLX5cFryBTROyT4cyKWW Cxy+5D9D/Rx8YCWdAj/nRLq2MQUp5SM+cxVSEJkQlFCEBf5UyV7sIXTMWNuOeYQRDmKnqul561Sf P1mSYM9dkWsT7p4zps5ClRjkj64AfFsv/brJAC5MfoJS0pbbFDMB9aB+AzRD0jJS7u1hxphF9GWq 0j9RlHRNNeu0HoR4kmHysmBdbO8QiBuzpD2iXPsXigdM6rwvgiiXbufRTpGOWGWWzSSi61laqC04 8YKfWh1SjdT+IUF/mlVTDDPAUYgrJrCB7X7sYgPQq4SgxLWXOcV5UoWUQdrfWJn4rzuBcoHuH88F cQEMlIrmz3/qfoLx05+cd6jjdyc1OKM7VFrdXcqmXAjj3qiroT+q8Emq5VHFz6ZtoRbTu+/OcTdM 4Aptlz5Tjxr/tauJQBHWOTxijNK698BhPfGOwIcLLDwYvpPgxM3cSq+zBUrI8CLPoIHFuwXzXiD+ kGCgapOymGz901sVxu8MDLTY3JDqbSC7Xe4DWtLAoi9hKaiSmxtiF+ubhIgxZL1zAtwSX/FkshJt cvjVLVLTb6cyK3gkiJ7WulO8zY8BzUhE7j5LOsNx3+OB2TkPjrHz0zjoq5o2L4DodDx7vujaJxsV j1GL1PxEIK8OrusUbrhhkhmqeIlJLT4wSh8I0HACMt78xfVw5Jdf05mfmsAsHejDeGoRn/6PJscD dkvdUuCXe7nulCIeBWPaHrrS08ekonHv05nkr8l7xV/zg1zDqwbJFNU8YwHwJVT2MGk58YgVZrHX dH2vrkemWOQfyQtWHe1Q0XN92wUDE1dx9lRIW7vHfGBH78/IGUJjeQo5yD78O87DzFrLqUuMAhPn LNdyjAfljUol6ajO0fCaDr1QlRTuClLjB497DPKlL3o27AT/9+zf/GxIaKu/UVNthe3giwMYz33U HF2f1KkVXgDM109NJoTXxE0ygtFYAMOUdyogXpTW7w++2wH+em4+lE2Xp27hLbP5eYAp8PhpDboW 5myg1cG17fK7VhX9oaOvQouhluiP3cYEak/XnwFAZvoLColCNXv+hJs9UBuNCuJZbg+l3eCerwdo ifVN1BwwoG3p38mgCl1iQGaegk4VCkhhTqHqo+VWAfX04oOuPmuzQp0q3jxTvK5eiKu22B4DyjPd YLcj9HlkBZRYpcTDJsfNbSnb+FH+YiTELP+wYEuEnlkoFgoZEoXxGVyT9vzCfSiFkfYoUj8bBvM7 CyXW9ToDxIp36lBycNbyi6CENsMz4mhCoPRUzkf8NAv3+KNj/AdmUBFTpP73EHxk1Adj7Jypw4P5 EB4fj8DfBHKBM/4F1gMBshSJm02QkvciZmbnYuEB+o/AQQ+amYS5nQCJxkmLaU6/yTlPUBUjEa3h yn/99lyuTl6OnitQrv2PmvK46yvyaq5KVRLeU/R0ugQ8JWfg46TXVT3ZRg+9qLN3rlIXXoRCv65p SUc8gJMaXdJqTUDvEGT1cy/aCMyJ5fHGZ6M5AJbx4aRXeDQfbklMjWVROBgK8hI03/nF0yArZklj uAS6OPHJHKIdGcw1zVp6vDcK9QqMJkOitRThMs60TWDyrQScruBkXloYjFbs9AWua21v6DJ/zYLg vwGeXFvrPsUJdMYEISRSO5v6fsYltaQNCOrnmucxS87x4XJSVM5KcKv/X7WusEt+pAbP1nkbnz+9 qK/7jxucZytfS549gLOJZP+1HZ3Mjct/AUrQZ7XGiinafnmisrkduRG44K+Vg1yGvU8MyThvMzsS SQPGz2cCZa+kluQaGmKtPe6Z4nDylZoSydE8W/lxFPCJXJ1kodX1YCmtsHorAf3lvr/O35UCcSMC ECVuh8jXXLsfd5cgPpoT5jVGoxeM+T+c4D9/jLZZYEjAWGcsrA/VYpyskE/BXA1U45vhHWTe4S7L U0I0XP5yPrKDj2Q8gkx+HHN8l0deJpGISj2JYDamGmRSL78vUJ+8YqVXImVtMbGIMECNwC3oFlCc 8WxoZo9snFD6XGRtUUAAg/U5PU0jMeZqmnHlceHnJEaB2aEa11ShmoWqNjD6UHiRAOXuEuiUqo7n iCW+GCOcPJWYFlGt2HTzEoFJ7rJXHFJ0y6H1jEiNNI6DCP6+7xa+jinPksEBDCZw5ZOr3FJy2Svd 9WsnHiP/olhRWHFHvn4UW8ncKcMlv7VuDhtAa0gou0nU8G4wX17D9RjmIHCvR8lJgdRFbCGfPdGh jzmiTiOPQzhfsPTffoOQfKsOy1S4jAVXyj0q/0okppgGk8mwqoFpTh+ONxygyWQEI6TttxQWDs3z t/JEhUsWaoZn3agLIj8EB9yeO3X0ujePBR02odst0DzTWFwJVDlD19BVpW45i9S+vXmOnxwUmbZ2 NKlwJw4PlmhZvkq+/dQnHWqgYx86B/rcY4gFlczYpFdH2T6FWO0chXtBuQDNZ0ewLUOn/BooKgIm VNX863ny4ZicvhzoTO9Q1+MTsOVrapk3FFjLrjA7BS6p4Db/35q6UvdD3FTfROeqds+QY85ctDtA UJxUanSE/KePGUM7C2mOlYL5KMNdtzdqJX2xyIsfWaQwvP/N6BCzNv5jOG8TKcj397bXYKFbbCtO Sg+A0hzYotmtyZFdQ7Wks9Opj3vdhY8KrZf1Qyg43Ms7zR2MQe591mu85xaym+t0uKcDt0ZGA1tC G7LzErAPDN1arMdaSlXtqv6VESTmxPjYqV05bI+kpzWiaSiqvBunqjnhkZAjg0UivIDcSSJQ5N2U Bmwl//qGSLZG+vw3NXtIHDmyasmbh7mRLdOuh2b8ty6klX7wpeD8Pqq3CmIJYSkEF7uS19Redcbb a1vMkSHDkwOc6vw3avC1vhxGH/DbMiVl+zeOp9/PoSyBg85aWpZjq55OVDzQYkrk+ywDsxdMzr3x jhbPYhIKVMT9Ddd1EbUKL+sJgcQcLgiH0+htKOKdoBkoSXCtQacIYQzKuDz/c3IQcv9Dw7Gtbfz0 0S5paR0xLmp+VnKOjCG+1zsRSi5n0zklK9/ZMC9yNj4siLKzYM5bs1hxaNclUIxFx5+7bMntcNZg xPdTc9woIBRs2jHgbDRFpSp+749avNBX/xVHMtTl7wu6T8FxeOVSbkq8X1ZpPtN5X7rPGrd3fRix TFIcLpWTTH7AEb4ub6Kfsp3/6uY2tRttiDf3idD0VKLyk1t8iblAHmEqKJiqTGoO91FS116dpymq TWqqeyvEpm4AfDgbvZHUayzAe5ZzgJn92yldJtQWDqPyaNxsD0BvuawFKE4ue/FlAycuXD+NsNyC AexXBKZaw4p3TFeQoWUm/GGe2j0g0wH8chzrjB4mOpVWXECRLzE3NzF/YxtPDuugoJDygi0RkWxr rsdEWx+uJYBBaOmmowDV3taFJ72/3erpaG/izQeq7Z8vx5OSlT6utgQengnrJiA5tqBxS+TL4PbC 78izgrPBTNcBKvpavq4Olg9lZ5beZlz/NNSCnn6tyV7FhzyBzCwyXu5NFOzP1Uf73nm8WTHvENHl 8qg890Cf9heEoDB46FGZITCTrstoEMC4tnNfLSBdC3Wgh1FM9KL641oujXlmZN9eX0q29oy0HNGI 2jNGsIwDeko8AE6vcRMm2uv4GqwvUwrwV19ifCwHOaiK5tQy+0wgrOXsZ5NLkGyoM1mNQLqBAyFl qWrEf/wh+N0dhJu0SVnaD+EZ6Q8IcB+Y1ESC7Kjf+yI1qQl+vd//336Hh+P5KM+chg72ysZ29VBP eH1C6mMuM++ORL5P7xQ0KkPILL9r6kwUqiaO/81NUy/uz4Om8vz61sLmmEvTOVHjBzeHTqOllSQi 74ekRm9CeC3z5Y17g15PcNF09AxxpC6EnpFBvZERY2t6KHt02CoK1LcGmERrbfhJJEglWwqJupML /IFQfc1DZLpBDNFG+3C+1nF983ukQf51A6dAOQaAFniRuFm8XhBNc0eSTC6tGZf7Xewk98Du2MeF osWgMs1UsZ6zVITVu7L8n/QhPjPK/gRU9eiUAxynMDWF1AlL1ktUicndvwybhK+PUr4U0aIn/mjD Z0yKfBUnZXNxB7+T07JOtSOhnFj6qbVpKzKN2BALVX4+P8faWfz5p2umFlmjGWALpPyLfU144zO+ gW2pbVpL/4I7304BdSoZqc0EbTVANZ5sGCN204gY9dFlaORrvixmNStdl/iX76aIpKPS7xEay7Kl J60LrhKlTndmQhp+hK1rsfnrPyXsFBbjN225cQGd9s1P+KEkrMQuE8FIBH42kEVPwV9bPLQlv3kh 7b4HZL/l5slGyovaohUiXs5fiAKXGKcLu6uH3Z7y30gw7fSCl7U1fdFXUWv6m60p9PCAt7Prxrqu 7xKaUHLMZm5LbIhNAKP5emGu2M9mV9yQLZGxeUyxz/As0LiFRTPH4H0bjNIbYSjB1z2ddzA5oWqT F9dsQozioXeV+DtnlC1aDKUsNnoyIkOpleUKEYZYGguJtHwTgnRvI0zBB3AVF7QA+sIlZnGLY2VP 3/9kDAFaVNWSsjXMg39R9x+59RCaY9rd88s5gtX9VicQVcWb/vqIt2SHH2YzOAIYnI+WX8Kg0yoz 2TypkfY0He/lWdpe4WpNlXsdkN+0zMhmnntg+RoOGyUinlK4v2hqTGWHwb+lVHVX+7qXH0GdfPKe sG2QAQi6Tl3xU1XkV6bmRpINGoyFDQ086ElrweCmUYjQcy1my2ObGYhF8e4u45agq+jyxEAPBiWS qHzwRBmU+Ms6jqDnSAix0vgjdfks5ADSkXtyybmWsFgPySuFdaavIpItlYES/tF7hEGsPTQAK3G2 bDEWrg9gWCdVDrABwkLZqBYr9yjFZcR5uubd37cac7doXH5N1TlZxTxBsi5YCl+XeQ+9dBwh6K/V OQJ45iG8DB+/t5nlEAVF+w14HcUre0tQuBAGPkQ3kK1pH+p5cKDtxfnjC4bjPVwOTFi5C9+92j9j 5K4iS30in80+3qyXWsSNrCRHFPa24Q+SY6AiNLFkK2f52LUtVowEgFLXxn8Zo44s0tgrltpf5Y92 5knKEiUFqL6KGD/R6IETXaUuiHSGSIb5cC1iXO+TVXCJHaF2sU2my6GY110HdWuiWw0jtRAtmgtl AgvH9x4bstISt9uKg9Gpl5Xgs9i89W0zH0TUyCMvXSEUxKMFoGKdx+bDBaVWaLXeavHYgXgKw9Yv GlBomKRW7D1IFZtYiGTffw8S7wYaXEKl10xn98kT04Uo0MsSHIN6ZTWx3A6nBiATRjMN5D9gHHAP jQaZysJNMuvzNjMJDwKKpmOgcgQnAxSZFdjj5Pi9Tqq9i0pZOqhxw16GjCTuEnuyrQzEZJjKV6ol fymrVQSAykZQ255EBSVMDu4xD/XybHq5mOQAKqrP5uYiNDkvU4ZCIaCjE5UjsrL5Zt2hdEdb7EWr mKT85bRr0oriV2HipDk+KDREzJ6EpVEir8TH7hr6OHG3oerGGaDtJuFpb+/2DssZVJYyzK7ClOD4 Foy7PlugJsNnagqBHgmpQCayKJaBDkvfNElTwYWwnzNrkN3bTxWy4VF7YVwIoKUzLpzh95bm2yDI snCr33YUfmfqx8r0zoPJn2CYSYYiCA9PgbpuQvUG6ivqkgB1InoN/oYnpeROJi65YmNEpNmV84xX 3xuq4IQSq5ArALjjy6O4DpZZ3vavu+0Av5D/CRrhQwvdr8J9j7C16tkJZJnTssRONM8zBryXPxOz +ecgyQwruS/RR4TrWuSDPbYsvEDipma1pjzpy+S5BAiqCgSyglRlxFcPnV27sJw9wRcz1UJz5TfP HM7FygY2n0LrZyOlcK2aDgszAJ9XY7Wt9YROEil895g4jbJyg0202X9FeKshMNxOjQN2KXTrqlBW tc7EZtIuhm1Bl3Q0TnGX/a0yKThSS5cFxD0yx76XhgWN/0sLcq/Kz1Uv0oucF2PDW4XbXhZcoGY/ 1s9wrWC7bGLcrT0LVG2jZ+mQuYSF4Oxp80WoCEmNdMgOi/HcZKFj3c9kw7K0BFhaNf9mBkwFxNye Ah7nydfTKedXb8Xg20Zi25wUkfEfW117zuu8n6zRranJK99wshy1eJTKN0mb7Jn1E67q4+QdbkHE V/rpwU/KHagz3zcJuayYtAVonxMCNh0BBp7vBNP3bacV+DkbxBffNsAFnfieUl2viKoYu+6QSV2i u+4CATsdjC2BvOI4K97dJ0+P10NtYkn6zgx2Q0QYFfhjDPpCUEK7DPRFcz+Fn6KrYhHK38nYwUBJ mv5BQl7BzWb221DftmWAOxE9jaf0lHewHRvDIwG0ddF9PrRcHK/AJeX5QcujJwLT0dzCIlEUzY0j HXzYhNqcvDXJ0GhLsdvikPW6plrf66iYH7VG5+OWzt+JCw7j35enLY0Vlwr1cDvrS5R0Z85q53Dy n2sb7Jhsyg2Vuuo5oEXEeJNM/C4zb8ouSe3ucKcB2/kzgbWhYoxdo+U97Q0jDzSkz4acVjJxAqhL 2VSK8mfHJsQomuVBrw3Q5Aj903CZneX3swGysIPmMTTj4T+J3R21kRnzByht/dgaufQjRsFe0YwF YRnhiJlwLYK7f074XAQK/697Nan78MFXANKFYrTzd+hliMdXPP8yL4luz4tL+QfpO4jmxzyA0wpz XFx4l2VyZ7Nf9w+JrAS4iW63Up2G18su9IdnFUgaILgoTZ3RYaQ9AA57a7gxHqw7AbBcSMSzRlli 4LkHu51EzKcv2OM69o530H3hy96zOalFVMS2DU9ixhJiegrwBl6mYNWD7VDQzjcyiDosncUlw7wZ l4likPP6GhoiV6qdUfnihjmv9boN9TkgkyF8w7N7beEDn2SalzxQJC8Z4zQzxs8lBYHarrVljOF8 Fop0/hCJkHSpICUfZjPIzvhgnlTnOUijV4+8MgNhIvF70s4TRVCJrg9cR8YzRpygb7to8Py8ziR9 gAX2RKNgFYJ39c1jnxRJoJUWgKE5GqkP/R6HJl39nFCSejZ0Y8dDBOPtEvRzMf2M14ppspUYYlzD 31Bj2OJgrZOtA5m9dHb+d+YB1fIN0nD28b2e6I9F4vi2dy4iebKTyLYUg6rdfRIa9EPInaC66IKQ gNW7SE7XmkxO3V2W/hZo0ySNtp/mnYgsLzjodDlzL8UYzG7RG3b9WXOnxDK/yxQYCt7BEizDXS+a ppdidR6MLxMBJN+W3nHQNsUvJPp6fBfi+w2UX8i0kyVIjA2W+nxvG/mFiiGI2e0cnSN+qVa0BcIc 1j6RUth8Jv60c/vQ4SZSGlqEFogI5bKNagRNfBJ+PinjLlEvdO+/mRnwLQGG8p2vcL6bY4a76SMP Huw5Bd4lrSj6/G/WT/zHjnMKzCCZJApFDHplydRcdfuGDPQtkj9FQecW7F2/jslY8a+cDaHsQ1Ex 6dsctfQ8y3f0oFURdU7VudtfBfZkL5YZDVpLZjYpDDo3RpZPqLxAfBIotmXttcgjSwAp2U47mm3g DO4pVC3/mxmwXQsT2+U+YKJZ55PvBj2WZ9O4CQnhJW4zZO8eDU+zE1pyFFxNVHUaqVY5Pep3ZI8k 7xi9YEFT+yZp5/6ymooqvJsu8GCRVGYqFaQtaMZRP66x7cvBV0abh7N6nlHIcdz3A3UMYkyAnDOH FpYoR9Yt2Hkfy0o3LnOmg3ZagfY4K+Vrtyvd3Ru8DrfBUIjDC8nYUWtoYY62RqOE3zH8QztG4J2y w4jQ4F84krQ4Qdkf9HzQ63OTxwwK32qfvNuNCmj4SFM05CCsxuwZIiBSz8sVuth4j/3qLd/2NAWI UyV0OwevimpTAzGMlV95i+fJn5efWd5ldlTXCmQkuCyEMsWViJYAeW4zUcApTdts8doqYxyftb5a tZm5EHXcUfVNdRCoxSKtCs90ObJfpqqzspoKe0MUyxxfMrh4cOYzep/LPl2lw7l5f8sJyqTeoT1Y mCh4tZSap6FSGi811kUsf00aWP3wYcb1zed1LXajxgkQ7URW5SWe44iYVNXZUH1S+8YyvasDJXZx JvwY5+NcnCgsEGO81o6sJKk4T499UBFsZCcx8nI+zBFZxWzYijaC1qcaoMeN3nTsxICdKECL4EXV HtJxG6rTVUpT3AQzrD01VsNuOFjZluZv7/ByKDNdpzL8hQh43L7mS5PbJsDD5wPJcaMxiRhssFQP Vt4UVy4Vf4VEjdZVYciWHie/a+G2McUjoDEPBupLkj1B3ba/Zrc7pmixaqRJsiFhRZ4VS7UjtoK3 X0NLNDBZXFPASUsvOpYzS2GhUKLQ6BI4gbR2Vi/TE1xY4eXC0fFa6qDuLR/yOsvYPywXwE1VocUI 0KO3dT0JIYa/1+KoYseLwxE7Za8HpvCPM61b8MIx2P0cB0IT24//oKJB17VqXfnazQc2mxDR1EFR ncJfHCUWN43qs3iTbig+c7/MQZqgs4i0uDyhd6Qxo4bgHWz3v+MxCYr3TQJmSOMn/NM0hrxCFGkw hm86KkphMJDlBXxoI+kpTnaMX8bTs7SGk/TEEtK6ukUiEPvoRffyOYnkKGWbr9+o3k+foVgWNqRw lz25z0UZ0NuysQ+rermkDBuxx3xmHZPi2DrkVt47pJCrrYhB8QbWw24JAam1bzEZ7xeP42QtH1ws PV0wXR0NuL6OQQX5PwMcDEK8v/hjmetOiWk61dBdXXktZjXcXhicMwVveH9hnuSJrXTn1yUe0JRI JdMEDU/uOFrEOLC+cRMxiNTADK7pOhHZ8ncZq35J1pdbmhwuvzX8bGNqKN5biMd2ayhfnjzKNQT/ UFKmes+niP4C233TuqjH735W3S36Tqc2NXiE2/LBHKwPivdCEvupsTc2PmDzfJkryy5lHCkPsHch F1ID7MVo1AgQeecpnWjYeCoaL2cb+YSRaT6a0s/68a+5eJ4HC9/lcGanTNZ+xJU3cpcUYnOvrpft 8BU2hS58n7VwjYkq5YHNJ85rOoycSYwHMVbZy1raOQOJpzw/o0sX3O6bKPVQfKEag7qNBuYLjN60 8y6g+ydKqbY4z0v59B/ZfC8DbctV/tbRCiDsW7Rl1bUJCHQfS1v0HUdN/9fHkzjju7oWGmacUJpX vDHXx7g/zU13rCqASkh4Nl3U7/2H2bNe5ZxXtKZrBTxPU1H7InbSqS+TsIv5VIUpaVFh5e1/UyzF 1uO6pD8OtBrt7WZns0GQDxOpJx1bFmXvgy9/RP1V378IUCd9FFOofEOyOX3nRY6wVj/g1S9CD1Yz ULKJTqloZuMgGFadqVmB5SgYr+SIs7XOSiyZ5kVDluZwt6tPsJuyYFvb48mExJ2VAYm57rhXAQOg mC0YZPstEInPB+mPcnP2B3S7g+LXTI7fneXLW/nf5Yhgd03djzr2T2FO7AOvZ0F1lZcJNCv8j9vL FyELsxNBr0e0MYt9ni0xZ0YajX6EdJ4mWvvt0seTDf/SSoq8Cv13Q/93esq1h7T+CF8TqshSzsDQ 2tMnf7FdDba7B8tilOtrdB0goNDGr3sOeG2LOKDJ6oajZxX/Y5SZy+1KF8K6zd5PqlQVlt05wm28 utryHzO+RBlu+hlZ4r3Mz+YfGLXL9HNFBzdIpPadLy/ruDUF1FJKiNR6W+nmXCBog85xFuUM02h8 TsmoaZGZWHa88v+/pxzIbp9jzETZ5LYyVMv7rCR+z1p4K/bVtLIxUjrF1T+GcFJPwdEeUOu9Q2z+ 77+keJei+umujfvWr/UapmmTk85QdgNIxtcow1qnlWP/+P8XUUtLYhiTQf2eXmJhv6th0Ou9Mdqu 4Lxido3ExEwYm1rMmRhN4LyHQwRH2FgWYlYmIls9ZdzIzW5WXnLtNegBvhGEMUJioImGYiXu/if4 88IXuxHvS2LVXW1IMY7zEkJf166KWrRu5oPm8aY1ym3zzgM/Xt57TRXM97ArEpDuygqLgrymiLTJ l8eWCXLM+8/3NZnrwSXWdKx8TqK+JbDa0FX6ibzJxb6ZrSwkcPfbvdkaqVRxAWv7boRC1Ugo0p7o Chba6wlUofpklUmt7fG0ivyueyLdr+KjnqpU5XdCwMawYCMeEellYOvirEuuvHbeXmrROm66uJLT 1ahPLbfHuou1Y0vQOFFvDtWD8pMf5KMVKJKx+oaMjMgDqFtR/Bz+L5hVdKGOz2Lf/eMVKjP2Bm48 e4EKRUtKRGZ+HBeHDq47J0yTJW2sFXT7CTbCXNxjISYrT/Owm/M4pbg5djlz0q8I7ar/YiO6oH5g rCWlNYRfc70rH2j3A9OWQ0oTlGDfd4naXcz+OI07zn707hujQGE6jz8tJ9GagYEAHQh9JXnouBb4 A+17XjeTyApWkZYxBtJnnCdq5lqYMqxNs+s2agpPNYzdrN9Bs1nrC0dmaeqF6ARjGFAUizSbGCXQ m+gCQF6WIIczojkQnmtEfKnB4FG6D48eygZD/2M4oUemoxpcoVEx8TatQROG9VREgyRbQ5M00XyR y0KPSnCLhrI6GL+ZHz8auvD/UJZ00UXdJ2aWePcbWT181WfEhzqI6oR+ym4Eqmf8UiQTHI1DA3YJ VMezKafxbDzxoyDJOupzPxK0jqMFxJsPMso/Sh/1qp1dkqvngeqXS4aRGILOkycQfaao9mvNxz/R qWAWrOXfTOkScrb72e8sJ/2fD4Z6EeQrzHAV2tjIj+uZw8McAuk8wwgAHeXGokhWUikOWPkqLgGa z6Xp0iWUvRDoXOiwM1VtiAJORAve/Q5uCH9Q2QRDat67xeSxWk4AUifv7P0kLab1Ga4sNl/vLlPA ygzMgYaX39/lf8J18dYvdhVnMRDueFJQtOzVQKLrIVUrB6AE5Ky6fZs+NPDNNMr8nlDhUccORGL/ YlKlr/d/gVUQgaVF1zOPs+qnew3q6Sj0vCdnQxc8ueZRY69ZntBwU5aEFnad9pQXqIgYXg6+yM/t DtBST8fC8X2dCrYdUHPs/u/00yq5Zwc47t3aY8Nh4p3+qOuMXwpjlZ7KbtUEoTsv+JpHKStBrlOw YkgEIJ62AluwMk3RJxk+SqJGxzDPDi0dHS3tALmFJp07vSXjNVuMwj2SKn8irzuq8oBEpIIkJsmN 8r3uzF5TrrTJL0qcxzV9/o8t1Es91Wza2NDTIF+PRLvuRpUH1G0wxU3ESrmZVQzfZ9bP11W56lI+ 7sFW3Fz+/iVsBMaOcYlaQlldJuztDjlVgA9guHkIvce6ChofjH3AwTNw5Y4sOz7KQtu3TOmEHrNA 2yFN3fLpblCWzGe06tQooatqwHdI1JbASjfONnIKfthK2DZGduAiCISm8yLSDuRORogmDLhhUofg axa/oORaUh5eRkJmTxGI4wj2QiuN9wfh3+Qnj/OGHXYQ0sjGQk/AX8k9ITtklPOTM3GdD2DDFajw ZUOWQNFuXckNl30uwy7C3/oHwVD6l5lfNG+Xkh836jUAfOOB/Ci5yW5kyFqqNvoRBDlpYzhL9XHQ sLW0WmFuZRrLvZx+8knGVqUhKnIzRWTgpkHQJC5mDG/NjXQyMqfojaCfAtIe3E84tYyfdUbEa1df tvQscfEriPFd3eXdldLqj5t+ZpQ/aiVizBXM6EWygOK/oo7MnQUWT5TZf7hdeZlIf5i4nqDWnSNG ljrr0vO66HpDcI2AHTfN8VU7qERYishf+wQfwkSa8Wk72wJcBBYCLIEz4sSNzxZMi1ZLw+ERrxjm 9tieSsMv2R+dHws9h73k9kRMg79mQD5cWZyxb5IbCA232iHz5QAwOCNOapHRgJyW+hrXRg00QWK+ OQ4XDGkBqJVmdZnOralPXVNYClslXsvltMa8+cDx6DaPVXGuIKmtFM9tNnM9hTpaO9Hzxf1bUZ2A Q7GBjL2PYxTPKh4dfi02ACnd7uPQNystGBEvWFhnbYx8KwDuLyYbirB4Ut1we63cuVqlY7lz6PWd iSZTwUTM8yAj7acoJlcct0aJaq/S2JLbktkuRmozelqp1EJAUTyrtzEMRRt9bVp86RZh23i4cb/5 u5eN5MqQiNWcfiQ4jb3zkHIBlySUGEOb1qTL8Gw21lpSzKQ1gcIBMGuuHhVwFOydfJ2sarCRnmT7 9Tx+KDUMg+YbE63qd2UHVSkGE6kUckYgxhA+a2AsjD+jNjgMpfROqLpglKMlYO494Lt5lRJcrQXJ no5D4Y9Vej9EDGLKd3h2SRkHlgU7ErF/eACs5HGLad2z7S5IU5jL+L4fiiBZhhGoGedMHWnGZn0h qIdeYbyHiChnHHAd5HwbD2hilOwuhHJOUXIiqeCZ2NxP4ncK/Vc5uUkgmBC+aaYeJn/HjmTS1X4G YiiJLjEYAZTcYBG4kh9Laf8LNRMdcCtfXnPwziSq1zTyv/z8TVcGZpgB4YWj5pgXHjBaFoy/Jjcj USAJIqngVQ433eYOhiZXwgE6Q6xpxFbBicXV9+V7+Sxj3ofTaKuBoi1bVsdgcBB2XOkRHVv5DLWA /SHsIePToRwnONdmJSmhh+f8IhBpyZ6xTQ2rssAxWoGNeDIhtzFDKE+mUHBGs5S1LMFWt67PFA8W avTfFhYyjMs1vAOwUsWaRtObWjRcSkhAHkN3mTV5GZFp69oMJJdK6nRmiCfVqmKAzglhMAEf1mYG ewK3R0osMJ4PAYsVqP7FvnVM99xH6GrzlCx1hmwovm8FNDzFGlFp1QuiPIRu0TP4wOTZ2xgYp7+z qA7tbp6Gzzv7TmS+0wZu4ucBLzfS60i10aVjjEXIClI/Ri6hZ8f4gH1qviItUifBNaeEZekeqC7d DydtG0m5HRjc3NaUZs7BmKFUZIwEzEVKXZ3ujGJ4z2lkuwt7YehNio5zPGLZ0LA91u2aA+RurNXC EU0LOrEHCquFXJDIKrmQJgLG5ONxZZ96LhNa4OoMpGIVhYeL615u7HyIsKvenmBKd1jvDIPjGr55 dgGiVj4qyhQkSrptZqpFtpObChx/s+cNd6Y6v1+Dw85f1wEsPqlqZJNul88QP2QXSM8EPhPrpE4L dFowj8IrYXw4foAVSX5S80YFUy6LwOGV9wU+OolkEJzYPMBDgjhmHFl4rqkKUraUatfvn1tGSlti iw2Yxy98ohQQ1ypVwhITD2ACZC4TYyvn4PhSiNI3Z0SWmv6b0mHJ1xa3OUHyjNeUJfXePofAhJJm NWbz9vhWbAR9E6xo4DYzFd+HvyiWVVo9nghkbAEOrTdURnfwdNcToUp7ks1l28g60n7jRIoEtpQh 5ieyou+bcL9VVGJRRQ3oYxAhYXkMNqhBhRBTGhoOwRz9tzsM7CYQNTVW8lGMMfXehacvr9LfMFdv H/IA3Q9wRJI8RaZezCt6U+l/Ewi0iEzLFNCwr0DR0dNILAqHzwrBsrlNeBWGS8PkYVzZJWIsrvuA PgFpkvrBeZNGvKexjN01kCFZWKLeYoyQCp6wZu2GURCKkjBy3ItxzKV+dK0bmVCZJit/1DDy34JN 8XGM/ahFTL7IC2EegRXcRJJrIZLUAmCayX8Sq2/IbgLCkuVthgjuwQgqy4RxTFEmSdit8p5NtnOa 2R+CEoZ/cy0cOJFOcAaqCFAwtiJaRQv1dKUN086M34uLL0CroTGVf+Sl++ThEVckdRWFGeEqGvAq tEowRWA6B34MZUJqbccP4VCWwSxF3ReNWKM6LSaC8N9NRMGrCoyyvm6Zlgj2L1G/YErB21sj5pEB NVD/IkK5QCPmqHyK9Jw/13d7oFhliiOrTXGMG66SIbsMzJRuakKuC3fXP+VtwiMXEAAgQAgczdMO SRgt41s4oVjvOb+Q1yFSz+v+dPF0d4a6q2Wf7aFHUTQKNsRxuYkndwM6YDJZbZ2uASnAKcrW7D4n 16/1XWlxZi9F8Q695nN/6YxhhvqXp44WBp57N3qMr0T1GWTxG0bNSIztsPsHH//uJMEOru5CM8em 61wQinkPq/EDDQPBcEDLCWxFOjt//SkS5ztGcUOv6smgzRxlClhRwet+nOtMeZBAUXbX/OUffU2Q +7IVvnrZW/k0y814+zQcD9SzTwbA9xFW/5tfIZFs+etDfwa9Hq+pQpOoana444EGcbZKb3/OA3Vs D5B34VwRxZgttxM2YDmAoSPf9igTOILaWkA9rKlmp1+1Z+zUOald8rHYA780fiTKGfW5pa872pVA 6G+xN2vF7IeibnxTThwh/uxQM9uWmrOJh0xQT4Ysl1uotIxZ2dZkl9PQc1DaIhCw/1LoGveqwv0A dTJsNveB32kEVipKxjrdPqIO7Wk70E/YKUyZ6pulfDvd9wF7ah3qtCXl3ECe81t2s0gWtidL/JCD XK9Q+ISZBQhwyBVDPSgwK8zrUA3JKbhJrQdmK5Q28PkBCTyWqCOSf84rsHRZTc+JbcB6vRnFOiom D/conmsl2DExEDbd3q8iSBfV1R10JcSjlsa5v7IpKfUWJNqm+p2/Yl0JZurZktrm7zDQK6iOa8mD UJlesg/ik6iVMvqQablzLsmPUzJkMIBx+9SfLxAvAxNFYx3DLRtYEUKJqsMyRkezvuJvw/MZjBtH +se/36GanSRLKYFJyyMVRyY30SniUnOj48AS9nmcj38WSGZCEiDMkrTGyhMdy+0CsRclp/S6qHI6 EU7IpRjYxCnBS+DCB8NrvAYrxz2TJkbacetVTMq7k4rvZavkl69S1yGZLfyrTKcCtYSvlR2bqQF3 ZVW7wZc3Z+rcvmTG8Pn/m4qez6foW8o4j+UEuA28OmEk9vEdTRIDqnUtofEcEJY7X2GCnTgQs5Kt JhCwtHC5lnYruuoUWaDWVJoyj5jZQA+knp+iMfjNGu2Jmk20GP7dpdKlnXKE4hN7CJnPOBgAGRhW hpB1gN3yHZqZVpR9N+FOc+3lGcJ84pG6DUpR1TXuTIu+IrooLUA/ns6FY8+P7BMtXHyiArwP/wjl t6n4BxmoXgKfUqLC5NUJjp+VXHXQ6Clvs3qp09MAvjCAqzw3u1clXOTTRuJjUMSNJjRNF+RJZCt5 3xHsGJS17DXStm0w+x78xNkHINMjbuLIA3fF9fh3IQyrrZ4+Jw2DamncyUDb3ogjsnnyEsg2Zqfx JqssKOfWGzIjrFC65BLfw1nBrBI3f2AR31nsWh1aowNVcTJboZGN0Elu7o0IgIjYHS7fs6ofdzs/ zFbi5fKsE7zGJNlqrWVMa3S1JLp6e74thr1zhrRpx6C3iIMVHTAejnx6PsUEIEadoJYhyjWVBcGl EJLRXvFr+Uam7xWFbcYZ9BeMYMSAQgWLMiuTS3x1iLGt0zB5+zRsZD86IStrT5J7wGry0PUfTxiG Zo9f8HIIKssPpti+GGVHLk4qzZ7LI3zChN8FVttSmi7E5aXVBl57GNVZ/O6JgJcv9WqSIS5b1Cvj K6vkqMBuFD6jHz06fjAyzYJCEqJj6ct7mjS34oDfZ6gr6jhBtCzl71IRWmS8y1vvf3GYeI+KaZS5 M7Y+wmfrraLrYfDGsmKF13ilH5ma/no9gRtkNp9kHhxBg2ggtSNn0sLroYfe9xQOj90cJu2ByJ4M rFgP5idQAFQrdYD9UZT54B5kFo3D5c55GH4BLcYycV+lYE5OUUJ2TDxvi6AvMYKftuMfHzsmQQxL 7Ryb2GaBGrqRA/tzawsUfuA4mf+ayew+NY8FWbm9Zljnjqv7hJwo1/oVALknQN1MVoKRJ5NxuZD5 kaToRdaDbUUGe2I68gnDwiQIDn3yNRPRmAUw4T2JBaiDSTNyDv64WDblMIJB5tOCLFFlKrSgNxlZ EOWkiwUA47PMIhSb1qvdtCLh+yxaWSkrUq+iYbiUMz67Vl59UubjYLcWcFv6FC2E9OkURsXmVoHY B+zrgCirePj10gtAROHPGYra9IrewPdWl4JIhElDvsBgcVxCehocyS6DgoAMFtvgrPFVYJXo6iEf 3jkzkc2RFsOVNmc6BEhseeXXlFtN3ZeUx5tpaeAgzV7/ukA5XOpRCXYSuPgJ9OlCHtUcBclcW6sC I7y+AcpxY+Gm9aEx1okAH5eZiBQoNPMu31I8MsX3UFQb2Ni7f3t5bq4y6glA3JQotEGmfQUwjLCP 4LA7yxOsUCL9mguU3IbY73qnDi76NIoLSLqkgKMBfP+ju4oEEIqy6qUY0Ntc9CtAyGqHND95H4l1 WKRytXiKw8Lzc6V+JTd2xrqA3ZcHy+BcYKv1jievEtRqoB7IoK5Syz2u99LrM2kFAx3Bk9GQvQX6 YPYSC4KVu53Efz2KdHZ+ZrnAnXYP4ccMqshL3LWQ+JrVSe6ix5zW+bMl7Kz5rMwj0yK9ER8UWqAo D1sembUWdnPAnmKoOY+FMoqRo7//49xe0l9+lWsQ33x9dyZbnEeAhwiBkAMmyxOWRdiuNUuIYHLy BrYeCy0MqCyFC5jcUT3k0KX2J4Zc95+q+tWHvU37YqnP6s0M23+ZSWnKLZO5W6esSNwrr1dCzklF gTecv0VH+mG5cQmptdDl0H3KG5J9dJO4orpcYAfY1uOj031SyDJmeT4EfwJokX9wI4c1JYV4HSVV xlqVoaZAm7Ft/uNUQ3dT4YNwXyiFxEP/N7TulVQFksabDmgPvycCXesA1qT69ZEg7kdtm9oI9aAG PUUaDv+pZ7A0twQooBirbLg0w9w9mLpyBqZiiQ225TSAhYVRtsVU3HQq63ezngODURoEGBOBphcE WtzoApguXWQ+WaqaMCqBlV1+YCDwxMob6ts+O/B/+XFLSPopGawwtox3SpxC1NxSOmXn0sMx7cGy tXVeudWgO5XZTSJR9QJtmTI5baHr+F/OxWw8XUQtCPIMS9ZpBIikZqX43K+DsZE3GrbCm9kIZgau NFdzcS1C155VsB2JrHz+h5P9ZmDC5t5ko7yVTjezEfczZHfOxUg+0sKhvX7+yHnCDmVmWGrXv/TW iXFuMiwfjh97nZc/ftjoSFV+mov0lkg/0nmAVIjBVTK88cflW2YiejnAdhwdlM/4K1MUQFI68HBA FjvO31s9Vr5G94oGikic926pOluOMezgT6W8nyWROs7N+zepCJWXWter01tT8eMOVcNbt/tp/dQu sUOSr+OxmJyN3Hl/XEx3RORqxcgj4Yr8jVpDYliFY97PKPaTfgBBwvBYTwzDs/ymutfWzPcPnLhB sv/q8DCpgsUtVX8vKAnET0Hroq8Q6nMv+MAdO2SMySbYs+MP2jccK3t4/BuJlXlS39ivtXLQBsgB JwkOSQwaL9tjJXhqfuPnLV+ieGdmjuwQCWo9tHQRAeO1H3NWli1BUBH7UrjSOjh/t20FuhqkSGmV SAevtB1qAkkG+P78w/Al1Wqi+fCldtbCtUt6FUsxUvPwqyLNkRTzWE1kWfI4KNWQr2O9jM4s7zj1 OK0lRi6bsNPpwfmtXI3GpsorUsSRMrPsIy9crMN3aZdJ/Zg5cieE02VcvmFGd+YaUdzHujh7Y4Rp NYtzwCaev1HtQS9Jjr7vGXJXaTZk4rQh9EenZW7M7shnOm/rVKYoU44I6eLA72ARJgsOjJMWBS3W T2tU0cIxFvm+YlsBCPZELZH48kBSsBGGfHXyxBF6dXp60noMBeWCKcO49oT3QW1WRWLvxALnfc7R CYtK4IvBqB3iki3gXHjDxj9b7FYy8lije7O84hn9erbsCNzzt8W03NLwAAXJLrec5ZSFid5O8KwD Wy11yCx1CY2SO3EUBBfixCy8E9HVju2AKERGzde6aJ1cCUaAg7ap1fqL9lrhptm5SsOo5UrcCs+v 6whc5BsvUDs56luSn7u1P0L6x+OkiSsBotneNeeNa1hAdNr1DB0Kzfde9PXSxW4zBQef/2k64+QI Akth5GsfuP/jhAnZ3rSlatJhGAZFonnMD0q1/XpiInjXMUOERz/kojoyIvKmLqqRf9JcMa5brJP+ nl8lccgrrwEir8VJndgPs7GoxJzEW29S3SgN2hWBZz2Beg1uYwpqz2Eaqv8s/iAAsXyMkXS208P3 V31MJxVdFaxWGs7a0V4CyVvVGlqXehhmSvHy03CLBvHiGxxjqg2yz+76ddOsOreuzVeVO9kAs4J5 yMUO0eF9Ivnigk7WApqjvmm0UZaKjhKaLC5cIU8/EKGsQpU8lLrx86df8FK/Uj/saKqHtCn8Xnhh kcBP6+gNphpWUZVxNp26mRK88MDxCL3RAAEs437zk1+lnpstQ025v3mTINYdIS1IV9jNgC5wh2Ji MT6irdqNMkQTgMIaqjHI84WQzRvDihPvQMY83gHqelaDg2OmHrAt9+YmjFZmC4ay8IbUuT0XQByM mxDtJYGTRtEpY5nGn7T+WrxLp0d0F04OUEdPwUi5cammu603y/XIhCLgDkWdwIfRwiD3nopBSc1z 1QOX1EgHOyKKvMBNjJuwyB1hpiUehiia304KyFRNfh692hAPqYUiaScVLOsy5gYehjAlL6QZuk6z fPwY3me5B0lQTUa6J4sYV5kcJsqT7yW5YzYkTdDbakIQib/PPpXylj6dXo5aQFTeOXpmEukmnLfP 35LINzD955cxWW6L2zdrHgSGLYLeeHLNBACDeryizBvLQ34pnhq5vzDkyYuxSuJ6e5QghZR2aJHs o6d7JZijKVlPj3ZUPBbLjVOWCOx5mHdbWbM17iR7ckukKGwIRz5Pg8V0o6Aw2rRGBTPuYEzMTWv4 Ev4YAiLo/BCvn5c769ovE6/hP7JDMBrha62Nw3LvDaNXs22tfY9n3pU2smpMkHXtaNOfTaRB74qt UAO91EpmPcobs3M63Z6oVVOdVItNlkJByQvdYdg8R7b71LthojuRQ6omE9WaLUihNVnXdHPyKls0 CQvIDeglDf3JLVMfpUKaYxX4cv57sQ+wGCku2j4v9dc4oXHGR/UU7ORi6wjR2yE8p+dAagR4LodJ 3MNAwohc5kn9nRkabbHBIrXeBJcE35eKuF2rWUdRqTPx2Jzlqn6ZB5TlfT7/PDZSbNqA0AcXcXg7 43X2s81/17XGo4Oh3uzMXqb90G2E4XnFyMZfHVNYey7up6vQtLVzbZAp7rvyzVNynjoU6Z/xz+QP /Fiws6r1C5rEdll1Gif8d7HD4OasOU3Q4Kn/dr2bxs9gZm9RwrYeGM92a9AmkEetuOOga68E2ZEd CBESSmkWvPipLl0ObOa9xoZmH99cMFs3bSkKHdcW+TRb9E5Hg/Gf9WSP1/k8IDUmlkBSZWIMzy1a xjIr8CNAqZTSc3q/EDkgB8/m+cDdMtnG8eDOMm/1pHyHHFiSkOQqr16e1HQ1OZb2KAuyaNFP9lRf 3ALP3L6VXar4uH8jFkwjdXEN6FW/nnOVyFYUzQrpa9NSMT/U1n+Ku/DcQkEetgD6cZMvxtqKQ1Ql XnmHutcW5KFERtP2P/dVgLYcSb9iR6Axl+j0gGJRac2Dc8uwIOTt59N71Bte5pqmDav+4gRB+r/D pnnGkz8G91K2EnfSCq9WVAL6WKW9capohvp3eP98C8b4GJnUDX0Vl9PkF0qGFIW5jc3/AqXYPf3Y gmVN1yf1nUt8Inm8h9GOsLi8sWaDjCeOxBnCAt5jd6kuyGoq6l/0oQVv++GWFsErIQek+e8xLdnn 1mEVLWAOtQKE/1SDTZ5PtdsuZCfhN3Y7nIC3AIdy6/ml7QhT7xy9BApOTkmXF4E6opOhCzgGc5kH /tFKHhV6kBUb15YEw/6TlRE9D7i5yqizqmoLKDdIVSr+tlxTqVN5Ek+JzMRkoldQGnO4d2XiLx03 pLm1Y0WZu/2FqJpUDa9UThRU/n/JPaszlmqwnQWMlNy17Uw2O/JIW2TXByXy3zUVnfHN2O9Mirp9 N0cmpjVJFBzL4GxUg3EyHI9BVLBuNETN9rwQlJvOD4OBqhoDniIbme0NOKHcn3r1vAkgIgWbhw0F f6jH+MXVNfxjciVukX/TIa1k7vxMisnskM4UImzHKgJU/GGixJg8QHcR6FVEQ8xifGoav3pnBk4I YKMh23EPJ7U77KkCYRP0UOEtVjXNQSZ6BGtr6I6epD6H5kKPBnTOk+AAif/fcLZ1i3JaP5NAeC8Z F0OgEf74Z/Hh0JBf1wmeeeHicvWQ+7YUjZI+kYaLnJxIDRpbFjBqPouM+C01H03TDrPdzM08nhOg ZgSIzA0hnPT4PBuuxmQJo3IQxHOtM525gZ5VWd70PLJH4I3GoyYk7+RT9nJZS1d6rNAKbUxWRzUB mQwr6p4dmDsXwYiWdZoiMH3qQdGxtkBiKpI+1+fVd3oL+puLj1APgYshVOW1kueErPXh3ksKT9aJ v6dXhqY3HPyxCx/f2KfiVoHomyZ4WopCLD8DzX2oEl9ySIQnhGrti55A0Jlg/eWwA8mNfbC4k8VP 9Pkz2pyV4PXvvwE+bxdtuxVXDE0E6G3tVSXRus8RIZ2VljNW7UJBl+dw3k+yzvEB4u41mil8cn3f TIyf6bmBQsS+Z0UYnsPWjGSB3Yd9d5Q/7dpxIS21seMo0OijPqHr6P83E7u90MPV0tqO4DJ6Q2Th gdsJDM/n/9n1LX86Xk291XJOqDw0AgrMC3Q1/fNL7xswAgmBs999hYaXYUr3SXEkRio0js8vAb+H 4hIjTBHNLrDLfsSMZacKrdajRYruzSbEJaEp3FWWNcbv1l13/t+2e49L1gEGwJYe0pXOzLcrTj/Q WPhdNE15a/+XGubjvlnz/lLsl+NmdOp8sHmUuh6TmZEkeOqRfWophIVg7PUDN9JHrhPbEKmDsoFm 9Cc4mliQIYYz39QQfAWBRKxdvBlpk9TQeG11pu0wtJjP+fvbxVLOXEpYqF9FmJEfL6l8x/454PrZ kZwQ4ddf+J6cxde/67Zaqj9BkiYD2jEJMLPVbhEEQQkCGsOHwCApIPdd/cZU4et1xKINj7r0/dE+ colXLO9iS3gTmF8tdDD6LegFEGYa1HC4V4BIRbNYCIsB3ML5YxjN6QlrrataeRGWjG1zBNYqMVSJ Nw/Yf6ECVnY/43qxqPxKXdfEMaFoKrs+D5JXUHvAmI8JmN9NC0KvcQv1pPqi4d+pWZfdiLRhmxRF 1a6sDb7czmJqAIry5kZpF5fOkC4r6qmMpI38i+eY2pP1qR6H6Rb2glUvIYAWRmxN6EbWxJvKxwz5 r/eXmjh4W+iO96/EsFIqnmgw5m60+BzaTrzmN9WisWC98T6/iuqzdPaHS4xc1hMppOYX7u6sYdnz 6SA4OLnjl/51hPt3FMaaosTeZOU4u8wWhQs3XTtqdEjPk6sTiHfUVslRf2YnLWYUk9ma0D6Mj0AQ KvPSLaaOebJtehZ1KsiVbDv+WKSsoGhSlkZ0ZJ3Y07wDccmYifZ1JZvlIss1BrSatksT5MYrX8uU dvWQ9xkCT1Iz+SSf/XBWzqhxVVE7IvW5axc/3TX7fMdU1GTP1BhUzYyRGh6ihvr0ir1w+4GIN5XQ Fok7AJMlYiLLX1xJdjMJq0pmlmIuw3+9ZUmXYrqOtN4cSMLp5xzH//sZw1juPD6FNsw8TbhttY3B tqfFOiFcPVwXlB/+p7N4knw0pHb2k8W1fogiL0hfkBlW1DfotdoQUy8Ypb3f7dmW0kTLkAZ4y3gY sHLp5vhS0T2AecgHb3BCyKUmMLqSxoBvfK4KYAEc1C36yK7dDpHRoaQSx7wbM/WyafvSW++BAMe6 DHkTfj3572kJhqpUKQJnwBVT5eNOzN4hgeL0wNqrkxBSfYEi387g1Cgpr6WvVTB85zqoW3h4Ks8Y Eb7M9XAPxExucHOC9wGC/dWWraHiVsSEwyR4uDFbbpajoL1LLRtP35uzAJDXMejFjHInJC74mMDy Pyiye3enTWWQqeNP8k/gkjgcHIoEHPJULAAZSbYJauX9RwgIM6FkkzVtbb4t6aX617ES4DE1aOjK +C/r6MGL4oLZE+u94zvxmKAu0SmpmC5B/LDmXRyUPNq9zPngqgjPGfNNtlKyVv9kD4PGKPu5RoLt 2qvCk9biWhhgXWx1FTGXbBtsgkd1lO82dG67jaA4nTL947GAQM9cSGdDLCvCobly+7PnAg6PL/d/ ZHvtEdrW2/CqWJqcQ62+2u1aJv4X7SzYN5N9SF5TR6H8e58ezNHxuZ9OuGOHl85T307D4ZB/T08Y XV4eAlbAsKLTya+8XUSwHVCFuWi+WH9Q+FVlulfCh6hjm1425gg9gfV1CuVokS93wSsFzIbcopl9 5csI8IT9r+ZEiMtE2x1G3IaiE0++M92+DHl2g86nqsXisGKwnDgDO8wSaazuiL3yQKF9MTWti+NK z55eaehh61ZPbx66OcD5BLNgAOlvpmQ5eyCb34GZjR1qSi6mpp/ITycOnyIDgrrhrAVU/Jn1XOp6 LG5ZQ0saK2MhQ7tR0FYEf/E+SJZ6E9ojT2rDf57r5YBiH2bQP/W60FrkT7cvMflSbiCiZp8K7U0J vFhlaXgYCSge0AYCBl0HtqR9tBDvNStGDLWrwbd1SFIoVbdtJOtvrDXv3vU9QltlQSaFb3+0Ln7d 6ycHxd4q/AKD71MF9x6X7PagmgmiFJEbIpLExx6WcAyLfxoT+g/HQYvT9rgPqiQkk0uwRskAuy3z pRDaUPJyxAGFcKgKDOoNpPPhhI97f3jXKyQKBV2e7jtG5nmMcdq6enx1mbDnnsuGXsnHUM+S5Il5 UBrLm3bDLAwWTaQZOCc8qQ7K8lchf5B6IFFS0DF6oZoMfTflTIe8uGCnI4aXVcQyOyr3SPhCCpZR qDX/a+YHhJbMq4PaCbPDNCK+xpVl648RofD9e3SY9Io76Uv0+uO4LxBaycPqNgHoNuN6wzMY/P9m XVeamhsVuP1y0gF35KU4s/T17KRTUtttt6wOChvsxs9A/iEfT9Iq1+VVG2slpksgg0n3NYD9rXJk V+d6wGnlt4dvXUsO4XR7WaOmhCzAY5VMzPix6MauOLWH2DbUNxzYVzGzXXdWFU6J5+tOQU3nIROL qxXn9k6YWMtZeOjFGxId2CaezBcLUfv3oEIC/sJA6pRQDhQP5tK0AVdxRysrx+t33qY0D2J/znZS Awskhqhcyq8r6qLEvtN9Bk7/AVQ4FRsMfFgIXs/69kdF5fomoSUMWpvmNPNb6A1QOUMyKG/QnPXU z74YHc41vk1Mss7GLHAt9MYg886hoK18U/OWowOCLgna9jLhlinsP1SmF8Ze4s+uLdyzsaNJWzN0 7b+b9vfc/fY6lieabIlHyaX7456YCyskVzE2+dJ7S1J8ahQtMAbb5C0QBY0i5/UjbmKszCg3ZcYO Kdy6Z2No7JOnAbOrIesT1DtqcYz5hlCHiKBPggZhuc1s9YiNgas3UCr8l9hV4h9fIf85X8C0BTwj DqZSuTZch0X8JqeF72QvfFg19Ql6wmWuX4RsKreh4DYW7NR0svpeoLa6o8xNIBkXDZ5X4sYxoTX+ gyR6PDRzPtU+swDbUcNhXVuIcr7hBtRIPzrHkQlJkB2SCFZp66Eo1StJjLYGr4hHxPCWPYH8v4CV ihkQjLMUW/Zg5zqFNfeqll3+sFyYKwGc6vOzARD9KbBgqvtglOG/jA0rovGot1tzjLWo9ITF2ooM PF+JbypHfannVecJYOiPJFfbn+bpOyerpDHU5PqEq0rJMMVc8ZAtKpb82gqjh6uWjfYV21YTgALf LHrng2V+oesYQI60vGHbhryv6fEN4IeFtCFmuko6A4ehUlEMO3Cx2s1Ut+2UZz5ikSMeK1gQe6h5 pDHJfpf+DquMRIcLPGVP8fnUrRisgGcYkST7dO7EssI1+SvTYBuMEiK9UA+D5JsF14a0WMz7kATY Qk1UJAXVZJdekmWaXryX/0lOJ53epj/qf5AD3UWndBuSLgdW6YkGaBYykZ/W4NqUDn82Eyj6S0Rq TyJaoz7CyR50zTx3z1cQBk4oH+mYAsD1eUH6nFploqTBTlgVgJjQ28sdnulP8Lgp6et2B4ikAAr/ s+9S6+8HfFsXb1y7annxPB9yYkKxsSdERtnhjty1e9MvgVr0ksLvWirRgzb6WIHbyjByoHWNO/XU S+CzA2XJRzvA8M5I7M/cxTVOS7tjOqQ/9gtCX/LJKizLM9jBUnwf99vPSHPBR2S7fdiPwWxSpUbK bP7pP4y/sBtZexvIHNRnByMpPLKjhW5pgQNCGQ1J9301jo6lvYW/w5biRd8EBpATyxKOTvnsqAo2 wpWPz4acYMrIZ3t6RKWja7uYBz2868XFHfVlIHNJfAL5MnhveYK6GWw2+MN680tl2cJ+lsFzR3mE PyP1NmjAtb8ueLBev1B2hUGgY5MnhMIp6hJRd700YwDlxpGw6WK7zkpD/moiX2Scl5hEZf9IFtUU VAD2PhYONIGh6/X5oUDCWEX3xHb5G61i4zKABbszf3dzvVPyBIVSy2botegH8J3e3lVMLfDMEQ8I GLg5wb83kTEuNJLglzLX19+w0VMcpsXOtvQYqt+fmohXmveGMeJfAj9sEl2IcUEA275cFOGeDftG AnaSTEa6p1QBHDnT0516winy6MnHmvaO+J41xE0hKtBqJzhvMCkDrhyZ/K/1H4fjN1Lw4rFKwr5O XSwMhnWnVs2/55daw8cotH5ux05TzRn6xv/xXIPNNwahHtBx0f4F2rpAV98iy0G86qGoqI/1ViiS PolPGVFzlNWrm9qTqmk9TEEziYvvTnOxZs91A4voTHd4ASp+9SlikGY47ugMeiPDdXIwrZXZOMce ioZ29XD3aC/HaUpkVgP06iG+p8j0JDYZ+0OOWy5t3J9u+S2z5LOQ6dFAniQ8I0M6igFTYBXiHqaM XxubYrmMKecXfK4zvnR9GNeBcObhqoa3VlGz225KteVkI3jcQvI19arkd350qEw15MROdut97gMY fFiVT9U+V922K4s4EoPlwNfRWSEtg+U65Y2PjS3YgexJwASZLwjjtY456oytFhlCXBsXp7541qSL zrOm/4ZEZE8gUB6R2tqaRoc6iCA+SgwFS1QejXyo6ssIOXsoOrn0glnIflffCNuGuaP2S/iIp6n9 Yshqn/slgZKrZM5IyEMcZ1xQTcznu2xKoMd0Do0jF9CB+o/Bc6L73JfnruCdDD0xCGZTBwKeJkL8 9HTreOecCHu+vJIcFVyme3SDWMUn0JPB814SsHhP0BeXOUn98jwpzgMAAZAF+QlNKZca9WkdZBDf 0ta3/OG0+Ub3EI8nx5mRXyf0h/mp5lbVmXafSI4xVp6X8/GhYZJnsDHf0vM0Lk8R+3UIzRATOo7z PTe0knv7d0zGeAVoCAghcp85cB7DFqY8uK7kqaJQBjw5fB2GCQXOzjvu2jic09BNCaAhbfNHP809 PLYjESu77sNqQYt288AiU/Z0Ul5o9y8arZoqp1SvSL8KzUiT+hqMUWto3f9pTZWebiMssxOhflwI Q1GdSdtJ+46k8F47TF/J6kmzCn66/l6a6YMHmSfO3P9iHsbaQLEag8fLxm0sgU2qn+rO+4JhZjfw 4I8KzNm188aScy6dHxQv34UVlasIbyP9UiFhtB+BPQia7Kts941KW5WyRL0tkH3ZYHmEJhaz5jJc Aomc/udYHOX72/AIlFGh26QgQ3i0QOotSQlCub4D0zxcg7c6h+GPLuG0R7W27ihW0jc7q931Q/zM i0GGef7jk0stJ1jIXv2YcuSq+ZT0JAfAQU1/GyTCz/OSHxWyycUXkYM9pvWIbz5PSt4tPrJXLlat gGChkLXtQ6fGVBkanktRUh56xDzPvGNwxHGg3Wz2TU+5ppRPUPZxOKiG8ht/VTYmnsoi39G76Awd TF94bgLxVGjI5sHTKRUaESzXMkXBDDOXaDxLD1be0sC00tqY9Dm1ro+3a11f24BtGi/KoTLS+bdO qlIO3Id+i4KFtVoIwJsgCrEYrMfEFgaRiaw+sKp1xbkh9IxOZTniRwn0SHpguXReKupLKwpYu2N5 66p8LG3BJfZrhaqnzIYEv6tipdk/7ljG7o7xA9Bp8b5BL+ukAlsbMQ0u/pofDe4fMMAf8+uyE5gB Rc2HoJC8MIWZTNegzBf77IzYa2m43ZRudYYi57WKPYEY71YgdDD2XmcWW+FzP7dKaDd0EoSLt7NY 8kU1+8mCA0P9PWuoXErXgEJKXTgrV1OloBojmaPrAw7WP7SW+Sqe8uSEsR01sRVnOFVtvklF7ryH 5OBvdiBnfz3xc5Uj89bbCusfnVFSAMp6NQDZ6wsya19HOl+CpyiRRvswb1E1aWMVABU4yCK198XX 2XDNLhcghkTjaiMgA1wqsJ71hvCk8N36AzynoRyYBj3v6BvjADkOYb8NcFPk+2/rdYQWCH/yGO7j wXLqk2z4JAH1FDgzsEMDKqm6icHp8i5tWybXUxU5LlmEKagjatrJqxoAWQnsxj/ZlNutuNqJQ1zo uu2zBBA0Edjv2WAF2Zf3YYWr4E2ZNGwxH5/regCf550aQlXrbfLfjGtdeZ2iJnSImNjQIeYPtY82 N2b7okIJ7X6TewpHFzDZggamZiM2fBER2/miGL+6ryWsr/rQMl3MVTZ6wVXe/HXmLUUxFi2Q5+wv NoAC24TiIGG91MGZ/g3fsaAijN1OUoYZfC740qK8zYS10+vKxNR2ivoY4hMm6eplPVsd4PYl1Ag9 GCXMmCIktUgGRkmSJ+2GmDmlxTk6xF745V1v+7pj15L3AYY7ucciktNBFVfMwWdgNptj9MuFvRSY y3LAXjpZcT7zpc5jHKQDI3RlSQQ7oW4b3+xxx3PQRUkQhiBgqOWWlvg2SHSBvM7FlN3xLvVrbh5g LQAnIQnC77UIL7LPGXRSg639HFJEj5PjCfUO4x5PIvDQ4c9VDsXZPkQUNSPUB6PcW4+lnqhR6ESA QR1v67K2LNozv6dHj0U0P4eTroGAK8DOVVPDQa1wAx2vypPgrByhucMZIvEPFz7nUVjyQdTPwEbD 2+dRQeBliVcPiGR22WoBk5LMzQI0xRjNXm74hcfe0CND4LN9y11lxk0hx3Qd/yW3a/C1TxQmpqHC 0QN/xJuO0sNWeAI69FbiNS3mjTFLzPl6DHW9AUy1DWYrYJCDTTfPqt+6NeXQcLIk+OIxPSv+f+hT c3uzIfsdrU/pxQzItojomUl47jy/WWIC26FHxK8QDWEdWev7iHYpkIfiQIb9OrdeJXHhZBj9lKFe j4KzfI7CHLkJfmF+7LoQDvrVSXqJS0VChRfAnv/M2ev7bIHaQSizn63oBX6Up/ZbdTuiBSr4bjwc cEHHXuptf+VeH8IMVBpdulolRvqRRVkE0WiDedhwvOzGoTuVjx4pJcnIzxIUasLyCxFCTX4JLZDU +OhN0mgLTysppnvigCaY4ys18oi1PZ2hI7D/mpL5mC7wakivtTHFOqAwMUwrHZJxKU7wAQNv2w3E tp1OE//j2KsvHGQR3VlzlKrGyhMZ1/U3QZSldXPeG67j3IiCH6Umof3BVBC4K3L204rvINX07y5b 07w2y5PbCXaffQGiJqcOP9vpHnu9C8CHXuuIe8lHMFK891CkgB0HKglIsjbi1JXiOKvFQ75iwgko NrYu/QAvfsXyTIKF3+hZ0qG2SwNBn2ljoJ84gJIOJb56fFusjlp5HtIgx49H8/9oxCmE35g6W1II J2/wx3LGmjcd2/ltJuAqg5PXEQyAkDNuhnFYmx4g3L3MqnJVJ1lHIemY144PrAEjGgKi8uINpzoQ ZG6+7AFE1IBN1OMjv5e30eTS8zlcd9qC0D3vMWtTYEPMLUCsBQ9ivNDOBzeQsoGpc/nAcqszvHd/ wvMdMYKfbX1SOeSaD0JJNmfkCB7v5H9gPgSBSk6HVBWQMFTj1XV8jOmdXHUaDG4yJB/8rHGiWIN5 QA6dzW8ZL/ArpiPUAzoztFoRSCo2zum/QZxolLQrtSARRqdQ9mYrq9DumlnrbMj4E3zwPqveOHIY S5q1Waqic7VirlSbiRFL0bU7FI34nHG2peb0UM7WPl3GAR2skicqDjgFmpDqfw7ghy3JFn32dS5k MCMdmOhboB+vCrcUwb65fauDY44awKdYCuFlxGMog6D7X0fEE1ZZymaN7mpG/VGZ0AelOpNREBcM JbPnS2L47mMjcQcdd16V+Ghx5eom2BofaLJq2G1zeP9NctxlE1RoR6055R1RUO3rZWHISs/AF7/e yTkGZn7vgZDxr/0f5amw9RiHWslsBMxhHF5vFFAGJ07RhsvS5sXWCXPoEe8XpVxK/snuFs8VnvsN ne3tfOzthw9CaLi2jFun4mt+T9f0ZaKaSbyUkhRXY9NiDX12rbafuthjCKP2DSmY1ehatkIDFJpB R4r9qJwDrIMK+xKCMiuGdxNcrsvkIwJqd4jZ7Jc7XTidSreKI9Ro8AoJM7tRfITb8Z/IAjF3YLkm f0EHJDVVXfiu6bp+MmctLTblYuD+KjTz7qX2YB/4keNZ8TDGEdclXrqaMM74jr4Qw9Xl58PY44mW 5ei8k6X9C1+P3mLJJvptjsK1dFO7vA0K2pYE4J1pUeR6BZrp1NUJ+K7cWCOYdfMRca3JrRvKH17f UA4bb/+FXMxHl8YPii3tfb0UfKYoODm53irCsPiNnrR91lRGNYc29GLzRm5GJUTC+Drel38O/V4w XTFdm/pP+t4D/z2N4uEEYhRanZsVawaLBG21uRQn/UM1wc+AcFaOJtYb+bGujvRJ5foNJ8qlWylj L9+Y+ERdSpmtC/damqXtBhg1/4NMbHtlPqqb6UAT4y9sNyn54uM/89FhMmWCPmeW/EWayoL+pFYH FbrOZPPFgfQ8hhYOvpPZJ/66q4GoSXH5YZ0ugQneO3FzsUtfie0RO7aj+wb3q7rPvcejGcbxMOYs atQJJkNDOiOnEgtTPZg2xMUrf0K3ETbzHtZwgpCvXg4Vd0067epUADCLYuXgbvYIN+F7fu8PiN4+ JIEwazPfLHspHLZl1NI9bljp5TPJk2dUNjJXv2+702YsFNECaZBLuDyA30NGJATl4yyFB7ay8ywC UTh1xM/oiF4nQxGKFSrcNVWeoszcv714Va1uvjSpKebLAWicLUQU7o66Jfue41mOSI/XWPVYnxgO yIW//y5jhJ9IsE0F1z5HNpnkehZXX7UBOoF6vwhPL5gfH1jG3HO0fit/5rP3zCTRkWIJPeRH6cAW MGwPjb1bfl7GMmcwEb+yqLawVbJw1QBpsG7cVVbU0ERss8MiViP90s08/8eOUwwkgBea5dkRl6p1 rGfMbLaTvD8jEBbm2HI7JsXGkYx9dEWgAq5oZneUhH4CZ/acFU+kxTsWCTchVjLEKGrzVagh25+P 9kdQH66YSuuXirh1KJbX3pK1DFNUqhlJOO4afKLfRgbRdHKtWEXR0k0FPA5t2GRV0sMvTKkJmmZE CDqOvC4yVib7PnqebdIi3cyMZl5RxH7qEBZ0lnhS5FI4UXnFIBJwPTS4Epmuw+RvsRDfuL6ik4GZ bDK+tHvqT4NkLOIEMD5fBlOxoIAF5JTiq1K6tsa0x0xMUPwUtyKaI/03b4/kuGDHqTRfmfSCsBF0 NXApy900CtUYFx070NDNZJ+uVq8R1eZduX1iHsdhLozyMwBGiFYM6VnqnhKIzVtBiRlDzXMtg+1O WuOMrcZHg2IIBKnu/OPXHiFvvcYL8pOcYSBso2S0bwk6mg+Q9MiF099IAkQ7CbcUB78QaOTLz9aU fvffNJJW5vIGpT8fH8N5ya3rX4RxnSTfKhB2LbrhbZNgjv7owtCnG6okQ+14h07gAMQny/5lOh1G CuQt6dd1KwHcUbTmCiGUXlrGsoKKxzlU5P/ab2Zl01o7P55YTAlaSXwgBuQTgi2ZnQ4g6NciM0QM g7AL2OOXkKKADNS1MXFmRUzyiWfInk8Dr5lYusxa36JAhhTs6d5HcHPylAArvW3HBxul+Uz0IbLf mXuZI3+lPgeyYEC+ttIGpeX54kk0ridxHqDQ5splSiPzEIx0EhZeMrw79IcPV7nMlU/eMNCIrwHs pfXqwZ1kbl5yRD0k9OywgOHH9uGKUbHMS+nmqSdBDOCR3HF0N78/0ot4dCwONquxIcHpwLaWgqBM Oi611uQbNoRtNWlyqwmxF0kagOZL1b4hWbWJg5I98gDz294TAz2SbImR/4DJLuREbtyQ/mZeifW7 sj1lqi0coTlxDHVoxh0p0T2suHjRMQFPkVtnXF54LNdPHztEG+5az7jY/1VkiJDW4DYWv0sPIhrX gGrkiUmLQsaS8QfjSqbKsDGgnvN+XkYQnu+Q9LACIru8ZcXttSrD23uM5CZtiNnhsuBmpzZfHJSO vBQWis3qQsvauHCOJPV/YOB6XQMeRcq8+O43paNl1TVXnBXIPMxfW2cveYLHh2mpa9Il4S1j594H LtBYsz+1CXMjM6kVdfmM2IOz2ZUBMtpCXXzAL9faoJ8dxkx9/koeDsUu/EnHJsGsPIG2BikXPEPu XcT4qFSSsA/ajZc01kaQYqPDZSINy1zZtadj968BEJI/xCiArTCwivx7wp4fYktvxJpWp8NtQByL IfPhSGT29N6EDcjLsMci4fo7U5z8GE7XhGEGaTbdEMyWC0rRroK0AiOeGC81miAmrraquvSlsTgs tnyK4E/1THGrLsBVcgT7FGT7z8kE2G55/8jpw+nfTIZPd+Jg8nBy5AZgYRqnF5GlFyUeCKBPzQOs bYk6tIUnGXRVA/jAa7dycHVfS+GUJRs/2/Go3z5K2b4OzGkcyxcXmYzIz8UGUGudajR88H7S+GMo 8PeIaMlGzgEw4E8qs2iJWYTKU8rFrKhPLTXqzJROHeqBJOb+uNu4wD53k+5fVnDBNiA5kRUj5syr BbM0/g5zPVc/dOuVhJ95ae597VphkpHurpLhhHaCdKQV4WGs1BMKzpxR5w8vTbym7uPBzzmPhnEE b8XkFoL2Zwdn+CzL99nEcZN0TQ8Mxo1y2+qp0w/x6xdghZ6C4WP1CjAe6d99Jk7rIh/jYCzWfRFH FwDaMgCTXupPri1crwoengs+nwnmkTqZpjNb2t/GrpXT9N03aXXJ76RgzdVjocmn4dh/PAS5Q8q+ tJea0lgdx4GQUQrwnRZNJUPn/Hu1Aq27CfktRJ5wFWQMl4RPq/yYU4jJCk8Ikm09OL2c5fHrpJ/6 ILi2ti9O7HM7pp7N0Q8fCByoWf+SdumolZa5+n3e0SgmNYS2MXiA8LXTC63Yxgb+YYT5XDD82ylJ ysbCRFBy/tQrNVo5TEJo0I25q5ZhMTPH3KEs6yh5i5NAap2Kv8LhkxfbuXi9fw7YkkrNHqd2Zc6T tkfQ4LckrlZwGNSgexfcyx2q7kkunHSD6/sNeaEiDho6oUAvxrXPsec+qlBgdQA1sBneXA3FNzcR 7ETIAFkins+Sb74y+SGyhOTTLTdZt/g+QASuPD0Lg2ONlbftvHKfAbN1kQuiqBtVj2FUS9AoOgmj 0yYpl8eP9v7xSCvpkEbfrKnjDS07BTvGYNll0v3Eo6kITc0YwzeVwx8DJuV8fbRei+nkwI5SGQhy Qnd4hygd+yknvzgKaFaeAja8mW+wkvJvLA35LBwFR0pfhDUQdBxFpAh3uXK7WKCsG+rz1HERlhyz cVbj2mP2mXxNs2tEtF/xjL6cEi6kIpSafjk8UnT0FzELy3IB/98/9V5+60UfWYMt9cVmOSzpwr3I AhBlxVNBepeBf2W3LN8mE6Ld/R7OG2Q+mdwlSV0TKgoop0mBVTm07Dx/e7WlOCD8/voA79Lt3DBa FAR5vkLMoUhmBIjV6Mg4o/Md6h5a79d4KsyuJOhJJURIl/9HhsLb0E+c2MlRyf/Ukwk/0uJeEKNK D3wahRCgS0BkegvxOw24C1d2+N0YGy03BY93JBmJTKaRSIzltIlUQ/QLg6Pd/uP0aQ/U56KtlUV2 5S9WcYytxfzcm/gARql4i8qlw6mtU5UtEKsdoJ18TMHO0JWCbhugCUAsQWF47lJ8mbRznY4hJdKA +3D0M87mVnaZy2VZDm4j2NGLZfi5Oc2j3QzumK0DNGffL0p3ETT7EMBuxqyWgt2MaN/E501Ebf3B QmtXL8gUEo5LWFHyLSAjOujwe2UY54AVRvk/byGgEXBmHz4tUTDlP3c9RcfL6lmRHbi9fxZ8csQl ao7wF1nd24A0UI8H9DXYKZnWMO0SaMB8kHDAFIffhfvZwrxRJUC7iSs4PpA5jjlHmaYHZZgQVlvh PbjbzQShEP1LMxUve9Q2gPgBwNboKGrm0QL/tWOhuxKDfUbxb9m5BNTYU2n9YUTnQQLX55FQaXyL lnrikDS1DEREmBVHJXrKQxOIrZgrl/oDCoTgAssR61Q5+d4ysCswUOMqr4CDizBMVzn6452zhvru cgi/ztXEOMDMzQPxGSL2rIKvhd6ZQ/8dMGB1xRoTAOYMmjnG9AneLJ5zr0wTF6JNwmCtwMJGqa9X O8dIyhwGHsesndDogoammTeWCgvT5Xr9KYJySlq3Nv8qff1N9drlxSPljgKcdzGcWakWCGaEd9H9 LgrhNo7MO12zhPhQm3W64LeZCYvyO6r7B5hOwUrCetm8iZTkrYwTOTMVkXb0I2+0sOysSnfNzLpJ TpV0mbeep8EeshpYedK55fPWeV+1RqUhCX+9O9ZY09cueH5dLjgxS+CMdzGj2TWXnAlfMPdGaUOp H6wmvnrdxhDxA5+DBjiYFCn9iesaCl6KniNKkIzxSdozgBRr10mrbbd08s6CmZOu2y/imSZO4RfM SPvGc184c7J8oTs/EjbAgD/BRQjp9BqzSVlzBCvIlehpHdTMNx6xULIdyHynukt8fxGQiLpIAbiI PJ99RD8+CCOZBu1Hu6tMVZFY1nwt26Gx+bsqm95nfG1mz5lpG0Log2z9HAJu0K+qyNKdAuuLM+79 nrVhnKpSMjfX99ShF0p2XdLVa3UZoa+BhsV0f2VVsYNqXsERCQ7mN78chc1qd8/3Nc8FS6hpn0F0 4B/c72KwPhtUMYuJ9acjnoyxELh81LdBoevtjad5TBzv8YoudHwscTTXke6caBW/rzo/7FMEHxa5 Gow2eiyao87FCjiEGYi5Wvf7+1JSbY4p61f31X2BQlLgxFcKVqbEi4qQiyA/i84BPJny/LOQCGOT BAfTTaP3zIYORQgIK7DH8xHMWvDCZ4TEVdGJe6vqF9i2R2bvujX7BLd6D4jTGHMc3U67iZjX6J8U LwY9m1NrSzy03bE3euM/+BXVevh+1MwXWynpZOtD1/JGOTk9TQOlBF8hgB0zcjPFzPeFgSm52SHz 36OwpImxWKPY57ABs8vI7USGrxXPS6GDjxm0H1y5CfMd5N5C00DvF5kmMMmeDiNjjLMmYB9q69RY SI+MrvGea4ZjTteFvqeAA3KjAuxoWF1yiVaIxZNpvwpy2TWTEQtbCVa7eFNgTSijkrI4EdSu4G39 FYo1YN88DBqNO0XXEzuw0OMyhmyUTdoyOmhcJhlm/ZYYE63nPQjf2sfUtoHprrZ8CxQS6Zu3+Ouj truwnkUbfDo0fk3D+g4x8B2a4Klf88nnmTup+S5s4uI6cvgSHa7/VBK6LVgOGiEApvNLBIBeZdZX qtS3PY5jqID0R22sdopYOakOzDqzU3Xj4qfG0TJ5FhcUiNEOo4oYjVYVAwp6Tn60jceG/c+5xILL aEQWZXb1qWYuMeL2n32byTIuRWdJ7J+vkGMnmtlpwnbDDVjXJ4F5/Zu5ZRbMSHVl5Tp1FT+j9ipT iUdVLCVYJ/FCnTsCZBPN6B8D5l8fEEC/6gmOM9FzSOuC23Nbftqa22foWrZ6AAtNotpqm8sJ1/yQ D9QJocqHqMlqdUSY4r27ZOIRM1PK6UMnIJKA8AHj327V5Fupr6Dx/tJAV9XWWa0/1m8RnjXyr/hm DDM+PP4xsWmqKZiQ5wHLQ+++c5KzUg71MWqGdmd1rss33jteNHqAYfF4QxvVL6gFuXNJeLNgveBo eIGx+P5sdkFtGh9P2YdqmvAg+4NoUfhgbUFMaSYCkImGO1IGxuwbyc+sflFdL7yN9+RKj0bhvD8G bbSAKyTmP31ayKTlEkMol5kOOiDSBpNqgX/e08P3hdlx6Gxw19Smh614GRFk36HnXETjajya3PNY Bz/g9FilDCw76anE2adSAoSPlIA60jNI1tRhoFyoxTQpL477yxHQcWcvaXRIm0TTfBaNeZOwocsd iTTIwovCEx21CgXz4NaTs3xWU9Mrd7tF6P5E1SWsiV+AZdEupQ7rdPgnPapAcWXhFpPqx0Upckzy ZYNbDxtnztGkH1Q/UdqvGqezjCJUJwVepCTPTIYIm/B5KjlLIDk5OriETp1ikvAb79o6mYJGHVK3 QESnxqoyAXndsBujcx4PKNFBtKiVeB6XoxSAvWkF8xuyNZ7kg9h4CJAHe+sBFln8H+/6bXe9CU++ dvts0OK1P2L6CcyYEhwXGON8BZvDdOtD0QTnFYju3t/ZhgFg053CA/7E5GQVZyYp931kAg13S7tk njDOp7/HOwiOxwsxQ88AT7TfPXV8nWW8wVOi0kfE8E4Zkh5DQ1FDiis4qveT/UB4VErMuKwOqw8w NAjXJjfDqrAhuK6rHyNNQAvBjSd7Ofwsm7XHKE+FdUuFraoQo8DiQ94NO6HTUYdRXi3YmfmfoB72 C3koVH+F2iPI1yCkKy3nMVFFF2/QmjwMXZrDEg05AwQ0gvnd6DZnp46zHQiWW2Ho0b7cNJAHsB9B YlCY6R6z6jPhciFgCIuCSKiHjqCAc3CXazqRCBY43pc2QgHzPK6tjQCPN/N0YIc7zKk6B87W2NUT nsukdx7K/C/IQg/gU2a9scjH3PycBuMvGkCRmV6KpYrIQRix4YCpaUPXP9ATw/J2evXqovzVJAyt aSwc/mSEOFNmErmj7cLb9X2uNecFQ96ZYZvFfZO30ELbpaz84H/WnAUZVU0d6U4Aj1U6EXkDAUrR 2bfGhjySEabCkmHc7FTHUEyudP+KsS4L3ZO2hLDF9ERLOL/RvTruQiA0nelZXL7B4UUJOaB/38hv KPDYnj6V73R7Ly3JnrQUsUrPv0E4q0Ep5D5x7vfHGUv8kPbI6FsZrjsDh2oHVlVR+Fwhs7fdl6XE Y3WaAJTH3873uCKNIpbScpaJbbGBfdN1NAiWfUN1h+jeftiA3bd6i/qCqpP2EwYVCZQqpQ5aQNUw XpVdQMKZ/3AJOrNIgfCvVLuT3PsaoWZk3Y4iGF/Y41rygX4OaEb9E9CT+3SCq4mR/CiPbRk2iLKm sscWkbv6Yi8NKTz8D4JICsDqAE44ZcAneDIPmSgOU+2zQE8/2UYdkH8UUMjc8r9Eo0EF8fCqBfd2 JU3xe9Hs4jBMjE/8TxuaCTIMKtal1Mg9V+B9HqIo1FPHEmEu8/dw9EeZ2eAPUnzfIcGtNi21Q8lJ qyBzBrqdOXPPntlFMwx6lhUI8oA5+WIxy5lFCi0TkhE434kxWrugstsMotSIgWl+adLUo+m9B/9i PSeErQd3PPZh3tW+OKy8+I6kHQXfi3QAKDxO0diNrdwcSKO4KpYQEV/thS2NlztJyiHT62jyiVGZ 7vy5M9bNFr2Bf12RclJ50lV+uJlxN+cR/gRkey8fUal/RD300BEIH0JNtmklazAdy92xQOuvzCfT mvQYzUa3a7jr7/qu4fELJaSIVXOVRb+VsGfZ90/kdAlMyNro7eIrVuP7yrEddvUYFuOmfDrBYcE7 1M0qFuhWb3aHeIzF5ByZnwvIZ0pkwWS8rtncTqj42XX2NqJw1fPzETHFvAe55tvZ8oKSWfBG4HV4 zaPodiaNBRDxWTr5QZSLqNpCyyHwny5pKwWexCurDrQFQlFlMvbTtn67AmZqTsYitCN4Vdy9APVr JIprP7fJ9C/RXiSEiQd8t5v5ehx/MhFf+Yt5F255CVGbL6Fb9iA4IZwz3KWpPniJiwB2GdFJO+m8 iQv+xV28Lh8k5Gcf90iTYk4+R8zYtLvEKlgWqSO+5OEa1dqsFbJkNIx0egX1WH4dXIbgwLBRxrZU gHMlqiJFp2VsAPG64pfi+qGAWBLwd7bMvSA64i9Y0MHzAN3RL82u3Px2G+S1tMtBMZk6vAyjZTgh 2fUtnin43nZ5aaKSGyan2fC/+qHoREgPLMzCb8PZJ6Bhbhl9S5Wa8+4nOWmmbX3BPBXxeMXmSmxm gMihLmjpTJMzdJ0cFWtSqBBUZ24S52qGk6AQB3fs4Te4ejvGaXx1auVryhl53gReQEj2kj7Yl0HP GF2RYHWlCt1X6hoIwxU2vBKkt4MLZUR2745hnpA1rPfH9bat4Fmg0xAGHtp7AVOamuoRXyRWq7GF oEWWLfFCg6MJMz2y3PEIIJ2FqT5TKg15duaqFuAWAIn236vCGWHeUyHbHUSw5QEoy9J6pm2EoCed zK8TW8CB3Adv+Tn47OZe03xtzkc0fC5vYa3aR5RQH2B9rH6ahlzR4VieYiuDADts/LAfKSytFKJa 4PtaiBAHXkC3kWHEQ/DqkAjX5RHoslSncGYuE9kzSeSyTGAQ0hUK7CyLTDuHAwsQfWjY2G3zsdLf X4H3vhfEZAtDHi5fNjVClIxIYN3z6WbCaCyZxe+7NqPD+uecTlJCZ7NL1YQ//1xFsmeVjdVIqv+F gfYFEQIeHlx0qLR0fWMpOuIZHgOctD8k+tG7vRLUV05bYWf+tlI3J00kDgApvUt9BN9v5GzLmuXN Tgb89wxqi56ggVu4CpTqzE6lAWrPgHorgzutnrKcL3u2CcdBnOc5jLUZwKXyfbZMKrvFUBIKxN9/ gPKrYKOJIkzvpYQHG+RB1Bnt1rbPJ7gy2euCPUy78KagzAZ1BD811RLrqnHyt+qUggIcFCJtFf8T eIMuHpNQYUxR8+pTcpvhZnUdRGe9WqUYvA5ykgThKPpOKcRpvwDV+g0JgHrrwsR5+2APufMqMS0P K8PllPq0cieFbkNFra3AnA21o/Pf9pfo59C7fumeY+JYvtYIMUQHEW+Stj2K7IiYSYaYIYijrZ4P g99fvKhN+OphtQtDGUPyig3ON6L06eowvq49C0+RGGDC2efJqlJfpPJdF074yC49ENcyKcPMU/j6 qAOSpPvcxGcVv9W6VHOJ9LQ6wkbWiaWf2mePuV4kXj61NDfyesLW/i+biNAqAgbwMUenK4I8znoD eFnqx3L7snnuk989kjFcPBEvMzxXHWnue+OLEtEjCbzfze4PykmdQdWIXPKfflID9Pz8nC/rEe6r sC0LWbpOoGWXWgrUwz6uejNXS2bGDDXVvOkrI2+1r5bBKUc80s6yu7UuN49SDfX+CLz45dj21UZ7 4MeV2kV0kqw0CWye0/JHWpOQnORp4KKPh11muZxcEkxYvAgunEAcqr5J97i6YwISpWMclh/YP0pA c2+EZLPvjFYVxw9fdGC191lOzH8YkA/ox68EE16SMjkPzw5sK3bT55o8SROl27TUXtzw/9uriYCB 7F7Lxb3FHs2VOPK9Y3De2/i/6/mt1andT+XhLu5LIn1KwNwo3vAAj3Pe0qkYoIF90NYZd6BPc4Cd LxRynnbc0pebeU0xho2xzntA8hoVuMfW4fKi9hcyNxzXf2LA5KZkexUf5k1GWbhlDIrmM+0mrZeK Ygl3HcVog3b6ZnlZgLhlEB4Ht39Qhqqo/lQMbD1f0Kc+vcBRgnEQC7CD3r/uxzcFmUk5BfWkc2fJ aJzxEqXMgE2Xs0HpCDJ5yqOS7sZI5PFVOEEO6MuVWTIC6Ny/mjiFj9rQV/FrM79Vv7ptVT5Zq2jN gXRKsVW4iyOhDLJbYxm23TRSXXi1UG9NIBYUtFw2ZlE0Ka4xlIbz4xbnHBXW0A/qpmlpwVHKyXYI acxcfT+R/7q8Q7UGtwrkTOkDlalMNXPrwa6J3uGxZ7y2MJHf286TWCbKIByvFAQmQlxr2BrwQFH/ B0y4wgqB8cuhYYmaCqJN8ASE2phE5yO4Ramignjq2jmOLRYEoXZ4zuVGe8p3ezfM3pdlgaBFZKqg Vb6cUiqQdKkhvq+poHnZ38iYYaWeD9Xn7mx48a5ZTQ/OHrSXTRY1yPE1kcaLt9MaN3h/jiZ8C1CE u0r8nPzkClXPH3MDog9UzHe319pDZwd0Vl1G3vqG+yNESD7X/AbbuASc43Yj8Ub+iibxalkh1v+e tIvi2K5SxqGU2XUIuo58MvefTyZz973JbY7oZd8i3GgjmcGsk0A0meqwMQZ2g6/cgQWajzbIRWRB 7ZIEXixSncBEl9+Z8cPgE3dveCisxDeoz5l4ylzDZvPsnAgXaNMzLYf7s9vSiOz93sbhgDua2Wkn /KCZX/eO9dNvrNcuNDv7hU937W+zg/lL6fh9gnERVYTxV0FgPBh+QHPjtUDVjE2dMcwF42zVXyTW rE6Kod+K793EYhqFd4AU7cCicm3MsWO5FQFQUbrsjvRxNEPuFDYhgONH2zXqUe9iHYpQy9SmqM3k aObaEIELoSIhrFey8vePTcScxCYblIbtdU7wRoS3y50sR8z1gP2z4TKfjU6/sHSPIPIjLoBTwabl AQvPAknhxG/X43W3r3M8bOVw+0NCNTBygrLpYuVsv2rm4LUYItM3Ub/9WHvfva3Y1WRvoZ7/bG5P FQUFJxBUAq72VZxWFAIvQgnmDsTUaj5g+fJfJm1Y6f6OoO7XqS7K1TxRRKyLePG+u9CxMAgD0nX3 dFfMFZgY7r8+VNhvFYxOHAnlxzUXNQpSYzCr2+iU83dO/m+67En96EfwGJQXrcQgrmPB2KUYrAG9 19KczRN6pX+t2IgX9ATjEo7vR9Roir0zxiRD0obMXAaUxF0yNI1pyE5nbkt5xgYp8dMaJNSmA6AH gQDlPuzCQHyUt5R9SOx3Fv+Zf/IA64rci14xwFpeyPzpCyZyQNno6I8JhZ3eQUT+vUj22dgNTccP btCHYuclYdbLgTV/YChGliDyWcNVTG6b73sQiVruyn+usYxZ1Fh2vLB8/xIij60AUGBP6nPA2E+p EeUsUukI/7JrvAh1dU1ykU5T1PTI3Xt/dtYnK9yL9/tF5TRhyBlzErUWG2TFGjvgG6xXyKI0Kn+B F8M5eLoVmXbDQF+NEoAW4MiD0NQ71Mi01yaC00Hd8U3H9BCZd5h7BWv4M/cRWm2rq3obhzADyPgz ihsAnANKkwb/HprxSnbg0TGxGg1fAbUBNZXSK4Fqh+mrd2pwPM0w2KAZbKrhQfEimAtWHKdRGLmU K5cml+IJLjBzw1/MFUiUAApndwGYTCfTopUfaRibyk6FX4UnWbeXwNZMJKUNpKHmXCv6Y6qTUNfG z5tBehc5A5P/RbV5s0pT0KX2yKZX6ifLPxg6U3AnW7IKMOlhoMDPkp5d+edqttriy6pqRh1pPjyN t1nA4pmRzAiuzqBmaDjl/rgb5NGNN6Fy65tpXU0Uqn88gtFi8dnhcXnvI6yTPwWDmbCh8TyEJfBK WfjwsUV9+O9f667NpAiVQaED2xs8stiaaOJsMh4aWtvVwKeIfKfKjQKqHizvQCGTT52mjwDMp0et kgpKrn+zeZt9M2xBvglro3CKh0yjthOM7Yod7xBykZFgJG9b9d6Bto0sfkBio6Q3iHHHqdpbV7Ry PQn/3CrtlgOckC3wcVrqfdB/8Zz4OAxqlQRom+b4hoycltKLk+LrIcRyOM5WrP+6CfmAXZqwOZe1 /nWusIbmMTsgeVnKdDxSM8EKfzpzCdoat/ou6TIxmDFLv/lv18Fo1AROtmvTcDS78mD085XNadxl DRSds5l/Ep36bVDzPr1sgQpFiGIX5eIOGJONLKBKfmrUQg9FohRzaHHIDzIzwhE1EK1KTLy+gkoi 5eKPvEecSpVcAETGKUEnJx3dR4FxGw0S92AXcAfRuzXeZrsl4AK0BpZDIH/g5cWFl9nzUW/AO1WS TknRZ7tEFjr1Apiy50D+SNe6mwOck5LPRnQrn4pK0zaACTMdCHLcJmYj9fAPz5hr9sfgwI2UNrRG z0qCsj+7sVsUwr2bjpUB3vWPYj8fX14C3XV5M5GRJ0JqdueoMdDatqu5289QMjmI36/9lhEtl+ja 1/z+PM6bmpObqQjoAtIFZuS2KC8Y13Ur6HrfTYdGHRmDp2yE4xw4A2e6qZkm6OdQF9QplSptSmkZ 0BKTbjRcpDRAfQ/uhR1cdPZeBSYewSiwHe2Z3zY/cOS+pXP7fExEyIzPgCexKMRZ1ceQDHv0cvq5 snu/rv25EVf2wCXdT5HPjA/1qYB23DPp1VzV0qL6f4cdyCkOQ7wWtyu2sca87dSbZBlyiyN5vK2T KSDmPm0Wz3DucrfJjOP5yU5QziOt0PCreFqcO1LX7fLvP+8+53VawZ83vA2ufb/yH0w7ZRq+tBsb f+MToZ9qNwzxvG1Ali9WqKp742VF3QtaVpPqlpftJ/OrZRLBJDNgaD4BCLAaoFK0MBdE3Gvus3qS N5QKUbUDs6BzXWqqGz8xaDFKRRDvDuBFjvAIk2nJY/kEqkULtoGXLu9wIYVA6pr6QJdzTq+dmZo8 DYIE64uoiHQeBdF3rtDw9hMHsT5rIWrDf9cYNcv6cjidXIuxAcc4Cu39NOJUL2f0fJDd19iQnXcu sYqTqSwTQeaxYNx4iOTGFx9rqyJpTYjR7IKxlg8cuKe/pfJ121u6pY1ECLeQCSeiUNHkGA4z7BWn rQVwbLgNSZNGNGLrbNDt7PpBj0lCIMM6/TM3sPd7SPNZvv2z6Rd6Y6tK2YvgDe4rDmsU+zziF9z7 LIdtnmRwQuEfaN1lz2BWYzhVO9DWgWfX+qKj2im4U3ymVFnhlciOhVuJlEfm3/8x4ma7wURI1uqO tVfPtz2uRsl4g3WxJUJoRxRJWQevj5h6fekczk+kGVkBH/FddCdLYzgcD1JeWAquJw5JYbjqsaiX hEM0JyU/y+n6llJREu+2/8daJKIT5PqIVV4XE90wrHd4DoYGvrk/ija4yQfJUypIu4JAePG1Ne2l XjQj4uwrHvnp5QMzVBxdp5yFA14TMEijtLdzHjkBJIb6QGG/eC68SfIpaeGn7AB8v3w/NcjLz/od M/GoUHJvW/U3e7OR+LQzXDRA/ZEYbZxvvQf4xqYrMGabwsRO0QQYfPZ9w/2LH/RPQ1in1b+0w0Gf rOtWk41ow8O/ECusVnFwEmUp3BJXcywyN6t9pqdPQNlh0Lju1hh94cnLq7lsdOoWs33/lop8KuFo s+tT01YoynHuHQz0oGcthbWdHXqpX3xVb+2W+HhOsJF/5pbA2A31FmONUonulBAA9YnpfWUMgCr1 vbq5ZJLqKDGwhd/bS2KYQtOduF2hhmS+7NeQhoz4GbBW+gVNewpGccqTyVrrGHaW8TqJZTdwBfbI mUc5BgtZqt2UNjV2aXaMpCsZMqpE69Qro0amx3AVqf2PTs+a9w3DCB4ZBxKOcfqZYruecemlImLp 31cR0na76IeTE9RGH9fSCt5p8XULo0d9G/CBVRTaEAFHIZ+jVFfLBGG0Qs/mb1iJgd+E1v+HCdkt QVlhtXd4aRM6MGdk/wPisdKl/VSDWv6amb6Ijzzyy3Hr225hDrMNEuTKqktv7dcuoeVJV81n8df/ zVo/ycM2V6Gn9aJeKDm8+QJyI5dEhz47Imcb1DTQ+JmjyTMVN+8iJ7xNKx6iwkB0oOzH3tXw74VW trjhXEPvTyo1FWyN6j+ot21fNyqnFRQyMROY5zsCI6/lVo+5Mtq2WhMtCEI67v7W17MEV38oVfHw 7MJyM3+FHaTCX9ITcNhwso/fNndQR6yupB6slSS1tewKwo82yLyE3UlsY1isVULt+UjQGGLVxWnf kR/drustt1P0Y3DaCVvJqQllvjKMXz2cWObS0WFI4/LDiK4Su7JstIG9G9WJSaT5V7pU0lWCOqzR l/wjHdxUbcMK0ILdACmZLiNdkxidbBvCR0u6m9J0V/nG6AUrK8T/NnpobhkLQu/wdzq8wh5ehRp5 ANE29kJTTfV5jJ7bCukOIld0499MxSzf7M8KIDJWbkV8JK8L3TRgAeaQry9XAA6X+DAL/tiU93AT /WEhwFRcR1zXVQqVClcP+eJjgFj5ZHD7D9HDmsk4Feq4+sFdesgnwQuipAf/9CPkWPPxzLfmDiEu 8mKNtqKEgbpdfgVHh7vn17SvM5LoGByZGPp3SVZchW1l6TkWICL+OYkRl6OTZqn/GfZngfrFamfv l0zGaH1J6EuD//PUi10HUpwKhX6XOzbdElvQTz00JAy/4kNWr8EAp+EEZ1cmUCSlD9d63AUVmYxa yIF/xKZ5XVvkNHJLmPqt8SrLl/4SgrFdsr0BBWlRQQcOW7WQXxKrVul/8AbBM1Z86CmWYeDel8cE ki2FGzUq/z0fLN+UB8Q6r1Z2Hagpz6xFYQ9y6uFcljmyR5ehlELYYRAN5aP7HEoLVacflYeovWzt gvKsaaFpL87ku/I3/iYJ8/LjDO881KUAO9AYRpGp3YcWPX9LDwQWEkZ9jjpAXMMK8SKCdT8dPZ2j vwdQHBzfYdA0EtIc8DPxicFPiiwU3+oXiwmKt0NKasf+JC5WpmE9m9bahFQLkl9anAtwLlzCcTqi Yss94IGa7pU+letqCCLRWsNFIbfPvoHJ/flq1iLGeo2NyJYtdiNJohqkmk6feLZYJ7pr9JuhmXkm 7Fc+g49kNlt+VOqLM49/y8is98THZ+SYE7q21SpktgWumV3Zh0KiWRAU9PZProftpZ4m2pkzO5Ek hJNkm27HIEP8QVLrC0g0CIaan5SYgU4I/pBzUz8ajAeuxcH2k7I1frJuHMTmGB5Jgkki+y2i/2R8 8q1BIRdlOtx/SnbIhJ0SbBIDmB4d/hrRUIARR69F/UZJd36+8bgeWXB9YfIPQXImgYhs+QmP5GVr wst7vqF8Zwo0y8usUT/XXOfy+sVxx/e+VxSYHyWjchRcGZCNXqL0Xz8R0qzldd5yYteYvh0gbYTk hOvNH81bn2xoYQp8LYI8s/Mfc9m9k/vHgHBqHUmySPT0Yoq9HLKbc4uIGwhCdWqpVU86RzFOVwwY PzH9ZlhBbWarLczXS0hkWJqF1kCiw2LP3Cfya6159C+ukirEhs6AmaFtFWDAlWpweI8lVATQGYEO wbqya7KyFJ9uYAiS0LjObx8zMQYy3/F+nFGr5loQ56xSU/TPM6Rvln7LT2RkTglw+y6EXm+qqgIa zpjoLfjfUm53Gpg4CyGsQ6FLYXTVuxh1b76hW7FG3I8Q9wWD8TnZstDY/BYnDA6yFowpOKcrM2GH rEjH3yZ00t77p4vWkB/HzpMxCbRNnP4SSgdWDVobfTlFXyjVIfK32IPC0eWv7IdGii0/6WfBUXui CqHjJ88DnrXs/9MkzarmjpFby3smKWmxoLWXDgOWLQTXVK8Nd+PaCy7pe4O0+h95811GFf8qY0hN wuxmutMMmR8yhqk+/azwb+joB83sMAvhYQ8AwVzNWkle9lvAqVKtsqXeF5ZOpVbmhRGkFbCeKBye yiZ48PGJjGNfxbUhvYTtPrup2HJXZqdgRt20Ilw2YiOp/h3RBcS/jJtzj3l+3onMsscLxqebBtsW dsAIXsATjo4bBWxT1c9UPBB2oiPXhMjeH30D5Rebe8nmjiELm3bwXiR+xRffEdxhIqzhh4ZdAbrH 4/EPmFGxMotBVcLb14icUGh/7cjZsu2Hbp+RHW/KCSoH72xpa2AQ5DawZNeCE14z53Mdt1wsYyXm uydA+78SPUvRHq0mCDQbuCLJUlT88LYLJvKTmtaDH99FQ/CVrQUrFwDQ1bRjjbEj3+YmHMqQJL0f 43g0++dhI+aThcYP7iIjnJCDStNjuN7UiipGabgaR0/j+dzo78ouzg7kwceMkZzDp+uxzKJGpYWa C40V/mrJOqXtbssaHBhXGSaVM6CwQLlU6VHa2Jd0pAhApQDpzeojYDL2h8tUk/JBjoXFjWR8xPIR xIpsVsYsRbq6mV6biiuWLaXMgOUvZYcY5PCi/BjxOmI/Rvk3GcbjFLRmh1xEQ3bOaV55y6dNO9ZW pIaGf8ZXlYzU3YOWbt6EfqiuwOebGu0TEzvxAaf22AKTdMiQD9VkXhmw5e4Hsv+sMOHjZD6NDgE5 z6tvC/kvTpl9oxz8ga7RQfWLn4+yzi7sKSv2x6lrfGIKoegA/PDISvZAUBwnUi33xOYBtKpDdkWJ EmQw8bzJo5AEZ0zUIVOM9TCbdD3K1vSaFb8VztdX54jVUsM65Sym5xsLmGBsx3U7fUjaEpKfcfqm D1O2UqQ+cEHkEW3I5GSQiaQfceOn5HQauGxY4EHnHvXyKymTO+kQ3YgdLnpzjkMUOpphjrqM9c4Z y/LyItR/SpBVhRawutkncsYzc3UJ2HRE7o+5qOx8lwf3xyGyPfcU2rkzBBrBuMgZMMBzsz6+17T3 ORjoGps/mLKc38IyBEw9so043J9Kxu3NkK20daFr7+0BxgGNZ45LskJAZqgzRybw0eyr3z3gGpyG vvKfgSAqHbToF7bLqQR4agj/RSRAdKM4KaTyFcQ77D7D5eKZF8dThhlGJyzxyeYrASMXUaWRMKes 5+d5CmfPtQNX+xFOBqXQ4DpArFAjHAgSE7cQrkwBfC0bIfRIt/3WeOb/Bl7+Njcd3oyWRX/QT96n EZ5TElhIftVQzY6E39ydU44Q92hBaiIhxFEaejARrldkMm665OEg9FJr+ejCKaNllQBjb9VfXHMI G8l1+z8JsW4HaxXkhgvl5AdCvVhjUACBqai3CIY7kxs4Akzf8aqhEk55S41L8Ko2FE5lWwxPGFSd /7LjB/ua2/516NVvdvyjuUYqFxvRiVPiph0h5BuZkQW6Yv1gbtvAuCc+fZdS9PgntLqSuW2WCn/v lfp3X9OngpjLgvGTE9Q/pA7rgDL782IjnCdvwgr8y+7CJ7yzlIJ5tIwnTb+rTu25/UMRTaHRgVay hSXHCdOAvstN38nQJzaRluugpyI77hG+8Vf/xt2tcQCkAvshtlx44bs7Nwoib3r16pyYavNGkwt+ iHq7Z60Qei+tmx113VXF+d7T5c/RuI+/qOXXgNaUHR8ngF8DDxZbgH3egCZ8Z2o2921saUu/xiKO bkIGVAVDCgKehkJORynKOSZL4CXPdWlXhzByph+cdI4QU6N1lUyDIfjolB/rZavd2Mbt6hDkqhXl Sp/g2mSFsSWw8SUJ7ZjgdhluVpAzFlpg8KmHlV7lQTZvi7mqfd+tQRz3uXrdGWojQfjoAqaJVjQP xKR2eoHRQE0A6pzP0+E5SZ9+8aOYUEW7rbihKeH61TQkVCbvi+9NF0rMl1DgK8b44K8XEtufrCqQ wy7Ew8yrP7ujQ9E5IxtTXv45csdKfIdz+ccL4nHuFdArYVm3W/pzF4J1HGNXYMjr4qxpdIjORy84 ry61agh7QTWm5v8r1qMuNkAO0HQ3a75qt4ijdKZVTq9UtyrBvIlGRZTzAcMqlOwbFNVHMdOkxzcV TyfI/xifwyjBRxVLbBDc/yfkLVUN+sEfyygDmhz3kfKOMHceg8ne+ns07OanAADEbZMS5R23/fg/ znZC9xVqM7zvez2miRGXiKgIYeY2B2hiOswfE+JJBrUaUKB0Gd/YMzT9WpC7F/KQpGkgaaD6Ruo+ uLMeGMxHNyegXJChblomGAPSWxGA2F5x/WLGO/8pZNluo/8lpxA8LAyF7ZFJr8IjNC2B6+uHUHBO icpJ4P6hic6ssyWI6EQ6V8xJPCrAWUO4JkqJZmNFbdIR1obbkQLuP/gpZZlGXL7G4JmPyK8LA2tC oCNGsiszJxOfFFhfwkJIpalRIWT98b3jVEa/Tq8BMJZcjQuloJjPJ7MW5unTATE/EET1vLxx+rp3 fGvMD2Pc/iqRsxzVZJet+ALW/XKu5vqR20zd92sIzP5dUjkOKhYeYAVI0z+K7y0Sp2qsQXArnInD weVt5mcbUWNUOcHkMpJJOY2ftTf7Lt8Ydh0at++Ka4Q9TU0k5H0y1luuVDUVZk/3x7yIcqKHY2BU 1lBUh0zktigBon8ag1kYP+lx5b44yol3E/YUnel9GKwB2FlsfiFqY0F1JNihUP89tdEKgt59n+HA y/ew042uMSbj0A47ncIgP1mSBtFSDt5mqaEdn0B65Tgk4BIY5SyoHbJpyturABnwrnDo6mdDbd4w wCiijuV9RKOZX49r9NJjfuOkb86qT+BHXz/4o9feiiDVSpCTWYyoWU5TOP2cx4+Wy1zNQgiA34rT nUt5kDeUrM++svBGGEy4oC8WNF0xveCLw6NR/QjRQD7VS8rF2i6kRN8wOQ2BjVvjWFm5ErE95kin 8M2jQgQX8g6jSdd1vll77kfAxkA+PDmHg0S2/pFlAbsilJowNruItlIV7q3dLSG+yJ9O1hAm1DJx nEAmCIbD518hoQaLSBNr1t8CRGdcL1SAIPdbJRE1sDPMVWGkfzYk+z8Ks1VqYSKH30nzA34wcm7/ FLOepp7OUCsjvU5V2bb0yHhQs78sUG9MpcRbWidS9ai6UR+qUL3ppea4Vi/XnomP1VILbeV8KClf U1WlTyw8cAE3ujdqBOyFfUiCup9Q1/DjHE0rKtl/+Ro8fCKtlg7EN6QaCXKdzmawWcYVHoVybFec wFU8v9atLUIUzoyr0j7N+KXWxsfiX+HZT3fLkC+hd5TQyFWXc2OtA0CsBBMJ8cDTyM3+ziSiQedk BFs+W0RKF8Uqgh8f6wQFlFmV7tVlkOWwGhhqUt2cn/VhTLCpzwJtbrTWoZZIAYtRrTxb7tg9fm1P OvwytgzfJxr5L2aYdWuuVrp5ppZgNIw1qXPu/wm9p1HjQaCsqK+Q3ePh6kLJwsDpuFopqgCQCXPB 2UsBXksI8uXjiZYvQOuivspl475iInsPom3MjVmoGURF9I1JmYpOYoWC+QSfPTm5frwpS8ENG+nm mIkn/sWgzLOoI8tQAAS2lYQnyRT4dR92VoM0naNUnaJlHBvIQrJdPIOfPS4Ek9mA5ZQHDM90kWLg mJrIV9LbBLJ6n1EY9N8mUy3RGVKj3ybR9vmpdneEweR9ooSNPO+vsWkGPzMA+i3gLm14RKVsrE8G BvjNBcOMbhNvg+7zFZFdL4WOed1taGPvtjuupGxG840Br7UEOfhpGKcihxCgi67PkGilyRTbDLxv yLm1ff8UB87SfMRJbOKNEoeto6P4VkwZd4phYokSK3ODSgZ8LrSYihYIEQeb/W6iTfpzlDYJHLLW Zh0M+VEytMeIwmjoHVAQO9j+eTCCZigzl3iVMlTmpFUImkYGWKmCiPwToInZzUFL01kUT9DiPmkG oA/w+nGWltwTmxsy6hXtK9fYi/oJYqZNHnEAjW7hHNn1gA4x8DtHVKnrFhnYBhVicJU7G8mldES3 jhRdUHH1d69U6Ls38fbNUeFCi5vx+/rziJtARMRDzvNPau6OaRVJ8xdj1mcSGsw9IZ2bqnz/ODrM WYhEQpdXfnOWD4JizJdhXEBd4uyW+9a1h6uXzdVd6vK9clJ1NGyHRHjBNsIlvzYwuT02onq+tK6C 2KpTy22URF8dC+hEW6SnLluk30hvenlo5m6MEtLlNbYTyyLaEhP+/8WuwaGqen56LZkS5pxGOW9/ LfKb8QcJ1JkSbe/p+JF/TCDIOqk/ys5kaCa9bxHga4nVqT8sQyC17XOWXnUEVTyEiPstDMwx8TAl 39k0baUnNVzJoeU0PU2WsxoR4JjrrTfcAmt8MLTUFiro3S6eO/LXaV7P0/wdzH5yXTlZ30Y5rbFp oaPANhQaRDzbnv00aA1yUdfz9EwEGh8zgntUa+rogBK31Yo69+ckXFirMgqPOjCXtfqZe91nYHIS m5u/yVSuXlDYfkmS+4jC/fYieFHL0xQPXLbDQHnxcapmNW7ocpVU4yIm5KmSrXX7F0OABfgSwb5i XvAOAPjOqczpKhEHAytR4alZghxGEhRzZjX0RjEuWaKEajsKp2M18vkfxcOzGIxIfMirXoTxqT7e uPnVo4VvwlLQsvzvG6xUovRtPDlVX0cdxmLNkwdOnE/8i1mW57toxa1rU2ZlgEOKemSOptDhz67g w+LdCFxN394cPBmy4j6LFKdWxFaAai5WnqyEX4fgWFa2p7poaFjPfYBr+35dFX0+61sAKa2NK+7b 4UxMtQfl+T5UcksYeJWlcw6mYnf7E8EJ07Nmm2Jsfc5oUV9rvM5TKFB1of6/uYm+oGzigxgb3pHN 1OqchPaTSrPdTWra6drxbmMQc2YD07DdEsfQEuww7tE4y8vkuh9NxN5dtVPWZzJJa8q/2pBDuaTX SfyQdHHCg0mf4PTPV94CLDERqUyIoKgH3mVgxwaU0zbNom5oSjpLyfnglx4Yun6Dozzn6JBXikfK KNenPDK90mABoaQM8dw2rk6kaURZvd1eX8MlqTfCaed1l4A3G9PLS3hTtP81Lbob0Ht2BeMAjcBF V8JP05I4VTXdIy88VBVhbGFCeFkQzg+NhJSAmF9bm9OAd7GzxqmaJnIzVAvXmZROUrUnxUkA5nVJ PUqhlP8HhOdM7t553v4SsDmGDnZ21fbybVurUn05sHwc64lh1AxGOGjQbxd9MY9gw9L/V9NFTWYU 6poJspSCzX6VjgjDLVvj2kQN17vgSK/HQT1laSW1V6X749JGkIQUYUtsCMR/E4mHAKMh98uAt/Br YYsOiPLhE8Ip2QRQy00Xm4egjWHlxGsRNbtL6KOL/IETxCg/jKACfmph3j2b5+Hwq7Bl+46xL0c5 3kCqCQEAPNrCznVoJAyKZN3t70+UI90zyHa30sPMeR7wfeG1NHtWjqUAvNzQuwLGcHKztToDSasa bJkYACrCNKOISGaSnGCcSfXeQFOgNi10qqKHuCRbRTZplhP36WFU2SQecJzZVYqCAlRdbNZgv8Li mUSge3t0l/MRDVqA3xabLDqwvhS9XvAZbTYLD6cjlDVKmb8+vMbv8WTOh6c8ZNFchk2crZTpMxh2 YglUywNe10ptXq1KQNmtASuKB33DwNqO94JSKOcsSQ1Vm7vLzliCY+F9IOIEbMMoGfdAR9LxHywq hh20HbWNBpErvk6J0+CoyyZmr7LVAb4YUI8ts59YO6idjoEY/D9VH/idBaYB7eu8ZHkEzoSbIHc7 FGESwr4n/WTb194zcsSw0bMJZRNtFBI/1XxdI2B7ueZR7bq4JejB8gTniekO5P8vadyaecovc7Wd wC32DrYw/mmVcSec0hhcfMymX9gc8MUGrZDnfBkAduuUqNYpfH6Ek00CAkoYZK9magw+aW8g8THj KURac3/+TBU8OyU9b8p8eRrt/a3xSgB5B2F0nzwBZkNPpzaxM1g4VHtAVmY7gF9qdgk1790gs/Rz iitudi2lxeCv1C2/47bd8lTo0UvhdHvJqVgO/jwPSUmMGm1eIkMsQi7/nWBEYbQnO1iUOMT39t15 YSDHC1zWkWO5iyUhHccYCCOIzSgLmu284obQ4Bwn+5+9SSfh0FgbR5u0TTr3/CK+cxC3aHGDY/IQ +3dnZZHy05zU6JveaJ+0OoHgh3+j/uCgLCpf9Y+gLV/rZej2elZ//pwJ8PXxuyazPxWOzHiUEZZH 7rtijzae/YSfycK0kJlh032OyErK8jULQ+n60jPAbug2C2Y6htS0fHnL+atKLXJvi7pN7kvTxZji 4SO5WrpLfUrOZiLH3FQ0j9MokYAFnto2qkw0yRNLkTr2FYd6o7hsqN1twuGlfFC8Yk+lyn1p8SGu GGrBCZPGyW4jR06o6emo23psKU3CnpsgPFymdAPo0tYsApspzOXLUog10hfVj2mnV6A0Po6lr/Tw XQcCAtGQBKnGnWNFrfMsWpceTgxYL/NJgubwwWK3/6SCXKrlY+Xi+Y58tM2QLDYNKHzKBn+6MxKF eX+P+o1nleFycTJ1oYKfXq2GQctudXMxz7hYXlUZcQAXl0HSTy/K2zTHkzhr2qV+fTJr1TbO9LEQ lawqGGa9XCygBVQrs63gFOZzXkvVxvFm7rvnOYciG0Cd+57sK1E3kfFe80Nf4w64MQ1RMy2TmLod L/V15Mw7TqdgupAMDnfzG8sjoq5/LYiLHM9sIiye0pd3LvEQJgKBotNpKd/yW7ofwD66zeUjcsOa Wx86vIWxNyAFlkoHSlDV7pOFq/EjP4Jb3u2bCs3vZiDLr8EZY+c6Lrq8Fr/Nx+EvyzJY2OZOyQ+F kEDcBKzyXx4MeOxtjKJbf2n6Qa7qVd1l8a2PwOGLfk0x6jBFvugreOTwvRisWQYmjwdf+XVnYp+a AboIM8F5t3RbX1XJjxFxbvDBF9vW/iB8VtH0WXZZYJ+qO0W9Ky69BCClsnUbfqCCUdUyZi3uRX9I 1vPVSllP2McdYh5DHyo9dgKzWRVPruL2bkMMD2ruYW9zKcXKOauSyQ6LAemkZEsA9U5kacO/fn+U OdrcxqUhKu2NMlI9jJ2yMqbov/fsyvq+MDkDgUl4PCoqS7UC0YAkn6zDzSvULoZiTfa0hDUit3rB 6x4IkNVFEzvIudzTgnVuE2XwfU79UeCcxvqNAS9742+rWQO1y2a9jhuNRSw988h1fxfosl/eLMVx oBnOKZJ7QThaX7PzE1U3afyTiIOHh5fl0THaXJXFcZnoc+K/+0zXYSqnXm8Lid73T7cwxvJEM3eS d2vlbbaZAhRvOvarIX9PaBEWwoH9GiaUVHxW6RC5E2rrwjS9WCldHzXU0lnDKAjc0aopkfuzYmNZ /xA8Yv6vftQbwZN2hEovaT8/hgxvuEHy8bRWv6wQwwGDtfW0Yqkm9cfFHChSptl7YWN/ZAMwaWAd bwJ0vfS5dOsyoG+Mh81RJiE08f4QMiR1/sjFxKcfRO48CPkdjmDvf+o5oQ+v2ipyLuZCSuKdt5Go 6ayADEJDFCKujt6I3CeYAxc73P69BMXlLUGmk8MeU0dOKfxVake6X/mEb7mhT2Btj4W9tDCN44Wr sjQjnqImVIBHqb3Vh5IICYvX2nJzZRRt5UvE657hlUXqKlZElKXqxwHwahHcf4uum2zdJkZCiJkj oJjdHDzn4hInJAjiB1gwQijRUowTjAFaztJdGhWZeFql3fpyFa6gb3StEnTeXP4MTVYR0LiMTZcn yN3slqboRHlAbKjFisZpKe6Dq6DcEuZL22vJgG2NEfUArLf9d7w9g6lwAauSfyFHW53iaggt5ag3 ixeNCZYipXBmew8fw64riwr+4UcVYXUhaIy/b86Z0n4luSSZ27MbVEvah7wVg7KUQhwh14cVeGqo SLF59RSmfU9aduHQ90Q14TIBQ+HzUwUeOa/8LxlvN8uFminBYcWgQcq3hkFu1QTdzh1P9r75sIU6 wcxyN3R750/4Y4Zg33Kq4Ptjq5C4CEPji94MdOiDHK8y3HAqH74wb2WBxLboZj5xS6XQF1A8+kZh CU9QjMzLBm3YBDkzQjayNTKcqK7Xd8BO6T8d36XINPESVDwV1TziaTLNAgTnlWhSomx8gk5fVej1 hNa7n5C++WZMxkuwAd0F0hlURSfN96fb2Ak4pJ5X9PILgh4+NZ6AInbh+mRszJ0NqBO18WmsVLLx ntCGBjQWwVCL7uGzbGsY3LkSO5lwBVkN1QiZDZpfYMU8cYo7Bxx+JXmPvZthG8pKbkKMZxuedSxc HvQSjG24Hei5rIrlSE1ljUfDDGqohoC6QhZt/z7eG9v93InhgjaZHKSl8fdcjnelqTEZnDsMdTdQ y5FtUDsRirrXzwRUy9dqrWFlQjQarB1+iwjBN3RjxygwdHPSFFfyutBS2cgM0JxuI9ZTgPS1WJEZ ImKy3pPo9LQzZnJLY8tANHkf08+ulAbzgBQ6nAeUoetP6OsrbemYRnab/MKG7lV80Brd+1aA8i4n YdMTYLzfHO+YXr5OeNZNY4BWVpa5VkjSsYrs+pWN3jM+1qBQB+gdjyw83VkA558tY5QyqHO9dr3g 2QQt2xHfsMni59Z4TR6k4GeX2WRe1tRvRj+cljc+b2+BuRD3yRdd1JxCQQhMLrKGCEqjPUzGz/Ss SqENHTlOKsTunHXFVkx6anHCzMrjfTFK6KEHR/KAFzaDGMrQEPTV7DuevoQ/N0VPXKgm+O2veYE4 P8AmTK2FVKLgTbeVBVNS1yxDxSF3Wrq1WQes9rL6hwQUK5me3bBT/VY3wYIX1xUj+Jr7hISLK8tI izvDdeNPaZyc4pjQlKE6iM2JOYK9Twv1Ds/f6urMzeLPZLJQeGa3fBKE4QoEwphUCjLfuKcOuU04 fYzqv/0gnp7YOkb8nm0DhqiTHJaNX+Vx11tZ8REmeKsAnLJ1sGcK8njGrJeW6V+35z7HMxxicHxs /BBVshA6bnQ1IpAvnO9DpOeVZqF1lq4jb8PQs4HLHbktGkZ1uj75OI4Lpj2pEUZAPdlXb5WVXYvj QsjlvnMS7aH+1RQulsV43abCs42nMD4Lf96mtKUS6/FCog4+p1uzKeJ1YtWfKAliqJ1rCFLZ1goD puensEu7RXb2YO4/NN6i4FAHm54ga4EJs/HvMXEHFjYBFu13rCt+dTjFw7CxKcSwGCrX/OSjuR47 ctAeZshjoPS/Xou9dzH7i3MU0kcpZE/wOI9JuBEo9WvEtZ4YY4O3fub9rCZSHj4WMMmzwn2MITOB eVdZU5vuasSpNAq3Kg== `protect end_protected

mit

6baa9e1d0839c23b982d8f3a36e43523

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/dualram_512x8.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- dualram_512x8 | -- | --------------------------------------------------------------------------------------------------- -- File dualram_512x8.vhd | -- | -- Description Instantiation of a template ProAsic3 RAM4K9 memory component with | -- o word width: 8 bits and | -- o depth : 512 bytes. | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 15/12/2010 | -- Version v0.02 | -- Depends on ProASIC3 lib | ---------------- | -- Last changes | -- 08/2010 v0.01 EG pepeline not used! data appears in output 1 clock cycle after the | -- address is given (otherwise it was 2 clock cycles later) slack | -- checked and is ok! code cleaned-up and commented | -- 15/12/2010 v0.02 EG comments for BLKA, BLKB; cleaning-up | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Component specific library library PROASIC3; -- ProASIC3 library use PROASIC3.all; --================================================================================================= -- Entity declaration for dualram_512x8 --================================================================================================= entity dualram_512x8 is port( -- INPUTS -- Inputs concerning port A CLKA : in std_logic; -- clock A for synchronous read/ write operations ADDRA : in std_logic_vector (8 downto 0); -- address A DINA : in std_logic_vector (7 downto 0); -- data in A RWA : in std_logic; -- read/ write mode; 1 for reading, 0 for writing -- Inputs concerning port B CLKB : in std_logic; -- clock B for synchronous read/ write operations ADDRB : in std_logic_vector (8 downto 0); -- address B DINB : in std_logic_vector (7 downto 0); -- data in B RWB : in std_logic; -- read/ write mode; 1 for reading, 0 for writing -- Reset RESETn : in std_logic; -- sets all outputs low; does not reset the memory -- OUTPUTS -- Output concerning port A DOUTA : out std_logic_vector (7 downto 0); -- data out A -- Output concerning port B DOUTB : out std_logic_vector (7 downto 0));-- data out B end dualram_512x8; --================================================================================================= -- architecture declaration --================================================================================================= architecture RAM4K9 of dualram_512x8 is --------------------------------------------------------------------------------------------------- -- General information concerning RAM4K9: a fully synchronous, true dual-port RAM with an optional -- pipeline stage. It provides variable aspect ratios of 4096 x 1, 2048 x 2, 1024 x 4 and 512 x 9. -- Both ports are capable of reading and writing, making it possible to write with both ports or -- read with both ports simultaneously. Moreover, reading from one port while writing to the other -- is possible. -- WIDTHA0, WIDTHA1 and WIDTHB0, WIDTHB1: -- Aspect ratio configuration. -- WENA, WENB: -- Switching between Read and Write modes for the respective ports. -- A Low indicates Write operation and a High indicates a Read. -- BLKA, BLKB: -- Active low enable for the respective ports. -- PIPEA, PIPEB: -- Control of the optional pipeline stages. -- A Low on the PIPEA or PIPEB indicates a non-pipelined Read and the data appears on the output -- in the same clock cycle. -- A High indicates a pipelined Read and data appears on the output in the next clock cycle. -- WMODEA, WMODEB: -- Configuration of the behavior of the output when the RAM is in the Write mode. -- A Low on this signal makes the output retain data from the previous Read. A High indicates a -- pass-through behavior where the data being written will appear on the output immediately. component RAM4K9 generic (MEMORYFILE : string := ""); port( ADDRA11, ADDRA10, ADDRA9, ADDRA8, ADDRA7, ADDRA6, ADDRA5, ADDRA4, ADDRA3, ADDRA2, ADDRA1, ADDRA0, ADDRB11, ADDRB10, ADDRB9, ADDRB8, ADDRB7, ADDRB6, ADDRB5, ADDRB4, ADDRB3, ADDRB2, ADDRB1, ADDRB0, DINA8, DINA7, DINA6, DINA5, DINA4, DINA3, DINA2, DINA1, DINA0, DINB8, DINB7, DINB6, DINB5, DINB4, DINB3, DINB2, DINB1, DINB0, WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1, PIPEA, PIPEB, WMODEA, WMODEB, BLKA, BLKB, WENA, WENB, CLKA, CLKB, RESET : in std_logic := 'U'; ---------------------------------------------------- DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3, DOUTA2, DOUTA1, DOUTA0, DOUTB8, DOUTB7, DOUTB6, DOUTB5, DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic); ---------------------------------------------------- end component; --------------------------------------------------------------------------------------------------- -- Instantiation of the component VCC component VCC port (Y : out std_logic); end component; --------------------------------------------------------------------------------------------------- -- Instantiation of the component GND component GND port (Y : out std_logic); end component; --------------------------------------------------------------------------------------------------- signal POWER, GROUND : std_logic; --================================================================================================= -- architecture begin --================================================================================================= begin power_supply_signal : VCC port map(Y => POWER); ground_signal : GND port map(Y => GROUND); --------------------------------------------------------------------------------------------------- -- Instantiation of the component RAM4K9. -- The following configuration has been applied: -- o aspect ratio : 9 x 512 (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1 : VCC) -- o word width : 8 bits (DINA8, DINB8: GND; DOUTA8, DOUTB8 : open) -- o memory depth : 512 bytes(ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9: GND) -- o BLKA, BLKB : GND (ports enabled) -- o PIPEA, PIPEB : GND (not pipelined read) -- o WMODEA, WMODEB: GND (in write mode the output retains the data from the previous read) A9D8DualClkRAM_R0C0 : RAM4K9 port map( -- INPUTS -- inputs concerning port A -- data in A (1 byte, (7 downto 0)) DINA8 => GROUND, DINA7 => DINA(7), DINA6 => DINA(6), DINA5 => DINA(5), DINA4 => DINA(4), DINA3 => DINA(3), DINA2 => DINA(2), DINA1 => DINA(1), DINA0 => DINA(0), -- address A (512 bytes depth, (8 downto 0)) ADDRA11 => GROUND, ADDRA10 => GROUND, ADDRA9 => GROUND, ADDRA8 => ADDRA(8), ADDRA7 => ADDRA(7), ADDRA6 => ADDRA(6), ADDRA5 => ADDRA(5), ADDRA4 => ADDRA(4), ADDRA3 => ADDRA(3), ADDRA2 => ADDRA(2), ADDRA1 => ADDRA(1), ADDRA0 => ADDRA(0), -- read/ write mode for A WENA => RWA, -- clock for A CLKA => CLKA, -- aspect ratio, block, pipeline, write mode configurations for port A WIDTHA0 => POWER, WIDTHA1 => POWER, BLKA => GROUND, PIPEA => GROUND, WMODEA => GROUND, -- inputs concerning port B -- data in B (1 byte, (7 downto 0)) DINB8 => GROUND, DINB7 => DINB(7), DINB6 => DINB(6), DINB5 => DINB(5), DINB4 => DINB(4), DINB3 => DINB(3), DINB2 => DINB(2), DINB1 => DINB(1), DINB0 => DINB(0), -- address B (512 bytes depth, (8 downto 0)) ADDRB11 => GROUND, ADDRB10 => GROUND, ADDRB9 => GROUND, ADDRB8 => ADDRB(8), ADDRB7 => ADDRB(7), ADDRB6 => ADDRB(6), ADDRB5 => ADDRB(5), ADDRB4 => ADDRB(4), ADDRB3 => ADDRB(3), ADDRB2 => ADDRB(2), ADDRB1 => ADDRB(1), ADDRB0 => ADDRB(0), -- read/ write mode for B WENB => RWB, -- clock for B CLKB => CLKB, -- aspect ratio, block, pipeline, write mode configurations for port B WIDTHB0 => POWER, WIDTHB1 => POWER, BLKB => GROUND, PIPEB => GROUND, WMODEB => GROUND, -- input reset RESET => RESETn, ------------------------------- -- OUTPUTS -- output concerning port A -- data out A (1 byte) DOUTA8 => open, DOUTA7 => DOUTA(7), DOUTA6 => DOUTA(6), DOUTA5 => DOUTA(5), DOUTA4 => DOUTA(4), DOUTA3 => DOUTA(3), DOUTA2 => DOUTA(2), DOUTA1 => DOUTA(1), DOUTA0 => DOUTA(0), -- output concerning port B -- data out B (1 byte) DOUTB8 => open, DOUTB7 => DOUTB(7), DOUTB6 => DOUTB(6), DOUTB5 => DOUTB(5), DOUTB4 => DOUTB(4), DOUTB3 => DOUTB(3), DOUTB2 => DOUTB(2), DOUTB1 => DOUTB(1), DOUTB0 => DOUTB(0)); ------------------------------- end RAM4K9; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

f7a88a4e17290e62410ad44d0fe322b1

wltr/cern-fgclite

critical_fpga/src/rtl/cf/fetch_page/fetch_page_sram_adc.vhd

------------------------------------------------------------------------------- --! @file fetch_page_sram_adc.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-11-19 --! @brief Prepare SRAM page with ADC data for NanoFIP communication. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; --! @brief Entity declaration of fetch_page_sram_adc --! @details --! This component prepares the SRAM ADC log page for the NanoFIP response. entity fetch_page_sram_adc is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Commands --! @{ --! Start flag start_i : in std_ulogic; --! Done flag done_o : out std_ulogic; --! @} --! @name Memory page interface --! @{ --! Address page_addr_o : out std_ulogic_vector(5 downto 0); --! Write enable page_wr_en_o : out std_ulogic; --! Data output page_data_o : out std_ulogic_vector(7 downto 0); --! Done flag page_done_i : in std_ulogic; --! @} --! @name External SRAM data --! @{ -- Address sram_addr_o : out std_ulogic_vector(4 downto 0); --! Read request sram_rd_en_o : out std_ulogic; --! Data input sram_data_i : in std_ulogic_vector(23 downto 0); --! Data input enable sram_data_en_i : in std_ulogic); --! @} end entity fetch_page_sram_adc; --! RTL implementation of fetch_page_sram_adc architecture rtl of fetch_page_sram_adc is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ type state_t is (IDLE, WRITE_LOW, WRITE_MIDDLE, WAIT_MIDDLE, WRITE_HIGH, DONE); type reg_t is record state : state_t; idx : unsigned(4 downto 0); addr : unsigned(5 downto 0); data : std_ulogic_vector(7 downto 0); wr_en : std_ulogic; rd_en : std_ulogic; done : std_ulogic; end record; constant init_c : reg_t := ( state => IDLE, idx => (others => '0'), addr => (others => '0'), data => (others => '0'), wr_en => '0', rd_en => '0', done => '0'); --! @} --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal reg : reg_t; --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal next_reg : reg_t; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- page_addr_o <= std_ulogic_vector(reg.addr); page_wr_en_o <= reg.wr_en; page_data_o <= reg.data; sram_addr_o <= std_ulogic_vector(reg.idx); sram_rd_en_o <= reg.rd_en; done_o <= reg.done; --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin reg <= init_c; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else reg <= next_reg; end if; end if; end process regs; --------------------------------------------------------------------------- -- Combinatorics --------------------------------------------------------------------------- comb : process (reg, start_i, page_done_i, sram_data_i, sram_data_en_i) is begin -- comb -- Defaults next_reg <= reg; next_reg.rd_en <= '0'; next_reg.wr_en <= '0'; next_reg.done <= '0'; case reg.state is when IDLE => if start_i = '1' then next_reg.rd_en <= '1'; next_reg.state <= WRITE_LOW; end if; when WRITE_LOW => if sram_data_en_i = '1' then next_reg.data <= sram_data_i(7 downto 0); next_reg.wr_en <= '1'; end if; if page_done_i = '1' then next_reg.addr <= reg.addr + 1; next_reg.state <= WRITE_MIDDLE; end if; when WRITE_MIDDLE => next_reg.data <= sram_data_i(15 downto 8); next_reg.wr_en <= '1'; next_reg.state <= WAIT_MIDDLE; when WAIT_MIDDLE => if page_done_i = '1' then next_reg.addr <= reg.addr + 1; next_reg.state <= WRITE_HIGH; end if; when WRITE_HIGH => next_reg.data <= sram_data_i(23 downto 16); next_reg.wr_en <= '1'; next_reg.state <= DONE; when DONE => if page_done_i = '1' then if to_integer(reg.idx) < 19 then next_reg.addr <= reg.addr + 1; next_reg.idx <= reg.idx + 1; next_reg.rd_en <= '1'; next_reg.state <= WRITE_LOW; else next_reg <= init_c; next_reg.done <= '1'; end if; end if; end case; end process comb; end architecture rtl;

mit

5ee535a25ad0212c0e878974951073cf

preusser/q27

src/vhdl/PoC/common/config.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann -- -- Package: Global configuration settings. -- -- Description: -- ------------------------------------- -- This file evaluates the settings declared in the project specific package my_config. -- See also template file my_config.vhdl.template. -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library PoC; use PoC.utils.all; package config_private is -- TODO: -- =========================================================================== subtype T_BOARD_STRING is string(1 to 16); subtype T_BOARD_CONFIG_STRING is string(1 to 64); subtype T_DEVICE_STRING is string(1 to 32); -- Data structures to describe UART / RS232 type T_BOARD_UART_DESC is record IsDTE : boolean; -- Data terminal Equipment (e.g. PC, Printer) FlowControl : T_BOARD_CONFIG_STRING; -- (NONE, SW, HW_CTS_RTS, HW_RTR_RTS) BaudRate : T_BOARD_CONFIG_STRING; -- e.g. "115.2 kBd" BaudRate_Max : T_BOARD_CONFIG_STRING; end record; -- Data structures to describe Ethernet type T_BOARD_ETHERNET_DESC is record IPStyle : T_BOARD_CONFIG_STRING; RS_DataInterface : T_BOARD_CONFIG_STRING; PHY_Device : T_BOARD_CONFIG_STRING; PHY_DeviceAddress : std_logic_vector(7 downto 0); PHY_DataInterface : T_BOARD_CONFIG_STRING; PHY_ManagementInterface : T_BOARD_CONFIG_STRING; end record; subtype T_BOARD_ETHERNET_DESC_INDEX is natural range 0 to 7; type T_BOARD_ETHERNET_DESC_VECTOR is array(natural range <>) of T_BOARD_ETHERNET_DESC; -- Data structures to describe a board layout type T_BOARD_INFO is record BoardName : T_BOARD_CONFIG_STRING; FPGADevice : T_BOARD_CONFIG_STRING; UART : T_BOARD_UART_DESC; Ethernet : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX); EthernetCount : T_BOARD_ETHERNET_DESC_INDEX; end record; type T_BOARD_INFO_VECTOR is array (natural range <>) of T_BOARD_INFO; constant C_POC_NUL : character; constant C_BOARD_STRING_EMPTY : T_BOARD_STRING; constant C_BOARD_CONFIG_STRING_EMPTY : T_BOARD_CONFIG_STRING; constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING; constant C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR; function conf(str : string) return T_BOARD_CONFIG_STRING; end package; package body config_private is constant C_POC_NUL : character := '~'; constant C_BOARD_STRING_EMPTY : T_BOARD_STRING := (others => C_POC_NUL); constant C_BOARD_CONFIG_STRING_EMPTY : T_BOARD_CONFIG_STRING := (others => C_POC_NUL); constant C_DEVICE_STRING_EMPTY : T_DEVICE_STRING := (others => C_POC_NUL); function conf(str : string) return T_BOARD_CONFIG_STRING is constant ConstNUL : string(1 to 1) := (others => C_POC_NUL); variable Result : string(1 to T_BOARD_CONFIG_STRING'length); begin Result := (others => C_POC_NUL); if (str'length > 0) then Result(1 to imin(T_BOARD_CONFIG_STRING'length, imax(1, str'length))) := ite((str'length > 0), str(1 to imin(T_BOARD_CONFIG_STRING'length, str'length)), ConstNUL); end if; return Result; end function; constant C_BOARD_ETHERNET_DESC_EMPTY : T_BOARD_ETHERNET_DESC := ( IPStyle => C_BOARD_CONFIG_STRING_EMPTY, RS_DataInterface => C_BOARD_CONFIG_STRING_EMPTY, PHY_Device => C_BOARD_CONFIG_STRING_EMPTY, PHY_DeviceAddress => x"00", PHY_DataInterface => C_BOARD_CONFIG_STRING_EMPTY, PHY_ManagementInterface => C_BOARD_CONFIG_STRING_EMPTY ); -- predefined UART descriptions function brd_CreateUART(IsDTE : boolean; FlowControl : string; BaudRate : string; BaudRate_Max : string := "") return T_BOARD_UART_DESC is variable Result : T_BOARD_UART_DESC; begin Result.IsDTE := IsDTE; Result.FlowControl := conf(FlowControl); Result.BaudRate := conf(BaudRate); Result.BaudRate_Max := ite((BaudRate_Max = ""), conf(BaudRate), conf(BaudRate_Max)); return Result; end function; -- IsDTE FlowControl BaudRate constant C_BOARD_UART_EMPTY : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "0 Bd"); constant C_BOARD_UART_DTE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(TRUE, "NONE", "115.2 kBd"); constant C_BOARD_UART_DCE_115200_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "115.2 kBd"); constant C_BOARD_UART_DCE_115200_HWCTS : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "HW_CTS_RTS", "115.2 kBd"); constant C_BOARD_UART_DCE_460800_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "460.8 kBd"); constant C_BOARD_UART_DTE_921600_NONE : T_BOARD_UART_DESC := brd_CreateUART(FALSE, "NONE", "921.6 kBd"); function brd_CreateEthernet(IPStyle : string; RS_DataInt : string; PHY_Device : string; PHY_DevAddress : std_logic_vector(7 downto 0); PHY_DataInt : string; PHY_MgntInt : string) return T_BOARD_ETHERNET_DESC is variable Result : T_BOARD_ETHERNET_DESC; begin Result.IPStyle := conf(IPStyle); Result.RS_DataInterface := conf(RS_DataInt); Result.PHY_Device := conf(PHY_Device); Result.PHY_DeviceAddress := PHY_DevAddress; Result.PHY_DataInterface := conf(PHY_DataInt); Result.PHY_ManagementInterface := conf(PHY_MgntInt); return Result; end function; constant C_BOARD_ETH_EMPTY : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("", "", "", x"00", "", ""); constant C_BOARD_ETH_SOFT_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO"); constant C_BOARD_ETH_HARD_GMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("HARD", "GMII", "MARVEL_88E1111", x"07", "GMII", "MDIO"); constant C_BOARD_ETH_SOFT_SGMII_88E1111 : T_BOARD_ETHERNET_DESC := brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"07", "SGMII", "MDIO_OVER_IIC"); constant C_BOARD_ETH_NONE : T_BOARD_ETHERNET_DESC_VECTOR(T_BOARD_ETHERNET_DESC_INDEX) := (others => C_BOARD_ETH_EMPTY); -- Board Descriptions -- =========================================================================== constant C_BOARD_INFO_LIST : T_BOARD_INFO_VECTOR := ( ( BoardName => conf("GENERIC"), FPGADevice => conf("GENERIC"), -- GENERIC UART => C_BOARD_UART_DTE_921600_NONE, Ethernet => ( 0 => C_BOARD_ETH_HARD_GMII_88E1111, others => C_BOARD_ETH_EMPTY ), EthernetCount => 1 ), -- Altera boards -- ========================================================================= ( BoardName => conf("DE0"), FPGADevice => conf("EP3C16F484"), -- EP3C16F484 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("S2GXAV"), FPGADevice => conf("EP2SGX90FF1508C3"), -- EP2SGX90FF1508C3 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("DE4"), FPGADevice => conf("EP4SGX230KF40C2"), -- EP4SGX230KF40C2 UART => C_BOARD_UART_DCE_460800_NONE, Ethernet => ( 0 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"00", "RGMII", "MDIO"), 1 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"01", "RGMII", "MDIO"), 2 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"02", "RGMII", "MDIO"), 3 => brd_CreateEthernet("SOFT", "GMII", "MARVEL_88E1111", x"03", "RGMII", "MDIO"), others => C_BOARD_ETH_EMPTY ), EthernetCount => 4 ),( BoardName => conf("DE5"), FPGADevice => conf("EP5SGXEA7N2F45C2"), -- EP5SGXEA7N2F45C2 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ), -- Lattice boards -- ========================================================================= ( BoardName => conf("ECP5 Versa"), FPGADevice => conf("LFE5UM-45F-6BG381C"), -- LFE5UM-45F-6BG381C UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ), -- Xilinx boards -- ========================================================================= ( BoardName => conf("S3SK200"), FPGADevice => conf("XC3S200FT256"), -- XC2S200FT256 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("S3ESK500"), FPGADevice => conf("XC3S500EFT256"), -- XC2S500FT256 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("S3SK1000"), FPGADevice => conf("XC3S1000FT256"), -- XC2S1000FT256 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("S3ESK1600"), FPGADevice => conf("XC3S1600EFT256"), -- XC2S1600FT256 UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("ATLYS"), FPGADevice => conf("XC6SLX45-3CSG324"), -- XC6SLX45-3CSG324 UART => C_BOARD_UART_DCE_460800_NONE, Ethernet => ( 0 => C_BOARD_ETH_HARD_GMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("ZC706"), FPGADevice => conf("XC7Z045-2FFG900"), -- XC7Z045-2FFG900C UART => C_BOARD_UART_DTE_921600_NONE, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("ZedBoard"), FPGADevice => conf("XC7Z020-1CLG484"), -- XC7Z020-1CLG484 UART => C_BOARD_UART_DTE_921600_NONE, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ),( BoardName => conf("AC701"), FPGADevice => conf("XC7A200T-2FBG676C"), -- XC7A200T-2FBG676C UART => C_BOARD_UART_DTE_921600_NONE, Ethernet => ( 0 => C_BOARD_ETH_SOFT_GMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("KC705"), FPGADevice => conf("XC7K325T-2FFG900C"), -- XC7K325T-2FFG900C UART => C_BOARD_UART_DTE_921600_NONE, Ethernet => ( 0 => C_BOARD_ETH_SOFT_GMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("ML505"), FPGADevice => conf("XC5VLX50T-1FF1136"), -- XC5VLX50T-1FF1136 UART => C_BOARD_UART_DCE_115200_NONE, Ethernet => ( 0 => C_BOARD_ETH_HARD_GMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("ML506"), FPGADevice => conf("XC5VSX50T-1FFG1136"), -- XC5VSX50T-1FFG1136 UART => C_BOARD_UART_DCE_115200_NONE, Ethernet => ( 0 => C_BOARD_ETH_HARD_GMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("ML507"), FPGADevice => conf("XC5VFX70T-1FFG1136"), -- XC5VFX70T-1FFG1136 UART => C_BOARD_UART_DCE_115200_NONE, Ethernet => ( 0 => C_BOARD_ETH_HARD_GMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("XUPV5"), FPGADevice => conf("XC5VLX110T-1FF1136"), -- XC5VLX110T-1FF1136 UART => C_BOARD_UART_DCE_115200_NONE, Ethernet => ( 0 => C_BOARD_ETH_HARD_GMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("ML605"), FPGADevice => conf("XC6VLX240T-1FF1156"), -- XC6VLX240T-1FF1156 UART => C_BOARD_UART_EMPTY, Ethernet => ( 0 => C_BOARD_ETH_HARD_GMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("VC707"), FPGADevice => conf("XC7VX485T-2FFG1761C"), -- XC7VX485T-2FFG1761C UART => C_BOARD_UART_DTE_921600_NONE, Ethernet => ( 0 => C_BOARD_ETH_SOFT_SGMII_88E1111, others => C_BOARD_ETH_EMPTY), EthernetCount => 1 ),( BoardName => conf("VC709"), FPGADevice => conf("XC7VX690T-2FFG1761C"), -- XC7VX690T-2FFG1761C UART => C_BOARD_UART_DTE_921600_NONE, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ), -- Custom Board (MUST BE LAST ONE) -- ========================================================================= ( BoardName => conf("Custom"), FPGADevice => conf("Device is unknown for a custom board"), UART => C_BOARD_UART_EMPTY, Ethernet => C_BOARD_ETH_NONE, EthernetCount => 0 ) ); end package body; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library PoC; use PoC.my_config.all; use PoC.my_project.all; use PoC.config_private.all; use PoC.utils.all; package config is constant PROJECT_DIR : string := MY_PROJECT_DIR; constant OPERATING_SYSTEM : string := MY_OPERATING_SYSTEM; -- List of known FPGA / Chip vendors -- --------------------------------------------------------------------------- type T_VENDOR is ( VENDOR_UNKNOWN, VENDOR_GENERIC, VENDOR_ALTERA, VENDOR_LATTICE, VENDOR_XILINX ); -- List of known synthesis tool chains -- --------------------------------------------------------------------------- type T_SYNTHESIS_TOOL is ( SYNTHESIS_TOOL_UNKNOWN, SYNTHESIS_TOOL_GENERIC, SYNTHESIS_TOOL_ALTERA_QUARTUS2, SYNTHESIS_TOOL_LATTICE_LSE, SYNTHESIS_TOOL_SYNOPSIS, SYNTHESIS_TOOL_XILINX_XST, SYNTHESIS_TOOL_XILINX_VIVADO ); -- List of known device families -- --------------------------------------------------------------------------- type T_DEVICE_FAMILY is ( DEVICE_FAMILY_UNKNOWN, DEVICE_FAMILY_GENERIC, -- Altera DEVICE_FAMILY_ARRIA, DEVICE_FAMILY_CYCLONE, DEVICE_FAMILY_STRATIX, -- Lattice DEVICE_FAMILY_ICE, DEVICE_FAMILY_MACHXO, DEVICE_FAMILY_ECP, -- Xilinx DEVICE_FAMILY_SPARTAN, DEVICE_FAMILY_ZYNQ, DEVICE_FAMILY_ARTIX, DEVICE_FAMILY_KINTEX, DEVICE_FAMILY_VIRTEX ); type T_DEVICE_SERIES is ( DEVICE_SERIES_UNKNOWN, DEVICE_SERIES_GENERIC, -- Xilinx FPGA series DEVICE_SERIES_7_SERIES, DEVICE_SERIES_ULTRASCALE, DEVICE_SERIES_ULTRASCALE_PLUS ); -- List of known devices -- --------------------------------------------------------------------------- type T_DEVICE is ( DEVICE_UNKNOWN, DEVICE_GENERIC, -- Altera DEVICE_MAX2, DEVICE_MAX10, -- Altera.Max DEVICE_ARRIA1, DEVICE_ARRIA2, DEVICE_ARRIA5, DEVICE_ARRIA10, -- Altera.Arria DEVICE_CYCLONE1, DEVICE_CYCLONE2, DEVICE_CYCLONE3, DEVICE_CYCLONE4, -- Altera.Cyclone DEVICE_CYCLONE5, -- DEVICE_STRATIX1, DEVICE_STRATIX2, DEVICE_STRATIX3, DEVICE_STRATIX4, -- Altera.Stratix DEVICE_STRATIX5, DEVICE_STRATIX10, -- -- Lattice DEVICE_ICE40, DEVICE_ICE65, DEVICE_ICE5, -- Lattice.iCE DEVICE_MACHXO, DEVICE_MACHXO2, -- Lattice.MachXO DEVICE_ECP3, DEVICE_ECP4, DEVICE_ECP5, -- Lattice.ECP -- Xilinx DEVICE_SPARTAN3, DEVICE_SPARTAN6, -- Xilinx.Spartan DEVICE_ZYNQ7, DEVICE_ZYNQ_ULTRA_PLUS, -- Xilinx.Zynq DEVICE_ARTIX7, -- Xilinx.Artix DEVICE_KINTEX7, DEVICE_KINTEX_ULTRA, DEVICE_KINTEX_ULTRA_PLUS, -- Xilinx.Kintex DEVICE_VIRTEX5, DEVICE_VIRTEX6, DEVICE_VIRTEX7, -- Xilinx.Virtex DEVICE_VIRTEX_ULTRA, DEVICE_VIRTEX_ULTRA_PLUS -- ); -- List of known device subtypes -- --------------------------------------------------------------------------- type T_DEVICE_SUBTYPE is ( DEVICE_SUBTYPE_NONE, DEVICE_SUBTYPE_GENERIC, -- Altera DEVICE_SUBTYPE_E, DEVICE_SUBTYPE_GS, DEVICE_SUBTYPE_GX, DEVICE_SUBTYPE_GT, -- Lattice DEVICE_SUBTYPE_U, DEVICE_SUBTYPE_UM, -- Xilinx DEVICE_SUBTYPE_X, DEVICE_SUBTYPE_T, DEVICE_SUBTYPE_XT, DEVICE_SUBTYPE_HT, DEVICE_SUBTYPE_LX, DEVICE_SUBTYPE_SXT, DEVICE_SUBTYPE_LXT, DEVICE_SUBTYPE_TXT, DEVICE_SUBTYPE_FXT, DEVICE_SUBTYPE_CXT, DEVICE_SUBTYPE_HXT ); -- List of known transceiver (sub-)types -- --------------------------------------------------------------------------- type T_TRANSCEIVER is ( TRANSCEIVER_NONE, TRANSCEIVER_GENERIC, -- TODO: add more? Altera transceivers -- Altera transceivers TRANSCEIVER_GXB, -- Altera GXB transceiver --Lattice transceivers TRANSCEIVER_MGT, -- Lattice transceiver -- Xilinx transceivers TRANSCEIVER_GTP_DUAL, TRANSCEIVER_GTPE1, TRANSCEIVER_GTPE2, -- Xilinx GTP transceivers TRANSCEIVER_GTX, TRANSCEIVER_GTXE1, TRANSCEIVER_GTXE2, -- Xilinx GTX transceivers TRANSCEIVER_GTH, TRANSCEIVER_GTHE1, TRANSCEIVER_GTHE2, -- Xilinx GTH transceivers TRANSCEIVER_GTZ, -- Xilinx GTZ transceivers TRANSCEIVER_GTY -- Xilinx GTY transceivers ); -- Properties of an FPGA architecture -- =========================================================================== type T_DEVICE_INFO is record Vendor : T_VENDOR; Device : T_DEVICE; DevFamily : T_DEVICE_FAMILY; DevGeneration : natural; DevNumber : natural; DevSubType : T_DEVICE_SUBTYPE; DevSeries : T_DEVICE_SERIES; TransceiverType : T_TRANSCEIVER; LUT_FanIn : positive; end record; -- Functions extracting board and PCB properties from "MY_BOARD" -- which is declared in package "my_config". -- =========================================================================== function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return natural; function BOARD_INFO(BoardConfig : string := C_BOARD_STRING_EMPTY) return T_BOARD_INFO; function BOARD_NAME(BoardConfig : string := C_BOARD_STRING_EMPTY) return string; function BOARD_DEVICE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string; function BOARD_UART_BAUDRATE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string; -- Functions extracting device and architecture properties from "MY_DEVICE" -- which is declared in package "my_config". -- =========================================================================== function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR; function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL; function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE; function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY; function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SUBTYPE; function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SERIES; function DEVICE_GENERATION(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural; function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural; function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER; function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive; function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO; -- force FSM to predefined encoding in debug mode function getFSMEncoding_gray(debug : boolean) return string; end package; package body config is -- inlined function from PoC.utils, to break dependency -- =========================================================================== function ite(cond : boolean; value1 : string; value2 : string) return string is begin if cond then return value1; else return value2; end if; end function; -- chr_is* function function chr_isDigit(chr : character) return boolean is begin return ((character'pos('0') <= CHARACTER'pos(chr)) and (character'pos(chr) <= CHARACTER'pos('9'))); end function; function chr_isAlpha(chr : character) return boolean is begin return (((character'pos('a') <= CHARACTER'pos(chr)) and (character'pos(chr) <= CHARACTER'pos('z'))) or ((character'pos('A') <= CHARACTER'pos(chr)) and (character'pos(chr) <= CHARACTER'pos('Z')))); end function; function str_length(str : string) return natural is begin for i in str'range loop if (str(i) = C_POC_NUL) then return i - str'low; end if; end loop; return str'length; end function; function str_trim(str : string) return string is begin for i in str'range loop if (str(i) = C_POC_NUL) then return str(str'low to i-1); end if; end loop; return str; end function; function str_imatch(str1 : string; str2 : string) return boolean is constant len : natural := imin(str1'length, str2'length); variable chr1 : character; variable chr2 : character; begin -- if both strings are empty if ((str1'length = 0 ) and (str2'length = 0)) then return TRUE; end if; -- compare char by char for i in 0 to len-1 loop chr1 := str1(str1'low + i); chr2 := str2(str2'low + i); if (character'pos('A') <= CHARACTER'pos(chr1)) and (character'pos(chr1) <= CHARACTER'pos('Z')) then chr1 := character'val(CHARACTER'pos(chr1) - character'pos('A') + CHARACTER'pos('a')); end if; if (character'pos('A') <= CHARACTER'pos(chr2)) and (character'pos(chr2) <= CHARACTER'pos('Z')) then chr2 := character'val(CHARACTER'pos(chr2) - character'pos('A') + CHARACTER'pos('a')); end if; if (chr1 /= chr2) then return FALSE; elsif ((chr1 = C_POC_NUL) xor (chr2 = C_POC_NUL)) then return FALSE; elsif ((chr1 = C_POC_NUL) and (chr2 = C_POC_NUL)) then return TRUE; end if; end loop; -- check special cases, if ((str1'length = len) and (str2'length = len)) then -- both strings are fully consumed and equal return TRUE; elsif (str1'length > len) then return (str1(str1'low + len) = C_POC_NUL); -- str1 is longer, but str_length equals len else return (str2(str2'low + len) = C_POC_NUL); -- str2 is longer, but str_length equals len end if; end function; function str_find(str : string; pattern : string; start : natural := 0) return boolean is begin for i in imax(str'low, start) to (str'high - pattern'length + 1) loop exit when (str(i) = C_POC_NUL); if (str(i to i + pattern'length - 1) = pattern) then return TRUE; end if; end loop; return FALSE; end function; -- private functions required by board description -- ModelSim requires that this functions is defined before it is used below. -- =========================================================================== function getLocalDeviceString(DeviceString : string) return string is constant ConstNUL : string(1 to 1) := (others => C_POC_NUL); constant MY_DEVICE_STR : string := BOARD_DEVICE; variable Result : string(1 to T_DEVICE_STRING'length); begin Result := (others => C_POC_NUL); -- report DeviceString for debugging if (POC_VERBOSE = TRUE) then report "getLocalDeviceString: DeviceString='" & str_trim(DeviceString) & "' MY_DEVICE='" & str_trim(MY_DEVICE) & "' MY_DEVICE_STR='" & str_trim(MY_DEVICE_STR) & "'" severity NOTE; end if; -- if DeviceString is populated if ((str_length(DeviceString) /= 0) and (str_imatch(DeviceString, "None") = FALSE)) then Result(1 to imin(T_DEVICE_STRING'length, imax(1, DeviceString'length))) := ite((DeviceString'length > 0), DeviceString(1 to imin(T_DEVICE_STRING'length, DeviceString'length)), ConstNUL); -- if MY_DEVICE is set, prefer it elsif ((str_length(MY_DEVICE) /= 0) and (str_imatch(MY_DEVICE, "None") = FALSE)) then Result(1 to imin(T_DEVICE_STRING'length, imax(1, MY_DEVICE'length))) := ite((MY_DEVICE'length > 0), MY_DEVICE(1 to imin(T_DEVICE_STRING'length, MY_DEVICE'length)), ConstNUL); -- otherwise use MY_BOARD else Result(1 to imin(T_DEVICE_STRING'length, imax(1, MY_DEVICE_STR'length))) := ite((MY_DEVICE_STR'length > 0), MY_DEVICE_STR(1 to imin(T_DEVICE_STRING'length, MY_DEVICE_STR'length)), ConstNUL); end if; return Result; end function; function extractFirstNumber(str : string) return natural is variable low : integer; variable high : integer; variable Result : natural; variable Digit : integer; begin low := -1; high := -1; for i in str'low to str'high loop if chr_isDigit(str(i)) then low := i; exit; end if; end loop; -- abort if no digit can be found if (low = -1) then return 0; end if; for i in (low + 1) to str'high loop if chr_isAlpha(str(i)) then high := i - 1; exit; end if; end loop; if (high = -1) then return 0; end if; -- return INTEGER'value(str(low to high)); -- 'value(...) is not supported by Vivado Synth 2014.1 -- convert substring to a number for i in low to high loop if (chr_isDigit(str(i)) = FALSE) then return 0; end if; Result := (Result * 10) + (character'pos(str(i)) - character'pos('0')); end loop; return Result; end function; -- Public functions -- =========================================================================== -- TODO: comment function BOARD(BoardConfig : string := C_BOARD_STRING_EMPTY) return natural is constant MY_BRD : T_BOARD_CONFIG_STRING := ite((BoardConfig /= C_BOARD_STRING_EMPTY), conf(BoardConfig), conf(MY_BOARD)); constant BOARD_NAME : string := str_trim(MY_BRD); begin if (POC_VERBOSE = TRUE) then report "PoC configuration: Used board is '" & BOARD_NAME & "'" severity NOTE; end if; for i in C_BOARD_INFO_LIST'range loop if str_imatch(BOARD_NAME, C_BOARD_INFO_LIST(i).BoardName) then return i; end if; end loop; report "Unknown board name in MY_BOARD = " & MY_BRD & "." severity failure; return C_BOARD_INFO_LIST'high; end function; function BOARD_INFO(BoardConfig : string := C_BOARD_STRING_EMPTY) return T_BOARD_INFO is constant BRD : natural := BOARD(BoardConfig); begin return C_BOARD_INFO_LIST(BRD); end function; -- TODO: comment function BOARD_NAME(BoardConfig : string := C_BOARD_STRING_EMPTY) return string is constant BRD : natural := BOARD(BoardConfig); begin return str_trim(C_BOARD_INFO_LIST(BRD).BoardName); end function; -- TODO: comment function BOARD_DEVICE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string is constant BRD : natural := BOARD(BoardConfig); begin return str_trim(C_BOARD_INFO_LIST(BRD).FPGADevice); end function; function BOARD_UART_BAUDRATE(BoardConfig : string := C_BOARD_STRING_EMPTY) return string is constant BRD : natural := BOARD(BoardConfig); begin return str_trim(C_BOARD_INFO_LIST(BRD).UART.BaudRate); end function; -- purpose: extract vendor from MY_DEVICE function VENDOR(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_VENDOR is constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString); constant VEN_STR2 : string(1 to 2) := MY_DEV(1 to 2); -- TODO: test if alias declarations also work out on all platforms constant VEN_STR3 : string(1 to 3) := MY_DEV(1 to 3); -- TODO: test if alias declarations also work out on all platforms begin case VEN_STR2 is when "GE" => return VENDOR_GENERIC; when "EP" => return VENDOR_ALTERA; when "XC" => return VENDOR_XILINX; when others => null; end case; case VEN_STR3 is when "iCE" => return VENDOR_LATTICE; -- iCE devices when "LCM" => return VENDOR_LATTICE; -- MachXO device when "LFE" => return VENDOR_LATTICE; -- ECP devices when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure; -- return statement is explicitly missing otherwise XST won't stop end case; end function; function SYNTHESIS_TOOL(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_SYNTHESIS_TOOL is constant VEN : T_VENDOR := VENDOR(DeviceString); begin case VEN is when VENDOR_GENERIC => return SYNTHESIS_TOOL_GENERIC; when VENDOR_ALTERA => return SYNTHESIS_TOOL_ALTERA_QUARTUS2; when VENDOR_LATTICE => return SYNTHESIS_TOOL_LATTICE_LSE; --return SYNTHESIS_TOOL_SYNOPSIS; when VENDOR_XILINX => if (1 fs /= 1 us) then return SYNTHESIS_TOOL_XILINX_XST; else return SYNTHESIS_TOOL_XILINX_VIVADO; end if; when others => return SYNTHESIS_TOOL_UNKNOWN; end case; end function; -- purpose: extract device from MY_DEVICE function DEVICE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE is constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString); constant VEN : T_VENDOR := VENDOR(DeviceString); constant DEV_STR : string(3 to 4) := MY_DEV(3 to 4); -- TODO: test if alias declarations also work out on all platforms begin case VEN is when VENDOR_GENERIC => if (MY_DEV(1 to 7) = "GENERIC") then return DEVICE_GENERIC; else report "Unknown Generic device in MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when VENDOR_ALTERA => case DEV_STR is when "1C" => return DEVICE_CYCLONE1; when "2C" => return DEVICE_CYCLONE2; when "3C" => return DEVICE_CYCLONE3; when "1S" => return DEVICE_STRATIX1; when "2S" => return DEVICE_STRATIX2; when "4S" => return DEVICE_STRATIX4; when "5S" => return DEVICE_STRATIX5; when others => report "Unknown Altera device in MY_DEVICE = '" & MY_DEV & "'" severity failure; end case; when VENDOR_LATTICE => if (MY_DEV(1 to 6) = "LCMX02") then return DEVICE_MACHXO2; elsif (MY_DEV(1 to 5) = "LCMX0") then return DEVICE_MACHXO; elsif (MY_DEV(1 to 5) = "iCE40") then return DEVICE_ICE40; elsif (MY_DEV(1 to 5) = "iCE65") then return DEVICE_ICE65; elsif (MY_DEV(1 to 4) = "iCE5") then return DEVICE_ICE5; elsif (MY_DEV(1 to 4) = "LFE3") then return DEVICE_ECP3; elsif (MY_DEV(1 to 4) = "LFE4") then return DEVICE_ECP4; elsif (MY_DEV(1 to 4) = "LFE5") then return DEVICE_ECP5; else report "Unknown Lattice device in MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when VENDOR_XILINX => case DEV_STR is when "7A" => return DEVICE_ARTIX7; when "7K" => return DEVICE_KINTEX7; when "KU" => return DEVICE_KINTEX_ULTRA; when "3S" => return DEVICE_SPARTAN3; when "6S" => return DEVICE_SPARTAN6; when "5V" => return DEVICE_VIRTEX5; when "6V" => return DEVICE_VIRTEX6; when "7V" => return DEVICE_VIRTEX7; when "VU" => return DEVICE_VIRTEX_ULTRA; when "7Z" => return DEVICE_ZYNQ7; when others => report "Unknown Xilinx device in MY_DEVICE = '" & MY_DEV & "'" severity failure; end case; when others => report "Unknown vendor in MY_DEVICE = " & MY_DEV & "." severity failure; -- return statement is explicitly missing otherwise XST won't stop end case; end function; -- purpose: extract device from MY_DEVICE function DEVICE_FAMILY(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_FAMILY is constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString); constant VEN : T_VENDOR := VENDOR(DeviceString); constant FAM_CHAR : character := MY_DEV(4); begin case VEN is when VENDOR_GENERIC => return DEVICE_FAMILY_GENERIC; when VENDOR_ALTERA => case FAM_CHAR is when 'C' => return DEVICE_FAMILY_CYCLONE; when 'S' => return DEVICE_FAMILY_STRATIX; when others => report "Unknown Altera device family in MY_DEVICE = '" & MY_DEV & "'" severity failure; end case; when VENDOR_LATTICE => case FAM_CHAR is --when 'M' => return DEVICE_FAMILY_MACHXO; when 'E' => return DEVICE_FAMILY_ECP; when others => report "Unknown Lattice device family in MY_DEVICE = '" & MY_DEV & "'" severity failure; end case; when VENDOR_XILINX => case FAM_CHAR is when 'A' => return DEVICE_FAMILY_ARTIX; when 'K' => return DEVICE_FAMILY_KINTEX; when 'S' => return DEVICE_FAMILY_SPARTAN; when 'V' => return DEVICE_FAMILY_VIRTEX; when 'Z' => return DEVICE_FAMILY_ZYNQ; when others => report "Unknown Xilinx device family in MY_DEVICE = '" & MY_DEV & "'" severity failure; end case; when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure; -- return statement is explicitly missing otherwise XST won't stop end case; end function; -- some devices share some common features: e.g. XADC, BlockRAM, ... function DEVICE_SERIES(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SERIES is constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString); constant DEV : T_DEVICE := DEVICE(DeviceString); begin case DEV is when DEVICE_GENERIC => return DEVICE_SERIES_GENERIC; -- all Xilinx ****7 devices when DEVICE_ARTIX7 | DEVICE_KINTEX7 | DEVICE_VIRTEX7 | DEVICE_ZYNQ7 => return DEVICE_SERIES_7_SERIES; -- all Xilinx ****UltraScale devices when DEVICE_KINTEX_ULTRA | DEVICE_VIRTEX_ULTRA => return DEVICE_SERIES_ULTRASCALE; -- all Xilinx ****UltraScale+ devices when DEVICE_KINTEX_ULTRA_PLUS | DEVICE_VIRTEX_ULTRA_PLUS | DEVICE_ZYNQ_ULTRA_PLUS => return DEVICE_SERIES_ULTRASCALE_PLUS; when others => return DEVICE_SERIES_UNKNOWN; end case; end function; function DEVICE_GENERATION(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is constant SERIES : T_DEVICE_SERIES := DEVICE_SERIES(DeviceString); begin if (SERIES = DEVICE_SERIES_7_SERIES) then return 7; else return 0; end if; end function; function DEVICE_NUMBER(DeviceString : string := C_DEVICE_STRING_EMPTY) return natural is constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString); constant VEN : T_VENDOR := VENDOR(DeviceString); begin case VEN is when VENDOR_GENERIC => return 0; when VENDOR_ALTERA => return extractFirstNumber(MY_DEV(5 to MY_DEV'high)); when VENDOR_LATTICE => return extractFirstNumber(MY_DEV(6 to MY_DEV'high)); when VENDOR_XILINX => return extractFirstNumber(MY_DEV(5 to MY_DEV'high)); when others => report "Unknown vendor in MY_DEVICE = '" & MY_DEV & "'" severity failure; -- return statement is explicitly missing otherwise XST won't stop end case; end function; function DEVICE_SUBTYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_SUBTYPE is constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString); constant DEV : T_DEVICE := DEVICE(MY_DEV); constant DEV_SUB_STR : string(1 to 2) := MY_DEV(5 to 6); -- WORKAROUND: for GHDL begin case DEV is when DEVICE_GENERIC => return DEVICE_SUBTYPE_GENERIC; -- TODO: extract Arria GX subtype when DEVICE_ARRIA1 => report "TODO: parse Arria device subtype." severity failure; return DEVICE_SUBTYPE_NONE; -- TODO: extract ArriaII GX,GZ subtype when DEVICE_ARRIA2 => report "TODO: parse ArriaII device subtype." severity failure; return DEVICE_SUBTYPE_NONE; -- TODO: extract ArriaV GX, GT, SX, GZ subtype when DEVICE_ARRIA5 => report "TODO: parse ArriaV device subtype." severity failure; return DEVICE_SUBTYPE_NONE; -- TODO: extract Arria10 GX, GT, SX subtype when DEVICE_ARRIA10 => report "TODO: parse Arria10 device subtype." severity failure; return DEVICE_SUBTYPE_NONE; -- Altera Cyclon I, II, III, IV, V devices have no subtype when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 | DEVICE_CYCLONE4 | DEVICE_CYCLONE5 => return DEVICE_SUBTYPE_NONE; when DEVICE_STRATIX2 => if chr_isDigit(DEV_SUB_STR(1)) then return DEVICE_SUBTYPE_NONE; elsif (DEV_SUB_STR = "GX") then return DEVICE_SUBTYPE_GX; else report "Unknown Stratix II subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_STRATIX4 => if (DEV_SUB_STR(1) = 'E') then return DEVICE_SUBTYPE_E; elsif (DEV_SUB_STR = "GX") then return DEVICE_SUBTYPE_GX; -- elsif (DEV_SUB_STR = "GT") then return DEVICE_SUBTYPE_GT; else report "Unknown Stratix IV subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; -- TODO: extract StratixV subtype when DEVICE_STRATIX5 => report "TODO: parse Stratix V device subtype." severity failure; return DEVICE_SUBTYPE_NONE; when DEVICE_ECP5 => if (DEV_SUB_STR(1) = 'U') then return DEVICE_SUBTYPE_U; elsif (DEV_SUB_STR = "UM") then return DEVICE_SUBTYPE_UM; else report "Unknown Lattice ECP5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_SPARTAN3 => report "TODO: parse Spartan3 / Spartan3E / Spartan3AN device subtype." severity failure; return DEVICE_SUBTYPE_NONE; when DEVICE_SPARTAN6 => if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX; elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT; else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_VIRTEX5 => if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX; elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT; elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT; elsif ((DEV_SUB_STR = "TX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_TXT; elsif ((DEV_SUB_STR = "FX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_FXT; else report "Unknown Virtex-5 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_VIRTEX6 => if ((DEV_SUB_STR = "LX") and (not str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LX; elsif ((DEV_SUB_STR = "LX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_LXT; elsif ((DEV_SUB_STR = "SX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_SXT; elsif ((DEV_SUB_STR = "CX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_CXT; elsif ((DEV_SUB_STR = "HX") and ( str_find(MY_DEV(7 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HXT; else report "Unknown Virtex-6 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_ARTIX7 => if ( ( str_find(MY_DEV(5 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T; else report "Unknown Artix-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_KINTEX7 => if ( ( str_find(MY_DEV(5 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T; else report "Unknown Kintex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_KINTEX_ULTRA => return DEVICE_SUBTYPE_NONE; when DEVICE_KINTEX_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE; when DEVICE_VIRTEX7 => if ( ( str_find(MY_DEV(5 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_T; elsif ((DEV_SUB_STR(1) = 'X') and ( str_find(MY_DEV(6 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_XT; elsif ((DEV_SUB_STR(1) = 'H') and ( str_find(MY_DEV(6 to MY_DEV'high), "T"))) then return DEVICE_SUBTYPE_HT; else report "Unknown Virtex-7 subtype: MY_DEVICE = '" & MY_DEV & "'" severity failure; end if; when DEVICE_VIRTEX_ULTRA => return DEVICE_SUBTYPE_NONE; when DEVICE_VIRTEX_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE; when DEVICE_ZYNQ7 => return DEVICE_SUBTYPE_NONE; when DEVICE_ZYNQ_ULTRA_PLUS => return DEVICE_SUBTYPE_NONE; when others => report "Device sub-type is unknown for the given device." severity failure; -- return statement is explicitly missing otherwise XST won't stop end case; end function; function LUT_FANIN(DeviceString : string := C_DEVICE_STRING_EMPTY) return positive is constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString); constant DEV : T_DEVICE := DEVICE(DeviceString); constant SERIES : T_DEVICE_SERIES := DEVICE_SERIES(DeviceString); begin case SERIES is when DEVICE_SERIES_GENERIC => return 6; when DEVICE_SERIES_7_SERIES | DEVICE_SERIES_ULTRASCALE | DEVICE_SERIES_ULTRASCALE_PLUS => return 6; when others => null; end case; case DEV is when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return 4; when DEVICE_STRATIX1 | DEVICE_STRATIX2 => return 4; when DEVICE_STRATIX4 | DEVICE_STRATIX5 => return 6; when DEVICE_ECP5 => return 4; when DEVICE_SPARTAN3 => return 4; when DEVICE_SPARTAN6 => return 6; when DEVICE_VIRTEX5 | DEVICE_VIRTEX6 => return 6; when others => report "LUT fan-in is unknown for the given device." severity failure; -- return statement is explicitly missing otherwise XST won't stop end case; end function; function TRANSCEIVER_TYPE(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_TRANSCEIVER is constant MY_DEV : string(1 to 32) := getLocalDeviceString(DeviceString); constant DEV : T_DEVICE := DEVICE(DeviceString); constant DEV_NUM : natural := DEVICE_NUMBER(DeviceString); constant DEV_SUB : T_DEVICE_SUBTYPE := DEVICE_SUBTYPE(DeviceString); begin case DEV is when DEVICE_GENERIC => return TRANSCEIVER_GENERIC; when DEVICE_MAX2 | DEVICE_MAX10 => return TRANSCEIVER_NONE; -- Altera MAX II, 10 devices have no transceivers when DEVICE_CYCLONE1 | DEVICE_CYCLONE2 | DEVICE_CYCLONE3 => return TRANSCEIVER_NONE; -- Altera Cyclon I, II, III devices have no transceivers when DEVICE_STRATIX2 => return TRANSCEIVER_GXB; when DEVICE_STRATIX4 => return TRANSCEIVER_GXB; --when DEVICE_STRATIX5 => return TRANSCEIVER_GXB; when DEVICE_ECP5 => return TRANSCEIVER_MGT; when DEVICE_SPARTAN3 => return TRANSCEIVER_NONE; -- Xilinx Spartan3 devices have no transceivers when DEVICE_SPARTAN6 => case DEV_SUB is when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE; when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTPE1; when others => report "Unknown Spartan-6 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure; end case; when DEVICE_VIRTEX5 => case DEV_SUB is when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE; when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTP_DUAL; when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTP_DUAL; when DEVICE_SUBTYPE_TXT => return TRANSCEIVER_GTX; when DEVICE_SUBTYPE_FXT => return TRANSCEIVER_GTX; when others => report "Unknown Virtex-5 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure; end case; when DEVICE_VIRTEX6 => case DEV_SUB is when DEVICE_SUBTYPE_LX => return TRANSCEIVER_NONE; when DEVICE_SUBTYPE_SXT => return TRANSCEIVER_GTXE1; when DEVICE_SUBTYPE_LXT => return TRANSCEIVER_GTXE1; when DEVICE_SUBTYPE_HXT => return TRANSCEIVER_GTXE1; when others => report "Unknown Virtex-6 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure; end case; when DEVICE_ARTIX7 => return TRANSCEIVER_GTPE2; when DEVICE_KINTEX7 => return TRANSCEIVER_GTXE2; when DEVICE_VIRTEX7 => case DEV_SUB is when DEVICE_SUBTYPE_T => return TRANSCEIVER_GTXE2; when DEVICE_SUBTYPE_XT => if (DEV_NUM = 485) then return TRANSCEIVER_GTXE2; else return TRANSCEIVER_GTHE2; end if; when DEVICE_SUBTYPE_HT => return TRANSCEIVER_GTHE2; when others => report "Unknown Virtex-7 subtype: " & T_DEVICE_SUBTYPE'image(DEV_SUB) severity failure; end case; when DEVICE_ZYNQ7 => case DEV_NUM is when 10 | 20 => return TRANSCEIVER_NONE; when 15 => return TRANSCEIVER_GTPE2; when others => return TRANSCEIVER_GTXE2; end case; when others => report "Unknown device." severity failure; -- return statement is explicitly missing otherwise XST won't stop end case; end function; -- purpose: extract architecture properties from DEVICE function DEVICE_INFO(DeviceString : string := C_DEVICE_STRING_EMPTY) return T_DEVICE_INFO is variable Result : T_DEVICE_INFO; begin Result.Vendor := VENDOR(DeviceString); Result.Device := DEVICE(DeviceString); Result.DevFamily := DEVICE_FAMILY(DeviceString); Result.DevSubType := DEVICE_SUBTYPE(DeviceString); Result.DevSeries := DEVICE_SERIES(DeviceString); Result.DevGeneration := DEVICE_GENERATION(DeviceString); Result.DevNumber := DEVICE_NUMBER(DeviceString); Result.TransceiverType := TRANSCEIVER_TYPE(DeviceString); Result.LUT_FanIn := LUT_FANIN(DeviceString); return Result; end function; -- force FSM to predefined encoding in debug mode function getFSMEncoding_gray(debug : boolean) return string is begin if (debug = true) then return "gray"; else case VENDOR is when VENDOR_ALTERA => return "default"; --when VENDOR_LATTICE => return "default"; when VENDOR_XILINX => return "auto"; when others => report "Unknown vendor." severity failure; -- return statement is explicitly missing otherwise XST won't stop end case; end if; end function; end package body;

agpl-3.0

0616c1009eb9be89f88676e8265d82c0

malkadi/FGPU

bitstreams/settings_and_utilization/V2_2CUs_float.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 1; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data por0s constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FSQRT_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

522896b227d45429c7091df95c7bafb7

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_no_float_area_estimation.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 1; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

e481914e4dad03e6266c90806db4bb1c

preusser/q27

src/vhdl/top/xilinx/s3sk_queens_uart.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2015 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity s3sk_queens_uart is generic ( N : positive := 27; L : positive := 2; SOLVERS : positive := 9; COUNT_CYCLES : boolean := false; CLK_FREQ : positive := 50000000; CLK_MUL : positive := 22; CLK_DIV : positive := 13; BAUDRATE : positive := 115200; SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte ); port ( clkx : in std_logic; rstx : in std_logic; rx : in std_logic; tx : out std_logic; leds : out std_logic_vector(7 downto 0) ); end s3sk_queens_uart; library IEEE; use IEEE.numeric_std.all; library UNISIM; use UNISIM.vcomponents.all; architecture rtl of s3sk_queens_uart is -- Global Control signal clk : std_logic; signal rst : std_logic; -- Solver Status signal avail : std_logic; begin ----------------------------------------------------------------------------- -- Generate Global Controls blkGlobal: block is signal clk_u : std_logic; -- Unbuffered Synthesized Clock signal rst_s : std_logic_vector(1 downto 0) := (others => '0'); begin -- Clock Generation DCM1 : DCM generic map ( CLKIN_PERIOD => 1000000000.0/real(CLK_FREQ), CLKIN_DIVIDE_BY_2 => FALSE, PHASE_SHIFT => 0, CLKFX_MULTIPLY => CLK_MUL, CLKFX_DIVIDE => CLK_DIV, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "NONE", -- only using clkfx DLL_FREQUENCY_MODE => "LOW", DFS_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, STARTUP_WAIT => TRUE -- Delay until DCM LOCK ) port map ( CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => clk_u, CLKFX180 => open, LOCKED => open, PSDONE => open, STATUS => open, CLKFB => open, CLKIN => clkx, PSCLK => '0', PSEN => '0', PSINCDEC => '0', RST => '0' ); clk_buf : BUFG port map ( I => clk_u, O => clk ); -- Reset Synchronization process(clk) begin if rising_edge(clk) then rst_s <= rstx & rst_s(rst_s'left downto 1); end if; end process; rst <= rst_s(0); end block blkGlobal; ---------------------------------------------------------------------------- -- Solver Chain chain: entity work.queens_uart generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES, CLK_FREQ => integer((real(CLK_MUL)*real(CLK_FREQ))/real(CLK_DIV)), BAUDRATE => BAUDRATE, SENTINEL => SENTINEL ) port map ( clk => clk, rst => rst, rx => rx, tx => tx, avail => avail ); ---------------------------------------------------------------------------- -- Basic Status Output leds <= std_logic_vector(to_unsigned((SOLVERS mod (2**(leds'length-1)-1))+1, leds'length-1)) & avail; end rtl;

agpl-3.0

d551a50b1d474843ae68ce7ef45bf474

malkadi/FGPU

RTL/ALU.vhd

-- libraries -------------------------------------------------------------------------------------------{{{ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library work; use work.all; use work.FGPU_definitions.all; ---------------------------------------------------------------------------------------------------------}}} entity ALU is -- {{{ port( rs_addr : in unsigned(REG_FILE_BLOCK_W-1 downto 0); -- level 1. rt_addr : in unsigned(REG_FILE_BLOCK_W-1 downto 0); -- level 1. rd_addr : in unsigned(REG_FILE_BLOCK_W-1 downto 0); -- level 1. regBlock_re : in std_logic_vector(N_REG_BLOCKS-1 downto 0); -- level 1. family : in std_logic_vector(FAMILY_W-1 downto 0); -- level 1. op_arith_shift : in op_arith_shift_type; -- level 6. code : in std_logic_vector(CODE_W-1 downto 0); -- level 6. immediate : in std_logic_vector(IMM_W-1 downto 0); -- level 6. rd_out : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- level 10. reg_we_mov : out std_logic := '0'; -- level 10. float_a : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- level 9. float_b : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- level 9. op_logical_v : in std_logic := '0'; -- level 14. res_low : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- level 16. res_high : out std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- level 16. reg_wrData : in slv32_array(N_REG_BLOCKS-1 downto 0) := (others=>(others=>'0')); -- level 18. reg_wrAddr : in reg_file_block_array(N_REG_BLOCKS-1 downto 0) := (others=>(others=>'0')); -- level 18. reg_we : in std_logic_vector(N_REG_BLOCKS-1 downto 0) := (others=>'0'); -- level 18. clk : in std_logic ); end ALU; -- }}} architecture Behavioral of ALU is -- signals definitions {{{ type regBlock_re_vec_type is array(natural range <>) of std_logic_vector(N_REG_BLOCKS-1 downto 0); signal regBlock_re_vec : regBlock_re_vec_type(6 downto 0) := (others=>(others=>'0')); -- attribute max_fanout of regBlock_re_vec : signal is 50; signal rs_vec, rt_vec, rd_vec : slv32_array(N_REG_BLOCKS-1 downto 0) := (others=>(others=>'0')); signal rs_a, rt_a : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal rs_b, rt_b : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal a, a_p0, c : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); signal b, b_shifted : std_logic_vector(DATA_W downto 0) := (others=>'0'); signal sra_sign : std_logic_vector(DATA_W downto 0) := (others=>'0'); signal sra_sign_v : std_logic := '0'; signal rs, rt, rd, rt_p0, rt_d0 : std_logic_vector(DATA_W-1 downto 0) := (others => '0'); signal shift : std_logic_vector(5 downto 0) := (others=>'0'); signal ignore : std_logic_vector(47-DATA_W-1 downto 0) := (others=>'0'); signal sub_op : std_logic := '0'; signal ce : std_logic := '0'; signal res_p0 : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); type immediate_vec_type is array(natural range <>) of std_logic_vector(IMM_W-1 downto 0); signal immediate_vec : immediate_vec_type(3 downto 0) := (others=>(others=>'0')); type op_arith_shift_vec_type is array(natural range <>) of op_arith_shift_type; signal op_arith_shift_vec : op_arith_shift_vec_type(2 downto 0) := (others => op_add); signal rs_addr_vec, rt_addr_vec : reg_file_block_array(3 downto 0) := (others=>(others=>'0')); signal rd_addr_vec : reg_file_block_array(3 downto 0) := (others=>(others=>'0')); type code_vec_type is array(natural range<>) of std_logic_vector(CODE_W-1 downto 0); signal code_vec : code_vec_type(2 downto 0) := (others=>(others=>'0')); signal res_low_p0 : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); -- level 8 signal res_logical : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); signal res_logical_vec : SLV32_ARRAY(4 downto 0) := (others=>(others=>'0')); signal op_logical_v_d0 : std_logic := '0'; signal a_logical, b_logical : std_logic_vector(DATA_W-1 downto 0) := (others=>'0'); signal instr_is_slt, instr_is_sltu : std_logic_vector(5 downto 0) := (others=>'0'); signal sltu_true : std_logic := '0'; signal rt_zero : std_logic := '0'; --}}} begin -- regFiles -------------------------------------------------------------------------------------------{{{ reg_blocks: for i in 0 to N_REG_BLOCKS-1 generate begin reg_file: entity regFile port map ( rs_addr => rs_addr_vec(rs_addr_vec'high-i), -- level i+2. rt_addr => rt_addr_vec(rt_addr_vec'high-i), -- level i+2. rd_addr => rd_addr_vec(rd_addr_vec'high-i), -- level i+2. re => regBlock_re_vec(regBlock_re_vec'high)(i), -- level i+2. rs => rs_vec(i), -- level i+7. rt => rt_vec(i), -- level i+6. rd => rd_vec(i), -- level i+8. we => reg_we(i), -- level 18. wrAddr => reg_wrAddr(i), -- level 18. wrData => reg_wrData(i), -- level 18. clk => clk ); end generate; ---------------------------------------------------------------------------------------------------------}}} -- logical -------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then res_logical_vec(res_logical_vec'high) <= res_logical; -- @ 11. res_logical_vec(res_logical_vec'high-1 downto 0) <= res_logical_vec(res_logical_vec'high downto 1); -- @ 12.->15. op_logical_v_d0 <= op_logical_v; -- @ 15. a_logical <= rs; --@ 9. if code_vec(code_vec'high-1)(0) = '1' then -- level 8. b_logical(DATA_W-1 downto IMM_ARITH_W) <= (others=>'0'); -- @ 9. b_logical(IMM_ARITH_W-1 downto 0) <= immediate_vec(immediate_vec'high-1)(IMM_ARITH_W-1 downto 0); -- @ 9. else b_logical <= rt; -- @ 9. end if; res_logical <= a_logical and b_logical; -- @ 10. if code_vec(code_vec'high-2)(1) = '1' then -- level 9. res_logical <= a_logical or b_logical; -- @ 10. end if; if code_vec(code_vec'high-2)(2) = '1' then res_logical <= a_logical xor b_logical; -- @ 10. end if; if code_vec(code_vec'high-2)(3) = '1' then res_logical <= a_logical nor b_logical; -- @ 10. end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- output mux -------------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then if op_logical_v_d0 = '0' then -- level 15. if instr_is_slt(0) = '1' then -- level 15. res_low <= (others=>'0'); res_low(0) <= res_low_p0(res_low_p0'high); -- @ 16. elsif instr_is_sltu(0) = '1' then -- level 15. res_low <= (others=>'0'); res_low(0) <= sltu_true; -- @ 16. else res_low <= res_low_p0; -- @ 16. end if; else res_low <= res_logical_vec(0); -- @ 16. end if; end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- pipelines & muxes ------------------------------------------------------------------------------------{{{ process(clk) begin if rising_edge(clk) then -- pipes {{{ rs_addr_vec(rs_addr_vec'high-1 downto 0) <= rs_addr_vec(rs_addr_vec'high downto 1); -- @ 1.->2. rs_addr_vec(rs_addr_vec'high) <= rs_addr; -- @ 2. rt_addr_vec(rt_addr_vec'high-1 downto 0) <= rt_addr_vec(rt_addr_vec'high downto 1); -- @ 1.->2. rt_addr_vec(rt_addr_vec'high) <= rt_addr; -- @ 2. rd_addr_vec(rd_addr_vec'high-1 downto 0) <= rd_addr_vec(rd_addr_vec'high downto 1); -- @ 1.->2. rd_addr_vec(rd_addr_vec'high) <= rd_addr; -- @ 2. op_arith_shift_vec(op_arith_shift_vec'high-1 downto 0) <= op_arith_shift_vec(op_arith_shift_vec'high downto 1); -- @ 8.->9. op_arith_shift_vec(op_arith_shift_vec'high) <= op_arith_shift; -- @ 7. code_vec(code_vec'high-1 downto 0) <= code_vec(code_vec'high downto 1); -- @ 8.->9. code_vec(code_vec'high) <= code; -- @ 7. immediate_vec(immediate_vec'high-1 downto 0) <= immediate_vec(immediate_vec'high downto 1); -- @ 8.->10. immediate_vec(immediate_vec'high) <= immediate; -- @ 7 regBlock_re_vec(regBlock_re_vec'high-1 downto 0) <= regBlock_re_vec(regBlock_re_vec'high downto 1); --@ 3.->8. regBlock_re_vec(regBlock_re_vec'high) <= regBlock_re; -- @ 2. --}}} -- @ 7 {{{ rt_p0 <= rt_vec(0); -- @ 7. for i in 1 to N_REG_BLOCKS-1 loop if regBlock_re_vec(2)(i) = '1' then rt_p0 <= rt_vec(i); -- @ i+7. end if; end loop; -- }}} -- @ 8 {{{ rt <= rt_p0; -- @ 8. rs <= rs_vec(0); -- @ 8. for i in 1 to N_REG_BLOCKS-1 loop if regBlock_re_vec(1)(i) = '1' then -- level 7. rs <= rs_vec(i); -- @ i+8. end if; end loop; if code_vec(code_vec'high)(CODE_W-1) = '0' then -- level 7. shift(5) <= '0'; -- @ 8. if code_vec(code_vec'high)(0) = '0' then -- level 7. shift(4 downto 0) <= rt_p0(4 downto 0); -- sll @8. else shift(4 downto 0) <= immediate_vec(immediate_vec'high)(4 downto 0); --slli -- @ 8. end if; else if code_vec(code_vec'high)(0) = '0' then -- shift right -- level 7 -- the width of port b of the mutiplier needs to be extended to 33, or the high part to 17 to enable a shift right logical with zero shift(5 downto 0) <= std_logic_vector("100000" - resize(unsigned(rt_p0(4 downto 0)), 6)); --srl & sra -- @ 8. else shift(5 downto 0) <= std_logic_vector("100000" - resize(unsigned(immediate_vec(immediate_vec'high)(4 downto 0)), 6)); -- srli & srai -- @ 8. end if; end if; -- }}} -- @ 9 {{{ float_a <= rs; -- @ 9. float_b <= rt; -- @ 9. rt_d0 <= rt; -- @ 9. rt_zero <= '0'; -- @ 9. if rt = (rt'reverse_range=>'0') then -- level 8. rt_zero <= '1'; -- @ 9. end if; b_shifted <= (others=>'0'); -- @ 9. b_shifted(to_integer(unsigned(shift))) <= '1'; -- @ 9. a_p0 <= rs; -- @ 9. rd <= rd_vec(0); -- @ 9. for i in 1 to N_REG_BLOCKS-1 loop if regBlock_re_vec(0)(i) = '1' then -- level 8. rd <= rd_vec(i); -- @ i+9. end if; end loop; -- }}} -- @ 10 {{{ rd_out <= rd; -- @ 10. a <= a_p0; -- @ 10. reg_we_mov <= rt_zero; -- movz, @10. if op_arith_shift_vec(0) = op_mov then -- level 9. if code_vec(code_vec'high-2)(CODE_W-1) = '0' then -- movn, level 9. reg_we_mov <= not rt_zero; -- @ 10. end if; end if; case op_arith_shift_vec(0) is -- level 9. when op_shift => if code_vec(code_vec'high-2)(CODE_W-1) = '1' and code_vec(code_vec'high-2)(CODE_W-2) = '1' and a_p0(DATA_W-1) = '1' then -- level 9. -- CODE_W-1 for right shift & CODE_W-2 for arithmetic & a_p0(DATA_W-1) for negative sra_sign <= b_shifted; -- @ 10. sra_sign_v <= '1'; -- @ 10. else sra_sign <= (others=>'0'); -- @ 10. sra_sign_v <= '0'; -- @ 10. end if; when others => sra_sign <= (others=>'0'); -- @ 10. sra_sign_v <= '0'; -- @ 10. end case; -- b {{{ case op_arith_shift_vec(0) is -- level 9. when op_lw => b(DATA_W downto 3) <= (others=>'0'); b(2 downto 0) <= code_vec(code_vec'high-2)(2 downto 0); -- @ 10. when op_mult => b(DATA_W) <= '0'; b(rt_d0'range) <= rt_d0; -- @ 10. when op_shift => b <= b_shifted; -- @ 10. when others => b <= (0=>'1', others=>'0'); -- @ 10. end case; -- }}} -- c {{{ case op_arith_shift_vec(0) is -- level 9. when op_add | op_slt => if code_vec(code_vec'high-2)(0) = '0' then -- "use immediate"-bit not set, level 9. c <= rt_d0; -- @ 10. elsif code_vec(code_vec'high-2)(CODE_W-1) = '0' then -- addi, slti, sltiu -- level 9. c <= std_logic_vector(resize(signed(immediate_vec(immediate_vec'high-2)(IMM_ARITH_W-1 downto 0)), DATA_W)); -- @ 10. elsif code_vec(code_vec'high-2)(CODE_W-2) = '0' then -- li -- level 4 & 4.5 c <= std_logic_vector(resize(signed(immediate_vec(immediate_vec'high-2)(IMM_W-1 downto 0)), DATA_W)); -- @ 10. else --lui c(DATA_W-1 downto DATA_W-IMM_W) <= immediate_vec(immediate_vec'high-2)(IMM_W-1 downto 0); -- @ 10. c(DATA_W-IMM_W-1 downto 0) <= rd(DATA_W-IMM_W-1 downto 0); -- @ 10. end if; when op_lw | op_ato => c <= rt_d0; -- @ 10. when op_lmem => c <= std_logic_vector(resize(signed(immediate_vec(immediate_vec'high-2)(IMM_ARITH_W-1 downto 0)), DATA_W)); -- @ 10. when op_mult => if code_vec(code_vec'high-2)(CODE_W-1) = '1' then -- macc -- level 9 c <= rd; -- @ 10. else c <= (others=>'0'); -- @ 10. end if; when op_bra => c <= rd; -- @ 10. when others => -- when op_shift | op_mov | nop c <= (others=>'0'); -- @ 10. end case; -- }}} -- slt & sltu {{{ instr_is_slt(instr_is_slt'high) <= '0'; -- @ 10. instr_is_sltu(instr_is_sltu'high) <= '0'; -- @ 10. if op_arith_shift_vec(0) = op_slt then -- level 9 if code_vec(code_vec'high-2)(2) = '0' then -- slt & slti, level 9 instr_is_slt(instr_is_slt'high) <= '1'; -- @ 10. else --sltu & sltiu instr_is_sltu(instr_is_sltu'high) <= '1'; -- @ 10. end if; end if; instr_is_slt(instr_is_slt'high-1 downto 0) <= instr_is_slt(instr_is_slt'high downto 1); -- @ 11.->15. instr_is_sltu(instr_is_sltu'high-1 downto 0) <= instr_is_sltu(instr_is_sltu'high downto 1); -- @ 11.->15. -- }}} sub_op <= '0'; -- @ 10. case op_arith_shift_vec(0) is -- level 9. when op_add | op_bra | op_slt => sub_op <= code_vec(code_vec'high-2)(1); -- @ 10. when op_lmem | op_lw | op_mult | op_shift | op_mov | op_ato=> end case; -- }}} end if; end process; ---------------------------------------------------------------------------------------------------------}}} -- mult_add_sub {{{ ce <= '1'; mult_adder: entity mult_add_sub port map ( clk => clk, ce => ce, sub => sub_op, -- level 10. a => unsigned(a), -- level 10. b => unsigned(b), -- level 10. c => unsigned(c), -- level 10. sra_sign => unsigned(sra_sign), -- 10. sra_sign_v => sra_sign_v, -- level 10. res_low_p0 => res_low_p0, -- level 15. sltu_true_p0=> sltu_true, --level 15. res_high => res_high -- level 16. ); -- }}} end Behavioral;

gpl-3.0

cafceba4509dce30b8c9168a89b7189c

joalcava/sparcv8-monocicle

instruction_memory.vhd

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:30:27 10/04/2016 -- Design Name: -- Module Name: instruction_memory - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use std.textio.all; entity instructionMemory is Port ( --clk : in STD_LOGIC; address : in STD_LOGIC_VECTOR (31 downto 0); reset : in STD_LOGIC; outInstruction : out STD_LOGIC_VECTOR (31 downto 0)); end instructionMemory; architecture arqInstructionMemory of instructionMemory is type rom_type is array (0 to 63) of std_logic_vector (31 downto 0); impure function InitRomFromFile (RomFileName : in string) return rom_type is FILE RomFile : text open read_mode is RomFileName; variable RomFileLine : line; variable temp_bv : bit_vector(31 downto 0); variable temp_mem : rom_type; begin for I in rom_type'range loop readline (RomFile, RomFileLine); read(RomFileLine, temp_bv); temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; signal instructions : rom_type := InitRomFromFile("testJMPL.data"); begin --reset,address, instructions) process(reset,address, instructions)--clk) begin --if(rising_edge(clk))then if(reset = '1')then outInstruction <= (others=>'0'); else outInstruction <= instructions(conv_integer(address(5 downto 0))); end if; --end if; end process; end arqInstructionMemory;

gpl-3.0

2554fbd60048744b89ce22c5d2d29671

preusser/q27

src/vhdl/top/xilinx/sdrc4_queens_uart.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; ------------------------------------------------------------------------------- -- This file is part of the Queens@TUD solver suite -- for enumerating and counting the solutions of an N-Queens Puzzle. -- -- Copyright (C) 2008-2016 -- Thomas B. Preusser <thomas.preusser@utexas.edu> ------------------------------------------------------------------------------- -- This design is free software: you can redistribute it and/or modify -- it under the terms of the GNU Affero General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU Affero General Public License for more details. -- -- You should have received a copy of the GNU Affero General Public License -- along with this design. If not, see <http://www.gnu.org/licenses/>. ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity sdrc4_queens_uart is generic ( N : positive := 27; L : positive := 2; SOLVERS : positive := 79; COUNT_CYCLES : boolean := false; CLK_FREQ : positive := 16000000; CLK_MUL : positive := 23; CLK_DIV : positive := 3; BAUDRATE : positive := 115200; SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte ); port ( clkx : in std_logic; rstx : in std_logic; rx : in std_logic; tx : out std_logic; cts : in std_logic; rts : out std_logic ); end sdrc4_queens_uart; library IEEE; use IEEE.numeric_std.all; library UNISIM; use UNISIM.vcomponents.all; architecture rtl of sdrc4_queens_uart is -- Global Control signal clk : std_logic; signal rst : std_logic; begin ----------------------------------------------------------------------------- -- Generate Global Controls blkGlobal: block is signal clk_u : std_logic; -- Unbuffered Synthesized Clock signal rst_s : std_logic_vector(1 downto 0) := (others => '0'); begin DCM0 : DCM_BASE generic map ( CLKIN_PERIOD => 1000000000.0/real(CLK_FREQ), CLKIN_DIVIDE_BY_2 => FALSE, PHASE_SHIFT => 0, CLKFX_MULTIPLY => CLK_MUL, CLKFX_DIVIDE => CLK_DIV, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "NONE", -- only using clkfx DLL_FREQUENCY_MODE => "LOW", DFS_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, STARTUP_WAIT => TRUE, DCM_AUTOCALIBRATION => FALSE ) port map ( CLK0 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLK90 => open, CLKDV => open, CLKFX => clk_u, CLKFX180 => open, LOCKED => open, CLKFB => '0', CLKIN => clkx, RST => '0' ); clk_buf : BUFG port map ( I => clk_u, O => clk ); -- Reset Synchronization process(clk) begin if rising_edge(clk) then rst_s <= (not rstx) & rst_s(rst_s'left downto 1); end if; end process; rst <= rst_s(0); end block blkGlobal; ---------------------------------------------------------------------------- -- Solver Chain chain: entity work.queens_uart generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES, CLK_FREQ => integer((real(CLK_MUL)*real(CLK_FREQ))/real(CLK_DIV)), BAUDRATE => BAUDRATE, SENTINEL => SENTINEL ) port map ( clk => clk, rst => rst, rx => rx, tx => tx, avail => open ); rts <= cts; end rtl;

agpl-3.0

5088d96406700fd6b2018c7fa78fbb6a

wltr/cern-fgclite

critical_fpga/src/rtl/cf/fetch_page.vhd

------------------------------------------------------------------------------- --! @file fetch_page.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-11-19 --! @brief Prepare page for NanoFIP communication. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; --! @brief Entity declaration of fetch_page --! @details --! The paged data of the NanoFIP response needs to be prepared every cycle. entity fetch_page is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Commands --! @{ --! Start flag start_i : in std_ulogic; --! Done flag done_o : out std_ulogic; --! Memory index idx_i : in std_ulogic_vector(14 downto 0); --! Memory index type idx_type_i : in std_ulogic_vector(2 downto 0); --! @} --! @name Memory page interface --! @{ --! Address page_addr_o : out std_ulogic_vector(5 downto 0); --! Write enable page_wr_en_o : out std_ulogic; --! Data output page_data_o : out std_ulogic_vector(7 downto 0); --! Done flag page_done_i : in std_ulogic; --! @} --! @name External SRAM ADC data --! @{ --! Address sram_adc_addr_o : out std_ulogic_vector(4 downto 0); --! Read request sram_adc_rd_en_o : out std_ulogic; --! Data input sram_adc_data_i : in std_ulogic_vector(23 downto 0); --! Data input enable sram_adc_data_en_i : in std_ulogic; --! Done flag sram_adc_done_o : out std_ulogic; --! @} --! @name External SRAM DIM data --! @{ --! Address sram_dim_addr_o : out std_ulogic_vector(4 downto 0); --! Read request sram_dim_rd_en_o : out std_ulogic; --! Data input sram_dim_data_i : in std_ulogic_vector(15 downto 0); --! Data input enable sram_dim_data_en_i : in std_ulogic; --! Done flag sram_dim_done_o : out std_ulogic; --! @} --! @name DIM data --! @{ --! Address dim_addr_o : out std_ulogic_vector(6 downto 0); --! Read enable dim_rd_en_o : out std_ulogic; --! Data input dim_data_i : in std_ulogic_vector(15 downto 0); --! Data input enable dim_data_en_i : in std_ulogic; --! @} --! @name One-wire data --! @{ --! Address ow_addr_o : out std_ulogic_vector(5 downto 0); --! Read enable ow_rd_en_o : out std_ulogic; --! Data input ow_data_i : in std_ulogic_vector(79 downto 0); --! Data input enable ow_data_en_i : in std_ulogic); --! @} end entity fetch_page; --! RTL implementation of fetch_page architecture rtl of fetch_page is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ type source_t is (DIM, ONEWIRE, SRAM_ADC, SRAM_DIM); --! @} --------------------------------------------------------------------------- --! @name Internal Registers --------------------------------------------------------------------------- --! @{ signal source : source_t; signal start_dim : std_ulogic; signal start_ow : std_ulogic; signal start_sram_adc : std_ulogic; signal start_sram_dim : std_ulogic; --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal sram_adc_addr : std_ulogic_vector(5 downto 0); signal sram_adc_wr_en : std_ulogic; signal sram_adc_data : std_ulogic_vector(7 downto 0); signal sram_adc_done : std_ulogic; signal sram_dim_addr : std_ulogic_vector(5 downto 0); signal sram_dim_wr_en : std_ulogic; signal sram_dim_data : std_ulogic_vector(7 downto 0); signal sram_dim_done : std_ulogic; signal dim_addr : std_ulogic_vector(5 downto 0); signal dim_wr_en : std_ulogic; signal dim_data : std_ulogic_vector(7 downto 0); signal dim_done : std_ulogic; signal ow_addr : std_ulogic_vector(5 downto 0); signal ow_wr_en : std_ulogic; signal ow_data : std_ulogic_vector(7 downto 0); signal ow_done : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- with source select page_addr_o <= sram_adc_addr when SRAM_ADC, sram_dim_addr when SRAM_DIM, dim_addr when DIM, ow_addr when ONEWIRE, (others => '0') when others; with source select page_wr_en_o <= sram_adc_wr_en when SRAM_ADC, sram_dim_wr_en when SRAM_DIM, dim_wr_en when DIM, ow_wr_en when ONEWIRE, '0' when others; with source select page_data_o <= sram_adc_data when SRAM_ADC, sram_dim_data when SRAM_DIM, dim_data when DIM, ow_data when ONEWIRE, (others => '0') when others; with source select done_o <= sram_adc_done when SRAM_ADC, sram_dim_done when SRAM_DIM, dim_done when DIM, ow_done when ONEWIRE, '0' when others; sram_adc_done_o <= sram_adc_done; sram_dim_done_o <= sram_dim_done; --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- fetch_dim_inst : entity work.fetch_page_dim port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, start_i => start_dim, done_o => dim_done, idx_i => idx_i, page_addr_o => dim_addr, page_wr_en_o => dim_wr_en, page_data_o => dim_data, page_done_i => page_done_i, dim_addr_o => dim_addr_o, dim_rd_en_o => dim_rd_en_o, dim_data_i => dim_data_i, dim_data_en_i => dim_data_en_i); fetch_ow_inst : entity work.fetch_page_ow port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, start_i => start_ow, done_o => ow_done, idx_i => idx_i, page_addr_o => ow_addr, page_wr_en_o => ow_wr_en, page_data_o => ow_data, page_done_i => page_done_i, ow_addr_o => ow_addr_o, ow_rd_en_o => ow_rd_en_o, ow_data_i => ow_data_i, ow_data_en_i => ow_data_en_i); fetch_sram_adc_inst : entity work.fetch_page_sram_adc port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, start_i => start_sram_adc, done_o => sram_adc_done, page_addr_o => sram_adc_addr, page_wr_en_o => sram_adc_wr_en, page_data_o => sram_adc_data, page_done_i => page_done_i, sram_addr_o => sram_adc_addr_o, sram_rd_en_o => sram_adc_rd_en_o, sram_data_i => sram_adc_data_i, sram_data_en_i => sram_adc_data_en_i); fetch_sram_dim_inst : entity work.fetch_page_sram_dim port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, start_i => start_sram_dim, done_o => sram_dim_done, page_addr_o => sram_dim_addr, page_wr_en_o => sram_dim_wr_en, page_data_o => sram_dim_data, page_done_i => page_done_i, sram_addr_o => sram_dim_addr_o, sram_rd_en_o => sram_dim_rd_en_o, sram_data_i => sram_dim_data_i, sram_data_en_i => sram_dim_data_en_i); --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin source <= DIM; start_dim <= '0'; start_ow <= '0'; start_sram_adc <= '0'; start_sram_dim <= '0'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; else start_dim <= '0'; start_ow <= '0'; start_sram_adc <= '0'; start_sram_dim <= '0'; if start_i = '1' then if idx_type_i = "000" then source <= DIM; start_dim <= '1'; elsif idx_type_i = "001" then source <= ONEWIRE; start_ow <= '1'; elsif idx_type_i = "101" then source <= SRAM_DIM; start_sram_dim <= '1'; else source <= SRAM_ADC; start_sram_adc <= '1'; end if; end if; end if; end if; end process regs; end architecture rtl;

mit

75a238bf3d8c4f62b28748f4c504db2f

jpidancet/mips

tests/cpu_tb.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; entity cpu_tb is generic (FIRMWARE : string); end entity cpu_tb; architecture behav of cpu_tb is component cpu is port (clk : in std_logic; rst : in std_logic; mem_halt : in std_logic; pc : out std_logic_vector(31 downto 0); instr : in std_logic_vector(31 downto 0); data_addr : out std_logic_vector(31 downto 0); data_read : out std_logic; data_in : in std_logic_vector(31 downto 0); data_write : out std_logic; data_out : out std_logic_vector(31 downto 0)); end component cpu; component rom is generic (FILENAME : string; DATA_WIDTH : integer; ADDR_WIDTH : integer); port (addr : in std_logic_vector(ADDR_WIDTH-1 downto 0); data : out std_logic_vector(DATA_WIDTH-1 downto 0)); end component rom; signal clk : std_logic; signal rst : std_logic := '1'; signal mem_halt : std_logic; signal pc : std_logic_vector(31 downto 0); signal instr : std_logic_vector(31 downto 0); signal data_addr : std_logic_vector(31 downto 0); signal data_read : std_logic; signal data_in : std_logic_vector(31 downto 0); signal data_write : std_logic; signal data_out : std_logic_vector(31 downto 0); constant RAM_DEPTH : integer := 1024; type ram_type is array (0 to RAM_DEPTH - 1) of std_logic_vector(31 downto 0); signal ram : ram_type; begin cpu0 : cpu port map (clk => clk, rst => rst, mem_halt => mem_halt, pc => pc, instr => instr, data_addr => data_addr, data_read => data_read, data_in => data_in, data_write => data_write, data_out => data_out); rom0: rom generic map (FILENAME => FIRMWARE, DATA_WIDTH => 32, ADDR_WIDTH => 10) port map (addr => pc(11 downto 2), data => instr); data_in <= ram(to_integer(unsigned(data_addr(11 downto 2)))) when data_read = '1' else (others => '-'); process procedure clock(cycles: in integer) is begin for i in 0 to cycles-1 loop clk <= '0'; wait for 10 ns; clk <= '1'; wait for 10 ns; end loop; end procedure clock; begin -- reset mem_halt <= '0'; rst <= '1'; clk <= '0'; wait for 10 ns; rst <= '0'; clock(1000); wait; end process; process (clk, rst) begin if rst = '1' then ram <= (others => (others => '1')); elsif rising_edge(clk) then if data_write = '1' then ram(to_integer(unsigned(data_addr(11 downto 2)))) <= data_out; end if; end if; end process; end architecture behav;

isc

74e344c3f1e19ce4b02d4f623ecb664a

jpidancet/mips

rtl/cpu.vhd

library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.all; use ieee.numeric_std.ALL; library work; use work.mips_defs.ALL; entity cpu is port (clk : in std_logic; rst : in std_logic; mem_halt : in std_logic; pc : out std_logic_vector(31 downto 0); instr : in std_logic_vector(31 downto 0); data_addr : out std_logic_vector(31 downto 0); data_read : out std_logic; data_in : in std_logic_vector(31 downto 0); data_write : out std_logic; data_out : out std_logic_vector(31 downto 0)); end entity cpu; architecture rtl of cpu is component register_file is port (clk : in std_logic; rst : in std_logic; a1 : in std_logic_vector(4 downto 0); a2 : in std_logic_vector(4 downto 0); a3 : in std_logic_vector(4 downto 0); wd3 : in std_logic_vector(31 downto 0); we3 : in std_logic; rd1 : out std_logic_vector(31 downto 0); rd2 : out std_logic_vector(31 downto 0)); end component register_file; component cpu_fetch is port (pc : in std_logic_vector(31 downto 0); pcbranch : in std_logic_vector(31 downto 0); pcsrc : in std_logic; instr_n : out std_logic_vector(31 downto 0); pcplus4_n : out std_logic_vector(31 downto 0); pc_n : out std_logic_vector(31 downto 0); imem_addr : out std_logic_vector(31 downto 0); imem_data : in std_logic_vector(31 downto 0)); end component cpu_fetch; component cpu_decode is port (instr : in std_logic_vector(31 downto 0); pcplus4 : in std_logic_vector(31 downto 0); rs_n : out std_logic_vector(4 downto 0); rt_n : out std_logic_vector(4 downto 0); rd_n : out std_logic_vector(4 downto 0); shamt_n : out std_logic_vector(4 downto 0); imm_n : out std_logic_vector(31 downto 0); alusrc_n : out std_logic; regdst_n : out std_logic; alucontrol_n : out alucontrol_type; ovf_en_n : out std_logic; regwrite_n : out std_logic; memtoreg_n : out std_logic; memread_n : out std_logic; memwrite_n : out std_logic; rd1_n : out std_logic_vector(31 downto 0); rd2_n : out std_logic_vector(31 downto 0); pcsrc_n : out std_logic; branch_n : out std_logic; pcbranch_n : out std_logic_vector(31 downto 0); -- Forward forward_a : in std_logic; forward_b : in std_logic; aluout_fwd : in std_logic_vector(31 downto 0); -- Register file reg_a1 : out std_logic_vector(4 downto 0); reg_a2 : out std_logic_vector(4 downto 0); reg_rd1 : in std_logic_vector(31 downto 0); reg_rd2 : in std_logic_vector(31 downto 0)); end component cpu_decode; component cpu_execute is port (rt : in std_logic_vector(4 downto 0); rd : in std_logic_vector(4 downto 0); shamt : in std_logic_vector(4 downto 0); imm : in std_logic_vector(31 downto 0); alusrc : in std_logic; regdst : in std_logic; alucontrol : in alucontrol_type; ovf_en : in std_logic; rd1 : in std_logic_vector(31 downto 0); rd2 : in std_logic_vector(31 downto 0); regwrite : in std_logic; memtoreg : in std_logic; memread : in std_logic; memwrite : in std_logic; regwrite_n : out std_logic; memtoreg_n : out std_logic; memread_n : out std_logic; memwrite_n : out std_logic; aluout_n : out std_logic_vector(31 downto 0); writedata_n : out std_logic_vector(31 downto 0); writereg_n : out std_logic_vector(4 downto 0); -- Forward forward_a : in std_logic_vector(1 downto 0); forward_b : in std_logic_vector(1 downto 0); aluout_fwd : in std_logic_vector(31 downto 0); result_fwd : in std_logic_vector(31 downto 0)); end component cpu_execute; component cpu_memory is port (regwrite : in std_logic; memtoreg : in std_logic; memread : in std_logic; memwrite : in std_logic; aluout : in std_logic_vector(31 downto 0); writedata : in std_logic_vector(31 downto 0); writereg : in std_logic_vector(4 downto 0); regwrite_n : out std_logic; memtoreg_n : out std_logic; aluout_n : out std_logic_vector(31 downto 0); readdata_n : out std_logic_vector(31 downto 0); writereg_n : out std_logic_vector(4 downto 0); data_addr : out std_logic_vector(31 downto 0); data_read : out std_logic; data_in : in std_logic_vector(31 downto 0); data_write : out std_logic; data_out : out std_logic_vector(31 downto 0)); end component cpu_memory; component cpu_writeback is port (regwrite : in std_logic; memtoreg : in std_logic; aluout : in std_logic_vector(31 downto 0); readdata : in std_logic_vector(31 downto 0); writereg : in std_logic_vector(4 downto 0); writereg_n : out std_logic_vector(4 downto 0); result_n : out std_logic_vector(31 downto 0); regwrite_n : out std_logic); end component cpu_writeback; component hazard is port (branch_d : in std_logic; rs_d : in std_logic_vector(4 downto 0); rt_d : in std_logic_vector(4 downto 0); rs_e : in std_logic_vector(4 downto 0); rt_e : in std_logic_vector(4 downto 0); writereg_e : in std_logic_vector(4 downto 0); memtoreg_e : in std_logic; regwrite_e : in std_logic; writereg_m : in std_logic_vector(4 downto 0); memtoreg_m : in std_logic; regwrite_m : in std_logic; writereg_w : in std_logic_vector(4 downto 0); regwrite_w : in std_logic; forward_ad : out std_logic; forward_bd : out std_logic; forward_ae : out std_logic_vector(1 downto 0); forward_be : out std_logic_vector(1 downto 0); stall : out std_logic); end component hazard; type fetch_state is record pc : std_logic_vector(31 downto 0); end record; constant fetch_reset : fetch_state := (pc => (others => '0')); signal fetch_reg, fetch_next : fetch_state; type decode_state is record instr : std_logic_vector(31 downto 0); pcplus4 : std_logic_vector(31 downto 0); end record; constant decode_reset : decode_state := (instr => (others => '0'), pcplus4 => (others => '0')); signal decode_reg, decode_next : decode_state; type execute_state is record rs : std_logic_vector(4 downto 0); rt : std_logic_vector(4 downto 0); rd : std_logic_vector(4 downto 0); shamt : std_logic_vector(4 downto 0); imm : std_logic_vector(31 downto 0); alusrc : std_logic; regdst : std_logic; alucontrol : alucontrol_type; ovf_en : std_logic; regwrite : std_logic; memtoreg : std_logic; memread : std_logic; memwrite : std_logic; rd1 : std_logic_vector(31 downto 0); rd2 : std_logic_vector(31 downto 0); end record; constant execute_reset : execute_state := (rs => "00000", rt => "00000", rd => "00000", shamt => "00000", imm => (others => '0'), alusrc => '0', regdst => '0', alucontrol => ALU_SLL, ovf_en => '0', regwrite => '0', memtoreg => '0', memread => '0', memwrite => '0', rd1 => (others => '0'), rd2 => (others => '0')); signal execute_reg, execute_next : execute_state; type memory_state is record regwrite : std_logic; memtoreg : std_logic; memread : std_logic; memwrite : std_logic; aluout : std_logic_vector(31 downto 0); writedata : std_logic_vector(31 downto 0); writereg : std_logic_vector(4 downto 0); end record; constant memory_reset : memory_state := (regwrite => '0', memtoreg => '0', memread => '0', memwrite => '0', aluout => (others => '0'), writedata => (others => '0'), writereg => "00000"); signal memory_reg, memory_next : memory_state; type writeback_state is record regwrite : std_logic; memtoreg : std_logic; aluout : std_logic_vector(31 downto 0); readdata : std_logic_vector(31 downto 0); writereg : std_logic_vector(4 downto 0); end record; constant writeback_reset : writeback_state := (regwrite => '0', memtoreg => '0', aluout => (others => '0'), readdata => (others => '0'), writereg => "00000"); signal writeback_reg, writeback_next : writeback_state; signal halt : std_logic; -- register file signal rs : std_logic_vector(4 downto 0); signal rt : std_logic_vector(4 downto 0); signal writereg : std_logic_vector(4 downto 0); signal result : std_logic_vector(31 downto 0); signal regwrite : std_logic; signal reg_rd1 : std_logic_vector(31 downto 0); signal reg_rd2 : std_logic_vector(31 downto 0); -- Jump / Branch signal pcbranch : std_logic_vector(31 downto 0); signal pcsrc : std_logic; signal branch : std_logic; -- Bypass / Forward signal decode_forward_a, decode_forward_b : std_logic; signal execute_forward_a, execute_forward_b : std_logic_vector(1 downto 0); -- Pipeline stall signal stall : std_logic; begin halt <= mem_halt; reg_file0: register_file port map (clk => clk, rst => rst, a1 => rs, a2 => rt, a3 => writereg, wd3 => result, we3 => regwrite, rd1 => reg_rd1, rd2 => reg_rd2); fetch0: cpu_fetch port map (pc => fetch_reg.pc, pcbranch => pcbranch, pcsrc => pcsrc, instr_n => decode_next.instr, pcplus4_n => decode_next.pcplus4, pc_n => fetch_next.pc, imem_addr => pc, imem_data => instr); decode0: cpu_decode port map (instr => decode_reg.instr, pcplus4 => decode_reg.pcplus4, rs_n => execute_next.rs, rt_n => execute_next.rt, rd_n => execute_next.rd, shamt_n => execute_next.shamt, imm_n => execute_next.imm, alusrc_n => execute_next.alusrc, regdst_n => execute_next.regdst, alucontrol_n => execute_next.alucontrol, ovf_en_n => execute_next.ovf_en, regwrite_n => execute_next.regwrite, memtoreg_n => execute_next.memtoreg, memread_n => execute_next.memread, memwrite_n => execute_next.memwrite, rd1_n => execute_next.rd1, rd2_n => execute_next.rd2, pcsrc_n => pcsrc, branch_n => branch, pcbranch_n => pcbranch, forward_a => decode_forward_a, forward_b => decode_forward_b, aluout_fwd => memory_reg.aluout, reg_a1 => rs, reg_a2 => rt, reg_rd1 => reg_rd1, reg_rd2 => reg_rd2); execute0: cpu_execute port map (rt => execute_reg.rt, rd => execute_reg.rd, shamt => execute_reg.shamt, imm => execute_reg.imm, alusrc => execute_reg.alusrc, regdst => execute_reg.regdst, alucontrol => execute_reg.alucontrol, ovf_en => execute_reg.ovf_en, rd1 => execute_reg.rd1, rd2 => execute_reg.rd2, regwrite => execute_reg.regwrite, memtoreg => execute_reg.memtoreg, memread => execute_reg.memread, memwrite => execute_reg.memwrite, regwrite_n => memory_next.regwrite, memtoreg_n => memory_next.memtoreg, memread_n => memory_next.memread, memwrite_n => memory_next.memwrite, aluout_n => memory_next.aluout, writedata_n => memory_next.writedata, writereg_n => memory_next.writereg, forward_a => execute_forward_a, forward_b => execute_forward_b, aluout_fwd => memory_reg.aluout, result_fwd => result); memory0 : cpu_memory port map (regwrite => memory_reg.regwrite, memtoreg => memory_reg.memtoreg, memread => memory_reg.memread, memwrite => memory_reg.memwrite, aluout => memory_reg.aluout, writedata => memory_reg.writedata, writereg => memory_reg.writereg, regwrite_n => writeback_next.regwrite, memtoreg_n => writeback_next.memtoreg, aluout_n => writeback_next.aluout, readdata_n => writeback_next.readdata, writereg_n => writeback_next.writereg, data_addr => data_addr, data_read => data_read, data_in => data_in, data_write => data_write, data_out => data_out); writeback0 : cpu_writeback port map (regwrite => writeback_reg.regwrite, memtoreg => writeback_reg.memtoreg, aluout => writeback_reg.aluout, readdata => writeback_reg.readdata, writereg => writeback_reg.writereg, writereg_n => writereg, result_n => result, regwrite_n => regwrite); hazard0 : hazard port map (branch_d => branch, rs_d => rs, rt_d => rt, rs_e => execute_reg.rs, rt_e => execute_reg.rt, writereg_e => memory_next.writereg, memtoreg_e => execute_reg.memtoreg, regwrite_e => execute_reg.regwrite, writereg_m => memory_reg.writereg, memtoreg_m => memory_reg.memtoreg, regwrite_m => memory_reg.regwrite, writereg_w => writeback_reg.writereg, regwrite_w => writeback_reg.regwrite, forward_ad => decode_forward_a, forward_bd => decode_forward_b, forward_ae => execute_forward_a, forward_be => execute_forward_b, stall => stall); process (clk, rst) begin if rst = '1' then fetch_reg <= fetch_reset; decode_reg <= decode_reset; execute_reg <= execute_reset; memory_reg <= memory_reset; writeback_reg <= writeback_reset; elsif rising_edge(clk) then if halt = '0' then if stall = '1' then execute_reg <= execute_reset; memory_reg <= memory_next; writeback_reg <= writeback_next; else fetch_reg <= fetch_next; decode_reg <= decode_next; execute_reg <= execute_next; memory_reg <= memory_next; writeback_reg <= writeback_next; end if; end if; end if; end process; end architecture rtl;

isc

72cfe58195f85b23e292810aa2785fba

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_defaults.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block BnoEZWf3Djhp2kZ+ui0lnt8ZGCB0m1vPR85wcqBP931/lwXgvso6fnCv9t77HyrKLLn8e5n4K0TS A2lRp5w9Gw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cqthFw02Z8ZEk8DO9DPlInm4qsd4caiEYcCP2lpyYIISJ7lJ/XceD7yqlya3Mdb72elz3nfy9DRa MvnCXHOfxryetPd7v1A2adnInxF37H8saWhXEsqp/3nrUA4Mhd0HvwgRD+dX02BYi8dAb3fEqs5E n+lRmv2eUlscCQ4ewPY= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block pZUswxIbm3SfIvRrN2oogmHMAMyx/J8+dCmSDCHeiBrFzfaegx8QPXUFxg1KIWn2gXtO1kC9nGKJ ZFBIbMCe8IIm6W6AQUsVTyf+BKN36OmHJXkDTs/ViWtTePxR6o2U1jf6bPEOyx9jcHDD0JqT5Jfs Onl4beRcfFT4MghhTOMbXwq/WxIq5OCIsxnFqawpwKKE6ItGfqpQDwJA/SLlvaXGtLJVJLoUlJSa Mc/2bLNjx2U0Z43uaDiCz2IAKGluntp8SddzhDHwSlVePK+8duiZAMakRfltuAQnXoSJZWon1GFa 6TfpxpKZl/XGtaDqxEenkalDKVS/skLo7w7U9Q== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block QPZffcEZwoAiXQcy0wFCB53tQ7nt12BRC6yR2zPpeg8PHRQMkuUByeQtYG7bc0R8ffF/gW2INnrS riB4EOXcLLjA20F73mzfJdDQIxG3EYWePVPf3fc2wIYdCSLSEaqTorOKoeFfpqbtxBYVff86X8uj Rr8Z3b1ZentWDkVZbyY= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block IdZfPVhK2lV9MG6SD3SToeIFyCMTxz8FrWx/ThycJwu1+dn/eFlxivHrQR1PfEucEWTPzl8cTzL6 J1BMCbsBAUeckSib0iUae+OcDPbk4LRNNnnZeFNN+wxRAvTGb5VAHXN+nHaZnXt0GZpmACdcb9VL xjxlPBBzP+IcVWIHuXc92kT284WEHP2I56Z5JtFDq6kJAflLS17+svHFVLDBY719WTxvFfJ+VwQs qtoVu4ZyOThIt97UmyN89lYvRSN+liC9y2D+csCwRbu+w0/COt4ZwSLcW4kA+TC928s/v9uSOMtn LxiYtcgRuOkeS9RPPmwDyZO9rffasXF+aPEWQA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22384) `protect data_block j5R+rB4nd05+bqLgaddzJl4uaeVXyrxUK98JH2hotzhrRYzmoK1jCdEdQkAhhkr1Izzd0H3em1cy b9X+rGJx6LOxlUsi3+9D+ULtZInv4l1mqpVVKUTR074ZRmiTRRIbSxQRTdcW+16VkMMMFiNQAD9O t+lEIxGxCasysbrQJQHHHTPGBAUbzBoWmcc4oHkJhxv1Qu2979fwjjI10P3ZopdXP0aK8vXoGQ5Z ifQ93RCOkRVolUMNC1K9O6c3++P9cqMf0hJH9Rnge+WpGb5uVVTTTFhmFU7jN2z5WMENqE68O3R+ 4ICC0FLFFJgA5EV6VuPdRvzbzmS9prTcDZ9TGSWFq0aJQIeq/T7/9jXuPCHpVIIeZpHhxxK5IhcV JdYqk8jL2fzXqtM51yE8DcQljS0VGT1sF3JJUeYMjILqhmNo0mm2YS9HcydbrCtl1LFNJfc56a+Y F69K1+m8TMX78ng9JDQCSZ4NYQXxhnFxFBj7X/Si3vRJxjmMoat+d6V9g4SUEDbjQoeIbGQC2t71 yRdR+ZJXyu/P1849OpSCo3obd+xj/ygST1YW6Ba3A47G//Cptl6sgzXPrqoozQ68IdlYIjttQLDx h9b8S2Bt/DPNIgepD6qOryGIvNYhnotKMVeSuVDrXN2z9gZ+lmlPQNPHjEJewUgjfbSB/FQOELiE +8e3HmHbwBPScG4ISeOGoWjx8+R7uDD8KnorfVW08byyPwu87XK4BMCO4dTa58OqClYW2Pbjb1gQ Prsidi3VvN2QlnDVUjiLBqqCUsajlXjQjj3PVf+g1AMOgGa34b2p+PKIgm4miUgn9OSIMZEZ6a1p HwMop+bT6sxAYlebrIzbR5LzZi6iN0TJuw9gkElwNoBqj8D1PV5dekYLDYpBvy2YkYVHKdzrxV8N 6la77IEcjHabatMcm9wZssMW0iRLCVJdeW51CcQocBWkTMEPu0rZ6F+DnUTrHj2AKBflrR3iEZxr Feq0/KbEbai9eE/uphNt64D1AZox89+qAQdfq0baCynTtNvHgLHNyXWU+fTTuT+op8XXiHkdvDLJ 6X+kM1f+JKVLQFYzOkDL30zLRpHlmOyOvpdRfOwEvJX8GrAAG6IxnFy703YHZD+DZWAdnbMxSH0t 6MCR0Y5oUWi7ymUVv0JqL7ndRBdxxJsg2mLm45ZmHqPWeKDjGqVhQx9O1IqDDrv37lEI3SIhJjm4 43vf+1Jhu9Bxzt60mjGXSV2rAy0H/0AFPU5DOFGyzVHegW4JV/8ZhKJPdm+Iave4+0vsVOdaseXw EegNjr1Rcl66schcwZwICpIN1K1sSJZo2o2E93ctiFe9QJRbsOERgVHgICr546OLqnm5uurgDoXd BJgdeClhvTdE/2xCAaqMx6vworpQbqlZZEEAuQh09oUwtYswQ2ol57kf0kdK3PAioEvBX7f4u/xB YPbITdtjC1US/czUEEiZGwg1ujbXCC2WOOUwoo30qF5xCJCVoKjd7Gj7OW5wcXOVaFU8gRVU7omq F7djJQ5U2+PT7W9i0WOTRpOlTCW80MShjBFXUhoM12Keen1yuVmz6SNFaHwTULEIXyBBVMdlC7Pw 6atx2ouzaDWDvt2ZoNRq2PZ2bfmIX/9PjWnddOELGv9L40Ch34oVofUcyEG7SX+a4//3+F1VM2Sl LRyZvPV8WFbXwOVslkQdfAlpAzv8O+k9LfF+5hz8A4DUHFMcJd5hn+CAmotbPHp/qz3hghRK5Upn cyWAPUZ9qLlOtnM2xK9rI7v8SHdMP5I4Fr7Hagygnj+2zjtGSF3oiiGYNvUsV/69ck/QK2bZDXLP qK61qxZbWJhaIfPS1MAjTcPfwFKPKzdD7pUzeRgpVgEcOjl4iLve9lhkq/BHQ5f6NtdtBdqkj0Z8 i1+IE55YsKuyZDP0z5pmk9+tkAbYIj3Rd8SaQ8MVFo56DNphojaC6Rw3+9JPnCZdY+jQrSysyWhK distNOawVDW7ro0xLc3WsVvN8Fn2B642ArToz1FZKGSqitqGvno6xCRraEsVSLE1jDd5SRJfbjvX M2/IJqeKwN2oax5yGycF0fxk4ztF5LDRirYZXinKSRMGQCBk5Wdvnv1wL3Uf+GihuTDA26TXDNNa 98cG0fIuik+Jweu679TCO5WR8vr4UTfzrYT29pQq/tyCIt/YRU4qhO6XpzLpe3J9TzZaAKCPaxTJ TgUup5fmQruKT11SzrHyFemY6Io+wfcDOyOW+yp6DH2TKiHr+9Qo0NwqmCbPjDL66vjWE00/Ffvt 35vYuNT9koeoEXOi0y1LEAqOuQLVeMKpsr4cEwzy5485FDWA0QBw+BNgpdf1fQOAK+8zJAtQyXqJ JhUnyufDOWfLCoNJYUhtQ+Y1pCEvS0F+6kf41Q67Tex3syVP4oXZlYjtSLYFBWk1fR0FNRGPyj2j I8EsyK7LEjPL4yQhTdLx8tM69uqlvgHiZWT+1nKE4mWk165wUWV3b5G8oIjC1dGUIBFKcU39oX0d rp4dkpfKZY1n6WkXxRgnfUVmbE6+wWctwKX3KpvHnWgz7lhoimTJmb6Fof6P161cMUWOsxNmLKw1 OAipsu9eCRN7mNA7IlbmYaPME6hg5LbxqGnQLwIzvf6rPpstIXBGq33i6EIjYqaLyhMs5q5PBfrl A5C+3Vbf1hOgvvz6HazGtgdkXJDol9tlwLI/GzmIBl8AsMMUdn0sRFc/YO5xYPjSniGBoIBXr/b+ DAQyYFPpP8ST3j7JEdPzG4aHxZ7DorvhmY1k8f+aOex9eOACJQIVmj1Q0oKL3CHT7B/9jxaWPOKB ruvCfeS3vjmBT7y+bsoPAsfh+JoXG6Zzrqmf4OgdDuG41DDOFjy/BXKUFz8BrpbuEifN4uSoVT7A h9F68lE7RDIC2ATY2OvpN7ifAwcHlL/ysB7uHZuRk7BZgOHiU/Q5hwcYuBW9D2eHT/Ef5+aUV9GY k8ELfVcdtgfKHQoQpnklYNqNkHPZjkgGH8rDDzJe6kPXmySLu9xHEHIJRh0UE1hHA4QbXeiCdH2A 57ZOdKdhS+iV99EuF50nswFg1sFwf1QisxesyPObk+DlfjVMgZe5JK7R3pwKuo02cBdvQEl8xOvs ezsm+BNerLf8BmXVJCn6zbNbnGGv+Fdx5ih/5xtnBcQDQqcjFayw1eAFB0ZwWCqZI2NuI8dQzo9j w1btQw9t+HrQXFkE57VyCjJtUb1EV9aU4QhBHRCr5tJzd/u4uSCN2VpyQWP0FBBBqHxm5a4vd/OS mjTb3WeWuABsGH7oWjsNoefthLxIiIqjeK+eUupP5OMWKbuSRR07Dj7AVcHLkIr8Z2Ds6YyPEzTF vj8sOPQHyx5RuIytKzEY447j7CfFqfM96nZh2PgdV5KK8Gdh+kCUjRpmN8pVVZYr4SYaeH1EoR0W 3YxqpgtvaYQ10eWqrUIA5+kbS21PU8KTXppYwCTCIwJfS/eX/8T6SWsogPLf7bJET9yTz+QK7xCL VZxF4L7mz2klYscGD83DF9E8d0v1ioRrXD3sq5V2u3XgcJaUhSrv5Ud9k8nUIw3mjyjORXCcH0p8 TQOUNx93daBn8trfnajUiVP8QOGrQ3lJ3RS2lWwsg24+OBnJJl1DWmGgq6BVleO+eZVkUY7z+SZ9 iwSQ1VPEqXbL4YP/y/guX2x07dcRPx26wJ9IoqqxhoaqoOIrjm4DhuHrHUVcvWZOiS3kG9/C7ODb UObltIncao2qBtoLD7zQHOvI0fYqJRKibywMKAyPpTVs2BeRJKiSI//KWQitc2bddAGrUWxU1KMb oFn1Y21MPUrZ0XFjB1EKqHRYMircn65KvnVQiaUn4ucXNVljzkw81Swa5eQK35nhD0x0H1VbdLH1 9EZU3IK+tmlw/2znWX9IjuVCrvSIu3PUJ3ejOM9WL/lUdg/Ruzay8NSR8CCegqeW0E2Fupon/Yuv 8AYiKR6FLBjLEYHmWtXuanQhlmOGt7tuIlNysFVl04NS4tghYi142lgxGwExk8VJe394q8tO8hEN ND6OOr0iYZvVHWPgPCQJLPeconCQOxROsA7pBcBy+ikFpo90PlIYOYdcNoEu20OJQq1XihArXnWJ FbK3Nj5P9PiWovQb2GnAqSmPps8FhpR1mtucgbAY0+sxVDKBS1/loAFMgS8D5m+KKurJzNHXlx42 fqKhd/Ya/BNVqNYZyObH7gCuUWnPvDn73NSolTf1lNJlwPrP/59P/bmgoQF868bPwvkLs5ygmiXN egpZaGw2NAaO/GSHX1UTYB4zj1O2YBDi/TUd/QkMT29Pao3E1tCfLt/8H/dA85LhaIOZEosDb9/A ZcjrIU2gb+SDVT8no/KaJsX/5ByZAZt6W91ebndV1mD0xccyjnsx6Qt+RWRfPCjOMnQvAktt7Nhp qziziX9p+L4U3LFOjV2wrmn3xnRX3F5txFOZ3hT/+wKb7aij6SYDn55zL2gFEB0Xv1FmVeNjGQ7/ B8DGM7lLlrc/Hw8V65gXq0jITrs6QKadz39eOmKMB+N0yuGD1xHNQOWCz8k5zqIeEh79M4uZEBqj CoCbMhjzlUItFbwZ/ZpSWnB4YglJVXbIOQqigClEEnJE1rQ8RH3mygHNt+NRfF1eR7LVJV890obX G9S8+qqHCa2dcuBTnENQOH0lYXx6u+cu/qeN4F7P+Y9RJuIEDyC/lvKvLV447oUqHbSFMTwQDZp1 gIEGQ6v0E2foT8zig9bmTny0hr2ToezY2/vu4lZXN7WGFGFKGeEBNWrtip1wSvJqflm471dPUdt8 SojUaBG9dXabPPOoYd6CmHLeSwm5bycPme0tmuR6WBuCMWOzTWV7afGw7E5EYqD09McsJcf1dA3+ TnPyNiaRdrXaK6QbVNABcXjBBJeFpJEWpFlnKN7kk/oO3B0CZKhpYGf6+bDMH/CrpFq2szvFsSBk Ke8cAgqoVOidUQRSEQ7FyXd72B90+zhgLN+HpmUPlvhxZN1ZB93DXd40gVhwePKjtFOBu41h7Tef XiFOPb8jX9VWAQTmTRGeARcTnCREI86/xbJtfb79MrqmHLBidDMBomC2pEP/EZdJp7Go1172a6Nj I62BDncbWzsTA8pv9E5hzZcBlPRN9KOyfzvBrvr9wrNU6gwAao8i5k9QhxTiU29zEZmxLhX0ObrS z3kycKiVoRTkKkb6l4iJdDGcjPChScZxwRn2trIFSVh62gZ3ZaK0MpLz2Duo+Xj+W0q4ORAjIKhV cB77j0XacvnaP0vQTF6aLrmpSwao3YN3UVc5SwvWIBe5xYk31ufRtj+nE2iOPmQxvkhOaAUMyIt0 3i5PXrdU9amt6mw5SX9jnPjn2B82w2DMBWGaT39x75Eiua9DBoIW9lnLRvFbztBsRKyJ2cSZXnsA TlmpEqf6FAtn/JmBDzQ9S5tQzJ5e+6FmWnUv2/EeoOBbnBb5n9kGAN1DorFaEBc3sE96sQsayk3d V9z/LRCV8fcZej36+do2H2jJSDu2oNFONcpS7lV9nl5qjVdzY7wLlj0ec3ozwVoZkYM9tk4pT/ar biSBC8SqAH4rTUeNeGM1RiEBVUKq6BrYIoB/u+0c+29ya2UkKQSCBrp/gKgML6Zn4PmIA2vBWwDn XBuJSL+kK4j9gWWlR7R8jRCT1oKQHYs5vu3QzjNQEMyFnfbSUuu/k60Pa3f/YNdXGJ1ekzUAMo8I NgjzTy0hpzg+nPTVedC4T6lZ37HwDuBgShYyYaX9g9VZgCSLQS/gbbOe5L6JcEMdx1ZXhTK02dYT 4+FN8i/saCwD7J1zd9PSbijw36oWdjO3i7907+1Cq63B6Em1hjIabXlQ39mujTQ09buWC0r6jPtQ hpK1paUkA1P6B/d3uhN/9LJNVbQRfZ3W88HLzrkPEAWiugvij0bhus6XwQP2vR8PWl7Y0ib9AUUO IpcIcPZH+tWyvoRc7JA2s4JKfk55hxMEfcEtEuckA61gEr3nYVuDSg/uujddUXE1jvVoSSuIa+tr XPxXo6f4MLxCNVIPBf5QWi0FbM5NMdCo74T4AjzEFa21a+831Rpi/dlgdRxLMBSIt13EJemUP3xX QpJ60bEisAx8ARr41x1koVLSci1jMLUIB8onDYskbxjViHVnW3OyG+KZ3tziKDnxNc53HtC4iun7 8jo0h+3gSIagz4J8YBH43WUbysBXphAaZTeYNNyDq/sYHullD+loQLiKGd7lxMeWs/EuPItedGEN kmrCbLLuib1hgFdV41fWfq1dy9qgp5nlSNoWpjuUzLMnU7nxawuuTXGgt7E4/zsnU3A/oFSYAP/o lXnbPg2eVrqzcWXKoIIlTaBuQx2xiYbAeXNG/5g8repLHdZD7SYTjnVVX7CBafGCqAVhxxZKeDsJ h2Mrq4AOmuM6Rk2ox44c76ulE+o37HT4q92MJMB0981HS7vw9cttR+uoEUC3KqW9a9T31iscwWw3 mxFrku8fSsLbwMbcy/yw+OIh75OFz4yx1L6BmHkm9i2fSyf4DTiFaUWfpSHo/qA4cjKGnnEojc39 QisPrxI5l69w0kMi8rGAudyHV3CTYYh9BdjeBcfUTllYZ0+8yIyG5n3e9EDUbRMV2CI0eBE+0hKk vPXWisIz1lNZcbHQkGahE+/k6UPhY7peWglJFj0p696qHHTNlJzSNmh0NYhNO/UEPQbMOJv7ug6q ufk8Er7Mn9l4U+j6PbSSu4ES5v9S0vwemAyy0W6GaMf10w2UFIkQ8DwJwWf+UWEh4xiUd0SrqjWe MWo1Iebs+fLvXJBpioUjwbo87dTzUSYuVGMSWgarMaJAO1Kgyk/0A5D0Z5pr1Hlu5EXMaEL0zToY rS0rXJLBVJMzA4ce5aDzIxJu63Z99jZCVF8DLN1CnamS8+ocgJ0WgxcJAJL2wr7YnrTi5U3Mv1Ay UP9U39y4PdFiOH+O2UKJ2PBUEvUAffb5TLZIVTJsm024KSfghrx8We1rZc7oCIccwSWG7Hl12JxB oRijyTVpsGV7qj6A7CMAY6KWrqz5wUioDfKu8lnxWw+C4GR3Xo0g+MzAGD3PCmIyEy/r76D1oMK6 ZQkxIWX3Aottjg3FmOkPK9kpdp2Yar+RtjY0KptrKR9v0QCkXfFfre2ToIdhnqwTSN8kP7QPWCk/ 5uDPl0Ut6afSeNYjexQqGmc3k2OwGOE6XpRmL9OjKIT4FmKTy/44ffIzRAFLUYUKbc9nnsT/b4sk LFXkcpOvpm1D4+I41Qwd1LYIJ5HeYpvAX5BZY9HeUbLGTDRxR9OuOhm+nLo2JdDmGhtQIQywZ6dC Nm6EOVLCRXghG9rcPrB5VAS7d17qUeiLqV4W0NkNUpNxIWpm9ZUe7I8LkwZSrdKKS0NISO5MbbsW jfcR47Lqs9Tnmw0WyfWSEy8+Kwmw0Z3iGrxvxfTCXayKnjl9PJZTLQtlg8UaWEu9nZVazXNleL1f kjPMw4Y3mqlcLe2MAmOQb3iZK5eYYTR7vD8ll6sRQe+X+t6GJfmPoPrIKewTmWKHrNzZCswU+2/b GTVlXMVi1QBjFEfTvmPFBBKvhX55wmyBB0gbXBh63n95D8dOpFY5TTC+vwkxmiyKdofNrEAZ0r07 zd4sf/4quA2PPE0ESeIUDvtudyC4sOz8nkzlET8Zt+yoS2N44f+g6J1XDwPzqd0nkWolUx3pYxC4 hZVWsQopnaMngI+Qvpl9wvpPbZxlttOhgHkUIona0bHTQl1e77q/x057N28lLRmgRczijREZ0aXH +lmcQBrEF89s1His0nyC7HlHWEnxB4pW+dtHMaCkCO/l5/3ZvmukWfWRuHJVRLopiQ40q4Si23GJ DQP557Rjipq8vLQUKA9AAb7AUWGzu1EW9oZiYQOEXQ0oJc7XAvHDwHlnUB5OB9NjNt6L05bta4wi fXSmvbH0WrGtEldnRPxtyeatdxhV9QX+qy4wYi81U3C872zCf02PFy4hcO5oqoZRDsiZMTA+ppf+ vZLjmk/62y5mn+IOA4yuv20+MlRUut6F57jmBwheuVIgYUZaiCeOLGC+9vKHdr97FDIbZ14ejN4N k6nhbmRbZ1Our/IV4dZuvHm52dFC5DD2Zoz4HXLq9m26BYV03LjUb7gjBenf8EGUUrHV3BNfYaxj 5p2uuqRg8nPwTaB1+SW2ib9pCFBkAr5Q8huuyAkihxWnsohA2J3TsjyUoayP7cGSLRh9r+ZsqyrT Xe0mnNG8jyuiZ57UBFXsrwSqNlDyO5OvgxXA7tzb7hhbLK/gq0hjPKwyMZUrvHAbOpAH5JfSdqG9 4rMXMHRkZ728cC0RmDuCp1lFCqlaKGBPe/4T/JgEL1PeVgTw57E16aVAsMIiBvRFGefeqdyGd7Uw 8Oltr5seLlGdzWWVCGdu+li+2ZNNlzWKU5KuTzWmTZ8mHsktw70jlCxqvpcc0rFzcrnoP+5JdVYw KP01VxVSm65zKsVoPtIQsFd4kOjn0Dx6CMEVhDtOUB/7ZN78P8UdJcDH2/8it1YTTPqX5b6KeJ52 S+52cY3d4nJZko3mWeZwG4Nrhf02RKecqTs2uOcZAId0qT8A/t11QvttPbTP3WAN8UiRuuNt19vq vm//rqtiencC/JvlQuUrzznvooPDULBADu0CcEGCtbpwuDbgVaK4Mc9ffAoA30NKhadXBziAgQOL 6lNPiU8hRFfmtxgl+cbM35qLhABZr3DcCoHaPy9HHNgBbIxPLSTKWfTc8PwN5BPZ27X2UUs4SAvr k8ROvKR5ydKjUeR9CFBJrFY9bnWhag2H+/8JnSKo79wPdXyAXfgzNEDbmGx8NcLvSrB+396E32df Rb+nd5EuoLYxZC1stPmmIdLOZb+Tf3FqpdfWnU+qyllOvZoBhQu7qcrzAZ+nRLn0/GoMbbPoqktm n0zTCgKkr7UcnijXUHfHLYzhmwtqMsI+Vw4ZLQhG24YbYeDB5BNHrGSU5IIV5MuLvR7Zc37xspDn /sxxw2bEf4d3b1/+sz2B2CIVziP2gdKIoSei7LTzCjl+tJC4iZicpITiNLNAS/fYchUjuRemR/6r P3dXb2KvGS/P0/3X7+8u2U2tKoW5ZIWUbk5eroTaGplngxqeoWB/zbEI2UY3ABcfaGL9jT1X7RFL nPMVv9xKXeDC+YLiebr7FmQ0lwDsyCrWXdWqK3V3kk7DEVMW9AsEOALXlOWgTD4OGQVmLbAMl14P /0rgp5grdXH3UrfYARYrHPLR1uHoEqbvQZt9/9zdCS2G59Im28QQNETHzwRA6jjLNO7MUs7UzYi+ WgDXNFE/QZ0aa/5S0jtHzO2irTtcmIolCIoL2K/+4QZAeaqwamuaDqUyx6fI6KXBrxG0esiejMyK Q0IyQB1E7eNXzX50yGNeJWUhG8w9hqTAlIoEhSnOGus3y/EHp+4ZMrdrcYR/8kZhCxcNYo9XYW9Z W3N0SJXh9qvmN0cTJGev0gL5n65s6dnZejzhiqii4ZC4PnXd//WzPe1MvawBiAV95qC/aUhYSMBb T3m476FnaPy1nYv/PtGm+b++/CmW+O/mfQouvens4G/1kuV/Qw/CF/5XgCc0MNMWSkPN8rcRZ0Jf vFjd3uVB6VB6/A6r2OLRmq4/1zS8jDTJxZC5xliNWhzE7TYgBnsFb+A+XK5Z8FvjRj8cDbxcxhB5 pqvAhOcMWwt2G6na4i+z+NJPam9eyj68k2BwPuKOzC25RFGLiHskJ2CQ9WAOdg/u3HjIHtzVuovt OotdAtGezcve/mpuA9/s9t5THLTv6VRUirWy6DWYWePTk9drG/2FcmoYBGzgegNb4GjuK6Wc54gD ai6ifbs7OhFIZcUf2mVoFSNLQdG6TQE8wzlbdi+wjRHd1mhzQ/KvoaKe59IkIHUIYlSXowJlxuVX 0Kwl4o0Ei6IjqaQI5wn04zZBKA5aahmfx4fqK5Lb3iCNtg0PDW1upfn9hZYbsFBnPb4ryC15JYKe YAeQRuj9VdSMnbaPtWR+w65eLAY7dYyHLEBMmq+oRHvtr3thY94nqr4qRZS09vkvtW7/82VpCkKY 3r3kuAvqaxLsGX+ay/LTEwK2HnqSQelK1nDpYsetq6qPchzL8ZtLMvigEDxnhwBvTgVqBWToPu54 QlYpYq0tnvD5CEpWK0DDE3w5XOEp56Y1QOgBc9v7w3p/ywd4k6j3ToeS3viT+uIAZonw1vw+BGJR A2W4d4X2GWtL9tWnlj6+gOK6LHWfHd3uw3Oj+3j7t7CBBHOlarpXLBWzI5isjmOr69lkBN6Aaclu UE71GCDPvx03ql4BHj95AXsDdTF7tgfWap2O6ZLjXcNpEM0RuO/o0iItPhM/KjSUiqyR16pikzXH 2oZ+A7silIIP9+R91lKP5/6DsI3lrdLFjiFlugvvPiNuGOS+e5q5EZ6bVn2ytG9rPkugeO0U69/R O63s9Z+jjMSDdWQuAv6He5XDt1g+NSNFMf9VLrhuD4dRVCTXyDs5fX9pbC22fyfO1x5qIGrscsrA 7mhiK5SUbx4Jb1U464GX9iJaaa56CSSsaMBc2Qd22pFPlBvhmlJIfvM0qpPLKap5qFHfJtGBYB7r 6WF9rQ/6BnQG7zsPald+DrXeZfiksOSFcJD+Sq+6Csvt/N5WxSlE8GEBR5pJOkP5BglVVkJ1pcYg hTyvtCf6v3U51nIh9C1bUKW5ou931I4cSwkO+ab1zV4HhYr1d1mmDOIpUC2KvzQ69qlfQC0WE0n8 Ua10AaLjcqkV/SDvszWi+WlzKvTNz8hiuh65Q98YCGC55melxiXighcPAhv3nX+rQDhAfhaMX7CL DZWvjz0+5MlFnaT0xrRh5OT+3Bgyje8ITTROC1tH8eI5Qc8o86wq+X9578TImL2FW5ma8H66EzPS NvteSgjGm/kgfIJA09AInKIqB7fH920bJ6ketuq/O6jxzDj998xjazvBPb/beYwfklIKZWy5KaSm 7ycnXSZCHPPz00URHPbI+lBv7+zAvKeoxWYsmnToQdl+r+hnD1IStb07dsSNhukjdtW/VC5yjrFT N7aoYt3+aZVFM8P5oC6l1488ZM6RWNDAwpJN6JTwc63YNDrUN9rlalifjOsJgj2L1pR+XuTxyE5n VvTUpSzel7WU9+OhaL1nWGivgT2Obd85nipVbBomwUEKJeIqm+6gFwlFNwKQIpVdnRG3a5Z3pCYU dVeeGLe3SZnxOeX3Pv3BaGOmBA3j3gVWSDaP9lW/DYXq2uBpdjT4hvTj7Pnnuf4Ea/YLHwVXLnjM i0JbiTJgPHZs5xamEZoSQ2kLSIhM+3UdYItTPC1hMa7GiG9RJffTMHzFp9YES46hDSX0HDajvM/r euXBq7lLQ/VkqC6Bp2SAWlahRTEPO7ws/b3I4rr+YcMOuYhv6miBzhhZ0Hkk4aNYa6H7mL+1JOSr QGvc7N89YEGIlBfqLnuFGYifRMI9nKjQaa6WfN9ZZtkeBMI6cYjyrM2QR6YUr7UnxoHpDlN0N8Ff vwQlOmwIK38d/D1x5mewUt3FoZwQw6NYJQRGOdHt4WugysMQ+SsT92jsAUqW6EEJj7lBnC/z+ZNk legE8cVQce1FzNMniMF8TUBoqwmOlYP0obGfO/SzFFDSCJ/AePScMnTmzrNdkz8O9LyN6tFX1x+W BHUCrCkzmrO2JX7reB8VWlM+88lVUcxOUM1b0ByZFAlB9VjPYCb33Rzr5cQqQ+71FQeiVYcDCbUZ txkgMRTG2SY2nRx6OjLOfJl6I6psnBw29c7LLHq3WYCyN+3rn79F9CN0cEVjoCVwzYt85XkgMBMf 7qand3O5KMp2abDIcFZibw43TUIV37ls5T2t7QY0HjGRI24kou9FkorM8TsOzW2ssb/umqPQZqD6 lXNiUQnWwYClmZN/in+wdlmOClzW9lHflMK4IIqBLggsx1BQTzmeteLBj1ldW2kKgw3ZKPhcgX3u 1YZYrLAgx1Hjmk4PARZs3zu6V+vqpELZgCng4U2AO9nZ8hn8rKNdSWMS3HY8/hx7FshtOfCs/TJf axtDE6g3O9IKMoKQ8yWhLxbTDtMHALOL3af5VU/wFYTeGIAZ7RdjlsfzlUbQvHVwHu0so4ZfWRi8 3d5IewCAxorw5Af4dw2yx4P0GFLB+B7xzYL4kjAOdlOlzzMk8p+0l7zipwK/jwzEzvPlN8JWMSKY 2EcAuTh2LGGNlRrwxZcLt0u3KWxJRSWR/zZdDvLHdwC2LyGt3pJzXUva4RvrVILFarUuL1k02m14 aFbye1J+igBLJUURbTtLdqM+IN8j+IvWeuqwdgOt06pTHJmcCKAjYtpOulcyHNtytvkxk+UHtBcA MhuJVIrklgVydH0uNX9lh6TKiuYyovAaNDIytmMZ+zHyHEYPfIm6aHV+mb2nFbCGr1aq+HGqA/12 DxOJQslv0YRpu4+vf/a+d+UF+eE6zreN1AvrPL97OWQLxWztZRliHyN5WNUJd1Bld0pVyfYmnAmq AgCpFNxUWm17DFRkEOjJjLGJHbJ+ohiXyIi6WJNJ62uJueur6l8aSETaWBAr+66a6SOJuHYB9b9o b/l6loR3+OgyNH+rHto8Xo8Z+8sfyB27th58ItIUXILQbRoUg2KFkDHPS6T1dtpTrHMdk5pOmvG+ /TnVmUI7MYpaIDhpsBdnEOeWQRB7sAnY/eckfXpO+F2TqMlv8W50RNCzWcOviBkz3jexbC6IhX/k jvnuWlzwejhe9REtkP0kjQedECvkQNfOeXUmu9fy4su32a1ub7SIb58CgXcLK6D6Qgcp77tTETiC Unap32740Vd30WwVYkiBt/WsqFfFCzeO4tnJIgfPoUCD83gJYYKexo55tNzpZxzOol2pxzJ+h/Qe YyE7c8w6PkKwJIx764k7m4iRfBi7OV/SWVW9tsYH9/Lf7aQvaTLkIsuJZLkjBPVSPawtRP8sXR/c OWZ09K8HGAG1hZY7fATEEaDR902ZZBtbIS32NSGhA8NqSEJ9QoC9665RSm36p8SEkc3zC9/LWE24 83x6iPiyYzVQNAkUqcya0Y60Gs6ryVTSihrmCDbTw6B1Pz5F9/3h+VW6KbdFNiv3QwJ67YtctHA4 0KqVIrtz5TjHX4LEDSlfuVO6u8gEB4/vOSnEuMnRU9oQ6WRTh8o4W2nnsPps2EOTIu5gwmD07q0f 4SGXceJIyJe/yCAp/PUmPPSbr/u03zHLNJ0ntmP0n5Woq9kypYiUa9ntGCRRmIZC0wJomgGId8c+ EYouT5Pa2IBYaTB8KePSmu4+ZNx12RoSyCSSpu6Og3jL9mOt1F/CncbMrSyw0FnDv4BDcWJMx0Pb F8vEo8uf+o6KUwXt/ozbkq5oehyWTH6pIb3uLew3hzTW4Bz4J4JWtH01Mc7rSa5Ja7yAmPJH0yZa h5XFUYpr5RhLIGmhtSuLsmVcHaFg3Xbf7N5PhI27F4J+HiwglhtocrTIBAvkbZZ+iM7LwtOsLF/F U6htBvFYyJf35vqa2eLVlD8k5ValeCgVtHfBrkSiMijIkzfYIgkZDFnn979t/WeArwRq6i9WPKlH iNBfMYaFru0uqqE6CgTn/XiaqwllUDbjR5WSj/l8mk8dZGC3RamhJJhkgBtADyzsx6pmZyMUsbLs T2tgyB5w7S4geTgxb64n9imUjlOa0McNrD04+1Iw983Ed2BlE9NaNwqL86WXuHzAj10n0VlzzMVw 49PPAo0ttAtH0a0u3l0oDVvGJj2e5kx1r+fD4s74CcbPH4KbuIN3YiAPE0ishIU+jlO6DLcCcRjL OYMPZJYFfdRNftfeD/3S4qyPZcdlaFexG9g4AQw5e5vMFxr7zgTeu7ODTs0/WU/nyxUlvz4uDpPw Q/F8av3FScoBgkRn0GYeWnryCOEG2/cgiO2cjsFWM2tfYIZsCpqsU075Wk99z8RUo03O27gdjeKX NWBbgu7lfPURTCRLLDE5JqntuZfafKhzAj7xhKE4j9dzJgXAi4QTT6FfUZEVPFe2xXuCOqSYq3E7 F7GianIVJgGPYBSJre+cfGS6EGTDqaicghFQOt5JoAs4/3h55V0S3zEIPLbvG2htnhpS2I6c3xLO FXX0qk0dggrfYNPhFo+RDTfPTrW9lkzdEMxKscSWKdbhr0Lrgll9+4iCa7EM54MxlM8x/Twb/ryo xvniiCWZpvN17o3RSKiGqg5QXyBorZASMADhpRKIT0IrbMt0RNf8IVQ1Wanw7oy7hJCuDenOA8Fn MXe0TYssPtc7GJ9aoSxYNE2rnEtaYGQl5rFvVK8ANItrUU38WghBs0haRNd9NuUnOm/0WAdYoriT Fo4LwaY/SWToxVKhN6Nfijb+pJ4qoEaus12vmE7ehEwPmKArOjgPE5J6p+LqtNT9xZipebU4CG7u b2AEZxu3m00afDKl+IIydMfSd0J1uKSXTSZ9mdRTMI7xYntDUm5R2ZFs5kjLKo0W4vqSRTAMr8rg FIkHbUOuOlxmsARgEw1ljpEU6m5U3EcVaImle7bY1DH8wAUtBvLpEwRUQ6zfXLmCHCXyJa/XFxx1 N3l9zXUSZ7TK9cJrTc7QvKgfURnZHS3f7iChkE7Ger6i3WVugnIVyQhqF2nYor0wAshzfcM2qUf4 94jiQmG28nV+AyfYY3M44Z9YD9Xc5pIZvDYuTkl4zT+5JJV/ZiLQwu80U2i+Dp+8KaSC5FQ3rJQw TqzwE49rNHgWYqR9ZiVSRL/F+sndXrOds9dfvOAlXDOmsZFaC47gASQft48cnLW163YHQnLuJgAF tDGYl2OUDAjsg/QQT+jDeGrCcLK9dhEleghB+wnpCF5b8AwZVmK4jT5QZrbCejDpKLFLIHOiDjWm Si8js394Lp6HuFxVqiMJ61LUWM/TdCNRAFnNzl3bb4kxR8fxB5evTIfBD72rvu/GOqpIf8WE3F3G 5kCfOLeABERqJnBbE/ofEi513fgSgCuzm+gSFrUNIzk/WW12vRFsVqJ3xeGQ+dNoBWFvwJ/cFzP4 pwLaHiiceAVh1W+o5nMCLcEMYZLHsNVkSZgDqpMLNg3o7lsuXCOTBQ5Yr7IquKPzUw3yPitHZ4cd aQvKjwtSGOSOsQ8zl4vSCpYavzP9IgwnGj3m9PATsG/3yw0jIVFKkInNF9SrlC3f2MLyh86UQ66I hs1aMKb6P6SI+mbvx9I4InjhkRoFiFkcUbtdIWD/IW08hgnhYzU4lHdwsakjBuzH2rDQWIeusFWU kuu0x5l342hiLbj9L9f7/9cJCfVXssFDoZZN4b4T8lEHGpgiL2A1RnwxDyFJ2MH84dgPaz+1w7bj ZEQfeRAQA0xPjRq6ojupHYd5H6jBcCSEJGARH8HDDMBbhmbyo6B/k/BkQqM2O7w+KxWxn0nJ8qPM O0LymCPjxza7XaZnzoGUcKEe/DM/ulUGA/ctsDmowDbQEeYgOOR3OSFPksbyefKywADgGJgMQtxP ld1jn02BOTg5/Prkwpb8jNElujTO0MJBl1ntKJsvq4lIMv109z34PnZRUBxhVPFZZ8ScJrGy4LvF yZ8Hh7svlmllvNv06mKV8CDTJM4nU0devQcJhNEdPgA6HYzOQgpGI3hDoc+uwlyRMsEFfo0HSNrL yQ1GM8E4dzQzpszD63oderKb2qyRaruqhlW3E25BoGQ1oZjcfhYjDH8ZhiFAwoXZDkIs4zFThtm+ TiLtkB6a1gQE1q4lTUQQMbLaH0XTiB1WtAp45snj4gZLjJrpLPry9RDOcMiNOAsyifmvX1MhRrrh QwLkUWvwz+edoXs6Coyt3Nqw3knpzkYKmWMnLxd2iall4vzzv6ZWt4TN/i9gyQjHvF1C5OECtrlV CG0nFZKEiyuwxf0YNmUEMufq8sn6IYJTIOTj3tuUzgvuvfl6z+xZ+Ki/RXn0yU7dCtE/pBoSTMvl 4SM+m8fyU33uft7y3OwIlOxJ/y2AwXL7dUWJ8Yy6gdh06hBpiKZvOz1K00xUrviwRva3/TDjFr3m fe5dcPJzWXukfBOctPbjId3NY3HscquXFNf8cfdobgqRdy6pgeE/qs8l3dMLq4Drbp1HxptAa8HC oXo/CxSbya72Uwhy21sK5L+IA2KR1GO+mMH1m7N4c23lpXZaAgYLrh7PR0D3Q99g/aBIanIokQb4 kcAssS7SEaMXJczaO+LYz6cQ2wn0U1nR/P0rO0JHe6s3xJn5cLogJd+K1jARQZpheTRmuJrJTPFW iL9CdKB34VFE3Js1zn6bKTVJcSnYVqz9sdUdAOMn07T3wYbCeJY/zOgv6RWR/3Oz++qlWa00I+XA Gbj+H5XutLPYiJWATN5NVZmWXSNeysj3/oaZ7gZbO/ub8uAqUQSmbKjD/KnqYkqvjzE235j3kHU3 HC1/7xytJU/N4/EnYJQc40ifXG7YtpnS2lWWOBWMjvf3RUFxV5MsZas4bm0O85mibor9Ovgh0hWa YZl8OBdeq7opFtsW+tZnlCqqGPt/hSqFgIXMBNEsH3G0Ss3pppS9iYhDRGv2TB1wJGkEuZzEgNS6 ejRK4/2TztGqW48K0uNtrLE12AlR72xkXP9TUMbLwAjayDSkzqajuotsfn8nLlZa0yZrF4zZ55PJ Qe4uw/8KcSX46/0kfXpJZGVrybOeSaw3nomUO1OvaQ8lOjA4+k8AJ6R/zbJTpiTf66mArjqNkyR0 Cgy8wMJQctatVftt8pTslCfi5fPzRA1RoquOiKKsThwZj2eaQnykaZnBrrj39g9FdkFEXRezh7UU Ox4zeQ7De/BZqXwxhJ6CRQbM85DSMVopWvYMPzUYXxUNI7yiKGMEgVsqZ3Ho2iMFDFtSeVgq47sh FhTye2aIRShGn9AsO9p87fHdd91Ls/GPKWh54KSVD6sXKXtyODjBVsEyzaHgDBFoa7Ez5wJ1FrOc L/OMhwtPUcF+qJBmCPSnD94Gzp0d1LG2IDDdQNGQrG/jgP3+ZPqLiyZwW2LQ/ozME+vDECFnCtZs 24Ufl4W6dy4PZL0x0omumW4wtG6Dw250rxjjPkCm6k1WoNWqobO31tmU5c309ShPK9az3D+9BzsC pEdHlchdRGwDp3/TJsGt+moH5BOBm8LQ4jj8htClmJDFZOx0qwugQRoA4MKSuEcUj6EB2kFugbyw y6auLEFUqFiQRup9RK62t7uIFxllb/CtfRE8nKR2qha7SqMHsoe4YEMo4jWQvgO9MfZUTn50Bqph mplELqTCbTVRobRvMRxFYwzsvrwQtkOtMxgbyEr8HmZqT+zFPb7ZlC9KsImBp0IQhChcb317AMgw qbgzZslM9/NcXwrRmFyn/K3EdXRtW0dIO2IRv1NvDLn5PbbY52oEpNP/nGdDpe2Er0E+X/hVTb4s ymRa2h39UfA3dHUZDwJ/nokR/JkFexat7LIIwboSj5ZelqdPXI2IqlvQ+7iZpaHPOYFPKK+iPV69 I98ACCcqces5ZxqM9sc3YfHrWjPFYItZyhqoLHprdlptVOdGS7MSsXDCjr4uaautlPXF7ybbhNRm iw+5+UunTWtq9J/Rs4eK4o1azunLhrF0Bcx5LOtdfIVXz44gs7QVkreL61kOwLh7eaVVIOGUMuMV sVkUOkJv6ybTmRfa3hw9I52aedS2S14wfM6iy4lRFynoMCv7LBWpWUo1KCnsCrqgvua1Ac3GC+Fm tyW29bJjRIqVmpej4ZFfZpKgUu4YYtzPEpiGhKIHoYje8C0gQqYYorLQFf3O5OuOXWLjMoWIITRW RJYVS41VtpuVCJYtDJXDYox09j4mGI4h+ptvmbHfrpp7vLfniDu3E+KddGTmvfAbBNNeuSsFZPxQ BZkkuLbHaGNS99mWYtsIBvVCbQWjWTd1sqD3cfmS795cbVeKZouf7Js5IhyxjqUO/TaLyqo1LOfg SeJQdKdoyKvogwqIJ/AkLIjEulwnMm/oLkHV+VRLYLhTPphc5Oky5En2R0clJiFCBLBbIEIYDNuI 2xbE11qZIP8FVsd+okpokaUR/xMiEoq0iS8vaMtpPc0XbdbFED3loww1w/L6PVq3rORdf/o3jIgq 1VDtKfX+TR2/bTU20YPQdG3fYbwT1Z1aTYt0iXPM1RuKcUUZDPY5x2EClAgZ8S7AG2+bXEa2Hg7L T+QydA3+9HgKe9hxecBUeieNq4fBMeyBD0pRn7kiZO7+RdkeMDhcu6r2ZhzwCtGuZ18KIqd7c9/P tzwribqRc5LuRbB0JxePPBEwQNyUIstqTHpkfAlwroHLvfk7JBF8NgzC48/qmqHxL8jX8ftwPN0s 7WqL8klbroIXyHdhq/Ks8y9N2bTPw9fHqfPEbSomsiyyPw7kaq4KaXyGe6wW7yrwf3Bu9WPaMK+4 cXU9YWjhcrh05DeZqRDZ0OQ+6BAt4nFPuJUUKnf4/lIBB18IkUwG/FjGc5NHD2mKneSKyIA5xV2l 9sowX2JYPmVu9J1dsIKEfAdgcQ0zCC3mlKwP/ypcSmg3x+7HY+n9GI/TqGci7nck1dd4ggkv8/xZ TUOPa4Th8TOHrnQGemFLwlW3G8BPLC7emdJBj9qbAsttwASJ0Rs8dMPlE21cMxNcMl6UWkU9XTci eKanTC09fWxLhzpHdiQxGS/GUUokGUtY0sMrwxYnRUR5dx7+9VSpQA9ByQqOfh4mg9up4KYsp/gQ UFmZcrVA+tuyYzgUa8cW5N1adth1APEjXnZ+TNde3T3jL0ZHirHxH8a7uwT1iEQasDr050HaTtOu 6nKY1sS5LmeSOQRlhKcwnDvSP3MMAMvh4a7KKxQP/3eNE9Bl10bevOb82eTEY2PdaDC5UHRJobsr 8nC6e7flgFrLHVX24S4VdIXeQgKvJwFQNqcRZIZl88wHKzJTRkj6P8tFp6A7yZnUkQilB1GfoiOG SO34WXtD7lIylAycXodKILZoiQdTMvGziQ8cGiOQF+VCtY0erarUhU2pafUsNrCreD9muYayvMzw hXCE2lDpFlgJFZvUVRE6O1ddUAbwHdCdjZ2jkQjCoCYP3eBTCLd0kyrMy2qKiG+HU6pOTPB7/jt4 lLbmvinRJeMXiWRPllEshX+O6UJ4gzoS8N0kBFEDdKx8qdAk0doLRelYcmvdt0mZqIGx4dMWrz+6 wU4hhnxyihTFULuaH7A0jtVqe5f/xEytXOJ35z+5Tk3YhhnF3Z3s2gGB8mzl3lEMpTTjxgUMNacT jEZfTLL85owRSuD/NEs8+G7Cp0VrhgyRPpEN/tqn8PiVznstFtPRLuIoLFbzZMXfV8oTxz52xaQg ifpYF6o7WBv7HceTGLxG85X2PPgSYJPI9vgsRiM7lcSxURrNv4TJnp86CVPwvQVAPt5GqgyLpdu1 49g7zb75wjNv+G3FGMzQ8h0d8fePRQI7kT3IOXCK+HfPPSzpMoZpAoZRXPW1w8hwWpzGNOTZQ3PF 9qiW9D76XadwUxC4IyW9D3dQaTfjgQGZMyjS/S7GXXe3M63REZmk19xasABn2OCfH3i2vmZ1Ok/D wP1vffO3BT2ei8C+ohJeAxYu1cZYZaUrjWQqOLMLeg5KDSLyztYRrPwSMFsjpM0ftIgutuntR50G ZTAvoSqTwrv9+EKXutZyv6cZWIwgK+0eXvkVAlDJX7NqEMk89I6/CEtMuIm9YC5TYCPWMY5QnU1K uPJ522nqWa+Ut+gCzPL1uvgiOn2aES2CgT2I7IbwKh4kQ9ajYapfGqpkW0+c46IzC03j+2b9JuPU XaFU/odlpIKigJ2bnGd6GbVCK815L6f8LrnSUtgXbCFHpFT+KfxnCg6m69DKwhJf5WliXaNmGFMK vXVKSJffA/Ny2w6oTXQ3ZNmW8DjpMpW6PdrsjB95HjmjuSREMsfqjshaCuoHxDicheCPkLiN8Cnn bl92gr0QAOV0ZiWemuS+BuHTadINs85TVaIiYWNCMewrY3sgOnhmlvO/RCjaPB5DBB7OQVa8ZR/S cyd8S7RaOiMBbZwyynmuLFIrA9YYZe+w4pHFtkPqXkHsRBzWP0kxDxPdY4b3OC+Crpf+xXCjvdH1 2mjFLHFtZH7bQmfZ3jvGexWhqQza1weVl/ovgoAHn5yd/aL9JP92vv7dWaL4BEgaXhb+eIcNg+Zu s7aZbCLFsOwoIu1OrExasvrH4fpd+WYqiJtKAWGpIR+uWnAgzhpYW7FAiL8tnNR6UFyCSX8pCue1 /4D0ai1Gzw+YRYZWgxOmOn0P28+aLf+dnt5y3DDT7HDtHo4kqCeL8LlBxoAe6wjb9/Wg/ZZvevYJ g4XRZhQLQChsAOWWVoDJwCWfgWUbPjZSvcUlrpzbz9uN86vEimMeBljTTdFjeQfCfNQcz/sgRk+C /ZIow7ol7d6p7rXAL6MvRRVkMlNMzNu/89FOnZJD+qPNU8I82k4wE13I13gxi614xFPH35uz9YeV 40B6YFX24diWfe+f1cs1h8sS7shk+D+qngg2O123FnLVQo4Bi1EdMeAcBnWUt6VRNfxf8W6m3Fmn 4rpm+wVQO16b/qkheY7NErPDYRMJKhfrjnJu/HDLWd+YWixcIl+WDJk6JA07pvXrk7GSH/coxR20 NkCsuF6hC32QdjwzgsNINosUCMazIjC4Fu4bm4WrF/VjVjm2nGC/DV3MPtM1UMxW7SlhbaXp8/Tn naTJihUyumv+SNlaV40WvmErlt7RIeX+hV9+xQg1EZRlU3vCz5WanFxJG8nl7bz0q+ugz5pm0jpQ pYv3en+4GX1kaahdTq0gX8NwHhlHvkOcQJ4USHYkCut5cOdH12Le3nD3VAVa093EJEeC1JLxadYG 87URkyYu6cesjgAPR9d9IQCExfsX5AtmW3dpR4h/ewijb3GPWVbnoH0OGpulIUSR1cFY5Nw0yD6s IoPuGNGTUokWuNPyR+JYG6lKu1hiLJYcFfSGfLdWXXyI5fNy9q5MEDyB2vMXRkoriQeJKjLqSIG3 ouvYNY2z/dyQEa7hjTGKvsvgK0FCWa7+Y148Ikzhy4e5PSmcv43jOhH6C41/FO3oKPYtFdDIHZZY LbBT96uuFumqWKib09u28vgd62jv0vWrJ26UjQXWAy6S4vJXQf9b7x7wYpWpKT8w3aSieclKwWzd rDLu+N1r/fYykyuHh1ejUYYjfpyHHfD0bq0dAHSY7wS2GlECsGoWMGQe6yf1rdIUYjMIkAqV2Nxh eQmwqk9kG4f4Sx7Tw2YM59VKWCVV94ZM9qCEON43uPUU0bO7fUELWcfYShghYWZFDaETXGhv4jZE SshmIXb3ijNshqFBiMG9OmYTzaaqcOiH4q4IZGOIen1O8/oAmoTx6uXP8O2EGpUKycl1PzLzEtiS MPAu5u65IPMwuKeG6Trv3lzuL36sPqn9rvrja5327ub7n1gF+W2wKnj/h9JfOhlNyLrNgjwnUAkv tg/LMOGUl7lO9YF1LKn64lEiPbxVXFsKFmQDlJU2FolYzttG9gb+hYnrCbD2L0FOfktOUrLZk3U9 LjKPrF0RBNdBNgMxUCn2+Usr/PDqb7rz9PUs7VQ7oKtkRlIpFc64srJAAeRG5DV5abquOAuJhZ6J 4mfSfaKwwqz0eaJlc/gUfdZryrIgjd944AN0juonwCFKNUikMf6XwsUohTCPFiOy2yME/9g2vBNO 1Qm5Q041Yaelp8oxbpCup1USBB8lLV7x8dd2cWwVnrYgzJ8KmetigoEVrRD4EDzEJwbgmh4SNryV iDY5rF90mDNijVgmdeitI3rdbRmSVE4wKcaxevo3BvUuwtskgXJD8JVifcWASDfwqPeJtL27diUf Gs7iCq0VGEODNZKWC4cyt4BjBW1QZRfP7zteRprlVVnhqvDgKrvzAj3syLjl+QJw8abCB2zBp4QG /k8ky9zVb7/9Wn6KugI8op9ZJjdkw9Aj9wNmCMK8duPUz52gj3DpLioy2UrtZzCcYi0pILxnJlOM p+kUlcMgX8x11GIegONMJjR/rFmfq8yRfu5BSfanlylw1ugV1Hjc7ZuLGKKdarqi1+CcgRmORvTx Kj+PRtygmfMvqhqqhlD26p5aGU0o2+Pg7D/lH+Dw6CO0im2J0DCWHCQxZZF17bDr3EgOcueZkXYg 2zCnFmvjWYAKNXANgHetnMtUrS2JD/EpxTVhY9AWegsc1m03FECgdfhTywSy8wqaHerhIEQKoyLX W9F0XkB9QWck/a79R6AnOKRAdBcDTzDac0n9Cn7pe8jv3cdKyRKr9l3ICO5HP6dgcIJ9ehheMzfJ 4TSpmHI6j/7JJbt21eWWSApQk7mjxnA5svvSHDjM31Jmg4Em6PSF1i6s+iCuVEkta6ZZ6z/kQYzo +gVHLuo8O2ZhbDRkgaLuOJtMpHT1JeKbBYr2ZsIOfxh4kNn3Fv+zCXEuurMnjQrtuJh7euNmvTDl iUYojT8mUStAzcWkJlsjJTinA60Hpr96AG0hIejmGOv5S3PLivdHMjCE8c6STfMWzghmYA6aAKmU uWXQNUxA/Gr4vlUrbFTksPf+OkS23vEJlOKTmBF1M/pc0OGiKPX2LPHQkyai4qogJ/712uHzw6zU PYWf+g+PX3qw+I4LAR2snP3vQvu89P9Q2kf24AYHbbwFPFEBYRNealmKUVMVkgJw2FbS1vQNuwiM zbyhneRTl+wOYXai61e2G+bY32uBoTqSNBvSy4Pv6mskwRvOeMljJN4yCY9eo7MNl8ubgWY2bQmc o09vi8M3EBjMmNoaX+4fXRa5f9nec4UJEIzzyKYMKf5s58MqSTq9qYWCoR3wYHnAPL+cMs9ylwzh V6WqX1e1NMeSzti+DmTCuxLKf9IqV3/+uertM4yTW+z2so9fuOutmkwMmKn5rYLIzjoIEkA27ksi ukuD/+VeTfJeXxvaOO2Otcu/H532dRAaqAYhxZMzUGSCAG31y0SK+NQuWcQR5GB6SiWsImmhKdtX XfWcrIEXvgWkAStNcjg8xfL6n8QBghp8s7HDneUMCa5/fPC021VA5fLOG8UAt9Fjz0Glx8WkbOta oQKs6Xrkqy8hKgTpHpoJz+bUKa3idJAGdH8a9MutrMzk1Yyc1q88Ds9VIxBHeoEnausxlqbMHSMy Im2pZLBWFty1EzDfgMGid2LB22rm87VALYNYO79tvkhbCl0jrMMpkBg2aYiApAPSOfFr1QdcTg2z aQAT08yc22sBa2XP6btz0XzhndPhSOP/sOM280is3pIm7t6liHpRZ6eF8n0JYZSVyOq/yrPTDHkA dw82aKN7xOlu+Xkg6xfyNmcqlCF4FR40FxWzQ98GvOS9xNyntOuWUOrQ7WN8WoAGtSVutRaJnVfT TwaeKEIG+FwmMST92DmDjSy8zNShNY2SKB2TSR8jopb0R6g1sjxqIv9rMPuzIZlp3WA0QZjzCNsu AmbUnwRd2fN5bEpv+5vyVde+G+3xD1jpdf14QPSy7Gtf1ujuiORFImmhaEXK2K9sHu4dX21eQgh2 5boSxhAHb4pUJmSlU+19xUDjJJU4LBQn1QcuqcVr8Ci/2VowhanCFcxjn0V2MqIBWTkWkiRcczeL DWTOBHAl5D6vV5hNbhUKFxWRZJcwNOUaBV+x6g7Pina7uQS5CCROq6lcSo96K5WV/r6OuoQ9Wqvv KTmhx5p5ew0hkDR1kHmMd5M1jZeF2s8kP1hnuEswOvSKlotdlaF7e//B5ckrn5aA1gCi/l8NPJMA Zt77yBlmZvH/c514howPVW5kzf6+X8OQs3tGHCQYiHCqy6HztCsIs0zeJclcRQcND2kuMJXHNY/E v8zx4acEDZUUg3kTKF1bxYXq/GzKX33mG0WC/Y9/JBERjqnGP7WBU3WA9DOSAgPmm0MP/j6o7DXe mtt/uzv2MsbrupOk9hp2ZuFyXnOLur+L3gHG2jlnFWMWQfIcYhBznqnzcwIneR9LJ4Y7iZ+blDh2 TFipM3wbdyDasLDyIMtwoYZBBHv6urPNgqgxU1eQ+PQM+V8JQ/tiR4A+Dkcbqg13r1loXSBJXsW+ k7bdThDTpczoTNzEAvlGXuYFiyY06Az6do8Z1vLT6lr0Ib5cacOctQFmKrywlOb7ZU4yrYNQ87y+ PjTTXCWRJee7gfo2WDP9jBeOpieCxChsY/UISQugjKLuHcPtsrN1pMQW1PdmehrDYrzWICzIr/Eh g1z9lQq6nYezibYbJ6reW0X+P9S/JaN4iQvgzUr2Jjb3rbXK7tNCfuIa2qLbH4NVtwKYqgkc2VcS vjKLlV0cNPFizgMitjVF9Xpl0ABFh9QimuwvYJoqrvGFOteyuaKn5JT/Puvnj8GOyCeN/zVZr1qi HNjdS3esYPpzUaEyEF+rVRQ4AabFyRccrNZUn8meWDM1OZIghII6MY2eiySWmRu32zETCNcYAcJf O6KP5Yb0oBERzoikramBsDBkiDJmJU5xiejFZqyl4HkJXf2s7p9KusP2/rmYq17wCHfNt6FGdQMr jCRGtq1wQh0C0XuRutST1iN1BFfdXTX8+0PtHqwFnVwDHuO3RFTMnves4U2UBG4O4RH/EUImFWmp ttNrsB9gJxzWYQyRcVkiRDPJ4ri1vDK580ZretTkmSkUd164PACh/WBEeHNDgtOGmHng4J6vJ3jy 4jeTBjmaWjF1VICkL8KGU0AhM1vRhqHTnNOfRa6Oxw8KAPprIpBEgQyoeSGdlyqBzsAQR0QQxXFK sxwqeuH87VqS+N84ySpc+MbIX/JN0CZXnZZ3aQVehK0WwRvFNN1YNsfFU6v07EEGctyHo0uha2A+ FUaV6cY6++Tv965yuIlYeiFWZcQUQZKkmCUScTGujVKSHPxt/JIWUIgnam1l0bI28OoJlFW9d8Kq M/xgT+UECPQrH72vMOedy8y26ZbdIi5C77rIRmKL1qyW9UGiqGRg9fVPe0FZB9O5CexW31os7iRJ aHJHeXwRPVcA2rEooReY4HqRz69YAJ5C1RLKKhsOny0OPY3GrwX/cdqP+MwPtPLnL78+EywUstVt oqnyCxHImVsSxmKBMl/99ZYTFa8THdEkrp7KzPsFbXvPzyyohH7omQakA1o1f4EQ97ZCgjDXIWtk z1Pf7J5OPhDF+7zNH8UTTQcTiJZTBqBSYtCTdfTrufsY4IeIrGEoqS0qU20NWa002x2jHcls908d 9mYN4aSfJZk4FuQKIIJlba7g1Ce309YgfhUsBsQq8lnnjaKqYcGdS6qt19X12la9BbNwjR8zmO7O tHwHJykbbw3qwZrU9LW+zZCP2/xPVvwMDlViObYgi/u1oJ3A58JgGO1x+BRRudiQlwa1ZXNpZzIp m6KwA1NqDQluk3FSjtLSWBfWvF/VOKjOlutjOqO0rgpw47ckyJYQ2qPS1oWGs7jioQubHHTsRzKj nRnL76lMvJxfGILp256Rr7UIh0E99BoHeIzVZi0nGbkHw/525TQexeukyuqnnMjxlV4mlSOS/pVf vztFfkOF2mLLGNul6KNIjONppwZDlankNlg39/pHLy/5CmtdJlN9YXenKzGVK7rICkdjYaScHZHM 3e9LKFztzUof7HbvN9rmMIYlyqWyFLm+0rOKQGK6BADMlCiA8jGxnpzA6wIyy0J+/7G/lWnnrCOz O14hzZUrYoFlrjZeOOreIK59hoAKmDHVs6Pma0MFtaKz6rmuITtOeClvMdVUA2FpOiMnecpPytok w7P9fFoRg4UEuZpblflfpC1Cq2lUVhS4fY2Wji3slUmdwV5VuTIclQ2zUl2jscz9+eIZCeKs5EKr 5fhhhi4bxSkfZK4G3qO+EIQ/FGte23T/jZKr3746gCmzVSbTUkz9Vzp5qyKUoqM9zTrKG8VUQgiD Nz32YGN9sdTZTFbk4DkGes+VCMH1vBI1AsjZooOAhKvf7b56k4+vk6fn0c2JjlmUVCfliis0hrpk Jq5EHtbqvlk/6cIdt0Wg9Lnig1+ESe4uAj5aXtPtSuReGe0kkBQsv3CXqij/scYzRrV12UPSeEAL vHR6xeJK3zFQcbm26GaUVljcyzc/FESEDw1y3+Eb6wabSFNbXzpDkhUTojyhFfZub2NB+kKsdQJC iS9TeDQ0VS8r02t2d59aUGDOwobcOwl5YypQjPYYO1fCGsn5LuD+0Bi3yfkHLRie14xvl5gasNAL 0KKkzuQHmv7Q/7Jj4xirLE2gz/dqn4uErH4uVxzAd1P0sAP3IdY2+zYlX20aoT83nh8ZM7nMnWh4 kwhQOciDbXcZ9O5OdjYrOE3nhXMaAohVtgQ/L1sQip3MstY6TVFeufhfvTCXjyW7GmblxjB+kchn kTnqHZpo5k1Gv4N8QS9I+cjYp4xccUmFMTh3TZ3Vu71PGl4qG4WNK75MjtYDMxbeESbUOff7eycJ KaUrWAYXr3/SXmWXZOal1Azk3+NCEMtL37f8uCBlUFt3vTBhTWqvYsclSk9q5m913bAuplcsdY8U AMMLdlkQYdKT/rHM+UyFIaOTsnlUuFWjxKnLSxLqcWk5hSe38daxgkbSkYO+N40Lxy1yV0fTuBzZ w0PVe2tilB4UlA7NA9sp1eElmSm/gMkTf5Q22HBZ5JYDQQjFmUCytm3PJqFQClAXq6KJ+dg7CkUj 4pu7lotE0bLNBsmUShRo3Gyyj3y3KdDe6hgiIUhpIuwd5J+0qDo/3huN4tNPpgkReMGhjdDC339Q 6zGnk2xiAxqgXox2XOmfcpO3qgLDGuh+Nkm2i3opCHWABp5cDxQ+6h/ELuoTAdGNnkgLwW686C+j pMN0hKJK+QTnT6seLF9BGtmdaaQR+mVjbcw/HndPSMtL0CXJRnJg8ubJKwj7K+Uyn5xEDB8ui8/4 hQay3eG1JAuUnCJyE1oSOQqHQA6r/5WjyMzXqcNY1L+OHAfTdC3Ve7qu1gJEk4f58ZDS2ysOPQZl J3AQaxMjPC9J1/HYuaKTCPDM+K+JiQB6ada7nDAgZ/QqYHfxojQBO3M1xwsef9IfXUp5Qx9ziatx euuGtTppHKTbGgkXRANorSpK6JXFcWube4fTjTAQNANT0OIoojshRpTUZKTxMXTNaSoS/ISk4QBu V5w4r94bfdU7zpRAA0cO4pgjo/sC4D3xFiHRtxD4uhQN3Yn1CvjP7qrt4yGAplXjpF/CfFVkqdWG o/GbqhxP+oWij7P1tj33vsSDB2pXs06PU+su8KCV3l0z/Dvcqpvntc/3pRgvZmDMCwgfSqK4tmuC oqiWMb3mA9OtGTT7y8ai6xWY6Nsagu2jugi+rVw3cnDblJym6kUaMoq9ep/pEQ0NHNLawLiKAYcd YP8OD103fgDkmka3QIWXxut3qbUZs6TQhrkdxkckTxTFvSiNn5QpOYFPSI0+CLXfw9cZZv4f6gly N/E/LmivagVZkpDWKSi9uhiQmFI/IGTmuC6+CYG4L1535aFZGTqb9elWSIEn+4lwCnQz/wde/jT9 ladm9b56Quc7capEvYmd3OE3mUNVBtSaqJRqcVYzKVCMZ3zYjr1e41/jnpWJu+j6gLSOAjr0M1he dRvQfBtwNGqCiqMoKomu7aNDm5hNWBv6uikFkAvHH4Po2ha2aXxFnVI7hE8Uv4YOBbXITFJ1G74W SyO9odTcGK8o72tmc4psNQgd4CvVCr8y7f85r4iEiHnKZ99YRpBIGAsBPI65isn0ZAtvFF3OhU5b D/O85W6hHc7lktr4qnYcZh5+5XV3e3X2ZSXsdEjWwJRehlSIztV7q08lND38VRIIWMrdCDUXznJS tvgFP2E+aQqZWEXxC+oJiSg6E8tZUljMcyx7D5or5Sb7AcChKZ6Mz2dNUbzY153MlyEin3R4GlNp 8AGcBrAQGNXMVyO/ND+1sJUK8ZDEZo9oX/N1kgo0qK1xKJ4H7nAJ3/LdSdogB412VWFPD7/ywbv6 GJjhnVcNDeZ29XPfqwF/vi0/39r1MKszTjQVcvQJuEsJrJGhEiJVnaCSRekj6AyhDViDMdOrCFiN qeaftJEIFzcItZ2U3OjmDs3TlaEjIfOfuYUDM8K+lYR4eFvhcg5CLmx6ouYyt1UloTbm8rbosO5p FkhrFc3Bqg2LqcETO6K7dRngmZxd2WWLCMwKLXNPn+OkN5jByLLd0ZnFvkOTpCPkWP3qlSwRte4m i4xxcZKIu3m+PP49SpZDuuYZ8tgXVIzfCCdOn5zo+CAvpJFjWa0wNj3pb9k0yAMZvNSZ6EDENtKP 0aVU13crg9dZVkm0bP6g02tb7hbsq4ph0P/PVlV+Qh77BqiJxbpiLT+UNpRCN1I7olLkESg2OY6j ge/Db15Igh+Xy2R6XXc68bvqK4BpAhrxsKkJq2svsyICwGrYf3/VIspevJ6DGPFec5kBRefAt3GS 2icMGACVd88354Y1sXKZFxYf76zbLsfE99GqKOGBtHysdlWedBCw3BLzZSvoP3r+Wpl4BpUndSZA UmWqiHFi7LXf49s9ao/AsmJeFYTfaL2u8qNTwmnyUq6fNRd4gubjJBz1jSNwlyGAMFvyor43KHTA UKnMT9qO48R+sVmDiFSRvLUajReCRchmoioNQM2FYTeoBDU6ng2Xd/Nu2zr1El3Hmc9nNsVmmkCP 8mZQvOCGFCi4cECDJY5V44DYvsZR6TNZWoghgXNFYtuv65/DsspJOYuWD9Y4uVSGJNJP3OTFh0oe pOJ7uj8GfNdpboAJU966AfMXg2e41Suzvro4QcduC8MQeBurf6Gl3c8A4vpbSFHSySyq+8FSXuCN U5bL9wdK2HfYrVFXGFuhTZjTYSwBvruyihpz85IxUbshtbUthyDa4AInRwmwVe4QHbv3TU2mkm1v Y++EiGH0oudflkgkr6ZKkcvf2HQ/tXWObDRdkGjXllexs1Ipg8BScHDC+UT/nJ7r8xxC6z6D571Z iP/sGyX8Ql61JIJAbQ2MfzhKx+ny+pdYM3lP1jwZX0w9Z+rEvBytSlcBazT5sSaCWBxsaGZUYPDH 6DT4ZK3pM8m2K8cb9rF8H7ndkRIhNuAtwDdclgeQ4YcPujmMYSFrTyArdFtfh51NJm2DpExZCeEU 12J2PZq+weVpd39hlvgf8soHFxj1LG+gK86gVLzGF7wh2+hoA1o1UljcznpN9UqmMhD95PrJxBPV uEXxHJ9lgtf+Fn3v+WGbAtZqVQpOC4E6cK2MeTar2e4hBTvp7ndPnAgcHdr/j3Damd46sZwgy3ji NvlKLlUqKvg8ALdONF2JHUDl91itDG9oo1unzWILvtIJTT6S1DuoLlXTOKZoxR5NlFfdh0BufaMy Jta6iBhbyrzVBWvDy9eB3QN3Ti7/3uBBw2h/GX+Y0An0zlt13+8NOXan/C6SnrNgl6Vz77MXvG/a hvrL6u+6zvII0ai6zcYI1cGVXIMrbQhnHQC/YMi7i+ZVi1AF4gU/Iao7yujbtm6paZG8/XwK4fgz vn97Br73dndgJ7Nq5oHwl3LMQd6NpwQs0xaU6gMLIyDobV9LnEhQTPuy27IwdWlEIOz9yAV4IJQd 8FJtcEUcySFzVT64Jm5505VcivSRbFWlYdNQC3dYF+Mh6+xO2bzj7ncakOOQrwxcqUY+A6fRwRwv BrjYdTXRz8Olykce8YlxtKxb2SsZmyTcW2nGTiDsr4Zo/aeatpznahIuJ/XOLReXkxBgS0GlXghF WPd7Qnra/QYBzwpx4EGrOF6pgYms6Tef16Qz17roOcngM8jEWV547LVKnc8HIkFOjLzWhPuiq8Ge CPR3UcXLlRnqrFR/NXzEijLStWe4vhxE00PErPe/adqQRZ28FpUDb+jrIStQRdAfax9U+Y0AVhr2 2w6nZAo7/ASfpGhHsU/2lidQ24d4oBoCnf69Qy/xUvx7Yoz9rWYQsPl1bWYuXSxFHIKke0y+iNF0 gx+Xa/etAhFE21fB06psQuq7mqWYrNqdFHjqLt6ityBmhmWawcnvOw== `protect end_protected

mit

7742bcbcf0f7803cd1925b5941f34166

dtysky/LD3320_AXI

src/LIST/synth/LIST.vhd

-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_2; USE blk_mem_gen_v8_2.blk_mem_gen_v8_2; ENTITY LIST IS PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END LIST; ARCHITECTURE LIST_arch OF LIST IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF LIST_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_2 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); sleep : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_2; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF LIST_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF LIST_arch : ARCHITECTURE IS "LIST,blk_mem_gen_v8_2,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF LIST_arch: ARCHITECTURE IS "LIST,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=1,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=LIST.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=256,C_READ_DEPTH_A=256,C_ADDRA_WIDTH=8,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=256,C_READ_DEPTH_B=256,C_ADDRB_WIDTH=8,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.68455 mW}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK"; ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR"; ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT"; BEGIN U0 : blk_mem_gen_v8_2 GENERIC MAP ( C_FAMILY => "zynq", C_XDEVICEFAMILY => "zynq", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 0, C_ENABLE_32BIT_ADDRESS => 0, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 1, C_BYTE_SIZE => 9, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 0, C_INIT_FILE_NAME => "no_coe_file_loaded", C_INIT_FILE => "LIST.mem", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 0, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 0, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 0, C_WEA_WIDTH => 1, C_WRITE_MODE_A => "WRITE_FIRST", C_WRITE_WIDTH_A => 8, C_READ_WIDTH_A => 8, C_WRITE_DEPTH_A => 256, C_READ_DEPTH_A => 256, C_ADDRA_WIDTH => 8, C_HAS_RSTB => 0, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 0, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 0, C_WEB_WIDTH => 1, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 8, C_READ_WIDTH_B => 8, C_WRITE_DEPTH_B => 256, C_READ_DEPTH_B => 256, C_ADDRB_WIDTH => 8, C_HAS_MEM_OUTPUT_REGS_A => 0, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "0", C_COUNT_18K_BRAM => "1", C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.68455 mW" ) PORT MAP ( clka => clka, rsta => '0', ena => '0', regcea => '0', wea => wea, addra => addra, dina => dina, clkb => clkb, rstb => '0', enb => '0', regceb => '0', web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), addrb => addrb, dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), doutb => doutb, injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END LIST_arch;

mit

121c6d0b4b3ff5e10aacd5dd4e86f481

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fdiv_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 0; constant FMUL_IMPLEMENT : integer := 0; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

1c050a1ab347aa17349a167de6a3826a

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_max_mem_cntrl.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 8; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

ab7d4656dc9b0bf226702bc574c9f717

chrbirks/NiosII-basic

nios_system/nios_system_inst.vhd

component nios_system is port ( switches_export : in std_logic_vector(3 downto 0) := (others => 'X'); -- export leds_export : out std_logic_vector(3 downto 0); -- export clk_clk : in std_logic := 'X'; -- clk reset_reset_n : in std_logic := 'X' -- reset_n ); end component nios_system; u0 : component nios_system port map ( switches_export => CONNECTED_TO_switches_export, -- switches.export leds_export => CONNECTED_TO_leds_export, -- leds.export clk_clk => CONNECTED_TO_clk_clk, -- clk.clk reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n );

gpl-3.0

33e21fe8a7dba255cf19074095d6bdd8

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_2AXI_2CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

6ca7d27e652775bfdae7d6a6f0ffff91

viccuad/fpga-thingies

tron/tron.vhd

-- hecho para ser visto con tab size = 3 library IEEE; library UNISIM; use UNISIM.vcomponents.all; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tron is port ( ps2Clk: IN std_logic; ps2Data: IN std_logic; clk: IN std_logic; reset: IN std_logic; --reset activo a baja! hSync: OUT std_logic; Vsync: OUT std_logic; colisionOUT: OUT std_logic; DI2: OUT std_logic_vector(0 downto 0); DI1: OUT std_logic_vector(0 downto 0); segs: OUT std_logic_vector (6 downto 0); R: OUT std_logic_vector (2 downto 0); -- alconversor D/A G: OUT std_logic_vector (2 downto 0); -- alconversor D/A B: OUT std_logic_vector (2 downto 0) -- alconversor D/A ); end tron; architecture Behavioral of tron is component ps2KeyboardInterface port ( clk: IN std_logic; rst: IN std_logic; ps2Clk: IN std_logic; ps2Data: IN std_logic; data: OUT std_logic_vector (7 DOWNTO 0); newData: OUT std_logic; newDataAck: IN std_logic ); end component; --señales maquina de estados type fsmEstados is (pulsadas, despulsadas); signal estado: fsmEstados; type fsmEstados2 is (jugando, parado, reseteo); signal estado2: fsmEstados2; --señales PS2 signal newData, newDataAck: std_logic; signal scancode: std_logic_vector (7 downto 0); --señales VGA signal senialHSync, senialVSync: std_logic; signal finPixelCont: std_logic; signal cuentaPixelCont: std_logic_vector (10 downto 0); signal cuentaLineCont: std_logic_vector (9 downto 0); signal comp1, comp2, comp3, comp4, comp5, comp6: std_logic; signal Rcoche1,Rcoche2,Restela: std_logic_vector (2 downto 0); signal Gcoche1,Gcoche2,Gestela: std_logic_vector (2 downto 0); signal Bcoche1,Bcoche2,Bestela: std_logic_vector (2 downto 0); --señales juego signal pixelCoche1Hor,pixelCoche2Hor: std_logic_vector (7 downto 0); --153 pixeles (10011001) signal pixelCoche1Ver,pixelCoche2Ver: std_logic_vector (6 downto 0); --102 pixeles signal movCoche1,movCoche2: std_logic_vector (1 downto 0); -- 00 = arriba , 01 = derecha , 10 = abajo , 11 = izquierda signal ldMov1,ldMov2: std_logic; signal moverCoches: std_logic; signal cuenta1dec: STD_LOGIC_VECTOR(19 downto 0); --contador1decima signal finCuenta1Dec: STD_LOGIC; signal cuentacontReseteo: std_logic_vector(14 downto 0); signal finCuentaContReseteo,enableContReseteo,hayColision: std_logic; signal coche1SeMueve, coche2SeMueve,coche1SeMueve2, coche2SeMueve2: std_logic; --señales teclas signal teclaSPC: std_logic; signal clTeclaSPC: std_logic; signal ldTeclaSPC: std_logic; --seniales memorias signal estelaCoche1MenosSig,estelaCoche2MenosSig,estelaCoche1MasSig,estelaCoche2MasSig,DOBcoche1MenosSig,DOBcoche1MasSig,DOBcoche2MenosSig,DOBcoche2MasSig: std_logic_vector(0 downto 0); signal selPixelPantalla: std_logic_vector (14 downto 0); -- pixeles logicos hor (120) concatenado con pixeles logicos ver (153): cuentaPixelCont(10 downto 3)++cuentaLineCont(8 downto 2) signal selPixelCoche1,selPixelCoche2: std_logic_vector (14 downto 0); --pixelCoche1/2Hor concatenado pixelCoche1/2Ver signal estelaMem: std_logic_vector (1 downto 0); signal WEBmenosSig1, WEBmasSig,WEBmenosSig2, WEBmasSig2,WEcoche1,WEcoche2,senialWEA: std_logic; signal DIBcoche1,DIBcoche2,DOBcoche1,DOBcoche2: std_logic_vector(0 downto 0); --señales de depuracion signal st : std_logic_vector (1 downto 0); begin --------------------------- RAM ------------------------------------------------ colisionOUT <= hayColision; DI1 <= DIBcoche1; DI2 <= DIBcoche2; selPixelCoche1(14 downto 7) <= pixelCoche1Hor; selPixelCoche1(6 downto 0) <= pixelCoche1Ver; selPixelCoche2(14 downto 7) <= pixelCoche2Hor; selPixelCoche2(6 downto 0) <= pixelCoche2Ver; selPixelPantalla(14 downto 7) <= cuentaPixelCont(10 downto 3); selPixelPantalla(6 downto 0) <= cuentaLineCont(8 downto 2); --http://www.xilinx.com/itp/xilinx10/books/docs/spartan3_hdl/spartan3_hdl.pdf rojoMenosSignif: RAMB16_S1_S1 generic map( WRITE_MODE_B => "READ_FIRST" ) port map ( DOA => estelaCoche1MenosSig, -- Port A 1-bit Data Output DOB => DOBcoche1MenosSig, -- Port B 1-bit Data Output ADDRA => selPixelPantalla(13 downto 0), -- Port A 14-bit Address Input ADDRB => selPixelCoche1(13 downto 0), -- Port B 14-bit Address Input CLKA => clk, -- Port A Clock CLKB => clk, -- Port B Clock DIA => "0", -- Port A 1-bit Data Input DIB => DIBcoche1, -- Port B 1-bit Data Input --pintamos rojo ENA => '1', -- Port A RAM Enable Input ENB => '1', -- PortB RAM Enable Input SSRA => '0', -- Port A Synchronous Set/Reset Input SSRB => '0', -- Port B Synchronous Set/Reset Input WEA => senialWEA, -- Port A Write Enable Input WEB => WEBmenosSig1 -- Port B Write Enable Input ); rojoMasSignif: RAMB16_S1_S1 generic map( WRITE_MODE_B => "READ_FIRST" ) port map ( DOA => estelaCoche1MasSig, -- Port A 1-bit Data Output DOB => DOBcoche1MasSig, -- Port B 1-bit Data Output ADDRA => selPixelPantalla(13 downto 0), -- Port A 14-bit Address Input ADDRB => selPixelCoche1(13 downto 0), -- Port B 14-bit Address Input CLKA => clk, -- Port A Clock CLKB => clk, -- Port B Clock DIA => "0", -- Port A 1-bit Data Input DIB => DIBcoche1, -- Port B 1-bit Data Input --pintamos rojo ENA => '1', -- Port A RAM Enable Input ENB => '1', -- PortB RAM Enable Input SSRA => '0', -- Port A Synchronous Set/Reset Input SSRB => '0', -- Port B Synchronous Set/Reset Input WEA => senialWEA, -- Port A Write Enable Input WEB =>WEBmasSig -- Port B Write Enable Input ); azulMenosSignif: RAMB16_S1_S1 generic map( WRITE_MODE_B => "READ_FIRST" ) port map ( DOA => estelaCoche2MenosSig, -- Port A 1-bit Data Output DOB => DOBcoche2MenosSig, -- Port B 2-bit Data Output ADDRA => selPixelPantalla(13 downto 0), -- Port A 14-bit Address Input ADDRB => selPixelCoche2(13 downto 0), -- Port B 14-bit Address Input CLKA => clk, -- Port A Clock CLKB => clk, -- Port B Clock DIA => "0", -- Port A 1-bit Data Input DIB => DIBcoche2, -- Port B 1-bit Data Input --pintamos azul ENA => '1', -- Port A RAM Enable Input ENB => '1', -- PortB RAM Enable Input SSRA => '0', -- Port A Synchronous Set/Reset Input SSRB => '0', -- Port B Synchronous Set/Reset Input WEA => senialWEA, -- Port A Write Enable Input WEB => WEBmenosSig2 -- Port B Write Enable Input ); azulMasSignif: RAMB16_S1_S1 generic map( WRITE_MODE_B => "READ_FIRST" ) port map ( DOA => estelaCoche2MasSig, -- Port A 1-bit Data Output DOB => DOBcoche2MasSig, -- Port B 1-bit Data Output ADDRA => selPixelPantalla(13 downto 0), -- Port A 14-bit Address Input ADDRB => selPixelCoche2(13 downto 0), -- Port B 14-bit Address Input CLKA => clk, -- Port A Clock CLKB => clk, -- Port B Clock DIA => "0", -- Port A 1-bit Data Input DIB => DIBcoche2, -- Port B 1-bit Data Input --pintamos azul ENA => '1', -- Port A RAM Enable Input ENB => '1', -- PortB RAM Enable Input SSRA => '0', -- Port A Synchronous Set/Reset Input SSRB => '0', -- Port B Synchronous Set/Reset Input WEA => senialWEA, -- Port A Write Enable Input WEB => WEBmasSig2 -- Port B Write Enable Input ); WEB_MasSig2 interfazPS2: ps2KeyboardInterface port map ( rst => reset, clk => clk, ps2Clk => ps2Clk, ps2Data => ps2Data, data => scancode, newData => newData, newDataAck => newDataAck ); decoSalida: process(selPixelCoche1,selPixelCoche2,selPixelPantalla,DOBcoche1MenosSig, DOBcoche1MasSig,DOBcoche2MenosSig,DOBcoche2MasSig,WEcoche1, WEcoche2,estelaCoche1MenosSig,estelaCoche1MasSig,estelaCoche2MenosSig, estelaCoche2MasSig) begin if (selPixelPantalla(14) = '0') then --direccionar a las menos signif estelaMem(1 downto 1) <= estelaCoche1MenosSig; estelaMem(0 downto 0) <= estelaCoche2MenosSig; else --direccionar a las mas signif estelaMem(1 downto 1) <= estelaCoche1MasSig; estelaMem(0 downto 0) <= estelaCoche2MasSig; end if; if (selPixelCoche1(14) = '0') then --direccionar a las menos signif WEBmenosSig1 <= WEcoche1; WEBmasSig <= '0'; DOBcoche1 <= DOBcoche1MenosSig; else --direccionar a las mas signif WEBmenosSig1 <= '0'; WEBmasSig <= WEcoche1; DOBcoche1 <= DOBcoche1MasSig; end if; if (selPixelCoche2(14) = '0') then --direccionar a las menos signif WEBmenosSig2 <= WEcoche2; WEBmasSig2 <= '0'; DOBcoche2 <= DOBcoche2MenosSig; else --direccionar a las mas signif WEBmenosSig2 <= '0'; WEBmasSig2 <= WEcoche2; DOBcoche2 <= DOBcoche2MasSig; end if; end process decoSalida; --------------------------- PANTALLA ------------------------------------------- hSync <= senialHSync; vSync <= senialVSync; pantalla: process(clk, reset,cuentaPixelCont,cuentaLineCont,Rcoche1,Rcoche2, Gcoche1,Gcoche2,Bcoche1,Bcoche2,Restela,Gestela,Bestela) begin --cont mod 1589 (pixelCont para sincronismo horizontal) if (cuentaPixelCont = "11000110100") then finPixelCont <= '1'; else finPixelCont <= '0'; end if; if(reset = '0')then cuentaPixelCont <= (others => '0'); finPixelCont <= '0'; elsif(clk'event and clk = '1') then if (cuentaPixelCont /= "11000110100") then --1588 cuentaPixelCont <= cuentaPixelCont + '1'; elsif (cuentaPixelCont = "11000110100") then cuentaPixelCont <= (others => '0'); end if; end if; --cont mod 528 (lineCont para sincronismo vertical) if(reset = '0')then cuentaLineCont <= (others => '0'); elsif(clk'event and clk = '1') then if (finPixelCont = '1' and cuentaLineCont /= "1000001111") then --527 cuentaLineCont <= cuentaLineCont + '1'; elsif (finPixelCont = '1' and cuentaLineCont = "1000001111") then cuentaLineCont <= (others => '0'); end if; end if; --comparaciones if (cuentaPixelCont > 1257) then comp1 <= '1'; else comp1 <= '0'; end if; if (cuentaPixelCont > 1304) then comp2 <= '1'; else comp2 <= '0'; end if; if (cuentaPixelCont <= 1493) then comp3 <= '1'; else comp3 <= '0'; end if; if (cuentaLineCont > 479) then comp4 <= '1'; else comp4 <= '0'; end if; if (cuentaLineCont > 493) then comp5 <= '1'; else comp5 <= '0'; end if; if (cuentaLineCont <= 495) then comp6 <= '1'; else comp6 <= '0'; end if; senialHSync <= comp2 nand comp3; senialVSync <= comp5 nand comp6; if (senialHSync = '0' or senialVSync = '0') then --no pinta R <= "000"; G <= "000"; B <= "000"; else R(2) <= ( (not (comp1 or comp4)) and (Rcoche1(2) or Rcoche2(2) or Restela(2)) ); R(1) <= ( (not (comp1 or comp4)) and (Rcoche1(1) or Rcoche2(1) or Restela(1)) ); R(0) <= ( (not (comp1 or comp4)) and (Rcoche1(0) or Rcoche2(0) or Restela(0)) ); G(2) <= ( (not (comp1 or comp4)) and (Gcoche1(2) or Gcoche2(2) or Gestela(2)) ); G(1) <= ( (not (comp1 or comp4)) and (Gcoche1(1) or Gcoche2(1) or Gestela(1)) ); G(0) <= ( (not (comp1 or comp4)) and (Gcoche1(0) or Gcoche2(0) or Gestela(0)) ); B(2) <= ( (not (comp1 or comp4)) and (Bcoche1(2) or Bcoche2(2) or Bestela(2)) ); B(1) <= ( (not (comp1 or comp4)) and (Bcoche1(1) or Bcoche2(1) or Bestela(1)) ); B(0) <= ( (not (comp1 or comp4)) and (Bcoche1(0) or Bcoche2(0) or Bestela(0)) ); end if; end process; ------------------------------- PINTAR JUEGO ---------------------------------- -- vertical: 479 limite de pixeles visibles -- 120 pixeles -> 479 x= (479*1)/120 = 3.99 = aprox 4 -- 1 pixeles -> x -- horizontal: 1257 limite de pixeles visibles -- 153 pixeles -> 1257 x= (1257*1)/153 = 8.21 = aprox 8 -- 1 pixeles -> x pintarCoche1: process(cuentaLineCont,cuentaPixelCont,pixelCoche1Ver,pixelCoche1Hor) begin -- inicializacion Rcoche1 <= "000"; Gcoche1 <= "000"; Bcoche1 <= "000"; --pintar if ((cuentaLineCont(9 downto 2) >= pixelCoche1Ver-1 and cuentaLineCont(9 downto 2) <= pixelCoche1Ver+1) and (cuentaPixelCont(10 downto 3) >= pixelCoche1Hor-1 and cuentaPixelCont(10 downto 3) <= pixelCoche1Hor+1)) then Rcoche1 <= "111";--coche rojo Gcoche1 <= "000"; Bcoche1 <= "000"; end if; end process pintarCoche1; pintarCoche2: process(cuentaLineCont,cuentaPixelCont,pixelCoche2Ver,pixelCoche2Hor) begin -- inicializacion Rcoche2 <= "000"; Gcoche2 <= "000"; Bcoche2 <= "000"; --pintar if ((cuentaLineCont(9 downto 2) >= pixelCoche2Ver-1 and cuentaLineCont(9 downto 2) <= pixelCoche2Ver+1) and (cuentaPixelCont(10 downto 3) >= pixelCoche2Hor-1 and cuentaPixelCont(10 downto 3) <= pixelCoche2Hor+1)) then Rcoche2 <= "000"; Gcoche2 <= "000"; Bcoche2 <= "111";--coche azul end if; end process pintarCoche2; pintarEstelas: process(cuentaLineCont,cuentaPixelCont,estelaMem) begin -- inicializacion Restela <= "000"; Gestela <= "000"; Bestela <= "000"; --pintar case estelaMem is when "01" => Restela <= "000"; --pintamos estela azul Gestela <= "000"; Bestela <= "111"; when "10" => Restela <= "111"; --pintamos estela rojo Gestela <= "000"; Bestela <= "000"; when "11" => Restela <= "111"; --las estelas se superponen Gestela <= "000"; Bestela <= "111"; when others => Restela <= "000"; --no hay estela Gestela <= "000"; Bestela <= "000"; end case; end process pintarEstelas; --#################### CONTROL JUEGO ########################################### contadorMediaDecima: process(reset,clk,cuenta1dec) --contador mod 5.000.000 (de 0 a 4.999.999) begin if (cuenta1dec = "11110100001000111111") then finCuenta1Dec <= '1'; else finCuenta1Dec <= '0'; end if; if(reset = '0')then cuenta1dec <= (others => '0'); finCuenta1Dec <= '0'; elsif(clk'event and clk = '1') then if (cuenta1dec /= "11110100001000111111") then cuenta1dec <= cuenta1dec + 1; elsif (cuenta1dec = "11110100001000111111") then cuenta1dec <= (others => '0'); end if; end if; end process contadorMediaDecima; coche1: process(moverCoches,finCuenta1Dec,clk,reset,movCoche1,pixelCoche1Hor,pixelCoche1Ver) begin coche1SeMueve <= '1'; if(finCuenta1Dec = '1' and moverCoches = '1') then coche1SeMueve <= '1'; else coche1SeMueve <= '0'; end if; --vertical: cont mod 102 y horizontal: cont mod 153 if (reset = '0')then --pos inicial coche1 pixelCoche1Ver <= "0001000"; --en 9 pixelCoche1Hor <= "00000000"; --en 1 coche1SeMueve <= '0'; elsif (clk'event and clk = '1') then if(finCuenta1Dec = '1' and moverCoches = '1') then case movCoche1 is when "00" => if (pixelCoche1Ver = 0) then --va hacia arriba pixelCoche1Ver <= "1110111"; else pixelCoche1Ver <= pixelCoche1Ver - '1'; end if; when "10" => if (pixelCoche1Ver = 120) then --va hacia abajo pixelCoche1Ver <= "0000000"; else pixelCoche1Ver <= pixelCoche1Ver + '1'; end if; when "11" => if ( pixelCoche1Hor = 0) then --va hacia izquierda pixelCoche1Hor <= "10011000"; else pixelCoche1Hor <= pixelCoche1Hor - '1'; end if; when "01" => if (pixelCoche1Hor = 153) then --va hacia derecha pixelCoche1Hor <= "00000000"; else pixelCoche1Hor <= pixelCoche1Hor + '1'; end if; when others => null; end case; end if; if (teclaSPC = '1') then pixelCoche1Ver <= "0001000"; --en 9 pixelCoche1Hor <= "00000000"; --en 1 end if; end if; end process coche1; coche2: process(finCuenta1Dec,moverCoches,clk,reset,movCoche2,pixelCoche2Hor,pixelCoche2Ver) begin coche2SeMueve <= '0'; if(finCuenta1Dec = '1' and moverCoches = '1') then coche2SeMueve <= '1'; else coche2SeMueve <= '0'; end if; --vertical: cont mod 102 y horizontal: cont mod 153 if (reset = '0')then --pos inicial coche2 pixelCoche2Ver <= "1101110"; --en 110 pixelCoche2Hor <= "10011000"; --en 152 coche2SeMueve <= '0'; elsif (clk'event and clk = '1') then if(finCuenta1Dec = '1' and moverCoches = '1') then case movCoche2 is when "00" => if (pixelCoche2Ver = 0) then --va hacia arriba pixelCoche2Ver <= "1110111"; else pixelCoche2Ver <= pixelCoche2Ver - '1'; end if; when "10" => if (pixelCoche2Ver = 120) then --va hacia abajo pixelCoche2Ver <= "0000000"; else pixelCoche2Ver <= pixelCoche2Ver + '1'; end if; when "11" => if ( pixelCoche2Hor = 0) then --va hacia izquierda pixelCoche2Hor <= "10011000"; else pixelCoche2Hor <= pixelCoche2Hor - '1'; end if; when "01" => if (pixelCoche2Hor = 153) then --va hacia derecha pixelCoche2Hor <= "00000000"; else pixelCoche2Hor <= pixelCoche2Hor + '1'; end if; when others => null; end case; end if; if (teclaSPC = '1') then pixelCoche2Ver <= "1101110"; --en 110 pixelCoche2Hor <= "10011000"; --en 152 end if; end if; end process coche2; colision: process(estelaMem,DOBcoche1,DOBcoche2,coche1SeMueve,coche2SeMueve,WEcoche1,WEcoche2) begin hayColision <= '0'; if (estelaMem = "11" or --chocan entre ellos (DOBcoche1 = "1" and WEcoche1 = '1') or (DOBcoche2 = "1" and WEcoche2 = '1') --chocan consigo mismo )then hayColision <= '1'; else hayColision <= '0'; end if; end process colision; ------maquina de estados con registros de flags--------------------------------- controladorEstados: process (clk, reset, newData, scancode) begin if(reset = '0') then estado <= pulsadas; elsif (clk'event and clk = '1') then estado <= pulsadas; -- estado por defecto, puede ser sobreescrito luego case estado is when pulsadas => estado <= pulsadas; if (newData = '1' and scancode = "11110000") then --11110000: F0 estado <= despulsadas; end if; when despulsadas => estado <= despulsadas; if (newData = '1') then estado <= pulsadas; end if; end case; end if; end process; generadorSalidaMealy: process (reset,newDataAck, scancode, estado, newData) begin newDataAck <= '0'; clTeclaSPC <= '0'; ldTeclaSPC <= '0'; case estado is when pulsadas => if (newData = '1') then --11110000: F0 case scancode is --registros de flags: when "00010101" => ldMov1 <= '1' ; --Q=15 arriba when "00011100" => ldMov1 <= '1' ; --A=1C abajo when "00011010" => ldMov1 <= '1' ; --Z=1A izq when "00100010" => ldMov1 <= '1' ; --X=22 der when "01001101" => ldMov2 <= '1' ; --P=4D arriba when "01001011" => ldMov2 <= '1' ; --L=4B abajo when "00110001" => ldMov2 <= '1' ; --N=31 izq when "00111010" => ldMov2 <= '1' ; --M=3A der when "00101001" => ldTeclaSPC <= '1'; clTeclaSPC <= '0'; --SPC=29 when others => null; end case; newDataAck <= '1'; end if; when despulsadas => if (newData = '1') then case scancode is --registros de flags: when "00101001" => ldTeclaSPC <= '0'; clTeclaSPC <= '1'; --SPC=29 when others => null; end case; newDataAck <= '1'; end if; when others => null; end case; end process; -------------------------------------------------------------------------------- biestableDteclaSPC: process(reset,clk,ldTeclaSPC,clTeclaSPC) begin if(reset = '0')then teclaSPC <= '0'; elsif(clk'event and clk = '1' ) then if (clTeclaSPC = '1') then teclaSPC <= '0'; elsif (ldTeclaSPC = '1') then teclaSPC <= '1'; end if; end if; end process biestableDteclaSPC; registroMovCoche1: process(reset,clk,ldMov1,teclaSPC,scancode) begin if(reset = '0')then movCoche1 <= "01"; --hacia der elsif(clk'event and clk = '1' ) then if (teclaSPC = '1') then movCoche1 <= "01"; --hacia der elsif (ldMov1 = '1') then case scancode is when "00010101" => movCoche1 <= "00"; --Q=15 arriba when "00011100" => movCoche1 <= "10"; --A=1C abajo when "00011010" => movCoche1 <= "11"; --Z=1A izq when "00100010" => movCoche1 <= "01"; --X=22 der when others => null; end case; end if; end if; end process registroMovCoche1; registroMovCoche2: process(reset,clk,ldMov2,teclaSPC,scancode) begin if(reset = '0')then movCoche2 <= "11"; --hacia der elsif(clk'event and clk = '1' ) then if (teclaSPC = '1') then movCoche2 <= "11"; --hacia der elsif (ldMov2 = '1') then case scancode is when "01001101" => movCoche2 <= "00"; --P=4D arriba when "01001011" => movCoche2 <= "10"; --L=4B abajo when "00110001" => movCoche2 <= "11"; --N=31 izq when "00111010" => movCoche2 <= "01"; --M=3A der when others => null; end case; end if; end if; end process registroMovCoche2; -----maquina de estados del juego ---------------------------------------------- controladorEstados2: process (clk, reset, finCuentaContReseteo, hayColision, teclaSPC, finCuenta1Dec) begin if(reset = '0') then estado2 <= jugando; elsif (clk'event and clk = '1') then estado2 <= jugando; -- estado por defecto, puede ser sobreescrito luego case estado2 is when jugando => estado2 <= jugando; if (hayColision = '1') then estado2 <= parado; elsif (teclaSPC = '1') then estado2 <= reseteo; end if; when parado => estado2 <= parado; if (teclaSPC = '1') then estado2 <= reseteo; end if; when reseteo => estado2 <= reseteo; if (finCuentaContReseteo = '1') then estado2 <= jugando; end if; end case; end if; end process; generadorSalidaMoore2: process (estado2) begin DIBcoche1 <= "1"; DIBcoche2 <= "1"; enableContReseteo <= '0'; moverCoches <= '1'; st <= "00"; senialWEA <= '0'; case estado2 is when jugando => DIBcoche1 <= "1"; DIBcoche2 <= "1"; enableContReseteo <= '0'; moverCoches <= '1'; st <= "00"; senialWEA <= '0'; when parado => DIBcoche1 <= "0"; DIBcoche2 <= "0"; enableContReseteo <= '0'; moverCoches <= '0'; st <= "01"; senialWEA <= '0'; when reseteo => DIBcoche1 <= "0"; DIBcoche2 <= "0"; enableContReseteo <= '1'; moverCoches <= '0'; st <= "10"; senialWEA <= '1'; when others => null; end case; end process; conversor7seg: process(st) begin case st is --gfedcba when "00" => segs <= "0111111"; when "01" => segs <= "0000110"; when "10" => segs <= "1011011"; when OTHERS => segs <= "1111001"; -- error end case; end process; -------------------------------------------------------------------------------- contReseteo: process(reset,clk,cuentacontReseteo,enableContReseteo) --contador mod 2^15=32768 (120 x 153 pixeles) begin if (cuentacontReseteo = "111111111111111") then finCuentaContReseteo <= '1'; else finCuentaContReseteo <= '0'; end if; if(reset = '0')then cuentacontReseteo <= (others => '0'); finCuentaContReseteo <= '0'; elsif(clk'event and clk = '1') then if(enableContReseteo = '1') then if (cuentacontReseteo /= "111111111111111") then cuentacontReseteo <= cuentacontReseteo + 1; end if; elsif (enableContReseteo = '0') then cuentacontReseteo <= (others => '0'); end if; end if; end process contReseteo; biestableDcoche1SeMueveRetrasa1ciclo: process(reset,clk,coche1SeMueve) --con estos biestablesD conseguimos escribir sólo una vez en memoria por cada movimiento de coche begin if(reset = '0')then coche1SeMueve2 <= '0'; elsif(clk'event and clk = '1' ) then coche1SeMueve2 <= coche1SeMueve; end if; end process biestableDcoche1SeMueveRetrasa1ciclo; biestableDcoche2SeMueveRetrasa1ciclo: process(reset,clk,coche2SeMueve) begin if(reset = '0')then coche2SeMueve2 <= '0'; elsif(clk'event and clk = '1' ) then coche2SeMueve2 <= coche2SeMueve; end if; end process biestableDcoche2SeMueveRetrasa1ciclo; biestableDWEcoche1: process(reset,clk,coche1SeMueve2) --con estos biestablesD conseguimos escribir sólo una vez en memoria por cada movimiento de coche begin if(reset = '0')then WEcoche1 <= '0'; elsif(clk'event and clk = '1' ) then WEcoche1 <= coche1SeMueve2; end if; end process biestableDWEcoche1; biestableDWEcoche2: process(reset,clk,coche2SeMueve2) begin if(reset = '0')then WEcoche2 <= '0'; elsif(clk'event and clk = '1' ) then WEcoche2 <= coche2SeMueve2; end if; end process biestableDWEcoche2; end Behavioral;

gpl-3.0

ccbab33b09ac435582eb81db029d8ee5

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_axi_read_wrapper.vhd

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block N/heajpNrarYNU3C254jDWshE5DbEj22fqC1Yucdjc4fkTOjG+ALNLiIqAjeHVj2PcYj0LHHhnDu v+EHF5nmJA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block BLPoCYfoVBAH3RZ9vFKtH2HtwnbxcgO7h8CjI3i5SLCIBQ6+XWBtF6JA5HvbM075qHjgpvtc+IIF FVyBkg4RsdPCzMj/qR1a/RLtGLYJdF4+boBc+WGB/O/67rOyITAHUOcztKjol5ZNj/U/HpifvIGW dcdRMlBStKHP2iqZE7Q= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Fns7Y/UN2G0Mm/9BCrk0/PTCU3+OxWxbVukLb0iRdQ5e86tBnY/XdBRlXS7i89fVO5yy6ur4wM0F wNggtwWgPTKVGUL7K5q78QwqUuUW3TVtQ6uebQB98k/cIp0JFaCU+isqVDkxh5PdylMgWStBNMW3 fD8ePbh4alm49PPnkz+XJHC/3yV/r3XR1EVRpq8xekTc9rjnlihJiAtSDk+2QpAYRUOaLxJ1uYaB f/c2hLCSCe31LwrwfS5Pvsywpw8WFUk9JEDmN5BAxbJXSczp53458FUIjHtSzaIjpSQI2rMeTs0E xIOpOi0vJuWt2qzsO5qKuAoVEDUFO01HT5jpSg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block K3OZnQdFhsFlHV5aceYU/PfEpky41qUo8FJUTs+MvxKOz4NeUesMc+saeFdHB4YNDk6if5jWLiEE +uGJ5c/yBUwFLcrQSRvnPbKbXUQ83Fyk2IZY1OPxRSAuwtcDnBl++ci6lGC6VMY4CjNYrlWywOq+ 7nGRVz1AG9veU+BjUvo= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block VCELSlKKPMR/IFGPoDE9R6BeRWqdprUDexz/T8r1eqgX/Re4giNmeSwY2/GrMnNEOBS8Ts76n32V p/YD+/eqH0r/IeRPVdYGUm84WUpN11Pwua3lsC4tbSra3iB6YgsWqJbr7t+aDuRlpfB6r4Hjl2Qb WpeZgbd4OO9+awYMKjw0qm3ImTGdeK3zY5JRN/Nh+u7Hov9AU6+fyXMbf1LLXhfSdXRK6KfNALZB JbfeKTUVRDnlixCKwXjcn4aN60xgtgCGuyju0v5vWJ9pwd9A58PSNMv23TOVk0ayFoB3lXmhnat2 OVwbFYaH2fxujE/goNnv+u5tblmJUtViPGRskQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 41056) `protect data_block f3Tvq9hPhVanV6FpZ0GDrcEwQADJitgVtQDhrmDo8KpbUMhU+3qlcgkcZLQNzmiEVYo31y3cQBu+ ZDBehN4JOHVQVypFHR5YMN+3xOL4AJ9Vy1NNR9RBIbS2atJBLg+IN7K3ydsIHZkwqDF6vve3wMtm Ews5C9EcVTYQ2AXfpz1Kqmbuhljmupz6qL+1wkQpAXKRhjqdDbOdfAf4Pm4ppvWz1LoIVFGhk2I8 Gu+Pj3B2C5zPNnjlpQyBhaLuDSD0qQzLpZ4bHV4WgwgIrOpqhlMfvkdKUsTpU9mvFa7zlKECisG7 4yQLQsDyBfb1icT51h1lGs2nKZB3ZN8S4azlkN9WMhejOIoxNJCa8ah7dAEa04xzhIRlpfqUOaRH DOBrWhC+7L7hDlBB1vJ5tRMjU5pfpPksbRxlaN4XsVdxoDD6ACIX0UnNaNBZs7yQ/pGOUVF+YxWQ 46hzKFvhfZvA6UPb130g+bFwcOMKTpC8zkRGl0KQAr8XsC0Bj51v1zZGVDnN6M/0cmOrTFQrihxJ FrtGiEPi3FFi1LSmy1IQjlFfZNmLtMZyoThn4enP2Z4dWu/sJ5iT57ZriMxlP6FoVy6OA+trISXb A4QFXe/txXONRxqnsvWeeO3EZuPl+D4mPE2+MlbABw4WIOtAwUWStQtixzSeulX1D3iXYopesK7h Sr5K30cmuh28QTiHYjDXMdSEOAw7lp/HK8Az5jjzKhUt98Kt/wI7rwO19kGiJdyztKZZisXlpXuc 1Tzi1ahCMZfUVPC8STeNxq5EdwhAqNlk4wBIiM+2u/8qElbzGHC8vo5ImYrwNMVWWHTBci9Jkf+z piiVFQ25BhevJFh33JAZ+1kIPArcb6VJ80hET4085U5N8DdZO5feYSOF3rUrZQdxagvcLrW7UB7G +T3pNqE80Yh3xCkG0jU+4yQFp/JF8geST3acrE5084btCuB+PG7m5pXRGndsxYtMK1K62uVMUaop 6LvjW+FUn4zP8Biig5cDS6vwpzLnvaM2oW4n96G8zAvYw99CfVJNnM/ZkDBRp+HwVZbJME/p5x4J U+ihMbxHI4T3EBlGDq6djERkKy1yBMz5Ov8IafOb590fFed8HLMtzpYYhqMHL7K48T+PZcITiSqJ gv6CH0pxZZTvVmLUz1H4ZTxfIkGKtJzPyDFsTN0moXYU4OczmhRpVdCSKh3kFpnPjlgqMEXYnIV5 NX3BonkN7hgd9EcTIpjTY65ZLe+6UQ0aIKVvSZ7yj52w6hLhE/fSxdFkjWLYMHY1Lmu9mxloN7dl rAbm3YvyfFA42rIxiXdAKKvXAijbCbcy8Nw+OsUYpLms9uvabUrXs56YFIdwmHgfdio+m/LM60eK UmjEu8W6rwTufWkIF0suYxz0B9SFs8FfgN3K7D8xHVqvuzzq+2TpQ7HKn2lChZbXzgcbiveYCeIu Xt5lmWtBMy722tz4qK6mLC4+Ct0e9Fa8S5cveL117voXwI7IwZjTdAChbwkaaQIF0Hj75u9Jplbd Fwob2DxBsnmZE0Pv4lLEfsekhbf6r+5gIMSEAwsfJLwMGRelSrPZNm13RnSUBZPM3Ijmm7n6Tw9U NO3Eu1vgMHyHbm9sLvvTIhi2J0N+ydtbP+5CbOGa2cur0BW0rRQtZBc90Mky41j37071bSqdZ2e2 HuO6hetMr0uXTK7ifpLD8WdNV/bAh+UQikWrUZAxzLtqvosYjDcVAK0ZVJHjGjxlELuInYcfiGBl pfsHsTePXpdDnfmuUt1lVh18vtcMIhZrs7pQPwe3B4ocMqpDe0Ca4DEEGnwmYOwanVlnwblAYfsv ZpQlGZhpq6Hz2zYxT4k+aq+p5e8bSQtK7mwtk/zBWIZEGHApAIMaBL3elpDb9pAMGzRvOOULVL+p EyHSLd7XX/CFOGU4LlctFVh4ZsG84qYEKNGYv5PMwCC4SUX/tDAvL5iLIN3HaufnfdQhxdUzkMYb LK8YJeBicZEfKBiax0nNXmavSaeQHJOvvSS09ThD12TmSqCjAwqrBeKnsWzf+V9G9dyE0jYaURES PE5KJaXK/NresWrRUUQtadzkFJRygoB1L/n/XWqyCXj1ufgWEEaATMJKDyv5KgX2D4x/f2wgpE5X KR9k935j1QOIu98iniG8kZX7O/BHRwFPKp/omWvXh5GsxwqrGzuq9U5IC2LsbyAwqHErTZFixm6x h+K4IGLthkuQhD0k6nGgv1iRawoedQecFhmL8HhX41kyvF+XnqxoNQ57zj8xCmYYaZRSqz/AfM8W O0RhKCtRDgZmUp1mgzui8fxsghdtO7CWG2/8qP4WP1qDE0aRaKnzO4X96VcbR4F37kPGiUG8/Sva 4+v5zwHwwHq9KmFRf/INf/v6amW8NZmJbXnmEzn/e/apuyVbq20KRh0RF035JXUD+QG6leQ7eTmf L0OyfMDI4HRTZdEB4LRLgs+aibfVJCaeBsfon5bzgqZcpsDoeEN/vf+mXvCaoaDslbQgHh+UlmVF vDeXis+BapQb54AmRG4Q7237vQrC38XiTvemvsLXqxORMVzFqsbtU9qXfaV0cnSYkih1gxaltAfD Zv/7c/T1bdq48wpV7OH8RIDpKys6nfJUPrQ0JmO+dhTC8nUARmLQkMAkCkkiOvaJVH8sKkRi0pcA /uM1m2dgSnt196kHrihg1qCCRY5xqySY4o9r7qDOLcwBcyO6ysPbnMzMypKbC0o9qXSxBpJBb6vK b52YOTcOMOD/Tabaw9e8935tF3lOEJwqL/JZSgQnhQFjyCVdBp4r5wUQ6vKcgUGMRmExIQWtaG+e U9coIWN/RGyCFWsPXnI/m7kUMwbtt/jkb5SN9njQ/IaPQUFpyHSrxgNjeTjTqHGuHHpB2tDdD+ia Pc9uuAmK2iEA80WtYplKqo9KUSiirYvHQeUMwL99jnaEuDDN0uPbY3h5v2tYjn8oWtZeEggZ/p9u wQduKz0/DsC15AdT0O2yUVJfOmDX1+XisQdKOay2HY8c2YKFhu5u0Y/hFi7nGjtdixToui8sr6/q M/ZWAYUUR13LcCBTkiTEARqJ39Cqfh618X5tAUfhvmdjhnQ6yudqne04XBYbSd535MiBRTLxkh0d DqKkcrGBgKm2gI60+PAX+yqmE+36gfioUhjnPgB8MWM27uqR2XjROE9exasjj1uBYv5tjVtsPrPS 012niNolfwVUd0Yc/UKjxQbmNY4rdPRZ5nmcoYZcsaNpr6+DOPqlbNCnfV4s9QNb5rlv/I+ZMgyg 6ppzjt/st4fwIlkI2PQQLVowgGifeAWSCk5usyC8pXe83/X684bw8uey8bauD5OGZ6qF7gaa86HV V9zVVGHHV+4/0rDVzgF5nHLr4XdzWVwT/KqaytjEuJ8yP9uGzfpfTNTTm4KhsaUzocPBOG525tYz IUCJkJwOnrF9IwcIABALjJHXOAAdr3bhpHx/iuZyVX/H4eo9pt1hUmJ+I7eR7zmTtX6IKFDqgWHm OZU2pXMeLVH2ik/T9wYJSE5IO3eWobnINZdl129AdTW03juLLfjW6syHEHitB1sCOy4e90py6z5D rHRsXz9UPcdCl1h5mH8jZ/XuLgZzADfoNi+v+Mzvftr4T/xreG58oX3Dpkp2onYFEZCJQaCgnS2t TFTr3qaqG0en49Y2DySerKpGi3P5kjH/7AMmjeio5s9/jz0IUTpXcsUOrk4TMW8uffBWV+OdBcF4 yA8wXOsLXSfZj1BMTKVr7z5L924ZodN57LLIKIRgkH87yGIehYuphhdQuMvyLUabehmX2xtVL17d DP++9uvziS2h1Feh4odwb06/Z5HfwjTCcEPR/LcPl6MiTeYYeLjvRbAtOAyulO3vPBLqE7iuMAKQ rqAPi2NxKtP8pmPlCvcHZ9vXoWb15AVvAGN15sq84A4sslSO+DOoWv7glq2Q27rZUQSTWSzY+p2Y TqCBm9qnk4pCS6Kk5nDmVHZCCEG8uSl+osiqdYwqNSuvVWbntBjOztTWrusG1Vd9Id4k4HoJZ/gJ 7nIcMg5LP5k88tHIKNnc3U/hK4LLudlWeaxvw07QraSgpHWYc484P5uukKQBSqocbyVLUdQGcOeR dC4WJ4Iiv++58VoHQ6TLRjzWU4vKz99TJ414G+wls6ryboNtSHn7hklhOLArU8UaL3jkHJ4MBYUB 5VvKlZZ7wxEsNXRGxnVLPvlH5b484yiYEVCIKCivENCpVs/4bR7ZP6BPeHbrJg9DC7iTeW/pjmkr juqnQpcg8+PpFGXoLwDx3EBM+moNxcyL5eTKrElxgUWSdUbsnBXzkpPW+4xchlkNfNnVvDnF8uWJ fdfXv8PkxMuQn3HyI7qwwQI9sU1yigWa7+qe0GBPDAKX+RCRlcUrIIkyERsMpZ8a1s5hSOSR4Ara AdgjCH3K7sX/Yr84+89BWXJQT7+rPCfcOfu7osuxltmKoLIirQdGddXqNUJLdmb6tnFH/MgMXBqw 42b2NSX4X8FAyfXiqneD2xQZ4BV8o53LJmyABsauweVz/jD0TzmJcu/bmu32j7wbuGDOQYMhPByo rs5Kh2aPoDz50PkNdiOrFxdxobxGUpFvzj+lKP+w5E8QkvQ18faw+tcH0WvL0vXlPwlaTqavn+Zx rdYrvuNAVThi8FWaCT2J63vr3f3CDixOTRRzINJzwj0EfzsA62uCMCYK4mdI67UsU4r2f5VzD7ca rUEcMdVtbQl6w0JiCVYGwjMQsmwdmEfh2jdCCDWqsU+loWOOd3Ad5FEeCthYotfLuBKyM852OGDu se7Ez1K0qhDoMdDGF88e+nJ3JCevz1JyttlCOipflH9BDwVyPGmHKkkRbUEWENKrxb4pDZj8A1rJ QSKkmoWgJlytBPlTTWhz87Dzt8kOA22CgubZui9+2FUyVLLXedml4ccAGMbduCEbcHAsFjylTsjZ mC9swomVTWAfay948hI0HWYGM43Jw6QkTnFMrw7ai6MvJWtxm6eXCwnAc2kAcVwbfw99SoIyZjZV +caciwRxRKv+uLWFshBwVyqj5kuvL3uuuu1PfSgHeNF0S0YeV5IwHZkeqgbR/LiEX+vqn/eomiXQ +h3ydxCeJjmh95eweJXvAX/bb7zdFBoKc+0OZ5s34ZkeE+EzpFNbL8c+w3T0Y3Jz0NAB93U/R/rm YBBdFbpctHODHEaDTkqu94kjGsNQOiohal7jF8525JxqIvCrfnHpQhK4RvdjszhR/U9Lp/H1/Ui1 MWVGGiouexUc/XgoLKySo32BUfhxJt50R/nJTQsmtSMANCepqcpk9xR4iLSzkM1Tco0LzKq2M+31 7iJdy/XWR/SVyVNPjD8yjojBxjBmf0gCodmhfkhJMeic9qo9JpwrJBY+/+UzI1G6V1C80aYbhpHS t6VNGI35UlWErfsgpmLEbACK8RGKVY02llBHVHJqlfv0zAhOzvgh+Bb5590xMihWRplMwK0Vi1R2 R15LOiIo5FMNW9g5jinzRTidDjLQ6f5LA6A41hAzdoAMf8BmwYrXsvQTDjRHEQG5BKyHwHmqorbr BjjBXdQkuXPbv1M7KoeiG0ETpvWXB++w3uMHe51a1OGjTEEaIP/5uQs0z8VnOCaeP6z65m8d23dH rNVCiVj3rPZmqHxNbcfjdY1mxljEUnT67QPkQBU/BFhXbXCQtwNNJ1fR4ddVUL/KkiEQX9ljNyJV bm92SS2LTAcC4BHJ7hI/qJIeDsVavxMtQxO1x3Hl/KaP5n2lclRU1N5QCLYXr0JbkAjqDaaOPADv tIYU6AjNAhXGyrGhboC5DyNmWzSyLpQlfdIrufij08OPvASzDse7swZ5af7uglSJYUAmClW3jqTW SckfmHL8J7aeeTVOKkFS8rnAypj3UfifSOWGzrQnd7KxXcNFt5dK4gvWCMaUfP1Teg+iajfGF9Wb Iwz0gkl8Ago4wkVcIwz2pdsa77iylNPpvZHmsefI5s5Ek2kZoL0AwKKueqIfvZ9AEbTRqSqfNy3n Gqp5E/K7Ljee0651X7cejXCCmmRt8fv6PbbqG8VT8ykxfcQD7W70DFJbWFdQarRc/MGoFVJCkKoi dSjb21CDqk7CFpD+q7IzAYVxqkd3OCcZq0CPpNas5srpsV59iAsi+YOPX5AiX4JwcqTitB4iYDAA JybuEbvt+Ohh6HtVe9mq3mCRg51xJXnwmmmi0M32ixgEbWtlATqIGejVYajl1ya3DBXDsxSIBmiD 1pcXpDiNA20yXKC2MAKeAJ3VCRQ9mpg1es9VW6ZHYklAgvucN09B3pV0RR/DsCr+YXJ6XnaVZExt 4OhPANXKb1tfK1vCuXtgnNXK/9JGYntdJxgzqvcwwyAMiC9Y0He1gYlbMsAUxi0/TmZ3mxQMz34t xADJ/OfdDfL5RPtagLebZlYPlJ/Mm16iPLC/53q4oi1pCP4oHRoUXNwOpFU0j7BsAywyXf0mAR/F oa7R6rYTYp+up6yBU96X86CgGp73j/AY25OW6NEq4NpLU+9PyCcmRmwCOIo5O0WCInc8phGoSMWb b2752sFfqqlCYKckmm+kCSF1oOUiDj1DRBFd/NhDIKleqNavgHL1Ld8bWwhr8a4kuprV/PBZuzVy SCWBxiTI0zMzon0wRpeyMpms9Cvr8dZdHDeQuMgEgat27EF+EEk7sFUBLlEwU2yhsIctnBl/2ir3 mwhcUALI7mqxVF5iUuvjhkQ0uBqw/0jZgUzpNivWVGmLpYO6b5/c1jgjfGepwURDfVUPmba9KiK6 9zylLCCOY4bABbaa4T8X/NnU5lW6bijYLmkY36u0G8omyioPAHdu+AtScG96LOpq+AIo11h3FS90 QHsgR44jPXG9Nu9Iealsc5t7r88L+1EhhaStDRLskzxoQuNMHyMRC3y3UzlDBiOz3bqEYgyZ1ZTd GYtmOKGhykK77o/RgRWrbn4GvLzgogLak1e40c/ss+2DaxPux9dCWEKTTiL9OYoUJFL5VuYrVKTs GFpEaCIKnYqVuhmIWLIxQaAAYqdGuHMhYAK3Y8SyPPw6WOm0E3/aImUmk3R/x278mW35bKOFtR1O P3oNBuTOQeZaO/sLYoLFaMuNKnLdvDdZ/6is4F9AGUWLHNiAny86KMud0K7Ar0WI/e+xrAz09qjQ OyymFgW0iwjzefvWhH4J1ysZs16AAiams0T0zisKUh6yVq4rIEhXzreCs9YCrKOUDPwpabB4vI3f 8Qdk/v0ewiOKa7pRX0f1CXll8s/NS7u76FP1Ai/uydwf7SVAZ/B8/HHXDDhryDPAh/pWlyGS6o/p zhb50GqrNJG3qQP2dstys8epPD5/5AqqJpKWsdxoLDq38TTWBxSqTHrk3jI70jPiL2iQLnzcceA+ Y00RPZOIauxCpraE4IPfPKvJhzXxR1V44/+G1lt+J74pOv3Ze3lQ0x/bgDo7rrRbZizCRLsU0EeL ATmyoaFrCYMxJxTNWNAJBtgm4yBllF8I7bAkRlx/5QLg33LEYTiVoLJuksZOvZavW47/CpUoojl1 4pzbJvrUJqOaLoquE90bEv8o6aFydvNechilmPIFxsQkrCr7O6qlNUj7eaPHyQoA4IlyphTOYQ8t gd+jt2lmZ3ABCswRFgvn1M0J93XiMZTZkuNnu+aO2tlWgEy9rItVi9hQrtSa0BDnOtV9fy5/wQFf xxEZgsiknZ8hsLYX4jMwsfSpgOWREVSmOBCCRtRku7G2YUs/TpuurVvfvyGL6S89fQ88m5LpOyNH U/+GmaxUiwv2Gdff8h0AkU6NlXiHtOsrx4lzT7+9nD1ry3I0+dnJPTvLH18eRDUWe1hCVdoZZvjx dJ3K2HX3ZQgEsFTVg1YgH0lI5arGRIPfo7kXUZDWhiCKJBdBjcnRY0+vc+F5rLIOKqQ0exG7ETyz k6ZLgxGnBP2YZrlDbWtQ3xV5l1JKZQLrhgOS57AnVWAnNN2PNVzqLM75o5f/+PaFrVy0ryLUk9SH T4scCiQkh0GlyeZbBd3O1V+Awg7/IxeBl0XJWHcZ2489dgwpJrNEzzHHUtdbsPejCYYJ6TyStPq0 XHvIgDIIBrnf1qjLyqixVbVbUKxvW1KpH5ZauzVzBKs9jl8Rk34tQSA/d2ukLdvOPWFX+lnhL3W8 WGZyw2aTri5S6hLiEVwnwlq+MKUBnqcmXPc9c1b0xODpodrrwhG/N4W3M0pgwZEs/sYPsERFiN3L BJ4iZRQvaxs6g8BW5G3U8ZzvoAlulT1njLK8/pvczxZ+SGUTjwAzzpvraFbl71G+GavtfbNIBtxP QYfqugBna8cXWuOsoawooQpf3o17sZnqSo5k3c2NM7xeUWgzyLl/ooR+g4oxlAvR8LNH9Aa43tTE NYD+L2QaFZW7I3+qajQeV2BaWofegg/mjwnUa3U/7lD+f9snHAT3+3GiH60DWC3sFAAicif9SlJu PKUzdo3YtUt1BjCzzSrTTCsFJfZEVp9s19vhdsu4g1Md8oxGaebstb6tRM/WB2jLQUCCHSifRPFo vGXj9Ogl5dh34xnfoADIzbUcwkcM/xVURYVSPhJoMkDtCy5b0nhfRqqLUk11xKLHqzpjUPYIsSkV 5lzdvTlHNJfKgLNa+z/jV7mjgflJeHZspt/5teexEFDdCiGfbGSSCZZQbDtLuZqd01Up3IuaH8E/ eAZe5fk4L25z1LRDS2/eIsH0YQFNTINdme1NBqRw6/9OOjrO4tTKQcObZc1X6V/3pclTnFA1Tc4s GeA2sMCIh6W0+KtQBsLD3LnHksv+4lTrGpiI24ijU77SimTx4DiJ7Suhcmz+veq8wviLuwM8JIo1 rp0cvFHUFCtziuClmPh0gZLjnZqpASsiPjtCr5N7ibFCRVni5qMUiCp2EOyiWyjG/2cYWlwjYlId CkJaya5F62nQfANXkj87dSO0DceaCAJXysnjMZLHd3O0LJMRvfBTll1TvyIQ7uO3BiwJu4Ci1TUY uBzmpTYOhm1nGXP3QcORzsWpFnHZWd/gGwPgX0nNaqwfx0/SdfE3drHORSUO++uuwcNFweYPpqfE 0tCIArT0YWvBH2MaElo0IzWnHJksurv5mW1zB+1B/gyn/QH4Mttm2QgegQyyZduizQlOvttL21k7 n34FJJBFRbRHpHlG0ORN9bLKoMhXCkHNR/FP8iqKKpsMp1Il//u+EfMCQ3PrIkmIlo3xpZm6yeEP aIkA3mLIUtFueugO7h/M7mDsFx1Vk/1JgOoEZc1nn8fQmU81FrqdhFz1wGM8Mlp181OTybIQWDuB iqp1MXTIOiREV9SBAWJYmZ67geBoALPq8iAvItYEOGZ3RVXf5XmEbkypLTAZciwqjNJ1rh+LQTj0 TKJA0UlvTOHgVxu7NYe/2AhYt9lzrfjsLy6nMVlTVMIA2EyBBrZjmkxUbqMO8dXdAY8UkzwcumC7 exy9QKzeDecbeSigZWyjXzKolj7OQPm6SkzwsE4YC7CdwXtqDh9Rx0Q4oXZWK9K8g/zzYCbXbtKR bDynazjbX8Y3sBitjHZRY0Zv6mnWdh8GJjxG0RpCXjDN74xVVbhAbUJzlyxvdlcc03KcVUaViIYj E+4H2L7oWGCPVLxh/YH6kegyYjFkIx7BIk+2N6nVSEkFen7Qu8n6EcTrSizvsDhyDwhiJnStrgOP G6z2FrfO5ujgOvu95QTFIaXpvSTLZ8ENDgO7iaUfHfL2qjHhr/ryaFWhgW23NsdzamTHimntPAsc j7wOj1wrAeMrdp7P94HORwsutfW1/oiyATxGgetete2bcHtOA9jcm018jblM+CtmR8qmAr1fihMU GkGQyr2HyMBllyqRAQ5bcyWNGreP72kYOTUwzYGsdFswAolMagS74ayf4meF+79H8iIo9tsyfrjB w+6RRQzRdVZb7KPztSQ4zLWoniHUBXCwq5LdOP6xP4XCaGdUrrhJmYQZUl0VXVAHJoWzQRPAzNK0 JYjI3RklpkWAOHhYUw1nefYPONS+7rBA8DiMTriCJvA/q3OXOhO0JSUfBPxlDfYgvERJoconfge+ KPfwPyfzq57zC2YLduEBth/WV0MWvB4WBtAcJwH3eqk9kG7pd92wSgdwWHORcUPg9mME9gGm8Utb trXIigBSXP1gBHtvlJQD/zHqFxt+D/Qxfipsf6F6hDKWn7dw9uS2uULQY+vPJZlmUuJMuHhhZXFh iRLWaxGnX0MTHBDUH7GIrT6gFjaLNISofcaS1wSeHz8l/KG/TVsecln+r12GRSysz+rNth/qkxMi AmVgOmN1CYTu5iyAWjZzPPzdD8GE9RlWgJbwiuXMKrXER5QcBTZvVs0ZNqyFJ3OBqMjH/PawNb7c SftGWjp6gXtqgK14hMHSekbYZJdag1XNG+Mc+CQP+kmUsVi4HL2FeloGrGVD9MUpvvgeKCRdgL71 5mbnseczAPXWg9t6nElKJrA1HTBYS8UceXA4LfQlY48V/Vag8OyShcBPREfdMFjgsp5TBFPaDQvd 9OrpPMdeu8av8EgYLS0avMz8X1Stfk9If/it8G0nMkgbgsuClWSTU7H4onFdPRCwwn/hWFC5nfmd 1CSCN3yl6BnezDHJ9kp/l0NngCjbBICwRhodrIQwIIEMirUNdq6USuuRYdKHEgquewNOmRR7Et8s 2ua+4Byofcdbr2tPnPdtrJhVFIgEa+ggEbMWo4rLPxxGn2bUabsr2rFXs2Vk/Kob7b54+mUoycXl jGiq96fFj22hxtYol4btzNmTMOQHbbqCLb1eQQxHfYgaQm8tEMRmIq3c/o8XPzVrPG8ITwfkKH59 WgTBLzV8OxN8VDzcrJk6EPfFIhnLfRavnaE4RJ3tQLrDpbvmCM/+6iVfiTcBG/drPrJ4HSg9FwB5 lltvRa6pGL3Sj1mkT/QHgHuEMi1lK558p16M/UVGkCrLPgVLadIUQvheRNF1g5aFKANe6X0fkpjm M97WCFVH2iMOozMeCHC422N2X2kJ1HvYazVTrh3RvD5hNj9z2HUfuQhQr0VmHxgj/8WWjhf7fiem qoP+WWsh13ql06sQk8dLKzuiPxzITS0oFgtVifR2zz5+JZidOxHLLlVVNUpJyN8UQzMTcM1ap2QR m+pH+gUndcPGn2uUfT1rvRvZvo/SQnDMvb4aMXEiSar2iLZ2FtizVUf+ZS3MWV24ZpZ7aJy0q1ui KVpsRF10MaLOGbz3VinWxFtvJZjnwve2hTlfIUSjic7T4FeiZs8zRk98lHbqDJCp7V7zvk2SoMdR zs3X3KsSLkR9FaEW5hf1UamaVaG8OxaJuMb1uZ+Uk05uz0E//h3Qs2PL7UV9vezKO0MDT1HM/1ZY 4gUItr8crYAXVAf5cOvvUx7vSqaMWwP39s4RjhVAh2hjQEktJb340MY3L5FEOxc19ccZMM9JWYBU giru9d44EneDF3mUJBbwtz7ybc7Ni33Rq9CA9sGhPb970wiGoRa1djpw2H7oNA6iK72ZQIdhIXVk AFWeLt98I/EH/SwgysZaTZ9Ccm55eAJ+Ljo6QBc63civ/RcTMdEUQjgMI/5vZ6auTJqVDSfTDTH/ iQb1PjJTmGXSkinBiJAh8I7axjK+vwTfBucdQtqxcGvZ5emhs2V7sLXiXpwRyIHAVd+uLYGV5giO yJ6MCY23RA+BbPPfuaY+bhYJ0qknBTA/WT80s+O7lzghtVodqFwegf73m3iC84yjAkQhS6zWJv5n bW5Jm6+5jsxCyMww0Gzn0ujBvDD2KDntfW6P/rtN1hypR82RzTEDRjeqA3NK0Lc8nUH0yZDip+QW dyMglSN/LAYhFEy1b/P5vSb8EDCDIRl+kXMgxGPOIrNPqKP98U34XU+10o8C07CbZBz7eNqdppUo 6y1CC0HX4aWng5ezkGFxi3sEU580RZhKQL+XlhF8a6bItcFXmYdUP+nLUEttIrMb7j2mGV254tZT wqvTio0Hcc5zsP2U+Z5dwvBXXB1Ar3LrEor5G9bzNZbGpYUQbqYHyEMMC4xlnr05Umz8Q3Kf33fb nnkfcm/NKUAzoRYw817akqXyW82RP0Gu9SkbvF50RIN/uywgLdu7lI15oLZABG5OwNt8yjhq1tXY wAHge6ZSRTIRjqdIDSrQUaSWIDUmlNspYGqEQoqBcDEq/MJacmXnesU4ym1lGIm4l7YTszSf8jmk A5Eniv4q7nkqZq017JRKmmdX3TGKXHdB81Lyi4f/Co+mGex59S0BBQm/bCRrz3KF8tAUwTuz2S+H pRlQZCnK+fsKs1YY63ggvEIXq2UHSgFPG+Mw2oJekHGI9lzrq+xizljPjVSecV3m4y8RYZLXB5m/ FI47WWB0Dj0rnlzV3Z7ZEcVMWOprbYKyvDYwXQmDND10mAFrg5il4gUYoDgCfRFTQbnUrVlXa6sS znZaojwPsYiASSn697v8PcAUi3T7VipsSPwpwBkH+5IUdm/bLJvedk+CM0yHQHVG0LJ59+8TbWUU 6CmAcMiROcEw1VweQJiiEJ0Lw43vUBwikZm6tDpkXA0BN+YyaclMZ0pyZ9x63R8pmLQIza2MFaF3 QRD3nei1Nhcp3jnM1uDjyet27waDtUnMLXW4YWIlzBkAh8Vc40f1ICMb9c68IZ8Bwas1s82iczgl nou3nR5dAkUk1kf4AZYM2a3OH/0u55dLxq+5ZQfc4bO396DvoN3sZo0GKrM+Rnd/Yvwg/FaOPxxU c2MzTppfWhIVOOToc+FkPpinlJzSqfNbCDGlP/JXCfbAWckHfETFxf6jUvYRuxlCLTiuPUjHNpca wM4yOe6eaY9TnwqrMCAtkMIH4JUU95ctbvtKw5qhTInLM5JwmuJWiOl2pODuRqaHMjXonRDizduz +ZhYPfzR1DuqJGJIRWJbRsq0R1qsiqDvpLaVz+jt2GtGTI5yJaEbxqzFDumTZsGPsbeP8FM1mV1n g/t5JCKYmKnBvnMYPQmYT7I8Wv8VWyvs3Grs6iDVcIF87ZB2bBuRL9wOuvSkp//Z8Lf4jeThN6eJ m/2cKgDFvzRzCO/nz7toVzK0eI7b+UB1MosdJCYrQ22MZtpTsSsU/Q1xZ7EJBakQM8L1h/QnK4xy plShonTqL+12FfKZjh4kY3/5DN4XgKkEDmcYigC1YyzBBCZt4K/uwc/ZrllOhdNy+fxthZWkwQ8T vg1kyhF0/nluSrlI36BWNYbzLa7XQZpX0oeyLelj7+zfTNHjXgFcBTPolGW1x/HH2Hq8i5pP8HCk WSxNqpYik+vLWg/mjh0ogewLZj2rs5kxG9VXPIHmDE05PrfADX/kXFymxJgiTqXkGuNNhbKUQVp7 rIC4dBqifb69MgAUZTXIaURj2O9zS495eeFhSlJQEhuvrGYP4+2UDTs1o4+bTkqdJqr8pqcHKCxv cN6RmFbmBBB0BRaiTsoGRtGZyE3P88Tdvei0H+Qu2PNMy9gGx0IEqX4rFMzyuyPnv/6ZGNyU8Z/z cPhS/5NIn7HYw5ypI1Rs9SB4CjLljqF8uYyP3+5hLOoNwP7QmU6OeUdXvYLi9J2lETJlETU3MV2A ooowbBol3ZDNIZ44+vcAhIM0dQtiskZg6KuAv233AJ1xglXymWzI5mMqtG7sHS4SyRi81EFbQVFa 9dtPMd+fK7fswfYtfZuSUw72swPQefuAbyf7daivZFLug3phZbZbfYNDP9P1M+oATu2rHpxU+1y5 Bj4JWCAYtvXgag3g0SR0xjEj0yOuqPEnOZdmYSNmmO5YgNNGZDaGaujweJJpExyTDzgkqRMURh+6 mlvl6cXGmF2wnbHX/xk5Ktfq9W3oCa8JzidDklBjeyimXorJ78eh00zEb7gfQYBz2u1F4tlpAChY DvTuPL3ayX/+yUs1gPrtI6r0yddf3FybJVJaSZmGwwgVz69euxxtUR87FKQvBmnAEIjfQm6rAmpt q3FnD3OGQP6mRqygYdQf0+Zlljbc9h9nxtn51YpdJtbBg5SEmbvAR7QI4fC8k1a1ieujFdrCRssB VzP9JPDyvEHGuIwDiMRZb17eRsW+3E3i/HR0d8kXN4FCdjFcw1gOK3zi3XV3qbuhTC5SlF7aM1tr xqp9aTOJ/Z0s/OHAGpYfwp5lMH2kNrdpHPwQKmyGAiVEu/ZIXN/qnwZCNDZvFkZDiwrhwkoKzSy4 Wk/O6OGvCrGT567bdrvWtcp0OIgzmMWxytzkZV8UEoRffejXjzr3aEg7i5F/nocz0GdLXOLl3kcM FaLV6Io6oMllfPpbOImMyfNRlCvl3QaCvEM8RirreuZFLAaLB2MgOlKd3ZuSbSZk/7ERks1jTjMp 0JwsqtHXOrzyuCCnXvtTpXiQibXYH9KEiq40EfDNQHZAEbG1DabeaXHwQgAzZI1+lzrTZbyIV6zi lxlmHYVPJJqg9LbxEEYs5GOAU9QESTWl4Mm60BpDTGARDMIQoNxn+cr+WDPG+/SEy8zJ7YHEioCU O7M1hvv5dVmCF4ugPcme5Y64+r8Q9R10R3CbwJPpucc4YRRFLKyIVdHzjPHY9h4KmXsn935GwQsQ ApOsvN+l8N6cPFrIkkPfsyhO/FvuUAEcWA3+fnK2ce4BNdoF7BaygfpunSTLd8yLoa1fdy0HKeO+ QC8IyS7iUaAo9nIW1idELF8YySlePNQdAZvr7Bxklfeqao6ynLAGZCJl4uYmEQne6LAco/7ro14d HvbSRG1NoNepBzzJ1vikJvGa6PqX/ascmuuPBPt10odborUcoDeUcy0s2SLkUkG5W5/uE9v3IT/5 +8TVhJk13ak7WzUYlb7yEJ17bEsxI4+o1MJg1qxs7mtxlSVKDfJBSloFpef+MQ2EDiFnsTDhUm3z Sh6YNROEL7UbDiH6/bZe3X7pbp6hW+r6omNgMZRCjOUZvMCHZvV7hmMQu6XTy2gTFjyM+UHqXvgr Oc857GrTrbNFtdbwI3zlYLKYcO9+xVczugmlLd9mQcQkRefvJkNfzG4RabkF5fisqx7tddrxtS/k qF4m97C1Riga+mKQaf+5RMEY4GQ0tsxsNc2LFeQlgP+vmKYwxQLy3tB0Glj0g9tiya2lrIoidzeS AbfT55nxuTIvrhKkyI0v7lVz84IkEi0ry9MmhocNO4xogL6/9WU6C1rVXyiMg9o3dVn3rcj/7hhr 66TgONZwod3ozWWV4OGKhWGB3XT+1L9d/83QmLvcc23hR0B/qf0sCwgMphL+SWACv1B7DE3hFJ7A UBCEFjsAS7WGpebDgWdIpKy1SZIoE2yQLg4TwOh6kvpK1HaoKSVvEjzp1ztMhMCGH8WKiVbMiHnh /6XWn3RnjQOu3+HQBveS+cdC0Hp00QEYdwOPWp5maZyB/alJhERzA/uvnSrRIIMF7x/0RTNMUXAs XKa06eqNqmauaHTlo304/DmjO+Mby1v99pr4+eoFF6wqYDK2gnHOUcmbZOXs9D9OvIhjwE/GQVAi GpjFIOsZCYxyXnvaNGiUm/CN/0pZIOkkmXauKRbyzImaKU+B/TKBiPoPCJlkT/tq46Zapwf/8+iy OKFTLWhXZYmuZ0vvJZP+e83z5ss4Djbf7ifHk8Jt8oBLCi4FO+Q4eQxC4hP7F7E+2KIy1hH02Wa+ F2abnY78wbzJ+SiMb7uX2Gl8V6WICp8nntBrv79EC0MoEKLw6Ynp/5Ed+Mz+te6Og25ZaPV+QVY6 6oS4xlr/+37XP3/6x5qHS/TWNPcve1Z6xXMshDnYIg0PcoMGW+BJbBwonm7CIUUGY0RiS8xAUbe0 v+NkMIZsJz2h8mPAGXlJ9ymgoPgTDTHvHTvVJeuEoUms3mXLh5v1CBjgeWWm/KjKyIK42NK5cdCI jufojDJFXJmR0i5S4V21CprOMNzoQ29ltgCt9OuFtjtEnhO67w9KL96IoFzT+Rw4HzPDAeXUq+QE v1Va2qFAo5cRXSn7qw2xZ3x1wpns3FpAJcTgCh5WlFm8Ga6M5vadDKmARAmcgazRn8dAahRJvzI4 UzUWLTjj5FM35r6mePYO136Tmo9nuHdj4eKzjePAac2zyQhgM5MEopw70e5n5GLzuhFpYiUT1Zrh yY5WcIlArdfxwnExueuJGqXGvImPtXDFsJQO/sLAu/2pmqkPpjP56aGcjcT7WG6LHi/SFtmilsy6 TCHBMS+3J21Vjo2AsOWcCdoo+/gB0XB1QpCEQPbJs+QDYz2r52NxQv5VQWsbRZHoiTLXTK6oOv2d h3w9WpTM9UvQbytsN9yD0Gb7cqKluqcneUG5/ZIjHQzvBDAJB4mLuntihIZEQ3NbNjD3a+pwyhTz IsAtL4mYkkWbYJuaqkPj5MfzhhLYWGe97Vvsf94o/xuoC+pE26aNCmUtPFWemoOjt06dZdMAZkaS gHDTWgLBJrtjmeWsdkBgK+E4pPezwLV/I1Snxg0k1wLq+2QQFbBHKUo0lq2uSsuCTW3LhF/LBi0l dzad+VaUKoLUpXgG79nMyxtZ16fDu8qJsZAAbQJrv1Wj8yuEMSGn5j2j3SmdHCwpcWXuMo4AAENE MmcFX6VF/SenSgxkI7B6zU6TjJ3UH/M6ZHk6fjfBkansOaywZHoaiqkJfmp+f/s+Uog6GFWMOtk9 f9WCTn7ZQMYM1t8LVnFzf6upp45RxspmXDeOivn7lKnXXd9gTtHIqU22l5qQB2sqAJeYKBUhf2LO WenbXrEnRBsxElJVUELuZMFzGdrgJPSTrqujoXrGA9/mLTtQkS0xFCBEURAZk701Rgz2LyTatnNP XAjQwKZ8wR4uvv5IUV9WgfeJwa4vwE3jzG9+8Wi4NZ0KhlsdThMU++r5uEtFS29bpjo0HaChVkVo Irm9fs19YPwcnasWwieXxaE+ZEOTz06ZY72pbm4zMbVouTrFKkwFWtHArxuGVzjk4goNiK/ASxNd DlITsGbDZCzqnL5eqSsSF7+RGn4XwRZ+1ccOlx4AighPV1MfokXk8FtQXzo3A27nsAwdTkKBCsII qUlmAJyOTf6kRwhvazeIlgGpD7BDEa/EI0AYqWhGplM/jcBf+aMf8PsGXQVfDgZhQCdRbZjo3mkH 4YZI+w1myJuz5rQ/Ql3pDoYL2KtUdhTiiu+8u+Iala15nGB2TVz5tyssaZ0INzMl3WQlWpzNheDz tVuci401lmzROUaAv46F64AVZRhwjYqJMMUhM00qq1Nxgyu1SDHO6XCmc78kqLv6/pZIMA0SVLVz braceTN56CIbgdxiWLpF1vtrLHuk8KymsNpip17PM0XkwdTVnSM5jySusj+KyDbbA0ncB+VR2Wat HB+hjB8jULVH1YPY6oDDokY31BVStKJDHyPuqQef6Z592M/OAtU9mhjFm5zPCFIofjkn7FNYGz7W bbjec9okfX2Kg0djBzn60B7A9B3F6IbQGJhdP+FtXlXcsmoFPKqWEDU5ntI5wMcsSyURRJp8bXC0 8jh/Vfd4hjlgU9YJ+5OmYZL/9sdXNBjlfwgmDCQL7A5v+evZnZ/QLTS8BoePJwVbJ73QVAwHuaHG hMtbwxWVYuK/qy0fvQJ8Lv+yEBySUt7+oEsbwkd21CjJ0WOmzueumXTyJ3LbReILqG43h+pH5g4y n2xeycUbgKRQtNvsHw2U5kX69zfNssIU4mlRcWeap0RPkgIn5+hscgfqNzZb8eP1DtDSjT/qYjtt /nBnCZ8UrDSYkxRwDnwwQU3+Au3zrS0rv/IUwGST6dP7J15tE4xUoa7ypzh9LnYWtP6l8ZPEV5J+ KRBzdepNAE0rWAA+Qw51OE3yYaiWAjbKezGJm1//IPSXzN+YTiEQ0sscyisGNmb4dKcVK0UWuvPk UZ6gebXhDyckZyEkH+2X+PZImJZrSGzaYdxvdgu7lOoI+Re3gut815wPCTsJr3TzNegpXED/UPBc aLg576tF1QxTgExEOe89ERbenkN2d9jo5Acz1yGwn252iaejniGlSILooklGMtiCvq4/aAU/XIpE SgXzQxd49Ld4Dx5JDum9aOjXC7mDDyaPaa42BrjlUUk5O6mgSYGvsIpV7COcWaJyRy7wP8T8/U9E t/9OjVnRN/Q7/R81HOKJ3pEP/mmtQNEDoge6C/NcpxNbV8MIMPRtCGUsSrH3giTdEWhC7RpC9Zu0 MwIs0uB88XLhXLYpduxb9dO5tIwTRjPoEd/hGCTAbul8/ugVt4I/E5ZoR1eMWE//vbZMbXLAZlpq BUWB0ZlOEkeZAmu9aLNdgt5hcyrwagor8V/ckILh+0aKIy9jci8LTcHs9ixVCuaum/sj5kE32sgH 06Fpo+PtDboMRjWByc7ZEGUwUn4BL7hfit7gXU654PUHSp81lfdZY4bU0JIthibEDVmKD/yv7L7a U8KUMzpUJFqk6795lwVLnjYYo/j5spkxVRZfKSL26iwA2PAh5VIIoCStuKW+55+WUesPTi5Cr/gy Ytq0MYdLAo4vod17Dp91Hxk2Xlb9heagAN4brKwgUTM3zzdzWEgt9TgQMdGSUZ7sAemFd8fhBy60 ygtqbgN30tZ3j3xklycjfssY/F3v6lUJc2Yt8k87iQV9zcuqFIl6SWM22rr0IoDlfncfE/v+beDf zLHYWFDXGU/U+YKc/rEogjjny4idEZxpjsxAfTaQQsIHIv6QbbVkdpiKQeTtohRukweAzM+7pgRL 7Kz0NvStO6TcZy39UvsQR0MKe1DTrt8o3Vvu1A78P+RHHalQySLPzu5r18VKrdVuLqRM0SVNFV7r Q4e8FbWRpKcLN8K/uYwOuyzhqclZ7Z632Unbvs9n6O+hEkrmFtfsnUlMw4yHF+ZTJixV8HrC3Ey+ 1IFM6splvSotrhUDa3EwKKWeRYF4ZD311lUjPrfaN0dLaf4+ETDnhyJHx95CmujBFftZGVDY5Va6 yhJwRzJZuCH1dt+c5f3iiJ75uu9vHv837rjCGyMcz0DCqcBAneg7LbTlpCmsLuVcSyERUnohbYKp mPgJ1xesvxDS6951ZIE0+YY3zkfZlYYYVNG2bJW90gnw6usN72jZEIJPCJflLRd+43ZLl58NIBEU +auuTsJUYpqmf0Bt/udJqsGWH8L53kiVvFq/RrbNqi76zPre0DOxT/8TWAPfpMbS3DAUSfPI33fv 4qcVdGzNKbiYRZrgYRsNMJvNZl7QiNR8k/tXVdEsO11A2QS8T7POYOU2/+AAw1Y71JTFcYddHU/Z tzwCNpDGK/3gog+HZYPvJT9DlOFW5JER1y1+4XiAilPWuCuXld6Usz9cC4XYQNFZF6UgjCAtTrVZ Bjg9R2eCP6F2Qrik1G8sVey8ChKpfnFXHjF7ex0HN1Q9K6TJ8tAthm/BnTtbXr9+oaz79oMZrCYy tcRJ+49Lo72bppRwA3cqvjcZV7r0ZTSctSFTi29CBIgNqTwQWL1+XPqO+TtZOdam0PqfkM+0m8CT XlITwd3IfJiK2nh5GPdmT3nedA9mygrr1Z/kLQ5uDpfVZIhs+wGDTGVsDFQa3f5/5ehZgnfYm4Ki eYyM4CaswVZrVD7FlenlsN91UvDgMrhK2r7NACgUcVSd6lS3yHvaS4B1jUJF6PntzEh6my/oHQPh pchyM9Bm/yNTlEFstOP05JM7zgu9E6T4Tj+QJFN5y2URPx+Kf7dr2jpf/0gVE9bffMBDLs5ks6hd HuIm3HnCgp2ycg4OVaCcYAdT4xD2R25W/4AjCYRuoQRagHpD8eBEtCaiQnqibCM+GoP5V2mO04YV f65uqJ2doccPtY/3iT785u6doo8f6Wv7UnSu8vNmdLM0fBC99+Ir+enFgiUogLbJlhhUnFDpsxb6 vKxBVnHs8mqMnpf4bA148gBTG93gCyfJXORKZKdDSGZScbPRZmrmGY7o1NtICrsx2hLaYJWk56Rl l718TCv6f8FSCz4Q+Aq3AkLo49FbULxUgct3seyprjjUGiFJTlv1RYNTcHUuJ4pE2pVkVFzFzuOz 38OduQ7JyeZaNYy7i0x0tdCa2TXdcy8jYV8FTGbgem/5nkqhPfwfL3xQyp3oVMlU4KYHNLR4qM+5 JsFl5BFsC5S1ST5oquMRqVdzKyLTWtKyJBr/v5cRAo5PGJTw2XSaeu0CasGRrs3tHtzeaFopaDu2 jHZsG+FY/VOynu/3DKWU6Jk6eKBj5gaFRWQsU8Ix5qq83OOsgq0ey2Qj3MsHy09Smg6+l21TzQ12 hhTxiNfu1/fejeu5fu4EHRC0C3GdesXVJusFUkIi2MKHkOkWwZT/6CG225rNigSF1xP7Hu1u3L+7 wX52hzf5b4xTERxTPWPM0K1vxlXGOr7Pglqu4uiZOToMUqMIoQ+YnQPqsN2wJEwlZWmp7+AOYI6E cmYwVScuGY+tzuxRiJN/Xt4annDiazzLSM88LXT0JjeMw7hHQgWIgmdKbfbCvt28Q686Al2mH8JD I388rI6joBoHF7WI0KRAmb3vZKU4hUKE2qc+ndghuKwxlPp/3/JVhkpp0fdZ70SOv64AH28Q5roI OShF1mRF59xbhstoLh1tyY7oCPlsZDvjpZlHkqBDiGibvwh3+wKFiVTCVizPTP+WSm4LkMZ0Kb4C MaxNcpzrO6ia9IAzyOWMymWLt9qqfiZZzmkeWVBzqiwbEN9t4NtxXe94fMNQabLo9sX1Si8WmjSI uV1184fG0StOhE2HDpplku8eMG08CGinIfICqqCdMn1nj9IHI32SsMQt/zv7MHcsrU8qfvoSsyfH ljBf3rl6/5onQ6GwtyODRSuPYcakMDQee0EJE2ntuW7RJZb0fCxxDAwsZS1rlfbSS4ZRaHM3lWQd tF0y5I16HOjdSso0zUCQm/WTXG5BTwcdOIhgDcJJfVAdZ4RNTpe98VRaUeEC8w5Cx0gRB+LJkVg2 df3brqnEsPh8MM/PJIoAUAFPHXOGJvh/Z+1Lx5iPfB7xOfC8oVTdgsqynxHD7VXuS46m7pl6EpfC ZuruZdCARKm9CDiDEtVK9KPbxjUwoIXk2WMeRNwxakn6hvSRqzt22kFifJhaov0MxYGPSkmXGPPb aZ8DxMxb9QSHypIc8i9XwMMtUn//MY/uPSfk1aKE1XA7VLOflVjL8+8GeNdC6aWClOa4o3ylfLeF 1uDXFZr2pcd+1NTOdbQMdj9QHWhLo02WqldNFF9LznEFkjdY6xbJbnW53lQ/cMycxulyWRklxKLm 4qkxXbu8RXj+HkA/QdrRDrBGZ//9Np4Zzx5ChwpVH5mEYVBQxaQXBDQcHE13AV3dw8PK5j+0wior NciCmnBTOf0JqV14yCTw2bJk3fg3CNzVLiEJ3TsEuSuCsv42ITXoWgc8ZOsap9Bba1fdFWH5yC8f /MYXtx9MhhRnE7Tgw3K0SJfVe0JrBl6ZyyaXbUvJfGISoWBV2KiWUzp+yFhSakp+U84Dsaw3NY0L C+JYn0BAgaNbNl9qwDLxBk97I4/0wJBvAsfvH1+koV/bAwzDEtUxFnf/Is85S8RuJh3/thbvyV8v nphr6RF3o6mTAzzPPFLG383LR4TsUv0Urf0uunzWjX0h/t7BUjBUbGl84XB/yhfDZEDiLJb57wVD YwDzT/m+OSdXEswz2qI/4VYTk5uObQvr3Ho0fESR29nQrpFGgYsMYlfjZN+BkQaNBVBZkdrW/wAQ QUNHBfkgxZBGP2crPVV8lv4FBnpiyf24fVrP79w+HD8ZnH76K9GG8Zp8GGK0/EPGM9HkwiY5ykph q3xeHApVTyMkAkP9vY6Z5kRYOj1FHBBp4aiKBLGmnLLPlaM4zSACcN/C/FPxHtth1CC9/upZQyO7 ZKRU2pgNQXhPJ4w4kNxVbJGafvmDgjCcNZv76QE/WKDtZvATaqARf8GDfeB1myHh/pW5Q6p4MuTN yKOReqmyDyF4dVgQ2GcRRo+k+dbrTTQioRwf5TapyoDb1XSNQqFsErlN38qbPO4ZacsnSoIM/QoY 1au2u3zLdEIUZJIrt/syY9M8f28NZ53TLyUNIVEvyYTxXQ3F4imilQVS4zYxy9vsIo9ItnKOV3lD fE1FhyRz4YCiY4GRy+k6h11o7oqiT3hGUdrAxnq7hYf6MeJG+5UPAJZdR7heTkrYlV3UaSzdAiR1 Gfxs78RN+7Ofn+SBE5XLVkOH0einpGxNGpOricXliTzv1ogmW14rYscWlK+NFuzU2o2R28If2OJn ecRzdk9b4Vh4YT0GS0rNcUnlqrKp8q3scmBvCC8YZuZIruo6qunW0KQo8MGxcw1oGswKPmsJDeX1 0JhZyzrF6+BLYMRoeu1p6JQOzn/wfEFZWw/c0rimwe8HN8+jBvpWa5t0LsVREUkI/x6I1/rmPuFs 58LS1hPjfy7E2VIY4UNIKUjr2pgn0EyLB2l0y37atk5wwhgXDYZ2DNs4RXGxh5aym31Il8oldDjW F9X7RLUDxjQ9gl4+eqXl0PD84iXPFmLgOeIZMMfMs7JbD1GlCksHsXKV2RR0bcjkR6TaFNLu13gv hKyxhehPaSt1FxsvZXZ75ON9Nr570wMplfNKPelcCicGeP1IrqbiukcLH61WD7CqYhECOrrFpAyr Px+KlWN50K9+dQ09bnnS/4ZOLiBgmNa6E6v1xDRqinZRbgmxN7zKk6rmzJkgwGDxV0AuSACfyuwN pJ5UGLdycye/5eiOAVIW6FFstvdbxsJa9ewwJHzSmxJmDC6IzD2UtzPzcwUR3ILpJHdmtPfJlh0/ zo7Pse0A7VelhQvaOdCpLLJoCKk925XBV4CSaAvq3/2MZu02Rc1V4JBz0rng1brfTiTqtlUgKfb0 7BcFzL6lqGD+YuQ8m58Erqo5U+DqaUTk2dkQagclpdjv6+LhYbX3SRRxy/lamuoEgefKWL2D8Evo WxbxZZIQVR6x2zxl+7FZTfaZ5SJQKx9IM+ePajbW52MrkzMBIpB4/h7QsyRBW3Q+TKMhW5TP1v2R 2NsKSHBnH9MaNK2RijtZ/Dx7mSfGcO4f2HuUkoTZLjov5fuu/mCIp77+b2icnDxfOBDVvFreww3d A22cLqjeLGAqbMFhcf41toCt2bnafIMFWaUJPzwD9gTp1kcwHFTzb1XogHoDmiC8a/+P3aKfsu90 z70LkL9zidl0FhDISulU/yNfM2UZ3nSN4Bqdo/ZggNVcgMk2WFOhj9bHthdMeyyYPHh9THbhW7eg 0f1pYvUQMBxmliFr8J6RpCeacrN78yrq4S2qO4Gahq7MAYH4jfrkAhOnE22ZKnS7qw5JxG+yaFm2 6vn00hueIej7Fcbar2rL7WucdG/DuxGt8RtphqONW+C+1lE76j6OtvcSGpWr7uuOX8Q0cla+EA81 01dcd85Q1r2oQIDBxW0n6OCeKeg9t9VZAXOdGOq5D9GQegwy3GIu/d05mt+6IHlG2JF344PGMR95 P3yUCtGxg9u5r7VeSljIS1ztTXHmnPFc7a/cioO9XzvYWeRv2sirP/v/U+Id8FUNJIvSyeWEQyO+ TUhuRb0zJlLFFojnVPHARUCJesC78PF2+9LHDIL8TmH5cShGj4z2Ic4BN+vRJ8Mm6OQfUs8Q/V8J h0YzsvX9QUt6OOF18dtA/whBgwDNgiOrM1tv81RVFY0KTTf+PctFh2pmhfW9e3vClhW7K1KeH3B9 VCo8oncZMEq6qkedNNueLBFhKMuhymR7Ptw5pMf3IS/S0wci+ZxhXfCAo6VdYSW+LoSwejQ9Z+Pv pqFXchk//wUfHWksJT70/5Ael6VUj9YnR29T0HPCTD/TG0Bj5vDiznjaONWOInxgPXXssbbJFw2N ji5tCWmVtjnjiA4Km0/z2BDfslHlWNo4Lfj5tTkhuzwfAqS4EqHGZCVwFFUKQZSJ9JUQG610jRcO F2MH1xy5gk/f5jMCn9cvO2XX5ujBRvPlglm44BMtXv56E4tkRLV/WqQOIDmIhZz7REdGC3fpppla 17kS6DYSPldyzusQZ+m1pOBUwL1iqfjeVUZHobjClbwb0gs29NY3UjSuN75KbRRYqeg9JMETZrWm kP+hgPO+D0ksVkzLz0N1AJ2GOdsJIUMAdL/i3E8B9mlYvZfdRh5rBXzl+7+v4Byxxz6XncBnjMlO mbqJusGYSaCM4hPmbo7WdH/8bKVdg4U2zIVbj/L90tapYHcCMqRAsst1c6+7jdJTuEacGp16mhHS idB6CwLc4ThFpzJ/rZW0teQvQZ9ZXfP74KBVAqgwRuR1ATAQ7NdeANcwqNzk6l9TYp8EWEWPPzVL S7TZIIsQu5ASE0cR2UmiML0tFP1USnDBwfnECNfVerH3cD1IkiAIxpZao92RLpeO0OagvdbzIM55 5Z1SXb9MNry9S9s6OxqvvMznzk/KQ3W+yKVdOv6zc/9yk09ErGsdcj/OnKqIHYQViWznQBCMrEHd XbGIh1Javv1pSI8DR6+QNGGUlX5b0LH3cmNZDeB48IX221IjK0ruteCOW81aH5/nlMWZCyh+IuVP rKY/cDTnq+e3jZ5Fbr2Y7NLsgxYzGW+Vvng8I30qrseSHk7sA8YvjkY06AULbawq+L58j+z8YoqL fwU+9y2CyZaLtBsA6OFklyzhCV/sLSbyaOyUY/WZp2np0qfDHPF8H7WSkJ7bGh8NSkBhl/bo8VqW 5Lxz7/66Dnl+vZtdLek/of+/ysj6B35gHnYTWy5jCA/nLR2HOHKdDTySIfI/XLAcqxZr9epQ6x86 2Ui9zL4VpqNA7+K2kePNCmYbnU5Azn/EJKtTMipwM8LsiLCilM2iFSAe57Pthh3Z59z7P3RPzqqh 2glOFSfbEpfpv7c3SkP76gsLGNYd/5MP/dIXFevc+H5iyF19f9VyLE1mFedR7wSgltQb1714ARhj FJWbi65Fo9XYmTURu9oMvRo6c7I4TFvQefK0JRk0KsXUnzy2riDLBTH1tvvQr3ICon5KLK5qbKbF 1a4rKwWlVsexOTLM9x+dSWxE5RZ0BdfU9991BRIn0NinTppsyWsoWqH4+jvFy4c2spNxGSVq+VHg dUnqgWppuDpDkAxg6X2H/bnjdDhcRIWZKtD9nO2ZnpjmW78VHCmjep62kJUf0WToTSPaTxhiiysS DHqwy3LmvY9nlHdCI+fRR/ErVxxeEbwcrsyv8ve7a9wbidUlJrIzeidH9hBC5Ubh3GHlYcLMgYXi GDUgWXgW2V3fsXcdnWTxJNbCvMQnLrQvloDGuy46GtJOC1+Gt+FUQqrqE+/77hfcRnB00KdXKvNr xBo6D1mV4crfAG34JYnthlJfd3qtmrL7TSc/N0vCPIXcJdsSf/am4g+6c2Ywm5wae2qSyxCkGS4B nHG3R5a+vFektED5SsshWNy6dz9dnIYDZQKdlKifT32s18+i97aC8c/7eEe83A16o+BOmF+H6oTk qE08461p7KVooU2Ydm1QOLDs6fWwx6SaDBqUk+UwSKDnUyi/vUIVR/z1TWZhmh0yjjrJVMG5YTn2 zLah18NZTJfSVw0n2PZSVNGkwBSf5U5ZePlkKUjB3iNYkOGqW7IfoDp9JOCdBqq17K4xxaeySvCn VBD842+wFocUcHjn7F6F46/WQQ/48LOvxA7cKzYaTKTLkzper22FUbGcDagDHUyYjo20Pu/QZWMu /skm/TfJv1176S4vhuSfF3KEeLFOsTLF8QPVQ/SXGmB4Wiy7EJONdsMSkzOkgzcyhehtwo1cMMYP 8VO4i7U6hIB2EdkE/fZ2GYSK74rL0ri23t1Fz8ICzy/tcx3RSKSFBOGg2IuDDSJf6vwNVwweBdnO jHEje2flStCA7lZGvv08l83txlO7KUMQ6zDXzO4hQHrEtV5qp0p3IFerzdaCCYtLHZtSbjElX+er tCJBCgmtLTM+Z0+gdBvfi1QcVaqSUf90wf4HYR0NlapUDY2OD39KJxf9CSceV7IfqVadkBN37wH7 ted16XErAKUsMeFXU/bzqDYpCRjCwwaWtGTnutyk+7JD+ljguwzrmXfgyrfXoz9g6vxvCWbxLEMP BI/r0DiOq4MXAylYgLS5plwNIWwnYxUS3GfuJJEIhK1b+o34LVo07sDn6AmlUllSn8chpe9gwWxO YzYSqTkC3nzKxEDuCkZkvg+4Aa8D5r+1YhfDpP/Am4uMJFtOLjF4LmrUnrnTniAYdwpo6Xz7ZCM3 MqtC7pZpvV1QfA5gBMXZUzyxRfjA0L/UY4zX9Nv27z1snY8Ld6hE2UajZnf1JeJfI+EsiAqS2Vf+ hnlP6tY30WpJJDJ7PrEeh/5eV2oAbWg55tZghVH7BG9j2d6Oo5YK5nys+9IRuajwfUyL58ofJoh3 hkgfyLc93ajJQHiJD7L3+h8OXKMWj11IgsMIv6k/TasS3r0RkHfidWhYVb7gP5ZHBwJfQQmgI4aK elTq3Am32tFjcVDd4/ejPhXUxlNAjlPR5Al5Hzv1Fj5DZ4gGobCH9ml7UzeHNIIsdtJulmVRkQlu n9KPLebGk/l8d/Gbvb/NQP0IHIvpC54rY4anV+hPT2+/B9YIzOiyVXCo6dWBQU/a00EfIrM+Bsy8 /9VFdphE1yU97r6Vk8+Ltr9PZ3KteBiXX+OlffDotOM+sWG03s5bGnF2ZYg99bCgIfTNZV/Bk6LO NVWgLYFTbiw3KKnXcun8dQu44hiHka6521btyLpNwEP+gmjQq891E4hbxtJM0eQfsFPnr5xgvCjY Rr7ztGsSrTOz2b06Z+yxzvnefxLLRVc+vzXXqSQgNus1S5W91VoEOi3hZH8MTru2zvZ3MBY1ch7/ z6sciVRugWqGGziichLc6K0Rj9Zvm9Xb20IZV4N8lTGO/ycyikZ9d7YMBfUvHg4MHFDT9r7Y9uRH GsyhTlSJM5zDsRDrba+Xx9XmKsYBVN2Rm9MWUru8/fBfKHIyd6laJFV6z/8iuRAWW5nFPCzLbUXx 06WfjAIisOv/J0bnSV0PNIyGHdhzIJlhGM4mlaJqs+8e5HYvnE/1hPegILjd1RU7yVerodLB1749 VzpINcN5d8vVLQCSIheBY7ZoVg9t+36eZtdKH3LRlAPO7l5Hg6mLgC/X010OumI35nBNnMAKa4AZ zriF8aRmFT3QhXYu24ys0P36NkkW1XFaCGAMJ1mCN1nAbNbNcQUu4QOf7IWZhXh3ggHuK44TvOw7 FW3oCtnCtVKT+k4FhWkrIP9t7hb9JBpeLPOJBppU+H22jv1tEwD3gqsMqxwsgXlDAd1XKNBjjDAy p2yYGOK/LqegRp+w0gdHN2zMEMHnVmByJ+ZXaXdlXgewWPoRYx3SqHRKg88KEsxtmwaOqQFFoCgX GflwGuuYjv60oN/jP5Af9WIAPTOutjRpimfz50+Lcug+TGLLp/uvNHbLROaPKz1HLp5GyjjZlIy2 PBYXppR3LudjsBsbvE4ET6Bl3GYFDsuAaQr4CRH3djDVZXMyIwwRyeCZ8rwnFDJTp6TtESPf9ZAq I/cqEQsFYUwvf8tMuJl1pgNmYZha+QDNI2f9fNKboDqkv9d77IWq37Lyxd+xY9pq+J9HilC18eSP WqnB25zfkW6SJfi6Fmag5/LW+APeuyA6oQS8O0Hg5S1JhJP1R0jc7hvom24ARcX4l5QlA94qEI79 xQ62msRZXvmJbGZ8TCdhTrqOA2Vp7z6XE1JHt5Kv7SkxYf2NI4JY4Pe16BG7fcZbMoQpe7cyRvPJ LuYtDXQWwqMJfrZObaLIPh4v0vyot0gXingUxc5CR4k6nJ60wN9WCMyOCOtXn5Ll/WTu43HAYJlj Yziew4xQ+GAjuwxaMfdUGFoa/KQElscP9rYK2T6mKC63ztFcsUFNJCKjzHBCcszyKU75ZyS8heSU 0w/r38ZBA0a7yHwsUSjlQU0GWGPyw2d8A1oaJNNMrFcar66BbOwtDbAg7IcJ5FCfd/RvrqCfGpx1 Q0hRY21hvy9ZboQ1UhnU0vcOW1Az9236cKeB5tnAn5/3IuiLGgw9x4UaqglG2RCPtfn5a7RGzvMw dx2N4li4KkXURwjZ8fV0gdR0dnQDZad9KC06lLgSKFaKmuP0GGrV4qtOdIt+aK8tCDY6wsO9H+Ll 8KoeKxIKCUcNp3AGSgy/A/ijMpWsdYnGNhPpd/iQL96X5Uuk/McdsU01g3AyfGYQQMIbTLmKSMl7 GbysLfybb0MHUcyjSYWsM8vI6Dh1cZeuQaT4b6+mJlrDLLHf0Xv6D2TjaunN++NBGD1cM8OZ5EqR MLAIaAi5VzmGKtjaD0Amkc++KCshAgsM1bWmlisNR/jwjslAacHWUk9Lh/FkrzqcGW+Mvr8bx6QI wWqzjZJ0nvj0GalQ4NE+CuNqEC9SbgdQIcu303wQV5OpeZ26uTKHQHT0hrFHf0lmg+veeO7VIMR9 4Kl9fIm8RSplZnq2jUOYaSCMHoA486/DJ7yatFNi534nB2pOa6MMDOdVMl4DhGA3r/vT7d819EAz VZ0JrFOLwULQuhBhQTd8Ih6dc1gm1M2NgGOrNzDnzsJRLrKGpUtSXbXw/TBh88fZangoUR/w3HPN SvZtTq5TA9I1emdtH/dg5+jbDkyuPxUeOHCRz4p/57FboHaW3WYoHzdmMM6O7Ul/OCrFkatZEOpZ xUVkjX9CX48StLtMTGYVF7sH1WrXSdkimi8MOivtPJjAp/MM4AdsvmKVv0SQB/F2me7Gx8zZij23 t8FdRUcbmb+zT5AZUpTV1o0OAG79fzDaIF28lmlicTFxj8Siz1ZpQqMjfVx2aUgg+ezKUck7FG+f sfr2CtUBFJWTOM+6TnwXwHKSt8u1O0OmuHYWn+xouLJZfH2YrqAY+TqFX0gMWt/BUaX2uYSBKhuu lbA3tWRlP1voZknypSQdD+Ev5R5QT49kxiuFQGzjhz2Ru2voZJw6Hoi6S4hQP5A1vqyqk10sBKY5 ZDYO+abCsnbzEPiZpCbRXTolg5Pyo8F9jfiQUd8tuWZ+44Wga/Ffmfn5lNTxqbEb9o0+vbKOUGIM jSixWFimDkVmAKPn3K5AXM3SzCsXOHa1/b4kcmMu3TdyYrTSUzkVFqJrKIpsU2x0ST3QKZSyBUCt jk9creBpTEz8IK+cSLhBnkU8vfNtYyRSc38p1nwizGHoKkYP3BHqr1DDUO80K5OhjglFSNhERZp/ gdifyCLlD3I17fQioHJ+MFx2VksmamZhL+/DrekDiO5MtZlHdX8MLLZm0akBBv7tFmZJTdeIokGG t9tUzPnnyI6/S1YPKrT4YD3kMwm/fwrHGXaKlozWkgI9Yc7a9LgFQgKusehnBDiO96epaVBje47A dsJC2mrMeK/4WWk23PdzmyUR0O9p2eV+LgwkeqSTZn+ReABeFLSyDy0F+fnPI+K3A4OxzBaoJpl5 vCHOB32cSrwQMcXar74iAJMifTDrRSJoSE3bzg763Honf5CO1aeUzvNYCZaAFmESG4ghUIo9qlPO 3SnIwbbSvlsjCfhusGqFz3HyhGBYXNiSCwbJjifA7exPmOO5LbBrVZmgxe7Ya/1H5yU3KnT0X8SP aiQZAaLdpFV6f7aa1cygenoP7lFlRl4wnsJ49cd3KvyMhSkYaxLtXOAgriL3TweScNglmFDeuYmc AgvLQWwhlhMIkhFPhqOhCK3AA8q6dj+xh/MNe0QkcPD9Vs1oWPF4BkljBu1LEaTNecl3FnOBiK9H 4jyFEYkcv7oiKmZces2bQ8aNwBG0BVMZFN8N69ulb7+ckzA6hFKjI2CyZJDCkmNj8kOirzk+f46S Cx095KEEb5XjISgJA1ZvI0MVzzXZQwUEBElFI0dZ9INgkDHiTvIPwwI8o0yrPDysuNccHRmtvhcu 5BbLu76hdwBGxNylc0g/aKJ2iHTN8BTdBUBxTTKwATbkcuyNq33PvHlmegpMmiZ3h7mfhyBhRD3v /0afldGnALW7wHVr9zn4MnKBomj3XaAq6aPNuZco7uj+EzDjN1kei1zIbc0hJd/jXywE46Uv1CGm O9rCwJeg0orOyv1S/tgvsNaoA3oyebr9Kyuxr6LNFrKcdTMFJb+vDxQ51iDPKjB8Kq7iJuVNCOEJ D6pEYjjM7u4oiDqIFSd84rYBP0T7N9LrugAcARo4pOSQ4fQvFav3bOsO8iW2eZxTS7BBACAi3SgQ tCC0os084x9QpMfj25rlL9/OrB90VaF5RqW0anccggVzQhg+7vC8SajEcC0vLTNce7XjzRSPV8eX SmmEsxm60ua/I7CD//CF0f19e4jkWochCIE3Yzr8uS7gbBSZub3EO38ysSqFEkFfsHTKFjPf2lHn 3m7mWyDF8fcrxyOsZ/q0+9b9JYIS8jXInrxiPUtS9gWZs/gFzKtdFJ24jm7MVmdq92Y0uwg0eLPd h7JeiWk70Z8/71PWk6h0gb54ThQbxZuJmF2YwDhIGdN1Uyjp1Fgo3Chxc0Z+kj8dJYRg4s3CMhXy 8/bvFB45uXILeGxKPWWjWRLIRcjZoDpz3My1aYTbLfTXWCLK1kgy19Iyg9PN7t1zIZYUSkp1jyod FNs7ky+/MiqH/INB7w75ODQZSHMHMh4R4QvFEiIH+PtqWITiSI0aHh7iL9mcViXRtWji0RBFuEEf FNsnonc24yBHqOqt753axZiVnR8JlfdE1KGnYTIQMX7GgtGB+XStQl7KBv5cRiACPrlPmOHCvhUU 7PBhADsF9rXXmON74Ob/nKrUvDzybM2Xuu4D3E/f7/7t6kfP6FRVdvNcv1bMMC/4jideCqjtqrQq /lcCq8kOzpA1QJhe3WDD7y1zZG9BgeeowL4EqF/di297ZHV3+Zm2fT+J9WqO0vs5AMi6XXvO3qlr 2Ml2RuVU0hgGZJLO/x0JDFIu7zxwevAfMwYQMHezzgQ3Wh+/ehVNEwV/3U7NmgVCIUxMSpq1AiuM bBb3X9fglb4PSx2aOcD7Vf5Y0c+BZH5vRPr4xVj9+zL17nfHHXrgyAvzkxgxgwuK7RuwSntw6wwm vrijS4okOzofhnYwavk6rbnr62Y2eHqxUL6dWPmOB7LzvZHLmyJ8OIM9f2FMZnYhoSf8H0g2qDhe LVNC7ZtUPitO5VqmG2+RoYnNw8SfWzl9Ami0gjsfc/9olP2cO5mfxlkF76p0N/sp5F6YTWxxuEdJ UWeiXmVd9XlBYH+2PW2Eu0eu3ymm7sBLiCHyKpdoyMcLxZyKzH8JqywScapECcAGcv5fqTfl2U22 jH/1TBpYnTRYABodcDzmCiIBnDoXFiHPGta7aPjylzPatkC46DuYhAgWxfpYRNoI61+Nq1JxP7bm neAdLrIkjk4/t2GKZk+mhqQxupgUJNJOtH6948Qb92pIKJJpQw2LBg/rpKqZtthCKCkC6amLjoFi DhunIj+eLwyYmLcRUFBQY1ljH8EODj7k4GUd61jQcqSfcFqNeHf8MD46nvVyCTpC8/lStwGkp+tm jn4Bp2E0gTH9FYToZ3MpfK0LJfbkXrNUqTR4OrxfM1D05NdiBDcWMI2EM0pavvUv7B2ot/EDewK0 +dkFIS7GGoovu/Ai3ukVcxenAW0vfeqROSa6KUq7cCEBnz+4KmT0gV0u/yF6F+i16NpUH3bmFhlK kNNJLOh8r1X2uWRNZiTtzuT+gAo5VHy9KM5kOvZyjqv4a3iDlwJgL6nbs4d8F290zVwEErCoVyTu E7jU3r6u3mKpNcRxSWGFMylaKJGiU/oe7ZZpdAZ7RI5bwWreD7CWNCohWDYJJUJj5k7GSYWVUINg 7MpmMBalhgnJkR2UTj+R3jlzj5WiyW4rL+8EH5i/o4VFaPwrYON5hehBTmW2d+IItppSfeuWt4ho 4hNtxg28yTkTm6RXVgU6OxBpZK0k1ecvWEzR6tNA+kiRmzLnaniFn2h+268kFth8z6n3lcAcMqDH Y4rBXYsy4+zc/7syqIXkcID0+xRL2t30y4bnmueYL5HGi2BBfPo2FS4jh34m38QYX1t7cf8etM4N Qip4SSjBWQFmGqCLTZFP1qYMF7EQVsxXSqo/Q/H9/mTk+1SA2Y9ZczD7kP+nCTZm4U6SQAMRr+ry RcLlRpPkQpdT4wIogXfwBp919bfza7em55vh56skWs/U7LBggGi+ZkoT5sVHwmXLMLu7OOUwZIhi xEF8l+umEVNa35de5Y1eS/alACa1rS+SBIY4gip1ehZZO5DI54evVXieaTWhm9AgegW0ZKV5YXMo t6j5zyaBRz1WtpBqTkB7DqDNNGvCqKo1XvidN8NNi9Ug4nqfxkiQDA8IVPDDLSHjVWJKjHXmjkWn k0doxXdKmJEsWxGsOkQu/Ai/ahNpHBUzRPnLfnBqpPccujN0xM/vUWTCixFC75SsvxLZyY7DZQTj WNlieh3ZCe9rfKBKIxQR5IQoShECqU53zeMwYGPTJXM3mNqgyf0oPoDZRwNyY8Gtsz8OUla5LECV Ar1n6KbKyrwlmlnX/eXUcfRHhLj/uSbUebfSlm7Ygj3NZn8uLq2l28hZshVnWnAoES5k8slLVejM kFFMWGE6gUzfrQ1MvWtWSrioL/IlT/TR2VCK5pBf85QF2eqKRRh0GyZSAgIp1a0ybCpg9FXp5KWd mJ22vYJ8K/drnzvK7IuAEheSjVRM4+LNplEiLbgUL3+49RhTMfhjXR+3KWhJ9UmvsXG73rl1+qvC 5YKUNTypuk+5wVfdkPlFwlb2wLuiTurfG363amWwLlOYZCCzxUrS7D20Zaz05AQcNdtYUVHz2EaC eQgg8etYDyFhW7YJPUO63d+G/ot5dPIxvYY4x2DlPUmVrhNiFdhPwYwaMMQlB3UtVYo0KWhe1pRh lkk6jbtl+xL17H6b9W9qiMSgmzqJO6Rr4n5PIksWodOtbJ4Y+Hm7nNd2etVhuP5wzsx7fX474Htt UvnAnfaZrm/aHeSuJbPxdQKupR10WZ+WOtDI6MSt+TpPsPzMd7IDz4C6lZR3o0phPPQG3O3Re+dB lHbNN9GdiILsBPkIBTWkPEIED+Vun9nzic1RFHRSY8x0T6ksa/iPZCyp75jaSgFRXlLZccco3n5g vLZqVtF5K7KIxaHpPeNZm6gy8CHJNHDHcJBfawrhlpT8yGcOnQsaLJ8QWn2xjki5qnDMzjynpZ+8 5rXn6PaZgzzBJ6FKFiDalTG0qvNjo7vAYG4jnaPovCtf5CMD1HBxSfCypQtecqHcwy1LhL33I5+K AxGVdkw/GHs9Reeuu99bMRy8JWp1WypsYFZUaV5KbvPRYwRVpFBPn2AVYYiyF8tkzDnNw1v+cP5S c1BG3cWAeG0SPWqfUPjn4vrCLTiKgfQxs9ikknh6HLFNNWLP8qkrvUmG/JUu3SZjZFKQp8QFFA/n /JlQzFTnPn6o61zWF+k6l/yCitKvhu3A4nihfrs67TMD6JLBV0exkkGDdwtZYw5Osws8BzTTajn4 nsopd/RcTOQVz0tO+vGf1Y4To1jp+qwsnKBFONOXErPGpDnlfI0wrgq1t4Rf5WWXS9OwEA3cqYp/ cpfDOBETL/XJ31DwFKdEHLfLS1TvPZZm81wFuczVHJmMZQkQkor81OSC+xs9ZHeKrAvOpotsNpos USql0TC9A12uudOQFnhb63osCqS7yrYkTSYC+SPEawF9Lck0kIpxfDDVtN5y2mgeLMNaySMKG77L kjxc/NUdKIxoHqpH2s9YOPmDKMJleW+0RPQ/m50foI9ssyI9kdYZAnNBUJ11CLwvLjMZN2N+1Iwc 6Juj5IxxTZOWJmQrlbpqK7fXsZqFzX/NvyOA3t60iYBBtSgpp9CrOkOCny96ljyIcsDRxOoGdx+l mv60DmQLNzv8F5NQfbqt1nHxp4YR1gNw4hV6Jkm0x8/9xuU68qjfh2PtIXZXYipcxGICdLr/lP40 SPkAAd/U3vOMKYkT0K5CFJf/ox466708L5nb9KHEySONQEqt43E9xODpX3/aa8UlRY4q2ZRMjt1p zphmEtfqaNJclVKj+cJk6WmbR3f7vuDKOTYC0dL0fp20AyOOZMJZYTsWktQ5iLklJ3PQRLykE1aR JnKWKLiWJTExhYT3XpaepFe1rkILKZ21rMOl8PtbuCliyeUJI1/SXDqBKFjS4ND0A9KZJFXxoZCe LutTNBwTw+Ctoo4LdiUCkR0Y3iREr1t/a4CrEzGWkNNtprQ85r73Y18I1rcIRfbF1qDiLdrR7tTX nIUca2oMfu+2jCQ4kIhhFADD5UWlyxZOxApAajFiEQa4E/uaF5x5ZJ8KsUushp4Jvv9XFZXg3SLd DTEqZZqE4yu9TvqOR1nhmN2lJhgCPIns368WVWKTXXi9PARZjD/8cHaUbi04em9GLscw8FYfGQ9T rNY2mgeia+GzSWcmvr746W97H8B2W/RsjbAeGOBcvraDBvphFtDcvPYclovSTE0phUB94sJ+9WTk VTIs8Gj89vM+NSsLcQ2tp8bk3t+2J0nHM6i/4A7uV03O2vEfK15mBuzXbzFv1KGD6Cj1ZvnbiY/8 LrvAFKHoDHCVnzF8yW0YBOsS8l09VExqrgu4elACL+DBeGhqq6jJ6cPv5RBsoAMDQxW7w0EzDMOw c7B+cE5gv85w6Jx3LELStx18x0nKPPuFOiptIDG0WKd3cqUJfrKMuULABg+y3t9zHlWfQGR+skvZ ++d8qzzFkWSmVk7bhWIyXwDjgVLBypDa7opqaagOQGRkd0BNnB5cLtyIjjxgq2fHiMIY8Mh2rUsX SE/fpK8w1VaAXjl5YB0diLlShsKclfkJ2MXN4FPGSDrgd+6Vo8qMWrUKX+j9Vise+QtFT/JDyYpb y8jaiGlLzR05+QjXZ67/Qla029bhvWi4a61MLfa+CTdlnVBFiV+9gkn8C2Q76twixyf//uBrN9c5 ZYYrwD2GyE94XdM6ZPh/lanoWojhrt7vrYZqkFu86wzfHfaV8e/rTAsrLYtXpWt0DU0XPFB5me0T z7G0rtJZy7rnxZvuXr/JhpPA343lvgZLry+C1q5xkDWehxY3CuoFLDwcJnDmpAXENRTqniqmVOsb iGll5iCJYaY+vt3O2iwO31Fmwfj6HDDM5egO3CItFtOdsv4ogf4j1/IfzbcCdnGZsBStBzmKVSSR 7ZOL0qYdOTA4Qfso7zhzzca1G+zpvTKwft9Sq+zELICEaccSHo5nowNTFBKnRAahJGTAcdKzVwiC ZHi73Vxt+fTYZ9YJqPQDF7XQREuqED+isygL2qr2J6/aED9VwagETLnNNLfwD6I1kDEvSfhoVZM4 ZcVVhj1oSi2UU2oNhVmm3tP8iXAACHpu0s6DNuPUeg8jP0UyEcm9vgFY8azRi2jsBN2fYhZdrQGr QQQ7e2fz8dnkmXiqdZqLRacgxNh0Uqe+ON6OT1RHGQaTZ0miWXc2aRtTCKUWZtYAxAoYPSKNDimF NKJt4gBRv1sFf0shaMOA2eGatmnnwyKzaVjHRSSAM0/Y61Fo3W8nF803Zeccw2saMMSe9cTA4ki+ 2ovpjBX1WebjJbrvEQcacELfq8uJEuKuDbT7mdCo7kqXCYhQ1Ph+NHROW6sJt59WLNfTr8YRTBaV CVvSQmTiOxiIsJZ8nh3K9lLLxEKaWmlinkKtxleJtvi1uuY846gh0NRCXvciqKdIKcIRJ2eVKTEW m6O4K35Wh+igIX9fe4cesL63Mp9sE+gboflEBI2IkDpiAum7+u6w96NvXwjGV8Q7asK5Y2qUcXno QlOiTvj9zV1IRCG9/G9mP8MdTub9Sq0Qe66zRo+aN3kvhAl0mEG4WFQxy3JdlYOCYn3uukBhnLfT 8v+PspeTsqEUtycA9kqmzSsaCH3MJjSAXXlvZGj5OPeyyCD3t8fl/P/sz7t61J6ZpgeD0Gez21dW QabfEdCXD9yzzMDTIsk5wh/Gd8WCnff2eesWLkxlxOXkIw9vDZ24dHtZsij3TMXF/OzQ9vYElzK8 Fo34QOhEx8K9AymI9tz9HQxiagcp6uuXOzKEFVmWG01pZe3REZ+8cXBaedZdt3un7Q+RhnzIgxmf 0P7SaGygr+lmAytLx6CzgQ191C1jAFMixVuDERpaYUuMRto216O7hZz4TVCXLnwmKu/a8STH1U5W mNJPMFlB92R25bc6BnGnseVH00rEGcutePnrcdy/Q5AMOZFbFxpRlGY4R2MnyJs0UBixE6jYZy9R rViA+oicy+cwLEiD0/p/4+9iV/ZgeZZ5Ae4Pr6ZW1Jf/DwSenm91TLYhnE031+kk102XwDuio5BA rH3JiDP0FansnkhPDbqIRpsgdRfSTV8B80ECd5EfHDZmxYjFf5T0tToMMDBmILd85H7Q7aT/VcQs tPlNVfNwaWf+JC4W/D2QnR7Vp0bHwsN5syDBNpxNDPXbuR/ziprm1pw52EzdbHou1B5fMs6wNWYv EFm+YOYl3dBZUzKheyfjFowg+v9mUKc96FfrFNPfX0teIC5+Da1Mmi9E+/YNbYmzwG4TNy4IDUdK yTXVH6ATr5VYnOZymi6p3M/KwFdf2KaAXcMm6HAyvIJz55PHxJBcR0JNbwAnKfaMZnvn68Y3/RV7 LHWqgql5i4LZbi+zG767YxX8RnTW8pNstsTHK4BSpbe6itFiybRaXQwV1idrWo9dF0oYEBrtDHqF ZtvamMFMVVxuU77icFgH/Oa9WTsH2OZ1yJKGYcaZgzRpkHovso/7+nM1KwILzvSyh5if3BKLh0PH v2+mY1XXHPPXKheeGZmqof6kZAdMtCTsGuPwWbfVaqSY5PBvICz8eelTMgTVzBvB2gzhMLAhPlyk cjJpUjgH9KPeJphZUZ60NCWpA6q64NOJhIY0IJ6bQfjkjKGFZA+IoKwP6TQ2GEjFsVUraGnD3Pf5 fM8ff5+YnJgH9/8R/MB7v2NK97dM3OdM/7CVAlQsrwhuL7FJL3PjCUDj+srvs8m6NAJ2sUlm/kwV hvVCfjECSY9aolcCgwXT4gpWFpffOuzyy4A7/mFzqWvHMyzYI51kKYYGKHxVLPP63PxJN5NXeFje 8Pa4GcwgIzfMJTaeL+BovNQmeXaNRK3PhmI4KR91U/5nnwIP4iRpDlW/fCNwSghw4doPPt3tcTB7 4tMP6DNsWLQ8a5IK+exlFGWzMqKT1F6f5uSZsyw7xZheMtgozN4Wg6F6ipjJAYkKypq1wwrMq65Q Y3L16WggG6GN4jvBrwdsOSARDFdBGcovzSEw78ma8xeNUj43AilwHpavCkBLy3Vjd3ytJYtJOChQ 2ybLTjgODhNaKyeDd+IJzjk0XJXxdZtIGprxVhb9Ey16yu3ljV1Xwu/aqgPTGolz1155p8KvbUbV +rfneiua9Pa5x0SazLonnwAJ4VAqSC3KHI8SuaNAT6O+3Spj/DcXqH1esRl2paHIMJnmTzfgxZy+ /eT9hS6x5sZ5M6c8xfBzzvVJ5wVRgC9pSm1rgZUrAmVOkMRr/WMbYb9GG3wfnOYz+9ktmKVDyhVP XDSZQ604G6hiZ54EhQ2PCAXfWJaCglFkjFkoHzAgfR8xD/HtbkRZB29vfL9qEUcxvOn5aAMcvsMQ MaylRoCNVyJcrD4HvqAJMu4HL+T4t3dR4832YnurG4No6gVrBgeXaK97jLeBRCdpu9vzGJ7ZTgYv rZjeJad6bTnN6ngzw7S0NIrmUaL0atdsb7PxF2TAEdj1IhkPsYIU7Qofu7sIUlLGv6oMWtN9S/2B eepZ1vASnkua+kfOoOOHP3WdkGR7wClQkvF0D8dVXpna+p5zDrTD0pSgKP6etpg1wh+pZm3nSqY1 6iqlaCK7eVz75Uzps0MQPQTwyvMsFcfCKTyS1IboilL2tiZyCqdfcFc3kV5si44t50oYcxyMmOD5 e+4mLm9cJVNUp4nkInsWij5Ceu0IE2O/sCmNiUn+wrH/cnLwumzoLLKPjFZxvRjrwUi8nZeDu6Rj FFjsbWfuRn6Gkjt99gsXtGVxudT1HyB/BkJNhYNEZ7V7DpCwe6k94e7MiUdIOb5mPDxXRlW5nMtP dqiUX8oNF9p43tk62SJaYpbi6oTQWxdeIEyVVnkJ2sLydVvhJS1FD01/Pj43At9X7z3JVNtdl3e8 a55yvgRzl8k3Hph0P68obqg4jUtcbHipaTP+4iU+skzzo4JLqnChNZDJFYJDUKpMfUVDIB9eLDSs 6YdGc6r29llIoA9f4XlGFG1Wn6+lDiickTBXMZ5StKHDb4gIF8sM2apB2uRx3drtK2R1uaW+Jg2z gV9IOeFobdVYqWU70bUEdd+4MlfxlaPUz/jEarcfu90NNuY+Tk1RME7hcMQzA8dfz8gG54dH68AX VjRhd40Q7vz1d16uVAMpaAXs5usHykRKZ+einBIB96ZmLsSESJWCMfHQx/W6rhP+xzJWSS3Od8w4 0IupuW0HSZbSJ342muYTrKdCKuSk37YvxwUrvYWR74AFxHoH5yfTW9VnuEFJwRPVdX8nOb6tQy73 73Z7AfVHHJgcuxiKaNzSGfmQDG75Zs3Eo2Q19jxRvF6GQpvjVHWokx3MZBHH1g7Wp89MI3VJParJ zblT0n4sv3xv29Bcq4ND/yOFhv2HKrNlt5natf470rGTxP/GTEyvC1m9GquOi3LPoUkX/nOO9Z6D gPcIwrgt3pNN8x4ZsGmWsm8Z5KZX9sEMxelDXJ0s1Ldx1C9WDtxn/2zR2YaFMKY+PJusG7XX5yB+ fHPWOpqNgPJjRFB8PguKuAnJxpCeWe019EksHwtiIF/BeziVxXvFmWv0djTrORoNuBXU2wAEZs2H 7F1Q37DJRpVs5d7s7sNCpHaGbUSDvCztuxGOerN4stK6kvx1Q1/Xy/nDp1oQzxsma7xMkg4gnAm1 Cc8ziri6aMq/UtU23q4mC/MOgxCFbKeqYYfZ5ago9YfpbBhCkAX8Nd63fR56FG0rJnIqFmk+EY9s b3r5uC8AIHPHaFD0kTMFQA0nHFvyhIcnkjjcvVKPRLF17pK4cwOCUdQRhY2/MRFzDTvbmJBLTC/f ANJjD5abeV58gM9MtY3SYxntm1zV8q/Ukt4tozANoTfDkchk2eHN21epkdl+Pek+Fv2C3o8RxDgK FVkoE6MH2tHJLC/eFg9+vD8H+wMkHDwCDStgn5hxtYBH8lZXab2JIA7MqafwZCjMEih4X6zLaiTM Aoysya5wCIolqb3nVYyFWClv/AXOTTp88PN2sADmiO5fNXy2rS6LgkAHNBxwkl7RqreB3H9sHPsj V+bSI/MHF+4DoyYstml2NNA8B7DUS3jRICtElbkCWsvpstcFs23n16hRv4DXGaLNihREDbeRp2eK VHzFJZc68bq0UhvSEuaBFekDTGCwh+bXQQGUC16DJzzJv4/TAKM7UuMXptQ+6WFnwX8FaZVxKbn8 82JB3dGayuXXkxZTHq7mED+ByW1/9SsuAW0ipEyOB+EzKsELJteCeWGz/vKGzVbuRQEN3ABMuXG8 ZC7e/hnLILVsQ3865yGxWuKKtNMc6gi+4KyJqHVseIoiarj3fWfUyMUffbvIYzNBKCsmKDjrdPui 0hlm1hnEmRKeWlGzazySsErnG5p7KQFt+dXgTMOnYEq8vv8r6ySrPP84p0iAmMPhAeUaU2ObpGmK dQxyJ88jQhrXckUuBQ3iP/xM+rvCUpk7qYfe6Mj8S+RlF7WKC7BU2Yltw/PSpKEyuC0mHpJ0S1nJ /Ses0BmcH+adnLWq/a+zdPcYzfy6cV4jrZvQf9PjNwmMVzF0/xyCEALstoXRSFmrxWogeKv2wo+2 RiKGCF0JDUz89AYoI6cFdoMcc1sZMcNP24AnV+1dahf9cCiHr5jMVMnbzlU9vgpjy+cBA1p2F9L4 2pLX/JAAxEiasurDV1TZ3+MR3LsQErS54q+iCnzEqNn6AMwKMMzqZkOpFwrccU5vgcXfcIVqsE7l GSiiau/grnQ2MAqv+lxdzMZNRK84ZVgVEP0eqgy1qH1ulIU6vnqU1dg6M5iGhElesTg3tWYfk0jH nbjR0c97MWzy7L6ldywz+TBZX7e6vefzLwThG5C37mvCl5lBN8zcL9Bxs+miHX8eqnaCgk85JfCd cnuNgmzMTiyNXw/00UXWWrhEFsxkamTz2h//YvMPS9M+8ferE5t+d2GDXvbfOdZFXhVHTKXiHL/O tJcdrkVLxmac2DpKYnR1JO+tTMllcQ1VgA3QOg4QTuYR9N2wNVTM9enMaaDQ5Vyj1SyQJDMOawm9 klgDxLu2CO1Kfk8MLUET1gl4BXZksJun6oeSuxdNCjDlECzapJA8h9y/Ry1NgM4p7iYevdpia82z 02477O9o2J8SLuzSVJWJ3+CMmypjcsnUK1vsnJ3HAznzoPZZsBeXsk6V7VB8jusffCEQ/zOGUjVu xxqLjXWUoiB8koBYS2SA4Crk3UTUnCDcuQIsflwUMnnh6fYNzBk5OeefPhEFLrJvfCc465RSDbrz ha3+nej3daOlhXkNJla5RzJfOg4BrVklztMs2WdD7z7/sRYJ7Z7+USoZmOs9Fu6KS2VBi7q7kxGL V1356FsjbBtjHHoygbrvGLeM1ppaCbb8se8wWf5d0I2evbPHWK9mWLVXyGgE+mHkuwytshq77dsp lZi951Sw5CEUVMkXr7AiayuHyqwL5Woz3ksdEtOqzzJ7KRJN6C31WhXyGf0nP0wj65/MrwKUo9sk WiUX/tPwJTJUrQwEu5U4aUm4OYdnd67VAP8sI1//xgt80mqMtiil+X4vBCfgnKOM3wGUrWCyWL4o L6S/LVDLOHapWeC0Y68rdx83yQfpy4TE7YtzhJfwbaOVHWZw8Eo7z0P78yVqhXFOOhzzWRkyXiTU py5Vg3TbxxPC7w93mPG8hDlrJHWZNUu7EN71RwTxOVfrr3vzqzOjbeQ0Mcf7bJpeFziYAZE9GWoj +FMcIxdh/kFRKlWnOTEvt7HaUi2142hj0Twx6EaJ0OVTCtFzyHNSAzBrB2DrKfmg5yOUWS1x8f4q cZW/GXbRd+65odhtMsJcruaPrDhGbHaTLczP3YnWkA0XvGUJG+vD6Zgpl19TEOT6nP0jvrIkKVm7 8luRlGHtgzKFrY/oRZgJ9pxrFVMUG7MOHlG+bvOXXkuwy5bfi8sdEc0pjpCdLgCs4gQCfTJU8D8T XnzSJyjt3jUak7WzODbA6JpGnSLfB9O9S3yb9nEl4wv2BnJk/gYDqsV4ZY0mOgPksLocCivS9G5g O0Do6D9KSRPKy88Td1MIbntwh2yxBW/coeguDsbq94rBReTfUbuIcGrxK9WHf6lomFn2eic7552m 9WX4ZFp+pyE9RjRMUOJ8WGPEj7RQYFpjaEXuiW8czVKPMsXeZMu5GPTmFMiC7jnvGnxaHk2WzB4E UivElaKCCZ0WL6PUXfTLMk5lZ+Ge+sBGwYEGhGKLlwkEa+C02xVCnb9Pxz4z/l4iC+dIx0laNJK8 n0kwLuby8uSjjpZekoAGbdmDy+IxQ0EPzJjVtz0MuKrQUASfiF8GZoyAD2cxeKmJ4nClx6tntZke UFjYeuoSWc9fABGkvjPkbdR4m1JIbVUaIcGJoM07pNxYdmeqLTCMcMysBPKKQ0vsdmS6joV2v5IL 05M4Oops5XBgn+eLtDxWNLmmSUSW/h/pUzYYE1b9V7DBRX1Cxv0EnnbgCvhlDrUPsLhsS68JyMSq BZ1vzEUAQkK8LWOIzmGTHAzkVeiAagYFeoW04uGN8sGGm27uH5xUKVTHV2UjlCenCwOQAhAXjiyW etpfJxWwIK1rCYMd67ZRKY7nwwFikXT5ljqqBxTvuPpASQ6DdiCzeQ3hn2pyHIRH0oOdBjZ/oAnz dbzBeN2DLViqOyfPoqijftGMRmGQeBK07C2LXNJ6/G9rgH5gKATRavt+ba1OkO/9GaTWlxoslV4E /coLwXX1wHSpQn7pd/WqWNYL6k1crXa9WTJnONAU9e+e4Y3c0a3T8d8ZOkcDU1vd0vhCXwOl+qd9 h+bj+AoniceNK3xDDD20SD45XwtFAVgFK1ME8xp5YXzjkSZu61KFTg3/s2MKuua0f/tArwzW4VpY 5bZPjLqyHfzlG1gSbUiyU/mqj4nQlwwumItntwyIWFsn3UixjHwhdlMGV5IQ96lWG8BmLF+97ACC AGLN8as51/Y/o4YXkMtUYSBTQ6mrIFlKgnYvVBcrMnFBejUTUenayHDADXtFdH/+hhF/ZAvVZb7h f+rqJxUBODIRNlcE+yJDCbfYm4wmXXitlobKNHdzhar5TdrY7AiSadGJL3JzkZHuIWr4HrUDM81Z xNGtVwFgrjHv34XOMn6iVYjXu+qUVs+8p5LCfbJKQVT3QvJtX6XIEgu/exWJXsmaN806WgXh/nWy CdpaNiM2RPOF2v/E1kQ6wnTMO3EdrVkwrLiUZRxjeZ/vPzAfUCULfjcrXr+9Afotg1ZNx/Ms0Mn6 GGl3NOAwt9+yhrAQBd3zz3LGCsrGgVUGz9O2LgbHEtcq6eUrWJpa9op0dYcwZ6GmwHwWmR71Tj5y Gvl1fpZn7w1J2eS1gOK0lNwKKNKDqZPS2FjdQl+TVVyfPgq2JXrX0lSu0lqWWkN35ZT9jxa6FCds Su2T4klBU44zwwlQ8kgTOfXiS5xiOtZt37auhd6vtTk0QAcIYC4MpUsmT9/ZBG+1dBz/zkWyttcV wB1PWuLmTEyb1JnxmagST69+cJkTzVtnlAMkwrYFPos5wTkiVXwjVPX4GzG6ubPqmtWtIQRtRQIb djo1HCJwF0frMWAYUj2ek547//jUn0sjlzMZr5iGs89EVnTw1EXe2zhRf2Oz9pqKkZKlJhoc6MoN VRnBe+YhtsfX93mAweo5cYnUOb/L+3pOekPb1tdM6aTts/fmzPPtKbtAlrvQ0mw8/c7C+kfLdRmC vo9l7fYFNu6CFOeNq7x5Qi7/rY3yGJWlSE74f7THv5d9n73FBZ74prWCylm0ALHQnwRX3IHhhg9Q jMC7+bY91Xg3ECA3XI67A5OHIUvFBtATf9j9asrqS+zSwqNzp8Aj8zt5s5mX0VW1Gzm+dXdXQrhE 4eXVfJBlzCbhBhCEnsYg4ZHC1Eb9rJNst6OmAWqa/Fs+6KM37K7OP/FsyYhGzCTry6cqOeOqGEkO q6oYkiJIAvCNEy9A6Hy1Gtdj9z0MC1chho9YuOqSvovgASlF4vHIWv8/XO7HmUW8BaJbquR7xAAx qavJc9+V1RQMUI7XnN3nV7/bTU9hNhn3d2j+Mh+EIfKOYqOyE8rhsimD9TzseV0FiFZKgS8vdUlV 81UkuGZ1RCBnKQP8INUNcNwy+6quvCvbiQ/U1FO653TfwOwOqF42CVtRxjJ2oTBUSODnLpcfcnu5 V0dM4ra6zOUc0/KfZ2OBOFwbxdLgzhnJBWJ/LLHPKcC608PzHdvzLB+oFI33kDEJ0/SUdPcIACMt vEOX3jORxpfG+2m0iRpEsJFcS2vjd0P5mgQzEFyUOBygoJ73SQccNmfBIeGlkOV8uDE76VVQeMWr c6/oYCQaxciQDlj2QynlcAA1EqIs/5nt3pV2rNcvkhFW3q678ByKTyINuuUSC1Y+FsR6JnUaMcTS nROEfWbVnq7ahj4do7Qriw4KMbcazJnz2KSqprrtE6eJ3FWkUD/hxtyJJK6Nzk/WVBsXZU3vSjXS 95gUMunDQ1cKvYhDHqoq5vC8txOHoxkSQdHV9f1xEKeEzDlDVREVGoojC0Ub3PpsDJunvFkljtf5 vin37DEe0CRQPgeQ0RUf7a1VIBtOCeIzk+CGOiwxVOfd9fQcVljR0ZH3oo+5QjDT1hcZUEFB8eDN j2RVBDxcJZ0AdrCfAUV6GYaQoNGIEXtrLaefNZnbFid2voMCw85DfVksU6/qEiYqrjBBnYHoWnzg laocywggnE3b+Ufyd/4f22kO6mFm8pIaTA1rVFcSYn2jJMiKxzqEEhswKA1Dz4L5rJWngHHskzU0 yefDfWhInG7Ibe/QnGWqv3PKKKciLShVUHWPPr7/EwS2nVYAeVuBDgOJlzgUNq29/2aJ5Nhh8KqH 3Cneu3dtafjSirMMF5FZzGkoXvA4eTm4mFuAx8vNx0LG4Qv6S3g5x8zL0i2rOpLx9JkmY7HvXuLw aBhSCOrYOBEyyqQIn4RYFQ0UDh67qN65EEolIw0zYjDaLQshVuowQLgIC2bGwSnACcJbhWci37Aa jfy8G4lXbPYvDqJsbj0M/Eje1H/Rv+5O1TduaROSYxBAls37ghtSS+CXX0MnNvOwbbhcQEwqybMH 7ijvjBV6YiCuwQ48noQx8OwopWicgoI7BhZh1OFa8I6pz8Jj2KBPBoMY+4AyV/zKZiKLJ8D0LDeR 39Sl5e4jY8ntR8zXwx17nMdtpVbIPXyu5peNSSYmWgzU8boxJY0+pZ8T83/e21stg4FkW0rfNb2y SvurtW6J+tmbzG+GB5cLCUvwzjqaAXK0st8rve5Tmgyf/RcmdjNcqL0c7LsS0Y1K6gpU/pViBLSa sOIrRfdBtF/276lPs9w0D0RWT1urv/y6bwIcE5vfoTNnYqu/MuqwGvCJNxoUqicB/kMUmzUg+bED oeIEJWZVUlc55aA35KrKNWj3nJXQC75wSgL15MC779HBBIoUHecn8QUWIiNLb6CIIUcS+OhijtC3 Fzx/eDiARMerQF0eY6BVAWqeDzhG5BgCtAQBVHOKQAYoKJjp05zo3ZGOHivhRTp+4A27uf//3ZuL J1tiGaBlIZRmr7PZOBRtMkUf2OzNTroy1Ei8dbUzkl9z7erl8JFsOTMGD2blGi6Z/DyXmkBqhI51 rTG5+XXmqQS3S+qy6yBVg7CPbx9AjRaciZ1A9YDHDbMJx3pcl4SWwei4wgTUh/TeRqWX5AydTQip 6JV7QYx+8USeo6vEgDwnqmpkow1rm2GhUcSw8N7Zca73Lb0bdfXQiztRHgGY48o+pBDiybJsGCsB 1hVnD3aEs9ESDKp+aZzxjs3KRgIjj/Nj3V9jnJoXsf505Ul8UqJVJYwvAMIZZx17YWbXVOqKiyhf pyXVJKEwr4pJvXpt2n8Lp1fP/TXAqC3ZLwH60SXRnr5mKPK+x8U9vUnHQSmztQ4qiLDcawmvAg+P W3KXFBP2DThUZipbavfUNe90I7jjpxY6hBhQ2wkzPa2cBEAT/EFKkjpihUex1gjKB+SMVYtKfd+Y Kqrdtuapft23Q5NpJpmhYwPV+Sk1HozfrI5mKRwIOVE3taIOOzYuOhJ9kwpRjPmXWIptlg7PcOMH MKv19lj94Ldfhxsj1SZuLMEiCxn5jU+JkWrAgH7Mx88GQifbuyH/nIuntkLyZhkmKH45tAO2DNhJ JmGjiXenaBB1cW7Cz3zc35abagjjl8YfTa0oJwjuZvS3lgmp/FJH5tMQLiZlzXnBwAitC9RpcXeM ps1tkR8wnpPyV1sjMlhWdm1/QZ9341eMZ6OcrdJjzOno4okcMYiPcINJM6UGkWyacepWwFnpuSm3 BGokKSNZQo0C+GZ3+jUVEq5esD3gOydHWdUGbv9Y794wn8RLmaqiIbWr3eIKiz+loDv0X/sfRbec 8EpbbEZJdrF/EyyjNmCUz7BnUKHJPliRIxs9SNcZxnij5VbeNQecxcbCsL5oJJAJ+Ew34evtG2UR FwDLhtQhw7DaddnhQfwrJpX2uVI3ua393zP/aQE5JlKwi2QX7mgAaXRa8FmsWJdg4+9ggDbGycOl +sM62QVapDBMu7cVLiEQuLcZ0iXnmF90LnjjJuBBkj9jvAD+qyGOdd7a0D7zZm6vphZNfXY8USo6 N0FAZtSx1Hw8CxQVQ6Vo24W3pQq5apxORUkVAqiSdcjFSNPcnVR//yKFwEP0esoYvv0kdNCGvQX0 NKAzjUVYKUwwKxUK3ixTZmx/HATUKjDfDpYvB1PdtqRGr7TQhArZJK+FJdA8x3QFDj//TQBHa4tr GnXMJ7O49s35H0zEUPRyAqBh5vnXc+JqotvhpsgpUVBkKJWzf0cAUo7Hp8GtMqPRXBsoqmOXQOzh CrNMXGkWTw+EQeUXhKCVj0kUSQ77XSJA4aG0wMv8g8VT6jwfRbxGAxxE67cDBy6JvgJXCX0Zy/uU Kx3S3ZCvSFLnI7QYORjDwfhHkG2iLPXbR3VdOMSB+N2EHHCiQ+l41RVoF8YIQl4kD3fPv7ZdbbvI Q4vrb3Ko+74O3BCCuqCcc5zWXvN1faGMMagJq77XRmu7VDaIoqZiAJun0Zv94kJU1o86EvxNyeR9 3mO3O4f5l9sF5Vfl+EUkGXN33Pr0x2R7PI42uoH6NS4VLm7pbXS8s8W/nWoGidaRAiuC+KAde4XA pgQOsqhLJ7fmznibAv9b+TOb/CVDJQxWtjvMsmC/q9Tw+OB5zO2Ao6/dIxwKlo5Nwv1IBsJdgFNz hfrUoU1mVAQQuS56Ln4WRVaMssON3/E1kalkuTcF8bcdKD6emVE5tG12h9mSJhOFROOUDVOLKr+k di6ttItZP159qxgpBVziyacDcIrgogkZ3BcWFCvL2t6ttfFSVy0ixj2QuBHg1U7WhXyb00Bmmi0N 2duJQeekmMPmIEOfLDhffqMrJxa+S/Pu9RxjYsT9ueS4Hi7OLZt94M6G5knG+ym1MewvO4JlT2a3 9QHNKiVIsGXWdBtAhyXe/Laz+Y2bIjygpRQMLsvFUsGohUVmqc+KMvPeGmPTe71qZR/KY8NgLxAN hwNr7OV/nfLFlzn4Bdz72PR+0yAkK0gTCOYBdz/NxBI9ogEN7nk7YJGaoIcikvIwi9WIBbqn3bi+ M0Wniy1ogiHXWyt2qZjGh6YcIub8kA++dxO4q8kgJkdEmZ3lOWXvs/61x3PbciSTw9H83cFPcBSv obX4HQNqGBTWq77OIplBvGASbyfU9EONUQW3F5cnxm9lsr47cEwHb3Nwe+3J4+hV/AnUWbwgXOf9 HLJyC2KFM7aIhiA/2ebI//d7m4eNIP0Ovg0WtfAeqPwjBpxcWIH7pAjy9uN+L0JIMCvE/ofVKJ5K iosmx/NEuGvMI+FVx+5eZhdqVZ936Gx0c0fGZ0tSzoMcpukYYFcGYaMvovERihqVRCa3HKaNrP5/ 73ttT00lUiAEg7OMezJFHrPC1gYWg//aWckOtiI3/j0gfkNpGonhxvBd/MotTD5QtniKcPOKUrFI hBBgOH7Xgm8v01iYySaa3+XmkjbWRF0hkSI1PqhRaQbCf7wbi5S4093oOoSOnvp3JImF5fpZlUYg eASYBpkYTnQR7xSVT8NaZttEsNZU5rBTFQEVhjLxAsM7tAEJTm0GIScb/NtCG6BfKU7VoCHb3uOu LfrniEF3FIYyX19VRwgNhNbT0pqrc8maR6jJCQyrNIAi9uuTZCWyduY4VI1SF9qK/XZLjdk9jmAp ITdcR4ckwqwrvasWq8kygyUFeE4zZ5Bh6JaZ7UUKi5N6wJvuP25rAFo5gRFLBOqaeJ+XLhW0bx3O 0oMBGKzQ9erl0Zo96O7mjfNbx/mVyKQ9/B61ZXQ/k23YNyNR4i7nBZFxvWMPHLR/a6cCwBCj4q3F DPEMH8Sg95cwz/V3+bni2NYiyv8lMuEZZpigiZ209pfnBG9ft7QJMy0wx/PI7ADKjxz6dmjS8swr EwjmlKQECjeUtnJzZnunS9ZecoXU7pwnPy5Vm6fLeFlxYyFhO3AW688uteeTr5hY0YBDYkutkygC o+4qusn5mYZn02aCCm2WL80OcFneFcuxuUmH1PIw1JR3qQ+G0xGBtKgG7qWe84ztegPMRYJHatKD HwS+og0RdmJqmKkg3fnssvOtfXsPlJldWFrLMDc0N0GJTXJYqJer6Xqj7JkhFFO+awhb40q2Ocet Gwf3N9nVKvKsUJf0pzFS3EZcsF2V/zXaXDsuUrZfwLvcVgVGh66Njpjt9yVbf8w2QwsifXGoxKHv KUeNZbx9cdJZl4AJyGxtkRTe6fRX4j4IK1/FXV0r2rlLt5MBNeEsIpEx5gnPUoSpv0BVH+3AksMb H1f+R5NZjguEJGvXRJ4BjtObd00qSmNjJ1De2mcdD40NVEV9w0aHHPQWwazfjRkMqnWoraFpwmRw OSOxl11zIjlKUqWhNBGTGpX/wkW2icgWzsWJu8VVZoMXNyzITT/kYmqJQY7dE7mpr95tvE2setL3 OubhR5DTEPXhUToYU5ckI+TIOmC3dTOU6kkX46UIJnehye03Ykn6yRKZti1+kWTyDyLiPGmxE7mN XsUo74twECmgoY0zDXAMoSUZHb1IyR7mvOI92UrdgFEKW4ovHRs4KBNEVhXFY1ABxjcn9jc9tfAx lutkxlvGSXwx98+kUv80FcvYJe774rM9mtGhtfRunKVtgCkSuGTeYWEChRzKcVXLgrx2XyUtne0M xI2B9+LBaki3+T4R1I5W+6X55raQLL+zH8J9fYZQp8d3YZ4yOuc+QYGEQYot/rkcpLRRWIREWAM6 kGxGdmT4dKd+vuWXLfYIje2EGReDZLDGCmpSlMRWZ94t4facTHKs6ms84v0Z82uO5tqV11MIT0Rj tV97zeGT5pT/t8VTFIlXkq7shxqoBYc6AuXhWLC3HA2ltWomy/GpX1wf0LAUAO1bddOhqOtjkmo9 dKN2DjIathPSdPf0NC+gew+5mIZnyAmI9OhkPlSjPZ/ub2xTV0qnLN3QUujSx+LUcC1qu+lQwifL MvQolVpOsXtOxbj29NFuUzLkAwdQq2z6RcnJFREXwblNUboWLNvxlWCeIdZ9XMhMMxuUAQ6VdsPo Tj7Zkv5etmFePILpjM3Zam+A5U8OezvL2luLsa3+/hw9jZFLkgfKf3pfWGMnoEzFqpjdaixg/YPO 5kNUrM5CT9IhxExZ0A2V65jDZ5Z0kWYsF8OGekN2ZRkTHXk43vsWQ5rBlgIMbeqPgYl5bmAQm+iD nwhCwE86QvSdZ4+BHsRMiY6Xe0v9cfd5H8Td3Qi0taC2DvvFj6Re5HYRd7iZOo6zmYmuYEumgyob b4GSI85iTShp4PevShZtYdhh/H1RkBwrfeo+KQdhtYrxZzYCiJlJnPm5wo4QOe0zD4i8xs/C3Fvu Sye6nmITirJhjXlp2ispb+Q98HrDKfggB4rVrHgciVvVhHZaEExCMv/WsotMLWZbAd1rMvh6SrGG rsVl1zmWJamTPbuHlKNU0Rw1XMIc6bCsd/7k28r0EVc7MZpux0XbvTvG2xpyT7yPgD8iI/aww/NG so9I+GeYl4Rw2Jj/qhLoe04ukJFv/Tp5IyO/T3gU9W8chI/wOqvmzPY+RDnt3J8RvMmvHMQfx1jS ZwuYclNTBGg7n14M2XBfbqdUq1vjPelenKSF1ZvlIBrsuy550JllGeztL/F/8dPzO52FCFHCTQ72 UWa/ZR4GQqT8qcz3mU8LivKycq14SOkwQpy9cn1EP+UnmtiDalGuW5Vuc3uZ8xAKAvw3UWXkhgXK fiUcvYEQAuNvqOJlI53LwpYHXlj45IyytixlEI+7bcel5A9P1F8fmbU850Z5evLVY+0aboVkVfTx J4lHeOY1EK1aYHZuG/0dCgJMJigknBppMpVjMo1b4p6cI/ACSuLD3k60Lr7TWrSMb8We7h58+Qg7 MeYjcQ2uinyncWzBIicwfGgxpJZDmZIeliVpf4RB7bEtQ83O10K4CL1MR/EAA4Mq1//UEjZ7jfx2 doRF/wuc7u+Q7RcKKQmKIH4lymjuMUhu2ei9+bJ2vy6VvKgcjuN1HZrGlhyyRur9yiPoYnQqLfrv kxKay0W+uK5zDLP9QBpqPTJmdx1cIPCGktNws8G0RvqGL7AE+gEVN9ItKzOsa8s/Nmd8J8Bje8G7 IANdpNkbPvFYMKLuEqH6fXshSypnejzFM7NcZqEAsBudXayWjTZ3K8/8J6f9L3WRwObG+iU9R4bf Ba9hd3yGLeC72MhIQzUJRZlIF9BPqSF5K76U0f6G80v9ATQ2twjfXRAqsOVhiasWycgb7WfnJBIx PT5vWgDcsl9NqDlFcSsSIp3PanA2MSU8K5j9jpJO7A2BbiiWdYgh9jSnnPEkfw6Z78UJ87NC5B+i QiPkYoUM6xzXXPBYAsrtYbD50gTbYuKkgQ9xP61Q9WGf+kIIu7H+HaTpC6sGy3xFCTFSASNbJFxp 80wQuwRwf0wqBlpbdW0vmTOApgvA8JL4hfjLKgiZxkHgVvLgIAvOzjzsce3+f+t/cyOEiGCf4w0u 3a37p7jfZTOHKZW8Al1aDYvV1EPKh9jXRSj1BGPFNB2NkMFMSABM8Jx+THWJnBE0GI8JgM6aPzpp LUaa5iivVtJCybd1/csGirM3slFxMcwUDg4UZzlgj+24nlOSYudas8yM3jMsH0wAuWYpkGvtOriU DYYEgW7QEkXVe2YlpDZMfj9Rpm2bkwCOcYExmf1N/N5jTqd+bIDVAKhxFRzH3IwikL8pfSNYlZWF oHEWox7Y+GdVkDj1pgzT+TqWvllUnFD9kZLCeA6Idq1zRx9H/NyI0ZaWMdvY1l3C2qFcZXTiiwv3 Vvn1dEeaJac/v6f0/qJFv8dJIxDhpB7TqtGfW9Ax2AEWuio7oERusus9HOi2UyzanKDbEQSx51He L/Sa9bl0TtO5jlDkshmULVv6+ttOqsyHIxL67V1LS14zcU4iK+bBhWC9Tp6jGxnkET1gcMloPLy6 Ta66CTwK021dEuWrqPnSjZIFcmxrejMh+mgn2xc3WZipLLTwDuCpJAPiIVy4ARBzLpieRyD5DrXu Y5B/VK5FYyvnWuZh/5J6aMQkvcRATa+YOS79Keic50RpPSuUr2RiLWczVGxN0jO0kq3OipFCBsWc ap4KNcPtpwTgKoZ5MF59+WOF94s+QvG8e68ISYCJg0iubOZMXulKyEksPRxY+D2m6t1kEJMTaV96 hPsfvOuZTjAi1hib2y2WsU3V2/4yNseFeCmzEf8rlLXr21atAu83Uzm0SW3ZoTAPL7x0r2xq71D3 Gd6qrwItFnjHWSI1q+TjLQsCAnjvDhB3+4fy8f+r+A8OMXsmC3NF9XoaJo5ZF5NHq8LbMknSSTnP RCNlS/2GOBtIHepUmcO00NDOESz4PZo0JWWEl/9zMDH5oK1rzEO1/y4Q0KGIY8BvBg1Eweufvjni d5ydLY/gJrpw3tRikmN0W15YsT5cS43s2xSnbIED+EIzZ4P9l5dI2uohXM+ufA/WEyzDbs+DtucW slGfooU7GB7JAWP6n84xfBhtEXi+/Ge7Jw90hRpeXbcX51QOZTANGSu6bP6CvHp/5wy8cyqoMD8n HuGQa0lzaPvbk3c92VMvltfrtZ/p6gYYo+c6GseA/FPzQ2LzavyoKgcbCDyYIdeeKYuS6ifPtrSI b4iOlTnqyQhhOJ9NglCkloVmy/nZTdLEHCwRdvIncMST7XIZxPmMtCAQ+eQenfZwUzerfB9AJLCF PwVAbdaJlcq85rbIEGRmM/zTAccDi1LIEkWddtVNF8x5KkB9VZR/ejX0UVp3B96lgocbp4v0/h4w kMLTVzlWGU0g/9EwTeotJnL/FQxszdwVw/2n+PTicwN5Eo2V6rZbOWFGxvr+wttCQe3/KLtS83O7 9H+jGMbj9xpKKCuifetASe7s9MoH4johvpsXLQ/pWJBXXTRtD0Rh8NHz1Ux7LGbAVTZ8B7iShKaL OrjlfCP35jGtrc0jZPzx7ol6Lyesw+k5m5AGDGCQkm0d+VPr9IFQx0eNsjBtwF2fXZZWOgjleeuw GFLrBQ0BUkAAALcefcHwM9moXMwMYf8qDkIhNiChOqBpDpB/v7CRKjnOF/Ggf1PXNcoJEbC6jvGX OkhSnWdavNhkukDpQhE+pddM+tRQBz+l+InLQRydqZOhiY1U0gC7LAWsFrRmvtQ4JK7W2P1HLlZ9 ZYJf6ggh4FZmaQp7WqbNSaqc1W3CyLf2FqRlWc5xvIWBqqEyi5VOeAWPETgTUv1FXKF4pHIWapRS WXOI56++rtzYRn+TIcyICMd2r0SthrlhkuqncWxCTS/ahM5BLirHQxaCaMccdouaiJk7TRaIYomr v+KuGi12wIBwhRQstfg4kOaHEOkKEupIUZIiVQuG2d/H1gLAounW00wPwLw9ZsGEZ99skayuJurE 4Dx+LQ/C1QVbhmp4ZfD9BSEC2JNbjPBYduUhbAFQPXrxk16lvbIKt37m6V8L2aEkyoR14wYo1TE1 wIBTWfa0gs91ZAEph6NvFK8Hrn0JkSHdl3nCKVoor34xIWQsomOmGPYD4uZI8pnTa03nWD1BlZuJ sXCSZ9ZIIc/AEr+x8VoXA0ykW8yy5wLFIv23MC3K/DcrcewsHbAT0VpqSG0MjH+kK8GX0BnMjAqx zInzQ96PnI8UtbrTsWZGJybGRRXlaNCvWS4g+gxTOZ/mal/XeagKBnMk6U8TNJ5teCYr1nvJTl2I 23hRi3lBlVJF8wB6wvHYHCkqYnPFArIfP659NsNGXtF6ECPi7kth8BwnEywJ6lmX2Tx/+scfYYg7 mnbe3HKCKAy7cIYa934lTAiz6iEsfhCU3QaDDALnETdndrbPMlWsBxAde1SlgF4z7KXl5RUrxwzg 7Yn5zTjgbxl2dgu03xyQhUAcX/YrPdw3m1y9VrA238fP4xG4IyoG1QwVhnCMAjBaD7b0Sz5eTGXg LypuqQ6PGCPP3Aq5Zs6FbnALQr9ksVophsdbFzN4DXPKz0j3baxeh+0qIDcsTKpvGx9lzQuyMfww RBGSx1SAzQesf8+5H175+iv8aT2ZuxrZzxS7qlTbg0EFi4csjbWjVFn7or/mxIitcQE+8aExDO5D SuR401iS0jItHBIs0bxAURjc3xWNkfryBwMooXN25qxO46X5nkHOK5vDdj3mPP5vLTcniDtkmrx6 JtQ1otbQMeTdtAqnb1Nww6FQchK+HTYlcNhNSTC/r2Yk1A4oAt9D06DHEQgRCfQpVfe0WzjCJ8bb Fm42IAMeYTGsnq6aq4PuEE4UsxtEWaOkmzWWiHcz22Qq0k3j6ODolX1AX3GWa91NBeG3FkF35MSp hWB7sAEALX+eCLehmgVJPID9cHPGSK2wJ44Wqya/Vev695NAkIfFxY/8yNtkPQ7zA46J7Ed86AdW uoMoNYrH60jGpb4ELiCJILVhxOsD8daMxDxwOfMSf77F6adbbzPF0e371ZB1YGioPZjiY3pl01K5 tDJ2+8g4Lva9uUDfCSR/lzwSkZSX2ali41KB1cTL0bpYb3aTiwnK4xbJlI1qkZBkruf0BclKIY55 rgJY9v9sMRjZUW/kJuDM8d1rGgx/jTzTfN4BIyUzmJUTwoAP31mpfXbjNYd5O6kcbZhRTLltn4oX nCu+IMGQTUr/N4VxhdRyVr633/JNc9eDjgDR31j4nY57rhZ9QGfNRMkBea1n/eMcbxF41OENByhX fVdOpzR8OtAkQWwKSyT3oWmJBaKZKu2IWRJKC9q4kYIsOpHSjt2ZKjGpZMGZyfNSCKYE9Rcsq1qs tSiWuI9IcmzF47/m7rpu1bHvlgqXu+I+lxpKSkqMyhoZ8j+ozamzdDyvx9QyKZ8KqNcDvngwS+dV mhjLoWLU1lB57uvzSGQ8eCmN20yu1k80W3RWdTG8hQTHcvxcxg8hCRhemZXIYpUopZC+HBXY44wZ v8YyaDSx3K9LUXb4+JfsyfE5XYs2ctVU0/5LXbl/9d3w0mXB7Xyle951Kzzog3bLDwHFtxf6kqnI LSQIemFoqIuaj/keYDMEI7pNrDy/SfH+xdGytA0EmnTlc6rEKXvgq4+Nd1G1ov0ezzy+LRx6vWvp VRe9ZYN2Tz61bGnG/iDKlHBqko4L3ucuuRU0KCcup3tjBxLFrJGtKtazyVci9Y4cQMBj89Q2sfyM iq6j/JkzvOemMWUe4PRTssr6Z+pfVq7Un/fj+GvNhFhGl0AleApWsqfZPbMZNUTG/K9DHGRSjMQr QRLoEsfijIjOFEYzSSetc0/mEY9wj4BJS61JjcPqI0yss5QHztSlZgd7BjiWHB3yHsSbJr4MbxMG nwieMO8SSsd0hQLqXoaqUihg763Zaeo6dB3CpyUbuFmH/OPoT7qEulCmGGccbGqszdzMDhekJeKM l5ZUsgc+bqazptBortBC/apRRRpr01EM2MF7HanlT+XIzDffO9mqd3P7r5nUr8gaLwKEm0+Kly0c t1ZU80CI2CAkAmjqDbmhgQSA91C9m8JsYlkrnWOwszgTWXGIJVb1Dp/kX6e9NiFdz68oLt3l7rqB PcoYq3wA/4qWpRa1lSCHXzoK7ipiICCZUnBYFTCIdoxo0g0SOxCPfahcLfjKOc3fe7oAp4TklxvI DXhJETIwnA9kH5QPjMNCqzr+K2OG8KwNavjPyw/CPMXAsXStvmPYgO/Cpyh4c4/od4vzw0tbitXQ AG4HbsBVSP/ZhU36dyQKJCM6HQzYZytPUzxa1o2uyyemVe5RtdhpVEwvdGeZy7sivuokF3c+ct/O F3nn4Ma7GSeDJbrkTNgQtEJeBHglfUnoVZm9PURKAFLYYVkxk+ZVdV+/5mlwRPCCwBR7H6nF3qhp B//zdFhCVTWWxsuF1+DOTIjmGcu0G8FP3QDJ06h/mNCJGdV9JDc9x9hR5HF6EsDA7mNRQG1RA4xT RRZfsBm+4XGN7s5BD2nw4L3L93lSG8uTM+FNHrwd9aa+YekL6/ivKu3B7zT38AgmIivfuCyk3Uum kJ8JEzC4ar3+EJawv5o4ZDq3eJsDtaw6gROD3jw+euZKOgHHYO6CcDv8/p9tOiMiMEy8dvVZgiAe iThi/LMFdQcOspPE8NgVFWKpLtU67kJsVIWkU8fIhLUrF54OWy82OM4eavPnm9PcpieUIx44Os4G nFukBiKNhcArApabpWVqRJAI0pO9/K0iQkuEZUGuUT4segd7Gw54iEsAvdPd6WS/pvMxBdQcQ/lO 7S0KfzkgjrNw54OV+mN3sg== `protect end_protected

mit

ca4938449d27ddff50df4f9606be9925

wltr/cern-fgclite

critical_fpga/src/rtl/cf/debug_serial.vhd

------------------------------------------------------------------------------- --! @file debug_serial.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2015-01-20 --! @brief Debugging serial interface. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; --! @brief Entity declaration of debug_serial --! @details --! Provide a serial debugging interface over UART. entity debug_serial is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Debugging interface --! @{ --! TX start flag start_i : in std_ulogic; --! Data input debug_i : in std_ulogic_vector(7 downto 0); --! Data input enable debug_en_i : in std_ulogic; --! Data output debug_o : out std_ulogic_vector(7 downto 0); --! Data output enable debug_en_o : out std_ulogic; --! @} --! @name Serial communication --! @{ --! Serial receiver rx_i : in std_ulogic; --! Serial transmitter tx_o : out std_ulogic); --! @} end entity debug_serial; --! RTL implementation of debug_serial architecture rtl of debug_serial is --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal tx_data : std_ulogic_vector(7 downto 0); signal tx_data_en : std_ulogic; signal tx_done : std_ulogic; signal fifo_rd_en : std_ulogic; signal fifo_empty : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Signal Assignments --------------------------------------------------------------------------- fifo_rd_en <= (start_i or tx_done) and (not fifo_empty); --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- --! FIFO fifo_inst : entity work.fifo_tmr generic map ( depth_g => 256, width_g => 8) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, wr_en_i => debug_en_i, data_i => debug_i, done_o => open, full_o => open, wr_busy_o => open, rd_en_i => fifo_rd_en, data_o => tx_data, data_en_o => tx_data_en, empty_o => fifo_empty, rd_busy_o => open); --! Serial transmitter uart_tx_inst : entity work.uart_tx generic map ( data_width_g => 8, parity_g => 0, stop_bits_g => 1, num_ticks_g => 156) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, data_i => tx_data, data_en_i => tx_data_en, busy_o => open, done_o => tx_done, tx_o => tx_o); --! Serial receiver uart_rx_inst : entity work.uart_rx generic map ( data_width_g => 8, parity_g => 0, stop_bits_g => 1, num_ticks_g => 156) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, rx_i => rx_i, data_o => debug_o, data_en_o => debug_en_o, error_o => open); end architecture rtl;

mit

fd5c1aa39591bb21324d015a0acfb869

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_2AXI.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 1; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 0; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6; constant FLOAT_IMPLEMENT : natural := 0; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FDIV_DELAY; constant CACHE_N_BANKS_W : natural := 2; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

18935be0c51b0848988ba5dbd1b5615c

preusser/q27

src/vhdl/PoC/common/components.vhdl

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- -- ============================================================================ -- Authors: Patrick Lehmann -- -- Package: Common primitives described as a function -- -- Description: -- ------------------------------------ -- This packages describes common primitives like flip flops and multiplexers -- as a function to use them as one-liners. -- -- License: -- ============================================================================ -- Copyright 2007-2015 Technische Universitaet Dresden - Germany -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library PoC; use PoC.utils.all; PACKAGE components IS -- FlipFlop functions function ffdre(q : STD_LOGIC; d : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- D-FlipFlop with reset and enable function ffdre(q : STD_LOGIC_VECTOR; d : STD_LOGIC_VECTOR; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR; -- D-FlipFlop with reset and enable function ffdse(q : STD_LOGIC; d : STD_LOGIC; set : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- D-FlipFlop with set and enable function fftre(q : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC; -- T-FlipFlop with reset and enable function ffrs(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC; -- RS-FlipFlop with dominant rst function ffsr(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC; -- RS-FlipFlop with dominant set -- adder function inc(value : STD_LOGIC_VECTOR; increment : NATURAL := 1) return STD_LOGIC_VECTOR; function inc(value : UNSIGNED; increment : NATURAL := 1) return UNSIGNED; function inc(value : SIGNED; increment : NATURAL := 1) return SIGNED; function dec(value : STD_LOGIC_VECTOR; decrement : NATURAL := 1) return STD_LOGIC_VECTOR; function dec(value : UNSIGNED; decrement : NATURAL := 1) return UNSIGNED; function dec(value : SIGNED; decrement : NATURAL := 1) return SIGNED; -- negate function neg(value : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; -- calculate 2's complement -- counter function upcounter_next(cnt : UNSIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : NATURAL := 0) return UNSIGNED; function upcounter_equal(cnt : UNSIGNED; value : NATURAL) return STD_LOGIC; function downcounter_next(cnt : SIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : INTEGER := 0) return SIGNED; function downcounter_equal(cnt : SIGNED; value : INTEGER) return STD_LOGIC; function downcounter_neg(cnt : SIGNED) return STD_LOGIC; -- shift/rotate registers function sr_left(q : STD_LOGIC_VECTOR; i : STD_LOGIC) return STD_LOGIC_VECTOR; function sr_right(q : STD_LOGIC_VECTOR; i : STD_LOGIC) return STD_LOGIC_VECTOR; function rr_left(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function rr_right(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; -- compare function comp(value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function comp(value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED; function comp(value1 : SIGNED; value2 : SIGNED) return SIGNED; function comp_allzero(value : STD_LOGIC_VECTOR) return STD_LOGIC; function comp_allzero(value : UNSIGNED) return STD_LOGIC; function comp_allzero(value : SIGNED) return STD_LOGIC; function comp_allone(value : STD_LOGIC_VECTOR) return STD_LOGIC; function comp_allone(value : UNSIGNED) return STD_LOGIC; function comp_allone(value : SIGNED) return STD_LOGIC; -- multiplexing function mux(sel : STD_LOGIC; sl0 : STD_LOGIC; sl1 : STD_LOGIC) return STD_LOGIC; function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function mux(sel : STD_LOGIC; us0 : UNSIGNED; us1 : UNSIGNED) return UNSIGNED; function mux(sel : STD_LOGIC; s0 : SIGNED; s1 : SIGNED) return SIGNED; end; package body components is -- d-flipflop with reset and enable function ffdre(q : STD_LOGIC; d : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is begin return ((d and en) or (q and not en)) and not rst; end function; function ffdre(q : STD_LOGIC_VECTOR; d : STD_LOGIC_VECTOR; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC_VECTOR is begin return ((d and (q'range => en)) or (q and not (q'range => en))) and not (q'range => rst); end function; -- d-flipflop with set and enable function ffdse(q : STD_LOGIC; d : STD_LOGIC; set : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is begin return ((d and en) or (q and not en)) or set; end function; -- t-flipflop with reset and enable function fftre(q : STD_LOGIC; rst : STD_LOGIC := '0'; en : STD_LOGIC := '1') return STD_LOGIC is begin return ((not q and en) or (q and not en)) and not rst; end function; -- rs-flipflop with dominant rst function ffrs(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC is begin return (q or set) and not rst; end function; -- rs-flipflop with dominant set function ffsr(q : STD_LOGIC; rst : STD_LOGIC := '0'; set : STD_LOGIC := '0') return STD_LOGIC is begin return (q and not rst) or set; end function; -- adder function inc(value : STD_LOGIC_VECTOR; increment : NATURAL := 1) return STD_LOGIC_VECTOR is begin return std_logic_vector(inc(unsigned(value), increment)); end function; function inc(value : UNSIGNED; increment : NATURAL := 1) return UNSIGNED is begin return value + increment; end function; function inc(value : SIGNED; increment : NATURAL := 1) return SIGNED is begin return value + increment; end function; function dec(value : STD_LOGIC_VECTOR; decrement : NATURAL := 1) return STD_LOGIC_VECTOR is begin return std_logic_vector(dec(unsigned(value), decrement)); end function; function dec(value : UNSIGNED; decrement : NATURAL := 1) return UNSIGNED is begin return value + decrement; end function; function dec(value : SIGNED; decrement : NATURAL := 1) return SIGNED is begin return value + decrement; end function; -- negate function neg(value : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is begin return std_logic_vector(inc(unsigned(not value))); -- 2's complement end function; -- counter function upcounter_next(cnt : UNSIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : NATURAL := 0) return UNSIGNED is begin if (rst = '1') then return to_unsigned(init, cnt'length); elsif (en = '1') then return cnt + 1; else return cnt; end if; end function; function upcounter_equal(cnt : UNSIGNED; value : NATURAL) return STD_LOGIC is begin -- optimized comparison for only up counting values return to_sl((cnt and to_unsigned(value, cnt'length)) = value); end function; function downcounter_next(cnt : SIGNED; rst : STD_LOGIC; en : STD_LOGIC := '1'; init : INTEGER := 0) return SIGNED is begin if (rst = '1') then return to_signed(init, cnt'length); elsif (en = '1') then return cnt - 1; else return cnt; end if; end function; function downcounter_equal(cnt : SIGNED; value : INTEGER) return STD_LOGIC is begin -- optimized comparison for only down counting values return to_sl((cnt nor to_signed(value, cnt'length)) /= value); end function; function downcounter_neg(cnt : SIGNED) return STD_LOGIC is begin return cnt(cnt'high); end function; -- shift/rotate registers function sr_left(q : STD_LOGIC_VECTOR; i : std_logic) return STD_LOGIC_VECTOR is begin return q(q'left - 1 downto q'right) & i; end function; function sr_right(q : STD_LOGIC_VECTOR; i : std_logic) return STD_LOGIC_VECTOR is begin return i & q(q'left downto q'right - 1); end function; function rr_left(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is begin return q(q'left - 1 downto q'right) & q(q'left); end function; function rr_right(q : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is begin return q(q'right) & q(q'left downto q'right - 1); end function; -- compare functions -- return value 1- => value1 < value2 (difference is negative) -- return value 00 => value1 = value2 (difference is zero) -- return value -1 => value1 > value2 (difference is positive) function comp(value1 : STD_LOGIC_VECTOR; value2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is begin report "Comparing two STD_LOGIC_VECTORs - implicit conversion to UNSIGNED" severity WARNING; return std_logic_vector(comp(unsigned(value1), unsigned(value2))); end function; function comp(value1 : UNSIGNED; value2 : UNSIGNED) return UNSIGNED is begin if (value1 < value2) then return "10"; elsif (value1 = value2) then return "00"; else return "01"; end if; end function; function comp(value1 : SIGNED; value2 : SIGNED) return SIGNED is begin if (value1 < value2) then return "10"; elsif (value1 = value2) then return "00"; else return "01"; end if; end function; function comp_allzero(value : STD_LOGIC_VECTOR) return STD_LOGIC is begin return comp_allzero(unsigned(value)); end function; function comp_allzero(value : UNSIGNED) return STD_LOGIC is begin return to_sl(value = (value'range => '0')); end function; function comp_allzero(value : SIGNED) return STD_LOGIC is begin return to_sl(value = (value'range => '0')); end function; function comp_allone(value : STD_LOGIC_VECTOR) return STD_LOGIC is begin return comp_allone(unsigned(value)); end function; function comp_allone(value : UNSIGNED) return STD_LOGIC is begin return to_sl(value = (value'range => '1')); end function; function comp_allone(value : SIGNED) return STD_LOGIC is begin return to_sl(value = (value'range => '1')); end function; -- multiplexing function mux(sel : STD_LOGIC; sl0 : STD_LOGIC; sl1 : STD_LOGIC) return STD_LOGIC is begin return (sl0 and not sel) or (sl1 and sel); end function; function mux(sel : STD_LOGIC; slv0 : STD_LOGIC_VECTOR; slv1 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is begin return (slv0 and not (slv0'range => sel)) or (slv1 and (slv1'range => sel)); end function; function mux(sel : STD_LOGIC; us0 : UNSIGNED; us1 : UNSIGNED) return UNSIGNED is begin return (us0 and not (us0'range => sel)) or (us1 and (us1'range => sel)); end function; function mux(sel : STD_LOGIC; s0 : SIGNED; s1 : SIGNED) return SIGNED is begin return (s0 and not (s0'range => sel)) or (s1 and (s1'range => sel)); end function; END PACKAGE BODY;

agpl-3.0

8201e53a7d6b1d4f7e821c914f8f1b2d

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_rx_deglitcher.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_rx_deglitcher | -- | --------------------------------------------------------------------------------------------------- -- File wf_rx_deglitcher.vhd | -- | -- Description The unit applies a glitch filter to the nanoFIP FIELDRIVE input FD_RXD. | -- It is capable of cleaning glitches up to c_DEGLITCH_THRESHOLD uclk ticks long. | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 14/02/2011 | -- Version v0.03 | -- Depends on wf_reset_unit | ---------------- | -- Last changes | -- 07/08/2009 v0.01 PAS Entity Ports added, start of architecture content | -- 23/08/2010 v0.02 EG code cleaned-up+commented | -- 14/02/2011 v0.03 EG complete change, no dependency on osc; | -- fd_rxd deglitched right at reception | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_rx_deglitcher --================================================================================================= entity wf_rx_deglitcher is port( -- INPUTS -- nanoFIP User Interface general signal uclk_i : in std_logic; -- 40 MHz clock -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- nanoFIP FIELDRIVE (synchronized with uclk) fd_rxd_a_i : in std_logic; -- receiver data -- OUTPUTS -- Signals to the wf_rx_deserializer unit fd_rxd_filt_o : out std_logic; -- filtered output signal fd_rxd_filt_edge_p_o : out std_logic; -- indicates an edge on the filtered signal fd_rxd_filt_f_edge_p_o : out std_logic);-- indicates a falling edge on the filtered signal end wf_rx_deglitcher; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_rx_deglitcher is signal s_fd_rxd_synch : std_logic_vector (1 downto 0); signal s_fd_rxd_filt, s_fd_rxd_filt_d1 : std_logic; signal s_fd_rxd_filt_r_edge_p, s_fd_rxd_filt_f_edge_p : std_logic; signal s_filt_c : unsigned (3 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- FD_RXD synchronization -- --------------------------------------------------------------------------------------------------- -- Synchronous process FD_RXD_synchronizer: Synchronization of the nanoFIP FIELDRIVE input -- FD_RXD to the uclk, using a set of 2 registers. FD_RXD_synchronizer: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_fd_rxd_synch <= (others => '0'); else s_fd_rxd_synch <= s_fd_rxd_synch(0) & fd_rxd_a_i; end if; end if; end process; --------------------------------------------------------------------------------------------------- -- Deglitching -- --------------------------------------------------------------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- Synchronous process FD_RXD_deglitcher: the output signal s_fd_rxd_filt is updated only -- after the accumulation of a sufficient (c_DEGLITCH_THRESHOLD + 1) amount of identical bits. -- The signal is therefore cleaned of any glitches up to c_DEGLITCH_THRESHOLD uclk ticks long. FD_RXD_deglitcher: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_filt_c <= to_unsigned (c_DEGLITCH_THRESHOLD, s_filt_c'length) srl 1;-- middle value s_fd_rxd_filt <= '0'; s_fd_rxd_filt_d1 <= '0'; else -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- if s_fd_rxd_synch(1) = '0' then -- arrival of a '0' if s_filt_c /= 0 then -- counter updated s_filt_c <= s_filt_c - 1; else s_fd_rxd_filt <= '0'; -- output updated end if; -- if counter = 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- elsif s_fd_rxd_synch(1) = '1' then -- arrival of a '1' if s_filt_c /= c_DEGLITCH_THRESHOLD then s_filt_c <= s_filt_c + 1; -- counter updated else s_fd_rxd_filt <= '1'; -- output updated end if; -- if counter = c_DEGLITCH_THRESHOLD end if; s_fd_rxd_filt_d1 <= s_fd_rxd_filt; -- used for the edges detection end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - -- Concurrent signal assignments s_fd_rxd_filt_r_edge_p <= (not s_fd_rxd_filt_d1) and s_fd_rxd_filt; -- pulse upon detection -- of a falling edge s_fd_rxd_filt_f_edge_p <= s_fd_rxd_filt_d1 and (not s_fd_rxd_filt); -- pulse upon detection -- of a rising edge fd_rxd_filt_edge_p_o <= s_fd_rxd_filt_f_edge_p or s_fd_rxd_filt_r_edge_p; fd_rxd_filt_f_edge_p_o <= s_fd_rxd_filt_f_edge_p; fd_rxd_filt_o <= s_fd_rxd_filt; end rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

6deff1c08ea25fefb50fa3dcfb45d4b5

wltr/cern-fgclite

critical_fpga/src/rtl/cf/ab.vhd

------------------------------------------------------------------------------- --! @file ab.vhd --! @author Johannes Walter <johannes.walter@cern.ch> --! @copyright CERN TE-EPC-CCE --! @date 2014-07-08 --! @brief Analogue board control and filters. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.ab_pkg.all; use work.nf_pkg.all; use work.ads1281_filter_pkg.all; --! @brief Entity declaration of ab --! @details --! This component controls the analogue board switches, DAC and ADCs. It --! also provides FIR filter implementations for the ADCs and has an internal --! pattern generator for test purposes. entity ab is port ( --! @name Clock and resets --! @{ --! System clock clk_i : in std_ulogic; --! Asynchronous active-low reset rst_asy_n_i : in std_ulogic; --! Synchronous active-high reset rst_syn_i : in std_ulogic; --! @} --! @name Analogue board interface --! @{ --! Inputs ab_i : in ab_in_t; --! Outputs ab_o : out ab_out_t; --! @} --! @name Internal interface --! @{ --! Millisecond strobe ms_strobe_i : in std_ulogic; --! Millisecond strobe indicating start of cycle ms_0_strobe_i : in std_ulogic; --! Commands command_i : in nf_command_t; --! SEFI detector sefi_o : out std_ulogic_vector(5 downto 0); --! Voltage reference when ramping down pf_vref_i : in std_ulogic_vector(15 downto 0); --! Voltage reference enable pf_vref_en_i : in std_ulogic; --! Voltage reference override pf_vref_ovr_i : in std_ulogic; --! @} --! @name ADC results --! @{ --! ADC VS result adc_vs_o : out std_ulogic_vector(23 downto 0); --! ADC VS result enable adc_vs_en_o : out std_ulogic; --! ADC IA result adc_ia_o : out std_ulogic_vector(23 downto 0); --! ADC IA result enable adc_ia_en_o : out std_ulogic; --! ADC IB result adc_ib_o : out std_ulogic_vector(23 downto 0); --! ADC IB result enable adc_ib_en_o : out std_ulogic; --! @} --! @name Accumulator results --! @{ --! Accumulator VS result acc_vs_o : out std_ulogic_vector(31 downto 0); --! Accumulator VS result enable acc_vs_en_o : out std_ulogic; --! Accumulator IA result acc_ia_o : out std_ulogic_vector(31 downto 0); --! Accumulator IA result enable acc_ia_en_o : out std_ulogic; --! Accumulator IB result acc_ib_o : out std_ulogic_vector(31 downto 0); --! Accumulator IB result enable acc_ib_en_o : out std_ulogic); --! @} end entity ab; --! RTL implementation of ab architecture rtl of ab is --------------------------------------------------------------------------- --! @name Types and Constants --------------------------------------------------------------------------- --! @{ type acc_result_t is array (0 to 2) of std_ulogic_vector(27 downto 0); type sefi_mode_t is array (0 to 5) of std_ulogic_vector(1 downto 0); --! @} --------------------------------------------------------------------------- --! @name Internal Wires --------------------------------------------------------------------------- --! @{ signal adc_m0 : std_ulogic_vector(2 downto 0); signal adc_m1 : std_ulogic_vector(2 downto 0); signal adc_result : ads1281_filter_result_t; signal adc_result_en : std_ulogic_vector(2 downto 0); signal acc_result : acc_result_t; signal acc_result_en : std_ulogic_vector(2 downto 0); signal ab : ab_out_t; signal sample_strb : std_ulogic; signal adc_m : std_ulogic_vector(5 downto 0); signal sefi_in : std_ulogic_vector(5 downto 0); signal sefi_mode : sefi_mode_t; signal vref : std_ulogic_vector(15 downto 0); signal vref_en : std_ulogic; --! @} begin -- architecture rtl --------------------------------------------------------------------------- -- Outputs --------------------------------------------------------------------------- -- Power up analogue board ab_o.pwr_on_n <= '0'; -- Start temperature control on analogue board ab_o.temp_stop <= '0'; ab_o.cal_dac <= ab.cal_dac; ab_o.cal_offset <= ab.cal_offset; ab_o.cal_vref_p <= ab.cal_vref_p; ab_o.cal_vref_n <= ab.cal_vref_n; ab_o.adc_vs_rst_n <= ab.adc_vs_rst_n; ab_o.sw_in_vs <= ab.sw_in_vs; ab_o.adc_a_rst_n <= ab.adc_a_rst_n; ab_o.sw_in_a <= ab.sw_in_a; ab_o.adc_b_rst_n <= ab.adc_b_rst_n; ab_o.sw_in_b <= ab.sw_in_b; adc_vs_o <= adc_result(0); adc_vs_en_o <= adc_result_en(0); adc_ia_o <= adc_result(1); adc_ia_en_o <= adc_result_en(1); adc_ib_o <= adc_result(2); adc_ib_en_o <= adc_result_en(2); acc_vs_o(31 downto 28) <= (31 downto 28 => acc_result(0)(acc_result(0)'high)); acc_vs_o(27 downto 0) <= acc_result(0); acc_vs_en_o <= acc_result_en(0); acc_ia_o(31 downto 28) <= (31 downto 28 => acc_result(1)(acc_result(1)'high)); acc_ia_o(27 downto 0) <= acc_result(1); acc_ia_en_o <= acc_result_en(1); acc_ib_o(31 downto 28) <= (31 downto 28 => acc_result(2)(acc_result(2)'high)); acc_ib_o(27 downto 0) <= acc_result(2); acc_ib_en_o <= acc_result_en(2); --------------------------------------------------------------------------- -- Signal Assignments --------------------------------------------------------------------------- adc_m0 <= ab_i.adc_vs(0) & ab_i.adc_a(0) & ab_i.adc_b(0); adc_m1 <= ab_i.adc_vs(1) & ab_i.adc_a(1) & ab_i.adc_b(1); adc_m <= ab_i.adc_b & ab_i.adc_a & ab_i.adc_vs; sefi_mode(0) <= command_i.sefi_test_vs_m0; sefi_mode(1) <= command_i.sefi_test_vs_m1; sefi_mode(2) <= command_i.sefi_test_ia_m0; sefi_mode(3) <= command_i.sefi_test_ia_m1; sefi_mode(4) <= command_i.sefi_test_ib_m0; sefi_mode(5) <= command_i.sefi_test_ib_m1; vref <= pf_vref_i when pf_vref_ovr_i = '1' else command_i.v_ref; vref_en <= pf_vref_en_i when pf_vref_ovr_i = '1' else ms_0_strobe_i; --------------------------------------------------------------------------- -- Instances --------------------------------------------------------------------------- --! SEFI detector test sefi_test_gen : for i in 0 to 5 generate sefi_test_inst : entity work.sefi_detector_test port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, ms_0_strobe_i => ms_0_strobe_i, en_i => command_i.vs_cmd(0), mode_i => sefi_mode(i), strb_i => sample_strb, adc_i => adc_m(i), test_o => sefi_in(i)); end generate sefi_test_gen; --! SEFI detectors sefi_detector_gen : for i in 0 to 5 generate sefi_detector_inst : entity work.sefi_detector generic map ( num_g => 30) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => ms_0_strobe_i, en_i => sample_strb, sig_i => sefi_in(i), sefi_o => sefi_o(i)); end generate sefi_detector_gen; --! Analogue board DAC interface max5541_interface_inst : entity work.max5541_interface port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, data_i => vref, data_en_i => vref_en, busy_o => open, done_o => open, cs_o => ab_o.dac_cs, sclk_o => ab_o.dac_sclk, din_o => ab_o.dac_din); --! ADS1281 filter ads1281_filter_inst : entity work.ads1281_filter port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => rst_syn_i, strb_ms_i => ms_strobe_i, strb_sample_o => sample_strb, adc_m0_i => adc_m0, adc_m1_i => adc_m1, result_o => adc_result, result_en_o => adc_result_en); --! ADS1281 result accumulator ads1281_result_accumulator_gen : for i in 0 to 2 generate ads1281_result_accumulator_inst : entity work.ads1281_result_accumulator generic map ( num_results_g => 10) port map ( clk_i => clk_i, rst_asy_n_i => rst_asy_n_i, rst_syn_i => ms_0_strobe_i, result_i => adc_result(i), result_en_i => adc_result_en(i), result_o => acc_result(i), result_en_o => acc_result_en(i)); end generate ads1281_result_accumulator_gen; --------------------------------------------------------------------------- -- Registers --------------------------------------------------------------------------- regs : process (clk_i, rst_asy_n_i) is procedure reset is begin ab.cal_dac <= '0'; ab.cal_offset <= '0'; ab.cal_vref_p <= '0'; ab.cal_vref_n <= '0'; ab.adc_vs_rst_n <= '1'; ab.sw_in_vs <= '0'; ab.adc_a_rst_n <= '1'; ab.sw_in_a <= '0'; ab.adc_b_rst_n <= '1'; ab.sw_in_b <= '0'; end procedure reset; begin -- process regs if rst_asy_n_i = '0' then reset; elsif rising_edge(clk_i) then if rst_syn_i = '1' then reset; elsif ms_0_strobe_i = '1' then case command_i.cal_source is when "00" => ab.cal_dac <= '0'; ab.cal_offset <= '1'; ab.cal_vref_n <= '0'; ab.cal_vref_p <= '0'; when "01" => ab.cal_dac <= '0'; ab.cal_offset <= '0'; ab.cal_vref_n <= '0'; ab.cal_vref_p <= '1'; when "10" => ab.cal_dac <= '0'; ab.cal_offset <= '0'; ab.cal_vref_n <= '1'; ab.cal_vref_p <= '0'; when "11" => ab.cal_dac <= '1'; ab.cal_offset <= '0'; ab.cal_vref_n <= '0'; ab.cal_vref_p <= '0'; when others => null; end case; ab.adc_vs_rst_n <= command_i.adc_vs_reset_n; ab.adc_a_rst_n <= command_i.adc_ia_reset_n; ab.adc_b_rst_n <= command_i.adc_ib_reset_n; if command_i.vs_cmd(0) = '0' then ab.sw_in_vs <= command_i.cal_vs_en; ab.sw_in_a <= command_i.cal_ia_en; ab.sw_in_b <= command_i.cal_ib_en; else ab.sw_in_vs <= '0'; ab.sw_in_a <= '0'; ab.sw_in_b <= '0'; end if; end if; end if; end process regs; end architecture rtl;

mit

f6c2aee3439e8916e76674475992ad0d

malkadi/FGPU

bitstreams/settings_and_utilization/V2_4CUs_float.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 2; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 11; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 0; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 1; constant FSQRT_IMPLEMENT : integer := 1; constant UITOFP_IMPLEMENT : integer := 1; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant MAX_FPU_DELAY : integer := FSQRT_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 4; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

079a63acf9c65477bf1d4e014cd772c3

malkadi/FGPU

bitstreams/settings_and_utilization/V2_8CUs_fadd_fmul_2AXI_2CACHE_WORDS.vhd

-- libraries --------------------------------------------------------------------------------- {{{ library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use ieee.std_logic_textio.all; use std.textio.all; ------------------------------------------------------------------------------------------------- }}} package FGPU_definitions is constant N_CU_W : natural := 3; --0 to 3 -- Bitwidth of # of CUs constant LMEM_ADDR_W : natural := 10; -- bitwidth of local memory address for a single PE constant N_AXI_W : natural := 1; -- Bitwidth of # of AXI data ports constant SUB_INTEGER_IMPLEMENT : natural := 0; -- implement sub-integer store operations constant N_STATIONS_ALU : natural := 4; -- # stations to store memory requests sourced by a single ALU constant ATOMIC_IMPLEMENT : natural := 0; -- implement global atomic operations constant LMEM_IMPLEMENT : natural := 0; -- implement local scratchpad constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1 -- Bitwidth of # tag controllers per CU constant RD_CACHE_N_WORDS_W : natural := 1; constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8; constant FLOAT_IMPLEMENT : natural := 1; constant FADD_IMPLEMENT : integer := 1; constant FMUL_IMPLEMENT : integer := 1; constant FDIV_IMPLEMENT : integer := 0; constant FSQRT_IMPLEMENT : integer := 0; constant UITOFP_IMPLEMENT : integer := 0; constant FSLT_IMPLEMENT : integer := 0; constant FRSQRT_IMPLEMENT : integer := 0; constant FADD_DELAY : integer := 11; constant UITOFP_DELAY : integer := 5; constant FMUL_DELAY : integer := 8; constant FDIV_DELAY : integer := 28; constant FSQRT_DELAY : integer := 28; constant FRSQRT_DELAY : integer := 28; constant FSLT_DELAY : integer := 2; constant MAX_FPU_DELAY : integer := FADD_DELAY; constant CACHE_N_BANKS_W : natural := 3; -- Bitwidth of # words within a cache line. Minimum is 2 constant N_RECEIVERS_CU_W : natural := 6-N_CU_W; -- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is. constant BURST_WORDS_W : natural := 5; -- Bitwidth # of words within a single AXI burst constant ENABLE_READ_PRIORIRY_PIPE : boolean := false; constant FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo size to store outgoing memory requests from a CU constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0; constant FINISH_FIFO_ADDR_W : natural := 3; -- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end -- constant CRAM_BLOCKS : natural := 1; -- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only) constant CV_W : natural := 3; -- bitwidth of # of PEs within a CV constant CV_TO_CACHE_SLICE : natural := 3; constant INSTR_READ_SLICE : boolean := true; constant RTM_WRITE_SLICE : boolean := true; constant WRITE_PHASE_W : natural := 1; -- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always. -- This incrmenetation should help to balance serving the receivers constant RCV_PRIORITY_W : natural := 3; constant N_WF_CU_W : natural := 3; -- bitwidth of # of WFs that can be simultaneously managed within a CU constant AADD_ATOMIC : natural := 1; constant AMAX_ATOMIC : natural := 1; constant GMEM_N_BANK_W : natural := 1; constant ID_WIDTH : natural := 6; constant PHASE_W : natural := 3; constant CV_SIZE : natural := 2**CV_W; constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W; constant WF_SIZE_W : natural := PHASE_W + CV_W; -- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W; -- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit -- The MSB if select between local indcs or other information -- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus constant RD_FIFO_N_BURSTS_W : natural := 1; constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W; constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W; constant N_AXI : natural := 2**N_AXI_W; constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W; constant INTERFCE_W_ADDR_W : natural := 14; constant CRAM_ADDR_W : natural := 12; -- TODO constant DATA_W : natural := 32; constant BRAM18kb32b_ADDR_W : natural := 9; constant BRAM36kb64b_ADDR_W : natural := 9; constant BRAM36kb_ADDR_W : natural := 10; constant INST_FIFO_PRE_LEN : natural := 8; constant CV_INST_FIFO_W : natural := 3; constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W; constant N_PARAMS_W : natural := 4; constant GMEM_ADDR_W : natural := 32; constant WI_REG_ADDR_W : natural := 5; constant N_REG_BLOCKS_W : natural := 2; constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9 constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W; constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W; constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W; constant STAT : natural := 1; constant STAT_LOAD : natural := 0; -- cache & gmem controller constants constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10 constant N_RD_PORTS : natural := 4; constant N : natural := CACHE_N_BANKS_W; -- max. 3 constant L : natural := BURST_WORDS_W-N; -- min. 2 constant M : natural := BRMEM_ADDR_W - L; -- max. 8 -- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM -- cache size = 2^(N+L+M) words; max.=8*4KB=32KB constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W; constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W; constant N_RECEIVERS : natural := 2**N_RECEIVERS_W; constant N_CU_STATIONS_W : natural := 6; constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2; constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N; constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W; constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W; constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W; constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W; constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W; constant REG_FILE_SIZE : natural := 2**REG_ADDR_W; constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W; constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W; constant N_PARAMS : natural := 2**N_PARAMS_W; constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W; constant PHASE_LEN : natural := 2**PHASE_W; constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W; constant N_CU : natural := 2**N_CU_W; constant N_WF_CU : natural := 2**N_WF_CU_W; constant WF_SIZE : natural := 2**WF_SIZE_W; constant CRAM_SIZE : natural := 2**CRAM_ADDR_W; constant RTM_SIZE : natural := 2**RTM_ADDR_W; constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W; constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file constant Rstat_regFile_addr : natural := 0; --address of status register in the register file constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file constant N_REG_W : natural := 2; constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS; -- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W; -- new kernel descriptor ---------------------------------------------------------------- constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started constant NEW_KRNL_DESC_LEN : natural := 12; constant WG_MAX_SIZE : natural := 2**WG_SIZE_W; constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W; constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W; constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W; constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0; constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1; constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2; constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3; constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4; constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5; constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6; constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7; constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8; constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9; constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10; constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11; constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16; constant WG_SIZE_0_OFFSET : natural := 0; constant WG_SIZE_1_OFFSET : natural := 10; constant WG_SIZE_2_OFFSET : natural := 20; constant N_DIM_OFFSET : natural := 30; constant ADDR_FIRST_INST_OFFSET : natural := 0; constant ADDR_LAST_INST_OFFSET : natural := 14; constant N_WF_OFFSET : natural := 28; constant N_WG_0_OFFSET : natural := 16; constant N_WG_1_OFFSET : natural := 0; constant N_WG_2_OFFSET : natural := 16; constant WG_SIZE_OFFSET : natural := 0; constant N_PARAMS_OFFSET : natural := 28; type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0); type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0); type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1; type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0); type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0); type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem); type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor); type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0); type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0); type sl_array is array(natural range <>) of std_logic; type nat_array is array(natural range <>) of natural; type nat_2d_array is array(natural range <>, natural range <>) of natural; type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0); type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0); type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0); type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0); type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0); type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0); type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0); type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0); type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0); type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0); type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0); type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0); type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0); type real_array is array (natural range <>) of real; type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0); attribute max_fanout: integer; attribute keep: string; attribute mark_debug : string; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type; impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY; impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type; function pri_enc(datain: in std_logic_vector) return integer; function max (LEFT, RIGHT: integer) return integer; function min_int (LEFT, RIGHT: integer) return integer; function clogb2 (bit_depth : integer) return integer; --- ISA -------------------------------------------------------------------------------------- constant FAMILY_W : natural := 4; constant CODE_W : natural := 4; constant IMM_ARITH_W : natural := 14; constant IMM_W : natural := 16; constant BRANCH_ADDR_W : natural := 14; constant FAMILY_POS : natural := 28; constant CODE_POS : natural := 24; constant RD_POS : natural := 0; constant RS_POS : natural := 5; constant RT_POS : natural := 10; constant IMM_POS : natural := 10; constant DIM_POS : natural := 5; constant PARAM_POS : natural := 5; constant BRANCH_ADDR_POS : natural := 10; --------------- families constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1"; constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2"; constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3"; constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4"; constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5"; constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6"; constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7"; constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8"; constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9"; constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A"; constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B"; constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C"; constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D"; --------------- codes --RTM constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1"; constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2"; constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3"; constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4"; constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8"; --ADD constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001"; constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101"; --MUL constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000"; --BRA constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100"; --GLS constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100"; --CTL constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010"; --SHF constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001"; --LGK constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000"; constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001"; constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011"; constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100"; constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101"; constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000"; --ATO constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010"; constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001"; type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0); type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0); type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0); end FGPU_definitions; package body FGPU_definitions is -- function called clogb2 that returns an integer which has the --value of the ceiling of the log base 2 function clogb2 (bit_depth : integer) return integer is variable depth : integer := bit_depth; variable count : integer := 1; begin for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers if (bit_depth <= 2) then count := 1; else if(depth <= 1) then count := count; else depth := depth / 2; count := count + 1; end if; end if; end loop; return(count); end; impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_bv : bit_vector(DATA_W-1 downto 0); variable temp_mem : KRNL_SCHEDULER_RAM_type; begin for i in 0 to 16*32-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); -- read(init_line, temp_bv); -- temp_mem(i) := to_stdlogicvector(temp_bv); end loop; return temp_mem; end function; function max (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return LEFT; else return RIGHT; end if; end max; function min_int (LEFT, RIGHT: integer) return integer is begin if LEFT > RIGHT then return RIGHT; else return LEFT; end if; end min_int; impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is file init_file : text open read_mode is file_name; variable init_line : line; variable cram : cram_type; -- variable tmp: std_logic_vector(DATA_W-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error -- cram(i) := tmp; -- if CRAM_BLOCKS > 1 then -- for j in 1 to max(1,CRAM_BLOCKS-1) loop -- cram(j)(i) := cram(0)(i); -- end loop; -- end if; end loop; return cram; end function; impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is file init_file : text open read_mode is file_name; variable init_line : line; variable temp_mem : SLV32_ARRAY(len-1 downto 0); begin for i in 0 to file_len-1 loop readline(init_file, init_line); hread(init_line, temp_mem(i)); end loop; return temp_mem; end function; function pri_enc(datain: in std_logic_vector) return integer is variable res : integer range 0 to datain'high; begin res := 0; for i in datain'high downto 1 loop if datain(i) = '1' then res := i; end if; end loop; return res; end function; end FGPU_definitions;

gpl-3.0

c5638b1cf009292e0cff592f8a3ca1c4

dtysky/LD3320_AXI

src/VOICE_ROM_INIT/synth/VOICE_ROM_INIT.vhd

-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2 -- IP Revision: 1 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_2; USE blk_mem_gen_v8_2.blk_mem_gen_v8_2; ENTITY VOICE_ROM_INIT IS PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END VOICE_ROM_INIT; ARCHITECTURE VOICE_ROM_INIT_arch OF VOICE_ROM_INIT IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF VOICE_ROM_INIT_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_2 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); sleep : IN STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_2; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF VOICE_ROM_INIT_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF VOICE_ROM_INIT_arch : ARCHITECTURE IS "VOICE_ROM_INIT,blk_mem_gen_v8_2,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF VOICE_ROM_INIT_arch: ARCHITECTURE IS "VOICE_ROM_INIT,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=1,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=VOICE_ROM_INIT.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=64,C_READ_DEPTH_A=64,C_ADDRA_WIDTH=6,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=64,C_READ_DEPTH_B=64,C_ADDRB_WIDTH=6,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.01735 mW}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK"; ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR"; ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT"; BEGIN U0 : blk_mem_gen_v8_2 GENERIC MAP ( C_FAMILY => "zynq", C_XDEVICEFAMILY => "zynq", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 0, C_ENABLE_32BIT_ADDRESS => 0, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 1, C_BYTE_SIZE => 9, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 0, C_INIT_FILE_NAME => "no_coe_file_loaded", C_INIT_FILE => "VOICE_ROM_INIT.mem", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 0, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 0, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 0, C_WEA_WIDTH => 1, C_WRITE_MODE_A => "WRITE_FIRST", C_WRITE_WIDTH_A => 16, C_READ_WIDTH_A => 16, C_WRITE_DEPTH_A => 64, C_READ_DEPTH_A => 64, C_ADDRA_WIDTH => 6, C_HAS_RSTB => 0, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 0, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 0, C_WEB_WIDTH => 1, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 16, C_READ_WIDTH_B => 16, C_WRITE_DEPTH_B => 64, C_READ_DEPTH_B => 64, C_ADDRB_WIDTH => 6, C_HAS_MEM_OUTPUT_REGS_A => 0, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "0", C_COUNT_18K_BRAM => "1", C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.01735 mW" ) PORT MAP ( clka => clka, rsta => '0', ena => '0', regcea => '0', wea => wea, addra => addra, dina => dina, clkb => clkb, rstb => '0', enb => '0', regceb => '0', web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), addrb => addrb, dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)), doutb => doutb, injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END VOICE_ROM_INIT_arch;

mit

55c629036c4a6883a57c195a28c96620

dtysky/LD3320_AXI

hdl/VOICE_DELAY.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_misc.all; use ieee.std_logic_unsigned.all; entity VOICE_DELAY is port ( clk:in std_logic; start:in std_logic:='0'; total:in std_logic_vector(7 downto 0); finish:out std_logic:='1' ); end entity; architecture delayx of VOICE_DELAY is signal delay_total:integer range 0 to 511:=0; signal start_last:std_logic; begin process(clk) variable con:integer range 0 to 400:=0; begin if clk'event and clk='1' then start_last<=start; if start_last='0' and start='1' then con:=1; delay_total<=conv_integer(total); finish<='0'; end if; if con=400 then if delay_total=0 then finish<='1'; con:=0; else delay_total<=delay_total-1; con:=1; end if; elsif con>0 then con:=con+1; end if; end if; end process; end delayx;

mit

3f9ffdd4bf55d4eb63ed4697c427dcc8

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_prod_data_lgth_calc.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_prod_data_lgth_calc | -- | --------------------------------------------------------------------------------------------------- -- File wf_prod_data_lgth_calc.vhd | -- | -- Description Calculation of the number of bytes, after the FSS and before the FCS, that have to| -- be transferred when a variable is produced (var_pres, var_identif, var_3, var_5) | -- As the following figure indicates, in detail, the unit adds-up: | -- o 1 byte RP_DAT.CTRL, | -- o 1 byte RP_DAT.Data.PDU_TYPE, | -- o 1 byte RP_DAT.Data.LGTH, | -- o 1-124 RP_DAT.Data.User_Data bytes according to the variable type: | -- - var_pres: 5 bytes | -- - var_pres: 8 bytes | -- - var_5 : 1 byte | -- - var_3 : 2-124 bytes defined by the "nanoFIP User Interface,General signal"| -- SLONE and the "nanoFIP WorldFIP Settings" input P3_LGTH, | -- o 1 byte RP_DAT.Data.nanoFIP_status, always for a var_5 | -- and for a var_3, if the "nanoFIP User | -- Interface General signal"NOSTAT is negated,| -- o 1 byte RP_DAT.Data.MPS_status, for a var_3 and a var_5 | -- | -- | -- Reminder: | -- | -- Produced RP_DAT frame structure : | -- ||--------------------- Data ---------------------|| | -- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______ | -- |____FSS____|_CTRL_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__| | -- | -- |-----P3_LGTH-----| | -- | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 09/12/2010 | -- Version v0.02 | -- Depends on wf_engine_control | ---------------- | -- Last changes | -- 12/2010 v0.02 EG code cleaned-up+commented | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_prod_data_lgth_calc --================================================================================================= entity wf_prod_data_lgth_calc is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- nanoFIP WorldFIP Settings p3_lgth_i : in std_logic_vector (2 downto 0); -- produced var user-data length -- User Interface, General signals nostat_i : in std_logic; -- if negated, nFIP status is sent slone_i : in std_logic; -- stand-alone mode -- Signal from the wf_engine_control unit var_i : in t_var; -- variable type that is being treated -- OUTPUT -- Signal to the wf_engine_control and wf_production units prod_data_lgth_o : out std_logic_vector (7 downto 0)); end entity wf_prod_data_lgth_calc; --================================================================================================= -- architecture declaration --================================================================================================= architecture behavior of wf_prod_data_lgth_calc is signal s_prod_data_lgth, s_p3_lgth_decoded : unsigned (7 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Combinatorial process data_length_calcul: calculation of the amount of bytes, after the -- FSS and before the FCS, that have to be transferred when a variable is produced. In the case -- of the presence, the identification and the var5 variables, the data length is predefined in the -- WF_PACKAGE. In the case of a var3 the inputs SLONE, NOSTAT and P3_LGTH[] are accounted for the -- calculation. data_length_calcul: process (var_i, s_p3_lgth_decoded, slone_i, nostat_i, p3_lgth_i) begin s_p3_lgth_decoded <= c_P3_LGTH_TABLE (to_integer(unsigned(p3_lgth_i))); case var_i is -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - when var_presence => -- data length information retrieval from the c_VARS_ARRAY matrix (WF_PACKAGE) s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).array_lgth; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - when var_identif => -- data length information retrieval from the c_VARS_ARRAY matrix (WF_PACKAGE) s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).array_lgth; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - when var_3 => -- data length calculation according to the operational mode (memory or stand-alone) -- in slone mode 2 bytes of user-data are produced (independently of P3_LGTH) -- to these there should be added: 1 byte CTRL -- 1 byte PDU_TYPE -- 1 byte LGTH -- 1 byte MPS status -- optionally 1 byte nFIP status -- in memory mode the signal "s_p3_lgth_decoded" indicates the amount of user-data; -- to these, there should be added 1 byte CTRL -- 1 byte PDU_TYPE -- 1 byte LGTH -- 1 byte MPS status -- optionally 1 byte nFIP status if slone_i = '1' then if nostat_i = '1' then -- 6 bytes (counting starts from 0!) s_prod_data_lgth <= to_unsigned(5, s_prod_data_lgth'length); else -- 7 bytes s_prod_data_lgth <= to_unsigned(6, s_prod_data_lgth'length); end if; else if nostat_i = '0' then s_prod_data_lgth <= s_p3_lgth_decoded + 4; else s_prod_data_lgth <= s_p3_lgth_decoded + 3; end if; end if; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - when var_5 => -- data length information retrieval from the c_VARS_ARRAY matrix (WF_PACKAGE) s_prod_data_lgth <= c_VARS_ARRAY(c_VAR_5_INDEX).array_lgth; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- - when others => s_prod_data_lgth <= (others => '0'); end case; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Registration of the output (coz of slack) Prod_Data_Lgth_Reg: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then prod_data_lgth_o <= (others =>'0'); else prod_data_lgth_o <= std_logic_vector (s_prod_data_lgth); end if; end if; end process; end architecture behavior; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

12d2c083d3fae2e0cb623af9803563b7

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_crc.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_crc | -- | --------------------------------------------------------------------------------------------------- -- File wf_crc.vhd | -- | -- Description The unit creates the modules for: | -- o the generation of the CRC of serial data, | -- o the verification of an incoming CRC syndrome. | -- The unit is instantiated in both the wf_fd_transmitter, for the generation of the | -- FCS field of produced RP_DAT frames, and the wf_fd_receiver for the validation of | -- of an incoming ID_DAT or consumed RP_DAT frame. | -- | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Date 23/02/2011 | -- Version v0.04 | -- Depends on wf_reset_unit | -- wf_rx_deserializer | -- wf_tx_serializer | ---------------- | -- Last changes | -- 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content | -- 08/2010 v0.03 EG Data_FCS_select and crc_ready_p_o signals removed, | -- variable v_q_check_mask replaced with a signal, | -- code cleaned-up+commented | -- 02/2011 v0.04 EG s_q_check_mask was not in Syndrome_Verification sensitivity list! | -- xor replaced with if(Syndrome_Verification); processes rewritten; | -- delay on data_bit_ready_p_i removed. | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_crc --================================================================================================= entity wf_crc is port( -- INPUTS -- nanoFIP User Interface, General signals uclk_i : in std_logic; -- 40 MHz clock -- Signal from the wf_reset_unit nfip_rst_i : in std_logic; -- nanoFIP internal reset -- Signals from the wf_rx_deserializer/ wf_tx_serializer units data_bit_i : in std_logic; -- incoming data bit stream data_bit_ready_p_i : in std_logic; -- indicates the sampling moment of data_bit_i start_crc_p_i : in std_logic; -- beginning of the CRC calculation -- OUTPUTS -- Signal to the wf_rx_deserializer unit crc_ok_p_o : out std_logic; -- signals a correct received CRC syndrome -- Signal to the wf_tx_serializer unit crc_o : out std_logic_vector (c_CRC_POLY_LGTH-1 downto 0)); -- calculated CRC end entity wf_crc; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_crc is signal s_q, s_q_nx : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- CRC Calculation -- --------------------------------------------------------------------------------------------------- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- The Gen_16_bit_Register_and_Interconnections generator, follows the scheme of figure A.1 -- of the Annex A 61158-4-7 IEC:2007 and constructs a register of 16 master-slave flip-flops which -- are interconnected as a linear feedback shift register. Generate_16_bit_Register_and_Interconnections: s_q_nx(0) <= data_bit_i xor s_q(s_q'left); G: for I in 1 to c_CRC_GENER_POLY'left generate s_q_nx(I) <= s_q(I-1) xor (c_CRC_GENER_POLY(I) and (data_bit_i xor s_q(s_q'left))); end generate; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Synchronous process CRC_calculation: the process "moves" the shift register described -- above, for the calculation of the CRC. CRC_calculation: process (uclk_i) begin if rising_edge (uclk_i) then if nfip_rst_i = '1' then s_q <= (others => '0'); else if start_crc_p_i = '1' then s_q <= (others => '1'); -- register initialization -- (initially preset, according to the Annex) elsif data_bit_ready_p_i = '1' then -- new bit to be considered for the CRC calculation s_q <= s_q_nx; -- data propagation end if; end if; end if; end process; -- -- -- -- -- crc_o <= not s_q; --------------------------------------------------------------------------------------------------- -- CRC Verification -- --------------------------------------------------------------------------------------------------- -- During reception, the CRC is being calculated as data is arriving (same as in the transmission) -- and at the same time it is being compared to the predefined c_CRC_VERIF_POLY. When the CRC -- calculated from the received data matches the c_CRC_VERIF_POLY, it is implied that a correct CRC -- word has been received for the preceded data and the signal crc_ok_p_o gives a 1 uclk-wide pulse. crc_ok_p_o <= data_bit_ready_p_i when s_q = not c_CRC_VERIF_POLY else '0'; end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

1cc1584fdadefe0fa117264303ad4bf0

preusser/q27

src/vhdl/top/dnk7_f5/dnk7_queens1.vhdl

library IEEE; use IEEE.std_logic_1164.all; library PoC; use PoC.physical.all; entity dnk7_queens1 is generic ( -- Design Parameters N : positive := 27; L : positive := 2; SOLVERS : positive := 240; COUNT_CYCLES : boolean := false; -- Local Clock Parameters CLK_FREQ : FREQ := 50 MHz; CLK_DIV : positive := 1; -- CLK_FREQ / CLK_DIV * CLK_MUL: CLK_MUL : positive := 22; -- as fast as possible but not above 1200 MHz -- Output Clocks CLK_DIV_COMP : positive := 5; -- fast computation clock CLK_DIV_SLOW : positive := 15 -- slower communication clock ); port ( --------------------------------------------------------------------------- -- 50-MHz Input Clock CLK_MBCLK : in std_logic; --------------------------------------------------------------------------- -- Ring Bus -- Input BUS_IN_CLKP : in std_logic; BUS_IN_CLKN : in std_logic; BUS_IN_PRE_DAT : in std_logic_vector(8 downto 0); BUS_IN_PRE_PUT : in std_logic; BUS_IN_PRE_STALL : out std_logic; BUS_IN_SOL_DAT : in std_logic_vector(8 downto 0); BUS_IN_SOL_PUT : in std_logic; BUS_IN_SOL_STALL : out std_logic; -- Output BUS_OUT_CLKP : out std_logic; BUS_OUT_CLKN : out std_logic; BUS_OUT_PRE_DAT : out std_logic_vector(8 downto 0); BUS_OUT_PRE_PUT : out std_logic; BUS_OUT_PRE_STALL : in std_logic; BUS_OUT_SOL_DAT : out std_logic_vector(8 downto 0); BUS_OUT_SOL_PUT : out std_logic; BUS_OUT_SOL_STALL : in std_logic ); end entity dnk7_queens1; library IEEE; use IEEE.numeric_std.all; library PoC; use PoC.utils.all; use PoC.fifo.all; library UNISIM; use UNISIM.vcomponents.all; architecture rtl of dnk7_queens1 is -- Bit Length of Pre-Placement constant PRE_BITS : positive := 4*L*log2ceil(N)-1; constant PRE_BYTES : positive := (PRE_BITS+7)/8; -- FIFO Dimensioning constant FIFO_DEPTH : positive := 5*(SOLVERS+5); ---------------------------------------------------------------------------- -- Global Control: Clocks and Resets signal clk_comp : std_logic; -- FRESHLY generated: signal rst_comp : std_logic; -- Fast Computation Clock signal clk_out : std_logic; -- FRESHLY generated: signal rst_out : std_logic; -- Slow Communication Clock (Output Side) ----------------------------------------------------------------------------- -- Solver Chain Connectivity signal piful : std_logic; signal pidat : byte; signal pieof : std_logic; signal piput : std_logic; signal sivld : std_logic; signal sidat : byte; signal sieof : std_logic; signal sigot : std_logic; signal poful : std_logic; signal podat : byte; signal poeof : std_logic; signal poput : std_logic; signal sovld : std_logic; signal sodat : byte; signal soeof : std_logic; signal sogot : std_logic; begin ---------------------------------------------------------------------------- -- Clock Generation blkClock: block -- Intermediate Clock Signals signal clk50 : std_logic; signal clkfb : std_logic; signal clk_compu : std_logic; signal clk_outu : std_logic; begin --------------------------------------------------------------------------- -- Freshly Generated clk_i : BUFG port map ( I => CLK_MBCLK, O => clk50 ); pll : PLLE2_BASE generic map ( CLKIN1_PERIOD => to_real(to_time(CLK_FREQ), 1 ns), DIVCLK_DIVIDE => CLK_DIV, CLKFBOUT_MULT => CLK_MUL, CLKOUT0_DIVIDE => CLK_DIV_COMP, CLKOUT1_DIVIDE => CLK_DIV_SLOW, STARTUP_WAIT => "true" ) port map ( RST => '0', CLKIN1 => clk50, CLKFBOUT => clkfb, CLKFBIN => clkfb, CLKOUT0 => clk_compu, CLKOUT1 => clk_outu, CLKOUT2 => open, CLKOUT3 => open, CLKOUT4 => open, CLKOUT5 => open, LOCKED => open, PWRDWN => '0' ); clk_compo : BUFG port map ( I => clk_compu, O => clk_comp ); rst_comp <= '0'; clk_outo : BUFG port map ( I => clk_outu, O => clk_out ); rst_out <= '0'; end block blkClock; --------------------------------------------------------------------------- -- Solver Chain blChain: block is signal pful : std_logic; signal pdat : byte; signal peof : std_logic; signal pput : std_logic; begin chain: entity work.queens_chain generic map ( N => N, L => L, SOLVERS => SOLVERS, COUNT_CYCLES => COUNT_CYCLES ) port map ( clk => clk_comp, rst => rst_comp, piful => piful, pidat => pidat, pieof => pieof, piput => piput, sivld => '0', sidat => (others => '-'), sieof => '-', sigot => open, poful => pful, podat => pdat, poeof => peof, poput => pput, sovld => sovld, sodat => sodat, soeof => soeof, sogot => sogot ); -- Resync stream so that frames are taken out in one piece sync: entity work.msg_tap generic map ( D => PRE_BYTES ) port map ( clk => clk_comp, rst => rst_comp, iful => pful, idat => pdat, ieof => peof, iput => pput, oful => poful, odat => podat, oeof => poeof, oput => poput, tful => '1', tdat => open, tput => open ); end block blChain; ----------------------------------------------------------------------------- -- Input Stream -> feeds pi(ful|dat|eof|put) and si(vld|dat|eof|got) blkInput: block -- Source synchronous clock domain signal clk_in : std_logic; signal rst_in : std_logic; -- Incoming Bus Data Capture Registers signal InPreDat : std_logic_vector(8 downto 0) := (others => '-'); signal InPrePut : std_logic := '0'; signal InPreCap : std_logic_vector(1 downto 0); signal InSolDat : std_logic_vector(8 downto 0) := (others => '-'); signal InSolPut : std_logic := '0'; signal InSolCap : std_logic_vector(1 downto 0); signal pivld : std_logic; begin --------------------------------------------------------------------------- -- Reading the Bus -- Clock reconstruction blkClock: block signal clk_in0 : std_logic; begin IBUFGDS_inst : IBUFGDS port map ( O => clk_in0, I => BUS_IN_CLKP, IB => BUS_IN_CLKN ); BUFG_inst : BUFG port map ( O => clk_in, I => clk_in0 ); rst_in <= '0'; end block blkClock; -- Bus Input Capture process(clk_in) begin if rising_edge(clk_in) then if rst_in = '1' then InPreDat <= (others => '-'); InPrePut <= '0'; InSolDat <= (others => '-'); InSolPut <= '0'; else InPreDat <= BUS_IN_PRE_DAT; InPrePut <= BUS_IN_PRE_PUT; InSolDat <= BUS_IN_SOL_DAT; InSolPut <= BUS_IN_SOL_PUT; end if; end if; end process; -- Input FIFO (ic): Pre-Placements buf_pre : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64, ESTATE_WR_BITS => InPreCap'length ) port map ( clk_wr => clk_in, rst_wr => rst_in, put => InPrePut, din => InPreDat, full => open, estate_wr => InPreCap, clk_rd => clk_comp, rst_rd => rst_comp, got => piput, dout(8) => pieof, dout(7 downto 0) => pidat, valid => pivld ); piput <= pivld and not piful; BUS_IN_PRE_STALL <= '1' when InPreCap = (InPreCap'range => '0') else '0'; -- Input FIFO (ic): Solutions buf_sol : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64, ESTATE_WR_BITS => InSolCap'length ) port map ( clk_wr => clk_in, rst_wr => rst_in, put => InSolPut, din => InSolDat, full => open, estate_wr => InSolCap, clk_rd => clk_out, rst_rd => rst_out, got => sigot, dout(8) => sieof, dout(7 downto 0) => sidat, valid => sivld ); BUS_IN_SOL_STALL <= '1' when InSolCap = (InSolCap'range => '0') else '0'; end block blkInput; blkOutput : block begin ------------------------------------------------------------------------- -- Output Inverted Clock blkClock : block signal clk_inv : std_logic; begin invert : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '1', SRTYPE => "SYNC" ) port map ( Q => clk_inv, -- 1-bit DDR output C => clk_out, -- 1-bit clock input CE => '1', -- 1-bit clock enable input D1 => '0', -- 1-bit data input (positive edge) D2 => '1', -- 1-bit data input (negative edge) R => rst_out, -- 1-bit reset input S => '0' -- 1-bit set input ); OBUFDS_inst : OBUFDS generic map ( IOSTANDARD => "DEFAULT", SLEW => "FAST" ) port map ( O => BUS_OUT_CLKP, OB => BUS_OUT_CLKN, I => clk_inv ); end block blkClock; blkPre: block -- Syncing the stall input signal stall_s : std_logic_vector(1 downto 0) := (others => '1'); -- Output FIFO signal pgot : std_logic; signal pdat : std_logic_vector(8 downto 0); signal pvld : std_logic; -- Outgoing Output Registers signal PreOutDat : std_logic_vector(8 downto 0) := (others => '0'); signal PreOutPut : std_logic := '0'; begin -- Syncing stall input process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then stall_s <= (others => '1'); else stall_s <= BUS_OUT_PRE_STALL & stall_s(stall_s'left downto 1); end if; end if; end process; -- Output FIFO (ic): Pre-Placements fifob : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64 ) port map ( clk_wr => clk_comp, rst_wr => rst_comp, put => poput, din(8) => poeof, din(7 downto 0) => podat, full => poful, clk_rd => clk_out, rst_rd => rst_out, got => pgot, dout => pdat, valid => pvld ); pgot <= pvld and not stall_s(0); -- Output Registers process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then PreOutDat <= (others => '0'); PreOutPut <= '0'; else PreOutDat <= pdat; PreOutPut <= pgot; end if; end if; end process; BUS_OUT_PRE_DAT <= PreOutDat; BUS_OUT_PRE_PUT <= PreOutPut; end block blkPre; blkSol: block -- Syncing the stall input signal stall_s : std_logic_vector(1 downto 0) := (others => '1'); -- Chain -> fifo_ic [clk_comp->clk_out] signal soful : std_logic; -- fifo_ic -> funnel signal scvld : std_logic; signal scdat : std_logic_vector(8 downto 0); signal scgot : std_logic; -- funnel -> fifo_glue signal sjful : std_logic; signal sjdat : std_logic_vector(8 downto 0); signal sjput : std_logic; -- fifo_glue -> output signal sfvld : std_logic; signal sfdat : std_logic_vector(8 downto 0); signal sfgot : std_logic; -- Outgoing Output Registers signal SolOutDat : std_logic_vector(8 downto 0) := (others => '0'); signal SolOutPut : std_logic := '0'; begin -- Syncing stall input process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then stall_s <= (others => '1'); else stall_s <= BUS_OUT_SOL_STALL & stall_s(stall_s'left downto 1); end if; end if; end process; -- fifo_ic: clk_comp -> clk_out fifob : fifo_ic_got generic map ( D_BITS => 9, MIN_DEPTH => 64 ) port map ( clk_wr => clk_comp, rst_wr => rst_comp, put => sogot, din(8) => soeof, din(7 downto 0) => sodat, full => soful, clk_rd => clk_out, rst_rd => rst_out, got => scgot, dout => scdat, valid => scvld ); sogot <= sovld and not soful; -- funnel: si* + sc* -> sj* join: entity work.msg_funnel generic map ( N => 2 ) port map ( clk => clk_out, rst => rst_out, ivld(0) => scvld, ivld(1) => sivld, idat(0) => scdat(7 downto 0), idat(1) => sidat, ieof(0) => scdat(8), ieof(1) => sieof, igot(0) => scgot, igot(1) => sigot, oful => sjful, odat => sjdat(7 downto 0), oeof => sjdat(8), oput => sjput ); -- fifo_glue glue: fifo_glue generic map ( D_BITS => 9 ) port map ( clk => clk_out, rst => rst_out, put => sjput, di => sjdat, ful => sjful, vld => sfvld, do => sfdat, got => sfgot ); sfgot <= sfvld and not stall_s(0); -- Output Registers process(clk_out) begin if rising_edge(clk_out) then if rst_out = '1' then SolOutDat <= (others => '0'); SolOutPut <= '0'; else SolOutDat <= sfdat; SolOutPut <= sfgot; end if; end if; end process; BUS_OUT_SOL_DAT <= SolOutDat; BUS_OUT_SOL_PUT <= SolOutPut; end block blkSol; end block blkOutput; end rtl;

agpl-3.0

5c6157a2c1b6f385b24d2a38c1658c61

wltr/cern-fgclite

nanofip_fpga/src/rtl/nanofip/wf_incr_counter.vhd

--_________________________________________________________________________________________________ -- | -- |The nanoFIP| | -- | -- CERN,BE/CO-HT | --________________________________________________________________________________________________| --------------------------------------------------------------------------------------------------- -- | -- wf_incr_counter | -- | --------------------------------------------------------------------------------------------------- -- File wf_incr_counter.vhd | -- Description Increasing counter with synchronous reinitialise and increase enable | -- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) | -- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) | -- Date 01/2011 | -- Version v0.011 | -- Depends on - | ---------------- | -- Last changes | -- 10/2010 EG v0.01 first version | -- 01/2011 EG v0.011 counter_full became a constant | --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- -- GNU LESSER GENERAL PUBLIC LICENSE | -- ------------------------------------ | -- This source file is free software; you can redistribute it and/or modify it under the terms of | -- the GNU Lesser General Public License as published by the Free Software Foundation; either | -- version 2.1 of the License, or (at your option) any later version. | -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; | -- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | -- See the GNU Lesser General Public License for more details. | -- You should have received a copy of the GNU Lesser General Public License along with this | -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html | --------------------------------------------------------------------------------------------------- --================================================================================================= -- Libraries & Packages --================================================================================================= -- Standard library library IEEE; use IEEE.STD_LOGIC_1164.all; -- std_logic definitions use IEEE.NUMERIC_STD.all; -- conversion functions -- Specific library library work; use work.WF_PACKAGE.all; -- definitions of types, constants, entities --================================================================================================= -- Entity declaration for wf_incr_counter --================================================================================================= entity wf_incr_counter is generic(g_counter_lgth : natural := 4); -- default length port( -- INPUTS -- nanoFIP User Interface general signal uclk_i : in std_logic; -- 40 MHz clock -- Signals from any unit counter_incr_i : in std_logic; -- increment enable counter_reinit_i : in std_logic; -- reinitializes counter to 0 -- OUTPUT -- Signal to any unit counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter counter_is_full_o : out std_logic); -- counter full indication -- (all bits to '1') end entity wf_incr_counter; --================================================================================================= -- architecture declaration --================================================================================================= architecture rtl of wf_incr_counter is constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1'); signal s_counter : unsigned (g_counter_lgth-1 downto 0); --================================================================================================= -- architecture begin --================================================================================================= begin --------------------------------------------------------------------------------------------------- -- Synchronous process Incr_Counter Incr_Counter: process (uclk_i) begin if rising_edge (uclk_i) then if counter_reinit_i = '1' then s_counter <= (others => '0'); elsif counter_incr_i = '1' then s_counter <= s_counter + 1; end if; end if; end process; -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- counter_o <= s_counter; counter_is_full_o <= '1' when s_counter = c_COUNTER_FULL else '0'; end architecture rtl; --================================================================================================= -- architecture end --================================================================================================= --------------------------------------------------------------------------------------------------- -- E N D O F F I L E ---------------------------------------------------------------------------------------------------

mit

dcfc2a40e7952cda7ee5404ad8c510c1