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// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // or agreed to in writing, software, hardware and materials distributed under // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. // // Author: Florian Zaruba, ETH Zurich // Date: 28/09/2018 // Description: Mock replacement for UART in testbench (not synthesiesable!) module mock_uart ( input logic clk_i, input logic rst_ni, input logic penable_i, input logic pwrite_i, input logic [31:0] paddr_i, input logic psel_i, input logic [31:0] pwdata_i, output logic [31:0] prdata_o, output logic pready_o, output logic pslverr_o ); localparam RBR = 0; localparam THR = 0; localparam IER = 1; localparam IIR = 2; localparam FCR = 2; localparam LCR = 3; localparam MCR = 4; localparam LSR = 5; localparam MSR = 6; localparam SCR = 7; localparam DLL = 0; localparam DLM = 1; localparam THRE = 5; // transmit holding register empty localparam TEMT = 6; // transmit holding register empty byte lcr = 0; byte dlm = 0; byte dll = 0; byte mcr = 0; byte lsr = 0; byte ier = 0; byte msr = 0; byte scr = 0; logic fifo_enabled = 1'b0; assign pready_o = 1'b1; assign pslverr_o = 1'b0; function void uart_tx(byte ch); $write("%c", ch); endfunction : uart_tx always_ff @(posedge clk_i or negedge rst_ni) begin if (rst_ni) begin if (psel_i & penable_i & pwrite_i) begin case ((paddr_i >> 'h2) & 'h7) THR: begin if (lcr & 'h80) dll <= byte'(pwdata_i[7:0]); else uart_tx(byte'(pwdata_i[7:0])); end IER: begin if (lcr & 'h80) dlm <= byte'(pwdata_i[7:0]); else ier <= byte'(pwdata_i[7:0] & 'hF); end FCR: begin if (pwdata_i[0]) fifo_enabled <= 1'b1; else fifo_enabled <= 1'b0; end LCR: lcr <= byte'(pwdata_i[7:0]); MCR: mcr <= byte'(pwdata_i[7:0] & 'h1F); LSR: lsr <= byte'(pwdata_i[7:0]); MSR: msr <= byte'(pwdata_i[7:0]); SCR: scr <= byte'(pwdata_i[7:0]); default:; endcase end end end always_comb begin prdata_o = '0; if (psel_i & penable_i & ~pwrite_i) begin case ((paddr_i >> 'h2) & 'h7) THR: begin if (lcr & 'h80) prdata_o = {24'b0, dll}; end IER: begin if (lcr & 'h80) prdata_o = {24'b0, dlm}; else prdata_o = {24'b0, ier}; end IIR: begin if (fifo_enabled) prdata_o = {24'b0, 8'hc0}; else prdata_o = {24'b0, 8'b0}; end LCR: prdata_o = {24'b0, lcr}; MCR: prdata_o = {24'b0, mcr}; LSR: prdata_o = {24'b0, (lsr | (1 << THRE) | (1 << TEMT))}; MSR: prdata_o = {24'b0, msr}; SCR: prdata_o = {24'b0, scr}; default:; endcase end end endmodule
// See LICENSE.SiFive for license details. //VCS coverage exclude_file import "DPI-C" function int debug_tick ( output bit debug_req_valid, input bit debug_req_ready, output int debug_req_bits_addr, output int debug_req_bits_op, output int debug_req_bits_data, input bit debug_resp_valid, output bit debug_resp_ready, input int debug_resp_bits_resp, input int debug_resp_bits_data ); module SimDTM( input clk, input reset, output debug_req_valid, input debug_req_ready, output [ 6:0] debug_req_bits_addr, output [ 1:0] debug_req_bits_op, output [31:0] debug_req_bits_data, input debug_resp_valid, output debug_resp_ready, input [ 1:0] debug_resp_bits_resp, input [31:0] debug_resp_bits_data, output [31:0] exit ); bit r_reset; wire #0.1 __debug_req_ready = debug_req_ready; wire #0.1 __debug_resp_valid = debug_resp_valid; wire [31:0] #0.1 __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp}; wire [31:0] #0.1 __debug_resp_bits_data = debug_resp_bits_data; bit __debug_req_valid; int __debug_req_bits_addr; int __debug_req_bits_op; int __debug_req_bits_data; bit __debug_resp_ready; int __exit; assign #0.1 debug_req_valid = __debug_req_valid; assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[6:0]; assign #0.1 debug_req_bits_op = __debug_req_bits_op[1:0]; assign #0.1 debug_req_bits_data = __debug_req_bits_data[31:0]; assign #0.1 debug_resp_ready = __debug_resp_ready; assign #0.1 exit = __exit; always @(posedge clk) begin r_reset <= reset; if (reset || r_reset) begin __debug_req_valid = 0; __debug_resp_ready = 0; __exit = 0; end else begin __exit = debug_tick( __debug_req_valid, __debug_req_ready, __debug_req_bits_addr, __debug_req_bits_op, __debug_req_bits_data, __debug_resp_valid, __debug_resp_ready, __debug_resp_bits_resp, __debug_resp_bits_data ); end end endmodule
// See LICENSE.SiFive for license details. //VCS coverage exclude_file import "DPI-C" function int jtag_tick ( output bit jtag_TCK, output bit jtag_TMS, output bit jtag_TDI, output bit jtag_TRSTn, input bit jtag_TDO ); module SimJTAG #( parameter TICK_DELAY = 50 )( input clock, input reset, input enable, input init_done, output jtag_TCK, output jtag_TMS, output jtag_TDI, output jtag_TRSTn, input jtag_TDO_data, input jtag_TDO_driven, output [31:0] exit ); reg [31:0] tickCounterReg; wire [31:0] tickCounterNxt; assign tickCounterNxt = (tickCounterReg == 0) ? TICK_DELAY : (tickCounterReg - 1); bit r_reset; wire [31:0] random_bits = $random; wire #0.1 __jtag_TDO = jtag_TDO_driven ? jtag_TDO_data : random_bits[0]; bit __jtag_TCK; bit __jtag_TMS; bit __jtag_TDI; bit __jtag_TRSTn; int __exit; reg init_done_sticky; assign #0.1 jtag_TCK = __jtag_TCK; assign #0.1 jtag_TMS = __jtag_TMS; assign #0.1 jtag_TDI = __jtag_TDI; assign #0.1 jtag_TRSTn = __jtag_TRSTn; assign #0.1 exit = __exit; always @(posedge clock) begin r_reset <= reset; if (reset || r_reset) begin __exit = 0; tickCounterReg <= TICK_DELAY; init_done_sticky <= 1'b0; end else begin init_done_sticky <= init_done | init_done_sticky; if (enable && init_done_sticky) begin tickCounterReg <= tickCounterNxt; if (tickCounterReg == 0) begin __exit = jtag_tick( __jtag_TCK, __jtag_TMS, __jtag_TDI, __jtag_TRSTn, __jtag_TDO); end end // if (enable && init_done_sticky) end // else: !if(reset || r_reset) end // always @ (posedge clock) endmodule
// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // or agreed to in writing, software, hardware and materials distributed under // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. // // Author: Florian Zaruba, ETH Zurich // Date: 3/11/2018 // Description: Wrapped Spike Model for Tandem Verification import uvm_pkg::*; `include "uvm_macros.svh" import "DPI-C" function int spike_create(string filename, longint unsigned dram_base, int unsigned size); typedef riscv::commit_log_t riscv_commit_log_t; import "DPI-C" function void spike_tick(output riscv_commit_log_t commit_log); import "DPI-C" function void clint_tick(); module spike #( parameter longint unsigned DramBase = 'h8000_0000, parameter int unsigned Size = 64 * 1024 * 1024 // 64 Mega Byte )( input logic clk_i, input logic rst_ni, input logic clint_tick_i, input ariane_pkg::scoreboard_entry_t [ariane_pkg::NR_COMMIT_PORTS-1:0] commit_instr_i, input logic [ariane_pkg::NR_COMMIT_PORTS-1:0] commit_ack_i, input ariane_pkg::exception_t exception_i, input logic [ariane_pkg::NR_COMMIT_PORTS-1:0][4:0] waddr_i, input logic [ariane_pkg::NR_COMMIT_PORTS-1:0][63:0] wdata_i, input riscv::priv_lvl_t priv_lvl_i ); static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst(); string binary = ""; logic fake_clk; logic clint_tick_q, clint_tick_qq, clint_tick_qqq, clint_tick_qqqq; initial begin void'(uvcl.get_arg_value("+PRELOAD=", binary)); assert(binary != "") else $error("We need a preloaded binary for tandem verification"); void'(spike_create(binary, DramBase, Size)); end riscv_commit_log_t commit_log; logic [31:0] instr; always_ff @(posedge clk_i) begin if (rst_ni) begin for (int i = 0; i < ariane_pkg::NR_COMMIT_PORTS; i++) begin if ((commit_instr_i[i].valid && commit_ack_i[i]) || (commit_instr_i[i].valid && exception_i.valid)) begin spike_tick(commit_log); instr = (commit_log.instr[1:0] != 2'b11) ? {16'b0, commit_log.instr[15:0]} : commit_log.instr; // $display("\x1B[32m%h %h\x1B[0m", commit_log.pc, instr); // $display("%p", commit_log); // $display("\x1B[37m%h %h\x1B[0m", commit_instr_i[i].pc, commit_instr_i[i].ex.tval[31:0]); assert (commit_log.pc === commit_instr_i[i].pc) else begin $warning("\x1B[33m[Tandem] PCs Mismatch\x1B[0m"); // $stop; end assert (commit_log.was_exception === exception_i.valid) else begin $warning("\x1B[33m[Tandem] Exception not detected\x1B[0m"); // $stop; $display("Spike: %p", commit_log); $display("Ariane: %p", commit_instr_i[i]); end if (!exception_i.valid) begin assert (commit_log.priv === priv_lvl_i) else begin $warning("\x1B[33m[Tandem] Privilege level mismatches\x1B[0m"); // $stop; $display("\x1B[37m %2d == %2d @ PC %h\x1B[0m", priv_lvl_i, commit_log.priv, commit_log.pc); end assert (instr === commit_instr_i[i].ex.tval) else begin $warning("\x1B[33m[Tandem] Decoded instructions mismatch\x1B[0m"); // $stop; $display("\x1B[37m%h === %h @ PC %h\x1B[0m", commit_instr_i[i].ex.tval, instr, commit_log.pc); end // TODO(zarubaf): Adapt for floating point instructions if (commit_instr_i[i].rd != 0) begin // check the return value // $display("\x1B[37m%h === %h\x1B[0m", commit_instr_i[i].rd, commit_log.rd); assert (waddr_i[i] === commit_log.rd) else begin $warning("\x1B[33m[Tandem] Destination register mismatches\x1B[0m"); // $stop; end assert (wdata_i[i] === commit_log.data) else begin $warning("\x1B[33m[Tandem] Write back data mismatches\x1B[0m"); $display("\x1B[37m%h === %h @ PC %h\x1B[0m", wdata_i[i], commit_log.data, commit_log.pc); end end end end end end end // we want to schedule the timer increment at the end of this cycle assign #1ps fake_clk = clk_i; always_ff @(posedge fake_clk) begin clint_tick_q <= clint_tick_i; clint_tick_qq <= clint_tick_q; clint_tick_qqq <= clint_tick_qq; clint_tick_qqqq <= clint_tick_qqq; end always_ff @(posedge clint_tick_qqqq) begin if (rst_ni) begin void'(clint_tick()); end end endmodule
// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // or agreed to in writing, software, hardware and materials distributed under // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. // // Author: Florian Zaruba, ETH Zurich // Date: 13.07.2017 // Description: Buffers a string until a new line appears. class string_buffer extends uvm_component; /*------------------------------------------------------------------------------- -- Interface, port, fields -------------------------------------------------------------------------------*/ // string buffer byte buffer [$]; // name to display in console string logger_name; /*------------------------------------------------------------------------------- -- UVM Factory register -------------------------------------------------------------------------------*/ // Provide implementations of virtual methods such as get_type_name and create `uvm_component_utils(string_buffer) /*------------------------------------------------------------------------------- -- Functions -------------------------------------------------------------------------------*/ // Constructor function new(string name = "string_buffer", uvm_component parent=null); super.new(name, parent); // default logger name logger_name = "String Buffer"; endfunction : new function void set_logger(string logger_name); this.logger_name = logger_name; endfunction : set_logger function void flush(); string s; // dump the buffer out the whole buffer foreach (buffer[i]) begin s = $sformatf("%s%c",s, buffer[i]); end uvm_report_info(logger_name, s, UVM_LOW); // clear buffer afterwards buffer = {}; endfunction : flush // put a char to the buffer function void append(byte ch); // wait for the new line if (ch == 8'hA) this.flush(); else buffer.push_back(ch); endfunction : append endclass : string_buffer
// Copyright (c) 2018 ETH Zurich, University of Bologna // All rights reserved. // // This code is under development and not yet released to the public. // Until it is released, the code is under the copyright of ETH Zurich and // the University of Bologna, and may contain confidential and/or unpublished // work. Any reuse/redistribution is strictly forbidden without written // permission from ETH Zurich. // // Bug fixes and contributions will eventually be released under the // SolderPad open hardware license in the context of the PULP platform // (http://www.pulp-platform.org), under the copyright of ETH Zurich and the // University of Bologna. // // Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich // Date: 15.08.2018 // Description: // ////////////////////////////////////////////////////////////////////////////// // use to ensure proper ATI timing /////////////////////////////////////////////////////////////////////////////// `define APPL_ACQ_WAIT #(ACQ_DEL-APPL_DEL); `define WAIT_CYC(CLK, N) \ repeat(N) @(posedge(CLK)); `define WAIT(CLK, SIG) \ do begin \ @(posedge(CLK)); \ end while(SIG == 1'b0); `define WAIT_SIG(CLK,SIG) \ do begin \ @(posedge(CLK)); \ end while(SIG == 1'b0); `define APPL_WAIT_COMB_SIG(CLK,SIG) \ `APPL_ACQ_WAIT \ while(SIG == 1'b0) begin \ @(posedge(CLK)); \ #(ACQ_DEL); \ end `define APPL_WAIT_SIG(CLK,SIG) \ do begin \ @(posedge(CLK)); \ #(APPL_DEL); \ end while(SIG == 1'b0); `define ACQ_WAIT_SIG(CLK,SIG) \ do begin \ @(posedge(CLK)); \ #(ACQ_DEL); \ end while(SIG == 1'b0); `define APPL_WAIT_CYC(CLK, N) \ repeat(N) @(posedge(CLK)); \ #(tb_pkg::APPL_DEL); `define ACQ_WAIT_CYC(CLK, N) \ repeat(N) @(posedge(CLK)); \ #(tb_pkg::ACQ_DEL);
// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // or agreed to in writing, software, hardware and materials distributed under // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. // // Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich // Date: 15.08.2018 // Description: testbench package with some helper functions. package tb_pkg; // // for abs(double) function // import mti_cstdlib::*; // for timestamps import "DPI-C" \time = function int _time (inout int tloc[4]); import "DPI-C" function string ctime(inout int tloc[4]); /////////////////////////////////////////////////////////////////////////////// // parameters /////////////////////////////////////////////////////////////////////////////// // creates a 10ns ATI timing cycle time CLK_HI = 5ns; // set clock high time time CLK_LO = 5ns; // set clock low time time CLK_PERIOD = CLK_HI+CLK_LO; time APPL_DEL = 2ns; // set stimuli application delay time ACQ_DEL = 8ns; // set response aquisition delay parameter ERROR_CNT_STOP_LEVEL = 1; // use 1 for debugging. 0 runs the complete simulation... // tb_readport sequences typedef enum logic [2:0] { RANDOM_SEQ, LINEAR_SEQ, BURST_SEQ, IDLE_SEQ, WRAP_SEQ, SET_SEQ, CONST_SEQ } seq_t; typedef enum logic [1:0] { OTHER, BYPASS, CACHED } port_type_t; /////////////////////////////////////////////////////////////////////////////// // progress /////////////////////////////////////////////////////////////////////////////// class progress; real newState, oldState; longint numResp, acqCnt, errCnt, totAcqCnt, totErrCnt; string name; function new(string name); begin this.name = name; this.acqCnt = 0; this.errCnt = 0; this.newState = 0.0; this.oldState = 0.0; this.numResp = 1; this.totAcqCnt = 0; this.totErrCnt = 0; end endfunction : new function void reset(longint numResp_); begin this.acqCnt = 0; this.errCnt = 0; this.newState = 0.0; this.oldState = 0.0; this.numResp = numResp_; end endfunction : reset function void addRes(int isError); begin this.acqCnt++; this.totAcqCnt++; this.errCnt += isError; this.totErrCnt += isError; if(ERROR_CNT_STOP_LEVEL <= this.errCnt && ERROR_CNT_STOP_LEVEL > 0) begin $error("%s> simulation stopped (ERROR_CNT_STOP_LEVEL = %d reached).", this.name, ERROR_CNT_STOP_LEVEL); $stop(); end end endfunction : addRes function void print(); begin this.newState = $itor(this.acqCnt) / $itor(this.numResp); if(this.newState - this.oldState >= 0.01) begin $display("%s> validated %03d%% -- %01d failed (%03.3f%%) ", this.name, $rtoi(this.newState*100.0), this.errCnt, $itor(this.errCnt) / $itor(this.acqCnt) * 100.0); // $fflush(); this.oldState = this.newState; end end endfunction : print function void printToFile(string file, bit summary = 0); begin int fptr; // sanitize string for(fptr=0; fptr<$size(file);fptr++) begin if(file[fptr] == " " || file[fptr] == "/" || file[fptr] == "\\") begin file[fptr] = "_"; end end fptr = $fopen(file,"w"); if(summary) begin $fdisplay(fptr, "Simulation Summary of %s", this.name); $fdisplay(fptr, "total: %01d of %01d vectors failed (%03.3f%%) ", this.totErrCnt, this.totAcqCnt, $itor(this.totErrCnt) / ($itor(this.totAcqCnt) * 100.0 + 0.000000001)); if(this.totErrCnt == 0) begin $fdisplay(fptr, "CI: PASSED"); end else begin $fdisplay(fptr, "CI: FAILED"); end end else begin $fdisplay(fptr, "test name: %s", file); $fdisplay(fptr, "this test: %01d of %01d vectors failed (%03.3f%%) ", this.errCnt, this.acqCnt, $itor(this.errCnt) / $itor(this.acqCnt) * 100.0); $fdisplay(fptr, "total so far: %01d of %01d vectors failed (%03.3f%%) ", this.totErrCnt, this.totAcqCnt, $itor(this.totErrCnt) / $itor(this.totAcqCnt) * 100.0); end $fclose(fptr); end endfunction : printToFile endclass : progress /////////////////////////////////////////////////////////////////////////////// // memory emulation /////////////////////////////////////////////////////////////////////////////// class tb_mem_port #( parameter string MEM_NAME = "TB_MEM", // AXI interface parameters parameter int AW = 32, parameter int DW = 32, parameter int IW = 8, parameter int UW = 1, // Stimuli application and test time parameter time TA = 0ps, parameter time TT = 0ps, // Upper and lower bounds on wait cycles on Ax, W, and resp (R and B) channels parameter int AX_MIN_WAIT_CYCLES = 0, parameter int AX_MAX_WAIT_CYCLES = 100, parameter int R_MIN_WAIT_CYCLES = 0, parameter int R_MAX_WAIT_CYCLES = 5, parameter int RESP_MIN_WAIT_CYCLES = 0, parameter int RESP_MAX_WAIT_CYCLES = 20, parameter int MEM_BYTES = 512 * 1024 ); typedef axi_test::axi_driver #( .AW(AW), .DW(DW), .IW(IW), .UW(UW), .TA(TA), .TT(TT) ) axi_driver_t; typedef rand_id_queue_pkg::rand_id_queue #( .data_t (axi_driver_t::ax_beat_t), .ID_WIDTH (IW) ) rand_ax_beat_queue_t; typedef axi_driver_t::ax_beat_t ax_beat_t; typedef axi_driver_t::b_beat_t b_beat_t; typedef axi_driver_t::r_beat_t r_beat_t; typedef axi_driver_t::w_beat_t w_beat_t; typedef logic [AW-1:0] addr_t; typedef logic [7:0] byte_t; port_type_t port_type; string port_name; int unsigned min_paddr; int unsigned max_paddr; axi_driver_t drv; rand_ax_beat_queue_t ar_queue; ax_beat_t aw_queue[$]; int unsigned b_wait_cnt; static byte_t memory_q[MEM_BYTES-1:0]; // Main memory static byte_t shadow_q[MEM_BYTES-1:0]; // Shadow of main memory for verification. static progress status; function new( virtual AXI_BUS_DV #( .AXI_ADDR_WIDTH(AW), .AXI_DATA_WIDTH(DW), .AXI_ID_WIDTH(IW), .AXI_USER_WIDTH(UW) ) axi, port_type_t port_type ); this.port_type = port_type; if (port_type == BYPASS) this.port_name = "Bypassed"; else if (port_type == CACHED) this.port_name = "Cached"; else this.port_name = ""; this.drv = new(axi); this.ar_queue = new; this.b_wait_cnt = 0; this.min_paddr = 0; this.max_paddr = 1<<MEM_BYTES; this.reset(); endfunction function void reset(); this.drv.reset_slave(); endfunction // Set the memory region this port is expected to access. Accesses outside this region will // throw an error. function void set_region(int unsigned min_paddr, int unsigned max_paddr); this.min_paddr = min_paddr; this.max_paddr = max_paddr; endfunction // Initialize shadow and real memory with identical random values static function void init_mem(); automatic byte_t val; for (int k=0; k<MEM_BYTES; k++) begin void'(std::randomize(val)); memory_q[k] <= val; shadow_q[k] <= val; end status = new(MEM_NAME); endfunction // Crosscheck whether shadow and real memory arrays still match static function void check_mem(); bit ok; status.reset(MEM_BYTES); for(int k=0; k<MEM_BYTES; k++) begin ok = (memory_q[k] == shadow_q[k]); if(!ok) begin $display("%s> mismatch at k=%016X: real[k>>3]=%016X, shadow[k>>3]=%016X", MEM_NAME, k, memory_q[k], shadow_q[k]); end status.addRes(!ok); status.print(); end endfunction static function void report_mem(); status.printToFile({MEM_NAME, "_summary.rep"}, 1); if(status.totErrCnt == 0) begin $display("%s> ----------------------------------------------------------------------", MEM_NAME); $display("%s> PASSED %0d VECTORS", MEM_NAME, status.totAcqCnt); $display("%s> ----------------------------------------------------------------------\n", MEM_NAME); end else begin $display("%s> ----------------------------------------------------------------------\n", MEM_NAME); $display("%s> FAILED %0d OF %0d VECTORS\n", MEM_NAME , status.totErrCnt, status.totAcqCnt); $display("%s> ----------------------------------------------------------------------\n", MEM_NAME); end endfunction task automatic rand_wait(input int unsigned min, max); int unsigned rand_success, cycles; rand_success = std::randomize(cycles) with { cycles >= min; cycles <= max; }; assert (rand_success) else $error("Failed to randomize wait cycles!"); repeat (cycles) @(posedge this.drv.axi.clk_i); endtask task recv_ars(); forever begin automatic ax_beat_t ar_beat; rand_wait(AX_MIN_WAIT_CYCLES, AX_MAX_WAIT_CYCLES); drv.recv_ar(ar_beat); assert (ar_beat.ax_burst != axi_pkg::BURST_WRAP) else $error("axi_pkg::BURST_WRAP not supported."); ar_queue.push(ar_beat.ax_id, ar_beat); end endtask task send_rs(); forever begin automatic logic rand_success; automatic ax_beat_t ar_beat; automatic r_beat_t r_beat = new; automatic addr_t byte_addr; // Receive AR // automatic byte_t byte_data; wait (!ar_queue.empty()); ar_beat = ar_queue.peek(); byte_addr = (ar_beat.ax_addr >> $clog2(DW/8)) << $clog2(DW/8); assert (min_paddr != max_paddr && byte_addr inside {[min_paddr:max_paddr]}) else $error("%s read out of bounds. Address: %16X -- Permitted region: %16X--%16X", port_name, byte_addr, min_paddr, max_paddr); // Prepare R // Read from real memory for (int unsigned i = 0; i < (DW/8); i++) begin r_beat.r_data[i*8+:8] = memory_q[byte_addr]; byte_addr++; end r_beat.r_resp = axi_pkg::RESP_OKAY; r_beat.r_id = ar_beat.ax_id; if (ar_beat.ax_lock) r_beat.r_resp[0]= $random(); rand_wait(R_MIN_WAIT_CYCLES, R_MAX_WAIT_CYCLES); if (ar_beat.ax_len == '0) begin r_beat.r_last = 1'b1; void'(ar_queue.pop_id(ar_beat.ax_id)); end else begin if (ar_beat.ax_burst == axi_pkg::BURST_INCR) begin ar_beat.ax_addr = ((ar_beat.ax_addr >> ar_beat.ax_size) << ar_beat.ax_size) + 2**ar_beat.ax_size; end ar_beat.ax_len--; ar_queue.set(ar_beat.ax_id, ar_beat); end drv.send_r(r_beat); end endtask task recv_aws(); forever begin automatic ax_beat_t aw_beat; rand_wait(AX_MIN_WAIT_CYCLES, AX_MAX_WAIT_CYCLES); drv.recv_aw(aw_beat); assert (aw_beat.ax_atop == '0) else $error("ATOP not supported."); assert (aw_beat.ax_burst != axi_pkg::BURST_WRAP) else $error("axi_pkg::BURST_WRAP not supported."); aw_queue.push_back(aw_beat); // Atomic{Load,Swap,Compare}s require an R response. if (aw_beat.ax_atop[5]) begin ar_queue.push(aw_beat.ax_id, aw_beat); end end endtask task recv_ws(); forever begin automatic ax_beat_t aw_beat; automatic addr_t byte_addr; forever begin automatic w_beat_t w_beat; rand_wait(RESP_MIN_WAIT_CYCLES, RESP_MAX_WAIT_CYCLES); drv.recv_w(w_beat); wait (aw_queue.size() > 0); aw_beat = aw_queue[0]; byte_addr = (aw_beat.ax_addr >> $clog2(DW/8)) << $clog2(DW/8); assert (min_paddr != max_paddr && byte_addr inside {[min_paddr:max_paddr]}) else $error("%s write out of bounds. Address: %16X -- Permitted region: %16X--%16X", port_name, byte_addr, min_paddr, max_paddr); // Write data to real memory if the strobe is defined for (int unsigned i = 0; i < (DW/8); i++) begin if (w_beat.w_strb[i]) begin memory_q[byte_addr] = w_beat.w_data[i*8+:8]; end byte_addr++; end // Update address in beat if (aw_beat.ax_burst == axi_pkg::BURST_INCR) begin aw_beat.ax_addr = ((aw_beat.ax_addr >> aw_beat.ax_size) << aw_beat.ax_size) + 2**aw_beat.ax_size; end aw_queue[0] = aw_beat; if (w_beat.w_last) break; end b_wait_cnt++; end endtask task send_bs(); forever begin automatic ax_beat_t aw_beat; automatic b_beat_t b_beat = new; automatic logic rand_success; wait (b_wait_cnt > 0 && (aw_queue.size() != 0)); aw_beat = aw_queue.pop_front(); rand_success = std::randomize(b_beat); assert(rand_success); b_beat.b_id = aw_beat.ax_id; if (aw_beat.ax_lock) begin b_beat.b_resp[0]= $random(); end rand_wait(RESP_MIN_WAIT_CYCLES, RESP_MAX_WAIT_CYCLES); b_beat.b_resp = axi_pkg::RESP_OKAY; drv.send_b(b_beat); b_wait_cnt--; end endtask task run(); fork recv_ars(); send_rs(); recv_aws(); recv_ws(); send_bs(); join endtask endclass : tb_mem_port endpackage : tb_pkg
// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // or agreed to in writing, software, hardware and materials distributed under // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. // // Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich // Date: 15.08.2018 // Description: program that emulates a cache readport. the program can generate // randomized or linear read sequences, and it checks the returned responses against // the expected responses coming directly from the emulated memory (tb_mem). // `include "tb.svh" program tb_readport import tb_pkg::*; import ariane_pkg::*; #( parameter string PortName = "read port 0", parameter FlushRate = 1, parameter KillRate = 5, parameter TlbHitRate = 95, parameter MemWords = 1024*1024,// in 64bit words parameter logic [63:0] CachedAddrBeg = 0, parameter logic [63:0] CachedAddrEnd = 0, parameter RndSeed = 1110, parameter Verbose = 0 ) ( input logic clk_i, input logic rst_ni, // to testbench master ref string test_name_i, input logic [6:0] req_rate_i, //a rate between 0 and 100 percent input seq_t seq_type_i, input logic tlb_rand_en_i, input logic flush_rand_en_i, input logic seq_run_i, input logic [31:0] seq_num_resp_i, input logic seq_last_i, output logic seq_done_o, // expresp interface output logic [63:0] exp_paddr_o, input logic [1:0] exp_size_i, input logic [63:0] exp_rdata_i, input logic [63:0] exp_paddr_i, input logic [63:0] act_paddr_i, // interface to DUT output logic flush_o, input logic flush_ack_i, output dcache_req_i_t dut_req_port_o, input dcache_req_o_t dut_req_port_i ); // leave this timeunit 1ps; timeprecision 1ps; logic [63:0] paddr; logic seq_end_req, seq_end_ack, prog_end; logic [DCACHE_TAG_WIDTH-1:0] tag_q; logic [DCACHE_TAG_WIDTH-1:0] tag_vld_q; /////////////////////////////////////////////////////////////////////////////// // Randomly delay the tag by at least one cycle /////////////////////////////////////////////////////////////////////////////// // // TODO: add randomization initial begin : p_tag_delay logic [63:0] tmp_paddr, val; int unsigned cnt; logic tmp_vld; tag_q <= '0; tag_vld_q <= 1'b0; `APPL_WAIT_CYC(clk_i, 10) `APPL_WAIT_SIG(clk_i,~rst_ni) `APPL_WAIT_CYC(clk_i,1) tmp_vld = 0; cnt = 0; forever begin `APPL_WAIT_CYC(clk_i,1) if(cnt==0) begin if(tmp_vld) begin tmp_vld = 0; tag_q <= tmp_paddr[DCACHE_TAG_WIDTH+DCACHE_INDEX_WIDTH-1:DCACHE_INDEX_WIDTH]; tag_vld_q <= 1'b1; end else begin tag_vld_q <= 1'b0; end `APPL_ACQ_WAIT; if(dut_req_port_i.data_gnt) begin tmp_paddr = paddr; tmp_vld = 1; if(tlb_rand_en_i) begin void'(randomize(val) with {val>0; val<=100;}); if(val>=TlbHitRate) begin void'(randomize(cnt) with {cnt>0; cnt<=50;}); end end end end else begin tag_vld_q <= 1'b0; cnt -= 1; `APPL_ACQ_WAIT; end if(dut_req_port_o.kill_req) begin tmp_vld = 0; cnt = 0; end end end assign dut_req_port_o.address_tag = tag_q; assign dut_req_port_o.tag_valid = tag_vld_q; assign dut_req_port_o.address_index = paddr[DCACHE_INDEX_WIDTH-1:0]; assign exp_paddr_o = paddr; /////////////////////////////////////////////////////////////////////////////// // Helper tasks /////////////////////////////////////////////////////////////////////////////// task automatic flushCache(); flush_o = 1'b1; `APPL_WAIT_SIG(clk_i, flush_ack_i); flush_o = 0'b0; `APPL_WAIT_CYC(clk_i,1) endtask : flushCache task automatic genRandReq(); automatic logic [63:0] val; automatic logic [1:0] size; void'($urandom(RndSeed)); paddr = '0; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.kill_req = '0; while(~seq_end_req) begin // randomize request dut_req_port_o.data_req = '0; // generate random control events void'(randomize(val) with {val > 0; val <= 100;}); if(val < KillRate) begin dut_req_port_o.kill_req = 1'b1; `APPL_WAIT_CYC(clk_i,1) dut_req_port_o.kill_req = 1'b0; end else begin void'(randomize(val) with {val > 0; val <= 100;}); if(val < FlushRate && flush_rand_en_i) begin flushCache(); end else begin void'(randomize(val) with {val > 0; val <= 100;}); if(val < req_rate_i) begin dut_req_port_o.data_req = 1'b1; // generate random address void'(randomize(val) with {val >= 0; val < (MemWords<<3);}); void'(randomize(size)); dut_req_port_o.data_size = size; paddr = val; // align to size unique case(size) 2'b01: paddr[0] = 1'b0; 2'b10: paddr[1:0] = 2'b00; 2'b11: paddr[2:0] = 3'b000; default: ; endcase `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) end `APPL_WAIT_CYC(clk_i,1) end end end dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.kill_req = '0; endtask : genRandReq task automatic genSeqRead(); automatic logic [63:0] val; paddr = '0; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.kill_req = '0; val = '0; while(~seq_end_req) begin dut_req_port_o.data_req = 1'b1; dut_req_port_o.data_size = 2'b11; paddr = val; // generate linear read val = (val + 8) % (MemWords<<3); `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) `APPL_WAIT_CYC(clk_i,1) end dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.kill_req = '0; endtask : genSeqRead // Generate a sequence of reads to the same set (constant index) task automatic genSetSeqRead(); automatic logic [63:0] val, rnd; paddr = CachedAddrBeg + 2 ** DCACHE_INDEX_WIDTH; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.kill_req = '0; val = CachedAddrBeg + 2 ** DCACHE_INDEX_WIDTH; while(~seq_end_req) begin void'(randomize(rnd) with {rnd > 0; rnd <= 100;}); if(rnd < req_rate_i) begin dut_req_port_o.data_req = 1'b1; dut_req_port_o.data_size = 2'b11; paddr = val; // generate linear read `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) // increment by set size val = (val + 2 ** DCACHE_INDEX_WIDTH) % (MemWords<<3); end `APPL_WAIT_CYC(clk_i,1) dut_req_port_o.data_req = '0; end dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.kill_req = '0; endtask : genSetSeqRead task automatic genWrapSeq(); automatic logic [63:0] val; paddr = CachedAddrBeg; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.kill_req = '0; val = '0; while(~seq_end_req) begin dut_req_port_o.data_req = 1'b1; dut_req_port_o.data_size = 2'b11; paddr = val; // generate wrapping read of 1 cachelines paddr = CachedAddrBeg + val; val = (val + 8) % (1*(DCACHE_LINE_WIDTH/64)*8); `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) `APPL_WAIT_CYC(clk_i,1) end dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.kill_req = '0; endtask : genWrapSeq /////////////////////////////////////////////////////////////////////////////// // Sequence application /////////////////////////////////////////////////////////////////////////////// initial begin : p_stim paddr = '0; dut_req_port_o.data_wdata = '0; dut_req_port_o.data_req = '0; dut_req_port_o.data_we = '0; dut_req_port_o.data_be = '0; dut_req_port_o.data_size = '0; dut_req_port_o.kill_req = '0; seq_end_ack = '0; flush_o = '0; // print some info $display("%s> current configuration:", PortName); $display("%s> KillRate %d", PortName, KillRate); $display("%s> FlushRate %d", PortName, FlushRate); $display("%s> TlbHitRate %d", PortName, TlbHitRate); $display("%s> RndSeed %d", PortName, RndSeed); `APPL_WAIT_CYC(clk_i,1) `APPL_WAIT_SIG(clk_i,~rst_ni) $display("%s> starting application", PortName); while(~seq_last_i) begin `APPL_WAIT_SIG(clk_i,seq_run_i) unique case(seq_type_i) RANDOM_SEQ: begin $display("%s> start random sequence with %04d responses and req_rate %03d", PortName, seq_num_resp_i, req_rate_i); genRandReq(); end LINEAR_SEQ: begin $display("%s> start linear sequence with %04d responses and req_rate %03d", PortName, seq_num_resp_i, req_rate_i); genSeqRead(); end SET_SEQ: begin $display("%s> start set sequence with %04d responses and req_rate %03d", PortName, seq_num_resp_i, req_rate_i); genSetSeqRead(); end WRAP_SEQ: begin $display("%s> start wrapping sequence with %04d responses and req_rate %03d", PortName, seq_num_resp_i, req_rate_i); genWrapSeq(); end IDLE_SEQ: begin `APPL_WAIT_SIG(clk_i,seq_end_req) end BURST_SEQ: begin $fatal(1, "Burst sequence not implemented for read port agent"); end CONST_SEQ: begin $fatal(1, "Constant sequence not implemented for read port agent."); end endcase // seq_type_i seq_end_ack = 1'b1; $display("%s> stop sequence", PortName); `APPL_WAIT_CYC(clk_i,1) seq_end_ack = 1'b0; end $display("%s> ending application", PortName); end /////////////////////////////////////////////////////////////////////////////// // Response acquisition /////////////////////////////////////////////////////////////////////////////// initial begin : p_acq bit ok; progress status; string failingTests, tmpstr1, tmpstr2; int n; logic [63:0] exp_rdata, exp_paddr; logic [1:0] exp_size; status = new(PortName); failingTests = ""; seq_done_o = 1'b0; seq_end_req = 1'b0; prog_end = 1'b0; `ACQ_WAIT_CYC(clk_i,1) `ACQ_WAIT_SIG(clk_i,~rst_ni) /////////////////////////////////////////////// // loop over tests n=0; while(~seq_last_i) begin `ACQ_WAIT_SIG(clk_i,seq_run_i) seq_done_o = 1'b0; $display("%s> %s", PortName, test_name_i); status.reset(seq_num_resp_i); for (int k=0;k<seq_num_resp_i && seq_type_i != IDLE_SEQ;k++) begin `ACQ_WAIT_SIG(clk_i, (dut_req_port_i.data_rvalid & ~dut_req_port_o.kill_req)) exp_rdata = 'x; unique case(exp_size_i) 2'b00: exp_rdata[exp_paddr_i[2:0]*8 +: 8] = exp_rdata_i[exp_paddr_i[2:0]*8 +: 8]; 2'b01: exp_rdata[exp_paddr_i[2:1]*16 +: 16] = exp_rdata_i[exp_paddr_i[2:1]*16 +: 16]; 2'b10: exp_rdata[exp_paddr_i[2] *32 +: 32] = exp_rdata_i[exp_paddr_i[2] *32 +: 32]; 2'b11: exp_rdata = exp_rdata_i; endcase // exp_size // note: wildcard as defined in right operand! ok=(dut_req_port_i.data_rdata ==? exp_rdata) && (exp_paddr_i == act_paddr_i); if(Verbose | !ok) begin tmpstr1 = $psprintf("vector: %02d - %06d -- exp_paddr: %16X -- exp_data: %16X -- access size: %01d Byte", n, k, exp_paddr_i, exp_rdata, 2**exp_size_i); tmpstr2 = $psprintf("vector: %02d - %06d -- act_paddr: %16X -- act_data: %16X -- access size: %01d Byte", n, k, act_paddr_i, dut_req_port_i.data_rdata, 2**exp_size_i); $display("%s> %s", PortName, tmpstr1); $display("%s> %s", PortName, tmpstr2); end if(!ok) begin failingTests = $psprintf("%s%s> %s\n%s> %s\n", failingTests, PortName, tmpstr1, PortName, tmpstr2); end status.addRes(!ok); status.print(); end seq_end_req = 1'b1; `ACQ_WAIT_SIG(clk_i, seq_end_ack) seq_end_req = 1'b0; `ACQ_WAIT_CYC(clk_i,1) seq_done_o = 1'b1; n++; end /////////////////////////////////////////////// status.printToFile({PortName, "_summary.rep"}, 1); if(status.totErrCnt == 0) begin $display("%s> ----------------------------------------------------------------------", PortName); $display("%s> PASSED %0d VECTORS", PortName, status.totAcqCnt); $display("%s> ----------------------------------------------------------------------\n", PortName); end else begin $display("%s> ----------------------------------------------------------------------\n", PortName); $display("%s> FAILED %0d OF %0d VECTORS\n", PortName , status.totErrCnt, status.totAcqCnt); $display("%s> failing tests:", PortName); $display("%s", failingTests); $display("%s> ----------------------------------------------------------------------\n", PortName); end prog_end = 1'b1; end endprogram // tb_readport
// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // or agreed to in writing, software, hardware and materials distributed under // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. // // Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich // Date: 15.08.2018 // Description: program that emulates a cache write port. the program can generate // randomized or linear read sequences. // `include "tb.svh" program tb_writeport import tb_pkg::*; import ariane_pkg::*; #( parameter string PortName = "write port 0", parameter MemWords = 1024*1024,// in 64bit words parameter logic [63:0] CachedAddrBeg = 0, parameter logic [63:0] CachedAddrEnd = 0, parameter RndSeed = 1110, parameter Verbose = 0 ) ( input logic clk_i, input logic rst_ni, // to testbench master ref string test_name_i, input logic [6:0] req_rate_i, input seq_t seq_type_i, input logic seq_run_i, input logic [31:0] seq_num_vect_i, input logic seq_last_i, output logic seq_done_o, // interface to DUT output dcache_req_i_t dut_req_port_o, input dcache_req_o_t dut_req_port_i ); // leave this timeunit 1ps; timeprecision 1ps; logic [63:0] paddr; assign dut_req_port_o.address_tag = paddr[DCACHE_TAG_WIDTH+DCACHE_INDEX_WIDTH-1:DCACHE_INDEX_WIDTH]; assign dut_req_port_o.address_index = paddr[DCACHE_INDEX_WIDTH-1:0]; assign dut_req_port_o.data_we = dut_req_port_o.data_req; /////////////////////////////////////////////////////////////////////////////// // Helper tasks /////////////////////////////////////////////////////////////////////////////// task automatic applyRandData(); automatic logic [63:0] val; automatic logic [7:0] be; automatic logic [1:0] size; void'(randomize(size)); // align to size, set correct byte enables be = '0; unique case(size) 2'b00: be[paddr[2:0] +: 1] = '1; 2'b01: be[paddr[2:1]<<1 +: 2] = '1; 2'b10: be[paddr[2:2]<<2 +: 4] = '1; 2'b11: be = '1; default: ; endcase paddr[2:0] = '0; void'(randomize(val)); for(int k=0; k<8; k++) begin if( be[k] ) begin dut_req_port_o.data_wdata[k*8 +: 8] = val[k*8 +: 8]; end end dut_req_port_o.data_be = be; dut_req_port_o.data_size = size; endtask : applyRandData task automatic genRandReq(); automatic logic [63:0] val; void'($urandom(RndSeed)); paddr = '0; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.data_be = '0; dut_req_port_o.data_wdata = 'x; repeat(seq_num_vect_i) begin // randomize request dut_req_port_o.data_req = '0; dut_req_port_o.data_be = '0; dut_req_port_o.data_wdata = 'x; void'(randomize(val) with {val > 0; val <= 100;}); if(val < req_rate_i) begin dut_req_port_o.data_req = 1'b1; // generate random address void'(randomize(paddr) with {paddr >= 0; paddr < (MemWords<<3);}); applyRandData(); `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) end `APPL_WAIT_CYC(clk_i,1) end paddr = '0; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.data_be = '0; dut_req_port_o.data_wdata = 'x; endtask : genRandReq task automatic genSeqWrite(); automatic logic [63:0] val; paddr = '0; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.data_be = '0; dut_req_port_o.data_wdata = 'x; val = '0; repeat(seq_num_vect_i) begin dut_req_port_o.data_req = 1'b1; dut_req_port_o.data_size = 2'b11; dut_req_port_o.data_be = '1; dut_req_port_o.data_wdata = val; paddr = val; // generate linear read val = (val + 8) % (MemWords<<3); `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) `APPL_WAIT_CYC(clk_i,1) end paddr = '0; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.data_be = '0; dut_req_port_o.data_wdata = 'x; endtask : genSeqWrite // Repeadedly write to the same address task automatic genConstWrite(); automatic logic [63:0] val; paddr = CachedAddrBeg; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.data_be = '0; dut_req_port_o.data_wdata = 'x; repeat(seq_num_vect_i) begin void'(randomize(val)); dut_req_port_o.data_req = 1'b1; dut_req_port_o.data_size = 2'b11; dut_req_port_o.data_be = '1; dut_req_port_o.data_wdata = val; `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) `APPL_WAIT_CYC(clk_i,1) end paddr = '0; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.data_be = '0; dut_req_port_o.data_wdata = 'x; endtask : genConstWrite task automatic genWrapSeq(); automatic logic [63:0] val; void'($urandom(RndSeed)); paddr = CachedAddrBeg; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.data_be = '0; dut_req_port_o.data_wdata = 'x; val = '0; repeat(seq_num_vect_i) begin dut_req_port_o.data_req = 1'b1; applyRandData(); // generate wrapping read of 1 cacheline paddr = CachedAddrBeg + val; val = (val + 8) % (1*(DCACHE_LINE_WIDTH/64)*8); `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) `APPL_WAIT_CYC(clk_i,1) end paddr = '0; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.data_be = '0; dut_req_port_o.data_wdata = 'x; endtask : genWrapSeq task automatic genSeqBurst(); automatic logic [63:0] val; automatic logic [7:0] be; automatic logic [1:0] size; automatic int cnt, burst_len; void'($urandom(RndSeed)); paddr = '0; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.data_be = '0; dut_req_port_o.data_wdata = 'x; cnt = 0; while(cnt < seq_num_vect_i) begin // randomize request dut_req_port_o.data_req = '0; dut_req_port_o.data_be = '0; dut_req_port_o.data_wdata = 'x; void'(randomize(val) with {val > 0; val <= 100;}); if(val < req_rate_i) begin dut_req_port_o.data_req = 1'b1; // generate random address base void'(randomize(paddr) with {paddr >= 0; paddr < (MemWords<<3);}); // do a random burst void'(randomize(burst_len) with {burst_len >= 1; burst_len < 100;}); for(int k=0; k<burst_len && cnt < seq_num_vect_i && paddr < ((MemWords-1)<<3); k++) begin applyRandData(); `APPL_WAIT_COMB_SIG(clk_i, dut_req_port_i.data_gnt) `APPL_WAIT_CYC(clk_i,1) //void'(randomize(val) with {val>=0 val<=8;};); paddr += 8; cnt ++; end end end paddr = '0; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.data_be = '0; dut_req_port_o.data_wdata = 'x; endtask : genSeqBurst /////////////////////////////////////////////////////////////////////////////// // Sequence application /////////////////////////////////////////////////////////////////////////////// initial begin : p_stim paddr = '0; dut_req_port_o.data_req = '0; dut_req_port_o.data_size = '0; dut_req_port_o.data_be = '0; dut_req_port_o.data_wdata = '0; dut_req_port_o.tag_valid = '0; dut_req_port_o.kill_req = '0; seq_done_o = 1'b0; // print some info $display("%s> current configuration:", PortName); $display("%s> RndSeed %d", PortName, RndSeed); `APPL_WAIT_CYC(clk_i,1) `APPL_WAIT_SIG(clk_i,~rst_ni) $display("%s> starting application", PortName); while(~seq_last_i) begin `APPL_WAIT_SIG(clk_i,seq_run_i) seq_done_o = 1'b0; unique case(seq_type_i) RANDOM_SEQ: begin $display("%s> start random sequence with %04d vectors and req_rate %03d", PortName, seq_num_vect_i, req_rate_i); genRandReq(); end LINEAR_SEQ: begin $display("%s> start linear sequence with %04d vectors and req_rate %03d", PortName, seq_num_vect_i, req_rate_i); genSeqWrite(); end CONST_SEQ: begin $display("%s> start constant sequence with %04d vectors and req_rate %03d", PortName, seq_num_vect_i, req_rate_i); genConstWrite(); end WRAP_SEQ: begin $display("%s> start wrapping sequence with %04d vectors and req_rate %03d", PortName, seq_num_vect_i, req_rate_i); genWrapSeq(); end IDLE_SEQ: ;// do nothing BURST_SEQ: begin $display("%s> start burst sequence with %04d vectors and req_rate %03d", PortName, seq_num_vect_i, req_rate_i); genSeqBurst(); end SET_SEQ: begin $fatal(1, "Set sequence not implemented for write port agent."); end endcase // seq_type_i seq_done_o = 1'b1; $display("%s> stop sequence", PortName); `APPL_WAIT_CYC(clk_i,1) end $display("%s> ending application", PortName); end endprogram // tb_readport
// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // or agreed to in writing, software, hardware and materials distributed under // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. // // Author: Unknown // Date: Unknown // Description: This module takes data over UART and prints them to the console // A string is printed to the console as soon as a '\n' character is found interface uart_bus #( parameter int unsigned BAUD_RATE = 115200, parameter int unsigned PARITY_EN = 0 )( input logic rx, output logic tx, input logic rx_en ); /* pragma translate_off */ `ifndef VERILATOR localparam time BIT_PERIOD = (1000000000 / BAUD_RATE) * 1ns; logic [7:0] character; logic [256*8-1:0] stringa; logic parity; integer charnum; integer file; initial begin tx = 1'bZ; file = $fopen("uart", "w"); end always begin if (rx_en) begin @(negedge rx); #(BIT_PERIOD/2); for (int i = 0; i <= 7; i++) begin #BIT_PERIOD character[i] = rx; end if (PARITY_EN == 1) begin // check parity #BIT_PERIOD parity = rx; for (int i=7;i>=0;i--) begin parity = character[i] ^ parity; end if (parity == 1'b1) begin $display("Parity error detected"); end end // STOP BIT #BIT_PERIOD; $fwrite(file, "%c", character); stringa[(255-charnum)*8 +: 8] = character; if (character == 8'h0A || charnum == 254) begin // line feed or max. chars reached if (character == 8'h0A) begin stringa[(255-charnum)*8 +: 8] = 8'h0; // null terminate string, replace line feed end else begin stringa[(255-charnum-1)*8 +: 8] = 8'h0; // null terminate string end $write("[UART]: %s\n", stringa); charnum = 0; stringa = ""; end else begin charnum = charnum + 1; end end else begin charnum = 0; stringa = ""; #10; end end task send_char(input logic [7:0] c); int i; // start bit tx = 1'b0; for (i = 0; i < 8; i++) begin #(BIT_PERIOD); tx = c[i]; end // stop bit #(BIT_PERIOD); tx = 1'b1; #(BIT_PERIOD); endtask `endif /* pragma translate_on */ endinterface
# EditorConfig (http://editorconfig.org/) root = true # Default Settings [*] charset = utf-8 end_of_line = lf indent_size = 4 indent_style = space insert_final_newline = true tab_width = 4 trim_trailing_whitespace = true max_line_length = 100 [Makefile] indent_style = tab [{*.sv,*.svh}] indent_size = 2 [*.yml] indent_size = 2
gitdir: ../../../.git/modules/corev_apu/tb/common_verification
package: name: common_verification authors: - "Andreas Kurth <akurth@iis.ee.ethz.ch>" sources: # Files in this package are meant for simulation only. - target: simulation files: # Source files grouped in levels. Files in level 0 have no dependencies on files in this # package. Files in level 1 only depend on files in level 0, files in level 2 on files in # levels 1 and 0, etc. Files within a level are ordered alphabetically. # Level 0 - src/clk_rst_gen.sv - src/rand_id_queue.sv - src/rand_stream_mst.sv - src/rand_synch_holdable_driver.sv - src/rand_verif_pkg.sv - src/sim_timeout.sv # Level 1 - src/rand_synch_driver.sv # Level 2 - src/rand_stream_slv.sv
# Changelog All notable changes to this project will be documented in this file. The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/) and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html). ## Unreleased ## v0.2.0 - 2019-08-20 ### Added - Add module to timeout simulations. ### Changed - Remove `timeunit` and `timeprecision` declarations from all modules. Multiple simulators do not properly implement precedence of these declarations (IEEE 1800-2012, 3.14.2.3), so we now avoid the declarations in favor of a simulation-wide precision declaration. - Rename parameters to comply with style guidelines. ## v0.1.2 - 2019-08-20 ### Fixed - rand_synch_driver: Fix instantiation of `rand_synch_holdable_driver`. - rand_stream_slv: Fix instantiation of `rand_sync_driver`. ## v0.1.1 - 2019-02-26 ### Fixed - Move all files into the `simulation` target. This precludes synthesis of files in this package when this package is included as dependency. ## v0.1.0 - 2019-02-25 ### Added - Add standalone clock and reset generator. - Add randomizing synchronous driver and holdable driver. - Add randomizing stream master and slave. - Add ID queue with randomizing output. - Add `rand_verif_pkg` with task to wait for a random number (within interval) of clock cycles.
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# Common Verification This repository contains commonly used SystemVerilog modules and classes for verification. This code is generally not synthesizable. ## Contents ### Basic Modules | Name | Description | Status | |---------------|---------------------------------------|--------| | `clk_rst_gen` | Standalone clock and reset generator | active | | `sim_timeout` | Timeout for simulations | active | ### Generic Functions and Tasks `rand_verif_pkg` defines the following functions and tasks: | Name | Description | Status | |---------------------|-------------------------------------------------------------|--------| | `rand_wait` | Wait for a random number (within interval) of clock cycles | active | ### Simple Synchronous Drivers | Name | Description | Status | |-------------------------------|---------------------------------------------------|--------| | `rand_synch_driver` | Randomizing synchronous driver | active | | `rand_synch_holdable_driver` | Randomizing synchronous driver that can be halted | active | ### Stream (Ready/Valid) Masters and Slaves | Name | Description | Status | |-------------------|---------------------------------------|--------| | `rand_stream_mst` | Randomizing stream master | active | | `rand_stream_slv` | Randomizing stream slave | active | ### Data Structures | Name | Description | Status | |-------------------|---------------------------------------|--------| | `rand_id_queue` | ID queue with randomizing output | active |
// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // or agreed to in writing, software, hardware and materials distributed under // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. // Clock and Reset Generator module clk_rst_gen #( parameter time ClkPeriod = 0ps, // minimum: 2ps parameter int unsigned RstClkCycles = 0 ) ( output logic clk_o, output logic rst_no ); logic clk; // Clock Generation initial begin clk = 1'b0; end always begin clk = ~clk; #(ClkPeriod / 2); end assign clk_o = clk; // Reset Generation initial begin static int unsigned rst_cnt = 0; rst_no = 1'b0; while (rst_cnt <= RstClkCycles) begin @(posedge clk); rst_cnt++; end rst_no = 1'b1; end // Validate parameters. `ifndef VERILATOR initial begin: validate_params assert (ClkPeriod >= 2ps) else $fatal("The clock period must be at least 2ps!"); // Reason: Gets divided by two, and some simulators do not support non-integer time steps, so // if the time unit is 1ps, this would fail. assert (RstClkCycles > 0) else $fatal("The number of clock cycles in reset must be greater than 0!"); end `endif endmodule
// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // or agreed to in writing, software, hardware and materials distributed under // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. // Wrapper package so class can be used after `import rand_id_queue_pkg::*;`. package rand_id_queue_pkg; // ID Queue with Randomizing Output class rand_id_queue #( type data_t = logic, int unsigned ID_WIDTH = 0 ); localparam int unsigned N_IDS = 2**ID_WIDTH; localparam type id_t = logic[ID_WIDTH-1:0]; data_t queues[N_IDS-1:0][$]; int unsigned size; function new(); size = 0; endfunction // Push a data element to the queue with the given ID. function void push(id_t id, data_t data); queues[id].push_back(data); size++; endfunction // Determine if the ID queue is empty. function bit empty(); return (size == 0); endfunction // Pick a non-empty queue at random and return the front element. Not defined if the ID queue is // empty. function data_t peek(); return queues[rand_id()][0]; endfunction // Pick a non-empty queue at random, remove the front element from that queue, and return that // element. Not defined if the ID queue is empty. function data_t pop(); return pop_id(rand_id()); endfunction // Remove the front element of the queue with the given ID and return that element. Not defined // if the queue with the given ID is empty. function data_t pop_id(id_t id); size--; return queues[id].pop_front(); endfunction // Pick a non-empty queue at random and return the ID of that queue. Not defined if the ID queue // is empty. function id_t rand_id(); if (!empty()) begin id_t id; do begin void'(std::randomize(id)); end while (queues[id].size() == 0); return id; end else begin return 'x; end endfunction // Set the front element of the queue with the given ID. Not defined if the queue with the given // ID is empty; instead use `push()` to insert a new element. function void set(id_t id, data_t data); queues[id][0] = data; endfunction // Get the front element of the queue with the given ID. Not defined if the queue with the given // ID is empty. function data_t get(id_t id); return queues[id][0]; endfunction endclass endpackage
// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // or agreed to in writing, software, hardware and materials distributed under // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. // Randomizing Stream (Ready/Valid) Master module rand_stream_mst #( parameter type data_t = logic, // Minimum number of clock cycles to wait between applying two consecutive values. parameter int MinWaitCycles = -1, // Maximum number of clock cycles to wait between applying two consecutive values. parameter int MaxWaitCycles = -1, // Application delay: time delay before output changes after an active clock edge. parameter time ApplDelay = 0ps, // Acquisition delay: time delay before ready input is read after an active clock edge. parameter time AcqDelay = 0ps ) ( input logic clk_i, input logic rst_ni, output data_t data_o, output logic valid_o, input logic ready_i ); int unsigned rand_wait_cycles; function static void randomize_wait_cycles(); int unsigned rand_success; rand_success = std::randomize(rand_wait_cycles) with { rand_wait_cycles >= MinWaitCycles; rand_wait_cycles <= MaxWaitCycles; }; assert (rand_success) else $error("Failed to randomize wait cycles!"); endfunction initial begin data_o = '0; valid_o = 1'b0; wait (rst_ni); // Initially pick a random number of cycles to wait until we offer the first valid data. randomize_wait_cycles(); @(posedge clk_i); forever begin // Wait for the picked number of clock cycles. repeat(rand_wait_cycles) begin @(posedge clk_i); end // Delay application of data and valid output. #(ApplDelay); // Randomize data output and set valid output. void'(std::randomize(data_o)); valid_o = 1'b1; // Delay acquisition of ready signal. AcqDelay is relative to the clock edge, and we have // already waited for ApplDelay in this edge, so we need to subtract ApplDelay. #(AcqDelay-ApplDelay); // Sample the ready input. While the slave is not ready, wait a clock cycle plus the // acquisition delay and resample the ready input. while (!ready_i) begin @(posedge clk_i); #(AcqDelay); end // The slave is ready to acquire data on the next rising edge, so we pick a new number of // cycles to wait until we offer the next valid data. randomize_wait_cycles(); if (rand_wait_cycles == 0) begin // If we have to wait 0 cycles, we apply new data directly after next clock edge plus the // application delay. @(posedge clk_i); end else begin // If we have to wait more than 0 cycles, we unset the valid output and randomize the data // output after the next clock edge plus the application delay. @(posedge clk_i); #(ApplDelay); valid_o = 1'b0; void'(std::randomize(data_o)); end end end // Validate parameters. `ifndef VERILATOR initial begin: validate_params assert (MinWaitCycles >= 0) else $fatal("The minimum number of wait cycles must be at least 0!"); assert (MaxWaitCycles >= 0) else $fatal("The maximum number of wait cycles must be at least 0!"); assert (MaxWaitCycles >= MinWaitCycles) else $fatal("The maximum number of wait cycles must be at least the minimum number of wait cycles!"); assert (ApplDelay > 0ps) else $fatal("The application delay must be greater than 0!"); assert (AcqDelay > 0ps) else $fatal("The acquisition delay must be greater than 0!"); assert (AcqDelay > ApplDelay) else $fatal("The acquisition delay must be greater than the application delay!"); end `endif endmodule
// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // or agreed to in writing, software, hardware and materials distributed under // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. // Randomizing Stream (Ready/Valid) Slave module rand_stream_slv #( parameter type data_t = logic, // Minimum number of clock cycles to wait between applying two consecutive values. parameter int MinWaitCycles = -1, // Maximum number of clock cycles to wait between applying two consecutive values. parameter int MaxWaitCycles = -1, // Application delay: time delay before output changes after an active clock edge. parameter time ApplDelay = 0ps, // Acquisition delay: time delay before ready input is read after an active clock edge. parameter time AcqDelay = 0ps, // Store each inupt beat in an internal queue. parameter bit Enqueue = 1'b0 ) ( input logic clk_i, input logic rst_ni, input data_t data_i, input logic valid_i, output logic ready_o ); if (Enqueue) begin: gen_queue data_t queue[$]; always @(posedge clk_i, negedge rst_ni) begin if (!rst_ni) begin queue = {}; end else begin #(AcqDelay); if (valid_i && ready_o) begin queue.push_back(data_i); end end end end rand_synch_driver #( .data_t (logic), .MinWaitCycles (MinWaitCycles), .MaxWaitCycles (MaxWaitCycles), .ApplDelay (ApplDelay) ) i_ready_driver ( .clk_i (clk_i), .rst_ni (rst_ni), .data_o (ready_o) ); `ifndef VERILATOR initial begin: validate_params assert (AcqDelay > 0ps) else $fatal("The acquisition delay must be greater than 0!"); assert (AcqDelay > ApplDelay) else $fatal("The acquisition delay must be greater than the application delay!"); end `endif endmodule
// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // or agreed to in writing, software, hardware and materials distributed under // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. // Randomizing Synchronous Driver module rand_synch_driver #( parameter type data_t = logic, // Minimum number of clock cycles to wait between applying two consecutive values. parameter int MinWaitCycles = -1, // Maximum number of clock cycles to wait between applying two consecutive values. parameter int MaxWaitCycles = -1, // Application delay: time delay before output changes after an active clock edge. parameter time ApplDelay = 0ps ) ( input logic clk_i, input logic rst_ni, output data_t data_o ); rand_synch_holdable_driver #( .data_t (data_t), .MinWaitCycles (MinWaitCycles), .MaxWaitCycles (MaxWaitCycles), .ApplDelay (ApplDelay) ) i_ready_driver ( .clk_i (clk_i), .rst_ni (rst_ni), .hold_i (1'b0), .data_o (data_o) ); endmodule
// Copyright 2018 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // or agreed to in writing, software, hardware and materials distributed under // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. // Randomizing Synchronous Holdable Driver module rand_synch_holdable_driver #( parameter type data_t = logic, // Minimum number of clock cycles to wait between applying two consecutive values. parameter int MinWaitCycles = -1, // Maximum number of clock cycles to wait between applying two consecutive values. parameter int MaxWaitCycles = -1, // Application delay: time delay before output changes after an active clock edge. parameter time ApplDelay = 0ps ) ( input logic clk_i, input logic rst_ni, input logic hold_i, output data_t data_o ); initial begin int unsigned rand_delay, rand_success; data_o = '0; wait (rst_ni); @(posedge clk_i); forever begin rand_success = std::randomize(rand_delay) with { rand_delay >= MinWaitCycles; rand_delay <= MaxWaitCycles; }; assert (rand_success) else $error("Failed to randomize wait cycles!"); repeat(rand_delay) begin @(posedge clk_i); end #(ApplDelay); if (!hold_i) begin void'(std::randomize(data_o)); end end end // Validate parameters. `ifndef VERILATOR initial begin: validate_params assert (MinWaitCycles >= 0) else $fatal("The minimum number of wait cycles must be at least 0!"); assert (MaxWaitCycles >= 0) else $fatal("The maximum number of wait cycles must be at least 0!"); assert (MaxWaitCycles >= MinWaitCycles) else $fatal("The maximum number of wait cycles must be at least the minimum number of wait cycles!"); assert (ApplDelay > 0ps) else $fatal("The application delay must be greater than 0!"); end `endif endmodule
// Copyright (c) 2019 ETH Zurich, University of Bologna // // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // or agreed to in writing, software, hardware and materials distributed under // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. // Package with functions and tasks commonly used in constrained randomized verification package rand_verif_pkg; // Pick a random number from the interval [min, max] and wait for that number of clock cyles. task automatic rand_wait(input int unsigned min, max, ref logic clk); int unsigned rand_success, cycles; rand_success = randomize(cycles) with { cycles >= min; cycles <= max; }; assert (rand_success) else $error("Failed to randomize wait cycles!"); repeat (cycles) @(posedge clk); endtask endpackage
module sim_timeout #( parameter longint unsigned Cycles = 0, parameter bit ResetRestartsTimeout = 1'b0 ) ( input logic clk_i, input logic rst_ni ); longint unsigned cycles = 0; always_ff @(posedge clk_i, negedge rst_ni) begin if (ResetRestartsTimeout && !rst_ni) begin cycles <= 0; end else begin cycles <= cycles + 1; end if (cycles > Cycles) begin $fatal(1, "Timeout exceeded!"); end end `ifndef VERILATOR initial begin: validate_params assert (Cycles > 0) else $fatal("The number of timeout cycles must be greater than 0!"); end `endif endmodule
// Auto-generated code const int reset_vec_size = 372; uint32_t reset_vec[reset_vec_size] = { 0x00100413, 0x01f41413, 0xf1402573, 0x00000597, 0x07458593, 0x00040067, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xf1402573, 0x00000597, 0x03c58593, 0x10500073, 0xffdff06f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xedfe0dd0, 0x4a050000, 0x38000000, 0x44040000, 0x28000000, 0x11000000, 0x10000000, 0x00000000, 0x06010000, 0x0c040000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000, 0x03000000, 0x04000000, 0x00000000, 0x02000000, 0x03000000, 0x04000000, 0x0f000000, 0x02000000, 0x03000000, 0x14000000, 0x1b000000, 0x2c687465, 0x61697261, 0x622d656e, 0x2d657261, 0x00766564, 0x03000000, 0x10000000, 0x26000000, 0x2c687465, 0x61697261, 0x622d656e, 0x00657261, 0x01000000, 0x73757063, 0x00000000, 0x03000000, 0x04000000, 0x00000000, 0x01000000, 0x03000000, 0x04000000, 0x0f000000, 0x00000000, 0x03000000, 0x04000000, 0x2c000000, 0x00800000, 0x01000000, 0x40757063, 0x00000030, 0x03000000, 0x04000000, 0x3f000000, 0x80f0fa02, 0x03000000, 0x04000000, 0x4f000000, 0x00757063, 0x03000000, 0x04000000, 0x5b000000, 0x00000000, 0x03000000, 0x05000000, 0x5f000000, 0x79616b6f, 0x00000000, 0x03000000, 0x12000000, 0x1b000000, 0x2c687465, 0x69726120, 0x00656e61, 0x63736972, 0x00000076, 0x03000000, 0x0b000000, 0x66000000, 0x34367672, 0x66616d69, 0x00006364, 0x03000000, 0x0b000000, 0x70000000, 0x63736972, 0x76732c76, 0x00003933, 0x03000000, 0x00000000, 0x79000000, 0x01000000, 0x65746e69, 0x70757272, 0x6f632d74, 0x6f72746e, 0x72656c6c, 0x00000000, 0x03000000, 0x04000000, 0x83000000, 0x01000000, 0x03000000, 0x00000000, 0x94000000, 0x03000000, 0x0f000000, 0x1b000000, 0x63736972, 0x70632c76, 0x6e692d75, 0x00006374, 0x03000000, 0x04000000, 0xa9000000, 0x01000000, 0x02000000, 0x02000000, 0x02000000, 0x01000000, 0x6f6d656d, 0x38407972, 0x30303030, 0x00303030, 0x03000000, 0x07000000, 0x4f000000, 0x6f6d656d, 0x00007972, 0x03000000, 0x10000000, 0x5b000000, 0x00000000, 0x00000080, 0x00000000, 0x00000010, 0x02000000, 0x01000000, 0x00636f73, 0x03000000, 0x04000000, 0x00000000, 0x02000000, 0x03000000, 0x04000000, 0x0f000000, 0x02000000, 0x03000000, 0x1f000000, 0x1b000000, 0x2c687465, 0x61697261, 0x622d656e, 0x2d657261, 0x00636f73, 0x706d6973, 0x622d656c, 0x00007375, 0x03000000, 0x00000000, 0xb1000000, 0x01000000, 0x6e696c63, 0x30324074, 0x30303030, 0x00000030, 0x03000000, 0x0d000000, 0x1b000000, 0x63736972, 0x6c632c76, 0x30746e69, 0x00000000, 0x03000000, 0x10000000, 0xb8000000, 0x01000000, 0x03000000, 0x01000000, 0x07000000, 0x03000000, 0x10000000, 0x5b000000, 0x00000000, 0x00000002, 0x00000000, 0x00000c00, 0x03000000, 0x08000000, 0xcc000000, 0x746e6f63, 0x006c6f72, 0x02000000, 0x01000000, 0x74726175, 0x30303140, 0x30303030, 0x00000030, 0x03000000, 0x09000000, 0x1b000000, 0x3631736e, 0x61303535, 0x00000000, 0x03000000, 0x10000000, 0x5b000000, 0x00000000, 0x00000010, 0x00000000, 0x00100000, 0x03000000, 0x04000000, 0x3f000000, 0x80f0fa02, 0x03000000, 0x04000000, 0xd6000000, 0x00c20100, 0x03000000, 0x04000000, 0xe4000000, 0x01000000, 0x03000000, 0x04000000, 0xef000000, 0x02000000, 0x03000000, 0x04000000, 0xf9000000, 0x04000000, 0x02000000, 0x01000000, 0x656d6974, 0x38314072, 0x30303030, 0x00003030, 0x03000000, 0x0f000000, 0x1b000000, 0x706c7570, 0x6270612c, 0x6d69745f, 0x00007265, 0x03000000, 0x10000000, 0xe4000000, 0x04000000, 0x05000000, 0x06000000, 0x07000000, 0x03000000, 0x10000000, 0x5b000000, 0x00000000, 0x00000018, 0x00000000, 0x00100000, 0x03000000, 0x08000000, 0xcc000000, 0x746e6f63, 0x006c6f72, 0x02000000, 0x02000000, 0x02000000, 0x09000000, 0x64646123, 0x73736572, 0x6c65632d, 0x2300736c, 0x657a6973, 0x6c65632d, 0x6300736c, 0x61706d6f, 0x6c626974, 0x6f6d0065, 0x006c6564, 0x656d6974, 0x65736162, 0x6572662d, 0x6e657571, 0x63007963, 0x6b636f6c, 0x6572662d, 0x6e657571, 0x64007963, 0x63697665, 0x79745f65, 0x72006570, 0x73006765, 0x75746174, 0x69720073, 0x2c766373, 0x00617369, 0x2d756d6d, 0x65707974, 0x626c7400, 0x6c70732d, 0x23007469, 0x65746e69, 0x70757272, 0x65632d74, 0x00736c6c, 0x65746e69, 0x70757272, 0x6f632d74, 0x6f72746e, 0x72656c6c, 0x61687000, 0x656c646e, 0x6e617200, 0x00736567, 0x65746e69, 0x70757272, 0x652d7374, 0x6e657478, 0x00646564, 0x2d676572, 0x656d616e, 0x75630073, 0x6e657272, 0x70732d74, 0x00646565, 0x65746e69, 0x70757272, 0x72007374, 0x732d6765, 0x74666968, 0x67657200, 0x2d6f692d, 0x74646977, 0x00000068, 0x00000000 };
// Copyright 2017-2020 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the "License"); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law // or agreed to in writing, software, hardware and materials distributed under // this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. // // Author: Nursultan Kabylkas, UCSC // Date: Jun 15, 2020 // Description: DPI wrappers to interface with Dromajo RISC-V emulator #include <svdpi.h> #include <iostream> #include "dromajo_cosim.h" #include "stdlib.h" #include <string> #include <vector> /** * pointer to the dromajo emulator this pointer gets * accessed from RTL */ dromajo_cosim_state_t* dromajo_pointer; /** * set the counter variable to number of instructions * you want to commit after the cosim failure. This is * sometimes useful when debugging to see waveform * activity post failure */ bool kill_soon = false; uint32_t counter = 0; /** * Initialize dromajo emulator * * This function should usually be called from the initial * block in RTL. * * @param config (.cfg) file with the configurations */ extern "C" void init_dromajo(char* cfg_f_name) { char *argv[] = {(char*)"Variane", cfg_f_name}; dromajo_pointer = dromajo_cosim_init(2, argv); } /** * Progress the emulator * * This function progresses the emulator by one instruction * and compares the results by the committed instruction * in RTL. The following parameters are passed from RTL to * dromajo for comparison purposes. * * @param hart_id - id of the HART that is commiting instruction * @param pc - pc of the instruction being committed * @param insn - RISCV instruction being committed * @param wdata - the value being committed (what's going to destination register) * @param cycle - clock cycle number (optional, this is not compared) */ extern "C" void dromajo_step(int hart_id, uint64_t pc, uint32_t insn, uint64_t wdata, uint64_t cycle) { int exit_code; do { exit_code = dromajo_cosim_step(dromajo_pointer, hart_id, pc, insn, wdata, 0, true); } while (exit_code == 0x3); if (exit_code > 3) { kill_soon = true; } else if (exit_code == 0x2){ exit(0); } if (kill_soon) { if (counter == 0) { std::cout << "Cosim failed!" << std::endl; exit(1); } else { std::cout << "Let's let it run for a couple of instructions" << std::endl; } counter--; } } /** * Redirects dromajo's execution flow on exception/interrupt * * @param hart_id - id of the HART that is trapping * @param cause - exception or interrupt cause */ extern "C" void dromajo_trap(int hart_id, uint64_t cause) { std::cout << "Dromajo trapping. Cause = " << cause << std::endl; dromajo_cosim_raise_trap(dromajo_pointer, hart_id, cause); }
#include <fesvr/elf.h> #include <fesvr/memif.h> #include <svdpi.h> #include <cstring> #include <string> #include <sys/stat.h> #include <fcntl.h> #include <sys/mman.h> #include <assert.h> #include <unistd.h> #include <stdlib.h> #include <stdio.h> #include <vector> #include <map> #include <iostream> #define SHT_PROGBITS 0x1 #define SHT_GROUP 0x11 // address and size std::vector<std::pair<reg_t, reg_t>> sections; std::map<std::string, uint64_t> symbols; // memory based address and content std::map<reg_t, std::vector<uint8_t>> mems; reg_t entry; int section_index = 0; void write (uint64_t address, uint64_t len, uint8_t* buf) { uint64_t datum; std::vector<uint8_t> mem; for (int i = 0; i < len; i++) { mem.push_back(buf[i]); } mems.insert(std::make_pair(address, mem)); } // Communicate the section address and len // Returns: // 0 if there are no more sections // 1 if there are more sections to load extern "C" char get_section (long long* address, long long* len) { if (section_index < sections.size()) { *address = sections[section_index].first; *len = sections[section_index].second; section_index++; return 1; } else return 0; } extern "C" void read_section (long long address, const svOpenArrayHandle buffer) { // get actual poitner void* buf = svGetArrayPtr(buffer); // check that the address points to a section assert(mems.count(address) > 0); // copy array int i = 0; for (auto &datum : mems.find(address)->second) { *((char *) buf + i) = datum; i++; } } extern "C" void read_elf(const char* filename) { int fd = open(filename, O_RDONLY); struct stat s; assert(fd != -1); if (fstat(fd, &s) < 0) abort(); size_t size = s.st_size; char* buf = (char*)mmap(NULL, size, PROT_READ, MAP_PRIVATE, fd, 0); assert(buf != MAP_FAILED); close(fd); assert(size >= sizeof(Elf64_Ehdr)); const Elf64_Ehdr* eh64 = (const Elf64_Ehdr*)buf; assert(IS_ELF32(*eh64) || IS_ELF64(*eh64)); std::vector<uint8_t> zeros; std::map<std::string, uint64_t> symbols; #define LOAD_ELF(ehdr_t, phdr_t, shdr_t, sym_t) do { \ ehdr_t* eh = (ehdr_t*)buf; \ phdr_t* ph = (phdr_t*)(buf + eh->e_phoff); \ entry = eh->e_entry; \ assert(size >= eh->e_phoff + eh->e_phnum*sizeof(*ph)); \ for (unsigned i = 0; i < eh->e_phnum; i++) { \ if(ph[i].p_type == PT_LOAD && ph[i].p_memsz) { \ if (ph[i].p_filesz) { \ assert(size >= ph[i].p_offset + ph[i].p_filesz); \ sections.push_back(std::make_pair(ph[i].p_paddr, ph[i].p_memsz)); \ write(ph[i].p_paddr, ph[i].p_filesz, (uint8_t*)buf + ph[i].p_offset); \ } \ zeros.resize(ph[i].p_memsz - ph[i].p_filesz); \ } \ } \ shdr_t* sh = (shdr_t*)(buf + eh->e_shoff); \ assert(size >= eh->e_shoff + eh->e_shnum*sizeof(*sh)); \ assert(eh->e_shstrndx < eh->e_shnum); \ assert(size >= sh[eh->e_shstrndx].sh_offset + sh[eh->e_shstrndx].sh_size); \ char *shstrtab = buf + sh[eh->e_shstrndx].sh_offset; \ unsigned strtabidx = 0, symtabidx = 0; \ for (unsigned i = 0; i < eh->e_shnum; i++) { \ unsigned max_len = sh[eh->e_shstrndx].sh_size - sh[i].sh_name; \ if ((sh[i].sh_type & SHT_GROUP) && strcmp(shstrtab + sh[i].sh_name, ".strtab") != 0 && strcmp(shstrtab + sh[i].sh_name, ".shstrtab") != 0) \ assert(strnlen(shstrtab + sh[i].sh_name, max_len) < max_len); \ if (sh[i].sh_type & SHT_PROGBITS) continue; \ if (strcmp(shstrtab + sh[i].sh_name, ".strtab") == 0) \ strtabidx = i; \ if (strcmp(shstrtab + sh[i].sh_name, ".symtab") == 0) \ symtabidx = i; \ } \ if (strtabidx && symtabidx) { \ char* strtab = buf + sh[strtabidx].sh_offset; \ sym_t* sym = (sym_t*)(buf + sh[symtabidx].sh_offset); \ for (unsigned i = 0; i < sh[symtabidx].sh_size/sizeof(sym_t); i++) { \ unsigned max_len = sh[strtabidx].sh_size - sym[i].st_name; \ assert(sym[i].st_name < sh[strtabidx]. sh_size); \ assert(strnlen(strtab + sym[i].st_name, max_len) < max_len); \ symbols[strtab + sym[i].st_name] = sym[i].st_value; \ } \ } \ } while(0) if (IS_ELF32(*eh64)) LOAD_ELF(Elf32_Ehdr, Elf32_Phdr, Elf32_Shdr, Elf32_Sym); else LOAD_ELF(Elf64_Ehdr, Elf64_Phdr, Elf64_Shdr, Elf64_Sym); munmap(buf, size); }
// Author: Florian Zaruba // Description: ModelSim Helper Functions #include <vpi_user.h> #include <vector> #include <string> #include <string.h> #include <stdio.h> // sanitize htif arguments std::vector<std::string> sanitize_args() { bool permissive_on = false; s_vpi_vlog_info info; if (!vpi_get_vlog_info(&info)) abort(); std::vector<std::string> htif_args; // sanitize arguments for (int i = 1; i < info.argc; i++) { if (strcmp(info.argv[i], "+permissive") == 0) { permissive_on = true; // printf("Found permissive %s\n", info.argv[i]); } // remove any two double pluses at the beginning (those are target arguments) if (info.argv[i][0] == '+' && info.argv[i][1] == '+' && strlen(info.argv[i]) > 3) { for (int j = 0; j < strlen(info.argv[i]) - 1; j++) { info.argv[i][j] = info.argv[i][j + 2]; } } if (!permissive_on) { htif_args.push_back(info.argv[i]); } if (strcmp(info.argv[i], "+permissive-off") == 0) { permissive_on = false; // printf("Found permissive-off %s\n", info.argv[i]); } } return htif_args; }
// Author: Florian Zaruba // Description: ModelSim Helper Functions #ifndef _MSIM_HELPER_H #define _MSIM_HELPER_H #include <vector> #include <string> // sanitize htif arguments std::vector<std::string> sanitize_args(); #endif
// See LICENSE.Berkeley for license details. #include <arpa/inet.h> #include <errno.h> #include <fcntl.h> #include <stdlib.h> #include <string.h> #include <unistd.h> #include <algorithm> #include <cassert> #include <cstdio> #include <cstdlib> #include "remote_bitbang.h" /////////// remote_bitbang_t remote_bitbang_t::remote_bitbang_t(uint16_t port) : socket_fd(0), client_fd(0), recv_start(0), recv_end(0), err(0) { socket_fd = socket(AF_INET, SOCK_STREAM, 0); if (socket_fd == -1) { fprintf(stderr, "remote_bitbang failed to make socket: %s (%d)\n", strerror(errno), errno); abort(); } fcntl(socket_fd, F_SETFL, O_NONBLOCK); int reuseaddr = 1; if (setsockopt(socket_fd, SOL_SOCKET, SO_REUSEADDR, &reuseaddr, sizeof(int)) == -1) { fprintf(stderr, "remote_bitbang failed setsockopt: %s (%d)\n", strerror(errno), errno); abort(); } struct sockaddr_in addr; memset(&addr, 0, sizeof(addr)); addr.sin_family = AF_INET; addr.sin_addr.s_addr = INADDR_ANY; addr.sin_port = htons(port); if (::bind(socket_fd, (struct sockaddr *) &addr, sizeof(addr)) == -1) { fprintf(stderr, "remote_bitbang failed to bind socket: %s (%d)\n", strerror(errno), errno); abort(); } if (listen(socket_fd, 1) == -1) { fprintf(stderr, "remote_bitbang failed to listen on socket: %s (%d)\n", strerror(errno), errno); abort(); } socklen_t addrlen = sizeof(addr); if (getsockname(socket_fd, (struct sockaddr *) &addr, &addrlen) == -1) { fprintf(stderr, "remote_bitbang getsockname failed: %s (%d)\n", strerror(errno), errno); abort(); } tck = 1; tms = 1; tdi = 1; trstn = 1; quit = 0; fprintf(stderr, "This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1.\n"); fprintf(stderr, "Listening on port %d\n", ntohs(addr.sin_port)); } void remote_bitbang_t::accept() { fprintf(stderr,"Attempting to accept client socket\n"); int again = 1; while (again != 0) { client_fd = ::accept(socket_fd, NULL, NULL); if (client_fd == -1) { if (errno == EAGAIN) { // No client waiting to connect right now. } else { fprintf(stderr, "failed to accept on socket: %s (%d)\n", strerror(errno), errno); again = 0; abort(); } } else { fcntl(client_fd, F_SETFL, O_NONBLOCK); fprintf(stderr, "Accepted successfully."); again = 0; } } } void remote_bitbang_t::tick( unsigned char * jtag_tck, unsigned char * jtag_tms, unsigned char * jtag_tdi, unsigned char * jtag_trstn, unsigned char jtag_tdo ) { if (client_fd > 0) { tdo = jtag_tdo; execute_command(); } else { this->accept(); } * jtag_tck = tck; * jtag_tms = tms; * jtag_tdi = tdi; * jtag_trstn = trstn; } void remote_bitbang_t::reset(){ //trstn = 0; } void remote_bitbang_t::set_pins(char _tck, char _tms, char _tdi){ tck = _tck; tms = _tms; tdi = _tdi; } void remote_bitbang_t::execute_command() { char command; int again = 1; while (again) { ssize_t num_read = read(client_fd, &command, sizeof(command)); if (num_read == -1) { if (errno == EAGAIN) { // We'll try again the next call. //fprintf(stderr, "Received no command. Will try again on the next call\n"); } else { fprintf(stderr, "remote_bitbang failed to read on socket: %s (%d)\n", strerror(errno), errno); again = 0; abort(); } } else if (num_read == 0) { fprintf(stderr, "No Command Received.\n"); again = 1; } else { again = 0; } } //fprintf(stderr, "Received a command %c\n", command); int dosend = 0; char tosend = '?'; switch (command) { case 'B': /* fprintf(stderr, "*BLINK*\n"); */ break; case 'b': /* fprintf(stderr, "_______\n"); */ break; case 'r': reset(); break; // This is wrong. 'r' has other bits that indicated TRST and SRST. case '0': set_pins(0, 0, 0); break; case '1': set_pins(0, 0, 1); break; case '2': set_pins(0, 1, 0); break; case '3': set_pins(0, 1, 1); break; case '4': set_pins(1, 0, 0); break; case '5': set_pins(1, 0, 1); break; case '6': set_pins(1, 1, 0); break; case '7': set_pins(1, 1, 1); break; case 'R': dosend = 1; tosend = tdo ? '1' : '0'; break; case 'Q': quit = 1; break; default: fprintf(stderr, "remote_bitbang got unsupported command '%c'\n", command); } if (dosend){ while (1) { ssize_t bytes = write(client_fd, &tosend, sizeof(tosend)); if (bytes == -1) { fprintf(stderr, "failed to write to socket: %s (%d)\n", strerror(errno), errno); abort(); } if (bytes > 0) { break; } } } if (quit) { // The remote disconnected. fprintf(stderr, "Remote end disconnected\n"); close(client_fd); client_fd = 0; } }
// See LICENSE.Berkeley for license details. #ifndef REMOTE_BITBANG_H #define REMOTE_BITBANG_H #include <stdint.h> #include <sys/types.h> class remote_bitbang_t { public: // Create a new server, listening for connections from localhost on the given // port. remote_bitbang_t(uint16_t port); // Do a bit of work. void tick(unsigned char * jtag_tck, unsigned char * jtag_tms, unsigned char * jtag_tdi, unsigned char * jtag_trstn, unsigned char jtag_tdo); unsigned char done() {return quit;} int exit_code() {return err;} private: int err; unsigned char tck; unsigned char tms; unsigned char tdi; unsigned char trstn; unsigned char tdo; unsigned char quit; int socket_fd; int client_fd; static const ssize_t buf_size = 64 * 1024; char recv_buf[buf_size]; ssize_t recv_start, recv_end; // Check for a client connecting, and accept if there is one. void accept(); // Execute any commands the client has for us. // But we only execute 1 because we need time for the // simulation to run. void execute_command(); // Reset. Currently does nothing. void reset(); void set_pins(char _tck, char _tms, char _tdi); }; #endif
// See LICENSE.SiFive for license details. #include "msim_helper.h" #include <fesvr/dtm.h> #include <vpi_user.h> #include <svdpi.h> #include <stdio.h> #include <string.h> #include <vector> dtm_t* dtm; extern "C" int debug_tick ( unsigned char* debug_req_valid, unsigned char debug_req_ready, int* debug_req_bits_addr, int* debug_req_bits_op, int* debug_req_bits_data, unsigned char debug_resp_valid, unsigned char* debug_resp_ready, int debug_resp_bits_resp, int debug_resp_bits_data ) { if (!dtm) { std::vector<std::string> htif_args = sanitize_args(); // convert vector to argc and argv int argc = htif_args.size() + 1; char * argv[argc]; argv[0] = (char *) "htif"; for (unsigned int i = 0; i < htif_args.size(); i++) { argv[i+1] = (char *) htif_args[i].c_str(); } dtm = new dtm_t(argc, argv); } dtm_t::resp resp_bits; resp_bits.resp = debug_resp_bits_resp; resp_bits.data = debug_resp_bits_data; dtm->tick ( debug_req_ready, debug_resp_valid, resp_bits ); *debug_resp_ready = dtm->resp_ready(); *debug_req_valid = dtm->req_valid(); *debug_req_bits_addr = dtm->req_bits().addr; *debug_req_bits_op = dtm->req_bits().op; *debug_req_bits_data = dtm->req_bits().data; return dtm->done() ? (dtm->exit_code() << 1 | 1) : 0; }
// See LICENSE.SiFive for license details. #include <cstdlib> #include "remote_bitbang.h" remote_bitbang_t* jtag; extern "C" int jtag_tick ( unsigned char * jtag_TCK, unsigned char * jtag_TMS, unsigned char * jtag_TDI, unsigned char * jtag_TRSTn, unsigned char jtag_TDO ) { if (!jtag) { // TODO: Pass in real port number jtag = new remote_bitbang_t(0); } jtag->tick(jtag_TCK, jtag_TMS, jtag_TDI, jtag_TRSTn, jtag_TDO); return jtag->done() ? (jtag->exit_code() << 1 | 1) : 0; }
// See LICENSE for license details. #include "sim_spike.h" #include "mmu.h" #include "dts.h" #include <map> #include <iostream> #include <sstream> #include <climits> #include <cstdlib> #include <cassert> #include <signal.h> #include <unistd.h> #include <sys/wait.h> #include <sys/types.h> #include <inttypes.h> sim_spike_t::sim_spike_t(const char* isa, size_t nprocs, std::vector<std::pair<reg_t, mem_t*>> mems, const std::vector<std::string>& args) : mems(mems), procs(std::max(nprocs, size_t(1))), current_step(0), current_proc(0), debug(false), log(true), histogram_enabled(false), dtb_enabled(true), remote_bitbang(NULL) { for (auto& x : mems) bus.add_device(x.first, x.second); debug_mmu = new mmu_t(this, NULL); for (size_t i = 0; i < procs.size(); i++) { procs[i] = new processor_t(isa, this, i, false); } clint.reset(new clint_t(procs)); // we need to bring the clint to a reproducible default value clint.get()->reset(); bus.add_device(CLINT_BASE, clint.get()); uart.reset(new uart_t()); bus.add_device(UART_BASE, uart.get()); make_bootrom(); set_procs_debug(true); } sim_spike_t::~sim_spike_t() { for (size_t i = 0; i < procs.size(); i++) delete procs[i]; delete debug_mmu; } commit_log_t sim_spike_t::tick(size_t n) { commit_log_t commit_log; reg_t pc = procs[0]->get_state()->pc; auto& reg = procs[0]->get_state()->log_reg_write; // execute instruction procs[0]->step(n); int priv = procs[0]->get_state()->last_inst_priv; int xlen = procs[0]->get_state()->last_inst_xlen; int flen = procs[0]->get_state()->last_inst_flen; commit_log.priv = priv; commit_log.pc = pc; commit_log.is_fp = reg.addr & 1; commit_log.rd = reg.addr >> 1; commit_log.data = reg.data.v[0]; commit_log.instr = procs[0]->get_state()->last_insn; commit_log.was_exception = procs[0]->get_state()->was_exception; return commit_log; } void sim_spike_t::clint_tick() { clint->increment(1); } void sim_spike_t::set_debug(bool value) { debug = value; } void sim_spike_t::set_log(bool value) { log = value; } void sim_spike_t::set_histogram(bool value) { histogram_enabled = value; for (size_t i = 0; i < procs.size(); i++) { procs[i]->set_histogram(histogram_enabled); } } void sim_spike_t::set_procs_debug(bool value) { for (size_t i=0; i< procs.size(); i++) procs[i]->set_debug(value); } bool sim_spike_t::mmio_load(reg_t addr, size_t len, uint8_t* bytes) { if (addr + len < addr) return false; return bus.load(addr, len, bytes); } bool sim_spike_t::mmio_store(reg_t addr, size_t len, const uint8_t* bytes) { if (addr + len < addr) return false; return bus.store(addr, len, bytes); } void sim_spike_t::make_bootrom() { start_pc = 0x80000000; #include "bootrom.h" std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec)); boot_rom.reset(new rom_device_t(rom)); bus.add_device(DEFAULT_RSTVEC, boot_rom.get()); } char* sim_spike_t::addr_to_mem(reg_t addr) { auto desc = bus.find_device(addr); if (auto mem = dynamic_cast<mem_t*>(desc.second)) if (addr - desc.first < mem->size()) return mem->contents() + (addr - desc.first); return NULL; }
// See LICENSE for license details. #ifndef _RISCV_SPIKE_H #define _RISCV_SPIKE_H #include "processor.h" #include "devices.h" #include "debug_module.h" #include "simif.h" #include <fesvr/htif.h> #include <fesvr/context.h> #include <vector> #include <string> #include <memory> #include <thread> class mmu_t; class remote_bitbang_t; typedef struct { char priv; uint64_t pc; char is_fp; char rd; uint64_t data; uint32_t instr; char was_exception; } commit_log_t; // this class encapsulates the processors and memory in a RISC-V machine. class sim_spike_t : public simif_t { public: sim_spike_t(const char* isa, size_t _nprocs, std::vector<std::pair<reg_t, mem_t*>> mems, const std::vector<std::string>& args); ~sim_spike_t(); int init_sim(); void producer_thread(); void clint_tick(); commit_log_t tick(size_t n); // step through simulation void set_debug(bool value); void set_log(bool value); void set_histogram(bool value); void set_procs_debug(bool value); void set_dtb_enabled(bool value) { this->dtb_enabled = value; } void set_remote_bitbang(remote_bitbang_t* remote_bitbang) { this->remote_bitbang = remote_bitbang; } const char* get_dts() { return dts.c_str(); } processor_t* get_core(size_t i) { return procs.at(i); } unsigned nprocs() const { return procs.size(); } private: std::vector<std::pair<reg_t, mem_t*>> mems; mmu_t* debug_mmu; // debug port into main memory std::vector<processor_t*> procs; reg_t start_pc; std::string dts; std::unique_ptr<rom_device_t> boot_rom; std::unique_ptr<clint_t> clint; std::unique_ptr<uart_t> uart; bus_t bus; std::thread t1; processor_t* get_core(const std::string& i); static const size_t INTERLEAVE = 5000; static const size_t INSNS_PER_RTC_TICK = 100; // 10 MHz clock for 1 BIPS core static const size_t CPU_HZ = 1000000000; // 1GHz CPU size_t current_step; size_t current_proc; bool debug; bool log; bool histogram_enabled; // provide a histogram of PCs bool dtb_enabled; remote_bitbang_t* remote_bitbang; // memory-mapped I/O routines char* addr_to_mem(reg_t addr); bool mmio_load(reg_t addr, size_t len, uint8_t* bytes); bool mmio_store(reg_t addr, size_t len, const uint8_t* bytes); void proc_reset(unsigned id) {}; void make_bootrom(); public: }; #endif
#include <fesvr/elf.h> #include <fesvr/memif.h> #include "sim_spike.h" #include "msim_helper.h" #include <vpi_user.h> #include "svdpi.h" #include <stdio.h> #include <stdlib.h> #include <vector> #include <string> #include <memory> #include <sys/mman.h> #include <sys/stat.h> #include <fcntl.h> #include <assert.h> #include <unistd.h> #include <map> #include <iostream> sim_spike_t* sim; std::vector<std::pair<reg_t, mem_t*>> mem; commit_log_t commit_log_val; #define SHT_PROGBITS 0x1 #define SHT_GROUP 0x11 void write_spike_mem (reg_t address, size_t len, uint8_t* buf) { memcpy(mem[0].second->contents() + (address & ~(1 << 31)), buf,len); } void read_elf(const char* filename) { int fd = open(filename, O_RDONLY); struct stat s; assert(fd != -1); if (fstat(fd, &s) < 0) abort(); size_t size = s.st_size; char* buf = (char*)mmap(NULL, size, PROT_READ, MAP_PRIVATE, fd, 0); assert(buf != MAP_FAILED); close(fd); assert(size >= sizeof(Elf64_Ehdr)); const Elf64_Ehdr* eh64 = (const Elf64_Ehdr*)buf; assert(IS_ELF32(*eh64) || IS_ELF64(*eh64)); std::vector<uint8_t> zeros; #define LOAD_ELF(ehdr_t, phdr_t, shdr_t, sym_t) do { \ ehdr_t* eh = (ehdr_t*)buf; \ phdr_t* ph = (phdr_t*)(buf + eh->e_phoff); \ assert(size >= eh->e_phoff + eh->e_phnum*sizeof(*ph)); \ for (unsigned i = 0; i < eh->e_phnum; i++) { \ if(ph[i].p_type == PT_LOAD && ph[i].p_memsz) { \ if (ph[i].p_filesz) { \ assert(size >= ph[i].p_offset + ph[i].p_filesz); \ write_spike_mem(ph[i].p_paddr, ph[i].p_filesz, (uint8_t*)buf + ph[i].p_offset); \ } \ zeros.resize(ph[i].p_memsz - ph[i].p_filesz); \ } \ } \ shdr_t* sh = (shdr_t*)(buf + eh->e_shoff); \ assert(size >= eh->e_shoff + eh->e_shnum*sizeof(*sh)); \ assert(eh->e_shstrndx < eh->e_shnum); \ assert(size >= sh[eh->e_shstrndx].sh_offset + sh[eh->e_shstrndx].sh_size); \ char *shstrtab = buf + sh[eh->e_shstrndx].sh_offset; \ unsigned strtabidx = 0, symtabidx = 0; \ for (unsigned i = 0; i < eh->e_shnum; i++) { \ unsigned max_len = sh[eh->e_shstrndx].sh_size - sh[i].sh_name; \ if ((sh[i].sh_type & SHT_GROUP) && strcmp(shstrtab + sh[i].sh_name, ".strtab") != 0 && strcmp(shstrtab + sh[i].sh_name, ".shstrtab") != 0) \ assert(strnlen(shstrtab + sh[i].sh_name, max_len) < max_len); \ if (sh[i].sh_type & SHT_PROGBITS) continue; \ if (strcmp(shstrtab + sh[i].sh_name, ".strtab") == 0) \ strtabidx = i; \ if (strcmp(shstrtab + sh[i].sh_name, ".symtab") == 0) \ symtabidx = i; \ } \ if (strtabidx && symtabidx) { \ char* strtab = buf + sh[strtabidx].sh_offset; \ sym_t* sym = (sym_t*)(buf + sh[symtabidx].sh_offset); \ for (unsigned i = 0; i < sh[symtabidx].sh_size/sizeof(sym_t); i++) { \ unsigned max_len = sh[strtabidx].sh_size - sym[i].st_name; \ assert(sym[i].st_name < sh[strtabidx]. sh_size); \ assert(strnlen(strtab + sym[i].st_name, max_len) < max_len); \ } \ } \ } while(0) if (IS_ELF32(*eh64)) LOAD_ELF(Elf32_Ehdr, Elf32_Phdr, Elf32_Shdr, Elf32_Sym); else LOAD_ELF(Elf64_Ehdr, Elf64_Phdr, Elf64_Shdr, Elf64_Sym); munmap(buf, size); } extern "C" void spike_create(const char* filename, uint64_t dram_base, unsigned int size) { mem = std::vector<std::pair<reg_t, mem_t*>>(1, std::make_pair(reg_t(dram_base), new mem_t(size))); // zero out memory memset(mem[0].second->contents(), 0, size_t(size)); read_elf(filename); if (!sim) { std::vector<std::string> htif_args = sanitize_args(); sim = new sim_spike_t("rv64imac", 1, mem, htif_args); } } // advance Spike and get the retired instruction extern "C" void spike_tick(commit_log_t* commit_log) { commit_log_val = sim->tick(1); commit_log->priv = commit_log_val.priv; commit_log->pc = commit_log_val.pc; commit_log->is_fp = commit_log_val.is_fp; commit_log->rd = commit_log_val.rd; commit_log->data = commit_log_val.data; commit_log->instr = commit_log_val.instr; commit_log->was_exception = commit_log_val.was_exception; } extern "C" void clint_tick() { sim->clint_tick(); }
#ifndef _ROCKET_VERILATOR_H #define _ROCKET_VERILATOR_H #include "verilated_vcd_c.h" #include <stdlib.h> #include <stdio.h> extern bool verbose; extern bool done_reset; class VerilatedVcdFILE : public VerilatedVcdFile { public: VerilatedVcdFILE(FILE* file) : file(file) {} ~VerilatedVcdFILE() {} bool open(const std::string& name) override { // file should already be open return file != NULL; } void close() override { // file should be closed elsewhere } ssize_t write(const char* bufp, ssize_t len) override { return fwrite(bufp, 1, len, file); } private: FILE* file; }; #endif
gitdir: ../../../.git/modules/corev_apu/tb/dromajo
*.o *.bootram *.mainram *.hex *.re_regs *.dtb *.d snap.* dromajo libdromajo_cosim.a *.swp tags
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# Dromajo - Esperanto Technology's RISC-V Reference Model Functional verification is key to have a strong RISC-V ecosystem. Esperanto is releasing Dromajo to help the RISC-V community. Dromajo is the Esperanto translation for an emu bird. It is a RISC-V RV64GC emulator designed for RTL co-simulation. This is the emulator used for cosimulation inside Esperanto, but it is designed with a simple API that can be leveraged to other RTL RISC-V cores. Dromajo enables executing application (such as benchmarks running on Linux) under fast software simulation, generating checkpoints after a given number of cycles, and resuming such checkpoints for HW/SW co-simulation. This has proven to be a very powerful way to capture bugs, especially in combination with randomized tests. Dromajo's semantic model is based on Fabrice Bellard's RISCVEMU (later renamed TinyEMU), but extensively verified, bug-fixed, and enhanced to take it to ISA 2.3/priv 1.11. ## Building ``` make -C src ``` The resulting artifacts are the `dromajo` simulator and the `libdromajo_cosim.a` library with associated `dromajo_cosim.h` header file. Check the [setup.md](run/setup.md) for instructions how to compile tests like booting Linux and baremetal for dromajo. ## Usage The co-simulation environment will link with the libraries and usage will depend on that, but the `src/dromajo.c` utility allows for standalone simulation of RISC-V ELF binaries. ``` cd src ./dromajo error: missing config file usage: ./dromajo [--load snapshot_name] [--save snapshot_name] [--maxinsns N] [--memory_size MB] config --load resumes a previously saved snapshot --save saves a snapshot upon exit --maxinsns terminates execution after a number of instructions --terminate-event name of the validate event to terminate execution --trace start trace dump after a number of instructions --memory_size sets the memory size in MiB (default 256 MiB) ./dromajo path/to/your/coremark.riscv ... ```
# dromajo and GitHub Dromajo was originally developed at Esperanto Tech, but the code has been open sourced at Chips Alliance. The dromajo team encourages contributions from other developers. This guide explains the git setup from some external teams Other groups may choose to adapt this technique for their own use. ## Github Configuration and Commands This section is for git first time users and to show the git configuration used. ### Configuration Suggested options for git first time users # Rebase no merge by default git config --global pull.rebase true # Set your name and email git config --global user.email "perico@lospalotes.com" git config --global user.name "Perico LosPalotes" git config --global pull.rebase true git config --global rebase.autoStash true ### Rebase vs No-Rebase Rebase creates cleaner logs, but sometimes it gets difficult to fix conflicts with rebase. For cases that you are struggling to merge a conflict, you could do this: # undo the failed rebase merge git rebase --abort # make sure that your code changes were committed git commit -a -m"Your commit message" git pull --no-rebase # Fix the conflict without rebase (easier) git commit -a -m"your merge message" git pull --no-rebase git push ### Typical git commands Clean the directory from any file not in git (it will remove all the files not committed) git clean -fdx Save and restore un-committed changes to allow a new git pull. stash is like a "push" and "pop" replays the changes in the current directory. This will happen automatically if you have the autoStash configuration option. git stash git pull git stash pop See the differences against the server (still not pushed). Everything may be committed, so git diff may be empty git diff @{u} ## Test/Developer (no commits) If you do not plan to do many changes, and just wants to try dromajo or be a dromajo user, the easiest way is to just clone the repo: git clone https://github.com/chipsalliance/dromajo.git From time to time, you should get the latest version to have the latest bug fixes/patches. Just a typical git pull should suffice: git pull ### Contributor Flow If you plan to develop/extend dromajo, you have two main options: fork or private clone. The fork approach requires you to have your repository public, if you have publications or work-in-progress that you do not want to share the best option is to have a private repo (dromajo-private). The simplest way to contribute to dromajo is to create a public repo or a public fork, and a pull request. Most git guides use the origin/master (in fork or private repo) to synchronize with upstream/master (upstream or chipsalliance main repo). This means that your local changes should NOT go to your origin/master. Instead, you should create a branch for your local work. This works like a charm if you do pull requests, and it is reasonable if you have a long development branch without intention to push upstream. Although it is possible to create a different setup, we recommend that you keep the origin/master clean to synchronize with upstream/origin. You should create a new branch for each feature that you may want to upstream (origin/pull_request_xxx), and a local development branch (dev) for all your team members. 1.a. To create a private repo: git clone --bare https://github.com/chipsalliance/dromajo.git dromajo-upstream cd dromajo-upstream.git git push --mirror git@github.com:XXX/dromajo-private.git cd .. rm -rf dromajo-upstream.git 1.b. To create a public fork repo: You could do the same steps as the private repo, or just fork ( https://github.com/chipsalliance/dromajo/fork ) the dromajo repo. 2. Create development branch (dev) git checkout -b dev 3. Create a branch from origin/master to create a pull request to upstream/master git checkout -b pull_request_xxx 4. Create a branch from dev for internal development if needed git checkout -b feature_xx_4dev dev 5. Synchronize origin/master from main upstream/master # Add remote upstream (if not added before) git remote -v # If remote -v did not list upstream. Add them git remote add upstream https://github.com/chipsalliance/dromajo.git git fetch upstream # Make sure that you are in origin/master git checkout master # Bring the changes from the remote upstream/master to local master/origin git merge upstream/master # Push to repo origin/master if everything was fine git push origin master # To see the difference with upstream (it should be empty) git diff @{upstream} 6. Synchronize the dev branch with the latest master sync git checkout dev git merge origin/master git push # same as "push origin dev" because dev is checkout 7. In case that you did not, push to the corresponding branch to the server git push origin dev git push origin pull_request_xxx git push origin feature_xx_4dev 8. Create new [pull][pull] request to upstream If you created a branch in a fork repository, you can go to your repository website. See the branch, and create a pull request to the upstream (chipsalliance master repo) directly. Alternatively, if you have a private repository, you can do this other flow to create a pull request. git clone https://github.com/chipsalliance/dromajo.git dromajo-upstream cd dromajo-upstream git remote add private https://github.com/yourname/private-repo.git git checkout -b pull_request_yourname git pull private master # make sure that there your changes are here git push origin pull_request_yourname Now create a [pull][pull] request through github chipsalliance site. [pull]: https://help.github.com/articles/creating-a-pull-request
# Example things on run on Dromajo ## Bare-metal riscv-tests (~ 2 min) Assumption: you have the `riscv64-unknown-elf-` (Newlib) toolchain. ``` git clone --recursive https://github.com/riscv/riscv-tests cd riscv-tests autoconf ./configure --prefix=${PWD}/../riscv-tests-root/ make make install cd .. ``` To run one of the benchmarks with trace enabled ``` ../src/dromajo --trace 0 riscv-tests-root/share/riscv-tests/isa/rv64ua-p-amoadd_d ``` ## Linux with buildroot ### Get a trivial buildroot (~ 23 min) ``` wget -nc https://github.com/buildroot/buildroot/archive/2019.08.1.tar.gz tar xzf 2019.08.1.tar.gz cp config-buildroot-2019.08.1 buildroot-2019.08.1/.config make -j16 -C buildroot-2019.08.1 ``` ### Get the Linux kernel up and running (~ 3 min) Assumption: you have the `riscv64-linux-gnu-` (GlibC) toolchain. ``` export CROSS_COMPILE=riscv64-linux-gnu- wget -nc https://github.com/torvalds/linux/archive/v5.7-rc4.tar.gz tar -xvf v5.7-rc4.tar.gz make -C linux-5.7-rc4 ARCH=riscv defconfig make -C linux-5.7-rc4 ARCH=riscv -j16 ``` ### OpenSBI (~ 1 min) ``` export CROSS_COMPILE=riscv64-linux-gnu- git clone https://github.com/riscv/opensbi.git cd opensbi git checkout 7be75f519f7705367030258c4410d9ff9ea24a6f -b temp make PLATFORM=generic cd .. ``` ### To boot Linux (login:root password:root) ``` cp buildroot-2019.08.1/output/images/rootfs.* . cp linux-5.7-rc4/arch/riscv/boot/Image . cp opensbi/build/platform/generic/firmware/fw_jump.bin . ../src/dromajo boot.cfg ``` ### To boot a quad-core RISC-V CPU ``` ../src/dromajo --ncpus 4 boot.cfg ``` ### Create and run checkpoints Dromajo creates checkpoints by dumping the memory state, and creating a bootram that includes a sequence of valid RISC-V instructions to recover the CPU to the same state as before the checkpoint was created. This information includes not only the architectural state, but CSRs, and PLIC/CLINT programmed registers. It does not include any state in a hardware devices. It allows to create Linux boot checkpoints. E.g: Run 1M instructions and create a checkpoint from a Linux+openSBI boot: ``` ../src/dromajo --save ck1 --maxinsn 2000000 ./boot.cfg OpenSBI v0.7-39-g7be75f5 ____ _____ ____ _____ / __ \ / ____| _ \_ _| | | | |_ __ ___ _ __ | (___ | |_) || | | | | | '_ \ / _ \ '_ \ \___ \| _ < | | | |__| | |_) | __/ | | |____) | |_) || |_ \____/| .__/ \___|_| |_|_____/|____/_____| | | |_| Platform Name : ucbbar,dromajo-bare Platform HART Count : 1 Boot HART ID : 0 Boot HART ISA : rv64imafdcsu Firmware Base : 0x80000000 Firmware Size : 76 KB Runtime SBI Version : 0.2 MIDELEG : 0x0000000000000222 MEDELEG : 0x000000000000b109 PMP0 : 0x0000000080000000-0x000000008001ffff (A) PMP1 : 0x0000000000000000-0x000001ffffffffff (A,R,W,X) Power off. plic: 0 0 timecmp=ffffffffffffffff NOTE: creating a new boot rom clint hartid=0 timecmp=-1 cycles (124999) ``` The previous example creates 3 files. ck1.re_regs is an ascii dump for debugging. The ck1.mainram is a memory dump of the main memory after 1M cycles. The ck1.bootram is the new bootram needed to recover the state. To continue booting Linux: ``` ../src/dromajo --load ck1 ./boot.cfg [ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000 [ 0.000000] Linux version 5.7.0-rc4 (anup@anup-ubuntu64) (gcc version 9.2.0 (GCC), GNU ld (GNU Binutils) 2.32) #1 SMP Fri May 8 10:04:14 IST 2020 [ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '') [ 0.000000] printk: bootconsole [sbi0] enabled [ 0.000000] Initial ramdisk at: 0x(____ptrval____) (4997120 bytes) [ 0.000000] Zone ranges: [ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000bfffffff] [ 0.000000] Normal empty [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000080200000-0x00000000bfffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000bfffffff] [ 0.000000] software IO TLB: mapped [mem 0xbad39000-0xbed39000] (64MB) [ 0.000000] SBI specification v0.2 detected [ 0.000000] SBI implementation ID=0x1 Version=0x7 [ 0.000000] SBI v0.2 TIME extension detected [ 0.000000] SBI v0.2 IPI extension detected [ 0.000000] SBI v0.2 RFENCE extension detected [ 0.000000] SBI v0.2 HSM extension detected [ 0.000000] elf_hwcap is 0x112d [ 0.000000] percpu: Embedded 17 pages/cpu s31976 r8192 d29464 u69632 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258055 [ 0.000000] Kernel command line: root=/dev/ram rw earlycon=sbi console=hvc0 [ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear) [ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear) [ 0.000000] Sorting __ex_table... [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off [ 0.000000] Memory: 942628K/1046528K available (6386K kernel code, 4285K rwdata, 4096K rodata, 235K init, 317K bss, 103900K reserved, 0K cma-reserved) [ 0.000000] Virtual kernel memory layout: [ 0.000000] fixmap : 0xffffffcefee00000 - 0xffffffceff000000 (2048 kB) [ 0.000000] pci io : 0xffffffceff000000 - 0xffffffcf00000000 ( 16 MB) [ 0.000000] vmemmap : 0xffffffcf00000000 - 0xffffffcfffffffff (4095 MB) [ 0.000000] vmalloc : 0xffffffd000000000 - 0xffffffdfffffffff (65535 MB) [ 0.000000] lowmem : 0xffffffe000000000 - 0xffffffe03fe00000 (1022 MB) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1 [ 0.000000] rcu: Hierarchical RCU implementation. [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1. [ 0.000000] rcu: RCU debug extended QS entry/exit. [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1 [ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0 [ 0.000000] plic: mapped 31 interrupts with 1 handlers for 2 contexts. [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0] [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x24e6a1710, max_idle_ns: 440795202120 ns [ 0.000024] sched_clock: 64 bits at 10MHz, resolution 100ns, wraps every 4398046511100ns [ 0.000752] Console: colour dummy device 80x25 [ 0.000995] printk: console [hvc0] enabled [ 0.000995] printk: console [hvc0] enabled [ 0.001400] printk: bootconsole [sbi0] disabled [ 0.001400] printk: bootconsole [sbi0] disabled [ 0.001878] Calibrating delay loop (skipped), value calculated using timer frequency.. 20.00 BogoMIPS (lpj=40000) [ 0.002403] pid_max: default: 32768 minimum: 301 [ 0.003226] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) [ 0.003630] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear) [ 0.008021] rcu: Hierarchical SRCU implementation. [ 0.009313] smp: Bringing up secondary CPUs ... [ 0.009557] smp: Brought up 1 node, 1 CPU [ 0.010551] devtmpfs: initialized [ 0.013004] random: get_random_u32 called from bucket_table_alloc.isra.0+0x4e/0x154 with crng_init=0 [ 0.013985] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns [ 0.014915] futex hash table entries: 256 (order: 2, 16384 bytes, linear) [ 0.016379] NET: Registered protocol family 16 [ 0.066786] vgaarb: loaded [ 0.067978] SCSI subsystem initialized [ 0.069291] usbcore: registered new interface driver usbfs [ 0.069711] usbcore: registered new interface driver hub [ 0.070082] usbcore: registered new device driver usb [ 0.073131] clocksource: Switched to clocksource riscv_clocksource [ 0.093678] NET: Registered protocol family 2 [ 0.095795] tcp_listen_portaddr_hash hash table entries: 512 (order: 2, 20480 bytes, linear) [ 0.096347] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear) [ 0.097372] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear) [ 0.099225] TCP: Hash tables configured (established 8192 bind 8192) [ 0.099781] UDP hash table entries: 512 (order: 3, 49152 bytes, linear) [ 0.100359] UDP-Lite hash table entries: 512 (order: 3, 49152 bytes, linear) [ 0.101320] NET: Registered protocol family 1 [ 0.102643] RPC: Registered named UNIX socket transport module. [ 0.102946] RPC: Registered udp transport module. [ 0.103193] RPC: Registered tcp transport module. [ 0.103442] RPC: Registered tcp NFSv4.1 backchannel transport module. [ 0.103772] PCI: CLS 0 bytes, default 64 [ 0.104442] Unpacking initramfs... [ 0.234261] Freeing initrd memory: 4880K [ 0.236114] workingset: timestamp_bits=62 max_order=18 bucket_order=0 [ 0.271749] NFS: Registering the id_resolver key type [ 0.272075] Key type id_resolver registered [ 0.272298] Key type id_legacy registered [ 0.272536] nfs4filelayout_init: NFSv4 File Layout Driver Registering... [ 0.273319] 9p: Installing v9fs 9p2000 file system support [ 0.274667] NET: Registered protocol family 38 [ 0.274973] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252) [ 0.275344] io scheduler mq-deadline registered [ 0.275584] io scheduler kyber registered update_mip: hartid=0 mask=0 value=0 [ 0.441363] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled [ 0.444490] sifive-serial 54000000.uart: IRQ index 0 not found [ 0.446348] [drm] radeon kernel modesetting enabled. [ 0.469590] loop: module loaded [ 0.472629] libphy: Fixed MDIO Bus: probed [ 0.475395] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k [ 0.475693] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. [ 0.476289] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver [ 0.476620] ehci-pci: EHCI PCI platform driver [ 0.476958] ehci-platform: EHCI generic platform driver [ 0.477417] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver [ 0.477752] ohci-pci: OHCI PCI platform driver [ 0.478089] ohci-platform: OHCI generic platform driver [ 0.479174] usbcore: registered new interface driver uas [ 0.479599] usbcore: registered new interface driver usb-storage [ 0.480257] mousedev: PS/2 mouse device common for all mice [ 0.482197] usbcore: registered new interface driver usbhid [ 0.482480] usbhid: USB HID core driver [ 0.485418] NET: Registered protocol family 10 [ 0.487962] Segment Routing with IPv6 [ 0.488378] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver [ 0.490490] NET: Registered protocol family 17 [ 0.491411] 9pnet: Installing 9P2000 support [ 0.491785] Key type dns_resolver registered [ 0.493290] sifive-serial 54000000.uart: IRQ index 0 not found [ 0.494004] sifive-serial 54000000.uart: IRQ index 0 not found [ 0.496251] Freeing unused kernel memory: 232K [ 0.501340] Run /init as init process Starting syslogd: OK Starting klogd: OK Running sysctl: OK Initializing random number generator... [ 0.743667] random: dd: uninitialized urandom read (512 bytes read) done. Starting network: OK Welcome to Dromajo Buildroot buildroot login: ```
{ "version":1, "machine":"riscv64", "memory_size":256, "bios":"sample.bin", "memory_base_addr":0x80000000, "missing_csrs": [0x323, 0x324, 0x325, 0x326, //mhpmevent csrs 0x327, 0x328, 0x329, 0x32a, 0x32b, 0x32c, 0x32d, 0x32e, 0x32f, 0x330, 0x331, 0x332, 0x333, 0x334, 0x335, 0x336, 0x337, 0x338, 0x339, 0x33a, 0x33b, 0x33c, 0x33d, 0x33e, 0x33f, 0x3a0, 0x3a1, 0x3a2, 0x3a3, //pmp csrs 0x3b0, 0x3b1, 0x3b2, 0x3b3, 0x3b4, 0x3b5, 0x3b6, 0x3b7, 0x3b8, 0x3b9, 0x3ba, 0x3bb, 0x3bc, 0x3bd, 0x3be, 0x3bf], "maxinsns": 100 "clint_base_addr": 0x02000000, "clint_size": 0xC0000, "plic_base_addr": 0x0C000000, "plic_size": 0x3FFFFFF, "uart_base_addr": 0x10000000, "uart_size": 0x1000 }
{ "version":1, "machine":"riscv64", "memory_size":1024, "bios":"fw_jump.bin", "kernel":"Image", "initrd":"rootfs.cpio", "cmdline": "root=/dev/ram rw earlycon=sbi console=hvc0", "memory_base_addr":0x80000000 }
# # Automatically generated file; DO NOT EDIT. # Buildroot 2019.08.1-g56b2596-dirty Configuration # BR2_HAVE_DOT_CONFIG=y BR2_HOST_GCC_AT_LEAST_4_5=y BR2_HOST_GCC_AT_LEAST_4_6=y BR2_HOST_GCC_AT_LEAST_4_7=y BR2_HOST_GCC_AT_LEAST_4_8=y BR2_HOST_GCC_AT_LEAST_4_9=y BR2_HOST_GCC_AT_LEAST_5=y BR2_HOST_GCC_AT_LEAST_6=y BR2_HOST_GCC_AT_LEAST_7=y BR2_HOST_GCC_AT_LEAST_8=y # # Target options # BR2_ARCH_IS_64=y BR2_ARCH_HAS_MMU_MANDATORY=y # BR2_arcle is not set # BR2_arceb is not set # BR2_arm is not set # BR2_armeb is not set # BR2_aarch64 is not set # BR2_aarch64_be is not set # BR2_csky is not set # BR2_i386 is not set # BR2_m68k is not set # BR2_microblazeel is not set # BR2_microblazebe is not set # BR2_mips is not set # BR2_mipsel is not set # BR2_mips64 is not set # BR2_mips64el is not set # BR2_nds32 is not set # BR2_nios2 is not set # BR2_or1k is not set # BR2_powerpc is not set # BR2_powerpc64 is not set # BR2_powerpc64le is not set BR2_riscv=y # BR2_sh is not set # BR2_sparc is not set # BR2_sparc64 is not set # BR2_x86_64 is not set # BR2_xtensa is not set BR2_ARCH_HAS_TOOLCHAIN_BUILDROOT=y BR2_ARCH_NEEDS_GCC_AT_LEAST_4_8=y BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9=y BR2_ARCH_NEEDS_GCC_AT_LEAST_5=y BR2_ARCH_NEEDS_GCC_AT_LEAST_6=y BR2_ARCH_NEEDS_GCC_AT_LEAST_7=y BR2_ARCH="riscv64" BR2_ENDIAN="LITTLE" BR2_GCC_TARGET_ABI="lp64d" BR2_BINFMT_SUPPORTS_SHARED=y BR2_READELF_ARCH_NAME="RISC-V" BR2_BINFMT_ELF=y BR2_RISCV_ISA_RVI=y BR2_RISCV_ISA_RVM=y BR2_RISCV_ISA_RVA=y BR2_RISCV_ISA_RVF=y BR2_RISCV_ISA_RVD=y BR2_riscv_g=y # BR2_riscv_custom is not set # BR2_RISCV_32 is not set BR2_RISCV_64=y # BR2_RISCV_ABI_LP64 is not set # BR2_RISCV_ABI_LP64F is not set BR2_RISCV_ABI_LP64D=y # # Build options # # # Commands # BR2_WGET="wget --passive-ftp -nd -t 3" BR2_SVN="svn --non-interactive" BR2_BZR="bzr" BR2_GIT="git" BR2_CVS="cvs" BR2_LOCALFILES="cp" BR2_SCP="scp" BR2_HG="hg" BR2_ZCAT="gzip -d -c" BR2_BZCAT="bzcat" BR2_XZCAT="xzcat" BR2_LZCAT="lzip -d -c" BR2_TAR_OPTIONS="" BR2_DEFCONFIG="$(CONFIG_DIR)/defconfig" BR2_DL_DIR="$(TOPDIR)/dl" BR2_HOST_DIR="$(BASE_DIR)/host" # # Mirrors and Download locations # BR2_PRIMARY_SITE="" BR2_BACKUP_SITE="http://sources.buildroot.net" BR2_KERNEL_MIRROR="https://cdn.kernel.org/pub" BR2_GNU_MIRROR="http://ftpmirror.gnu.org" BR2_LUAROCKS_MIRROR="http://rocks.moonscript.org" BR2_CPAN_MIRROR="http://cpan.metacpan.org" BR2_JLEVEL=0 # BR2_CCACHE is not set # BR2_ENABLE_DEBUG is not set BR2_STRIP_strip=y BR2_STRIP_EXCLUDE_FILES="" BR2_STRIP_EXCLUDE_DIRS="" # BR2_OPTIMIZE_0 is not set # BR2_OPTIMIZE_1 is not set # BR2_OPTIMIZE_2 is not set # BR2_OPTIMIZE_3 is not set # BR2_OPTIMIZE_G is not set BR2_OPTIMIZE_S=y # BR2_OPTIMIZE_FAST is not set # BR2_STATIC_LIBS is not set BR2_SHARED_LIBS=y # BR2_SHARED_STATIC_LIBS is not set BR2_PACKAGE_OVERRIDE_FILE="$(CONFIG_DIR)/local.mk" BR2_GLOBAL_PATCH_DIR="" # # Advanced # BR2_COMPILER_PARANOID_UNSAFE_PATH=y # BR2_FORCE_HOST_BUILD is not set # BR2_REPRODUCIBLE is not set # # Security Hardening Options # # BR2_PIC_PIE is not set BR2_SSP_NONE=y # BR2_SSP_REGULAR is not set # BR2_SSP_STRONG is not set # BR2_SSP_ALL is not set BR2_RELRO_NONE=y # BR2_RELRO_PARTIAL is not set # BR2_RELRO_FULL is not set BR2_FORTIFY_SOURCE_NONE=y # BR2_FORTIFY_SOURCE_1 is not set # BR2_FORTIFY_SOURCE_2 is not set # # Toolchain # BR2_TOOLCHAIN=y BR2_TOOLCHAIN_USES_GLIBC=y BR2_TOOLCHAIN_BUILDROOT=y # BR2_TOOLCHAIN_EXTERNAL is not set # # Toolchain Buildroot Options # BR2_TOOLCHAIN_BUILDROOT_VENDOR="buildroot" BR2_TOOLCHAIN_BUILDROOT_GLIBC=y # BR2_TOOLCHAIN_BUILDROOT_MUSL is not set BR2_TOOLCHAIN_BUILDROOT_LIBC="glibc" # # Kernel Header Options # # BR2_KERNEL_HEADERS_4_19 is not set # BR2_KERNEL_HEADERS_5_1 is not set BR2_KERNEL_HEADERS_5_2=y # BR2_KERNEL_HEADERS_VERSION is not set # BR2_KERNEL_HEADERS_CUSTOM_TARBALL is not set # BR2_KERNEL_HEADERS_CUSTOM_GIT is not set BR2_DEFAULT_KERNEL_HEADERS="5.2.18" BR2_PACKAGE_LINUX_HEADERS=y BR2_PACKAGE_GLIBC=y # # Binutils Options # BR2_PACKAGE_HOST_BINUTILS_SUPPORTS_CFI=y # BR2_BINUTILS_VERSION_2_30_X is not set BR2_BINUTILS_VERSION_2_31_X=y # BR2_BINUTILS_VERSION_2_32_X is not set BR2_BINUTILS_VERSION="2.31.1" BR2_BINUTILS_EXTRA_CONFIG_OPTIONS="" # # GCC Options # # BR2_GCC_VERSION_7_X is not set # BR2_GCC_VERSION_8_X is not set BR2_GCC_VERSION_9_X=y BR2_GCC_VERSION="9.1.0" BR2_EXTRA_GCC_CONFIG_OPTIONS="" # BR2_TOOLCHAIN_BUILDROOT_CXX is not set # BR2_TOOLCHAIN_BUILDROOT_FORTRAN is not set # BR2_GCC_ENABLE_LTO is not set # BR2_GCC_ENABLE_OPENMP is not set # BR2_GCC_ENABLE_GRAPHITE is not set # # Toolchain Generic Options # BR2_TOOLCHAIN_SUPPORTS_ALWAYS_LOCKFREE_ATOMIC_INTS=y BR2_TOOLCHAIN_SUPPORTS_VARIADIC_MI_THUNK=y BR2_TOOLCHAIN_HAS_NATIVE_RPC=y BR2_USE_WCHAR=y BR2_ENABLE_LOCALE=y BR2_TOOLCHAIN_HAS_THREADS=y BR2_TOOLCHAIN_HAS_THREADS_DEBUG=y BR2_TOOLCHAIN_HAS_THREADS_NPTL=y BR2_TOOLCHAIN_HAS_SSP=y BR2_TOOLCHAIN_HAS_UCONTEXT=y BR2_TOOLCHAIN_SUPPORTS_PIE=y # BR2_TOOLCHAIN_GLIBC_GCONV_LIBS_COPY is not set BR2_TOOLCHAIN_HAS_FULL_GETTEXT=y BR2_USE_MMU=y BR2_TARGET_OPTIMIZATION="" BR2_TARGET_LDFLAGS="" # BR2_ECLIPSE_REGISTER is not set BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_0=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_1=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_2=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_3=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_4=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_5=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_6=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_7=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_8=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_9=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_10=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_11=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_12=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_13=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_14=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_15=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_16=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_17=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_18=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_3_19=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_0=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_1=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_2=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_3=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_4=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_5=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_6=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_7=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_8=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_9=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_10=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_11=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_12=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_13=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_14=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_15=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_16=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_17=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_18=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_19=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_4_20=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_0=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_1=y BR2_TOOLCHAIN_HEADERS_AT_LEAST_5_2=y BR2_TOOLCHAIN_HEADERS_AT_LEAST="5.2" BR2_TOOLCHAIN_GCC_AT_LEAST_4_3=y BR2_TOOLCHAIN_GCC_AT_LEAST_4_4=y BR2_TOOLCHAIN_GCC_AT_LEAST_4_5=y BR2_TOOLCHAIN_GCC_AT_LEAST_4_6=y BR2_TOOLCHAIN_GCC_AT_LEAST_4_7=y BR2_TOOLCHAIN_GCC_AT_LEAST_4_8=y BR2_TOOLCHAIN_GCC_AT_LEAST_4_9=y BR2_TOOLCHAIN_GCC_AT_LEAST_5=y BR2_TOOLCHAIN_GCC_AT_LEAST_6=y BR2_TOOLCHAIN_GCC_AT_LEAST_7=y BR2_TOOLCHAIN_GCC_AT_LEAST_8=y BR2_TOOLCHAIN_GCC_AT_LEAST_9=y BR2_TOOLCHAIN_GCC_AT_LEAST="9" BR2_TOOLCHAIN_HAS_MNAN_OPTION=y BR2_TOOLCHAIN_HAS_SYNC_1=y BR2_TOOLCHAIN_HAS_SYNC_2=y BR2_TOOLCHAIN_HAS_SYNC_4=y BR2_TOOLCHAIN_HAS_SYNC_8=y BR2_TOOLCHAIN_HAS_LIBATOMIC=y BR2_TOOLCHAIN_HAS_ATOMIC=y # # System configuration # BR2_ROOTFS_SKELETON_DEFAULT=y # BR2_ROOTFS_SKELETON_CUSTOM is not set BR2_TARGET_GENERIC_HOSTNAME="buildroot" BR2_TARGET_GENERIC_ISSUE="Welcome to Dromajo Buildroot" BR2_TARGET_GENERIC_PASSWD_SHA256=y # BR2_TARGET_GENERIC_PASSWD_SHA512 is not set BR2_TARGET_GENERIC_PASSWD_METHOD="sha-256" BR2_INIT_BUSYBOX=y # BR2_INIT_SYSV is not set # BR2_INIT_OPENRC is not set # BR2_INIT_SYSTEMD is not set # BR2_INIT_NONE is not set # BR2_ROOTFS_DEVICE_CREATION_STATIC is not set BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_DEVTMPFS=y # BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_MDEV is not set # BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_EUDEV is not set BR2_ROOTFS_DEVICE_TABLE="system/device_table.txt" # BR2_ROOTFS_DEVICE_TABLE_SUPPORTS_EXTENDED_ATTRIBUTES is not set # BR2_ROOTFS_MERGED_USR is not set BR2_TARGET_ENABLE_ROOT_LOGIN=y BR2_TARGET_GENERIC_ROOT_PASSWD="root" BR2_SYSTEM_BIN_SH_BUSYBOX=y # # bash, dash, mksh, zsh need BR2_PACKAGE_BUSYBOX_SHOW_OTHERS # # BR2_SYSTEM_BIN_SH_NONE is not set BR2_TARGET_GENERIC_GETTY=y BR2_TARGET_GENERIC_GETTY_PORT="console" BR2_TARGET_GENERIC_GETTY_BAUDRATE_KEEP=y # BR2_TARGET_GENERIC_GETTY_BAUDRATE_9600 is not set # BR2_TARGET_GENERIC_GETTY_BAUDRATE_19200 is not set # BR2_TARGET_GENERIC_GETTY_BAUDRATE_38400 is not set # BR2_TARGET_GENERIC_GETTY_BAUDRATE_57600 is not set # BR2_TARGET_GENERIC_GETTY_BAUDRATE_115200 is not set BR2_TARGET_GENERIC_GETTY_BAUDRATE="0" BR2_TARGET_GENERIC_GETTY_TERM="vt100" BR2_TARGET_GENERIC_GETTY_OPTIONS="" BR2_TARGET_GENERIC_REMOUNT_ROOTFS_RW=y BR2_SYSTEM_DHCP="" BR2_SYSTEM_DEFAULT_PATH="/bin:/sbin:/usr/bin:/usr/sbin" BR2_ENABLE_LOCALE_PURGE=y BR2_ENABLE_LOCALE_WHITELIST="C en_US" BR2_GENERATE_LOCALE="" # BR2_SYSTEM_ENABLE_NLS is not set # BR2_TARGET_TZ_INFO is not set BR2_ROOTFS_USERS_TABLES="" BR2_ROOTFS_OVERLAY="" BR2_ROOTFS_POST_BUILD_SCRIPT="" BR2_ROOTFS_POST_FAKEROOT_SCRIPT="" BR2_ROOTFS_POST_IMAGE_SCRIPT="" # # Kernel # # BR2_LINUX_KERNEL is not set # # Target packages # BR2_PACKAGE_BUSYBOX=y BR2_PACKAGE_BUSYBOX_CONFIG="package/busybox/busybox.config" BR2_PACKAGE_BUSYBOX_CONFIG_FRAGMENT_FILES="" # BR2_PACKAGE_BUSYBOX_SHOW_OTHERS is not set # BR2_PACKAGE_BUSYBOX_SELINUX is not set # BR2_PACKAGE_BUSYBOX_INDIVIDUAL_BINARIES is not set # BR2_PACKAGE_BUSYBOX_WATCHDOG is not set BR2_PACKAGE_SKELETON=y BR2_PACKAGE_HAS_SKELETON=y BR2_PACKAGE_PROVIDES_SKELETON="skeleton-init-sysv" BR2_PACKAGE_SKELETON_INIT_COMMON=y BR2_PACKAGE_SKELETON_INIT_SYSV=y # # Audio and video applications # # BR2_PACKAGE_ALSA_UTILS is not set # BR2_PACKAGE_ATEST is not set # BR2_PACKAGE_AUMIX is not set # # bellagio needs a toolchain w/ C++, threads, dynamic library # # BR2_PACKAGE_BLUEZ_ALSA is not set # BR2_PACKAGE_DVBLAST is not set # BR2_PACKAGE_DVDAUTHOR is not set # # dvdrw-tools needs a toolchain w/ threads, C++, wchar # # # espeak needs a toolchain w/ C++, wchar, threads, dynamic library # # BR2_PACKAGE_FAAD2 is not set BR2_PACKAGE_FFMPEG_ARCH_SUPPORTS=y # BR2_PACKAGE_FFMPEG is not set # BR2_PACKAGE_FLAC is not set # BR2_PACKAGE_FLITE is not set # BR2_PACKAGE_GMRENDER_RESURRECT is not set # BR2_PACKAGE_GSTREAMER is not set # BR2_PACKAGE_GSTREAMER1 is not set # BR2_PACKAGE_JACK1 is not set # # jack2 needs a toolchain w/ threads, C++, dynamic library # BR2_PACKAGE_KODI_ARCH_SUPPORTS=y # # kodi needs python w/ .py modules, a uClibc or glibc toolchain w/ C++, threads, wchar, dynamic library, gcc >= 4.8, host gcc >= 4.6 # # # kodi needs an OpenGL EGL backend with OpenGL support # # BR2_PACKAGE_LAME is not set # BR2_PACKAGE_MADPLAY is not set # BR2_PACKAGE_MIMIC is not set # # miraclecast needs systemd and a glibc toolchain w/ threads and wchar # # # mjpegtools needs a toolchain w/ C++, threads # # # modplugtools needs a toolchain w/ C++ # # BR2_PACKAGE_MOTION is not set # # mpd needs a toolchain w/ C++, threads, wchar, gcc >= 6 # # BR2_PACKAGE_MPD_MPC is not set # BR2_PACKAGE_MPG123 is not set # BR2_PACKAGE_MPV is not set # BR2_PACKAGE_MULTICAT is not set # BR2_PACKAGE_MUSEPACK is not set # # ncmpc needs a toolchain w/ C++, wchar, threads, gcc >= 6 # # BR2_PACKAGE_OPUS_TOOLS is not set BR2_PACKAGE_PULSEAUDIO_HAS_ATOMIC=y # BR2_PACKAGE_PULSEAUDIO is not set # BR2_PACKAGE_SOX is not set # BR2_PACKAGE_SQUEEZELITE is not set # # tovid needs a toolchain w/ threads, C++, wchar, gcc >= 4.5 # # BR2_PACKAGE_TSTOOLS is not set # BR2_PACKAGE_TWOLAME is not set # BR2_PACKAGE_UDPXY is not set # # upmpdcli needs a toolchain w/ C++, NPTL, gcc >= 4.9 # # # v4l2grab needs a toolchain w/ threads, dynamic library, C++ and headers >= 3.0 # # # v4l2loopback needs a Linux kernel to be built # # # vlc needs a toolchain w/ C++, dynamic library, wchar, threads, gcc >= 4.9, headers >= 3.7 # # BR2_PACKAGE_VORBIS_TOOLS is not set # BR2_PACKAGE_WAVPACK is not set # BR2_PACKAGE_YAVTA is not set # BR2_PACKAGE_YMPD is not set # # Compressors and decompressors # # BR2_PACKAGE_BROTLI is not set # BR2_PACKAGE_BZIP2 is not set # BR2_PACKAGE_LZ4 is not set # # lzip needs a toolchain w/ C++ # # BR2_PACKAGE_LZOP is not set # # p7zip needs a toolchain w/ threads, wchar, C++ # # BR2_PACKAGE_PIGZ is not set # BR2_PACKAGE_PIXZ is not set # # unrar needs a toolchain w/ C++, wchar, threads # # BR2_PACKAGE_XZ is not set # BR2_PACKAGE_ZIP is not set # BR2_PACKAGE_ZSTD is not set # # Debugging, profiling and benchmark # # BR2_PACKAGE_BLKTRACE is not set # # bonnie++ needs a toolchain w/ C++ # # BR2_PACKAGE_CACHE_CALIBRATOR is not set # # clinfo needs an OpenCL provider # # # dacapo needs OpenJDK # # BR2_PACKAGE_DHRYSTONE is not set # BR2_PACKAGE_DIEHARDER is not set # BR2_PACKAGE_DMALLOC is not set # BR2_PACKAGE_DROPWATCH is not set # BR2_PACKAGE_DSTAT is not set # BR2_PACKAGE_DT is not set # # duma needs a toolchain w/ C++, threads, dynamic library # # BR2_PACKAGE_FIO is not set BR2_PACKAGE_GDB_ARCH_SUPPORTS=y # # gdb/gdbserver >= 8.x needs a toolchain w/ C++, gcc >= 4.8 # # BR2_PACKAGE_IOZONE is not set # # ktap needs a Linux kernel to be built # # BR2_PACKAGE_LATENCYTOP is not set # BR2_PACKAGE_LMBENCH is not set BR2_PACKAGE_LTP_TESTSUITE_ARCH_SUPPORTS=y # BR2_PACKAGE_LTP_TESTSUITE is not set # BR2_PACKAGE_LTTNG_BABELTRACE is not set # # lttng-modules needs a Linux kernel to be built # BR2_PACKAGE_MEMSTAT=y # BR2_PACKAGE_NETPERF is not set # BR2_PACKAGE_NMON is not set # BR2_PACKAGE_PAX_UTILS is not set # BR2_PACKAGE_PV is not set BR2_PACKAGE_RAMSMP=y # BR2_PACKAGE_RAMSPEED is not set # BR2_PACKAGE_RT_TESTS is not set # BR2_PACKAGE_SPIDEV_TEST is not set # BR2_PACKAGE_STRACE is not set # BR2_PACKAGE_STRESS is not set # BR2_PACKAGE_STRESS_NG is not set # BR2_PACKAGE_TINYMEMBENCH is not set # BR2_PACKAGE_TRACE_CMD is not set # BR2_PACKAGE_UCLIBC_NG_TEST is not set # BR2_PACKAGE_VMTOUCH is not set # BR2_PACKAGE_WHETSTONE is not set # # Development tools # # BR2_PACKAGE_BINUTILS is not set # BR2_PACKAGE_BSDIFF is not set # BR2_PACKAGE_CHECK is not set # # cppunit needs a toolchain w/ C++, dynamic library # # BR2_PACKAGE_CUNIT is not set # BR2_PACKAGE_CVS is not set # # cxxtest needs a toolchain w/ C++ support # # BR2_PACKAGE_FLEX is not set # BR2_PACKAGE_GETTEXT is not set BR2_PACKAGE_PROVIDES_HOST_GETTEXT="host-gettext-tiny" # BR2_PACKAGE_GIT is not set # # git-crypt needs a toolchain w/ C++, gcc >= 4.9 # # # gperf needs a toolchain w/ C++ # # BR2_PACKAGE_JO is not set # BR2_PACKAGE_JQ is not set # BR2_PACKAGE_LIBTOOL is not set # BR2_PACKAGE_MAKE is not set # BR2_PACKAGE_PKGCONF is not set # BR2_PACKAGE_SUBVERSION is not set # BR2_PACKAGE_TREE is not set # # Filesystem and flash utilities # # BR2_PACKAGE_ABOOTIMG is not set # # aufs-util needs a linux kernel and a toolchain w/ threads # # BR2_PACKAGE_AUTOFS is not set # BR2_PACKAGE_BTRFS_PROGS is not set # BR2_PACKAGE_CIFS_UTILS is not set # BR2_PACKAGE_CPIO is not set # BR2_PACKAGE_CRAMFS is not set # BR2_PACKAGE_CURLFTPFS is not set # BR2_PACKAGE_DAVFS2 is not set # BR2_PACKAGE_DOSFSTOOLS is not set # BR2_PACKAGE_E2FSPROGS is not set # BR2_PACKAGE_E2TOOLS is not set # BR2_PACKAGE_ECRYPTFS_UTILS is not set # BR2_PACKAGE_EXFAT is not set # BR2_PACKAGE_EXFAT_UTILS is not set # BR2_PACKAGE_F2FS_TOOLS is not set # BR2_PACKAGE_FLASHBENCH is not set # BR2_PACKAGE_FSCRYPTCTL is not set # BR2_PACKAGE_FWUP is not set # BR2_PACKAGE_GENEXT2FS is not set # BR2_PACKAGE_GENPART is not set # BR2_PACKAGE_GENROMFS is not set # BR2_PACKAGE_IMX_USB_LOADER is not set # BR2_PACKAGE_MMC_UTILS is not set # BR2_PACKAGE_MTD is not set # BR2_PACKAGE_MTOOLS is not set # BR2_PACKAGE_NFS_UTILS is not set # BR2_PACKAGE_NILFS_UTILS is not set # BR2_PACKAGE_NTFS_3G is not set # BR2_PACKAGE_SP_OOPS_EXTRACT is not set # BR2_PACKAGE_SQUASHFS is not set # BR2_PACKAGE_SSHFS is not set # BR2_PACKAGE_UDFTOOLS is not set # BR2_PACKAGE_UNIONFS is not set # BR2_PACKAGE_XFSPROGS is not set # # Fonts, cursors, icons, sounds and themes # # # Cursors # # BR2_PACKAGE_COMIX_CURSORS is not set # BR2_PACKAGE_OBSIDIAN_CURSORS is not set # # Fonts # # BR2_PACKAGE_BITSTREAM_VERA is not set # BR2_PACKAGE_CANTARELL is not set # BR2_PACKAGE_DEJAVU is not set # BR2_PACKAGE_FONT_AWESOME is not set # BR2_PACKAGE_GHOSTSCRIPT_FONTS is not set # BR2_PACKAGE_INCONSOLATA is not set # BR2_PACKAGE_LIBERATION is not set # # Icons # # BR2_PACKAGE_GOOGLE_MATERIAL_DESIGN_ICONS is not set # BR2_PACKAGE_HICOLOR_ICON_THEME is not set # # Sounds # # BR2_PACKAGE_SOUND_THEME_BOREALIS is not set # BR2_PACKAGE_SOUND_THEME_FREEDESKTOP is not set # # Themes # # # Games # # BR2_PACKAGE_ASCII_INVADERS is not set # BR2_PACKAGE_CHOCOLATE_DOOM is not set # # flare-engine needs a toolchain w/ C++, dynamic library # # # gnuchess needs a toolchain w/ C++, threads # # BR2_PACKAGE_LBREAKOUT2 is not set # BR2_PACKAGE_LTRIS is not set # BR2_PACKAGE_OPENTYRIAN is not set # BR2_PACKAGE_PRBOOM is not set # BR2_PACKAGE_SL is not set # # stella needs a toolchain w/ dynamic library, C++, threads, gcc >= 5 # # # Graphic libraries and applications (graphic/text) # # # Graphic applications # # # cog needs wpewebkit and a toolchain w/ threads # # BR2_PACKAGE_FSWEBCAM is not set # BR2_PACKAGE_GHOSTSCRIPT is not set # # glmark2 needs a toolchain w/ C++, gcc >= 4.9 # # BR2_PACKAGE_GNUPLOT is not set # BR2_PACKAGE_JHEAD is not set # # libva-utils needs a toolchain w/ C++, threads, dynamic library # BR2_PACKAGE_NETSURF_ARCH_SUPPORTS=y # BR2_PACKAGE_NETSURF is not set # BR2_PACKAGE_PNGQUANT is not set # BR2_PACKAGE_RRDTOOL is not set # # stellarium needs Qt5 and an OpenGL provider # # # tesseract-ocr needs a toolchain w/ threads, C++, gcc >= 4.8, dynamic library, wchar # # # Graphic libraries # # # cegui06 needs a toolchain w/ C++, threads, dynamic library # # # directfb needs a glibc or uClibc toolchain w/ C++, NPTL, gcc >= 4.5, dynamic library # # BR2_PACKAGE_FB_TEST_APP is not set # BR2_PACKAGE_FBDUMP is not set # BR2_PACKAGE_FBGRAB is not set # # fbterm needs a toolchain w/ C++, wchar, locale # # BR2_PACKAGE_FBV is not set # # freerdp needs a toolchain w/ wchar, dynamic library, threads, C++ # # BR2_PACKAGE_IMAGEMAGICK is not set # # linux-fusion needs a Linux kernel to be built # # # mesa3d needs a toolchain w/ C++, NPTL, dynamic library # # # ocrad needs a toolchain w/ C++ # # BR2_PACKAGE_PSPLASH is not set # BR2_PACKAGE_SDL is not set # BR2_PACKAGE_SDL2 is not set # # Other GUIs # # # Qt5 needs a toolchain w/ wchar, NPTL, C++, dynamic library # # # tekui needs a Lua interpreter and a toolchain w/ threads, dynamic library # # # weston needs udev and a toolchain w/ locale, threads, dynamic library, headers >= 3.0 # # BR2_PACKAGE_XORG7 is not set # # vte needs a toolchain w/ wchar, threads, C++, gcc >= 4.8, host gcc >= 4.8 # # # vte needs an OpenGL or an OpenGL-EGL/wayland backend # # BR2_PACKAGE_XKEYBOARD_CONFIG is not set # # Hardware handling # # # Firmware # # BR2_PACKAGE_ARMBIAN_FIRMWARE is not set # BR2_PACKAGE_B43_FIRMWARE is not set # BR2_PACKAGE_LINUX_FIRMWARE is not set # BR2_PACKAGE_MURATA_CYW_FW is not set # BR2_PACKAGE_UX500_FIRMWARE is not set # BR2_PACKAGE_WILC1000_FIRMWARE is not set # BR2_PACKAGE_WILINK_BT_FIRMWARE is not set # BR2_PACKAGE_ZD1211_FIRMWARE is not set # BR2_PACKAGE_18XX_TI_UTILS is not set # BR2_PACKAGE_ACPICA is not set # BR2_PACKAGE_ACPID is not set # # acpitool needs a toolchain w/ threads, C++, dynamic library # # BR2_PACKAGE_AER_INJECT is not set # BR2_PACKAGE_AVRDUDE is not set # # bcache-tools needs udev /dev management # # # brickd needs udev /dev management, a toolchain w/ threads, wchar # # BR2_PACKAGE_BRLTTY is not set # # cc-tool needs a toolchain w/ C++, threads, wchar # # BR2_PACKAGE_CDRKIT is not set # BR2_PACKAGE_CRYPTSETUP is not set # BR2_PACKAGE_CWIID is not set # # dahdi-linux needs a Linux kernel to be built # # # dahdi-tools needs a toolchain w/ threads and a Linux kernel to be built # # BR2_PACKAGE_DBUS is not set # BR2_PACKAGE_DFU_UTIL is not set # BR2_PACKAGE_DMRAID is not set # # dt-utils needs udev /dev management # # BR2_PACKAGE_DTV_SCAN_TABLES is not set # BR2_PACKAGE_DUMP1090 is not set # BR2_PACKAGE_DVB_APPS is not set # BR2_PACKAGE_DVBSNOOP is not set # BR2_PACKAGE_EDID_DECODE is not set # # eudev needs eudev /dev management # # BR2_PACKAGE_EVEMU is not set # BR2_PACKAGE_EVTEST is not set # BR2_PACKAGE_FAN_CTRL is not set # BR2_PACKAGE_FCONFIG is not set # BR2_PACKAGE_FIS is not set BR2_PACKAGE_FLASHROM_ARCH_SUPPORTS=y # BR2_PACKAGE_FLASHROM is not set # BR2_PACKAGE_FMTOOLS is not set # BR2_PACKAGE_FXLOAD is not set # BR2_PACKAGE_GADGETFS_TEST is not set # BR2_PACKAGE_GPM is not set # BR2_PACKAGE_GPSD is not set # # gptfdisk needs a toolchain w/ C++ # # BR2_PACKAGE_GVFS is not set # BR2_PACKAGE_HWDATA is not set # BR2_PACKAGE_HWLOC is not set # BR2_PACKAGE_INPUT_EVENT_DAEMON is not set # BR2_PACKAGE_IOSTAT is not set # BR2_PACKAGE_IPMITOOL is not set # BR2_PACKAGE_IRDA_UTILS is not set # BR2_PACKAGE_KBD is not set # BR2_PACKAGE_LCDPROC is not set # BR2_PACKAGE_LIBUBOOTENV is not set # BR2_PACKAGE_LIBUIO is not set # # linux-backports needs a Linux kernel to be built # # BR2_PACKAGE_LINUXCONSOLETOOLS is not set # # lirc-tools needs a toolchain w/ threads, dynamic library, C++ # # BR2_PACKAGE_LM_SENSORS is not set # # lshw needs a toolchain w/ C++, wchar # # BR2_PACKAGE_LSSCSI is not set # BR2_PACKAGE_LSUIO is not set # BR2_PACKAGE_LUKSMETA is not set # BR2_PACKAGE_LVM2 is not set # BR2_PACKAGE_MDADM is not set # BR2_PACKAGE_MEMTESTER is not set # BR2_PACKAGE_MEMTOOL is not set # BR2_PACKAGE_MINICOM is not set # BR2_PACKAGE_NANOCOM is not set # BR2_PACKAGE_NEARD is not set # BR2_PACKAGE_NVME is not set # BR2_PACKAGE_OFONO is not set # BR2_PACKAGE_OPEN2300 is not set # BR2_PACKAGE_OPENIPMI is not set # BR2_PACKAGE_OPENOCD is not set # BR2_PACKAGE_PARTED is not set # BR2_PACKAGE_PCIUTILS is not set # BR2_PACKAGE_PDBG is not set # BR2_PACKAGE_PICOCOM is not set # # powertop needs a toolchain w/ C++, threads, wchar # # BR2_PACKAGE_PPS_TOOLS is not set # BR2_PACKAGE_READ_EDID is not set # BR2_PACKAGE_RNG_TOOLS is not set # BR2_PACKAGE_RS485CONF is not set # BR2_PACKAGE_RTC_TOOLS is not set # # rtl8188eu needs a Linux kernel to be built # # # rtl8189fs needs a Linux kernel to be built # # # rtl8723bs needs a Linux kernel to be built # # # rtl8723bu needs a Linux kernel to be built # # # rtl8821au needs a Linux kernel to be built # # BR2_PACKAGE_SANE_BACKENDS is not set # BR2_PACKAGE_SDPARM is not set # BR2_PACKAGE_SETSERIAL is not set # BR2_PACKAGE_SG3_UTILS is not set # BR2_PACKAGE_SIGROK_CLI is not set # BR2_PACKAGE_SISPMCTL is not set # # smartmontools needs a toolchain w/ C++ # # BR2_PACKAGE_SMSTOOLS3 is not set # BR2_PACKAGE_SPI_TOOLS is not set # BR2_PACKAGE_SREDIRD is not set # BR2_PACKAGE_STATSERIAL is not set # BR2_PACKAGE_STM32FLASH is not set # BR2_PACKAGE_SYSSTAT is not set # # targetcli-fb depends on Python # # # ti-sgx-um needs the ti-sgx-km driver # # BR2_PACKAGE_TI_UIM is not set # BR2_PACKAGE_TI_UTILS is not set # BR2_PACKAGE_TRIGGERHAPPY is not set # BR2_PACKAGE_UBOOT_TOOLS is not set # BR2_PACKAGE_UBUS is not set # # uccp420wlan needs a Linux kernel >= 4.2 to be built # # # udisks needs udev /dev management # # BR2_PACKAGE_UHUBCTL is not set # # upower needs udev /dev management # # BR2_PACKAGE_USB_MODESWITCH is not set # BR2_PACKAGE_USB_MODESWITCH_DATA is not set # # usbmount requires udev to be enabled # # # usbutils needs udev /dev management and toolchain w/ threads # # BR2_PACKAGE_W_SCAN is not set # BR2_PACKAGE_WIPE is not set # BR2_PACKAGE_XORRISO is not set # # xr819-xradio driver needs a Linux kernel to be built # # # Interpreter languages and scripting # # BR2_PACKAGE_4TH is not set # BR2_PACKAGE_ENSCRIPT is not set BR2_PACKAGE_HOST_ERLANG_ARCH_SUPPORTS=y # BR2_PACKAGE_EXECLINE is not set # BR2_PACKAGE_FICL is not set # BR2_PACKAGE_HASERL is not set # BR2_PACKAGE_JIMTCL is not set # BR2_PACKAGE_LUA is not set BR2_PACKAGE_PROVIDES_HOST_LUAINTERPRETER="host-lua" # BR2_PACKAGE_MICROPYTHON is not set BR2_PACKAGE_HOST_MONO_ARCH_SUPPORTS=y BR2_PACKAGE_HOST_OPENJDK_BIN_ARCH_SUPPORTS=y # BR2_PACKAGE_PERL is not set # BR2_PACKAGE_PHP is not set # BR2_PACKAGE_PYTHON is not set # BR2_PACKAGE_PYTHON3 is not set # BR2_PACKAGE_RUBY is not set # BR2_PACKAGE_TCL is not set # # Libraries # # # Audio/Sound # # BR2_PACKAGE_ALSA_LIB is not set # BR2_PACKAGE_AUBIO is not set # # audiofile needs a toolchain w/ C++ # # BR2_PACKAGE_BCG729 is not set # BR2_PACKAGE_CELT051 is not set # BR2_PACKAGE_LIBAO is not set # # asplib needs a toolchain w/ C++ # # BR2_PACKAGE_LIBBROADVOICE is not set # BR2_PACKAGE_LIBCDAUDIO is not set # BR2_PACKAGE_LIBCDDB is not set # BR2_PACKAGE_LIBCDIO is not set # BR2_PACKAGE_LIBCDIO_PARANOIA is not set # BR2_PACKAGE_LIBCODEC2 is not set # BR2_PACKAGE_LIBCUE is not set # BR2_PACKAGE_LIBCUEFILE is not set # BR2_PACKAGE_LIBEBUR128 is not set # BR2_PACKAGE_LIBG7221 is not set # BR2_PACKAGE_LIBGSM is not set # BR2_PACKAGE_LIBID3TAG is not set # BR2_PACKAGE_LIBILBC is not set # BR2_PACKAGE_LIBLO is not set # BR2_PACKAGE_LIBMAD is not set # # libmodplug needs a toolchain w/ C++ # # BR2_PACKAGE_LIBMPD is not set # BR2_PACKAGE_LIBMPDCLIENT is not set # BR2_PACKAGE_LIBREPLAYGAIN is not set # BR2_PACKAGE_LIBSAMPLERATE is not set # # libsidplay2 needs a toolchain w/ C++ # # BR2_PACKAGE_LIBSILK is not set # BR2_PACKAGE_LIBSNDFILE is not set # # libsoundtouch needs a toolchain w/ C++ # # BR2_PACKAGE_LIBSOXR is not set # BR2_PACKAGE_LIBVORBIS is not set # # mp4v2 needs a toolchain w/ C++ # BR2_PACKAGE_OPENAL_ARCH_SUPPORTS=y # # openal needs a toolchain w/ NPTL, C++ # # # opencore-amr needs a toolchain w/ C++ # # BR2_PACKAGE_OPUS is not set # BR2_PACKAGE_OPUSFILE is not set # BR2_PACKAGE_PORTAUDIO is not set # BR2_PACKAGE_SBC is not set # BR2_PACKAGE_SPANDSP is not set # BR2_PACKAGE_SPEEX is not set # BR2_PACKAGE_SPEEXDSP is not set # # taglib needs a toolchain w/ C++, wchar # # BR2_PACKAGE_TINYALSA is not set # BR2_PACKAGE_TREMOR is not set # BR2_PACKAGE_VO_AACENC is not set # # Compression and decompression # # BR2_PACKAGE_LIBARCHIVE is not set # # libsquish needs a toolchain w/ C++ # # BR2_PACKAGE_LIBZIP is not set # BR2_PACKAGE_LZO is not set # BR2_PACKAGE_MINIZIP is not set # # snappy needs a toolchain w/ C++ # # BR2_PACKAGE_SZIP is not set BR2_PACKAGE_ZLIB=y BR2_PACKAGE_LIBZLIB=y BR2_PACKAGE_HAS_ZLIB=y BR2_PACKAGE_PROVIDES_ZLIB="libzlib" BR2_PACKAGE_PROVIDES_HOST_ZLIB="host-libzlib" # BR2_PACKAGE_ZZIPLIB is not set # # Crypto # # BR2_PACKAGE_BEECRYPT is not set # BR2_PACKAGE_CA_CERTIFICATES is not set # # cryptodev needs a Linux kernel to be built # # BR2_PACKAGE_GCR is not set # BR2_PACKAGE_GNUTLS is not set # BR2_PACKAGE_LIBASSUAN is not set # BR2_PACKAGE_LIBGCRYPT is not set BR2_PACKAGE_LIBGPG_ERROR_ARCH_SUPPORTS=y # BR2_PACKAGE_LIBGPG_ERROR is not set BR2_PACKAGE_LIBGPG_ERROR_SYSCFG="riscv64-unknown-linux-gnu" # BR2_PACKAGE_LIBGPGME is not set # BR2_PACKAGE_LIBKCAPI is not set # BR2_PACKAGE_LIBKSBA is not set # BR2_PACKAGE_LIBMCRYPT is not set # BR2_PACKAGE_LIBMHASH is not set # BR2_PACKAGE_LIBNSS is not set # BR2_PACKAGE_LIBP11 is not set # BR2_PACKAGE_LIBSCRYPT is not set # BR2_PACKAGE_LIBSECRET is not set # BR2_PACKAGE_LIBSHA1 is not set # BR2_PACKAGE_LIBSODIUM is not set # BR2_PACKAGE_LIBSSH is not set # BR2_PACKAGE_LIBSSH2 is not set # BR2_PACKAGE_LIBTOMCRYPT is not set # BR2_PACKAGE_LIBUECC is not set # BR2_PACKAGE_MBEDTLS is not set # BR2_PACKAGE_NETTLE is not set # BR2_PACKAGE_OPENSSL is not set BR2_PACKAGE_PROVIDES_HOST_OPENSSL="host-libopenssl" # BR2_PACKAGE_RHASH is not set # BR2_PACKAGE_TINYDTLS is not set # BR2_PACKAGE_TPM2_TSS is not set # BR2_PACKAGE_TROUSERS is not set # BR2_PACKAGE_USTREAM_SSL is not set # BR2_PACKAGE_WOLFSSL is not set # # Database # # BR2_PACKAGE_BERKELEYDB is not set # BR2_PACKAGE_GDBM is not set # BR2_PACKAGE_HIREDIS is not set # # kompexsqlite needs a toolchain w/ C++, wchar, threads, dynamic library # # # leveldb needs a toolchain w/ C++, threads # # BR2_PACKAGE_LIBGIT2 is not set # # mysql needs a toolchain w/ C++, threads # # BR2_PACKAGE_POSTGRESQL is not set # BR2_PACKAGE_REDIS is not set # BR2_PACKAGE_SQLCIPHER is not set # BR2_PACKAGE_SQLITE is not set # BR2_PACKAGE_UNIXODBC is not set # # Filesystem # # BR2_PACKAGE_GAMIN is not set # BR2_PACKAGE_LIBCONFIG is not set # BR2_PACKAGE_LIBCONFUSE is not set # BR2_PACKAGE_LIBFUSE is not set # BR2_PACKAGE_LIBLOCKFILE is not set # BR2_PACKAGE_LIBNFS is not set # BR2_PACKAGE_LIBSYSFS is not set # BR2_PACKAGE_LOCKDEV is not set # # physfs needs a toolchain w/ C++, threads # # # Graphics # # # assimp needs a toolchain w/ C++, wchar # # # at-spi2-atk depends on X.org # # # at-spi2-core depends on X.org # # BR2_PACKAGE_ATK is not set # # atkmm needs a toolchain w/ C++, wchar, threads, gcc >= 4.9 # # # bullet needs a toolchain w/ C++ # # BR2_PACKAGE_CAIRO is not set # # cairomm needs a toolchain w/ C++, wchar, threads, gcc >= 4.8 # # # chipmunk needs an OpenGL backend # # # exempi needs a toolchain w/ C++, dynamic library, threads # # # exiv2 needs a uClibc or glibc toolchain w/ C++, wchar, dynamic library, threads # # BR2_PACKAGE_FONTCONFIG is not set # BR2_PACKAGE_FREETYPE is not set # BR2_PACKAGE_GD is not set # BR2_PACKAGE_GDK_PIXBUF is not set # BR2_PACKAGE_GIFLIB is not set # # granite needs libgtk3 and a toolchain w/ wchar, threads # # # graphite2 needs a toolchain w/ C++, dynamic library # # # gtkmm3 needs libgtk3 and a toolchain w/ C++, wchar, threads, gcc >= 4.9, host gcc >= 4.8 # # # harfbuzz needs a toolchain w/ C++, gcc => 4.8 # # BR2_PACKAGE_IJS is not set # BR2_PACKAGE_IMLIB2 is not set # # irrlicht needs a toolchain w/ C++ # # BR2_PACKAGE_JASPER is not set # BR2_PACKAGE_JPEG is not set # # kms++ needs a toolchain w/ threads, C++, gcc >= 4.8, headers >= 3.8 # # BR2_PACKAGE_LCMS2 is not set # # lensfun needs a toolchain w/ C++, threads, wchar # # BR2_PACKAGE_LEPTONICA is not set # BR2_PACKAGE_LIBART is not set # BR2_PACKAGE_LIBDMTX is not set # BR2_PACKAGE_LIBDRM is not set # # libepoxy needs an OpenGL and/or OpenGL EGL backend # # BR2_PACKAGE_LIBEXIF is not set # # libfm needs X.org and a toolchain w/ wchar, threads, C++, gcc >= 4.8 # # BR2_PACKAGE_LIBFM_EXTRA is not set # # libfreeglut depends on X.org and needs an OpenGL backend # # # libfreeimage needs a toolchain w/ C++, dynamic library, wchar # # BR2_PACKAGE_LIBGEOTIFF is not set # # libglew depends on X.org and needs an OpenGL backend # # # libglfw depends on X.org and needs an OpenGL backend # # # libglu needs an OpenGL backend # # BR2_PACKAGE_LIBGTA is not set # # libgtk3 needs a toolchain w/ wchar, threads, C++, gcc >= 4.8, host gcc >= 4.8 # # # libgtk3 needs an OpenGL or an OpenGL-EGL/wayland backend # # BR2_PACKAGE_LIBMEDIAART is not set # BR2_PACKAGE_LIBMNG is not set # BR2_PACKAGE_LIBPNG is not set # BR2_PACKAGE_LIBQRENCODE is not set # # libraw needs a toolchain w/ C++ # # # librsvg needs a toolchain w/ wchar, threads, C++, gcc >= 4.8 # # # libsoil needs an OpenGL backend and a toolchain w/ dynamic library # # BR2_PACKAGE_LIBSVG is not set # BR2_PACKAGE_LIBSVG_CAIRO is not set # BR2_PACKAGE_LIBSVGTINY is not set # BR2_PACKAGE_LIBVA is not set # # libvips needs a toolchain w/ wchar, threads, C++ # # # libwpe needs a toolchain w/ C++, dynamic library and an OpenEGL-capable backend # # BR2_PACKAGE_MENU_CACHE is not set # # opencv needs a toolchain w/ C++, NPTL, wchar # # # opencv3 needs a toolchain w/ C++, NPTL, wchar, dynamic library # # BR2_PACKAGE_OPENJPEG is not set # # pango needs a toolchain w/ wchar, threads, C++, gcc >= 4.8 # # # pangomm needs a toolchain w/ C++, wchar, threads, gcc >= 4.9 # # BR2_PACKAGE_PIXMAN is not set # # poppler needs a toolchain w/ wchar, C++, threads, dynamic library, gcc >= 5 # # BR2_PACKAGE_TIFF is not set # BR2_PACKAGE_WAYLAND is not set # BR2_PACKAGE_WEBP is not set # # woff2 needs a toolchain w/ C++ # # # wpebackend-fdo needs a toolchain w/ C++, wchar, threads, dynamic library and an OpenEGL-capable Wayland backend # # # zbar needs a toolchain w/ threads, C++ and headers >= 3.0 # # # zxing-cpp needs a toolchain w/ C++, dynamic library # # # Hardware handling # # BR2_PACKAGE_ACSCCID is not set # BR2_PACKAGE_C_PERIPHERY is not set # BR2_PACKAGE_CCID is not set # BR2_PACKAGE_DTC is not set # BR2_PACKAGE_HACKRF is not set # # hidapi needs udev /dev management and a toolchain w/ NPTL threads # # # lcdapi needs a toolchain w/ C++, threads # # # let-me-create needs a toolchain w/ C++, threads, dynamic library # # BR2_PACKAGE_LIBAIO is not set # # libatasmart requires udev to be enabled # # # libcec needs a toolchain w/ C++, wchar, threads, dynamic library, gcc >= 4.7 # # BR2_PACKAGE_LIBFREEFARE is not set # BR2_PACKAGE_LIBFTDI is not set # BR2_PACKAGE_LIBFTDI1 is not set # BR2_PACKAGE_LIBGPHOTO2 is not set # BR2_PACKAGE_LIBGPIOD is not set # # libgudev needs udev /dev handling and a toolchain w/ wchar, threads # # BR2_PACKAGE_LIBHID is not set # BR2_PACKAGE_LIBIIO is not set # # libinput needs udev /dev management and a toolchain w/ locale # # BR2_PACKAGE_LIBIQRF is not set # BR2_PACKAGE_LIBLLCP is not set # BR2_PACKAGE_LIBMBIM is not set # BR2_PACKAGE_LIBNFC is not set # BR2_PACKAGE_LIBPCIACCESS is not set # BR2_PACKAGE_LIBPHIDGET is not set # # libpri needs a kernel to be built # # BR2_PACKAGE_LIBQMI is not set # BR2_PACKAGE_LIBRAW1394 is not set # BR2_PACKAGE_LIBRTLSDR is not set # # libserial needs a toolchain w/ C++, gcc >= 5, threads, wchar # # BR2_PACKAGE_LIBSERIALPORT is not set # BR2_PACKAGE_LIBSIGROK is not set # BR2_PACKAGE_LIBSIGROKDECODE is not set # BR2_PACKAGE_LIBSOC is not set # # libss7 needs a kernel to be built # # BR2_PACKAGE_LIBUSB is not set # BR2_PACKAGE_LIBUSBGX is not set # # libv4l needs a toolchain w/ threads, C++ and headers >= 3.0 # # BR2_PACKAGE_LIBXKBCOMMON is not set # BR2_PACKAGE_MTDEV is not set # BR2_PACKAGE_NEARDAL is not set # BR2_PACKAGE_OWFS is not set # BR2_PACKAGE_PCSC_LITE is not set # BR2_PACKAGE_TSLIB is not set # # urg needs a toolchain w/ C++ # # BR2_PACKAGE_WIRINGPI is not set # # Javascript # # BR2_PACKAGE_ANGULARJS is not set # BR2_PACKAGE_BOOTSTRAP is not set # BR2_PACKAGE_DUKTAPE is not set # BR2_PACKAGE_EXPLORERCANVAS is not set # BR2_PACKAGE_FLOT is not set # BR2_PACKAGE_JQUERY is not set # BR2_PACKAGE_JSMIN is not set # BR2_PACKAGE_JSON_JAVASCRIPT is not set # # JSON/XML # # # benejson needs a toolchain w/ C++ # # BR2_PACKAGE_CJSON is not set # BR2_PACKAGE_EXPAT is not set # BR2_PACKAGE_EZXML is not set # BR2_PACKAGE_JANSSON is not set # BR2_PACKAGE_JOSE is not set # BR2_PACKAGE_JSMN is not set # BR2_PACKAGE_JSON_C is not set # # json-for-modern-cpp needs a toolchain w/ C++, gcc >= 4.9 # # BR2_PACKAGE_JSON_GLIB is not set # # jsoncpp needs a toolchain w/ C++, gcc >= 4.7 # # BR2_PACKAGE_LIBBSON is not set # BR2_PACKAGE_LIBFASTJSON is not set # # libjson needs a toolchain w/ C++ # # BR2_PACKAGE_LIBROXML is not set # BR2_PACKAGE_LIBUCL is not set # BR2_PACKAGE_LIBXML2 is not set # # libxml++ needs a toolchain w/ C++, wchar, threads, gcc >= 4.9 # # BR2_PACKAGE_LIBXMLRPC is not set # BR2_PACKAGE_LIBXSLT is not set # BR2_PACKAGE_LIBYAML is not set # BR2_PACKAGE_MXML is not set # # pugixml needs a toolchain w/ C++ # # # rapidjson needs a toolchain w/ C++ # # BR2_PACKAGE_RAPIDXML is not set # BR2_PACKAGE_RAPTOR is not set # # tinyxml needs a toolchain w/ C++ # # # tinyxml2 needs a toolchain w/ C++ # # # valijson needs a toolchain w/ C++, threads, wchar support # # # xerces-c++ needs a toolchain w/ C++, wchar # # BR2_PACKAGE_YAJL is not set # # yaml-cpp needs a toolchain w/ C++, gcc >= 4.7 # # # Logging # # BR2_PACKAGE_EVENTLOG is not set # # glog needs a toolchain w/ C++, threads, dynamic library # # BR2_PACKAGE_LIBLOG4C_LOCALTIME is not set # BR2_PACKAGE_LIBLOGGING is not set # # log4cplus needs a toolchain w/ C++, wchar, threads, gcc >= 4.8 # # # log4cpp needs a toolchain w/ C++, threads # # # log4cxx needs a toolchain w/ C++, threads, dynamic library # # # opentracing-cpp needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8 # # # spdlog needs a toolchain w/ C++, wchar # # BR2_PACKAGE_ZLOG is not set # # Multimedia # # BR2_PACKAGE_BITSTREAM is not set # # kvazaar needs a toolchain w/ C++, threads # # BR2_PACKAGE_LIBAACS is not set # BR2_PACKAGE_LIBASS is not set # BR2_PACKAGE_LIBBDPLUS is not set # BR2_PACKAGE_LIBBLURAY is not set # # libcamera needs udev and a toolchain w/ C++, threads, gcc >= 5 # # BR2_PACKAGE_LIBDCADEC is not set # BR2_PACKAGE_LIBDVBCSA is not set # BR2_PACKAGE_LIBDVBPSI is not set # # libdvbsi++ needs a toolchain w/ C++, wchar, threads # # BR2_PACKAGE_LIBDVDCSS is not set # BR2_PACKAGE_LIBDVDNAV is not set # BR2_PACKAGE_LIBDVDREAD is not set # # libebml needs a toolchain w/ C++, wchar # # BR2_PACKAGE_LIBHDHOMERUN is not set # # libmatroska needs a toolchain w/ C++, wchar # # BR2_PACKAGE_LIBMMS is not set # BR2_PACKAGE_LIBMPEG2 is not set # BR2_PACKAGE_LIBOGG is not set # BR2_PACKAGE_LIBOPUSENC is not set # BR2_PACKAGE_LIBPLAYER is not set # BR2_PACKAGE_LIBTHEORA is not set # BR2_PACKAGE_LIBVPX is not set # # libyuv needs a toolchain w/ C++, dynamic library # # # live555 needs a toolchain w/ C++ # # # mediastreamer needs a toolchain w/ threads, C++ # # BR2_PACKAGE_X264 is not set # # x265 needs a toolchain w/ C++, threads, dynamic library # # # Networking # # # agent++ needs a toolchain w/ threads, C++, dynamic library # # # alljoyn needs a toolchain w/ C++, threads, wchar and dynamic library # # # alljoyn-base needs a toolchain w/ C++, threads, wchar, dynamic library # # BR2_PACKAGE_ALLJOYN_TCL is not set # BR2_PACKAGE_ALLJOYN_TCL_BASE is not set # # azmq needs a toolchain w/ C++11, wchar and NTPL # # # azure-iot-sdk-c needs a toolchain w/ C++ and NPTL # # # batman-adv needs a Linux kernel to be built # # BR2_PACKAGE_C_ARES is not set # BR2_PACKAGE_CGIC is not set # # cppzmq needs a toolchain w/ C++, threads # # # curlpp needs a toolchain w/ C++, dynamic library # # # czmq needs a toolchain w/ C++, threads # # BR2_PACKAGE_DAQ is not set # BR2_PACKAGE_DAVICI is not set # BR2_PACKAGE_ENET is not set # # filemq needs a toolchain w/ C++, threads # # BR2_PACKAGE_FLICKCURL is not set # BR2_PACKAGE_FREERADIUS_CLIENT is not set # BR2_PACKAGE_GEOIP is not set # BR2_PACKAGE_GLIB_NETWORKING is not set # # grpc needs a toolchain w/ C++, threads, dynamic library, host and target gcc >= 4.8 # # BR2_PACKAGE_GSSDP is not set # BR2_PACKAGE_GUPNP is not set # BR2_PACKAGE_GUPNP_AV is not set # BR2_PACKAGE_GUPNP_DLNA is not set # # ibrcommon needs a toolchain w/ C++, threads # # # ibrdtn needs a toolchain w/ C++, threads # # BR2_PACKAGE_LIBCGI is not set # # libcgicc needs a toolchain w/ C++ # # BR2_PACKAGE_LIBCOAP is not set # # libcpprestsdk needs a toolchain w/ NPTL, C++, wchar # # BR2_PACKAGE_LIBCURL is not set # BR2_PACKAGE_LIBDNET is not set # BR2_PACKAGE_LIBEXOSIP2 is not set # BR2_PACKAGE_LIBFCGI is not set # BR2_PACKAGE_LIBGSASL is not set # BR2_PACKAGE_LIBHTP is not set # BR2_PACKAGE_LIBHTTPPARSER is not set # BR2_PACKAGE_LIBIDN is not set # BR2_PACKAGE_LIBIDN2 is not set # BR2_PACKAGE_LIBISCSI is not set # BR2_PACKAGE_LIBKRB5 is not set # BR2_PACKAGE_LIBLDNS is not set # BR2_PACKAGE_LIBMAXMINDDB is not set # BR2_PACKAGE_LIBMBUS is not set # # libmemcached needs a toolchain w/ C++, threads # # BR2_PACKAGE_LIBMICROHTTPD is not set # BR2_PACKAGE_LIBMINIUPNPC is not set # BR2_PACKAGE_LIBMNL is not set # BR2_PACKAGE_LIBMODBUS is not set # BR2_PACKAGE_LIBNATPMP is not set # BR2_PACKAGE_LIBNDP is not set # BR2_PACKAGE_LIBNET is not set # BR2_PACKAGE_LIBNETFILTER_ACCT is not set # BR2_PACKAGE_LIBNETFILTER_CONNTRACK is not set # BR2_PACKAGE_LIBNETFILTER_CTHELPER is not set # BR2_PACKAGE_LIBNETFILTER_CTTIMEOUT is not set # BR2_PACKAGE_LIBNETFILTER_LOG is not set # BR2_PACKAGE_LIBNETFILTER_QUEUE is not set # BR2_PACKAGE_LIBNFNETLINK is not set # BR2_PACKAGE_LIBNFTNL is not set # BR2_PACKAGE_LIBNICE is not set # BR2_PACKAGE_LIBNL is not set # BR2_PACKAGE_LIBOAUTH is not set # BR2_PACKAGE_LIBOPING is not set # BR2_PACKAGE_LIBOSIP2 is not set # BR2_PACKAGE_LIBPAGEKITE is not set # BR2_PACKAGE_LIBPCAP is not set # # libpjsip needs a toolchain w/ C++, threads # # BR2_PACKAGE_LIBRSYNC is not set # BR2_PACKAGE_LIBSHAIRPLAY is not set # BR2_PACKAGE_LIBSHOUT is not set # BR2_PACKAGE_LIBSOCKETCAN is not set # BR2_PACKAGE_LIBSOUP is not set # BR2_PACKAGE_LIBSRTP is not set # BR2_PACKAGE_LIBSTROPHE is not set # BR2_PACKAGE_LIBTIRPC is not set # # libtorrent needs a toolchain w/ C++, threads # # # libtorrent-rasterbar needs a toolchain w/ C++, threads, wchar, gcc >= 4.9 # # BR2_PACKAGE_LIBUPNP is not set # BR2_PACKAGE_LIBUPNP18 is not set # # libupnpp needs a toolchain w/ C++, threads, gcc >= 4.9 # # BR2_PACKAGE_LIBURIPARSER is not set # BR2_PACKAGE_LIBVNCSERVER is not set # BR2_PACKAGE_LIBWEBSOCK is not set # BR2_PACKAGE_LIBWEBSOCKETS is not set # BR2_PACKAGE_LKSCTP_TOOLS is not set # BR2_PACKAGE_MONGOOSE is not set # BR2_PACKAGE_NANOMSG is not set # BR2_PACKAGE_NEON is not set # BR2_PACKAGE_NGHTTP2 is not set # # norm needs a toolchain w/ C++, threads, dynamic library # # BR2_PACKAGE_NSS_MYHOSTNAME is not set # BR2_PACKAGE_NSS_PAM_LDAPD is not set # # omniORB needs a toolchain w/ C++, threads # # BR2_PACKAGE_OPENLDAP is not set # # openmpi needs a toolchain w/ dynamic library, NPTL, wchar, C++ # # BR2_PACKAGE_OPENPGM is not set # # openzwave needs a toolchain w/ C++, dynamic library, NPTL, wchar # # # ortp needs a toolchain w/ C++, threads # # BR2_PACKAGE_PAHO_MQTT_C is not set # # paho-mqtt-cpp needs a toolchain w/ threads, C++, dynamic library support # # BR2_PACKAGE_QDECODER is not set # BR2_PACKAGE_QPID_PROTON is not set # BR2_PACKAGE_RABBITMQ_C is not set # BR2_PACKAGE_RTMPDUMP is not set # BR2_PACKAGE_SLIRP is not set # # snmp++ needs a toolchain w/ threads, C++, dynamic library # # BR2_PACKAGE_SOFIA_SIP is not set # # thrift needs a toolchain w/ C++, wchar, threads # # BR2_PACKAGE_USBREDIR is not set # # wampcc needs a toolchain w/ C++, NPTL, dynamic library # # # websocketpp needs a toolchain w/ C++ and gcc >= 4.8 # # # zeromq needs a toolchain w/ C++, threads # # # zmqpp needs a toolchain w/ C++, threads, gcc >= 4.7 # # # zyre needs a toolchain w/ C++, threads # # # Other # # BR2_PACKAGE_APR is not set # BR2_PACKAGE_APR_UTIL is not set # # armadillo needs a toolchain w/ C++ # # # atf needs a toolchain w/ C++ # # # bctoolbox needs a toolchain w/ C++, threads # # # boost needs a toolchain w/ C++, threads, wchar # # # c-capnproto needs host and target gcc >= 4.8 w/ C++, threads, atomic # # # capnproto needs host and target gcc >= 4.8 w/ C++, threads, atomic # # BR2_PACKAGE_CLAPACK is not set # BR2_PACKAGE_CMOCKA is not set # # cppcms needs a toolchain w/ C++, NPTL, wchar, dynamic library # # BR2_PACKAGE_CRACKLIB is not set # # dawgdic needs a toolchain w/ C++, gcc >= 4.6 # # BR2_PACKAGE_DING_LIBS is not set # # eigen needs a toolchain w/ C++ # # BR2_PACKAGE_ELFUTILS is not set # BR2_PACKAGE_ELL is not set # BR2_PACKAGE_FFTW is not set # # flann needs a toolchain w/ C++, dynamic library # # # flatbuffers needs a toolchain w/ C++, gcc >= 4.7 # # BR2_PACKAGE_FLATCC is not set # BR2_PACKAGE_GCONF is not set # # gflags needs a toolchain w/ C++ # # # gli needs a toolchain w/ C++ # # # glibmm needs a toolchain w/ C++, wchar, threads, gcc >= 4.9 # # # glm needs a toolchain w/ C++ # # BR2_PACKAGE_GMP is not set # BR2_PACKAGE_GSL is not set # # gtest needs a toolchain w/ C++, wchar, threads # BR2_PACKAGE_JEMALLOC_ARCH_SUPPORTS=y # BR2_PACKAGE_JEMALLOC is not set # # lapack/blas needs a toolchain w/ fortran # # BR2_PACKAGE_LIBARGTABLE2 is not set # BR2_PACKAGE_LIBB64 is not set BR2_PACKAGE_LIBBSD_ARCH_SUPPORTS=y # BR2_PACKAGE_LIBBSD is not set # BR2_PACKAGE_LIBCAP is not set # BR2_PACKAGE_LIBCAP_NG is not set # # libcgroup needs a glibc toolchain w/ C++ # # BR2_PACKAGE_LIBCORRECT is not set # BR2_PACKAGE_LIBCROCO is not set # # libcrossguid needs a toolchain w/ C++, gcc >= 4.7 # # BR2_PACKAGE_LIBCSV is not set # BR2_PACKAGE_LIBDAEMON is not set # BR2_PACKAGE_LIBEE is not set # BR2_PACKAGE_LIBEV is not set # BR2_PACKAGE_LIBEVDEV is not set # BR2_PACKAGE_LIBEVENT is not set BR2_PACKAGE_LIBFFI=y # BR2_PACKAGE_LIBGEE is not set # BR2_PACKAGE_LIBGLIB2 is not set # BR2_PACKAGE_LIBGLOB is not set # # libical needs a toolchain w/ C++, dynamic library, wchar # # BR2_PACKAGE_LIBITE is not set # # liblinear needs a toolchain w/ C++ # # # libloki needs a toolchain w/ C++, threads # # BR2_PACKAGE_LIBNPTH is not set BR2_PACKAGE_LIBNSPR_ARCH_SUPPORT=y # BR2_PACKAGE_LIBNSPR is not set # BR2_PACKAGE_LIBPFM4 is not set # # libplist needs a toolchain w/ C++, threads # # BR2_PACKAGE_LIBPTHREAD_STUBS is not set # BR2_PACKAGE_LIBPTHSEM is not set # BR2_PACKAGE_LIBPWQUALITY is not set # # libsigc++ needs a toolchain w/ C++, gcc >= 4.8 # BR2_PACKAGE_LIBSIGSEGV_ARCH_SUPPORTS=y # BR2_PACKAGE_LIBSIGSEGV is not set # # libspatialindex needs a toolchain w/ C++ # # BR2_PACKAGE_LIBTASN1 is not set # BR2_PACKAGE_LIBTOMMATH is not set # BR2_PACKAGE_LIBTPL is not set # BR2_PACKAGE_LIBUBOX is not set # BR2_PACKAGE_LIBUCI is not set # BR2_PACKAGE_LIBUV is not set # BR2_PACKAGE_LINUX_PAM is not set # BR2_PACKAGE_LIQUID_DSP is not set # BR2_PACKAGE_MPC is not set # BR2_PACKAGE_MPDECIMAL is not set # BR2_PACKAGE_MPFR is not set # BR2_PACKAGE_MPIR is not set # # msgpack needs a toolchain w/ C++ # # BR2_PACKAGE_MTDEV2TUIO is not set # BR2_PACKAGE_ORC is not set # BR2_PACKAGE_P11_KIT is not set # # poco needs a toolchain w/ wchar, NPTL, C++, dynamic library # BR2_PACKAGE_PROTOBUF_ARCH_SUPPORTS=y # # protobuf needs a toolchain w/ C++, threads, dynamic library, host and target gcc >= 4.8 # # # protobuf-c needs a toolchain w/ C++, threads, host gcc >= 4.8 # # # qhull needs a toolchain w/ C++, dynamic library, gcc >= 4.4 # # BR2_PACKAGE_QLIBC is not set # # riemann-c-client needs a toolchain w/ C++, threads, host gcc >= 4.8 # # # shapelib needs a toolchain w/ C++, threads # # BR2_PACKAGE_SKALIBS is not set # BR2_PACKAGE_SPHINXBASE is not set # BR2_PACKAGE_TINYCBOR is not set # # xapian needs a toolchain w/ C++ # # # Security # # BR2_PACKAGE_LIBSELINUX is not set # BR2_PACKAGE_LIBSEPOL is not set # BR2_PACKAGE_SAFECLIB is not set # # Text and terminal handling # # BR2_PACKAGE_AUGEAS is not set # # enchant needs a toolchain w/ C++, threads, wchar # # # fmt needs a toolchain w/ C++, wchar # # # icu needs a toolchain w/ C++, wchar, threads, gcc >= 4.8, host gcc >= 4.8 # # BR2_PACKAGE_LIBCLI is not set # BR2_PACKAGE_LIBEDIT is not set # BR2_PACKAGE_LIBENCA is not set # BR2_PACKAGE_LIBESTR is not set # BR2_PACKAGE_LIBFRIBIDI is not set # BR2_PACKAGE_LIBUNISTRING is not set # BR2_PACKAGE_LINENOISE is not set BR2_PACKAGE_NCURSES=y # BR2_PACKAGE_NCURSES_WCHAR is not set # BR2_PACKAGE_NCURSES_TARGET_PROGS is not set BR2_PACKAGE_NCURSES_ADDITIONAL_TERMINFO="" # BR2_PACKAGE_NEWT is not set # BR2_PACKAGE_ONIGURUMA is not set BR2_PACKAGE_PCRE=y # BR2_PACKAGE_PCRE_16 is not set # BR2_PACKAGE_PCRE_32 is not set BR2_PACKAGE_PCRE_UTF=y BR2_PACKAGE_PCRE_UCP=y # BR2_PACKAGE_PCRE2 is not set # BR2_PACKAGE_POPT is not set # BR2_PACKAGE_READLINE is not set # BR2_PACKAGE_SLANG is not set # # tclap needs a toolchain w/ C++ # # BR2_PACKAGE_USTR is not set # # Mail # # BR2_PACKAGE_DOVECOT is not set # BR2_PACKAGE_EXIM is not set # BR2_PACKAGE_FETCHMAIL is not set # BR2_PACKAGE_HEIRLOOM_MAILX is not set # BR2_PACKAGE_LIBESMTP is not set # BR2_PACKAGE_MSMTP is not set # BR2_PACKAGE_MUTT is not set # # Miscellaneous # # BR2_PACKAGE_AESPIPE is not set # BR2_PACKAGE_BC is not set # # clamav needs a toolchain w/ C++, threads, wchar # # BR2_PACKAGE_COLLECTD is not set # # domoticz needs lua 5.3 and a toolchain w/ C++, gcc >= 4.8, NPTL, wchar, dynamic library # # BR2_PACKAGE_EMPTY is not set # # gnuradio needs a toolchain w/ C++, NPTL, wchar, dynamic library # # BR2_PACKAGE_GOOGLEFONTDIRECTORY is not set # # gqrx needs a toolchain w/ C++, threads, wchar, dynamic library # # # gqrx needs qt5 # # BR2_PACKAGE_GSETTINGS_DESKTOP_SCHEMAS is not set # BR2_PACKAGE_HAVEGED is not set # BR2_PACKAGE_LINUX_SYSCALL_SUPPORT is not set # BR2_PACKAGE_MCRYPT is not set # BR2_PACKAGE_MOBILE_BROADBAND_PROVIDER_INFO is not set # BR2_PACKAGE_PROJ is not set # # qpdf needs a toolchain w/ C++ # # BR2_PACKAGE_SHARED_MIME_INFO is not set # # taskd needs a toolchain w/ C++, wchar, dynamic library # # BR2_PACKAGE_XUTIL_UTIL_MACROS is not set # # Networking applications # # # aircrack-ng needs a toolchain w/ dynamic library, threads, C++ # # BR2_PACKAGE_AOETOOLS is not set # BR2_PACKAGE_APACHE is not set # BR2_PACKAGE_ARGUS is not set # BR2_PACKAGE_ARP_SCAN is not set # BR2_PACKAGE_ARPTABLES is not set # # asterisk needs a glibc or uClibc toolchain w/ C++, dynamic library, threads, wchar # # BR2_PACKAGE_ATFTP is not set # BR2_PACKAGE_AVAHI is not set # BR2_PACKAGE_AXEL is not set # BR2_PACKAGE_BABELD is not set # BR2_PACKAGE_BANDWIDTHD is not set # BR2_PACKAGE_BATCTL is not set # # bcusdk needs a toolchain w/ C++ # # BR2_PACKAGE_BIND is not set # BR2_PACKAGE_BIRD is not set # BR2_PACKAGE_BLUEZ_UTILS is not set # BR2_PACKAGE_BLUEZ5_UTILS is not set # BR2_PACKAGE_BMON is not set # BR2_PACKAGE_BOA is not set # # boinc needs a toolchain w/ dynamic library, C++, threads # # BR2_PACKAGE_BRCM_PATCHRAM_PLUS is not set # BR2_PACKAGE_BRIDGE_UTILS is not set # BR2_PACKAGE_BWM_NG is not set # BR2_PACKAGE_C_ICAP is not set # BR2_PACKAGE_CAN_UTILS is not set # # cannelloni needs a toolchain w/ C++, threads, dynamic library, gcc >= 4.8 # # BR2_PACKAGE_CHRONY is not set # BR2_PACKAGE_CIVETWEB is not set # BR2_PACKAGE_CONNMAN is not set # # connman-gtk needs libgtk3 and a glibc or uClibc toolchain w/ wchar, threads, resolver, dynamic library # # BR2_PACKAGE_CONNTRACK_TOOLS is not set # BR2_PACKAGE_CORKSCREW is not set # BR2_PACKAGE_CRDA is not set # # ctorrent needs a toolchain w/ C++ # # # cups needs a toolchain w/ C++, threads # # # cups-filters needs a toolchain w/ wchar, C++, threads and dynamic library, gcc >= 4.8 # # BR2_PACKAGE_DANTE is not set # BR2_PACKAGE_DARKHTTPD is not set # BR2_PACKAGE_DEHYDRATED is not set # BR2_PACKAGE_DHCPCD is not set # BR2_PACKAGE_DHCPDUMP is not set # BR2_PACKAGE_DNSMASQ is not set # BR2_PACKAGE_DRBD_UTILS is not set # BR2_PACKAGE_DROPBEAR is not set # BR2_PACKAGE_EBTABLES is not set # # ejabberd needs erlang, toolchain w/ C++ # # BR2_PACKAGE_ETHTOOL is not set # BR2_PACKAGE_FAIFA is not set # BR2_PACKAGE_FASTD is not set # BR2_PACKAGE_FCGIWRAP is not set # BR2_PACKAGE_FPING is not set # # freeswitch needs a toolchain w/ C++, dynamic library, threads, wchar # # # gerbera needs a toolchain w/ C++, threads, gcc >= 7 # # BR2_PACKAGE_GESFTPSERVER is not set # BR2_PACKAGE_GLORYTUN is not set # # gupnp-tools needs libgtk3 # # # hans needs a toolchain w/ C++ # BR2_PACKAGE_HAPROXY_ARCH_SUPPORTS=y # BR2_PACKAGE_HAPROXY is not set # BR2_PACKAGE_HIAWATHA is not set # BR2_PACKAGE_HOSTAPD is not set # BR2_PACKAGE_HTTPING is not set # # i2pd needs a toolchain w/ C++, NPTL, wchar # # # ibrdtn-tools needs a toolchain w/ C++, threads # # # ibrdtnd needs a toolchain w/ C++, threads # # BR2_PACKAGE_IFMETRIC is not set # BR2_PACKAGE_IFTOP is not set BR2_PACKAGE_IFUPDOWN_SCRIPTS=y # BR2_PACKAGE_IGD2_FOR_LINUX is not set # # igh-ethercat needs a Linux kernel to be built # # BR2_PACKAGE_IGMPPROXY is not set # BR2_PACKAGE_INADYN is not set # BR2_PACKAGE_IODINE is not set # # iperf needs a toolchain w/ C++ # # BR2_PACKAGE_IPERF3 is not set # BR2_PACKAGE_IPROUTE2 is not set # BR2_PACKAGE_IPSEC_TOOLS is not set # BR2_PACKAGE_IPSET is not set # BR2_PACKAGE_IPTABLES is not set # BR2_PACKAGE_IPTRAF_NG is not set # BR2_PACKAGE_IPUTILS is not set # BR2_PACKAGE_IRSSI is not set # BR2_PACKAGE_IW is not set # BR2_PACKAGE_IWD is not set # BR2_PACKAGE_JANUS_GATEWAY is not set # BR2_PACKAGE_KEEPALIVED is not set # # kismet needs a toolchain w/ threads, C++, dynamic library # # BR2_PACKAGE_KNOCK is not set # BR2_PACKAGE_LEAFNODE2 is not set # BR2_PACKAGE_LFT is not set # # lftp requires a toolchain w/ C++, wchar # # BR2_PACKAGE_LIGHTTPD is not set # # linknx needs a toolchain w/ C++ # # BR2_PACKAGE_LINKS is not set # # linphone needs a toolchain w/ threads, C++ # # BR2_PACKAGE_LINUX_ZIGBEE is not set # BR2_PACKAGE_LINUXPTP is not set # BR2_PACKAGE_LLDPD is not set # BR2_PACKAGE_LRZSZ is not set # BR2_PACKAGE_LYNX is not set # BR2_PACKAGE_MACCHANGER is not set # BR2_PACKAGE_MEMCACHED is not set # BR2_PACKAGE_MII_DIAG is not set # BR2_PACKAGE_MINI_SNMPD is not set # BR2_PACKAGE_MINIDLNA is not set # BR2_PACKAGE_MINISSDPD is not set # BR2_PACKAGE_MJPG_STREAMER is not set # BR2_PACKAGE_MODEM_MANAGER is not set BR2_PACKAGE_MONGREL2_LIBC_SUPPORTS=y # # mongrel2 needs a uClibc or glibc toolchain w/ C++, threads, dynamic library # # BR2_PACKAGE_MONKEY is not set # # mosh needs a toolchain w/ C++, threads, dynamic library, wchar, host and target gcc >= 4.8 # # BR2_PACKAGE_MOSQUITTO is not set # BR2_PACKAGE_MROUTED is not set # BR2_PACKAGE_MTR is not set # BR2_PACKAGE_NBD is not set # BR2_PACKAGE_NCFTP is not set # BR2_PACKAGE_NDISC6 is not set # BR2_PACKAGE_NETATALK is not set # BR2_PACKAGE_NETPLUG is not set # BR2_PACKAGE_NETSNMP is not set # BR2_PACKAGE_NETSTAT_NAT is not set # # NetworkManager needs udev /dev management and a glibc toolchain w/ headers >= 3.2, dynamic library # # BR2_PACKAGE_NFACCT is not set # BR2_PACKAGE_NFTABLES is not set # BR2_PACKAGE_NGINX is not set # BR2_PACKAGE_NGIRCD is not set # BR2_PACKAGE_NGREP is not set # # nload needs a toolchain w/ C++ # # # nmap-nmap needs a toolchain w/ C++, threads # # BR2_PACKAGE_NOIP is not set # BR2_PACKAGE_NTP is not set # BR2_PACKAGE_NUTTCP is not set # BR2_PACKAGE_ODHCP6C is not set # BR2_PACKAGE_ODHCPLOC is not set # BR2_PACKAGE_OLSR is not set # BR2_PACKAGE_OPEN_LLDP is not set # BR2_PACKAGE_OPEN_PLC_UTILS is not set # BR2_PACKAGE_OPENNTPD is not set # BR2_PACKAGE_OPENOBEX is not set # BR2_PACKAGE_OPENRESOLV is not set # BR2_PACKAGE_OPENSSH is not set # BR2_PACKAGE_OPENSWAN is not set # BR2_PACKAGE_OPENVPN is not set # BR2_PACKAGE_P910ND is not set # BR2_PACKAGE_PHIDGETWEBSERVICE is not set # BR2_PACKAGE_PHYTOOL is not set # BR2_PACKAGE_PIMD is not set # BR2_PACKAGE_PIXIEWPS is not set # BR2_PACKAGE_POUND is not set # BR2_PACKAGE_PPPD is not set # BR2_PACKAGE_PPTP_LINUX is not set # BR2_PACKAGE_PRIVOXY is not set # BR2_PACKAGE_PROFTPD is not set # # prosody needs the lua interpreter, dynamic library # # BR2_PACKAGE_PROXYCHAINS_NG is not set # BR2_PACKAGE_PTPD is not set # BR2_PACKAGE_PTPD2 is not set # BR2_PACKAGE_PURE_FTPD is not set # BR2_PACKAGE_PUTTY is not set # BR2_PACKAGE_QUAGGA is not set # # rabbitmq-server needs erlang # # BR2_PACKAGE_RADVD is not set # BR2_PACKAGE_REAVER is not set # BR2_PACKAGE_RP_PPPOE is not set # BR2_PACKAGE_RPCBIND is not set # BR2_PACKAGE_RSH_REDONE is not set # BR2_PACKAGE_RSYNC is not set # # rtorrent needs a toolchain w/ C++, threads, wchar, gcc >= 4.9 # # BR2_PACKAGE_RTPTOOLS is not set # BR2_PACKAGE_RYGEL is not set # BR2_PACKAGE_S6_DNS is not set # BR2_PACKAGE_S6_NETWORKING is not set # BR2_PACKAGE_SAMBA4 is not set # # sconeserver needs a toolchain with dynamic library, C++, NPTL # # BR2_PACKAGE_SER2NET is not set # BR2_PACKAGE_SHADOWSOCKS_LIBEV is not set # # shairport-sync needs a toolchain w/ C++, NPTL # # BR2_PACKAGE_SHELLINABOX is not set # BR2_PACKAGE_SMCROUTE is not set # BR2_PACKAGE_SNGREP is not set # BR2_PACKAGE_SNORT is not set # BR2_PACKAGE_SOCAT is not set # BR2_PACKAGE_SOCKETCAND is not set # BR2_PACKAGE_SOFTETHER is not set # BR2_PACKAGE_SPAWN_FCGI is not set # BR2_PACKAGE_SPICE_PROTOCOL is not set # # squid needs a toolchain w/ C++, gcc >= 4.8 not affected by bug 64735 # # BR2_PACKAGE_SSHGUARD is not set # BR2_PACKAGE_SSHPASS is not set # # sslh needs a toolchain w/ C++ # # BR2_PACKAGE_STRONGSWAN is not set # BR2_PACKAGE_STUNNEL is not set # BR2_PACKAGE_SURICATA is not set # BR2_PACKAGE_TCPDUMP is not set # BR2_PACKAGE_TCPING is not set # BR2_PACKAGE_TCPREPLAY is not set # BR2_PACKAGE_THTTPD is not set # BR2_PACKAGE_TINC is not set # BR2_PACKAGE_TINYHTTPD is not set # BR2_PACKAGE_TOR is not set # BR2_PACKAGE_TRACEROUTE is not set # BR2_PACKAGE_TRANSMISSION is not set # BR2_PACKAGE_TUNCTL is not set # BR2_PACKAGE_TVHEADEND is not set # BR2_PACKAGE_UDPCAST is not set # BR2_PACKAGE_UFTP is not set # BR2_PACKAGE_UHTTPD is not set # BR2_PACKAGE_ULOGD is not set # BR2_PACKAGE_USHARE is not set # BR2_PACKAGE_USSP_PUSH is not set # BR2_PACKAGE_VDE2 is not set # # vdr needs a glibc toolchain w/ C++, dynamic library, NPTL, wchar, headers >= 3.9 # # BR2_PACKAGE_VNSTAT is not set # BR2_PACKAGE_VPNC is not set # BR2_PACKAGE_VSFTPD is not set # BR2_PACKAGE_VTUN is not set # BR2_PACKAGE_WAVEMON is not set # BR2_PACKAGE_WIREGUARD is not set # BR2_PACKAGE_WIRELESS_REGDB is not set # BR2_PACKAGE_WIRELESS_TOOLS is not set # BR2_PACKAGE_WIRESHARK is not set # BR2_PACKAGE_WPA_SUPPLICANT is not set # BR2_PACKAGE_WPAN_TOOLS is not set # BR2_PACKAGE_XINETD is not set # BR2_PACKAGE_XL2TP is not set # # xtables-addons needs a Linux kernel to be built # # # znc needs a toolchain w/ C++, dynamic library, gcc >= 4.8, threads # # # Package managers # # # ------------------------------------------------------- # # # Please note: # # # - Buildroot does *not* generate binary packages, # # # - Buildroot does *not* install any package database. # # # * # # # It is up to you to provide those by yourself if you # # # want to use any of those package managers. # # # * # # # See the manual: # # # http://buildroot.org/manual.html#faq-no-binary-packages # # # ------------------------------------------------------- # # BR2_PACKAGE_OPKG is not set # # Real-Time # # BR2_PACKAGE_XENOMAI is not set # # Security # # BR2_PACKAGE_CHECKPOLICY is not set # BR2_PACKAGE_OPTEE_BENCHMARK is not set # BR2_PACKAGE_OPTEE_CLIENT is not set # BR2_PACKAGE_PAXTEST is not set # BR2_PACKAGE_RESTORECOND is not set # BR2_PACKAGE_SELINUX_PYTHON is not set # BR2_PACKAGE_SEMODULE_UTILS is not set # BR2_PACKAGE_SETOOLS is not set # # setools needs a glibc toolchain w/ threads, C++, wchar, dynamic library # # # Shell and utilities # # # Shells # # BR2_PACKAGE_MKSH is not set # BR2_PACKAGE_ZSH is not set # # Utilities # # BR2_PACKAGE_AT is not set # BR2_PACKAGE_CCRYPT is not set # BR2_PACKAGE_DIALOG is not set # BR2_PACKAGE_DTACH is not set # BR2_PACKAGE_EASY_RSA is not set # BR2_PACKAGE_FILE is not set # BR2_PACKAGE_GNUPG is not set # BR2_PACKAGE_GNUPG2 is not set # BR2_PACKAGE_INOTIFY_TOOLS is not set # BR2_PACKAGE_LOCKFILE_PROGS is not set # BR2_PACKAGE_LOGROTATE is not set # BR2_PACKAGE_LOGSURFER is not set # BR2_PACKAGE_PDMENU is not set # BR2_PACKAGE_PINENTRY is not set # BR2_PACKAGE_RANGER is not set # BR2_PACKAGE_SCREEN is not set # BR2_PACKAGE_SUDO is not set # BR2_PACKAGE_TINI is not set # BR2_PACKAGE_TMUX is not set # BR2_PACKAGE_XMLSTARLET is not set # BR2_PACKAGE_XXHASH is not set # # System tools # # BR2_PACKAGE_ACL is not set # BR2_PACKAGE_ANDROID_TOOLS is not set # BR2_PACKAGE_ATOP is not set # BR2_PACKAGE_ATTR is not set # BR2_PACKAGE_CGROUPFS_MOUNT is not set # # circus needs Python and a toolchain w/ C++, threads # # BR2_PACKAGE_CPULOAD is not set # BR2_PACKAGE_DAEMON is not set # BR2_PACKAGE_DC3DD is not set # # ddrescue needs a toolchain w/ C++ # # BR2_PACKAGE_DOCKER_COMPOSE is not set # # emlog needs a Linux kernel to be built # # BR2_PACKAGE_FTOP is not set # BR2_PACKAGE_GETENT is not set # BR2_PACKAGE_HTOP is not set BR2_PACKAGE_INITSCRIPTS=y # # iotop depends on python or python3 # # BR2_PACKAGE_IPRUTILS is not set # BR2_PACKAGE_IRQBALANCE is not set # BR2_PACKAGE_KEYUTILS is not set # BR2_PACKAGE_KMOD is not set # BR2_PACKAGE_LIBOSTREE is not set # BR2_PACKAGE_LXC is not set # BR2_PACKAGE_MONIT is not set # BR2_PACKAGE_NCDU is not set # # nut needs a toolchain w/ C++ # # # pamtester depends on linux-pam # # BR2_PACKAGE_POLKIT is not set # BR2_PACKAGE_PROCRANK_LINUX is not set # BR2_PACKAGE_PWGEN is not set # BR2_PACKAGE_QUOTA is not set # BR2_PACKAGE_QUOTATOOL is not set # BR2_PACKAGE_RAUC is not set # BR2_PACKAGE_S6 is not set # BR2_PACKAGE_S6_LINUX_INIT is not set # BR2_PACKAGE_S6_LINUX_UTILS is not set # BR2_PACKAGE_S6_PORTABLE_UTILS is not set # BR2_PACKAGE_S6_RC is not set # BR2_PACKAGE_SCRUB is not set # BR2_PACKAGE_SCRYPT is not set # BR2_PACKAGE_SMACK is not set # # supervisor needs the python interpreter # # BR2_PACKAGE_SWUPDATE is not set BR2_PACKAGE_SYSTEMD_ARCH_SUPPORTS=y # BR2_PACKAGE_TPM_TOOLS is not set # BR2_PACKAGE_TPM2_ABRMD is not set # BR2_PACKAGE_TPM2_TOOLS is not set # BR2_PACKAGE_TPM2_TOTP is not set # BR2_PACKAGE_UNSCD is not set BR2_PACKAGE_UTIL_LINUX=y BR2_PACKAGE_UTIL_LINUX_LIBBLKID=y # BR2_PACKAGE_UTIL_LINUX_LIBFDISK is not set BR2_PACKAGE_UTIL_LINUX_LIBMOUNT=y # BR2_PACKAGE_UTIL_LINUX_LIBSMARTCOLS is not set BR2_PACKAGE_UTIL_LINUX_LIBUUID=y # BR2_PACKAGE_UTIL_LINUX_BINARIES is not set # BR2_PACKAGE_UTIL_LINUX_AGETTY is not set # BR2_PACKAGE_UTIL_LINUX_BFS is not set # BR2_PACKAGE_UTIL_LINUX_CAL is not set # BR2_PACKAGE_UTIL_LINUX_CHFN_CHSH is not set # BR2_PACKAGE_UTIL_LINUX_CHMEM is not set # BR2_PACKAGE_UTIL_LINUX_CRAMFS is not set # BR2_PACKAGE_UTIL_LINUX_EJECT is not set # BR2_PACKAGE_UTIL_LINUX_FALLOCATE is not set # BR2_PACKAGE_UTIL_LINUX_FDFORMAT is not set # BR2_PACKAGE_UTIL_LINUX_FSCK is not set # BR2_PACKAGE_UTIL_LINUX_HARDLINK is not set # BR2_PACKAGE_UTIL_LINUX_HWCLOCK is not set # BR2_PACKAGE_UTIL_LINUX_IPCRM is not set # BR2_PACKAGE_UTIL_LINUX_IPCS is not set # BR2_PACKAGE_UTIL_LINUX_KILL is not set # BR2_PACKAGE_UTIL_LINUX_LAST is not set # BR2_PACKAGE_UTIL_LINUX_LINE is not set # BR2_PACKAGE_UTIL_LINUX_LOGGER is not set # BR2_PACKAGE_UTIL_LINUX_LOGIN is not set # BR2_PACKAGE_UTIL_LINUX_LOSETUP is not set # BR2_PACKAGE_UTIL_LINUX_LSLOGINS is not set # BR2_PACKAGE_UTIL_LINUX_LSMEM is not set # BR2_PACKAGE_UTIL_LINUX_MESG is not set # BR2_PACKAGE_UTIL_LINUX_MINIX is not set # BR2_PACKAGE_UTIL_LINUX_MORE is not set # BR2_PACKAGE_UTIL_LINUX_MOUNT is not set # BR2_PACKAGE_UTIL_LINUX_MOUNTPOINT is not set # BR2_PACKAGE_UTIL_LINUX_NEWGRP is not set # BR2_PACKAGE_UTIL_LINUX_NOLOGIN is not set # BR2_PACKAGE_UTIL_LINUX_NSENTER is not set # BR2_PACKAGE_UTIL_LINUX_PG is not set # BR2_PACKAGE_UTIL_LINUX_PARTX is not set # BR2_PACKAGE_UTIL_LINUX_PIVOT_ROOT is not set # BR2_PACKAGE_UTIL_LINUX_RAW is not set # BR2_PACKAGE_UTIL_LINUX_RENAME is not set # BR2_PACKAGE_UTIL_LINUX_RFKILL is not set # BR2_PACKAGE_UTIL_LINUX_RUNUSER is not set # BR2_PACKAGE_UTIL_LINUX_SCHEDUTILS is not set # BR2_PACKAGE_UTIL_LINUX_SETPRIV is not set # BR2_PACKAGE_UTIL_LINUX_SETTERM is not set # BR2_PACKAGE_UTIL_LINUX_SU is not set # BR2_PACKAGE_UTIL_LINUX_SULOGIN is not set # BR2_PACKAGE_UTIL_LINUX_SWITCH_ROOT is not set # BR2_PACKAGE_UTIL_LINUX_TUNELP is not set # BR2_PACKAGE_UTIL_LINUX_UL is not set # BR2_PACKAGE_UTIL_LINUX_UNSHARE is not set # BR2_PACKAGE_UTIL_LINUX_UTMPDUMP is not set # BR2_PACKAGE_UTIL_LINUX_UUIDD is not set # BR2_PACKAGE_UTIL_LINUX_VIPW is not set # BR2_PACKAGE_UTIL_LINUX_WALL is not set # BR2_PACKAGE_UTIL_LINUX_WDCTL is not set # BR2_PACKAGE_UTIL_LINUX_WRITE is not set # BR2_PACKAGE_UTIL_LINUX_ZRAMCTL is not set # # Text editors and viewers # # BR2_PACKAGE_ED is not set # BR2_PACKAGE_JOE is not set # BR2_PACKAGE_MC is not set # BR2_PACKAGE_MOST is not set # BR2_PACKAGE_NANO is not set # BR2_PACKAGE_UEMACS is not set # # Filesystem images # # BR2_TARGET_ROOTFS_AXFS is not set # BR2_TARGET_ROOTFS_BTRFS is not set # BR2_TARGET_ROOTFS_CLOOP is not set BR2_TARGET_ROOTFS_CPIO=y BR2_TARGET_ROOTFS_CPIO_NONE=y # BR2_TARGET_ROOTFS_CPIO_GZIP is not set # BR2_TARGET_ROOTFS_CPIO_BZIP2 is not set # BR2_TARGET_ROOTFS_CPIO_LZ4 is not set # BR2_TARGET_ROOTFS_CPIO_LZMA is not set # BR2_TARGET_ROOTFS_CPIO_LZO is not set # BR2_TARGET_ROOTFS_CPIO_XZ is not set # BR2_TARGET_ROOTFS_CPIO_UIMAGE is not set # BR2_TARGET_ROOTFS_CRAMFS is not set BR2_TARGET_ROOTFS_EXT2=y BR2_TARGET_ROOTFS_EXT2_2=y # BR2_TARGET_ROOTFS_EXT2_2r0 is not set BR2_TARGET_ROOTFS_EXT2_2r1=y # BR2_TARGET_ROOTFS_EXT2_3 is not set # BR2_TARGET_ROOTFS_EXT2_4 is not set BR2_TARGET_ROOTFS_EXT2_GEN=2 BR2_TARGET_ROOTFS_EXT2_REV=1 BR2_TARGET_ROOTFS_EXT2_LABEL="" BR2_TARGET_ROOTFS_EXT2_SIZE="60M" BR2_TARGET_ROOTFS_EXT2_INODES=0 BR2_TARGET_ROOTFS_EXT2_RESBLKS=5 BR2_TARGET_ROOTFS_EXT2_MKFS_OPTIONS="-O ^64bit" BR2_TARGET_ROOTFS_EXT2_NONE=y # BR2_TARGET_ROOTFS_EXT2_GZIP is not set # BR2_TARGET_ROOTFS_EXT2_BZIP2 is not set # BR2_TARGET_ROOTFS_EXT2_LZ4 is not set # BR2_TARGET_ROOTFS_EXT2_LZMA is not set # BR2_TARGET_ROOTFS_EXT2_LZO is not set # BR2_TARGET_ROOTFS_EXT2_XZ is not set # BR2_TARGET_ROOTFS_F2FS is not set # # initramfs needs a Linux kernel to be built # # BR2_TARGET_ROOTFS_JFFS2 is not set # BR2_TARGET_ROOTFS_ROMFS is not set # BR2_TARGET_ROOTFS_SQUASHFS is not set BR2_TARGET_ROOTFS_TAR=y BR2_TARGET_ROOTFS_TAR_NONE=y # BR2_TARGET_ROOTFS_TAR_GZIP is not set # BR2_TARGET_ROOTFS_TAR_BZIP2 is not set # BR2_TARGET_ROOTFS_TAR_LZ4 is not set # BR2_TARGET_ROOTFS_TAR_LZMA is not set # BR2_TARGET_ROOTFS_TAR_LZO is not set # BR2_TARGET_ROOTFS_TAR_XZ is not set BR2_TARGET_ROOTFS_TAR_OPTIONS="" # BR2_TARGET_ROOTFS_UBI is not set # BR2_TARGET_ROOTFS_UBIFS is not set # BR2_TARGET_ROOTFS_YAFFS2 is not set # # Bootloaders # # BR2_TARGET_BAREBOX is not set # BR2_TARGET_OPENSBI is not set # # riscv-pk needs a Linux kernel to be built # # BR2_TARGET_UBOOT is not set # # Host utilities # # BR2_PACKAGE_HOST_AESPIPE is not set # BR2_PACKAGE_HOST_ANDROID_TOOLS is not set # BR2_PACKAGE_HOST_BTRFS_PROGS is not set # BR2_PACKAGE_HOST_CARGO is not set # BR2_PACKAGE_HOST_CHECKPOLICY is not set # BR2_PACKAGE_HOST_CHECKSEC is not set # BR2_PACKAGE_HOST_CMAKE is not set # BR2_PACKAGE_HOST_CRAMFS is not set # BR2_PACKAGE_HOST_CRYPTSETUP is not set # BR2_PACKAGE_HOST_DBUS_PYTHON is not set # BR2_PACKAGE_HOST_DFU_UTIL is not set # BR2_PACKAGE_HOST_DOS2UNIX is not set # BR2_PACKAGE_HOST_DOSFSTOOLS is not set # BR2_PACKAGE_HOST_DTC is not set BR2_PACKAGE_HOST_E2FSPROGS=y # BR2_PACKAGE_HOST_E2TOOLS is not set # BR2_PACKAGE_HOST_F2FS_TOOLS is not set # BR2_PACKAGE_HOST_FAKETIME is not set # BR2_PACKAGE_HOST_FATCAT is not set # BR2_PACKAGE_HOST_FWUP is not set # BR2_PACKAGE_HOST_GENEXT2FS is not set # BR2_PACKAGE_HOST_GENIMAGE is not set # BR2_PACKAGE_HOST_GENPART is not set # BR2_PACKAGE_HOST_GNUPG is not set BR2_PACKAGE_HOST_GO_HOST_ARCH_SUPPORTS=y BR2_PACKAGE_HOST_GO_BOOTSTRAP_ARCH_SUPPORTS=y BR2_PACKAGE_HOST_GOOGLE_BREAKPAD_ARCH_SUPPORTS=y # BR2_PACKAGE_HOST_GPTFDISK is not set # BR2_PACKAGE_HOST_IMAGEMAGICK is not set # BR2_PACKAGE_HOST_IMX_MKIMAGE is not set # BR2_PACKAGE_HOST_JQ is not set # BR2_PACKAGE_HOST_JSMIN is not set # BR2_PACKAGE_HOST_LIBP11 is not set # BR2_PACKAGE_HOST_LPC3250LOADER is not set # BR2_PACKAGE_HOST_LTTNG_BABELTRACE is not set # BR2_PACKAGE_HOST_MENDER_ARTIFACT is not set BR2_PACKAGE_HOST_MKPASSWD=y # BR2_PACKAGE_HOST_MTD is not set # BR2_PACKAGE_HOST_MTOOLS is not set # BR2_PACKAGE_HOST_OPENOCD is not set # BR2_PACKAGE_HOST_OPKG_UTILS is not set # BR2_PACKAGE_HOST_PARTED is not set BR2_PACKAGE_HOST_PATCHELF=y # BR2_PACKAGE_HOST_PKGCONF is not set # BR2_PACKAGE_HOST_PWGEN is not set # BR2_PACKAGE_HOST_PYTHON_CYTHON is not set # BR2_PACKAGE_HOST_PYTHON_LXML is not set # BR2_PACKAGE_HOST_PYTHON_SIX is not set # BR2_PACKAGE_HOST_PYTHON_XLRD is not set BR2_PACKAGE_HOST_QEMU_ARCH_SUPPORTS=y BR2_PACKAGE_HOST_QEMU_SYSTEM_ARCH_SUPPORTS=y BR2_PACKAGE_HOST_QEMU_USER_ARCH_SUPPORTS=y # BR2_PACKAGE_HOST_QEMU is not set # BR2_PACKAGE_HOST_RAUC is not set # BR2_PACKAGE_HOST_RCW is not set BR2_PACKAGE_HOST_RUSTC_ARCH_SUPPORTS=y BR2_PACKAGE_HOST_RUSTC_ARCH="riscv64" # BR2_PACKAGE_HOST_RUSTC is not set BR2_PACKAGE_PROVIDES_HOST_RUSTC="host-rust-bin" # BR2_PACKAGE_HOST_SAM_BA is not set # BR2_PACKAGE_HOST_SQUASHFS is not set # BR2_PACKAGE_HOST_SWIG is not set # BR2_PACKAGE_HOST_UBOOT_TOOLS is not set BR2_PACKAGE_HOST_UTIL_LINUX=y # BR2_PACKAGE_HOST_UTP_COM is not set # BR2_PACKAGE_HOST_VBOOT_UTILS is not set # BR2_PACKAGE_HOST_XORRISO is not set # BR2_PACKAGE_HOST_ZIP is not set # BR2_PACKAGE_HOST_ZSTD is not set # # Legacy config options # # # Legacy options removed in 2019.08 # # BR2_TARGET_TS4800_MBRBOOT is not set # BR2_PACKAGE_LIBAMCODEC is not set # BR2_PACKAGE_ODROID_SCRIPTS is not set # BR2_PACKAGE_ODROID_MALI is not set # BR2_PACKAGE_KODI_PLATFORM_AML is not set # BR2_GCC_VERSION_6_X is not set # BR2_GCC_VERSION_4_9_X is not set # BR2_GDB_VERSION_7_12 is not set # BR2_PACKAGE_XAPP_MKFONTDIR is not set # BR2_GDB_VERSION_8_0 is not set # BR2_KERNEL_HEADERS_4_20 is not set # BR2_KERNEL_HEADERS_5_0 is not set # # Legacy options removed in 2019.05 # # BR2_CSKY_DSP is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_COMPOSITOR is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_IQA is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_OPENCV is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_STEREO is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_VCD is not set # BR2_PACKAGE_LUNIT is not set # BR2_PACKAGE_FFMPEG_FFSERVER is not set # BR2_PACKAGE_LIBUMP is not set # BR2_PACKAGE_SUNXI_MALI is not set # BR2_BINUTILS_VERSION_2_29_X is not set # BR2_BINUTILS_VERSION_2_28_X is not set # BR2_PACKAGE_GST_PLUGINS_BAD_PLUGIN_APEXSINK is not set # # Legacy options removed in 2019.02 # # BR2_PACKAGE_QT is not set # BR2_PACKAGE_QTUIO is not set # BR2_PACKAGE_PINENTRY_QT4 is not set # BR2_PACKAGE_POPPLER_QT is not set # BR2_PACKAGE_OPENCV3_WITH_QT is not set # BR2_PACKAGE_OPENCV_WITH_QT is not set # BR2_PACKAGE_AMD_CATALYST_CCCLE is not set # BR2_PACKAGE_SDL_QTOPIA is not set # BR2_PACKAGE_PYTHON_PYQT is not set # BR2_PACKAGE_GNURADIO_QTGUI is not set # BR2_PACKAGE_LUACRYPTO is not set # BR2_PACKAGE_TN5250 is not set # BR2_PACKAGE_BOOST_SIGNALS is not set # BR2_PACKAGE_FFTW_PRECISION_SINGLE is not set # BR2_PACKAGE_FFTW_PRECISION_DOUBLE is not set # BR2_PACKAGE_FFTW_PRECISION_LONG_DOUBLE is not set # BR2_PACKAGE_LUA_5_2 is not set # BR2_TARGET_GENERIC_PASSWD_MD5 is not set # # Legacy options removed in 2018.11 # # BR2_TARGET_XLOADER is not set # BR2_PACKAGE_TIDSP_BINARIES is not set # BR2_PACKAGE_DSP_TOOLS is not set # BR2_PACKAGE_GST_DSP is not set # BR2_PACKAGE_BOOTUTILS is not set # BR2_PACKAGE_EXPEDITE is not set # BR2_PACKAGE_MESA3D_OPENGL_TEXTURE_FLOAT is not set # BR2_KERNEL_HEADERS_4_10 is not set # BR2_KERNEL_HEADERS_4_11 is not set # BR2_KERNEL_HEADERS_4_12 is not set # BR2_KERNEL_HEADERS_4_13 is not set # BR2_KERNEL_HEADERS_4_15 is not set # BR2_KERNEL_HEADERS_4_17 is not set # BR2_PACKAGE_LIBNFTNL_XML is not set # BR2_KERNEL_HEADERS_3_2 is not set # BR2_KERNEL_HEADERS_4_1 is not set # BR2_KERNEL_HEADERS_4_16 is not set # BR2_KERNEL_HEADERS_4_18 is not set # # Legacy options removed in 2018.08 # # BR2_PACKAGE_DOCKER_ENGINE_STATIC_CLIENT is not set # BR2_PACKAGE_XSERVER_XORG_SERVER_V_1_19 is not set # BR2_PACKAGE_XPROTO_APPLEWMPROTO is not set # BR2_PACKAGE_XPROTO_BIGREQSPROTO is not set # BR2_PACKAGE_XPROTO_COMPOSITEPROTO is not set # BR2_PACKAGE_XPROTO_DAMAGEPROTO is not set # BR2_PACKAGE_XPROTO_DMXPROTO is not set # BR2_PACKAGE_XPROTO_DRI2PROTO is not set # BR2_PACKAGE_XPROTO_DRI3PROTO is not set # BR2_PACKAGE_XPROTO_FIXESPROTO is not set # BR2_PACKAGE_XPROTO_FONTCACHEPROTO is not set # BR2_PACKAGE_XPROTO_FONTSPROTO is not set # BR2_PACKAGE_XPROTO_GLPROTO is not set # BR2_PACKAGE_XPROTO_INPUTPROTO is not set # BR2_PACKAGE_XPROTO_KBPROTO is not set # BR2_PACKAGE_XPROTO_PRESENTPROTO is not set # BR2_PACKAGE_XPROTO_RANDRPROTO is not set # BR2_PACKAGE_XPROTO_RECORDPROTO is not set # BR2_PACKAGE_XPROTO_RENDERPROTO is not set # BR2_PACKAGE_XPROTO_RESOURCEPROTO is not set # BR2_PACKAGE_XPROTO_SCRNSAVERPROTO is not set # BR2_PACKAGE_XPROTO_VIDEOPROTO is not set # BR2_PACKAGE_XPROTO_WINDOWSWMPROTO is not set # BR2_PACKAGE_XPROTO_XCMISCPROTO is not set # BR2_PACKAGE_XPROTO_XEXTPROTO is not set # BR2_PACKAGE_XPROTO_XF86BIGFONTPROTO is not set # BR2_PACKAGE_XPROTO_XF86DGAPROTO is not set # BR2_PACKAGE_XPROTO_XF86DRIPROTO is not set # BR2_PACKAGE_XPROTO_XF86VIDMODEPROTO is not set # BR2_PACKAGE_XPROTO_XINERAMAPROTO is not set # BR2_PACKAGE_XPROTO_XPROTO is not set # BR2_PACKAGE_XPROTO_XPROXYMANAGEMENTPROTOCOL is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_OPENGL is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_GLES2 is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_GLX is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_EGL is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_X11 is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_WAYLAND is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_LIB_OPENGL_DISPMANX is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_AUDIOMIXER is not set # BR2_PACKAGE_GST1_PLUGINS_UGLY_PLUGIN_LAME is not set # BR2_PACKAGE_GST1_PLUGINS_UGLY_PLUGIN_MPG123 is not set # BR2_GDB_VERSION_7_11 is not set # BR2_GDB_VERSION_7_10 is not set # # Legacy options removed in 2018.05 # # BR2_PACKAGE_MEDIAART_BACKEND_NONE is not set # BR2_PACKAGE_MEDIAART_BACKEND_GDK_PIXBUF is not set # BR2_PACKAGE_TI_SGX_AM335X is not set # BR2_PACKAGE_TI_SGX_AM437X is not set # BR2_PACKAGE_TI_SGX_AM4430 is not set # BR2_PACKAGE_TI_SGX_AM5430 is not set # BR2_PACKAGE_JANUS_AUDIO_BRIDGE is not set # BR2_PACKAGE_JANUS_ECHO_TEST is not set # BR2_PACKAGE_JANUS_RECORDPLAY is not set # BR2_PACKAGE_JANUS_SIP_GATEWAY is not set # BR2_PACKAGE_JANUS_STREAMING is not set # BR2_PACKAGE_JANUS_TEXT_ROOM is not set # BR2_PACKAGE_JANUS_VIDEO_CALL is not set # BR2_PACKAGE_JANUS_VIDEO_ROOM is not set # BR2_PACKAGE_JANUS_MQTT is not set # BR2_PACKAGE_JANUS_RABBITMQ is not set # BR2_PACKAGE_JANUS_REST is not set # BR2_PACKAGE_JANUS_UNIX_SOCKETS is not set # BR2_PACKAGE_JANUS_WEBSOCKETS is not set # BR2_PACKAGE_IPSEC_SECCTX_DISABLE is not set # BR2_PACKAGE_IPSEC_SECCTX_ENABLE is not set # BR2_PACKAGE_IPSEC_SECCTX_KERNEL is not set # BR2_PACKAGE_LIBTFDI_CPP is not set # BR2_PACKAGE_JQUERY_UI_THEME_BLACK_TIE is not set # BR2_PACKAGE_JQUERY_UI_THEME_BLITZER is not set # BR2_PACKAGE_JQUERY_UI_THEME_CUPERTINO is not set # BR2_PACKAGE_JQUERY_UI_THEME_DARK_HIVE is not set # BR2_PACKAGE_JQUERY_UI_THEME_DOT_LUV is not set # BR2_PACKAGE_JQUERY_UI_THEME_EGGPLANT is not set # BR2_PACKAGE_JQUERY_UI_THEME_EXCITE_BIKE is not set # BR2_PACKAGE_JQUERY_UI_THEME_FLICK is not set # BR2_PACKAGE_JQUERY_UI_THEME_HOT_SNEAKS is not set # BR2_PACKAGE_JQUERY_UI_THEME_HUMANITY is not set # BR2_PACKAGE_JQUERY_UI_THEME_LE_FROG is not set # BR2_PACKAGE_JQUERY_UI_THEME_MINT_CHOC is not set # BR2_PACKAGE_JQUERY_UI_THEME_OVERCAST is not set # BR2_PACKAGE_JQUERY_UI_THEME_PEPPER_GRINDER is not set # BR2_PACKAGE_JQUERY_UI_THEME_REDMOND is not set # BR2_PACKAGE_JQUERY_UI_THEME_SMOOTHNESS is not set # BR2_PACKAGE_JQUERY_UI_THEME_SOUTH_STREET is not set # BR2_PACKAGE_JQUERY_UI_THEME_START is not set # BR2_PACKAGE_JQUERY_UI_THEME_SUNNY is not set # BR2_PACKAGE_JQUERY_UI_THEME_SWANKY_PURSE is not set # BR2_PACKAGE_JQUERY_UI_THEME_TRONTASTIC is not set # BR2_PACKAGE_JQUERY_UI_THEME_UI_DARKNESS is not set # BR2_PACKAGE_JQUERY_UI_THEME_UI_LIGHTNESS is not set # BR2_PACKAGE_JQUERY_UI_THEME_VADER is not set # BR2_PACKAGE_BLUEZ5_PLUGINS_HEALTH is not set # BR2_PACKAGE_BLUEZ5_PLUGINS_MIDI is not set # BR2_PACKAGE_BLUEZ5_PLUGINS_NFC is not set # BR2_PACKAGE_BLUEZ5_PLUGINS_SAP is not set # BR2_PACKAGE_BLUEZ5_PLUGINS_SIXAXIS is not set # BR2_PACKAGE_TRANSMISSION_REMOTE is not set # BR2_PACKAGE_LIBKCAPI_APPS is not set # BR2_PACKAGE_MPLAYER is not set # BR2_PACKAGE_MPLAYER_MPLAYER is not set # BR2_PACKAGE_MPLAYER_MENCODER is not set # BR2_PACKAGE_LIBPLAYER_MPLAYER is not set # BR2_PACKAGE_IQVLINUX is not set # BR2_BINFMT_FLAT_SEP_DATA is not set # BR2_bfin is not set # BR2_PACKAGE_KODI_ADSP_BASIC is not set # BR2_PACKAGE_KODI_ADSP_FREESURROUND is not set # # Legacy options removed in 2018.02 # # BR2_KERNEL_HEADERS_3_4 is not set # BR2_KERNEL_HEADERS_3_10 is not set # BR2_KERNEL_HEADERS_3_12 is not set # BR2_BINUTILS_VERSION_2_27_X is not set # BR2_PACKAGE_EEPROG is not set # BR2_PACKAGE_GNUPG2_GPGV2 is not set # BR2_PACKAGE_IMX_GPU_VIV_APITRACE is not set # BR2_PACKAGE_IMX_GPU_VIV_G2D is not set # # Legacy options removed in 2017.11 # # BR2_PACKAGE_RFKILL is not set # BR2_PACKAGE_UTIL_LINUX_RESET is not set # BR2_PACKAGE_POLICYCOREUTILS_AUDIT2ALLOW is not set # BR2_PACKAGE_POLICYCOREUTILS_RESTORECOND is not set # BR2_PACKAGE_SEPOLGEN is not set # BR2_PACKAGE_OPENOBEX_BLUEZ is not set # BR2_PACKAGE_OPENOBEX_LIBUSB is not set # BR2_PACKAGE_OPENOBEX_APPS is not set # BR2_PACKAGE_OPENOBEX_SYSLOG is not set # BR2_PACKAGE_OPENOBEX_DUMP is not set # BR2_PACKAGE_AICCU is not set # BR2_PACKAGE_UTIL_LINUX_LOGIN_UTILS is not set # # Legacy options removed in 2017.08 # # BR2_TARGET_GRUB is not set # BR2_PACKAGE_SIMICSFS is not set # BR2_BINUTILS_VERSION_2_26_X is not set BR2_XTENSA_OVERLAY_DIR="" BR2_XTENSA_CUSTOM_NAME="" # BR2_PACKAGE_HOST_MKE2IMG is not set BR2_TARGET_ROOTFS_EXT2_BLOCKS=0 BR2_TARGET_ROOTFS_EXT2_EXTRA_INODES=0 # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_CDXAPARSE is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_DATAURISRC is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_DCCP is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_HDVPARSE is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_MVE is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_NUVDEMUX is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_PATCHDETECT is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_SDI is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_TTA is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_VIDEOMEASURE is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_APEXSINK is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_SDL is not set # BR2_PACKAGE_GST1_PLUGINS_UGLY_PLUGIN_MAD is not set # BR2_STRIP_none is not set # BR2_PACKAGE_BEECRYPT_CPP is not set # BR2_PACKAGE_SPICE_CLIENT is not set # BR2_PACKAGE_SPICE_GUI is not set # BR2_PACKAGE_SPICE_TUNNEL is not set # BR2_PACKAGE_INPUT_TOOLS is not set # BR2_PACKAGE_INPUT_TOOLS_INPUTATTACH is not set # BR2_PACKAGE_INPUT_TOOLS_JSCAL is not set # BR2_PACKAGE_INPUT_TOOLS_JSTEST is not set # BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_SH is not set # BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_X86 is not set # BR2_GCC_VERSION_4_8_X is not set # # Legacy options removed in 2017.05 # # BR2_PACKAGE_SUNXI_MALI_R2P4 is not set # BR2_PACKAGE_NODEJS_MODULES_COFFEESCRIPT is not set # BR2_PACKAGE_NODEJS_MODULES_EXPRESS is not set # BR2_PACKAGE_BLUEZ5_UTILS_GATTTOOL is not set # BR2_PACKAGE_OPENOCD_FT2XXX is not set # BR2_PACKAGE_KODI_RTMPDUMP is not set # BR2_PACKAGE_KODI_VISUALISATION_FOUNTAIN is not set # BR2_PACKAGE_PORTMAP is not set # BR2_BINUTILS_VERSION_2_25_X is not set # BR2_TOOLCHAIN_BUILDROOT_INET_RPC is not set BR2_TARGET_ROOTFS_EXT2_EXTRA_BLOCKS=0 # BR2_PACKAGE_SYSTEMD_KDBUS is not set # BR2_PACKAGE_POLARSSL is not set # BR2_NBD_CLIENT is not set # BR2_NBD_SERVER is not set # BR2_PACKAGE_GMOCK is not set # BR2_KERNEL_HEADERS_4_8 is not set # BR2_KERNEL_HEADERS_3_18 is not set # BR2_GLIBC_VERSION_2_22 is not set # # Legacy options removed in 2017.02 # # BR2_PACKAGE_PERL_DB_FILE is not set # BR2_KERNEL_HEADERS_4_7 is not set # BR2_KERNEL_HEADERS_4_6 is not set # BR2_KERNEL_HEADERS_4_5 is not set # BR2_KERNEL_HEADERS_3_14 is not set # BR2_TOOLCHAIN_EXTERNAL_MUSL_CROSS is not set # BR2_UCLIBC_INSTALL_TEST_SUITE is not set # BR2_TOOLCHAIN_EXTERNAL_BLACKFIN_UCLINUX is not set # BR2_PACKAGE_MAKEDEVS is not set # BR2_TOOLCHAIN_EXTERNAL_ARAGO_ARMV7A is not set # BR2_TOOLCHAIN_EXTERNAL_ARAGO_ARMV5TE is not set # BR2_PACKAGE_SNOWBALL_HDMISERVICE is not set # BR2_PACKAGE_SNOWBALL_INIT is not set # BR2_GDB_VERSION_7_9 is not set # # Legacy options removed in 2016.11 # # BR2_PACKAGE_PHP_SAPI_CLI_CGI is not set # BR2_PACKAGE_PHP_SAPI_CLI_FPM is not set # BR2_PACKAGE_WVSTREAMS is not set # BR2_PACKAGE_WVDIAL is not set # BR2_PACKAGE_WEBKITGTK24 is not set # BR2_PACKAGE_TORSMO is not set # BR2_PACKAGE_SSTRIP is not set # BR2_KERNEL_HEADERS_4_3 is not set # BR2_KERNEL_HEADERS_4_2 is not set # BR2_PACKAGE_KODI_ADDON_XVDR is not set # BR2_PACKAGE_IPKG is not set # BR2_GCC_VERSION_4_7_X is not set # BR2_BINUTILS_VERSION_2_24_X is not set # BR2_PACKAGE_WESTON_RPI is not set # BR2_GCC_VERSION_4_8_ARC is not set # BR2_KERNEL_HEADERS_4_0 is not set # BR2_KERNEL_HEADERS_3_19 is not set # BR2_PACKAGE_LIBEVAS_GENERIC_LOADERS is not set # BR2_PACKAGE_ELEMENTARY is not set # BR2_LINUX_KERNEL_CUSTOM_LOCAL is not set # # Legacy options removed in 2016.08 # # BR2_PACKAGE_EFL_JP2K is not set # BR2_PACKAGE_SYSTEMD_COMPAT is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_LIVEADDER is not set # BR2_PACKAGE_LIBFSLVPUWRAP is not set # BR2_PACKAGE_LIBFSLPARSER is not set # BR2_PACKAGE_LIBFSLCODEC is not set # BR2_PACKAGE_UBOOT_TOOLS_MKIMAGE_FIT_SIGNATURE_SUPPORT is not set # BR2_PTHREADS_OLD is not set # BR2_BINUTILS_VERSION_2_23_X is not set # BR2_TOOLCHAIN_BUILDROOT_EGLIBC is not set # BR2_GDB_VERSION_7_8 is not set # # Legacy options removed in 2016.05 # # BR2_PACKAGE_OPENVPN_CRYPTO_POLARSSL is not set # BR2_PACKAGE_NGINX_HTTP_SPDY_MODULE is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_RTP is not set # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_MPG123 is not set # BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_POWERPC is not set # BR2_TOOLCHAIN_EXTERNAL_CODESOURCERY_POWERPC_E500V2 is not set # BR2_x86_i386 is not set # BR2_PACKAGE_QT5QUICK1 is not set BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="" # BR2_PACKAGE_XDRIVER_XF86_INPUT_VOID is not set # BR2_KERNEL_HEADERS_3_17 is not set # BR2_GDB_VERSION_7_7 is not set # BR2_PACKAGE_FOOMATIC_FILTERS is not set # BR2_PACKAGE_SAMBA is not set # BR2_PACKAGE_KODI_WAVPACK is not set # BR2_PACKAGE_KODI_RSXS is not set # BR2_PACKAGE_KODI_GOOM is not set # BR2_PACKAGE_SYSTEMD_ALL_EXTRAS is not set # BR2_GCC_VERSION_4_5_X is not set # BR2_PACKAGE_SQLITE_READLINE is not set # # Legacy options removed in 2016.02 # # BR2_PACKAGE_DOVECOT_BZIP2 is not set # BR2_PACKAGE_DOVECOT_ZLIB is not set # BR2_PACKAGE_E2FSPROGS_FINDFS is not set # BR2_PACKAGE_OPENPOWERLINK_DEBUG_LEVEL is not set # BR2_PACKAGE_OPENPOWERLINK_KERNEL_MODULE is not set # BR2_PACKAGE_OPENPOWERLINK_LIBPCAP is not set # BR2_LINUX_KERNEL_SAME_AS_HEADERS is not set # BR2_PACKAGE_CUPS_PDFTOPS is not set # BR2_KERNEL_HEADERS_3_16 is not set # BR2_PACKAGE_PYTHON_PYXML is not set # BR2_ENABLE_SSP is not set # BR2_PACKAGE_DIRECTFB_CLE266 is not set # BR2_PACKAGE_DIRECTFB_UNICHROME is not set # BR2_PACKAGE_LIBELEMENTARY is not set # BR2_PACKAGE_LIBEINA is not set # BR2_PACKAGE_LIBEET is not set # BR2_PACKAGE_LIBEVAS is not set # BR2_PACKAGE_LIBECORE is not set # BR2_PACKAGE_LIBEDBUS is not set # BR2_PACKAGE_LIBEFREET is not set # BR2_PACKAGE_LIBEIO is not set # BR2_PACKAGE_LIBEMBRYO is not set # BR2_PACKAGE_LIBEDJE is not set # BR2_PACKAGE_LIBETHUMB is not set # BR2_PACKAGE_INFOZIP is not set # BR2_BR2_PACKAGE_NODEJS_0_10_X is not set # BR2_BR2_PACKAGE_NODEJS_0_12_X is not set # BR2_BR2_PACKAGE_NODEJS_4_X is not set # # Legacy options removed in 2015.11 # # BR2_PACKAGE_GST1_PLUGINS_BAD_PLUGIN_REAL is not set # BR2_PACKAGE_MEDIA_CTL is not set # BR2_PACKAGE_SCHIFRA is not set # BR2_PACKAGE_ZXING is not set # BR2_PACKAGE_BLACKBOX is not set # BR2_KERNEL_HEADERS_3_0 is not set # BR2_KERNEL_HEADERS_3_11 is not set # BR2_KERNEL_HEADERS_3_13 is not set # BR2_KERNEL_HEADERS_3_15 is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_ANDI is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_BLTLOAD is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_CPULOAD is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_DATABUFFER is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_DIOLOAD is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_DOK is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_DRIVERTEST is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_FIRE is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_FLIP is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_FONTS is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_INPUT is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_JOYSTICK is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_KNUCKLES is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_LAYER is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_MATRIX is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_MATRIX_WATER is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_NEO is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_NETLOAD is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_PALETTE is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_PARTICLE is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_PORTER is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_STRESS is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_TEXTURE is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_VIDEO is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_VIDEO_PARTICLE is not set # BR2_PACKAGE_DIRECTFB_EXAMPLES_WINDOW is not set # BR2_PACKAGE_KOBS_NG is not set # BR2_PACKAGE_SAWMAN is not set # BR2_PACKAGE_DIVINE is not set # # Legacy options removed in 2015.08 # # BR2_PACKAGE_KODI_PVR_ADDONS is not set # BR2_BINUTILS_VERSION_2_23_2 is not set # BR2_BINUTILS_VERSION_2_24 is not set # BR2_BINUTILS_VERSION_2_25 is not set # BR2_PACKAGE_PERF is not set # BR2_BINUTILS_VERSION_2_22 is not set # BR2_PACKAGE_GPU_VIV_BIN_MX6Q is not set # BR2_TARGET_UBOOT_NETWORK is not set # # Legacy options removed in 2015.05 # # BR2_TARGET_ROOTFS_JFFS2_NANDFLASH_512_16K is not set # BR2_TARGET_ROOTFS_JFFS2_NANDFLASH_2K_128K is not set # BR2_PACKAGE_MONO_20 is not set # BR2_PACKAGE_MONO_40 is not set # BR2_PACKAGE_MONO_45 is not set # BR2_CIVETWEB_WITH_LUA is not set # BR2_PACKAGE_TIFF_TIFF2PDF is not set # BR2_PACKAGE_TIFF_TIFFCP is not set # BR2_LINUX_KERNEL_EXT_RTAI_PATCH is not set # BR2_TARGET_GENERIC_PASSWD_DES is not set # BR2_PACKAGE_GTK2_THEME_HICOLOR is not set # BR2_PACKAGE_VALGRIND_PTRCHECK is not set # # Legacy options removed in 2015.02 # # BR2_PACKAGE_LIBGC is not set # BR2_PACKAGE_WDCTL is not set # BR2_PACKAGE_UTIL_LINUX_ARCH is not set # BR2_PACKAGE_UTIL_LINUX_DDATE is not set # BR2_PACKAGE_RPM_BZIP2_PAYLOADS is not set # BR2_PACKAGE_RPM_XZ_PAYLOADS is not set # BR2_PACKAGE_M4 is not set # BR2_PACKAGE_FLEX_BINARY is not set # BR2_PACKAGE_BISON is not set # BR2_PACKAGE_GOB2 is not set # BR2_PACKAGE_DISTCC is not set # BR2_PACKAGE_HASERL_VERSION_0_8_X is not set # BR2_PACKAGE_STRONGSWAN_TOOLS is not set # BR2_PACKAGE_XBMC_ADDON_XVDR is not set # BR2_PACKAGE_XBMC_PVR_ADDONS is not set # BR2_PACKAGE_XBMC is not set # BR2_PACKAGE_XBMC_ALSA_LIB is not set # BR2_PACKAGE_XBMC_AVAHI is not set # BR2_PACKAGE_XBMC_DBUS is not set # BR2_PACKAGE_XBMC_LIBBLURAY is not set # BR2_PACKAGE_XBMC_GOOM is not set # BR2_PACKAGE_XBMC_RSXS is not set # BR2_PACKAGE_XBMC_LIBCEC is not set # BR2_PACKAGE_XBMC_LIBMICROHTTPD is not set # BR2_PACKAGE_XBMC_LIBNFS is not set # BR2_PACKAGE_XBMC_RTMPDUMP is not set # BR2_PACKAGE_XBMC_LIBSHAIRPLAY is not set # BR2_PACKAGE_XBMC_LIBSMBCLIENT is not set # BR2_PACKAGE_XBMC_LIBTHEORA is not set # BR2_PACKAGE_XBMC_LIBUSB is not set # BR2_PACKAGE_XBMC_LIBVA is not set # BR2_PACKAGE_XBMC_WAVPACK is not set # BR2_PREFER_STATIC_LIB is not set # # Legacy options removed in 2014.11 # # BR2_x86_generic is not set # BR2_GCC_VERSION_4_4_X is not set # BR2_sparc_sparchfleon is not set # BR2_sparc_sparchfleonv8 is not set # BR2_sparc_sparcsfleon is not set # BR2_sparc_sparcsfleonv8 is not set # BR2_PACKAGE_LINUX_FIRMWARE_XC5000 is not set # BR2_PACKAGE_LINUX_FIRMWARE_CXGB4 is not set # BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_3160_7260_7 is not set # BR2_PACKAGE_LINUX_FIRMWARE_IWLWIFI_3160_7260_8 is not set # # Legacy options removed in 2014.08 # # BR2_PACKAGE_LIBELF is not set # BR2_KERNEL_HEADERS_3_8 is not set # BR2_PACKAGE_GETTEXT_TOOLS is not set # BR2_PACKAGE_PROCPS is not set # BR2_BINUTILS_VERSION_2_20_1 is not set # BR2_BINUTILS_VERSION_2_21 is not set # BR2_BINUTILS_VERSION_2_23_1 is not set # BR2_UCLIBC_VERSION_0_9_32 is not set # BR2_GCC_VERSION_4_3_X is not set # BR2_GCC_VERSION_4_6_X is not set # BR2_GDB_VERSION_7_4 is not set # BR2_GDB_VERSION_7_5 is not set # BR2_BUSYBOX_VERSION_1_19_X is not set # BR2_BUSYBOX_VERSION_1_20_X is not set # BR2_BUSYBOX_VERSION_1_21_X is not set # BR2_PACKAGE_LIBV4L_DECODE_TM6000 is not set # BR2_PACKAGE_LIBV4L_IR_KEYTABLE is not set # BR2_PACKAGE_LIBV4L_V4L2_COMPLIANCE is not set # BR2_PACKAGE_LIBV4L_V4L2_CTL is not set # BR2_PACKAGE_LIBV4L_V4L2_DBG is not set # # Legacy options removed in 2014.05 # # BR2_PACKAGE_EVTEST_CAPTURE is not set # BR2_KERNEL_HEADERS_3_6 is not set # BR2_KERNEL_HEADERS_3_7 is not set # BR2_PACKAGE_VALA is not set BR2_PACKAGE_TZDATA_ZONELIST="" # BR2_PACKAGE_LUA_INTERPRETER_EDITING_NONE is not set # BR2_PACKAGE_LUA_INTERPRETER_READLINE is not set # BR2_PACKAGE_LUA_INTERPRETER_LINENOISE is not set # BR2_PACKAGE_DVB_APPS_UTILS is not set # BR2_KERNEL_HEADERS_SNAP is not set # BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_UDEV is not set # BR2_PACKAGE_UDEV is not set # BR2_PACKAGE_UDEV_RULES_GEN is not set # BR2_PACKAGE_UDEV_ALL_EXTRAS is not set # # Legacy options removed in 2014.02 # # BR2_sh2 is not set # BR2_sh3 is not set # BR2_sh3eb is not set # BR2_KERNEL_HEADERS_3_1 is not set # BR2_KERNEL_HEADERS_3_3 is not set # BR2_KERNEL_HEADERS_3_5 is not set # BR2_GDB_VERSION_7_2 is not set # BR2_GDB_VERSION_7_3 is not set # BR2_PACKAGE_CCACHE is not set # BR2_HAVE_DOCUMENTATION is not set # BR2_PACKAGE_AUTOMAKE is not set # BR2_PACKAGE_AUTOCONF is not set # BR2_PACKAGE_XSTROKE is not set # BR2_PACKAGE_LZMA is not set # BR2_PACKAGE_TTCP is not set # BR2_PACKAGE_LIBNFC_LLCP is not set # BR2_PACKAGE_MYSQL_CLIENT is not set # BR2_PACKAGE_SQUASHFS3 is not set # BR2_TARGET_ROOTFS_SQUASHFS3 is not set # BR2_PACKAGE_NETKITBASE is not set # BR2_PACKAGE_NETKITTELNET is not set # BR2_PACKAGE_LUASQL is not set # BR2_PACKAGE_LUACJSON is not set # # Legacy options removed in 2013.11 # # BR2_PACKAGE_LVM2_DMSETUP_ONLY is not set # BR2_PACKAGE_QT_JAVASCRIPTCORE is not set # BR2_PACKAGE_MODULE_INIT_TOOLS is not set BR2_TARGET_UBOOT_CUSTOM_GIT_REPO_URL="" BR2_TARGET_UBOOT_CUSTOM_GIT_VERSION="" BR2_LINUX_KERNEL_CUSTOM_GIT_REPO_URL="" BR2_LINUX_KERNEL_CUSTOM_GIT_VERSION="" # # Legacy options removed in 2013.08 # # BR2_ARM_OABI is not set # BR2_PACKAGE_DOSFSTOOLS_DOSFSCK is not set # BR2_PACKAGE_DOSFSTOOLS_DOSFSLABEL is not set # BR2_PACKAGE_DOSFSTOOLS_MKDOSFS is not set # BR2_ELF2FLT is not set # BR2_VFP_FLOAT is not set # BR2_PACKAGE_GCC_TARGET is not set # BR2_HAVE_DEVFILES is not set
{ "version":1, "machine":"riscv64", "memory_size":256, "load": "/mada/users/nkabylka/ariane_pr/ariane/tb/dromajo/run/checkpoints/qsort/qs", "bios":"/mada/users/nkabylka/ariane_pr/ariane/tb/dromajo/run/checkpoints/qsort/qsort.bin", "memory_base_addr":0x80000000, "skip_commit": [0x73, 0x9002, 0x100073], "clint_base_addr": 0x02000000, "clint_size": 0xC0000, "plic_base_addr": 0x0C000000, "plic_size": 0x3FFFFFF, "uart_base_addr": 0x10000000, "uart_size": 0x1000 }
{ "version":1, "machine":"riscv64", "memory_size":256, // "load": "/mada/users/nkabylka/ariane_pr/ariane/tb/dromajo/run/checkpoints/qsort/qs", "bios":"/mada/users/nkabylka/ariane_pr/ariane/tb/dromajo/run/checkpoints/qsort/qsort.bin", "memory_base_addr":0x80000000, "missing_csrs": [0x323, 0x324, 0x325, 0x326, //mhpmevent csrs 0x327, 0x328, 0x329, 0x32a, 0x32b, 0x32c, 0x32d, 0x32e, 0x32f, 0x330, 0x331, 0x332, 0x333, 0x334, 0x335, 0x336, 0x337, 0x338, 0x339, 0x33a, 0x33b, 0x33c, 0x33d, 0x33e, 0x33f, 0x3a0, 0x3a1, 0x3a2, 0x3a3, //pmp csrs 0x3b0, 0x3b1, 0x3b2, 0x3b3, 0x3b4, 0x3b5, 0x3b6, 0x3b7, 0x3b8, 0x3b9, 0x3ba, 0x3bb, 0x3bc, 0x3bd, 0x3be, 0x3bf, 0x320], //mcountinhibit "maxinsns": 100, "clint_base_addr": 0x02000000, "clint_size": 0xC0000, "plic_base_addr": 0x0C000000, "plic_size": 0x3FFFFFF, "uart_base_addr": 0x10000000, "uart_size": 0x1000 }
/* * Misc C utilities * * Copyright (c) 2016-2017 Fabrice Bellard * Copyright (C) 2017,2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http: //www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED UNDER * THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #include <stdlib.h> #include <stdio.h> #include <string.h> #include <inttypes.h> #include <assert.h> #include <stdarg.h> #include <sys/time.h> #include <ctype.h> #include "cutils.h" void *mallocz(size_t size) { void *ptr; ptr = malloc(size); if (!ptr) return NULL; memset(ptr, 0, size); return ptr; } void pstrcpy(char *buf, int buf_size, const char *str) { int c; char *q = buf; if (buf_size <= 0) return; for (;;) { c = *str++; if (c == 0 || q >= buf + buf_size - 1) break; *q++ = c; } *q = '\0'; } char *pstrcat(char *buf, int buf_size, const char *s) { int len; len = strlen(buf); if (len < buf_size) pstrcpy(buf + len, buf_size - len, s); return buf; } int strstart(const char *str, const char *val, const char **ptr) { const char *p, *q; p = str; q = val; while (*q != '\0') { if (*p != *q) return 0; p++; q++; } if (ptr) *ptr = p; return 1; } void dbuf_init(DynBuf *s) { memset(s, 0, sizeof *s); } void dbuf_write(DynBuf *s, size_t offset, const uint8_t *data, size_t len) { size_t end, new_size; new_size = end = offset + len; if (new_size > s->allocated_size) { new_size = max_int(new_size, s->allocated_size * 3 / 2); s->buf = (uint8_t *)realloc(s->buf, new_size); s->allocated_size = new_size; } memcpy(s->buf + offset, data, len); if (end > s->size) s->size = end; } void dbuf_putc(DynBuf *s, uint8_t c) { dbuf_write(s, s->size, &c, 1); } void dbuf_putstr(DynBuf *s, const char *str) { dbuf_write(s, s->size, (const uint8_t *)str, strlen(str)); } void dbuf_free(DynBuf *s) { free(s->buf); memset(s, 0, sizeof *s); }
/* * C utilities * * Copyright (c) 2016 Fabrice Bellard * Copyright (C) 2017,2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http: //www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED UNDER * THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #ifndef CUTILS_H #define CUTILS_H #include <stdlib.h> #include <inttypes.h> #define likely(x) __builtin_expect(!!(x), 1) #define unlikely(x) __builtin_expect(!!(x), 0) #define force_inline inline __attribute__((always_inline)) #define no_inline __attribute__((noinline)) #define __maybe_unused __attribute__((unused)) #define xglue(x, y) x ## y #define glue(x, y) xglue(x, y) #define stringify(s) tostring(s) #define tostring(s) #s #ifndef offsetof #define offsetof(type, field) ((size_t) &((type *)0)->field) #endif #define countof(x) (sizeof(x) / sizeof(x[0])) #ifndef _BOOL_defined #define _BOOL_defined #undef FALSE #undef TRUE typedef int BOOL; enum { FALSE = 0, TRUE = 1, }; #endif /* this test works at least with gcc */ #if defined(__SIZEOF_INT128__) #define HAVE_INT128 #endif #ifdef HAVE_INT128 typedef __int128 int128_t; typedef unsigned __int128 uint128_t; #endif static inline int max_int(int a, int b) { if (a > b) return a; else return b; } static inline int min_int(int a, int b) { if (a < b) return a; else return b; } void *mallocz(size_t size); #if defined(__APPLE__) static inline uint32_t bswap_32(uint32_t v) { return ((v & 0xff000000) >> 24) | ((v & 0x00ff0000) >> 8) | ((v & 0x0000ff00) << 8) | ((v & 0x000000ff) << 24); } #include <sys/select.h> #else #include <byteswap.h> #endif static inline uint16_t get_le16(const uint8_t *ptr) { return ptr[0] | (ptr[1] << 8); } static inline uint32_t get_le32(const uint8_t *ptr) { return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); } static inline uint64_t get_le64(const uint8_t *ptr) { return get_le32(ptr) | ((uint64_t)get_le32(ptr + 4) << 32); } static inline void put_le16(uint8_t *ptr, uint16_t v) { ptr[0] = v; ptr[1] = v >> 8; } static inline void put_le32(uint8_t *ptr, uint32_t v) { ptr[0] = v; ptr[1] = v >> 8; ptr[2] = v >> 16; ptr[3] = v >> 24; } static inline void put_le64(uint8_t *ptr, uint64_t v) { put_le32(ptr, v); put_le32(ptr + 4, v >> 32); } static inline uint32_t get_be32(const uint8_t *d) { return (d[0] << 24) | (d[1] << 16) | (d[2] << 8) | d[3]; } static inline void put_be32(uint8_t *d, uint32_t v) { d[0] = v >> 24; d[1] = v >> 16; d[2] = v >> 8; d[3] = v >> 0; } static inline void put_be64(uint8_t *d, uint64_t v) { put_be32(d, v >> 32); put_be32(d + 4, v); } #ifdef WORDS_BIGENDIAN static inline uint32_t cpu_to_be32(uint32_t v) { return v; } #else static inline uint32_t cpu_to_be32(uint32_t v) { return bswap_32(v); } #endif static inline int ctz32(uint32_t a) { int i; if (a == 0) return 32; for (i = 0; i < 32; i++) { if ((a >> i) & 1) return i; } return 32; } void *mallocz(size_t size); void pstrcpy(char *buf, int buf_size, const char *str); char *pstrcat(char *buf, int buf_size, const char *s); int strstart(const char *str, const char *val, const char **ptr); typedef struct { uint8_t *buf; size_t size; size_t allocated_size; } DynBuf; void dbuf_init(DynBuf *s); void dbuf_write(DynBuf *s, size_t offset, const uint8_t *data, size_t len); void dbuf_putc(DynBuf *s, uint8_t c); void dbuf_putstr(DynBuf *s, const char *str); void dbuf_free(DynBuf *s); #endif /* CUTILS_H */
/* * Top-level driver * * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "dromajo.h" #include <stdlib.h> #include <stdarg.h> #include <string.h> #include <inttypes.h> #include <assert.h> #include <fcntl.h> #include <errno.h> #include <unistd.h> #include <time.h> #include <getopt.h> #include <termios.h> #include <sys/ioctl.h> #include <net/if.h> #include <sys/stat.h> #include <signal.h> #include "cutils.h" #include "iomem.h" #include "virtio.h" #include "riscv_machine.h" #include "LiveCacheCore.h" //#define REGRESS_COSIM 1 #ifdef REGRESS_COSIM #include "dromajo_cosim.h" #endif int iterate_core(RISCVMachine *m, int hartid) { if (m->common.maxinsns-- <= 0) /* Succeed after N instructions without failure. */ return 0; RISCVCPUState *cpu = m->cpu_state[hartid]; /* Instruction that raises exceptions should be marked as such in * the trace of retired instructions. */ uint64_t last_pc = virt_machine_get_pc(m, hartid); int priv = riscv_get_priv_level(cpu); uint32_t insn_raw = -1; (void) riscv_read_insn(cpu, &insn_raw, last_pc); int keep_going = virt_machine_run(m, hartid); if (last_pc == virt_machine_get_pc(m, hartid)) return 0; if (m->common.trace) { --m->common.trace; return keep_going; } fprintf(dromajo_stderr, "%d %d 0x%016" PRIx64 " (0x%08x)", hartid, priv, last_pc, (insn_raw & 3) == 3 ? insn_raw : (uint16_t) insn_raw); int iregno = riscv_get_most_recently_written_reg(cpu); int fregno = riscv_get_most_recently_written_fp_reg(cpu); if (cpu->pending_exception != -1) fprintf(dromajo_stderr, " exception %d, tval %016" PRIx64, cpu->pending_exception, riscv_get_priv_level(cpu) == PRV_M ? cpu->mtval : cpu->stval); else if (iregno > 0) fprintf(dromajo_stderr, " x%2d 0x%016" PRIx64, iregno, virt_machine_get_reg(m, hartid, iregno)); else if (fregno >= 0) fprintf(dromajo_stderr, " f%2d 0x%016" PRIx64, fregno, virt_machine_get_fpreg(m, hartid, fregno)); putc('\n', dromajo_stderr); return keep_going; } int main(int argc, char **argv) { #ifdef REGRESS_COSIM dromajo_cosim_state_t *costate = 0; costate = dromajo_cosim_init(argc, argv); if (!costate) return 1; while (!dromajo_cosim_step(costate, 0, 0, 0, 0, 0, false)); dromajo_cosim_fini(costate); #else RISCVMachine *m = virt_machine_main(argc, argv); #ifdef LIVECACHE //m->llc = new LiveCache("LLC", 1024*1024*32); // 32MB LLC (should be ~2x larger than real) m->llc = new LiveCache("LLC", 1024*32); // Small 32KB for testing #endif if (!m) return 1; int keep_going; do { keep_going = 0; for (int i = 0; i < m->ncpus; ++i) keep_going |= iterate_core(m, i); } while (keep_going); for (int i = 0; i < m->ncpus; ++i) { int benchmark_exit_code = riscv_benchmark_exit_code(m->cpu_state[i]); if (benchmark_exit_code != 0) { fprintf(dromajo_stderr, "\nBenchmark exited with code: %i \n", benchmark_exit_code); return 1; } } fprintf(dromajo_stderr, "\nPower off.\n"); virt_machine_end(m); #endif #ifdef LIVECACHE #if 0 // LiveCache Dump int addr_size; uint64_t *addr = m->llc->traverse(addr_size); for (int i = 0; i < addr_size; ++i) { printf("addr:%llx %s\n", (unsigned long long)addr[i], (addr[i] & 1) ? "ST" : "LD"); } #endif delete m->llc; #endif return 0; }
/* * Copyright (C) 2017,2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef DROMAJO_H #define DROMAJO_H #include "riscv_machine.h" #include <stdio.h> extern FILE *dromajo_stdout; extern FILE *dromajo_stderr; #endif
/* * API for Dromajo-based cosimulation * * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "dromajo.h" #include "dromajo_cosim.h" #include "cutils.h" #include "iomem.h" #include "riscv_machine.h" #include <inttypes.h> #include <stdbool.h> #include <stdio.h> #include <assert.h> /* * dromajo_cosim_init -- * * Creates and initialize the state of the RISC-V ISA golden model * Returns NULL upon failure. */ dromajo_cosim_state_t *dromajo_cosim_init(int argc, char *argv[]) { RISCVMachine *m = virt_machine_main(argc, argv); #ifdef LIVECACHE //m->llc = new LiveCache("LLC", 1024*1024*32); // 32MB LLC (should be ~2x larger than real) m->llc = new LiveCache("LLC", 1024*32); // Small 32KB for testing #endif m->common.cosim = true; m->common.pending_interrupt = -1; m->common.pending_exception = -1; return (dromajo_cosim_state_t *)m; } void dromajo_cosim_fini(dromajo_cosim_state_t *state) { virt_machine_end((RISCVMachine *)state); } static bool is_store_conditional(uint32_t insn) { int opcode = insn & 0x7f, funct3 = insn >> 12 & 7; return opcode == 0x2f && insn >> 27 == 3 && (funct3 == 2 || funct3 == 3); } static inline uint32_t get_field1(uint32_t val, int src_pos, int dst_pos, int dst_pos_max) { int mask; assert(dst_pos_max >= dst_pos); mask = ((1 << (dst_pos_max - dst_pos + 1)) - 1) << dst_pos; if (dst_pos >= src_pos) return (val << (dst_pos - src_pos)) & mask; else return (val >> (src_pos - dst_pos)) & mask; } /* detect AMO instruction, including LR, but excluding SC */ static inline bool is_amo(uint32_t insn) { int opcode = insn & 0x7f; if (opcode != 0x2f) return false; switch (insn >> 27) { case 1: /* amiswap.w */ case 2: /* lr.w */ case 0: /* amoadd.w */ case 4: /* amoxor.w */ case 0xc: /* amoand.w */ case 0x8: /* amoor.w */ case 0x10: /* amomin.w */ case 0x14: /* amomax.w */ case 0x18: /* amominu.w */ case 0x1c: /* amomaxu.w */ return true; default: return false; } } /* * is_mmio_load() -- * calculated the effective address and check if the physical backing * is MMIO space. NB: get_phys_addr() is the identity if the CPU is * running without virtual memory enabled. */ static inline bool is_mmio_load(RISCVCPUState *s, int reg, int offset, uint64_t mmio_start, uint64_t mmio_end) { uint64_t pa; uint64_t va = riscv_get_reg_previous(s, reg) + offset; if(!riscv_cpu_get_phys_addr(s, va, ACCESS_READ, &pa) && mmio_start <= pa && pa < mmio_end) { return true; } if (s->machine->mmio_addrset_size > 0) { RISCVMachine *m = s->machine; for (size_t i =0; i < m->mmio_addrset_size; ++i) { uint64_t start = m->mmio_addrset[i].start; uint64_t end = m->mmio_addrset[i].start + m->mmio_addrset[i].size; if (!riscv_cpu_get_phys_addr(s, va, ACCESS_READ, &pa) && start <= pa && pa < end) return true; } } return false; } /* * handle_dut_overrides -- * * Certain sequences cannot be simulated faithfully so this function * is responsible for detecting them and overriding the simulation * with the DUT result. Cases include interrupts, loads from MMIO * space, and certain CRSs like cycle and time. * * Right now we handle just mcycle. */ static inline void handle_dut_overrides(RISCVCPUState *s, uint64_t mmio_start, uint64_t mmio_end, int priv, uint64_t pc, uint32_t insn, uint64_t emu_wdata, uint64_t dut_wdata) { int opcode = insn & 0x7f; int csrno = insn >> 20; int rd = (insn >> 7) & 0x1f; int rdc = ((insn >> 2) & 7) + 8; int reg, offset; /* Catch reads from CSR mcycle, ucycle, instret, hpmcounters, * hpmoverflows, mip, and sip. * If the destination register is x0 then it is actually a csr-write */ if (opcode == 0x73 && rd != 0 && (0xB00 <= csrno && csrno < 0xB20 || 0xC00 <= csrno && csrno < 0xC20 || (csrno == 0x344 /* mip */ || csrno == 0x144 /* sip */))) riscv_set_reg(s, rd, dut_wdata); /* Catch loads and amo from MMIO space */ if ((opcode == 3 || is_amo(insn)) && rd != 0) { reg = (insn >> 15) & 0x1f; offset = opcode == 3 ? (int32_t) insn >> 20 : 0; } else if ((insn & 0xE003) == 0x6000 && rdc != 0) { // c.ld 011 uimm[5:3] rs1'[2:0] uimm[7:6] rd'[2:0] 00 reg = ((insn >> 7) & 7) + 8; offset = get_field1(insn, 10, 3, 5) | get_field1(insn, 5, 6, 7); rd = rdc; } else if ((insn & 0xE003) == 0x4000 && rdc != 0) { // c.lw 010 uimm[5:3] rs1'[2:0] uimm[2] uimm[6] rd'[2:0] 00 reg = ((insn >> 7) & 7) + 8; offset = (get_field1(insn, 10, 3, 5) | get_field1(insn, 6, 2, 2) | get_field1(insn, 5, 6, 6)); rd = rdc; } else return; if (is_mmio_load(s, reg, offset, mmio_start, mmio_end)) { riscv_set_reg(s, rd, dut_wdata); } } /* * dromajo_cosim_raise_trap -- * * DUT raises a trap (exception or interrupt) and provides the cause. * MSB indicates an asynchronous interrupt, synchronous exception * otherwise. */ void dromajo_cosim_raise_trap(dromajo_cosim_state_t *state, int hartid, int64_t cause) { VirtMachine *m = (VirtMachine *)state; if (cause < 0) { assert(m->pending_interrupt == -1); m->pending_interrupt = cause & 63; fprintf(dromajo_stderr, "DUT raised interrupt %d\n", m->pending_interrupt); } else { m->pending_exception = cause; } } /* * dromajo_cosim_step -- * * executes exactly one instruction in the golden model and returns * zero if the supplied expected values match and execution should * continue. A non-zero value signals termination with the exit code * being the upper bits (ie., all but LSB). Caveat: the DUT provides * the instructions bit after expansion, so this is only matched on * non-compressed instruction. * * There are a number of situations where the model cannot match the * DUT, such as loads from IO devices, interrupts, and CSRs cycle, * time, and instret. For all these cases the model will override * with the expected values. */ int dromajo_cosim_step(dromajo_cosim_state_t *state, int hartid, uint64_t dut_pc, uint32_t dut_insn, uint64_t dut_wdata, uint64_t dut_mstatus, bool check) { RISCVMachine *r = (RISCVMachine *)state; RISCVCPUState *s = r->cpu_state[hartid]; uint64_t emu_pc, emu_wdata = 0; int emu_priv; uint32_t emu_insn; bool emu_wrote_data = false; int exit_code = 0; bool verbose = true; int iregno, fregno; uint32_t tohost; bool fail = true; tohost = riscv_phys_read_u32(r->cpu_state[hartid], r->htif_tohost_addr, &fail); if (!fail && tohost & 1) { fprintf(dromajo_stderr, "Done. Cosim passed!\n\n"); return 2; } /* Succeed after N instructions without failure. */ if (r->common.maxinsns == 0) { return 1; } r->common.maxinsns--; if (riscv_terminated(s)) { return 1; } /* * Execute one instruction in the simulator. Because exceptions * may fire, the current instruction may not be executed, thus we * have to iterate until one does. */ iregno = -1; fregno = -1; for (;;) { emu_priv = riscv_get_priv_level(s); emu_pc = riscv_get_pc(s); riscv_read_insn(s, &emu_insn, emu_pc); if ((emu_insn & 3) != 3) emu_insn &= 0xFFFF; if (emu_pc == dut_pc && emu_insn == dut_insn && is_store_conditional(emu_insn) && dut_wdata != 0) { /* When DUT fails an SC, we must simulate the same behavior */ iregno = emu_insn >> 7 & 0x1f; if (iregno > 0) riscv_set_reg(s, iregno, dut_wdata); riscv_set_pc(s, emu_pc + 4); break; } if (r->common.pending_interrupt != -1 && r->common.pending_exception != -1) { /* On the DUT, the interrupt can race the exception. Let's try to match that behavior */ fprintf(dromajo_stderr, "DUT also raised exception %d\n", r->common.pending_exception); riscv_cpu_interp64(s, 1); // Advance into the exception int cause = s->priv == PRV_S ? s->scause : s->mcause; if (r->common.pending_exception != cause) { char priv = s->priv["US?M"]; /* Unfortunately, handling the error case is awkward, * so we just exit from here */ fprintf(dromajo_stderr, "%d 0x%016" PRIx64 " ", emu_priv, emu_pc); fprintf(dromajo_stderr, "(0x%08x) ", emu_insn); fprintf(dromajo_stderr, "[error] EMU %cCAUSE %d != DUT %cCAUSE %d\n", priv, cause, priv, r->common.pending_exception); return 0x1FFF; } } if (r->common.pending_interrupt != -1) riscv_cpu_set_mip(s, riscv_cpu_get_mip(s) | 1 << r->common.pending_interrupt); if (riscv_cpu_interp64(s, 1) != 0) { iregno = riscv_get_most_recently_written_reg(s); fregno = riscv_get_most_recently_written_fp_reg(s); break; } r->common.pending_interrupt = -1; r->common.pending_exception = -1; } if (check) handle_dut_overrides(s, r->mmio_start, r->mmio_end, emu_priv, emu_pc, emu_insn, emu_wdata, dut_wdata); if (verbose) { fprintf(dromajo_stderr, "%d 0x%016" PRIx64 " ", emu_priv, emu_pc); fprintf(dromajo_stderr, "(0x%08x) ", emu_insn); } if (iregno > 0) { emu_wdata = riscv_get_reg(s, iregno); emu_wrote_data = 1; if (verbose) fprintf(dromajo_stderr, "x%-2d 0x%016" PRIx64, iregno, emu_wdata); } else if (fregno >= 0) { emu_wdata = riscv_get_fpreg(s, fregno); emu_wrote_data = 1; if (verbose) fprintf(dromajo_stderr, "f%-2d 0x%016" PRIx64, fregno, emu_wdata); } else fprintf(dromajo_stderr, " "); if (verbose) fprintf(dromajo_stderr, " DASM(0x%08x)\n", emu_insn); if (!check) return 0; uint64_t emu_mstatus = riscv_cpu_get_mstatus(s); /* * Ariane does not commit ecalls and ebreaks. So we dromajo * needs to skip this one. TODO: maybe make this part of cfg */ bool skip_commit = false; for (uint64_t i = 0; i < r->skip_commit_size; i++) { if (r->skip_commit[i] == emu_insn) { skip_commit = true; break; } } if (skip_commit) { fprintf(dromajo_stderr, "skipping emu_insn 0x%08x\n", emu_insn); exit_code = 3; /* * XXX We currently do not compare mstatus because DUT's mstatus * varies between pre-commit (all FP instructions) and post-commit * (CSR instructions). */ } else if (emu_pc != dut_pc || emu_insn != dut_insn && (emu_insn & 3) == 3 || // DUT expands all C instructions emu_wdata != dut_wdata && emu_wrote_data) { fprintf(dromajo_stderr, "[error] EMU PC %016" PRIx64 ", DUT PC %016" PRIx64 "\n", emu_pc, dut_pc); fprintf(dromajo_stderr, "[error] EMU INSN %08x, DUT INSN %08x\n", emu_insn, dut_insn); if (emu_wrote_data) fprintf(dromajo_stderr, "[error] EMU WDATA %016" PRIx64 ", DUT WDATA %016" PRIx64 "\n", emu_wdata, dut_wdata); fprintf(dromajo_stderr, "[error] EMU MSTATUS %08" PRIx64 ", DUT MSTATUS %08" PRIx64 "\n", emu_mstatus, dut_mstatus); fprintf(dromajo_stderr, "[error] DUT pending exception %d pending interrupt %d\n", r->common.pending_exception, r->common.pending_interrupt); exit_code = 0x1FFF; } riscv_cpu_sync_regs(s); if (exit_code == 0 || skip_commit) riscv_cpu_sync_regs(s); return exit_code; }
/* * API for Dromajo-based cosimulation * * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef _DROMAJO_COSIM_H #define _DROMAJO_COSIM_H 1 #include <stdint.h> #include <stdbool.h> #ifdef __cplusplus extern "C" { #endif typedef struct dromajo_cosim_state_st dromajo_cosim_state_t; /* * dromajo_cosim_init -- * * Creates and initialize the state of the RISC-V ISA golden model * Returns NULL upon failure. */ dromajo_cosim_state_t *dromajo_cosim_init(int argc, char *argv[]); /* * dromajo_cosim_fini -- * * Destroys the states and releases the resources. */ void dromajo_cosim_fini(dromajo_cosim_state_t *state); /* * dromajo_cosim_step -- * * executes exactly one instruction in the golden model and returns * zero if the supplied expected values match and execution should * continue. A non-zero value signals termination with the exit code * being the upper bits (ie., all but LSB). Caveat: the DUT is * assumed to provide the instructions bit after expansion, so this is * only matched on non-compressed instruction. * * There are a number of situations where the model cannot match the * DUT, such as loads from IO devices, interrupts, and CSRs cycle, * time, and instret. For all these cases the model will override * with the expected values. */ int dromajo_cosim_step(dromajo_cosim_state_t *state, int hartid, uint64_t dut_pc, uint32_t dut_insn, uint64_t dut_wdata, uint64_t mstatus, bool check); /* * dromajo_cosim_raise_trap -- * * DUT raises a trap (exception or interrupt) and provides the cause. * MSB indicates an asynchronous interrupt, synchronous exception * otherwise. */ void dromajo_cosim_raise_trap(dromajo_cosim_state_t *state, int hartid, int64_t cause); #ifdef __cplusplus } // extern C #endif #endif
/* * Test bench for dromajo_cosim A * * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * Parse the trace output and check that we cosim correctly. */ #include "dromajo.h" #include <unistd.h> #include <stdlib.h> #include <string.h> #include "dromajo_cosim.h" void usage(char *progname) { fprintf(stderr, "Usage:\n" " %s cosim $trace $dromajoargs ...\n" " %s read $trace\n", progname, progname); exit(EXIT_FAILURE); } int main(int argc, char *argv[]) { char *progname = argv[0]; bool cosim = false; int exit_code = EXIT_SUCCESS; if (argc < 3) usage(progname); char *cmd = argv[1]; if (strcmp(cmd, "read") == 0) cosim = false; else if (strcmp(cmd, "cosim") == 0) cosim = true; else usage(progname); char *trace_name = argv[2]; FILE *f = fopen(trace_name, "r"); if (!f) { perror(trace_name); usage(progname); } dromajo_cosim_state_t *s = NULL; if (cosim) { /* Prep args for dromajo_cosim_init */ argc -= 2; argv += 2; argv[0] = progname; s = dromajo_cosim_init(argc, argv); if (!s) usage(progname); } for (int lineno = 1; !feof(f); ++lineno) { char buf[99]; uint64_t insn_addr, wdata; uint32_t insn, rd; int priv; if (!fgets(buf, sizeof buf, f)) break; int got = sscanf(buf, "%d 0x%lx (0x%x) x%d 0x%lx", &priv, &insn_addr, &insn, &rd, &wdata); switch (got) { case 3: fprintf(dromajo_stdout, "%d %016lx %08x DASM(%08x)\n", priv, insn_addr, insn, insn); break; case 5: fprintf(dromajo_stdout, "%d %016lx %08x [x%-2d <- %016lx] DASM(%08x)\n", priv, insn_addr, insn, rd, wdata, insn); break; default: fprintf(dromajo_stderr, "%s:%d: couldn't parse %s\n", trace_name, lineno, buf); goto fail; case 0: case -1: continue; } if (cosim) { int hartid = 0; // FIXME: MULTICORE cosim. Must get hartid from commit int r = dromajo_cosim_step(s, hartid, insn_addr, insn, wdata, 0, 0, 0, 0, true); if (r) { fprintf(dromajo_stdout, "Exited with %08x\n", r); goto fail; } } } done: dromajo_cosim_fini(s); if (exit_code == EXIT_SUCCESS) fprintf(dromajo_stdout, "\nSUCCESS, PASSED, GOOD!\n"); else fprintf(dromajo_stdout, "\nFAIL!\n"); if (dromajo_stdout != stdout) fclose(dromajo_stdout); exit(exit_code); fail: exit_code = EXIT_FAILURE; goto done; }
/* * Dromajo * * Copyright (c) 2016 Fabrice Bellard * Copyright (C) 2017,2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED UNDER * THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #if F_SIZE == 32 #define OPID 0 #define F_HIGH F32_HIGH #elif F_SIZE == 64 #define OPID 1 #define F_HIGH F64_HIGH #elif F_SIZE == 128 #define OPID 3 #define F_HIGH 0 #else #error unsupported F_SIZE #endif /* This template is included for each of F_SIZE=32 (single precision), F_SIZE=64 (double precision), and F_SIZE=128 (quad precision). unbox() checks that the value is corrected NaN-boxed _according to F_SIZE_. That means, that when XLEN=F_SIZE, it's a no-op, when XLEN < F_SIZE it's undefined and not used. It's only non-trivial when XLEN > F_SIZE (and the case we case the most about is XLEN=64 and F_SIZE=32. However, some of the instruction below are operating on two formats at once and care must applied to only use box() upon generic arguments (that is, values that depend on F_SIZE) */ #define unbox glue(f_unbox, F_SIZE) #define FSIGN_MASK glue(FSIGN_MASK, F_SIZE) case (0x00 << 2) | OPID: rm = get_insn_rm(s, rm); if (rm < 0) goto illegal_insn; write_fp_reg(rd, glue(add_sf, F_SIZE)(unbox(read_fp_reg(rs1)), unbox(read_fp_reg(rs2)), (RoundingModeEnum)rm, &s->fflags) | F_HIGH); s->fs = 3; break; case (0x01 << 2) | OPID: rm = get_insn_rm(s, rm); if (rm < 0) goto illegal_insn; write_fp_reg(rd, glue(sub_sf, F_SIZE)(unbox(read_fp_reg(rs1)), unbox(read_fp_reg(rs2)), (RoundingModeEnum)rm, &s->fflags) | F_HIGH); s->fs = 3; break; case (0x02 << 2) | OPID: rm = get_insn_rm(s, rm); if (rm < 0) goto illegal_insn; write_fp_reg(rd, glue(mul_sf, F_SIZE)(unbox(read_fp_reg(rs1)), unbox(read_fp_reg(rs2)), (RoundingModeEnum)rm, &s->fflags) | F_HIGH); s->fs = 3; break; case (0x03 << 2) | OPID: rm = get_insn_rm(s, rm); if (rm < 0) goto illegal_insn; write_fp_reg(rd, glue(div_sf, F_SIZE)(unbox(read_fp_reg(rs1)), unbox(read_fp_reg(rs2)), (RoundingModeEnum)rm, &s->fflags) | F_HIGH); s->fs = 3; break; case (0x0b << 2) | OPID: rm = get_insn_rm(s, rm); if (rm < 0 || rs2 != 0) goto illegal_insn; write_fp_reg(rd, glue(sqrt_sf, F_SIZE)(unbox(read_fp_reg(rs1)), (RoundingModeEnum)rm, &s->fflags) | F_HIGH); s->fs = 3; break; case (0x04 << 2) | OPID: switch (rm) { case 0: /* fsgnj */ write_fp_reg(rd, (unbox(read_fp_reg(rs1)) & ~FSIGN_MASK) | (unbox(read_fp_reg(rs2)) & FSIGN_MASK) | F_HIGH); break; case 1: /* fsgnjn */ write_fp_reg(rd, (unbox(read_fp_reg(rs1)) & ~FSIGN_MASK) | ((unbox(read_fp_reg(rs2)) & FSIGN_MASK) ^ FSIGN_MASK) | F_HIGH); break; case 2: /* fsgnjx */ write_fp_reg(rd, (unbox(read_fp_reg(rs1)) ^ (unbox(read_fp_reg(rs2)) & FSIGN_MASK)) | F_HIGH); break; default: goto illegal_insn; } s->fs = 3; break; case (0x05 << 2) | OPID: switch (rm) { case 0: /* fmin */ write_fp_reg(rd, glue(min_sf, F_SIZE)(unbox(read_fp_reg(rs1)), unbox(read_fp_reg(rs2)), &s->fflags) | F_HIGH); break; case 1: /* fmax */ write_fp_reg(rd, glue(max_sf, F_SIZE)(unbox(read_fp_reg(rs1)), unbox(read_fp_reg(rs2)), &s->fflags) | F_HIGH); break; default: goto illegal_insn; } s->fs = 3; break; case (0x18 << 2) | OPID: rm = get_insn_rm(s, rm); if (rm < 0) goto illegal_insn; switch (rs2) { case 0: /* fcvt.w.[sdq] */ val = (int32_t)glue(glue(cvt_sf, F_SIZE), _i32)(unbox(read_fp_reg(rs1)), (RoundingModeEnum)rm, &s->fflags); break; case 1: /* fcvt.wu.[sdq] */ val = (int32_t)glue(glue(cvt_sf, F_SIZE), _u32)(unbox(read_fp_reg(rs1)), (RoundingModeEnum)rm, &s->fflags); break; #if XLEN >= 64 case 2: /* fcvt.l.[sdq] */ val = (int64_t)glue(glue(cvt_sf, F_SIZE), _i64)(unbox(read_fp_reg(rs1)), (RoundingModeEnum)rm, &s->fflags); break; case 3: /* fcvt.lu.[sdq] */ val = (int64_t)glue(glue(cvt_sf, F_SIZE), _u64)(unbox(read_fp_reg(rs1)), (RoundingModeEnum)rm, &s->fflags); break; default: goto illegal_insn; } if (rd != 0) write_reg(rd, val); break; case (0x14 << 2) | OPID: switch (rm) { case 0: /* fle */ val = glue(le_sf, F_SIZE)(unbox(read_fp_reg(rs1)), unbox(read_fp_reg(rs2)), &s->fflags); break; case 1: /* flt */ val = glue(lt_sf, F_SIZE)(unbox(read_fp_reg(rs1)), unbox(read_fp_reg(rs2)), &s->fflags); break; case 2: /* feq */ val = glue(eq_quiet_sf, F_SIZE)(unbox(read_fp_reg(rs1)), unbox(read_fp_reg(rs2)), &s->fflags); break; default: goto illegal_insn; } if (rd != 0) write_reg(rd, val); break; case (0x1a << 2) | OPID: rm = get_insn_rm(s, rm); if (rm < 0) goto illegal_insn; switch (rs2) { case 0: /* fcvt.[sdq].w */ write_fp_reg(rd, glue(cvt_i32_sf, F_SIZE)(read_reg(rs1), (RoundingModeEnum)rm, &s->fflags) | F_HIGH); break; case 1: /* fcvt.[sdq].wu */ write_fp_reg(rd, glue(cvt_u32_sf, F_SIZE)(read_reg(rs1), (RoundingModeEnum)rm, &s->fflags) | F_HIGH); break; case 2: /* fcvt.[sdq].l */ write_fp_reg(rd, glue(cvt_i64_sf, F_SIZE)(read_reg(rs1), (RoundingModeEnum)rm, &s->fflags) | F_HIGH); break; case 3: /* fcvt.[sdq].lu */ write_fp_reg(rd, glue(cvt_u64_sf, F_SIZE)(read_reg(rs1), (RoundingModeEnum)rm, &s->fflags) | F_HIGH); break; #endif default: goto illegal_insn; } s->fs = 3; break; case (0x08 << 2) | OPID: rm = get_insn_rm(s, rm); if (rm < 0) goto illegal_insn; switch (rs2) { #if F_SIZE == 32 && FLEN >= 64 case 1: /* cvt.s.d */ write_fp_reg(rd, cvt_sf64_sf32(read_fp_reg(rs1), (RoundingModeEnum)rm, &s->fflags) | F32_HIGH); break; #if FLEN >= 128 case 3: /* cvt.s.q */ write_fp_reg(rd, cvt_sf128_sf32(read_fp_reg(rs1), (RoundingModeEnum)rm, &s->fflags) | F32_HIGH); break; #endif #endif /* F_SIZE == 32 */ #if F_SIZE == 64 case 0: /* cvt.d.s */ { /* Check NaN-boxing of the *explictly* 32-bit float */ fp_uint v = read_fp_reg(rs1); if ((v & F32_HIGH) != F32_HIGH) v = f_qnan32; v = cvt_sf32_sf64(v, &s->fflags) | F64_HIGH; write_fp_reg(rd, v); } break; #if FLEN >= 128 case 1: /* cvt.d.q */ write_fp_reg(rd, cvt_sf128_sf64(read_fp_reg(rs1), (RoundingModeEnum)rm, &s->fflags) | F64_HIGH); break; #endif #endif /* F_SIZE == 64 */ #if F_SIZE == 128 case 0: /* cvt.q.s */ write_fp_reg(rd, cvt_sf32_sf128(unbox(read_fp_reg(rs1)), &s->fflags)); break; case 1: /* cvt.q.d */ write_fp_reg(rd, cvt_sf64_sf128(unbox(read_fp_reg(rs1)), &s->fflags)); break; #endif /* F_SIZE == 128 */ default: goto illegal_insn; } s->fs = 3; break; case (0x1c << 2) | OPID: if (rs2 != 0) goto illegal_insn; switch (rm) { #if F_SIZE <= XLEN case 0: /* fmv.x.w */ #if F_SIZE == 32 val = (int32_t)read_fp_reg(rs1); #elif F_SIZE == 64 val = (int64_t)read_fp_reg(rs1); #else val = (int128_t)read_fp_reg(rs1); #endif break; #endif /* F_SIZE <= XLEN */ case 1: /* fclass */ val = glue(fclass_sf, F_SIZE)(unbox(read_fp_reg(rs1))); break; default: goto illegal_insn; } if (rd != 0) write_reg(rd, val); break; #if F_SIZE <= XLEN case (0x1e << 2) | OPID: /* fmv.w.x */ if (rs2 != 0 || rm != 0) goto illegal_insn; #if F_SIZE == 32 write_fp_reg(rd, (int32_t)read_reg(rs1) | F_HIGH); #elif F_SIZE == 64 write_fp_reg(rd, (int64_t)read_reg(rs1) | F_HIGH); #else write_fp_reg(rd, (int128_t)read_reg(rs1) | F_HIGH); #endif s->fs = 3; break; #endif /* F_SIZE <= XLEN */ #undef F_SIZE #undef F_HIGH #undef OPID #undef FSIGN_MASK
/* * RISCV emulator * * Copyright (c) 2016-2017 Fabrice Bellard * Copyright (C) 2017,2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #include "dromajo.h" #include <stdlib.h> #include <stdio.h> #include <stdbool.h> #include <stdarg.h> #include <string.h> #include <inttypes.h> #include <assert.h> #include <fcntl.h> #include <errno.h> #include <unistd.h> #include <time.h> #include <getopt.h> #include <termios.h> #include <sys/ioctl.h> #include <net/if.h> #ifndef __APPLE__ #include <linux/if_tun.h> #endif #include <sys/stat.h> #include <signal.h> #include <err.h> #include "cutils.h" #include "iomem.h" #include "virtio.h" #ifdef CONFIG_FS_NET #include "fs_utils.h" #include "fs_wget.h" #endif #include "riscv_machine.h" #ifdef CONFIG_SLIRP #include "slirp/libslirp.h" #endif #include "elf64.h" FILE *dromajo_stdout; FILE *dromajo_stderr; typedef struct { FILE *stdin, *out; int console_esc_state; BOOL resize_pending; } STDIODevice; static struct termios oldtty; static int old_fd0_flags; static STDIODevice *global_stdio_device; static void term_exit(void) { tcsetattr (0, TCSANOW, &oldtty); fcntl(0, F_SETFL, old_fd0_flags); } static void term_init(BOOL allow_ctrlc) { struct termios tty; memset(&tty, 0, sizeof(tty)); tcgetattr (0, &tty); oldtty = tty; old_fd0_flags = fcntl(0, F_GETFL); tty.c_iflag &= ~(IGNBRK|BRKINT|PARMRK|ISTRIP |INLCR|IGNCR|ICRNL|IXON); tty.c_oflag |= OPOST; tty.c_lflag &= ~(ECHO|ECHONL|ICANON|IEXTEN); if (!allow_ctrlc) tty.c_lflag &= ~ISIG; tty.c_cflag &= ~(CSIZE|PARENB); tty.c_cflag |= CS8; tty.c_cc[VMIN] = 1; tty.c_cc[VTIME] = 0; tcsetattr (0, TCSANOW, &tty); atexit(term_exit); } static void console_write(void *opaque, const uint8_t *buf, int len) { STDIODevice *s = (STDIODevice *)opaque; fwrite(buf, 1, len, s->out); fflush(s->out); } static int console_read(void *opaque, uint8_t *buf, int len) { STDIODevice *s = (STDIODevice *)opaque; if (len <= 0) return 0; int ret = fread(buf, len, 1, s->stdin); if (ret <= 0) return 0; int j = 0; for (int i = 0; i < ret; i++) { uint8_t ch = buf[i]; if (s->console_esc_state) { s->console_esc_state = 0; switch (ch) { case 'x': fprintf(dromajo_stderr, "Terminated\n"); exit(0); case 'h': fprintf(dromajo_stderr, "\n" "C-b h print this help\n" "C-b x exit emulator\n" "C-b C-b send C-b\n"); break; case 1: goto output_char; default: break; } } else { if (ch == 2) { // Change to work with tmux s->console_esc_state = 1; } else { output_char: buf[j++] = ch; } } } return j; } static void term_resize_handler(int sig) { if (global_stdio_device) global_stdio_device->resize_pending = TRUE; } CharacterDevice *console_init(BOOL allow_ctrlc, FILE *stdin, FILE *out) { term_init(allow_ctrlc); CharacterDevice *dev = (CharacterDevice *)mallocz(sizeof *dev); STDIODevice *s = (STDIODevice *)mallocz(sizeof *s); s->stdin = stdin; s->out = out; /* Note: the glibc does not properly tests the return value of write() in printf, so some messages on out may be lost */ fcntl(fileno(s->stdin), F_SETFL, O_NONBLOCK); s->resize_pending = TRUE; global_stdio_device = s; /* use a signal to get the host terminal resize events */ struct sigaction sig; sig.sa_handler = term_resize_handler; sigemptyset(&sig.sa_mask); sig.sa_flags = 0; sigaction(SIGWINCH, &sig, NULL); dev->opaque = s; dev->write_data = console_write; dev->read_data = console_read; return dev; } typedef enum { BF_MODE_RO, BF_MODE_RW, BF_MODE_SNAPSHOT, } BlockDeviceModeEnum; #define SECTOR_SIZE 512UL typedef struct BlockDeviceFile { FILE *f; int64_t nb_sectors; BlockDeviceModeEnum mode; uint8_t **sector_table; } BlockDeviceFile; static int64_t bf_get_sector_count(BlockDevice *bs) { BlockDeviceFile *bf = (BlockDeviceFile *)bs->opaque; return bf->nb_sectors; } //#define DUMP_BLOCK_READ static int bf_read_async(BlockDevice *bs, uint64_t sector_num, uint8_t *buf, int n, BlockDeviceCompletionFunc *cb, void *opaque) { BlockDeviceFile *bf = (BlockDeviceFile *)bs->opaque; #ifdef DUMP_BLOCK_READ { static FILE *f; if (!f) f = fopen("/tmp/read_sect.txt", "wb"); fprintf(f, "%" PRId64 " %d\n", sector_num, n); } #endif if (!bf->f) return -1; if (bf->mode == BF_MODE_SNAPSHOT) { int i; for (i = 0; i < n; i++) { if (!bf->sector_table[sector_num]) { fseek(bf->f, sector_num * SECTOR_SIZE, SEEK_SET); size_t got = fread(buf, 1, SECTOR_SIZE, bf->f); assert(got == SECTOR_SIZE); } else { memcpy(buf, bf->sector_table[sector_num], SECTOR_SIZE); } sector_num++; buf += SECTOR_SIZE; } } else { fseek(bf->f, sector_num * SECTOR_SIZE, SEEK_SET); size_t got = fread(buf, 1, n * SECTOR_SIZE, bf->f); assert(got == n * SECTOR_SIZE); } /* synchronous read */ return 0; } static int bf_write_async(BlockDevice *bs, uint64_t sector_num, const uint8_t *buf, int n, BlockDeviceCompletionFunc *cb, void *opaque) { BlockDeviceFile *bf = (BlockDeviceFile *)bs->opaque; int ret; switch (bf->mode) { case BF_MODE_RO: ret = -1; /* error */ break; case BF_MODE_RW: fseek(bf->f, sector_num * SECTOR_SIZE, SEEK_SET); fwrite(buf, 1, n * SECTOR_SIZE, bf->f); ret = 0; break; case BF_MODE_SNAPSHOT: { if ((unsigned int)(sector_num + n) > bf->nb_sectors) return -1; for (int i = 0; i < n; i++) { if (!bf->sector_table[sector_num]) { bf->sector_table[sector_num] = (uint8_t *)malloc(SECTOR_SIZE); } memcpy(bf->sector_table[sector_num], buf, SECTOR_SIZE); sector_num++; buf += SECTOR_SIZE; } ret = 0; } break; default: abort(); } return ret; } static BlockDevice *block_device_init(const char *filename, BlockDeviceModeEnum mode) { const char *mode_str; if (mode == BF_MODE_RW) { mode_str = "r+b"; } else { mode_str = "rb"; } FILE *f = fopen(filename, mode_str); if (!f) { perror(filename); exit(1); } fseek(f, 0, SEEK_END); int64_t file_size = ftello(f); BlockDevice *bs = (BlockDevice *)mallocz(sizeof *bs); BlockDeviceFile *bf = (BlockDeviceFile *)mallocz(sizeof *bf); bf->mode = mode; bf->nb_sectors = file_size / 512; bf->f = f; if (mode == BF_MODE_SNAPSHOT) { bf->sector_table = (uint8_t **)mallocz(sizeof(bf->sector_table[0]) * bf->nb_sectors); } bs->opaque = bf; bs->get_sector_count = bf_get_sector_count; bs->read_async = bf_read_async; bs->write_async = bf_write_async; return bs; } #define MAX_EXEC_CYCLE 1 #define MAX_SLEEP_TIME 10 /* in ms */ #if !defined(__APPLE__) typedef struct { int fd; BOOL select_filled; } TunState; static void tun_write_packet(EthernetDevice *net, const uint8_t *buf, int len) { TunState *s = (TunState *)net->opaque; ssize_t got = write(s->fd, buf, len); assert(got == len); } static void tun_select_fill(EthernetDevice *net, int *pfd_max, fd_set *rfds, fd_set *wfds, fd_set *efds, int *pdelay) { TunState *s = (TunState *)net->opaque; int net_fd = s->fd; s->select_filled = net->device_can_write_packet(net); if (s->select_filled) { FD_SET(net_fd, rfds); *pfd_max = max_int(*pfd_max, net_fd); } } static void tun_select_poll(EthernetDevice *net, fd_set *rfds, fd_set *wfds, fd_set *efds, int select_ret) { TunState *s = (TunState *)net->opaque; int net_fd = s->fd; uint8_t buf[2048]; int ret; if (select_ret <= 0) return; if (s->select_filled && FD_ISSET(net_fd, rfds)) { ret = read(net_fd, buf, sizeof(buf)); if (ret > 0) net->device_write_packet(net, buf, ret); } } /* configure with: # bridge configuration (connect tap0 to bridge interface br0) ip link add br0 type bridge ip tuntap add dev tap0 mode tap [user x] [group x] ip link set tap0 master br0 ip link set dev br0 up ip link set dev tap0 up # NAT configuration (eth1 is the interface connected to internet) ifconfig br0 192.168.3.1 echo 1 > /proc/sys/net/ipv4/ip_forward iptables -D FORWARD 1 iptables -t nat -A POSTROUTING -o eth1 -j MASQUERADE In the VM: ifconfig eth0 192.168.3.2 route add -net 0.0.0.0 netmask 0.0.0.0 gw 192.168.3.1 */ static EthernetDevice *tun_open(const char *ifname) { struct ifreq ifr; int fd, ret; fd = open("/dev/net/tun", O_RDWR); if (fd < 0) { fprintf(dromajo_stderr, "Error: could not open /dev/net/tun\n"); return NULL; } memset(&ifr, 0, sizeof(ifr)); ifr.ifr_flags = IFF_TAP | IFF_NO_PI; pstrcpy(ifr.ifr_name, sizeof(ifr.ifr_name), ifname); ret = ioctl(fd, TUNSETIFF, (void *) &ifr); if (ret != 0) { fprintf(dromajo_stderr, "Error: could not configure /dev/net/tun\n"); close(fd); return NULL; } fcntl(fd, F_SETFL, O_NONBLOCK); EthernetDevice *net = (EthernetDevice *)mallocz(sizeof *net); net->mac_addr[0] = 0x02; net->mac_addr[1] = 0x00; net->mac_addr[2] = 0x00; net->mac_addr[3] = 0x00; net->mac_addr[4] = 0x00; net->mac_addr[5] = 0x01; TunState *s = (TunState *)mallocz(sizeof *s); s->fd = fd; net->opaque = s; net->write_packet = tun_write_packet; net->select_fill = tun_select_fill; net->select_poll = tun_select_poll; return net; } #endif /* !__APPLE__*/ #ifdef CONFIG_SLIRP /*******************************************************/ /* slirp */ static Slirp *slirp_state; static void slirp_write_packet(EthernetDevice *net, const uint8_t *buf, int len) { Slirp *slirp_state = net->opaque; slirp_input(slirp_state, buf, len); } int slirp_can_output(void *opaque) { EthernetDevice *net = opaque; return net->device_can_write_packet(net); } void slirp_output(void *opaque, const uint8_t *pkt, int pkt_len) { EthernetDevice *net = opaque; return net->device_write_packet(net, pkt, pkt_len); } static void slirp_select_fill1(EthernetDevice *net, int *pfd_max, fd_set *rfds, fd_set *wfds, fd_set *efds, int *pdelay) { Slirp *slirp_state = net->opaque; slirp_select_fill(slirp_state, pfd_max, rfds, wfds, efds); } static void slirp_select_poll1(EthernetDevice *net, fd_set *rfds, fd_set *wfds, fd_set *efds, int select_ret) { Slirp *slirp_state = net->opaque; slirp_select_poll(slirp_state, rfds, wfds, efds, (select_ret <= 0)); } static EthernetDevice *slirp_open(void) { EthernetDevice *net; struct in_addr net_addr = { .s_addr = htonl(0x0a000200) }; /* 10.0.2.0 */ struct in_addr mask = { .s_addr = htonl(0xffffff00) }; /* 255.255.255.0 */ struct in_addr host = { .s_addr = htonl(0x0a000202) }; /* 10.0.2.2 */ struct in_addr dhcp = { .s_addr = htonl(0x0a00020f) }; /* 10.0.2.15 */ struct in_addr dns = { .s_addr = htonl(0x0a000203) }; /* 10.0.2.3 */ const char *bootfile = NULL; const char *vhostname = NULL; int restricted = 0; if (slirp_state) { fprintf(dromajo_stderr, "Only a single slirp instance is allowed\n"); return NULL; } net = mallocz(sizeof(*net)); slirp_state = slirp_init(restricted, net_addr, mask, host, vhostname, "", bootfile, dhcp, dns, net); net->mac_addr[0] = 0x02; net->mac_addr[1] = 0x00; net->mac_addr[2] = 0x00; net->mac_addr[3] = 0x00; net->mac_addr[4] = 0x00; net->mac_addr[5] = 0x01; net->opaque = slirp_state; net->write_packet = slirp_write_packet; net->select_fill = slirp_select_fill1; net->select_poll = slirp_select_poll1; return net; } #endif /* CONFIG_SLIRP */ BOOL virt_machine_run(RISCVMachine *s, int hartid) { (void) virt_machine_get_sleep_duration(s, hartid, MAX_SLEEP_TIME); riscv_cpu_interp64(s->cpu_state[hartid], 1); if (s->htif_tohost_addr) { uint32_t tohost; bool fail = true; tohost = riscv_phys_read_u32(s->cpu_state[hartid], s->htif_tohost_addr, &fail); if (!fail && tohost & 1) return false; } return !riscv_terminated(s->cpu_state[hartid]) && s->common.maxinsns > 0; } void launch_alternate_executable(char **argv) { char filename[1024]; char new_exename[64]; const char *p, *exename; int len; snprintf(new_exename, sizeof(new_exename), "dromajo64"); exename = argv[0]; p = strrchr(exename, '/'); if (p) { len = p - exename + 1; } else { len = 0; } if (len + strlen(new_exename) > sizeof(filename) - 1) { fprintf(dromajo_stderr, "%s: filename too long\n", exename); exit(1); } memcpy(filename, exename, len); filename[len] = '\0'; strcat(filename, new_exename); argv[0] = filename; if (execvp(argv[0], argv) < 0) { perror(argv[0]); exit(1); } } #ifdef CONFIG_FS_NET static BOOL net_completed; static void net_start_cb(void *arg) { net_completed = TRUE; } static BOOL net_poll_cb(void *arg) { return net_completed; } #endif static void usage(const char *prog, const char *msg) { fprintf(dromajo_stderr, "error: %s\n" CONFIG_VERSION ", Copyright (c) 2016-2017 Fabrice Bellard," " Copyright (c) 2018,2019 Esperanto Technologies\n" "usage: %s {options} [config|elf-file]\n" " --cmdline Kernel command line arguments to append\n" " --ncpus number of cpus to simulate (default 1)\n" " --load resumes a previously saved snapshot\n" " --save saves a snapshot upon exit\n" " --save_format [0(default)=bin, 1=hex]\n" " --maxinsns terminates execution after a number of instructions\n" " --terminate-event name of the validate event to terminate execution\n" " --trace start trace dump after a number of instructions. Trace disabled by default\n" " --ignore_sbi_shutdown continue simulation even upon seeing the SBI_SHUTDOWN call\n" " --dump_memories dump memories that could be used to load a cosimulation\n" " --memory_size sets the memory size in MiB (default 256 MiB)\n" " --memory_addr sets the memory start address (default 0x%lx)\n" " --bootrom load in a bootrom img file (default is dromajo bootrom)\n" " --dtb load in a dtb file (default is dromajo dtb)\n" " --compact_bootrom have dtb be directly after bootrom (default 256B after boot base)\n" " --reset_vector set reset vector (default 0x%lx)\n" " --mmio_range START:END [START,END) mmio range for cosim (overridden by config file)\n" " --plic START:SIZE set PLIC start address and size (defaults to 0x%lx:0x%lx)\n" " --clint START:SIZE set CLINT start address and size (defaults to 0x%lx:0x%lx)\n" " --custom_extension add X extension to isa\n", msg, prog, (long)BOOT_BASE_ADDR, (long)RAM_BASE_ADDR, (long)PLIC_BASE_ADDR, (long)PLIC_SIZE, (long)CLINT_BASE_ADDR, (long)CLINT_SIZE); exit(EXIT_FAILURE); } static bool load_elf_and_fake_the_config(VirtMachineParams *p, const char *path) { uint8_t *buf; int buf_len = load_file(&buf, path); if (elf64_is_riscv64(buf, buf_len)) { /* Fake the corresponding config file */ p->files[VM_FILE_BIOS].filename = strdup(path); p->files[VM_FILE_BIOS].buf = buf; p->files[VM_FILE_BIOS].len = buf_len; p->ram_size = (size_t)256 << 20; // Default to 256 MiB p->ram_base_addr = elf64_get_entrypoint(buf); elf64_find_global(buf, buf_len, "tohost", &p->htif_base_addr); return true; } free(buf); return false; } RISCVMachine *virt_machine_main(int argc, char **argv) { const char *prog = argv[0]; const char *snapshot_load_name = 0; const char *snapshot_save_name = 0; const char *path = NULL; const char *cmdline = NULL; uint32_t save_format = 0; long ncpus = 0; uint64_t maxinsns = 0; uint64_t trace = UINT64_MAX; long memory_size_override = 0; uint64_t memory_addr_override = 0; bool ignore_sbi_shutdown = false; bool dump_memories = false; const char *bootrom_name = 0; const char *dtb_name = 0; bool compact_bootrom = false; uint64_t reset_vector_override = 0; uint64_t mmio_start_override = 0; uint64_t mmio_end_override = 0; uint64_t plic_base_addr_override = 0; uint64_t plic_size_override = 0; uint64_t clint_base_addr_override = 0; uint64_t clint_size_override = 0; bool custom_extension = false; dromajo_stdout = stdout; dromajo_stderr = stderr; optind = 0; for (;;) { int option_index = 0; static struct option long_options[] = { {"cmdline", required_argument, 0, 'c' }, // CFG {"ncpus", required_argument, 0, 'n' }, // CFG {"load", required_argument, 0, 'l' }, {"save", required_argument, 0, 's' }, {"save_format", required_argument, 0, 'f' }, {"maxinsns", required_argument, 0, 'm' }, // CFG {"trace ", required_argument, 0, 't' }, {"ignore_sbi_shutdown", required_argument, 0, 'P' }, // CFG {"dump_memories", required_argument, 0, 'D' }, // CFG {"memory_size", required_argument, 0, 'M' }, // CFG {"memory_addr", required_argument, 0, 'A' }, // CFG {"bootrom", required_argument, 0, 'b' }, // CFG {"compact_bootrom", no_argument, 0, 'o' }, {"reset_vector", required_argument, 0, 'r' }, // CFG {"dtb", required_argument, 0, 'd' }, // CFG {"mmio_range", required_argument, 0, 'R' }, // CFG {"plic", required_argument, 0, 'p' }, // CFG {"clint", required_argument, 0, 'C' }, // CFG {"custom_extension", no_argument, 0, 'u' }, // CFG {0, 0, 0, 0 } }; int c = getopt_long(argc, argv, "", long_options, &option_index); if (c == -1) break; switch (c) { case 'c': if (cmdline) usage(prog, "already had a kernel command line"); cmdline = strdup(optarg); break; case 'n': if (ncpus != 0) usage(prog, "already had a ncpus set"); ncpus = atoll(optarg); break; case 'l': if (snapshot_load_name) usage(prog, "already had a snapshot to load"); snapshot_load_name = strdup(optarg); break; case 's': if (snapshot_save_name) usage(prog, "already had a snapshot to save"); snapshot_save_name = strdup(optarg); break; case 'f': if (save_format) usage(prog, "already had a save format set"); save_format = (uint32_t) atoll(optarg); break; case 'm': if (maxinsns) usage(prog, "already had a max instructions"); maxinsns = (uint64_t) atoll(optarg); break; case 't': if (trace != UINT64_MAX) usage(prog, "already had a trace set"); trace = (uint64_t) atoll(optarg); break; case 'P': ignore_sbi_shutdown = true; break; case 'D': dump_memories = true; break; case 'M': memory_size_override = atoi(optarg); break; case 'A': if (optarg[0] != '0' || optarg[1] != 'x') usage(prog, "--memory_addr expects argument to start with 0x... "); memory_addr_override = strtoll(optarg + 2, NULL, 16); break; case 'b': if (bootrom_name) usage(prog, "already had a bootrom to load"); bootrom_name = strdup(optarg); break; case 'd': if (dtb_name) usage(prog, "already had a dtb to load"); dtb_name = strdup(optarg); break; case 'o': compact_bootrom = true; break; case 'r': if (optarg[0] != '0' || optarg[1] != 'x') usage(prog, "--reset_vector expects argument to start with 0x... "); reset_vector_override = strtoll(optarg+2, NULL, 16); break; case 'R': { if (!strchr(optarg, ':')) usage(prog, "--mmio_range expects an argument like START:END"); char *mmio_start = strtok(optarg, ":"); char *mmio_end = strtok(NULL, ":"); if (mmio_start[0] != '0' || mmio_start[1] != 'x') usage(prog, "--mmio_range START address must begin with 0x..."); mmio_start_override = strtoll(mmio_start+2, NULL, 16); if (mmio_end[0] != '0' || mmio_end[1] != 'x') usage(prog, "--mmio_range END address must begin with 0x..."); mmio_end_override = strtoll(mmio_end+2, NULL, 16); } break; case 'p': { if (!strchr(optarg, ':')) usage(prog, "--plic expects an argument like START:SIZE"); char *plic_base_addr = strtok(optarg, ":"); char *plic_size = strtok(NULL, ":"); if (plic_base_addr[0] != '0' || plic_base_addr[1] != 'x') usage(prog, "--plic START address must begin with 0x..."); plic_base_addr_override = strtoll(plic_base_addr+2, NULL, 16); if (plic_size[0] != '0' || plic_size[1] != 'x') usage(prog, "--plic SIZE must begin with 0x..."); plic_size_override = strtoll(plic_size+2, NULL, 16); } break; case 'C': { if (!strchr(optarg, ':')) usage(prog, "--clint expects an argument like START:SIZE"); char *clint_base_addr = strtok(optarg, ":"); char *clint_size = strtok(NULL, ":"); if (clint_base_addr[0] != '0' || clint_base_addr[1] != 'x') usage(prog, "--clint START address must begin with 0x..."); clint_base_addr_override = strtoll(clint_base_addr+2, NULL, 16); if (clint_size[0] != '0' || clint_size[1] != 'x') usage(prog, "--clint SIZE must begin with 0x..."); clint_size_override = strtoll(clint_size+2, NULL, 16); } break; case 'u': custom_extension = true; break; default: usage(prog, "I'm not having this argument"); } } if (optind >= argc) usage(prog, "missing config file"); else path = argv[optind++]; if (optind < argc) usage(prog, "too many arguments"); assert(path); BlockDeviceModeEnum drive_mode = BF_MODE_SNAPSHOT; VirtMachineParams p_s, *p = &p_s; virt_machine_set_defaults(p); #ifdef CONFIG_FS_NET fs_wget_init(); #endif if (!load_elf_and_fake_the_config(p, path)) virt_machine_load_config_file(p, path, NULL, NULL); if (p->logfile) { FILE *log_out = fopen(p->logfile, "w"); if (!log_out) { perror(p->logfile); exit(1); } dromajo_stdout = log_out; dromajo_stderr = log_out; } #ifdef CONFIG_FS_NET fs_net_event_loop(NULL, NULL); #endif /* override some config parameters */ if (memory_addr_override) p->ram_base_addr = memory_addr_override; if (memory_size_override) p->ram_size = memory_size_override << 20; if (ncpus) p->ncpus = ncpus; if (p->ncpus>=MAX_CPUS) usage(prog, "ncpus limit reached (MAX_CPUS). Increase MAX_CPUS"); if (p->ncpus == 0) p->ncpus = 1; if (cmdline) vm_add_cmdline(p, cmdline); /* open the files & devices */ for (int i = 0; i < p->drive_count; i++) { BlockDevice *drive; char *fname; fname = get_file_path(p->cfg_filename, p->tab_drive[i].filename); #ifdef CONFIG_FS_NET if (is_url(fname)) { net_completed = FALSE; drive = block_device_init_http(fname, 128 * 1024, net_start_cb, NULL); /* wait until the drive is initialized */ fs_net_event_loop(net_poll_cb, NULL); } else #endif { drive = block_device_init(fname, drive_mode); } free(fname); p->tab_drive[i].block_dev = drive; } for (int i = 0; i < p->fs_count; i++) { FSDevice *fs; const char *path; path = p->tab_fs[i].filename; #ifdef CONFIG_FS_NET if (is_url(path)) { fs = fs_net_init(path, NULL, NULL); if (!fs) exit(1); fs_net_event_loop(NULL, NULL); } else #endif { #if defined(__APPLE__) fprintf(dromajo_stderr, "Filesystem access not supported yet\n"); exit(1); #else char *fname; fname = get_file_path(p->cfg_filename, path); fs = fs_disk_init(fname); if (!fs) { fprintf(dromajo_stderr, "%s: must be a directory\n", fname); exit(1); } free(fname); #endif } p->tab_fs[i].fs_dev = fs; } for (int i = 0; i < p->eth_count; i++) { #ifdef CONFIG_SLIRP if (!strcmp(p->tab_eth[i].driver, "user")) { p->tab_eth[i].net = slirp_open(); if (!p->tab_eth[i].net) exit(1); } else #endif #if !defined(__APPLE__) if (!strcmp(p->tab_eth[i].driver, "tap")) { p->tab_eth[i].net = tun_open(p->tab_eth[i].ifname); if (!p->tab_eth[i].net) exit(1); } else #endif { fprintf(dromajo_stderr, "Unsupported network driver '%s'\n", p->tab_eth[i].driver); exit(1); } } p->console = console_init(TRUE, stdin, dromajo_stdout); p->dump_memories = dump_memories; // Setup bootrom params if (bootrom_name) p->bootrom_name = bootrom_name; if (dtb_name) p->dtb_name = dtb_name; p->compact_bootrom = compact_bootrom; // Setup particular reset vector if (reset_vector_override) p->reset_vector = reset_vector_override; // MMIO ranges if (mmio_start_override) p->mmio_start = mmio_start_override; if (mmio_end_override) p->mmio_end = mmio_end_override; // PLIC params if (plic_base_addr_override) p->plic_base_addr = plic_base_addr_override; if (plic_size_override) p->plic_size = plic_size_override; // CLINT params if (clint_base_addr_override) p->clint_base_addr = clint_base_addr_override; if (clint_size_override) p->clint_size = clint_size_override; // ISA modifications p->custom_extension = custom_extension; RISCVMachine *s = virt_machine_init(p); if (!s) return NULL; // Overwrite the value specified in the configuration file if (snapshot_load_name) { s->common.snapshot_load_name = snapshot_load_name; } s->common.snapshot_save_name = snapshot_save_name; s->common.save_format = save_format; s->common.trace = trace; // Allow the command option argument to overwrite the value // specified in the configuration file if (maxinsns > 0) { s->common.maxinsns = maxinsns; } // If not value is specified in the configuration or the command line // then run indefinitely if (s->common.maxinsns == 0) s->common.maxinsns = UINT64_MAX; for (int i = 0; i < s->ncpus; ++i) s->cpu_state[i]->ignore_sbi_shutdown = ignore_sbi_shutdown; virt_machine_free_config(p); if (s->common.net) s->common.net->device_set_carrier(s->common.net, TRUE); if (s->common.snapshot_load_name) virt_machine_deserialize(s, s->common.snapshot_load_name); return s; }
/* * RISCV emulator * * Copyright (c) 2016 Fabrice Bellard * Copyright (C) 2017,2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Copyright (c) 2016 Fabrice Bellard * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #if XLEN == 32 #define uintx_t uint32_t #define intx_t int32_t #elif XLEN == 64 #define uintx_t uint64_t #define intx_t int64_t #elif XLEN == 128 #define uintx_t uint128_t #define intx_t int128_t #else #error unsupported XLEN #endif static inline intx_t glue(div, XLEN)(intx_t a, intx_t b) { if (b == 0) { return -1; } else if (a == ((intx_t)1 << (XLEN - 1)) && b == -1) { return a; } else { return a / b; } } static inline uintx_t glue(divu, XLEN)(uintx_t a, uintx_t b) { if (b == 0) { return -1; } else { return a / b; } } static inline intx_t glue(rem, XLEN)(intx_t a, intx_t b) { if (b == 0) { return a; } else if (a == ((intx_t)1 << (XLEN - 1)) && b == -1) { return 0; } else { return a % b; } } static inline uintx_t glue(remu, XLEN)(uintx_t a, uintx_t b) { if (b == 0) { return a; } else { return a % b; } } #if XLEN == 32 static inline uint32_t mulh32(int32_t a, int32_t b) { return ((int64_t)a * (int64_t)b) >> 32; } static inline uint32_t mulhsu32(int32_t a, uint32_t b) { return ((int64_t)a * (int64_t)b) >> 32; } static inline uint32_t mulhu32(uint32_t a, uint32_t b) { return ((int64_t)a * (int64_t)b) >> 32; } #elif XLEN == 64 && defined(HAVE_INT128) static inline uint64_t mulh64(int64_t a, int64_t b) { return ((int128_t)a * (int128_t)b) >> 64; } static inline uint64_t mulhsu64(int64_t a, uint64_t b) { return ((int128_t)a * (int128_t)b) >> 64; } static inline uint64_t mulhu64(uint64_t a, uint64_t b) { return ((int128_t)a * (int128_t)b) >> 64; } #else #if XLEN == 64 #define UHALF uint32_t #define UHALF_LEN 32 #elif XLEN == 128 #define UHALF uint64_t #define UHALF_LEN 64 #else #error unsupported XLEN #endif static uintx_t glue(mulhu, XLEN)(uintx_t a, uintx_t b) { UHALF a0, a1, b0, b1, r2, r3; uintx_t r00, r01, r10, r11, c; a0 = a; a1 = a >> UHALF_LEN; b0 = b; b1 = b >> UHALF_LEN; r00 = (uintx_t)a0 * (uintx_t)b0; r01 = (uintx_t)a0 * (uintx_t)b1; r10 = (uintx_t)a1 * (uintx_t)b0; r11 = (uintx_t)a1 * (uintx_t)b1; // r0 = r00; c = (r00 >> UHALF_LEN) + (UHALF)r01 + (UHALF)r10; // r1 = c; c = (c >> UHALF_LEN) + (r01 >> UHALF_LEN) + (r10 >> UHALF_LEN) + (UHALF)r11; r2 = c; r3 = (c >> UHALF_LEN) + (r11 >> UHALF_LEN); // *plow = ((uintx_t)r1 << UHALF_LEN) | r0; return ((uintx_t)r3 << UHALF_LEN) | r2; } #undef UHALF static inline uintx_t glue(mulh, XLEN)(intx_t a, intx_t b) { uintx_t r1; r1 = glue(mulhu, XLEN)(a, b); if (a < 0) r1 -= a; if (b < 0) r1 -= b; return r1; } static inline uintx_t glue(mulhsu, XLEN)(intx_t a, uintx_t b) { uintx_t r1; r1 = glue(mulhu, XLEN)(a, b); if (a < 0) r1 -= a; return r1; } #endif #define DUP2(F, n) F(n) F(n+1) #define DUP4(F, n) DUP2(F, n) DUP2(F, n + 2) #define DUP8(F, n) DUP4(F, n) DUP4(F, n + 4) #define DUP16(F, n) DUP8(F, n) DUP8(F, n + 8) #define DUP32(F, n) DUP16(F, n) DUP16(F, n + 16) #define C_QUADRANT(n) \ case n+(0 << 2): case n+(1 << 2): case n+(2 << 2): case n+(3 << 2): \ case n+(4 << 2): case n+(5 << 2): case n+(6 << 2): case n+(7 << 2): \ case n+(8 << 2): case n+(9 << 2): case n+(10 << 2): case n+(11 << 2): \ case n+(12 << 2): case n+(13 << 2): case n+(14 << 2): case n+(15 << 2): \ case n+(16 << 2): case n+(17 << 2): case n+(18 << 2): case n+(19 << 2): \ case n+(20 << 2): case n+(21 << 2): case n+(22 << 2): case n+(23 << 2): \ case n+(24 << 2): case n+(25 << 2): case n+(26 << 2): case n+(27 << 2): \ case n+(28 << 2): case n+(29 << 2): case n+(30 << 2): case n+(31 << 2): #define GET_PC() (target_ulong)((uintptr_t)code_ptr + code_to_pc_addend) #define GET_INSN_COUNTER() (insn_counter_addend - n_cycles) #define C_NEXT_INSN code_ptr += 2; break #define NEXT_INSN code_ptr += 4; break #define JUMP_INSN(kind) do { \ code_ptr = NULL; \ code_end = NULL; \ code_to_pc_addend = s->pc; \ s->info = kind; \ s->next_addr = s->pc; \ goto jump_insn; \ } while (0) #define chkfp32 glue(chkfp32, XLEN) static uint32_t chkfp32(target_ulong a) { if ((a & 0xFFFFFFFF00000000ULL) != 0xFFFFFFFF00000000ULL) return -1U << 22; // Not boxed => return float32 QNAN return (uint32_t) a; } /* * Table 2.1: Return-address stack prediction hints * rd rs1 rs1=rd RAS action * !x1/x5 !x1/x5 - none * !x1/x5 x1/x5 - pop * x1/x5 !x1/x5 - push * x1/x5 x1/x5 0 pop, then push * x1/x5 x1/x5 1 push */ int no_inline glue(riscv_cpu_interp, XLEN)(RISCVCPUState *s, int n_cycles); int no_inline glue(riscv_cpu_interp, XLEN)(RISCVCPUState *s, int n_cycles) { uint32_t opcode, insn, rd, rs1, rs2, funct3; int32_t imm, cond, err; target_ulong addr, val, val2; uint8_t *code_ptr, *code_end; target_ulong code_to_pc_addend; uint64_t insn_counter_addend; uint64_t insn_counter_start = s->insn_counter; #if FLEN > 0 uint32_t rs3; int32_t rm; #endif int insn_executed = 0; s->most_recently_written_reg = -1; s->most_recently_written_fp_reg = -1; s->info = ctf_nop; if (n_cycles == 0) return 0; insn_counter_addend = s->insn_counter + n_cycles; /* check pending interrupts */ if (unlikely(((s->mip & s->mie) != 0) && (s->machine->common.pending_interrupt != -1 || !s->machine->common.cosim))) { if (raise_interrupt(s)) { --insn_counter_addend; goto done_interp; } } s->pending_exception = -1; n_cycles++; /* Note: we assume NULL is represented as a zero number */ code_ptr = NULL; code_end = NULL; code_to_pc_addend = s->pc; /* we use a single execution loop to keep a simple control flow for emscripten */ for (;;) { s->pc = GET_PC(); if (unlikely(!--n_cycles)) goto the_end; ++insn_executed; /* Handled any breakpoint triggers in order (note, we * precompute the mask and pattern to lower some of the * cost). */ target_ulong t_mctl = MCONTROL_EXECUTE | (MCONTROL_U << s->priv); target_ulong t_mask = ((target_ulong)0xF << 60) | t_mctl; target_ulong t_match = ((target_ulong)0x2 << 60) | t_mctl; for (int i = 0; i < MAX_TRIGGERS; ++i) if ((s->tdata1[i] & t_mask) != t_match && s->tdata2[i] == s->pc) { --insn_counter_addend; s->pending_exception = CAUSE_BREAKPOINT; s->pending_tval = 0; raise_exception2(s, s->pending_exception, s->pending_tval); goto done_interp; } if (unlikely(code_ptr >= code_end)) { uint32_t tlb_idx; uint16_t insn_high; target_ulong addr; /* check pending interrupts */ if (unlikely(((s->mip & s->mie) != 0) && (s->machine->common.pending_interrupt != -1 || !s->machine->common.cosim))) { if (raise_interrupt(s)) { goto the_end; } } addr = s->pc; tlb_idx = (addr >> PG_SHIFT) & (TLB_SIZE - 1); if (likely(s->tlb_code[tlb_idx].vaddr == (addr & ~PG_MASK))) { /* TLB match */ uintptr_t mem_addend; mem_addend = s->tlb_code[tlb_idx].mem_addend; code_ptr = (uint8_t *)(mem_addend + (uintptr_t)addr); code_end = (uint8_t *)(mem_addend + (uintptr_t)((addr & ~PG_MASK) + PG_MASK - 1)); code_to_pc_addend = addr - (uintptr_t)code_ptr; if (unlikely(code_ptr >= code_end)) { /* instruction is potentially half way between two pages ? */ insn = *(uint16_t *)code_ptr; if ((insn & 3) == 3) { /* instruction is half way between two pages */ if (unlikely(target_read_insn_u16(s, &insn_high, addr + 2))) goto mmu_exception; insn |= insn_high << 16; } } else { insn = get_insn32(code_ptr); } } else { if (unlikely(target_read_insn_slow(s, &insn, 32, addr))) goto mmu_exception; } } else { /* fast path */ insn = get_insn32(code_ptr); } opcode = insn & 0x7f; rd = (insn >> 7) & 0x1f; rs1 = (insn >> 15) & 0x1f; rs2 = (insn >> 20) & 0x1f; switch (opcode) { C_QUADRANT(0) funct3 = (insn >> 13) & 7; rd = ((insn >> 2) & 7) | 8; switch (funct3) { case 0: /* c.addi4spn */ imm = get_field1(insn, 11, 4, 5) | get_field1(insn, 7, 6, 9) | get_field1(insn, 6, 2, 2) | get_field1(insn, 5, 3, 3); if (imm == 0) goto illegal_insn; write_reg(rd, (intx_t)(read_reg(2) + imm)); break; #if XLEN >= 128 case 1: /* c.lq */ imm = get_field1(insn, 11, 4, 5) | get_field1(insn, 10, 8, 8) | get_field1(insn, 5, 6, 7); rs1 = ((insn >> 7) & 7) | 8; addr = (intx_t)(read_reg(rs1) + imm); s->last_addr = addr; if (target_read_u128(s, &val, addr)) goto mmu_exception; write_reg(rd, val); break; #elif FLEN >= 64 case 1: /* c.fld */ { uint64_t rval; if (s->fs == 0) goto illegal_insn; imm = get_field1(insn, 10, 3, 5) | get_field1(insn, 5, 6, 7); rs1 = ((insn >> 7) & 7) | 8; addr = (intx_t)(read_reg(rs1) + imm); if (target_read_u64(s, &rval, addr)) goto mmu_exception; write_fp_reg(rd, rval | F64_HIGH); } break; #endif case 2: /* c.lw */ { uint32_t rval; imm = get_field1(insn, 10, 3, 5) | get_field1(insn, 6, 2, 2) | get_field1(insn, 5, 6, 6); rs1 = ((insn >> 7) & 7) | 8; addr = (intx_t)(read_reg(rs1) + imm); if (target_read_u32(s, &rval, addr)) goto mmu_exception; write_reg(rd, (int32_t)rval); } break; #if XLEN >= 64 case 3: /* c.ld */ { uint64_t rval; imm = get_field1(insn, 10, 3, 5) | get_field1(insn, 5, 6, 7); rs1 = ((insn >> 7) & 7) | 8; addr = (intx_t)(read_reg(rs1) + imm); if (target_read_u64(s, &rval, addr)) goto mmu_exception; write_reg(rd, (int64_t)rval); } break; #elif FLEN >= 32 case 3: /* c.flw */ { uint32_t rval; if (s->fs == 0) goto illegal_insn; imm = get_field1(insn, 10, 3, 5) | get_field1(insn, 6, 2, 2) | get_field1(insn, 5, 6, 6); rs1 = ((insn >> 7) & 7) | 8; addr = (intx_t)(read_reg(rs1) + imm); if (target_read_u32(s, &rval, addr)) goto mmu_exception; write_fp_reg(rd, rval | F32_HIGH); } break; #endif #if XLEN >= 128 case 5: /* c.sq */ imm = get_field1(insn, 11, 4, 5) | get_field1(insn, 10, 8, 8) | get_field1(insn, 5, 6, 7); rs1 = ((insn >> 7) & 7) | 8; addr = (intx_t)(read_reg(rs1) + imm); val = read_reg(rd); if (target_write_u128(s, addr, val)) goto mmu_exception; break; #elif FLEN >= 64 case 5: /* c.fsd */ if (s->fs == 0) goto illegal_insn; imm = get_field1(insn, 10, 3, 5) | get_field1(insn, 5, 6, 7); rs1 = ((insn >> 7) & 7) | 8; addr = (intx_t)(read_reg(rs1) + imm); if (target_write_u64(s, addr, read_fp_reg(rd))) goto mmu_exception; break; #endif case 6: /* c.sw */ imm = get_field1(insn, 10, 3, 5) | get_field1(insn, 6, 2, 2) | get_field1(insn, 5, 6, 6); rs1 = ((insn >> 7) & 7) | 8; addr = (intx_t)(read_reg(rs1) + imm); val = read_reg(rd); if (target_write_u32(s, addr, val)) goto mmu_exception; break; #if XLEN >= 64 case 7: /* c.sd */ imm = get_field1(insn, 10, 3, 5) | get_field1(insn, 5, 6, 7); rs1 = ((insn >> 7) & 7) | 8; addr = (intx_t)(read_reg(rs1) + imm); val = read_reg(rd); if (target_write_u64(s, addr, val)) goto mmu_exception; break; #elif FLEN >= 32 case 7: /* c.fsw */ if (s->fs == 0) goto illegal_insn; imm = get_field1(insn, 10, 3, 5) | get_field1(insn, 6, 2, 2) | get_field1(insn, 5, 6, 6); rs1 = ((insn >> 7) & 7) | 8; addr = (intx_t)(read_reg(rs1) + imm); if (target_write_u32(s, addr, read_fp_reg(rd))) goto mmu_exception; break; #endif default: goto illegal_insn; } C_NEXT_INSN; C_QUADRANT(1) funct3 = (insn >> 13) & 7; switch (funct3) { case 0: /* c.addi/c.nop */ if (rd != 0) { imm = sext(get_field1(insn, 12, 5, 5) | get_field1(insn, 2, 0, 4), 6); write_reg(rd, (intx_t)(read_reg(rd) + imm)); } break; #if XLEN == 32 case 1: /* c.jal */ imm = sext(get_field1(insn, 12, 11, 11) | get_field1(insn, 11, 4, 4) | get_field1(insn, 9, 8, 9) | get_field1(insn, 8, 10, 10) | get_field1(insn, 7, 6, 6) | get_field1(insn, 6, 7, 7) | get_field1(insn, 3, 1, 3) | get_field1(insn, 2, 5, 5), 12); write_reg(1, GET_PC() + 2); s->pc = (intx_t)(GET_PC() + imm); JUMP_INSN(ctf_taken_jump); #else case 1: /* c.addiw */ if (rd == 0) goto illegal_insn; imm = sext(get_field1(insn, 12, 5, 5) | get_field1(insn, 2, 0, 4), 6); write_reg(rd, (int32_t)(read_reg(rd) + imm)); break; #endif case 2: /* c.li */ if (rd != 0) { imm = sext(get_field1(insn, 12, 5, 5) | get_field1(insn, 2, 0, 4), 6); write_reg(rd, imm); } break; case 3: if (rd == 2) { /* c.addi16sp */ imm = sext(get_field1(insn, 12, 9, 9) | get_field1(insn, 6, 4, 4) | get_field1(insn, 5, 6, 6) | get_field1(insn, 3, 7, 8) | get_field1(insn, 2, 5, 5), 10); if (imm == 0) goto illegal_insn; write_reg(2, (intx_t)(read_reg(2) + imm)); } else if (rd != 0) { /* c.lui */ imm = sext(get_field1(insn, 12, 17, 17) | get_field1(insn, 2, 12, 16), 18); if (imm == 0) goto illegal_insn; write_reg(rd, imm); } break; case 4: funct3 = (insn >> 10) & 3; rd = ((insn >> 7) & 7) | 8; switch (funct3) { case 0: /* c.srli */ case 1: /* c.srai */ imm = get_field1(insn, 12, 5, 5) | get_field1(insn, 2, 0, 4); #if XLEN == 32 if (imm & 0x20) goto illegal_insn; #elif XLEN == 128 if (imm == 0) imm = 64; else if (imm >= 32) imm = 128 - imm; #endif if (funct3 == 0) write_reg(rd, (intx_t)((uintx_t)read_reg(rd) >> imm)); else write_reg(rd, (intx_t)read_reg(rd) >> imm); break; case 2: /* c.andi */ imm = sext(get_field1(insn, 12, 5, 5) | get_field1(insn, 2, 0, 4), 6); write_reg(rd, read_reg(rd) & imm); break; case 3: rs2 = ((insn >> 2) & 7) | 8; funct3 = ((insn >> 5) & 3) | ((insn >> (12 - 2)) & 4); switch (funct3) { case 0: /* c.sub */ write_reg(rd, (intx_t)(read_reg(rd) - read_reg(rs2))); break; case 1: /* c.xor */ write_reg(rd, read_reg(rd) ^ read_reg(rs2)); break; case 2: /* c.or */ write_reg(rd, read_reg(rd) | read_reg(rs2)); break; case 3: /* c.and */ write_reg(rd, read_reg(rd) & read_reg(rs2)); break; #if XLEN >= 64 case 4: /* c.subw */ write_reg(rd, (int32_t)(read_reg(rd) - read_reg(rs2))); break; case 5: /* c.addw */ write_reg(rd, (int32_t)(read_reg(rd) + read_reg(rs2))); break; #endif default: goto illegal_insn; } break; } break; case 5: /* c.j */ imm = sext(get_field1(insn, 12, 11, 11) | get_field1(insn, 11, 4, 4) | get_field1(insn, 9, 8, 9) | get_field1(insn, 8, 10, 10) | get_field1(insn, 7, 6, 6) | get_field1(insn, 6, 7, 7) | get_field1(insn, 3, 1, 3) | get_field1(insn, 2, 5, 5), 12); s->pc = (intx_t)(GET_PC() + imm); JUMP_INSN(ctf_taken_jump); case 6: /* c.beqz */ rs1 = ((insn >> 7) & 7) | 8; imm = sext(get_field1(insn, 12, 8, 8) | get_field1(insn, 10, 3, 4) | get_field1(insn, 5, 6, 7) | get_field1(insn, 3, 1, 2) | get_field1(insn, 2, 5, 5), 9); if (read_reg(rs1) == 0) { s->pc = (intx_t)(GET_PC() + imm); JUMP_INSN(ctf_taken_branch); } break; case 7: /* c.bnez */ rs1 = ((insn >> 7) & 7) | 8; imm = sext(get_field1(insn, 12, 8, 8) | get_field1(insn, 10, 3, 4) | get_field1(insn, 5, 6, 7) | get_field1(insn, 3, 1, 2) | get_field1(insn, 2, 5, 5), 9); if (read_reg(rs1) != 0) { s->pc = (intx_t)(GET_PC() + imm); JUMP_INSN(ctf_taken_branch); } break; default: goto illegal_insn; } C_NEXT_INSN; C_QUADRANT(2) funct3 = (insn >> 13) & 7; rs2 = (insn >> 2) & 0x1f; switch (funct3) { case 0: /* c.slli */ imm = get_field1(insn, 12, 5, 5) | rs2; #if XLEN == 32 if (imm & 0x20) goto illegal_insn; #elif XLEN == 128 if (imm == 0) imm = 64; #endif if (rd != 0) write_reg(rd, (intx_t)(read_reg(rd) << imm)); break; #if XLEN == 128 case 1: /* c.lqsp */ if (rd == 0) goto illegal_insn; imm = get_field1(insn, 12, 5, 5) | (rs2 & (1 << 4)) | get_field1(insn, 2, 6, 9); addr = (intx_t)(read_reg(2) + imm); if (target_read_u128(s, &val, addr)) goto mmu_exception; if (rd != 0) write_reg(rd, val); break; #elif FLEN >= 64 case 1: /* c.fldsp */ { uint64_t rval; if (s->fs == 0) goto illegal_insn; imm = get_field1(insn, 12, 5, 5) | (rs2 & (3 << 3)) | get_field1(insn, 2, 6, 8); addr = (intx_t)(read_reg(2) + imm); if (target_read_u64(s, &rval, addr)) goto mmu_exception; write_fp_reg(rd, rval | F64_HIGH); } break; #endif case 2: /* c.lwsp */ { uint32_t rval; if (rd == 0) goto illegal_insn; imm = get_field1(insn, 12, 5, 5) | (rs2 & (7 << 2)) | get_field1(insn, 2, 6, 7); addr = (intx_t)(read_reg(2) + imm); if (target_read_u32(s, &rval, addr)) goto mmu_exception; write_reg(rd, (int32_t)rval); } break; #if XLEN >= 64 case 3: /* c.ldsp */ { uint64_t rval; if (rd == 0) goto illegal_insn; imm = get_field1(insn, 12, 5, 5) | (rs2 & (3 << 3)) | get_field1(insn, 2, 6, 8); addr = (intx_t)(read_reg(2) + imm); if (target_read_u64(s, &rval, addr)) goto mmu_exception; write_reg(rd, (int64_t)rval); } break; #elif FLEN >= 32 case 3: /* c.flwsp */ { uint32_t rval; if (s->fs == 0) goto illegal_insn; imm = get_field1(insn, 12, 5, 5) | (rs2 & (7 << 2)) | get_field1(insn, 2, 6, 7); addr = (intx_t)(read_reg(2) + imm); if (target_read_u32(s, &rval, addr)) goto mmu_exception; write_fp_reg(rd, rval | F32_HIGH); } break; #endif case 4: if (((insn >> 12) & 1) == 0) { if (rs2 == 0) { /* c.jr */ if (rd == 0) goto illegal_insn; s->pc = read_reg(rd) & ~1; JUMP_INSN(ctf_compute_hint(0, rd)); } else { /* c.mv */ if (rd != 0) write_reg(rd, read_reg(rs2)); } } else { if (rs2 == 0) { if (rd == 0) { /* c.ebreak */ s->pending_exception = CAUSE_BREAKPOINT; s->pending_tval = 0; goto exception; } else { /* c.jalr */ val = GET_PC() + 2; s->pc = read_reg(rd) & ~1; write_reg(1, val); JUMP_INSN(ctf_compute_hint(1, rd)); } } else { if (rd != 0) write_reg(rd, (intx_t)(read_reg(rd) + read_reg(rs2))); } } break; #if XLEN == 128 case 5: /* c.sqsp */ imm = get_field1(insn, 10, 3, 5) | get_field1(insn, 7, 6, 8); addr = (intx_t)(read_reg(2) + imm); if (target_write_u128(s, addr, read_reg(rs2))) goto mmu_exception; break; #elif FLEN >= 64 case 5: /* c.fsdsp */ if (s->fs == 0) goto illegal_insn; imm = get_field1(insn, 10, 3, 5) | get_field1(insn, 7, 6, 8); addr = (intx_t)(read_reg(2) + imm); if (target_write_u64(s, addr, read_fp_reg(rs2))) goto mmu_exception; break; #endif case 6: /* c.swsp */ imm = get_field1(insn, 9, 2, 5) | get_field1(insn, 7, 6, 7); addr = (intx_t)(read_reg(2) + imm); if (target_write_u32(s, addr, read_reg(rs2))) goto mmu_exception; break; #if XLEN >= 64 case 7: /* c.sdsp */ imm = get_field1(insn, 10, 3, 5) | get_field1(insn, 7, 6, 8); addr = (intx_t)(read_reg(2) + imm); if (target_write_u64(s, addr, read_reg(rs2))) goto mmu_exception; break; #elif FLEN >= 32 case 7: /* c.swsp */ if (s->fs == 0) goto illegal_insn; imm = get_field1(insn, 9, 2, 5) | get_field1(insn, 7, 6, 7); addr = (intx_t)(read_reg(2) + imm); if (target_write_u32(s, addr, read_fp_reg(rs2))) goto mmu_exception; break; #endif default: goto illegal_insn; } C_NEXT_INSN; case 0x37: /* lui */ if (rd != 0) write_reg(rd, (int32_t)(insn & 0xfffff000)); NEXT_INSN; case 0x17: /* auipc */ if (rd != 0) write_reg(rd, (intx_t)(GET_PC() + (int32_t)(insn & 0xfffff000))); NEXT_INSN; case 0x6f: /* jal */ imm = ((insn >> (31 - 20)) & (1 << 20)) | ((insn >> (21 - 1)) & 0x7fe) | ((insn >> (20 - 11)) & (1 << 11)) | (insn & 0xff000); imm = (imm << 11) >> 11; { intx_t new_pc = (intx_t)(GET_PC() + imm); if (!(s->misa & MCPUID_C) && (new_pc & 3) != 0) { s->pending_exception = CAUSE_MISALIGNED_FETCH; s->pending_tval = 0; goto exception; } } if (rd != 0) write_reg(rd, GET_PC() + 4); s->pc = (intx_t)(GET_PC() + imm); JUMP_INSN(ctf_taken_jump); case 0x67: /* jalr */ funct3 = (insn >> 12) & 7; if (funct3 != 0) goto illegal_insn; imm = (int32_t)insn >> 20; val = GET_PC() + 4; { intx_t new_pc = (intx_t)(read_reg(rs1) + imm) & ~1; if (!(s->misa & MCPUID_C) && (new_pc & 3) != 0) { s->pending_exception = CAUSE_MISALIGNED_FETCH; s->pending_tval = 0; goto exception; } } s->pc = (intx_t)(read_reg(rs1) + imm) & ~1; if (rd != 0) write_reg(rd, val); JUMP_INSN(ctf_compute_hint(rd, rs1)); case 0x63: funct3 = (insn >> 12) & 7; switch (funct3 >> 1) { case 0: /* beq/bne */ cond = (read_reg(rs1) == read_reg(rs2)); break; case 2: /* blt/bge */ cond = ((target_long)read_reg(rs1) < (target_long)read_reg(rs2)); break; case 3: /* bltu/bgeu */ cond = (read_reg(rs1) < read_reg(rs2)); break; default: goto illegal_insn; } cond ^= (funct3 & 1); if (cond) { imm = ((insn >> (31 - 12)) & (1 << 12)) | ((insn >> (25 - 5)) & 0x7e0) | ((insn >> (8 - 1)) & 0x1e) | ((insn << (11 - 7)) & (1 << 11)); imm = (imm << 19) >> 19; intx_t new_pc = (intx_t)(GET_PC() + imm); if (!(s->misa & MCPUID_C) && (new_pc & 3) != 0) { s->pending_exception = CAUSE_MISALIGNED_FETCH; s->pending_tval = 0; goto exception; } s->pc = (intx_t)(GET_PC() + imm); JUMP_INSN(ctf_taken_branch); } NEXT_INSN; case 0x03: /* load */ funct3 = (insn >> 12) & 7; imm = (int32_t)insn >> 20; addr = read_reg(rs1) + imm; switch (funct3) { case 0: /* lb */ { uint8_t rval; if (target_read_u8(s, &rval, addr)) goto mmu_exception; val = (int8_t)rval; } break; case 1: /* lh */ { uint16_t rval; if (target_read_u16(s, &rval, addr)) goto mmu_exception; val = (int16_t)rval; } break; case 2: /* lw */ { uint32_t rval; if (target_read_u32(s, &rval, addr)) goto mmu_exception; val = (int32_t)rval; } break; case 4: /* lbu */ { uint8_t rval; if (target_read_u8(s, &rval, addr)) goto mmu_exception; val = rval; } break; case 5: /* lhu */ { uint16_t rval; if (target_read_u16(s, &rval, addr)) goto mmu_exception; val = rval; } break; #if XLEN >= 64 case 3: /* ld */ { uint64_t rval; if (target_read_u64(s, &rval, addr)) goto mmu_exception; val = (int64_t)rval; } break; case 6: /* lwu */ { uint32_t rval; if (target_read_u32(s, &rval, addr)) goto mmu_exception; val = rval; } break; #endif #if XLEN >= 128 case 7: /* ldu */ { uint64_t rval; if (target_read_u64(s, &rval, addr)) goto mmu_exception; val = rval; } break; #endif default: goto illegal_insn; } if (rd != 0) write_reg(rd, val); NEXT_INSN; case 0x23: /* store */ funct3 = (insn >> 12) & 7; imm = rd | ((insn >> (25 - 5)) & 0xfe0); imm = (imm << 20) >> 20; addr = read_reg(rs1) + imm; val = read_reg(rs2); switch (funct3) { case 0: /* sb */ if (target_write_u8(s, addr, val)) goto mmu_exception; break; case 1: /* sh */ if (target_write_u16(s, addr, val)) goto mmu_exception; break; case 2: /* sw */ if (target_write_u32(s, addr, val)) goto mmu_exception; break; #if XLEN >= 64 case 3: /* sd */ if (target_write_u64(s, addr, val)) goto mmu_exception; break; #endif #if XLEN >= 128 case 4: /* sq */ if (target_write_u128(s, addr, val)) goto mmu_exception; break; #endif default: goto illegal_insn; } NEXT_INSN; case 0x13: funct3 = (insn >> 12) & 7; imm = (int32_t)insn >> 20; switch (funct3) { case 0: /* addi */ val = (intx_t)(read_reg(rs1) + imm); break; case 1: /* slli */ if ((imm & ~(XLEN - 1)) != 0) goto illegal_insn; val = (intx_t)(read_reg(rs1) << (imm & (XLEN - 1))); break; case 2: /* slti */ val = (target_long)read_reg(rs1) < (target_long)imm; break; case 3: /* sltiu */ val = read_reg(rs1) < (target_ulong)imm; break; case 4: /* xori */ val = read_reg(rs1) ^ imm; break; case 5: /* srli/srai */ if ((imm & ~((XLEN - 1) | 0x400)) != 0) goto illegal_insn; if (imm & 0x400) val = (intx_t)read_reg(rs1) >> (imm & (XLEN - 1)); else val = (intx_t)((uintx_t)read_reg(rs1) >> (imm & (XLEN - 1))); break; case 6: /* ori */ val = read_reg(rs1) | imm; break; default: case 7: /* andi */ val = read_reg(rs1) & imm; break; } if (rd != 0) write_reg(rd, val); NEXT_INSN; #if XLEN >= 64 case 0x1b:/* OP-IMM-32 */ funct3 = (insn >> 12) & 7; imm = (int32_t)insn >> 20; val = read_reg(rs1); switch (funct3) { case 0: /* addiw */ val = (int32_t)(val + imm); break; case 1: /* slliw */ if ((imm & ~31) != 0) goto illegal_insn; val = (int32_t)(val << (imm & 31)); break; case 5: /* srliw/sraiw */ if ((imm & ~(31 | 0x400)) != 0) goto illegal_insn; if (imm & 0x400) val = (int32_t)val >> (imm & 31); else val = (int32_t)((uint32_t)val >> (imm & 31)); break; default: goto illegal_insn; } if (rd != 0) write_reg(rd, val); NEXT_INSN; #endif #if XLEN >= 128 case 0x5b: /* OP-IMM-64 */ funct3 = (insn >> 12) & 7; imm = (int32_t)insn >> 20; val = read_reg(rs1); switch (funct3) { case 0: /* addid */ val = (int64_t)(val + imm); break; case 1: /* sllid */ if ((imm & ~63) != 0) goto illegal_insn; val = (int64_t)(val << (imm & 63)); break; case 5: /* srlid/sraid */ if ((imm & ~(63 | 0x400)) != 0) goto illegal_insn; if (imm & 0x400) val = (int64_t)val >> (imm & 63); else val = (int64_t)((uint64_t)val >> (imm & 63)); break; default: goto illegal_insn; } if (rd != 0) write_reg(rd, val); NEXT_INSN; #endif case 0x33: imm = insn >> 25; val = read_reg(rs1); val2 = read_reg(rs2); if (imm == 1) { funct3 = (insn >> 12) & 7; switch (funct3) { case 0: /* mul */ val = (intx_t)((intx_t)val * (intx_t)val2); break; case 1: /* mulh */ val = (intx_t)glue(mulh, XLEN)(val, val2); break; case 2:/* mulhsu */ val = (intx_t)glue(mulhsu, XLEN)(val, val2); break; case 3:/* mulhu */ val = (intx_t)glue(mulhu, XLEN)(val, val2); break; case 4:/* div */ val = glue(div, XLEN)(val, val2); break; case 5:/* divu */ val = (intx_t)glue(divu, XLEN)(val, val2); break; case 6:/* rem */ val = glue(rem, XLEN)(val, val2); break; case 7:/* remu */ val = (intx_t)glue(remu, XLEN)(val, val2); break; default: goto illegal_insn; } } else { if (imm & ~0x20) goto illegal_insn; funct3 = ((insn >> 12) & 7) | ((insn >> (30 - 3)) & (1 << 3)); switch (funct3) { case 0: /* add */ val = (intx_t)(val + val2); break; case 0 | 8: /* sub */ val = (intx_t)(val - val2); break; case 1: /* sll */ val = (intx_t)(val << (val2 & (XLEN - 1))); break; case 2: /* slt */ val = (target_long)val < (target_long)val2; break; case 3: /* sltu */ val = val < val2; break; case 4: /* xor */ val = val ^ val2; break; case 5: /* srl */ val = (intx_t)((uintx_t)val >> (val2 & (XLEN - 1))); break; case 5 | 8: /* sra */ val = (intx_t)val >> (val2 & (XLEN - 1)); break; case 6: /* or */ val = val | val2; break; case 7: /* and */ val = val & val2; break; default: goto illegal_insn; } } if (rd != 0) write_reg(rd, val); NEXT_INSN; #if XLEN >= 64 case 0x3b: /* OP-32 */ imm = insn >> 25; val = read_reg(rs1); val2 = read_reg(rs2); if (imm == 1) { funct3 = (insn >> 12) & 7; switch (funct3) { case 0: /* mulw */ val = (int32_t)((int32_t)val * (int32_t)val2); break; case 4:/* divw */ val = div32(val, val2); break; case 5:/* divuw */ val = (int32_t)divu32(val, val2); break; case 6:/* remw */ val = rem32(val, val2); break; case 7:/* remuw */ val = (int32_t)remu32(val, val2); break; default: goto illegal_insn; } } else { if (imm & ~0x20) goto illegal_insn; funct3 = ((insn >> 12) & 7) | ((insn >> (30 - 3)) & (1 << 3)); switch (funct3) { case 0: /* addw */ val = (int32_t)(val + val2); break; case 0 | 8: /* subw */ val = (int32_t)(val - val2); break; case 1: /* sllw */ val = (int32_t)((uint32_t)val << (val2 & 31)); break; case 5: /* srlw */ val = (int32_t)((uint32_t)val >> (val2 & 31)); break; case 5 | 8: /* sraw */ val = (int32_t)val >> (val2 & 31); break; default: goto illegal_insn; } } if (rd != 0) write_reg(rd, val); NEXT_INSN; #endif #if XLEN >= 128 case 0x7b: /* OP-64 */ imm = insn >> 25; val = read_reg(rs1); val2 = read_reg(rs2); if (imm == 1) { funct3 = (insn >> 12) & 7; switch (funct3) { case 0: /* muld */ val = (int64_t)((int64_t)val * (int64_t)val2); break; case 4:/* divd */ val = div64(val, val2); break; case 5:/* divud */ val = (int64_t)divu64(val, val2); break; case 6:/* remd */ val = rem64(val, val2); break; case 7:/* remud */ val = (int64_t)remu64(val, val2); break; default: goto illegal_insn; } } else { if (imm & ~0x20) goto illegal_insn; funct3 = ((insn >> 12) & 7) | ((insn >> (30 - 3)) & (1 << 3)); switch (funct3) { case 0: /* addd */ val = (int64_t)(val + val2); break; case 0 | 8: /* subd */ val = (int64_t)(val - val2); break; case 1: /* slld */ val = (int64_t)((uint64_t)val << (val2 & 63)); break; case 5: /* srld */ val = (int64_t)((uint64_t)val >> (val2 & 63)); break; case 5 | 8: /* srad */ val = (int64_t)val >> (val2 & 63); break; default: goto illegal_insn; } } if (rd != 0) write_reg(rd, val); NEXT_INSN; #endif case 0x73: funct3 = (insn >> 12) & 7; imm = insn >> 20; if (funct3 & 4) val = rs1; else val = read_reg(rs1); funct3 &= 3; switch (funct3) { case 1: /* csrrw */ s->insn_counter = GET_INSN_COUNTER(); if (!s->stop_the_counter) { int delta = s->insn_counter - insn_counter_start; assert(delta >= 0); s->mcycle += delta; s->minstret += delta; } if (csr_read(s, &val2, imm, TRUE)) goto illegal_insn; val2 = (intx_t)val2; err = csr_write(s, imm, val); if (err == -2) goto mmu_exception; if (err < 0) goto illegal_insn; if (rd != 0) write_reg(rd, val2); insn_counter_addend = s->insn_counter + n_cycles; if (err > 0) { s->pc = GET_PC() + 4; if (err == 2) JUMP_INSN(ctf_nop); else goto done_interp; } break; case 2: /* csrrs */ case 3: /* csrrc */ s->insn_counter = GET_INSN_COUNTER(); if (!s->stop_the_counter) { int delta = s->insn_counter - insn_counter_start; assert(delta >= 0); s->mcycle += delta; s->minstret += delta; } if (csr_read(s, &val2, imm, (rs1 != 0))) goto illegal_insn; val2 = (intx_t)val2; if (rs1 != 0) { if (funct3 == 2) val = val2 | val; else val = val2 & ~val; err = csr_write(s, imm, val); if (err == -2) goto mmu_exception; if (err < 0) goto illegal_insn; } else { err = 0; } if (rd != 0) write_reg(rd, val2); if (err > 0) { s->pc = GET_PC() + 4; if (err == 2) JUMP_INSN(ctf_nop); else goto done_interp; } break; case 0: switch (imm) { case 0x000: /* ecall */ if (insn & 0x000fff80) goto illegal_insn; s->pending_exception = CAUSE_USER_ECALL + s->priv; s->pending_tval = 0; /* Intercept SBI_SHUTDOWN, that is, ecall with a7 == SBI_SHUTDOWN */ if (!s->ignore_sbi_shutdown && s->priv == PRV_M && read_reg(0x17) == SBI_SHUTDOWN) s->terminate_simulation = 1; goto exception; case 0x001: /* ebreak */ if (insn & 0x000fff80) goto illegal_insn; s->pending_exception = CAUSE_BREAKPOINT; s->pending_tval = 0; goto exception; case 0x102: /* sret */ { if (insn & 0x000fff80) goto illegal_insn; if (s->priv < PRV_S) goto illegal_insn; if (s->priv == PRV_S && s->mstatus & MSTATUS_TSR) goto illegal_insn; s->pc = GET_PC(); handle_sret(s); goto done_interp; } break; case 0x302: /* mret */ { if (insn & 0x000fff80) goto illegal_insn; if (s->priv < PRV_M) goto illegal_insn; s->pc = GET_PC(); handle_mret(s); goto done_interp; } break; case 0x7b2: /* dret */ if (!s->debug_mode) goto illegal_insn; { if (insn & 0x000fff80) goto illegal_insn; if (s->priv < PRV_M) // FIXME: It should be illegal even in M, but this is the only that we have now goto illegal_insn; s->pc = GET_PC(); handle_dret(s); goto done_interp; } break; case 0x105: /* wfi */ if (insn & 0x00007f80) goto illegal_insn; if (s->priv == PRV_U) goto illegal_insn; /* "When TW=1, if WFI is executed in S- mode, and it does not complete within an implementation-specific, bounded time limit, the WFI instruction causes an illegal instruction trap." */ if (s->priv == PRV_S && s->mstatus & MSTATUS_TW) goto illegal_insn; /* go to power down if no enabled interrupts are pending */ if (((s->mip & s->mie) == 0) && (s->machine->common.pending_interrupt == -1) || !s->machine->common.cosim) { s->power_down_flag = TRUE; s->pc = GET_PC() + 4; goto done_interp; } break; default: if ((imm >> 5) == 0x09) { /* sfence.vma */ if (insn & 0x00007f80) goto illegal_insn; if (s->priv == PRV_U) goto illegal_insn; if (s->priv == PRV_S && s->mstatus & MSTATUS_TVM) goto illegal_insn; if (rs1 == 0) { tlb_flush_all(s); } else { tlb_flush_vaddr(s, read_reg(rs1)); } /* the current code TLB may have been flushed */ s->pc = GET_PC() + 4; JUMP_INSN(ctf_nop); } else { goto illegal_insn; } break; } break; default: goto illegal_insn; } NEXT_INSN; case 0x0f: /* misc-mem */ funct3 = (insn >> 12) & 7; switch (funct3) { case 0: /* fence */ if (insn & 0xf00fff80) goto illegal_insn; break; case 1: /* fence.i */ if (insn != 0x0000100f) goto illegal_insn; break; #if XLEN >= 128 case 2: /* lq */ imm = (int32_t)insn >> 20; addr = read_reg(rs1) + imm; if (target_read_u128(s, &val, addr)) goto mmu_exception; if (rd != 0) write_reg(rd, val); break; #endif default: goto illegal_insn; } NEXT_INSN; case 0x2f: funct3 = (insn >> 12) & 7; #define OP_A(size) \ { \ uint ## size ##_t rval; \ \ addr = read_reg(rs1); \ funct3 = insn >> 27; \ switch (funct3) { \ case 2: /* lr.w */ \ if (rs2 != 0) \ goto illegal_insn; \ if (target_read_u ## size(s, &rval, addr)) \ goto mmu_exception; \ val = (int## size ## _t)rval; \ s->load_res = addr; \ break; \ \ case 3: /* sc.w */ \ \ if ((addr & (size/8 - 1)) != 0) { \ s->pending_tval = addr; \ s->pending_exception = CAUSE_MISALIGNED_STORE; \ goto mmu_exception; \ } \ \ if (s->load_res == addr) { \ if (target_write_u ## size(s, addr, read_reg(rs2))) \ goto mmu_exception; \ val = 0; \ s->load_res = ~0; \ } else { \ val = 1; \ } \ break; \ case 1: /* amiswap.w */ \ case 0: /* amoadd.w */ \ case 4: /* amoxor.w */ \ case 0xc: /* amoand.w */ \ case 0x8: /* amoor.w */ \ case 0x10: /* amomin.w */ \ case 0x14: /* amomax.w */ \ case 0x18: /* amominu.w */ \ case 0x1c: /* amomaxu.w */ \ if (target_read_u ## size(s, &rval, addr)) { \ s->pending_exception += 2; /* LD -> ST */ \ goto mmu_exception; \ } \ val = (int## size ## _t)rval; \ val2 = read_reg(rs2); \ switch (funct3) { \ case 1: /* amiswap.w */ \ break; \ case 0: /* amoadd.w */ \ val2 = (int## size ## _t)(val + val2); \ break; \ case 4: /* amoxor.w */ \ val2 = (int## size ## _t)(val ^ val2); \ break; \ case 0xc: /* amoand.w */ \ val2 = (int## size ## _t)(val & val2); \ break; \ case 0x8: /* amoor.w */ \ val2 = (int## size ## _t)(val | val2); \ break; \ case 0x10: /* amomin.w */ \ if ((int## size ## _t)val < (int## size ## _t)val2) \ val2 = (int## size ## _t)val; \ break; \ case 0x14: /* amomax.w */ \ if ((int## size ## _t)val > (int## size ## _t)val2) \ val2 = (int## size ## _t)val; \ break; \ case 0x18: /* amominu.w */ \ if ((uint## size ## _t)val < (uint## size ## _t)val2) \ val2 = (int## size ## _t)val; \ break; \ case 0x1c: /* amomaxu.w */ \ if ((uint## size ## _t)val > (uint## size ## _t)val2) \ val2 = (int## size ## _t)val; \ break; \ default: \ goto illegal_insn; \ } \ if (target_write_u ## size(s, addr, val2)) \ goto mmu_exception; \ break; \ default: \ goto illegal_insn; \ } \ } switch (funct3) { case 2: OP_A(32); break; #if XLEN >= 64 case 3: OP_A(64); break; #endif #if XLEN >= 128 case 4: OP_A(128); break; #endif default: goto illegal_insn; } if (rd != 0) write_reg(rd, val); NEXT_INSN; #if FLEN > 0 /* FPU */ case 0x07: /* fp load */ if (s->fs == 0) goto illegal_insn; funct3 = (insn >> 12) & 7; imm = (int32_t)insn >> 20; addr = read_reg(rs1) + imm; switch (funct3) { case 2: /* flw */ { uint32_t rval; if (target_read_u32(s, &rval, addr)) goto mmu_exception; write_fp_reg(rd, rval | F32_HIGH); } break; #if FLEN >= 64 case 3: /* fld */ { uint64_t rval; if (target_read_u64(s, &rval, addr)) goto mmu_exception; write_fp_reg(rd, rval | F64_HIGH); } break; #endif #if FLEN >= 128 case 4: /* flq */ { uint128_t rval; if (target_read_u128(s, &rval, addr)) goto mmu_exception; write_fp_reg(rd, rval); } break; #endif default: goto illegal_insn; } NEXT_INSN; case 0x27: /* fp store */ if (s->fs == 0) goto illegal_insn; funct3 = (insn >> 12) & 7; imm = rd | ((insn >> (25 - 5)) & 0xfe0); imm = (imm << 20) >> 20; addr = read_reg(rs1) + imm; switch (funct3) { case 2: /* fsw */ if (target_write_u32(s, addr, read_fp_reg(rs2))) goto mmu_exception; break; #if FLEN >= 64 case 3: /* fsd */ if (target_write_u64(s, addr, read_fp_reg(rs2))) goto mmu_exception; break; #endif #if FLEN >= 128 case 4: /* fsq */ if (target_write_u128(s, addr, read_fp_reg(rs2))) goto mmu_exception; break; #endif default: goto illegal_insn; } NEXT_INSN; case 0x43: /* fmadd */ if (s->fs == 0) goto illegal_insn; funct3 = (insn >> 25) & 3; rs3 = insn >> 27; rm = get_insn_rm(s, (insn >> 12) & 7); if (rm < 0) goto illegal_insn; switch (funct3) { case 0: write_fp_reg(rd, (fp_uint)fma_sf32(chkfp32(read_fp_reg(rs1)), chkfp32(read_fp_reg(rs2)), chkfp32(read_fp_reg(rs3)), (RoundingModeEnum)rm, &s->fflags) | F32_HIGH); break; #if FLEN >= 64 case 1: write_fp_reg(rd, (fp_uint)fma_sf64(read_fp_reg(rs1), read_fp_reg(rs2), read_fp_reg(rs3), (RoundingModeEnum)rm, &s->fflags) | F64_HIGH); break; #endif #if FLEN >= 128 case 3: write_fp_reg(rd, (fp_uint)fma_sf128(read_fp_reg(rs1), read_fp_reg(rs2), read_fp_reg(rs3), (RoundingModeEnum)rm, &s->fflags));; #endif default: goto illegal_insn; } NEXT_INSN; case 0x47: /* fmsub */ if (s->fs == 0) goto illegal_insn; funct3 = (insn >> 25) & 3; rs3 = insn >> 27; rm = get_insn_rm(s, (insn >> 12) & 7); if (rm < 0) goto illegal_insn; switch (funct3) { case 0: write_fp_reg(rd, fma_sf32(chkfp32(read_fp_reg(rs1)), chkfp32(read_fp_reg(rs2)), chkfp32(read_fp_reg(rs3)) ^ FSIGN_MASK32, (RoundingModeEnum)rm, &s->fflags) | F32_HIGH); break; #if FLEN >= 64 case 1: write_fp_reg(rd, fma_sf64(read_fp_reg(rs1), read_fp_reg(rs2), read_fp_reg(rs3) ^ FSIGN_MASK64, (RoundingModeEnum)rm, &s->fflags) | F64_HIGH); break; #endif #if FLEN >= 128 case 3: write_fp_reg(rd, fma_sf128(read_fp_reg(rs1), read_fp_reg(rs2), read_fp_reg(rs3) ^ FSIGN_MASK128, (RoundingModeEnum)rm, &s->fflags)); break; #endif default: goto illegal_insn; } NEXT_INSN; case 0x4b: /* fnmsub */ if (s->fs == 0) goto illegal_insn; funct3 = (insn >> 25) & 3; rs3 = insn >> 27; rm = get_insn_rm(s, (insn >> 12) & 7); if (rm < 0) goto illegal_insn; switch (funct3) { case 0: write_fp_reg(rd, fma_sf32(chkfp32(read_fp_reg(rs1)) ^ FSIGN_MASK32, chkfp32(read_fp_reg(rs2)), chkfp32(read_fp_reg(rs3)), (RoundingModeEnum)rm, &s->fflags) | F32_HIGH); break; #if FLEN >= 64 case 1: write_fp_reg(rd, fma_sf64(read_fp_reg(rs1) ^ FSIGN_MASK64, read_fp_reg(rs2), read_fp_reg(rs3), (RoundingModeEnum)rm, &s->fflags) | F64_HIGH); break; #endif #if FLEN >= 128 case 3: write_fp_reg(rd, fma_sf128(read_fp_reg(rs1) ^ FSIGN_MASK128, read_fp_reg(rs2), read_fp_reg(rs3), (RoundingModeEnum)rm, &s->fflags)); break; #endif default: goto illegal_insn; } NEXT_INSN; case 0x4f: /* fnmadd */ if (s->fs == 0) goto illegal_insn; funct3 = (insn >> 25) & 3; rs3 = insn >> 27; rm = get_insn_rm(s, (insn >> 12) & 7); if (rm < 0) goto illegal_insn; switch (funct3) { case 0: write_fp_reg(rd, fma_sf32(chkfp32(read_fp_reg(rs1)) ^ FSIGN_MASK32, chkfp32(read_fp_reg(rs2)), chkfp32(read_fp_reg(rs3)) ^ FSIGN_MASK32, (RoundingModeEnum)rm, &s->fflags) | F32_HIGH); break; #if FLEN >= 64 case 1: write_fp_reg(rd, fma_sf64(read_fp_reg(rs1) ^ FSIGN_MASK64, read_fp_reg(rs2), read_fp_reg(rs3) ^ FSIGN_MASK64, (RoundingModeEnum)rm, &s->fflags) | F64_HIGH); break; #endif #if FLEN >= 128 case 3: write_fp_reg(rd, fma_sf128(read_fp_reg(rs1) ^ FSIGN_MASK128, read_fp_reg(rs2), read_fp_reg(rs3) ^ FSIGN_MASK128, (RoundingModeEnum)rm, &s->fflags)); break; #endif default: goto illegal_insn; } NEXT_INSN; case 0x53: if (s->fs == 0) goto illegal_insn; imm = insn >> 25; rm = (insn >> 12) & 7; switch (imm) { #define F_SIZE 32 #include "dromajo_fp_template.h" #if FLEN >= 64 #define F_SIZE 64 #include "dromajo_fp_template.h" #endif #if FLEN >= 128 #define F_SIZE 128 #include "dromajo_fp_template.h" #endif default: goto illegal_insn; } NEXT_INSN; #endif default: goto illegal_insn; } /* update PC for next instruction */ jump_insn: ; } /* end of main loop */ illegal_insn: s->pending_exception = CAUSE_ILLEGAL_INSTRUCTION; s->pending_tval = 0; mmu_exception: exception: s->pc = GET_PC(); if (s->pending_exception >= 0) { if ((s->pending_exception < CAUSE_USER_ECALL || s->pending_exception > CAUSE_USER_ECALL + 3) && s->pending_exception != CAUSE_BREAKPOINT) { /* All other causes cancelled the instruction and shouldn't be * counted in minstret */ --insn_counter_addend; --insn_executed; } raise_exception2(s, s->pending_exception, s->pending_tval); } /* we exit because XLEN may have changed */ done_interp: n_cycles--; the_end: s->insn_counter = GET_INSN_COUNTER(); if (!s->stop_the_counter) { int delta = s->insn_counter - insn_counter_start; assert(delta >= 0); s->mcycle += delta; s->minstret += delta; } return insn_executed; } #undef uintx_t #undef intx_t #undef XLEN #undef OP_A
/* * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "dw_apb_uart.h" #include <stdio.h> #include <assert.h> static const char *reg_names[256/4] = { "rx buf / div latch lo", "intr en / div latch hi", "intr id / FIFO ctrl", "line control", "modem control", "line status", "modem status", "scratch", "reserved0", "reserved1", "reserved2", "reserved3", "shadow rx/tx buf0", "shadow rx/tx buf1", "shadow rx/tx buf2", "shadow rx/tx buf3", "shadow rx/tx buf4", "shadow rx/tx buf5", "shadow rx/tx buf6", "shadow rx/tx buf7", "shadow rx/tx buf8", "shadow rx/tx buf9", "shadow rx/tx buf10", "shadow rx/tx buf11", "shadow rx/tx buf12", "shadow rx/tx buf13", "shadow rx/tx buf14", "shadow rx/tx buf15", "FIFO access", "tx FIFO read", "rxr FIFO write", "uart status", "tx FIFO level", "rx FIFO level", "software reset", "shadow RTS", "shadow break control", "shadow dma mode", "shadow FIFO enable", "shadow rx trigger", "shadow tx trigger", "halt Tx", "dma software ack", #ifndef __cplusplus [0xf4/4] = "component parameters", [0xf8/4] = "component version", [0xfc/4] = "component type", #endif }; /* The most important registers (only ones implemented) */ enum { uart_reg_rx_buf = 0x00, uart_reg_intren = 0x04, uart_reg_intrid = 0x08, uart_reg_linecontrol= 0x0c, uart_reg_linestatus = 0x14, uart_reg_comptype = 0xfc, }; /* Configuration parameters at hardware instantiation time (only includes features relevant to sim) */ #define FEATURE_FIFO_MODE 64 #define FEATURE_REG_TIMEOUT_WIDTH 4 #define FEATURE_HC_REG_TIMEOUT_VALUE 0 #define FEATURE_REG_TIMEOUT_VALUE 8 #define FEATURE_UART_RS485_INTERFACE_EN 0 #define FEATURE_UART_9BIT_DATA_EN 0 #define FEATURE_APB_DATA_WIDTH 32 #define FEATURE_MEM_SELECT_USER 1 // == internal #define FEATURE_SIR_MODE 0 // disabled #define FEATURE_AFCE_MODE 0 #define FEATURE_THRE_MODE_USER 1 // enabled #define FEATURE_FIFO_ACCESS 1 // programmable FIFOQ access mode enabled #define FEATURE_ADDITIONAL_FEATURES 1 #define FEATURE_FIFO_STAT 1 #define FEATURE_SHADOW 1 #define FEATURE_UART_ADD_ENCODED_PARAMS 1 #define FEATURE_UART_16550_COMPATIBLE 0 #define FEATURE_FRACTIONAL_BAUD_DIVISOR_EN 1 #define FEATURE_DLF_SIZE 4 #define FEATURE_LSR_STATUS_CLEAR 0 // Both RBR Read and LSR Read clears OE, PE, FE, and BI //#define DEBUG(fmt ...) fprintf(dromajo_stderr, fmt) #define DEBUG(fmt ...) (void) 0 uint32_t dw_apb_uart_read(void *opaque, uint32_t offset, int size_log2) { DW_apb_uart_state *s = (DW_apb_uart_state *)opaque; int res = 0; assert(offset % 4 == 0 && offset/4 < 64); switch (offset) { case uart_reg_rx_buf: // 0x00 if (s->lcr & (1 << 7)) { res = s->div_latch & 255; } else { res = s->rbr; s->lsr &= ~1; // XXX more side effects here, opt. drain FIFO when in FIFO mode // Read from device maybe if (FEATURE_LSR_STATUS_CLEAR == 0) s->lsr &= ~30; // Reading clears BI, FE, PE, OE } break; case uart_reg_intren: // 0x04 if (s->lcr & (1 << 7)) { res = s->div_latch >> 8; } else { res = s->ier; } break; case uart_reg_intrid: // 0x08 s->iid = 1; // XXX Value After Reset res = ((s->fcr & 1) ? 0xc0 : 0) + s->iid; break; case uart_reg_linecontrol: // 0x0c res = s->lcr; break; case uart_reg_linestatus: // 0x14 res = s->lsr; s->lsr |= (1 << 6) | (1 << 5); // TX empty, Holding Empty s->lsr &= ~30; // Reading clears BI, FE, PE, OE if (!(s->lsr & 1)) { CharacterDevice *cs = s->cs; uint8_t buf; if (cs->read_data(cs->opaque, &buf, 1)) { s->lsr |= 1; s->rbr = buf; } } break; case uart_reg_comptype: // 0xfc default:; } if (reg_names[offset/4]) DEBUG("dw_apb_uart_read(0x%02x \"%s\") -> %d\n", offset, reg_names[offset/4], res); else DEBUG("dw_apb_uart_read(0x%02x, %d) -> %d\n", offset, size_log2, res); return res; } void dw_apb_uart_write(void *opaque, uint32_t offset, uint32_t val, int size_log2) { DW_apb_uart_state *s = (DW_apb_uart_state *)opaque; val &= 255; assert(offset % 4 == 0 && offset/4 < 64); if (reg_names[offset/4] && size_log2 == 2) DEBUG("dw_apb_uart_write(0x%02x \"%s\", %d)\n", offset, reg_names[offset/4], val); else DEBUG("dw_apb_uart_write(0x%02x, %d, %d)\n", offset, val, size_log2); switch (offset) { case uart_reg_rx_buf: // 0x00 if (s->lcr & (1 << 7)) { s->div_latch = (s->div_latch & ~255) + val; DEBUG(" div latch is now %d\n", s->div_latch); } else { CharacterDevice *cs = s->cs; unsigned char ch = val; DEBUG(" TRANSMIT '%c' (0x%02x)\n", val, val); cs->write_data(cs->opaque, &ch, 1); s->lsr &= ~(1 << 5); // XXX Assumes non-fifo mode s->lsr &= ~(1 << 6); } break; case uart_reg_intren: // 0x04 if (s->lcr & (1 << 7)) { s->div_latch = (s->div_latch & 255) + val * 256; DEBUG(" div latch is now %d\n", s->div_latch); } else { s->ier = val & (FEATURE_THRE_MODE_USER ? 0xFF : 0x7F); } break; case uart_reg_intrid: // 0x08 s->fcr = val; for (int i = 0; i < 8; ++i) if (s->fcr & (1 << i)) switch (i) { case 0: DEBUG(" FIFO enable\n"); break; case 1: DEBUG(" receiver FIFO reset\n"); break; case 2: DEBUG(" transmitter FIFO reset\n"); break; case 3: DEBUG(" dma mode\n"); break; case 4: DEBUG(" transmitter empty trigger\n"); break; case 6: DEBUG(" receiver trigger\n"); break; default: DEBUG(" ?? bit %d isn't implemented\n", i); break; } break; case uart_reg_linecontrol: // 0x0c s->lcr = val; DEBUG(" %d bits per character\n", (val & 3) + 5); break; default:; DEBUG(" ignored write\n"); break; } }
/* * Elf64 utilities * * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "elf64.h" #include <string.h> bool elf64_is_riscv64(const uint8_t *image, size_t image_size) { const Elf64_Ehdr *ehdr = (const Elf64_Ehdr *)image; if (image_size < sizeof *ehdr) return false; if (strncmp((char *)ehdr->e_ident, ELFMAG, SELFMAG) != 0) // header read, file corrupted? return false; if (ehdr->e_ident[EI_CLASS] != ELFCLASS64) // Only support 64-bit return false; if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) // Unsupported endian (big) return false; if (ehdr->e_machine != EM_RISCV) // Only handle RISC-V return false; /* We have an RV64 ELF file */ if (ehdr->e_ehsize != sizeof *ehdr) // Unexpected e_ehsize field value return false; if (ehdr->e_phentsize != sizeof(Elf64_Phdr)) // Unexpected e_phentsize field value return false; return true; } uint64_t elf64_get_entrypoint(const uint8_t *image) { const Elf64_Ehdr *ehdr = (const Elf64_Ehdr *)image; return ehdr->e_entry; } bool elf64_find_global(const uint8_t *image, size_t image_size, const char *key, uint64_t *value) { const uint8_t *image_end = image + image_size; Elf64_Ehdr *ehdr = (Elf64_Ehdr *)image; if (ehdr->e_shoff + sizeof(Elf64_Shdr) - 1 > image_size) return false; Elf64_Shdr *shdr = (Elf64_Shdr *)&image[ehdr->e_shoff]; if ((const uint8_t *)&shdr[ehdr->e_shstrndx + 1] > image_end) return false; const Elf64_Sym *symtab = 0; int symtab_len = 0; const char *strtab = 0; if ((const uint8_t *)&shdr[ehdr->e_shnum] > image_end) return false; /* Look for symbol table */ for (int i = 0; i < ehdr->e_shnum; ++i) { Elf64_Shdr *sh = &shdr[i]; if (sh->sh_type == SHT_STRTAB && i != ehdr->e_shstrndx) strtab = (const char *)(image + sh->sh_offset); if (sh->sh_type == SHT_SYMTAB) { symtab = (Elf64_Sym *)&image[sh->sh_offset]; symtab_len = sh->sh_size / sizeof(Elf64_Sym); } } if (symtab && strtab) { if ((const uint8_t *)&symtab[symtab_len] > image_end) return false; for (int i = 0; i < symtab_len; ++i) { const Elf64_Sym *sym = &symtab[i]; if (strcmp(key, strtab + sym->st_name) == 0 && ELF32_ST_BIND(sym->st_info) == STB_GLOBAL) { *value = sym->st_value; return true; } } } return false; }
/* * Elf64 utilities * * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef _ELF64_H #define _ELF64_H 1 #if defined(__APPLE__) #include <libelf/gelf.h> /* brew install libelf */ #else #include <elf.h> #endif #include <stdint.h> #include <stdbool.h> #include <stddef.h> #ifndef EM_RISCV #define EM_RISCV 0xF3 /* Little endian RISC-V, 32- and 64-bit */ #endif bool elf64_is_riscv64(const uint8_t *image, size_t image_size); bool elf64_find_global(const uint8_t *image, size_t image_size, const char *key, uint64_t *value); uint64_t elf64_get_entrypoint(const uint8_t *image); #endif
/* * Filesystem utilities * * Copyright (c) 2016 Fabrice Bellard * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #include <stdlib.h> #include <stdio.h> #include <string.h> #include <inttypes.h> #include <assert.h> #include <stdarg.h> #include "cutils.h" #include "fs.h" FSFile *fs_dup(FSDevice *fs, FSFile *f) { FSQID qid; fs->fs_walk(fs, &f, &qid, f, 0, NULL); return f; } FSFile *fs_walk_path1(FSDevice *fs, FSFile *f, const char *path, char **pname) { const char *p; char *name; FSFile *f1; FSQID qid; int len, ret; BOOL is_last, is_first; if (path[0] == '/') path++; is_first = TRUE; for (;;) { p = strchr(path, '/'); if (!p) { name = (char *)path; if (pname) { *pname = name; if (is_first) { ret = fs->fs_walk(fs, &f, &qid, f, 0, NULL); if (ret < 0) f = NULL; } return f; } is_last = TRUE; } else { len = p - path; name = (char *)malloc(len + 1); memcpy(name, path, len); name[len] = '\0'; is_last = FALSE; } ret = fs->fs_walk(fs, &f1, &qid, f, 1, &name); if (!is_last) free(name); if (!is_first) fs->fs_delete(fs, f); f = f1; is_first = FALSE; if (ret <= 0) { fs->fs_delete(fs, f); f = NULL; break; } else if (is_last) { break; } path = p + 1; } return f; } FSFile *fs_walk_path(FSDevice *fs, FSFile *f, const char *path) { return fs_walk_path1(fs, f, path, NULL); } void fs_end(FSDevice *fs) { fs->fs_end(fs); free(fs); }
/* * Filesystem abstraction * * Copyright (c) 2016 Fabrice Bellard * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ /* FSQID.type */ #define P9_QTDIR 0x80 #define P9_QTAPPEND 0x40 #define P9_QTEXCL 0x20 #define P9_QTMOUNT 0x10 #define P9_QTAUTH 0x08 #define P9_QTTMP 0x04 #define P9_QTSYMLINK 0x02 #define P9_QTLINK 0x01 #define P9_QTFILE 0x00 /* mode bits */ #define P9_S_IRWXUGO 0x01FF #define P9_S_ISVTX 0x0200 #define P9_S_ISGID 0x0400 #define P9_S_ISUID 0x0800 #define P9_S_IFMT 0xF000 #define P9_S_IFIFO 0x1000 #define P9_S_IFCHR 0x2000 #define P9_S_IFDIR 0x4000 #define P9_S_IFBLK 0x6000 #define P9_S_IFREG 0x8000 #define P9_S_IFLNK 0xA000 #define P9_S_IFSOCK 0xC000 /* flags for lopen()/lcreate() */ #define P9_O_RDONLY 0x00000000 #define P9_O_WRONLY 0x00000001 #define P9_O_RDWR 0x00000002 #define P9_O_NOACCESS 0x00000003 #define P9_O_CREAT 0x00000040 #define P9_O_EXCL 0x00000080 #define P9_O_NOCTTY 0x00000100 #define P9_O_TRUNC 0x00000200 #define P9_O_APPEND 0x00000400 #define P9_O_NONBLOCK 0x00000800 #define P9_O_DSYNC 0x00001000 #define P9_O_FASYNC 0x00002000 #define P9_O_DIRECT 0x00004000 #define P9_O_LARGEFILE 0x00008000 #define P9_O_DIRECTORY 0x00010000 #define P9_O_NOFOLLOW 0x00020000 #define P9_O_NOATIME 0x00040000 #define P9_O_CLOEXEC 0x00080000 #define P9_O_SYNC 0x00100000 /* for fs_setattr() */ #define P9_SETATTR_MODE 0x00000001 #define P9_SETATTR_UID 0x00000002 #define P9_SETATTR_GID 0x00000004 #define P9_SETATTR_SIZE 0x00000008 #define P9_SETATTR_ATIME 0x00000010 #define P9_SETATTR_MTIME 0x00000020 #define P9_SETATTR_CTIME 0x00000040 #define P9_SETATTR_ATIME_SET 0x00000080 #define P9_SETATTR_MTIME_SET 0x00000100 #define P9_EPERM 1 #define P9_ENOENT 2 #define P9_EIO 5 #define P9_EEXIST 17 #define P9_ENOTDIR 20 #define P9_EINVAL 22 #define P9_ENOSPC 28 #define P9_ENOTEMPTY 39 #define P9_EPROTO 71 #define P9_ENOTSUP 524 typedef struct FSDevice FSDevice; typedef struct FSFile FSFile; typedef struct { uint32_t f_bsize; uint64_t f_blocks; uint64_t f_bfree; uint64_t f_bavail; uint64_t f_files; uint64_t f_ffree; } FSStatFS; typedef struct { uint8_t type; /* P9_IFx */ uint32_t version; uint64_t path; } FSQID; typedef struct { FSQID qid; uint32_t st_mode; uint32_t st_uid; uint32_t st_gid; uint64_t st_nlink; uint64_t st_rdev; uint64_t st_size; uint64_t st_blksize; uint64_t st_blocks; uint64_t st_atime_sec; uint32_t st_atime_nsec; uint64_t st_mtime_sec; uint32_t st_mtime_nsec; uint64_t st_ctime_sec; uint32_t st_ctime_nsec; } FSStat; #define P9_LOCK_TYPE_RDLCK 0 #define P9_LOCK_TYPE_WRLCK 1 #define P9_LOCK_TYPE_UNLCK 2 #define P9_LOCK_FLAGS_BLOCK 1 #define P9_LOCK_FLAGS_RECLAIM 2 #define P9_LOCK_SUCCESS 0 #define P9_LOCK_BLOCKED 1 #define P9_LOCK_ERROR 2 #define P9_LOCK_GRACE 3 #define FSCMD_NAME ".fscmd" typedef struct { uint8_t type; uint32_t flags; uint64_t start; uint64_t length; uint32_t proc_id; char *client_id; } FSLock; typedef void FSOpenCompletionFunc(FSDevice *fs, FSQID *qid, int err, void *opaque); struct FSDevice { void (*fs_end)(FSDevice *s); void (*fs_delete)(FSDevice *s, FSFile *f); void (*fs_statfs)(FSDevice *fs, FSStatFS *st); int (*fs_attach)(FSDevice *fs, FSFile **pf, FSQID *qid, uint32_t uid, const char *uname, const char *aname); int (*fs_walk)(FSDevice *fs, FSFile **pf, FSQID *qids, FSFile *f, int n, char **names); int (*fs_mkdir)(FSDevice *fs, FSQID *qid, FSFile *f, const char *name, uint32_t mode, uint32_t gid); int (*fs_open)(FSDevice *fs, FSQID *qid, FSFile *f, uint32_t flags, FSOpenCompletionFunc *cb, void *opaque); int (*fs_create)(FSDevice *fs, FSQID *qid, FSFile *f, const char *name, uint32_t flags, uint32_t mode, uint32_t gid); int (*fs_stat)(FSDevice *fs, FSFile *f, FSStat *st); int (*fs_setattr)(FSDevice *fs, FSFile *f, uint32_t mask, uint32_t mode, uint32_t uid, uint32_t gid, uint64_t size, uint64_t atime_sec, uint64_t atime_nsec, uint64_t mtime_sec, uint64_t mtime_nsec); void (*fs_close)(FSDevice *fs, FSFile *f); int (*fs_readdir)(FSDevice *fs, FSFile *f, uint64_t offset, uint8_t *buf, int count); int (*fs_read)(FSDevice *fs, FSFile *f, uint64_t offset, uint8_t *buf, int count); int (*fs_write)(FSDevice *fs, FSFile *f, uint64_t offset, const uint8_t *buf, int count); int (*fs_link)(FSDevice *fs, FSFile *df, FSFile *f, const char *name); int (*fs_symlink)(FSDevice *fs, FSQID *qid, FSFile *f, const char *name, const char *symgt, uint32_t gid); int (*fs_mknod)(FSDevice *fs, FSQID *qid, FSFile *f, const char *name, uint32_t mode, uint32_t major, uint32_t minor, uint32_t gid); int (*fs_readlink)(FSDevice *fs, char *buf, int buf_size, FSFile *f); int (*fs_renameat)(FSDevice *fs, FSFile *f, const char *name, FSFile *new_f, const char *new_name); int (*fs_unlinkat)(FSDevice *fs, FSFile *f, const char *name); int (*fs_lock)(FSDevice *fs, FSFile *f, const FSLock *lock); int (*fs_getlock)(FSDevice *fs, FSFile *f, FSLock *lock); }; FSDevice *fs_disk_init(const char *root_path); FSDevice *fs_mem_init(void); FSDevice *fs_net_init(const char *url, void (*start)(void *opaque), void *opaque); void fs_net_set_pwd(FSDevice *fs, const char *pwd); void fs_export_file(const char *filename, const uint8_t *buf, int buf_len); void fs_end(FSDevice *fs); FSFile *fs_dup(FSDevice *fs, FSFile *f); FSFile *fs_walk_path1(FSDevice *fs, FSFile *f, const char *path, char **pname); FSFile *fs_walk_path(FSDevice *fs, FSFile *f, const char *path);
/* * Filesystem on disk * * Copyright (c) 2016 Fabrice Bellard * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #if !defined(__APPLE__) #include <stdlib.h> #include <stdio.h> #include <string.h> #include <inttypes.h> #include <assert.h> #include <stdarg.h> #include <sys/statfs.h> #include <sys/stat.h> #include <sys/sysmacros.h> #include <unistd.h> #include <fcntl.h> #include <dirent.h> #include <errno.h> #include "cutils.h" #include "list.h" #include "fs.h" typedef struct { FSDevice common; char *root_path; } FSDeviceDisk; static void fs_close(FSDevice *fs, FSFile *f); struct FSFile { uint32_t uid; char *path; /* complete path */ BOOL is_opened; BOOL is_dir; union { int fd; DIR *dirp; } u; }; static void fs_delete(FSDevice *fs, FSFile *f) { if (f->is_opened) fs_close(fs, f); free(f->path); free(f); } /* warning: path belong to fid_create() */ static FSFile *fid_create(FSDevice *s1, char *path, uint32_t uid) { FSFile *f = (FSFile *)mallocz(sizeof *f); f->path = path; f->uid = uid; return f; } static int errno_table[][2] = { { P9_EPERM, EPERM }, { P9_ENOENT, ENOENT }, { P9_EIO, EIO }, { P9_EEXIST, EEXIST }, { P9_EINVAL, EINVAL }, { P9_ENOSPC, ENOSPC }, { P9_ENOTEMPTY, ENOTEMPTY }, { P9_EPROTO, EPROTO }, { P9_ENOTSUP, ENOTSUP }, }; static int errno_to_p9(int err) { if (err == 0) return 0; for (unsigned int i = 0; i < countof(errno_table); i++) { if (err == errno_table[i][1]) return errno_table[i][0]; } return P9_EINVAL; } static int open_flags[][2] = { { P9_O_CREAT, O_CREAT }, { P9_O_EXCL, O_EXCL }, // { P9_O_NOCTTY, O_NOCTTY }, { P9_O_TRUNC, O_TRUNC }, { P9_O_APPEND, O_APPEND }, { P9_O_NONBLOCK, O_NONBLOCK }, { P9_O_DSYNC, O_DSYNC }, // { P9_O_FASYNC, O_FASYNC }, // { P9_O_DIRECT, O_DIRECT }, // { P9_O_LARGEFILE, O_LARGEFILE }, // { P9_O_DIRECTORY, O_DIRECTORY }, { P9_O_NOFOLLOW, O_NOFOLLOW }, // { P9_O_NOATIME, O_NOATIME }, // { P9_O_CLOEXEC, O_CLOEXEC }, { P9_O_SYNC, O_SYNC }, }; static int p9_flags_to_host(int flags) { int ret = (flags & P9_O_NOACCESS); for (unsigned int i = 0; i < countof(open_flags); i++) { if (flags & open_flags[i][0]) ret |= open_flags[i][1]; } return ret; } static void stat_to_qid(FSQID *qid, const struct stat *st) { if (S_ISDIR(st->st_mode)) qid->type = P9_QTDIR; else if (S_ISLNK(st->st_mode)) qid->type = P9_QTSYMLINK; else qid->type = P9_QTFILE; qid->version = 0; /* no caching on client */ qid->path = st->st_ino; } static void fs_statfs(FSDevice *fs1, FSStatFS *st) { FSDeviceDisk *fs = (FSDeviceDisk *)fs1; struct statfs st1; statfs(fs->root_path, &st1); st->f_bsize = st1.f_bsize; st->f_blocks = st1.f_blocks; st->f_bfree = st1.f_bfree; st->f_bavail = st1.f_bavail; st->f_files = st1.f_files; st->f_ffree = st1.f_ffree; } static char *compose_path(const char *path, const char *name) { int path_len = strlen(path); int name_len = strlen(name); char *d = (char *)malloc(path_len + 1 + name_len + 1); memcpy(d, path, path_len); d[path_len] = '/'; memcpy(d + path_len + 1, name, name_len + 1); return d; } static int fs_attach(FSDevice *fs1, FSFile **pf, FSQID *qid, uint32_t uid, const char *uname, const char *aname) { FSDeviceDisk *fs = (FSDeviceDisk *)fs1; struct stat st; FSFile *f; if (lstat(fs->root_path, &st) != 0) { *pf = NULL; return -errno_to_p9(errno); } f = fid_create(fs1, strdup(fs->root_path), uid); stat_to_qid(qid, &st); *pf = f; return 0; } static int fs_walk(FSDevice *fs, FSFile **pf, FSQID *qids, FSFile *f, int n, char **names) { char *path, *path1; struct stat st; int i; path = strdup(f->path); for (i = 0; i < n; i++) { path1 = compose_path(path, names[i]); if (lstat(path1, &st) != 0) { free(path1); break; } free(path); path = path1; stat_to_qid(&qids[i], &st); } *pf = fid_create(fs, path, f->uid); return i; } static int fs_mkdir(FSDevice *fs, FSQID *qid, FSFile *f, const char *name, uint32_t mode, uint32_t gid) { char *path; struct stat st; path = compose_path(f->path, name); if (mkdir(path, mode) < 0) { free(path); return -errno_to_p9(errno); } if (lstat(path, &st) != 0) { free(path); return -errno_to_p9(errno); } free(path); stat_to_qid(qid, &st); return 0; } static int fs_open(FSDevice *fs, FSQID *qid, FSFile *f, uint32_t flags, FSOpenCompletionFunc *cb, void *opaque) { struct stat st; fs_close(fs, f); if (stat(f->path, &st) != 0) return -errno_to_p9(errno); stat_to_qid(qid, &st); if (flags & P9_O_DIRECTORY) { DIR *dirp; dirp = opendir(f->path); if (!dirp) return -errno_to_p9(errno); f->is_opened = TRUE; f->is_dir = TRUE; f->u.dirp = dirp; } else { int fd; fd = open(f->path, p9_flags_to_host(flags) & ~O_CREAT); if (fd < 0) return -errno_to_p9(errno); f->is_opened = TRUE; f->is_dir = FALSE; f->u.fd = fd; } return 0; } static int fs_create(FSDevice *fs, FSQID *qid, FSFile *f, const char *name, uint32_t flags, uint32_t mode, uint32_t gid) { struct stat st; char *path; int ret, fd; fs_close(fs, f); path = compose_path(f->path, name); fd = open(path, p9_flags_to_host(flags) | O_CREAT, mode); if (fd < 0) { free(path); return -errno_to_p9(errno); } ret = lstat(path, &st); if (ret != 0) { free(path); close(fd); return -errno_to_p9(errno); } free(f->path); f->path = path; f->is_opened = TRUE; f->is_dir = FALSE; f->u.fd = fd; stat_to_qid(qid, &st); return 0; } static int fs_readdir(FSDevice *fs, FSFile *f, uint64_t offset, uint8_t *buf, int count) { struct dirent *de; int len, pos, name_len, type, d_type; if (!f->is_opened || !f->is_dir) return -P9_EPROTO; if (offset == 0) rewinddir(f->u.dirp); else seekdir(f->u.dirp, offset); pos = 0; for (;;) { de = readdir(f->u.dirp); if (de == NULL) break; name_len = strlen(de->d_name); len = 13 + 8 + 1 + 2 + name_len; if ((pos + len) > count) break; offset = telldir(f->u.dirp); d_type = de->d_type; if (d_type == DT_UNKNOWN) { char *path; struct stat st; path = compose_path(f->path, de->d_name); if (lstat(path, &st) == 0) { d_type = st.st_mode >> 12; } else { d_type = DT_REG; /* default */ } free(path); } if (d_type == DT_DIR) type = P9_QTDIR; else if (d_type == DT_LNK) type = P9_QTSYMLINK; else type = P9_QTFILE; buf[pos++] = type; put_le32(buf + pos, 0); /* version */ pos += 4; put_le64(buf + pos, de->d_ino); pos += 8; put_le64(buf + pos, offset); pos += 8; buf[pos++] = d_type; put_le16(buf + pos, name_len); pos += 2; memcpy(buf + pos, de->d_name, name_len); pos += name_len; } return pos; } static int fs_read(FSDevice *fs, FSFile *f, uint64_t offset, uint8_t *buf, int count) { int ret; if (!f->is_opened || f->is_dir) return -P9_EPROTO; ret = pread(f->u.fd, buf, count, offset); if (ret < 0) return -errno_to_p9(errno); else return ret; } static int fs_write(FSDevice *fs, FSFile *f, uint64_t offset, const uint8_t *buf, int count) { int ret; if (!f->is_opened || f->is_dir) return -P9_EPROTO; ret = pwrite(f->u.fd, buf, count, offset); if (ret < 0) return -errno_to_p9(errno); else return ret; } static void fs_close(FSDevice *fs, FSFile *f) { if (!f->is_opened) return; if (f->is_dir) closedir(f->u.dirp); else close(f->u.fd); f->is_opened = FALSE; } static int fs_stat(FSDevice *fs, FSFile *f, FSStat *st) { struct stat st1; if (lstat(f->path, &st1) != 0) return -P9_ENOENT; stat_to_qid(&st->qid, &st1); st->st_mode = st1.st_mode; st->st_uid = st1.st_uid; st->st_gid = st1.st_gid; st->st_nlink = st1.st_nlink; st->st_rdev = st1.st_rdev; st->st_size = st1.st_size; st->st_blksize = st1.st_blksize; st->st_blocks = st1.st_blocks; st->st_atime_sec = st1.st_atim.tv_sec; st->st_atime_nsec = st1.st_atim.tv_nsec; st->st_mtime_sec = st1.st_mtim.tv_sec; st->st_mtime_nsec = st1.st_mtim.tv_nsec; st->st_ctime_sec = st1.st_ctim.tv_sec; st->st_ctime_nsec = st1.st_ctim.tv_nsec; return 0; } static int fs_setattr(FSDevice *fs, FSFile *f, uint32_t mask, uint32_t mode, uint32_t uid, uint32_t gid, uint64_t size, uint64_t atime_sec, uint64_t atime_nsec, uint64_t mtime_sec, uint64_t mtime_nsec) { BOOL ctime_updated = FALSE; if (mask & (P9_SETATTR_UID | P9_SETATTR_GID)) { if (lchown(f->path, (mask & P9_SETATTR_UID) ? uid : -1, (mask & P9_SETATTR_GID) ? gid : -1) < 0) return -errno_to_p9(errno); ctime_updated = TRUE; } /* must be done after uid change for suid */ if (mask & P9_SETATTR_MODE) { if (chmod(f->path, mode) < 0) return -errno_to_p9(errno); ctime_updated = TRUE; } if (mask & P9_SETATTR_SIZE) { if (truncate(f->path, size) < 0) return -errno_to_p9(errno); ctime_updated = TRUE; } if (mask & (P9_SETATTR_ATIME | P9_SETATTR_MTIME)) { struct timespec ts[2]; if (mask & P9_SETATTR_ATIME) { if (mask & P9_SETATTR_ATIME_SET) { ts[0].tv_sec = atime_sec; ts[0].tv_nsec = atime_nsec; } else { ts[0].tv_sec = 0; ts[0].tv_nsec = UTIME_NOW; } } else { ts[0].tv_sec = 0; ts[0].tv_nsec = UTIME_OMIT; } if (mask & P9_SETATTR_MTIME) { if (mask & P9_SETATTR_MTIME_SET) { ts[1].tv_sec = mtime_sec; ts[1].tv_nsec = mtime_nsec; } else { ts[1].tv_sec = 0; ts[1].tv_nsec = UTIME_NOW; } } else { ts[1].tv_sec = 0; ts[1].tv_nsec = UTIME_OMIT; } if (utimensat(AT_FDCWD, f->path, ts, AT_SYMLINK_NOFOLLOW) < 0) return -errno_to_p9(errno); ctime_updated = TRUE; } if ((mask & P9_SETATTR_CTIME) && !ctime_updated) { if (lchown(f->path, -1, -1) < 0) return -errno_to_p9(errno); } return 0; } static int fs_link(FSDevice *fs, FSFile *df, FSFile *f, const char *name) { char *path; path = compose_path(df->path, name); if (link(f->path, path) < 0) { free(path); return -errno_to_p9(errno); } free(path); return 0; } static int fs_symlink(FSDevice *fs, FSQID *qid, FSFile *f, const char *name, const char *symgt, uint32_t gid) { char *path; struct stat st; path = compose_path(f->path, name); if (symlink(symgt, path) < 0) { free(path); return -errno_to_p9(errno); } if (lstat(path, &st) != 0) { free(path); return -errno_to_p9(errno); } free(path); stat_to_qid(qid, &st); return 0; } static int fs_mknod(FSDevice *fs, FSQID *qid, FSFile *f, const char *name, uint32_t mode, uint32_t major, uint32_t minor, uint32_t gid) { char *path; struct stat st; path = compose_path(f->path, name); if (mknod(path, mode, makedev(major, minor)) < 0) { free(path); return -errno_to_p9(errno); } if (lstat(path, &st) != 0) { free(path); return -errno_to_p9(errno); } free(path); stat_to_qid(qid, &st); return 0; } static int fs_readlink(FSDevice *fs, char *buf, int buf_size, FSFile *f) { int ret; ret = readlink(f->path, buf, buf_size - 1); if (ret < 0) return -errno_to_p9(errno); buf[ret] = '\0'; return 0; } static int fs_renameat(FSDevice *fs, FSFile *f, const char *name, FSFile *new_f, const char *new_name) { char *path, *new_path; int ret; path = compose_path(f->path, name); new_path = compose_path(new_f->path, new_name); ret = rename(path, new_path); free(path); free(new_path); if (ret < 0) return -errno_to_p9(errno); return 0; } static int fs_unlinkat(FSDevice *fs, FSFile *f, const char *name) { char *path; int ret; path = compose_path(f->path, name); ret = remove(path); free(path); if (ret < 0) return -errno_to_p9(errno); return 0; } static int fs_lock(FSDevice *fs, FSFile *f, const FSLock *lock) { int ret; struct flock fl; if (!f->is_opened || f->is_dir) return -P9_EPROTO; fl.l_type = lock->type; fl.l_whence = SEEK_SET; fl.l_start = lock->start; fl.l_len = lock->length; ret = fcntl(f->u.fd, F_SETLK, &fl); if (ret == 0) { ret = P9_LOCK_SUCCESS; } else if (errno == EAGAIN || errno == EACCES) { ret = P9_LOCK_BLOCKED; } else { ret = -errno_to_p9(errno); } return ret; } static int fs_getlock(FSDevice *fs, FSFile *f, FSLock *lock) { int ret; struct flock fl; if (!f->is_opened || f->is_dir) return -P9_EPROTO; fl.l_type = lock->type; fl.l_whence = SEEK_SET; fl.l_start = lock->start; fl.l_len = lock->length; ret = fcntl(f->u.fd, F_GETLK, &fl); if (ret < 0) { ret = -errno_to_p9(errno); } else { lock->type = fl.l_type; lock->start = fl.l_start; lock->length = fl.l_len; } return ret; } static void fs_disk_end(FSDevice *fs1) { FSDeviceDisk *fs = (FSDeviceDisk *)fs1; free(fs->root_path); } FSDevice *fs_disk_init(const char *root_path) { struct stat st; lstat(root_path, &st); if (!S_ISDIR(st.st_mode)) return NULL; FSDeviceDisk *fs = (FSDeviceDisk *)mallocz(sizeof *fs); fs->common.fs_end = fs_disk_end; fs->common.fs_delete = fs_delete; fs->common.fs_statfs = fs_statfs; fs->common.fs_attach = fs_attach; fs->common.fs_walk = fs_walk; fs->common.fs_mkdir = fs_mkdir; fs->common.fs_open = fs_open; fs->common.fs_create = fs_create; fs->common.fs_stat = fs_stat; fs->common.fs_setattr = fs_setattr; fs->common.fs_close = fs_close; fs->common.fs_readdir = fs_readdir; fs->common.fs_read = fs_read; fs->common.fs_write = fs_write; fs->common.fs_link = fs_link; fs->common.fs_symlink = fs_symlink; fs->common.fs_mknod = fs_mknod; fs->common.fs_readlink = fs_readlink; fs->common.fs_renameat = fs_renameat; fs->common.fs_unlinkat = fs_unlinkat; fs->common.fs_lock = fs_lock; fs->common.fs_getlock = fs_getlock; fs->root_path = strdup(root_path); return (FSDevice *)fs; } #endif
/* * Misc FS utilities * * Copyright (c) 2016-2017 Fabrice Bellard * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #define HEAD_FILENAME "head" #define ROOT_FILENAME "files" #define FILEID_SIZE_MAX 32 #define FS_KEY_LEN 16 /* default block size to determine the total filesytem size */ #define FS_BLOCK_SIZE_LOG2 12 #define FS_BLOCK_SIZE (1 << FS_BLOCK_SIZE_LOG2) typedef enum { FS_ERR_OK = 0, FS_ERR_GENERIC = -1, FS_ERR_SYNTAX = -2, FS_ERR_REVISION = -3, FS_ERR_FILE_ID = -4, FS_ERR_IO = -5, FS_ERR_NOENT = -6, FS_ERR_COUNTERS = -7, FS_ERR_QUOTA = -8, FS_ERR_PROTOCOL_VERSION = -9, FS_ERR_HEAD = -10, } FSCommitErrorCode; typedef uint64_t FSFileID; static inline BOOL isspace_nolf(int c) { return (c == ' ' || c == '\t'); } static inline int from_hex(int c) { if (c >= '0' && c <= '9') return c - '0'; else if (c >= 'A' && c <= 'F') return c - 'A' + 10; else if (c >= 'a' && c <= 'f') return c - 'a' + 10; else return -1; } static inline uint64_t block_align(uint64_t val, uint64_t align) { return (val + align - 1) & ~(align - 1); } void pstrcpy(char *buf, int buf_size, const char *str); char *pstrcat(char *buf, int buf_size, const char *s); char *compose_path(const char *path, const char *name); char *compose_url(const char *base_url, const char *name); void skip_line(const char **pp); char *quoted_str(const char *str); int parse_fname(char *buf, int buf_size, const char **pp); int parse_uint32_base(uint32_t *pval, const char **pp, int base); int parse_uint64_base(uint64_t *pval, const char **pp, int base); int parse_uint64(uint64_t *pval, const char **pp); int parse_uint32(uint32_t *pval, const char **pp); int parse_time(uint32_t *psec, uint32_t *pnsec, const char **pp); int parse_file_id(FSFileID *pval, const char **pp); char *file_id_to_filename(char *buf, FSFileID file_id); void encode_hex(char *str, const uint8_t *buf, int len); int decode_hex(uint8_t *buf, const char *str, int len); BOOL is_url(const char *path); const char *skip_header(const char *p); int parse_tag(char *buf, int buf_size, const char *str, const char *tag); int parse_tag_uint64(uint64_t *pval, const char *str, const char *tag); int parse_tag_file_id(FSFileID *pval, const char *str, const char *tag); int parse_tag_version(const char *str);
/* * IO memory handling * * Copyright (c) 2016-2017 Fabrice Bellard * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #include "dromajo.h" #include <stdlib.h> #include <stdarg.h> #include <string.h> #include <inttypes.h> #include <assert.h> #include "cutils.h" #include "iomem.h" static PhysMemoryRange *default_register_ram(PhysMemoryMap *s, uint64_t addr, uint64_t size, int devram_flags); static void default_free_ram(PhysMemoryMap *s, PhysMemoryRange *pr); static const uint32_t *default_get_dirty_bits(PhysMemoryMap *map, PhysMemoryRange *pr); static void default_set_addr(PhysMemoryMap *map, PhysMemoryRange *pr, uint64_t addr, BOOL enabled); PhysMemoryMap *phys_mem_map_init(void) { PhysMemoryMap *s = (PhysMemoryMap *)mallocz(sizeof(PhysMemoryMap)); s->register_ram = default_register_ram; s->free_ram = default_free_ram; s->get_dirty_bits = default_get_dirty_bits; s->set_ram_addr = default_set_addr; return s; } void phys_mem_map_end(PhysMemoryMap *s) { for (int i = 0; i < s->n_phys_mem_range; i++) { PhysMemoryRange *pr = &s->phys_mem_range[i]; if (pr->is_ram) { s->free_ram(s, pr); } } free(s); } /* return NULL if not found */ /* XXX: optimize */ PhysMemoryRange *get_phys_mem_range(PhysMemoryMap *s, uint64_t paddr) { for (int i = s->n_phys_mem_range-1; i >= 0; --i) { PhysMemoryRange *pr = &s->phys_mem_range[i]; if (paddr >= pr->addr && paddr < pr->addr + pr->size) return pr; } return NULL; } PhysMemoryRange *register_ram_entry(PhysMemoryMap *s, uint64_t addr, uint64_t size, int devram_flags) { PhysMemoryRange *pr; assert(s->n_phys_mem_range < PHYS_MEM_RANGE_MAX); assert((size & (DEVRAM_PAGE_SIZE - 1)) == 0 && size != 0); pr = &s->phys_mem_range[s->n_phys_mem_range++]; pr->map = s; pr->is_ram = TRUE; pr->devram_flags = devram_flags & ~DEVRAM_FLAG_DISABLED; pr->addr = addr; pr->org_size = size; if (devram_flags & DEVRAM_FLAG_DISABLED) pr->size = 0; else pr->size = pr->org_size; pr->phys_mem = NULL; pr->dirty_bits = NULL; return pr; } static PhysMemoryRange *default_register_ram(PhysMemoryMap *s, uint64_t addr, uint64_t size, int devram_flags) { PhysMemoryRange *pr; pr = register_ram_entry(s, addr, size, devram_flags); pr->phys_mem = (uint8_t *)mallocz(size); if (!pr->phys_mem) { fprintf(dromajo_stderr, "Could not allocate VM memory\n"); exit(1); } if (devram_flags & DEVRAM_FLAG_DIRTY_BITS) { size_t nb_pages; int i; nb_pages = size >> DEVRAM_PAGE_SIZE_LOG2; pr->dirty_bits_size = ((nb_pages + 31) / 32) * sizeof(uint32_t); pr->dirty_bits_index = 0; for (i = 0; i < 2; i++) { pr->dirty_bits_tab[i] = (uint32_t *)mallocz(pr->dirty_bits_size); } pr->dirty_bits = pr->dirty_bits_tab[pr->dirty_bits_index]; } return pr; } /* return a pointer to the bitmap of dirty bits and reset them */ static const uint32_t *default_get_dirty_bits(PhysMemoryMap *map, PhysMemoryRange *pr) { uint32_t *dirty_bits; BOOL has_dirty_bits; size_t n, i; dirty_bits = pr->dirty_bits; has_dirty_bits = FALSE; n = pr->dirty_bits_size / sizeof(uint32_t); for (i = 0; i < n; i++) { if (dirty_bits[i] != 0) { has_dirty_bits = TRUE; break; } } if (has_dirty_bits && pr->size != 0) { /* invalidate the corresponding CPU write TLBs */ map->flush_tlb_write_range(map->opaque, pr->phys_mem, pr->org_size); } pr->dirty_bits_index ^= 1; pr->dirty_bits = pr->dirty_bits_tab[pr->dirty_bits_index]; memset(pr->dirty_bits, 0, pr->dirty_bits_size); return dirty_bits; } static void default_free_ram(PhysMemoryMap *s, PhysMemoryRange *pr) { free(pr->phys_mem); } PhysMemoryRange *cpu_register_device(PhysMemoryMap *s, uint64_t addr, uint64_t size, void *opaque, DeviceReadFunc *read_func, DeviceWriteFunc *write_func, int devio_flags) { PhysMemoryRange *pr; assert(s->n_phys_mem_range < PHYS_MEM_RANGE_MAX); assert(size <= 0xffffffff); pr = &s->phys_mem_range[s->n_phys_mem_range++]; pr->map = s; pr->addr = addr; pr->org_size = size; if (devio_flags & DEVIO_DISABLED) pr->size = 0; else pr->size = pr->org_size; pr->is_ram = FALSE; pr->opaque = opaque; pr->read_func = read_func; pr->write_func = write_func; pr->devio_flags = devio_flags; return pr; } static void default_set_addr(PhysMemoryMap *map, PhysMemoryRange *pr, uint64_t addr, BOOL enabled) { if (enabled) { if (pr->size == 0 || pr->addr != addr) { /* enable or move mapping */ if (pr->is_ram) { map->flush_tlb_write_range(map->opaque, pr->phys_mem, pr->org_size); } pr->addr = addr; pr->size = pr->org_size; } } else { if (pr->size != 0) { /* disable mapping */ if (pr->is_ram) { map->flush_tlb_write_range(map->opaque, pr->phys_mem, pr->org_size); } pr->addr = 0; pr->size = 0; } } } void phys_mem_set_addr(PhysMemoryRange *pr, uint64_t addr, BOOL enabled) { PhysMemoryMap *map = pr->map; if (!pr->is_ram) { default_set_addr(map, pr, addr, enabled); } else { return map->set_ram_addr(map, pr, addr, enabled); } } /* IRQ support */ void irq_init(IRQSignal *irq, SetIRQFunc *set_irq, void *opaque, int irq_num) { irq->set_irq = set_irq; irq->opaque = opaque; irq->irq_num = irq_num; }
/* * IO memory handling * * Copyright (c) 2016-2017 Fabrice Bellard * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #ifndef IOMEM_H #define IOMEM_H #include "cutils.h" typedef void DeviceWriteFunc(void *opaque, uint32_t offset, uint32_t val, int size_log2); typedef uint32_t DeviceReadFunc(void *opaque, uint32_t offset, int size_log2); #define DEVIO_SIZE8 (1 << 0) #define DEVIO_SIZE16 (1 << 1) #define DEVIO_SIZE32 (1 << 2) /* not supported, could add specific 64 bit callbacks when needed */ //#define DEVIO_SIZE64 (1 << 3) #define DEVIO_DISABLED (1 << 4) #define DEVRAM_FLAG_ROM (1 << 0) /* not writable */ #define DEVRAM_FLAG_DIRTY_BITS (1 << 1) /* maintain dirty bits */ #define DEVRAM_FLAG_DISABLED (1 << 2) /* allocated but not mapped */ #define DEVRAM_PAGE_SIZE_LOG2 12 #define DEVRAM_PAGE_SIZE (1 << DEVRAM_PAGE_SIZE_LOG2) typedef struct PhysMemoryMap PhysMemoryMap; typedef struct { PhysMemoryMap *map; uint64_t addr; uint64_t org_size; /* original size */ uint64_t size; /* =org_size or 0 if the mapping is disabled */ BOOL is_ram; /* the following is used for RAM access */ int devram_flags; uint8_t *phys_mem; int dirty_bits_size; /* in bytes */ uint32_t *dirty_bits; /* NULL if not used */ uint32_t *dirty_bits_tab[2]; int dirty_bits_index; /* 0-1 */ /* the following is used for I/O access */ void *opaque; DeviceReadFunc *read_func; DeviceWriteFunc *write_func; int devio_flags; } PhysMemoryRange; #define PHYS_MEM_RANGE_MAX 32 struct PhysMemoryMap { int n_phys_mem_range; PhysMemoryRange phys_mem_range[PHYS_MEM_RANGE_MAX]; PhysMemoryRange *(*register_ram)(PhysMemoryMap *s, uint64_t addr, uint64_t size, int devram_flags); void (*free_ram)(PhysMemoryMap *s, PhysMemoryRange *pr); const uint32_t *(*get_dirty_bits)(PhysMemoryMap *s, PhysMemoryRange *pr); void (*set_ram_addr)(PhysMemoryMap *s, PhysMemoryRange *pr, uint64_t addr, BOOL enabled); void *opaque; void (*flush_tlb_write_range)(void *opaque, uint8_t *ram_addr, size_t ram_size); }; PhysMemoryMap *phys_mem_map_init(void); void phys_mem_map_end(PhysMemoryMap *s); PhysMemoryRange *register_ram_entry(PhysMemoryMap *s, uint64_t addr, uint64_t size, int devram_flags); static inline PhysMemoryRange *cpu_register_ram(PhysMemoryMap *s, uint64_t addr, uint64_t size, int devram_flags) { return s->register_ram(s, addr, size, devram_flags); } PhysMemoryRange *cpu_register_device(PhysMemoryMap *s, uint64_t addr, uint64_t size, void *opaque, DeviceReadFunc *read_func, DeviceWriteFunc *write_func, int devio_flags); PhysMemoryRange *get_phys_mem_range(PhysMemoryMap *s, uint64_t paddr); void phys_mem_set_addr(PhysMemoryRange *pr, uint64_t addr, BOOL enabled); static inline const uint32_t *phys_mem_get_dirty_bits(PhysMemoryRange *pr) { PhysMemoryMap *map = pr->map; return map->get_dirty_bits(map, pr); } static inline void phys_mem_set_dirty_bit(PhysMemoryRange *pr, size_t offset) { size_t page_index; uint32_t mask, *dirty_bits_ptr; if (pr->dirty_bits) { page_index = offset >> DEVRAM_PAGE_SIZE_LOG2; mask = 1 << (page_index & 0x1f); dirty_bits_ptr = pr->dirty_bits + (page_index >> 5); *dirty_bits_ptr |= mask; } } static inline BOOL phys_mem_is_dirty_bit(PhysMemoryRange *pr, size_t offset) { size_t page_index; uint32_t *dirty_bits_ptr; if (!pr->dirty_bits) return TRUE; page_index = offset >> DEVRAM_PAGE_SIZE_LOG2; dirty_bits_ptr = pr->dirty_bits + (page_index >> 5); return (*dirty_bits_ptr >> (page_index & 0x1f)) & 1; } /* IRQ support */ typedef void SetIRQFunc(void *opaque, int irq_num, int level); typedef struct { SetIRQFunc *set_irq; void *opaque; int irq_num; } IRQSignal; void irq_init(IRQSignal *irq, SetIRQFunc *set_irq, void *opaque, int irq_num); static inline void set_irq(IRQSignal *irq, int level) { irq->set_irq(irq->opaque, irq->irq_num, level); } #endif /* IOMEM_H */
/* * Pseudo JSON parser * * Copyright (c) 2017 Fabrice Bellard * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #include <stdlib.h> #include <stdio.h> #include <stdarg.h> #include <string.h> #include <inttypes.h> #include <assert.h> #include <fcntl.h> #include <errno.h> #include <unistd.h> #include <time.h> #include <ctype.h> #include "cutils.h" #include "json.h" #include "fs_utils.h" static JSONValue parse_string(const char **pp) { char buf[4096], *q; const char *p; int c, h; q = buf; p = *pp; p++; for (;;) { c = *p++; if (c == '\0' || c == '\n') { return json_error_new("unterminated string"); } else if (c == '\"') { break; } else if (c == '\\') { c = *p++; switch (c) { case '\'': case '\"': case '\\': goto add_char; case 'n': c = '\n'; goto add_char; case 'r': c = '\r'; goto add_char; case 't': c = '\t'; goto add_char; case 'x': h = from_hex(*p++); if (h < 0) return json_error_new("invalid hex digit"); c = h << 4; h = from_hex(*p++); if (h < 0) return json_error_new("invalid hex digit"); c |= h; goto add_char; default: return json_error_new("unknown escape code"); } } else { add_char: if (q >= buf + sizeof(buf) - 1) return json_error_new("string too long"); *q++ = c; } } *q = '\0'; *pp = p; return json_string_new(buf); } static JSONProperty *json_object_get2(JSONObject *obj, const char *name) { JSONProperty *f; int i; for (i = 0; i < obj->len; i++) { f = &obj->props[i]; if (!strcmp(f->name.u.str->data, name)) return f; } return NULL; } JSONValue json_object_get(JSONValue val, const char *name) { JSONProperty *f; JSONObject *obj; if (val.type != JSON_OBJ) return json_undefined_new(); obj = val.u.obj; f = json_object_get2(obj, name); if (!f) return json_undefined_new(); return f->value; } int json_object_set(JSONValue val, const char *name, JSONValue prop_val) { JSONObject *obj; JSONProperty *f; int new_size; if (val.type != JSON_OBJ) return -1; obj = val.u.obj; f = json_object_get2(obj, name); if (f) { json_free(f->value); f->value = prop_val; } else { if (obj->len >= obj->size) { new_size = max_int(obj->len + 1, obj->size * 3 / 2); obj->props = (JSONProperty *)realloc(obj->props, new_size * sizeof(JSONProperty)); obj->size = new_size; } f = &obj->props[obj->len++]; f->name = json_string_new(name); f->value = prop_val; } return 0; } JSONValue json_array_get(JSONValue val, int idx) { JSONArray *array; if (val.type != JSON_ARRAY) return json_undefined_new(); array = val.u.array; if (idx < array->len) { return array->tab[idx]; } else { return json_undefined_new(); } } int json_array_set(JSONValue val, int idx, JSONValue prop_val) { JSONArray *array; int new_size; if (val.type != JSON_ARRAY) return -1; array = val.u.array; if (idx < array->len) { json_free(array->tab[idx]); array->tab[idx] = prop_val; } else if (idx == array->len) { if (array->len >= array->size) { new_size = max_int(array->len + 1, array->size * 3 / 2); array->tab = (JSONValue *)realloc(array->tab, new_size * sizeof(JSONValue)); array->size = new_size; } array->tab[array->len++] = prop_val; } else { return -1; } return 0; } const char *json_get_str(JSONValue val) { if (val.type != JSON_STR) return NULL; return val.u.str->data; } const char *json_get_error(JSONValue val) { if (val.type != JSON_EXCEPTION) return NULL; return val.u.str->data; } JSONValue json_string_new2(const char *str, int len) { JSONString *str1 = (JSONString *)malloc(sizeof(JSONString) + len + 1); str1->len = len; memcpy(str1->data, str, len + 1); JSONValue val; val.type = JSON_STR; val.u.str = str1; return val; } JSONValue json_string_new(const char *str) { return json_string_new2(str, strlen(str)); } JSONValue __attribute__((format(printf, 1, 2))) json_error_new(const char *fmt, ...) { JSONValue val; va_list ap; char buf[256]; va_start(ap, fmt); vsnprintf(buf, sizeof(buf), fmt, ap); va_end(ap); val = json_string_new(buf); val.type = JSON_EXCEPTION; return val; } JSONValue json_object_new(void) { JSONObject *obj = (JSONObject *)mallocz(sizeof(JSONObject)); JSONValue val; val.type = JSON_OBJ; val.u.obj = obj; return val; } JSONValue json_array_new(void) { JSONArray *array = (JSONArray *)mallocz(sizeof(JSONArray)); JSONValue val; val.type = JSON_ARRAY; val.u.array = array; return val; } void json_free(JSONValue val) { switch (val.type) { case JSON_STR: case JSON_EXCEPTION: free(val.u.str); break; case JSON_INT: case JSON_BOOL: case JSON_NULL: case JSON_UNDEFINED: break; case JSON_ARRAY: { JSONArray *array = val.u.array; int i; for (i = 0; i < array->len; i++) { json_free(array->tab[i]); } free(array); } break; case JSON_OBJ: { JSONObject *obj = val.u.obj; JSONProperty *f; int i; for (i = 0; i < obj->len; i++) { f = &obj->props[i]; json_free(f->name); json_free(f->value); } free(obj); } break; default: abort(); } } static void skip_spaces(const char **pp) { const char *p; p = *pp; for (;;) { if (isspace(*p)) { p++; } else if (p[0] == '/' && p[1] == '/') { p += 2; while (*p != '\0' && *p != '\n') p++; } else if (p[0] == '/' && p[1] == '*') { p += 2; while (*p != '\0' && (p[0] != '*' || p[1] != '/')) p++; if (*p != '\0') p += 2; } else { break; } } *pp = p; } static inline BOOL is_ident_first(int c) { return (c >= 'a' && c <= 'z') || (c >= 'A' && c <= 'Z') || c == '_' || c == '$'; } static int parse_ident(char *buf, int buf_size, const char **pp) { char *q; const char *p; p = *pp; q = buf; *q++ = *p++; /* first char is already tested */ while (is_ident_first(*p) || isdigit(*p)) { if ((q - buf) >= buf_size - 1) return -1; *q++ = *p++; } *pp = p; *q = '\0'; return 0; } JSONValue json_parse_value2(const char **pp) { char buf[128]; const char *p; JSONValue val, val1, tag; p = *pp; skip_spaces(&p); if (*p == '\0') { return json_error_new("unexpected end of file"); } if (*p == '0' && p[1] == 'x') { p += 2; val = json_int64_new(strtoll(p, (char **)&p, 16)); } else if (isdigit(*p)) { val = json_int64_new(strtoll(p, (char **)&p, 0)); } else if (*p == '"') { val = parse_string(&p); } else if (*p == '{') { p++; val = json_object_new(); for (;;) { skip_spaces(&p); if (*p == '}') { p++; break; } if (*p == '"') { tag = parse_string(&p); if (json_is_error(tag)) return tag; } else if (is_ident_first(*p)) { if (parse_ident(buf, sizeof(buf), &p) < 0) goto invalid_prop; tag = json_string_new(buf); } else { goto invalid_prop; } // fprintf(dromajo_stdout, "property: %s\n", json_get_str(tag)); if (tag.u.str->len == 0) { invalid_prop: return json_error_new("Invalid property name"); } skip_spaces(&p); if (*p != ':') { return json_error_new("':' expected"); } p++; val1 = json_parse_value2(&p); json_object_set(val, tag.u.str->data, val1); skip_spaces(&p); if (*p == ',') { p++; } else if (*p != '}') { return json_error_new("expecting ',' or '}'"); } } } else if (*p == '[') { int idx; p++; val = json_array_new(); idx = 0; for (;;) { skip_spaces(&p); if (*p == ']') { p++; break; } val1 = json_parse_value2(&p); json_array_set(val, idx++, val1); skip_spaces(&p); if (*p == ',') { p++; } else if (*p != ']') { return json_error_new("expecting ',' or ']'"); } } } else if (is_ident_first(*p)) { if (parse_ident(buf, sizeof(buf), &p) < 0) goto unknown_id; if (!strcmp(buf, "null")) { val = json_null_new(); } else if (!strcmp(buf, "true")) { val = json_bool_new(TRUE); } else if (!strcmp(buf, "false")) { val = json_bool_new(FALSE); } else { unknown_id: return json_error_new("unknown identifier: '%s'", buf); } } else { return json_error_new("unexpected character"); } *pp = p; return val; } JSONValue json_parse_value(const char *p) { JSONValue val; val = json_parse_value2(&p); if (json_is_error(val)) return val; skip_spaces(&p); if (*p != '\0') { json_free(val); return json_error_new("unexpected characters at the end"); } return val; } JSONValue json_parse_value_len(const char *p, int len) { char *str = (char *)malloc(len + 1); memcpy(str, p, len); str[len] = '\0'; JSONValue val = json_parse_value(str); free(str); return val; }
/* * Pseudo JSON parser * * Copyright (c) 2017 Fabrice Bellard * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #ifndef JSON_H #define JSON_H #include <stdint.h> #include "cutils.h" typedef enum { JSON_STR, JSON_INT, JSON_OBJ, JSON_ARRAY, JSON_BOOL, JSON_NULL, JSON_UNDEFINED, JSON_EXCEPTION, } JSONTypeEnum; typedef struct { int len; char data[0]; } JSONString; typedef struct JSONValue { JSONTypeEnum type; union { JSONString *str; int64_t int64; BOOL b; struct JSONObject *obj; struct JSONArray *array; } u; } JSONValue; typedef struct JSONProperty { JSONValue name; JSONValue value; } JSONProperty; typedef struct JSONObject { int len; int size; JSONProperty *props; } JSONObject; typedef struct JSONArray { int len; int size; JSONValue *tab; } JSONArray; JSONValue json_string_new2(const char *str, int len); JSONValue json_string_new(const char *str); JSONValue __attribute__((format(printf, 1, 2))) json_error_new(const char *fmt, ...); void json_free(JSONValue val); JSONValue json_object_new(void); JSONValue json_object_get(JSONValue val, const char *name); int json_object_set(JSONValue val, const char *name, JSONValue prop_val); JSONValue json_array_new(void); JSONValue json_array_get(JSONValue val, int idx); int json_array_set(JSONValue val, int idx, JSONValue prop_val); static inline BOOL json_is_error(JSONValue val) { return val.type == JSON_EXCEPTION; } static inline BOOL json_is_undefined(JSONValue val) { return val.type == JSON_UNDEFINED; } static inline JSONValue json_undefined_new(void) { JSONValue val; val.type = JSON_UNDEFINED; val.u.int64 = 0; return val; } static inline JSONValue json_null_new(void) { JSONValue val; val.type = JSON_NULL; val.u.int64 = 0; return val; } static inline JSONValue json_int64_new(int64_t v) { JSONValue val; val.type = JSON_INT; val.u.int64 = v; return val; } static inline JSONValue json_bool_new(BOOL v) { JSONValue val; val.type = JSON_BOOL; val.u.b = v; return val; } const char *json_get_str(JSONValue val); const char *json_get_error(JSONValue val); JSONValue json_parse_value(const char *p); JSONValue json_parse_value_len(const char *p, int len); #endif /* JSON_H */
/* * Linux klist like system * * Copyright (c) 2016-2017 Fabrice Bellard * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #ifndef LIST_H #define LIST_H struct list_head { struct list_head *prev; struct list_head *next; }; /* return the pointer of type 'type *' containing 'el' as field 'member' */ #define list_entry(el, type, member) \ ((type *)((uint8_t *)(el) - offsetof(type, member))) static inline void init_list_head(struct list_head *head) { head->prev = head; head->next = head; } /* insert 'el' between 'prev' and 'next' */ static inline void __list_add(struct list_head *el, struct list_head *prev, struct list_head *next) { prev->next = el; el->prev = prev; el->next = next; next->prev = el; } /* add 'el' at the head of the list 'head' (= after element head) */ static inline void list_add(struct list_head *el, struct list_head *head) { __list_add(el, head, head->next); } /* add 'el' at the end of the list 'head' (= before element head) */ static inline void list_add_tail(struct list_head *el, struct list_head *head) { __list_add(el, head->prev, head); } static inline void list_del(struct list_head *el) { struct list_head *prev, *next; prev = el->prev; next = el->next; prev->next = next; next->prev = prev; el->prev = NULL; /* fail safe */ el->next = NULL; /* fail safe */ } static inline int list_empty(struct list_head *el) { return el->next == el; } #define list_for_each(el, head) \ for (el = (head)->next; el != (head); el = el->next) #define list_for_each_safe(el, el1, head) \ for (el = (head)->next, el1 = el->next; el != (head); \ el = el1, el1 = el->next) #define list_for_each_prev(el, head) \ for (el = (head)->prev; el != (head); el = el->prev) #define list_for_each_prev_safe(el, el1, head) \ for (el = (head)->prev, el1 = el->prev; el != (head); \ el = el1, el1 = el->prev) #endif /* LIST_H */
// Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // // THIS FILE IS BASED ON ESESC SOURCE CODE WHICH IS DISTRIBUTED UNDER // THE FOLLOWING LICENSE: // // copyright and includes {{{1 // Contributed by Sina Hassani // Jose Renau // // The ESESC/BSD License // // Copyright (c) 2005-2015, Regents of the University of California and // the ESESC Project. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // // - Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. // // - Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. // // - Neither the name of the University of California, Santa Cruz nor the // names of its contributors may be used to endorse or promote products // derived from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. #include "LiveCacheCore.h" //#define MTRACE(a...) do{ fprintf(stderr,"@%lld %s %d 0x%x:",(long long int)globalClock,getName(), (int)mreq->getID(), (unsigned // int)mreq->getAddr()); fprintf(stderr,##a); fprintf(stderr,"\n"); }while(0) #define MTRACE(a...) LiveCache::LiveCache(const std::string &_name, int size) :name(_name) { cacheBank = CacheType::create(size, 16, 64, "LRU", false); lineSize = cacheBank->getLineSize(); lineSizeBits = log2i(lineSize); nReadHit = 0; nReadMiss = 0; nWriteHit = 0; nWriteMiss = 0; assert(getLineSize() < 4096); // To avoid bank selection conflict (insane LiveCache line) lineCount = (uint64_t)cacheBank->getNumLines(); maxOrder = 0; } LiveCache::~LiveCache() { if (nWriteMiss==0 && nWriteHit==0) nWriteMiss = 1; if (nReadMiss==0 && nReadHit==0) nReadMiss = 1; fprintf(stderr,"%s nReadHit:%lld nReadMiss:%lld nReadMissRate:%3.1f%% nWriteHit:%lld nWriteMiss:%lld nWriteMissRate:%3.1f%%\n" ,name.c_str() ,nReadHit ,nReadMiss ,100.0*((double)nReadMiss)/(nReadHit+nReadMiss) ,nWriteHit ,nWriteMiss ,100.0*((double)nWriteMiss)/(nWriteHit+nWriteMiss) ); cacheBank->destroy(); } void LiveCache::read(uint64_t addr) { Line *l = cacheBank->findLine(addr); if(l) { l->order = maxOrder++; nReadHit++; return; } nReadMiss++; l = cacheBank->fillLine(addr); l->st = false; l->order = maxOrder++; } void LiveCache::write(uint64_t addr) { Line *l = cacheBank->findLine(addr); if(l) { l->order = maxOrder++; l->st = true; nWriteHit++; return; } nWriteMiss++; l = cacheBank->fillLine(addr); l->st = true; l->order = maxOrder++; } uint64_t *LiveCache::traverse(int &n_entries) { // Creating an array of cache lines Line * arr[lineCount]; uint64_t cnt = 0; for(uint64_t i = 0; i < lineCount; i++) { if(cacheBank->getPLine(i) && cacheBank->getPLine(i)->order) { arr[cnt] = cacheBank->getPLine(i); cnt++; } } mergeSort(arr, cnt); uint64_t *addrs = (uint64_t *)malloc(sizeof(uint64_t)*cnt); // creating loads and stores arrays uint64_t in = 0; for(uint64_t i = 0; i < cnt; i++) { if(!arr[i]->getTag()) continue; if (arr[i]->st) { addrs[in] = 1 | (uint64_t)cacheBank->calcAddr4Tag(arr[i]->getTag()); }else{ addrs[in] = (uint64_t)cacheBank->calcAddr4Tag(arr[i]->getTag()); assert((addrs[in]&1)==0); } in++; } n_entries = in; return addrs; } void LiveCache::mergeSort(Line **arr, uint64_t len) { // in case we had one element if(len < 2) return; // in case we had two elements if(len == 2) { if(arr[0]->order > arr[1]->order) { // swap Line *t = arr[0]; arr[0] = arr[1]; arr[1] = t; } return; } // divide and conquer uint64_t mid = (uint64_t)(len / 2); Line * arr1[mid]; Line * arr2[len - mid]; for(uint64_t i = 0; i < mid; i++) arr1[i] = arr[i]; for(uint64_t i = 0; i < len - mid; i++) arr2[i] = arr[mid + i]; mergeSort(arr1, mid); mergeSort(arr2, len - mid); // merging uint64_t m = 0; uint64_t n = 0; for(uint64_t i = 0; i < len; i++) { if(n >= (len - mid) || (m < mid && arr1[m]->order <= arr2[n]->order)) { arr[i] = arr1[m]; m++; } else { arr[i] = arr2[n]; n++; } } }
// Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // // THIS FILE IS BASED ON ESESC SOURCE CODE WHICH IS DISTRIBUTED UNDER // THE FOLLOWING LICENSE: // // copyright and includes {{{1 // Contributed by Sina Hassani // Jose Renau // // The ESESC/BSD License // // Copyright (c) 2005-2015, Regents of the University of California and // the ESESC Project. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // // - Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. // // - Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. // // - Neither the name of the University of California, Santa Cruz nor the // names of its contributors may be used to endorse or promote products // derived from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. #ifndef LiveCache_H #define LiveCache_H #include <stdint.h> #include <assert.h> #include <stdint.h> #include <stdio.h> #include <stdlib.h> #include <string.h> #include <unistd.h> #include <limits.h> #include <string> class LiveCache { protected: class CState : public StateGeneric<uint64_t> { private: enum StateType { M, E, S, I }; StateType state; public: bool st; uint64_t order; CState() { state = I; clearTag(); } bool isModified() const { return state == M; } void setModified() { state = M; } bool isValid() const { return state != I; } bool isInvalid() const { return state == I; } StateType getState() const { return state; }; void invalidate() { state = I; } }; typedef CacheGeneric<CState, uint64_t> CacheType; typedef CacheGeneric<CState, uint64_t>::CacheLine Line; const std::string name; CacheType *cacheBank; int32_t lineSize; int32_t lineSizeBits; uint64_t lineCount; uint64_t maxOrder; long long nReadHit; long long nReadMiss; long long nWriteHit; long long nWriteMiss; void mergeSort(Line **arr, uint64_t len); public: LiveCache(const std::string &_name, int size); virtual ~LiveCache(); int32_t getLineSize() const { return lineSize; } void read(uint64_t addr); void write(uint64_t addr); uint64_t *traverse(int &n_entries); }; #endif
// Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. // You may obtain a copy of the License at // // http://www.apache.org/licenses/LICENSE-2.0 // // Unless required by applicable law or agreed to in writing, software // distributed under the License is distributed on an "AS IS" BASIS, // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. // See the License for the specific language governing permissions and // limitations under the License. // // THIS FILE IS BASED ON ESESC SOURCE CODE WHICH IS DISTRIBUTED UNDER // THE FOLLOWING LICENSE: // // Contributed by Jose Renau // Basilio Fraguela // James Tuck // Milos Prvulovic // Smruti Sarangi // // The ESESC/BSD License // // Copyright (c) 2005-2013, Regents of the University of California and // the ESESC Project. // All rights reserved. // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are met: // // - Redistributions of source code must retain the above copyright notice, // this list of conditions and the following disclaimer. // // - Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the distribution. // // - Neither the name of the University of California, Santa Cruz nor the // names of its contributors may be used to endorse or promote products // derived from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE // POSSIBILITY OF SUCH DAMAGE. #ifndef LIVECACHECORE_H #define LIVECACHECORE_H #include <vector> #include <stdlib.h> #include <stdio.h> #include <stdint.h> #include <assert.h> #include <stdarg.h> #include <string.h> #include <strings.h> //------------------------------------------------------------- #define RRIP_M 4 // max value = 2^M | 4 | 8 | 16 | //------------------------------------------------------------- #define DISTANT_REF 3 // 2^M - 1 | 3 | 7 | 15 | #define IMM_REF 1 // nearimm<imm<dist | 1 | 1-6 | 1-14 | #define NEAR_IMM_REF 0 // 0 | 0 | 0 | 0 | #define LONG_REF 1 // 2^M - 2 | 1 | 6 | 14 | //------------------------------------------------------------- static inline uint32_t roundUpPower2(uint32_t x) { // efficient branchless code extracted from "Hacker's Delight" by // Henry S. Warren, Jr. x = x - 1; x = x | (x >> 1); x = x | (x >> 2); x = x | (x >> 4); x = x | (x >> 8); x = x | (x >> 16); return x + 1; } static inline short log2i(uint32_t n) { uint32_t m = 1; uint32_t i = 0; if(n == 1) return 0; n = roundUpPower2(n); // assume integer power of 2 assert((n & (n - 1)) == 0); while(m < n) { i++; m <<= 1; } return i; } enum ReplacementPolicy { LRU, LRUp, RANDOM}; template<class State, class Addr_t> class CacheGeneric { private: static const int32_t STR_BUF_SIZE = 1024; protected: const uint32_t size; const uint32_t lineSize; const uint32_t assoc; const uint32_t log2Assoc; const uint64_t log2AddrLs; const uint64_t maskAssoc; const uint32_t sets; const uint32_t maskSets; const uint32_t log2Sets; const uint32_t numLines; const bool xorIndex; bool goodInterface; public: class CacheLine : public State { public: CacheLine() { } // Pure virtual class defines interface // // Tag included in state. Accessed through: // // Addr_t getTag() const; // void setTag(Addr_t a); // void clearTag(); // // // bool isValid() const; // void invalidate(); }; // findLine returns a cache line that has tag == addr, NULL otherwise virtual CacheLine *findLinePrivate(Addr_t addr) = 0; protected: CacheGeneric(uint32_t s, uint32_t a, uint32_t b, bool xr) : size(s) , lineSize(b) , assoc(a) , log2Assoc(log2i(a)) , log2AddrLs(log2i(b)) , maskAssoc(a - 1) , sets((s / b) / a) , maskSets(sets - 1) , log2Sets(log2i(sets)) , numLines(s / b) , xorIndex(xr) { // TODO : assoc and sets must be a power of 2 } virtual ~CacheGeneric() { } public: // Do not use this interface, use other create static CacheGeneric<State, Addr_t> *create(int32_t size, int32_t assoc, int32_t blksize, const char *pStr, bool xr); void destroy() { delete this; } virtual CacheLine *findLine2Replace(Addr_t addr) = 0; // TO DELETE if flush from Cache.cpp is cleared. At least it should have a // cleaner interface so that Cache.cpp does not touch the internals. // // Access the line directly without checking TAG virtual CacheLine *getPLine(uint32_t l) = 0; // ALL USERS OF THIS CLASS PLEASE READ: // // readLine and writeLine MUST have the same functionality as findLine. The only // difference is that readLine and writeLine update power consumption // statistics. So, only use these functions when you want to model a physical // read or write operation. // Use this is for debug checks. Otherwise, a bad interface can be detected CacheLine *findLineDebug(Addr_t addr) { IS(goodInterface = true); CacheLine *line = findLine(addr); IS(goodInterface = false); return line; } CacheLine *findLineNoEffect(Addr_t addr) { IS(goodInterface = true); CacheLine *line = findLine(addr); IS(goodInterface = false); return line; } CacheLine *findLine(Addr_t addr) { return findLinePrivate(addr); } CacheLine *readLine(Addr_t addr) { IS(goodInterface = true); CacheLine *line = findLine(addr); IS(goodInterface = false); return line; } CacheLine *writeLine(Addr_t addr) { IS(goodInterface = true); CacheLine *line = findLine(addr); IS(goodInterface = false); return line; } CacheLine *fillLine(Addr_t addr) { CacheLine *l = findLine2Replace(addr); assert(l); l->setTag(calcTag(addr)); return l; } CacheLine *fillLine(Addr_t addr, Addr_t &rplcAddr) { CacheLine *l = findLine2Replace(addr); assert(l); rplcAddr = 0; Addr_t newTag = calcTag(addr); if(l->isValid()) { Addr_t curTag = l->getTag(); if(curTag != newTag) { rplcAddr = calcAddr4Tag(curTag); } } l->setTag(newTag); return l; } uint32_t getLineSize() const { return lineSize; } uint32_t getAssoc() const { return assoc; } uint32_t getLog2AddrLs() const { return log2AddrLs; } uint32_t getLog2Assoc() const { return log2Assoc; } uint32_t getMaskSets() const { return maskSets; } uint32_t getNumLines() const { return numLines; } uint32_t getNumSets() const { return sets; } Addr_t calcTag(Addr_t addr) const { return (addr >> log2AddrLs); } // Addr_t calcSet4Tag(Addr_t tag) const { return (tag & maskSets); } // Addr_t calcSet4Addr(Addr_t addr) const { return calcSet4Tag(calcTag(addr)); } // Addr_t calcIndex4Set(Addr_t set) const { return (set << log2Assoc); } // Addr_t calcIndex4Tag(Addr_t tag) const { return calcIndex4Set(calcSet4Tag(tag)); } // uint32_t calcIndex4Addr(Addr_t addr) const { return calcIndex4Set(calcSet4Addr(addr)); } Addr_t calcIndex4Tag(Addr_t tag) const { Addr_t set; if(xorIndex) { tag = tag ^ (tag >> log2Sets); // Addr_t odd = (tag&1) | ((tag>>2) & 1) | ((tag>>4)&1) | ((tag>>6)&1) | ((tag>>8)&1) | ((tag>>10)&1) | ((tag>>12)&1) | // ((tag>>14)&1) | ((tag>>16)&1) | ((tag>>18)&1) | ((tag>>20)&1); // over 20 bit index??? set = tag & maskSets; } else { set = tag & maskSets; } Addr_t index = set << log2Assoc; return index; } Addr_t calcAddr4Tag(Addr_t tag) const { return (tag << log2AddrLs); } }; template <class State, class Addr_t> class CacheAssoc : public CacheGeneric<State, Addr_t> { using CacheGeneric<State, Addr_t>::numLines; using CacheGeneric<State, Addr_t>::assoc; using CacheGeneric<State, Addr_t>::maskAssoc; using CacheGeneric<State, Addr_t>::goodInterface; private: public: typedef typename CacheGeneric<State, Addr_t>::CacheLine Line; protected: Line *mem; Line **content; uint16_t irand; ReplacementPolicy policy; friend class CacheGeneric<State, Addr_t>; CacheAssoc(int32_t size, int32_t assoc, int32_t blksize, const char *pStr, bool xr); Line *findLinePrivate(Addr_t addr); public: virtual ~CacheAssoc() { } // TODO: do an iterator. not this junk!! Line *getPLine(uint32_t l) { // Lines [l..l+assoc] belong to the same set assert(l < numLines); return content[l]; } Line *findLine2Replace(Addr_t addr); }; template <class State, class Addr_t> class CacheDM : public CacheGeneric<State, Addr_t> { using CacheGeneric<State, Addr_t>::numLines; using CacheGeneric<State, Addr_t>::goodInterface; private: public: typedef typename CacheGeneric<State, Addr_t>::CacheLine Line; protected: Line *mem; Line **content; friend class CacheGeneric<State, Addr_t>; CacheDM(int32_t size, int32_t blksize, const char *pStr, bool xr); Line *findLinePrivate(Addr_t addr); public: virtual ~CacheDM() { }; // TODO: do an iterator. not this junk!! Line *getPLine(uint32_t l) { // Lines [l..l+assoc] belong to the same set assert(l < numLines); return content[l]; } Line *findLine2Replace(Addr_t addr); }; template <class Addr_t> class StateGeneric { private: Addr_t tag; public: virtual ~StateGeneric() { tag = 0; } Addr_t getTag() const { return tag; } void setTag(Addr_t a) { assert(a); tag = a; } void clearTag() { tag = 0; } void initialize(void *c) { clearTag(); } virtual bool isValid() const { return tag; } virtual void invalidate() { clearTag(); } virtual void dump(const char *str) { } Addr_t getSignature() const { return 0; } void setSignature(Addr_t a) { assert(0); } bool getOutcome() const { return 0; } void setOutcome(bool a) { assert(0); } uint8_t getRRPV() const { return 0; } void setRRPV(uint8_t a) { assert(0); } void incRRPV() { assert(0); } }; #include "LiveCache.h" #define k_RANDOM "RANDOM" #define k_LRU "LRU" #define k_LRUp "LRUp" // // Class CacheGeneric, the combinational logic of Cache // template <class State, class Addr_t> CacheGeneric<State, Addr_t> *CacheGeneric<State, Addr_t>::create(int32_t size, int32_t assoc, int32_t bsize, const char *pStr, bool xr) { CacheGeneric *cache; if(assoc == 1) { cache = new CacheDM<State, Addr_t>(size, bsize, pStr, xr); } else { cache = new CacheAssoc<State, Addr_t>(size, assoc, bsize, pStr, xr); } assert(cache); return cache; } /********************************************************* * CacheAssoc *********************************************************/ template <class State, class Addr_t> CacheAssoc<State, Addr_t>::CacheAssoc(int32_t size, int32_t assoc, int32_t blksize, const char *pStr, bool xr) : CacheGeneric<State, Addr_t>(size, assoc, blksize, xr) { assert(numLines > 0); assert((int32_t)numLines > assoc); if(strcasecmp(pStr, k_RANDOM) == 0) policy = RANDOM; else if(strcasecmp(pStr, k_LRU) == 0) policy = LRU; else if(strcasecmp(pStr, k_LRUp) == 0) policy = LRUp; else { fprintf(stderr,"Invalid cache policy [%s]\n", pStr); exit(0); } mem = (Line *)malloc(sizeof(Line) * (numLines + 1)); for(uint32_t i = 0; i < numLines; i++) { new (&mem[i]) Line; } content = new Line *[numLines + 1]; for(uint32_t i = 0; i < numLines; i++) { mem[i].initialize(this); mem[i].invalidate(); content[i] = &mem[i]; } irand = 0; } template <class State, class Addr_t> typename CacheAssoc<State, Addr_t>::Line *CacheAssoc<State, Addr_t>::findLinePrivate(Addr_t addr) { Addr_t tag = this->calcTag(addr); Line **theSet = &content[this->calcIndex4Tag(tag)]; // Check most typical case if((*theSet)->getTag() == tag) { return *theSet; } Line **lineHit = 0; Line **setEnd = theSet + assoc; // For sure that position 0 is not (short-cut) { Line **l = theSet + 1; while(l < setEnd) { if((*l)->getTag() == tag) { lineHit = l; break; } l++; } } if(lineHit == 0) return 0; Line *tmp = *lineHit; { Line **l = lineHit; while(l > theSet) { Line **prev = l - 1; *l = *prev; ; l = prev; } *theSet = tmp; } return tmp; } template <class State, class Addr_t> typename CacheAssoc<State, Addr_t>::Line *CacheAssoc<State, Addr_t>::findLine2Replace(Addr_t addr) { Addr_t tag = this->calcTag(addr); assert(tag); Line **theSet = &content[this->calcIndex4Tag(tag)]; // Check most typical case if((*theSet)->getTag() == tag) { // GI(tag,(*theSet)->isValid()); //TODO: why is this assertion failing return *theSet; } Line **lineHit = 0; Line **lineFree = 0; // Order of preference, invalid Line **setEnd = theSet + assoc; { Line **l = setEnd - 1; while(l >= theSet) { if((*l)->getTag() == tag) { lineHit = l; break; } if(!(*l)->isValid()) lineFree = l; else if(lineFree == 0) lineFree = l; l--; } } Line * tmp; Line **tmp_pos; if(!lineHit) { assert(lineFree); if(policy == RANDOM) { lineFree = &theSet[irand]; irand = (irand + 1) & maskAssoc; if(irand == 0) irand = (irand + 1) & maskAssoc; // Not MRU } else { assert(policy == LRU || policy == LRUp); // Get the oldest line possible lineFree = setEnd - 1; } assert(lineFree); if(lineFree == theSet) return *lineFree; // Hit in the first possition tmp = *lineFree; tmp_pos = lineFree; } else { tmp = *lineHit; tmp_pos = lineHit; } if(policy == LRUp) { #if 0 Line **l = tmp_pos; while(l > &theSet[13]) { Line **prev = l - 1; *l = *prev;; l = prev; } theSet[13] = tmp; #endif } else { Line **l = tmp_pos; while(l > theSet) { Line **prev = l - 1; *l = *prev; ; l = prev; } *theSet = tmp; } return tmp; } /********************************************************* * CacheDM *********************************************************/ template <class State, class Addr_t> CacheDM<State, Addr_t>::CacheDM(int32_t size, int32_t blksize, const char *pStr, bool xr) : CacheGeneric<State, Addr_t>(size, 1, blksize, xr) { assert(numLines > 0); mem = (Line *)malloc(sizeof(Line) * (numLines + 1)); for(uint32_t i = 0; i < numLines; i++) { new (&mem[i]) Line; } content = new Line *[numLines + 1]; for(uint32_t i = 0; i < numLines; i++) { mem[i].initialize(this); mem[i].invalidate(); content[i] = &mem[i]; } } template <class State, class Addr_t> typename CacheDM<State, Addr_t>::Line *CacheDM<State, Addr_t>::findLinePrivate(Addr_t addr) { Addr_t tag = this->calcTag(addr); assert(tag); Line *line = content[this->calcIndex4Tag(tag)]; if(line->getTag() == tag) { assert(line->isValid()); return line; } return 0; } template <class State, class Addr_t> typename CacheDM<State, Addr_t>::Line *CacheDM<State, Addr_t>::findLine2Replace(Addr_t addr) { Addr_t tag = this->calcTag(addr); Line * line = content[this->calcIndex4Tag(tag)]; return line; } #endif // LIVECACHECORE_H
/* * VM utilities * * Copyright (c) 2017 Fabrice Bellard * Copyright (C) 2017,2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #include "dromajo.h" #include <stdlib.h> #include <stdint.h> #include <stdarg.h> #include <string.h> #include <inttypes.h> #include <assert.h> #include <fcntl.h> #include <errno.h> #include <unistd.h> #include <time.h> #include "cutils.h" #include "iomem.h" #include "virtio.h" #include "fs_utils.h" #ifdef CONFIG_FS_NET #include "fs_wget.h" #endif #include "riscv_machine.h" #include "elf64.h" void __attribute__((format(printf, 1, 2))) vm_error(const char *fmt, ...) { va_list ap; va_start(ap, fmt); vfprintf(dromajo_stderr, fmt, ap); va_end(ap); } int vm_get_int(JSONValue obj, const char *name, int64_t *pval) { JSONValue val = json_object_get(obj, name); if (json_is_undefined(val)) { vm_error("expecting '%s' property\n", name); return -1; } if (val.type != JSON_INT) { vm_error("%s: integer expected\n", name); return -1; } *pval = val.u.int64; return 0; } int vm_get_mmio_addrset_opt(JSONValue obj, VirtMachineParams *p) { JSONValue val = json_object_get(obj, "mmio_addrset"); if (json_is_undefined(val)) return 0; if (val.type != JSON_ARRAY) { vm_error("%s: array expected\n", "mmio_addrset"); return -1; } uint64_t mmio_addrset_size = val.u.array->len; AddressSet *mmio_addrset = (AddressSet *)mallocz(sizeof(AddressSet)*mmio_addrset_size); for (int i = 0; i < val.u.array->len; ++i) { JSONValue obj = json_array_get(val, i); vm_get_int(obj, "start", (int64_t*)&mmio_addrset[i].start); vm_get_int(obj, "size",(int64_t*)&mmio_addrset[i].size); } p->mmio_addrset = mmio_addrset; p->mmio_addrset_size = mmio_addrset_size; return 0; } int vm_get_missing_csrs_opt(JSONValue obj, VirtMachineParams *p) { JSONValue val = json_object_get(obj, "missing_csrs"); if (json_is_undefined(val)) return 0; if (val.type != JSON_ARRAY) { vm_error("%s: array expected\n", "missing_csrs"); return -1; } uint64_t array_size = val.u.array->len; uint64_t* array_ptr = (uint64_t*)mallocz(sizeof(uint64_t)*array_size); for (uint64_t i = 0; i < array_size; i++) { JSONValue obj = json_array_get(val, i); array_ptr[i] = obj.u.int64; } p->missing_csrs = array_ptr; p->missing_csrs_size = array_size; return 0; } int vm_get_skip_commit_opt(JSONValue obj, VirtMachineParams *p) { JSONValue val = json_object_get(obj, "skip_commit"); if (json_is_undefined(val)) return 0; if (val.type != JSON_ARRAY) { vm_error("%s: array expected\n", "skip_commit"); return -1; } uint64_t array_size = val.u.array->len; uint64_t* array_ptr = (uint64_t*)mallocz(sizeof(uint64_t)*array_size); for (uint64_t i = 0; i < array_size; i++) { JSONValue obj = json_array_get(val, i); array_ptr[i] = obj.u.int64; } p->skip_commit = array_ptr; p->skip_commit_size = array_size; return 0; } static void vm_get_uint64_opt(JSONValue obj, const char *name, uint64_t *pval) { JSONValue val = json_object_get(obj, name); if (json_is_undefined(val)) return; if (val.type != JSON_INT) { vm_error("%s: integer expected\n", name); return; } *pval = (uint64_t)val.u.int64; } static int vm_get_str2(JSONValue obj, const char *name, const char **pstr, BOOL is_opt) { JSONValue val; val = json_object_get(obj, name); if (json_is_undefined(val)) { if (is_opt) { *pstr = NULL; return 0; } else { vm_error("expecting '%s' property\n", name); return -1; } } if (val.type != JSON_STR) { vm_error("%s: string expected\n", name); return -1; } *pstr = val.u.str->data; return 0; } static int vm_get_str(JSONValue obj, const char *name, const char **pstr) { return vm_get_str2(obj, name, pstr, FALSE); } static int vm_get_str_opt(JSONValue obj, const char *name, const char **pstr) { return vm_get_str2(obj, name, pstr, TRUE); } static char *strdup_null(const char *str) { if (!str) return NULL; else return strdup(str); } /* currently only for "TZ" */ static char *cmdline_subst(const char *cmdline) { DynBuf dbuf; const char *p; char var_name[32], *q, buf[32]; dbuf_init(&dbuf); p = cmdline; while (*p != '\0') { if (p[0] == '$' && p[1] == '{') { p += 2; q = var_name; while (*p != '\0' && *p != '}') { if ((q - var_name) < (int)sizeof(var_name) - 1) *q++ = *p; p++; } *q = '\0'; if (*p == '}') p++; if (!strcmp(var_name, "TZ")) { time_t ti; struct tm tm; int n, sg; /* get the offset to UTC */ time(&ti); localtime_r(&ti, &tm); n = tm.tm_gmtoff / 60; sg = '-'; if (n < 0) { sg = '+'; n = -n; } snprintf(buf, sizeof(buf), "UTC%c%02d:%02d", sg, n / 60, n % 60); dbuf_putstr(&dbuf, buf); } } else { dbuf_putc(&dbuf, *p++); } } dbuf_putc(&dbuf, 0); return (char *)dbuf.buf; } static int virt_machine_parse_config(VirtMachineParams *p, char *config_file_str, int len) { int64_t version, val; const char *tag_name, *machine_name, *str; char buf1[256]; JSONValue cfg, obj, el; p->maxinsns = 0; p->dump_memories = false; cfg = json_parse_value_len(config_file_str, len); if (json_is_error(cfg)) { vm_error("error: %s\n", json_get_error(cfg)); json_free(cfg); return -1; } if (vm_get_int(cfg, "version", &version) < 0) goto tag_fail; if (version != VM_CONFIG_VERSION) { if (version > VM_CONFIG_VERSION) { vm_error("The emulator is too old to run this VM: please upgrade\n"); return -1; } else { vm_error("The VM configuration file is too old for this emulator version: please upgrade the VM configuration file\n"); return -1; } } if (vm_get_str(cfg, "machine", &str) < 0) goto tag_fail; machine_name = virt_machine_get_name(); if (strcmp(machine_name, str) != 0) { vm_error("Unsupported machine: '%s' (running machine is '%s')\n", str, machine_name); return -1; } vm_get_uint64_opt(cfg, "memory_base_addr", &p->ram_base_addr); tag_name = "memory_size"; if (vm_get_int(cfg, tag_name, &val) < 0) goto tag_fail; p->ram_size = (size_t)val << 20; tag_name = "bios"; if (vm_get_str_opt(cfg, tag_name, &str) < 0) goto tag_fail; if (str) { p->files[VM_FILE_BIOS].filename = strdup(str); } tag_name = "kernel"; if (vm_get_str_opt(cfg, tag_name, &str) < 0) goto tag_fail; if (str) { p->files[VM_FILE_KERNEL].filename = strdup(str); } tag_name = "initrd"; if (vm_get_str_opt(cfg, tag_name, &str) < 0) goto tag_fail; if (str) { p->files[VM_FILE_INITRD].filename = strdup(str); } if (vm_get_str_opt(cfg, "cmdline", &str) < 0) goto tag_fail; if (str) { p->cmdline = cmdline_subst(str); } if (vm_get_missing_csrs_opt(cfg, p) < 0) goto tag_fail; if (vm_get_skip_commit_opt(cfg, p) < 0) goto tag_fail; vm_get_uint64_opt(cfg, "htif_base_addr", &p->htif_base_addr); vm_get_uint64_opt(cfg, "maxinsns", &p->maxinsns); // checkpoint file path p->snapshot_load_name = NULL; tag_name = "load"; str = NULL; if (vm_get_str_opt(cfg, tag_name, &str) == 0 && str != NULL) { p->snapshot_load_name = strdup(str); } for (;;) { snprintf(buf1, sizeof(buf1), "drive%d", p->drive_count); obj = json_object_get(cfg, buf1); if (json_is_undefined(obj)) break; if (p->drive_count >= MAX_DRIVE_DEVICE) { vm_error("Too many drives\n"); return -1; } if (vm_get_str(obj, "file", &str) < 0) goto tag_fail; p->tab_drive[p->drive_count].filename = strdup(str); if (vm_get_str_opt(obj, "device", &str) < 0) goto tag_fail; p->tab_drive[p->drive_count].device = strdup_null(str); p->drive_count++; } for (;;) { snprintf(buf1, sizeof(buf1), "fs%d", p->fs_count); obj = json_object_get(cfg, buf1); if (json_is_undefined(obj)) break; if (p->fs_count >= MAX_DRIVE_DEVICE) { vm_error("Too many filesystems\n"); return -1; } if (vm_get_str(obj, "file", &str) < 0) goto tag_fail; p->tab_fs[p->fs_count].filename = strdup(str); if (vm_get_str_opt(obj, "tag", &str) < 0) goto tag_fail; if (!str) { if (p->fs_count == 0) strcpy(buf1, "/dev/root"); else snprintf(buf1, sizeof(buf1), "/dev/root%d", p->fs_count); str = buf1; } p->tab_fs[p->fs_count].tag = strdup(str); p->fs_count++; } for (;;) { snprintf(buf1, sizeof(buf1), "eth%d", p->eth_count); obj = json_object_get(cfg, buf1); if (json_is_undefined(obj)) break; if (p->eth_count >= MAX_ETH_DEVICE) { vm_error("Too many ethernet interfaces\n"); return -1; } if (vm_get_str(obj, "driver", &str) < 0) goto tag_fail; p->tab_eth[p->eth_count].driver = strdup(str); if (!strcmp(str, "tap")) { if (vm_get_str(obj, "ifname", &str) < 0) goto tag_fail; p->tab_eth[p->eth_count].ifname = strdup(str); } p->eth_count++; } p->display_device = NULL; obj = json_object_get(cfg, "display0"); if (!json_is_undefined(obj)) { if (vm_get_str(obj, "device", &str) < 0) goto tag_fail; p->display_device = strdup(str); if (vm_get_int(obj, "width", &p->width) < 0) goto tag_fail; if (vm_get_int(obj, "height", &p->height) < 0) goto tag_fail; if (vm_get_str_opt(obj, "vga_bios", &str) < 0) goto tag_fail; if (str) { p->files[VM_FILE_VGA_BIOS].filename = strdup(str); } } if (vm_get_str_opt(cfg, "input_device", &str) < 0) goto tag_fail; p->input_device = strdup_null(str); if (vm_get_str_opt(cfg, "accel", &str) < 0) goto tag_fail; if (str) { if (!strcmp(str, "none")) { p->accel_enable = FALSE; } else if (!strcmp(str, "auto")) { p->accel_enable = TRUE; } else { vm_error("unsupported 'accel' config: %s\n", str); return -1; } } tag_name = "rtc_local_time"; el = json_object_get(cfg, tag_name); if (!json_is_undefined(el)) { if (el.type != JSON_BOOL) { vm_error("%s: boolean expected\n", tag_name); goto tag_fail; } p->rtc_local_time = el.u.b; } vm_get_uint64_opt(cfg, "ncpus", &p->ncpus); vm_get_uint64_opt(cfg, "mmio_start", &p->mmio_start); vm_get_uint64_opt(cfg, "mmio_end", &p->mmio_end); if (vm_get_mmio_addrset_opt(cfg, p) < 0) goto tag_fail; vm_get_uint64_opt(cfg, "physical_addr_len", &p->physical_addr_len); if (vm_get_str_opt(cfg, "logfile", &str) < 0) goto tag_fail; if (str) p->logfile = strdup(str); json_free(cfg); return 0; tag_fail: json_free(cfg); return -1; } typedef void FSLoadFileCB(void *opaque, uint8_t *buf, int buf_len); typedef struct { VirtMachineParams *vm_params; void (*start_cb)(void *opaque); void *opaque; FSLoadFileCB *file_load_cb; void *file_load_opaque; int file_index; } VMConfigLoadState; static void config_file_loaded(void *opaque, uint8_t *buf, int buf_len); static void config_additional_file_load(VMConfigLoadState *s); static void config_additional_file_load_cb(void *opaque, uint8_t *buf, int buf_len); char *get_file_path(const char *base_filename, const char *filename) { if (!base_filename) return strdup(filename); if (strchr(filename, ':')) return strdup(filename); if (filename[0] == '/') return strdup(filename); const char *p = strrchr(base_filename, '/'); if (!p) return strdup(filename); int len = p + 1 - base_filename; int len1 = strlen(filename); char *fname = (char *)malloc(len + len1 + 1); memcpy(fname, base_filename, len); memcpy(fname + len, filename, len1 + 1); return fname; } /* return -1 if error. */ int load_file(uint8_t **pbuf, const char *filename) { FILE *f = fopen(filename, "rb"); if (!f) { perror(filename); exit(1); } fseek(f, 0, SEEK_END); size_t size = ftell(f); fseek(f, 0, SEEK_SET); uint8_t *buf = (uint8_t *)malloc(size); if (fread(buf, 1, size, f) != size) { fprintf(dromajo_stderr, "%s: read error\n", filename); exit(1); } fclose(f); *pbuf = buf; return size; } #ifdef CONFIG_FS_NET static void config_load_file_cb(void *opaque, int err, void *data, size_t size) { VMConfigLoadState *s = opaque; // fprintf(dromajo_stdout, "err=%d data=%p size=%ld\n", err, data, size); if (err < 0) { vm_error("Error %d while loading file\n", -err); exit(1); } s->file_load_cb(s->file_load_opaque, data, size); } #endif static void config_load_file(VMConfigLoadState *s, const char *filename, FSLoadFileCB *cb, void *opaque) { // printf("loading %s\n", filename); #ifdef CONFIG_FS_NET if (is_url(filename)) { s->file_load_cb = cb; s->file_load_opaque = opaque; fs_wget(filename, NULL, NULL, s, config_load_file_cb, TRUE); } else #endif { uint8_t *buf; int size = load_file(&buf, filename); cb(opaque, buf, size); free(buf); } } void virt_machine_load_config_file(VirtMachineParams *p, const char *filename, void (*start_cb)(void *opaque), void *opaque) { VMConfigLoadState *s = (VMConfigLoadState *)mallocz(sizeof(*s)); s->vm_params = p; s->start_cb = start_cb; s->opaque = opaque; p->cfg_filename = strdup(filename); config_load_file(s, filename, config_file_loaded, s); } static void config_file_loaded(void *opaque, uint8_t *buf, int buf_len) { VMConfigLoadState *s = (VMConfigLoadState *)opaque; VirtMachineParams *p = s->vm_params; if (virt_machine_parse_config(p, (char *)buf, buf_len) < 0) exit(1); /* load the additional files */ s->file_index = 0; config_additional_file_load(s); } static void config_additional_file_load(VMConfigLoadState *s) { VirtMachineParams *p = s->vm_params; while (s->file_index < VM_FILE_COUNT && p->files[s->file_index].filename == NULL) { s->file_index++; } if (s->file_index == VM_FILE_COUNT) { if (s->start_cb) s->start_cb(s->opaque); free(s); } else { char *fname; fname = get_file_path(p->cfg_filename, p->files[s->file_index].filename); config_load_file(s, fname, config_additional_file_load_cb, s); free(fname); } } static void config_additional_file_load_cb(void *opaque, uint8_t *buf, int buf_len) { VMConfigLoadState *s = (VMConfigLoadState *)opaque; VirtMachineParams *p = s->vm_params; p->files[s->file_index].buf = (uint8_t *)malloc(buf_len); memcpy(p->files[s->file_index].buf, buf, buf_len); p->files[s->file_index].len = buf_len; /* load the next files */ s->file_index++; config_additional_file_load(s); } void vm_add_cmdline(VirtMachineParams *p, const char *cmdline) { char *new_cmdline; if (cmdline[0] == '!') { new_cmdline = strdup(cmdline + 1); } else { const char *old_cmdline = p->cmdline; if (!old_cmdline) old_cmdline = ""; new_cmdline = (char *)malloc(strlen(old_cmdline) + 1 + strlen(cmdline) + 1); strcpy(new_cmdline, old_cmdline); strcat(new_cmdline, " "); strcat(new_cmdline, cmdline); } free(p->cmdline); p->cmdline = new_cmdline; } void virt_machine_free_config(VirtMachineParams *p) { int i; free(p->cmdline); for (i = 0; i < VM_FILE_COUNT; i++) { free(p->files[i].filename); free(p->files[i].buf); } for (i = 0; i < p->drive_count; i++) { free(p->tab_drive[i].filename); free(p->tab_drive[i].device); } for (i = 0; i < p->fs_count; i++) { free(p->tab_fs[i].filename); free(p->tab_fs[i].tag); } for (i = 0; i < p->eth_count; i++) { free(p->tab_eth[i].driver); free(p->tab_eth[i].ifname); } free(p->input_device); free(p->display_device); free(p->cfg_filename); }
/* * VM definitions * * Copyright (c) 2016-2017 Fabrice Bellard * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #include <stdint.h> #include "json.h" typedef struct RISCVMachine RISCVMachine; typedef struct FBDevice FBDevice; typedef void SimpleFBDrawFunc(FBDevice *fb_dev, void *opaque, int x, int y, int w, int h); struct FBDevice { /* the following is set by the device */ int width; int height; int stride; /* current stride in bytes */ uint8_t *fb_data; /* current pointer to the pixel data */ int fb_size; /* frame buffer memory size (info only) */ void *device_opaque; void (*refresh)(struct FBDevice *fb_dev, SimpleFBDrawFunc *redraw_func, void *opaque); }; #ifndef MACHINE_H #define MACHINE_H #include <stdint.h> #include "virtio.h" #define MAX_DRIVE_DEVICE 4 #define MAX_FS_DEVICE 4 #define MAX_ETH_DEVICE 1 #define VM_CONFIG_VERSION 1 typedef enum { VM_FILE_BIOS, VM_FILE_VGA_BIOS, VM_FILE_KERNEL, VM_FILE_INITRD, VM_FILE_COUNT, } VMFileTypeEnum; typedef struct { char *filename; uint8_t *buf; int len; } VMFileEntry; typedef struct { char *device; char *filename; BlockDevice *block_dev; } VMDriveEntry; typedef struct { char *device; char *tag; /* 9p mount tag */ char *filename; FSDevice *fs_dev; } VMFSEntry; typedef struct { char *driver; char *ifname; EthernetDevice *net; } VMEthEntry; typedef struct AddressSet{ uint64_t start; uint64_t size; } AddressSet; typedef struct { char *cfg_filename; uint64_t ram_base_addr; uint64_t ram_size; BOOL rtc_local_time; char *display_device; /* NULL means no display */ int64_t width, height; /* graphic width & height */ CharacterDevice *console; VMDriveEntry tab_drive[MAX_DRIVE_DEVICE]; int drive_count; VMFSEntry tab_fs[MAX_FS_DEVICE]; int fs_count; VMEthEntry tab_eth[MAX_ETH_DEVICE]; int eth_count; uint64_t htif_base_addr; /* some csrs may not be implemented in some implementations, * this arrya contains list of these csrs to make sure bootcode * is not generated for them */ uint64_t* missing_csrs; uint64_t missing_csrs_size; /* commit of some instruction in the RTL is not visible, * this array contains the list of these instructions * to hide them in dromajo as well */ uint64_t* skip_commit; uint64_t skip_commit_size; char *cmdline; /* bios or kernel command line */ BOOL accel_enable; /* enable acceleration (KVM) */ char *input_device; /* NULL means no input */ /* kernel, bios and other auxiliary files */ VMFileEntry files[VM_FILE_COUNT]; /* maximum increment of instructions to execute */ uint64_t maxinsns; /* snapshot load file */ const char *snapshot_load_name; /* bootrom params */ const char *bootrom_name; const char *dtb_name; bool compact_bootrom; /* reset vector used at startup */ uint64_t reset_vector; /* number of cpus */ uint64_t ncpus; /* MMIO range (for co-simulation only) */ uint64_t mmio_start; uint64_t mmio_end; AddressSet *mmio_addrset; uint64_t mmio_addrset_size; /* PLIC/CLINT Params */ uint64_t plic_base_addr; uint64_t plic_size; uint64_t clint_base_addr; uint64_t clint_size; /* Add to misa custom extensions */ bool custom_extension; uint64_t physical_addr_len; char *logfile; // If non-zero, all output goes here, stderr and stdout bool dump_memories; } VirtMachineParams; typedef struct VirtMachine { /* network */ EthernetDevice *net; /* console */ VIRTIODevice *console_dev; CharacterDevice *console; /* graphics */ FBDevice *fb_dev; const char *snapshot_load_name; const char *snapshot_save_name; const char *terminate_event; uint32_t save_format; uint64_t maxinsns; uint64_t trace; /* For co-simulation only, they are -1 if nothing is pending. */ bool cosim; int pending_interrupt; int pending_exception; } VirtMachine; int load_file(uint8_t **pbuf, const char *filename); void __attribute__((format(printf, 1, 2))) vm_error(const char *fmt, ...); int vm_get_int(JSONValue obj, const char *name, int64_t *pval); const char *virt_machine_get_name(void); void virt_machine_set_defaults(VirtMachineParams *p); void virt_machine_load_config_file(VirtMachineParams *p, const char *filename, void (*start_cb)(void *opaque), void *opaque); void vm_add_cmdline(VirtMachineParams *p, const char *cmdline); char *get_file_path(const char *base_filename, const char *filename); void virt_machine_free_config(VirtMachineParams *p); RISCVMachine *virt_machine_init(const VirtMachineParams *p); int virt_machine_get_sleep_duration(RISCVMachine *s, int hartid, int delay); BOOL vm_mouse_is_absolute(RISCVMachine *s); void vm_send_mouse_event(RISCVMachine *s1, int dx, int dy, int dz, unsigned int buttons); void vm_send_key_event(RISCVMachine *s1, BOOL is_down, uint16_t key_code); /* gui */ void sdl_refresh(RISCVMachine *m); void sdl_init(int width, int height); /* simplefb.c */ typedef struct SimpleFBState SimpleFBState; SimpleFBState *simplefb_init(PhysMemoryMap *map, uint64_t phys_addr, FBDevice *fb_dev, int width, int height); void simplefb_refresh(FBDevice *fb_dev, SimpleFBDrawFunc *redraw_func, void *opaque, PhysMemoryRange *mem_range, int fb_page_count); /* vga.c */ typedef struct VGAState VGAState; VGAState *pci_vga_init(PCIBus *bus, FBDevice *fb_dev, int width, int height, const uint8_t *vga_rom_buf, int vga_rom_size); /* block_net.c */ BlockDevice *block_device_init_http(const char *url, int max_cache_size_kb, void (*start_cb)(void *opaque), void *start_opaque); #ifdef __cplusplus extern "C" { #endif RISCVMachine*virt_machine_main (int argc, char **argv); void virt_machine_end (RISCVMachine *s); void virt_machine_serialize (RISCVMachine *m, const char *dump_name); void virt_machine_deserialize(RISCVMachine *m, const char *dump_name); BOOL virt_machine_run (RISCVMachine *m, int hartid); uint64_t virt_machine_get_pc (RISCVMachine *m, int hartid); uint64_t virt_machine_get_reg (RISCVMachine *m, int hartid, int rn); uint64_t virt_machine_get_fpreg (RISCVMachine *m, int hartid, int rn); #ifdef __cplusplus } // extern C #endif #endif
# # Dromajo, a RISC-V Emulator (based on Fabrice Bellard's RISCVEMU/TinyEMU) # # Copyright (c) 2016-2017 Fabrice Bellard # Copyright (c) 2018,2019 Esperanto Technology # # Licensed under the Apache License, Version 2.0 (the "License") # you may not use this file except in compliance with the License. # You may obtain a copy of the License at # # http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. # See the License for the specific language governing permissions and # limitations under the License. # # THIS FILE IS BASED ON RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED UNDER # THE FOLLOWING LICENSE: # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell # copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN # THE SOFTWARE. # VERSION=Dromajo-0.1 CXX=g++ CFLAGS_OPT=-Ofast CXXFLAGS=$(CFLAGS_OPT) -Wall -std=c++11 -g -Wno-parentheses -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE -MMD CXXFLAGS+=-D_GNU_SOURCE -DCONFIG_VERSION=\"$(VERSION)\" #CXXFLAGS+=-DLIVECACHE LDFLAGS= bindir=/usr/local/bin INSTALL=install PROGS=dromajo libdromajo_cosim.a all: $(PROGS) EMU_OBJS:=virtio.o pci.o fs.o cutils.o iomem.o dw_apb_uart.o \ json.o machine.o elf64.o LiveCache.o fs_disk.o UNAME_S := $(shell uname -s) ifeq ($(UNAME_S),Linux) CXXFLAGS += -Werror EMU_LIBS=-lrt endif ifeq ($(UNAME_S),Darwin) EMU_LIBS= endif dromajo: dromajo.o libdromajo_cosim.a $(CXX) $(LDFLAGS) -o $@ $^ $(DROMAJO_LIBS) $(EMU_LIBS) dromajo_cosim_test: dromajo_cosim_test.o libdromajo_cosim.a $(CXX) $(LDFLAGS) -o $@ $^ $(DROMAJO_LIBS) $(EMU_LIBS) libdromajo_cosim.a: dromajo_cosim.o riscv_cpu.o dromajo_main.o \ riscv_machine.o softfp.o $(EMU_OBJS) ar rvs $@ $^ install: $(PROGS) $(INSTALL) -m755 $(PROGS) "$(DESTDIR)$(bindir)" %.o: %.c $(CXX) $(CXXFLAGS) -c -o $@ $< %.o: %.cpp $(CXX) $(CXXFLAGS) -c -o $@ $< debug: $(MAKE) CFLAGS_OPT= build: mkdir -p build clean: rm -f *.o *.d *~ $(PROGS) rm -rf build -include $(wildcard *.d) tags: etags *.[hc] release: git archive HEAD | xz -9 > dromajo-$(shell date +%Y%m%d)-$(shell git rev-parse --short HEAD).tar.xz git tag release-$(shell date +%Y%m%d)
/* * Simple PCI bus driver * * Copyright (c) 2017 Fabrice Bellard * Copyright (C) 2017,2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #include <stdlib.h> #include <stdio.h> #include <string.h> #include <inttypes.h> #include <assert.h> #include <stdarg.h> #include "cutils.h" #include "pci.h" //#define DEBUG_CONFIG typedef struct { uint32_t size; /* 0 means no mapping defined */ uint8_t type; uint8_t enabled; /* true if mapping is enabled */ void *opaque; PCIBarSetFunc *bar_set; } PCIIORegion; struct PCIDevice { PCIBus *bus; uint8_t devfn; IRQSignal irq[4]; uint8_t config[256]; uint8_t next_cap_offset; /* offset of the next capability */ char *name; /* for debug only */ PCIIORegion io_regions[PCI_NUM_REGIONS]; }; struct PCIBus { int bus_num; PCIDevice *device[256]; PhysMemoryMap *mem_map; PhysMemoryMap *port_map; uint32_t irq_state[4][8]; /* one bit per device */ IRQSignal irq[4]; }; static int bus_map_irq(PCIDevice *d, int irq_num) { int slot_addend; slot_addend = (d->devfn >> 3) - 1; return (irq_num + slot_addend) & 3; } static void pci_device_set_irq(void *opaque, int irq_num, int level) { PCIDevice *d = (PCIDevice *)opaque; PCIBus *b = d->bus; uint32_t mask; int i, irq_level; // printf("%s: pci_device_seq_irq: %d %d\n", d->name, irq_num, level); irq_num = bus_map_irq(d, irq_num); mask = 1 << (d->devfn & 0x1f); if (level) b->irq_state[irq_num][d->devfn >> 5] |= mask; else b->irq_state[irq_num][d->devfn >> 5] &= ~mask; /* compute the IRQ state */ mask = 0; for (i = 0; i < 8; i++) mask |= b->irq_state[irq_num][i]; irq_level = (mask != 0); set_irq(&b->irq[irq_num], irq_level); } static int devfn_alloc(PCIBus *b) { int devfn; for (devfn = 0; devfn < 256; devfn += 8) { if (!b->device[devfn]) return devfn; } return -1; } /* devfn < 0 means to allocate it */ PCIDevice *pci_register_device(PCIBus *b, const char *name, int devfn, uint16_t vendor_id, uint16_t device_id, uint8_t revision, uint16_t class_id) { int i; if (devfn < 0) { devfn = devfn_alloc(b); if (devfn < 0) return NULL; } if (b->device[devfn]) return NULL; PCIDevice *d = (PCIDevice *)mallocz(sizeof(PCIDevice)); d->bus = b; d->name = strdup(name); d->devfn = devfn; put_le16(d->config + 0x00, vendor_id); put_le16(d->config + 0x02, device_id); d->config[0x08] = revision; put_le16(d->config + 0x0a, class_id); d->config[0x0e] = 0x00; /* header type */ d->next_cap_offset = 0x40; for (i = 0; i < 4; i++) irq_init(&d->irq[i], pci_device_set_irq, d, i); b->device[devfn] = d; return d; } IRQSignal *pci_device_get_irq(PCIDevice *d, unsigned int irq_num) { assert(irq_num < 4); return &d->irq[irq_num]; } static uint32_t pci_device_config_read(PCIDevice *d, uint32_t addr, int size_log2) { uint32_t val; switch (size_log2) { case 0: val = *(uint8_t *)(d->config + addr); break; case 1: /* Note: may be unaligned */ if (addr <= 0xfe) val = get_le16(d->config + addr); else val = *(uint8_t *)(d->config + addr); break; case 2: /* always aligned */ val = get_le32(d->config + addr); break; default: abort(); } #ifdef DEBUG_CONFIG fprintf(dromajo_stdout, "pci_config_read: dev=%s addr=0x%02x val=0x%x s=%d\n", d->name, addr, val, 1 << size_log2); #endif return val; } PhysMemoryMap *pci_device_get_mem_map(PCIDevice *d) { return d->bus->mem_map; } PhysMemoryMap *pci_device_get_port_map(PCIDevice *d) { return d->bus->port_map; } void pci_register_bar(PCIDevice *d, unsigned int bar_num, uint32_t size, int type, void *opaque, PCIBarSetFunc *bar_set) { PCIIORegion *r; uint32_t val, config_addr; assert(bar_num < PCI_NUM_REGIONS); assert((size & (size - 1)) == 0); /* power of two */ assert(size >= 4); r = &d->io_regions[bar_num]; assert(r->size == 0); r->size = size; r->type = type; r->enabled = FALSE; r->opaque = opaque; r->bar_set = bar_set; /* set the config value */ val = 0; if (bar_num == PCI_ROM_SLOT) { config_addr = 0x30; } else { val |= r->type; config_addr = 0x10 + 4 * bar_num; } put_le32(&d->config[config_addr], val); } static void pci_update_mappings(PCIDevice *d) { int cmd, i, offset; uint32_t new_addr; BOOL new_enabled; PCIIORegion *r; cmd = get_le16(&d->config[PCI_COMMAND]); for (i = 0; i < PCI_NUM_REGIONS; i++) { r = &d->io_regions[i]; if (i == PCI_ROM_SLOT) { offset = 0x30; } else { offset = 0x10 + i * 4; } new_addr = get_le32(&d->config[offset]); new_enabled = FALSE; if (r->size != 0) { if ((r->type & PCI_ADDRESS_SPACE_IO) && (cmd & PCI_COMMAND_IO)) { new_enabled = TRUE; } else { if (cmd & PCI_COMMAND_MEMORY) { if (i == PCI_ROM_SLOT) { new_enabled = (new_addr & 1); } else { new_enabled = TRUE; } } } } if (new_enabled) { /* new address */ new_addr = get_le32(&d->config[offset]) & ~(r->size - 1); r->bar_set(r->opaque, i, new_addr, TRUE); r->enabled = TRUE; } else if (r->enabled) { r->bar_set(r->opaque, i, 0, FALSE); r->enabled = FALSE; } } } /* return != 0 if write is not handled */ static int pci_write_bar(PCIDevice *d, uint32_t addr, uint32_t val) { PCIIORegion *r; int reg; if (addr == 0x30) reg = PCI_ROM_SLOT; else reg = (addr - 0x10) >> 2; // printf("%s: write bar addr=%x data=%x\n", d->name, addr, val); r = &d->io_regions[reg]; if (r->size == 0) return -1; if (reg == PCI_ROM_SLOT) { val = val & ((~(r->size - 1)) | 1); } else { val = (val & ~(r->size - 1)) | r->type; } put_le32(d->config + addr, val); pci_update_mappings(d); return 0; } static void pci_device_config_write8(PCIDevice *d, uint32_t addr, uint32_t data) { int can_write; if (addr == PCI_STATUS || addr == (PCI_STATUS + 1)) { /* write 1 reset bits */ d->config[addr] &= ~data; return; } switch (d->config[0x0e]) { case 0x00: case 0x80: switch (addr) { case 0x00: case 0x01: case 0x02: case 0x03: case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0e: case 0x10 ... 0x27: /* base */ case 0x30 ... 0x33: /* rom */ case 0x3d: can_write = 0; break; default: can_write = 1; break; } break; default: case 0x01: switch (addr) { case 0x00: case 0x01: case 0x02: case 0x03: case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0e: case 0x38 ... 0x3b: /* rom */ case 0x3d: can_write = 0; break; default: can_write = 1; break; } break; } if (can_write) d->config[addr] = data; } static void pci_device_config_write(PCIDevice *d, uint32_t addr, uint32_t data, int size_log2) { int size, i; uint32_t addr1; #ifdef DEBUG_CONFIG printf("pci_config_write: dev=%s addr=0x%02x val=0x%x s=%d\n", d->name, addr, data, 1 << size_log2); #endif if (size_log2 == 2 && ((addr >= 0x10 && addr < 0x10 + 4 * 6) || addr == 0x30)) { if (pci_write_bar(d, addr, data) == 0) return; } size = 1 << size_log2; for (i = 0; i < size; i++) { addr1 = addr + i; if (addr1 <= 0xff) { pci_device_config_write8(d, addr1, (data >> (i * 8)) & 0xff); } } if (PCI_COMMAND >= addr && PCI_COMMAND < addr + size) { pci_update_mappings(d); } } static void pci_data_write(PCIBus *s, uint32_t addr, uint32_t data, int size_log2) { PCIDevice *d; int bus_num, devfn, config_addr; bus_num = (addr >> 16) & 0xff; if (bus_num != s->bus_num) return; devfn = (addr >> 8) & 0xff; d = s->device[devfn]; if (!d) return; config_addr = addr & 0xff; pci_device_config_write(d, config_addr, data, size_log2); } static const uint32_t val_ones[3] = { 0xff, 0xffff, 0xffffffff }; static uint32_t pci_data_read(PCIBus *s, uint32_t addr, int size_log2) { PCIDevice *d; int bus_num, devfn, config_addr; bus_num = (addr >> 16) & 0xff; if (bus_num != s->bus_num) return val_ones[size_log2]; devfn = (addr >> 8) & 0xff; d = s->device[devfn]; if (!d) return val_ones[size_log2]; config_addr = addr & 0xff; return pci_device_config_read(d, config_addr, size_log2); } /* warning: only valid for one DEVIO page. Return NULL if no memory at the given address */ uint8_t *pci_device_get_dma_ptr(PCIDevice *d, uint64_t addr) { PhysMemoryRange *pr; pr = get_phys_mem_range(d->bus->mem_map, addr); if (!pr || !pr->is_ram) return NULL; return pr->phys_mem + (uintptr_t)(addr - pr->addr); } void pci_device_set_config8(PCIDevice *d, uint8_t addr, uint8_t val) { d->config[addr] = val; } void pci_device_set_config16(PCIDevice *d, uint8_t addr, uint16_t val) { put_le16(&d->config[addr], val); } int pci_device_get_devfn(PCIDevice *d) { return d->devfn; } /* return the offset of the capability or < 0 if error. */ int pci_add_capability(PCIDevice *d, const uint8_t *buf, int size) { int offset; offset = d->next_cap_offset; if ((offset + size) > 256) return -1; d->next_cap_offset += size; d->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; memcpy(d->config + offset, buf, size); d->config[offset + 1] = d->config[PCI_CAPABILITY_LIST]; d->config[PCI_CAPABILITY_LIST] = offset; return offset; } /* i440FX host bridge */ struct I440FXState { PCIBus *pci_bus; PCIDevice *pci_dev; PCIDevice *piix3_dev; uint32_t config_reg; uint8_t pic_irq_state[16]; IRQSignal *pic_irqs; /* 16 irqs */ }; static void i440fx_write_addr(void *opaque, uint32_t offset, uint32_t data, int size_log2) { I440FXState *s = (I440FXState *)opaque; s->config_reg = data; } static uint32_t i440fx_read_addr(void *opaque, uint32_t offset, int size_log2) { I440FXState *s = (I440FXState *)opaque; return s->config_reg; } static void i440fx_write_data(void *opaque, uint32_t offset, uint32_t data, int size_log2) { I440FXState *s = (I440FXState *)opaque; if (s->config_reg & 0x80000000) { if (size_log2 == 2) { /* it is simpler to assume 32 bit config accesses are always aligned */ pci_data_write(s->pci_bus, s->config_reg & ~3, data, size_log2); } else { pci_data_write(s->pci_bus, s->config_reg | offset, data, size_log2); } } } static uint32_t i440fx_read_data(void *opaque, uint32_t offset, int size_log2) { I440FXState *s = (I440FXState *)opaque; if (!(s->config_reg & 0x80000000)) return val_ones[size_log2]; if (size_log2 == 2) { /* it is simpler to assume 32 bit config accesses are always aligned */ return pci_data_read(s->pci_bus, s->config_reg & ~3, size_log2); } else { return pci_data_read(s->pci_bus, s->config_reg | offset, size_log2); } } static void i440fx_set_irq(void *opaque, int irq_num, int irq_level) { I440FXState *s = (I440FXState *)opaque; PCIDevice *hd = s->piix3_dev; int pic_irq; /* map to the PIC irq (different IRQs can be mapped to the same PIC irq) */ hd->config[0x60 + irq_num] &= ~0x80; pic_irq = hd->config[0x60 + irq_num]; if (pic_irq < 16) { if (irq_level) s->pic_irq_state[pic_irq] |= 1 << irq_num; else s->pic_irq_state[pic_irq] &= ~(1 << irq_num); set_irq(&s->pic_irqs[pic_irq], (s->pic_irq_state[pic_irq] != 0)); } } I440FXState *i440fx_init(PCIBus **pbus, int *ppiix3_devfn, PhysMemoryMap *mem_map, PhysMemoryMap *port_map, IRQSignal *pic_irqs) { I440FXState *s = (I440FXState *)mallocz(sizeof *s); PCIBus *b = (PCIBus *)mallocz(sizeof *b); b->bus_num = 0; b->mem_map = mem_map; b->port_map = port_map; s->pic_irqs = pic_irqs; for (int i = 0; i < 4; i++) { irq_init(&b->irq[i], i440fx_set_irq, s, i); } cpu_register_device(port_map, 0xcf8, 1, s, i440fx_read_addr, i440fx_write_addr, DEVIO_SIZE32); cpu_register_device(port_map, 0xcfc, 4, s, i440fx_read_data, i440fx_write_data, DEVIO_SIZE8 | DEVIO_SIZE16 | DEVIO_SIZE32); PCIDevice *d = pci_register_device(b, "i440FX", 0, 0x8086, 0x1237, 0x02, 0x0600); put_le16(&d->config[PCI_SUBSYSTEM_VENDOR_ID], 0x1af4); /* Red Hat, Inc. */ put_le16(&d->config[PCI_SUBSYSTEM_ID], 0x1100); /* QEMU virtual machine */ s->pci_dev = d; s->pci_bus = b; s->piix3_dev = pci_register_device(b, "PIIX3", 8, 0x8086, 0x7000, 0x00, 0x0601); pci_device_set_config8(s->piix3_dev, 0x0e, 0x80); /* header type */ *pbus = b; *ppiix3_devfn = s->piix3_dev->devfn; return s; } /* in case no BIOS is used, map the interrupts. */ void i440fx_map_interrupts(I440FXState *s, uint8_t *elcr, const uint8_t *pci_irqs) { PCIBus *b = s->pci_bus; PCIDevice *d, *hd; int irq_num, pic_irq, devfn, i; /* set a default PCI IRQ mapping to PIC IRQs */ hd = s->piix3_dev; elcr[0] = 0; elcr[1] = 0; for (i = 0; i < 4; i++) { irq_num = pci_irqs[i]; hd->config[0x60 + i] = irq_num; elcr[irq_num >> 3] |= (1 << (irq_num & 7)); } for (devfn = 0; devfn < 256; devfn++) { d = b->device[devfn]; if (!d) continue; if (d->config[PCI_INTERRUPT_PIN]) { irq_num = 0; irq_num = bus_map_irq(d, irq_num); pic_irq = hd->config[0x60 + irq_num]; if (pic_irq < 16) { d->config[PCI_INTERRUPT_LINE] = pic_irq; } } } }
/* * Simple PCI bus driver * * Copyright (c) 2017 Fabrice Bellard * Copyright (C) 2017,2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #ifndef PCI_H #define PCI_H #include "iomem.h" typedef struct PCIBus PCIBus; typedef struct PCIDevice PCIDevice; /* bar type */ #define PCI_ADDRESS_SPACE_MEM 0x00 #define PCI_ADDRESS_SPACE_IO 0x01 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08 #define PCI_ROM_SLOT 6 #define PCI_NUM_REGIONS 7 /* PCI config addresses */ #define PCI_VENDOR_ID 0x00 /* 16 bits */ #define PCI_DEVICE_ID 0x02 /* 16 bits */ #define PCI_COMMAND 0x04 /* 16 bits */ #define PCI_COMMAND_IO (1 << 0) #define PCI_COMMAND_MEMORY (1 << 1) #define PCI_STATUS 0x06 /* 16 bits */ #define PCI_STATUS_CAP_LIST (1 << 4) #define PCI_CLASS_PROG 0x09 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */ #define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */ #define PCI_CAPABILITY_LIST 0x34 /* 8 bits */ #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ typedef void PCIBarSetFunc(void *opaque, int bar_num, uint32_t addr, BOOL enabled); PCIDevice *pci_register_device(PCIBus *b, const char *name, int devfn, uint16_t vendor_id, uint16_t device_id, uint8_t revision, uint16_t class_id); PhysMemoryMap *pci_device_get_mem_map(PCIDevice *d); PhysMemoryMap *pci_device_get_port_map(PCIDevice *d); void pci_register_bar(PCIDevice *d, unsigned int bar_num, uint32_t size, int type, void *opaque, PCIBarSetFunc *bar_set); IRQSignal *pci_device_get_irq(PCIDevice *d, unsigned int irq_num); uint8_t *pci_device_get_dma_ptr(PCIDevice *d, uint64_t addr); void pci_device_set_config8(PCIDevice *d, uint8_t addr, uint8_t val); void pci_device_set_config16(PCIDevice *d, uint8_t addr, uint16_t val); int pci_device_get_devfn(PCIDevice *d); int pci_add_capability(PCIDevice *d, const uint8_t *buf, int size); typedef struct I440FXState I440FXState; I440FXState *i440fx_init(PCIBus **pbus, int *ppiix3_devfn, PhysMemoryMap *mem_map, PhysMemoryMap *port_map, IRQSignal *pic_irqs); void i440fx_map_interrupts(I440FXState *s, uint8_t *elcr, const uint8_t *pci_irqs); #endif /* PCI_H */
/* * RISC-V definitions * * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Implementation independent ISA definitions -- most of this comes * straight from the specifications. */ #ifndef RISCV_H #define RISCV_H #define MIP_USIP (1 << 0) #define MIP_SSIP (1 << 1) //#define MIP_HSIP (1 << 2) Removed in Priv 1.11 (draft) #define MIP_MSIP (1 << 3) #define MIP_UTIP (1 << 4) #define MIP_STIP (1 << 5) //#define MIP_HTIP (1 << 6) Removed in Priv 1.11 (draft) #define MIP_MTIP (1 << 7) #define MIP_UEIP (1 << 8) #define MIP_SEIP (1 << 9) //#define MIP_HEIP (1 << 10) Removed in Priv 1.11 (draft) #define MIP_MEIP (1 << 11) // ET-specific, non-standard counter overflow interrupts. //#define MIP_UCIP (1 << 16) probably not necessary. //#define MIP_SCIP (1 << 17) probably not necessary. #define MIP_MCIP (1 << 18) #define MIE_USIE MIP_USIP #define MIE_SSIE MIP_SSIP #define MIE_MSIE MIP_MSIP #define MIE_UTIE MIP_UTIP #define MIE_STIE MIP_STIP #define MIE_MTIE MIP_MTIP #define MIE_UEIE MIP_UEIP #define MIE_SEIE MIP_SEIP #define MIE_MEIE MIP_MEIP #define MIE_MCIP MIP_MCIP #define CAUSE_MISALIGNED_FETCH 0x0 #define CAUSE_FAULT_FETCH 0x1 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 #define CAUSE_BREAKPOINT 0x3 #define CAUSE_MISALIGNED_LOAD 0x4 #define CAUSE_FAULT_LOAD 0x5 #define CAUSE_MISALIGNED_STORE 0x6 #define CAUSE_FAULT_STORE 0x7 #define CAUSE_USER_ECALL 0x8 #define CAUSE_SUPERVISOR_ECALL 0x9 #define CAUSE_HYPERVISOR_ECALL 0xa #define CAUSE_MACHINE_ECALL 0xb #define CAUSE_FETCH_PAGE_FAULT 0xc #define CAUSE_LOAD_PAGE_FAULT 0xd #define CAUSE_STORE_PAGE_FAULT 0xf #define SCAUSE_MASK 0x800000000000001full // 5 writable bits+MSB #define MCAUSE_MASK 0x80000000000000ffull // 8 writable bits+MSB #define CAUSE_INTERRUPT 0x8000000000000000ull #define PRV_U 0 #define PRV_S 1 #define PRV_H 2 #define PRV_M 3 /* misa CSR */ #define MCPUID_SUPER (1 << ('S' - 'A')) #define MCPUID_USER (1 << ('U' - 'A')) #define MCPUID_I (1 << ('I' - 'A')) #define MCPUID_M (1 << ('M' - 'A')) #define MCPUID_A (1 << ('A' - 'A')) #define MCPUID_F (1 << ('F' - 'A')) #define MCPUID_D (1 << ('D' - 'A')) #define MCPUID_Q (1 << ('Q' - 'A')) #define MCPUID_C (1 << ('C' - 'A')) #define MCPUID_X (1 << ('X' - 'A')) /* mstatus CSR */ #define MSTATUS_SPIE_SHIFT 5 #define MSTATUS_MPIE_SHIFT 7 #define MSTATUS_SPP_SHIFT 8 #define MSTATUS_MPP_SHIFT 11 #define MSTATUS_FS_SHIFT 13 #define MSTATUS_UXL_SHIFT 32 #define MSTATUS_SXL_SHIFT 34 #define MSTATUS_UIE (1 << 0) #define MSTATUS_SIE (1 << 1) #define MSTATUS_HIE (1 << 2) #define MSTATUS_MIE (1 << 3) #define MSTATUS_UPIE (1 << 4) #define MSTATUS_SPIE (1 << MSTATUS_SPIE_SHIFT) #define MSTATUS_HPIE (1 << 6) #define MSTATUS_MPIE (1 << MSTATUS_MPIE_SHIFT) #define MSTATUS_SPP (1 << MSTATUS_SPP_SHIFT) #define MSTATUS_HPP (3 << 9) #define MSTATUS_MPP (3 << MSTATUS_MPP_SHIFT) #define MSTATUS_FS (3 << MSTATUS_FS_SHIFT) #define MSTATUS_XS (3 << 15) #define MSTATUS_MPRV (1 << 17) #define MSTATUS_SUM (1 << 18) #define MSTATUS_MXR (1 << 19) #define MSTATUS_TVM (1 << 20) #define MSTATUS_TW (1 << 21) #define MSTATUS_TSR (1 << 22) #define MSTATUS_UXL_MASK ((uint64_t)3 << MSTATUS_UXL_SHIFT) #define MSTATUS_SXL_MASK ((uint64_t)3 << MSTATUS_SXL_SHIFT) // A few of Debug Trigger Match Control bits (there are many more) #define MCONTROL_M (1 << 6) #define MCONTROL_S (1 << 4) #define MCONTROL_U (1 << 3) #define MCONTROL_EXECUTE (1 << 2) #define MCONTROL_STORE (1 << 1) #define MCONTROL_LOAD (1 << 0) #define PHYSICAL_ADDR_LEN_DEFAULT 40 /* SBI calls */ typedef enum { SBI_SET_TIMER, SBI_CONSOLE_PUTCHAR, SBI_CONSOLE_GETCHAR, SBI_CLEAR_IPI, SBI_SEND_IPI, SBI_REMOTE_FENCE_I, SBI_REMOTE_SFENCE_VMA, SBI_REMOTE_SFENCE_VMA_ASID, SBI_SHUTDOWN, SBI_DISK_READ, SBI_DISK_WRITE, SBI_DISK_SIZE, } sbi_call_t; /* PMP */ #define CSR_PMPCFG(n) (0x3A0 + (n)) // n = 0 or 2 #define CSR_PMPADDR(n) (0x3B0 + (n)) // n = 0..15 #define PMP_N 8 // Spec defines 16, we implement 8 typedef enum { PMPCFG_R = 1, // NB: the three bottom bits follow the standard permissions order PMPCFG_W = 2, PMPCFG_X = 4, PMPCFG_A_MASK = 0x18, PMPCFG_A_OFF = 0, PMPCFG_A_TOR = 8, PMPCFG_A_NA4 = 0x10, PMPCFG_A_NAPOT = 0x18, PMPCFG_RES = 0x60, PMPCFG_L = 0x80, } pmpcfg_t; /* Copy & paste from qemu include/hw/riscv/virt.h */ #define PLIC_HART_CONFIG "MS" #define PLIC_NUM_SOURCES 127 #define PLIC_NUM_PRIORITIES 7 #define PLIC_PRIORITY_BASE 4 #define PLIC_PENDING_BASE 0x1000 #define PLIC_ENABLE_BASE 0x2000 #define PLIC_ENABLE_STRIDE 0x80 #define PLIC_CONTEXT_BASE 0x200000 #define PLIC_CONTEXT_STRIDE 0x1000 #define PLIC_BITFIELD_WORDS ((PLIC_NUM_SOURCES + 31) >> 5) #endif
/* * RISCV CPU emulator * * Copyright (c) 2016-2017 Fabrice Bellard * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #include "dromajo.h" #include <stdlib.h> #include <stdarg.h> #include <stdbool.h> #include <string.h> #include <inttypes.h> #include <assert.h> #include <fcntl.h> #include <unistd.h> #include <err.h> #include <fstream> #include <iomanip> #include "cutils.h" #include "iomem.h" #include "riscv_machine.h" #include "LiveCacheCore.h" // NOTE: Use GET_INSN_COUNTER not mcycle because this is just to track advancement of simulation #define write_reg(x, val) ({s->most_recently_written_reg = (x); \ s->reg_prior[x] = s->reg[x]; \ s->reg[x] = (val);}) #define read_reg(x) (s->reg[x]) #define write_fp_reg(x, val) ({s->most_recently_written_fp_reg = (x); \ s->fp_reg[x] = (val); \ s->fs = 3;}) #define read_fp_reg(x) (s->fp_reg[x]) /* * Boom/Rocket doesn't implement all bits in all CSRs but * stores Sv+1, that, is 49 bits and reads are sign-extended from bit * 49 onwards. For the emulator we achieve this by keeping the * register canonical on writes (as opposed to reads). */ #define CANONICAL_S49(v) ((intptr_t)(v) << (63-48) >> (63-48)) #define MEPC_TRUNCATE CANONICAL_S49 #define MTVAL_TRUNCATE CANONICAL_S49 #define SEPC_TRUNCATE CANONICAL_S49 #define STVAL_TRUNCATE CANONICAL_S49 // PMPADDR CSRs only have 38-bits #define PMPADDR_MASK 0x3fffffffff #ifdef CONFIG_LOGFILE static FILE *log_file; void log_vprintf(const char *fmt, va_list ap) { if (!log_file) log_file = fopen("/tmp/riscemu.log", "wb"); vfprintf(log_file, fmt, ap); } #else void log_vprintf(const char *fmt, va_list ap) { vprintf(fmt, ap); } #endif void __attribute__((format(printf, 1, 2))) log_printf(const char *fmt, ...) { va_list ap; va_start(ap, fmt); log_vprintf(fmt, ap); va_end(ap); } static void fprint_target_ulong(FILE *f, target_ulong a) { fprintf(f, "%" PR_target_ulong, a); } static void print_target_ulong(target_ulong a) { fprint_target_ulong(dromajo_stderr, a); } static const char *reg_name[32] = { "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6" }; static target_ulong get_mstatus(RISCVCPUState *s, target_ulong mask); static void dump_regs(RISCVCPUState *s) { int i, cols; const char *priv_str = "USHM"; cols = 256 / 64; fprintf(dromajo_stderr, "pc ="); print_target_ulong(s->pc); fprintf(dromajo_stderr, " "); for (i = 1; i < 32; i++) { fprintf(dromajo_stderr, "%-3s=", reg_name[i]); print_target_ulong(s->reg[i]); if ((i & (cols - 1)) == (cols - 1)) fprintf(dromajo_stderr, "\n"); else fprintf(dromajo_stderr, " "); } fprintf(dromajo_stderr, "priv=%c", priv_str[s->priv]); fprintf(dromajo_stderr, " mstatus="); print_target_ulong(get_mstatus(s, (target_ulong)-1)); fprintf(dromajo_stderr, " insn_counter=%" PRId64, s->insn_counter); fprintf(dromajo_stderr, " minstret=%" PRId64, s->minstret); fprintf(dromajo_stderr, " mcycle=%" PRId64, s->mcycle); fprintf(dromajo_stderr, "\n"); #if 1 fprintf(dromajo_stderr, " mideleg="); print_target_ulong(s->mideleg); fprintf(dromajo_stderr, " mie="); print_target_ulong(s->mie); fprintf(dromajo_stderr, " mip="); print_target_ulong(s->mip); fprintf(dromajo_stderr, "\n"); #endif } static inline void track_write(RISCVCPUState *s, uint64_t vaddr, uint64_t paddr, uint64_t data, int size) { #ifdef LIVECACHE s->machine->llc->write(paddr); #endif } static inline uint64_t track_dread(RISCVCPUState *s, uint64_t vaddr, uint64_t paddr, uint64_t data, int size) { #ifdef LIVECACHE s->machine->llc->read(paddr); #endif return data; } static inline uint64_t track_iread(RISCVCPUState *s, uint64_t vaddr, uint64_t paddr, uint64_t data, int size) { #ifdef LIVECACHE s->machine->llc->read(paddr); #endif assert(size == 16 || size == 32); return data; } /* "PMP checks are applied to all accesses when the hart is running in * S or U modes, and for loads and stores when the MPRV bit is set in * the mstatus register and the MPP field in the mstatus register * contains S or U. Optionally, PMP checks may additionally apply to * M-mode accesses, in which case the PMP registers themselves are * locked, so that even M-mode software cannot change them without a * system reset. In effect, PMP can grant permissions to S and U * modes, which by default have none, and can revoke permissions from * M-mode, which by default has full permissions." */ bool riscv_cpu_pmp_access_ok(RISCVCPUState *s, uint64_t paddr, size_t size, pmpcfg_t perm) { return true; //FIXME: HACK for Ariane int priv; /* rv64mi-p-access expects illegal physical addresses to fail. */ if ((uint64_t)paddr >> s->physical_addr_len != 0) return false; if ((s->mstatus & MSTATUS_MPRV) && !(perm & PMPCFG_X)) { /* use previous privilege */ priv = (s->mstatus >> MSTATUS_MPP_SHIFT) & 3; } else { priv = s->priv; } // Check for _any_ bytes from the range overlapping with a PMP // region (we don't support the cases where the PMP region is // smaller than the access). for (int i = 0; i < s->pmp_n; ++i) // [lo;hi) `intersect` [paddr;paddr+size) is non-empty if (s->pmp[i].lo <= paddr + size - 1 && paddr < s->pmp[i].hi) if (priv < PRV_M || s->pmpcfg[i] & PMPCFG_L) return (perm & s->pmpcfg[i]) == perm; else return true; return priv == PRV_M; } static inline PhysMemoryRange * get_phys_mem_range_pmp(RISCVCPUState *s, uint64_t paddr, size_t size, pmpcfg_t perm) { if (!riscv_cpu_pmp_access_ok(s, paddr, size, perm)) return NULL; else return get_phys_mem_range(s->mem_map, paddr); } /* addr must be aligned. Only RAM accesses are supported */ #define PHYS_MEM_READ_WRITE(size, uint_type) \ void riscv_phys_write_u ## size(RISCVCPUState *s, target_ulong paddr, \ uint_type val, bool *fail) \ { \ PhysMemoryRange *pr = get_phys_mem_range_pmp(s, paddr, size/8, PMPCFG_W); \ if (!pr || !pr->is_ram) { \ *fail = true; \ return; \ } \ track_write(s, paddr, paddr, val, size); \ *(uint_type *)(pr->phys_mem + (uintptr_t)(paddr - pr->addr)) = val; \ *fail = false; \ } \ \ uint_type riscv_phys_read_u ## size(RISCVCPUState *s, target_ulong paddr, \ bool *fail) \ { \ PhysMemoryRange *pr = get_phys_mem_range_pmp(s, paddr, size/8, PMPCFG_R); \ if (!pr) { \ *fail = true; \ return 0; \ } \ uint_type pval = *(uint_type *)(pr->phys_mem + \ (uintptr_t)(paddr - pr->addr)); \ pval = track_dread(s, paddr, paddr, pval, size); \ *fail = false; \ return pval; \ } PHYS_MEM_READ_WRITE(8, uint8_t) PHYS_MEM_READ_WRITE(32, uint32_t) PHYS_MEM_READ_WRITE(64, uint64_t) /* return 0 if OK, != 0 if exception */ #define TARGET_READ_WRITE(size, uint_type, size_log2) \ static inline __exception int target_read_u ## size(RISCVCPUState *s, uint_type *pval, target_ulong addr) \ { \ uint32_t tlb_idx; \ if (!CONFIG_ALLOW_MISALIGNED_ACCESS && (addr & (size/8 - 1)) != 0) { \ s->pending_tval = addr; \ s->pending_exception = CAUSE_MISALIGNED_LOAD; \ return -1; \ } \ tlb_idx = (addr >> PG_SHIFT) & (TLB_SIZE - 1); \ if (likely(s->tlb_read[tlb_idx].vaddr == (addr & ~(PG_MASK & ~((size / 8) - 1))))) { \ uint64_t data = *(uint_type *)(s->tlb_read[tlb_idx].mem_addend + (uintptr_t)addr); \ uint64_t paddr = s->tlb_read_paddr_addend[tlb_idx] + addr; \ *pval = track_dread(s, addr, paddr, data, size); \ return 0; \ } \ \ mem_uint_t val; \ int ret = riscv_cpu_read_memory(s, &val, addr, size_log2); \ if (ret) \ return ret; \ *pval = val; \ return 0; \ } \ \ static inline __exception int target_write_u ## size(RISCVCPUState *s, target_ulong addr, uint_type val) \ { \ uint32_t tlb_idx; \ if (!CONFIG_ALLOW_MISALIGNED_ACCESS && (addr & (size/8 - 1)) != 0) { \ s->pending_tval = addr; \ s->pending_exception = CAUSE_MISALIGNED_STORE; \ return -1; \ } \ tlb_idx = (addr >> PG_SHIFT) & (TLB_SIZE - 1); \ if (likely(s->tlb_write[tlb_idx].vaddr == (addr & ~(PG_MASK & ~((size / 8) - 1))))) { \ *(uint_type *)(s->tlb_write[tlb_idx].mem_addend + (uintptr_t)addr) = val; \ uint64_t paddr = s->tlb_write_paddr_addend[tlb_idx] + addr; \ track_write(s, addr, paddr, val, size); \ return 0; \ } \ \ return riscv_cpu_write_memory(s, addr, val, size_log2); \ } TARGET_READ_WRITE(8, uint8_t, 0) TARGET_READ_WRITE(16, uint16_t, 1) TARGET_READ_WRITE(32, uint32_t, 2) #if MLEN >= 64 TARGET_READ_WRITE(64, uint64_t, 3) #endif #if MLEN >= 128 TARGET_READ_WRITE(128, uint128_t, 4) #endif #define PTE_V_MASK (1 << 0) #define PTE_U_MASK (1 << 4) #define PTE_A_MASK (1 << 6) #define PTE_D_MASK (1 << 7) /* access = 0: read, 1 = write, 2 = code. Set the exception_pending field if necessary. return 0 if OK, -1 if translation error, -2 if the physical address is illegal. */ int riscv_cpu_get_phys_addr(RISCVCPUState *s, target_ulong vaddr, riscv_memory_access_t access, target_ulong *ppaddr) { int mode, levels, pte_bits, pte_idx, pte_mask, pte_size_log2, xwr, priv; int need_write, vaddr_shift, i, pte_addr_bits; target_ulong pte_addr, pte, vaddr_mask, paddr; if ((s->mstatus & MSTATUS_MPRV) && access != ACCESS_CODE) { /* use previous privilege */ priv = (s->mstatus >> MSTATUS_MPP_SHIFT) & 3; } else { priv = s->priv; } if (priv == PRV_M) { *ppaddr = vaddr; return 0; } mode = (s->satp >> 60) & 0xf; if (mode == 0) { /* bare: no translation */ *ppaddr = vaddr; return 0; } else { /* sv39/sv48 */ levels = mode - 8 + 3; pte_size_log2 = 3; vaddr_shift = 64 - (PG_SHIFT + levels * 9); if ((((target_long)vaddr << vaddr_shift) >> vaddr_shift) != (target_long)vaddr) return -1; pte_addr_bits = 44; } pte_addr = (s->satp & (((target_ulong)1 << pte_addr_bits) - 1)) << PG_SHIFT; pte_bits = 12 - pte_size_log2; pte_mask = (1 << pte_bits) - 1; for (i = 0; i < levels; i++) { bool fail; vaddr_shift = PG_SHIFT + pte_bits * (levels - 1 - i); pte_idx = (vaddr >> vaddr_shift) & pte_mask; pte_addr += pte_idx << pte_size_log2; if (pte_size_log2 == 2) pte = riscv_phys_read_u32(s, pte_addr, &fail); else pte = riscv_phys_read_u64(s, pte_addr, &fail); if (fail) return -2; if (!(pte & PTE_V_MASK)) return -1; /* invalid PTE */ paddr = (pte >> 10) << PG_SHIFT; xwr = (pte >> 1) & 7; if (xwr != 0) { if (xwr == 2 || xwr == 6) return -1; /* priviledge check */ if (priv == PRV_S) { if ((pte & PTE_U_MASK) && !(s->mstatus & MSTATUS_SUM)) return -1; } else { if (!(pte & PTE_U_MASK)) return -1; } /* protection check */ /* MXR allows read access to execute-only pages */ if (s->mstatus & MSTATUS_MXR) xwr |= (xwr >> 2); if (((xwr >> access) & 1) == 0) return -1; /* 6. Check for misaligned superpages */ unsigned ppn = pte >> 10; int j = levels-1 - i; if (((1 << j) - 1) & ppn) return -1; /* RISC-V Priv. Spec 1.11 (draft) Section 4.3.1 offers two ways to handle the A and D TLB flags. Spike uses the software managed approach whereas DROMAJO used to manage them (causing far fewer exceptions). */ if (CONFIG_SW_MANAGED_A_AND_D) { if (!(pte & PTE_A_MASK)) return -1; // Must have A on access if (access == ACCESS_WRITE && !(pte & PTE_D_MASK)) return -1; // Must have D on write } else { need_write = !(pte & PTE_A_MASK) || (!(pte & PTE_D_MASK) && access == ACCESS_WRITE); pte |= PTE_A_MASK; if (access == ACCESS_WRITE) pte |= PTE_D_MASK; if (need_write) { bool fail; if (pte_size_log2 == 2) riscv_phys_write_u32(s, pte_addr, pte, &fail); else riscv_phys_write_u64(s, pte_addr, pte, &fail); if (fail) return -2; } } vaddr_mask = ((target_ulong)1 << vaddr_shift) - 1; *ppaddr = paddr & ~vaddr_mask | vaddr & vaddr_mask; return 0; } pte_addr = paddr; } return -1; } /* return 0 if OK, != 0 if exception */ no_inline int riscv_cpu_read_memory(RISCVCPUState *s, mem_uint_t *pval, target_ulong addr, int size_log2) { int size, tlb_idx, err, al; target_ulong paddr, offset; uint8_t *ptr; PhysMemoryRange *pr; mem_uint_t ret; /* first handle unaligned accesses */ size = 1 << size_log2; al = addr & (size - 1); if (!CONFIG_ALLOW_MISALIGNED_ACCESS && al != 0) { s->pending_tval = addr; s->pending_exception = CAUSE_MISALIGNED_LOAD; return -1; } if (al != 0) { switch (size_log2) { case 1: { uint8_t v0, v1; err = target_read_u8(s, &v0, addr); if (err) return err; err = target_read_u8(s, &v1, addr + 1); if (err) return err; ret = v0 | (v1 << 8); } break; case 2: { uint32_t v0, v1; addr -= al; err = target_read_u32(s, &v0, addr); if (err) return err; err = target_read_u32(s, &v1, addr + 4); if (err) return err; ret = (v0 >> (al * 8)) | (v1 << (32 - al * 8)); } break; #if MLEN >= 64 case 3: { uint64_t v0, v1; addr -= al; err = target_read_u64(s, &v0, addr); if (err) return err; err = target_read_u64(s, &v1, addr + 8); if (err) return err; ret = (v0 >> (al * 8)) | (v1 << (64 - al * 8)); } break; #endif #if MLEN >= 128 case 4: { uint128_t v0, v1; addr -= al; err = target_read_u128(s, &v0, addr); if (err) return err; err = target_read_u128(s, &v1, addr + 16); if (err) return err; ret = (v0 >> (al * 8)) | (v1 << (128 - al * 8)); } break; #endif default: abort(); } paddr = addr; // No translation for this request } else { int err = riscv_cpu_get_phys_addr(s, addr, ACCESS_READ, &paddr); if (err) { s->pending_tval = addr; s->pending_exception = err == -1 ? CAUSE_LOAD_PAGE_FAULT : CAUSE_FAULT_LOAD; return -1; } pr = get_phys_mem_range_pmp(s, paddr, size, PMPCFG_R); if (!pr) { #ifdef DUMP_INVALID_MEM_ACCESS fprintf(dromajo_stderr, "riscv_cpu_read_memory: invalid physical address 0x"); print_target_ulong(paddr); fprintf(dromajo_stderr, "\n"); #endif s->pending_tval = addr; s->pending_exception = CAUSE_FAULT_LOAD; return -1; } if (pr->is_ram) { tlb_idx = (addr >> PG_SHIFT) & (TLB_SIZE - 1); ptr = pr->phys_mem + (uintptr_t)(paddr - pr->addr); s->tlb_read[tlb_idx].vaddr = addr & ~PG_MASK; #ifdef PADDR_INLINE s->tlb_read[tlb_idx].paddr_addend = paddr - addr; #else s->tlb_read_paddr_addend[tlb_idx] = paddr - addr; #endif s->tlb_read[tlb_idx].mem_addend = (uintptr_t)ptr - addr; switch (size_log2) { case 0: ret = *(uint8_t *)ptr; break; case 1: ret = *(uint16_t *)ptr; break; case 2: ret = *(uint32_t *)ptr; break; #if MLEN >= 64 case 3: ret = *(uint64_t *)ptr; break; #endif #if MLEN >= 128 case 4: ret = *(uint128_t *)ptr; break; #endif default: abort(); } } else { offset = paddr - pr->addr; if (((pr->devio_flags >> size_log2) & 1) != 0) { ret = pr->read_func(pr->opaque, offset, size_log2); } #if MLEN >= 64 else if ((pr->devio_flags & DEVIO_SIZE32) && size_log2 == 3) { /* emulate 64 bit access */ ret = pr->read_func(pr->opaque, offset, 2); ret |= (uint64_t)pr->read_func(pr->opaque, offset + 4, 2) << 32; } #endif else { #ifdef DUMP_INVALID_MEM_ACCESS fprintf(dromajo_stderr, "unsupported device read access: addr=0x"); print_target_ulong(paddr); fprintf(dromajo_stderr, " width=%d bits\n", 1 << (3 + size_log2)); #endif ret = 0; } } } *pval = track_dread(s, addr, paddr, ret, size); return 0; } /* return 0 if OK, != 0 if exception */ no_inline int riscv_cpu_write_memory(RISCVCPUState *s, target_ulong addr, mem_uint_t val, int size_log2) { int size, i, tlb_idx, err; target_ulong paddr, offset; uint8_t *ptr; PhysMemoryRange *pr; /* first handle unaligned accesses */ size = 1 << size_log2; if (!CONFIG_ALLOW_MISALIGNED_ACCESS && (addr & (size - 1)) != 0) { s->pending_tval = addr; s->pending_exception = CAUSE_MISALIGNED_STORE; return -1; } else if ((addr & (size - 1)) != 0) { for (i = 0; i < size; i++) { err = target_write_u8(s, addr + i, (val >> (8 * i)) & 0xff); if (err) return err; } paddr = addr; } else { int err = riscv_cpu_get_phys_addr(s, addr, ACCESS_WRITE, &paddr); if (err) { s->pending_tval = addr; s->pending_exception = err == -1 ? CAUSE_STORE_PAGE_FAULT : CAUSE_FAULT_STORE; return -1; } pr = get_phys_mem_range_pmp(s, paddr, size, PMPCFG_W); if (!pr) { #ifdef DUMP_INVALID_MEM_ACCESS fprintf(dromajo_stderr, "riscv_cpu_write_memory: invalid physical address 0x"); print_target_ulong(paddr); fprintf(dromajo_stderr, "\n"); #endif s->pending_tval = addr; s->pending_exception = CAUSE_FAULT_STORE; return -1; } else if (pr->is_ram) { phys_mem_set_dirty_bit(pr, paddr - pr->addr); tlb_idx = (addr >> PG_SHIFT) & (TLB_SIZE - 1); ptr = pr->phys_mem + (uintptr_t)(paddr - pr->addr); s->tlb_write[tlb_idx].vaddr = addr & ~PG_MASK; #ifdef PADDR_INLINE s->tlb_write[tlb_idx].paddr_addend = paddr - addr; #else s->tlb_write_paddr_addend[tlb_idx] = paddr - addr; #endif s->tlb_write[tlb_idx].mem_addend = (uintptr_t)ptr - addr; switch (size_log2) { case 0: *(uint8_t *)ptr = val; break; case 1: *(uint16_t *)ptr = val; break; case 2: *(uint32_t *)ptr = val; break; #if MLEN >= 64 case 3: *(uint64_t *)ptr = val; break; #endif #if MLEN >= 128 case 4: *(uint128_t *)ptr = val; break; #endif default: abort(); } } else { offset = paddr - pr->addr; if (((pr->devio_flags >> size_log2) & 1) != 0) { pr->write_func(pr->opaque, offset, val, size_log2); } #if MLEN >= 64 else if ((pr->devio_flags & DEVIO_SIZE32) && size_log2 == 3) { /* emulate 64 bit access */ pr->write_func(pr->opaque, offset, val & 0xffffffff, 2); pr->write_func(pr->opaque, offset + 4, (val >> 32) & 0xffffffff, 2); } #endif else { #ifdef DUMP_INVALID_MEM_ACCESS fprintf(dromajo_stderr, "unsupported device write access: addr=0x"); print_target_ulong(paddr); fprintf(dromajo_stderr, " width=%d bits\n", 1 << (3 + size_log2)); #endif } } } track_write(s, addr, paddr, val, size); return 0; } struct __attribute__((packed)) unaligned_u32 { uint32_t u32; }; /* unaligned access at an address known to be a multiple of 2 */ static uint32_t get_insn32(uint8_t *ptr) { return ((struct unaligned_u32 *)ptr)->u32; } /* return 0 if OK, != 0 if exception */ static no_inline __exception int target_read_insn_slow(RISCVCPUState *s, uint32_t *insn, int size, target_ulong addr) { int tlb_idx; target_ulong paddr; uint8_t *ptr; PhysMemoryRange *pr; int err = riscv_cpu_get_phys_addr(s, addr, ACCESS_CODE, &paddr); if (err) { s->pending_tval = addr; s->pending_exception = err == -1 ? CAUSE_FETCH_PAGE_FAULT : CAUSE_FAULT_FETCH; return -1; } pr = get_phys_mem_range_pmp(s, paddr, size/8, PMPCFG_X); if (!pr || !pr->is_ram) { /* We only allow execution from RAM */ s->pending_tval = addr; s->pending_exception = CAUSE_FAULT_FETCH; return -1; } tlb_idx = (addr >> PG_SHIFT) & (TLB_SIZE - 1); ptr = pr->phys_mem + (uintptr_t)(paddr - pr->addr); if (riscv_cpu_pmp_access_ok(s, paddr & ~PG_MASK, PG_MASK + 1, PMPCFG_X)) { /* All of this page has full execute access so we can bypass * the slow PMP checks. */ s->tlb_code[tlb_idx].vaddr = addr & ~PG_MASK; s->tlb_code_paddr_addend[tlb_idx] = paddr - addr; s->tlb_code[tlb_idx].mem_addend = (uintptr_t)ptr - addr; } /* check for page crossing */ int tlb_idx_cross = ((addr+2) >> PG_SHIFT) & (TLB_SIZE - 1); if (tlb_idx != tlb_idx_cross && size == 32) { target_ulong paddr_cross; int err = riscv_cpu_get_phys_addr(s, addr+2, ACCESS_CODE, &paddr_cross); if (err) { s->pending_tval = addr; s->pending_exception = err == -1 ? CAUSE_FETCH_PAGE_FAULT : CAUSE_FAULT_FETCH; return -1; } PhysMemoryRange *pr_cross = get_phys_mem_range_pmp(s, paddr_cross, 2, PMPCFG_X); if (!pr_cross || !pr_cross->is_ram) { /* We only allow execution from RAM */ s->pending_tval = addr; s->pending_exception = CAUSE_FAULT_FETCH; return -1; } uint8_t *ptr_cross = pr_cross->phys_mem + (uintptr_t)(paddr_cross - pr_cross->addr); uint32_t data1 = (uint32_t)*((uint16_t*)ptr); uint32_t data2 = (uint32_t)*((uint16_t*)ptr_cross); data1 = track_iread(s, addr, paddr, data1, 16); data2 = track_iread(s, addr, paddr_cross, data2, 16); *insn = data1 | (data2 << 16); return 0; } if (size == 32) { *insn = (uint32_t)*((uint32_t*)ptr); } else if (size == 16) { *insn = (uint32_t)*((uint16_t*)ptr); } else { assert(0); } *insn = track_iread(s, addr, paddr, *insn, size); return 0; } /* addr must be aligned */ static inline __exception int target_read_insn_u16(RISCVCPUState *s, uint16_t *pinsn, target_ulong addr) { uintptr_t mem_addend; uint32_t tlb_idx = (addr >> PG_SHIFT) & (TLB_SIZE - 1); if (likely(s->tlb_code[tlb_idx].vaddr == (addr & ~PG_MASK))) { mem_addend = s->tlb_code[tlb_idx].mem_addend; uint32_t data = *(uint16_t *)(mem_addend + (uintptr_t)addr); #ifdef PADDR_INLINE *pinsn = track_iread(s, addr, s->tlb_code[tlb_idx].paddr_addend + addr, data, 16); #else *pinsn = track_iread(s, addr, s->tlb_code_paddr_addend[tlb_idx] + addr, data, 16); #endif return 0; } uint32_t pinsn_temp; if (target_read_insn_slow(s, &pinsn_temp, 16, addr)) return -1; *pinsn = pinsn_temp; return 0; } static void tlb_init(RISCVCPUState *s) { for (int i = 0; i < TLB_SIZE; i++) { s->tlb_read[i].vaddr = -1; s->tlb_write[i].vaddr = -1; s->tlb_code[i].vaddr = -1; } } static void tlb_flush_all(RISCVCPUState *s) { tlb_init(s); } static void tlb_flush_vaddr(RISCVCPUState *s, target_ulong vaddr) { tlb_flush_all(s); } void riscv_cpu_flush_tlb_write_range_ram(RISCVCPUState *s, uint8_t *ram_ptr, size_t ram_size) { uint8_t *ram_end = ram_ptr + ram_size; for (int i = 0; i < TLB_SIZE; i++) if (s->tlb_write[i].vaddr != (target_ulong)-1) { uint8_t *ptr = (uint8_t *) (s->tlb_write[i].mem_addend + (uintptr_t)s->tlb_write[i].vaddr); if (ram_ptr <= ptr && ptr < ram_end) s->tlb_write[i].vaddr = -1; } } #define SSTATUS_MASK ( MSTATUS_SIE \ | MSTATUS_SPIE \ | MSTATUS_SPP \ | MSTATUS_FS \ | MSTATUS_SUM \ | MSTATUS_MXR \ | MSTATUS_UXL_MASK ) #define MSTATUS_MASK ( MSTATUS_SIE \ | MSTATUS_MIE \ | MSTATUS_SPIE \ | MSTATUS_MPIE \ | MSTATUS_SPP \ | MSTATUS_MPP \ | MSTATUS_FS \ | MSTATUS_MPRV \ | MSTATUS_SUM \ | MSTATUS_MXR \ | MSTATUS_TVM \ | MSTATUS_TW \ | MSTATUS_TSR \ | MSTATUS_UXL_MASK \ | MSTATUS_SXL_MASK ) /* return the complete mstatus with the SD bit */ static target_ulong get_mstatus(RISCVCPUState *s, target_ulong mask) { target_ulong val; BOOL sd; val = s->mstatus | (s->fs << MSTATUS_FS_SHIFT); val &= mask; sd = ((val & MSTATUS_FS) == MSTATUS_FS) | ((val & MSTATUS_XS) == MSTATUS_XS); if (sd) val |= (target_ulong)1 << 63; return val; } static void set_mstatus(RISCVCPUState *s, target_ulong val) { /* flush the TLBs if change of MMU config */ target_ulong mod = s->mstatus ^ val; if ((mod & (MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR)) != 0 || ((s->mstatus & MSTATUS_MPRV) && (mod & MSTATUS_MPP) != 0)) { tlb_flush_all(s); } s->fs = (val >> MSTATUS_FS_SHIFT) & 3; target_ulong mask = MSTATUS_MASK & ~(MSTATUS_FS | MSTATUS_UXL_MASK | MSTATUS_SXL_MASK); s->mstatus = s->mstatus & ~mask | val & mask; } static BOOL counter_access_ok(RISCVCPUState *s, uint32_t csr) { uint32_t counteren = 0; switch (s->priv) { case PRV_U: counteren = s->scounteren; break; case PRV_S: counteren = s->mcounteren; break; case PRV_M: counteren = ~0; break; default: ; } return (counteren >> (csr & 31)) & 1; } /* return -1 if invalid CSR. 0 if OK. 'will_write' indicate that the csr will be written after (used for CSR access check) */ static int csr_read(RISCVCPUState *s, target_ulong *pval, uint32_t csr, BOOL will_write) { target_ulong val; if (((csr & 0xc00) == 0xc00) && will_write) return -1; /* read-only CSR */ if (s->priv < ((csr >> 8) & 3)) return -1; /* not enough priviledge */ switch (csr) { #if FLEN > 0 case 0x001: /* fflags */ if (s->fs == 0) return -1; val = s->fflags; break; case 0x002: /* frm */ if (s->fs == 0) return -1; val = s->frm; break; case 0x003: if (s->fs == 0) return -1; val = s->fflags | (s->frm << 5); break; #endif case 0x100: val = get_mstatus(s, SSTATUS_MASK); break; case 0x104: /* sie */ val = s->mie & s->mideleg; break; case 0x105: val = s->stvec; break; case 0x106: val = s->scounteren; break; case 0x140: val = s->sscratch; break; case 0x141: val = s->sepc; break; case 0x142: val = s->scause; break; case 0x143: val = s->stval; break; case 0x144: /* sip */ val = s->mip & s->mideleg; break; case 0x180: if (s->priv == PRV_S && s->mstatus & MSTATUS_TVM) return -1; val = s->satp; break; case 0x300: val = get_mstatus(s, (target_ulong)-1); break; case 0x301: val = s->misa; val |= (target_ulong)2 << 62; break; case 0x302: val = s->medeleg; break; case 0x303: val = s->mideleg; break; case 0x304: val = s->mie; break; case 0x305: val = s->mtvec; break; case 0x306: val = s->mcounteren; break; case 0x320: val = s->mcountinhibit; break; case 0x340: val = s->mscratch; break; case 0x341: val = s->mepc; break; case 0x342: val = s->mcause; break; case 0x343: val = s->mtval; break; case 0x344: val = s->mip; break; case 0x7a0: // tselect val = s->tselect; break; case 0x7a1: // tdata1 val = s->tdata1[s->tselect]; break; case 0x7a2: // tdata2 val = s->tdata2[s->tselect]; break; case 0x7a3: // tdata3 val = s->tdata3[s->tselect]; break; case 0x7b0: if (!s->debug_mode) goto invalid_csr; val = s->dcsr; break; case 0x7b1: if (!s->debug_mode) goto invalid_csr; val = s->dpc; break; case 0x7b2: if (!s->debug_mode) goto invalid_csr; val = s->dscratch; break; case 0xb00: /* mcycle */ case 0xc00: /* cycle */ if (!counter_access_ok(s, csr)) goto invalid_csr; val = (int64_t)s->mcycle; break; case 0xb02: /* minstret */ case 0xc02: /* uinstret */ if (!counter_access_ok(s, csr)) goto invalid_csr; val = (int64_t)s->minstret; break; case 0xb03: case 0xc03: case 0xb04: case 0xc04: case 0xb05: case 0xc05: case 0xb06: case 0xc06: case 0xb07: case 0xc07: case 0xb08: case 0xc08: case 0xb09: case 0xc09: case 0xb0a: case 0xc0a: case 0xb0b: case 0xc0b: case 0xb0c: case 0xc0c: case 0xb0d: case 0xc0d: case 0xb0e: case 0xc0e: case 0xb0f: case 0xc0f: case 0xb10: case 0xc10: case 0xb11: case 0xc11: case 0xb12: case 0xc12: case 0xb13: case 0xc13: case 0xb14: case 0xc14: case 0xb15: case 0xc15: case 0xb16: case 0xc16: case 0xb17: case 0xc17: case 0xb18: case 0xc18: case 0xb19: case 0xc19: case 0xb1a: case 0xc1a: case 0xb1b: case 0xc1b: case 0xb1c: case 0xc1c: case 0xb1d: case 0xc1d: case 0xb1e: case 0xc1e: case 0xb1f: case 0xc1f: if (!counter_access_ok(s, csr)) goto invalid_csr; val = 0; // mhpmcounter3..31 break; case 0xf14: val = s->mhartid; break; case 0xf13: val = s->mimpid; break; case 0xf12: val = s->marchid; break; case 0xf11: val = s->mvendorid; break; case 0x323: case 0x324: case 0x325: case 0x326: case 0x327: case 0x328: case 0x329: case 0x32a: case 0x32b: case 0x32c: case 0x32d: case 0x32e: case 0x32f: case 0x330: case 0x331: case 0x332: case 0x333: case 0x334: case 0x335: case 0x336: case 0x337: case 0x338: case 0x339: case 0x33a: case 0x33b: case 0x33c: case 0x33d: case 0x33e: case 0x33f: val = s->mhpmevent[csr & 0x1F]; break; case CSR_PMPCFG(0): // NB: 1 and 3 are _illegal_ in RV64 case CSR_PMPCFG(2): val = s->csr_pmpcfg[csr - CSR_PMPCFG(0)]; break; case CSR_PMPADDR(0): // NB: *must* support either none or all case CSR_PMPADDR(1): case CSR_PMPADDR(2): case CSR_PMPADDR(3): case CSR_PMPADDR(4): case CSR_PMPADDR(5): case CSR_PMPADDR(6): case CSR_PMPADDR(7): case CSR_PMPADDR(8): case CSR_PMPADDR(9): case CSR_PMPADDR(10): case CSR_PMPADDR(11): case CSR_PMPADDR(12): case CSR_PMPADDR(13): case CSR_PMPADDR(14): case CSR_PMPADDR(15): val = s->csr_pmpaddr[csr - CSR_PMPADDR(0)]; break; default: invalid_csr: if (s->machine->hooks.csr_read) return s->machine->hooks.csr_read(s, csr, pval); #ifdef DUMP_INVALID_CSR /* the 'time' counter is usually emulated */ if (csr != 0xc01 && csr != 0xc81) { fprintf(dromajo_stderr, "csr_read: invalid CSR=0x%x\n", csr); } #endif *pval = 0; return -1; } #if defined(DUMP_CSR) fprintf(stderr, "csr_read: hartid=%d csr=0x%03x val=0x%x\n", (int)s->mhartid, csr, (int)val); #endif *pval = val; return 0; } #if FLEN > 0 static void set_frm(RISCVCPUState *s, unsigned int val) { s->frm = val; } /* return -1 if invalid roundind mode */ static int get_insn_rm(RISCVCPUState *s, unsigned int rm) { if (rm == 7) rm = s->frm; if (rm >= 5) return -1; else return rm; } #endif static void unpack_pmpaddrs(RISCVCPUState *s) { uint8_t cfg; s->pmp_n = 0; for (int i = 0; i < 16; ++i) { if (i < 8) cfg = s->csr_pmpcfg[0] >> (i * 8); else cfg = s->csr_pmpcfg[2] >> ((i - 8) * 8); switch (cfg & PMPCFG_A_MASK) { case PMPCFG_A_OFF: break; case PMPCFG_A_TOR: s->pmpcfg[s->pmp_n] = cfg; s->pmp[s->pmp_n].lo = i == 0 ? 0 : s->csr_pmpaddr[i-1] << 2; s->pmp[s->pmp_n].hi = s->csr_pmpaddr[i] << 2; s->pmp_n++; break; case PMPCFG_A_NA4: s->pmpcfg[s->pmp_n] = cfg; s->pmp[s->pmp_n].lo = s->csr_pmpaddr[i] << 2; s->pmp[s->pmp_n].hi = (s->csr_pmpaddr[i] << 2) + 4; s->pmp_n++; break; case PMPCFG_A_NAPOT: { s->pmpcfg[s->pmp_n] = cfg; int j; // Count trailing ones for (j = 0; j < 64; ++j) if ((s->csr_pmpaddr[i] & (1 << j)) == 0) break; j += 3; // 8-byte is the lowest option // NB, meaningless when i >= 56! if (j >= 64) { s->pmp[s->pmp_n].lo = 0; s->pmp[s->pmp_n].hi = ~0ll; } else { s->pmp[s->pmp_n].lo = (s->csr_pmpaddr[i] << 2) & ~((1llu << j) - 1); s->pmp[s->pmp_n].hi = s->pmp[s->pmp_n].lo + (1llu << j); if (s->pmp[s->pmp_n].hi <= s->pmp[s->pmp_n].lo) // Overflowed s->pmp[s->pmp_n].hi = ~0ll; } s->pmp_n++; break; } } } tlb_flush_all(s); // The TLB partically caches PMP decisions } /* return -1 if invalid CSR, 0 if OK, -2 if CSR raised an exception, * 2 if TLBs have been flushed. */ static int csr_write(RISCVCPUState *s, uint32_t csr, target_ulong val) { target_ulong mask; #if defined(DUMP_CSR) fprintf(dromajo_stderr, "csr_write: hardid=%d csr=0x%03x val=0x", (int)s->mhartid, csr); print_target_ulong(val); fprintf(dromajo_stderr, "\n"); #endif switch (csr) { #if FLEN > 0 case 0x001: /* fflags */ s->fflags = val & 0x1f; s->fs = 3; break; case 0x002: /* frm */ set_frm(s, val & 7); s->fs = 3; break; case 0x003: /* fcsr */ set_frm(s, (val >> 5) & 7); s->fflags = val & 0x1f; s->fs = 3; break; #endif case 0x100: /* sstatus */ set_mstatus(s, s->mstatus & ~SSTATUS_MASK | val & SSTATUS_MASK); break; case 0x104: /* sie */ mask = s->mideleg; s->mie = s->mie & ~mask | val & mask; break; case 0x105: // enforce 256-byte alignment for vectored interrupts if (val & 1) val &= ~255 + 1; s->stvec = val & ~2; break; case 0x106: s->scounteren = val; break; case 0x140: s->sscratch = val; break; case 0x141: s->sepc = val & (s->misa & MCPUID_C ? ~1 : ~3); s->sepc = SEPC_TRUNCATE(s->sepc); break; case 0x142: s->scause = val & SCAUSE_MASK; break; case 0x143: s->stval = STVAL_TRUNCATE(val); break; case 0x144: /* sip */ mask = s->mideleg; s->mip = s->mip & ~mask | val & mask; break; case 0x180: if (s->priv == PRV_S && s->mstatus & MSTATUS_TVM) return -1; { uint64_t mode = (val >> 60) & 15; if (mode == 0 || mode == 8 || mode == 9) s->satp = val & SATP_MASK; } /* no ASID implemented [yet] */ tlb_flush_all(s); return 2; case 0x300: set_mstatus(s, val); break; case 0x301: /* misa */ /* We don't support changing misa */ break; case 0x302: { target_ulong mask = 0xB109; // matching Spike s->medeleg = s->medeleg & ~mask | val & mask; break; } case 0x303: mask = MIP_SSIP | MIP_STIP | MIP_SEIP; s->mideleg = s->mideleg & ~mask | val & mask; break; case 0x304: mask = MIE_MCIP /*| MIE_SCIP | MIE_UCIP*/ | MIE_MEIE | MIE_SEIE /*| MIE_UEIE*/ | MIE_MTIE | MIE_STIE | /*MIE_UTIE | */ MIE_MSIE | MIE_SSIE /*| MIE_USIE */; s->mie = s->mie & ~mask | val & mask; break; case 0x305: // enforce 256-byte alignment for vectored interrupts if (val & 1) val &= ~255 + 1; s->mtvec = val & ((1ull << s->physical_addr_len) - 3); // mtvec[1] === 0 break; case 0x306: s->mcounteren = val; break; case 0x320: s->mcountinhibit = val & ~2; break; case 0x340: s->mscratch = val; break; case 0x341: s->mepc = val & (s->misa & MCPUID_C ? ~1 : ~3); s->mepc = MEPC_TRUNCATE(s->mepc); break; case 0x342: s->mcause = val & MCAUSE_MASK; break; case 0x343: s->mtval = MTVAL_TRUNCATE(val); break; case 0x344: mask = /* MEIP | */ MIP_SEIP | /*MIP_UEIP | MTIP | */ MIP_STIP | /*MIP_UTIP | MSIP | */ MIP_SSIP /*| MIP_USIP*/; s->mip = s->mip & ~mask | val & mask; break; case 0x7a0: // tselect s->tselect = val % MAX_TRIGGERS; break; case 0x7a1: // tdata1 // Only support No Trigger and MControl { int type = val >> 60; if (type != 0 && type != 2) break; // SW can write type and mcontrol bits M and EXECUTE mask = ((target_ulong)15 << 60) | MCONTROL_M | MCONTROL_EXECUTE; s->tdata1[s->tselect] = s->tdata1[s->tselect] & ~mask | val & mask; } break; case 0x7a2: // tdata2 s->tdata2[s->tselect] = val; break; case 0x7a3: // tdata3 s->tdata3[s->tselect] = val; break; case 0x7b0: if (!s->debug_mode) goto invalid_csr; /* XXX We have a very incomplete implementation of debug mode, only just enough to restore a snapshot and stop counters */ mask = 0x603; // stopcount and stoptime && also the priv level to return s->dcsr = s->dcsr & ~mask | val & mask; s->stop_the_counter = s->dcsr & 0x600 != 0; break; case 0x7b1: if (!s->debug_mode) goto invalid_csr; s->dpc = val & (s->misa & MCPUID_C ? ~1 : ~3); break; case 0x7b2: if (!s->debug_mode) goto invalid_csr; s->dscratch = val; break; case 0x323: case 0x324: case 0x325: case 0x326: case 0x327: case 0x328: case 0x329: case 0x32a: case 0x32b: case 0x32c: case 0x32d: case 0x32e: case 0x32f: case 0x330: case 0x331: case 0x332: case 0x333: case 0x334: case 0x335: case 0x336: case 0x337: case 0x338: case 0x339: case 0x33a: case 0x33b: case 0x33c: case 0x33d: case 0x33e: case 0x33f: s->mhpmevent[csr & 0x1F] = val & (HPM_EVENT_SETMASK | HPM_EVENT_EVENTMASK); break; case CSR_PMPCFG(0): // NB: 1 and 3 are _illegal_ in RV64 case CSR_PMPCFG(2): { assert(PMP_N % 8 == 0); int c = csr - CSR_PMPCFG(0); if (PMP_N <= c/2 * 8) break; uint64_t orig = s->csr_pmpcfg[c]; uint64_t new_val = 0; for (int i = 0; i < 8; ++i) { uint64_t cfg = (orig >> (i * 8)) & 255; if ((cfg & PMPCFG_L) == 0) cfg = (val >> (i * 8)) & 255; cfg &= ~PMPCFG_RES; new_val |= cfg << (i * 8); } s->csr_pmpcfg[c] = new_val; unpack_pmpaddrs(s); break; } case CSR_PMPADDR(0): // NB: *must* support either none or all case CSR_PMPADDR(1): case CSR_PMPADDR(2): case CSR_PMPADDR(3): case CSR_PMPADDR(4): case CSR_PMPADDR(5): case CSR_PMPADDR(6): case CSR_PMPADDR(7): case CSR_PMPADDR(8): case CSR_PMPADDR(9): case CSR_PMPADDR(10): case CSR_PMPADDR(11): case CSR_PMPADDR(12): case CSR_PMPADDR(13): case CSR_PMPADDR(14): case CSR_PMPADDR(15): if (PMP_N <= csr - CSR_PMPADDR(0)) break; // Note, due to TOR ranges, one PMPADDR can affect two entries // but we just recalculate all of them s->csr_pmpaddr[csr - CSR_PMPADDR(0)] = val & PMPADDR_MASK; unpack_pmpaddrs(s); break; case 0xb00: /* mcycle */ s->mcycle = val; break; case 0xb02: /* minstret */ s->minstret = val; break; case 0xb03: case 0xb04: case 0xb05: case 0xb06: case 0xb07: case 0xb08: case 0xb09: case 0xb0a: case 0xb0b: case 0xb0c: case 0xb0d: case 0xb0e: case 0xb0f: case 0xb10: case 0xb11: case 0xb12: case 0xb13: case 0xb14: case 0xb15: case 0xb16: case 0xb17: case 0xb18: case 0xb19: case 0xb1a: case 0xb1b: case 0xb1c: case 0xb1d: case 0xb1e: case 0xb1f: // Allow, but ignore to write to performance counters mhpmcounter break; default: if (s->machine->hooks.csr_write) return s->machine->hooks.csr_write(s, csr, val); invalid_csr: #ifdef DUMP_INVALID_CSR fprintf(dromajo_stderr, "csr_write: invalid CSR=0x%x\n", csr); #endif return -1; } return 0; } static void set_priv(RISCVCPUState *s, int priv) { if (s->priv != priv) { tlb_flush_all(s); s->priv = priv; } } static void raise_exception2(RISCVCPUState *s, uint64_t cause, target_ulong tval) { BOOL deleg; #if defined(DUMP_EXCEPTIONS) const static char *cause_s[] = { "misaligned_fetch", "fault_fetch", "illegal_instruction", "breakpoint", "misaligned_load", "fault_load", "misaligned_store", "fault_store", "user_ecall", "<reserved (supervisor_ecall?)>", "<reserved (hypervisor_ecall?)>", "<reserved (machine_ecall?)>", "fetch_page_fault", "load_page_fault", "<reserved_14>", "store_page_fault", }; if (cause & CAUSE_INTERRUPT) fprintf(dromajo_stderr, "hartid=%d: exception interrupt #%d, epc 0x%016jx\n", (int)s->mhartid, cause & 63, (uintmax_t)s->pc); else if (cause <= CAUSE_STORE_PAGE_FAULT) { fprintf(dromajo_stderr, "hartid=%d priv: %d exception %s, epc 0x%016jx\n", (int)s->mhartid, s->priv, cause_s[cause], (uintmax_t)s->pc); fprintf(dromajo_stderr, "hartid=%d0 tval 0x%016jx\n", (int)s->mhartid, (uintmax_t)tval); } else { fprintf(dromajo_stderr, "hartid=%d: exception %d, epc 0x%016jx\n", (int)s->mhartid, cause, (uintmax_t)s->pc); fprintf(dromajo_stderr, "hartid=%d: tval 0x%016jx\n", (int)s->mhartid, (uintmax_t)tval); } #endif if (s->priv <= PRV_S) { /* delegate the exception to the supervisor priviledge */ if (cause & CAUSE_INTERRUPT) deleg = (s->mideleg >> (cause & 63)) & 1; else deleg = (s->medeleg >> cause) & 1; } else { deleg = 0; } target_ulong effective_tvec; if (deleg) { s->scause = cause; s->sepc = SEPC_TRUNCATE(s->pc); s->stval = STVAL_TRUNCATE(tval); s->mstatus = (s->mstatus & ~MSTATUS_SPIE) | (!!(s->mstatus & MSTATUS_SIE) << MSTATUS_SPIE_SHIFT); s->mstatus = (s->mstatus & ~MSTATUS_SPP) | (s->priv << MSTATUS_SPP_SHIFT); s->mstatus &= ~MSTATUS_SIE; set_priv(s, PRV_S); effective_tvec = s->stvec; } else { s->mcause = cause; s->mepc = MEPC_TRUNCATE(s->pc); s->mtval = MTVAL_TRUNCATE(tval); /* When a trap is taken from privilege mode y into privilege mode x, xPIE is set to the value of xIE; xIE is set to 0; and xPP is set to y. Here x = M, thus MPIE = MIE; MIE = 0; MPP = s->priv */ s->mstatus = (s->mstatus & ~MSTATUS_MPIE) | (!!(s->mstatus & MSTATUS_MIE) << MSTATUS_MPIE_SHIFT); s->mstatus = (s->mstatus & ~MSTATUS_MPP) | (s->priv << MSTATUS_MPP_SHIFT); s->mstatus &= ~MSTATUS_MIE; set_priv(s, PRV_M); effective_tvec = s->mtvec; } int mode = effective_tvec & 3; target_ulong base = effective_tvec & ~3; s->pc = base; if (mode == 1 && cause & CAUSE_INTERRUPT) s->pc += 4 * (cause & ~CAUSE_INTERRUPT); } static void raise_exception(RISCVCPUState *s, uint64_t cause) { raise_exception2(s, cause, 0); } static void handle_sret(RISCVCPUState *s) { /* Copy down SPIE to SIE and set SPIE */ s->mstatus &= ~MSTATUS_SIE; s->mstatus |= (s->mstatus >> 4) & MSTATUS_SIE; s->mstatus |= MSTATUS_SPIE; int spp = (s->mstatus & MSTATUS_SPP) >> MSTATUS_SPP_SHIFT; s->mstatus &= ~MSTATUS_SPP; set_priv(s, spp); s->pc = s->sepc; } static void handle_mret(RISCVCPUState *s) { /* Copy down MPIE to MIE and set MPIE */ s->mstatus &= ~MSTATUS_MIE; s->mstatus |= (s->mstatus >> 4) & MSTATUS_MIE; s->mstatus |= MSTATUS_MPIE; int mpp = (s->mstatus & MSTATUS_MPP) >> MSTATUS_MPP_SHIFT; s->mstatus &= ~MSTATUS_MPP; set_priv(s, mpp); s->pc = s->mepc; } static void handle_dret(RISCVCPUState *s) { s->stop_the_counter = FALSE; // Enable counters again s->debug_mode = FALSE; set_priv(s, s->dcsr & 3); s->pc = s->dpc; } static inline uint32_t get_pending_irq_mask(RISCVCPUState *s) { uint32_t pending_ints, enabled_ints; pending_ints = s->mip & s->mie; if (pending_ints == 0) return 0; enabled_ints = 0; switch (s->priv) { case PRV_M: if (s->mstatus & MSTATUS_MIE) enabled_ints = ~s->mideleg; break; case PRV_S: enabled_ints = ~s->mideleg; if (s->mstatus & MSTATUS_SIE) enabled_ints |= s->mideleg; break; default: case PRV_U: enabled_ints = -1; break; } return pending_ints & enabled_ints; } static __exception int raise_interrupt(RISCVCPUState *s) { uint32_t mask; int irq_num; mask = get_pending_irq_mask(s); if (mask == 0) return 0; irq_num = ctz32(mask); #ifdef DUMP_INTERRUPTS fprintf(dromajo_stderr, "raise_interrupt: irq=%d priv=%d pc=%llx hartid=%d\n", irq_num, s->priv, (unsigned long long)s->pc, (int)s->mhartid); #endif raise_exception(s, irq_num | CAUSE_INTERRUPT); return -1; } static inline int32_t sext(int32_t val, int n) { return (val << (32 - n)) >> (32 - n); } static inline uint32_t get_field1(uint32_t val, int src_pos, int dst_pos, int dst_pos_max) { int mask; assert(dst_pos_max >= dst_pos); mask = ((1 << (dst_pos_max - dst_pos + 1)) - 1) << dst_pos; if (dst_pos >= src_pos) return (val << (dst_pos - src_pos)) & mask; else return (val >> (src_pos - dst_pos)) & mask; } static inline RISCVCTFInfo ctf_compute_hint(int rd, int rs1) { int rd_link = rd == 1 || rd == 5; int rs1_link = rs1 == 1 || rs1 == 5; RISCVCTFInfo k = (RISCVCTFInfo)(rd_link * 2 + rs1_link + (int)ctf_taken_jalr); if (k == ctf_taken_jalr_pop_push && rs1 == rd) return ctf_taken_jalr_push; return k; } /* * While the 32-bit QNAN is defined in softfp.h, we need it here to * pull f_unbox{32,64} out of the fragile macro magic. */ static const sfloat64 f_qnan32 = 0x7fc00000; static sfloat64 f_unbox32(sfloat64 r) { if ((r & F32_HIGH) != F32_HIGH) return f_qnan32; return r; } static sfloat64 f_unbox64(sfloat64 r) { return r; } #define XLEN 32 #include "dromajo_template.h" #define XLEN 64 #include "dromajo_template.h" int riscv_cpu_interp(RISCVCPUState *s, int n_cycles) { return riscv_cpu_interp64(s, n_cycles); } /* Note: the value is not accurate when called in riscv_cpu_interp() */ uint64_t riscv_cpu_get_cycles(RISCVCPUState *s) { return s->mcycle; } void riscv_cpu_set_mip(RISCVCPUState *s, uint32_t mask) { s->mip |= mask; /* exit from power down if an interrupt is pending */ if (s->power_down_flag && (s->mip & s->mie) != 0 && (s->machine->common.pending_interrupt != -1 || !s->machine->common.cosim)) s->power_down_flag = FALSE; } void riscv_cpu_reset_mip(RISCVCPUState *s, uint32_t mask) { s->mip &= ~mask; } uint32_t riscv_cpu_get_mip(RISCVCPUState *s) { return s->mip; } BOOL riscv_cpu_get_power_down(RISCVCPUState *s) { return s->power_down_flag; } RISCVCPUState *riscv_cpu_init(RISCVMachine *machine, int hartid) { RISCVCPUState *s = (RISCVCPUState *)mallocz(sizeof *s); s->machine = machine; s->mem_map = machine->mem_map; s->pc = machine->reset_vector; s->priv = PRV_M; s->mstatus = ((uint64_t)2 << MSTATUS_UXL_SHIFT) | ((uint64_t)2 << MSTATUS_SXL_SHIFT) | (3 << MSTATUS_MPP_SHIFT); s->plic_enable_irq = 0; s->misa |= MCPUID_SUPER | MCPUID_USER | MCPUID_I | MCPUID_M | MCPUID_A; s->most_recently_written_reg = -1; #if FLEN >= 32 s->most_recently_written_fp_reg = -1; s->misa |= MCPUID_F; #endif #if FLEN >= 64 s->misa |= MCPUID_D; #endif #if FLEN >= 128 s->misa |= MCPUID_Q; #endif s->misa |= MCPUID_C; if (machine->custom_extension) s->misa |= MCPUID_X; s->mvendorid = 11 * 128 + 101; // Esperanto JEDEC number 101 in bank 11 (Change for your own) s->marchid = (1ULL << 63) | 2; s->mimpid = 1; s->mhartid = hartid; s->tselect = 0; for (int i = 0; i < MAX_TRIGGERS; ++i) { s->tdata1[i] = 2l << 60; s->tdata2[i] = ~(target_ulong)0; } tlb_init(s); // Exit code of the user-space benchmark app s->benchmark_exit_code = 0; return s; } void riscv_cpu_end(RISCVCPUState *s) { free(s); } void riscv_set_pc(RISCVCPUState *s, uint64_t val) { s->pc = val & (s->misa & MCPUID_C ? ~1 : ~3); } uint64_t riscv_get_pc(RISCVCPUState *s) { return s->pc; } uint64_t riscv_get_reg(RISCVCPUState *s, int rn) { assert(0 <= rn && rn < 32); return s->reg[rn]; } uint64_t riscv_get_reg_previous(RISCVCPUState *s, int rn) { assert(0 <= rn && rn < 32); return s->reg_prior[rn]; } void riscv_repair_csr(RISCVCPUState *s, uint32_t reg_num, uint64_t csr_num, uint64_t csr_val) { switch (csr_num & 0xFFF) { case 0xb00: case 0xc00: // mcycle s->mcycle = csr_val; s->reg[reg_num] = csr_val; break; case 0xb02: case 0xc02: // minstret s->minstret = csr_val; s->reg[reg_num] = csr_val; break; default: fprintf(dromajo_stderr, "riscv_repair_csr: This CSR is unsupported for repairing: %lx\n", (unsigned long)csr_num); break; } } /* Sync up the shadow register state if there are no errors */ void riscv_cpu_sync_regs(RISCVCPUState *s) { for (int i = 1; i < 32; ++i) { s->reg_prior[i] = s->reg[i]; } } uint64_t riscv_cpu_get_mstatus(RISCVCPUState* s) { return get_mstatus(s, MSTATUS_MASK); } uint64_t riscv_cpu_get_medeleg(RISCVCPUState* s) { return s->medeleg; } uint64_t riscv_get_fpreg(RISCVCPUState *s, int rn) { assert(0 <= rn && rn < 32); return s->fp_reg[rn]; } void riscv_set_reg(RISCVCPUState *s, int rn, uint64_t val) { assert(0 < rn && rn < 32); s->reg[rn] = val; } void riscv_dump_regs(RISCVCPUState *s) { dump_regs(s); } int riscv_read_insn(RISCVCPUState *s, uint32_t *insn, uint64_t addr) { /* target_read_insn_slow() wasn't designed for being used outside execution and will potentially raise exceptions. Unfortunately fixing this correctly is invasive so we just protect the affected state. */ int saved_pending_exception = s->pending_exception; target_ulong saved_pending_tval = s->pending_tval; int res = target_read_insn_slow(s, insn, 32, addr); s->pending_exception = saved_pending_exception; s->pending_tval = saved_pending_tval; return res; } uint32_t riscv_cpu_get_misa(RISCVCPUState *s) { return s->misa; } int riscv_get_priv_level(RISCVCPUState *s) { return s->priv; } int riscv_get_most_recently_written_reg(RISCVCPUState *s) { return s->most_recently_written_reg; } int riscv_get_most_recently_written_fp_reg(RISCVCPUState *s) { return s->most_recently_written_fp_reg; } int riscv_benchmark_exit_code(RISCVCPUState *s) { return s->benchmark_exit_code; } void riscv_get_ctf_info(RISCVCPUState *s, RISCVCTFInfo *info) { *info = s->info; } void riscv_get_ctf_target(RISCVCPUState *s, uint64_t *target) { *target = s->next_addr; } BOOL riscv_terminated(RISCVCPUState *s) { return s->terminate_simulation; } void riscv_set_debug_mode(RISCVCPUState *s, bool on) { s->debug_mode = on; } static void serialize_memory(const void *base, size_t size, const char *file) { int f_fd = open(file, O_CREAT | O_WRONLY | O_TRUNC, 0777); if (f_fd < 0) err(-3, "trying to write %s", file); while (size) { ssize_t written = write(f_fd, base, size); if (written <= 0) err(-3, "while writing %s", file); size -= written; } close(f_fd); } static void deserialize_memory(void *base, size_t size, const char *file) { int f_fd = open(file, O_RDONLY); if (f_fd < 0) err(-3, "trying to read %s", file); size_t sz = read(f_fd, base, size); if (sz != size) err(-3, "%s %zd size does not match memory size %zd", file, sz, size); close(f_fd); } static void dump_hex_memory(const void *base, size_t size, const char *file) { uint8_t* mem_pointer = (uint8_t*)base; std::ofstream hex_file; hex_file.open(file); int num_bytes = 8; uint32_t iter = 0; while (size) { // format uint32_t buffer1=0; uint32_t buffer2=0; for (int i=0; i<num_bytes; i++) { uint8_t b = *(mem_pointer); mem_pointer++; if (i < num_bytes/2) { buffer1 = buffer1 | (b << 8*i); } else { buffer2 = buffer2 | (b << 8*(i-num_bytes/2)); } } // dump if non-zero if (buffer1 > 0 || buffer2 > 0) { hex_file << std::dec << iter << " "; hex_file << std::hex << std::setfill('0') << std::setw(8) << buffer2; hex_file << std::hex << std::setfill('0') << std::setw(8) << buffer1; hex_file << std::endl; } size-=num_bytes; iter++; } hex_file.close(); } static uint32_t create_csrrw(int rs, uint32_t csrn) { return 0x1073 | ((csrn & 0xFFF) << 20) | ((rs & 0x1F) << 15); } static uint32_t create_csrrs(int rd, uint32_t csrn) { return 0x2073 | ((csrn & 0xFFF) << 20) | ((rd & 0x1F) << 7); } static uint32_t create_auipc(int rd, uint32_t addr) { if (addr & 0x800) addr += 0x800; return 0x17 | ((rd & 0x1F) << 7) | ((addr >> 12) << 12); } static uint32_t create_addi(int rd, uint32_t addr) { uint32_t pos = addr & 0xFFF; return 0x13 | ((rd & 0x1F) << 7) | ((rd & 0x1F) << 15) | ((pos & 0xFFF) << 20); } static uint32_t create_seti(int rd, uint32_t data) { return 0x13 | ((rd & 0x1F) << 7) | ((data & 0xFFF) << 20); } static uint32_t create_ld(int rd, int rs1) { return 3 | ((rd & 0x1F) << 7) | (3 << 12) | ((rs1 & 0x1F) << 15); } static uint32_t create_sd(int rs1, int rs2) { return 0x23 | ((rs2 & 0x1F) << 20) | (3 << 12) | ((rs1 & 0x1F) << 15); } static uint32_t create_fld(int rd, int rs1) { return 7 | ((rd & 0x1F) << 7) | (0x3<<12) | ((rs1 & 0x1F) << 15); } static bool skip_csr_recovery(RISCVCPUState *s, uint32_t csrn) { for (uint64_t i = 0; i < s->machine->missing_csrs_size; i++) { if (s->machine->missing_csrs[i] == csrn) { return true; } } return false; } static void create_csr12_recovery(uint32_t *rom, uint32_t *code_pos, uint32_t csrn, uint16_t val, RISCVCPUState *s) { if (skip_csr_recovery(s, csrn)) return; rom[(*code_pos)++] = create_seti(1, val & 0xFFF); rom[(*code_pos)++] = create_csrrw(1, csrn); } #ifdef LIVECACHE static void create_read_warmup(uint32_t *rom, uint32_t *code_pos, uint32_t *data_pos, uint64_t val) { uint32_t data_off = sizeof(uint32_t) * (*data_pos - *code_pos); rom[(*code_pos)++] = create_auipc(1, data_off); rom[(*code_pos)++] = create_addi(1, data_off); rom[(*code_pos)++] = create_ld(1, 1); rom[(*code_pos)++] = create_ld(1, 1); rom[(*data_pos)++] = val & 0xFFFFFFFF; rom[(*data_pos)++] = val >> 32; } #endif static void create_csr64_recovery(uint32_t *rom, uint32_t *code_pos, uint32_t *data_pos, uint32_t csrn, uint64_t val, RISCVCPUState *s) { if (skip_csr_recovery(s, csrn)) return; uint32_t data_off = sizeof(uint32_t) * (*data_pos - *code_pos); rom[(*code_pos)++] = create_auipc(1, data_off); rom[(*code_pos)++] = create_addi(1, data_off); rom[(*code_pos)++] = create_ld(1, 1); rom[(*code_pos)++] = create_csrrw(1, csrn); rom[(*data_pos)++] = val & 0xFFFFFFFF; rom[(*data_pos)++] = val >> 32; } static void create_reg_recovery(uint32_t *rom, uint32_t *code_pos, uint32_t *data_pos, int rn, uint64_t val) { uint32_t data_off = sizeof(uint32_t) * (*data_pos - *code_pos); rom[(*code_pos)++] = create_auipc(rn, data_off); rom[(*code_pos)++] = create_addi(rn, data_off); rom[(*code_pos)++] = create_ld(rn, rn); rom[(*data_pos)++] = val & 0xFFFFFFFF; rom[(*data_pos)++] = val >> 32; } static void create_io64_recovery(uint32_t *rom, uint32_t *code_pos, uint32_t *data_pos, uint64_t addr, uint64_t val) { uint32_t data_off = sizeof(uint32_t) * (*data_pos - *code_pos); rom[(*code_pos)++] = create_auipc(1, data_off); rom[(*code_pos)++] = create_addi(1, data_off); rom[(*code_pos)++] = create_ld(1, 1); rom[(*data_pos)++] = addr & 0xFFFFFFFF; rom[(*data_pos)++] = addr >> 32; uint32_t data_off2 = sizeof(uint32_t) * (*data_pos - *code_pos); rom[(*code_pos)++] = create_auipc(2, data_off2); rom[(*code_pos)++] = create_addi(2, data_off2); rom[(*code_pos)++] = create_ld(2, 2); rom[(*code_pos)++] = create_sd(1, 2); rom[(*data_pos)++] = val & 0xFFFFFFFF; rom[(*data_pos)++] = val >> 32; } static void create_hang_nonzero_hart(uint32_t *rom, uint32_t *code_pos, uint32_t *data_pos) { /* Note, this matches the boot loader prologue from copy_kernel() */ rom[(*code_pos)++] = 0xf1402573; // start: csrr a0, mhartid rom[(*code_pos)++] = 0x00050663; // beqz a0, 1f rom[(*code_pos)++] = 0x10500073; // 0: wfi rom[(*code_pos)++] = 0xffdff06f; // j 0b // 1: } static void create_boot_rom(RISCVCPUState *s, const char *file, const uint64_t clint_base_addr) { uint32_t rom[ROM_SIZE / 4]; memset(rom, 0, sizeof rom); // ROM organization // 0000..003F wasted // 0040..0AFF boot code (2,752 B) // 0B00..0FFF boot data ( 512 B) uint32_t code_pos = (BOOT_BASE_ADDR - ROM_BASE_ADDR) / sizeof *rom; uint32_t data_pos = 0xB00 / sizeof *rom; uint32_t data_pos_start = data_pos; if (s->machine->ncpus == 1) // FIXME: May be interesting to freeze hartid >= ncpus create_hang_nonzero_hart(rom, &code_pos, &data_pos); create_csr64_recovery(rom, &code_pos, &data_pos, 0x7b1, s->pc, s); // Write to DPC (CSR, 0x7b1) // Write current priviliege level to prv in dcsr (0 user, 1 supervisor, 2 user) // dcsr is at 0x7b0 prv is bits 0 & 1 // dcsr.stopcount = 1 // dcsr.stoptime = 1 // dcsr = 0x600 | (PrivLevel & 0x3) if (s->priv == 2) { fprintf(dromajo_stderr, "UNSUPORTED Priv mode (no hyper)\n"); exit(-4); } create_csr12_recovery(rom, &code_pos, 0x7b0, 0x600 | s->priv, s); #ifdef LIVECACHE int addr_size; uint64_t *addr = s->machine->llc->traverse(addr_size); if (addr_size > ROM_SIZE / 4) { fprintf(stderr, "LiveCache: truncating boot rom from %d to %d\n", addr_size, ROM_SIZE / 4); addr_size = ROM_SIZE/4; } for (int i = 0; i < addr_size; ++i) { uint64_t a = addr[i] & ~0x1ULL; printf("addr:%llx %s\n", (unsigned long long)a, (addr[i] & 1) ? "ST" : "LD"); create_read_warmup(rom, &code_pos, &data_pos, a); // treat write like reads for the moment } #endif // NOTE: mstatus & misa should be one of the first because risvemu breaks down this // register for performance reasons. E.g: restoring the fflags also changes // parts of the mstats create_csr64_recovery(rom, &code_pos, &data_pos, 0x300, get_mstatus(s, (target_ulong)-1), s); // mstatus create_csr64_recovery(rom, &code_pos, &data_pos, 0x301, s->misa | ((target_ulong)2 << 62), s); // misa // All the remaining CSRs if (s->fs) { // If the FPU is down, you can not recover flags create_csr12_recovery(rom, &code_pos, 0x001, s->fflags, s); // Only if fflags, otherwise it would raise an illegal instruction create_csr12_recovery(rom, &code_pos, 0x002, s->frm, s); create_csr12_recovery(rom, &code_pos, 0x003, s->fflags | (s->frm << 5), s); // do the FP registers, iff fs is set for (int i = 0; i < 32; i++) { uint32_t data_off = sizeof(uint32_t) * (data_pos - code_pos); rom[code_pos++] = create_auipc(1, data_off); rom[code_pos++] = create_addi(1, data_off); rom[code_pos++] = create_fld(i, 1); rom[data_pos++] = (uint32_t)s->fp_reg[i]; rom[data_pos++] = (uint64_t)s->reg[i] >> 32; } } // Recover CPU CSRs // Cycle and instruction are alias across modes. Just write to m-mode counter // Already done before CLINT. create_csr64_recovery(rom, &code_pos, &data_pos, 0xb00, s->insn_counter); // mcycle //create_csr64_recovery(rom, &code_pos, &data_pos, 0xb02, s->insn_counter); // instret for (int i = 3; i < 32 ; ++i) { create_csr12_recovery(rom, &code_pos, 0xb00 + i, 0, s); // reset mhpmcounter3..31 create_csr64_recovery(rom, &code_pos, &data_pos, 0x320 + i, s->mhpmevent[i], s); // mhpmevent3..31 } create_csr64_recovery(rom, &code_pos, &data_pos, 0x7a0, s->tselect, s); // tselect //FIXME: create_csr64_recovery(rom, &code_pos, &data_pos, 0x7a1, s->tdata1); // tdata1 //FIXME: create_csr64_recovery(rom, &code_pos, &data_pos, 0x7a2, s->tdata2); // tdata2 //FIXME: create_csr64_recovery(rom, &code_pos, &data_pos, 0x7a3, s->tdata3); // tdata3 create_csr64_recovery(rom, &code_pos, &data_pos, 0x302, s->medeleg, s); create_csr64_recovery(rom, &code_pos, &data_pos, 0x303, s->mideleg, s); create_csr64_recovery(rom, &code_pos, &data_pos, 0x304, s->mie, s); // mie & sie create_csr64_recovery(rom, &code_pos, &data_pos, 0x305, s->mtvec, s); create_csr64_recovery(rom, &code_pos, &data_pos, 0x105, s->stvec, s); create_csr12_recovery(rom, &code_pos, 0x320, s->mcountinhibit, s); create_csr12_recovery(rom, &code_pos, 0x306, s->mcounteren, s); create_csr12_recovery(rom, &code_pos, 0x106, s->scounteren, s); // NB: restore addr before cfgs for fewer surprises! for (int i = 0; i < 16; ++i) create_csr64_recovery(rom, &code_pos, &data_pos, CSR_PMPADDR(i), s->csr_pmpaddr[i], s); for (int i = 0; i < 4; i += 2) create_csr64_recovery(rom, &code_pos, &data_pos, CSR_PMPCFG(i), s->csr_pmpcfg[i], s); create_csr64_recovery(rom, &code_pos, &data_pos, 0x340, s->mscratch, s); create_csr64_recovery(rom, &code_pos, &data_pos, 0x341, s->mepc, s); create_csr64_recovery(rom, &code_pos, &data_pos, 0x342, s->mcause, s); create_csr64_recovery(rom, &code_pos, &data_pos, 0x343, s->mtval, s); create_csr64_recovery(rom, &code_pos, &data_pos, 0x140, s->sscratch, s); create_csr64_recovery(rom, &code_pos, &data_pos, 0x141, s->sepc, s); create_csr64_recovery(rom, &code_pos, &data_pos, 0x142, s->scause, s); create_csr64_recovery(rom, &code_pos, &data_pos, 0x143, s->stval, s); create_csr64_recovery(rom, &code_pos, &data_pos, 0x344, s->mip, s); // mip & sip for (int i = 3; i < 32; i++) { // Not 1 and 2 which are used by create_... create_reg_recovery(rom, &code_pos, &data_pos, i, s->reg[i]); } // Recover CLINT (Close to the end of the recovery to avoid extra cycles) // TODO: One per hart (multicore/SMP) fprintf(dromajo_stderr, "clint hartid=%d timecmp=%" PRId64 " cycles (%" PRId64 ")\n", (int)s->mhartid, s->timecmp, s->mcycle/RTC_FREQ_DIV); // Assuming 16 ratio between CPU and CLINT and that CPU is reset to zero create_io64_recovery( rom, &code_pos, &data_pos, clint_base_addr + 0x4000, s->timecmp); create_csr64_recovery(rom, &code_pos, &data_pos, 0xb02, s->minstret, s); create_csr64_recovery(rom, &code_pos, &data_pos, 0xb00, s->mcycle, s); create_io64_recovery( rom, &code_pos, &data_pos, clint_base_addr + 0xbff8, s->mcycle/RTC_FREQ_DIV); for (int i = 1; i < 3; i++) { // recover 1 and 2 now create_reg_recovery(rom, &code_pos, &data_pos, i, s->reg[i]); } rom[code_pos++] = create_csrrw(1, 0x7b2); create_csr64_recovery(rom, &code_pos, &data_pos, 0x180, s->satp, s); // last Thing because it changes addresses. Use dscratch register to remember reg 1 rom[code_pos++] = create_csrrs(1, 0x7b2); // dret 0x7b200073 rom[code_pos++] = 0x7b200073; if (sizeof rom / sizeof *rom <= data_pos || data_pos_start <= code_pos) { fprintf(dromajo_stderr, "ERROR: ROM is too small. ROM_SIZE should increase. " "Current code_pos=%d data_pos=%d\n", code_pos, data_pos); exit(-6); } serialize_memory(rom, ROM_SIZE, file); if (s->machine->common.save_format > 0) { char *f_name = (char *)alloca(strlen(file)+32); sprintf(f_name, "%s.hex", file); dump_hex_memory(rom, ROM_SIZE, f_name); } } void riscv_cpu_serialize(RISCVCPUState *s, const char *dump_name, const uint64_t clint_base_addr) { FILE *conf_fd = 0; size_t n = strlen(dump_name) + 64; char *conf_name = (char *)alloca(n); snprintf(conf_name, n, "%s.re_regs", dump_name); conf_fd = fopen(conf_name, "w"); if (conf_fd == 0) err(-3, "opening %s for serialization", conf_name); fprintf(conf_fd, "# DROMAJO serialization file\n"); fprintf(conf_fd, "pc:0x%llx\n", (long long)s->pc); for (int i = 1; i < 32; i++) { fprintf(conf_fd, "reg_x%d:%llx\n", i, (long long)s->reg[i]); } #if LEN > 0 for (int i = 0; i < 32; i++) { fprintf(conf_fd, "reg_f%d:%llx\n", i, (long long)s->fp_reg[i]); } fprintf(conf_fd, "fflags:%c\n", s->fflags); fprintf(conf_fd, "frm:%c\n", s->frm); #endif const char *priv_str = "USHM"; fprintf(conf_fd, "priv:%c\n", priv_str[s->priv]); fprintf(conf_fd, "insn_counter:%" PRIu64 "\n", s->insn_counter); fprintf(conf_fd, "pending_exception:%d\n", s->pending_exception); fprintf(conf_fd, "mstatus:%llx\n", (unsigned long long)s->mstatus); fprintf(conf_fd, "mtvec:%llx\n", (unsigned long long)s->mtvec); fprintf(conf_fd, "mscratch:%llx\n", (unsigned long long)s->mscratch); fprintf(conf_fd, "mepc:%llx\n", (unsigned long long)s->mepc); fprintf(conf_fd, "mcause:%llx\n", (unsigned long long)s->mcause); fprintf(conf_fd, "mtval:%llx\n", (unsigned long long)s->mtval); fprintf(conf_fd, "misa:%" PRIu32 "\n", s->misa); fprintf(conf_fd, "mie:%" PRIu32 "\n", s->mie); fprintf(conf_fd, "mip:%" PRIu32 "\n", s->mip); fprintf(conf_fd, "medeleg:%" PRIu32 "\n", s->medeleg); fprintf(conf_fd, "mideleg:%" PRIu32 "\n", s->mideleg); fprintf(conf_fd, "mcounteren:%" PRIu32 "\n", s->mcounteren); fprintf(conf_fd, "mcountinhibit:%" PRIu32 "\n", s->mcountinhibit); fprintf(conf_fd, "tselect:%" PRIu32 "\n", s->tselect); fprintf(conf_fd, "stvec:%llx\n", (unsigned long long)s->stvec); fprintf(conf_fd, "sscratch:%llx\n", (unsigned long long)s->sscratch); fprintf(conf_fd, "sepc:%llx\n", (unsigned long long)s->sepc); fprintf(conf_fd, "scause:%llx\n", (unsigned long long)s->scause); fprintf(conf_fd, "stval:%llx\n", (unsigned long long)s->stval); fprintf(conf_fd, "satp:%llx\n", (unsigned long long)s->satp); fprintf(conf_fd, "scounteren:%llx\n", (unsigned long long)s->scounteren); for (int i = 0; i < 4; i += 2) fprintf(conf_fd, "pmpcfg%d:%llx\n", i, (unsigned long long)s->csr_pmpcfg[i]); for (int i = 0; i < 16; ++i) fprintf(conf_fd, "pmpaddr%d:%llx\n", i, (unsigned long long)s->csr_pmpaddr[i]); PhysMemoryRange *boot_ram = 0; int main_ram_found = 0; for (int i = s->mem_map->n_phys_mem_range-1; i >= 0; --i) { PhysMemoryRange *pr = &s->mem_map->phys_mem_range[i]; fprintf(conf_fd, "mrange%d:0x%llx 0x%llx %s\n", i, (long long)pr->addr, (long long)pr->size, pr->is_ram ? "ram" : "io"); if (pr->is_ram && pr->addr == ROM_BASE_ADDR) { assert(!boot_ram); boot_ram = pr; } else if (pr->is_ram && pr->addr == s->machine->ram_base_addr) { assert(!main_ram_found); main_ram_found = 1; char *f_name = (char *)alloca(strlen(dump_name)+64); sprintf(f_name, "%s.mainram", dump_name); serialize_memory(pr->phys_mem, pr->size, f_name); if (s->machine->common.save_format > 0) { char *f_name_hex = (char *)alloca(strlen(dump_name)+96); sprintf(f_name_hex, "%s.mainram.hex", dump_name); dump_hex_memory(pr->phys_mem, pr->size, f_name_hex); } } } if (!boot_ram || !main_ram_found) { fprintf(dromajo_stderr, "ERROR: could not find boot and main ram???\n"); exit(-3); } n = strlen(dump_name) + 64; char *f_name = (char *)alloca(n); snprintf(f_name, n, "%s.bootram", dump_name); if (s->priv != 3 || ROM_BASE_ADDR + ROM_SIZE < s->pc) { fprintf(dromajo_stderr, "NOTE: creating a new boot rom\n"); create_boot_rom(s, f_name, clint_base_addr); } else if (BOOT_BASE_ADDR < s->pc) { fprintf(dromajo_stderr, "ERROR: could not checkpoint when running inside the ROM\n"); exit(-4); } else if (s->pc == BOOT_BASE_ADDR && boot_ram) { fprintf(dromajo_stderr, "NOTE: using the default dromajo ROM\n"); serialize_memory(boot_ram->phys_mem, boot_ram->size, f_name); } else { fprintf(dromajo_stderr, "ERROR: unexpected PC address 0x%llx\n", (long long)s->pc); exit(-4); } } void riscv_cpu_deserialize(RISCVCPUState *s, const char *dump_name) { for (int i = s->mem_map->n_phys_mem_range - 1; i >= 0; --i) { PhysMemoryRange *pr = &s->mem_map->phys_mem_range[i]; if (pr->is_ram && pr->addr == ROM_BASE_ADDR) { size_t n = strlen(dump_name) + 64; char *boot_name = (char *)alloca(n); snprintf(boot_name, n, "%s.bootram", dump_name); deserialize_memory(pr->phys_mem, pr->size, boot_name); } else if (pr->is_ram && pr->addr == s->machine->ram_base_addr) { size_t n = strlen(dump_name) + 64; char *main_name = (char *)alloca(n); snprintf(main_name, n, "%s.mainram", dump_name); deserialize_memory(pr->phys_mem, pr->size, main_name); } } }
/* * RISCV CPU emulator * * Copyright (c) 2016-2017 Fabrice Bellard * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #ifndef RISCV_CPU_H #define RISCV_CPU_H #include "riscv.h" #include <stdbool.h> #define ROM_SIZE 0x00001000 #define ROM_BASE_ADDR 0x00010000 #define BOOT_BASE_ADDR 0x00010000 // The default RAM base, can be relocated with config "memory_base_addr" #define RAM_BASE_ADDR 0x80000000 #define KERNEL_OFFSET 0x200000 #ifndef FLEN #define FLEN 64 #endif /* !FLEN */ #define DUMP_INVALID_MEM_ACCESS #define DUMP_MMU_EXCEPTIONS //#define DUMP_INTERRUPTS #define DUMP_INVALID_CSR //#define DUMP_ILLEGAL_INSTRUCTION //#define DUMP_EXCEPTIONS //#define DUMP_CSR #define CONFIG_LOGFILE #define CONFIG_SW_MANAGED_A_AND_D 1 #define CONFIG_ALLOW_MISALIGNED_ACCESS 0 #if FLEN > 0 #include "softfp.h" #endif #define __exception __attribute__((warn_unused_result)) typedef uint64_t target_ulong; typedef int64_t target_long; #define PR_target_ulong "016" PRIx64 /* FLEN is the floating point register width */ #if FLEN > 0 #if FLEN == 32 typedef uint32_t fp_uint; #define F32_HIGH 0 #elif FLEN == 64 typedef uint64_t fp_uint; #define F32_HIGH ((fp_uint)-1 << 32) #define F64_HIGH 0 #elif FLEN == 128 typedef uint128_t fp_uint; #define F32_HIGH ((fp_uint)-1 << 32) #define F64_HIGH ((fp_uint)-1 << 64) #else #error unsupported FLEN #endif #endif /* MLEN is the maximum memory access width */ #if 64 <= 32 && FLEN <= 32 #define MLEN 32 #elif 64 <= 64 && FLEN <= 64 #define MLEN 64 #else #define MLEN 128 #endif #if MLEN == 32 typedef uint32_t mem_uint_t; #elif MLEN == 64 typedef uint64_t mem_uint_t; #elif MLEN == 128 typedef uint128_t mem_uint_t; #else #unsupported MLEN #endif #define TLB_SIZE 256 #define PG_SHIFT 12 #define PG_MASK ((1 << PG_SHIFT) - 1) #define ASID_BITS 0 #define SATP_MASK ((15ULL << 60) | (((1ULL << ASID_BITS) - 1) << 44) | ((1ULL << 44) - 1)) #ifndef MAX_TRIGGERS #define MAX_TRIGGERS 1 // As of right now, one trigger register #endif /* HPM masks Follows Rocket here; the lower 8-bits are reserved in any HPM event selector to identify an "event-setid" i.e. with 8-bits we can define 256-possible event-sets. An event-set can contain 56 possible events, i.e. 64-8, where each bit represents the mask for a particular event in an event-set. Dromajo currently has 7 event-sets and not all 56-events are implemented for each set. */ #define HPM_EVENT_SETMASK 0x00000007 #define HPM_EVENT_EVENTMASK 0xffffff00 typedef struct { target_ulong vaddr; uintptr_t mem_addend; } TLBEntry; /* Control-flow summary information */ typedef enum { ctf_nop = 1, ctf_taken_jump, ctf_taken_branch, // Indirect jumps come in four variants depending on hits // NB: the order is important ctf_taken_jalr, ctf_taken_jalr_pop, ctf_taken_jalr_push, ctf_taken_jalr_pop_push, } RISCVCTFInfo; typedef struct RISCVCPUState { RISCVMachine *machine; target_ulong pc; target_ulong reg[32]; /* Co-simulation sometimes need to see the value of a register * prior to the just excuted instruction. */ target_ulong reg_prior[32]; int most_recently_written_reg; #if FLEN > 0 fp_uint fp_reg[32]; int most_recently_written_fp_reg; uint32_t fflags; uint8_t frm; #endif uint8_t priv; /* see PRV_x */ uint8_t fs; /* MSTATUS_FS value */ uint64_t insn_counter; // Simulator internal uint64_t minstret; // RISCV CSR (updated when insn_counter increases) uint64_t mcycle; // RISCV CSR (updated when insn_counter increases) BOOL debug_mode; BOOL stop_the_counter; // Set in debug mode only (cleared after ending Debug) BOOL power_down_flag; /* True when the core is idle awaiting * interrupts, does NOT mean terminate * simulation */ BOOL terminate_simulation; int pending_exception; /* used during MMU exception handling */ target_ulong pending_tval; /* CSRs */ target_ulong mstatus; target_ulong mtvec; target_ulong mscratch; target_ulong mepc; target_ulong mcause; target_ulong mtval; target_ulong mvendorid; /* ro */ target_ulong marchid; /* ro */ target_ulong mimpid; /* ro */ target_ulong mhartid; /* ro */ uint32_t misa; uint32_t mie; uint32_t mip; uint32_t medeleg; uint32_t mideleg; uint32_t mcounteren; uint32_t mcountinhibit; uint32_t tselect; target_ulong tdata1[MAX_TRIGGERS]; target_ulong tdata2[MAX_TRIGGERS]; target_ulong tdata3[MAX_TRIGGERS]; target_ulong mhpmevent[32]; uint64_t csr_pmpcfg[4]; // But only 0 and 2 are valid uint64_t csr_pmpaddr[16]; // pmpcfg and pmpadddr unpacked int pmp_n; // 0..pmp_n-1 entries are valid struct pmp_addr { uint64_t lo, hi; // [lo; hi) NB: not inclusive } pmp[16]; uint8_t pmpcfg[16]; target_ulong stvec; target_ulong sscratch; target_ulong sepc; target_ulong scause; target_ulong stval; uint64_t satp; /* currently 64 bit physical addresses max */ uint32_t scounteren; target_ulong dcsr; // Debug CSR 0x7b0 (debug spec only) target_ulong dpc; // Debug DPC 0x7b1 (debug spec only) target_ulong dscratch; // Debug dscratch 0x7b2 (debug spec only) uint32_t plic_enable_irq; target_ulong load_res; /* for atomic LR/SC */ PhysMemoryMap *mem_map; int physical_addr_len; TLBEntry tlb_read[TLB_SIZE]; TLBEntry tlb_write[TLB_SIZE]; TLBEntry tlb_code[TLB_SIZE]; #ifndef PADDR_INLINE target_ulong tlb_read_paddr_addend[TLB_SIZE]; target_ulong tlb_write_paddr_addend[TLB_SIZE]; target_ulong tlb_code_paddr_addend[TLB_SIZE]; #endif // Benchmark return value uint64_t benchmark_exit_code; /* Control Flow Info */ RISCVCTFInfo info; target_ulong next_addr; /* the CFI target address-- only valid for CFIs. */ /* RTC */ uint64_t timecmp; bool ignore_sbi_shutdown; /* Extension state, not used by Dromajo itself */ void *ext_cpu_state; } RISCVCPUState; RISCVCPUState *riscv_cpu_init(RISCVMachine *machine, int hartid); void riscv_cpu_end(RISCVCPUState *s); int riscv_cpu_interp(RISCVCPUState *s, int n_cycles); uint64_t riscv_cpu_get_cycles(RISCVCPUState *s); void riscv_cpu_set_mip(RISCVCPUState *s, uint32_t mask); void riscv_cpu_reset_mip(RISCVCPUState *s, uint32_t mask); uint32_t riscv_cpu_get_mip(RISCVCPUState *s); BOOL riscv_cpu_get_power_down(RISCVCPUState *s); uint32_t riscv_cpu_get_misa(RISCVCPUState *s); void riscv_cpu_flush_tlb_write_range_ram(RISCVCPUState *s, uint8_t *ram_ptr, size_t ram_size); void riscv_set_pc(RISCVCPUState *s, uint64_t pc); uint64_t riscv_get_pc(RISCVCPUState *s); uint64_t riscv_get_reg(RISCVCPUState *s, int rn); uint64_t riscv_get_reg_previous(RISCVCPUState *s, int rn); uint64_t riscv_get_fpreg(RISCVCPUState *s, int rn); void riscv_set_reg(RISCVCPUState *s, int rn, uint64_t val); void riscv_dump_regs(RISCVCPUState *s); int riscv_read_insn(RISCVCPUState *s, uint32_t *insn, uint64_t addr); void riscv_repair_csr(RISCVCPUState *s, uint32_t reg_num, uint64_t csr_num, uint64_t csr_val); void riscv_cpu_sync_regs(RISCVCPUState *s); int riscv_get_priv_level(RISCVCPUState *s); int riscv_get_most_recently_written_reg(RISCVCPUState *s); int riscv_get_most_recently_written_fp_reg(RISCVCPUState *s); void riscv_get_ctf_info(RISCVCPUState *s, RISCVCTFInfo *info); void riscv_get_ctf_target(RISCVCPUState *s, uint64_t *target); int riscv_cpu_interp64(RISCVCPUState *s, int n_cycles); BOOL riscv_terminated(RISCVCPUState *s); void riscv_set_debug_mode(RISCVCPUState *s, bool on); int riscv_benchmark_exit_code(RISCVCPUState *s); #include "riscv_machine.h" void riscv_cpu_serialize(RISCVCPUState *s, const char *dump_name, const uint64_t clint_base_addr); void riscv_cpu_deserialize(RISCVCPUState *s, const char *dump_name); int riscv_cpu_read_memory(RISCVCPUState *s, mem_uint_t *pval, target_ulong addr, int size_log2); int riscv_cpu_write_memory(RISCVCPUState *s, target_ulong addr, mem_uint_t val, int size_log2); #define PHYS_MEM_READ_WRITE(size, uint_type) \ void riscv_phys_write_u ## size(RISCVCPUState *, target_ulong, uint_type, bool *); \ uint_type riscv_phys_read_u ## size(RISCVCPUState *, target_ulong, bool *); PHYS_MEM_READ_WRITE(8, uint8_t) PHYS_MEM_READ_WRITE(32, uint32_t) PHYS_MEM_READ_WRITE(64, uint64_t) #undef PHYS_MEM_READ_WRITE typedef enum { ACCESS_READ, ACCESS_WRITE, ACCESS_CODE, } riscv_memory_access_t; int riscv_cpu_get_phys_addr(RISCVCPUState *s, target_ulong vaddr, riscv_memory_access_t access, target_ulong *ppaddr); uint64_t riscv_cpu_get_mstatus(RISCVCPUState* s); bool riscv_cpu_pmp_access_ok(RISCVCPUState *s, uint64_t paddr, size_t size, pmpcfg_t perm); #endif
/* * RISCV machine * * Copyright (c) 2016 Fabrice Bellard * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #ifndef RISCV_MACHINE_H #define RISCV_MACHINE_H #include "virtio.h" #include "machine.h" #include "riscv_cpu.h" #ifdef LIVECACHE #include "LiveCacheCore.h" #endif #define MAX_CPUS 8 /* Hooks */ typedef struct RISCVMachineHooks { /* Returns -1 if invalid CSR, 0 if OK. */ int (*csr_read) (RISCVCPUState *s, uint32_t csr, uint64_t *pval); int (*csr_write)(RISCVCPUState *s, uint32_t csr, uint64_t val); } RISCVMachineHooks; struct RISCVMachine { VirtMachine common; RISCVMachineHooks hooks; PhysMemoryMap *mem_map; #ifdef LIVECACHE LiveCache *llc; #endif RISCVCPUState *cpu_state[MAX_CPUS]; int ncpus; uint64_t ram_size; uint64_t ram_base_addr; /* PLIC */ uint32_t plic_pending_irq; uint32_t plic_served_irq; IRQSignal plic_irq[32]; /* IRQ 0 is not used */ /* HTIF */ uint64_t htif_tohost_addr; VIRTIODevice *keyboard_dev; VIRTIODevice *mouse_dev; int virtio_count; /* MMIO range (for co-simulation only) */ uint64_t mmio_start; uint64_t mmio_end; AddressSet *mmio_addrset; uint64_t mmio_addrset_size; /* Reset vector */ uint64_t reset_vector; /* Bootrom Params */ bool compact_bootrom; /* PLIC/CLINT Params */ uint64_t plic_base_addr; uint64_t plic_size; uint64_t clint_base_addr; uint64_t clint_size; /* Append to misa custom extensions */ bool custom_extension; /* Extension state, not used by Dromajo itself */ void *ext_state; /* Core specific configs */ uint64_t* missing_csrs; uint64_t missing_csrs_size; uint64_t* skip_commit; uint64_t skip_commit_size; }; #define PLIC_BASE_ADDR 0x10000000 #define PLIC_SIZE 0x2000000 #define CLINT_BASE_ADDR 0x02000000 #define CLINT_SIZE 0x000c0000 #define RTC_FREQ_DIV 16 /* arbitrary, relative to CPU freq to have a 10 MHz frequency */ #define HTIF_BASE_ADDR 0x40008000 #define IDE_BASE_ADDR 0x40009000 #define VIRTIO_BASE_ADDR 0x40010000 #define VIRTIO_SIZE 0x1000 #define VIRTIO_IRQ 1 #define FRAMEBUFFER_BASE_ADDR 0x41000000 // sifive,uart, same as qemu UART0 (qemu has 2 sifive uarts) #define UART0_BASE_ADDR 0x54000000 #define UART0_SIZE 32 #define UART0_IRQ 3 #define RTC_FREQ 10000000 #endif
/* * SoftFP Library * * Copyright (c) 2016 Fabrice Bellard * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #include <stdlib.h> #include <stdio.h> #include <assert.h> #include <string.h> #include "cutils.h" #include "softfp.h" static inline int clz32(uint32_t a) { int r; if (a == 0) { r = 32; } else { r = __builtin_clz(a); } return r; } static inline int clz64(uint64_t a) { int r; if (a == 0) { r = 64; } else { r = __builtin_clzll(a); } return r; } #ifdef HAVE_INT128 static inline int clz128(uint128_t a) { int r; if (a == 0) { r = 128; } else { uint64_t ah, al; ah = a >> 64; al = a; if (ah != 0) r = __builtin_clzll(ah); else r = __builtin_clzll(al) + 64; } return r; } #endif #include "softfp.h" #define F_SIZE 32 #include "softfp_template.h" #define F_SIZE 64 #include "softfp_template.h" #ifdef HAVE_INT128 #define F_SIZE 128 #include "softfp_template.h" #endif
/* * SoftFP Library * * Copyright (c) 2016 Fabrice Bellard * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #ifndef SOFTFP_H #define SOFTFP_H #include <inttypes.h> #include "cutils.h" typedef enum { RM_RNE, /* Round to Nearest, ties to Even */ RM_RTZ, /* Round towards Zero */ RM_RDN, /* Round Down */ RM_RUP, /* Round Up */ RM_RMM, /* Round to Nearest, ties to Max Magnitude */ } RoundingModeEnum; #define FFLAG_INVALID_OP (1 << 4) #define FFLAG_DIVIDE_ZERO (1 << 3) #define FFLAG_OVERFLOW (1 << 2) #define FFLAG_UNDERFLOW (1 << 1) #define FFLAG_INEXACT (1 << 0) #define FCLASS_NINF (1 << 0) #define FCLASS_NNORMAL (1 << 1) #define FCLASS_NSUBNORMAL (1 << 2) #define FCLASS_NZERO (1 << 3) #define FCLASS_PZERO (1 << 4) #define FCLASS_PSUBNORMAL (1 << 5) #define FCLASS_PNORMAL (1 << 6) #define FCLASS_PINF (1 << 7) #define FCLASS_SNAN (1 << 8) #define FCLASS_QNAN (1 << 9) typedef uint32_t sfloat32; typedef uint64_t sfloat64; #ifdef HAVE_INT128 typedef uint128_t sfloat128; #endif /* 32 bit floats */ #define FSIGN_MASK32 (1 << 31) sfloat32 add_sf32(sfloat32 a, sfloat32 b, RoundingModeEnum rm, uint32_t *pfflags); sfloat32 sub_sf32(sfloat32 a, sfloat32 b, RoundingModeEnum rm, uint32_t *pfflags); sfloat32 mul_sf32(sfloat32 a, sfloat32 b, RoundingModeEnum rm, uint32_t *pfflags); sfloat32 div_sf32(sfloat32 a, sfloat32 b, RoundingModeEnum rm, uint32_t *pfflags); sfloat32 sqrt_sf32(sfloat32 a, RoundingModeEnum rm, uint32_t *pfflags); sfloat32 fma_sf32(sfloat32 a, sfloat32 b, sfloat32 c, RoundingModeEnum rm, uint32_t *pfflags); sfloat32 min_sf32(sfloat32 a, sfloat32 b, uint32_t *pfflags); sfloat32 max_sf32(sfloat32 a, sfloat32 b, uint32_t *pfflags); int eq_quiet_sf32(sfloat32 a, sfloat32 b, uint32_t *pfflags); int le_sf32(sfloat32 a, sfloat32 b, uint32_t *pfflags); int lt_sf32(sfloat32 a, sfloat32 b, uint32_t *pfflags); uint32_t fclass_sf32(sfloat32 a); sfloat64 cvt_sf32_sf64(sfloat32 a, uint32_t *pfflags); sfloat32 cvt_sf64_sf32(sfloat64 a, RoundingModeEnum rm, uint32_t *pfflags); int32_t cvt_sf32_i32(sfloat32 a, RoundingModeEnum rm, uint32_t *pfflags); uint32_t cvt_sf32_u32(sfloat32 a, RoundingModeEnum rm, uint32_t *pfflags); int64_t cvt_sf32_i64(sfloat32 a, RoundingModeEnum rm, uint32_t *pfflags); uint64_t cvt_sf32_u64(sfloat32 a, RoundingModeEnum rm, uint32_t *pfflags); #ifdef HAVE_INT128 int128_t cvt_sf32_i128(sfloat32 a, RoundingModeEnum rm, uint32_t *pfflags); uint128_t cvt_sf32_u128(sfloat32 a, RoundingModeEnum rm, uint32_t *pfflags); #endif sfloat32 cvt_i32_sf32(int32_t a, RoundingModeEnum rm, uint32_t *pfflags); sfloat32 cvt_u32_sf32(uint32_t a, RoundingModeEnum rm, uint32_t *pfflags); sfloat32 cvt_i64_sf32(int64_t a, RoundingModeEnum rm, uint32_t *pfflags); sfloat32 cvt_u64_sf32(uint64_t a, RoundingModeEnum rm, uint32_t *pfflags); #ifdef HAVE_INT128 sfloat32 cvt_i128_sf32(int128_t a, RoundingModeEnum rm, uint32_t *pfflags); sfloat32 cvt_u128_sf32(uint128_t a, RoundingModeEnum rm, uint32_t *pfflags); #endif /* 64 bit floats */ #define FSIGN_MASK64 ((uint64_t)1 << 63) sfloat64 add_sf64(sfloat64 a, sfloat64 b, RoundingModeEnum rm, uint32_t *pfflags); sfloat64 sub_sf64(sfloat64 a, sfloat64 b, RoundingModeEnum rm, uint32_t *pfflags); sfloat64 mul_sf64(sfloat64 a, sfloat64 b, RoundingModeEnum rm, uint32_t *pfflags); sfloat64 div_sf64(sfloat64 a, sfloat64 b, RoundingModeEnum rm, uint32_t *pfflags); sfloat64 sqrt_sf64(sfloat64 a, RoundingModeEnum rm, uint32_t *pfflags); sfloat64 fma_sf64(sfloat64 a, sfloat64 b, sfloat64 c, RoundingModeEnum rm, uint32_t *pfflags); sfloat64 min_sf64(sfloat64 a, sfloat64 b, uint32_t *pfflags); sfloat64 max_sf64(sfloat64 a, sfloat64 b, uint32_t *pfflags); int eq_quiet_sf64(sfloat64 a, sfloat64 b, uint32_t *pfflags); int le_sf64(sfloat64 a, sfloat64 b, uint32_t *pfflags); int lt_sf64(sfloat64 a, sfloat64 b, uint32_t *pfflags); uint32_t fclass_sf64(sfloat64 a); sfloat64 cvt_sf32_sf64(sfloat32 a, uint32_t *pfflags); sfloat32 cvt_sf64_sf32(sfloat64 a, RoundingModeEnum rm, uint32_t *pfflags); int32_t cvt_sf64_i32(sfloat64 a, RoundingModeEnum rm, uint32_t *pfflags); uint32_t cvt_sf64_u32(sfloat64 a, RoundingModeEnum rm, uint32_t *pfflags); int64_t cvt_sf64_i64(sfloat64 a, RoundingModeEnum rm, uint32_t *pfflags); uint64_t cvt_sf64_u64(sfloat64 a, RoundingModeEnum rm, uint32_t *pfflags); #ifdef HAVE_INT128 int128_t cvt_sf64_i128(sfloat64 a, RoundingModeEnum rm, uint32_t *pfflags); uint128_t cvt_sf64_u128(sfloat64 a, RoundingModeEnum rm, uint32_t *pfflags); #endif sfloat64 cvt_i32_sf64(int32_t a, RoundingModeEnum rm, uint32_t *pfflags); sfloat64 cvt_u32_sf64(uint32_t a, RoundingModeEnum rm, uint32_t *pfflags); sfloat64 cvt_i64_sf64(int64_t a, RoundingModeEnum rm, uint32_t *pfflags); sfloat64 cvt_u64_sf64(uint64_t a, RoundingModeEnum rm, uint32_t *pfflags); #ifdef HAVE_INT128 sfloat64 cvt_i128_sf64(int128_t a, RoundingModeEnum rm, uint32_t *pfflags); sfloat64 cvt_u128_sf64(uint128_t a, RoundingModeEnum rm, uint32_t *pfflags); #endif /* 128 bit floats */ #ifdef HAVE_INT128 #define FSIGN_MASK128 ((uint128_t)1 << 127) sfloat128 add_sf128(sfloat128 a, sfloat128 b, RoundingModeEnum rm, uint32_t *pfflags); sfloat128 sub_sf128(sfloat128 a, sfloat128 b, RoundingModeEnum rm, uint32_t *pfflags); sfloat128 mul_sf128(sfloat128 a, sfloat128 b, RoundingModeEnum rm, uint32_t *pfflags); sfloat128 div_sf128(sfloat128 a, sfloat128 b, RoundingModeEnum rm, uint32_t *pfflags); sfloat128 sqrt_sf128(sfloat128 a, RoundingModeEnum rm, uint32_t *pfflags); sfloat128 fma_sf128(sfloat128 a, sfloat128 b, sfloat128 c, RoundingModeEnum rm, uint32_t *pfflags); sfloat128 min_sf128(sfloat128 a, sfloat128 b, uint32_t *pfflags); sfloat128 max_sf128(sfloat128 a, sfloat128 b, uint32_t *pfflags); int eq_quiet_sf128(sfloat128 a, sfloat128 b, uint32_t *pfflags); int le_sf128(sfloat128 a, sfloat128 b, uint32_t *pfflags); int lt_sf128(sfloat128 a, sfloat128 b, uint32_t *pfflags); uint32_t fclass_sf128(sfloat128 a); sfloat128 cvt_sf32_sf128(sfloat32 a, uint32_t *pfflags); sfloat32 cvt_sf128_sf32(sfloat128 a, RoundingModeEnum rm, uint32_t *pfflags); sfloat128 cvt_sf64_sf128(sfloat64 a, uint32_t *pfflags); sfloat64 cvt_sf128_sf64(sfloat128 a, RoundingModeEnum rm, uint32_t *pfflags); int32_t cvt_sf128_i32(sfloat128 a, RoundingModeEnum rm, uint32_t *pfflags); uint32_t cvt_sf128_u32(sfloat128 a, RoundingModeEnum rm, uint32_t *pfflags); int64_t cvt_sf128_i64(sfloat128 a, RoundingModeEnum rm, uint32_t *pfflags); uint64_t cvt_sf128_u64(sfloat128 a, RoundingModeEnum rm, uint32_t *pfflags); int128_t cvt_sf128_i128(sfloat128 a, RoundingModeEnum rm, uint32_t *pfflags); uint128_t cvt_sf128_u128(sfloat128 a, RoundingModeEnum rm, uint32_t *pfflags); sfloat128 cvt_i32_sf128(int32_t a, RoundingModeEnum rm, uint32_t *pfflags); sfloat128 cvt_u32_sf128(uint32_t a, RoundingModeEnum rm, uint32_t *pfflags); sfloat128 cvt_i64_sf128(int64_t a, RoundingModeEnum rm, uint32_t *pfflags); sfloat128 cvt_u64_sf128(uint64_t a, RoundingModeEnum rm, uint32_t *pfflags); sfloat128 cvt_i128_sf128(int128_t a, RoundingModeEnum rm, uint32_t *pfflags); sfloat128 cvt_u128_sf128(uint128_t a, RoundingModeEnum rm, uint32_t *pfflags); #endif #endif /* SOFTFP_H */
/* * SoftFP Library * * Copyright (c) 2016 Fabrice Bellard * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #if ICVT_SIZE == 32 #define ICVT_UINT uint32_t #define ICVT_INT int32_t #elif ICVT_SIZE == 64 #define ICVT_UINT uint64_t #define ICVT_INT int64_t #elif ICVT_SIZE == 128 #define ICVT_UINT uint128_t #define ICVT_INT int128_t #else #error unsupported icvt #endif /* conversions between float and integers */ static ICVT_INT glue(glue(glue(internal_cvt_sf, F_SIZE), _i), ICVT_SIZE)(F_UINT a, RoundingModeEnum rm, uint32_t *pfflags, BOOL is_unsigned) { uint32_t a_sign, addend, rnd_bits; int32_t a_exp; F_UINT a_mant; ICVT_UINT r, r_max; a_sign = a >> (F_SIZE - 1); a_exp = (a >> MANT_SIZE) & EXP_MASK; a_mant = a & MANT_MASK; if (a_exp == EXP_MASK && a_mant != 0) a_sign = 0; /* NaN is like +infinity */ if (a_exp == 0) { a_exp = 1; } else { a_mant |= (F_UINT)1 << MANT_SIZE; } a_mant <<= RND_SIZE; a_exp = a_exp - (EXP_MASK / 2) - MANT_SIZE; if (is_unsigned) r_max = (ICVT_UINT)a_sign - 1; else r_max = ((ICVT_UINT)1 << (ICVT_SIZE - 1)) - (ICVT_UINT)(a_sign ^ 1); if (a_exp >= 0) { if (a_exp <= (ICVT_SIZE - 1 - MANT_SIZE)) { r = (ICVT_UINT)(a_mant >> RND_SIZE) << a_exp; if (r > r_max) goto overflow; } else { overflow: *pfflags |= FFLAG_INVALID_OP; return r_max; } } else { a_mant = rshift_rnd(a_mant, -a_exp); switch (rm) { case RM_RNE: case RM_RMM: addend = (1 << (RND_SIZE - 1)); break; case RM_RTZ: addend = 0; break; default: case RM_RDN: case RM_RUP: if (a_sign ^ (rm & 1)) addend = (1 << RND_SIZE) - 1; else addend = 0; break; } rnd_bits = a_mant & ((1 << RND_SIZE ) - 1); a_mant = (a_mant + addend) >> RND_SIZE; /* half way: select even result */ if (rm == RM_RNE && rnd_bits == (1 << (RND_SIZE - 1))) a_mant &= ~1; if (a_mant > r_max) goto overflow; r = a_mant; if (rnd_bits != 0) *pfflags |= FFLAG_INEXACT; } if (a_sign) r = -r; return r; } ICVT_INT glue(glue(glue(cvt_sf, F_SIZE), _i), ICVT_SIZE)(F_UINT a, RoundingModeEnum rm, uint32_t *pfflags) { return glue(glue(glue(internal_cvt_sf, F_SIZE), _i), ICVT_SIZE)(a, rm, pfflags, FALSE); } ICVT_UINT glue(glue(glue(cvt_sf, F_SIZE), _u), ICVT_SIZE)(F_UINT a, RoundingModeEnum rm, uint32_t *pfflags) { return glue(glue(glue(internal_cvt_sf, F_SIZE), _i), ICVT_SIZE) (a, rm, pfflags, TRUE); } /* conversions between float and integers */ static F_UINT glue(glue(glue(internal_cvt_i, ICVT_SIZE), _sf), F_SIZE)(ICVT_INT a, RoundingModeEnum rm, uint32_t *pfflags, BOOL is_unsigned) { uint32_t a_sign; int32_t a_exp; F_UINT a_mant; ICVT_UINT r, mask; int l; if (!is_unsigned && a < 0) { a_sign = 1; r = -a; } else { a_sign = 0; r = a; } a_exp = (EXP_MASK / 2) + F_SIZE - 2; /* need to reduce range before generic float normalization */ l = ICVT_SIZE - glue(clz, ICVT_SIZE)(r) - (F_SIZE - 1); if (l > 0) { mask = r & (((ICVT_UINT)1 << l) - 1); r = (r >> l) | ((r & mask) != 0); a_exp += l; } a_mant = r; return normalize_sf(a_sign, a_exp, a_mant, rm, pfflags); } F_UINT glue(glue(glue(cvt_i, ICVT_SIZE), _sf), F_SIZE)(ICVT_INT a, RoundingModeEnum rm, uint32_t *pfflags) { return glue(glue(glue(internal_cvt_i, ICVT_SIZE), _sf), F_SIZE)(a, rm, pfflags, FALSE); } F_UINT glue(glue(glue(cvt_u, ICVT_SIZE), _sf), F_SIZE)(ICVT_UINT a, RoundingModeEnum rm, uint32_t *pfflags) { return glue(glue(glue(internal_cvt_i, ICVT_SIZE), _sf), F_SIZE)(a, rm, pfflags, TRUE); } #undef ICVT_SIZE #undef ICVT_INT #undef ICVT_UINT
/* * VIRTIO driver * * Copyright (c) 2016 Fabrice Bellard * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #include <stdlib.h> #include <stdio.h> #include <string.h> #include <inttypes.h> #include <assert.h> #include <stdarg.h> #include "cutils.h" #include "list.h" #include "virtio.h" #define DEBUG_VIRTIO /* MMIO addresses - from the Linux kernel */ #define VIRTIO_MMIO_MAGIC_VALUE 0x000 #define VIRTIO_MMIO_VERSION 0x004 #define VIRTIO_MMIO_DEVICE_ID 0x008 #define VIRTIO_MMIO_VENDOR_ID 0x00c #define VIRTIO_MMIO_DEVICE_FEATURES 0x010 #define VIRTIO_MMIO_DEVICE_FEATURES_SEL 0x014 #define VIRTIO_MMIO_DRIVER_FEATURES 0x020 #define VIRTIO_MMIO_DRIVER_FEATURES_SEL 0x024 #define VIRTIO_MMIO_GUEST_PAGE_SIZE 0x028 /* version 1 only */ #define VIRTIO_MMIO_QUEUE_SEL 0x030 #define VIRTIO_MMIO_QUEUE_NUM_MAX 0x034 #define VIRTIO_MMIO_QUEUE_NUM 0x038 #define VIRTIO_MMIO_QUEUE_ALIGN 0x03c /* version 1 only */ #define VIRTIO_MMIO_QUEUE_PFN 0x040 /* version 1 only */ #define VIRTIO_MMIO_QUEUE_READY 0x044 #define VIRTIO_MMIO_QUEUE_NOTIFY 0x050 #define VIRTIO_MMIO_INTERRUPT_STATUS 0x060 #define VIRTIO_MMIO_INTERRUPT_ACK 0x064 #define VIRTIO_MMIO_STATUS 0x070 #define VIRTIO_MMIO_QUEUE_DESC_LOW 0x080 #define VIRTIO_MMIO_QUEUE_DESC_HIGH 0x084 #define VIRTIO_MMIO_QUEUE_AVAIL_LOW 0x090 #define VIRTIO_MMIO_QUEUE_AVAIL_HIGH 0x094 #define VIRTIO_MMIO_QUEUE_USED_LOW 0x0a0 #define VIRTIO_MMIO_QUEUE_USED_HIGH 0x0a4 #define VIRTIO_MMIO_CONFIG_GENERATION 0x0fc #define VIRTIO_MMIO_CONFIG 0x100 /* PCI registers */ #define VIRTIO_PCI_DEVICE_FEATURE_SEL 0x000 #define VIRTIO_PCI_DEVICE_FEATURE 0x004 #define VIRTIO_PCI_GUEST_FEATURE_SEL 0x008 #define VIRTIO_PCI_GUEST_FEATURE 0x00c #define VIRTIO_PCI_MSIX_CONFIG 0x010 #define VIRTIO_PCI_NUM_QUEUES 0x012 #define VIRTIO_PCI_DEVICE_STATUS 0x014 #define VIRTIO_PCI_CONFIG_GENERATION 0x015 #define VIRTIO_PCI_QUEUE_SEL 0x016 #define VIRTIO_PCI_QUEUE_SIZE 0x018 #define VIRTIO_PCI_QUEUE_MSIX_VECTOR 0x01a #define VIRTIO_PCI_QUEUE_ENABLE 0x01c #define VIRTIO_PCI_QUEUE_NOTIFY_OFF 0x01e #define VIRTIO_PCI_QUEUE_DESC_LOW 0x020 #define VIRTIO_PCI_QUEUE_DESC_HIGH 0x024 #define VIRTIO_PCI_QUEUE_AVAIL_LOW 0x028 #define VIRTIO_PCI_QUEUE_AVAIL_HIGH 0x02c #define VIRTIO_PCI_QUEUE_USED_LOW 0x030 #define VIRTIO_PCI_QUEUE_USED_HIGH 0x034 #define VIRTIO_PCI_CFG_OFFSET 0x0000 #define VIRTIO_PCI_ISR_OFFSET 0x1000 #define VIRTIO_PCI_CONFIG_OFFSET 0x2000 #define VIRTIO_PCI_NOTIFY_OFFSET 0x3000 #define VIRTIO_PCI_CAP_LEN 16 #define MAX_QUEUE 8 #define MAX_CONFIG_SPACE_SIZE 256 #define MAX_QUEUE_NUM 16 typedef struct { uint32_t ready; /* 0 or 1 */ uint32_t num; uint16_t last_avail_idx; virtio_phys_addr_t desc_addr; virtio_phys_addr_t avail_addr; virtio_phys_addr_t used_addr; BOOL manual_recv; /* if TRUE, the device_recv() callback is not called */ } QueueState; #define VRING_DESC_F_NEXT 1 #define VRING_DESC_F_WRITE 2 #define VRING_DESC_F_INDIRECT 4 typedef struct { uint64_t addr; uint32_t len; uint16_t flags; /* VRING_DESC_F_x */ uint16_t next; } VIRTIODesc; /* return < 0 to stop the notification (it must be manually restarted later), 0 if OK */ typedef int VIRTIODeviceRecvFunc(VIRTIODevice *s1, int queue_idx, int desc_idx, int read_size, int write_size); /* return NULL if no RAM at this address. The mapping is valid for one page */ typedef uint8_t *VIRTIOGetRAMPtrFunc(VIRTIODevice *s, virtio_phys_addr_t paddr); struct VIRTIODevice { PhysMemoryMap *mem_map; PhysMemoryRange *mem_range; /* PCI only */ PCIDevice *pci_dev; /* MMIO only */ IRQSignal *irq; VIRTIOGetRAMPtrFunc *get_ram_ptr; int debug; uint32_t int_status; uint32_t status; uint32_t device_features_sel; uint32_t queue_sel; /* currently selected queue */ QueueState queue[MAX_QUEUE]; /* device specific */ uint32_t device_id; uint32_t vendor_id; uint32_t device_features; VIRTIODeviceRecvFunc *device_recv; void (*config_write)(VIRTIODevice *s); /* called after the config is written */ uint32_t config_space_size; /* in bytes, must be multiple of 4 */ uint8_t config_space[MAX_CONFIG_SPACE_SIZE]; }; static uint32_t virtio_mmio_read(void *opaque, uint32_t offset1, int size_log2); static void virtio_mmio_write(void *opaque, uint32_t offset, uint32_t val, int size_log2); static uint32_t virtio_pci_read(void *opaque, uint32_t offset, int size_log2); static void virtio_pci_write(void *opaque, uint32_t offset, uint32_t val, int size_log2); static void virtio_reset(VIRTIODevice *s) { int i; s->status = 0; s->queue_sel = 0; s->device_features_sel = 0; s->int_status = 0; for (i = 0; i < MAX_QUEUE; i++) { QueueState *qs = &s->queue[i]; qs->ready = 0; qs->num = MAX_QUEUE_NUM; qs->desc_addr = 0; qs->avail_addr = 0; qs->used_addr = 0; qs->last_avail_idx = 0; } } static uint8_t *virtio_pci_get_ram_ptr(VIRTIODevice *s, virtio_phys_addr_t paddr) { return pci_device_get_dma_ptr(s->pci_dev, paddr); } static uint8_t *virtio_mmio_get_ram_ptr(VIRTIODevice *s, virtio_phys_addr_t paddr) { PhysMemoryRange *pr; pr = get_phys_mem_range(s->mem_map, paddr); if (!pr || !pr->is_ram) return NULL; return pr->phys_mem + (uintptr_t)(paddr - pr->addr); } static void virtio_add_pci_capability(VIRTIODevice *s, int cfg_type, int bar, uint32_t offset, uint32_t len, uint32_t mult) { uint8_t cap[20]; int cap_len; if (cfg_type == 2) cap_len = 20; else cap_len = 16; memset(cap, 0, cap_len); cap[0] = 0x09; /* vendor specific */ cap[2] = cap_len; /* set by pci_add_capability() */ cap[3] = cfg_type; cap[4] = bar; put_le32(cap + 8, offset); put_le32(cap + 12, len); if (cfg_type == 2) put_le32(cap + 16, mult); pci_add_capability(s->pci_dev, cap, cap_len); } static void virtio_pci_bar_set(void *opaque, int bar_num, uint32_t addr, BOOL enabled) { VIRTIODevice *s = (VIRTIODevice *)opaque; phys_mem_set_addr(s->mem_range, addr, enabled); } static void virtio_init(VIRTIODevice *s, VIRTIOBusDef *bus, uint32_t device_id, int config_space_size, VIRTIODeviceRecvFunc *device_recv) { memset(s, 0, sizeof(*s)); if (bus->pci_bus) { uint16_t pci_device_id, class_id; char name[32]; int bar_num; switch (device_id) { case 1: pci_device_id = 0x1000; /* net */ class_id = 0x0200; break; case 2: pci_device_id = 0x1001; /* block */ class_id = 0x0100; /* XXX: check it */ break; case 3: pci_device_id = 0x1003; /* console */ class_id = 0x0780; break; case 9: pci_device_id = 0x1040 + device_id; /* use new device ID */ class_id = 0x2; break; case 18: pci_device_id = 0x1040 + device_id; /* use new device ID */ class_id = 0x0980; break; default: abort(); } snprintf(name, sizeof(name), "virtio_%04x", pci_device_id); s->pci_dev = pci_register_device(bus->pci_bus, name, -1, 0x1af4, pci_device_id, 0x00, class_id); pci_device_set_config16(s->pci_dev, 0x2c, 0x1af4); pci_device_set_config16(s->pci_dev, 0x2e, device_id); pci_device_set_config8(s->pci_dev, PCI_INTERRUPT_PIN, 1); bar_num = 4; virtio_add_pci_capability(s, 1, bar_num, VIRTIO_PCI_CFG_OFFSET, 0x1000, 0); /* common */ virtio_add_pci_capability(s, 3, bar_num, VIRTIO_PCI_ISR_OFFSET, 0x1000, 0); /* isr */ virtio_add_pci_capability(s, 4, bar_num, VIRTIO_PCI_CONFIG_OFFSET, 0x1000, 0); /* config */ virtio_add_pci_capability(s, 2, bar_num, VIRTIO_PCI_NOTIFY_OFFSET, 0x1000, 0); /* notify */ s->get_ram_ptr = virtio_pci_get_ram_ptr; s->irq = pci_device_get_irq(s->pci_dev, 0); s->mem_map = pci_device_get_mem_map(s->pci_dev); s->mem_range = cpu_register_device(s->mem_map, 0, 0x4000, s, virtio_pci_read, virtio_pci_write, DEVIO_SIZE8 | DEVIO_SIZE16 | DEVIO_SIZE32 | DEVIO_DISABLED); pci_register_bar(s->pci_dev, bar_num, 0x4000, PCI_ADDRESS_SPACE_MEM, s, virtio_pci_bar_set); } else { /* MMIO case */ s->mem_map = bus->mem_map; s->irq = bus->irq; s->mem_range = cpu_register_device(s->mem_map, bus->addr, VIRTIO_PAGE_SIZE, s, virtio_mmio_read, virtio_mmio_write, DEVIO_SIZE8 | DEVIO_SIZE16 | DEVIO_SIZE32); s->get_ram_ptr = virtio_mmio_get_ram_ptr; } s->device_id = device_id; s->vendor_id = 0xffff; s->config_space_size = config_space_size; s->device_recv = device_recv; virtio_reset(s); } static uint16_t virtio_read16(VIRTIODevice *s, virtio_phys_addr_t addr) { uint8_t *ptr; if (addr & 1) return 0; /* unaligned access are not supported */ ptr = s->get_ram_ptr(s, addr); if (!ptr) return 0; return *(uint16_t *)ptr; } static void virtio_write16(VIRTIODevice *s, virtio_phys_addr_t addr, uint16_t val) { uint8_t *ptr; if (addr & 1) return; /* unaligned access are not supported */ ptr = s->get_ram_ptr(s, addr); if (!ptr) return; *(uint16_t *)ptr = val; } static void virtio_write32(VIRTIODevice *s, virtio_phys_addr_t addr, uint32_t val) { uint8_t *ptr; if (addr & 3) return; /* unaligned access are not supported */ ptr = s->get_ram_ptr(s, addr); if (!ptr) return; *(uint32_t *)ptr = val; } static int virtio_memcpy_from_ram(VIRTIODevice *s, uint8_t *buf, virtio_phys_addr_t addr, int count) { uint8_t *ptr; int l; while (count > 0) { l = min_int(count, VIRTIO_PAGE_SIZE - (addr & (VIRTIO_PAGE_SIZE - 1))); ptr = s->get_ram_ptr(s, addr); if (!ptr) return -1; memcpy(buf, ptr, l); addr += l; buf += l; count -= l; } return 0; } static int virtio_memcpy_to_ram(VIRTIODevice *s, virtio_phys_addr_t addr, const uint8_t *buf, int count) { uint8_t *ptr; int l; while (count > 0) { l = min_int(count, VIRTIO_PAGE_SIZE - (addr & (VIRTIO_PAGE_SIZE - 1))); ptr = s->get_ram_ptr(s, addr); if (!ptr) return -1; memcpy(ptr, buf, l); addr += l; buf += l; count -= l; } return 0; } static int get_desc(VIRTIODevice *s, VIRTIODesc *desc, int queue_idx, int desc_idx) { QueueState *qs = &s->queue[queue_idx]; return virtio_memcpy_from_ram(s, (uint8_t *)desc, qs->desc_addr + desc_idx * sizeof(VIRTIODesc), sizeof(VIRTIODesc)); } static int memcpy_to_from_queue(VIRTIODevice *s, uint8_t *buf, int queue_idx, int desc_idx, int offset, int count, BOOL to_queue) { VIRTIODesc desc; int l, f_write_flag; if (count == 0) return 0; get_desc(s, &desc, queue_idx, desc_idx); if (to_queue) { f_write_flag = VRING_DESC_F_WRITE; /* find the first write descriptor */ for (;;) { if ((desc.flags & VRING_DESC_F_WRITE) == f_write_flag) break; if (!(desc.flags & VRING_DESC_F_NEXT)) return -1; desc_idx = desc.next; get_desc(s, &desc, queue_idx, desc_idx); } } else { f_write_flag = 0; } /* find the descriptor at offset */ for (;;) { if ((desc.flags & VRING_DESC_F_WRITE) != f_write_flag) return -1; if (offset < (int)desc.len) break; if (!(desc.flags & VRING_DESC_F_NEXT)) return -1; desc_idx = desc.next; offset -= desc.len; get_desc(s, &desc, queue_idx, desc_idx); } for (;;) { l = min_int(count, desc.len - offset); if (to_queue) virtio_memcpy_to_ram(s, desc.addr + offset, buf, l); else virtio_memcpy_from_ram(s, buf, desc.addr + offset, l); count -= l; if (count == 0) break; offset += l; buf += l; if (offset == (int)desc.len) { if (!(desc.flags & VRING_DESC_F_NEXT)) return -1; desc_idx = desc.next; get_desc(s, &desc, queue_idx, desc_idx); if ((desc.flags & VRING_DESC_F_WRITE) != f_write_flag) return -1; offset = 0; } } return 0; } static int memcpy_from_queue(VIRTIODevice *s, void *buf, int queue_idx, int desc_idx, int offset, int count) { return memcpy_to_from_queue(s, (uint8_t *)buf, queue_idx, desc_idx, offset, count, FALSE); } static int memcpy_to_queue(VIRTIODevice *s, int queue_idx, int desc_idx, int offset, const void *buf, int count) { return memcpy_to_from_queue(s, (uint8_t *)buf, queue_idx, desc_idx, offset, count, TRUE); } /* signal that the descriptor has been consumed */ static void virtio_consume_desc(VIRTIODevice *s, int queue_idx, int desc_idx, int desc_len) { QueueState *qs = &s->queue[queue_idx]; virtio_phys_addr_t addr; uint32_t index; addr = qs->used_addr + 2; index = virtio_read16(s, addr); virtio_write16(s, addr, index + 1); addr = qs->used_addr + 4 + (index & (qs->num - 1)) * 8; virtio_write32(s, addr, desc_idx); virtio_write32(s, addr + 4, desc_len); s->int_status |= 1; set_irq(s->irq, 1); } static int get_desc_rw_size(VIRTIODevice *s, int *pread_size, int *pwrite_size, int queue_idx, int desc_idx) { VIRTIODesc desc; int read_size, write_size; read_size = 0; write_size = 0; get_desc(s, &desc, queue_idx, desc_idx); for (;;) { if (desc.flags & VRING_DESC_F_WRITE) break; read_size += desc.len; if (!(desc.flags & VRING_DESC_F_NEXT)) goto done; desc_idx = desc.next; get_desc(s, &desc, queue_idx, desc_idx); } for (;;) { if (!(desc.flags & VRING_DESC_F_WRITE)) return -1; write_size += desc.len; if (!(desc.flags & VRING_DESC_F_NEXT)) break; desc_idx = desc.next; get_desc(s, &desc, queue_idx, desc_idx); } done: *pread_size = read_size; *pwrite_size = write_size; return 0; } /* XXX: test if the queue is ready ? */ static void queue_notify(VIRTIODevice *s, int queue_idx) { QueueState *qs = &s->queue[queue_idx]; uint16_t avail_idx; int desc_idx, read_size, write_size; if (qs->manual_recv) return; avail_idx = virtio_read16(s, qs->avail_addr + 2); while (qs->last_avail_idx != avail_idx) { desc_idx = virtio_read16(s, qs->avail_addr + 4 + (qs->last_avail_idx & (qs->num - 1)) * 2); if (!get_desc_rw_size(s, &read_size, &write_size, queue_idx, desc_idx)) { #ifdef DEBUG_VIRTIO if (s->debug & VIRTIO_DEBUG_IO) { printf("queue_notify: idx=%d read_size=%d write_size=%d\n", queue_idx, read_size, write_size); } #endif if (s->device_recv(s, queue_idx, desc_idx, read_size, write_size) < 0) break; } qs->last_avail_idx++; } } static uint32_t virtio_config_read(VIRTIODevice *s, uint32_t offset, int size_log2) { uint32_t val; switch (size_log2) { case 0: if (offset < s->config_space_size) { val = s->config_space[offset]; } else { val = 0; } break; case 1: if (offset < (s->config_space_size - 1)) { val = get_le16(&s->config_space[offset]); } else { val = 0; } break; case 2: if (offset < (s->config_space_size - 3)) { val = get_le32(s->config_space + offset); } else { val = 0; } break; default: abort(); } return val; } static void virtio_config_write(VIRTIODevice *s, uint32_t offset, uint32_t val, int size_log2) { switch (size_log2) { case 0: if (offset < s->config_space_size) { s->config_space[offset] = val; if (s->config_write) s->config_write(s); } break; case 1: if (offset < s->config_space_size - 1) { put_le16(s->config_space + offset, val); if (s->config_write) s->config_write(s); } break; case 2: if (offset < s->config_space_size - 3) { put_le32(s->config_space + offset, val); if (s->config_write) s->config_write(s); } break; } } static uint32_t virtio_mmio_read(void *opaque, uint32_t offset, int size_log2) { VIRTIODevice *s = (VIRTIODevice *)opaque; uint32_t val; if (offset >= VIRTIO_MMIO_CONFIG) { return virtio_config_read(s, offset - VIRTIO_MMIO_CONFIG, size_log2); } if (size_log2 == 2) { switch (offset) { case VIRTIO_MMIO_MAGIC_VALUE: val = 0x74726976; break; case VIRTIO_MMIO_VERSION: val = 2; break; case VIRTIO_MMIO_DEVICE_ID: val = s->device_id; break; case VIRTIO_MMIO_VENDOR_ID: val = s->vendor_id; break; case VIRTIO_MMIO_DEVICE_FEATURES: switch (s->device_features_sel) { case 0: val = s->device_features; break; case 1: val = 1; /* version 1 */ break; default: val = 0; break; } break; case VIRTIO_MMIO_DEVICE_FEATURES_SEL: val = s->device_features_sel; break; case VIRTIO_MMIO_QUEUE_SEL: val = s->queue_sel; break; case VIRTIO_MMIO_QUEUE_NUM_MAX: val = MAX_QUEUE_NUM; break; case VIRTIO_MMIO_QUEUE_NUM: val = s->queue[s->queue_sel].num; break; case VIRTIO_MMIO_QUEUE_DESC_LOW: val = s->queue[s->queue_sel].desc_addr; break; case VIRTIO_MMIO_QUEUE_AVAIL_LOW: val = s->queue[s->queue_sel].avail_addr; break; case VIRTIO_MMIO_QUEUE_USED_LOW: val = s->queue[s->queue_sel].used_addr; break; case VIRTIO_MMIO_QUEUE_DESC_HIGH: val = s->queue[s->queue_sel].desc_addr >> 32; break; case VIRTIO_MMIO_QUEUE_AVAIL_HIGH: val = s->queue[s->queue_sel].avail_addr >> 32; break; case VIRTIO_MMIO_QUEUE_USED_HIGH: val = s->queue[s->queue_sel].used_addr >> 32; break; case VIRTIO_MMIO_QUEUE_READY: val = s->queue[s->queue_sel].ready; break; case VIRTIO_MMIO_INTERRUPT_STATUS: val = s->int_status; break; case VIRTIO_MMIO_STATUS: val = s->status; break; case VIRTIO_MMIO_CONFIG_GENERATION: val = 0; break; default: val = 0; break; } } else { val = 0; } #ifdef DEBUG_VIRTIO if (s->debug & VIRTIO_DEBUG_IO) { printf("virto_mmio_read: offset=0x%x val=0x%x size=%d\n", offset, val, 1 << size_log2); } #endif return val; } static void set_low32(virtio_phys_addr_t *paddr, uint32_t val) { *paddr = (*paddr & ~(virtio_phys_addr_t)0xffffffff) | val; } static void set_high32(virtio_phys_addr_t *paddr, uint32_t val) { *paddr = (*paddr & 0xffffffff) | ((virtio_phys_addr_t)val << 32); } static void virtio_mmio_write(void *opaque, uint32_t offset, uint32_t val, int size_log2) { VIRTIODevice *s = (VIRTIODevice *)opaque; #ifdef DEBUG_VIRTIO if (s->debug & VIRTIO_DEBUG_IO) { printf("virto_mmio_write: offset=0x%x val=0x%x size=%d\n", offset, val, 1 << size_log2); } #endif if (offset >= VIRTIO_MMIO_CONFIG) { virtio_config_write(s, offset - VIRTIO_MMIO_CONFIG, val, size_log2); return; } if (size_log2 == 2) { switch (offset) { case VIRTIO_MMIO_DEVICE_FEATURES_SEL: s->device_features_sel = val; break; case VIRTIO_MMIO_QUEUE_SEL: if (val < MAX_QUEUE) s->queue_sel = val; break; case VIRTIO_MMIO_QUEUE_NUM: if ((val & (val - 1)) == 0 && val > 0) { s->queue[s->queue_sel].num = val; } break; case VIRTIO_MMIO_QUEUE_DESC_LOW: set_low32(&s->queue[s->queue_sel].desc_addr, val); break; case VIRTIO_MMIO_QUEUE_AVAIL_LOW: set_low32(&s->queue[s->queue_sel].avail_addr, val); break; case VIRTIO_MMIO_QUEUE_USED_LOW: set_low32(&s->queue[s->queue_sel].used_addr, val); break; case VIRTIO_MMIO_QUEUE_DESC_HIGH: set_high32(&s->queue[s->queue_sel].desc_addr, val); break; case VIRTIO_MMIO_QUEUE_AVAIL_HIGH: set_high32(&s->queue[s->queue_sel].avail_addr, val); break; case VIRTIO_MMIO_QUEUE_USED_HIGH: set_high32(&s->queue[s->queue_sel].used_addr, val); break; case VIRTIO_MMIO_STATUS: s->status = val; if (val == 0) { /* reset */ set_irq(s->irq, 0); virtio_reset(s); } break; case VIRTIO_MMIO_QUEUE_READY: s->queue[s->queue_sel].ready = val & 1; break; case VIRTIO_MMIO_QUEUE_NOTIFY: if (val < MAX_QUEUE) queue_notify(s, val); break; case VIRTIO_MMIO_INTERRUPT_ACK: s->int_status &= ~val; if (s->int_status == 0) { set_irq(s->irq, 0); } break; } } } static uint32_t virtio_pci_read(void *opaque, uint32_t offset1, int size_log2) { VIRTIODevice *s = (VIRTIODevice *)opaque; uint32_t offset; uint32_t val = 0; offset = offset1 & 0xfff; switch (offset1 >> 12) { case VIRTIO_PCI_CFG_OFFSET >> 12: if (size_log2 == 2) { switch (offset) { case VIRTIO_PCI_DEVICE_FEATURE: switch (s->device_features_sel) { case 0: val = s->device_features; break; case 1: val = 1; /* version 1 */ break; default: val = 0; break; } break; case VIRTIO_PCI_DEVICE_FEATURE_SEL: val = s->device_features_sel; break; case VIRTIO_PCI_QUEUE_DESC_LOW: val = s->queue[s->queue_sel].desc_addr; break; case VIRTIO_PCI_QUEUE_AVAIL_LOW: val = s->queue[s->queue_sel].avail_addr; break; case VIRTIO_PCI_QUEUE_USED_LOW: val = s->queue[s->queue_sel].used_addr; break; case VIRTIO_PCI_QUEUE_DESC_HIGH: val = s->queue[s->queue_sel].desc_addr >> 32; break; case VIRTIO_PCI_QUEUE_AVAIL_HIGH: val = s->queue[s->queue_sel].avail_addr >> 32; break; case VIRTIO_PCI_QUEUE_USED_HIGH: val = s->queue[s->queue_sel].used_addr >> 32; break; } } else if (size_log2 == 1) { switch (offset) { case VIRTIO_PCI_NUM_QUEUES: val = MAX_QUEUE_NUM; break; case VIRTIO_PCI_QUEUE_SEL: val = s->queue_sel; break; case VIRTIO_PCI_QUEUE_SIZE: val = s->queue[s->queue_sel].num; break; case VIRTIO_PCI_QUEUE_ENABLE: val = s->queue[s->queue_sel].ready; break; case VIRTIO_PCI_QUEUE_NOTIFY_OFF: val = 0; break; } } else if (size_log2 == 0) { switch (offset) { case VIRTIO_PCI_DEVICE_STATUS: val = s->status; break; } } break; case VIRTIO_PCI_ISR_OFFSET >> 12: if (offset == 0 && size_log2 == 0) { val = s->int_status; s->int_status = 0; set_irq(s->irq, 0); } break; case VIRTIO_PCI_CONFIG_OFFSET >> 12: val = virtio_config_read(s, offset, size_log2); break; } #ifdef DEBUG_VIRTIO if (s->debug & VIRTIO_DEBUG_IO) { printf("virto_pci_read: offset=0x%x val=0x%x size=%d\n", offset1, val, 1 << size_log2); } #endif return val; } static void virtio_pci_write(void *opaque, uint32_t offset1, uint32_t val, int size_log2) { VIRTIODevice *s = (VIRTIODevice *)opaque; uint32_t offset; #ifdef DEBUG_VIRTIO if (s->debug & VIRTIO_DEBUG_IO) { printf("virto_pci_write: offset=0x%x val=0x%x size=%d\n", offset1, val, 1 << size_log2); } #endif offset = offset1 & 0xfff; switch (offset1 >> 12) { case VIRTIO_PCI_CFG_OFFSET >> 12: if (size_log2 == 2) { switch (offset) { case VIRTIO_PCI_DEVICE_FEATURE_SEL: s->device_features_sel = val; break; case VIRTIO_PCI_QUEUE_DESC_LOW: set_low32(&s->queue[s->queue_sel].desc_addr, val); break; case VIRTIO_PCI_QUEUE_AVAIL_LOW: set_low32(&s->queue[s->queue_sel].avail_addr, val); break; case VIRTIO_PCI_QUEUE_USED_LOW: set_low32(&s->queue[s->queue_sel].used_addr, val); break; case VIRTIO_PCI_QUEUE_DESC_HIGH: set_high32(&s->queue[s->queue_sel].desc_addr, val); break; case VIRTIO_PCI_QUEUE_AVAIL_HIGH: set_high32(&s->queue[s->queue_sel].avail_addr, val); break; case VIRTIO_PCI_QUEUE_USED_HIGH: set_high32(&s->queue[s->queue_sel].used_addr, val); break; } } else if (size_log2 == 1) { switch (offset) { case VIRTIO_PCI_QUEUE_SEL: if (val < MAX_QUEUE) s->queue_sel = val; break; case VIRTIO_PCI_QUEUE_SIZE: if ((val & (val - 1)) == 0 && val > 0) { s->queue[s->queue_sel].num = val; } break; case VIRTIO_PCI_QUEUE_ENABLE: s->queue[s->queue_sel].ready = val & 1; break; } } else if (size_log2 == 0) { switch (offset) { case VIRTIO_PCI_DEVICE_STATUS: s->status = val; if (val == 0) { /* reset */ set_irq(s->irq, 0); virtio_reset(s); } break; } } break; case VIRTIO_PCI_CONFIG_OFFSET >> 12: virtio_config_write(s, offset, val, size_log2); break; case VIRTIO_PCI_NOTIFY_OFFSET >> 12: if (val < MAX_QUEUE) queue_notify(s, val); break; } } void virtio_set_debug(VIRTIODevice *s, int debug) { s->debug = debug; } static void virtio_config_change_notify(VIRTIODevice *s) { /* INT_CONFIG interrupt */ s->int_status |= 2; set_irq(s->irq, 1); } /*********************************************************************/ /* block device */ typedef struct { uint32_t type; uint8_t *buf; int write_size; int queue_idx; int desc_idx; } BlockRequest; typedef struct VIRTIOBlockDevice { VIRTIODevice common; BlockDevice *bs; BOOL req_in_progress; BlockRequest req; /* request in progress */ } VIRTIOBlockDevice; typedef struct { uint32_t type; uint32_t ioprio; uint64_t sector_num; } BlockRequestHeader; #define VIRTIO_BLK_T_IN 0 #define VIRTIO_BLK_T_OUT 1 #define VIRTIO_BLK_T_FLUSH 4 #define VIRTIO_BLK_T_FLUSH_OUT 5 #define VIRTIO_BLK_S_OK 0 #define VIRTIO_BLK_S_IOERR 1 #define VIRTIO_BLK_S_UNSUPP 2 #define SECTOR_SIZE 512 static void virtio_block_req_end(VIRTIODevice *s, int ret) { VIRTIOBlockDevice *s1 = (VIRTIOBlockDevice *)s; int write_size; int queue_idx = s1->req.queue_idx; int desc_idx = s1->req.desc_idx; uint8_t *buf, buf1[1]; switch (s1->req.type) { case VIRTIO_BLK_T_IN: write_size = s1->req.write_size; buf = s1->req.buf; if (ret < 0) { buf[write_size - 1] = VIRTIO_BLK_S_IOERR; } else { buf[write_size - 1] = VIRTIO_BLK_S_OK; } memcpy_to_queue(s, queue_idx, desc_idx, 0, buf, write_size); free(buf); virtio_consume_desc(s, queue_idx, desc_idx, write_size); break; case VIRTIO_BLK_T_OUT: if (ret < 0) buf1[0] = VIRTIO_BLK_S_IOERR; else buf1[0] = VIRTIO_BLK_S_OK; memcpy_to_queue(s, queue_idx, desc_idx, 0, buf1, sizeof(buf1)); virtio_consume_desc(s, queue_idx, desc_idx, 1); break; default: abort(); } } static void virtio_block_req_cb(void *opaque, int ret) { VIRTIODevice *s = (VIRTIODevice *)opaque; VIRTIOBlockDevice *s1 = (VIRTIOBlockDevice *)s; virtio_block_req_end(s, ret); s1->req_in_progress = FALSE; /* handle next requests */ queue_notify((VIRTIODevice *)s, s1->req.queue_idx); } /* XXX: handle async I/O */ static int virtio_block_recv_request(VIRTIODevice *s, int queue_idx, int desc_idx, int read_size, int write_size) { VIRTIOBlockDevice *s1 = (VIRTIOBlockDevice *)s; BlockDevice *bs = s1->bs; BlockRequestHeader h; uint8_t *buf; int len, ret; if (s1->req_in_progress) return -1; if (memcpy_from_queue(s, &h, queue_idx, desc_idx, 0, sizeof(h)) < 0) return 0; s1->req.type = h.type; s1->req.queue_idx = queue_idx; s1->req.desc_idx = desc_idx; switch (h.type) { case VIRTIO_BLK_T_IN: s1->req.buf = (uint8_t *)malloc(write_size); s1->req.write_size = write_size; ret = bs->read_async(bs, h.sector_num, s1->req.buf, (write_size - 1) / SECTOR_SIZE, virtio_block_req_cb, s); if (ret > 0) { /* asyncronous read */ s1->req_in_progress = TRUE; } else { virtio_block_req_end(s, ret); } break; case VIRTIO_BLK_T_OUT: assert(write_size >= 1); len = read_size - sizeof(h); buf = (uint8_t *)malloc(len); memcpy_from_queue(s, buf, queue_idx, desc_idx, sizeof(h), len); ret = bs->write_async(bs, h.sector_num, buf, len / SECTOR_SIZE, virtio_block_req_cb, s); free(buf); if (ret > 0) { /* asyncronous write */ s1->req_in_progress = TRUE; } else { virtio_block_req_end(s, ret); } break; default: break; } return 0; } VIRTIODevice *virtio_block_init(VIRTIOBusDef *bus, BlockDevice *bs) { uint64_t nb_sectors; VIRTIOBlockDevice *s = (VIRTIOBlockDevice *)mallocz(sizeof(*s)); virtio_init(&s->common, bus, 2, 8, virtio_block_recv_request); s->bs = bs; nb_sectors = bs->get_sector_count(bs); put_le32(s->common.config_space, nb_sectors); put_le32(s->common.config_space + 4, nb_sectors >> 32); return (VIRTIODevice *)s; } /*********************************************************************/ /* network device */ typedef struct VIRTIONetDevice { VIRTIODevice common; EthernetDevice *es; int header_size; } VIRTIONetDevice; typedef struct { uint8_t flags; uint8_t gso_type; uint16_t hdr_len; uint16_t gso_size; uint16_t csum_start; uint16_t csum_offset; uint16_t num_buffers; } VIRTIONetHeader; static int virtio_net_recv_request(VIRTIODevice *s, int queue_idx, int desc_idx, int read_size, int write_size) { VIRTIONetDevice *s1 = (VIRTIONetDevice *)s; EthernetDevice *es = s1->es; VIRTIONetHeader h; uint8_t *buf; int len; if (queue_idx == 1) { /* send to network */ if (memcpy_from_queue(s, &h, queue_idx, desc_idx, 0, s1->header_size) < 0) return 0; len = read_size - s1->header_size; buf = (uint8_t *)malloc(len); memcpy_from_queue(s, buf, queue_idx, desc_idx, s1->header_size, len); es->write_packet(es, buf, len); free(buf); virtio_consume_desc(s, queue_idx, desc_idx, 0); } return 0; } static BOOL virtio_net_can_write_packet(EthernetDevice *es) { VIRTIODevice *s = (VIRTIODevice *)es->device_opaque; QueueState *qs = &s->queue[0]; uint16_t avail_idx; if (!qs->ready) return FALSE; avail_idx = virtio_read16(s, qs->avail_addr + 2); return qs->last_avail_idx != avail_idx; } static void virtio_net_write_packet(EthernetDevice *es, const uint8_t *buf, int buf_len) { VIRTIODevice *s = (VIRTIODevice *)es->device_opaque; VIRTIONetDevice *s1 = (VIRTIONetDevice *)s; int queue_idx = 0; QueueState *qs = &s->queue[queue_idx]; int desc_idx; VIRTIONetHeader h; int len, read_size, write_size; uint16_t avail_idx; if (!qs->ready) return; avail_idx = virtio_read16(s, qs->avail_addr + 2); if (qs->last_avail_idx == avail_idx) return; desc_idx = virtio_read16(s, qs->avail_addr + 4 + (qs->last_avail_idx & (qs->num - 1)) * 2); if (get_desc_rw_size(s, &read_size, &write_size, queue_idx, desc_idx)) return; len = s1->header_size + buf_len; if (len > write_size) return; memset(&h, 0, s1->header_size); memcpy_to_queue(s, queue_idx, desc_idx, 0, &h, s1->header_size); memcpy_to_queue(s, queue_idx, desc_idx, s1->header_size, buf, buf_len); virtio_consume_desc(s, queue_idx, desc_idx, len); qs->last_avail_idx++; } static void virtio_net_set_carrier(EthernetDevice *es, BOOL carrier_state) { #if 0 VIRTIODevice *s1 = es->device_opaque; VIRTIONetDevice *s = (VIRTIONetDevice *)s1; int cur_carrier_state; // printf("virtio_net_set_carrier: %d\n", carrier_state); cur_carrier_state = s->common.config_space[6] & 1; if (cur_carrier_state != carrier_state) { s->common.config_space[6] = (carrier_state << 0); virtio_config_change_notify(s1); } #endif } VIRTIODevice *virtio_net_init(VIRTIOBusDef *bus, EthernetDevice *es) { VIRTIONetDevice *s = (VIRTIONetDevice *)mallocz(sizeof(*s)); virtio_init(&s->common, bus, 1, 6 + 2, virtio_net_recv_request); /* VIRTIO_NET_F_MAC, VIRTIO_NET_F_STATUS */ s->common.device_features = (1 << 5) /* | (1 << 16) */; s->common.queue[0].manual_recv = TRUE; s->es = es; memcpy(s->common.config_space, es->mac_addr, 6); /* status */ s->common.config_space[6] = 0; s->common.config_space[7] = 0; s->header_size = sizeof(VIRTIONetHeader); es->device_opaque = s; es->device_can_write_packet = virtio_net_can_write_packet; es->device_write_packet = virtio_net_write_packet; es->device_set_carrier = virtio_net_set_carrier; return (VIRTIODevice *)s; } /*********************************************************************/ /* console device */ typedef struct VIRTIOConsoleDevice { VIRTIODevice common; CharacterDevice *cs; } VIRTIOConsoleDevice; static int virtio_console_recv_request(VIRTIODevice *s, int queue_idx, int desc_idx, int read_size, int write_size) { VIRTIOConsoleDevice *s1 = (VIRTIOConsoleDevice *)s; CharacterDevice *cs = s1->cs; uint8_t *buf; if (queue_idx == 1) { /* send to console */ buf = (uint8_t *)malloc(read_size); memcpy_from_queue(s, buf, queue_idx, desc_idx, 0, read_size); cs->write_data(cs->opaque, buf, read_size); free(buf); virtio_consume_desc(s, queue_idx, desc_idx, 0); } return 0; } BOOL virtio_console_can_write_data(VIRTIODevice *s) { QueueState *qs = &s->queue[0]; uint16_t avail_idx; if (!qs->ready) return FALSE; avail_idx = virtio_read16(s, qs->avail_addr + 2); return qs->last_avail_idx != avail_idx; } int virtio_console_get_write_len(VIRTIODevice *s) { int queue_idx = 0; QueueState *qs = &s->queue[queue_idx]; int desc_idx; int read_size, write_size; uint16_t avail_idx; if (!qs->ready) return 0; avail_idx = virtio_read16(s, qs->avail_addr + 2); if (qs->last_avail_idx == avail_idx) return 0; desc_idx = virtio_read16(s, qs->avail_addr + 4 + (qs->last_avail_idx & (qs->num - 1)) * 2); if (get_desc_rw_size(s, &read_size, &write_size, queue_idx, desc_idx)) return 0; return write_size; } int virtio_console_write_data(VIRTIODevice *s, const uint8_t *buf, int buf_len) { int queue_idx = 0; QueueState *qs = &s->queue[queue_idx]; int desc_idx; uint16_t avail_idx; if (!qs->ready) return 0; avail_idx = virtio_read16(s, qs->avail_addr + 2); if (qs->last_avail_idx == avail_idx) return 0; desc_idx = virtio_read16(s, qs->avail_addr + 4 + (qs->last_avail_idx & (qs->num - 1)) * 2); memcpy_to_queue(s, queue_idx, desc_idx, 0, buf, buf_len); virtio_consume_desc(s, queue_idx, desc_idx, buf_len); qs->last_avail_idx++; return buf_len; } /* send a resize event */ void virtio_console_resize_event(VIRTIODevice *s, int width, int height) { /* indicate the console size */ put_le16(s->config_space + 0, width); put_le16(s->config_space + 2, height); virtio_config_change_notify(s); } VIRTIODevice *virtio_console_init(VIRTIOBusDef *bus, CharacterDevice *cs) { VIRTIOConsoleDevice *s = (VIRTIOConsoleDevice *)mallocz(sizeof(*s)); virtio_init(&s->common, bus, 3, 4, virtio_console_recv_request); s->common.device_features = (1 << 0); /* VIRTIO_CONSOLE_F_SIZE */ s->common.queue[0].manual_recv = TRUE; s->cs = cs; return (VIRTIODevice *)s; } /*********************************************************************/ /* input device */ enum { VIRTIO_INPUT_CFG_UNSET = 0x00, VIRTIO_INPUT_CFG_ID_NAME = 0x01, VIRTIO_INPUT_CFG_ID_SERIAL = 0x02, VIRTIO_INPUT_CFG_ID_DEVIDS = 0x03, VIRTIO_INPUT_CFG_PROP_BITS = 0x10, VIRTIO_INPUT_CFG_EV_BITS = 0x11, VIRTIO_INPUT_CFG_ABS_INFO = 0x12, }; #define VIRTIO_INPUT_EV_SYN 0x00 #define VIRTIO_INPUT_EV_KEY 0x01 #define VIRTIO_INPUT_EV_REL 0x02 #define VIRTIO_INPUT_EV_ABS 0x03 #define VIRTIO_INPUT_EV_REP 0x14 #define BTN_LEFT 0x110 #define BTN_RIGHT 0x111 #define BTN_MIDDLE 0x112 #define BTN_GEAR_DOWN 0x150 #define BTN_GEAR_UP 0x151 #define REL_X 0x00 #define REL_Y 0x01 #define REL_Z 0x02 #define REL_WHEEL 0x08 #define ABS_X 0x00 #define ABS_Y 0x01 #define ABS_Z 0x02 typedef struct VIRTIOInputDevice { VIRTIODevice common; VirtioInputTypeEnum type; uint32_t buttons_state; } VIRTIOInputDevice; static const uint16_t buttons_list[] = { BTN_LEFT, BTN_RIGHT, BTN_MIDDLE }; static int virtio_input_recv_request(VIRTIODevice *s, int queue_idx, int desc_idx, int read_size, int write_size) { if (queue_idx == 1) { /* led & keyboard updates */ // printf("%s: write_size=%d\n", __func__, write_size); virtio_consume_desc(s, queue_idx, desc_idx, 0); } return 0; } /* return < 0 if could not send key event */ static int virtio_input_queue_event(VIRTIODevice *s, uint16_t type, uint16_t code, uint32_t value) { int queue_idx = 0; QueueState *qs = &s->queue[queue_idx]; int desc_idx, buf_len; uint16_t avail_idx; uint8_t buf[8]; if (!qs->ready) return -1; put_le16(buf, type); put_le16(buf + 2, code); put_le32(buf + 4, value); buf_len = 8; avail_idx = virtio_read16(s, qs->avail_addr + 2); if (qs->last_avail_idx == avail_idx) return -1; desc_idx = virtio_read16(s, qs->avail_addr + 4 + (qs->last_avail_idx & (qs->num - 1)) * 2); // printf("send: queue_idx=%d desc_idx=%d\n", queue_idx, desc_idx); memcpy_to_queue(s, queue_idx, desc_idx, 0, buf, buf_len); virtio_consume_desc(s, queue_idx, desc_idx, buf_len); qs->last_avail_idx++; return 0; } int virtio_input_send_key_event(VIRTIODevice *s, BOOL is_down, uint16_t key_code) { VIRTIOInputDevice *s1 = (VIRTIOInputDevice *)s; int ret; if (s1->type != VIRTIO_INPUT_TYPE_KEYBOARD) return -1; ret = virtio_input_queue_event(s, VIRTIO_INPUT_EV_KEY, key_code, is_down); if (ret) return ret; return virtio_input_queue_event(s, VIRTIO_INPUT_EV_SYN, 0, 0); } /* also used for the tablet */ int virtio_input_send_mouse_event(VIRTIODevice *s, int dx, int dy, int dz, unsigned int buttons) { VIRTIOInputDevice *s1 = (VIRTIOInputDevice *)s; int ret, b, last_b; if (s1->type != VIRTIO_INPUT_TYPE_MOUSE && s1->type != VIRTIO_INPUT_TYPE_TABLET) return -1; if (s1->type == VIRTIO_INPUT_TYPE_MOUSE) { ret = virtio_input_queue_event(s, VIRTIO_INPUT_EV_REL, REL_X, dx); if (ret != 0) return ret; ret = virtio_input_queue_event(s, VIRTIO_INPUT_EV_REL, REL_Y, dy); if (ret != 0) return ret; } else { ret = virtio_input_queue_event(s, VIRTIO_INPUT_EV_ABS, ABS_X, dx); if (ret != 0) return ret; ret = virtio_input_queue_event(s, VIRTIO_INPUT_EV_ABS, ABS_Y, dy); if (ret != 0) return ret; } if (dz != 0) { ret = virtio_input_queue_event(s, VIRTIO_INPUT_EV_REL, REL_WHEEL, dz); if (ret != 0) return ret; } if (buttons != s1->buttons_state) { for (unsigned int i = 0; i < countof(buttons_list); i++) { b = (buttons >> i) & 1; last_b = (s1->buttons_state >> i) & 1; if (b != last_b) { ret = virtio_input_queue_event(s, VIRTIO_INPUT_EV_KEY, buttons_list[i], b); if (ret != 0) return ret; } } s1->buttons_state = buttons; } return virtio_input_queue_event(s, VIRTIO_INPUT_EV_SYN, 0, 0); } static void set_bit(uint8_t *tab, int k) { tab[k >> 3] |= 1 << (k & 7); } static void virtio_input_config_write(VIRTIODevice *s) { VIRTIOInputDevice *s1 = (VIRTIOInputDevice *)s; uint8_t *config = s->config_space; // printf("config_write: %02x %02x\n", config[0], config[1]); switch (config[0]) { case VIRTIO_INPUT_CFG_UNSET: break; case VIRTIO_INPUT_CFG_ID_NAME: { const char *name; int len; switch (s1->type) { case VIRTIO_INPUT_TYPE_KEYBOARD: name = "virtio_keyboard"; break; case VIRTIO_INPUT_TYPE_MOUSE: name = "virtio_mouse"; break; case VIRTIO_INPUT_TYPE_TABLET: name = "virtio_tablet"; break; default: abort(); } len = strlen(name); config[2] = len; memcpy(config + 8, name, len); } break; default: case VIRTIO_INPUT_CFG_ID_SERIAL: case VIRTIO_INPUT_CFG_ID_DEVIDS: case VIRTIO_INPUT_CFG_PROP_BITS: config[2] = 0; /* size of reply */ break; case VIRTIO_INPUT_CFG_EV_BITS: config[2] = 0; switch (s1->type) { case VIRTIO_INPUT_TYPE_KEYBOARD: switch (config[1]) { case VIRTIO_INPUT_EV_KEY: config[2] = 128 / 8; memset(config + 8, 0xff, 128 / 8); /* bitmap */ break; case VIRTIO_INPUT_EV_REP: /* allow key repetition */ config[2] = 1; break; default: break; } break; case VIRTIO_INPUT_TYPE_MOUSE: switch (config[1]) { case VIRTIO_INPUT_EV_KEY: config[2] = 512 / 8; memset(config + 8, 0, 512 / 8); /* bitmap */ for (unsigned int i = 0; i < countof(buttons_list); i++) set_bit(config + 8, buttons_list[i]); break; case VIRTIO_INPUT_EV_REL: config[2] = 2; config[8] = 0; config[9] = 0; set_bit(config + 8, REL_X); set_bit(config + 8, REL_Y); set_bit(config + 8, REL_WHEEL); break; default: break; } break; case VIRTIO_INPUT_TYPE_TABLET: switch (config[1]) { case VIRTIO_INPUT_EV_KEY: config[2] = 512 / 8; memset(config + 8, 0, 512 / 8); /* bitmap */ for (unsigned int i = 0; i < countof(buttons_list); i++) set_bit(config + 8, buttons_list[i]); break; case VIRTIO_INPUT_EV_REL: config[2] = 2; config[8] = 0; config[9] = 0; set_bit(config + 8, REL_WHEEL); break; case VIRTIO_INPUT_EV_ABS: config[2] = 1; config[8] = 0; set_bit(config + 8, ABS_X); set_bit(config + 8, ABS_Y); break; default: break; } break; default: abort(); } break; case VIRTIO_INPUT_CFG_ABS_INFO: if (s1->type == VIRTIO_INPUT_TYPE_TABLET && config[1] <= 1) { /* for ABS_X and ABS_Y */ config[2] = 5 * 4; put_le32(config + 8, 0); /* min */ put_le32(config + 12, VIRTIO_INPUT_ABS_SCALE - 1) ; /* max */ put_le32(config + 16, 0); /* fuzz */ put_le32(config + 20, 0); /* flat */ put_le32(config + 24, 0); /* res */ } break; } } VIRTIODevice *virtio_input_init(VIRTIOBusDef *bus, VirtioInputTypeEnum type) { VIRTIOInputDevice *s = (VIRTIOInputDevice *)mallocz(sizeof(*s)); virtio_init(&s->common, bus, 18, 256, virtio_input_recv_request); s->common.queue[0].manual_recv = TRUE; s->common.device_features = 0; s->common.config_write = virtio_input_config_write; s->type = type; return (VIRTIODevice *)s; } /*********************************************************************/ /* 9p filesystem device */ typedef struct { struct list_head link; uint32_t fid; FSFile *fd; } FIDDesc; typedef struct VIRTIO9PDevice { VIRTIODevice common; FSDevice *fs; int msize; /* maximum message size */ struct list_head fid_list; /* list of FIDDesc */ BOOL req_in_progress; } VIRTIO9PDevice; static FIDDesc *fid_find1(VIRTIO9PDevice *s, uint32_t fid) { struct list_head *el; FIDDesc *f; list_for_each(el, &s->fid_list) { f = list_entry(el, FIDDesc, link); if (f->fid == fid) return f; } return NULL; } static FSFile *fid_find(VIRTIO9PDevice *s, uint32_t fid) { FIDDesc *f; f = fid_find1(s, fid); if (!f) return NULL; return f->fd; } static void fid_delete(VIRTIO9PDevice *s, uint32_t fid) { FIDDesc *f; f = fid_find1(s, fid); if (f) { s->fs->fs_delete(s->fs, f->fd); list_del(&f->link); free(f); } } static void fid_set(VIRTIO9PDevice *s, uint32_t fid, FSFile *fd) { FIDDesc *f = fid_find1(s, fid); if (f) { s->fs->fs_delete(s->fs, f->fd); f->fd = fd; return; } f = (FIDDesc *)malloc(sizeof(*f)); f->fid = fid; f->fd = fd; list_add(&f->link, &s->fid_list); } #ifdef DEBUG_VIRTIO typedef struct { uint8_t tag; const char *name; } Virtio9POPName; static const Virtio9POPName virtio_9p_op_names[] = { { 8, "statfs" }, { 12, "lopen" }, { 14, "lcreate" }, { 16, "symlink" }, { 18, "mknod" }, { 22, "readlink" }, { 24, "getattr" }, { 26, "setattr" }, { 30, "xattrwalk" }, { 40, "readdir" }, { 50, "fsync" }, { 52, "lock" }, { 54, "getlock" }, { 70, "link" }, { 72, "mkdir" }, { 74, "renameat" }, { 76, "unlinkat" }, { 100, "version" }, { 104, "attach" }, { 108, "flush" }, { 110, "walk" }, { 116, "read" }, { 118, "write" }, { 120, "clunk" }, { 0, NULL }, }; static const char *get_9p_op_name(int tag) { const Virtio9POPName *p; for (p = virtio_9p_op_names; p->name != NULL; p++) { if (p->tag == tag) return p->name; } return NULL; } #endif /* DEBUG_VIRTIO */ static int marshall(VIRTIO9PDevice *s, uint8_t *buf1, int max_len, const char *fmt, ...) { va_list ap; int c; uint32_t val; uint64_t val64; uint8_t *buf, *buf_end; #ifdef DEBUG_VIRTIO if (s->common.debug & VIRTIO_DEBUG_9P) printf(" ->"); #endif va_start(ap, fmt); buf = buf1; buf_end = buf1 + max_len; for (;;) { c = *fmt++; if (c == '\0') break; switch (c) { case 'b': assert(buf + 1 <= buf_end); val = va_arg(ap, int); #ifdef DEBUG_VIRTIO if (s->common.debug & VIRTIO_DEBUG_9P) printf(" b=%d", val); #endif buf[0] = val; buf += 1; break; case 'h': assert(buf + 2 <= buf_end); val = va_arg(ap, int); #ifdef DEBUG_VIRTIO if (s->common.debug & VIRTIO_DEBUG_9P) printf(" h=%d", val); #endif put_le16(buf, val); buf += 2; break; case 'w': assert(buf + 4 <= buf_end); val = va_arg(ap, int); #ifdef DEBUG_VIRTIO if (s->common.debug & VIRTIO_DEBUG_9P) printf(" w=%d", val); #endif put_le32(buf, val); buf += 4; break; case 'd': assert(buf + 8 <= buf_end); val64 = va_arg(ap, uint64_t); #ifdef DEBUG_VIRTIO if (s->common.debug & VIRTIO_DEBUG_9P) printf(" d=%" PRId64, val64); #endif put_le64(buf, val64); buf += 8; break; case 's': { char *str; int len; str = va_arg(ap, char *); #ifdef DEBUG_VIRTIO if (s->common.debug & VIRTIO_DEBUG_9P) printf(" s=\"%s\"", str); #endif len = strlen(str); assert(len <= 65535); assert(buf + 2 + len <= buf_end); put_le16(buf, len); buf += 2; memcpy(buf, str, len); buf += len; } break; case 'Q': { FSQID *qid; assert(buf + 13 <= buf_end); qid = va_arg(ap, FSQID *); #ifdef DEBUG_VIRTIO if (s->common.debug & VIRTIO_DEBUG_9P) printf(" Q=%d:%d:%" PRIu64, qid->type, qid->version, qid->path); #endif buf[0] = qid->type; put_le32(buf + 1, qid->version); put_le64(buf + 5, qid->path); buf += 13; } break; default: abort(); } } va_end(ap); return buf - buf1; } /* return < 0 if error */ /* XXX: free allocated strings in case of error */ static int unmarshall(VIRTIO9PDevice *s, int queue_idx, int desc_idx, int *poffset, const char *fmt, ...) { VIRTIODevice *s1 = (VIRTIODevice *)s; va_list ap; int offset, c; uint8_t buf[16]; offset = *poffset; va_start(ap, fmt); for (;;) { c = *fmt++; if (c == '\0') break; switch (c) { case 'b': { uint8_t *ptr; if (memcpy_from_queue(s1, buf, queue_idx, desc_idx, offset, 1)) return -1; ptr = va_arg(ap, uint8_t *); *ptr = buf[0]; offset += 1; #ifdef DEBUG_VIRTIO if (s->common.debug & VIRTIO_DEBUG_9P) printf(" b=%d", *ptr); #endif } break; case 'h': { uint16_t *ptr; if (memcpy_from_queue(s1, buf, queue_idx, desc_idx, offset, 2)) return -1; ptr = va_arg(ap, uint16_t *); *ptr = get_le16(buf); offset += 2; #ifdef DEBUG_VIRTIO if (s->common.debug & VIRTIO_DEBUG_9P) printf(" h=%d", *ptr); #endif } break; case 'w': { uint32_t *ptr; if (memcpy_from_queue(s1, buf, queue_idx, desc_idx, offset, 4)) return -1; ptr = va_arg(ap, uint32_t *); *ptr = get_le32(buf); offset += 4; #ifdef DEBUG_VIRTIO if (s->common.debug & VIRTIO_DEBUG_9P) printf(" w=%d", *ptr); #endif } break; case 'd': { uint64_t *ptr; if (memcpy_from_queue(s1, buf, queue_idx, desc_idx, offset, 8)) return -1; ptr = va_arg(ap, uint64_t *); *ptr = get_le64(buf); offset += 8; #ifdef DEBUG_VIRTIO if (s->common.debug & VIRTIO_DEBUG_9P) printf(" d=%" PRId64, *ptr); #endif } break; case 's': { int len; if (memcpy_from_queue(s1, buf, queue_idx, desc_idx, offset, 2)) return -1; len = get_le16(buf); offset += 2; char *str = (char *)malloc(len + 1); if (memcpy_from_queue(s1, str, queue_idx, desc_idx, offset, len)) return -1; str[len] = '\0'; offset += len; char **ptr = va_arg(ap, char **); *ptr = str; #ifdef DEBUG_VIRTIO if (s->common.debug & VIRTIO_DEBUG_9P) printf(" s=\"%s\"", *ptr); #endif } break; default: abort(); } } va_end(ap); *poffset = offset; return 0; } static void virtio_9p_send_reply(VIRTIO9PDevice *s, int queue_idx, int desc_idx, uint8_t id, uint16_t tag, uint8_t *buf, int buf_len) { int len; #ifdef DEBUG_VIRTIO if (s->common.debug & VIRTIO_DEBUG_9P) { if (id == 6) printf(" (error)"); printf("\n"); } #endif len = buf_len + 7; uint8_t *buf1 = (uint8_t *)malloc(len); put_le32(buf1, len); buf1[4] = id + 1; put_le16(buf1 + 5, tag); memcpy(buf1 + 7, buf, buf_len); memcpy_to_queue((VIRTIODevice *)s, queue_idx, desc_idx, 0, buf1, len); virtio_consume_desc((VIRTIODevice *)s, queue_idx, desc_idx, len); free(buf1); } static void virtio_9p_send_error(VIRTIO9PDevice *s, int queue_idx, int desc_idx, uint16_t tag, uint32_t error) { uint8_t buf[4]; int buf_len; buf_len = marshall(s, buf, sizeof(buf), "w", -error); virtio_9p_send_reply(s, queue_idx, desc_idx, 6, tag, buf, buf_len); } typedef struct { VIRTIO9PDevice *dev; int queue_idx; int desc_idx; uint16_t tag; } P9OpenInfo; static void virtio_9p_open_reply(FSDevice *fs, FSQID *qid, int err, P9OpenInfo *oi) { VIRTIO9PDevice *s = oi->dev; uint8_t buf[32]; int buf_len; if (err < 0) { virtio_9p_send_error(s, oi->queue_idx, oi->desc_idx, oi->tag, err); } else { buf_len = marshall(s, buf, sizeof(buf), "Qw", qid, s->msize - 24); virtio_9p_send_reply(s, oi->queue_idx, oi->desc_idx, 12, oi->tag, buf, buf_len); } free(oi); } static void virtio_9p_open_cb(FSDevice *fs, FSQID *qid, int err, void *opaque) { P9OpenInfo *oi = (P9OpenInfo *)opaque; VIRTIO9PDevice *s = oi->dev; int queue_idx = oi->queue_idx; virtio_9p_open_reply(fs, qid, err, oi); s->req_in_progress = FALSE; /* handle next requests */ queue_notify((VIRTIODevice *)s, queue_idx); } static int virtio_9p_recv_request(VIRTIODevice *s1, int queue_idx, int desc_idx, int read_size, int write_size) { VIRTIO9PDevice *s = (VIRTIO9PDevice *)s1; int offset, header_len; uint8_t id; uint16_t tag; uint8_t buf[1024]; int buf_len, err; FSDevice *fs = s->fs; if (queue_idx != 0) return 0; if (s->req_in_progress) return -1; offset = 0; header_len = 4 + 1 + 2; if (memcpy_from_queue(s1, buf, queue_idx, desc_idx, offset, header_len)) { tag = 0; goto protocol_error; } //size = get_le32(buf); id = buf[4]; tag = get_le16(buf + 5); offset += header_len; #ifdef DEBUG_VIRTIO if (s1->debug & VIRTIO_DEBUG_9P) { const char *name; name = get_9p_op_name(id); printf("9p: op="); if (name) printf("%s", name); else printf("%d", id); } #endif /* Note: same subset as JOR1K */ switch (id) { case 8: /* statfs */ { FSStatFS st; fs->fs_statfs(fs, &st); buf_len = marshall(s, buf, sizeof(buf), "wwddddddw", 0, st.f_bsize, st.f_blocks, st.f_bfree, st.f_bavail, st.f_files, st.f_ffree, 0, /* id */ 256 /* max filename length */ ); virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, buf, buf_len); } break; case 12: /* lopen */ { uint32_t fid, flags; if (unmarshall(s, queue_idx, desc_idx, &offset, "ww", &fid, &flags)) goto protocol_error; FSFile *f = fid_find(s, fid); if (!f) goto fid_not_found; P9OpenInfo *oi = (P9OpenInfo *)malloc(sizeof(*oi)); oi->dev = s; oi->queue_idx = queue_idx; oi->desc_idx = desc_idx; oi->tag = tag; FSQID qid; err = fs->fs_open(fs, &qid, f, flags, virtio_9p_open_cb, oi); if (err <= 0) { virtio_9p_open_reply(fs, &qid, err, oi); } else { s->req_in_progress = TRUE; } } break; case 14: /* lcreate */ { uint32_t fid, flags, mode, gid; char *name; FSFile *f; FSQID qid; if (unmarshall(s, queue_idx, desc_idx, &offset, "wswww", &fid, &name, &flags, &mode, &gid)) goto protocol_error; f = fid_find(s, fid); if (!f) { err = -P9_EPROTO; } else { err = fs->fs_create(fs, &qid, f, name, flags, mode, gid); } free(name); if (err) goto error; buf_len = marshall(s, buf, sizeof(buf), "Qw", &qid, s->msize - 24); virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, buf, buf_len); } break; case 16: /* symlink */ { uint32_t fid, gid; char *name, *symgt; FSFile *f; FSQID qid; if (unmarshall(s, queue_idx, desc_idx, &offset, "wssw", &fid, &name, &symgt, &gid)) goto protocol_error; f = fid_find(s, fid); if (!f) { err = -P9_EPROTO; } else { err = fs->fs_symlink(fs, &qid, f, name, symgt, gid); } free(name); free(symgt); if (err) goto error; buf_len = marshall(s, buf, sizeof(buf), "Q", &qid); virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, buf, buf_len); } break; case 18: /* mknod */ { uint32_t fid, mode, major, minor, gid; char *name; FSFile *f; FSQID qid; if (unmarshall(s, queue_idx, desc_idx, &offset, "wswwww", &fid, &name, &mode, &major, &minor, &gid)) goto protocol_error; f = fid_find(s, fid); if (!f) { err = -P9_EPROTO; } else { err = fs->fs_mknod(fs, &qid, f, name, mode, major, minor, gid); } free(name); if (err) goto error; buf_len = marshall(s, buf, sizeof(buf), "Q", &qid); virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, buf, buf_len); } break; case 22: /* readlink */ { uint32_t fid; char buf1[1024]; FSFile *f; if (unmarshall(s, queue_idx, desc_idx, &offset, "w", &fid)) goto protocol_error; f = fid_find(s, fid); if (!f) { err = -P9_EPROTO; } else { err = fs->fs_readlink(fs, buf1, sizeof(buf1), f); } if (err) goto error; buf_len = marshall(s, buf, sizeof(buf), "s", buf1); virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, buf, buf_len); } break; case 24: /* getattr */ { uint32_t fid; uint64_t mask; FSFile *f; FSStat st; if (unmarshall(s, queue_idx, desc_idx, &offset, "wd", &fid, &mask)) goto protocol_error; f = fid_find(s, fid); if (!f) goto fid_not_found; err = fs->fs_stat(fs, f, &st); if (err) goto error; buf_len = marshall(s, buf, sizeof(buf), "dQwwwddddddddddddddd", mask, &st.qid, st.st_mode, st.st_uid, st.st_gid, st.st_nlink, st.st_rdev, st.st_size, st.st_blksize, st.st_blocks, st.st_atime_sec, (uint64_t)st.st_atime_nsec, st.st_mtime_sec, (uint64_t)st.st_mtime_nsec, st.st_ctime_sec, (uint64_t)st.st_ctime_nsec, (uint64_t)0, (uint64_t)0, (uint64_t)0, (uint64_t)0); virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, buf, buf_len); } break; case 26: /* setattr */ { uint32_t fid, mask, mode, uid, gid; uint64_t size, atime_sec, atime_nsec, mtime_sec, mtime_nsec; FSFile *f; if (unmarshall(s, queue_idx, desc_idx, &offset, "wwwwwddddd", &fid, &mask, &mode, &uid, &gid, &size, &atime_sec, &atime_nsec, &mtime_sec, &mtime_nsec)) goto protocol_error; f = fid_find(s, fid); if (!f) goto fid_not_found; err = fs->fs_setattr(fs, f, mask, mode, uid, gid, size, atime_sec, atime_nsec, mtime_sec, mtime_nsec); if (err) goto error; virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, NULL, 0); } break; case 30: /* xattrwalk */ { /* not supported yet */ err = -P9_ENOTSUP; goto error; } break; case 40: /* readdir */ { uint32_t fid, count; uint64_t offs; uint8_t *buf; int n; FSFile *f; if (unmarshall(s, queue_idx, desc_idx, &offset, "wdw", &fid, &offs, &count)) goto protocol_error; f = fid_find(s, fid); if (!f) goto fid_not_found; buf = (uint8_t *)malloc(count + 4); n = fs->fs_readdir(fs, f, offs, buf + 4, count); if (n < 0) { err = n; goto error; } put_le32(buf, n); virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, buf, n + 4); free(buf); } break; case 50: /* fsync */ { uint32_t fid; if (unmarshall(s, queue_idx, desc_idx, &offset, "w", &fid)) goto protocol_error; /* ignored */ virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, NULL, 0); } break; case 52: /* lock */ { uint32_t fid; FSFile *f; FSLock lock; if (unmarshall(s, queue_idx, desc_idx, &offset, "wbwddws", &fid, &lock.type, &lock.flags, &lock.start, &lock.length, &lock.proc_id, &lock.client_id)) goto protocol_error; f = fid_find(s, fid); if (!f) err = -P9_EPROTO; else err = fs->fs_lock(fs, f, &lock); free(lock.client_id); if (err < 0) goto error; buf_len = marshall(s, buf, sizeof(buf), "b", err); virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, buf, buf_len); } break; case 54: /* getlock */ { uint32_t fid; FSFile *f; FSLock lock; if (unmarshall(s, queue_idx, desc_idx, &offset, "wbddws", &fid, &lock.type, &lock.start, &lock.length, &lock.proc_id, &lock.client_id)) goto protocol_error; f = fid_find(s, fid); if (!f) err = -P9_EPROTO; else err = fs->fs_getlock(fs, f, &lock); if (err < 0) { free(lock.client_id); goto error; } buf_len = marshall(s, buf, sizeof(buf), "bddws", &lock.type, &lock.start, &lock.length, &lock.proc_id, &lock.client_id); free(lock.client_id); virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, buf, buf_len); } break; case 70: /* link */ { uint32_t dfid, fid; char *name; FSFile *f, *df; if (unmarshall(s, queue_idx, desc_idx, &offset, "wws", &dfid, &fid, &name)) goto protocol_error; df = fid_find(s, dfid); f = fid_find(s, fid); if (!df || !f) { err = -P9_EPROTO; } else { err = fs->fs_link(fs, df, f, name); } free(name); if (err) goto error; virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, NULL, 0); } break; case 72: /* mkdir */ { uint32_t fid, mode, gid; char *name; FSFile *f; FSQID qid; if (unmarshall(s, queue_idx, desc_idx, &offset, "wsww", &fid, &name, &mode, &gid)) goto protocol_error; f = fid_find(s, fid); if (!f) goto fid_not_found; err = fs->fs_mkdir(fs, &qid, f, name, mode, gid); if (err != 0) goto error; buf_len = marshall(s, buf, sizeof(buf), "Q", &qid); virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, buf, buf_len); } break; case 74: /* renameat */ { uint32_t fid, new_fid; char *name, *new_name; FSFile *f, *new_f; if (unmarshall(s, queue_idx, desc_idx, &offset, "wsws", &fid, &name, &new_fid, &new_name)) goto protocol_error; f = fid_find(s, fid); new_f = fid_find(s, new_fid); if (!f || !new_f) { err = -P9_EPROTO; } else { err = fs->fs_renameat(fs, f, name, new_f, new_name); } free(name); free(new_name); if (err != 0) goto error; virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, NULL, 0); } break; case 76: /* unlinkat */ { uint32_t fid, flags; char *name; FSFile *f; if (unmarshall(s, queue_idx, desc_idx, &offset, "wsw", &fid, &name, &flags)) goto protocol_error; f = fid_find(s, fid); if (!f) { err = -P9_EPROTO; } else { err = fs->fs_unlinkat(fs, f, name); } free(name); if (err != 0) goto error; virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, NULL, 0); } break; case 100: /* version */ { uint32_t msize; char *version; if (unmarshall(s, queue_idx, desc_idx, &offset, "ws", &msize, &version)) goto protocol_error; s->msize = msize; // printf("version: msize=%d version=%s\n", msize, version); free(version); buf_len = marshall(s, buf, sizeof(buf), "ws", s->msize, "9P2000.L"); virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, buf, buf_len); } break; case 104: /* attach */ { uint32_t fid, afid, uid; char *uname, *aname; FSQID qid; FSFile *f; if (unmarshall(s, queue_idx, desc_idx, &offset, "wwssw", &fid, &afid, &uname, &aname, &uid)) goto protocol_error; err = fs->fs_attach(fs, &f, &qid, uid, uname, aname); if (err != 0) goto error; fid_set(s, fid, f); free(uname); free(aname); buf_len = marshall(s, buf, sizeof(buf), "Q", &qid); virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, buf, buf_len); } break; case 108: /* flush */ { uint16_t oldtag; if (unmarshall(s, queue_idx, desc_idx, &offset, "h", &oldtag)) goto protocol_error; /* ignored */ virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, NULL, 0); } break; case 110: /* walk */ { uint32_t fid, newfid; uint16_t nwname; FSQID *qids; char **names; FSFile *f; int i; if (unmarshall(s, queue_idx, desc_idx, &offset, "wwh", &fid, &newfid, &nwname)) goto protocol_error; f = fid_find(s, fid); if (!f) goto fid_not_found; names = (char **)mallocz(sizeof(names[0]) * nwname); qids = (FSQID *)malloc(sizeof(qids[0]) * nwname); for (i = 0; i < nwname; i++) { if (unmarshall(s, queue_idx, desc_idx, &offset, "s", &names[i])) { err = -P9_EPROTO; goto walk_done; } } err = fs->fs_walk(fs, &f, qids, f, nwname, names); walk_done: for (i = 0; i < nwname; i++) { free(names[i]); } free(names); if (err < 0) { free(qids); goto error; } buf_len = marshall(s, buf, sizeof(buf), "h", err); for (i = 0; i < err; i++) { buf_len += marshall(s, buf + buf_len, sizeof(buf) - buf_len, "Q", &qids[i]); } free(qids); fid_set(s, newfid, f); virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, buf, buf_len); } break; case 116: /* read */ { uint32_t fid, count; uint64_t offs; uint8_t *buf; int n; FSFile *f; if (unmarshall(s, queue_idx, desc_idx, &offset, "wdw", &fid, &offs, &count)) goto protocol_error; f = fid_find(s, fid); if (!f) goto fid_not_found; buf = (uint8_t *)malloc(count + 4); n = fs->fs_read(fs, f, offs, buf + 4, count); if (n < 0) { err = n; free(buf); goto error; } put_le32(buf, n); virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, buf, n + 4); free(buf); } break; case 118: /* write */ { uint32_t fid, count; uint64_t offs; uint8_t *buf1; int n; FSFile *f; if (unmarshall(s, queue_idx, desc_idx, &offset, "wdw", &fid, &offs, &count)) goto protocol_error; f = fid_find(s, fid); if (!f) goto fid_not_found; buf1 = (uint8_t *)malloc(count); if (memcpy_from_queue(s1, buf1, queue_idx, desc_idx, offset, count)) { free(buf1); goto protocol_error; } n = fs->fs_write(fs, f, offs, buf1, count); free(buf1); if (n < 0) { err = n; goto error; } buf_len = marshall(s, buf, sizeof(buf), "w", n); virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, buf, buf_len); } break; case 120: /* clunk */ { uint32_t fid; if (unmarshall(s, queue_idx, desc_idx, &offset, "w", &fid)) goto protocol_error; fid_delete(s, fid); virtio_9p_send_reply(s, queue_idx, desc_idx, id, tag, NULL, 0); } break; default: printf("9p: unsupported operation id=%d\n", id); goto protocol_error; } return 0; error: virtio_9p_send_error(s, queue_idx, desc_idx, tag, err); return 0; protocol_error: fid_not_found: err = -P9_EPROTO; goto error; } VIRTIODevice *virtio_9p_init(VIRTIOBusDef *bus, FSDevice *fs, const char *mount_tag) { int len = strlen(mount_tag); VIRTIO9PDevice *s = (VIRTIO9PDevice *)mallocz(sizeof(*s)); virtio_init(&s->common, bus, 9, 2 + len, virtio_9p_recv_request); s->common.device_features = 1 << 0; /* set the mount tag */ uint8_t *cfg = s->common.config_space; cfg[0] = len; cfg[1] = len >> 8; memcpy(cfg + 2, mount_tag, len); s->fs = fs; s->msize = 8192; init_list_head(&s->fid_list); return (VIRTIODevice *)s; }
/* * VIRTIO driver * * Copyright (c) 2016 Fabrice Bellard * Copyright (C) 2018,2019, Esperanto Technologies Inc. * * Licensed under the Apache License, Version 2.0 (the "License") * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * THIS FILE IS BASED ON THE RISCVEMU SOURCE CODE WHICH IS DISTRIBUTED * UNDER THE FOLLOWING LICENSE: * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #ifndef VIRTIO_H #define VIRTIO_H #include "iomem.h" #include "pci.h" #include "cutils.h" #define VIRTIO_PAGE_SIZE 4096 #define VIRTIO_ADDR_BITS 64 typedef uint64_t virtio_phys_addr_t; typedef struct { /* PCI only: */ PCIBus *pci_bus; /* MMIO only: */ PhysMemoryMap *mem_map; uint64_t addr; IRQSignal *irq; } VIRTIOBusDef; typedef struct VIRTIODevice VIRTIODevice; #define VIRTIO_DEBUG_IO (1 << 0) #define VIRTIO_DEBUG_9P (1 << 1) void virtio_set_debug(VIRTIODevice *s, int debug_flags); /* block device */ typedef void BlockDeviceCompletionFunc(void *opaque, int ret); typedef struct BlockDevice BlockDevice; struct BlockDevice { int64_t (*get_sector_count)(BlockDevice *bs); int (*read_async)(BlockDevice *bs, uint64_t sector_num, uint8_t *buf, int n, BlockDeviceCompletionFunc *cb, void *opaque); int (*write_async)(BlockDevice *bs, uint64_t sector_num, const uint8_t *buf, int n, BlockDeviceCompletionFunc *cb, void *opaque); void *opaque; }; VIRTIODevice *virtio_block_init(VIRTIOBusDef *bus, BlockDevice *bs); /* network device */ typedef struct EthernetDevice EthernetDevice; struct EthernetDevice { uint8_t mac_addr[6]; /* mac address of the interface */ void (*write_packet)(EthernetDevice *net, const uint8_t *buf, int len); void *opaque; void (*select_fill)(EthernetDevice *net, int *pfd_max, fd_set *rfds, fd_set *wfds, fd_set *efds, int *pdelay); void (*select_poll)(EthernetDevice *net, fd_set *rfds, fd_set *wfds, fd_set *efds, int select_ret); /* the following is set by the device */ void *device_opaque; BOOL (*device_can_write_packet)(EthernetDevice *net); void (*device_write_packet)(EthernetDevice *net, const uint8_t *buf, int len); void (*device_set_carrier)(EthernetDevice *net, BOOL carrier_state); }; VIRTIODevice *virtio_net_init(VIRTIOBusDef *bus, EthernetDevice *es); /* console device */ typedef struct { void *opaque; void (*write_data)(void *opaque, const uint8_t *buf, int len); int (*read_data)(void *opaque, uint8_t *buf, int len); } CharacterDevice; VIRTIODevice *virtio_console_init(VIRTIOBusDef *bus, CharacterDevice *cs); BOOL virtio_console_can_write_data(VIRTIODevice *s); int virtio_console_get_write_len(VIRTIODevice *s); int virtio_console_write_data(VIRTIODevice *s, const uint8_t *buf, int buf_len); void virtio_console_resize_event(VIRTIODevice *s, int width, int height); /* input device */ typedef enum { VIRTIO_INPUT_TYPE_KEYBOARD, VIRTIO_INPUT_TYPE_MOUSE, VIRTIO_INPUT_TYPE_TABLET, } VirtioInputTypeEnum; #define VIRTIO_INPUT_ABS_SCALE 32768 int virtio_input_send_key_event(VIRTIODevice *s, BOOL is_down, uint16_t key_code); int virtio_input_send_mouse_event(VIRTIODevice *s, int dx, int dy, int dz, unsigned int buttons); VIRTIODevice *virtio_input_init(VIRTIOBusDef *bus, VirtioInputTypeEnum type); /* 9p filesystem device */ #include "fs.h" VIRTIODevice *virtio_9p_init(VIRTIOBusDef *bus, FSDevice *fs, const char *mount_tag); #endif /* VIRTIO_H */
build/ install/ *.gch autom4te.cache/ .*.swp *.o *.d .gdb_history
#========================================================================= # Local Autoconf Macros #========================================================================= # This file contains the macros for the Modular C++ Build System and # additional autoconf macros which developers can use in their # configure.ac scripts. Please read the documentation in # 'mcppbs-doc.txt' for more details on how the Modular C++ Build System # works. The documenation for each macro should include information # about the author, date, and copyright. #------------------------------------------------------------------------- # MCPPBS_PROG_INSTALL #------------------------------------------------------------------------- # This macro will add an --enable-stow command line option to the # configure script. When enabled, this macro will first check to see if # the stow program is available and if so it will set the $stow shell # variable to the binary name and the $enable_stow shell variable to # "yes". These variables can be used in a makefile to conditionally use # stow for installation. # # This macro uses two environment variables to help setup default stow # locations. The $STOW_PREFIX is used for stowing native built packages. # The packages are staged in $STOW_PREFIX/pkgs and then symlinks are # created from within $STOW_PREFIX into the pkgs subdirectory. If you # only do native builds then this is all you need to set. If you don't # set $STOW_PREFIX then the default is just the normal default prefix # which is almost always /usr/local. # # For non-native builds we probably want to install the packages in a # different location which includes the host architecture name as part # of the prefix. For these kind of builds, we can specify the $STOW_ROOT # environment variable and the effective prefix will be # $STOW_ROOT/${host_alias} where ${host_alias} is specified on the # configure command line with "--host". # # Here is an example setup: # # STOW_ROOT="$HOME/install" # STOW_ARCH="i386-macosx10.4" # STOW_PREFIX="${STOW_ROOT}/${STOW_ARCH}" # AC_DEFUN([MCPPBS_PROG_INSTALL], [ # Configure command line option AC_ARG_ENABLE(stow, AS_HELP_STRING(--enable-stow,[Enable stow-based install]), [enable_stow="yes"],[enable_stow="no"]) AC_SUBST([enable_stow]) # Environment variables AC_ARG_VAR([STOW_ROOT], [Root for non-native stow-based installs]) AC_ARG_VAR([STOW_PREFIX], [Prefix for stow-based installs]) # Check for install script AC_PROG_INSTALL # Deterimine if native build and set prefix appropriately AS_IF([ test ${enable_stow} = "yes" ], [ AC_CHECK_PROGS([stow],[stow],[no]) AS_IF([ test ${stow} = "no" ], [ AC_MSG_ERROR([Cannot use --enable-stow since stow is not available]) ]) # Check if native or non-native build AS_IF([ test "${build}" = "${host}" ], [ # build == host so this is a native build. Make sure --prefix not # set and $STOW_PREFIX is set, then set prefix=$STOW_PREFIX. AS_IF([ test "${prefix}" = "NONE" && test -n "${STOW_PREFIX}" ], [ prefix="${STOW_PREFIX}" AC_MSG_NOTICE([Using \$STOW_PREFIX from environment]) AC_MSG_NOTICE([prefix=${prefix}]) ]) ],[ # build != host so this is a non-native build. Make sure --prefix # not set and $STOW_ROOT is set, then set # prefix=$STOW_ROOT/${host_alias}. AS_IF([ test "${prefix}" = "NONE" && test -n "${STOW_ROOT}" ], [ prefix="${STOW_ROOT}/${host_alias}" AC_MSG_NOTICE([Using \$STOW_ROOT from environment]) AC_MSG_NOTICE([prefix=${prefix}]) ]) ]) ]) ]) #------------------------------------------------------------------------- # MCPPBS_PROG_RUN # ------------------------------------------------------------------------- # If we are doing a non-native build then we look for an isa simulator # to use for running tests. We set the RUN substitution variable to be # empty for native builds or to the name of the isa simulator for # non-native builds. Thus a makefile can run compiled programs # regardless if we are doing a native or non-native build like this: # # $(RUN) $(RUNFLAGS) ./test-program # AC_DEFUN([MCPPBS_PROG_RUN], [ AS_IF([ test "${build}" != "${host}" ], [ AC_CHECK_TOOLS([RUN],[isa-run run],[no]) AS_IF([ test ${RUN} = "no" ], [ AC_MSG_ERROR([Cannot find simulator for target ${target_alias}]) ]) ],[ RUN="" ]) AC_SUBST([RUN]) AC_SUBST([RUNFLAGS]) ]) #------------------------------------------------------------------------- # MCPPBS_SUBPROJECTS([ sproj1, sproj2, ... ]) #------------------------------------------------------------------------- # The developer should call this macro with a list of the subprojects # which make up this project. One should order the list such that any # given subproject only depends on subprojects listed before it. The # subproject names can also include an * suffix which indicates that # this is an optional subproject. Optional subprojects are only included # as part of the project build if enabled on the configure command line # with a --enable-<subproject> flag. The user can also specify that all # optional subprojects should be included in the build with the # --enable-optional-subprojects flag. # # Subproject names can also include a ** suffix which indicates that it # is an optional subproject, but there is a group with the same name. # Thus the --enable-<sproj> command line option will enable not just the # subproject sproj but all of the subprojects which are in the group. # There is no error checking to make sure that if you use the ** suffix # you actually define a group so be careful. # # Both required and optional subprojects should have a 'subproject.ac' # file. The script's filename should be the abbreivated subproject name # (assuming the subproject name is sproj then we would use 'sproj.ac') # The MCPPBS_SUBPROJECTS macro includes the 'subproject.ac' files for # enabled subprojects. Whitespace and newlines are allowed within the # list. # # Author : Christopher Batten # Date : September 10, 2008 AC_DEFUN([MCPPBS_SUBPROJECTS], [ # Add command line argument to enable all optional subprojects AC_ARG_ENABLE(optional-subprojects, AS_HELP_STRING([--enable-optional-subprojects], [Enable all optional subprojects])) # Loop through the subprojects given in the macro argument m4_foreach([MCPPBS_SPROJ],[$1], [ # Determine if this is a required or an optional subproject m4_define([MCPPBS_IS_REQ], m4_bmatch(MCPPBS_SPROJ,[\*+],[false],[true])) # Determine if there is a group with the same name m4_define([MCPPBS_IS_GROUP], m4_bmatch(MCPPBS_SPROJ,[\*\*],[true],[false])) # Create variations of the subproject name suitable for use as a CPP # enabled define, a shell enabled variable, and a shell function m4_define([MCPPBS_SPROJ_NORM], m4_normalize(m4_bpatsubsts(MCPPBS_SPROJ,[*],[]))) m4_define([MCPPBS_SPROJ_DEFINE], m4_toupper(m4_bpatsubst(MCPPBS_SPROJ_NORM[]_ENABLED,[-],[_]))) m4_define([MCPPBS_SPROJ_FUNC], m4_bpatsubst(_mpbp_[]MCPPBS_SPROJ_NORM[]_configure,[-],[_])) m4_define([MCPPBS_SPROJ_UNDERSCORES], m4_bpatsubsts(MCPPBS_SPROJ,[-],[_])) m4_define([MCPPBS_SPROJ_SHVAR], m4_bpatsubst(enable_[]MCPPBS_SPROJ_NORM[]_sproj,[-],[_])) # Add subproject to our running list subprojects="$subprojects MCPPBS_SPROJ_NORM" # Process the subproject appropriately. If enabled add it to the # $enabled_subprojects running shell variable, set a # SUBPROJECT_ENABLED C define, and include the appropriate # 'subproject.ac'. m4_if(MCPPBS_IS_REQ,[true], [ AC_MSG_NOTICE([configuring default subproject : MCPPBS_SPROJ_NORM]) AC_CONFIG_FILES(MCPPBS_SPROJ_NORM[].mk:MCPPBS_SPROJ_NORM[]/MCPPBS_SPROJ_NORM[].mk.in) MCPPBS_SPROJ_SHVAR="yes" subprojects_enabled="$subprojects_enabled MCPPBS_SPROJ_NORM" AC_DEFINE(MCPPBS_SPROJ_DEFINE,, [Define if subproject MCPPBS_SPROJ_NORM is enabled]) m4_include(MCPPBS_SPROJ_NORM[]/MCPPBS_SPROJ_NORM[].ac) ],[ # For optional subprojects we capture the 'subproject.ac' as a # shell function so that in the MCPPBS_GROUP macro we can just # call this shell function instead of reading in 'subproject.ac' # again. MCPPBS_SPROJ_FUNC () { AC_MSG_NOTICE([configuring optional subproject : MCPPBS_SPROJ_NORM]) AC_CONFIG_FILES(MCPPBS_SPROJ_NORM[].mk:MCPPBS_SPROJ_NORM[]/MCPPBS_SPROJ_NORM[].mk.in) MCPPBS_SPROJ_SHVAR="yes" subprojects_enabled="$subprojects_enabled MCPPBS_SPROJ_NORM" AC_DEFINE(MCPPBS_SPROJ_DEFINE,, [Define if subproject MCPPBS_SPROJ_NORM is enabled]) m4_include(MCPPBS_SPROJ_NORM[]/MCPPBS_SPROJ_NORM[].ac) }; # Optional subprojects add --enable-subproject command line # options, _if_ the subproject name is not also a group name. m4_if(MCPPBS_IS_GROUP,[false], [ AC_ARG_ENABLE(MCPPBS_SPROJ_NORM, AS_HELP_STRING(--enable-MCPPBS_SPROJ_NORM, [Subproject MCPPBS_SPROJ_NORM]), [MCPPBS_SPROJ_SHVAR="yes"],[MCPPBS_SPROJ_SHVAR="no"]) AS_IF([test "$MCPPBS_SPROJ_SHVAR" = "yes"], [ eval "MCPPBS_SPROJ_FUNC" ],[ AC_MSG_NOTICE([processing optional subproject : MCPPBS_SPROJ_NORM]) ]) ],[ # If the subproject name is also a group name then we need to # make sure that we set the shell variable for that subproject to # no so that the group code knows we haven't run it yet. AC_MSG_NOTICE([processing optional subproject : MCPPBS_SPROJ_NORM]) MCPPBS_SPROJ_SHVAR="no" ]) # Always execute the subproject configure code if we are enabling # all subprojects. AS_IF([ test "$enable_optional_subprojects" = "yes" \ && test "$MCPPBS_SPROJ_SHVAR" = "no" ], [ eval "MCPPBS_SPROJ_FUNC" ]) ]) ]) # Output make variables AC_SUBST([subprojects]) AC_SUBST([subprojects_enabled]) ]) #------------------------------------------------------------------------- # MCPPBS_GROUP( [group-name], [ sproj1, sproj2, ... ] ) #------------------------------------------------------------------------- # This macro creates a subproject group with the given group-name. When # a user specifies --enable-<group-name> the listed subprojects will be # enabled. Groups can have the same name as a subproject and in that # case whenever a user specifies --enable-<subproject> the subprojects # listed in the corresponding group will also be enabled. Groups are # useful for specifying related subprojects which are usually enabled # together, as well as for specifying that a specific optional # subproject has dependencies on other optional subprojects. # # Author : Christopher Batten # Date : September 10, 2008 AC_DEFUN([MCPPBS_GROUP], [ m4_define([MCPPBS_GROUP_NORM], m4_normalize([$1])) m4_define([MCPPBS_GROUP_SHVAR], m4_bpatsubst(enable_[]MCPPBS_GROUP_NORM[]_group,[-],[_])) AC_ARG_ENABLE(MCPPBS_GROUP_NORM, AS_HELP_STRING(--enable-MCPPBS_GROUP_NORM, [Group MCPPBS_GROUP_NORM: $2]), [MCPPBS_GROUP_SHVAR="yes"],[MCPPBS_GROUP_SHVAR="no"]) AS_IF([test "$MCPPBS_GROUP_SHVAR" = "yes" ], [ AC_MSG_NOTICE([configuring optional group : MCPPBS_GROUP_NORM]) ]) m4_foreach([MCPPBS_SPROJ],[$2], [ m4_define([MCPPBS_SPROJ_NORM], m4_normalize(MCPPBS_SPROJ)) m4_define([MCPPBS_SPROJ_SHVAR], m4_bpatsubst(enable_[]MCPPBS_SPROJ_NORM[]_sproj,[-],[_])) m4_define([MCPPBS_SPROJ_FUNC], m4_bpatsubst(_mpbp_[]MCPPBS_SPROJ_NORM[]_configure,[-],[_])) AS_IF([ test "$MCPPBS_GROUP_SHVAR" = "yes" \ && test "$MCPPBS_SPROJ_SHVAR" = "no" ], [ eval "MCPPBS_SPROJ_FUNC" ]) ]) ])
/* config.h.in. Generated from configure.ac by autoheader. */ /* Define if building universal (internal helper macro) */ #undef AC_APPLE_UNIVERSAL_BUILD /* Default value for --isa switch */ #undef DEFAULT_ISA /* Path to the device-tree-compiler */ #undef DTC /* Define if subproject MCPPBS_SPROJ_NORM is enabled */ #undef DUMMY_ROCC_ENABLED /* Define to 1 if you have the <inttypes.h> header file. */ #undef HAVE_INTTYPES_H /* Define to 1 if you have the `fesvr' library (-lfesvr). */ #undef HAVE_LIBFESVR /* Define to 1 if you have the `pthread' library (-lpthread). */ #undef HAVE_LIBPTHREAD /* Define to 1 if you have the <memory.h> header file. */ #undef HAVE_MEMORY_H /* Define to 1 if you have the <stdint.h> header file. */ #undef HAVE_STDINT_H /* Define to 1 if you have the <stdlib.h> header file. */ #undef HAVE_STDLIB_H /* Define to 1 if you have the <strings.h> header file. */ #undef HAVE_STRINGS_H /* Define to 1 if you have the <string.h> header file. */ #undef HAVE_STRING_H /* Define to 1 if you have the <sys/stat.h> header file. */ #undef HAVE_SYS_STAT_H /* Define to 1 if you have the <sys/types.h> header file. */ #undef HAVE_SYS_TYPES_H /* Define to 1 if you have the <unistd.h> header file. */ #undef HAVE_UNISTD_H /* Define to the address where bug reports for this package should be sent. */ #undef PACKAGE_BUGREPORT /* Define to the full name of this package. */ #undef PACKAGE_NAME /* Define to the full name and version of this package. */ #undef PACKAGE_STRING /* Define to the one symbol short name of this package. */ #undef PACKAGE_TARNAME /* Define to the home page for this package. */ #undef PACKAGE_URL /* Define to the version of this package. */ #undef PACKAGE_VERSION /* Define if subproject MCPPBS_SPROJ_NORM is enabled */ #undef RISCV_ENABLED /* Enable commit log generation */ #undef RISCV_ENABLE_COMMITLOG /* Enable hardware management of PTE accessed and dirty bits */ #undef RISCV_ENABLE_DIRTY /* Enable PC histogram generation */ #undef RISCV_ENABLE_HISTOGRAM /* Enable hardware support for misaligned loads and stores */ #undef RISCV_ENABLE_MISALIGNED /* Define if subproject MCPPBS_SPROJ_NORM is enabled */ #undef SOFTFLOAT_ENABLED /* Define if subproject MCPPBS_SPROJ_NORM is enabled */ #undef SPIKE_MAIN_ENABLED /* Define to 1 if you have the ANSI C header files. */ #undef STDC_HEADERS /* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most significant byte first (like Motorola and SPARC, unlike Intel). */ #if defined AC_APPLE_UNIVERSAL_BUILD # if defined __BIG_ENDIAN__ # define WORDS_BIGENDIAN 1 # endif #else # ifndef WORDS_BIGENDIAN # undef WORDS_BIGENDIAN # endif #endif
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#========================================================================= # Toplevel configure.ac for the Modular C++ Build System #========================================================================= # Please read the documenation in 'mcppbs-doc.txt' for more details on # how the Modular C++ Build System works. For most new projects, a # developer will only need to make the following changes: # # - change the project metadata listed right below # - update the list of subprojects via the 'MCPPBS_SUBPROJECTS' macro # - possibly add subproject groups if needed to ease configuration # - add more configure checks for platform specific configuration # #------------------------------------------------------------------------- # Project metadata #------------------------------------------------------------------------- m4_define( proj_name, [RISC-V ISA Simulator]) m4_define( proj_maintainer, [Andrew Waterman]) m4_define( proj_abbreviation, [spike]) #------------------------------------------------------------------------- # Project version information #------------------------------------------------------------------------- # Version information is meant to be managed through a version control # system's tags and revision numbers. In a working copy the version will # not be defined here (you should just use the version control system's # mechanisms). When we make a distribution then we can set the version # here as formed by the scripts/vcs-version.sh script so that the # distribution knows what version it came from. If you are not using # version control then it is fine to set this directly. m4_define( proj_version, [?]) #------------------------------------------------------------------------- # Setup #------------------------------------------------------------------------- AC_INIT(proj_name,proj_version,proj_maintainer,proj_abbreviation) AC_LANG_CPLUSPLUS AC_CONFIG_SRCDIR([riscv/common.h]) AC_CONFIG_AUX_DIR([scripts]) AC_CANONICAL_BUILD AC_CANONICAL_HOST #------------------------------------------------------------------------- # Checks for programs #------------------------------------------------------------------------- AC_PROG_CC AC_PROG_CXX AC_CHECK_TOOL([AR],[ar]) AC_CHECK_TOOL([RANLIB],[ranlib]) AC_PATH_PROG([DTC],[dtc],[no]) AS_IF([test x"$DTC" == xno],AC_MSG_ERROR([device-tree-compiler not found])) AC_DEFINE_UNQUOTED(DTC, ["$DTC"], [Path to the device-tree-compiler]) AC_C_BIGENDIAN(AC_MSG_ERROR([Spike requires a little-endian host])) #------------------------------------------------------------------------- # MCPPBS specific program checks #------------------------------------------------------------------------- # These macros check to see if we can do a stow-based install and also # check for an isa simulator suitable for running the unit test programs # via the makefile. MCPPBS_PROG_INSTALL #------------------------------------------------------------------------- # Checks for header files #------------------------------------------------------------------------- AC_HEADER_STDC #------------------------------------------------------------------------- # Default compiler flags #------------------------------------------------------------------------- AC_SUBST([CFLAGS], ["-Wall -Wno-unused -g -O2"]) AC_SUBST([CXXFLAGS],["-Wall -Wno-unused -g -O2 -std=c++11"]) #------------------------------------------------------------------------- # MCPPBS subproject list #------------------------------------------------------------------------- # Order list so that subprojects only depend on those listed earlier. # The '*' suffix indicates an optional subproject. The '**' suffix # indicates an optional subproject which is also the name of a group. MCPPBS_SUBPROJECTS([ riscv, dummy_rocc, softfloat, spike_main ]) #------------------------------------------------------------------------- # MCPPBS subproject groups #------------------------------------------------------------------------- # If a group has the same name as a subproject then you must add the # '**' suffix in the subproject list above. The list of subprojects in a # group should be ordered so that subprojets only depend on those listed # earlier. Here is an example: # # MCPPBS_GROUP( [group-name], [sproja,sprojb,...] ) # #------------------------------------------------------------------------- # Output #------------------------------------------------------------------------- AC_CONFIG_HEADERS([config.h]) AC_CONFIG_FILES([Makefile]) AC_CONFIG_FILES([riscv-spike.pc]) AC_CONFIG_FILES([riscv-riscv.pc]) AC_CONFIG_FILES([riscv-softfloat.pc]) AC_CONFIG_FILES([riscv-dummy_rocc.pc]) AC_CONFIG_FILES([riscv-spike_main.pc]) AC_OUTPUT
Copyright (c) 2010-2017, The Regents of the University of California (Regents). All Rights Reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of the Regents nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
#========================================================================= # Toplevel Makefile for the Modular C++ Build System #========================================================================= # Please read the documenation in 'mcppbs-doc.txt' for more details on # how the Modular C++ Build System works. For most projects, a developer # will not need to make any changes to this makefile. The key targets # are as follows: # # - default : build all libraries and programs # - check : build and run all unit tests # - install : install headers, project library, and some programs # - clean : remove all generated content (except autoconf files) # - dist : make a source tarball # - distcheck : make a source tarball, untar it, check it, clean it # - distclean : remove everything # #------------------------------------------------------------------------- # Basic setup #------------------------------------------------------------------------- # Remove all default implicit rules since they can cause subtle bugs # and they just make things run slower .SUFFIXES: % : %,v % : RCS/%,v % : RCS/% % : s.% % : SCCS/s.% # Default is to build the prereqs of the all target (defined at bottom) default : all .PHONY : default project_name := @PACKAGE_TARNAME@ src_dir := @srcdir@ scripts_dir := $(src_dir)/scripts # If the version information is not in the configure script, then we # assume that we are in a working directory. We use the vcs-version.sh # script in the scripts directory to generate an appropriate version # string. Currently the way things are setup we have to run this script # everytime we run make so the script needs to be as fast as possible. ifeq (@PACKAGE_VERSION@,?) project_ver:=$(shell $(scripts_dir)/vcs-version.sh $(src_dir)) else project_ver:=@PACKAGE_VERSION@ endif # Installation directories prefix := @prefix@ enable_stow := @enable_stow@ ifeq ($(enable_stow),yes) stow_pkg_dir := $(prefix)/pkgs INSTALLDIR ?= $(DESTDIR)$(stow_pkg_dir)/$(project_name)-$(project_ver) else INSTALLDIR ?= $(DESTDIR)$(prefix) endif install_hdrs_dir := $(INSTALLDIR)/include/$(project_name) install_libs_dir := $(INSTALLDIR)/lib install_exes_dir := $(INSTALLDIR)/bin #------------------------------------------------------------------------- # List of subprojects #------------------------------------------------------------------------- sprojs := @subprojects@ sprojs_enabled := @subprojects_enabled@ sprojs_include := -I. -I$(src_dir) $(addprefix -I$(src_dir)/, $(sprojs_enabled)) VPATH := $(addprefix $(src_dir)/, $(sprojs_enabled)) #------------------------------------------------------------------------- # Programs and flags #------------------------------------------------------------------------- # C++ compiler # - CPPFLAGS : flags for the preprocessor (eg. -I,-D) # - CXXFLAGS : flags for C++ compiler (eg. -Wall,-g,-O3) CC := @CC@ CXX := @CXX@ CFLAGS += @CFLAGS@ -DPREFIX=\"$(prefix)\" CPPFLAGS += @CPPFLAGS@ CXXFLAGS += @CXXFLAGS@ -DPREFIX=\"$(prefix)\" COMPILE := $(CXX) -fPIC -MMD -MP $(CPPFLAGS) $(CXXFLAGS) \ $(sprojs_include) COMPILE_C := $(CC) -fPIC -MMD -MP $(CPPFLAGS) $(CFLAGS) \ $(sprojs_include) # Linker # - LDFLAGS : Flags for the linker (eg. -L) # - LIBS : Library flags (eg. -l) comma := , LD := $(CXX) LDFLAGS := @LDFLAGS@ LIBS := @LIBS@ LINK := $(LD) -L. $(LDFLAGS) -Wl,-rpath,$(install_libs_dir) $(patsubst -L%,-Wl$(comma)-rpath$(comma)%,$(filter -L%,$(LDFLAGS))) # Library creation AR := @AR@ RANLIB := @RANLIB@ # Host simulator RUN := @RUN@ RUNFLAGS := @RUNFLAGS@ # Installation MKINSTALLDIRS := $(scripts_dir)/mk-install-dirs.sh INSTALL := @INSTALL@ INSTALL_HDR := $(INSTALL) -m 444 INSTALL_LIB := $(INSTALL) -m 644 INSTALL_EXE := $(INSTALL) -m 555 STOW := @stow@ # Tests bintests = $(src_dir)/tests/ebreak.py #------------------------------------------------------------------------- # Include subproject makefile fragments #------------------------------------------------------------------------- sprojs_mk = $(addsuffix .mk, $(sprojs_enabled)) -include $(sprojs_mk) dist_junk += $(sprojs_mk) #------------------------------------------------------------------------- # Reverse list helper function #------------------------------------------------------------------------- # This function is used by the subproject template to reverse the list # of dependencies. It uses recursion to perform the reversal. # # Arguments: # $(1) : space separated input list # retval : input list in reverse order # reverse_list = $(call reverse_list_h,$(1),) define reverse_list_h $(if $(strip $(1)), \ $(call reverse_list_h, \ $(wordlist 2,$(words $(1)),$(1)), \ $(firstword $(1)) $(2)), \ $(2)) endef #------------------------------------------------------------------------- # Template for per subproject rules #------------------------------------------------------------------------- # The template is instantiated for each of the subprojects. It relies on # subprojects defining a certain set of make variables which are all # prefixed with the subproject name. Since subproject names can have # dashes in them (and the make variables are assumed to only use # underscores) the template takes two arguments - one with the regular # subproject name and one with dashes replaced with underscores. # # Arguments: # $(1) : real subproject name (ie with dashes) # $(2) : normalized subproject name (ie dashes replaced with underscores) # define subproject_template # In some (rare) cases, a subproject might not have any actual object # files. It might only include header files or program sources. To keep # things consistent we still want a library for this subproject, so in # this spectial case we create a dummy source file and thus the build # system will create a library for this subproject with just the # corresponding dummy object file. ifeq ($$(strip $$($(2)_srcs) $$($(2)_c_srcs)),) $(2)_srcs += _$(1).cc $(2)_junk += _$(1).cc endif _$(1).cc : echo "int _$(2)( int arg ) { return arg; }" > $$@ # Build the object files for this subproject $(2)_pch := $$(patsubst %.h, %.h.gch, $$($(2)_precompiled_hdrs)) $(2)_objs := $$(patsubst %.cc, %.o, $$($(2)_srcs)) $(2)_c_objs := $$(patsubst %.c, %.o, $$($(2)_c_srcs)) $(2)_deps := $$(patsubst %.o, %.d, $$($(2)_objs)) $(2)_deps += $$(patsubst %.o, %.d, $$($(2)_c_objs)) $(2)_deps += $$(patsubst %.h, %.h.d, $$($(2)_precompiled_hdrs)) $$($(2)_pch) : %.h.gch : %.h $(COMPILE) -x c++-header $$< -o $$@ # If using clang, don't depend (and thus don't build) precompiled headers $$($(2)_objs) : %.o : %.cc $$($(2)_gen_hdrs) $(if $(filter-out clang,$(CC)),$$($(2)_pch)) $(COMPILE) -c $$< $$($(2)_c_objs) : %.o : %.c $$($(2)_gen_hdrs) $(COMPILE_C) -c $$< $(2)_junk += $$($(2)_pch) $$($(2)_objs) $$($(2)_c_objs) $$($(2)_deps) \ $$($(2)_gen_hdrs) # Reverse the dependency list so that a given subproject only depends on # subprojects listed to its right. This is the correct order for linking # the list of subproject libraries. $(2)_reverse_deps := $$(call reverse_list,$$($(2)_subproject_deps)) # Build a library for this subproject $(2)_lib_libs := $$($(2)_reverse_deps) $(2)_lib_libnames := $$(patsubst %, lib%.so, $$($(2)_lib_libs)) $(2)_lib_libarg := $$(patsubst %, -l%, $$($(2)_lib_libs)) lib$(1).so : $$($(2)_objs) $$($(2)_c_objs) $$($(2)_lib_libnames) $(LINK) -shared -o $$@ $(if $(filter Darwin,$(shell uname -s)),-install_name $(install_libs_dir)/$$@) $$^ $$($(2)_lib_libarg) $(LIBS) $(2)_junk += lib$(1).so # Build unit tests $(2)_test_objs := $$(patsubst %.cc, %.o, $$($(2)_test_srcs)) $(2)_test_deps := $$(patsubst %.o, %.d, $$($(2)_test_objs)) $(2)_test_exes := $$(patsubst %.t.cc, %-utst, $$($(2)_test_srcs)) $(2)_test_outs := $$(patsubst %, %.out, $$($(2)_test_exes)) $(2)_test_libs := $(1) $$($(2)_reverse_deps) utst $(2)_test_libnames := $$(patsubst %, lib%.so, $$($(2)_test_libs)) $(2)_test_libarg := $$(patsubst %, -l%, $$($(2)_test_libs)) $$($(2)_test_objs) : %.o : %.cc $(COMPILE) -c $$< $$($(2)_test_exes) : %-utst : %.t.o $$($(2)_test_libnames) $(LINK) -o $$@ $$< $$($(2)_test_libarg) $(LIBS) $(2)_deps += $$($(2)_test_deps) $(2)_junk += \ $$($(2)_test_objs) $$($(2)_test_deps) \ $$($(2)_test_exes) *.junk-dat # Run unit tests $$($(2)_test_outs) : %.out : % $(RUN) $(RUNFLAGS) ./$$< default | tee $$@ $(2)_junk += $$($(2)_test_outs) # Build programs $(2)_prog_objs := $$(patsubst %.cc, %.o, $$($(2)_prog_srcs)) $(2)_prog_deps := $$(patsubst %.o, %.d, $$($(2)_prog_objs)) $(2)_prog_exes := $$(patsubst %.cc, %, $$($(2)_prog_srcs)) $(2)_prog_libs := $(1) $$($(2)_reverse_deps) $(2)_prog_libnames := $$(patsubst %, lib%.so, $$($(2)_prog_libs)) $(2)_prog_libarg := $$(patsubst %, -l%, $$($(2)_prog_libs)) $$($(2)_prog_objs) : %.o : %.cc $(COMPILE) -c $$< $$($(2)_prog_exes) : % : %.o $$($(2)_prog_libnames) $(LINK) -o $$@ $$< $$($(2)_prog_libarg) $(LIBS) $(2)_deps += $$($(2)_prog_deps) $(2)_junk += $$($(2)_prog_objs) $$($(2)_prog_deps) $$($(2)_prog_exes) # Build programs which will be installed $(2)_install_prog_objs := $$(patsubst %.cc, %.o, $$($(2)_install_prog_srcs)) $(2)_install_prog_deps := $$(patsubst %.o, %.d, $$($(2)_install_prog_objs)) $(2)_install_prog_exes := $$(patsubst %.cc, %, $$($(2)_install_prog_srcs)) $$($(2)_install_prog_objs) : %.o : %.cc $$($(2)_gen_hdrs) $(COMPILE) -c $$< $$($(2)_install_prog_exes) : % : %.o $$($(2)_prog_libnames) $(LINK) -o $$@ $$< $$($(2)_prog_libarg) $(LIBS) $(2)_deps += $$($(2)_install_prog_deps) $(2)_junk += \ $$($(2)_install_prog_objs) $$($(2)_install_prog_deps) \ $$($(2)_install_prog_exes) # Subproject specific targets all-$(1) : lib$(1).so $$($(2)_install_prog_exes) check-$(1) : $$($(2)_test_outs) echo; grep -h -e'Unit Tests' -e'FAILED' -e'Segementation' $$^; echo clean-$(1) : rm -rf $$($(2)_junk) .PHONY : all-$(1) check-$(1) clean-$(1) # Update running variables libs += lib$(1).so objs += $$($(2)_objs) srcs += $$(addprefix $(src_dir)/$(1)/, $$($(2)_srcs)) hdrs += $$(addprefix $(src_dir)/$(1)/, $$($(2)_hdrs)) $$($(2)_gen_hdrs) junk += $$($(2)_junk) deps += $$($(2)_deps) test_outs += $$($(2)_test_outs) install_hdrs += $$(addprefix $(src_dir)/$(1)/, $$($(2)_hdrs)) $$($(2)_gen_hdrs) install_libs += lib$(1).so install_exes += $$($(2)_install_prog_exes) install_pcs += riscv-$(1).pc endef # Iterate over the subprojects and call the template for each one $(foreach sproj,$(sprojs_enabled), \ $(eval $(call subproject_template,$(sproj),$(subst -,_,$(sproj))))) #------------------------------------------------------------------------- # Autodependency files #------------------------------------------------------------------------- -include $(deps) deps : $(deps) .PHONY : deps #------------------------------------------------------------------------- # Check #------------------------------------------------------------------------- bintest_outs = $(bintests:=.out) junk += $(bintest_outs) %.out: % all ./$* < /dev/null 2>&1 | tee $@ check-cpp : $(test_outs) @echo ! grep -h -e'Unit Tests' -e'FAILED' -e'Segmentation' $^ < /dev/null @echo check-bin : $(bintest_outs) ! tail -n 1 $^ < /dev/null 2>&1 | grep FAILED check : check-cpp check-bin .PHONY : check #------------------------------------------------------------------------- # Installation #------------------------------------------------------------------------- install-hdrs : $(install_hdrs) config.h $(MKINSTALLDIRS) $(install_hdrs_dir) for file in $^; \ do \ $(INSTALL_HDR) $$file $(install_hdrs_dir); \ done install-libs : $(install_libs) $(MKINSTALLDIRS) $(install_libs_dir) for file in $^; \ do \ $(INSTALL_LIB) $$file $(install_libs_dir); \ done install-exes : $(install_exes) $(MKINSTALLDIRS) $(install_exes_dir) for file in $^; \ do \ $(INSTALL_EXE) $$file $(install_exes_dir); \ done install-pc : $(install_pcs) $(MKINSTALLDIRS) $(install_libs_dir)/pkgconfig/ for file in $^; \ do \ $(INSTALL_HDR) $$file $(install_libs_dir)/pkgconfig/; \ done install : install-hdrs install-libs install-exes install-pc ifeq ($(enable_stow),yes) $(MKINSTALLDIRS) $(stow_pkg_dir) cd $(stow_pkg_dir) && \ $(STOW) --delete $(project_name)-* && \ $(STOW) $(project_name)-$(project_ver) endif .PHONY : install install-hdrs install-libs install-exes #------------------------------------------------------------------------- # Regenerate configure information #------------------------------------------------------------------------- config.status : $(src_dir)/configure ./config.status --recheck sprojs_mk_in = \ $(join $(addprefix $(src_dir)/, $(sprojs_enabled)), \ $(patsubst %, /%.mk.in, $(sprojs_enabled))) Makefile : $(src_dir)/Makefile.in $(sprojs_mk_in) config.status ./config.status dist_junk += config.status config.h Makefile config.log #------------------------------------------------------------------------- # Distribution #------------------------------------------------------------------------- # The distribution tarball is named project-ver.tar.gz and it includes # both enabled and disabled subprojects. dist_files = \ $(sprojs) \ README \ style-guide.txt \ mcppbs-uguide.txt \ scripts \ configure.ac \ aclocal.m4 \ configure \ config.h.in \ Makefile.in \ dist_dir := $(project_name)-$(project_ver) dist_tgz := $(project_name)-$(project_ver).tar.gz # Notice that when we make the distribution we rewrite the configure.ac # script with the current version and we rerun autoconf in the new # source directory so that the distribution will have the proper version # information. We also rewrite the "Version : " line in the README. dist : rm -rf $(dist_dir) mkdir $(dist_dir) tar -C $(src_dir) -cf - $(dist_files) | tar -C $(dist_dir) -xpf - sed -i.bak 's/^\(# Version :\).*/\1 $(project_ver)/' $(dist_dir)/README sed -i.bak 's/\( proj_version,\).*/\1 [$(project_ver)])/' $(dist_dir)/configure.ac cd $(dist_dir) && \ autoconf && autoheader && \ rm -rf autom4te.cache configure.ac.bak README.bak tar -czvf $(dist_tgz) $(dist_dir) rm -rf $(dist_dir) # You can use the distcheck target to try untarring the distribution and # then running configure, make, make check, and make distclean. A # "directory is not empty" error means distclean is not removing # everything. distcheck : dist rm -rf $(dist_dir) tar -xzvf $(dist_tgz) mkdir -p $(dist_dir)/build cd $(dist_dir)/build; ../configure; make; make check; make distclean rm -rf $(dist_dir) junk += $(project_name)-*.tar.gz .PHONY : dist distcheck #------------------------------------------------------------------------- # Default #------------------------------------------------------------------------- all : $(install_hdrs) $(install_libs) $(install_exes) .PHONY : all #------------------------------------------------------------------------- # Makefile debugging #------------------------------------------------------------------------- # This handy rule will display the contents of any make variable by # using the target debug-<varname>. So for example, make debug-junk will # display the contents of the junk variable. debug-% : @echo $* = $($*) #------------------------------------------------------------------------- # Clean up junk #------------------------------------------------------------------------- clean : rm -rf *~ \#* $(junk) distclean : rm -rf *~ \#* $(junk) $(dist_junk) .PHONY : clean distclean
Spike RISC-V ISA Simulator ============================ About ------------- Spike, the RISC-V ISA Simulator, implements a functional model of one or more RISC-V processors. Spike is named after the golden spike used to celebrate the completion of the US transcontinental railway. Build Steps --------------- We assume that the RISCV environment variable is set to the RISC-V tools install path, and that the riscv-fesvr package is installed there. $ apt-get install device-tree-compiler $ mkdir build $ cd build $ ../configure --prefix=$RISCV --with-fesvr=$RISCV $ make $ [sudo] make install Compiling and Running a Simple C Program ------------------------------------------- Install spike (see Build Steps), riscv-gnu-toolchain, and riscv-pk. Write a short C program and name it hello.c. Then, compile it into a RISC-V ELF binary named hello: $ riscv64-unknown-elf-gcc -o hello hello.c Now you can simulate the program atop the proxy kernel: $ spike pk hello Simulating a New Instruction ------------------------------------ Adding an instruction to the simulator requires two steps: 1. Describe the instruction's functional behavior in the file riscv/insns/<new_instruction_name>.h. Examine other instructions in that directory as a starting point. 2. Add the opcode and opcode mask to riscv/opcodes.h. Alternatively, add it to the riscv-opcodes package, and it will do so for you: $ cd ../riscv-opcodes $ vi opcodes // add a line for the new instruction $ make install 3. Rebuild the simulator. Interactive Debug Mode --------------------------- To invoke interactive debug mode, launch spike with -d: $ spike -d pk hello To see the contents of an integer register (0 is for core 0): : reg 0 a0 To see the contents of a floating point register: : fregs 0 ft0 or: : fregd 0 ft0 depending upon whether you wish to print the register as single- or double-precision. To see the contents of a memory location (physical address in hex): : mem 2020 To see the contents of memory with a virtual address (0 for core 0): : mem 0 2020 You can advance by one instruction by pressing <enter>. You can also execute until a desired equality is reached: : until pc 0 2020 (stop when pc=2020) : until mem 2020 50a9907311096993 (stop when mem[2020]=50a9907311096993) Alternatively, you can execute as long as an equality is true: : while mem 2020 50a9907311096993 You can continue execution indefinitely by: : r At any point during execution (even without -d), you can enter the interactive debug mode with `<control>-<c>`. To end the simulation from the debug prompt, press `<control>-<c>` or: : q Debugging With Gdb ------------------ An alternative to interactive debug mode is to attach using gdb. Because spike tries to be like real hardware, you also need OpenOCD to do that. OpenOCD doesn't currently know about address translation, so it's not possible to easily debug programs that are run under `pk`. We'll use the following test program: ``` $ cat rot13.c char text[] = "Vafgehpgvba frgf jnag gb or serr!"; // Don't use the stack, because sp isn't set up. volatile int wait = 1; int main() { while (wait) ; // Doesn't actually go on the stack, because there are lots of GPRs. int i = 0; while (text[i]) { char lower = text[i] | 32; if (lower >= 'a' && lower <= 'm') text[i] += 13; else if (lower > 'm' && lower <= 'z') text[i] -= 13; i++; } while (!wait) ; } $ cat spike.lds OUTPUT_ARCH( "riscv" ) SECTIONS { . = 0x10010000; .text : { *(.text) } .data : { *(.data) } } $ riscv64-unknown-elf-gcc -g -Og -o rot13-64.o -c rot13.c $ riscv64-unknown-elf-gcc -g -Og -T spike.lds -nostartfiles -o rot13-64 rot13-64.o ``` To debug this program, first run spike telling it to listen for OpenOCD: ``` $ spike --rbb-port=9824 -m0x10000000:0x20000 rot13-64 Listening for remote bitbang connection on port 9824. ``` In a separate shell run OpenOCD with the appropriate configuration file: ``` $ cat spike.cfg interface remote_bitbang remote_bitbang_host localhost remote_bitbang_port 9824 set _CHIPNAME riscv jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913 set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME riscv -chain-position $_TARGETNAME gdb_report_data_abort enable init halt $ openocd -f spike.cfg Open On-Chip Debugger 0.10.0-dev-00002-gc3b344d (2017-06-08-12:14) ... riscv.cpu: target state: halted ``` In yet another shell, start your gdb debug session: ``` tnewsome@compy-vm:~/SiFive/spike-test$ riscv64-unknown-elf-gdb rot13-64 GNU gdb (GDB) 7.12.50.20170505-git Copyright (C) 2016 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "--host=x86_64-pc-linux-gnu --target=riscv64-unknown-elf". Type "show configuration" for configuration details. For bug reporting instructions, please see: <http://www.gnu.org/software/gdb/bugs/>. Find the GDB manual and other documentation resources online at: <http://www.gnu.org/software/gdb/documentation/>. For help, type "help". Type "apropos word" to search for commands related to "word"... Reading symbols from rot13-64...done. (gdb) target remote localhost:3333 Remote debugging using localhost:3333 0x000000001001000a in main () at rot13.c:8 8 while (wait) (gdb) print wait $1 = 1 (gdb) print wait=0 $2 = 0 (gdb) print text $3 = "Vafgehpgvba frgf jnag gb or serr!" (gdb) b 23 Breakpoint 1 at 0x10010064: file rot13.c, line 23. (gdb) c Continuing. Breakpoint 1, main () at rot13.c:23 23 while (!wait) (gdb) print wait $4 = 0 (gdb) print text ... ```
prefix=@prefix@ exec_prefix=@prefix@ libdir=${prefix}/@libdir@ includedir=${prefix}/@includedir@ Name: riscv-dummy_rocc Description: Example RISC-V ROCC accelerator Version: git Libs: -Wl,-rpath,${libdir} -L${libdir} -ldummy_rocc Cflags: -I${includedir} URL: http://riscv.org/download.html#tab_spike
prefix=@prefix@ exec_prefix=@prefix@ libdir=${prefix}/@libdir@ includedir=${prefix}/@includedir@ Name: riscv-riscv Description: RISC-V Version: git Libs: -Wl,-rpath,${libdir} -L${libdir} -lriscv Cflags: -I${includedir} URL: http://riscv.org/download.html#tab_spike
prefix=@prefix@ exec_prefix=@prefix@ libdir=${prefix}/@libdir@ includedir=${prefix}/@includedir@ Name: riscv-softfloat Description: RISC-V softfloat library Version: git Libs: -Wl,-rpath,${libdir} -L${libdir} -lsoftfloat Cflags: -I${includedir} URL: http://riscv.org/download.html#tab_spike
prefix=@prefix@ exec_prefix=@prefix@ libdir=${prefix}/@libdir@ includedir=${prefix}/@includedir@ Name: riscv-spike Description: RISC-V spike meta library Version: git Depends: riscv-spike_main riscv-riscv riscv-softfloat URL: http://riscv.org/download.html#tab_spike