vlsi-moe-yarn

A domain-specialized language model for VLSI and chip design reasoning. Built on a custom Qwen-based architecture where 10% of FFN layers are replaced with reasoning-optimized feed-forward blocks, extended to 262,144 tokens via YaRN, and trained through knowledge distillation on a VLSI-domain corpus. Served on AMD Instinct MI300X using ROCm and vLLM.

Model Details

Model Description

vlsi-moe-yarn is a chip-design AI assistant that can reason over RTL code, architecture documents, timing constraints, and full datasheets in a single 262K-token context window. It was created by replacing 10% of the standard Qwen FFN layers with reasoning-specialized feed-forward blocks, then knowledge-distilling from a larger teacher model on hardware design data.

• Developed by: Vicky (Vickyrrrrrr)
• Model type: Causal Language Model — Qwen-based with reasoning FFN substitution + YaRN
• Language(s): English (technical/domain: VLSI, EDA, RTL, chip architecture)
• License: MIT
• Finetuned from model: Qwen (base architecture)

Model Usage In :

• Repository: https://github.com/Vickyrrrrrr/AgentIC

Uses

Direct Use

Use this model directly as a chip design assistant via the vLLM OpenAI-compatible API. Ask it architecture questions, paste RTL for review, query SDC constraints, or load an entire datasheet into context and interrogate it — no fine-tuning needed.

Downstream Use

• Plug into agentic frameworks (LangChain, LlamaIndex, AutoGen , CrewAI) as the reasoning backbone
• Embed in EDA tool pipelines for automated RTL review or constraint generation
• Power internal VLSI copilot tools at chip design companies or research labs

Out-of-Scope Use

• General-purpose conversation or creative writing
• Medical, legal, or financial advice
• Any domain outside hardware design, RTL, and chip architecture

Bias, Risks, and Limitations

• The model's knowledge is bounded by its VLSI distillation corpus — it may lack awareness of very recent process nodes, proprietary EDA tool specifics, or niche IP.
• It can hallucinate plausible-sounding but incorrect timing numbers, constraints, or RTL constructs. Always verify outputs against your