Exposing the Robustness and Vulnerability of Hybrid 8T-6T SRAM Memory Architectures to Adversarial Attacks in Deep Neural Networks

Deep Learning is able to solve a plethora of once impossible problems. However, they are vulnerable to input adversarial attacks preventing them from being autonomously deployed in critical applications. Several algorithm-centered works have discussed methods to cause adversarial attacks and improve adversarial robustness of a Deep Neural Network (DNN). In this work, we elicit the advantages and vulnerabilities of hybrid 6T-8T memories to improve the adversarial robustness and cause adversarial attacks on DNNs. We show that bit-error noise in hybrid memories due to erroneous 6T-SRAM cells have deterministic behaviour based on the hybrid memory configurations ($V_{DD}$, 8T-6T ratio). This controlled noise (surgical noise) can be strategically introduced into specific DNN layers to improve the adversarial accuracy of DNNs. At the same time, surgical noise can be carefully injected into the DNN parameters stored in hybrid memory to cause adversarial attacks. To improve the adversarial robustness of DNNs using surgical noise, we propose a methodology to select appropriate DNN layers and their corresponding hybrid memory configurations to introduce the required surgical noise. Using this, we achieve 2-8% higher adversarial accuracy without re-training against white-box attacks like FGSM, than the baseline models (with no surgical noise introduced). To demonstrate adversarial attacks using surgical noise, we design a novel, white-box attack on DNN parameters stored in hybrid memory banks that causes the DNN inference accuracy to drop by more than 60% with over 90% confidence value. We support our claims with experiments, performed using benchmark datasets-CIFAR10 and CIFAR100 on VGG19 and ResNet18 networks.

DNN accelerators, Adversarial robustness, Adversarial Attacks, Hybrid CMOS memories, Supply Voltage Scaling.

Introduction
============

Learning has conquered a significant portion of modern day artificial intelligence applications. However, recent works show that they can be easily fooled by making very minimal changes on the input data @szegedy2013intriguing. What's far worse is that, these minimal changes are invisible to the naked eye. The result is that, the network makes a wrong prediction with a very high confidence. Such failure can prove to be catastrophic for critical applications like medical diagnostics, autonomous driving and stock markets. Hence, the deployment of Deep Neural Networks (DNNs) in real-time applications can be hindered due to the security risks of adversarial attacks.

Since the advent of this problem, there have been extensive works in literature focused on improving the adversarial robustness of DNNs. One of the most promising solution is adversarial training which achieves state-of-the-art results @goodfellow2014explaining [@madry2017towards]. Here, the network is trained on adversarial inputs in order to improve the model's robustness. Other works have tried to mitigate the effects of adversarial attacks through image compression @dziugaite2016study, random input resizing and randomization @xie2017adversarial [@xie2017mitigating], and random gaussian noise augmentation during training @he2019parametric. Naveed et al. and Yuan et al. describe many other recent works in this direction @MIT_survey [@yuan2019adversarial]. We would like to note that most prior works are algorithm-centered and improve adversarial performance by focusing on better training or data optimization strategies.

Efficient hardware implementation of DNNs have shown promising results in terms of improved speed and energy efficiency @finn [@xcel_ram; @resparc]. For instance, approximate computing leverages the fact that DNNs have a high tolerance towards inaccurate calculations. Thus, we can approximate underlying DNN computing blocks, such as, memory or Multiply-and-ACcumulate (MAC) circuits to minimise energy consumption without affecting the application-level accuracy @mehrotra1994fault [@moons2016energy; @chakraborty2020constructing; @panda2020invited; @venkataramani2015approximate]. So far, most hardware related research on DNNs have been focused on trading off energy-and-accuracy.

There are however, two interesting directions that still remain under-explored i) Using hardware approaches to improve the adversarial robustness of DNNs ii) Exposing the potential vulnerabilities of these hardware approaches specifically towards adversarial attacks. Works such as @bhattacharjee2020rethinking show that hardware-based approaches can improve the adversarial robustness of DNNs. Other recent works have also shown that homogeneous and heterogeneous (or layer-specific) quantization, can also improve the adversarial accuracy of a DNN @quanos [@panda2019discretization]. These works inform that hardware optimization strategies, used for reducing energy consumption, can be used effectively to address the software vulnerabilities in DNNs, specifically adversarial attacks. Other works have shown that hardware attacks can be made on DNN accelerators to cause them to malfunction resulting in serious performance degradation @hw_trojans [@memory_attacks1; @iia]. These works exploit the structural vulnerabilities of the hardware accelerator such as the micro-architecture and memory access patterns. However, none of these works have employed hardware-based adversarial attacks.

Based on the above insight, in our paper, we take an approximate computing route and explore the robustness and vulnerabilities of hybrid memory architectures towards adversarial attacks on DNNs. Hybrid memories are a combination of 8T and 6T SRAM cells with the most significant bits (MSBs) stored in the 8T cells and the least significant bits (LSBs) stored in the 6T cells. They have been shown to be highly energy efficient for DNN acceleration with minimum performance degradation. This is attributed to its operation under reduced (or scaled) supply voltage. However, at scaled voltages, the 6T SRAM cells behave erroneously leading to bit-error noise which is considered a major drawback of hybrid memories. In this work however, we ask, *"Can the bit-error noise due to LSB 6T-SRAM cells, be introduced in a controlled manner into specific sections of the hybrid memory to improve the adversarial robustness of DNNs? Also, can these noises be used to adversarially attack hybrid memory architectures?"*

We find that for different configurations of 8T-6T ratios and scaled $V_{DD}$, the bit-error noise introduced in the hybrid memory is bound within specific limits. In this paper, we call this strategically crafted bit-error noise as the **surgical noise**. We show that the surgical noise can be deliberately added in a controlled way into specific sections of the hybrid memory through the process of **surgical noise injection (SNI)** that can potentially interfere with the creation of adversarial attacks in DNNs, yielding robustness. It is evident that our method preserves the energy-efficiency benefits of hybrid memories due to low $V_{DD}$ operation. Furthermore, we do not require any re-training or training with adversarial data @dq [@quanos; @vortex].

At the same time, we show that SNI can be used to generate adversarial attacks on hybrid memory architectures. To demonstrate this we design a novel white-box surgical noise-based DNN parameter attack, where we assume that the attacker has complete knowledge of the network architecture and parameters of the model. With SNI on specific sections of the hybrid memory storing the DNN parameters, perturbations in the parameter values cause significant performance degradation. Interestingly, we find that these perturbations are adversarial in nature causing the DNN model to incur high confidence mis-classifications. In summary the novel contributions of our work are as follows:

1.  We empirically show that the bit-error noise due to LSB 6T-SRAM cells at scaled voltages $V_{DD}$ is a function of 8T-6T cell ratio $r$ and $V_{DD}$. We refer this strategically crafted bit-error noise as surgical noise.

2.  We show that surgical noise in hybrid memory architectures can improve the adversarial robustness of the DNN model when compared to baseline models- without any surgical noise.

3.  We also bring out a potential vulnerability of hybrid memories by devising a novel white-box, surgical noise-based DNN parameter attack wherein, surgical noise is introduced into specific sections of the hybrid memory storing the DNN parameters which cause high confidence mis-classifications by the model.

To validate our proposed methodology to improve adversarial robustness using hybrid memories, we run experiments using CIFAR10 and CIFAR100 datasets on both VGG19 and ResNet18 network architectures. Likewise, we validate our proposed adversarial, surgical noise-based DNN parameter attack scheme using the CIFAR10 dataset on VGG19 and ResNet18 architectures.

Related Works {#Related works}
=============

Since the advent of adversarial attacks, there have been numerous algorithm-centric works in the direction to abate such attacks. The most prominent work relates to adversarial training @domain_adv_training [@tramer2017ensemble]. This technique of introducing adversarial examples during training, by far has shown very promising results. Specifically, adversarial training with Projected Gradient Decent (PGD) attacked examples has been shown to be the most effective @athalye2018obfuscated [@cisse2017parseval]. Other works involve input gradient regularization to minimize the effect of adversarial inputs on the DNN @ross2017improving and input denoising @xie2019feature that designed new network architectures that minimize the noise on the input examples for better robustness.

Recently hardware focused approaches like the one by Panda et al. showed that discretization of input examples improves the adversarial robustness of a DNN manifolds. Also, binary neural networks are shown to be more adversarially robust than their full precision counterparts @panda2019discretization. Works such as QUANOS and Defensive Quantization (DQ) train the network to obtain the best optimized data quantization for improved adversarial robustness @quanos [@dq]. While DQ uses homogeneous data quantization for all the layers of the DNN, QUANOS uses adversarial noise sensitivity to determine layer specific data quantization values. The work by Rakin et al @he2019parametric uses gaussian noise injection on the DNN parameters during the training phase to improve the adversarial robustness of the trained model. The authors show that adding the DNN parameter noise acts as a regularizer. This helps the network to generalize well over the dataset and achieve a higher adversarial accuracy when combined with PGD adversarial training.

Hybrid memories have been extensively used for energy efficient and approximate storage. Works by Chang et al and Bortolotti et al have used hybrid memories to minimize the energy consumption of tasks like MPEG video processing and bio-signal processing respectively @chang2011priority [@bortolotti2014approximate]. In the light of approximate computing for deep learning applications, Srinivasan et al showed that hybrid memories can be used for energy efficient computations while maintaining good performance in DNN accelerators @hybridmem. The authors also show that using different 8T-6T ratios for different layers in the DNN can yield better energy calhounleslie@example.org.

Over time, research in the field of hardware-based side-channel attacks have shown that hardware trojans @hw_trojans [@liu2017neural] can degrade the performance of DNN hardware accelerators while remaining extremely stealthy and difficult to detect. In the works by Tolulope et al and Zhao et al, hardware trojans have been used to attack DNN accelerators by analysing the memory data patterns @memory_attacks1 [@iia]. Recently, a work by Kim et al has shown that DNN performance is adversely affected by frequent accesses of the DRAM memory storing the DNN parameters, which cause bit-flipping @kim2014flipping. They call it the Row-Hammer attack. Further, Rakin et al @rakin2019bit designed a progressive bit-search algorithm to detect the most sensitive bits for such bit-flip based attacks.

In this work, we use bit-error noise in hybrid memories to improve the adversarial robustness of the model which is to the best of our knowledge, the first of its kind in the literature. On top of that, we also show that hybrid memories are vulnerable to adversarial bit-error noise attacks which we demonstrate by designing a novel, white-box attack on the DNN parameters stored in the hybrid memory.

Background {#backgroud}
==========

Adversarial Attacks {#adversarial_attacks}
-------------------

In recent times, various adversarial attack methods have been developed to completely fool a DNN by introducing visibly minor perturbations in the input image data. Such adversarial attacks can be classified into two categories: white-box attacks and black-box attacks.

White-box attacks are based on attacking the target model with complete knowledge of the model architecture and parameters. On the other hand, black-box attacks are realised when the attacker has no knowledge of the target model's network architecture and parameters. It must be noted that robustness against white-box attacks ensures robustness under black-box attacks with similar strengths ($\epsilon$). In this paper, we refer to *clean accuracy* as the accuracy when the DNN model is fed clean inputs without any adversarial perturbations. Similary, *adversarial accuracy* refers to the model accuracy when the DNN is fed with images perturbed with adversarial disturbances. Our objective is to improve the *adversarial accuracy*, which determines the adversarial robustness of the model.

### Fast Gradient Sign Method (FGSM)

FGSM attack is one of the most efficient and powerful single-step attack. The generation of the adversarial example $\hat{x}$ from clean example $x$ with target value $t$, and DNN parameters $\theta$ follows the equation: $$\hat{x} = x + \epsilon . sign(\nabla_{x} \mathcal{L}(g(x_{i};\theta),t))$$ The value of $\epsilon$ determines the strength of the adversarial attack. Note that the perturbations are created in the direction of the gradient $\nabla_{x} \mathcal{L}(g(x_{i};\theta),t)$ such that it increases the loss, thereby causing adversarial effects. It has been shown that even with small perturbation values, the DNN model incurs high confidence mis-classifications.

Hybrid memories
---------------

![Structure of (left) 6T-SRAM having six transistors and common read write bit-lines (BL/BLB) and (right) 8T-SRAM cell having eight transistors and separate read write bit-lines (BL/BLB and RBL)<span data-label="sram"></span>](IEEEtran/figure/SRAM.png){width="50.00000%"}

The most ubiquitous SRAM memory architecture is one having a homogeneous 6T SRAM shown in Fig. \[sram\](left). The reason for its popularity is the small silicon footprint which implies higher data storage. However, they suffer from read/write bit-errors at scaled voltages ($V_{DD}$) which is because of the single read/write line ($BL/BLB$). On the other hand, the 8T SRAM shown in Fig. \[sram\](right) is nearly unaffected by voltage scaling which makes it suitable for critical applications like aerospace where error resilience is of prime importance @chang20088t.

Hybrid memories concoct the area efficiency of 6T-SRAM cells and resilience of 8T-SRAM cells at scaled voltages to yield an energy efficient approximate computing solution @chang2011priority [@bortolotti2014approximate]. With regard to DNNs, it has been shown that hybrid memories facilitate aggressive voltage scaling while retaining high accuracy performance which can be used to reduce the energy consumption in DNN accelerators @hybridmem. Throughout this paper, we refer to the 8T-6T ratio $r$ and $V_{DD}$ as the hybrid memory configurations. The hybrid memory configurations ($r$, $V_{DD}$), can vary or remain constant across different DNN layers.

DNN Accelerator Architecture {#dnn accelerator}
----------------------------

![DNN inference accelerator architecture with hybrid memory banks *Parameter MB* and *Activation MB* for storing DNN parameters and activation values respectively<span data-label="design_arch"></span>](IEEEtran/figure/design_arch.png){width="50.00000%"}

The architecture design of the Von-Neumann inference-only accelerator considered for this work is shown in Fig. \[design\_arch\] (only two layers shown). The accelerator uses hybrid memory banks (MB) to store both parameters (in parameters MB) and activations (in activation MB). Memory banks help improve the memory bandwidth by increasing the number of read channels. Also, the memory to compute-unit distance is minimized which improves the speed and energy efficiency of data-transfer @ozturk2008ilp [@koc2006minimizing]. The processing elements (PE) perform MAC operations between input and parameter data and store the results into activations MB which are used as inputs in the next layer. For each layer, the hybrid memory configurations may vary depending on the amount of surgical noise that needs to be introduced.

Characterization of surgical noise {#surgical_noise}
==================================

In hybrid memory architectures, at scaled voltages, bit-errors in the LSB 6T-SRAM cells introduce noise in the stored data values. To estimate the bit-error noise at various scaled voltages, we design a 6T-SRAM cell in 22nm technology using predictive models. The transistors are sized to have a nominal static read noise margin of 195 mV and write margin of 250 mV. Next we follow the procedure adopted by @hybridmem to calculate the bit-error rate values for different $V_{DD}$. Using the bit-error rates, we can model the bit-error noise in hybrid memories as a function of $V_{DD}$ and 8T-6T ratio $r$.

Through our experiments we find that the mean bit-error noise exhibits some amount of deterministic behaviour depending upon the hybrid memory configurations: supply voltage $V_{DD}$ and 8T-6T ratio $r$. Note, $r$ implies $\frac{\#8T cells}{\#6T cells}$. Hence, we can deliberately introduce strategically crafted bit-error noise using appropriate hybrid memory configurations to improve the adversarial robustness of DNNs and adversarially attack hybrid memory architectures. We call this controlled bit-error noise as **surgical noise** and the process of deliberately introducing different amounts of surgical noise into specific sections of hybrid memories as **surgical noise injection (SNI)**.

Mathematically, we can formulate the surgical noise by considering a vector $\nu_{l}$ being stored in layer $l$'s hybrid memory bank. Then, the vector after addition of surgical noise, $\nu_{sni, l}$, is given by the Equation \[N\]. $$\label{N}
    \nu_{sni, l} = \nu_l + \mathcal{N}, ~where ~\mathcal{N} ~= ~f(V_{DD}, r)$$ $$\label{mue}
    \mu = mean(|\mathcal{N}|) = mean(|\nu_{sni, l}-\nu_l|)$$ Where $\mathcal{N}$ is the surgical noise added to the vector, $\mu$ is a scalar value shown in Equation \[mue\] called the average surgical noise perturbation. In other words, $\mu$ denotes the net absolute perturbation introduced on vector $\nu_l$. The variation of $\mu$ for different values of $r$ and $V_{DD}$ is shown in Fig. \[sn\_vs\_r\_vs\_vdd\]. It can be observed that with lower 8T-6T ratios, the value of $\mu$ increases because of the rise in the number of erroneous 6T-SRAM cells. Likewise, since the value of bit-error rates in 6T-SRAMs increase with higher voltage scaling, it can be seen that the overall $\mu$ value increases for lower $V_{DD}$ values.

![Variation of average surgical noise perturbation $\mu$ with 8T-6T SRAM cell ratio $r$ for different supply voltages $V_{DD}$<span data-label="sn_vs_r_vs_vdd"></span>](IEEEtran/figure/sn.png){width="35.00000%"}

Improving Adversarial Robustness with Surgical Noise {#adv_rob}
====================================================

In this section, we investigate the idea of introducing surgical noise into hybrid memory architectures to improve the adversarial robustness of the model.

Methodology to determine the amount of surgical noise for each layer
--------------------------------------------------------------------

![Methodology for selecting the DNN layers suitable for SNI and determining required $\mu$ values for the suitable layers. The required $\mu$ is obtained via choosing the right hybrid memory configurations shown in Fig. \[sn\_vs\_r\_vs\_vdd\]<span data-label="algo_rob"></span>](IEEEtran/figure/Algo_rob.png){width="40.00000%"}

To improve the adversarial robustness of the DNN model, we introduce surgical noise into the hybrid memory banks of specific layers of the DNN accelerator shown in Fig. \[design\_arch\]. We would like to point out that one can follow either or both the approaches- **1) Introducing surgical noise into the *Parameter MB*, 2) Introducing surgical noise into the *Activation MB***. For both the approaches, the heuristics-based methodology proposed in Fig.\[algo\_rob\] can be applied. However, from our experiments we find that introducing surgical noise into the *Acivation MB* yields much better result than introducing surgical noise into the *Parameter MB*.

The heuristics-based methodology shown in Fig. \[algo\_rob\] determines the DNN layers suitable for SNI and the amount of surgical noise that needs to be introduced into the suitable layers to yield higher adversarial robustness. The amount of surgical noise is controlled by changing the hybrid memory configurations. To reduce the design space exploration however, we maintain the $V_{DD}$ at some constant value and vary the parameter $r$. The goal here is to check individual layers for their sensitivity towards SNI.

To determine the suitable amount of $\mu$ required in each layer, the proposed methodology, in Fig. \[algo\_rob\] incrementally iterates over possible number of 8T-6T SRAM cell ratios $r$ (i,e \#6T-SRAM cells $\in [1,7]$) and introduces corresponding surgical noise into the layer. At each iteration, the DNN model is attacked using the FGSM method and the resulting adversarial accuracy is recorded. Note, while calculation of gradients for FGSM attack, surgical noise is not introduced into any of the DNN activations. Among all the iterations, the hybrid memory configuration that produced the best adversarial accuracy is stored for later evaluations. This process is repeated until all the layers are analysed.

The DNN layers that produce more than 10% higher adversarial accuracy upon SNI than the baseline models without introduction of surgical noise, are labeled as strong layers. Similarly, layers that produced higher than 5% improvement in adversarial accuracy than baseline models are categorized as moderate layers. Weak response layers are the ones which produce same or lower adversarial accuracy upon SNI than the baseline models. At the end of this stage, the labels of individual DNN layers along with their favourable hybrid memory configurations are stored in the *store best configs* module.

As an example, Fig. \[ind\_layers\] shows the *store best configs* module data which comprises of the best adversarial accuracy obtained by introducing surgical noise into the corresponding layers individually, under FGSM ($\epsilon$= 0.05) attack. The 8T-6T ratios $r$ (mentioned alongside each bar) at $V_{DD}$= 0.68V are the corresponding favourable hybrid memory configurations for each layer. Strong layers shown in red produce high increment in adversarial accuracy while moderate (in green) and weak layers (in blue) show little or no increment respectively. For reference, the black dotted line shows the adversarial accuracy of the baseline model- without any SNI.

After categorizing the layers, the proposed methodology tries to find the best possible combination of layers that yield the best adversarial robustness. For this the strong and moderate layers with their favourable configurations (i,e, with configuration that generated good accuracy when tested individually) are combined and the adversarial accuracy of the DNN model is recorded under FGSM attack. For example, from the Fig.\[ind\_layers\], we see that layers \[1, 2, 3\] are strong while \[5, 6, 15, 18\] are moderate layers with favourable 8T-6T ratios as (3-5), (2-6), (5-3) and so on. The proposed methodology iterates over various combinations of the strong and moderate layers, ie {\[1,2\], \[1,5\], \[2,3\], \[1,2,3,6\] and so on}, with their respective favourable 8T-6T ratios and chooses the combination that yields the best adversarial accuracy. This gives us the final set of layers along with their hybrid memory configurations that yield the best adversarial robustness.

![Adversarial accuracy (with FGSM attack of strength $\epsilon = 0.05$) of the VGG19 network when surgical noise is introduced into each layer individually. For each layer, the value of $r$ corresponding to the best adversarial accuracy with SNI has been shown. The value of $V_{DD} = 0.68V$ <span data-label="ind_layers"></span>](IEEEtran/figure/ind.png){width="50.00000%"}

Possible hybrid memory architectures
------------------------------------

Table \[layer\_config vgg\] and Table \[layer\_config resnet\] show the 8T-6T ratios (at $V_{DD} = 0.68$V) for individual layers of VGG19 and ResNet18 DNN architectures trained to perform classifications on benchmark datasets- CIFAR10 and CIFAR100. The last column of each table shows the DNN's clean accuracy with SNI into the respective layers and the deviation with respect to clean accuracy of the baseline model (with no SNI). In the Table \[layer\_config vgg\], layers with P denote the pooling layers while in Table \[layer\_config resnet\], S denotes the residual layers in the ResNet18 network. The layers chosen using our proposed methodology above are shown with the respective $r$ values of their hybrid activation memories. Note that we do not perform SNI on the DNN parameter memories. The rest of the layers in which introducing surgical noise into the hybrid activation memories will have a degrading effect on the DNN's performance are shown using H. Meaning that they are composed of either homogeneous 8T-SRAM or homogeneous 6T-SRAM memory. The choice of memory to design the non-noisy layers gives rise to two design paradigms: **1) Design for Power efficiency 2) Design for Area efficiency.**

\[\]

\[\]

### Design for Energy Efficiency

![Activation memory architecture design for energy efficient implementation. Both hybrid memory banks (red) and homogeneous memory banks (blue) are connected to the same scaled voltage line.<span data-label="pe_hm"></span>](IEEEtran/figure/ee.png){width="40.00000%"}

In this design, the activation memories of the non-noisy DNN layers are stored in homogeneous 8T-SRAM memory. Fig.\[pe\_hm\] shows a block design for this approach where the red blocks represent the noisy activation memories and the blue blocks are the non-noisy activation memories. Here, a common supply voltage $V_{DD, SCALED}$ which is a scaled voltage, is fed to all the DNN layers. The result is that the overall energy is lowered because of voltage scaling. Since 8T-SRAM cells are error resilient at low voltages, scaling the supply voltage will have no effect on the DNN model accuracy.

### Design for Area Efficiency

![Activation memory architecture design for area efficient implementation. Here hybrid memory banks (red) are connected to the scaled voltage line and homogeneous memory banks (blue) are connected to the nominal voltage line.<span data-label="ae_hm"></span>](IEEEtran/figure/ae_hm.png){width="40.00000%"}

![Comparative analysis of the energy and area efficient design paradigms<span data-label="pe_ae"></span>](IEEEtran/figure/pe_ae.png){width="40.00000%"}

In contrast to the previous approach, if the non-noisy layers are designed using homogeneous 6T-SRAM cells, the silicon footprint will be greatly reduced. However, if we supply the same $V_{DD,SCALED}$ value to all the layers, like in the previous case, bit-error noise in the homogeneous 6T-SRAM memories will degrade the DNN's performance significantly. Hence, in order to maintain the DNN's performance, two supply voltage lines, one with $V_{DD}$, the nominal voltage value is fed to the homogeneous 6T-SRAM memories while the other with $V_{DD,SCALED}$ value is fed to the chosen noisy layers. This has been shown in Fig.\[ae\_hm\].

A comparative analysis shown in Fig.\[pe\_ae\], explains the energy and area advantages of individual design paradigms. The homogeneous 8T-SRAM memory design is energy efficient as it consumes around 35.45% less energy than when the activations are stored in 6T-SRAM memory. However, this design paradigm incurs a 30% increase in silicon area than homogeneous 6T-SRAM memory architecture.

Results and Discussions
-----------------------

### Experimental Setup

The surgical noise values are estimated using SPICE simulations with 22nm predictive models. For all our experiments, to estimate the adversarial accuracy values with and without SNI, the DNN models are implemented on a DNN functional simulator designed using Pytorch. The functional simulator provides support for introducing specific amounts of surgical noise as required into specific layers of the DNN model. For faster simulations, we implement the functional simulator on a 2 Nvidia RTX2080ti GPU back-end platform. Additionally, in all our experiments, the DNNs are trained with 8-bit homogeneous bit-precision.

### Datasets and Network Architectures {#section_data_network}

We use two visual datasets namely CIFAR10 and CIFAR100. The CIFAR10 dataset has 60K examples distributed among 10 classes. The CIFAR100 dataset is similar to CIFAR10 with the difference being that there are 100 classes. Both have 50K training and 10K test examples. The reduction in number of examples per class in CIFAR100 leads to lower clean and adversarial accuracies.

For both the datasets, we evaluate our results using two different network architectures- 1) VGG19 network considered in this work has 16 convolutional layers with 5 pooling layers in between and 1 fully connected layer at the end of the network. 2) The ResNet18 network which is a standard residual network consists of 4 blocks with each block containing 4 convolutional layers and 2 residual layer. The network has an average pooling layer and a fully connected layer at the end. We perform inferences with surgical noise on both datasets on two different types of network architectures to get an understanding of how different networks respond to noise injection and their adversarial performance.

### Results for CIFAR10 and CIFAR100 datasets

To validate the performance of our proposed methodology for improving the adversarial robustness of DNNs using surgical noise, we employ white-box attacks, specifically FGSM attacks explained in the section \[adversarial\_attacks\]. To generate adversarial examples using the FGSM attacks, we perturb the input examples with varying strengths, $\epsilon$ between 0.05 to 0.3. Increasing the perturbation beyond 0.3 does not ensure "visibly minor changes" in the input images and hence makes no sense. Also we ensure that surgical noise is not introduced into the activations during the gradient calculation for the FGSM attack. However, during inference, we introduce surgical noise into the specific layers of the DNN according to Table \[layer\_config vgg\] and table \[layer\_config resnet\] chosen using our proposed methodology.

<span>0.4</span> ![Variation of adversarial loss with FGSM perturbation strength $\epsilon$ for a) CIFAR10 and b) CIFAR100 with SNI on both VGG19 and ResNet18 network architectures. Adversarial loss for *Baseline* models is calculated without SNI into the DNN network.](IEEEtran/figure/adv_loss_cifar10.png "fig:"){width="\textwidth"}

<span>0.4</span> ![Variation of adversarial loss with FGSM perturbation strength $\epsilon$ for a) CIFAR10 and b) CIFAR100 with SNI on both VGG19 and ResNet18 network architectures. Adversarial loss for *Baseline* models is calculated without SNI into the DNN network.](IEEEtran/figure/adv_loss_epsilon.png "fig:"){width="\textwidth"}

Fig.\[fig cifar10 r\_v\] and Fig.\[fig cifar100\] show the improvements in adversarial loss for CIFAR10 and CIFAR100 datasets respectively. For each dataset, we perform our experiments using both the VGG19 and ResNet18 network architectures. Adversarial loss is calculated using the Equation \[adv\_loss\]: $$adv~loss = clean~accuracy-adv~accuracy
    \label{adv_loss}$$ Both clean and adversarial accuracy have been defined in section \[backgroud\]. To compute the baseline adversarial loss, the clean accuracy of the DNN model without any SNI and the adversarial accuracy of the DNN model without SNI are computed corresponding to each $\epsilon$. Similarly, the adversarial loss of the DNN with surgical noise is computed using clean accuracy and adversarial accuracy of the DNN with SNI.

An important thing to note here is the clean accuracy of the DNN with SNI when compared to the clean accuracy of the baseline model. Table \[layer\_config vgg\] and Table \[layer\_config resnet\] show the clean accuracy of the DNN models after SNI along with the deviation from the clean accuracy of the baseline model. It can be observed that due to SNI, the clean accuracy value decreases slightly with respect to the baseline model. This accuracy degradation can be improved by re-training the surgical noise injected DNN model on clean examples.

### Discussions

It is evident from Fig.\[fig cifar10 r\_v\] and Fig.\[fig cifar100\] that SNI into hybrid memories storing the activations of the DNN leads to a decrease in adversarial loss. Adversarial loss is the difference between the *clean accuracy* and the *adversarial accuracy* of the DNN model. It should be noted that lower value of adversarial loss means higher robustness. Interestingly, we find that initial layers in both the network architectures offer higher adversarial robustness with SNI. This is expected since, in the later layers, features become more and more specific and can be easily corrupted by SNI. Additionally, it must be noted that the adversarial loss for the ResNet18 network is higher than the VGG19 network for both CIFAR10 and CIFAR100 datasets. Also, the improvements in adversarial loss is less for residual networks than VGG networks.

At this point, we also want to highlight the challenge of effective design space exploration in our proposed methodology. The multitude of layers and hybrid memory configurations lead to a very high design space for optimization. Although, in our heuristics algorithm, we explored a small design space and showed that higher adversarial accuracy can be achieved by introducing surgical noise into hybrid memories, these results might certainly not be the most optimum. Employing more structured optimization algorithms like Genetic Algorithm @whitley1994genetic and Particle Swarm Optimization @kennedy1995particle might lead to much better results.

Using surgical noise to attack hybrid memories {#attack}
==============================================

In this section, we bring out a potential vulnerability of hybrid memory based DNN accelerators by proposing a novel, white-box DNN parameter attack methodology. Unlike the previous section, where we used surgical noise in hybrid memories to improve the adversarial robustness of the DNN model, here we show that surgical noise can be strategically injected into a small, specific section of the hybrid memory storing the DNN parameters to cause high confidence misclassifications. We further show that this attack is adversarial in nature.

Surgical noise based white-box attack on DNN parameters
-------------------------------------------------------

To design the white-box DNN parameter attack, we perform a gradient-based perturbation like the one used in FGSM @goodfellow2014explaining. In this work however, unlike FGSM, that perturbs the input image, we use the gradient-based method to perturb the DNN parameters for performing adversarial attacks. This has been shown in Equation \[adv\_attack\]. First, the gradients of the parameters with respect to the DNN model loss is calculated. Note, that during the gradient calculations with respect to the loss, no surgical noise is introduced into the layers of the DNN model. We define a variable $\epsilon$, that accounts for the magnitude of perturbation introduced into the DNN parameters. To introduce adversarial perturbations however, we need to ensure that the perturbation is applied along the direction of the gradients. $$\label{adv_attack}
    W_{adv} = W_{orig} + \epsilon ~ sign(\frac{\partial \mathcal{L}}{\partial W_{orig}})$$where, $\mathcal{L}$ is the loss of the DNN model without adversarial attack and $W_{orig}$ is the original DNN parameter vector that is adversarially perturbed to create $W_{adv}$.

This method is fairly straightforward to execute in software. However, in hardware since surgical noise is crafted using bit-error noise due to the erroneous 6T-SRAM cells, we have to account for the probabilistic nature of perturbations introduced into the DNN parameters by surgical noise. Hence, we propose a probabilistic approach for introducing adversarial perturbations into the DNN parameters stored in the hybrid memory. For this, we redefine the terms $\epsilon$ and $sign(\frac{\partial \mathcal{L}}{\partial W_{orig}})$ as $\mu$ and $\mathcal{D}$ respectively. The term $\mu$ shown in Equation \[mu\] is same as the one shown in Equation \[mue\]. $\mu$ is the average magnitude of the surgical noise $\mathcal{N}_{W_{orig}}$ for all the elements in the vector $W_{orig}$. Similarly, $\mathcal{D}$ shown in Equation \[D\] denotes the direction of perturbation due to surgical noise for each element in $W_{orig}$. It must be noted that the terms $\mu$ and $\mathcal{D}$ are equivalent to the terms $\epsilon$ and $sign(\frac{\partial \mathcal{L}}{\partial W_{orig}})$ in Equation \[adv\_attack\] respectively. $$\label{mu}
     \mu = mean((|\mathcal{N}_{W_{orig}}|)$$ $$\label{D}
     \mathcal{D} = sign(\mathcal{N}_{W_{orig}})$$ $$\label{sni_adv}
    W_{adv,sni} = W_{orig} + \mu \times \mathcal{D}$$ Hence, Equation \[adv\_attack\] can be reformulated to realise surgical noise-based adversarial attack on DNN parameters $W_{orig}$ as shown in Equation \[sni\_adv\]. Note that $\mu$ is a scalar and $\mathcal{D}$ is a vector having the same dimensions as $W_{orig}$. Since, the terms $\mathcal{D}$ and $sign(\frac{\partial Loss}{\partial W_{orig}})$ are equivalent, we want their values to closely resemble each other for introducing an adversarial attack on DNN parameters stored in the hybrid memory.

Proposed methodology for the surgical noise based adversarial attack
--------------------------------------------------------------------

Due to the probabilistic nature of surgical noise in hybrid memories, it is not always guaranteed that the perturbations in each and every DNN parameter $W$ ($W$ denotes the vector containing the DNN parameters) due to surgical noise follow the same direction as $\frac{\partial \mathcal{L}}{\partial W}$. To overcome this issue, we propose a methodology that perturbs a smaller section of the hybrid memory $W_{i} \subset W$ for which the surgical noise induced perturbations follow the same direction as the gradient of loss with respect to the DNN parameters stored in that section. In other words, we choose a section $W_i \subset W$ such that $\mathcal{D}_i$ is very close to $sign(\frac{\partial \mathcal{L}}{\partial W_{i}})$.

Fig. \[mem\_bank\_Arch\] shows how the surgical noise-based attack is performed on the DNN parameters. We assume that the parameters of each layer in the model are stored in separate hybrid memory banks. For each layer $l$, the corresponding hybrid memory bank stores its parameters in the form of a vector $W^l$. The dimensions of this vector is $[N^l_{ofm},N^l_{ifm},k^l,k^l]$, where $N^l_{ofm}$ is the number of output feature maps of the layer $l$, $N^l_{ifm}$, the number of input feature maps and $k^l$ is the kernel dimension. For this work, $W^l_{i}s$ are defined as vectors along the first dimension ($N^l_{ofm}$) of $W^l$. In other words, we perform DNN parameter attack on a smaller section $W^l_i$ of dimensions $[N^l_{ifm},k^l,k^l]$.

![Methodology to select a section from a hybrid memory bank to introduce adversarial perturbations using surgical noise<span data-label="mem_bank_Arch"></span>](IEEEtran/figure/memory_bank.png){width="40.00000%"}

We propose a methodology shown in Fig. \[wa\_algo\] to find the best section $W^l_i$ in each layer $l$ for introducing surgical noise-based adversarial attack. First, based on the average magnitude of surgical noise perturbation $\mu$ desired, we choose the hybrid memory configurations from the data shown in Fig. \[sn\_vs\_r\_vs\_vdd\]. Then, for each layer, we iterate over all the $W^l_i$s in the vector $W^l$ along the $N_{ofm}$ dimension. For each $W_i^l$, we calculate the value of $sign(\frac{\partial \mathcal{L}}{\partial W^l_{i}})$. Next, for the section $W^l_i$, we introduce surgical noise into the DNN parameters stored in the section and calculate the value of $\mathcal{D}^l_i$. After this, a comparison is made between $\mathcal{D}^l_i$ and $sign(\frac{\partial \mathcal{L}}{\partial W^l_{i}})$ to check the percentage match between the two vectors. This is repeated for each and every section $W^l_i$ and the section with the highest match value is chosen for the attack.

![Proposed methodology for selecting the appropriate section $W^l_i$ from $W$ to ensure adversarial DNN parameter attack.<span data-label="wa_algo"></span>](IEEEtran/figure/attack_flow.png){width="30.00000%"}

\[t!\]

![image](IEEEtran/figure/vgg19_cifar10.png){width="95.00000%"}

![image](IEEEtran/figure/resnet_cifar10.png){width="95.00000%"}

Results
=======

Experimental Setup
------------------

To demonstrate the surgical noise-based adversarial attack on the DNN parameters, we perform experiments on two DNN architectures VGG19 and RESNET18. To compare their sensitivity towards the attack, both have been trained on a single visual dataset- CIFAR10. A detailed account of the dataset and network architectures have been presented in section \[section\_data\_network\]. The baseline VGG19 and ResNet18 networks without surgical noise-based attack, yield a clean accuracy of 91.39% and 95.34%, respectively, for the CIFAR10 dataset. Also, note that we do not attack the residual layers in the ResNet18 network to maintain simplicity. For all our experiments, we implement our proposed method using our DNN Functional simulator.

Results of surgical noise-based DNN parameter attack
----------------------------------------------------

Based on our proposed methodology of attacking the DNN parameters stored in the hybrid memory, we report the accuracy of the DNN model under various surgical noise perturbation strengths $\mu$. The required value of $\mu$ is obtained from Fig. \[sn\_vs\_r\_vs\_vdd\] and have been shown in Table \[perturbation\_table\]. For each perturbation strength $\mu$, we introduce the respective surgical noise into the section of hybrid memory chosen by our proposed methodology.

The demonstration of our analysis has been shown in Fig. \[vgg19\_wa\] and Fig. \[resnet\_wa\]. The analysis clearly shows that different layers have different levels of sensitivity towards the surgical noise-based adversarial attack. For all the classification experiments shown, the network classifies the images with a confidence score of more than 90%. The average percentage match between $\mathcal{D}^l_i$ and $sign(\frac{\partial \mathcal{L}}{\partial W^l_{i}})$ for the chosen section $i$ of the DNN layer $l$ is above 99%. Thus, we ensure the surgical noise-based DNN parameter attack to be adversarial in nature.

Discussions
-----------

We see that the input layer in both the networks are considerably robust even for high $\mu$ values. Because the input layers are tasked with coarse feature extraction, introducing any perturbations into their synaptic weights will have little or no effects on the output. However, we see that the very next layer (layer 2) for both VGG19 and ResNet18 networks pose a strong vulnerability. Here, even for low $\mu$ values, the DNN clean accuracy starts degrading by over 60%. Additionally, a contrasting difference in the susceptibility towards surgical noise-based attack that can be noticed between the two DNN architectures is that VGG19 has more number of robust layers than ResNet18.

We perform another analysis to check if the DNN's clean accuracy is affected by introducing surgical noise into sub-sections of size smaller than $W^l_i$ of the hybrid memory. For this, the size of the sub-section in the given section $W^l_i$ is varied from a quarter to three-fourths of the size of the section. This has been shown in Fig. \[finer\]. In this example, we choose the selected section of the second layer in the VGG19 network and gradually increment the size of the sub-section while introducing surgical noise perturbation of magnitude $\mu$= 0.01 in order to check the accuracy and confidence value of the DNN. We observe that even for a smaller attack region, our surgical noise-based adversarial attack can successfully degrade the DNN's performance.

![Variation of clean accuracy of the VGG19 network when smaller subsections of the selected section $W^l_i$ from layer 2 is attacked<span data-label="finer"></span>](IEEEtran/figure/finer.png){width="50.00000%"}

Conclusion
==========

In this work we show that bit-error noise in hybrid memories due to erroneus 6T-SRAM cells can be controlled using the hybrid memory configurations. The surgical noise can be strategically injected into hybrid memories storing the activations and DNN parameters to improve the adversarial robustness of the DNN model. Additionally, the DNN parameters stored in the hybrid memory banks can be adversarially attacked using surgical noise injected in a strategic manner causing a huge degradation in the DNN inference accuracy. Hence, implementing 6T-8T hybrid memories in DNN hardware accelerators can not only make the design more energy efficient but can also impact the adversarial robustness of the DNN model.

Acknowledgement
===============

This work was supported in part by National Science Foundation (Grant\#1947826), the Technological Innovation Institute, and the Amazon Research Award.

[^1]: Abhishek Moitra and Priyadarshini Panda are with the Department of Electrical Engineering, Yale University.

{'source': 'arXiv_out/2011'}