End FA_4bit; Architecture behave of FA_4bit is Signal c : std_logic_vector (4 downto 0); Begin Process (a,b,cin,c) Begin C(0) < cin; for I in a’range loop Sum(i) <= a(i) xor b(i) xor c(i); C(i+1) <= (a(i) and b(i)) or (c(i) and (a(i) or b(i)); End loop; Cout <= c(c’HIGH); .UCF file for FPGA XC3S400 NET “a<0>” LOC = “p33” NET “a<1>” LOC = “p26”; NET “a<2>” LOC = “p24”; NET “a<3>” LOC = “p22”; NET “b<0>” LOC = “p37”; NET “b<1>” LOC = “p36”; NET “b<2>” LOC = “p35”; NET “b<3>” LOC = “p34”; NET “cin” LOC = “p42”; NET “cout” LOC = “p133”;
Architecture behave of Counter_4bit is Signal cnt_state : std_logic_vector (7 downto 0); Begin Process (clk, reset, cnt_en) Begin If(reset = ‘1’) then --asynchronous reset Cnt_state <= “00000000”; Elsif (clk’event and clk=’1’ ) then If (cnt_en = ‘1’) then Cnt_state <= cnt_state+1; End if; End if; End process; Dout <= cnt_state (6 downto 3); End behave; .UCF file for FPGA XC3S400 NET “clk” LOC = “p180”; NET “cnt_en” LOC = “p22”; NET “dout<0>” LOC = “p143”; NET “dout<1>” LOC = “p140”; NET “dout<2>” LOC = “p139”; NET “dout<3>” LOC = “p138”; NET LOC = “p204”;
Decoder 2 to 4 Line Library IEEE; Use ieee.std_logic_1164.all; Entity decode2to4 is PORT ( a,b, enable : in std_logic; z : out std_logic_vector ( 3 downto 0) ); End decode2to4; Architecture DECODE_Concurrent of decode2to4 is Begin Z(0) <= ‘1’ when ((enable =’1’) and (a=’0’) and (b=’0’)) else ‘0’; Z(1) <= ‘1’ when ((enable =’1’) and (a=’0’) and (b=’1’)) else ‘0’; Z(0) <= ‘1’ when ((enable =’1’) and (a=’1’) and (b=’0’)) else ‘0’; Z(0) <= ‘1’ when ((enable =’1’) and (a=’1’) and (b=’1’)) else ‘0’; End DECODE_Concurrent; .UCF file for FPGA XC3S400 NET “a” LOC = “p22”; NET “b” LOC = “p24”; NET “a” LOC = “p22”; NET “enable” LOC = “p26”; NET “z<0>” LOC = “p143”; NET “z<1>” LOC = “p140”; NET “z<2>” LOC = “p139”; NET “z<3>” LOC = “p138”;
Truth Table for 2 to 4 decoder Sw S3 input En Sw S2 input a Sw S2 input a LED4 o/p Y3 LED3 o/p Y2 LED2 o/p Y1 LED1 o/p Y0 1 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 Decoder 3 to 8 Line Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity decoder3to8 is PORT ( signal sel : in std_logic_vector( 2 downto 0); Signal en : in std_logic; Signal Y : out std_logic_vector( 7 downto 0) ); End decoder3to8; Architecture behave of decoder3to8 is Process ( sel, en) Y <= “11111111”; If(en=’1’) then Case sel is
When “000” => Y(0) <= ‘0’; When “000” => Y(0) <= ‘0’; When “001” => Y(1) <= ‘0’; When “010” => Y(2) <= ‘0’; When “011” => Y(3) <= ‘0’; When “100” => Y(4) <= ‘0’; When “101” => Y(5) <= ‘0’; When “110” => Y(6) <= ‘0’; When “111” => Y(7) <= ‘0’; End case; End if; End process; End behave; .UCF file for FPGA XC3S400 NET “en” LOC = “p33”; NET “sel<0>” LOC = “p26”; NET “sel<1>” LOC = “p24” NET “sel<2> LOC = “p22”; NET “Y<0>” LOC = “p143”; NET “Y<1>” LOC = “p140”; NET “Y<2>” LOC = “p139”; NET “Y<3>” LOC = “p138”; NET “Y<4>” LOC = “p133”; NET “Y<5>” LOC = “p132”;
NET “Y<6>” LOC = “p131”; NET “Y<7>” LOC = “p130”; Half Adder Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity HA is PORT (X, Y : in std_logic; SUM, Carry : out std_logic ); End HA; Architecture behave of HA is begin Sum <= X xor Y; <= X and Y; End behave; .UCF file for FPGA XC3S400 NET “X” LOC = “p22”; NET “Y” LOC = “p24”; NET “SUM” LOC = “p140”; NET “Carry” LOC = “p143”; Half Subtractor
Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity HS is PORT (X, Y : in std_logic; Diff, Borrow : out std_logic ); End HS; Architecture behave of HS is begin Diff <= X xor Y; Borrow <= NOT X and Y; End behave; .UCF file for FPGA XC3S400 NET “X” LOC = “p22”; NET “Y” LOC = “p24”; NET “Diff” LOC = “p140”; NET “Borrow” LOC = “p143”; Encoder Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all;
Entity encoder is PORT ( Reset : in std_logic; Clk : in std_logic; D_in : in std_logic_vector (7 downto 0); D_out : out std_logic_vector (2 downto 0) ); End encoder Architecture behave of encoder is Begin Process(reset, clk, D_in) Begin If (reset=’1’) then D_out <= “000”; Elsif (Clk’event and Clk = ‘1’) then Case D_in is When “00000001” => D_out <= “000”; When “00000010” => D_out <= “001”; When “00000100” => D_out <= “010”; When “00001000” => D_out <= “011”; When “00010000” => D_out <= “100”; When “00100000” => D_out <= “101”; When “01000000” => D_out <= “110”; When “10000000” => D_out <= “111”; End case;
End if; End process; End behave; .UCF file for FPGA XC3S400 NET “clk” LOC = “p180”; NET “D_in<0>” LOC = “p22”; NET “D_in<1>” LOC = “p24”; NET “D_in<2>” LOC = “p26”; NET “D_in<3>” LOC = “p33”; NET “D_in<4>” LOC = “p34”; NET “D_in<5>” LOC = “p35”; NET “D_in<6>” LOC = “p36”; NET “D_in<7>” LOC = “p37”; NET “D_out<0>” LOC = “p143”; NET LOC = “p140”; NET LOC = “p139”; Flip-Flop Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity D_flipflop is
NET “Sel<0>” LOC = “p34”; NET “Sel<1>” LOC = “p35”; NET “A” LOC = “p22”; NET “B” LOC = “p24”; NET “C” LOC = “p26”; NET “D” LOC = “p33”; NET “Dout” LOC = “p143”; DeMultiplexure Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity DeMux is PORT ( A : in std_logic; SEL : in std_logic_vector(1 downto 0); Dout : out std_logic_vector(3 downto 0); ); Architecture behave of DeMux is Begin Process(SEL,A) Begin Case SEL is when “00” => Dout <= (0 => A, <= ‘1’); when “01” => Dout <= (1 => A, other <= ‘1’);
when “00” => Dout <= (2 => A, <= ‘1’); when “00” => Dout <= (3 => A, other <= ‘1’); when others => Dout <= NULL; end case; end process; end behave; .UCF File NET “A” LOC = “P22”; NET “SEL<0>” LOC = “P24”; NET “SEL<1>” LOC = “P26”; NET”Dout<0>” LOC = “P143”; NET “Dout<1>” LOC = “140”; NET “Dout<2>” LOC = “P139”; NET “Dout<3>” LOC = “P138”; Parity Checker Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity Parity_Checker is PORT ( A,B,C : in std_logic;
Else Y(0) <= ‘0’; End if; ------------Remainder----------------------------- R <= conv_std_logic_vector (temp,4); End if; End process; End behavioural; .UCF File NET “a<0> LOC = “p34”; NET “a<1> LOC = “p35”; NET “a<2> LOC = “p36”; NET “a<3> LOC = “p37”; NET “b<0> LOC = “p22”; NET “b<1> LOC = “p24”; NET “b<2> LOC = “p26”; NET “b<3> LOC = “p33”; NET “y<0> LOC = “p143”; NET “y<1> LOC = “p140”; NET “y<2> LOC = “p139”; NET “y<3> LOC = “p138”; NET “r<0> LOC = “p133”; NET “r<1> LOC = “p132”; NET “r<2> LOC = “p131”;
NET “SW<2> LOC = “p26”; NET “SW<3> LOC = “p33”; NET “SW<4> LOC = “p34”; NET “SW<5> LOC = “p35”; NET “SW<6> LOC = “p36”; NET “Sw<7> LOC = “p37”; NET “LED<0> LOC = “p143”; NET “LED<1> LOC = “p140”; NET “LED<2> LOC = “p139”; NET “LED<3> LOC = “p138”; NET “LED<5> LOC = “p133”; NET “LED<6> LOC = “p132”; NET “LED<7> LOC = “p131”; NET “LED<8> LOC = “p130”; ENCODER An encoder has a number of input lines, only one of which is activated at a given time, and produces an N-bit output code, depending on which input is activated. An encoder (8-line-to-3-line encoder) performs the opposite function: it accepts eight input lines and produces a three-bit output code corresponding to the activated input. Figure 9-13 shows the logic circuit and the truth table for an octal-to-binary encoder with active-LOW inputs.
Variable ring : std_logic_vector(3 downto 0); If clk’event and clk=’1’ then If FREEZE = ‘0’ then Case ring is When “1110” => ring := “1101”; When “1101” => ring := “1011”; When “1011” => ring := “0111”; When “0111” => ring := “1110”; When others => ring := “1110”; End case; End if; DAV <= FREEZE; End if; Row <= ring; CASE ring is When “1110” => DATA(3 downt 2) <= “00”; When “1101” => DATA(3 2) <= “01”; When “1011” => DATA(3 downt 2) <= “10”; When “0111” => DATA(3 2) <= “11”; When others => DATA(3 downt 2) <= “00”; End case; CASE col is When “1110” => DATA(1 downt 0) <= “00”; FREEZE <= ‘1’; When “1101” => DATA(1 downt 0) <= “01”; FREEZE <= ‘1’;
Library IEEE; Use ieee.std_logic_1164.all Entity Priority_Encod is PORT ( Sw : in std_logic_vector(9 downto 0); OE : in std_logic; D : out std_logic_vector(3 downto 0) ); End; Architecture concur of Priority_Encod is Begin D <= “ZZZZ” when OE = ‘0’ or SW=”1111111111” else “1001” when SW(9)=’0’ else “1000” when SW(8)=’0’ else “0111” when SW(7)=’0’ else “0110” when SW(6)=’0’ else “0101” when SW(5)=’0’ else “0100” when SW(4)=’0’ else “0011” when SW(3)=’0’ else “0010” when SW(2)=’0’ else “0001” when SW(1)=’0’ else “0000” when SW(0)=’0’ ; End;
.UCF File for Keyboard FPGA XCS400 NET “CLK” LOC = “P79”; NET “KBDATA” LOC = “P144”; NET “KBCLK” LOC = “P155”; NET “Switch” LOC = “P22”; NET “LED<0>” LOC = “P143”; NET “LED<1>” LOC = “P140”; NET “LED<2>” LOC = “P139”; NET “LED<3>” LOC = “P138”; NET “LED<4>” LOC = “P133”; NET “LED<5>” LOC = “P132”; NET “LED<6>” LOC = “P131”; NET “LED<6>” LOC = “P130”; When X”7A” => ASCII_Equiv <= X”33”; -------------------3 When X”7A” => ASCII_Equiv <= X”33”; -------------------3 When X”7A” => ASCII_Equiv <= X”33”; -------------------3 When X”7A” => ASCII_Equiv <= X”33”; -------------------3 When X”7A” => ASCII_Equiv <= X”33”; -------------------3 When X”7A” => ASCII_Equiv <= X”33”; -------------------3 When X”7A” => ASCII_Equiv <= X”33”; -------------------3