the logical OR of the FIFO Full Flag and the Latency Error Flag, both of which also appear separately in the Triggered Data packet, and are also stored in a register which can be read via the I2C interface. The SYNC bit is output with every Stub Data packet (every 8 clock cycles at 320MHz) and can be used by the receiver for data synchronization purposes. Figure — Illustration of the Stub Data packet. Figure — An illustration of the serial Triggered Data packet in relationship to the Stub Data Packet. ► NOTE: The Triggered Data header (11) is always aligned with the SYNC bit. Interfaces Fast Control Interface In addition to the I2C Slow Control Interface, there is a Fast Control Interface operating serially at 320 MHz via a differential SLVS input. Running at the 320 MHz clock frequency allows eight bits of serial data to be input within a Bunch-Crossing period of 25 ns. These eight bits of data have pre-defined functions, as set out in Table 1 below. Fast Command B7 B6 B5 B4 B3 B2 B1 B0 Fast Reset 1 1 0 1 0 0 0 1 Trigger 1 1 0 0 1 0 0 1 Test Trigger 1 1 0 0 0 1 0 1 Orbit Reset 1 1 0 0 0 0 1 1 Orbit Reset & Fast Reset 1 1 0 1 0 0 1 1 Orbit Reset & Trigger 1 1 0 0 1 0 1 1 Orbit Reset & Test Pulse Trigger 1 1 0 0 0 1 1 1 Table — Fast Control Interface commands and their corresponding serial codes The CBC3 detects the 110 synchronisation pattern on bits <7:5> and uses this to produce the on-chip 40 MHz reference clock. In the event that this synchronisation pattern is not received, the on-chip 40 MHz clock will freeze until the synchronisation pattern is resumed. Two flags are made available via the I2C
2 Sync lost (read only) 0 1 Sync stat (read only) 0 0 Bad code (read only) 0 Table — Fast Command Interface and Error Flags Bits (7:6) are used to select a delay to the serial command word by either one or two 320 MHz clock cycles. This is used to coarsely adjust the timing of the 40MHz clock derived from the serial command. The default is no delay. Values 00, 01 (one clock cycle delay) and 11 (two clock cycles delay) are valid. The value 10 is not valid. Bits (4:0) are error flags and are read only. Bit 4 indicates an overflow in the buffer RAM in the event that more than 32 triggers are received before the L1 data can be read. Bit 3 indicates a mismatch between the programmed latency and the difference between the pipeline read and write counters. Bits (2:0) are error flags for the fast command interface. Bit 2 indicates that synchronization has been lost at some time and does not imply that this is still the case. Bit one indicates the current synchronization status only. Bit zero indicates whether an invalid code has been received. This may be due to synchronization issues or simply the user sending an incorrect command code. Page1 — Register 32 to 62: Mask Channels 1-248 Addresses 00100000 to 00111110 Bit Function Default 7 Mask Channel<8> … <248> 1 6 Mask Channel<7> … <247> 1 5 Mask Channel<6> … <246> 1 4 Mask Channel<5> … <245> 1 3 Mask Channel<4> … <244> 1 2 Mask Channel<3> … <243> 1 1 Mask Channel<2> … <242> 1 0 Mask Channel<1> … <241> 1 Table — Channel Masking registers These registers are used to either mask channels that are behaving badly or for test purposes. One bit is used per channel, with 8 bits per register requiring 31 register for channels 1-248. In the default case all of channels are unmasked. Page1 — Register 63: Mask Channels 249-254