ports “ASYNC” and “CLOCK” and 1 output port “SYNC”. The first ‘D’ flip-flop has 2 inputs “ASYNC” and “CLOCK” and 1 output “C1_ASYNC”. The second ‘D’ flip-flop 2 inputs “C1_ASYNC” and “CLOCK” and 1 output “SYNC”. 2.3.1 MODULE PORT CONNECTION BY module SYNCHRO(ASYNC,SYNC,CLOCK); input ASYNC; input CLOCK; output SYNC; wire C1_ASYNC; DFF DFF1 (C1_ASYNC, ASYNC, CLOCK); DFF DFF2 (SYNC, C1_ASYNC, CLOCK); //DFF DFF1 (ASYNC, C1_ASYNC, CLOCK); //DFF DFF2 (SYNC, C1_ASYNC, CLOCK); endmodule Here first instance name of ‘D’ flip-flop is “DFF1” and second instance name is “DFF2”. In this module ports are connected by order. Order of ports in instantiation of DFF1 and DFF2 is same as order of ports in DFF. If the number of ports increased, then it is very difficult to do “module ports connection by order”. 2.3.2 MODULE PORT CONNECTION BY NAME Module SYNCHRO (ASYNC, SYNC, CLOCK); input ASYNC; input CLOCK; output SYNC; wire C1_ASYNC; DFF DFF1 (.D (ASYNC), .CLK (CLOCK), .Q (C1_ASYNC)); DFF DFF2 (.D (C1_ASYNC), .Q (SYNC), .CLK (CLOCK)); endmodule; In this module are connected by Name. Order of ports in instantiation of DFF1 and DFF2 is different from order of ports in DFF. In this ‘.’ Is used to represent port name followed by
‘include File inclusion. The contents of another Verilog source file is inserted where the ‘include directive appears. Here the contents of ‘define.h’ are included within the ‘idu’ module. ‘define Allows a text string to be defined as a macro name. Example ‘define gate_regression 1 Allows ‘gate_regression’ to be substituted by 1 where ever it gets used. 2.8 WHAT ARE THE TIMING CONTROL STATEMENTS IN VERILOG Timing Controls Description # It delays execution for a specific amount of time, ‘delay’ may be a number, a variable or an expression. Example of a procedural block using ‘#” is shown below. Here ‘(c & d)’ gets evaluated at time 0 but gets assigned to ‘a’ after 2 time units whereas gets evaluated after 3 time units and gets assigned to ‘e’ immediately.
if It executes the statement or statement_group if the condition evaluates as true. If we need more than one statement (i.e statement_group) then we need to use begin-end or a fork-join block. The condition here can be an expression or a single value. If the condition evaluates to ‘0’ or unknown then the condition is considered false, and if the condition evaluates to ‘1’ or more then the condition is considered true. if (alu_func == 2’b00) aluout = a + b; else if (alu_func == 2’b01) aluout = a - b; else if (alu_func == 2’b10) aluout = a & b; else // alu_func == 2’b11 aluout = a | b; if (a == b) begin x = 1; ot = 4’b1111; end if-else It executes the first statement or statement_group if the condition evaluates as true and executes the second statement or statement_group if the condition evaluates as false. The condition here can be an expression or a single value. If the condition evaluates to ‘0’ or unknown then the condition is considered false, and if the condition evaluates to ‘ 1’ or more then the condition is considered true. case It compares the expression with each of the case_item’s and executes the statement or case (alu_ctr) 2’b00: aluout = a + b; 2’b01: aluout = a - b; 2’b10: aluout = a & b; default: aluout = 1’bx; /* Treated as don’t for minimum logic generation. */ endcase case (x, y, z) 2’b00: aluout = a + b; /*case if x or y or z is 2’b00.*/
statement_group associated with the matching case_item. It executes the default if none of the case_item’s match. Here the default case is optional. 2’b01: aluout = a - b; 2’b10: aluout = a & b; default: aluout = a | b; endcase It is special version of case statement where ‘z’ and ‘?’ are treated as don’t cares. Similar to case statement it compares the expression with each of the case_item’s and executes the statement or statement_group associated with the first matching case_item. It executes the default if none of the case_item’s match. Here the default case is optional. casez (d) 3’b1??: b = 2’b11; /* b = 11 if d = 100 or 101 or 110 or 111 */ 3’b01?: b = 2’b10; // b = 10 if d = 010 or 011 default: b = 2’b00; endcase casex It is special version of case statement where ‘x’, ‘z’ and ‘?’ are treated as don’t cares. Similar to case statement it compares the expression with each of the case_item’s and executes the statement or statement_group casex (a) 2’b1x: msb = 1; // msb = 1 if a = 10 or a = 11 /* If this were case(a) then only a=1x would match.*/ default: msb = 0; endcase
statement or statement_group) should be executed. If the loop condition expression is true, the loop is entered. The final expression (step) is evaluated at the end of the loop. disable Syntax disable group_name; It discontinues execution of a named group of statements. begin: accumulate forever @(posedge clk); a = a + 1; if (a == 2’b0111) disable accumulate; end end 3. FUNCTION and TASK Verilog provides Functions and Tasks to allow the behavioral description of a module to be broken into more manageable parts allowing better readability and manageability. Functions and Tasks are useful for several reasons which are, they allow often used behavioral sequences to be written once and called when needed, they allow for a cleaner writing style and finally they allow data to be hidden from other parts of the design. 3.1 FUNCTION Functions are defined in the module in which they are used. It is possible to define function in separate file and use compile directive 'include to include the function in the file which instantiates the function. Function can call other functions, but cannot call task. The following are some of the general rules for functions: Functions must contain at least one input argument and cannot drive more than one output. Functions cannot contain an inout or output declaration. Functions cannot contain time controlled statements (#, @, wait), i.e., it cannot contain delays . Function cannot include timing delays, like posedge, negedge, # delay. Which means that function should be executed in "zero" time delay. Functions must contain a statement that assigns the return to the implicit function name register. The variables declared within the function are local to that function. The order of declaration within the function defines how the variables passed to the function by the caller are used. Syntax