│ ├── [Number Of Pins] │ ├── [Pin Numbers] Len, L, R, C, Fork, Endfork │ ├── [Model Data] │ │ ├── [Resistance Matrix] Banded_matrix, Sparse_matrix, │ │ │ │ Full_matrix │ │ │ ├── [Bandwidth] │ │ │ └── [Row] │ │ │ │ │ ├── [Inductance Matrix] Banded_matrix, Sparse_matrix, │ │ │ │ Full_matrix │ │ │ ├── [Bandwidth] │ │ │ └── [Row] │ │ │ │ │ ├── [Capacitance Matrix] Banded_matrix, Sparse_matrix, │ │ │ │ Full_matrix │ │ │ ├── [Bandwidth] │ │ │ └── [Row] │ │ │ │ │ └── [End Model Data] │ │ │ └── [End Package Model] │ └── [End] .pkg FILE ├── File Header Section │ ├── [IBIS Ver] │ ├── [Comment Char] │ ├── [File Name] │ ├── [File Rev] │ ├── [Date] │ ├── [Source] │ ├── [Notes] │ ├── [Disclaimer] │ └── [Copyright] │ ├── [Define Package Model] │ ├── [Manufacturer] │ ├── [OEM] │ ├── [Description] │ ├── [Number Of Sections] │ ├── [Number Of Pins] │ ├── [Pin Numbers] Len, L, R, C, Fork, Endfork │ ├── [Model Data] │ │ ├── [Resistance Matrix] Banded_matrix, Sparse_matrix,
│ │ │ │ Full_matrix │ │ │ ├── [Bandwidth] │ │ │ └── [Row] │ │ │ │ │ ├── [Inductance Matrix] Banded_matrix, Sparse_matrix, │ │ │ │ Full_matrix │ │ │ ├── [Bandwidth] │ │ │ └── [Row] │ │ │ │ │ ├── [Capacitance Matrix] Banded_matrix, Sparse_matrix, │ │ │ │ Full_matrix │ │ │ ├── [Bandwidth] │ │ │ └── [Row] │ │ │ │ │ └── [End Model Data] │ │ │ └── [End Package Model] │ └── [End] .ebd FILE ├── File Header Section │ ├── [IBIS Ver] │ ├── [Comment Char] │ ├── [File Name] │ ├── [File Rev] │ ├── [Date] │ ├── [Source] │ ├── [Notes] │ ├── [Disclaimer] │ └── [Copyright] │ ├── [Begin Board Description] │ ├── [Manufacturer] │ ├── [Number of Pins] │ ├── [Pin List] signal_name │ ├── [Path Description] Len, L, R, C, Fork, Endfork, Pin, │ │ Node │ ├── [Reference Designator Map] │ └── [End Board Description] │ └── [End]
INTRODUCTION: The SPICE, VHDL-AMS and Verilog-AMS languages are supported by IBIS. This chapter describes how models written in these languages can be referenced and used by IBIS files. Table 11 shows the keywords used by the language extensions within the IBIS framework. Table – Language Extension Keywords Keyword Description [External Circuit] [End External Circuit] References enhanced descriptions of structures on the die, including digital and/or analog, active and/or passive circuits [External Model] [End External Model] Same as [External Circuit], except limited to the connection format and usage of the [Model] keyword, with one additional feature added: support for true differential buffers [Node Declarations] [End Node Declarations] Lists on-die connection points related to the [Circuit Call] keyword [Circuit Call] [End Circuit Call] Instantiates [External Circuit]s and connects them to each other and/or die pads The placement of these keywords within the hierarchy of IBIS is shown below: ├── [Component] │ │… │ │── [Node Declarations] │ └── [End Node Declarations] │ │… │ │… │ │── [Circuit Call] │ └── [End Circuit Call] │… ├── [Model] │ │... │ │ │ ├── [External Model] │ └── [End External Model] │… ├── [External Circuit] │ └── [End External Circuit]
– Paths Connected by Series Resistors as Differential Terminators Keyword: [Reference Designator Map] Required: Yes, if any of the path descriptions use the Node subparameter Description: Maps a reference designator to a component or electrical board description contained in a .ibs or .ebd file. Usage Rules: The [Reference Designator Map] keyword must be followed by a list of all of the reference designators called out by the Node subparameters used in the various path descriptions. Each reference designator is followed by the name of the .ibs or .ebd file containing the electrical description of the component or board, then the name of the component itself as given by the .ibs or .ebd file’s [Component] or [Begin Board Description] keyword respectively. The reference designator, file name and component name terms are separated by white space. By default the .ibs or .ebd files are assumed to exist in the same directory as the calling .ebd file. It is legal for a reference designator to point to a component that is contained in the calling .ebd file. The reference designator is limited to ten characters. Example: [Reference Designator Map] | | External Part References: | | Ref Des File name Component name u23 pp100.ibs Processor u24 simm.ebd 16Meg X 36 SIMM Module u25 ls244.ibs NoName 74LS244a u26 r10K.ibs My_10K_Pullup Keyword: [End Board Description] Required: Yes Description: Marks the end of an Electrical Interconnect Description. Usage Rules: This keyword must come at the end of each complete electrical interconnect model description. Optionally, a comment may be added after the [End Electrical Description] keyword to clarify which board model has ended. Example: [End Board Description] | End: 16Meg X 8 SIMM Module Keyword: [End]
Parameter: Init_Returns_Impulse Required: Yes Descriptors: Usage: Info Type: Boolean Format: Value Default: <Boolean_literal> Description: <string_literal> Definition: Tells EDA tool whether the AMI_Init function returns a modified impulse response. Usage Rules: When the Boolean_literal value is set to “True”, the model returns the convolution of the impulse response with the impulse response of the equalization. Other Notes: Examples: (Init_Returns_Impulse (Usage Info)(Type Boolean)(Default True) (Description “Valid for all AMI_Version levels”) ) (Init_Returns_Impulse (Usage Info)(Type Boolean)(Value True) (Description “Valid for all AMI_Version levels”) ) Parameter: GetWave_Exists Required: Yes Descriptors: Usage: Info Type: Boolean Format: Value Default: <Boolean_literal> Description: <string_literal> Definition: Tells EDA tool whether the AMI_GetWave is implemented in this model Usage Rules: Note that if Init_Returns_Impulse is set to “False”, then GetWave_Exists SHALL be set to “True”. Other Notes: Examples: (GetWave_Exists (Usage Info)(Type Boolean)(Default True) (Description “Valid for all AMI_Version levels”) ) (GetWave_Exists (Usage Info)(Type Boolean)(Value True) (Description “Valid for all AMI_Version levels”) )