access is directed to that overlay page. Otherwise, the access is directed to the underlying GPA page. When the hypervisor performs a guest page table walk either in response to a virtual processor memory access or a call to HvTranslateVirtualAddress, it might find that a page table is located on a GPA location associated with an overlay page. In this case, the hypervisor may choose to do any one of the following: generate a guest page fault, reference the contents of the overlay page, or reference the contents of the underlying GPA mapping. Because this behavior can vary from one hypervisor implementation to the next, it is strongly recommended that guests avoid this situation. GPA Data Types Map Page Flags The following flags are used with the HvMapGpaPages hypercall. typedef UINT32 HV_MAP_GPA_FLAGS; #define HV_MAP_GPA_READABLE 0x00000001 #define HV_MAP_GPA_WRITABLE 0x00000002 #define HV_MAP_GPA_EXECUTABLE 0x00000004 GPA Interfaces HvMapGpaPages The HvMapGpaPages hypercall maps one or more GPA pages within the caller’s GPA space to pages within the target partition’s GPA space. Wrapper Interface HV_STATUS HvMapGpaPages( __in HV_PARTITION_ID TargetPartitionId, __in HV_GPA_PAGE_NUMBER TargetGpaBase, __in HV_MAP_GPA_FLAGS MapFlags, __inout PUINT32 PageCount, __in_ecount(PageCount) PCHV_GPA_PAGE_NUMBER SourceGpaPageList ); Native Interface HvMapGpaPages [rep] Call Code = 0x004B Input Parameter Header 0 TargetPartitionId (8 bytes) 8 TargetGpaBase (8 bytes) 16 MapFlags (4 bytes) Padding (4 bytes) Input List Element 0 SourceGpaPage (8 bytes)
Wrapper Interface HV_STATUS HvAssertVirtualInterrupt( __in HV_PARTITION_ID DestinationPartition, __in HV_INTERRUPT_CONTROL InterruptControl, __in UINT64 DestinationAddress, __in HV_INTERRUPT_VECTOR RequestedVector ); Native Interface HvAssertVirtualInterrupt Call Code = 0x0055 Input Parameters 0 DestinationPartition (8 bytes) 8 InterruptControl (8 bytes) 16 DestinationAddress (8 bytes) 24 RequestedVector (4 bytes) Padding (4 bytes) Description For information on virtual interrupts, see section . If the call is made twice in a row with the same interrupt type specified in the InterruptControl parameter, the behavior depends upon whether or not the first interrupt was acknowledged by the virtual processor before the second call is made. If the first interrupt has already been acknowledged, then the second call is treated as a new assertion. If the first interrupt has not yet been acknowledged, then the second call supersedes the previous assertion with the new vector. If the second call specifies the vector HV_INTERRUPT_VECTOR_NONE, then the call acts as a deassertion. The behavior of this call differs for interrupts of type HvX64InterruptTypeExtInt in the following ways: This interrupt type is always targeted at the boot processor. The boot processor is identified by a virtual processor index of zero. The DestinationAddress parameter must, therefore, be zero. Calls to HvAssertVirtualInterrupt will fail if the interrupt asserted by a previous call has already been acknowledged by the processor. This acknowledgement must first be cleared by calling HvClearVirtualInterrupt. This is especially useful when implementing an external interrupt controller, such as the 8259 PIC. It prevents HvAssertVirtualInterrupt from overwriting the previous acknowledgement, which may need to be reported through the external interrupt controller. Input Parameters DestinationPartition specifies the partition. InterruptControl specifies the type of the virtual interrupt that should be asserted, its destination mode and whether the virtual interrupt is edge or level triggered.
Index A AccessPartitionId in MSR 7 See Partition State C CPUID Instruction 5 Microsoft leafs 6 6 6 6 6 7 8 standard leafs 5 5 5 CreatePartitions in MSR 7 E Endianness 4 enum 3 Exceptions #GP AccessApicMsrs privilege 22 AccessHypercallMsrs privilege 22 AccessSynicMsrs privilege 22 AccessSyntheticTimers privilege 22 AccessVpIndex privilege 22 AccessVpRuntime privilege 22 feature not present 60 hypercall interface 16 read from APIC EOI MSR 116 reference counter MSR 152 segment registers 74 write to SVERSION MSR 128 #MC SIM and SIEF pages 130 statistics page mappings 207 #UD hypercall environment 12 MONITOR instruction 82 MWAIT instruction 82 double/triple faults 96 F Finalized See Partition State Finalizing See Partition State G See guest physical address guest physical address 3 guest virtual address 3 GVA See guest virtual address H HV_ADDRESS_SPACE_ID 102 102 HV_FLUSH_FLAGS 102 HV_GPA 3 HV_GPA_PAGE_NUMBER 3 HV_GVA 3 HV_GVA_PAGE_NUMBER 3 HV_INTERCEPT_ACCESS_TYPE_MASK 61 HV_INTERCEPT_DESCRIPTOR 61 HV_INTERCEPT_PARAMETERS 61 HV_INTERCEPT_TYPE 60 HV_LOGICAL_PROCESSOR_INDEX 37 HV_LOGICAL_PROCESSOR_POWER_STATE 37 HV_MAP_GPA_FLAGS 53, 171 HV_NANO100_TIME 38 HV_PAGE_SIZE 3 HV_PARTITION_ID 19 HV_PARTITION_ID_INVALID 19 HV_PARTITION_PRIVILEGE_MASK 21 HV_PARTITION_PROPERTY 20 HV_REGISTER_NAME 69 70 HV_SCHEDULING_CONTROL 176 HV_SPA 3 HV_SPA_PAGE_NUMBER 3 HV_STATS_OBJECT_IDENTITY 210 HV_STATS_OBJECT_TYPE 209 HV_STATUS 3 HV_TRACE_BUFFER_HEADER 187 HV_TRACE_BUFFER_STATE 186 HV_TRACE_TYPE 186 HV_VP_INDEX 66 HV_X64_PAGE_SIZE 3 HvAllocateTraceBufferGroup 194, 203 120 HvClearLogicalProcessorRunTimeGroup 40 HvClearVirtualInterrupt 122