M.Tech VLSI 2016-2017 S.No PROJECT NAME Design IEEE 1 Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding Front End 2016 2 Floating-Point Butterfly Architecture Based on Binary Representation Front End 2016 3 Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic Front End 2016 4 A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Front End 2016 5 A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits Front End 2016 6 On Efficient Retiming of Fixed-Point Circuits Front End 2016 7 Concept, Design, and Implementation of Reconfigurable CORDIC Front End 2016 8 Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks Front End 2016 9 Low-Power Parallel Chien Search Architecture Using a Approach Front End 2016 10 An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24,12) Extended Golay Code Front End 2016 11 Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression Front End 2016 12 Multiple Constant Multiplication Algorithm for High-Speed and Low-Power Design Front End 2016 13 Design and Analysis of Inexact Floating-Point Adders Front End 2016 14 A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT Front End 2016 15 A Modified Partial Product Generator for Redundant Binary Multipliers Front End 2016 16 A Cellular Network Architecture With Polynomial Weight Functions Front End 2016 17 A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO Front End 2016 18 High Speed Hybrid Double Multiplication Architectures Using New Serial-Out Bit- Level Mastrovito Multipliers Front End 2016 19 Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication Front End 2016 20 A High-Speed FPGA Implementation of an RSD-Based ECC Processor Front End 2016
Basis For FPGA And ASIC Implementations 47 A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable Orthogonal Approximation Of DCT Front End 2015 48 Fully Reused VLSI Architecture Of Fm0/Manchester Encoding Using Sols Technique For DSRC Applications Front End 2015 49 Obfuscating DSP Circuits Via High-Level Transformations Front End 2015 50 Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit Encoding Front End 2015 51 Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic Front End 2015 52 Fault Tolerant Parallel Filters Based On Error Correction Codes Front End 2015 53 A Synergetic Use Of Bloom Filters For Error Detection And Correction Front End 2015 54 Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block Front End 2015 55 Recursive Approach To The Design Of A Parallel Self-Timed Adder Front End 2015 56 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic Front End 2015 57 Fine-Grained Critical Path Analysis And Optimization For Area-Time Efficient Realization Of Multiple Constant Multiplications Front End 2015 58 Scan Test Bandwidth Management For Ultralarge-Scale System-On-Chip Architectures Front End 2015 59 Low-Power And Area-Efficient Shift Register Using Pulsed Latches Front End 2015 60 Low-Power Programmable PRPG With Test Compression Capabilities Front End 2015 61 One Minimum Only Trellis Decoder For Non – Binary Low - Density Parity - Check Codes Front End 2015 62 A Low Complexity Scaling Method For The Lanczos Kernel In Fixed-Point Arithmetic Front End 2015 63 Low-Latency High-Throughput Systolic Multipliers Over GF(2m) For NIST Recommended Pentanomials Front End 2015 64 Efficient Coding Schemes For Fault-Tolerant Parallel Filters Front End 2015 65 Partially Parallel Encoder Architecture For Long Polar Codes Front End 2015 66 Novel Block-Formulation And Area-Delay - Efficient Reconfigurable Interpolation Filter Architecture For multi - Standard SDR Applications Front End 2015 67 Algorithm And Architecture For A Low-Power Memory Based On Sparse Clustered Networks Back End 2015 68 A Self-Powered High-Efficiency Rectifier With Automatic Resetting Of Transducer Capacitance In Piezoelectric Energy Harvesting Systems Back End 2015 69 Mixing Drivers In Clock-Tree For Supply Noise Back End 2015