yusuke1997/dblp-id-title huggingface dataset:
An FPGA-Based Implementation of Multi-Alphabet Arithmetic Coding
Online Built-In Self-Test of High Switching Frequency DC-DC Converters Using Model Reference Based System Identification Techniques
Power-Scaling Output-Compensated Three-Stage OTAs for Wide Load Range Applications
Theory and Design of a Quadrature Analog-to-Information Converter for Energy-Efficient Wideband Spectrum Sensing
Hardware Architecture of IOTA Pulse Shaping Filters for Multicarrier Systems
Some Properties of Multiple-Antenna-Port and Multiple-User-Port Antenna Tuners
Analysis of a Switched-Capacitor Second-Order Delta-Sigma Modulator Using Integrator Multiplexing
Numerical Design Optimization Methodology for Wideband and Multi-Band Inductively Degenerated Cascode CMOS Low Noise Amplifiers
An FPGA Implementation of MML-DFE for Spatially Multiplexed MIMO Systems
Untrimmed BGR of 1.1% $3\sigma$ Based on Dynamic-Biased Op Amp With Reduced ${V} _{\rm off}$
A Regulated Charge Pump for Tunneling Floating-Gate Transistors
Hardware Implementation Overhead of Switchable Matching Networks
Chaotic and subharmonic oscillations of a nonlinear power system
A Low-Power Visual-Horizon Estimation Chip
Implementation and Testing of High-Speed CMOS True Random Number Generators Based on Chaotic Systems
Analysis of a Class-E Power Amplifier With Shunt Filter for Any Duty Ratio
ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit
Delay-dependent exponential stability of delayed neural networks with time-varying delay
A 5 Gb/s Automatic Within-Pair Skew Compensator for Differential Data in 0.13 muhboxm CMOS
A 124-Gb/s Decoder for Generalized Integrated Interleaved Codes
Low-Complexity Reconfigurable DCT-V Architecture
Stochastic Stability Condition for the Extended Kalman Filter With Intermittent Observations
Consensus Conditions for Multi-Agent Systems Under Delayed Information
Accurate and Fast On-Wafer Test Circuitry for Device Array Characterization in Wafer Acceptance Test
Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM
A Miniaturized 0.003 mm 2 PNP-Based Thermal Sensor for Dense CPU Thermal Monitoring
Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process
Stabilization of Bilinear Power Converters by Affine State Feedback Under Input and State Constraints
CAVLC Encoder Design for Real-Time Mobile Video Applications
Power Supply Pads Assignment for Maximum Timing Yield
An Efficient Delay Model for MOS Current-Mode Logic Automated Design and Optimization
Evidence for self-organized criticality in a time series of electric power system blackouts
Electrothermal Design Procedure to Observe RF Circuit Power and Linearity Characteristics With a Homodyne Differential Temperature Sensor
Rigorous analysis of delta-sigma modulators for fractional-N PLL frequency synthesis
Mantissa-Exponent-Based Tone Mapping for Wide Dynamic Range Image Sensors
Robust Multikernel Maximum Correntropy Filters
Built-in Self-Calibration Circuit for Monotonic Digitally Controlled Oscillator Design in 65-nm CMOS Technology
Qualitative analysis for recurrent neural networks with linear threshold transfer functions
Warped discrete cosine transform-based noisy speech enhancement
A 14-Band Low-Complexity and High-Performance Synthesizer Architecture for MB-OFDM Communication
A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion
Bulk Voltage Trimming Offset Calibration for High-Speed Flash ADCs
Loss-free complex impedance network elements
A 1.5-V 50-MHz pseudodifferential CMOS sample-and-hold circuit with low hold pedestal
High Power Amplifier Based on a Transformer-Type Power Combiner in CMOS Technology
Deadbeat Dissipative FIR Filtering
A Fast Algorithm Based on SRFFT for Length N = q × 2 m DFTs
Global Asymptotical Synchronization of Chaotic Lur'e Systems Using Sampled Data: A Linear Matrix Inequality Approach
Normalized Subband Adaptive Filtering Algorithm With Reduced Computational Complexity
A CMOS Seawater Salinity to Digital Converter for IoT Applications of Fish Farms
An Enhanced Frequency Ratio Dual Band Balun Augmented With High Impedance Transformation
Time Division Multiplexing Front-Ends for Multiantenna Integrated Wireless Receivers
A Crystal-Less Self-Synchronized Bit-Level Duty-Cycled IR-UWB Transceiver System
IC Random Number Generator Exploiting Two Simultaneous Metastable Events of Tetrahedral Oscillators
A Separable Maximum Correntropy Adaptive Algorithm
A 1.0-8.3 GHz Cochlea-Based Real-Time Spectrum Analyzer With Δ-Σ-Modulated Digital Outputs
Analytical Delay Model Considering Variability Effects in Subthreshold Domain
Pathological Equivalents of Fully-Differential Active Devices for Symbolic Nodal Analysis
Ultralow-Power Optical CDR for Integrated Photovoltaic Energy-Harvesting Sensors
A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs
Multi-Agent Bipartite Tracking Control Over General Cooperative-Hostile Networks
A Power-Efficient Reconfigurable OTA-C Filter for Low-Frequency Biomedical Applications
A 29.5 dBm Class-E Outphasing RF Power Amplifier With Efficiency and Output Power Enhancement Circuits in 45nm CMOS
A Cyclic Vernier TDC for ADPLLs Synthesized From a Standard Cell Library
RF I/Q Downconverter With Gain/Phase Calibration
A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist
A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of -252.5 dB
Design and Performance Analysis of Multilevel Code-Shifted $M$ -Ary Differential Chaos Shift Keying System
New Compact CMOS Li-Ion Battery Charger Using Charge-Pump Technique for Portable Applications
High-speed and high-precision current winner-take-all circuit
Robustness of Coherence in Noisy Scale-Free Networks and Applications to Identification of Influential Spreaders
Configurable Folded IIR Filter Design
Differential current-mode tunable wave active filters based on single-ended wave port terminators
A Sizing Methodology for On-Chip Switched-Capacitor DC/DC Converters
A Novel VLSI DHT Algorithm for a Highly Modular and Parallel Architecture
On Learning With Nonlinear Memristor-Based Neural Network and its Replication
A Charge-Domain Switched-G m -C Band-Pass Filter Using Interleaved Semi-Passive Charge-Sharing Technique
A continuous-time ΣΔ Modulator with reduced sensitivity to clock jitter through SCR feedback
Robust Sliding Mode Control: An Event-Triggering Approach
Generalized Average Method for Time-Invariant Modeling of Inverters
Bi-Minimax Design of Even-Order Variable Fractional-Delay FIR Digital Filters
An ON-OFF orientation selective address event representation image transceiver chip
Pseudo-Type-III Compensation Integrated in a Voltage-Mode Buck Regulator
Known-Plaintext Attack to Two Cryptosystems Based on the BB Equation
A Behavioral Model of Digital Resistive Switching for Systems Level DNN Acceleration
Semi-Supervised Learning Based on Hybrid Neural Network for the Signal Integrity Analysis
A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits
Design of a CMOS Potentiostat Circuit for Electrochemical Detector Arrays
Dynamics and Stability Issues of a Single-Inductor Dual-Switching DC-DC Converter
Removing Muscle Artifacts From EEG Data via Underdetermined Joint Blind Source Separation: A Simulation Study
Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in a Scan Chain
Generalized neural network for nonsmooth nonlinear programming problems
Kickback noise reduction techniques for CMOS latched comparators
A 20-Mb/s Pulse Harmonic Modulation Transceiver for Wideband Near-Field Data Transmission
A Switching Sequence for Unary Digital-to-Analog Converters Based on a Knight's Tour
Observer-Based Asynchronous Fault Detection for Conic-Type Nonlinear Jumping Systems and its Application to Separately Excited DC Motor
A 0.49-13.3 MHz Tunable Fourth-Order LPF with Complex Poles Achieving 28.7 dBm OIP3
Digital Complex Delta-Sigma Modulators With Highly Configurable Notches for Multi-Standard Coexistence in Wireless Transmitters
Anti-Disturbance Bumpless Transfer Control for Switched Systems With its Application to Switched Circuit Model
Discrete Lattice Wavelet Transform
Miniature Dual-Band Quadrature Coupler With Arbitrary Power Division Ratios Over the Two Bands
Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing
An Ultra-Low-Power Long Range Battery/Passive RFID Tag for UHF and Microwave Bands With a Current Consumption of 700 nA at 1.5 V
An Area and Energy Efficient Ultra-Low Voltage Level Shifter With Pass Transistor and Reduced-Swing Output Buffer in 65-nm CMOS
Improving Time-Efficiency of Fault-Coverage Simulation for MOS Analog Circuit
Over-Current Protection for Power Packet Dispatching System
An Efficient Sinusoid-Like Pseudo Random Sequence Modulator/Demodulator System With Reduced Adjacent Channel Leakage and High Rejection to Random and Systematic Interference
A 60-V, >225°C Half-Bridge Driver for Piezoelectric Acoustic Transducer, on SOI CMOS
Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation
A Novel XOR/XNOR Structure for Modular Design of QCA Circuits
A 100-nW 9.1-ENOB 20-kS/s SAR ADC for Portable Pulse Oximeter
Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design
Sampled-Data Modeling of Hysteretic Converters Accounting for Intracycle Waveform Propagation
The design of digital all-pass filters using second-order cone programming (SOCP)
A 40-GHz Flip-Flop-Based Frequency Divider
A Charge Recycling SAR ADC With a LSB-Down Switching Scheme
Systematic Design Centering of Continuous Time Oversampling Converters
Parametric adaptive control of multimachine power systems with nonlinear loads
Binary-Weighted Digital-to-Analog Converter Design Using Floating-Gate Voltage References
A Single Slope ADC With Row-Wise Noise Reduction Technique for CMOS Image Sensor
A Power-Efficient Voltage Upconverter for Embedded EEPROM Application
Current-Mode Phase-Locked Loops With CMOS Active Transformers
A 1.2V-to-0.4V 3.2GHz-to-14.3MHz Power-Efficient 3-Port Register File in 65-nm CMOS
A burst-mode word-serial address-event link-II: receiver design
Arithmetic Unit for Finite Field GF(2 m )
Strength-Reduced Parallel Chien Search Architecture for Strong BCH Codes
Hankel-Norm Approximation of IIR by FIR Models: A Constructive Method
Numerical Jitter Minimization for PLL-Based FMCW Radar Systems
Joint Sparsity and Order Optimization Based on ADMM With Non-Uniform Group Hard Thresholding
Design of Nonlinear Filters Using Affine Projection Algorithm Based Exact and Approximate Adaptive Exponential Functional Link Networks
Thermal-Noise-Canceling Switched-Capacitor Circuit
Automated Deep Neural Learning-Based Optimization for High Performance High Power Amplifier Designs
Area-Efficient Configurable High-Throughput Signal Detector Supporting Multiple MIMO Modes
Periodic Properties of Chebyshev Polynomial Sequences Over the Residue Ring ℤ/2 k ℤ
An Intrusion Detection System for Cyber Attacks in Wireless Networked Control Systems
Design and evaluation of current-mode image sensors in CMOS-technology
Dynamical Analysis of Full-Range Cellular Neural Networks by Exploiting Differential Variational Inequalities
Improvement of pixel electrode circuit for active-matrix OLED by application of reversed-biased voltage
A CMOS Rectifier With a Cross-Coupled Latched Comparator for Wireless Power Transfer in Biomedical Applications
CMOS Differential Logic Family With Conditional Operation for Low-Power Application
A Low-Power Synchronizer for Multistandard Wireless Communications
A self-driven active clamp forward converter using the auxiliary winding of the power transformer
Incremental Delta-Sigma ADCs: A Tutorial Review
An Unbounded Frequency Detection Mechanism for Continuous-Rate CDR Circuits
A CMOS VGA With DC Offset Cancellation for Direct-Conversion Receivers
Comments on "Model-Order Reduction Using Variational Balanced Truncation With Spectral Shaping"
Fast Digital Clock Calibration of a Differential 6.4 Gb/s/pin Bidirectional Asymmetric Memory Interface
Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self-Timing
Exploiting Gate Leakage in Deep-Submicrometer CMOS for Input Offset Adaptation
Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2 m ) Based on Irreducible All-One Polynomials
Second-Order Intermodulation in Current-Commutating Passive FET Mixers
Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM
Grouped signed power-of-two algorithms for low-complexity adaptive equalization
High-Throughput Low-Complexity Unified Multipliers Over GF(2 m ) in Dual and Triangular Bases
Power Bounds and Energy Efficiency in Incremental ΔΣ Analog-to-Digital Converters
Rate-Dependent Mixed H 2 / H infty Filter Design for Parameter-Dependent State Delayed LPV Systems
Matrix Inductor With DC-Bias Effect Reduction Capability for GaN-Based DC-DC Boost Converter
A Low-Power CMOS Image Sensor With Area-Efficient 14-bit Two-Step SA ADCs Using Pseudomultiple Sampling Method
Design Methodology to Explore Hybrid Approximate Adders for Energy-Efficient Image and Video Processing Accelerators
A Sizing Methodology for Rise-Time Minimization of Dickson Charge Pumps With Capacitive Loads
250-mV Supply Subthreshold CMOS Voltage Reference Using a Low-Voltage Comparator and a Charge-Pump Circuit
A Model for MOS Diodes With V th Cancellation in RFID Rectifiers
A High-Sensitivity and Low-Walk Error LADAR Receiver for Military Application
Realization of Biquadratic Impedances as Five-Element Bridge Networks
Enhanced Belief Propagation Decoder for 5G Polar Codes With Bit-Flipping
A High-Efficiency CMOS DC-DC Converter With 9-µs Transient Recovery Time
Design of an FFT/IFFT Processor for MIMO OFDM Systems
Generalized Method of Analog Circuit Characteristic Function Analysis
Hard Bounds on the Probability of Performance With Application to Circuit Analysis
A Time-Constant Calibrated Phase-Locked Loop With a Fast-Locked Time
11.25-ms-Group-Delay and Low-Complexity Algorithm Design of 18-Band Quasi-ANSI S1.11 1/3 Octave Digital Filterbank for Hearing Aids
Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters
Robust Stabilization of Complex Switched Networks With Parametric Uncertainties and Delays Via Impulsive Control
CRT-Based High-Speed Parallel Architecture for Long BCH Encoding
Analysis of Phase Noise in Phase/Frequency Detectors
Implications of Passive Mixer Transparency for Impedance Matching and Noise Figure in Passive Mixer-First Receivers
Corrections to "Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference"
A Class of Proportional-Integral With Anti-Windup Controllers for DC-DC Buck Power Converters With Saturating Input
Compact Wide-Stopband Dual-Band Balanced Filter Using an Electromagnetically Coupled SIR Pair With Controllable Transmission Zeros and Bandwidths
A Low-Profile High-Efficiency Fast Battery Charger With Unifiable Constant-Current and Constant-Voltage Regulation
A High Frame Rate Wearable EIT System Using Active Electrode ASICs for Lung Respiration and Heart Rate Monitoring
A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency
Effective Capacitance of Inductive Interconnects for Short-Circuit Power Analysis
Wire Optimization for Multimedia SoC and SiP Designs
RNS-To-Binary Converter for a New Three-Moduli Set {2 n+1 -1, 2 n , 2 n -1}
Stabilizing unstable equilibria of chaotic systems from a State observer approach
Pinning Control Design for the Synchronization of Two Coupled Boolean Networks
A Second-Order Lowpass Parameter-Varying Filter Based on the Interconnection of First-Order Stages
Approximate Multipliers With Dynamic Truncation for Energy Reduction via Graceful Quality Degradation
A New IIP2 Enhancement Technique for CMOS Down-Converter Mixers
Sufficient and necessary conditions for global exponential stability of discrete-time recurrent neural networks
Tunable FIR and IIR Fractional-Delay Filter Design and Structure Based on Complex Cepstrum
A Flexible DSP Architecture for MIMO Sphere Decoding
A Power-Efficient Signal-Specific ADC for Sensor-Interface Applications
Temperature-Compensated β-Multiplier Current Reference Circuit
120-GHz 8-Stage Broadband Amplifier With Quantitative Stagger Tuning Technique
Color Superresolution Reconstruction and Demosaicing Using Elastic Net and Tight Frame
Self-Tuned Class-D Audio Amplifier With Post-Filter Digital Feedback Implemented on Digital Signal Controller
Probability-Dependent Gain-Scheduled Filtering for Stochastic Systems With Missing Measurements
A High-Performance Elliptic Curve Cryptographic Processor for General Curves Over GF(p) Based on a Systolic Arithmetic Unit
TIME - Tunable Inductors Using MEmristors
A Stochastic Model of Cascading Failure Dynamics in Communication Networks
A CMOS-Compatible Spectrum Analyzer for Cognitive Radio Exploiting Crosscorrelation to Improve Linearity and Noise Performance
Layered Approx-Regular LDPC: Code Construction and Encoder/Decoder Design
From Zhang Neural Network to Newton Iteration for Matrix Inversion
A New Constructive Procedure for 2-D Coprime Realization in Fornasini-Marchesini Model
A Resource-Efficient Multiplierless Systolic Array Architecture for Convolutions in Deep Networks
A Proportionate Diffusion LMS Algorithm for Sparse Distributed Estimation
An analysis of global asymptotic stability of delayed Cohen-Grossberg neural networks via nonsmooth analysis
A Flexible Load-Independent Multi-Output Wireless Power Transfer System Based on Cascaded Double T-Resonant Circuits: Analysis, Design and Experimental Verification
A Multi-Cycle Switching Technique for Efficient Ultrasonic Wireless Power Delivery
Controller and Observer design for Chaotic Systems: A Vector Based Contraction Approach
Guest Editorial Special Section on 2009 IEEE System-on-Chip Conference
Optimal Robustness in Power Grids From a Network Science Perspective
Modeling and Analysis of Class-E Amplifier With a Shunt Inductor at Sub-Nominal Operation for Any Duty Ratio
A Continuous-Time ΔΣ ADC Utilizing Time Information for Two Cycles of Excess Loop Delay Compensation
A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector
A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions
A Comparative Analysis of Adaptive Digital Predistortion Algorithms for Multiple Antenna Transmitters
A Compact Low-Power Biquad for Active- RC Complex Filter
Power and Area Efficient Transimpedance Amplifier Driving Large Capacitive Loads Based on Modified RGC Structure
Blind adaptive equalization of mismatch errors in a time-interleaved A/D converter system
Adaptive Matrix Design for Boosting Compressed Sensing
Chaos Control in Duffing System Using Impulsive Parametric Perturbations
Real Discrete Fractional Fourier, Hartley, Generalized Fourier and Generalized Hartley Transforms With Many Parameters
A Bias-Bounded Digital True Random Number Generator Architecture
Noise figure of digital communication receivers-revisited
Realization of High Octave Decomposition for Breast Cancer Feature Extraction on Ultrasound Images
Nonlinearity correction for multibit ΔΣ DACs
MEMS Closed-Loop Control Incorporating a Memristor as Feedback Sensing Element
A Double-Balanced Quadrature-Input Quadrature-Output Regenerative Frequency Divider for UWB Synthesizer Applications
A Low-Voltage Micropower Digital Class-D Amplifier Modulator for Hearing Aids
Optimizing the Identification of Digital Predistorters for Improved Power Amplifier Linearization Performance
A 62.5-625-MHz Anti-Reset All-Digital Delay-Locked Loop
Interconnection of state space structures and wave digital filters
Stability Enhancement of One-Cycle Controlled Buck-Boost Converters With a Composite Function Embedded
A Current Injection Built-In Test Technique for RF Low-Noise Amplifiers
Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter
Feedback Dissipativity and Stabilization for Switched Positive Systems With a Combined Switching Law
Performance Analysis of Energy-Efficient BBPLL-Based Sensor-to-Digital Converters
Low Complexity VLSI Architecture Design Methodology for Wigner Ville Distribution
Impact of Sampling Clock Phase Noise on Sigma Delta Frequency Discriminators
Minimax design of adjustable-bandwidth linear-phase FIR filters
A new CMOS electronically tunable current conveyor and its application to current-mode filters
Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets
Synthesis Design of Chebyshev Wideband Band-Pass Filters With Independently Reconfigurable Lower Passband Edge
Optimal transmission frequency for ultralow-power short-range radio links
A High-Speed and Ultra Low-Power Subthreshold Signal Level Shifter
On the VLSI Implementation of Adaptive-Frequency Hopf Oscillator
On Synchronization Errors in Networked Feedback Systems
A Novel Window Function for Memristor Model With Application in Programming Analog Circuits
Novel One-Dimensional Sampling Method to Calculate Two-Dimensional Diamond-Shaped Discrete Frequency Distributions
A 15-V Bidirectional Ultrasound Interface Analog Front-End IC for Medical Imaging Using Standard CMOS Technology
A novel Fourier series time function for modeling and simulation of PWM
A Distortion Cancelation Technique With the Recursive DFT Method for Successive Approximation Analog-to-Digital Converters
Transient Analysis of Signed LMS Algorithms With Cyclostationary Colored Gaussian Inputs
Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation
Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler
An Energy-Efficient ECG Processor With Weak-Strong Hybrid Classifier for Arrhythmia Detection
Enhanced Single-Stage Folded Cascode OTA Suitable for Large Capacitive Loads
A New Parametric Adaptive Source Domain Method for Sound Field Synthesis
A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation
Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM
Guest Editorial Special Section on the 2016 IEEE Latin American Symposium on Circuits and Systems (LASCAS 2016)
A 10-Gb/s, 107-mW Double-Edge Pulsewidth Modulation Transceiver
IIR Filter Adaptation Using Branch-and-Bound: A Novel Approach
Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell
Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits
A CMOS IR-UWB Transceiver Design for Contact-Less Chip Testing Applications
Wide-band system identification using multiple tones with allpass filters and square-law detectors
Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC
Substrate Integrated Waveguide Multi-Channel Filtering Crossover With Extended Channel Number and Controllable Frequencies
A Systematic Algorithm for the Design of Lattice Wave Digital Filters With Short-Coefficient Wordlength
Global exponential stability and periodicity of recurrent neural networks with time delays
Numerically efficient optimal design of cosine-modulated filter banks with peak-constrained least-squares behavior
Analysis of Spatiotemporal Patterns in an Infinite-Dimensional Electromagnetic System
Finite-Time Consensus for Power Regulation of Parallel PV Grid-Connected Inverters
Device Noise in Continuous-Time Oversampling Converters
A Multiband Transceiver System in 45-nm CMOS for Extended Data Rate through Notchy Wireline Channels
Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers
Dynamic Braess's Paradox in Complex Communication Networks
Scalable Networks-on-Chip Interconnected Architecture for Astrocyte-Neuron Networks
On the Effects of Mismatch on Quadrature Accuracy in Tapped-Capacitor Load Independent Quadrature LC-Oscillators
An On-Chip Thermal Monitoring System With a Temperature Sensing Area of 52 µm 2 in 180-nm CMOS