yusuke1997/dblp-id-title huggingface dataset:
Design Space Exploration of Deeply Nested Loop 2D Filtering and 6 Level FSBM Algorithm Mapped onto Systolic Array
Computer-Aided Testing Systems: Evaluation and Benchmark Circuits
Resolution Enhancement in I DDQ Testing for Large ICs
Integration of SPICE with TEK LV500 ASIC Design Verification System
BIST Analysis of an Embedded Memory Associated Logic
Analytical Engines are Unnecessary in Top-down Partitioning-based Placement
Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits
First Steps in Creating Online Testable Reversible Sequential Circuits
Pioneer: A New Tool for Coding of Multi-Level Finite State Machines Based on Evolution Programming
Efficient Hardware Trojan Detection with Differential Cascade Voltage Switch Logic
Hierarchy Restructuring for Hierarchical LVS Comparison
The Cost of Adaptivity and Virtual Lanes in a Wormhole Router
Novel Single and Double Output TSC CMOS Checkers for m -out-of- n Codes
Monte Carlo Simulation of Non-Local Transport Effects in Strained Si on Relaxed Si 1 - x Ge x Heterostructures
Cellular Automaton Study of Time-Dynamics of Avalanche Breakdown in IMPATT Diodes
An Analytic Expression of Thermal Diffusion Coefficient for the Hydrodynamic Simulation of Semiconductor Devices
Exact Output Response Computation of RC Interconnects Under General Polynomial Input Waveforms
Simulation of Optical Excitation to and Emission from Electron Fabry-Perot States Subject to Strong Inelastic Scattering
A Hydrodynamic Model for Transport in Semiconductors without Free Parameters
Testability-Driven Layout of Combinational Circuits
Numerical Simulation of Quantum Logic Gates Based on Quantum Wires
Fast Algorithms to Partition Simple Rectilinear Polygons
Tutorial on VLSI Partitioning
2D Finite Element Method Simulation of Lateral Resonant Tunneling Devices
Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance
New Algorithmic Techniques for Complex EDA Problems
Wave Function Scarring Effects in Open Ballistic Quantum Cavities
Maximizing Memory Data Reuse for Lower Power Motion Estimation
Register-Transfer Synthesis of Pipelined Data Paths
Performance and Area Optimization of VLSI Systems Using Genetic Algorithms
A Modified Approach to Test Plan Generation for Combinational Logic Blocks
A Percolative Approach to Reliability of Thin Film Interconnects and Ultra-thin Dielectrics
Semi-classical Limit in a Semiconductor Superlattice
An Edge-endpoint-based Configurable Hardware Architecture for VLSI Layout Design Rule Checking
An Improved Ionized Impurity Scattering Model for Monte Carlo Calculations
Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits
An Analytical, Temperature-dependent Model for Majority- and Minority-carrier Mobility in Silicon Devices
Wigner Function Methods in Modeling of Switching in Resonant Tunneling Devices
Timing-Driven Circuit Implementation
A New Method to Recover Vectorial Electric Fields and Current Densities from Unstructured Meshes
An Efficient Solution Scheme for the Spherical-Harmonics Expansion of the Boltzmann Transport Equation Applied to Two-Dimensional Devices
FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW
Signal Coding and CMOS Gates for Combinational Functional Blocks of Very Deep Submicron Self-checking Circuits
Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts
Hardware Acceleration of Beamforming in a UWB Imaging Unit for Breast Cancer Detection
Modeling Light-Extraction Characteristics of Packaged Light-Emitting Diodes
The Design of Low Noise Amplifiers in Deep Submicron CMOS Processes: A Convex Optimization Approach
CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization
Theory of Electron Transport in Small Semiconductor Devices Using the Pauli Master Equation
New Approach to Hot Electron Effects in Si-MOSFETs Based on an Evolutionary Algorithm Using a Monte Carlo Like Mutation Operator
Verification of Mixed-Signal Systems with Affine Arithmetic Assertions
Oscillation-Based Test Applied to a Wideband CCII
Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks
Additive Decomposition Applied to the Semiconductor Drift-Diffusion Model
Integrated Test Solutions for a System Design Environment
An Efficient and Fast Algorithm for Routing Over the Cells
Formulation of the Boltzmann Equation as a Multi-Mode Drift-Diffusion Equation
Applicability of the High Field Model: A Preliminary Numerical Study
Hybrid Particle-based Full-band Analysis of Ultra-small MOS
3D Modelling of Fluctuation Effects in Highly Scaled VLSI Devices
A Programmable Max-Log-MAP Turbo Decoder Implementation
A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation
Using Signal Envelope Detection for Online and Offline RF MEMS Switch Testing
PGEN: A Novel Approach to Sequential Circuit Test Generation
A Programmable Hardware Cellular Automaton: Example of Data Flow Transformation
General Decomposition and Its Use in Digital Circuit Synthesis
Post-Mapping Transformations for Low-Power Synthesis
VLSI Architectures for Image Interpolation: A Survey
Characterization of Catastrophic Faults in Reconfigurable Systolic Arrays
A Discrete Event System Approach to Online Testing of Speed Independent Circuits
A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
Embedded Parity and Two-Rail TSC Checkers with Error-Memorizing Capability
Low Cost Design of a Hybrid Architecture of Integer Inverse DCT for H.264, VC-1, AVS, and HEVC
Frequency Domain Kernel Estimation for 2nd-order Volterra Models Using Random Multi-tone Excitation
Lossless and Low-Power Image Compressor for Wireless Capsule Endoscopy
A Case Study of Self-Checking Circuits Reliability
Electrostatic Formation of Coupled Si/SiO 2 Quantum Dot Systems
High-Performance Timing-Driven Rank Filter
A Pipelined and Parallel Architecture for Quantum Monte Carlo Simulations on FPGAs
A Simple Model for the Quantum Hydrodynamic Simulation of Electron Transport in Quantum Confined Structures in the Presence of Vortices
One-Dimensional Analysis of Subthreshold Characteristics of SOI-MOSFET Considering Quantum Mechanical Effects
Architectural Power Estimation Based on Behavior Level Profiling
A General Approach to Boolean Function Decomposition and its Application in FPGABased Synthesis
Weak Limits of the Quantum Hydrodynamic Model
Observation of Anomalous Negative Differential Resistance in Diode Breakdown Simulation Using Carrier Temperature Dependent Impact Ionization
Strain-Dependence of Electron Transport in Bulk Si and Deep-Submicron MOSFETs
On Channel Routing Problems With Interchangeable Terminals
Design Procedure Based on VHDL Language Transformations
An Efficient Algorithm for the Split K-Layer Circular Topological Via Minimization Problem
A High-Efficiency Monolithic DC-DC PFM Boost Converter with Parallel Power MOS Technique
SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection
Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits
Approximation of the BTE by a Relaxation-time Operator: Simulations for a 50 nm-channel Si Diode
Foundations for Applications of Gibbs Derivatives in Logic Design and VLSI
Study of Electronic Transport in Tunneling Devices Using an Incoherent Superposition of Time Dependent Wave Packets
Impact Ionization and Hot-Electron Injection Derived Consistently from Boltzmann Transport
Simulation of Quantum-Dot Structures in Si/SiO 2
Cellular Automata Studies of Vertical Silicon Devices
A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic
A Backward Monte Carlo Method for Simulation of the Electron Quantum Kinetics in Semiconductors
Moving Adaptive Unstructured 3-D Meshes in Semiconductor Process Modeling Applications
Quantum Monte Carlo Study of Silicon Self-interstitial Defects
Redundant Logic Insertion and Latency Reduction in Self-Timed Adders
Placement with Incomplete Data
Memory Chips with Adjustable Configurations
FPGA Partitioning with Complex Resource Constraints
Monte Carlo Simulation of a Submicron MOSFET Including Inversion Layer Quantization
Ultra-small MOSFETs: The Importance of the Full Coulomb Interaction on Device Characteristics
Non-linear Hybrid Cellular Automata as Pseudorandom Pattern Generators for VLSI Systems
A Fine Grain Configurable Logic Block for Self-checking FPGAs
Scalability Analysis for Conservative Simulation of Logical Circuits
Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis
Microscopic Theory of Transconductivity
Classical and Quantum Hydrodynamic Device Models and Energy Transport
Moment Equations with Maximum Entropy Closure for Carrier Transport in Semiconductor Devices: Validation in Bulk Silicon
Logic Synthesis for a Regular Layout
COPAS: A New Algorithm for the Partial Input Encoding Problem
Semiclassical Analysis of Discretizations of Schrödinger-type Equations
Novel Receiver Architecture for LTE-A Downlink Physical Control Format Indicator Channel with Diversity
Routability Crossing Distribution and Floating Pin Assignment for T -type Junction Region
Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors
Exploiting Data-dependencies in Ultra Low-power DSP Arithmetic
Point DCT VLSI Architecture for Emerging HEVC Standard
Electron Mobility and Monte Carlo device simulation of MOSFETs
Simulation of Enhanced Interface Trapping Due to Carrier Dynamics in Warped Valence Bands in SiGe Devices
νMOS-based Sorter for Arithmetic Applications
Partial Reset: An Alternative DFT Approach
Two-dimensional Modelling of HEMTs Using Multigrids with Quantum Correction
Shell-Filling Effects in Circular Quantum Dots
Testing and Diagnosing Dynamic Reconfigurable FPGA
Corrigendum to "High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability"
Identification of Disjoint Bi-decompositions in Boolean Functions through Walsh Spectrum
A New Theory for Testability-Preserving Optimization of Combinational Circuits
Statistical Estimation of the , Switching Activity in VLSI Circuits
Hardware Architectures for the Orthogonal and Biorthogonal Wavelet Transform
Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL
Effective Coupling Between Logic Synthesis and Layout Tools for Synthesis of Area and Speed-Efficient Circuits
Simulation of a Complete Chain of QCA Cells with Realistic Potentials
An Upstream Flux Splitting Method for Hydrodynamic Modeling of Deep Submicron Devices
Advanced Numerical Methods and Software Approaches for Semiconductor Device Simulation
Development of a Method for Determining the Dependence of the Electron Mobility on the Longitudinal-Electric Field in MOSFETs
An O(NlogN) Algorithm for Region Definition Using Channels/Switchboxes and Ordering Assignment
Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing
Empirical Study of Block Placement by Cluster Refinement
New Methods for the Construction of Test Cases for Partitioning Heuristics
A New Clustering Method Based on General Connectivity
Langevin Forces and Generalized Transfer Fields for Noise Modelling in Deep Submicron Devices
An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits
Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics
Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression
Timing Challenges for Very Deep Sub-Micron (VDSM) IC
Temperature Dependence of the Electron and Hole Scattering Mechanisms in Silicon Analyzed through a Full-Band, Spherical-Harmonics Solution of the BTE
Multiplication of Matrices With Different Sparseness Properties on Dynamically Reconfigurable Meshes
A New Concept for Solving the Boltzmann Transport Equation in Ultra-fast Transient Situations
The Deterministic Circuit Model for Noise Influence on the Averaged Transient Responses of Large-scale Nonlinear ICs Analyzed with Itô's Stochastic Differential Equations
I DDQ Detectable Bridges in Combinational CMOS Circuits
Coverage of Node Shorts Using Internal Access and Equivalence Classes
Evaluation of an Equivalent Hole Effective Mass for Si/SiGe Structures
Hardware Design Rule Checker Using a CAM Architecture
Selected Papers from the Midwest Symposium on Circuits and Systems
Comparative Power Analysis of an Adaptive Bus Encoding Method on the MBUS Structure
A Novel, Automatic Quality Control Scheme for Real Time Image Transmission
Sorting on Reconfigurable Meshes: An Irregular Decomposition Approach
Reduced Voltage Scaling in Clock Distribution Networks
A Combined Coefficient Segmentation and Block Processing Algorithm for Low Power Implementation of FIR Digital Filters
Zener Zap Anti-Fuse Trim in VLSI Circuits
Modeling of Shot Noise in Resonant Tunneling Structures
Quantum Contributions and Violations of the Classical Law of Mass Action
Surface Evolution During Semiconductor Processing
Optimal Detector Design for On-line Testing of Linear Analog Systems
Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic
Single-Electron Parametron
A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies
On Self-Checking Design of CMOS Circuits for Multiple Faults
Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs
Energy Minimization Under Area and Performance Constraints for Multimedia Applications Realized on Embedded Cores
Open Problems in Quantum Simulation in Ultra-Submicron Devices
Design and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless Receiver
Iterative Partitioning with Varying Node Weights
Low-Complexity Hardware Interleaver/Deinterleaver for IEEE 802.11a/g/n WLAN
Self-Consistent Solution of the Multi Band Boltzmann, Poisson and Hole-Continuity Equations
Tight Binding Simulation of Quantum Transport in Interband Tunneling Devices
Impact of Scaling on CMOS Chip Failure Rate, and Design Rules for Hot Carrier Reliability
Mixed-RKDG Finite Element Methods for the 2-D Hydrodynamic Model for Semiconductor Device Simulation
A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop
Simple Evaluation of the Nonlinearity Signature of an ADC Using a Spectral Approach
New Self-dual Circuits for Error Detection and Testing
A Comparison of Bit Serial and Bit Parallel DCT Designs
Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting
Symmetric and Programmable Multi-Chip Module for Low-Power Prototyping System
Applicability of the High Field Model: An Analytical Study Via Asymptotic Parameters Defining Domain Decomposition
Taking Thermal Considerations Into Account During High-Level Synthesis
CORDIC Architectures: A Survey
Chebyshev Bandpass Filter Using Resonator of Tunable Active Capacitor and Inductor
New "Irreducible Wedge" for Scattering Rate Calculations in Full-Zone Monte Carlo Simulations
Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey
Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits
Comparison of Single-Particle Monte Carlo Simulation with Measured Output Characteristics of an 0.1µm n-MOSFET
Network Delays and Link Capacities in Application-Specific Wormhole NoCs
Integration of the Density Gradient Model into a General Purpose Device Simulator
Line Search-Based Inverse Lithography Technique for Mask Design
Analysis of Q 0 -Independent Single-Electron Systems
A Contraction-based Ratio-cut Partitioning Algorithm
Advancements in Power Supply Current Testing
Fault Modeling of ECL for High Fault Coverage of Physical Defects
Spectral Transforms Calculation through Decision Diagrams
LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization
An lnterband Tunnel Oscillator: Intrinsic Bistability and Hysteresis of Trapped Hole Charge in a Double-Barrier Structure
Layout Modeling and Design Space Exploration in Pss1 System
Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design
Efficient Implementation of a Demultiplexer Based on a Multirate Filter Bank for the Skyplex Satellites DVB System
Multilevel Algorithms for Large-scope Molecular Dynamics Simulations of Nanostructures on Parallel Computers
Low-power Application-specific Parallel Array Multiplier Design for DSP Applications
Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs
Using Temporal and Functional Information in Crosstalk Aware Static Timing Analysis
Simulation of Submicron Silicon Diodes with a Non-Parabolic Hydrodynamical Model Based on the Maximum Entropy Principle
Simulation of a Single Electron Tunnel Transistor with Inclusion of Inelastic Macroscopic Quantum Tunneling of Charge
Basic Algorithms for the Asynchronous Reconfigurable Mesh
A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic
A VHDL Based Expert System for Hardware Synthesis
Design of MOS-translinear Multiplier/Dividers in Analog VLSI
RF Performance of Si/SiGe MODFETs: A Simulation Study
A Parallel Residue-to-binary Converter for the Moduli Set {2m-1, 220m+1, 221m+1, ..., 22km+1}
Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder
A Cache System Design for CMPs with Built-In Coherence Verification
A 3D Nonlinear Poisson Solver
The Combination of Equipment Scale and Feature Scale Models for Chemical Vapor Deposition Via a Homogenization Technique
Self-Consistent Scattering Calculation of Resonant Tunneling Diode Characteristics
Inclusion of Bandstructure and Many-Body Effects in a Quantum Well Laser Simulator
A Size-optimization Design for Variable Length Coding Using Distributed Logic
Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS
Boundary Condition for the Modeling of Open-circuited Devices in Non-equilibrium
Second Order Newton Iteration Method and Its Application to MOS Compact Modeling and Circuit Simulation
Monte Carlo Simulations of Intersubband Hole Relaxation in a GaAs/AlAs Quantum Well
Power Distribution Synthesis for VLSI
Cluster-based Parallel 3-D Monte Carlo Device Simulation
Parallel Jacobi EVD Methods on Integrated Circuits
Eight-Bit Semiflash A/D Converter
Design and Analysis of Radix-8/4/2 64b/32b Integer Divider Using COMPASS Cell Library
Rate Equation Modelling of Nonlinear Dynamics in Directly Modulated Multiple Quantum Well Laser Diodes
Effect of Reverse Body Bias on Current Testing of 0.18 μm Gates
Analysis and Characterization of State Assignment Techniques for Sequential Machines
Configurable 2-D Linear Feedback Shift Registers for VLSI Built-in Self-test Designs
Complexity of Scheduling in High Level Synthesis
Hyperbolic Hydrodynamical Model of Carrier Transport in Semiconductors
A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops
A New CDS Structure for High Density FPA with Low Power
An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization
Figure-of-Merit-Based Area-Constrained Design of Differential Amplifiers
Random Pattern Testability Enhancement by Circuit Rewiring
Ultra-Low-Voltage Self-Body Biasing Scheme and Its Application to Basic Arithmetic Circuits
Particle Swarm Optimization for Constrained Instruction Scheduling
Improving Path Sensitizability of Combinational Circuits
Low Power Built-In Self-Test Schemes for Array and Booth Multipliers
Stochastic Communication: A New Paradigm for Fault-Tolerant Networks-on-Chip
Three-dimensional Spectral Solution of Schrödinger Equation
Quantum Potential Approaches for Nano-scale Device Simulation
Nearly Balanced Quad List Quad Tree -A Data Structure for VLSI Layout Systems
A Dependable Micro-Electronic Peptide Synthesizer Using Electrode Data
Simulation of Si-MOSFETs with the Mutation Operator Monte Carlo Method
The Impact of Statistical Leakage Models on Design Yield Estimation
Engineering Change Orders Design Using Multiple Variables Linear Programming for VLSI Design
Transient Phenomena in High Speed Bipolar Devices
Studies of Chaotic Transport of Electrons in Quantum Boxes
Gain Calculation in a Quantum Well Laser Simulator Using an Eight Band k.p Model
Electro-thermal Modelling of Monolithic and Hybrid Microwave and Millimeter Wave IC's
Formal Codesign Methodology with Multistep Partitioning
Ionic Channels in Biological Membranes: Natural Nanotubes Described by the Drift-Diffusion Equations
DP-FPGA: An FPGA Architecture Optimized for Datapaths
A New Computational Approach to Photon-Assisted Tunneling in Intense Driving Fields Based on a Fabry-Perot Analogy
Hydrodynamic Models of Semiconductor Electron Transport at High Fields
Dispersion Lemmas Revisited
A Low-Power Scalable Stream Compute Accelerator for General Matrix Multiply (GEMM)
The Quantum Hydrodynamic Smooth Effective Potential
Convergence Properties of the Bi-CGSTAB Method for the Solution of the 3D Poisson and 3D Electron Current Continuity Equations for Scaled Si MOSFETs
A Robust Low-Voltage On-Chip LDO Voltage Regulator in 180 nm
Quantum Distribution-function Transport Equations in Non-normal Systems and in Ultra-fast Dynamics of Optically-excited Semiconductors
A Q-Enhanced 3.6 GHz, Tunable, Sixth-Order Bandpass Filter Using 0.18 μm CMOS
Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction
A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees
Cluster Partitioning Techniques for Data Path Synthesis
Implementation of Hardware-Accelerated Scalable Parallel Random Number Generators
Overlapped Subarray Segmentation: An Efficient Test Method for Cellular Arrays
Fully Pipelined Parallel Architecture for Candidate Block and Pixel-Subsampling-Based Motion Estimation
Comparison of Non-Parabolic Hydrodynamic Models Based On Different Band Structure Models
Closed Form Aliasing Probability For Q-ary Symmetric Errors
I DDQ Testing Experiments for Various CMOS Logic Design Structures
A New Bus Assignment Algorithm for a Shared Bus Switch Fabric
Two-valley Hydrodynamical Models for Electron Transport in Gallium Arsenide: Simulation of Gunn Oscillations
Dynamical Equation and Monte Carlo Simulation of the Two-time Wigner Function for Electron Quantum Transport
Unified and Modular Modeling and Functional Verification Framework of Real-Time Image Signal Processors
A New 2-way Multi-level Partitioning Algorithm
Architecture and Implementation of Fading Compensation for Dynamic Spectrum Access Wireless Communication Systems
A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model
Design of an ASIC Chip for Skeletonization of Graylevel Digital Images
Timing-Driven-Testable Convergent Tree Adders
Simulation of 0.35 μm/0.25 μm CMOS Technology Doping Profiles
A Pull-in Based Test Mechanism for Device Diagnostic and Process Characterization
Statistical Module Level Area and Delay Estimation
A Quadratic Programming Approach to Estimating the Testability and Random or Deterministic Coverage of a VLSl Circuit
VLSI Testing for High Reliability: Mixing IDDQ Testing With Logic Testing
Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping
Placement and Routing for Performance-Oriented FPGA Layout
Applying Neural Networks to Find the Minimum Cost Coverage of a Boolean Function
Application of the Wigner-Function Formulation to Mesoscopic Systems in Presence of Electron-Phonon Interaction
Modelling of Hot Acoustic Phonon Propagation in Two Dimensional Layers
Power Consumption and BER of Flip-Flop Inserted Global Interconnect
On the Structure and Closure-Condition of the Hydrodynamic Model
Networks-on-Chip: Emerging Research Topics and Novel Ideas
Integrated Area-power Optimal State Assignment
Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits
High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic