yusuke1997/dblp-id-title huggingface dataset:
A Fully Integrated Programmable 6.0-8.5-GHz UWB IR Transmitter Front-End for Energy-Harvesting Devices
A 2.4-V pp 60-Gb/s CMOS Driver With Digitally Variable Amplitude and Pre-Emphasis Control at Multiple Peaking Frequencies
Integrated circuit implementation of fuzzy controllers
A 300-MHz 16-b BiCMOS video signal processor
A 2/3-in 400k-pixel sticking-free stack-CCD image sensor
A low-voltage ultra-low-power translinear integrator for audio filter applications
A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme
A dual-path bandwidth extension amplifier topology with dual-loop parallel compensation
A 19-mW 2.6-mm 2 L1/L2 dual-band CMOS GPS receiver
VLSI partitioning of a 2-Gs/s digital spectrometer
A 2× Time-Interleaved 4-GS/s 14-Bit DAC With On-Chip Calibration of Interleaving Nonlinearities
A 0.00175 mm 2 and 9.62 μW per Channel Direct-Digitization Front End With EDO Compensation for Neural Probes With a Spatial Resolution of 35 μm
InGaAs/InP DHBT technology and design methodology for over 40 Gb/s optical communication circuits
A 500-MHz pipelined burst SRAM with improved SER immunity
An on-chip smart memory for a data-flow CPU
A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell
A Sub-Nanosecond Pulsed VCSEL Driver With PVT-Compensated Constant Current, Integrated Boost Switching Regulator and Class-1 Laser Eye Safety
A 4-Phase DAB Current-Mode Hysteretic Controlled Buck Converter With Relaxed Inductor Requirements and Enhanced DC and Dynamic Performance
A Harmonic-Rejecting CMOS LNA for Broadband Radios
A 103-dB SFDR Calibration-Free Oversampled SAR ADC With Mismatch Error Shaping and Pre-Comparison Techniques
BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks
Introduction to the 2006 Bipolar/BiCMOS Circuits and Technology Meeting
A Digitally Controlled Injection-Locked Oscillator With Fine Frequency Resolution
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-μm silicide CMOS process
A 900-mV low-power ΔΣ A/D converter with 77-dB dynamic range
Introduction to the Special Issue on the 2013 Symposium on VLSI Circuits
A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces
Energy-Efficient CMOS Humidity Sensors Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array
A Highly Integrated CMOS Analog Baseband Transceiver With 180 MSPS 13-bit Pipelined CMOS ADC and Dual 12-bit DACs
Intermittent Operation Control Scheme for Reducing Power Consumption of UWB-IR Receiver
A reduced-area low-power low-voltage single-ended differential pair
A low jitter 0.3-165 MHz CMOS PLL frequency synthesizer for 3 V/5 V operation
A high-speed, low-power clock generator for a microprocessor application
A 15-Bit Quadrature Digital Power Amplifier With Transformer-Based Complex-Domain Efficiency Enhancement
A 100-MHz 100-dB operational amplifier with multipath nested Miller compensation structure
A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications
A 2 kfps Sub-µW/Pix Uncooled-PbSe Digital Imager With 10 Bit DR Adjustment and FPN Correction for High-Speed and Low-Cost MWIR Applications
A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System
A 65-nm GSM/GPRS/EDGE SoC With Integrated BT/FM
Sizing of cell-level analog circuits using constrained optimization techniques
Impact of self-heating and thermal coupling on analog circuits in SOI CMOS
Techniques for phase noise suppression in recirculating DLLs
Introduction to the 34th Annual IEEE Compound Semiconductor Integrated Circuit Symposium
An SC Voltage Doubler with Pseudo-Continuous Output Regulation Using a Three-Stage Switchable Opamp
Two schemes for detecting CMOS analog faults
An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters
A Dual-Mode Wi-Fi/BLE Wake-Up Receiver
A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference
An 8.5-Gb/s Fully Integrated CMOS Optoelectronic Receiver Using Slope-Detection Adaptive Equalizer
Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS
A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider
Statistical integrated circuit design
A 40-nm 91-mW, 90-fps Learning-Based Full HD Super-Resolution Accelerator
A quadrature charge-domain sampler with embedded FIR and IIR filtering functions
Integrated laser-diode voltage driver for 20-Gb/s optical systems using 0.3- mu m gate length quantum-well HEMT's
An X-Band Transformer-Coupled Varactor-Less Quadrature Current-Controlled Oscillator in 0.18 μm SiGe BiCMOS Technology
Introduction to the Special Issue on the IEEE 2006 Custom Integrated Circuits Conference
A Highly Selective Receiver With Programmable Zeros and Second-Order TIA
A limiting amplifier with low phase deviation using an AlGaAs/GaAs HBT
INTIACC: A Programmable Floating- Point Accelerator for Partial Differential Equations
A Compiled 9-bit 20-MS/s 3.5-fJ/conv.step SAR ADC in 28-nm FDSOI for Bluetooth Low Energy Receivers
GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSI's
36-GHz, 16×6-Bit ROM in InP DHBT Technology Suitable for DDS Application
A Highly Parallel and Scalable CABAC Decoder for Next Generation Video Coding
Guest Editorial 2021 Custom Integrated Circuits Conference
An enhanced fully differential folded-cascode op amp
A 12-bit 500-ns subranging ADC
Multiband cellular RF solutions
A low-noise phase-locked loop design by loop bandwidth optimization
Cell-Based Variable-Gain Amplifiers With Accurate dB-Linear Characteristic in 0.18 µm CMOS Technology
A 25-34-GHz Eight-Element MIMO Transmitter for Keyless High Throughput Directionally Secure Communication
A Jitter Programmable Digital Bang-Bang PLL Using PVT-Invariant Stochastic Jitter Monitor
Introduction to RF simulation and its application
Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges
10-MHz 64-bit error-tolerant signature recognition circuit
Introduction to the Special Section on the IEEE Radio Frequency Integrated Circuits (RFIC) Symposium
A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed
Reconfigurable Processor for Energy-Efficient Computational Photography
An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM
A Full-Wave Rectifier With Integrated Peak Selection for Multiple Electrode Piezoelectric Energy Harvesters
A low-voltage line driver for digital signaling interface
CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference
A Push-Pull Class-C CMOS VCO
Active Millimeter-Wave Phase-Shift Doherty Power Amplifier in 45-nm SOI CMOS
A VHF Wide-Input Range CMOS Passive Rectifier With Active Bias Tuning
An On-Chip Power-Supply Noise Analyzer With Compressed Sensing and Enhanced Quantization
A Fully Integrated Reconfigurable Self-Startup RF Energy-Harvesting System With Storage Capability
Remotely powered addressable UHF RFID integrated system
The design and analysis of a Miller-divider-based clock generator for MBOA-UWB application
De-embedding the noise figure of differential amplifiers
A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking
An Element-Matched Electromechanical ΔΣ ADC for Ultrasound Imaging
Adiabatic dynamic logic
A Tri-Slope Gate Driving GaN DC-DC Converter With Spurious Noise Compression and Ringing Suppression for Automotive Applications
10-bit Driver IC Using 3-bit DAC Embedded Operational Amplifier for Spatial Optical Modulators (SOMs)
Efficiency of body biasing in 90-nm CMOS for low-power digital circuits
A Highly Linear and Efficient V-Band CMOS Power Amplifier Using Hybrid NMOS/PMOS for Double Nonlinearity Cancellation With Four-Way Distributed-Active-Transformer
0.9-V DSP blocks: a 15-ns 4-k SRAM and a 45-ns 16-b multiply/accumulator
Modeling of frequency and temperature effects in GaAs MESFETs
An adjustable output driver with a self-recovering Vpp generator for a 4M⨉16 DRAM
An 8 ns 4 Mb serial access memory
A Fully Integrated Multi-Phase Voltage Regulator With Flying-Capacitor-Based Inter-Inductor Current Self-Balancing Scheme and Charge-Recycling Gate Driver
A 100-MHz CMOS DAC for video-graphic systems
Guest editorial [Special issue of the digital, memory, and signal processing sessions of the 2003 ISSCC]
A 1 Mb EEPROM with MONOS memory cell for semiconductor disk application
On-chip spiral inductors with patterned ground shields for Si-based RF ICs
A flexible multiport RAM compiler for data path
A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique
A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops
A Voltage Multiplier With Adaptive Threshold Voltage Compensation
A 64-site multishank CMOS low-profile neural stimulating probe
A 1.0-V V DD CMOS active-pixel sensor with complementary pixel architecture and pulsewidth modulation fabricated with a 0.25-μm CMOS process
A 96.1% Efficiency Single-Inductor Multiple-Output (SIMO) Buck Converter With 2.1-A/ns Transient Speed and 2.2-A Maximum Current Capacity
Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors
A 1-V Bandgap Reference in 7-nm FinFET With a Programmable Temperature Coefficient and Inaccuracy of ±0.2% From -45°C to 125°C
A 58-65 GHz Neutralized CMOS Power Amplifier With PAE Above 10% at 1-V Supply
Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module
Low-jitter process-independent DLL and PLL based on self-biased techniques
A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring
A Low-Power, Compact, 0.1-5.5-GHz, 40-dBm IB OIP3 LNTA-First Receiver for SDR
A 2- mu m CMOS fifth-order low-pass continuous-time filter for video-frequency applications
A 256-element associative parallel processor
30-ps 7.5-GHz GaAs MESFET macrocell array
A Wideband Highly Integrated and Widely Tunable Transceiver for In-Band Full-Duplex Communication
A 6-GHz integrated phase-locked loop using AlGaAs/GaAs heterojunction bipolar transistors
A Colpitts Oscillator-Based Self-Starting Boost Converter for Thermoelectric Energy Harvesting With 40-mV Startup Voltage and 75% Maximum Efficiency
A Ratiometric Readout Circuit for Thermal-Conductivity-Based Resistive CO 2 Sensors
A 59-to-276-GHz CMOS Signal Generator Using Varactor-Less VCO and Dual-Mode ILFD
CMOS output buffers for megabit DRAMs
A Low-Cost Scalable 32-Element 28-GHz Phased Array Transceiver for 5G Communication Links Based on a 2×2 Beamformer Flip-Chip Unit Cell
A Power-Efficient Fractional-N DPLL With Phase Error Quantized in Fully Differential-Voltage Domain
Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies
A 2-V CMOS 455-kHz FM/FSK demodulator using feedforward offset cancellation limiting amplifier
A Calibration-Free 800 MHz Fractional-N Digital PLL With Embedded TDC
An Ultra-Low-Power Injection Locked Transmitter for Wireless Sensor Networks
12-Gb/s decision circuit IC using AlGaAs/GaAS HBT technology
A 10/20/30/40 MHz Feedforward FIR DAC Continuous-Time ΔΣ ADC With Robust Blocker Performance for Radio Receivers
Wideband High-Gain Amplifiers in 45-nm CMOS SOI Operating at 0.56f max : An Analytical Approach on Reversed Feedback Amplifiers
A CMOS 400-Mb/s serial link for AS-memory systems using a PWM scheme
Low-power video encoder/decoder chip set for digital VCRs
0.5-1-V, 90-400-mA, Modular, Distributed, 3 × 3 Digital LDOs Based on Event-Driven Control and Domino Sampling and Regulation
Converters dedicated to long-term monitoring of strain gauge transducers
A monolithic 480 Mb/s parallel AGG/decision/clock-recovery circuit in 1.2- mu m CMOS
Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver
A Broadband mm-Wave and Terahertz Traveling-Wave Frequency Multiplier on CMOS
A 0.68-0.72-THz 2-D Scalable Radiator Array With -3-dBm Radiated Power and 27.3-dBm EIRP in 65-nm CMOS
A 0.9-V Input Discontinuous-Conduction-Mode Boost Converter With CMOS-Control Rectifier
A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM
Energy Supply and ULP Detection Circuits for an RFID Localization System in 130 nm CMOS
A BJT-Based Temperature-to-Frequency Converter With ± 1°C (3\Σ) Inaccuracy From - 40 °C to 140 °C for On-Chip Thermal Monitoring
A true-1-V 300-μW CMOS-subthreshold log-domain hearing-aid-on-chip
A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line Discharge
Pseudomorphic 2DEG FET IC's for 10 Gb/s optical communication systems with external optical modulation
A 2-ns 16K bipolar ECL RAM with reduced word-line voltage swing
Metastability behavior of CMOS ASIC flip-flops in theory and test
A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm 2 and 500 mW in 40 nm Digital CMOS
A 1.3-GHz fifth-generation SPARC64 microprocessor
A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology
A 130-mm/ 2 , 256-Mbit NAND flash with shallow trench isolation technology
A 1.87-mm 2 56.9-GOPS Accelerator for Solving Partial Differential Equations
A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth
Comments on 'A CMOS four-quadrant multiplier': effects of threshold voltage
LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS
A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4-GHz LNAs
A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry
Redundant Crossfire: A Technique to Achieve Super-Resolution in Neurostimulator Design by Exploiting Transistor Mismatch
Discrete-time parametric amplification based on a three-terminal MOS varactor: analysis and experimental results
All-Digital LTE SAW-Less Transmitter With DSP-Based Programming of RX-Band Noise
A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS
An Optically Powered, High-Voltage, Switched- Capacitor Drive Circuit for Microrobotics
A 0.4-μm 3.3-V 1T1C 4-Mb nonvolatile ferroelectric RAM with fixed bitline reference voltage scheme and data protection circuit
A Study of Injection Locking in Oscillators and Frequency Dividers
The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks
A seventh-generation x86 microprocessor
A circuit design to suppress asymmetrical characteristics in high-density DRAM sense amplifiers
A dynamic analysis of the Dickson charge pump circuit
An offset-free LPF for π/4-shift QPSK signal generator
High-accuracy charge-redistribution SC video bandpass filter in standard CMOS
A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp Third-Order Σ Δ Modulator
Ultrahigh-speed direct digital synthesizer using InP DHBT technology
A 14-b direct digital frequency synthesizer with sigma-delta noise shaping
A High-Speed Fully-Integrated POF Receiver With Large-Area Photo Detectors in 65 nm CMOS
An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS
High-Speed Optical Receivers With Integrated Photodiode in 130 nm CMOS
An InGaP-GaAs HBT MMIC smart power amplifier for W-CDMA mobile handsets
High-drive CMOS current amplifier
A Self-Sustained CMOS Microwave Chemical Sensor Using a Frequency Synthesizer
A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE
MANTIS: A Mixed-Signal Near-Sensor Convolutional Imager SoC Using Charge-Domain 4b-Weighted 5-to-84-TOPS/W MAC Operations for Feature Extraction and Region-of-Interest Detection
Design of Soft-Charging Switched-Capacitor DC-DC Converters Using Stage Outphasing and Multiphase Soft-Charging
A 430- μ A 68.2-dB-SNR 133-dBSPL-AOP CMOS-MEMS Digital Microphone Based on Electrostatic Force Feedback Control
A 10-bit Source-Driver IC With Charge-Modulation DAC for Enhanced Frame-Rate Mobile OLED Displays
A VGA Indirect Time-of-Flight CMOS Image Sensor With 4-Tap 7- $\mu$ m Global-Shutter Pixel and Fixed-Pattern Phase Noise Self-Compensation
A 65 nm CMOS Quad-Band SAW-Less Receiver SoC for GSM/GPRS/EDGE
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction
Estimation of typical power of synchronous CMOS circuits using a hierarchy of simulators
A Differential Oscillator Injection Locking Technique for an 8 GHz Outphasing Modulator With 22.7% Modulation Efficiency
A Fully Integrated Direct-Conversion Receiver for CDMA and GPS Applications
A highly integrated analog front-end for 3G
A 107.4 dB SNR Multi-Bit Sigma Delta ADC With 1-PPM THD at -0.12 dB From Full Scale Input
0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file
An RF MEMS Sensor Driver/Readout SoC With Resonant Frequency Shift and Closed-Loop Envelope Regulation for Portable Microplastic Detection
An Area and Power Efficient Source Driver IC With Multi-Line Sensing Real-Time Pixel Compensation for OLED Displays
STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS
A 4-Bit Mixed-Signal MAC Macro With One-Shot ADC Conversion
A Flexible, Event-Driven Digital Filter With Frequency Response Independent of Input Sample Rate
An All-Digital RF Signal Generator Using High-Speed ΔΣ Modulators
A new design of a fast barrel switch network
Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving
A 16.1-bit Resolution 0.064-mm 2 Compact Highly Digital Closed-Loop Single-VCO-Based 1-1 Sturdy-MASH Resistance-to-Digital Converter With High Robustness in 180-nm CMOS
A 700-MHz 24-b pipelined accumulator in 1.2- mu m CMOS for application as a numerically controlled oscillator
915-MHz FSK/OOK Wireless Neural Recording SoC With 64 Mixed-Signal FIR Filters
A low-power, high-performance, 1024-point FFT processor
Automated low-power technique exploiting multiple supply voltages applied to a media processor
A direct-skew-detect synchronous mirror delay for application-specific integrated circuits
High-speed circuit designs for transmitters in broadband data links
A CMOS gate array with 600 Mb/s simultaneous bidirectional I/O circuits
A 47-nW Voice Activity Detector (VAD) Featuring a Short-Time CNN Feature Extractor and an RNN-Based Classifier With a Non-Volatile CAP-ROM
1 Mb 0.41 µm 2 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing
Neuro chips with on-chip back-propagation and/or Hebbian learning
Differential current switch logic: a low power DCVS logic family
A 108-nW 0.8-mm 2 Analog Voice Activity Detector Featuring a Time-Domain CNN With Sparsity-Aware Computation and Sparsified Quantization in 28-nm CMOS
ΔΣ PLL Transmitter With a Loop-Bandwidth Calibration System
Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $\mu$ A Sensing Resolution, and 17.5-nS Read Access Time
A Fully Differential Low-Power Divide-by-8 Injection-Locked Frequency Divider Up to 18 GHz
Operational-amplifier compilation with performance optimization
A World-Band Triple-Mode 802.11a/b/g SOC in 130-nm CMOS
A Fast Startup Crystal Oscillator Using Impedance Guided Chirp Injection in 22 nm FinFET CMOS
Experimental characterization of circuits for controlled programming of floating-gate MOSFET's
RF-Powered Transceiver With an Energy- and Spectral-Efficient IF-Based Quadrature Backscattering Transmitter
A 40-GHz D-type flip-flop using AlGaAs/GaAs HBT's
A 6-ns 1-Mb CMOS SRAM with latched sense amplifier
A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS
Optimum voltage swing on on-chip and off-chip interconnect
Introduction to the Special Section on the 2014 Compound Semiconductor Integrated Circuit Symposium
Corrections to "Split-Array, C-2C Switched-Capacitor Power Amplifiers"
A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO
A mixed-signal approach to high-performance low-power linear filters
A Switchable Digital-Analog Low-Dropout Regulator for Analog Dynamic Voltage Scaling Technique
A Scalable High-Current High-Accuracy Dual-Loop Four-Phase Switching LDO for Microprocessors
A Reconfigurable 3-D-Stacked SPAD Imager With In-Pixel Histogramming for Flash LIDAR or High-Speed Time-of-Flight Imaging
A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 µm CMOS Technology
Development of Embedded Three-Dimensional 35-nF/mm 2 MIM Capacitor and BiCMOS Circuits Characterization
A highly integrated wideband millimeter-wave MMIC converter using 0.25- mu m P-HEMT technology
"EChO" Reconfigurable Power Management Unit for Energy Reduction in Sleep-Active Transitions
A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μm CMOS with over 80-dB SFDR
A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltage Positioning Using a Beat-Frequency Quantizer
A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs
A high-swing 2-V CMOS operational amplifier with replica-amp gain enhancement
A 6.5-to-8-GHz Cascaded Dual-Fractional-N Digital PLL Achieving -52.79-dBc Fractional Spur With 50-MHz Reference
A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-µm Technology
A Simultaneous Energy Transferring SIBO Converter Achieving Low Ripple and High Efficiency for AMOLED Applications
A 1.2-GS/s 8-bit Two-Step SAR ADC in 65-nm CMOS With Passive Residue Transfer
A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC
2-MHz clocked LCD drivers on glass
85-110-GHz CMOS Magnetic-Free Nonreciprocal Components for Full-Duplex Transceivers
A Josephson 4 bit RALU for a prototype computer
A Continuous-Time Programmable Digital FIR Filter
A low-frequency GaAs MESFET circuit model
A Fully Passive RF Front End With 13-dB Gain Exploiting Implicit Capacitive Stacking in a Bottom-Plate N-Path Filter/Mixer
Efficient 6-bit A/D converter using a 1-bit folding front end
Variable V CC design techniques for battery-operated DRAMs
A 2.4-GHz 1.3-mW OQPSK RF Front-End TX Based on an Injection-Locked Power Amplifier
RF Oscillator Based on a Passive RC Bandpass Filter
A partitioning scheme for optimizing interconnect power
A 151-mm 2 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology
A four-terminal compact model for high voltage diffused resistors with field plates
A 3.1 GHz-8.0 GHz Single-Chip Transceiver for MB-OFDM UWB in 0.18-µm CMOS Process
A Cascaded Hybrid Switched-Capacitor DC-DC Converter Capable of Fast Self Startup for USB Power Delivery
CMOS switched-current ladder filters
A Low-Voltage Energy-Sampling IR-UWB Digital Baseband Employing Quadratic Correlation
A Series-Parallel Switched-Photovoltaic DC-DC Converter
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme
A 12-Level Series-Capacitor 48-1V DC-DC Converter With On-Chip Switch and GaN Hybrid Power Conversion
A 92.3%-Efficiency Switching-Mode Dual-Output Regulating Rectifier With Improved Link Adaptability for Wireless Power Transfer
A 62-92-GHz 12.4% Efficiency Harmonics-Recycling CMOS Frequency Quadrupler Using Amplitude-Phase Coordinating Technique
Selective Change Driven Vision Sensor With Continuous-Time Logarithmic Photoreceptor and Winner-Take-All Circuit for Pixel Selection
A 30-ns 64-Mb DRAM with built-in self-test and self-repair function
A microprogrammable real-time image processor
A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler
A low-power 98-dB multibit audio DAC in a standard 3.3-V 0.35-μm CMOS technology
Design of an X-band transformer-coupled amplifier with improved stability and layout