yusuke1997/dblp-id-title huggingface dataset:
Blind-Channel Estimation for MIMO Systems With Structured Transmit Delay Scheme
A Silicon-Based Low-Power Broadband Transimpedance Amplifier
Dual-Input Pseudo-Switch RF Low Noise Amplifier
A Sub-Nyquist Sampling Algorithm for Fractional Bandlimited Signals Based on AIC
Stabilizing the Average-Current-Mode-Controlled Boost PFC Converter via Washout-Filter-Aided Method
Event-Based Robust Sampled-Data Model Predictive Control: A Non-Monotonic Lyapunov Function Approach
Decentralized nonlinear adaptive control for multimachine power systems via high-gain perturbation observer
Dimensionless Approach to Multi-Parametric Stability Analysis of Nonlinear Time-Periodic Systems: Theory and Its Applications to Switching Converters
A Low Power Impulse Radio Design for Body-Area-Networks
Double-sampling single-loop ΣΔ modulator topologies for broad-band applications
Automatic Scaling Procedures for Analog Design Reuse
A new CMOS pixel structure for low-dark-current and large-array-size still imager applications
Positive Feedback Pilot System for Second Loop Control in a Feedforward Power Amplifier
A 20-kHz~16-MHz Programmable-Bandwidth 4th Order Active Filter Using Gain-Boosted Opamp With Negative Resistance in 65-nm CMOS
A Low Complexity Sparse Code Multiple Access Detector Based on Stochastic Computing
Design and Implementation of Fully Integrated Digitally Controlled Current-Mode Buck Converter
VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications
An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes
Frequency Response Mismatch Analysis in Time-Interleaved Analog I/Q Processing and ADCs
Modeling and Mitigation of Static Noise Margin Variation in Subthreshold SRAM Cells
A Tunable Pseudo-Differential OTA With -78~hbox dB THD Consuming 1.25 mW
Feature-Temporal Semi-Supervised Extreme Learning Machine for Robotic Terrain Classification
Improvement of State Feedback Controller Design for Networked Control Systems
SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus
Global Robust Stability Criteria for Interval Delayed Neural Networks Via an LMI Approach
l 2 -l ∞ Suppression of Limit Cycles in Interfered Two-Dimensional Digital Filters: A Fornasini-Marchesini Model Case
Synchronous filtering
An Approximate Transfer Function Model of Two Serially Connected Heterogeneous Transmission Lines
An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit
Direct Interfacing of Dynamic Average Models of Line-Commutated Rectifier Circuits in Nodal Analysis EMTP-Type Solution
Scalable Adaptive Spintronic Reconfigurable Logic Using Area-Matched MTJ Design
Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology
Synchronization of Networks of Non-Identical Chua's Circuits: Analysis and Experiments
Reference-Modulated DCSK: A Novel Chaotic Communication Scheme
Optimality of Bus-Invert Coding
Parametric Lyapunov Equation Approach to Stabilization of Discrete-Time Systems With Input Delay and Saturation
A 14b, Twofold Time-Interleaved Incremental ΔΣ ADC Using Hardware Sharing
A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector
A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-μm CMOS
High Gain Observer-Based Saturated Controller for Feedback Linearizable System
A 9-Bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS
A Study of Multi-Phase Injection on Accelerating Crystal Oscillator Start-Up
Planar Wideband High-Selectivity Impedance-Transforming Differential Bandpass Filter With Deep Common-Mode Suppression
Programmable ANalog Device Array (PANDA): A Methodology for Transistor-Level Analog Emulation
Deeply Pipelined Digit-Serial LDPC Decoding
A novel differential high-frequency CFA integrator
Joint Optimal Design of Digital Filters and State-Space Realizations
Lattice Reduction for MIMO Detection: From Theoretical Analysis to Hardware Realization
Analysis of the Coverage of Tunable Matching Networks for the Imperfect Matching Case
Presynaptic Spike-Driven Spike Timing-Dependent Plasticity With Address Event Representation for Large-Scale Neuromorphic Systems
Analytical and experimental verification of substrate noise spectrum for mixed-signal ICs
Calibration and Characterization of Self-Powered Floating-Gate Usage Monitor With Single Electron per Second Operational Limit
Sparse FIR Filter Design via Partial 1-Norm Optimization
Diffusion Improved Multiband-Structured Subband Adaptive Filter Algorithm With Dynamic Selection of Nodes Over Distributed Networks
Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-μm digital CMOS technology
Entropy and Energy Bounds for Metastability Based TRNG with Lightweight Post-Processing
A General Method to Design GCF Compensation Filter
High Selectivity Wideband Balanced Filters With Multiple Transmission Zeros
Prediction of chaotic behavior
Memristor-Based Adaptive Coupling for Consensus and Synchronization
Combining the Standard Histogram Method and a Stimulus Identification Algorithm for A/D Converter INL Testing With a Low-Quality Sine Wave Stimulus
A 0.4-V 10.9- $\mu$ W/Pole Third-Order Complex BPF for Low Energy RF Receivers
A 101.4 GOPS/W Reconfigurable and Scalable Control-Centric Embedded Processor for Domain-Specific Applications
Conditions on Polynomials Involved in Admittance Functions Passively Realizable by Using RLC and Two Fractional Elements
Feedforward FFT Hardware Architectures Based on Rotator Allocation
Consensus of Multiagent Systems and Synchronization of Complex Networks: A Unified Viewpoint
Fastest linearly independent transforms over GF(2) and their properties
Small-Signal Modeling and Dynamic Analysis of a Novel ZVZCS Three-Level Converter
Integrated Circuit for Super-Regenerative Low-Frequency Amplification
A Discrete-Time Input Delta Sigma ADC Architecture Using a Dual-VCO-Based Integrator
Distributed H ∞ Consensus of Higher Order Multiagent Systems With Switching Topologies
A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR
A Phase-Domain ΔΣ Ranging Method for FMCW Radar Receivers
A 6.5-µW/MHz Charge Buffer With 7-fF Input Capacitance in 65-nm CMOS for Noncontact Electropotential Sensing
Iterative Gain Enhancement in an Algorithmic ADC
Analytical Noise Optimization of Single-/Dual-Band MOS LNAs With Substrate and Metal Loss Effects of Inductors
A 9 Gb/s/ch Transceiver With Reference-Less Data-Embedded Pseudo-Differential Clock Signaling for Graphics Memory Interfaces
Transconductance amplifier with low-power consumption
Design of PWM Ramp Signal in Voltage-Mode CCM Random Switching Frequency Buck Converter for Conductive EMI Reduction
Fully Integrated High-Voltage Front-End Interface for Ultrasonic Sensing Applications
Passive Circuit Technologies for mm-Wave Wireless Systems on Silicon
Toward Stronger Robustness of Network Controllability: A Snapback Network Model
A Continuous-Time Delta-Sigma Modulator for RF Subsampling Receivers
A Low-Power, Compact, Adaptive Logarithmic Transimpedance Amplifier Operating Over Seven Decades of Current
Improving the Performance of Multitask Diffusion APA via Controlled Inter-Cluster Cooperation
Aging Benefits in Nanometer CMOS Designs
Asynchronous Filtering of Discrete-Time Switched Linear Systems With Average Dwell Time
A Novel Multi-Shape Chaotic Attractor and Its FPGA Implementation
0.3-V RC-to-Digital Converter Using a Negative Charge-Pump Switch
Nonlinear Dynamics of Memristor Oscillators
An Energy-Aware CMOS Receiver Front End for Low-Power 2.4-GHz Applications
Delay-Dependent H ∞ Control and Filtering for Uncertain Markovian Jump Systems With Time-Varying Delays
A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment
Corrections to "Guaranteed Cost Control of Uncertain Differential Linear Repetitive Processes"
The Effects of Flying-Adder Clocks on Digital-to-Analog Converters
Unique Measurement and Modeling of Total Phase Noise in RF Receiver
A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration
An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing
Bias compensation based recursive least-squares identification algorithm for MISO systems
A Low Power Double-Sampling Extended Counting ADC With Class-AB OTA for Sensor Arrays
Magnetic-Feedback-Based Predistortion Method for Low-Noise Amplifier Linearization
2-D Laguerre Distributed Approximating Functional: A Circular Low-Pass/Band-Pass Filter
Low-Complexity Channel Prediction Using Approximated Recursive DCT
Hierarchical Folding and Synthesis of Iterative Data Flow Graphs
An Ultralow-Power Overcurrent Protection Circuit for Micropower Class D Amplifiers
Time-Domain Operational Amplifier With Voltage-Controlled Oscillator and Its Application to Active-RC Analog Filter
Synthesis and Design of LTCC Filtering Balun With Wide Stopband
A 0.5-V 3.69-nW Complementary Source-Follower-C Based Low-Pass Filter for Wearable Biomedical Applications
Joint Data and Pilot Power Allocation for Massive MU-MIMO Downlink TDD Systems
Generalized Discontinuous Conduction Modes in the Complementarity Formalism
An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits
Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS Transistors
An improved ρDFIIt structure for digital filters with minimum roundoff noise
On the Passivity of Polynomial Chaos-Based Augmented Models for Stochastic Circuits
Charge Amplifier With an Enhanced Frequency Response for SPM-Based Data Storage
Bifurcation analysis of switched dynamical systems with periodically moving borders
New high-efficiency 2.5 V/0.45 W RWDM class-D audio amplifier for portable consumer electronics
An Analysis of the Tradeoff Between the Energy and Spectrum Efficiencies in an Uplink Massive MIMO-OFDM System
Hardware Implementation of an Event-Based Message Passing Graphical Model Network
A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS
Area-Delay-Power Efficient Carry-Select Adder
The Analysis and Improvement of a Current-Steering DAC's Dynamic SFDR - II: The Output-Dependent Delay Differences
Fully Differential Current-Mode CMOS Triode Translinear Multiplier
Single Ping-multiple measurements: sonar bearing angle estimation using spatiotemporal frequency filters
A Compact +10/+5 dBm 800/2600 MHz LTE Driver Amplifier With Ground-Bounce Reduction
Utilization of Multi-Resonant Defected Ground Structure Resonators in the Oscillator Feedback for Phase Noise Reduction of K-Band VCOs in 0.18- $\mu$ m CMOS Technology
A time-multiplexed switched-capacitor CDS equalizer with reduced crosstalk layout
A 0.1-5.0 GHz Reconfigurable Transmitter With Dual-Mode Power Amplifier and Digitally-Assisted Self-Calibration for Private Network Communications
Power-Aware Multiband-Multistandard CMOS Receiver System-Level Budgeting
A Chaotic System With Equilibria Located on the Rounded Square Loop and Its Circuit Implementation
Unsupervised Single-Channel Separation of Nonstationary Signals Using Gammatone Filterbank and Itakura-Saito Nonnegative Matrix Two-Dimensional Factorizations
Improving Resistive RAM Hard and Soft Decision Correctable BERs by Using Improved-LLR and Reset-Check-Reverse-Flag Concatenating LDPC Code
An Area-Efficient Column-Parallel Digital Decimation Filter With Pre-BWI Topology for CMOS Image Sensor
Compact Lowpass and Dual-Band Bandpass Filter With Controllable Transmission Zero/Center Frequencies/Passband Bandwidth
Processor Speed Control With Thermal Constraints
Memory-Optimized Re-Gridding Architecture for Non-Uniform Fast Fourier Transform
An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications
Soft Error Detection and Correction Architecture for Asynchronous Bundled Data Designs
Optimal Lossy Matching by Pareto Fronts
A Low-Power and High-Speed Voltage Level Shifter Based on a Regulated Cross-Coupled Pull-Up Network
On the Asymptotic Stability of Positive 2-D Systems Described by the Roesser Model
Vibration Control of a Riser-Vessel System Subject to Input Backlash and Extraneous Disturbances
Design of Linear-Phase FIR Multiple-Notch Filters via an Iterative Reweighted OMP Scheme
A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA
Driving-Scheme Algorithms for Intelligent Energy-Efficient High-Voltage Display Drivers
An LMI approach to the H ∞ filter design for uncertain systems with distributed delays
An inductance enhancement technique and its application to a shunt-peaked 2.5 Gb/s transimpedance amplifier design
Linear-phase FIR interpolation, decimation, and mth-band filters utilizing the farrow structure
A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops
A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems
Modeling and Experimental Validation of a Capacitive Link for Wireless Power Transfer to Biomedical Implants
Available Energy of Improper Lossy LLTIP One-Ports
High-Speed Polynomial Basis Multipliers Over GF(2 m ) for Special Pentanomials
A High-Linearity Capacitance-to-Digital Converter Suppressing Charge Errors From Bottom-Plate Switches
An On-Chip Linear, Squaring, Cubic and Exponential Analog Function Generator
A New Switched-Capacitor Boost-Multilevel Inverter Using Partial Charging
A Novel Hybrid Phase-Locked-Loop Frequency Synthesizer Using Single-Electron Devices and CMOS Transistors
Corrections to "Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications" [Jan 07 153-166]
An Area-Efficient Multistage 3.0- to 8.5-GHz CMOS UWB LNA Using Tunable Active Inductors
Analysis and CMOS implementation of a chaos-based communication system
Capacity of stable periodic solutions in discrete-time bidirectional associative memory neural networks
Passive Realization of Fractional-Order Impedances by a Fractional Element and RLC Components: Conditions and Procedure
A 4.2 mm 2 72 mW Multistandard Direct-Conversion DTV Tuner in 65 nm CMOS
Algebraic Approach to Ambiguity-Group Determination in Nonlinear Analog Circuits
Auto-Resonant Tuning for Capacitive Power and Data Telemetry Using Flexible Patches
Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration
An Efficiency-Enhanced DCM Buck Regulator With Improved Switching Timing of Power Transistors
A Pixel-Parallel Self-Similitude Processing for Multiple-Resolution Edge-Filtering Analog Image Sensors
On the Transfer Function Error of State-Space Filters in Fixed-Point Context
Modeling and Estimation of DC-DC Buck Converter Dynamics Using Relay Feedback Output With Performance Evaluation
An RF Receiver Detection Technique for Cognitive Radio Coexistence
Multiple integration method for a high signal-to-noise ratio readout integrated circuit
A unifying proof of global asymptotical stability of neural networks with delay
Robust filtering for discrete nonlinear fractional transformation systems
A Simple Autonomous Chaotic Circuit With Dead-Zone Nonlinearity
High-Efficiency ZVS AC-DC LED Driver Using a Self-Driven Synchronous Rectifier
Digital Iterative Harmonic Rejection and Image Cancellation for LPF-Less Frequency-Interleaved Analog-to-Digital Converters
A 12-Bit Dynamic Tracking Algorithm-Based SAR ADC With Real-Time QRS Detection
A CMOS-Imager-Pixel-Based Temperature Sensor for Dark Current Compensation
A Passive RFID Tag Embedded Temperature Sensor With Improved Process Spreads Immunity for a -30°C to 60°C Sensing Range
Design of Symmetrical Class E Power Amplifiers for Very Low Harmonic-Content Applications
Analysis of Circuit Noise and Non-Ideal Filtering Impact on Energy Detection Based Ultra-Low-Power Radios Performance
Fully Digital Feedforward Background Calibration of Clock Skews for Sub-Sampling TIADCs Using the Polyphase Decomposition
Toward the LPV Approach for Adaptive Distributed Consensus of Lipschitz Multi-Agents
Steady-State Analysis of Switching Converters via Frequency-Domain Circuit Equivalents
Design Methodology Based on the Inversion Coefficient and its Application to Inductorless LNA Implementations
Synchronization: An Obstacle to Identification of Network Topology
A Robust Image Watermarking Scheme Using Local Statistical Distribution in the Contourlet Domain
Off-Nominal Operation of Class-E Amplifier at Any Duty Ratio
Photodiode Peripheral Utilization Effect on CMOS APS Pixel Performance
A Logic Resistive Memory Chip for Embedded Key Storage With Physical Security
Design and analysis of multiscroll chaotic attractors from saturated function series
Constrained Partial Response Receivers for High-Speed Links
Ultralow-Voltage Power Gating Structure Using Low Threshold Voltage
New Improved Recursive Least-Squares Adaptive-Filtering Algorithms
A Closed-Loop, All-Electronic Pixel-Wise Adaptive Imaging System for High Dynamic Range Videography
An Efficient Eligible Error Locator Polynomial Searching Algorithm and Hardware Architecture for One-Pass Chase Decoding of BCH Codes
A fully integrated low-power BPSK demodulator for implantable medical devices
Short-Range Low-Data-Rate FM-UWB Transceivers: Overview, Analysis, and Design
Robust Design of a Class of Time-Delay Iterative Learning Control Systems With Initial Shifts
Model predictive flocking control for second-order multi-agent systems with input constraints
Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices
The Δ 2 -conjecture for L(2, 1)-labelings is true for direct and strong products of graphs
The Circuit Theory Behind Coupled-Mode Magnetic Resonance-Based Wireless Power Transmission
A 2.41-pJ/bit 5.4-Gb/s Dual-Loop Reference-Less CDR With Fully Digital Quarter-Rate Linear Phase Detector for Embedded DisplayPort
Theory of Flying-Adder Frequency Synthesizers - Part II: Time- and Frequency-Domain Properties of the Output Signal
An Iteration-Based Variable Step-Size Algorithm for Joint Explicit Adaptation of Time Delay
Pinning a complex dynamical network to its equilibrium
An Architecture With Pipelined Background Suppression and In-Situ Noise Cancelling for 2D/3D CMOS Image Sensor
Comparison Principle and Stability of Discrete-Time Impulsive Hybrid Systems
Multistate and Multistage Synchronization of Hindmarsh-Rose Neurons With Excitatory Chemical and Electrical Synapses
Analysis of charge-pump phase-locked loops
DAC Quantization-Noise Cancellation in an Echo-Canceling Transceiver
A Reinforcement Learning-Based Markov-Decision Process (MDP) Implementation for SRAM FPGAs
A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization
Thoughts on Possible Future Charge-Based Technologies for Nano-Electronics
Novel Low-Leakage and High-Speed Triple-Threshold-Voltage Buffers With Skewed Inputs and Outputs
One Analog STBC-DCSK Transmission Scheme not Requiring Channel State Information
All-Pass Filter-Based 2-D IIR Filter-Enhanced Beamformers for AESA Receivers
Jitter Noise of Sampled Multitone Signals
Stability of the 2-D Givone-Roesser Model With Periodic Coefficients
Compact Multi-Layer Bandpass Filter With Wide Stopband Using Selective Feeding Scheme
Delay Estimation in the Presence of Timing Noise
Analysis of Direct-Conversion IQ Transmitters With 25% Duty-Cycle Passive Mixers
A 180-V pp Integrated Linear Amplifier for Ultrasonic Imaging Applications in a High-Voltage CMOS SOI Technology
Adaptive Fault-Tolerant Consensus for a Class of Uncertain Nonlinear Second-Order Multi-Agent Systems With Circuit Implementation
Stabilization of Uncertain Singularly Perturbed Systems With Pole-Placement Constraints
3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital Circuits
Monolithic large-signal transimpedance amplifier for use in multi-gigabit, short-range optoelectronic interconnect applications
Design and Implementation of a Polar Codes Blind Detection Scheme
On-Chip Solar Energy Harvester and PMU With Cold Start-Up and Regulated Output Voltage for Biomedical Applications
A Fully Integrated 60 mV Cold-Start Circuit for Single Coil DC-DC Boost Converter for Thermoelectric Energy Harvesting
Energy-Saving Cooperative Spectrum Sensing Processor for Cognitive Radio System
A Low-Power Time-to-Digital Converter for Sensor Interface Circuits
A biochemical translinear principle with weak inversion ISFETs
High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation
Guest Editorial Special Issue on the 2017 IEEE International Symposium on Circuits and Systems (ISCAS 2017)
A 1.2-V 2.41-GHz Three-Stage CMOS OTA With Efficient Frequency Compensation Technique
Phase Noise Simulation in Analog Mixed Signal Circuits: An Application to Pulse Energy Oscillators
Synchronization of Coupled Harmonic Oscillators via Sampled Position Data Control
Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F 2 /Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM
A 0.4-V, 90 ∼ 350-MHz PLL With an Active Loop-Filter Charge Pump
Multiparameter Sensor Interface Circuit With Integrative Baseline/Offset Compensation by Switched-Capacitor Level Shifting/Balancing
Bounded Input Dissipativity of Linearized Circuit Models
High-Gain Zero-Voltage Switching Bidirectional Converter With a Reduced Number of Switches
A Fast Algorithm for Testability Analysis of Large Linear Time-Invariant Networks
A Pulse Generator for UWB-IR Based on a Relaxation Oscillator
An All-Digital Spread-Spectrum Clock Generator With Self-Calibrated Bandwidth
A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment
Design Techniques and Architectures for Low-Leakage SRAMs
Ultrafast Analog Fourier Transform Using 2-D LC Lattice
High-Efficiency Class-FE Tuned Power Amplifiers
Design of Low-Power Low-Area Tunable Active RC Filters
Capacitor Multiplier With Wide Dynamic Range and Large Multiplication Factor for Filter Applications
Memoryless Viterbi decoder
A Methodology for Implementation of High-Efficiency Broadband Power Amplifiers With Second-Harmonic Manipulation
An RF-to-DC Rectifier With High Efficiency Over Wide Input Power Range for RF Energy Harvesting Applications
High-Efficiency Broadband Rectifier With Wide Ranges of Input Power and Output Load Based on Branch-Line Coupler
Cascading Failure of Cyber-Coupled Power Systems Considering Interactions Between Attack and Defense
Dual-Band LC VCO Architecture With a Fourth-Order Resonator
An 18-23 GHz 57.4-fs RMS Jitter -253.5-dB FoM Sub-Harmonically Injection-Locked All-Digital PLL With Single-Ended Injection Technique and ILFD Aided Adaptive Injection Timing Alignment Technique
Switched-Capacitor Power Management Integrated Circuit for Autonomous Internet of Things Node
A Low Loss and Area Efficient RC Passive Poly Phase Filter for Monolithic GHz Vector-Sum Circuits
Statistical Design of the 6T SRAM Bit Cell
A 405-nW CMOS Temperature Sensor Based on Linear MOS Operation
Digital Background Calibration of a Split Current-Steering DAC
Chaotic Pulse-Position Baseband Modulation for an Ultra-Wideband Transceiver in CMOS
An Efficient Digital Background Control for Hybrid Transformer-Based Receivers
A Resource-Efficient and Side-Channel Secure Hardware Implementation of Ring-LWE Cryptographic Processor
Multi-Channel Analog-to-Digital Conversion Techniques Using a Continuous-Time Delta-Sigma Modulator Without Reset
Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture
A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector Using 0.13- muhboxm CMOS Technology
A Bit-Line Voltage Sensing Circuit With Fused Offset Compensation and Cancellation Scheme
A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier
Chaos-Coded Modulations Over Rician and Rayleigh Flat Fading Channels
A wide-band 280-MHz four-path time-interleaved bandpass sigma-delta modulator
Lossless Systems Storage Function: New Results and Numerically Stable and Non-Iterative Computational Methods
A unified small-signal simulation algorithm for SMPS
Predicting and Avoiding Spurious Tones in a DWA-Mismatch-Shaping DAC
Observations and Analysis of Wandering Spurs in MASH-Based Fractional-N Frequency Synthesizers