yusuke1997/dblp-id-title huggingface dataset:
Verification and Codesign of the Package and Die Power Delivery System Using Wavelets
Simulation lossless symmetrical three conductor systems
Modeling STI Edge Parasitic Current for Accurate Circuit Simulations
Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC
Multilevel and mixed-domain simulation of analog circuits and systems
EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions
Optrone: Maximizing Performance and Energy Resources of Drone Batteries
Helper Data Algorithms for PUF-Based Key Generation: Overview and Analysis
Simulating digital circuits with one bit per wire
A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design
Architecting the Autocuckoo Filter to Defend Against Cross-Core Cache Attacks
PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays
Structural methods for the synthesis of speed-independent circuits
Adaptive Energy Management for Dynamically Reconfigurable Processors
Debugging RTL Using Structural Dominance
Highly VM-Scalable SSD in Cloud Storage Systems
Floating Random Walk-Based Capacitance Simulation Considering General Floating Metals
MoDSE: A High-Accurate Multiobjective Design Space Exploration Framework for CPU Microarchitectures
Probabilistic modeling of dependencies during switching activity analysis
An integrated system for assigning signal flow directions to CMOS transistors
Static Test Compaction for Scan Circuits by Using Restoration to Modify and Remove Tests
Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations
Switch bound allocation for maximizing routability in timing-driven routing of FPGA's
Checking Robustness Against EM Side-Channel Attacks Prior to Manufacturing
Structured Decomposition for Reversible Boolean Functions
A 2-D boundary element method approach to the simulation of DMOS transistors
ViA: A Novel Vision-Transformer Accelerator Based on FPGA
Design hierarchy-guided multilevel circuit partitioning
High-Dimensional Bayesian Optimization for Analog Integrated Circuit Sizing Based on Dropout and g/I Methodology
Accelerating Queries of Big Data Systems by Storage-Side CPU-FPGA Co-Design
Stochastic Behavioral Modeling and Analysis for Analog/Mixed-Signal Circuits
Nonconvex Gate Delay Modeling and Delay Optimization
FastSim: A Fast Simulation Framework for High-Level Synthesis
Analysis of power dissipation in embedded systems using real-time operating systems
Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method
VLSI logic and fault simulation on general-purpose parallel computers
Estimating Circuit Aging Due to BTI and HCI Using Ring-Oscillator-Based Sensors
Interval diagrams for efficient symbolic verification of processnetworks
Netwise Detection of Hardware Trojans Using Scalable Convolution of Graph Embedding Clouds
Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip
A complete substrate current model including band-to-band tunneling current for circuit simulation
APPcache+: An STT-MRAM-Based Approximate Cache System With Low Power and Long Lifetime
Combining multiple DFT schemes with test generation
RAPIDx: High-Performance ReRAM Processing In-Memory Accelerator for Sequence Alignment
HARP: FORTRAN to silicon [compilation system]
A trajectory piecewise-linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices
Exterior templates for capacitance computations [interconnections]
Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs
Models for a New Profit-Based Methodology for Statistical Design of Integrated Circuits
Self-Adaptive Data Caches for Soft-Error Reliability
Fair watermarking using combinatorial isolation lemmas
Carbon Nanotube Interconnect Optimizations With Bayesian Neural Network and Bayesian Optimization
Online Energy-Efficient Task-Graph Scheduling for Multicore Platforms
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model
Two-dimensional IC layout compaction based on topological design rule checking
Semantic Segmentation-Based Wafer Map Mixed-Type Defect Pattern Recognition
AutoAI2C: An Automated Hardware Generator for DNN Acceleration on Both FPGA and ASIC
Knowledge-Intensive Diagnostics Using Case-Based Reasoning and Synthetic Case Generation
Layout placement for sliced architecture
Distributed-memory parallel routing for field-programmable gatearrays
Numerical analysis of magnetic-field-sensitive bipolar devices
Toward Precise and Explainable Hardware Trojan Localization at LUT Level
Synthesis of Active Cell Balancing Architectures for Battery Packs
Fanout-Bounded Logic Synthesis for Emerging Technologies
Optimal phase conflict removal for layout of dark field alternatingphase shifting masks
Efficient Automatic Design of IGBT Structural Parameters Using Differential Evolution and Machine Learning Model
Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation
Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design
DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis
Channel Routing Algorithms for Overlap Models
A yield improvement technique for IC layout using local design rules
Estimating the minimum of partitioning and floorplanning problems
Optimality-Guaranteed Design Space Pruning for CAN-FD Frame Packing
Learning-Driven Physically Aware Large-Scale Circuit Gate Sizing
COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems
P-Val: Antifuse-Based Package-Level Defense Against Counterfeit ICs
GC-Steering: GC-Aware Request Steering and Parallel Reconstruction Optimizations for SSD-Based RAIDs
Accelerating Graph-Connected Component Computation With Emerging Processing-In-Memory Architecture
On path selection in combinational logic circuits
Pattern matching and refinement hybrid approach to circuit comparison
Dynamic Test Compaction of a Compressed Test Set Shared Among Logic Blocks
Parametric Delay Test of Post-Bond Through-Silicon Vias in 3-D ICs via Variable Output Thresholding Analysis
A Parameter Extraction Method for LC Circuit of DB-BPF Based on Fully Connected Network
Process-Driven Variability Analysis of Single and Multiple Voltage-Frequency Island Latency-Constrained Systems
TVTAC: Triple Voltage Threshold Approximate Cache for Energy Harvesting Nonvolatile Processors
A Reduced State-Space Generation Method for Concurrent Systems Based on CPN-PR Model
Dual Multimodal Fusions With Convolution and Transformer Layers for VLSI Congestion Prediction
Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint
Enhanced Double Via Insertion Using Wire Bending
VoxImp: Impedance Extraction Simulator for Voxelized Structures
Parameter Optimization of VLSI Placement Through Deep Reinforcement Learning
HEDALS: Highly Efficient Delay-Driven Approximate Logic Synthesis
Ferroelectric FET-Based Implementation of FitzHugh-Nagumo Neuron Model
Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays
Using global code motions to improve the quality of results for high-level synthesis
DVLASIC: catastrophic fault yield simulation in a distributed processing environment
PBS: proven Boolean simplification
Quadratic zero-one programming-based synthesis of application-specific data paths
Built-In Self-Heating Thermal Testing of FPGAs
Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction
An algorithm for multiple output minimization
Error Detection Architectures for Hardware/Software Co-Design Approaches of Number-Theoretic Transform
Quantitative Robustness for Signal Temporal Logic With Time-Freeze Quantifiers
Energy-Efficient Multiobjective Thermal Control for Liquid-Cooled 3-D Stacked Architectures
Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences
Bottleneck removal algorithm for dynamic compaction in sequential circuits
Optimizing resource utilization using transformations
DBB-ECC: Random Double Bit and Burst Error Correction Code for HBM3
Current testability analysis of feedback bridging faults in CMOS circuits
An integral equation of the second kind for computation of capacitance
Interconnect Criticality-Driven Delay Relaxation
Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies
Revisiting Assumptions Ordering in CAR-Based Model Checking
A digital design flow for secure integrated circuits
Enhanced Design Flow and Optimizations for Multiproject Wafers
Routability-driven technology mapping for lookup table-based FPGA's
TF-Predictor: Transformer-Based Prerouting Path Delay Prediction Framework
The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis
Bridging Mismatched Granularity Between Embedded File Systems and Flash Memory
Two Approaches for Timing-Driven Placement by Lagrangian Relaxation
Contamination-Aware Synthesis for Programmable Microfluidic Devices
RV-SCNN: A RISC-V Processor With Customized Instruction Set for SNN and CNN Inference Acceleration on Edge Platforms
Testing SoC interconnects for signal integrity using extended JTAG architecture
Cooperative Communication Between Two Transiently Powered Sensor Nodes by Reinforcement Learning
Input space-adaptive optimization for embedded-software synthesis
An SOS MOSFET model based on calculation of the surface potential
2-D Inductor-Capacitor Lattice Synthesis
Toward massively parallel automatic test generation
State Separate Modular Modeling Methodology of Multioutput DC-DC Converters
A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration
AxFTL: Exploiting Error Tolerance for Extending Lifetime of NAND Flash Storage
A new reasoning scheme for efficient redundancy addition and removal
High-Dimensional Uncertainty Quantification of Electronic and Photonic IC With Non-Gaussian Correlated Process Variations
Interval-Valued Reduced-Order Statistical Interconnect Modeling
A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation
An Efficient Timing Model for CMOS Combinational Logic Gates
Optimal net assignment
Automated Energy/Performance Macromodeling of Embedded Software
Electrical-logic simulation and its applications
HLS-Based Approach for Embedded Real-Time Ray Tracing in Wireless Communications
Algorithmic Aspects of One-Dimensional Layout Compaction
A physics-based semiconductor noise model suitable for efficient numerical implementation
Alleviating Scalability Limitation of Accelerator-Based Platforms
Leveraging the Interplay of RAID and SSD for Lifetime Optimization of Flash-Based SSD RAID
Dynamic Power Management of a System With a Two-Priority Request Queue Using Probabilistic-Model Checking
TSV Extracted Equivalent Circuit Model and an On-Chip Test Solution
EM-Fuzz: Augmented Firmware Fuzzing via Memory Checking
An Efficient Gustavson-Based Sparse Matrix-Matrix Multiplication Accelerator on Embedded FPGAs
FlowTune: End-to-End Automatic Logic Optimization Exploration via Domain-Specific Multiarmed Bandit
Overcoming the Tradeoff Between Accuracy and Compactness in Decision Diagrams for Quantum Computation
CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning Strategies
Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling
eLDPC: An Efficient LDPC Coding Scheme for Phase-Change Memory
A mapped Scharfetter-Gummel formulation for the efficient simulation of semiconductor device models
Dependent-Latch Identification in Reachable State Space
Built-In Self-Repair Schemes for Flash Memories
A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic
NPRC-I/O: An NoC-Based Real-Time I/O System With Reduced Contention and Enhanced Predictability
A boundary gradient search technique and its applications in design centering
Combinational test generation using satisfiability
XOR-AND-XOR Logic Forms for Autosymmetric Functions and Applications to Quantum Computing
Diagonal Matrix Regression Layer: Training Neural Networks on Resistive Crossbars With Interconnect Resistance Effect
An r-DFA-Based Layout Pattern Match Method Supporting Fuzzy Matching
MNSIM: Simulation Platform for Memristor-Based Neuromorphic Computing System
Logical effort model extension to propagation delay representation
Layout Decomposition and Legalization for Double-Patterning Technology
Power efficient technology decomposition and mapping under an extended power consumption model
A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations
Probability models for pseudorandom test sequences
A Fast-Timing Simulator for Digital MOS Circuits
SPICE models for flicker noise in p-MOSFETs in the saturationregion
Functional Design-for-Testability for Functional Test Sequences
Fast Vectorless Power Grid Verification Under an RLC Model
DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies
Corrections to "Physically Rigorous Modeling of Internal Laser-Probing Techniques for Microstructured Semiconductor Devices"
On necessary and nonconflicting assignments in algorithmic test pattern generation
Local memory exploration and optimization in embedded systems
Enabling Security-Enhanced Attestation With Intel SGX for Remote Terminal and IoT
On X-Variable Filling and Flipping for Capture-Power Reduction in Linear Decompressor-Based Test Compression Environment
Golden-Free Robust Age Estimation to Triage Recycled ICs
AdaptHM: A Fully Adaptive Data Migration Strategy for Hybrid Memory Systems
Formal Verification of Resource Synchronization Protocol Implementations: A Case Study in RTEMS
Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time Analysis
Retiming and clock scheduling for digital circuit optimization
Testability-Driven Statistical Path Selection
Semi-Automatic Generation of Device Drivers for Rapid Embedded Platform Development
ECO Optimization Using Metal-Configurable Gate-Array Spare Cells
Automatic grid refinement and higher order flux discretization for diffusion modeling
A fast algorithm for OR-AND-OR synthesis
MATCH: Model-Aware TVM-Based Compilation for Heterogeneous Edge Devices
Strongly NP-hard discrete gate-sizing problems
On n-detection test sets and variable n-detection test sets fortransition faults
An improved two-dimensional simulation model (MEGA) for GaAs MESFET applicable to LSI design
Toward Secure Checkpointing for Micro-Electrode-Dot-Array Biochips
ORACALL: An Oracle-Based Attack on Cellular Automata Guided Logic Locking
Worst Case O(N) Comparison-Free Hardware Sorting Engine
Crosstalk in VLSI interconnections
Hibernus++: A Self-Calibrating and Adaptive System for Transiently-Powered Embedded Devices
Analysis and optimization of structured power/ground networks
An improved two-way partitioning algorithm with stable performance [VLSI]
Formulations for the Estimation of IMD Levels in an Envelope Feedback RFIC Amplifier: An Extension to Dynamic AM and PM Behavior
An improved long distance treatment for mutual inductance
Pulse-Vanishing Test for Interposers Wires in 2.5-D IC
A global router with a theoretical bound on the optimal solution
Direct Mapping of Low-Latency Asynchronous Controllers From STGs
HuNT: Exploiting Heterogeneous PIM Devices to Design a 3-D Manycore Architecture for DNN Training
Dynamic-II Pipeline: Compiling Loops With Irregular Branches on Static-Scheduling CGRA
Evaluating Statistical Power Optimization
X-Canceling MISR Architectures for Output Response Compaction With Unknown Values
INDRA: Intrusion Detection Using Recurrent Autoencoders in Automotive Embedded Systems
SASDenSebLE: A Compact Vision Transformer Inference Architecture With Saturation-Approximate Softmax Dataflow Enabling Sequence-Parallelism Boosted Layer-Fusion Execution
Don't cares in synthesis: theoretical pitfalls and practical solutions
Efficient Block Storage in the Cloud
A-Stable and L-Stable High-Order Integration Methods for Solving Stiff Differential Equations
Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips
Resistance Extraction from Mask Layout Data
An efficient transient analysis algorithm for mildly nonlinearcircuits
An All-MOSFET Voltage Reference-Based PUF Featuring Low BER Sensitivity to VT Variations and 163 fJ/Bit in 180-nm CMOS
Minimization of the number of layers for single row routing with fixed street capacity
Hardware-Enabled Efficient Data Processing With Tensor-Train Decomposition
A timing-driven pseudoexhaustive testing for VLSI circuits
Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation
An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing
The effect of placement of automatically extracted structure
A Scalable, Memory-Efficient Algorithm for Minimum Cycle Mean Calculation in Directed Graphs
Fault equivalence identification in combinational circuits using implication and evaluation techniques
Learned Approximate Computing: Algorithm Hardware Co-Optimization
MinMaxEntropy: Bound Model Errors for Side-Channel Leakages From Information Theory
Silicon-Proven ASIC Design for the Polynomial Operations of Fully Homomorphic Encryption
Balancing the Numbers of Detected Faults for Improved Test Set Quality
Retention Trimming for Lifetime Improvement of Flash Memory Storage Systems
Catch the Star: Weight Recovery Attack Using Side-Channel Star Map Against DNN Accelerator
C-Testing and Efficient Fault Localization for AI Accelerators
ReSPIR: A Response Surface-Based Pareto Iterative Refinement for Application-Specific Design Space Exploration
Numerical modeling of nonplanar oxidation coupled with stress effects
VECBEE: A Versatile Efficiency-Accuracy Configurable Batch Error Estimation Method for Greedy Approximate Logic Synthesis
Efficient extra material critical area algorithms
On designing universal logic blocks and their application to FPGA design
The Implementation and Optimization of Neuromorphic Hardware for Supporting Spiking Neural Networks With MLP and CNN Topologies
ArSMART: An Improved SMART NoC Design Supporting Arbitrary-Turn Transmission
Template-based MOSFET device model
Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System
ESM: A Plug-in Power Side Channel Shuffling Protection for Scalar Processors
Mitigating and Tolerating Read Disturbance in STT-MRAM-Based Main Memory via Device and Architecture Innovations
HyperSpikeASIC: Accelerating Event-Based Workloads With HyperDimensional Computing and Spiking Neural Networks
A Hybrid Approach for Fast and Accurate Trace Signal Selection for Post-Silicon Debug
RoboSpike: Fully Utilizing the Heterogeneous System With Subcallback Scheduling in ROS 2
DCP-CNN: Efficient Acceleration of CNNs With Dynamic Computing Parallelism on FPGA
PipePIM: Maximizing Computing Unit Utilization in ML-Oriented Digital PIM by Pipelining and Dual Buffering
3-Step Rectilinear Minimum Spanning Tree Construction for Obstacle-Avoiding Component-to-Component Routing
Formal Synthesis of Neural Barrier Certificates for Dynamical Systems via DC Programming
Using an asymmetric error model to study aliasing in signature analysis registers
A divide-and-conquer algorithm for 3-D capacitance extraction
NV-APP: Invalid Programming Performance Improved No-Verify and Adaptive Pulse Programming Scheme for 3-D QLC nand Flash
DTATrans: Leveraging Dynamic Token-Based Quantization With Accuracy Compensation Mechanism for Efficient Transformer Architecture
Securing SoCs With FPGAs Against Rowhammer Attacks
PAC Model Checking of Black-Box Continuous-Time Dynamical Systems
A Multiloop and Full Amplitude Hysteresis Model for Molecular Electronics
ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction
Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments
A library compatible driver output model for on-chip RLC transmission lines
Energy Minimization for Multicore Platforms Through DVFS and VR Phase Scaling With Comprehensive Convex Model
Leakage Models for High-Level Power Estimation
Meshed Bluetree: Time-Predictable Multimemory Interconnect for Multicore Architectures
A Formal Approach to Design-Rule Checking
GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits
A Best-First Search Algorithm for Optimal PLA Folding
Correction to "Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability"
PDF: Path-Oriented, Derivative-Free Approach for Safety Falsification of Nonlinear and Nondeterministic CPS
INFORM: Inverse Design Methodology for Constrained Multiobjective Optimization
HS: a hierarchical search package for CAD data
Integrated parametric timing optimization of digital systems
Wirelength minimization for min-cut placements via placement feedback
Advance Interconnect Circuit Modeling Design Using Fractional-Order Elements
An Efficient Data Migration Scheme to Optimize Garbage Collection in SSDs
TransCODE: Co-Design of Transformers and Accelerators for Efficient Training and Inference
Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools
EnsGuard: A Novel Acceleration Framework for Adversarial Ensemble Learning
Realization of Logic Functions Using Switching Lattices Under a Delay Constraint
Current Lines and Accurate Contact Current Evaluation in 2-D Numerical Simulation of Semiconductor Devices
Analyzing Functional Coverage in Bounded Model Checking
Realizable Reduction of RC Networks
Computing the Perturbation Projection Vector of Oscillators via Frequency Domain Analysis
State Asymmetry Driven State Remapping in Phase Change Memory
Gate Sizing for Cell-Library-Based Designs
A CMOS fault extractor for inductive fault analysis
Combinational Logic Design Using Six-Terminal NEM Relays
Task scheduling for exploiting parallelism and hierarchy in VLSI CAD algorithms
Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test
MOS Table Models for Fast and Accurate Simulation of Analog and Mixed-Signal Circuits Using Efficient Oscillation-Diminishing Interpolations
Fast FPGA Accelerator of Graph Cut Algorithm With Threshold Global Relabel and Inertial Push
An Efficient Network-on-Chip Yield Estimation Approach Based on Gibbs Sampling
COALA: Concurrently Assigning Wire Segments to Layers for 2-D Global Routing
Cost-Effective Robustness in Clock Networks Using Near-Tree Structures
Fast Surrogate-Assisted Constrained Multiobjective Optimization for Analog Circuit Sizing via Self-Adaptive Incremental Learning
Toffoli network synthesis with templates
Statistical clock skew analysis considering intradie-process variations
Monte Carlo Simulation of the Photoelectron Crosstalk in Silicon Imaging Devices
Synthesis of fully testable circuits from BDDs
Formal Analysis of End-Around-Carry Adder in Floating-Point Unit
Sequence compaction for power estimation: theory and practice
Non-isothermal extension of the Scharfetter-Gummel technique for hot carrier transport in heterostructure simulations
Bitwise scheduling to balance the computational cost of behavioral specifications
Robust Extraction of Spatial Correlation
Computing signal delay in general RC networks by tree/link partitioning
Software-controlled processor speed setting for low-power streamingmultimedia
Scalable Synthesis and Clustering Techniques Using Decision Diagrams
Redundancy and testability in digital filter datapaths
Multicast FullHD H.264 Intra Video Encoder Architecture
ECO Timing Optimization Using Spare Cells and Technology Remapping
Compact Modeling of Nonlinear Analog Circuits Using System Identification via Semidefinite Programming and Incremental Stability Certification