yusuke1997/dblp-id-title huggingface dataset:
A 63 dB SNR, 75-mW Bandpass RF ΣΔ ADC at 950 MHz Using 3.8-GHz Clock in 0.25-µm SiGe BiCMOS Technology
A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver
Fully integrated passive UHF RFID transponder IC with 16.7-μW minimum RF input power
A subnanosecond clock Josephson 4-bit processor
A Broadband Low-Cost Direct-Conversion Receiver Front-End in 90 nm CMOS
A 25.1-TOPS/W Sparsity-Aware Hybrid CNN-GCN Deep Learning SoC for Mobile Augmented Reality
A 2.4 GHz Interferer-Resilient Wake-Up Receiver Using A Dual-IF Multi-Stage N-Path Architecture
A CMOS integrated capacitive fingerprint sensor with 32-bit RISC microcontroller
A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques
A 25 3 μW at 60 fps 240 × 160 Pixel Vision Sensor for Motion Capturing With In-Pixel Nonvolatile Analog Memory Using CAAC-IGZO FET
A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC
A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling
A frequency-agile single-chip QAM modulator with beamforming diversity
A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS
A 112-Gb/s - 8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes
Bidirectional Communication Circuits for a 120-GHz PMF Data Link in 40-nm CMOS
A low-jitter mixed-mode DLL for high-speed DRAM applications
Analysis of the switching speed of BiCMOS buffer under high current
A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler
A 0.42-mW 1-Mb/s 3- to 4-GHz Transceiver in 0.18-µm CMOS With Flexible Efficiency, Bandwidth, and Distance Control for IoT Applications
Pseudo-complementary FET logic (PCFL): a low-power logic family in GaAs
An extended Tanh law MOSFET model for high temperature circuit simulation
InP D-HBT ICs for 40-Gb/s and higher bitrate lightwave transceivers
A 110 nW Resistive Frequency Locked On-Chip Oscillator with 34.3 ppm/°C Temperature Stability for System-on-Chip Designs
A 40 nm CMOS 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers
An antifuse EPROM circuitry scheme for field-programmable repair in DRAM
A 48.6-to-105.2 µW Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications
Fast-access BiCMOS SRAM architecture with a V SS generator
Improved Power/EM Side-Channel Attack Resistance of 128-Bit AES Engines With Random Fast Voltage Dithering
A Receiver Architecture for Dual-Antenna Systems
New Associate Editors
A 915 MHz, Ultra-Low Power 2-Tone Transceiver With Enhanced Interference Resilience
Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation
A 700-MHz switched-capacitor analog waveform sampling circuit
Design and Self-Calibration Techniques for Inductor-Less Millimeter-Wave Frequency Dividers
Static CMOS latch-up considerations in HVIC design
RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter
0.5-V analog circuit techniques and their application in OTA and filter design
An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks
A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier
A Class-F CMOS Oscillator
An Energy-Efficient Discrete-Time Delta-Sigma Modulator With Dynamic-Range Enhancement and Tri-Level CDAC
Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz
An efficient scaling procedure for domain CMOS logic
TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization
Pipelined delay-sum architecture based on bucket-brigade devices for on-chip ultrasound beamforming
A High-Voltage Dual-Input Buck Converter Achieving 52.9% Maximum End-to-End Efficiency for Triboelectric Energy-Harvesting Applications
A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL
A 14-bit current-mode ΣΔ DAC based upon rotated data weighted averaging
A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bits at Nyquist
A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS
A Pipeline Replica Bitline Technique for Suppressing Timing Variation of SRAM Sense Amplifiers in a 28-nm CMOS Process
Design and Analysis of Ka-Band Variable-Gain Phase Shifter With Impedance-Invariant Vector Modulation
Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery
Compact and Supply-Voltage-Scalable Temperature Sensors for Dense On-Chip Thermal Monitoring
A 1-V +31 dBm IIP3, Reconfigurable, Continuously Tunable, Power-Adjustable Active-RC LPF
Decoded-source sense amplifier for high-density DRAMs
An all DC-powered Josephson logic circuit
Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating
A mm-Wave Frequency Modulated Transmitter Array for Superior Resolution in Angular Localization Supporting Low-Latency Joint Communication and Sensing
Automatic phase alignment for a fully integrated Cartesian feedback power amplifier system
An Asymmetrical QPSK/OOK Transceiver SoC and 15: 1 JPEG Encoder IC for Multifunction Wireless Capsule Endoscopy
A Millimeter-Wave Circuit Technique
An ISDN echo-cancelling transceiver chip set for 2B1Q coded U-interface
An EEG Acquisition and Biomarker-Extraction System Using Low-Noise-Amplifier and Compressive-Sensing Circuits Based on Flexible, Thin-Film Electronics
A 0.13-µm CMOS SoC for Simultaneous Multichannel Optogenetics and Neural Recording
A 22.8-26.0-GHz VCO With Discriminative-Harmonic-Current-Manipulating for Phase Noise Improvement
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache
A 103.125-Gb/s Reverse Gearbox IC in 40-nm CMOS for Supporting Legacy 10- and 40-GbE Links
Near speed-of-light signaling over on-chip electrical interconnects
A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel
A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery
A Bipolar-Input Thermoelectric Energy-Harvesting Interface With Boost/Flyback Hybrid Converter and On-Chip Cold Starter
A 164- $\mu$ W 915-MHz Sub-Sampling Phase-Tracking Zero-IF Receiver With 5-Mb/s Data Rate for Short-Range Applications
A low-power 1-GHz super-regenerative transceiver with time-shared PLL control
A Distributed Oscillator Based All-Digital PLL With a 32-Phase Embedded Phase-to-Digital Converter
An AC Input Switching-Converter-Free LED Driver With Low-Frequency-Flicker Reduction
A power-efficient single-chip OFDM demodulator and channel decoder for multimedia broadcasting
Recryptor: A Reconfigurable Cryptographic Cortex-M0 Processor With In-Memory and Near-Memory Computing for IoT Security
A 45 nm 8-Core Enterprise Xeon¯ Processor
A Reference-Less Single-Loop Half-Rate Binary CDR
A 60 GHz Antenna-Referenced Frequency-Locked Loop in 0.13 µ CMOS for Wireless Sensor Networks
G m -boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18-μm CMOS
A Scalable 32-56 Gb/s 0.56-1.28 pJ/b Voltage-Mode VCSEL-Based Optical Transmitter in 28-nm CMOS
A 29-mm 2 , 1.8-V-only, 16-Mb DINOR flash memory with gate-protected-poly-diode (GPPD) charge pump
A 9 b, 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue
An 8 Ω 2.5 W 1%-THD 104 dB(A)-Dynamic-Range Class-D Audio Amplifier With Ultra-Low EMI System and Current Sensing for Speaker Protection
A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS
Comments on "Cancellation of OpAmp Virtual Ground Imperfections by a Negative Conductance Applied to Improve RF Receiver Linearity"
A 389 TOPS/W, Always ON Region Proposal Integrated Circuit Using In-Memory Computing in 65 nm CMOS
A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking
A 1.9-mW 750-kb/s 2.4-GHz F-OOK Transmitter With Symmetric FM Template and High-Point Modulation PLL
A Quantization Noise Suppression Technique for$DeltaSigma$Fractional-$N$Frequency Synthesizers
A Low-Spurious Low-Power 12-bit 160-MS/s DAC in 90-nm CMOS for Baseband Wireless Transmitter
An ASIC for Hartmann-Shack wavefront detection
120-Gb/s multiplexing and 110-Gb/s demultiplexing ICs
A 350 µW CMOS MSK Transmitter and 400 µW OOK Super-Regenerative Receiver for Medical Implant Communications
An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback
A multilevel parasitic interconnect capacitance modeling and extraction for reliable VLSI on-chip clock delay evaluation
A Portable Micro Gas Chromatography System for Lung Cancer Associated Volatile Organic Compound Detection
3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver
Single Photon-Counting Pixel Readout Chip Operating Up to 1.2 Gcps/mm 2 for Digital X-Ray Imaging Systems
CMOS current reference without resistance
A 14-b Energy-Efficient BW/Power Scalable CTDSM With a Frequency-Controlled Current Source
A submicrometer NMOS multiplexer-demultiplexer chip set for 622.08-Mb/s SONET applications
High-speed low-power AC-coupled complementary push-pull ECL circuit
A 640 $\times$ 640 Fully Dynamic CMOS Image Sensor for Always-On Operation
An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-μm CMOS
A Recursive Switched-Capacitor DC-DC Converter Achieving 2 N -1 Ratios With High Efficiency Over a Wide Output Voltage Range
A 12.8 GS/s Time-Interleaved ADC With 25 GHz Effective Resolution Bandwidth and 4.6 ENOB
A 50.7-dB-DR Finger-Resistance Extracting Multi-Touch Sensor IC for Soft Classification of Fingers Contacted on 6.7-in Capacitive Touch Screen Panel
A 20 K GaAs array with 10 K of embedded SRAM
A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS
A 0.46-THz 25-Element Scalable and Wideband Radiator Array With Optimized Lens Integration in 65-nm CMOS
Introduction to the Special Issue on ESSCIRC 2006
Test generation for data-path logic: the F-path method
SILAS: a knowledge-based simulation assistant
A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC
A 110-K transistor 25-MPixels/s configurable image transform processor unit
A 3-Phase Resonant Switched Capacitor Converter Delivering 7.7 W at 85% Efficiency Using 1.1 nH PCB Trace Inductors
A 13b 600-675MS/s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Residue Amplifier
Design of a 15-MHz CMOS continuous-time filter with on-chip tuning
A 58-nm 2-Gb MLC "B4-Flash" Memory with Flexible Multisector Architecture
A Broadband Spectrum Channelizer With PWM-LO-Based Sub-Band Gain Control
A fully integrated 0.18-μm CMOS direct conversion receiver front-end with on-chip LO for UMTS
A CMOS GSM IF-sampling circuit with reduced in-channel aliasing
A 60-MS/s 5-MHz BW Noise-Shaping SAR ADC With Integrated Input Buffer Achieving 84.2-dB SNDR and 97.3-dB SFDR Using Dynamic Level-Shifting and ISI-Error Correction
A High IIP2 SAW-Less Superheterodyne Receiver With Multistage Harmonic Rejection
A 12-ps-resolution digital variable-delay macro cell on GaAs 100 K-gates gate array using a meshed air bridge structure
A sixth-order continuous-time bandpass sigma-delta modulator for digital radio IF
A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation
Low-insertion-loss DP3T MMIC switch for dual-band cellular phones
A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration
Hybrid CMOS/GaN 40-MHz Maximum 20-V Input DC-DC Multiphase Buck Converter
An integrated switched-capacitor signal processing design system
A 14-ns 14-Mb CMOS DRAM with 300-mW active power
An embedded 32-b microprocessor core for low-power and high-performance applications
A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion
A Filtering ΔΣ ADC for LTE and Beyond
A 3-µW CMOS Glucose Sensor for Wireless Contact-Lens Tear Glucose Monitoring
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET
A 900-MHz RF front-end with integrated discrete-time filtering
A 5-MHz 91% Peak-Power-Efficiency Buck Regulator With Auto-Selectable Peak- and Valley-Current Control
A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search
High-speed, highly sensitive OEIC using clocked vertical BJT's photoDarlington in CMOS technology
A 30 Gb/s/Link 2.2 Tb/s/mm 2 Inductively-Coupled Injection-Locking CDR for High-Speed DRAM Interface
The first MAJC microprocessor: a dual CPU system-on-a-chip
A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors
A High-Current-Efficiency Digital-Assisted Analog LDO With Dual-Biasing Mode for Near-Threshold Regulation
An accurate analytical propagation delay model for high-speed CML bipolar circuits
Even-Harmonic Class-E CMOS Oscillator
An 800-MHz embedded DRAM with a concurrent refresh mode
A 2.4-2.5 GHz WLAN Direct-Conversion Receiver Front-End With Low-Distortion Baseband Filters
A Low-Power Wideband Reconfigurable Integrated Active-RC Filter With 73 dB SFDR
A compact rail-to-rail output stage for CMOS operational amplifiers
A BiCMOS limiting amplifier for SONET OC-3
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS
The SDC cell-A novel design methodology for high-speed arithmetic modules using CMOS/BiCMOS precharged circuits
A 85-dB dynamic range multibit delta-sigma ADC for ADSL-CO applications in 0.18-μm CMOS
A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio
An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and -98 dB THD
A 0.25-mW low-pass passive sigma-delta modulator with built-in mixer for a 10-MHz IF input
A CMOS continuous-time NTSC-to-color-difference decoder
An 802.11a/b/g/n/ac WLAN Transceiver for 2×2 MIMO and Simultaneous Dual-Band Operation With +29 dBm P sat Integrated Power Amplifiers
HBT transmitter and data regenerator arrays for WDM optical communications application
An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS
A Fully Integrated Counter Flow Energy Reservoir for Peak Power Delivery in Small Form-Factor Sensor Systems
Design of Highly Efficient Wideband RF Polar Transmitters Using the Envelope-Tracking Technique
Delta-sigma modulators using frequency-modulated intermediate values
A Fully Integrated Energy-Efficient H.265/HEVC Decoder With eDRAM for Wearable Devices
A scalable switched-capacitor filter implemented in 1.25- mu m technology
A high-dynamic-range CMOS image sensor for automotive applications
Corrections to "A General Theory of Phase Noise in Electrical Oscillators"
A Millimeter-Scale Single Charged Particle Dosimeter for Cancer Radiotherapy
Low-jitter digital timing recovery techniques for CAP-based VDSL applications
A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory
A baseband codec for digital cellular telephony
A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery
Thermal coupling in integrated circuits: application to thermal testing
Device mismatch and tradeoffs in the design of analog circuits
A 500-Mb/s soft-output Viterbi decoder
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS
An accurate biomedical temperature transducer with on-chip microcomputer interfacing
An RF Receiver for Intra-Band Carrier Aggregation
High-performance low-power dual transition preferentially sized (DTPS) logic
Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor
A 10-Bit Column-Driver IC With Parasitic-Insensitive Iterative Charge-Sharing Based Capacitor-String Interpolation for Mobile Active-Matrix LCDs
Design Considerations for a 11.3 Gbit/s SiGe Bipolar Driver Array With a 5 × 6 V pp Chip-to-Chip Bondwire Output to an MZM PIC
A High-Density 45 nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing
A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator
A Low-Phase-Noise Multi-Phase Oscillator Based on Left-Handed LC-Ring
A Fully Integrated Cryo-CMOS SoC for State Manipulation, Readout, and High-Speed Gate Pulsing of Spin Qubits
Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC)
A 24 to 30-GHz Phased Array Transceiver Front End With 2.8 to 3.1-dB RX NF and 22 to 24% TX Peak Efficiency
A circuit concept for reducing soft error in high-speed memory cells
A CMOS smart temperature sensor with a 3σ inaccuracy of ±0.5°C from -50°C to 120°C
A 5-GHz SiGe HBT return-to-zero comparator for RF A/D conversion
New single-clock CMOS latches and flipflops with improved speed and power savings
A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth
An Injection-Locked Ring-Oscillator-Based Fractional-N Digital PLL Supporting BLE Frequency Modulation
A TX VCO for WCDMA/EDGE in 90 nm RF CMOS
Testing of differential cascode voltage switch one-count generators
A monolithic digital clock-generator for on-chip clocking of custom DSP's
A 10 nW-1µW Power Management IC With Integrated Battery Management and Self-Startup for Energy Harvesting Applications
A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter
A Compact 77% Fractional Bandwidth CMOS Band-Pass Distributed Amplifier With Mirror-Symmetric Norton Transforms
A 2.7-4.5 V single chip GSM transceiver RF integrated circuit
A 90-nm CMOS 1.8-V 2-Gb NAND flash memory for mass storage applications
Gigahertz-band high-gain GaAs monolithic amplifiers using parallel feedback technique
An Inductorless 20-Gb/s CDR With High Jitter Tolerance
A Flexible Phased-Array Architecture for Reception and Rapid Direction-of-Arrival Finding Utilizing Pseudo-Random Antenna Weight Modulation and Compressive Sampling
Fast Low Power eDRAM Hierarchical Differential Sense Amplifier
A programmable multi-channel CMOS pulser chip to drive ultrasonic array transducers
A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS
A 951-fs rms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator
A Pixelated Monolithic CMOS PPG Sensor for Spatial Feature Acquisition
An alpha -immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell
A 0.13 µm SiGe BiCMOS Technology Featuring f T /f max of 240/330 GHz and Gate Delays Below 3 ps
An Integrated 0.6-4.6 GHz, 5-7 GHz, 10-14 GHz, and 20-28 GHz Frequency Synthesizer for Software-Defined Radio Applications
High-speed current-mode logic amplifier using positive feedback and feed-forward source-follower techniques for high-speed CMOS I/O buffer
Substrate noise coupling through planar spiral inductor
Analysis and modeling of bang-bang clock and data recovery circuits
A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits
A 0.25 V 460 nW Asynchronous Neural Signal Processor With Inherent Leakage Suppression
A 120-MHz BiCMOS superscalar RISC processor
A concurrent error detection IC in 2-μm static CMOS logic
A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With ≪ -16 dB Return Loss Over 10 GHz Bandwidth
A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS
Integrated Line Driver for Digital Pulse-Width Modulation Driven AMOLED Displays on Flex
User Customizable Logic Paper (UCLP) With Sea-Of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects
1.25-Gb/s burst-mode receiver ICs with quick response for PON systems
A signal-swing suppressing strategy for power and layout area savings using time-multiplexed differential data-transfer scheme
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector
A subscriber digital signal processor LSI for PCM applications
A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line
A 2-GHz clocked AlGaAs/GaAs HBT byte-slice datapath chip
An Emulated Curve Assisted Fast-Transient Buck Converter With One-Cycle Charge Balance
A 0.0056-mm 2 -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs
A 0.003 mm 2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching
A rail-to-rail, constant gain, buffered op-amp for real time video applications
A Fully-Integrated 16-Element Phased-Array Receiver in SiGe BiCMOS for 60-GHz Communications
Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's
A 1920 × 1080 Array 2-D/3-D Image Sensor With 3-μ s Row-Time Single-Slope ADC and 100-MHz Demodulated PPD Locked-In Pixel
Daedalus: A Physics-Inspired Mixed-Signal Optimization Engine With Dynamic Continuous-Time Injection for Solving 3-SAT Problems
All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS
A 0.016 mm 2 0.26- $\mu$ W/MHz 60-240-MHz Digital PLL With Delay-Modulating Clock Buffer in 65 nm CMOS
A 40-MHz-to-1-GHz Fully Integrated Multistandard Silicon Tuner in 80-nm CMOS
Leading-zero anticipatory logic for high-speed floating point addition
A 64-MHz clock-rate ΣΔ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency
PICO-RAM: A PVT-Insensitive Analog Compute-In-Memory SRAM Macro With In Situ Multi-Bit Charge Computing and 6T Thin-Cell-Compatible Layout
High-speed on-chip ECC for synergistic fault-tolerance memory chips
Design for concurrent error detection and testability in storage/logic arrays
A robust single phase clocking for low power, high-speed VLSI applications
A CMOS Code-Modulated Path-Sharing Multi-Antenna Receiver Front-End
An Automotive LiDAR SoC for 240 × 192-Pixel 225-m-Range Imaging With a 40-Channel 0.0036-mm 2 Voltage/Time Dual-Data-Converter-Based AFE
Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump
A 50 dB variable gain amplifier using parasitic bipolar transistors in CMOS
A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC
Substrate coupling evaluation in BiCMOS technology
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time
A Broadband Linear Ultra-Compact mm-Wave Power Amplifier With Distributed-Balun Output Network: Analysis and Design
A 20-pW Discontinuous Switched-Capacitor Energy Harvester for Smart Sensor Applications
Time-Interleaved Switched Emitter Followers to Extend Front-End Sampling Rates to up to 200 GS/s
A 10 ps Time-Resolution CMOS Image Sensor With Two-Tap True-CDS Lock-In Pixels for Fluorescence Lifetime Imaging
A CMOS uncooled heat-balancing infrared imager
A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation
Minimum achievable phase noise of RC oscillators
Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter
A second-order double-sampled delta-sigma modulator using individual-level averaging
A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers
A 0.6-1.8-mW 3.4-dB NF Mixer-First Receiver With an N-Path Harmonic-Rejection Transformer-Mixer
A 200-mA Digital Low Drop-Out Regulator With Coarse-Fine Dual Loop in Mobile Application Processor
Monostatic and Bistatic G-Band BiCMOS Radar Transceivers With On-Chip Antennas and Tunable TX-to-RX Leakage Cancellation
A 0.6 V Input CCM/DCM Operating Digital Buck Converter in 40 nm CMOS