yusuke1997/dblp-id-title huggingface dataset:
Fixed-Order Placement of Pipelined Architecture in Rapid Single-Flux-Quantum Circuits
X-Former: In-Memory Acceleration of Transformers
Efficient VLSI architectures for Columnsort
Securing Against Side-Channel Attacks With Wide-Range In Situ Random Voltage Dithering on Async-Logic AES Engine
A Flexible Parallel Hardware Architecture for AdaBoost-Based Real-Time Object Detection
A 28 nm Dual-Mode SRAM-CIM Macro With Local Computing Cell for CNNs and Grayscale Edge Detection
Analysis and Implementation of Multiple-Input, Multiple-Output VBLAST Receiver From Area and Power Efficiency Perspective
Toward High-Performance Network Coding: FPGA Acceleration With Bounded-Value Generators
A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM
Active Filter-Based Hybrid On-Chip DC-DC Converter for Point-of-Load Voltage Regulation
A Ring-Oscillator-Based Reliability Monitor for Isolated Measurement of NBTI and PBTI in High-k/Metal Gate Technology
System Architecture and Implementation of MIMO Sphere Decoders on FPGA
Content Addressable Memory - Early Predict and Terminate Precharge of Match-Line
Fault-sensitivity analysis and reliability enhancement of analog-to-digital converters
COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC
IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test
POLAR: A Pipelined/Overlapped FPGA-Based LSTM Accelerator
Low Latency Systolic Montgomery Multiplier for Finite Field $GF(2^{m})$ Based on Pentanomials
Built-In Self-Test of Transmitter I/Q Mismatch and Nonlinearity Using Self-Mixing Envelope Detector
Coupling Mitigation in 3-D Multiple-Stacked Devices
A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation
A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control
Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection
Publicly Verifiable Watermarking for Intellectual Property Protection in FPGA Design
Flexible Low-Cost Power-Efficient Video Memory With ECC-Adaptation
T/R Switch Composed of Three HV-MOSFETs With 12.1-μW Consumption That Enables Per-Channel Self-Loopback AC Tests and -18.1-dB Switching Noise Suppression for 3-D Ultrasound Imaging With 3072-Ch Transceiver
Gate leakage reduction for scaled devices using transistor stacking
Self-Test Techniques for Crypto-Devices
Revisiting the Itoh-Tsujii Inversion Algorithm for FPGA Platforms
CLIP: Circuit Level IC Protection Through Direct Injection of Process Variations
A Scalable Synthesis Methodology for Application-Specific Processors
A Variation Tolerant Current-Mode Signaling Scheme for On-Chip Interconnects
Design Specification for BER Analysis Methods Using Built-In Jitter Measurements
Yield improvement of a large area magnetic field sensor array using redundancy schemes
Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs
A methodology and design tools to support system-level VLSI design
Built-In Binary Code Inversion Technique for On-Chip Flash Memory Sense Amplifier With Reduced Read Current Consumption
Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout
Asynchronous Fine-Grain Power-Gated Logic
Cost-Effective Analytical Models of Resistive Opens Defects in FinFET Technology
On Reducing Test Power and Test Volume by Selective Pattern Compression Schemes
UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors
A VLSI Architecture for Image Registration in Real Time
A "flying-adder" architecture of frequency and phase synthesis with scalability
A Case for Asymmetric-Cell Cache Memories
Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array
Outer Loop Pipelining for Application Specific Datapaths in FPGAs
The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology
Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration
Area-Efficient Nano-AES Implementation for Internet-of-Things Devices
TSV Redundancy: Architecture and Design Issues in 3-D IC
A Generic and Scalable Architecture for a Large Acoustic Model and Large Vocabulary Speech Recognition Accelerator Using Logic on Memory
Resource-Efficient FPGA Architecture and Implementation of Hough Transform
Interconnect-based system-level energy and power prediction to guide architecture exploration
Efficient Low-Power Digital Baseband Transceiver for IEEE 802.15.6 Narrowband Physical Layer
Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators
PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors
Realizing a high measure of confidence for defect level analysis of random testing [VLSI]
A General Digit-Serial Architecture for Montgomery Modular Multiplication
Frequency-Locked RF Power Oscillator With 43-dBm Output Power and 58% Efficiency
A fault-tolerant permutation network modulo arithmetic processor
Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation
Design Techniques to Improve Blocker Tolerance of Continuous-Time ΔΣ ADCs
GALDS: a complete framework for designing multiclock ASICs and SoCs
Physical Attack Protection Techniques for IC Chip Level Hardware Security
A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS
A 16-Gb/s Low-Power Inductorless Wideband Gain-Boosted Baseband Amplifier With Skewed Differential Topology for Wireless Network-on-Chip
An Energy-Efficient and Wide-Range Voltage Level Shifter With Dual Current Mirror
Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks
Dynamic Neural Fields Accelerator Design for a Millimeter-Scale Tracking System
Fully CMOS-Compatible On-Chip Optical Clock Distribution and Recovery
Scalable Device Array for Statistical Characterization of BTI-Related Parameters
Automatic generation and compaction of March tests for memory arrays
Demonstrating HW-SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane
Robust Concurrent Online Testing of Network-on-Chip-Based SoCs
A Variation-Tolerant Near-Threshold Processor With Instruction-Level Error Correction
DMSA: An Efficient Architecture for Sparse-Sparse Matrix Multiplication Based on Distribute-Merge Product Dataflow
Implementation of micropipelines in enable/disable CMOS differential logic
A 32-bit carry lookahead adder using dual-path all-N logic
A 675 Mbps, 4 × 4 64-QAM K-Best MIMO Detector in 0.13 µm CMOS
Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults
Modular and rapid testing of SOCs with unwrapped logic blocks
A novel FPGA architecture supporting wide, shallow memories
Area-Efficient 128- to 2048/1536-Point Pipeline FFT Processor for LTE and Mobile WiMAX Systems
Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips
Code Acceleration Using Memristor-Based Approximate Matrix Multiplier: Application to Convolutional Neural Networks
Low-power operation using self-timed circuits and adaptive scaling of the supply voltage
SLECTS: Slew-Driven Clock Tree Synthesis
A New Optimal Algorithm for Energy Saving in Embedded System With Multiple Sleep Modes
New Bit Parallel Multiplier With Low Space Complexity for All Irreducible Trinomials Over GF(2 n )
Exposing Reliability Degradation and Mitigation in Approximate DNNs Under Permanent Faults
A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient
State-Aware Dynamic Frequency Selection Scheme for Energy-Harvesting Real-Time Systems
Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs
Hybrid Cascode Frequency Compensation for Four-Stage OTAs Driving a Wide Range of C L
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks
Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology
Peephole optimization of asynchronous macromodule networks
Sense and React: Self-Destructive Polymorphic Mechanism Against Voltage Tampered Active Physical Attacks
Low-Complexity VLSI Architecture for OTFS Transceiver Under Multipath Fading Channel
Antiwear Leveling Design for SSDs With Hybrid ECC Capability
Simultaneous V t selection and assignment for leakage optimization
A Simple Yet Efficient Accuracy-Configurable Adder Design
Test infrastructure design for mixed-signal SOCs with wrapped analog cores
Gigabit age microelectronics and their manufacture
An Adaptive Algorithm for Single-Electron Device and Circuit Simulation
Analysis and Design of a Multistage CMOS Band-Pass Low-Noise Preamplifier for Ultrawideband RF Receiver
Fuzzy logic approach to VLSI placement
Efficient Modeling of Transmission Lines With Electromagnetic Wave Coupling by Using the Finite Difference Quadrature Method
RMC_NoC: A Reliable On-Chip Network Architecture With Reconfigurable Multifunctional Channel
Bundle-Updatable SRAM-Based TCAM Design for OpenFlow-Compliant Packet Processor
Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver
A 4.86-pJ/b Energy-Efficient Fully Parallel Stochastic LDPC Decoder With Two-Stage Shared Memory
Worst Case Noise Prediction With Nonzero Current Transition Times for Power Grid Planning
Raising FPGA Logic Density Through Synthesis-Inspired Architecture
Write Current Self-Configuration Scheme for MRAM Yield Improvement
Interfacing synchronous and asynchronous modules within a high-speed pipeline
Fully differential optical interconnections for high-speed digital systems
BIST-based test and diagnosis of FPGA logic blocks
Routing architecture optimizations for high-density embedded programmable IP cores
Efficient Hardware Implementation of Encoder and Decoder for Golay Code
A Multi-Granularity Power Modeling Methodology for Embedded Processors
ARXON: A Framework for Approximate Communication Over Photonic Networks-on-Chip
74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations
A Low-Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2 m )
Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching
Optimal Runtime Algorithm to Improve Fault Tolerance of Bus-Based Reconfigurable Designs
An Efficient Hard-Detection GRAND Decoder for Systematic Linear Block Codes
High-performance automatic target recognition through data-specific VLSI
Nonlinearity Estimation for Compensation of Phase Interpolator in Bang-Bang CDRs
Extraction error modeling and automated model debugging in high-performance custom designs
Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation
Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods
A Fast Transient Response Distributed Power Supply With Dynamic Output Switching for Power Side-Channel Attack Mitigation
A 4T Low-Power Linear-Output Current-Mediated CMOS Image Sensor
Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall Caches
Economizing TSV Resources in 3-D Network-on-Chip Design
10-Gb/s Distributed Amplifier-Based VCSEL Driver IC With ESD Protection in 130-nm CMOS
Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA
Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs
Wire retiming as fixpoint computation
An Inter/Intra-Chip Optical Network for Manycore Processors
A Synergetic Use of Bloom Filters for Error Detection and Correction
Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration
Application-Dependent Testing of FPGAs
Memory Bandwidth Efficient Design for Super-Resolution Accelerators With Structure Adaptive Fusion and Channel-Aware Addressing
Multitimescale Mitigation for Performance Variability Improvement in Time-Critical Systems
Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell
Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees
Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes
Cyclic Sparsely Connected Architectures for Compact Deep Convolutional Neural Networks
A New Artificial Neural Network-Based Calibration Mechanism for ADCs: A Time-Interleaved ADC Case Study
On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS
ATPG for combinational circuits on configurable hardware
An Energy-Efficient L2 Cache Architecture Using Way Tag Information Under Write-Through Policy
Exploring the Design of Energy-Efficient Intermittently Powered Systems Using Reconfigurable Ferroelectric Transistors
A 0.6-V 9.38-Bit 6.9-kS/s Capacitor-Splitting Bypass Window SAR ADC for Wearable 12-Lead ECG Acquisition Systems
A Compact 0.9μ W Direct-Conversion Frequency Analyzer for Speech Recognition With Wide- Range Q-Controllable Bandpass Rectifier
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
An automated process for compiling dataflow graphs into reconfigurable hardware
Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance
A Runtime Framework for Robust Application Scheduling With Adaptive Parallelism in the Dark-Silicon Era
Skewed CMOS: noise-tolerant high-performance low-power static circuit family
A System Level Energy Model and Energy-Quality Evaluation for Integrated Transceiver Front-Ends
A Response-Nonlinearized DEMUX-TDC PUF for Resistance Against Modeling Attacks and Secure Authentication Protocols
An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation
Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding
Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization
Power Management of MIMO Network Interfaces on Mobile Systems
A Gaussian synapse circuit for analog VLSI neural networks
Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems
Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors
A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula
Optimization of throughput performance for low-power VLSI interconnects
An Efficient Polynomial Multiplication Accelerator for Lattice-Based Cryptography With a 2-D Winograd-Based Divide-and-Conquer Method
Architectural Modifications to Enhance the Floating-Point Performance of FPGAs
CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing
Extra Clocking of LFSR Seeds for Improved Path Delay Fault Coverage
A Compact High-Speed Capacitive Data Transfer Link With Common Mode Transient Rejection for Isolated Sensor Interfaces
Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures
Robust Secure Scan Design Against Scan-Based Differential Cryptanalysis
Unipolar Logic Gates Based on Spatial Wave-Function Switched FETs
Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error
Development of a Short-Term to Long-Term Supervised Spiking Neural Network Processor
Fixed-Point Computing Element Design for Transcendental Functions and Primary Operations in Speech Processing
A Fine-Grained Control Flow Integrity Approach Against Runtime Memory Attacks for Embedded Systems
Single-Bit Pseudoparallel Processing Low-Oversampling Delta-Sigma Modulator Suitable for SDR Wireless Transmitters
Ultrawideband Power-Switchable Transmitter With 17.7-dBm Output Power for See-Through-Wall Radar
Optimized Design of an LSSD Scan Cell
Flexible Biometric Online Speaker-Verification System Implemented on FPGA Using Vector Floating-Point Units
Dark Silicon Aware Multicore Systems: Employing Design Automation With Architectural Insight
A Bias-Dependent Model for the Impact of Process Variations on the SRAM Soft Error Immunity
An Efficient Reconfigurable Encoder for the IEEE 1901 Standard
An Efficient List Decoder Architecture for Polar Codes
Scalable Multilevel Vectorless Power Grid Voltage Integrity Verification
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications
Processor Tile Shapes and Interconnect Topologies for Dense On-Chip Networks
Guest Editorial Special Section On Impacts Of Emerging Technologies On VLSI Systems
Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint
Memristive Threshold Logic Circuit Design of Fast Moving Object Detection
A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs
DVFS-Based Long-Term Task Scheduling for Dual-Channel Solar-Powered Sensor Nodes
Thermal-Aware Fixed-Outline 3-D IC Floorplanning: An End-to-End Learning-Based Approach
Reliable and Error Detection Architectures of Pomaranch for False-Alarm-Sensitive Cryptographic Applications
Data Criticality in Multithreaded Applications: An Insight for Many-Core Systems
A Double-Data-Rate Ripple Counter With Calibration Circuits for Correlated Multiple Sampling in CMOS Image Sensors
Design of FPGA-Implemented Reed-Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory
All-Digital CMOS Pulse-Shrinking Time-to-Digital Converter With Built-in Offset-Error Cancellation and Smart Temperature Sensor
Design Exploration of Energy-Efficient Accuracy-Configurable Dadda Multipliers With Improved Lifetime Based on Voltage Overscaling
Guest editorial: System-level interconnect prediction
Stochastic Computing Using Amplitude and Frequency Encoding
Power estimation methods for sequential logic circuits
A Cellular Network Architecture With Polynomial Weight Functions
A New Pathway Toward Implementing a Fully Integrated Band-Switchable CMOS Power Amplifier Utilizing Bit Optimized Reconfigurable Network (BORN)
Impact of 3-D Integration on Thermal Performance of RISC-V MemPool Multicore SOC
Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators
Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's
Location Cache Design and Performance Analysis for Chip Multiprocessors
High Repair-Efficiency BISR Scheme for RAMs by Reusing Bitmap for Bit Redundancy
High Productivity Circuit Methodology for a Semi-Custom Embedded Processor
Large-signal two-terminal device model for nanoelectronic circuit analysis
Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates
ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips
Timing driven gate duplication
Design and Optimization of Nonvolatile Multibit 1T1R Resistive RAM
Low-Power Programmable PRPG With Test Compression Capabilities
A 6-18-GHz 6-bit Full-360° Vector-Sum Phase Shifter With Low Error in 40-nm CMOS
A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio
Area-Efficient Extended 3-D Inductor Based on TSV Technology for RF Applications
Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches
Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems
Masked Dual-Rail Precharge Logic Encounters State-of-the-Art Power Analysis Methods
A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model
Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays
Securing the PRESENT Block Cipher Against Combined Side-Channel Analysis and Fault Attacks
Design and analysis of compact dictionaries for diagnosis in scan-BIST
Design Optimization of Time- and Cost-Constrained Fault-Tolerant Embedded Systems With Checkpointing and Replication
Efficient exploration of bus-based system-on-chip architectures
Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate
Low-Power SDR Design on an FPGA for Intersatellite Communications
An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks
Automated In-Situ Monitoring for Variability-Resilient and Energy-Efficient Digital Circuits Demonstrated on a Viterbi Decoder in 22-nm CMOS
Complex-argument universal nonlinear cell for rapid prototyping
SWIFT: A Low-Power Network-On-Chip Implementing the Token Flow Control Router Architecture With Swing-Reduced Interconnects
AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers
Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers
A Systematic Evaluation of Profiling Through Focused Feature Selection
Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication
Mapping of generalized template matching onto reconfigurable computers
RAMON: Region-Aware Memory Controller
Soft Error Tolerant Convolutional Neural Networks on FPGAs With Ensemble Learning
Dynamic Workload Allocation for Edge Computing
Designing Novel AAD Pooling in Hardware for a Convolutional Neural Network Accelerator
Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip
Efficient Hierarchical Motion Estimation Algorithm and Its VLSI Architecture
Overlay techniques for scratchpad memories in low power embedded processors
Low-Complexity Switch Network for Reconfigurable LDPC Decoders
Memory allocation and mapping in high-level synthesis - an integrated approach
Global interconnect design in a three-dimensional system-on-a-chip
Process Variation Delay and Congestion Aware Routing Algorithm for Asynchronous NoC Design
Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method
Low-Cost Low-Power ASIC Solution for Both DAB+ and DAB Audio Decoding
Saturation-Volume Estimation for Multisegment Copper Interconnect Wires
Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware
Faulty behavior of storage elements and its effects on sequential circuits
Control Principles and On-Chip Circuits for Active Cooling Using Integrated Superlattice-Based Thin-Film Thermoelectric Devices
Implementation of a Multipath Fully Differential OTA in 0.18-μm CMOS Process
A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing
A novel wavelet transform-based transient current analysis for fault detection and localization
Low-Complexity Framework for Movement Classification Using Body-Worn Sensors
Obstacle-Avoiding Length-Matching Bus Routing Considering Nonuniform Track Resources
Fast coupled noise estimation for crosstalk avoidance in the MCG multichip module autorouter
Adaptive Frequency-Domain Channel Estimator in 4 , times , 4 MIMO-OFDM Modems
ILP-based cost-optimal DSP synthesis with module selection and data format conversion
Software-Based Self Test Methodology for On-Line Testing of L1 Caches in Multithreaded Multicore Architectures
VLSI architectural design tradeoffs for sliding-window log-MAP decoders
Soft Error Reliability Analysis of Vision Transformers
Efficient Delay and Crosstalk Modeling of RLC Interconnects Using Delay Algebraic Equations
High-performance FIR filter design based on sharing multiplication
Design and analysis of an ultrawide-band distributed CMOS mixer
Compiler-Assisted Leakage- and Temperature- Aware Instruction-Level VLIW Scheduling
High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology
A Study of Read Margin Enhancement for 3T2R Nonvolatile TCAM Using Adaptive Bias Training
Analog Implementation of a Novel Resistive-Type Sigmoidal Neuron
L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture
Energy-Aware Video Encoding for Image Quality Improvement in Battery-Operated Surveillance Camera
An EEG-Based Hypnotic State Monitor for Patients During General Anesthesia
Statistical Design Optimization of FinFET SRAM Using Back-Gate Voltage
On-chip oscilloscopes for noninvasive time-domain measurement of waveforms in digital integrated circuits