yusuke1997/dblp-id-title huggingface dataset:
Modeling the Effect of SEUs on the Configuration Memory of SRAM-FPGA-Based CNN Accelerators
Analytical Calculation of Radiation Characteristics of Metasurface-Based Solar Antennas "SOLANTs" With Uniform and Non-Uniform Cells
CGVC-T: Contextual Generative Video Compression With Transformers
Novel Low-Complexity Polynomial Multiplication Over Hybrid Fields for Efficient Implementation of Binary Ring-LWE Post-Quantum Cryptography
A Self-Contained System With CNTs-Based Biosensors for Cell Culture Monitoring
An Overview of Neural Rendering Accelerators: Challenges, Trends, and Future Directions
Design and Analysis of 3D Integrated Folded Ferro-Capacitive Crossbar Array (FC²A) for Brain-Inspired Computing System
Guest Editorial Design of Energy-Efficient Distributed Power Generation Systems
Recent Progress and Development of Hyperdimensional Computing (HDC) for Edge Intelligence
Guest Editorial Emerging Circuits and Systems Techniques for Ultra-Low Power Body Sensor Networks
Analog Spike-Timing-Dependent Resistive Crossbar Design for Brain Inspired Computing
Effects of Cyber Coupling on Cascading Failures in Power Systems
LightRot: A Light-Weighted Rotation Scheme and Architecture for Accurate Low-Bit Large Language Model Inference
Efficient Design of Micro-Scale Energy Harvesting Systems
A Decentralized Approach for Frequency Control and Economic Dispatch in Smart Grids
Modal Analysis-Based Analytical Method for Frequency Estimation During Inertia Response Stage of Power Systems
MiCE: An ANN-to-SNN Conversion Technique to Enable High Accuracy and Low Latency
A Wideband Digital Receiver With Hard-Switching Mixers for Cognitive Radio
Geometry-Based Object Association and Consistent Labeling in Multi-Camera Surveillance
Pre-Defined Sparse Neural Networks With Hardware Acceleration
EMG-Based Gestures Classification Using a Mixed-Signal Neuromorphic Processing System
Rate-Utility Optimized Streaming of Volumetric Media for Augmented Reality
Efficient Die-to-Die Communication: UCIe Link Simulation and Optimization in a Chiplet-Based System
Spectral Ranking in Complex Networks Using Memristor Crossbars
Representing Visual Objects in HEVC Coding Loop
Automatic On-Chip Clock Network Optimization for Electromagnetic Side-Channel Protection
A Statistic-Based Scan Chain Reordering for Energy-Quality Scalable Scan Test
Compressed Sensing Based Joint-Compensation of Power Amplifier's Distortions in OFDMA Cognitive Radio Systems
Design of Broadband Doherty Power Amplifier Based on Single Loop Load Modulation Network
Hardware-Robust In-RRAM-Computing for Object Detection
Coordinated Active Power Dispatch for a Microgrid via Distributed Lambda Iteration
BUP: A Deadlock Resolution Framework for 2.5D Chiplet Networks by Update Packet Bypassing
Energy-Aware Adaptive Rate and Resolution Sampling of Spectrally Sparse Signals Leveraging VCMA-MTJ Devices
A Custom MPSoC Architecture With Integrated Power Management for Real-Time Neural Signal Decoding
Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops
High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM
Power Reduction in Frequency-Selective FIR Filters Under Voltage Overscaling
GEBA: Gradient-Error-Based Approximation of Activation Functions
A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference
AM 4 : MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing
Building Time-Surfaces by Exploiting the Complex Volatility of an ECRAM Memristor
Image Retargeting Via Adaptive Scaling With Geometry Preservation
Data-Driven Priors for Robust PSSE via Gauss-Newton Unrolled Neural Networks
Design and Performance Analysis of Supercapacitor Charging Circuits for Wireless Sensor Nodes
Ultra-Low-Power Radio Microphone for Cochlear Implant Application
Guest Editorial Complex Cyber-Multitudinal-Physical Systems: Analysis, Decision-Making, and AI Applications
A Silicon-Organic Hybrid Voltage Equalizer for Supercapacitor Balancing
VLSI Friendly ECG QRS Complex Detector for Body Sensor Networks
Hardware-Efficient Residual Neural Network Execution in Line-Buffer Depth-First Processing
A Novel Power and Signal Composite Modulation Strategy for CCC-Based SRG in Distributed Microgrid
Machine Learning Based Multi-Agent System for Detecting and Neutralizing Unseen Cyber-Attacks in AGC and HVDC Systems
Tightly Coupled Machine Learning Coprocessor Architecture With Analog In-Memory Computing for Instruction-Level Acceleration
Rich-Club Impact on Cascading Failures in Interdependent Power and Communication Networks
FPGA Codec System of Learned Image Compression With Algorithm-Architecture Co-Optimization
Combined HW/SW Drift and Variability Mitigation for PCM-Based Analog In-Memory Computing for Neural Network Applications
Millimeter-Wave Transmission Line in 90-nm CMOS Technology
Blind Opportunistic Interference Alignment in MIMO Cognitive Radio Systems
EEG-Based Multi-Frequency Multilayer Network for Exploring the Brain State Evolution Underlying Motor Imagery
Low-Power Computer Vision: Status, Challenges, and Opportunities
Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics
Circuit-Level Benchmarking of Access Devices for Resistive Nonvolatile Memory Arrays
Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing
Digital-Assisted Asynchronous Compressive Sensing Front-End
Compact Visual Data Representation for Green Multimedia-A Human Visual System Perspective
Energy Neutral Wireless Sensing for Server Farms Monitoring
Guest Editorial Emerging Topics in Multiple-Valued Logic and Its Applications
Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation
An Encryption Architecture Suitable for on Chip Integration With Sensors
Stuck-at Fault Tolerance in RRAM Computing Systems
A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits
SWANN: Small-World Architecture for Fast Convergence of Neural Networks
A Non-Idealities Aware Software-Hardware Co-Design Framework for Edge-AI Deep Neural Network Implemented on Memristive Crossbar
Exploring the Tradeoffs of Application-Specific Processing
Small-Signal Stability Analysis Method for Hybrid AC-DC Systems With Multiple DC Buses
Broadband Millimeter-Wave GaAs Dual-Function Switching Attenuators With Low Insertion Loss and Large Attenuation Range
Fully-Automated and Portable Design Methodology for Optimal Sizing of Energy-Efficient CMOS Voltage Rectifiers
Multimodal Video Analysis on Self-Powered Resource-Limited Wireless Smart Camera
CDSTTN: A Data Imputation Method for Cyber-Physical Systems by Causal Dense Spatial-Temporal Transformer Network
Undersea Wireless Power and Data Transfer System With Shared Channel Powered by Marine Renewable Energy System
Input-Aware Flow-Based Computing on Memristor Crossbars With Applications to Edge Detection
A Sub-Nyquist Rate Compressive Sensing Data Acquisition Front-End
Circuit Design and Application of Discrete Cosine Transform Based on Memristor
A Circuits and Systems Perspective of Organic/Printed Electronics: Review, Challenges, and Contemporary and Emerging Design Approaches
Energy Efficient Cognitive Radio System for Joint Spectrum Sensing and Data Transmission
Experimental Evaluation of an Adaptive Nonlinear Interference Suppressor for Multimode Transceivers
Energy and Reliability Improvement of Voltage-Based, Clustered, Coarse-Grain Reconfigurable Architectures by Employing Quality-Aware Mapping
Stabilization and Non-Weighted L 2 Gain Analysis of Switched Systems With Distributed Delay Under Asynchronous Event-Triggered Control
Improving the Stability of Standalone MMCs by Shaping the AC Side Impedance Using Insertion Index Compensation
A 1 TB/s 1 pJ/b 6.4 mm 2 /(TB/s) QDR Inductive-Coupling Interface Between 65-nm CMOS Logic and Emulated 100-nm DRAM
Xbar-Partitioning: A Practical Way for Parasitics and Noise Tolerance in Analog IMC Circuits
Progressive Compressed Sensing and Reconstruction of Multidimensional Signals Using Hybrid Transform/Prediction Sparsity Model
An Assigned Color Depth Packing Method With Centralized Texture Depth Packing Formats for 3D VR Broadcasting Services
GenPolar: Generative AI-Aided Complexity Reduction for Polar SCL Decoding
Multi-View ML Object Tracking With Online Learning on Riemannian Manifolds by Combining Geometric Constraints
Extracting DNN Architectures via Runtime Profiling on Mobile GPUs
Leveraging Stochastic Memristor Devices in Neuromorphic Hardware Systems
Highly Accurate Dual-Band Cellular Field Potential Acquisition For Brain-Machine Interface
SwInt: A Non-Blocking Switch-Based Silicon Photonic Interposer Network for 2.5D Machine Learning Accelerators
HyDe: A brid PCM/FeFET/SRAM vice-Search for Optimizing Area and Energy-Efficiencies in Analog IMC Platforms
Design of a DC-DC Converter With Phase-Controlled Class-D ZVS Inverter
Fast and Accurate Jitter Amplification Modeling With Variable Pulse Width Response for Statistical BER Analysis in Chiplet Interconnects and Beyond
Power Distribution in TSV-Based 3-D Processor-Memory Stacks
A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip
Enhancing DFT Security in Chiplet-Based Systems With Encryption and Integrity Checking
SoC FPAA Hardware Implementation of a VMM+WTA Embedded Learning Classifier
Analog Circuit Implementation of Fractional Order Damped Sine and Cosine Functions
Circuits and Systems for Green Video Communications: Fundamentals and Recent Trends
An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology
An SRAM-Based Hybrid Computation-in-Memory Macro Using Current-Reused Differential CCO
Interval-Passing Algorithm for Non-Negative Measurement Matrices: Performance and Reconstruction Analysis
Low Latency IDMA With Interleaved Domain Architecture for 5G Communications
Gradient-Based Neuromorphic Learning on Dynamical RRAM Arrays
Energy-Efficient Iterative Refinement Using Dynamic Precision
Leakage Reuse for Energy Efficient Near-Memory Computing of Heterogeneous DNN Accelerators
Design of Processing-in-Memory With Triple Computational Path and Sparsity Handling for Energy-Efficient DNN Training
How to Feed a Growing Population - An IoT Approach to Crop Health and Growth
Introduction to the Special Issue on the 1st IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2019)
The Implementation of a Low-Power Biomedical Signal Processor for Real-Time Epileptic Seizure Detection on Absence Animal Models
STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks
Delta Sigma Modulator-Based Dividers for Accurate and Low Latency Stochastic Computing Systems
Correction to "Closed-Form Rational Approximations of Fractional, Analog and Digital Differentiators/Integrators"
Guest Editorial Energy-Quality Scalable Circuits and Systems for Sensing and Computing: From Approximate to Communication-Inspired and Learning-Based
Compressive Spectrum Sensing Using a Bandpass Sampling Architecture
Designing a Process Variability Robust Energy-Efficient Control for Complex SoCs
Intra Block Copy in HEVC Screen Content Coding Extensions
Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms
Error Analysis of Programmable Metasurfaces for Beam Steering
A Heterogeneous In-Memory Computing Cluster for Flexible End-to-End Inference of Real-World Deep Neural Networks
LSHIM: Low-Power and Small-Area Inexact Multiplier for High-Speed Error-Resilient Applications
Nonnegative Matrix Factorization With Regularizations
Fractional Order Generalization of Anomalous Diffusion as a Multidimensional Extension of the Transmission Line Equation
Resistive Second-Harmonic Impedance Continuous Class-F Power Amplifier With Over One Octave Bandwidth for Cognitive Radios
Near-Sensor Distributed DNN Processing for Augmented and Virtual Reality
VLSI Design of a Monolithic Compressive-Sensing Wideband Analog-to-Information Converter
SimuNN: A Pre-RTL Inference, Simulation and Evaluation Framework for Neural Networks
Bi-Directional Trajectory Tracking With Variable Block-Size Motion Estimation for Frame Rate Up-Convertor
Secure Consensus Control for Constrained Multi-Agent Systems Against Intermittent Denial-of-Service Attacks: An Adaptive Dynamic Programming Method
LoRaWAN ESL for Food Retail and Logistics
ASP: Learning to Forget With Adaptive Synaptic Plasticity in Spiking Neural Networks
Fast and Compact Serial IMPLY-Based Approximate Full Adders Applied in Image Processing
Genetic Algorithm-Based Energy-Aware CNN Quantization for Processing-In-Memory Architecture
Microgrid Energy Management Combining Sensitivities, Interval and Probabilistic Uncertainties of Renewable Generation and Loads
A High-Voltage-Tolerant and Power-Efficient Stimulator With Adaptive Power Supply Realized in Low-Voltage CMOS Process for Implantable Biomedical Applications
Analysis of Dynamical Robustness to Noise in Power Grids
Low Power Magnetic Quantum Cellular Automata Realization Using Magnetic Multi-Layer Structures
Thermal Perspective Design and Analysis of Multi-Stacked Structures
Feature Selection for Automatic Burst Detection in Neonatal Electroencephalogram
Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices
Deep Learning-Based Composite Fault Diagnosis
Feature Extraction and Representation for Distributed Multi-View Human Action Recognition
Emitter-Coupled Spin-Transistor Logic: Cascaded Spintronic Computing Beyond 10 GHz
High-Speed Plastic Integrated Circuits: Process Integration, Design, and Test
Diffense: Defense Against Backdoor Attacks on Deep Neural Networks With Latent Diffusion
A 299-315-GHz Dual-Band Radiator Array With Cascaded Transmission Line-Based Feedback Network for Phase Noise Improvement
An In-memory-Computing DNN Achieving 700 TOPS/W and 6 TOPS/mm 2 in 130-nm CMOS
An Energy Efficient VLSI Architecture of Decision Feedback Equalizer for 5G Communication System
Guest Editorial Special Issue on Brain-Machine Interface
Phase Change Memory Write Cost Minimization by Data Encoding
A Theoretical Approach to Memristor Devices
Doppler Radar Techniques for Accurate Respiration Characterization and Subject Identification
A Selective Bit Dropping and Encoding Co-Strategy in Image Processing for Low-Power Design in DRAM and SRAM
Muller C-Element Exploiting Programmable Metallization Cell for Bayesian Inference
Overview of Recent Development on Wireless Sensing Circuits and Systems for Healthcare and Biomedical Applications
Guest Editorial Solid-state Memristive Devices and Systems
A Background Calibration Technique Based on Limit Cycles for Reconfigurable Sigma Delta Modulators
Exploring and Analyzing the Token Ecosystem: A Complex Network Analysis Perspective
Distributed On-Chip Power Delivery
Structured Learning for Action Recognition in Videos
An Unobtrusive System for Heart Rate Monitoring Based on Ballistocardiogram Using Hilbert Transform and Viterbi Decoding
An Optically Powered CMOS Receiver System for Intravascular Magnetic Resonance Applications
Exploring Spin Transfer Torque Devices for Unconventional Computing
Nonlinear Modeling of Multi-Converter Systems Within DC-Link Timescale
A Spatial Multi-Bit Sub-1-V Time-Domain Matrix Multiplier Interface for Approximate Computing in 65-nm CMOS
Generative AI Through CAS Lens: An Integrated Overview of Algorithmic Optimizations, Architectural Advances, and Automated Designs
Embedding Multi-Order Spatial Clues for Scalable Visual Matching and Retrieval
RobustDA: Lightweight Robust Domain Adaptation for Evolving Data at Edge
Embedding the Dynamics of Forced Nonlinear Systems in Multistable Memristor Circuits
Time-Interleaved Noise-Coupling Delta-Sigma Modulator Using Modified Noise-Shaped Integrating Quantizer
Maximum Virtual Inertia From DC-Link Capacitors Considering System Stability at Voltage Control Timescale
RLFL: A Reinforcement Learning Aggregation Approach for Hybrid Federated Learning Systems Using Full and Ternary Precision
Ultra-High Input Impedance, Low Noise Integrated Amplifier for Noncontact Biopotential Sensing
Nonlinear Analysis of Discretization Effects in a Digital Current Mode Controlled Boost Converter
DND: Deep Learning-Based Directed Network Disintegrator
A Miniature Configurable Wireless System for Recording Gastric Electrophysiological Activity and Delivering High-Energy Electrical Stimulation
Quantum PUF for Security and Trust in Quantum Computing
Delay Impact on MPEG OMAF's Tile-Based Viewport-Dependent 360° Video Streaming
Enabling Non-Hebbian Learning in Recurrent Spiking Neural Processors With Hardware-Friendly On-Chip Intrinsic Plasticity
A Historical Perspective on Hardware AI Inference, Charge-Based Computational Circuits and an 8 bit Charge-Based Multiply-Add Core in 16 nm FinFET CMOS
Custom Sub-Systems and Circuits for Deep Learning: Guest Editorial Overview
Design of Low Voltage Tunneling-FET Logic Circuits Considering Asymmetric Conduction Characteristics
Compressed-Domain Vision Transformer for Image Classification
Low-Power Multiversion Interpolation Filter Accelerator With Hardware Reuse for AV1 Codec
Neural State Machines for Robust Learning and Control of Neuromorphic Agents
Low-Invasive Implantable Devices of Low-Power Consumption Using High-Efficiency Antennas for Cloud Health Care
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity
Hardware Security in Emerging Technologies: Vulnerabilities, Attacks, and Solutions
TAD-MAC: Traffic-Aware Dynamic MAC Protocol for Wireless Body Area Sensor Networks
Analysis of Defects and Variations in Embedded Spin Transfer Torque (STT) MRAM Arrays
An Analogue In-Memory Ridge Regression Circuit With Application to Massive MIMO Acceleration
Screen Content Image Segmentation Using Robust Regression and Sparse Decomposition
Memristors Empower Spiking Neurons With Stochasticity
Benchmarking Open-Source Static 3D Mesh Codecs for Immersive Media Interactive Live Streaming
Modeling Methodology Based on Fast and Refined Neural Networks for Non-Isolated DC-DC Converters With Configurable Parameter Settings
Recursive Algorithms in Memristive Logic Arrays
Hematoxylin and Eosin (H&E) Stained Liver Portal Area Segmentation Using Multi-Scale Receptive Field Convolutional Neural Network
Efficient Approximate Posit Multipliers for Deep Learning Computation
HALO: Communication-Aware Heterogeneous 2.5-D System for Energy-Efficient LLM Execution at Edge
RDDM: A Rate-Distortion Guided Diffusion Model for Learned Image Compression Enhancement
Stochastic Synchronization of Semi-Markovian Switching Cyber-Physical Impulsive Complex Networks via Dynamic Event-Triggered SMC
Flexible Hybrid Electronic Circuits and Systems
F 3 : An FPGA-Based Transformer Fine-Tuning Accelerator With Flexible Floating Point Format
Guest Editorial Immersive Video Coding and Transmission
Compact CMOS-Compatible Majority Gate Using Body Biasing in FDSOI Technology
PKU-AIGI-500K: A Neural Compression Benchmark and Model for AI-Generated Images
Low Power Sparse Approximation on Reconfigurable Analog Hardware
A Lego-Based Neural Network Design Methodology With Flexible NoC
A 340-GHz THz Amplifier-Frequency-Multiplier Chain With 360° Phase-Shifting Range and its Phase Characterization
Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology
PowerSleep: A Smart Power-Saving Scheme With Sleep for Servers Under Response Time Constraint
Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks
Exploring MRAM Technologies for Energy Efficient Systems-On-Chip
Energy-Efficient and Rotationally Adjustable Millimeter-Wave Wireless Interconnects
C-DNN V2: Complementary Deep-Neural-Network Processor With Full-Adder/OR-Based Reduction Tree and Reconfigurable Spatial Weight Reuse
Core-Level Activity Prediction for Multicore Power Management
Memristive Circuits for LDPC Decoding
Swizzle-Switch Networks for Many-Core Systems
Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers
Guest Editorial Circuits and Systems for Industry X.0 Applications
An Energy-Efficient Deep Belief Network Processor Based on Heterogeneous Multi-Core Architecture With Transposable Memory and On-Chip Learning
AutoRank: Automated Rank Selection for Effective Neural Network Customization
VWC-SDK: Convolutional Weight Mapping Using Shifted and Duplicated Kernel With Variable Windows and Channels
Artificial Intelligence for 5G and Beyond 5G: Implementations, Algorithms, and Optimizations
Transformerless Three-Level Flying-Capacitor Step-Up PV Micro-Inverter Without Electrolytic Capacitors
Complementary Detection for Hardware Efficient On-Site Monitoring of Parkinsonian Progress
Testing Scalable Bell Inequalities for Quantum Graph States on IBM Quantum Devices
A TinyML Platform for On-Device Continual Learning With Quantized Latent Replays
Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology
Mosaic-CNN: A Combined Two-Step Zero Prediction Approach to Trade off Accuracy and Computation Energy in Convolutional Neural Networks
Aligner-D: Leveraging In-DRAM Computing to Accelerate DNA Short Read Alignment
IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS): A New Chapter Begins
WHYPE: A Scale-Out Architecture With Wireless Over-the-Air Majority for Scalable In-Memory Hyperdimensional Computing
Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias
A 60 GHz Low Power Self-mixing Receiver in 65-nm CMOS for a Radio-Triggered Battery-Less Monolithic Wireless Sensor
On-Chip Error-Triggered Learning of Multi-Layer Memristive Spiking Neural Networks
Factored Forms for Memristive Material Implication Stateful Logic
Programmable Neuron Array Based on a 2-Transistor Multiplier Using Organic Floating-Gate for Intelligent Sensors
Bias-Scalable Near-Memory CMOS Analog Processor for Machine Learning
A Low-Power 0.7 $\mu {\rm V_{rms}}$ 32-Channel Mixed-Signal Circuit for ECoG Recordings
An Accelerator-Based Wireless Sensor Network Processor in 130 nm CMOS
Analogue Frontend Amplifiers for Bio-Potential Measurements Manufactured With a-IGZO TFTs on Flexible Substrate
Exploring Compute-in-Memory Architecture Granularity for Structured Pruning of Neural Networks
Distributed Power Control for Transient Stability of Multimachine Power Systems
A Neuro-Inspired Spike Pattern Classifier
Power Side-Channel Attacks on BNN Accelerators in Remote FPGAs
Predictive Modeling of MEMS via Generic Meminductors: The Multiport Inductor Approach
COIN: Communication-Aware In-Memory Acceleration for Graph Convolutional Networks
Design of a WSN Platform for Long-Term Environmental Monitoring for IoT Applications
Programming Weights to Analog In-Memory Computing Cores by Direct Minimization of the Matrix-Vector Multiplication Error
Guest Editorial: 2.5-D/3-D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test - Part II
Multilevel-Cell Phase-Change Memory: A Viable Technology
Incremental Analog-to-Digital Converters for High-Resolution Energy-Efficient Sensor Interfaces
A High-Frequency Compensated Crosstalk and ISI Equalizer for Multi-Channel On-Chip Interconnect in 130-nm CMOS
Which Generation Unit Should be Selected as Control Leader in Secondary Frequency Control of Microgrids?
An Open Platform for Fully-Additive Printed Electronics
Improvements of HEVC SCC Palette Mode and Intra Block Copy
Mixed Integer Second Order Cone Relaxation With Dynamic Simulation for Proper Power System Islanding Operations
Guest Editorial Computational and Smart Cameras
High-Speed Compressed Sensing Reconstruction in Dynamic Parallel MRI Using Augmented Lagrangian and Parallel Processing
Guest Editorial Circuits and Systems for Smart Agriculture and Healthy Foods
Space-Time Spectral White Spaces in Cognitive Radio: Theory, Algorithms, and Circuits
A Low-Cost Hardware Design of Learning-Based One-Dimensional Interpolation for Real-Time Video Applications at the Edge
LLM4Netlist: LLM-Enabled Step-Based Netlist Generation From Natural Language Description
Aspects of Reversible and Quantum Computing in a p-Valued Domain