yusuke1997/dblp-id-title huggingface dataset:
A Four-Step Incremental ADC Based on Double Extended Binary Counting With Capacitive DAC
A Li-Ion Battery Charger With Smooth Control Circuit and Built-In Resistance Compensator for Achieving Stable and Fast Charging
Blind Second-Order Source Extraction of Instantaneous Noisy Mixtures
Fixed-Time Consensus of Nonlinear Multi-Agent Systems With General Directed Topologies
New Sliding-Mode Learning Law for Dynamic Neural Network Observer
Efficient Fixed-Width Adder-Tree Design
Pseudo-Chaotic Lossy Compressors for True Random Number Generation
Correction to "A Note on Minimality of Positive Realizations"
A Scaling Parameter Approach to Delay-Dependent State Estimation of Delayed Neural Networks
A Current-Mode Circuit With a Linearized Input V/I Conversion Scheme and the Realization of a 2-V/2.5-V Operational, 100-MS/s, MOS SHA
Optimum Circuits for Bit Reversal
An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range
Short-Range Quality-Factor Modulation (SQuirM) for Low Power High Speed Inductive Data Transfer
A Novel Dynamic Detection for Flash Memory
Serial Addition: Locally Connected Architectures
A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip
Jittery Signal Generation for High-Speed Interconnect Simulation
Robust Adaptive Control of a Class of Nonlinear Systems and Its Applications
A Unified Methodology for Designing Hardware Random Number Generators Based on Any Probability Distribution
A 16 mW 250 ps Double-Hit-Resolution Input-Sampled Time-to-Digital Converter in 45-nm CMOS
Micro-power low-offset instrumentation amplifier IC design for biomedical system applications
Kernel Kalman Filtering With Conditional Embedding and Maximum Correntropy Criterion
An Efficient Optimization Based Method to Evaluate the DRV of SRAM Cells
Angle of Arrival Estimation Through a Full-Hardware Approach for Adaptive Beamforming
Direct Synthesis of General Chebyshev Bandpass Filters in the Bandpass Domain
Highly Efficient Environment for FMCW Radar Phase Noise Simulations in IF Domain
A G-Band Wideband Bidirectional Transceiver Front-End in 40-nm CMOS
An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count
Dual-Sampling Skewed CMOS Design for Soft-Error Tolerance
Hardware Reduction in Digital Delta-Sigma Modulators Via Error Masking - Part II: SQ-DDSM
Finite-Time Synchronization of a Class of Second-Order Nonlinear Multi-Agent Systems Using Output Feedback Control
Differential Transmission Lines Loaded With Magnetic LC Resonators and Application in Common Mode Suppression
A Low-Latency and Area-Efficient Gram-Schmidt-Based QRD Architecture for MIMO Receiver
Design and simulation of a nanoelectronic single-electron universal Fredkin gate
A 21-GS/s Single-Bit Second-Order Delta-Sigma Modulator for FPGAs
A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications
An 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS
A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High Performance Joint Source Channel Codes
Sliding Conjugate Symmetric Sequency-Ordered Complex Hadamard Transform: Fast Algorithm and Applications
Improved Architectures for a Fused Floating-Point Add-Subtract Unit
Quad-Mode LTCC Surface Mounted Packaging Common-Mode Filter Based on the Asymmetric Short-Stub Loaded Resonator
An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS
A 1.9-GHz Fractional-N Digital PLL With Subexponent ΔΣ TDC and IIR-Based Noise Cancellation
Low-Complexity Pipelined Architecture for FBMC/OQAM Transmitter
ETHFB: A New Class of Even-Length Biorthogonal Wavelet Filters for Hilbert Pair Design
SensorNet: A Scalable and Low-Power Deep Convolutional Neural Network for Multimodal Data Classification
A High-Voltage DAC-Based Transmitter for Coded Signals in High Frequency Ultrasound Imaging Applications
Initiation of Characteristic Ferroresonance States Based on Flux Reflection Model
Distributed Consensus of Heterogeneous Linear Time-Varying Systems on UAVs-USVs Coordination
Introduction to the Special Issue on Biomedical and Bioelectronic Circuits for Enhanced Diagnosis and Therapy
Bifurcation and Border Collision Analysis of Voltage-Mode-Controlled Flyback Converter Based on Total Ampere-Turns
Finite-Time Consensus of Finite Field Networks With Stochastic Time Delays
A 12 Gb/s 1.59 mW/Gb/s Input-Data-Jitter-Tolerant Injection-Type CDR With Super-Harmonic Injection-Locking in 65-nm CMOS
Digital Self-Interference Cancellation for Full-Duplex Underwater Acoustic Systems
Improved Area-Efficient Weighted Modulo 2 n + 1 Adder Design With Simple Correction Schemes
Detection and Removal of Limit Cycles in Sigma Delta Modulators
FPGA-Based Low-Visibility Enhancement Accelerator for Video Sequence by Adaptive Histogram Equalization With Dynamic Clip-Threshold
Equation-Error Adaptive IIR Filtering Based on Data Reuse
Serial-Link Bus: A Low-Power On-Chip Bus Architecture
Single Amplifier Bi-Quadratic Filter Topologies in Transimpedance Configuration
Restricted Partial Stability and Synchronization
Closed-Form Design of Half-Sample Delay IIR Filter Using Continued Fraction Expansion
A 10-Gb/s CDR With an Adaptive Optimum Loop-Bandwidth Calibrator for Serial Communication Links
A Low Power Diode-Clamped Inverter-Based Strong Physical Unclonable Function for Robust and Lightweight Authentication
Design of a 60 GHz 32% PAE Class-AB PA with 2 nd Harmonic Control in 45-nm PD-SOI CMOS
An Adaptive Blind Calibration Technique for Frequency Response Mismatches in M-Channel Time-Interleaved ADCs
Cryptanalysis of Chaotic Masking Secure Communication Systems Using an Adaptive Observer
A 3-GHz Serial ATA Spread-Spectrum Clock Generator Employing a Chaotic PAM Modulation
A 3-8 GHz Delay-Locked Loop With Cycle Jitter Calibration
Energy Efficiency of Pulsed Actuations on Linear Resonators
Can threshold networks be trained directly?
Bandpass Sigma-Delta Modulator Employing SAW Resonator as Loop Filter
Effects of nonlinear feedback in the frequency domain
A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm
Correlation Between the Theory of Lissajous Figures and the Generation of Pinched Hysteresis Loops in Nonlinear Circuits
Cellular Neural Networks With Transient Chaos
A Fully Integrated and Reconfigurable Architecture for Coherent Self-Testing of High Speed Analog-to-Digital Converters
A 32/16-Gb/s Dual-Mode Pulsewidth Modulation Pre-Emphasis (PWM-PE) Transmitter With 30-dB Loss Compensation Using a High-Speed CML Design Methodology
Low-Power Parallel Chien Search Architecture Using a Two-Step Approach
Secure and Lightweight Compressive Sensing Using Stream Cipher
MultiObjective Evolutionary Approach to Grey-Box Identification of Buck Converter
CMix-NN: Mixed Low-Precision CNN Library for Memory-Constrained Edge Devices
Theory of Switched RF Resonators
A Fully Integrated Analog Front End for Biopotential Signal Sensing
A Class-D FVF LDO With Multi-Level PWM Gate Control, 280-ns Settling Time, and No Overshoot/Undershoot
Fully-Digital Blind Compensation of Non-Linear Distortions in Wideband Receivers
Carry-free approximate squaring functions with O(n) complexity and O(1) delay
A Fifth-Order Butterworth OTA-C LPF With Multiple-Output Differential-Input OTA for ECG Applications
A V-Band Power Amplifier With Integrated Wilkinson Power Dividers-Combiners and Transformers in 0.18- $\mu$ m SiGe BiCMOS
The Feedback Vertex Set Problem of Multiplex Networks
An RF Choke-Less Class E Power Amplifier
A Novel Framework to Estimate the Path Delay Variability On the Back of an Envelope via the Fan-Out-of-4 Metric
A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique
Log-domain wave filters
A Nonlinear Behavioral Ferrite-Core Inductance Model Able to Reproduce Thermal Transients in Switch-Mode Power Supplies
Charging Time Characterization for Wireless RF Energy Transfer
Behavior Analysis of Directed Signed Networks Under Dynamic Protocols
Higher Order Sliding Mode Control-Based Finite-Time Constrained Stabilization
An Area Efficient Early Z -Test Method for 3-D Graphics Rendering Hardware
A 250-µW 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications
A Method of Transformation from Symbolic Transfer Function to Active-RC Circuit by Admittance Matrix Expansion
System Identification Under Relay and PI Control
Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-Locked Loop
A dc-dc Converter for a Fully Integrated PID Compensator With a Single Capacitor
Reduced-Order Observer Based-Fault Estimation for Markovian Jump Systems With Time-Varying Generally Uncertain Transition Rates
ΔΣ Noise-Shaping in 2-D Space-Time for Wideband Antenna Array Receivers
Design and Demonstration of a Fully Integrated Multi-Technology FPGA: A Reconfigurable Architecture for Photonic and Other Multi-Technology Applications
On Linear Analysis of the Power Flow Equations for DC and AC Grids With CPLs
A 10-Gb/s 0.71-pJ/bit Forwarded-Clock Receiver Tolerant to High-Frequency Jitter in 65-nm CMOS
Low-Voltage Bootstrapped CMOS Drivers With Efficient Conditional Bootstrapping
Implementation of a High-Throughput Modified Merge Sort in MIMO Detection Systems
Radix-2 Fast Algorithm for Computing Discrete Hartley Transform of Type III
Crosstalk in Balanced Interconnections Used for Differential Signal Transmission
Low-Routing-Complexity Convolutional/Turbo Decoder Design for Iterative Detection and Decoding Receivers
An efficient VLSI design for a residue to binary converter for general balance moduli (2 n -3, 2 n +1, 2 n -1, 2 n +3)
Parallel Implementation of Particle Swarm Optimization on FPGA
Delay-Reduction Technique for DWA Algorithms
Low-Distortion Sine Wave Generation Using a Novel Harmonic Cancellation Technique
A 2 mW, 50 dB DR, 10 MHz BW 5 × Interleaved Bandpass Delta-Sigma Modulator at 50 MHz IF
Algebraic and Combinatorial Algorithms for Translinear Network Synthesis
Comments on "Novel Dual-Band Matching Network for Effective Design of Concurrent Dual-Band Power Amplifiers"
Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders
Robust Gain Scheduling Synchronization Method for Quadratic Chaotic Systems With Channel Time Delay
Current Ripple Characterization in DCM Interleaved Power Converters Under Inductance Mismatch
Spur Minimization Techniques for Ultra-Low-Power Injection-Locked Transmitters
A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop
Current Tracking Technique Enabling 1-Bit/Cell Storage in Ge-Rich Phase Change Memory
Energy Efficient Peripheral and System Buses for Low-Area and Low-Power SoC Applications
An Adaptive Filtering Algorithm for Direct-Conversion Receivers: Architecture and Performance Analysis
Average-Consensus Filter of First-Order Multi-Agent Systems With Disturbances
Design of Robust Broadband Beamformers With Discrete Coefficients and Least Squared Criterion
Two New Types of Zhang Neural Networks Solving Systems of Time-Varying Nonlinear Inequalities
A 16×16 Pixel Post-Processing Free Quantum Random Number Generator Based on SPADs
Two-Mode Reed-Solomon Decoder Using A Simplified Step-by-Step Algorithm
A Calibration Technique for Simultaneous Estimation of Actual Sensing Matrix Coefficients on Modulated Wideband Converters
Efficient Design and Implementation of Variable Fractional Delay Filters Using Differentiators
Guest Editorial Special Issue on the 2019 IEEE International Symposium on Circuits and Systems
Power-Efficient Clock/Data Distribution Technique for Polyphase Comb Filter in Digital Receivers
2.2 GHz all-n-p-n second-generation controlled conveyor in pseudoclass AB using 0.8-μm BiCMOS technology
On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits
Stable Organic LED Displays Using RMS Estimation of Threshold Voltage Dispersion
On the Output Impedance and an Output Current-Power Efficiency Relationship of Dickson Charge Pump Circuits
Robust super-exponential methods for blind equalization in the presence of Gaussian noise
A Switched-Capacitor DC-DC Converter Powering an LC Oscillator to Achieve 85% System Peak Power Efficiency and -65dBc Spurious Tones
Analog DFT Processors for OFDM Receivers: Circuit Mismatch and System Performance Analysis
A Timer-Based Distributed Channel Access Mechanism in Networked Control Systems
Energy-Efficient Semi-Flocking Control of Mobile Sensor Networks on Rough Terrains
Methodologies for Evaluating and Measuring Capacitance Mismatch in CMOS Integrated Circuits
Predistortion of Digital RF PWM Signals Considering Conditional Memory
Using Mixed-Signal Defect Simulation to Close the Loop Between Design and Test
Dynamic Bias-Current Boosting Technique for Ultralow-Power Low-Dropout Regulator in Biomedical Applications
A Novel Physical Layer Authentication With PAPR Reduction Based on Channel and Hardware Frequency Responses
Simultaneous Blind Separation of Instantaneous Mixtures With Arbitrary Rank
Asymptotic Stability of Two-Dimensional Discrete Systems With Saturation Nonlinearities
Noise Analysis and Simulation Method for a Single-Slope ADC With CDS in a CMOS Image Sensor
Adaptive blind calibration of timing offset and gain mismatch for two-channel time-interleaved ADCs
A Storage-Based Carry Randomization Technique for Spurs Reduction in Flying-Adder Frequency Synthesizer
On the Design of Nearly-PR and PR FIR Cosine Modulated Filter Banks Having Approximate Cosine-Rolloff Transition Band
The Mathematical Foundation of Distributed Interleaved Systems
A 10.4-Gb/s 1-Tap Decision Feedback Equalizer With Different Pull-Up and Pull-Down Tap Weights for Asymmetric Memory Interfaces
New configurations for the measurement of small resistance changes
High-Order Monocycle Design and Its Waveform-Generating Circuit for UWB Communications
Class-J 2 Power Amplifiers
A 4-GHz Active Scatterer in 130-nm CMOS for Phase Sweep Amplify-and-Forward
A Fully Parallel LDPC Decoder Architecture Using Probabilistic Min-Sum Algorithm for High-Throughput Applications
Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions
CMOS Image Sensors With Self-Powered Generation Capability
Stability in Small Signal Common Base Amplifiers
A hybrid evolutionary programming method for circuit optimization
A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators
A Robust [K, KL] Sector for Nonlinear System
A 16-Ώ Audio Amplifier With 93.8-mW Peak Load Power and 1.43-mW Quiescent Power Consumption
Area Efficient VLSI Architectures for Weak Signal Detection in Additive Generalized Cauchy Noise
Colored Noise in Oscillators. Phase-Amplitude Analysis and a Method to Avoid the itô-Stratonovich Dilemma
A Quad-Band CMOS Linear Power Amplifier for EDGE Applications Using an Anti-Phase Method to Enhance its Linearity
Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division
Unloaded Quality Factor of Transmission Line Resonators With Capacitors
Robust CMOS Micromachined Inductors With Structure Supports for Gilbert Mixer Matching Circuits
Power-Rate Global Stability of Dynamical Systems With Unbounded Time-Varying Delays
IC Design and Measurement of an Inductorless 48 V DC/DC Converter in Low-Cost CMOS Technology Facing Harsh Environments
Phase-domain all-digital phase-locked loop
Reply to "Comments on Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers"
Irrational-Based Time-Hopping Modulation for UWB Communications
Fault Identifiability Analysis of Linear Discrete Time-Varying Systems
The Quarternion Maximum Correntropy Algorithm
Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop
Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping
Adaptive and Robust Digital Harmonic-Reject Mixer With Optimized Local Oscillator Spacing
Circuit Function Characterizing Tunability of Resonators
Laser Fine-Tuneable Deep-Submicrometer CMOS 14-bit DAC
Wideband Bandpass Filtering Balun With Perfect In-Band Matching and Isolation
A CMOS Switched Load Harmonic Rejection Mixer for DTV Tuner Applications
Control for EESS in Three-Phase Microgrids Under Time-Domain Reference Frame via PBC Theory
Phase-domain fractional-N frequency synthesizers
Spectral spurs due to quantization in Nyquist ADCs
Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs
Design and Implementation of a Digital Secure Code-Shifted Reference UWB Transmitter and Receiver
RF Built-in Self Test of a Wireless Transmitter
An Analytical Method for the Multiplierless 2-D FIR Filter Functions and Hilbert Transform in z2 Domain
Design of reduced-order H ∞ filter for Markovian jumping systems with time delay
A 3-25 Gb/s Four-Channel Receiver With Noise-Canceling TIA and Power-Scalable LA
Recasting modified nodal analysis to improve reliability in numerical circuit Simulation
A Switched Capacitor Energy Harvester Based on a Single-Cycle Criterion for MPPT to Eliminate Storage Capacitor
Voltage loop of boost PWM DC-DC converters with peak current-mode control
An Attack Against the Revised Murthy-Swamy Cryptosystem
An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture
A 1-V, 5.5-GHz, CMOS LNA With Multiple Magnetic Feedback
An Efficient Massive MIMO Detector Based on Second-Order Richardson Iteration: From Algorithm to Flexible Architecture
Robust stability of 2-D discrete systems described by the Fornasini-Marchesini second model employing quantization/overflow nonlinearities
A Multiple-Input Boost Converter for Low-Power Energy Harvesting
Study of Periodic Solutions in Discretized Two-Dimensional Sliding-Mode Control Systems
A Highly Linear 10-Bit DAC of Data Driver IC Using Source Degeneration Load for Active Matrix Flat-Panel Displays
A 0.6-V +4 dBm IIP3 LC Folded Cascode CMOS LNA With g m Linearization
Joint Estimation of Propagation Delay Dispersion and Time of Arrival in a 40-nm CMOS Comparator Bank for Time-Based Receivers
Global Exponential Stability Analysis of Cohen-Grossberg Neural Networks
8.1 nJ/b 2.4 GHz Short-Range Communication Receiver in 65 nm CMOS
Further Result on H ∞ Performance State Estimation of Delayed Static Neural Networks Based on an Improved Reciprocally Convex Inequality
Design of Synthetic Central Pattern Generators Producing Desired Quadruped Gaits
Resistance of Feedback Amplifiers: A Novel Representation
Systematic Co-Design of Matching Networks and Rectifiers for CMOS Radio Frequency Energy Harvesters
Consensus in Fractional-Order Multi-Agent Systems With Intermittence Sampled Data Over Directed Networks
Discrete Adjoint Sensitivity Analysis of Hybrid Dynamical Systems With Switching
Continuous Class-B/J Power Amplifier Using a Nonlinear Embedding Technique
A PVT-Resilient, Highly-Linear Fifth-Order Ring-Oscillator-Based Filter
Auto-Tuner-Based Controller for Quadcopter Attitude Tracking Applications
Hybrid Coupled Local Minimizers
Optimal Design for Realizing a Grounded Fractional Order Inductor Using GIC
VFAB: A Novel 2-Stage STTRAM Sensing Using Voltage Feedback and Boosting
A Low Power Real-time On-Chip Power Sensor in 45-nm SOI
Highly Integrated and Tunable RF Front Ends for Reconfigurable Multiband Transceivers: A Tutorial
SMI-MVDR Beamformer Implementations for Large Antenna Array and Small Sample Size
A Programmable 25-MHz to 6-GHz K vco Compensation
A Leakage-Compensated PLL in 65-nm CMOS Technology
Even Order Harmonic Series-L/Parallel-Tuned Class-E Frequency Multiplier
Low Latency Angle Recoding Methods for the Higher Bit-Width Parallel CORDIC Rotator Implementations
A Multiobjective Approach for Source Estimation in Fuzzy Networked Systems
A new method of Lyapunov functionals for delayed cellular neural networks
Theoretical Model of Ungrounded Inductance Realized With Two Gyrators
An Efficient Layered Decoding Architecture for Nonbinary QC-LDPC Codes
A 3.2 V -15 dBm Adaptive Threshold-Voltage Compensated RF Energy Harvester in 130 nm CMOS
Simplified Hysteresis Sliding-Mode Control for Superbuck Converter
An Efficient Variable Gain Homotopy Method Using the SPICE-Oriented Approach
Low-Order IIR Filter Bank Design
16-Channel Integrated Potentiostat for Distributed Neurochemical Sensing
A Low-Error, Memory-Based Fast Binary Logarithmic Converter
A computational method for the calculation of the feasibility boundary and clustering in differential-algebraic systems
Improved Continuous-Time Delta-Sigma Modulators With Embedded Active Filtering
Synthesis of Nonseparable 3-D Spatiotemporal Bandpass Filters on Analog Networks
Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance
A Single-Inductor Dual-Input Dual-Output DC-DC Converter for Photovoltaic and Piezoelectric Energy Harvesting Systems
A High-Speed Two-Cell BCH Decoder for Error Correcting in MLC nor Flash Memories
A 64-Channel 965-µW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS
Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization
Continuous-time ΔΣ modulators using distributed resonators
Error Correction With Chaotic Switching Between Convolutional Codecs
Further Results on Consensus of Second-Order Multi-Agent Systems With Exogenous Disturbance
Mixer-First FSK Receiver With Automatic Frequency Control for Body Area Networks
Weighted Improved Multiband-Structured Sub-Band Adaptive Filter Algorithms
Design of a fully-pipelined systolic array for flexible transposition-free VLSI of 2-D DFT
Corner block list representation and its application to floorplan optimization
Power-Saving 4 ˟ 4 Lattice-Reduction Processor for MIMO Detection With Redundancy Checking
Closed-Form Mixed Design of High-Accuracy All-Pass Variable Fractional-Delay Digital Filters
A Digital CMOS Silicon Photomultiplier Using Perimeter Gated Single Photon Avalanche Diodes With Asynchronous AER Readout
Novel Structures for Cyclic Convolution Using Improved First-Order Moment Algorithm
Fourth-Order Cascaded Sigma Delta Modulator Using Tri-Level Quantization and Bandpass Noise Shaping for Broadband Telecommunication Applications
The Adiabatically Driven StrongARM Comparator
The Bio-Oscillator: A Circuit for Cell-Culture Assays
Low Voltage Differential Input Stage With Improved CMRR and True Rail-to-Rail Common Mode Input Range
Low-Voltage CMOS subthreshold log-domain filtering
A 9-T 833-MHz 1.72-fJ/Bit/Search Quasi-Static Ternary Fully Associative Cache Tag With Selective Matchline Evaluation for Wire Speed Applications
A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS
Time-Interleaved Analog-to-Digital-Converter Compensation Using Multichannel Filters
A Modified Signal Flow Graph and Corresponding Conflict-Free Strategy for Memory-Based FFT Processor Design
A UWB-Based Sensor-to-Time Transmitter for RF-Powered Sensing Applications
Optimal Power Management in Fueled Systems With Finite Storage Capacity
A Novel Tunable Grounded Positive and Negative Impedance Multiplier
Modulation Flexibility in PLC: A Unified MCM Transceiver Design and Implementation
Current-Mode High-Accuracy High-Precision CMOS Amplifiers
High Power-Supply-Rejection (PSR) Current-Mode Low-Dropout (LDO) Regulator
All-Digital Fast-Locked Synchronous Duty-Cycle Corrector
Libra: An Automatic Design Methodology for CMOS Complex Gates
Quasi-equivalent feedforward system in asymptotic ΣΔ modulation
Robust Stability of Uncertain Discrete Impulsive Systems
An Architecture for Real-Time Arbitrary and Variable Sampling Rate Conversion With Application to the Processing of Harmonic Signals
An Efficient Method to Analyze Lock Range in Ring Oscillators With Multiple Injections
A Simultaneous Power and Downlink Data Transfer System With Pulse Phase Modulation
A Digitally Programmable Wide Tuning-Range Active Transformer for Inductorless BPF and DCOs
Compact Balanced Dual-Band BPFs Based on Short and Open Stub Loaded Resonators With Wide Common-Mode Suppression
A Receiver-Controlled Coupler for Multiple Output Wireless Power Transfer Applications
A Wide Dynamic Range CMOS Laser Radar Receiver With a Time-Domain Walk Error Compensation Scheme
An Efficient Zero Current Switching Control for L-Based DC-DC Converters in TEG Applications