yusuke1997/dblp-id-title huggingface dataset:
On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator
Solving Mesoscale Atmospheric Dynamics Using a Reconfigurable Dataflow Architecture
United Semiconductors of America
What is Happening to Power, Performance, and Software?
On the edge-thermal resistance [ICs]
The AMD Opteron Processor for Multiprocessor Servers
Evolution of the PowerPC architecture
Ubiquitous Parallel Computing from Berkeley, Illinois, and Stanford
Automated High-Level Code Optimization for Warehouse Performance
An Experimental Study of Soft Errors in Microprocessors
Moore's Law and Economic Architectures
The Proposed IEEE 1000 Microcomputer System Bus Standard
On-Demand Mobile CPU Cooling With Thin-Film Thermoelectric Array
Centipedes, SDOs, and Consortia (Standards)
Big Data and Democratization [Editorial]
IBM Power9 Processor Architecture
A performance analysis of Pentium processor systems
Area I/O's potential for future processor systems
A High-Throughput Neural Network Accelerator
Memory Built-in Self Test in Multicore Chips with Mesh-Based Networks
An Extreme Processor for an Extreme Experiment
Talisman: multimedia for the PC
Time for a Change in U.S. Antitrust for Technology?
A Compressed Spiking Neural Network Onto a Memcapacitive In-Memory Computing Array
History of Microcontrollers: First 50 Years
The MAP1000A VLIW Mediaprocessor
Real products, real technology Guest Editor's Introduction]
Reliable and Time-Efficient Virtualized Function Placement
How does processor MHz relate to end-user performance? II. Memory subsystem and instruction set
Accelerating Application Start-up with Nonvolatile Memory in Android Systems
Guest Editors' Introduction: Hot Chips 15--Scaling the Silicon Mountain
Optimizing Fault Tolerance in Embedded Distributed Systems
IBM Power5 Chip: A Dual-Core Multithreaded Processor
Microprocessor Bus Structures and Standards
Trace Wringing for Program Trace Privacy
An Interactive Debugging Environment
The data-driven microprocessor
Sparc64 VIIIfx: A New-Generation Octocore Processor for Petascale Computing
Special Issue on Hot Interconnects 30
Where Does Security Stand? New Vulnerabilities vs. Trusted Computing
Peach: A Multicore Communication System on Chip with PCI Express
Connectivity! Connectivity! Connectivity! May You Be More Connected Than Ever!!
The Q100 Database Processing Unit
Digital Signal Processor Trends
Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 2
Mauricio Breternitz Jr
Designing Digital Systems - SSI And MSI Vs. LSI And VLSI
Programmable DSPs: a brief overview
High-Speed Data Communication With Advanced Networks in Large Language Model Training
A software-hardware cosynthesis approach to digital system simulation
Optical High Radix Switch Design
MicroNews
Special Issue on Contemporary Industry Products 2025
iCFP: Tolerating All-Level Cache Misses in In-Order Processors
The MC68881 Floating-point Coprocessor
Special Issue on In-Memory Computing
Hot Chips: The Annual Feast of Riches
To the Era of Intelligent Chips and Systems
An Open Inter-Chiplet Communication Link: Bunch of Wires (BoW)
When elephants dance, mice watch out! [legal issues]
Delay-Space Arithmetic and Architecture
The Academic and Business Marriage
Detour: informed Internet routing and transport
Analog VLSI neural networks for impact signal processing
Design and Analysis of a Robust Real-Time Engine Control Network
Leadership Annoyances
A dynamic associative processor for machine vision applications
The IBM Telum II Processor
Intel Xeon 6 Product Family
Fault-Tolerant Microprocessor-Based Systems
The i486 CPU: executing instructions in one clock cycle
Implementation studies for a VLSI Prolog coprocessor
Standardization Skullduggery Never Ends: Apple v. Motorola
A TMS320C25-based multirate filter
A Mobile 3-D Object Recognition Processor With Deep-Learning-Based Monocular Depth Estimation
Weird Turn of Events in Continuing Rambus Saga
Going through the database
A time-multiplexed reconfigurable neuroprocessor
Bill, adopt a mensch strategy
Hardware-Software Codesign for High-Speed Signature-based Virus Scanning
Taiwan Semiconductor Manufacturing Company's $165 Billion Bet
Adjusting to Autonomous Trucking
The Paradigms, They Are A-Changin'
Multicore Resource Management
Voltage Noise in Production Processors
2015 Maurice Wilkes Award Given to Christos Kozyrakis
Commercializing the Internet
MPA: Parallelizing an Application onto a Multicore Platform Made Easy
Cerebras Architecture Deep Dive: First Look Inside the Hardware/Software Co-Design for Deep Learning
A Microprocessor-Based Pulse-Height Analyzer
A Personal Computer-based Speech Analysis And Synthesis System
KMDS: an expert system for integrated hardware/software design of microprocessor-based digital systems
Three-dimensional optical architecture and data-parallel algorithms for massively parallel computing
Approximate Computing, Intelligent Computing
Energy-Efficient Fast Fourier Transforms for Cognitive Radio Systems
The IBM Blue Gene/Q Interconnection Fabric
Portable and fault-tolerant software systems
Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing
Accelerating Genome Analysis: A Primer on an Ongoing Journey
Another Update on Standardization Skullduggery
Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance
Reconfiguring fault-tolerant two-dimensional array architectures
A Scalable Body Bias Optimization Method Toward Low-Power CGRAs
Subword parallelism with MAX-2
Computer-aided hardware-software codesign
A Design Philosophy for Microcomputers
Memory Persistency: Semantics for Byte-Addressable Nonvolatile Memory Technologies
The AMD Next-Generation "Zen 3" Core
Memory Pooling With CXL
Measure for Measure in the New Economy (Micro Economics)
An Architectural Comparison of 32-Bit Microprocessors
Improving Remote File Access in Distributed Object Stores by Decoupling Metadata and Data Paths Using NVMe-oF
Fast Protection-Domain Crossing in the CHERI Capability-System Architecture
Magnitude Approximations for Microprocessor Implementation
Performance Analysis of Unix-based Network File Systems
Full-Stack Memory Model Verification with TriCheck
PCI Express 6.0 Specification: A Low-Latency, High-Bandwidth, High-Reliability, and Cost-Effective Interconnect With 64.0 GT/s PAM-4 Signaling
System on a Package Innovations With Universal Chiplet Interconnect Express (UCIe) Interconnect
Low-Power Design and Temperature Management
Simultaneous multithreading: a platform for next-generation processors
Compiling Java just in time
Smart: Single-Cycle Multihop Traversals over a Shared Network on Chip
UCIe: Standard for an Open Chiplet Ecosystem
Reducing the Impact of Interjob Interference in Dragonfly Networks Using Virtual Partitions
Design and Verification of a Stack Processor Virtual Component
SuperENC: MPEG-2 video encoder chip
Guest Editors' Introduction: Interaction of Many-Core Computer Architecture and Operating Systems
Wish Branches: Enabling Adaptive and Aggressive Predicated Execution
Microarchitecture-Independent Workload Characterization
System optimization for OLTP workloads
Fuzzy inference on an analog fuzzy chip
A floating-point VLSI chip for the TRON architecture: an architecture for reliable numerical programming
Fuzzy Hardware Challenges
Trends and Challenges in VLSI Circuit Reliability
Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences
A Microcomputer-Based Controller for an Amusement Park Ride
A Flexible, Self-Tuning, Fault-Tolerant Functional Unit Array Processor
Always-on Vision Processing Unit for Mobile Applications
Fuzzy inference and fuzzy inference processor
Toward Ideal On-Chip Communication Using Express Virtual Channels
Guest Editors' Introduction: Hot Interconnects
Improving Throughput of Power-Constrained Many-Core Processors Based on Unreliable Devices
VLSI And System Performance Modeling
e6500: Freescale's Low-Power, High-Performance Multithreaded Embedded Processor
Portable electronics packaging technologies
Product Summary
A high-speed wireless LAN
Synchronous Dataflow Architecture for Network Processors
Micro Economics: Does Google Have Too Much Money?
The Next Security Frontier: Taking the Mystery Out of the Supply Chain
DOOM: A Decentralized Object-Oriented Machine
Monitoring and Attestation of Virtual Machine Security Health in Cloud Computing
Model-Based Fault-tolerant Control Reconfiguration for General Network Topologies
Special Issue on Hot Chips 2024
Using NUMA interconnects for highly available filers
Fine-Grained Activation for Power Reduction in DRAM
Canaries, whips, and sails
Micro view. Clipper: soon a de facto standard?
A Heterogeneous Von Neumann/Explicit Dataflow Processor
From the Memory Lane!
The Economics of Confrontational Conversation
TinyML but by No Means a Tiny Feat!
European Cooperation in the Information Technology Industry
Thinking about Technology
Machine Learning Acceleration
Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems
Compute Solution for Tesla's Full Self-Driving Computer
DataPlay's Mobile Information Distribution and Storage Technology
The associative processor system CAPRA: architecture and applications
HAMLeT Architecture for Parallel Data Reorganization in Memory
Why standards are here to stay
Combining microcontroller units and PLDs for best system design
Visual IoT: Architectural Challenges and Opportunities; Toward a Self-Learning and Energy-Neutral IoT
RMP: fault-tolerant group communication
Energy-Aware Accounting and Billing in Large-Scale Computing Facilities
A Performance Comparison of Three Contemporary 16-bit Microprocessors
FPGA Computing and More!
QoS for High-Performance SMT Processors in Embedded Systems
Future system-on-silicon LSI chips
The superscalar architecture of the MC68060
Microarchitectural Protection Against Stack-Based Buffer Overflow Attacks
PivotPoint: Clockless Crossbar Switch for High-Performance Embedded Systems
Architectures for the Post-Moore Era
LSI Testing Techniques
Top Picks from the 2012 Computer Architecture Conferences
Microlithography: Trends, Challenges, Solutions, and Their Impact on Design
PEFL: Deep Privacy-Encoding-Based Federated Learning Framework for Smart Agriculture
Joseph A. (Josh) Fisher Receives the 2012 IEEE B. Ramakrishna Rau Award
Coping with Parametric Variation at Near-Threshold Voltages
Who Is Gordon Moore, and Why Is There a Law Named for Him?
An OASIS Simulation of the ZNET Microcomputer Network
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies - Part X: Patent Families
Power- and Complexity-Aware Issue Queue Designs
Array-based analog computation
Virtual Hierarchies
Detecting Hardware Covert Timing Channels
Making Address-Correlated Prefetching Practical
2018 International Symposium on Computer Architecture Influential Paper Award
Butterfly Effects and Legacies
The Blackford Northbridge Chipset for the Intel 5000
The Long Arc Behind Bill Gates' Wealth, Part 2
Performance Evaluation and Its Impact on Design
Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor
TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture
An Update on "Exhaustion" - Supreme Court Decides Quanta Case
AMD Versal AI Edge Series Gen 2
Virtual-address caches. Part 1: problems and solutions in uniprocessors
Process and Circuit Optimization for Power Reduction Using DDC Transistors
An Efficient Software Driver Processor Implementation
Napster: A Walking Copyright Infringement?
Transputers-past, present and future
Database Analytics: A Reconfigurable-Computing Approach
When is two too many? [standards]
Micro Law: a guardedly cheerful note-for a change [computer program copyright]
Virtual-address caches.2. Multiprocessor issues
The Gmicro/300 32-bit microprocessor
Graph Analytics Accelerators for Cognitive Systems
Fault Tolerance in Continuous Process Control
A Resistive CAM Processing-in-Storage Architecture for DNA Sequence Alignment
Design automation in MEDEA: present and future
SiMul: An Algorithm-Driven Approximate Multiplier Design for Machine Learning
Improving Key-Value Cache Performance With Heterogeneous Memory Tiering: A Case Study of Compute-Express-Link-Based Memory Expansion
Resilient High-Performance Processors with Spare RIBs
The Structure of Computer Architecture (R)evolution
A New 40-nm FPGA and ASIC Common Platform
Intelligent-Memory Architecture for Artificial Neural Networks
Antitrust in Three Acts
A fast digital fuzzy processor
The VLSI Control Structure of a CMOS Microcomputer
Three SoCs in Three Years: How to Get Agile
Introducing the Intel i860 64-bit microprocessor
Precise Interrupts
Platform Conflicts
Special Issue on Top Picks From the 2022 Computer Architecture Conferences
ACCL: Architecting Highly Scalable Distributed Training Systems With Highly Efficient Collective Communication Library
CMOS Scaling Trends and Beyond
The Arm Neoverse N1 Platform: Building Blocks for the Next-Gen Cloud-to-Edge Infrastructure SoC
Fault-tolerant communication in embedded supercomputing
BiFrost: A Composable, Resilient Interconnect Network Architecture for Scalable Artificial Intelligence Systems
Parallel computers for advanced information processing
Accelerating Allreduce With In-Network Reduction on Intel PIUMA
Exploiting instruction- and data-level parallelism
FPGAs versus GPUs in Data centers
Hot Chips and the Incomplete Job of Exploiting Them
Network-Assisted Noncontiguous Transfers for GPU-Aware MPI Libraries
The RISC penalty
A QoS-Enabled On-Die Interconnect Fabric for Kilo-Node Chips
Unpriced and Crucial
Trends in semiconductor memories
Arm Architecture And Systems
The Gnat versus the Borg [Microsoft]
Scalable Hardware Memory Disambiguation for High-ILP Processors
Achieving supercomputer performane for neural net simulation with an array of digital signal processors
Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications
Pentium 4 Performance-Monitoring Features
Room for a Thousand Flowers to Bloom
Countering Load-to-Use Stalls in the NVIDIA Turing GPU
Floppy Disk Data Transfer Techniques
The ChARM tool for tuning embedded systems
Power-Efficient TCAMS for Bursty Access Patterns
Address Translation Aware Memory Consistency
Optical neural chips
News: IBM's Cell chip; Electroluminescent light source; Disc storage; Electron microscope; Cornell expands research center; Low-voltage gas sensor; Plastics explored
Patents and High-Speed Datacenter Interconnects
Emergent Behaviors in the Internet of Things: The Ultimate Ultra-Large-Scale System
Domain Partitioning Technology for Embedded Multicore Processors
speedAI240: A 2-Petaflop, 30-Teraflops/W At-Memory Inference Acceleration Device With 1456 RISC-V Cores
HDTV research in Japan
VIS speeds new media processing
Architecture and implementation of ICs for a DSC-HDTV video decoder system
Language Support for Memory Persistency
Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches
The software industry through an academic looking glass
Applying and implementing the MPEG-4 multimedia standard
Approximate Fair Dropping for Variable-Length Packets
IEEE-USA Tells Congress that Patent Reform Is Essential to Economic Recovery
Digitization and Value Creation
Processing element design for a parallel computer
Large chip vs. MCM for a high-performance system
Plasticine: A Reconfigurable Accelerator for Parallel Patterns
More on Old Topics
Quantum Computing - From NISQ to PISQ
Special Issue on Cool Chips and Hot Interconnects
Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning
A low-cost graphics and multimedia workstation chip set
The Breakthrough Memory Solutions for Improved Performance on LLM Inference
A multilevel systolic approach for fuzzy inference hardware
Inviting participants in standard setting
Hardware monitoring of a multiprocessor system
The AzusA 16-Way Itanium Server
Hot Interconnects and Hot Topics
Developing the AMD-K5 architecture
The Alpha AXP architecture and 21064 processor
Domain-Specific Approximation for Object Detection
Godson-T: An Efficient Many-Core Processor Exploring Thread-Level Parallelism
Unlocking Ordered Parallelism with the Swarm Architecture
Guest Editors' Introduction: Power and Complexity Aware Design
End-to-End Performance of 10-Gigabit Ethernet on Commodity Systems
Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance
Axilog: Abstractions for Approximate Hardware Design and Reuse
Micro standards-building standards
Performance features of the PA7100 microprocessor
Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures
2014 International Symposium on Computer Architecture Influential Paper Award; 2014 Maurice Wilkes Award Given to Ravi Rajwar
Architectural Simulators Considered Harmful
SSDStreamer: Specializing I/O Stack for Large-Scale Machine Learning
The Vital Two Percent
High Availability and Reliability in the Itanium Processor
A Quantitative, Experimental Approach to Measuring Processor Side-Channel Security
MetaTM/TxLinux: Transactional Memory for an Operating System
Analyzing Data Locality in Numeric Applications
The PAL20RA10 Story - The Customization of a Standard Product
SDAARC: An Extended Cache-Only Memory Architecture
Intel Local Network Architecture
Automatic Compilation Will Be Key for Success of the Accelerator Revolution!
The Gmicro/500 superscalar microprocessor with branch buffers
Special Issue on Artificial Intelligence at the Edge
iWatcher: Simple, General Architectural Support for Software Debugging
Format wars all over again
Hot Chips: Industry and Academia Cutting-Edge Microprocessors
Luiz André Barroso: Brilliant Engineer, Humble Leader, and Mentor
Addressing the challenges of advanced packaging and interconnection
Parallel Computing Experiences with CUDA
The Case for Full-Throttle Computing: An Alternative Datacenter Design Strategy
Evaluating the Mflops measure
Efficient Disaggregated Cloud Storage for Cold Videos With Neural Enhancement
A Real-Time Fortran Executive
Low-Power Convolutional Neural Network Processor for a Face-Recognition System
Chip Design 2020
Overcoming Communication Latency Barriers in Massively Parallel Scientific Computation
The MC68824 Token Bus Controller VLSI for the Factory LAN
Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
Active Standards Projects [Micro Standards]
Appropriate and inappropriate legal protection of user interfaces and screen displays. 3. Copyright law, the courts, and the copyright office
More Hot Stuff
Micro law: paradigms lost
New Route In System Integration: Chip-Package Codesign
Warp: A Hardware Platform for Efficient Multimodal Sensing With Adaptive Approximation
Consumer applications: a driving force for high-level synthesis of signal-processing architectures
Kabini: An AMD Accelerated Processing Unit System on A Chip
ARM7TDMI power consumption
The Design Space of Register Renaming Techniques
Top Picks and Welcoming New Editorial Board Members
Designing reliable systems with unreliable components
The Mechanics of Filing a Patent
Scaling Reverse Time Migration Performance through Reconfigurable Dataflow Engines
High-Performance Cooling for Power Electronics via Electrochemical Additive Manufacturing
Transactional Coherence and Consistency: Simplifying Parallel Hardware and Software
Supercharging Your Creative Skills
A Low-Power Artificial-Intelligence-Based 3-D Rendering Processor With Hybrid Deep Neural Network Computing
DMP: Deterministic Shared-Memory Multiprocessing
A PWM fuzzy logic controller
Meet the FaM1ly
Java-centric distributed computing
CPUs, GPUs, and More From Hot Chips'32
Scalable Vector Processors for Embedded Systems
Are Field-Programmable Gate Arrays Ready for the Mainstream?
Hardware Acceleration and a Grateful Goodbye
Temporal Approximate Function Memoization
A CMOS neural network for pattern association
The Texas Instruments TMS320C25 Digital Signal Microcomputer
A Programmable State Machine Architecture for Packet Processing
Top Picks
Starting an international standard
Combining Multiple Tiny Machine Learning Models for Multimodal Context-Aware Stress Recognition on Constrained Microcontrollers
The Memory-Integrated Network Interface
Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model
Configurable Clouds
Accelerating Next-Generation Public-Key Cryptosystems on General-Purpose CPUs
Rapid Prototyping Using Field-Programmable Logic Devices
Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap
Compute Express Link (CXL): Enabling Heterogeneous Data-Centric Computing With Heterogeneous Memory Hierarchy
Improving SQL Join Algorithms for Distributed Systems: A Case Study of Compute Express Link-Based Multihost Shared Memory
Looking Forward to the 2016 Theme Issues
Y2K Product Liability
Special Issue on Hot Chips 34
When technologies converge
Analyzing and comparing Montgomery multiplication algorithms
Transient fault tolerance in digital systems
Top Picks From Computer Architecture Conferences!
Anti-knockoff article protection law
What Kinds of Computer-Software-Related Advances (if Any) Are Eligible for Patents? Part I
A Synthetic Instruction Mix for Evaluating Microprocessor Performance
Restraints on technology advances
Accelerators and Coherence: An SoC Perspective
A Heuristic Routing Algorithm
An Introduction to Life-Cycle Emissions of Artificial Intelligence Hardware
Parallel, high-speed PC fuzzy control
Will Carbon Nanotube Memory Replace DRAM?
How RISCy is DSP?
System implementations of analog VLSI velocity sensors
Z80 - The 1970s Microprocessor Still Alive
MHADBOR: AI-Enabled Administrative-Distance-Based Opportunistic Load Balancing Scheme for an Agriculture Internet of Things Network
Expertise at Our Fingertips
Return Of The Jaded
Impact of Future Technologies on Architecture
Agile Paging for Efficient Memory Virtualization
Winsocking the competition
Rise of the Agentic AI Workforce
Fuzziness versus all or nothing
The Jrpm System for Dynamically Parallelizing Sequential Java Programs
Deep Packet Inspection using Parallel Bloom Filters
Formal SDOs: They're Still Alive
No More Wishful Thinking
Heterogeneous Wireless Sensor Nodes that Target the Internet of Things
Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication
Automotive Computing
Unlocking Hardware Potential With Usage Meters
The Online Honesty Box
Building Ultralow-Latency Interconnection Networks Using Photonic Integration
Micro standards: truth and specious urban myths
A 4-bit, 250-MIPS processor using Josephson technology
The history of the 4004
Fast, Accurate, and Validated Full-System Software Simulation of x86 Hardware
Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems
Intelligent cruise control and roadside information
The Birth of the Microprocessor
Standardization Skullduggery Revisited
Democratizing Data-Driven Agriculture Using Affordable Hardware
Introducing the Adaptive Energy Management Features of the Power7 Chip
Architectural Considerations for CPU and Network Interface Integration
Automotive Computing, Neuromorphic Computing, and Beyond
Programming Multicores: Do Applications Programmers Need to Write Explicitly Parallel Programs?
A Virtualization Solution for BYOD With Dynamic Platform Context Switching
Design challenges of technology scaling
The architecture of the Sure System 2000 communications processor
FERMTOR: A Tunable Multiprocessor Architecture
An extensible DBMS for small and medium systems
Software report-completely automated assembly
Hot Chips 27 Highlights
The General-Purpose Interface Bus
Active Low-Power Modes for Main Memory with MemScale
Memory management for user-level network interfaces
Micro Law-software patents
Special Issue on Hot Chips 33
The Role of the CPU in Energy-Efficient Mobile Web Browsing
Implementing Ultra-Low-Latency Datacenter Services with Programmable Logic
Alice v. CLS Bank: Are US Business-Method and Software Patents Doomed? Part 1
Network-on-Chip Design Guidelines for Monolithic 3-D Integration
Compiling for the IBM Matrix Engine for Enterprise Workloads
Nanoscale Optical Computing Using Resonance Energy Transfer Logic