yusuke1997/dblp-id-title huggingface dataset:
Delay-fault test generation and synthesis for testability under a standard scan design methodology
Access-Pattern-Aware On-Chip Memory Allocation for SIMD Processors
Efficient Memristor Model Implementation for Simulation and Application
Stochastic Testing Method for Transistor-Level Uncertainty Quantification Based on Generalized Polynomial Chaos
A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method
Inverter models of CMOS gates for supply current and delay evaluation
When Random Is Bad: Selective CRPs for Protecting PUFs Against Modeling Attacks
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning
Pseudorandom test-length analysis using differential solutions
A genetic algorithm framework for test generation
The MEET Approach: Securing Cryptographic Embedded Software Against Side Channel Attacks
Functional timing analysis using ATPG
High-Throughput Training of Deep CNNs on ReRAM-Based Heterogeneous Architectures via Optimized Normalization Layers
Hybrid Neural Network Model for Raw Bit Error Rate Prediction of 3-D TLC NAND Flash Memory
Transient simulation of integrated circuits in the charge-voltage plane
Learning Memory-Contention Timing Models With Automated Platform Profiling
Device and circuit simulation interface for an integrated VLSI design environment
Exploiting near symmetry in multilevel logic synthesis
Analog testing by characteristic observation inference
Omega-an octree-based mixed element grid allocator for the simulation of complex 3-D device structures
SPROUT - Smart Power Routing Tool for Board-Level Exploration and Prototyping
Selective Determination of Floquet Quantities for the Efficient Assessment of Limit Cycle Stability and Oscillator Noise
Rapid Assessment of Design Sensitivity to Process Excursions via Scaled Sigma Sampling
Energy-Aware Nonpreemptive Scheduling of Mixed-Criticality Real-Time Task Systems
Addendum to "Synthesis of robust delay-fault testable circuits: Theory"
An approach for the formal verification of DSP designs using Theorem proving
AnyHLS: High-Level Synthesis With Partial Evaluation
Hardware Protection via Logic Locking Test Points
EBDN: Entropy-Based Double Nonuniform Sensing Algorithm for LDPC Decoding in TLC nand Flash Memory
Timing-driven maze routing
Performance-driven routing with multiple sources
L2O-ILT: Learning to Optimize Inverse Lithography Techniques
PCB Escape Routing and Layer Minimization for Digital Microfluidic Biochips
Robust Analog/RF Circuit Design With Projection-Based Performance Modeling
Retention Accelerated Testing for 3-D QLC nand Flash Memory: Characterization, Analysis, and Modeling
Effective Power Optimization Under Timing and Voltage-Island Constraints Via Simultaneous V dd , V th Assignments, Gate Sizing, and Placement
Flex-SFU: Activation Function Acceleration With Nonuniform Piecewise Approximation
Chip-level charged-device modeling and simulation in CMOS integrated circuits
Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble
System simulation of mixed-signal multi-domain microsystems with piecewise linear models
A Droplet-Manipulation Method for Achieving High-Throughput in Cross-Referencing-Based Digital Microfluidic Biochips
A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping
Testing 3-D IC Through-Silicon-Vias (TSVs) by Direct Probing
A multiple-strength multiple-delay compiled-code logic simulator
Inferring Assertion for Complementary Synthesis
Dynamic Radial Placement and Routing in Paper Microfluidics
On reducing test application time for scan circuits using limited scan operations and transfer sequences
A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation
Polynomial splines for MOSFET model approximation
Fast Thermal Simulation for Runtime Temperature Tracking and Management
DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning Accelerators
An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis
SUN: Dynamic Hybrid-Precision SRAM-Based CIM Accelerator With High Macro Utilization Using Structured Pruning Mixed-Precision Networks
Compact reduced-order modeling of weakly nonlinear analog and RF circuits
SCRIPT: a critical path tracing algorithm for synchronous sequential circuits
Mixed-Criticality Scheduling Upon Permitted Failure Probability and Dynamic Priority
Symbolic Layout System: Application Results and Functional Improvements
Reverse Engineering for 2.5-D Split Manufactured ICs
Waveform relaxation solution of the ABCD matrices of nonuniform transmission lines for transient analysis
Yield-Aware Pareto Front Extraction for Discrete Hierarchical Optimization of Analog Circuits
ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture
Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement
Longest-path selection for delay test under process variation
Timed state space exploration using POSETs
Fast Retraining of Approximate CNNs for High Accuracy
Client Scheduling and Resource Management for Efficient Training in Heterogeneous IoT-Edge Federated Learning
Global routing based on Steiner min-max trees
End-to-End Latency Analysis of Dataflow Scenarios Mapped Onto Shared Heterogeneous Resources
MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis
Automated bus generation for multiprocessor SoC design
Fast-Accurate Full-Chip Dynamic Thermal Simulation With Fine Resolution Enabled by a Learning Method
RP-SYN: synthesis of random pattern testable circuits with test point insertion
Co-Optimization and Analysis of Signal, Power, and Thermal Interconnects in 3-D ICs
Channel-Routing Problem in the Knock-Knee Mode Is NP-Complete
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation
Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits
New techniques for untestable fault identification in sequential circuits
Self-referential verification for gate-level implementations of arithmetic circuits
Unary Coding and Variation-Aware Optimal Mapping Scheme for Reliable ReRAM-Based Neuromorphic Computing
Locating bridging faults using dynamically computed stuck-at fault dictionaries
Tag compression for low power in dynamically customizable embedded processors
The Dark Side: Security and Reliability Concerns in Machine Learning for EDA
Acceleration of relaxation-based circuit simulation using a multiprocessor system
Leveraging the Error Resilience of Neural Networks for Designing Highly Energy Efficient Accelerators
Fault secure datapath synthesis using hybrid time and hardware redundancy
Reliability-Aware Personalized Deployment of Approximate Computation IoT Applications in Serverless Mobile Edge Computing
Placement and Routing for Cross-Referencing Digital Microfluidic Biochips
An I/O Scheduling Strategy for Embedded Flash Storage Devices With Mapping Cache
LPRAM: a novel low-power high-performance RAM design with testability and scalability
An ASIC Accelerator for QNN With Variable Precision and Tunable Energy Efficiency
FAUST: An MOS Fault Simulator with Timing Information
VeriTrust: Verification for Hardware Trust
Compact Model Parameter Extraction Using Bayesian Inference, Incomplete New Measurements, and Optimal Bias Selection
POLAR-Express: Efficient and Precise Formal Reachability Analysis of Neural-Network Controlled Systems
Hierarchical tolerance analysis using statistical behavioral models
Charge-Sharing Models for Switch-Level Simulation
Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains
NVQuery: Efficient Query Processing in Nonvolatile Memory
Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model
Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages
Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration
Computing the Synchronization Regions of Injection-Locked Strongly Nonlinear Oscillators for Frequency Division Applications
Detailed Placement for Enhanced Control of Resist and Etch CDs
Multiple Transient Faults in Combinational and Sequential Circuits: A Systematic Approach
Scenario-Based Online Reachability Validation for CPS Fault Prediction
LeGO: A Learning-Guided Obfuscation Framework for Hardware IP Protection
Ærø: A Platform Architecture for Mixed-Criticality Airborne Systems
Generation of New Low-Complexity March Algorithms for Optimum Faults Detection in SRAM
Application of General Orthogonal Polynomials to Fast Simulation of Nonlinear Descriptor Systems Through Piecewise-Linear Approximation
Efficient approximation of symbolic expressions for analog behavioral modeling and analysis
Layering Algorithms For Single-Row Routing
Efficient BIST TPG design and test set compaction via input reduction
Dynamic Priority Scheduling of Multithreaded ROS 2 Executor With Shared Resources
Temperature Effects of Program Operation in 3-D nand Flash Memory: Observations, Analysis, and Solutions
Verification of Code Motion Techniques Using Value Propagation
Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation
Determining the Number of Paths in Decision Diagrams by Using Autocorrelation Coefficients
Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application
PARoute2: Enhanced Analog Routing via Performance-Drive Guidance Generation
Multitoken-Based Power Management for NAND Flash Storage Devices
Retiming and Resynthesis: A Complexity Perspective
Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC
Hierarchical Behavioral Learning-Based Dynamic Electromigration Analysis for Signal Networks
An H-V alternating router
Imitating Functional Operations for Mitigating Side-Channel Leakage
ITT-RNA: Imperfection Tolerable Training for RRAM-Crossbar-Based Deep Neural-Network Accelerator
Compact and efficient code generation through program restructuringon limited memory embedded DSPs
BIST of PCB interconnects using boundary-scan architecture
Automatic Verification of Embedded System Code Manipulating Dynamic Structures Stored in Contiguous Regions
TRAVERSAL: A Fast and Adaptive Graph-Based Placement and Routing for CGRAs
Efficient FHE Radix-2 Arithmetic Operations Based on Redundant Encoding
C-based SoC design flow and EDA tools: an ASIC and system vendorperspective
Area minimization for floorplans
Statistical Compact Modeling With Artificial Neural Networks
State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design Validation
Analytical bound for unwanted clock skew due to wire width variation
An Efficient Bit-Sparse DNN Accelerator Exploiting Adaptive Bit-Serial Computations
Adaptive mesh generation preserving the quality of the initial grid
TRIM: A Design Space Exploration Model for Deep Neural Networks Inference and Training Accelerators
Electrical analysis and modeling of floating-gate fault
New implicit integration method for efficient latency exploitation in circuit simulation
Technology Legalization and Optimization for Adiabatic Quantum-Flux Parametron
A Compact Modeling Methodology for Experimental Memristive Devices
Method of temporary coordinate domains for moving boundary value problems [semiconductor processing simulation]
On Phase Models for Oscillators
Synthesis of Hidden State Transitions for Sequential Logic Locking
Enhancing Design Qualities Utilizing Multibit Flip-Flops: A Design and Technology Co-Optimization Driven Approach
pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment
End-to-End Analysis and Design of a Drone Flight Controller
Lookup Table-Based Fast Reliability-Aware Sample Preparation Using Digital Microfluidic Biochips
Improved Physics for Simulating Submicron Bipolar Devices
Comments on "Modeling of Metallic Carbon-Nanotube Interconnects for Circuit Simulations and a Comparison With Cu Interconnects for Sealed Technologies"
Equivalence Checking of Sequential Quantum Circuits
Reducing power dissipation in CMOS circuits by signal probability based transistor reordering
Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers
Exploring the Effect of Energy Storage Sizing on Intermittent Computing System Performance
Nonstationary carrier dynamics in quarter-micron Si MOSFETs
FlexHMB: A Flexible HMB Design Toward Bufferless Mobile Flash
Learning as applied to stochastic optimization for standard-cellplacement
Linear cofactor relationships in Boolean functions
Modeling Interrupts for Software-Based System-on-Chip Verification
Creating small fault dictionaries [logic circuit fault diagnosis]
Aggressor alignment for worst-case crosstalk noise
Continuous signature monitoring: low-cost concurrent detection of processor control errors
BRoCoM: A Bayesian Framework for Robust Computing on Memristor Crossbar
Memory-Based High-Level Synthesis Optimizations Security Exploration on the Power Side-Channel
Preparing Fluid Samples Under Retention Time Constraints Using Flow-Based Microfluidic Biochips
Scrubbing-Aware Secure Deletion for 3-D NAND Flash
Accurate Predictions of Process-Execution Time and Process Status Based on Support-Vector Regression for Enterprise Information Systems
DiagNNose: Toward Error Localization in Deep Learning Hardware-Based on VTA-TVM Stack
Robust Deep Reservoir Computing Through Reliable Memristor With Improved Heat Dissipation Capability
Janus: A Flexible Processing-in-Memory Graph Accelerator Toward Sparsity
AccALS 2.0: Accelerating Approximate Logic Synthesis by Simultaneous Selection of Multiple Local Approximate Changes
Analysis of Digital Circuit Dynamic Behavior With Timed Ternary Decision Diagrams for Better-Than-Worst-Case Design
Study of p-(6H, 4H, 3C)SiC/n-GaN Heterojunction SDR, DDR IMPATT Diodes
1-D Cell Generation With Printability Enhancement
Pin assignment with global routing for VLSI building block layout
Minimizing the number of switchboxes for region definition and ordering assignment
Automating the design of computer systems
On-Chip Optical Channel Routing for Signal Loss Minimization
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
Synchronization of pipelines
Layer Assignment of Buses and Nets With Via-Count Constraint in High-Speed PCB Designs
VoltJockey: A New Dynamic Voltage Scaling-Based Fault Injection Attack on Intel SGX
HaloFL: Efficient Heterogeneity-Aware Federated Learning Through Optimal Submodel Extraction and Dynamic Sparse Adjustment
Feature Indented Assertions for Analog and Mixed-Signal Validation
Entropy Production-Based Full-Chip Fatigue Analysis: From Theory to Mobile Applications
Defending Hardware-Based Malware Detectors Against Adversarial Attacks
TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA's Interconnect Network
Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits
Efficient Backward Reachability Using the Minkowski Difference of Constrained Zonotopes
Automated Dimensioning of Networked Labs-on-Chip
Systolic routing hardware: performance evaluation and optimization
General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects
Sequence-pair approach for rectilinear module placement
Two-dimensional analysis of a merged BiPMOS device
Vectorless Estimation of Maximum Instantaneous Current for Sequential Circuits
Unconstrained via minimization for topological multilayer routing
On "A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters"
Multischedule Synthesis for Variant Management in Automotive Time-Triggered Systems
Efficient Statistical Parameter Extraction for Modeling MOSFET Mismatch
A Multiagent Minority-Game-Based Demand-Response Management of Smart Buildings Toward Peak Load Reduction
Modeling of VLSI RC parasitics based on the network reduction algorithm
Identifying Biases of a Defect Diagnosis Procedure
Advantages of Collocation Methods Over Finite Differences in One-Dimensional Monte Carlo Simulations of Submicron Devices
A region-based theory for state assignment in speed-independent circuits
Minimum-Period Register Binding
Reduced-Pin-Count BOST for Test-Cost Reduction
A Markov Chain Framework for Modeling the Statistical Properties of Stochastic Computing Finite-State Machines
Optimization of Imprecise Circuits Represented by Taylor Series and Real-Valued Polynomials
SuperSlash: A Unified Design Space Exploration and Model Compression Methodology for Design of Deep Learning Accelerators With Reduced Off-Chip Memory Access Volume
CoGNN: An Algorithm-Hardware Co-Design Approach to Accelerate GNN Inference With Minibatch Sampling
Structured Term Pruning for Computational Efficient Neural Networks Inference
SnapMem: Hardware/Software Cooperative Memory Resistant to Cache-Related Attacks on ARM-FPGA Embedded SoC
Global Clean Page First Replacement and Index-Aware Multistream Prefetcher in Hybrid Memory Architecture
High-Quality Transition Fault ATPG for Small Delay Defects
Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability
BEAVER: a computational-geometry-based tool for switchbox routing
A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits
ATPG-XP: Test Generation for Maximal Crosstalk-Induced Faults
On Improving the Security of Logic Locking
New performance-driven FPGA routing algorithms
A Predictor/CAD Model for Buried-Channel MOS Transistors
Architectural Exploration of Large-Scale Hierarchical Chip Multiprocessors
A Fuzzy-Matching Model With Grid Reduction for Lithography Hotspot Detection
Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits
A novel scheme to reduce test application time in circuits with full scan
Pruning Deep Reinforcement Learning for Dual User Experience and Storage Lifetime Improvement on Mobile Devices
C5M-a control-logic layout synthesis system for high-performance microprocessors
Three-Dimensional Neuromorphic Computing System With Two-Layer and Low-Variation Memristive Synapses
Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach
Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression
Design-Intent Coverage - A New Paradigm for Formal Property Verification
ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches
Capacitance of top leads metal - comparison between formula, simulation, and experiment
Low-power state assignment targeting two- and multilevel logic implementations
High-level crosstalk defect Simulation methodology for system-on-chip interconnects
MDA: A Reconfigurable Memristor-Based Distance Accelerator for Time Series Mining on Data Centers
An Integrated Automated Layout Generation System for DSP Circuits
System-level data-format exploration for dynamically allocated datastructures
Preservation of passivity during RLC network reduction via split congruence transformations
Analytical CAD Models for the Signal Transients and Crosstalk Noise of Inductance-Effect-Prominent Multicoupled RLC Interconnect Lines
Efficient Image Processing via Memristive-Based Approximate In-Memory Computing
Generation of Two-Cycle Tests for Structurally Similar Circuits
A Compile-Time Framework for Tolerating Read Disturbance in STT-RAM
Ultralow Power Zirconium Electrolyte-Based Synaptic Device for Neuromorphic Computing
Some conditions under which hierarchical verification is O(N)
Hierarchical Mapping of Large-Scale Spiking Convolutional Neural Networks Onto Resource-Constrained Neuromorphic Processor
Hierarchical Formal Verification of Hardware
Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function
Security Assessment of Micro-Electrode-Dot-Array Biochips
Equivalent Elmore delay for RLC trees
A Retrospective on Path ORAM
Perturb and simplify: multilevel Boolean network optimizer
Electromagnetic interconnects and passives modeling: softwareimplementation issues
BeeGOns!: A Wireless Sensor Node for Fog Computing in Smart City Applications
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs
Bit-fixing in pseudorandom sequences for scan BIST
On synchronizable circuits and their synchronizing sequences
ATA-Cache: Contention Mitigation for GPU Shared L1 Cache With Aggregated Tag Array
Improvement in norm-reducing Newton methods for circuit simulation
WiND: An Efficient Post-Silicon Debug Strategy for Network on Chip
Measurements and analyses of substrate noise waveform inmixed-signal IC environment
Multilevel cooperative search for the circuit/hypergraphpartitioning problem
A macrocell approach for VLSI processor design
Automating Logic Transformations With Approximate SPFDs
Approaches for Assigning Offsets to Signals for Improving Frame Packing in CAN-FD
Analysis and synthesis of combinational pass transistor circuits
An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating
An SFS Berger check prediction ALU and its application to self-checking processor designs
MULTES: Multilevel Temporal-Parallel Event-Driven Simulation
CacheTree: Reducing Integrity Verification Overhead of Secure Nonvolatile Memories
Modeling and formal verification of the Fairisle ATM switch fabricusing MDGs
Risk-5: Controlled Approximations for RISC-V
Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits
A Q-Learning-Based Display Energy Optimization Scheme for Android Systems
Optimized Selection of Reliable and Cost-Effective Safety-Critical System Architectures
Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis
PISOV: Physics-Informed Separation of Variables Solvers for Full-Chip Thermal Analysis
A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards
Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits
Automatic configuration of embedded multicomputer systems
Group delay as an estimate of delay in logic
Low-Cost EVM Measurement of ZigBee Transmitters From 1-bit Undersampled Acquisition
ABCFI: Fast and Lightweight Fine-Grained Hardware-Assisted Control-Flow Integrity
Circuit Pack Parameter Estimation Using Rent's Rule
Online Rare Category Identification and Data Diversification for Edge Computing
Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs
pPIRW: An Efficient and Accurate Precalculation Path Integral Random Walk Solver for Steady-State Thermal Simulation With Robin Boundary Conditions
The use of small pivot perturbation in circuit analysis
TCAD EIC Message: February 2019
Information theoretic measures for power analysis [logic design]
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems
Crosstalk- and performance-driven multilevel full-chip routing
Design Space Exploration for Wireless NoCs Incorporating Irregular Network Routing
A wire length estimation technique utilizing neighborhood density equations
Nanowire-Aware Routing Considering High Cut Mask Complexity
Computational Restructuring: Rethinking Image Compression Using Resistive Crossbar Arrays
CAST: Content-Aware STT-MRAM Cache Write Management for Different Levels of Approximation
System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip
Improved Synthesis of Compressor Trees in High-Level Synthesis for Modern FPGAs
An O(bn 2 ) time algorithm for optimal buffer insertion with b buffer types
Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects
Robust VLSI circuit simulation techniques based on overlapped waveform relaxation
Synthesis of single-output space compactors for scan-based sequential circuits
QFP wiring problem-introduction and analytical considerations
DC Statistical Circuit Analysis for Bipolar IC's Using Parameter Correlations-An Experimental Example