yusuke1997/dblp-id-title huggingface dataset:
Improving the Quality of Delay-Based PUFs via Optical Proximity Correction
SILK: a simulated evolution router
MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design
Automated Nonintrusive Analysis of Electronic System Level Designs
A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs
Entropy-Directed Scheduling for FPGA High-Level Synthesis
Memory Built-in Self-Repair Planning Framework for RAMs in SoCs
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies
Multiobjective Coverage Optimization for 3-D Heterogeneous Wireless Sensor Networks
Simultaneous Area and Latency Optimization for Stochastic Circuits by D Flip-Flop Insertion
Adaptive mesh refinement for multilayer process simulation using the finite element method
On effective slack management in postscheduling phase
Corrigendum to "A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints"
Energy-Aware Clock-Frequency Assignment in Microprocessors and Memory Devices for Dynamic Voltage Scaling
An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs
Scope-Aware Useful Cache Block Calculation for Cache-Related Pre-Emption Delay Analysis With Set-Associative Data Caches
An improved model for solving the optimal placement for river-routing problem
Compact Geometric Feature Representation for Improved Capacitance Pattern-Matching in Parasitic Extraction
A globally and quadratically convergent algorithm for solving nonlinear resistive networks
The effects of unsymmetric matrix permutations and scalings in semiconductor device and circuit simulation
A two-dimensional resistance simulator using the boundary element method
A Three-Dimensional Photoresist Imaging Process Simulator for Strong Standing-Wave Effect Environment
Linking the Behavioral and Structural Domains of Representation for Digital System Design
ObSteiner: An Exact Algorithm for the Construction of Rectilinear Steiner Minimum Trees in the Presence of Complex Rectilinear Obstacles
Mapping Imperfect Loops to Coarse-Grained Reconfigurable Architectures
Ant Colony Optimizations for Resource- and Timing-Constrained Operation Scheduling
Vulnerability Detection of ICS Protocols via Cross-State Fuzzing
Using cone structures for circuit partitioning into FPGA packages
Equivalent Thermal Conductance Network (ETCN) Model for Domain Decomposition and Efficient Thermal Simulation of GaN HEMTs
Understanding and Exploiting the Full Potential of SSD Address Remapping
A Unified Parallel Framework for LUT Mapping and Logic Optimization
A Generic Data-Driven Nonparametric Framework for Variability Analysis of Integrated Circuits in Nanometer Technologies
Digital Foveation: An Energy-Aware Machine Vision Framework
Phase-Noise Analysis and Simulation of LC Oscillator-Based Injection-Locked Frequency Dividers
A hybrid device simulator that combines Monte Carlo and drift-diffusion analysis
The inversion algorithm for digital simulation
Variation-Aware Task and Communication Mapping for MPSoC Architecture
GRCA: a hybrid genetic algorithm for circuit ratio-cut partitioning
Mismatch simulation for layout sensitive parameters of IC components and devices
Design Automation of Meandered Interconnects for Stretchable Circuits
Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study
Traffic: a novel geometric algorithm for fast wire-optimized floorplanning
Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern Generation
ECG: Augmenting Embedded Operating System Fuzzing via LLM-Based Corpus Generation
FastCap: a multipole accelerated 3-D capacitance extraction program
Re-FeMAT: A Reconfigurable Multifunctional FeFET-Based Memory Architecture
Managing Laser Power in Silicon-Photonic NoC Through Cache and NoC Reconfiguration
Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks
Analytical Models for Three-Dimensional Ion Implantation Profiles in FinFETs
The Constant-Flow Patch Test -- A Unique Guideline for the Evaluation of Discretization Schemes for the Current Continuity Equations
Software Model Checking SystemC
A circuit-level simulation model of PNPN devices
Fast Positive-Real Balanced Truncation Via Quadratic Alternating Direction Implicit Iteration
Lite-Stereo: A Resource-Efficient Hardware Accelerator for Real-Time High-Quality Stereo Estimation Using Binary Neural Network
Interconnection analysis for standard cell layouts
Count-based BIST compaction schemes and aliasing probability computation
Simulation of the hydrodynamic device model on distributed memory parallel computers
Filling algorithms and analyses for layout density control
Bayesian Learning-Enhanced Embedded Memory Design With Automated Circuit Variant Generation
Large Data Transfer Optimization for Improved Robustness in Real-Time V2X-Communication
TRACER-fpga: a router for RAM-based FPGA's
Automated Transient Input Stimuli Generation for Analog Circuits
READY: Reliability- and Deadline-Aware Power-Budgeting for Heterogeneous Multicore Systems
Methodologies for Diagnosis of Unreachable States via Property Directed Reachability
Test Time Reduction of 3-D Stacked ICs Using Ternary Coded Simultaneous Bidirectional Signaling in Parallel Test Ports
Gradient Error Compensation in SC-MDACs
Indoor-Outdoor Energy Management for Wearable IoT Devices With Conformal Prediction and Rollout
A process and device model for GaAs MESFET technology: GATES
Technology Mapping and Cell Merger for Asynchronous Threshold Networks
Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques
XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference
Modeling Time-Dependent Elements for SPICE Transient Analyses
Generating Unified Platforms Using Multigranularity Domain DSE (MG-DmDSE) Exploiting Application Similarities
Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors
TOSCA: a simulator for switched-capacitor noise-shaping A/D converters
COMPACT: Flow-Based Computing on Nanoscale Crossbars With Minimal Semiperimeter and Maximum Dimension
Numerical simulation of optical devices
OPTIMA: A nonlinear model parameter extraction program with statistical confidence region algorithms
Sequential logic optimization for low power using input-disabling precomputation architectures
TritonRoute: The Open-Source Detailed Router
Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems
BitCluster: Fine-Grained Weight Quantization for Load-Balanced Bit-Serial Neural Network Accelerators
Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction
A Procedure for Placement of Standard-Cell VLSI Circuits
ROHOM: Requirement-Aware Online Hybrid On-Chip Memory Management for Multicore Systems
A discussion on the history of research in arithmetic andReed-Muller expressions
Nontree routing for reliability and yield improvement [IC layout]
Real-Time Data Retrieval With Multiple Availability Intervals in CPS Under Freshness Constraints
Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits
Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process
A method for area estimation of data-path in high level synthesis
Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation
PMC-3D: a parallel three-dimensional Monte Carlo semiconductor device simulator
Drain-to-Drain Abutment-Aware Detailed Placement Refinement for Power Staple Insertion Optimization
A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal
Comments on 'Asymptotic waveform evaluation for timing analysis'
Ultrafast Source Mask Optimization via Conditional Discrete Diffusion
Cambricon-G: A Polyvalent Energy-Efficient Accelerator for Dynamic Graph Neural Networks
Scheduling of microfluidic operations for reconfigurabletwo-dimensional electrowetting arrays
ApproxIt: A Quality Management Framework of Approximate Computing for Iterative Methods
A Unified Deep Reinforcement Learning Approach for Constructing Rectilinear and Octilinear Steiner Minimum Tree
Analysis of Deskew Signaling Via Adaptive Timing
ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips
Covering rectilinear polygons by rectangles
Simultaneous floor plan and buffer-block optimization
Dual-Threshold CAD Framework for Subthreshold Leakage Power Aware FPGAs
A comparison of strong and weak distributed transverse couplingbetween VLSI interconnects
ADS: Leveraging Approximate Data for Efficient Data Sanitization in SSDs
Security-Aware Obfuscated Priority Assignment for CAN FD Messages in Real-Time Parallel Automotive Applications
Toward Model Checking-Driven Fair Comparison of Dynamic Thermal Management Techniques Under Multithreaded Workloads
Intermittent OTA Code Update Framework for Tiny Energy Harvesting Devices
Logic Synthesis of Pass-Gate Logic Circuits With Emerging Ambipolar Technologies
Synthesis of Active-Mode Power-Gating Circuits
Applications of the Multi-Interval Chebyshev Collocation Method in RF Circuit Simulation
Reliable and Fault Diagnosis Architectures for Hardware and Software-Efficient Block Cipher KLEIN Benchmarked on FPGA
A Novel Design for Memristor-Based Multiplexer Via NOT-Material Implication
Bipartite Folding and Partitioning of a PLA
Patch-Based Data Management for Dual-Copy Buffers in RAID-Enabled SSDs
Fast and efficient parametric modeling of contact-to-substratecoupling
Measurements for structural logic synthesis optimizations
Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias
Modeling of the distributed gate RC effect in MOSFET's
A GPU-Enabled Level-Set Method for Mask Optimization
A Design Flow for Click-Based Asynchronous Circuits Design With Conventional EDA Tools
A General Framework to Perform the MAX/MIN Operations in Parameterized Statistical Timing Analysis Using Information Theoretic Concepts
Derivation and Refinement of Fan-Out Constraints to Generate Tests in Combinational Logic Circuits
Contention Cognizant Scheduling of Task Graphs on Shared Bus-Based Heterogeneous Platforms
Mining Patterns From Concurrent Execution Traces
A Blind Dynamic Fingerprinting Technique for Sequential Circuit Intellectual Property Protection
Massively parallel electromagnetic simulation for photolithographic applications
Testudo: Collaborative Intelligence for Latency-Critical Autonomous Systems
MOMC3D: A Novel Multiobjective Optimization Method With Mixed-Coding Strategy for Standard Cells in Chip 3-D Placement
Optimal floorplan area optimization
RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture
Bitmask-Based Code Compression for Embedded Systems
An efficient parallel critical path algorithm
Metal-Density-Driven Placement for CMP Variation and Routability
Scan-based transition test
Automatic synthesis of asynchronous circuits from high-level specifications
Fast exact minimization of BDD's
TPE-Det: A Tamper-Proof External Detector via Hardware Traces Analysis Against IoT Malware
A Physical and SPICE-Compatible Model for the MOS Depletion Device
Fine-Grained Access Management in Reconfigurable Scan Networks
Symbolic Verification of Cache Side-Channel Freedom
A Unified Scheduling Approach for Power and Resource Optimization With Multiple V dd or/and V th in High-Level Synthesis
Modeling of Minority Carrier Current in Heavily Doped Regions of Bipolar Regions
Secure and Efficient Architectures for Single Exponentiations in Finite Fields Suitable for High-Performance Cryptographic Applications
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems
New Approaches of Side-Channel Attacks Based on Chip Testing Methods
Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks
Optimized test application timing for AC test
A Post-Bond TSV Test Method Based on RGC Parameters Measurement
Signal-Division-Aware Analog Circuit Topology Synthesis Aided by Transfer Learning
MOZART: a concurrent multilevel simulator
Enhancing random-pattern coverage of programmable logic arrays via masking technique
Temperature- and Voltage-Aware Timing Analysis
Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning
A nonequilibrium one-dimensional quantum-mechanical simulation for AlGaAs/GaAs HEMT structures
Effective computer methods for the calculation of Rademacher-Walsh spectrum for completely and incompletely specified Boolean functions
A unified approach for fault tolerance and dynamic power management in fixed-priority real-time embedded systems
FSPDA: A Full Sequence Program Data Allocation Scheme for Boosting 3-D nand Flash Read Performance
Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip
NebulaFL: Self-Organizing Efficient Multilayer Federated Learning Framework With Adaptive Load Tuning in Heterogeneous Edge Systems
Conditional Differential Coefficients Method for the Realization of Powers-of-Two FIR Filter
A neural network design for circuit partitioning
Minimum-Via Topological Routing
Power-Efficient Mapping of Large Applications on Modern Heterogeneous FPGAs
BonnPlace Legalization: Minimizing Movement by Iterative Augmentation
On the Solution of Coupled System of PDE by a Multigrid Method
Hierarchical test generation using precomputed tests for modules
Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree
A high-performance data path for synthesizing DSP kernels
Fast Methods for Switch-Level Verification of MOS Circuits
Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications
Multilevel logic synthesis of symmetric switching functions
Time stability of Monte Carlo device simulation
Energy Optimization for Many-Core Platforms: Communication and PVT Aware Voltage-Island Formation and Voltage Selection Algorithm
Constrained floorplanning using network flows
Detection and Diagnosis of Single Faults in Quantum Circuits
PABTEC: Passivity-Preserving Balanced Truncation for Electrical Circuits
On fault equivalence, fault dominance, and incompletely specified test sets
Zram Instance Pool Framework for Adaptive Memory Compression in Resource-Sensitive Embedded Operating Systems
Accurate Prediction of Random Telegraph Noise Effects in SRAMs and DRAMs
Principles of substrate crosstalk generation in CMOS circuits
Using Error Modes Aware LDPC to Improve Decoding Performance of 3-D TLC NAND Flash
Hardware/Software Co-Exploration of Neural Architectures
A phase assignment method for virtual-wire-based hardware emulation
OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions
Maze routing with buffer insertion under transition time constraints
FPGA Acceleration for 3-D Low-Dose Tomographic Reconstruction
Assertion Ranking Using RTL Source Code Analysis
Algorithms and models for cellular based topography simulation
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing
Predictive Formulae for OPC With Applications to Lithography-Friendly Routing
An LDE-Aware g m /I D -Based Hybrid Sizing Method for Analog Integrated Circuits
Steiner tree optimization for buffers, blockages, and bays
Identifying Reliability-Critical Primary Inputs of Combinational Circuits Based on the Model of Gate-Sensitive Attributes
A detailed router for field-programmable gate arrays
Probabilistic Wire Resistance Degradation Due to Electromigration in Power Grids
A design of programmable logic arrays with random pattern-testability
On the complexity of minimizing the OBDD size for incompletely specified functions
Combating Enhanced Thermal Covert Channel in Multi-/Many-Core Systems With Channel-Aware Jamming
Multitarget Sample Preparation Using MEDA Biochips
Bursting Firings in Memristive Hopfield Neural Network With Image Encryption and Hardware Implementation
Optimal design of macrocells for low power and high speed
Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands
Reliable 3-D Clock-Tree Synthesis Considering Nonlinear Capacitive TSV Model With Electrical-Thermal-Mechanical Coupling
Using simulation and satisfiability to compute flexibilities in Boolean networks
The testability-preserving concurrent decomposition and factorization of Boolean expressions
Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables
On extending slicing floorplan to handle L/T-shaped modules andabutment constraints
Parallel waveform-Newton algorithms for circuit simulation
PUF-FSM: A Controlled Strong PUF
BLADES: an artificial intelligence approach to analog circuit design
On Random Dynamic Voltage Scaling for Internet-of-Things: A Game-Theoretic Approach
Enhancing the Reliability of MEDA Biochips Using IJTAG and Wear Leveling
Enhancing the Utilization of Processing Elements in Spatial Deep Neural Network Accelerators
An efficient graph representation for arithmetic circuitverification
Recursive Boolean Formula Minimization Algorithms for Implication Logic
Adaptive Board-Level Functional Fault Diagnosis Using Incremental Decision Trees
On using signature registers as pseudorandom pattern generators in built-in self-testing
Novel Partitioning-Based Approach for Electromigration Assessment With Neural Networks
Enhancing Delay-Driven LUT Mapping With Boolean Decomposition
Efficient per-nonlinearity distortion analysis for analog and RF circuits
Energy-Efficient DNN Inference on Approximate Accelerators Through Formal Property Exploration
A simple theorem prover based on symbolic trajectory evaluation and BDD's
PDG: A Prefetcher for Dynamic Graph Updating
Interconnect thermal modeling for accurate simulation of circuittiming and reliability
Dynamic Supply Noise Aware Timing Analysis With JIT Machine Learning Integration
Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations
3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations
An Analytical Model for Hot Carrier Induced Long-Term Degradation in Power Amplifiers
Low-Energy Standby-Sparing for Hard Real-Time Systems
Ant Colony Optimization-Based Fault-Aware Routing in Mesh-Based Network-on-Chip Systems
A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment
Temperature and supply Voltage aware performance and power modeling at microarchitecture level
Native Simulation of MPSoC Using Hardware-Assisted Virtualization
Probabilistic analysis and algorithms for reconfiguration of memory arrays
Formal Vulnerability Analysis of Security Components
Automating Technology Relative Logic Synthesis and Module Selection
Applications of one-dimensional cellular automata and linear feedback shift registers for pseudo-exhaustive testing
F-LEMMA: Fast Learning-Based Energy Management for Multi-/Many-Core Processors
Learning-Based Quality Management for Approximate Communication in Network-on-Chips
Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs
Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences
Application-Specific Wear Leveling for Extending Lifetime of Phase Change Memory in Embedded Systems
A Database-Driven VLSI Design System
Efficient event-driven simulation by exploiting the output observability of gate clusters
A Fast Hierarchical Quadratic Placement Algorithm
Experimental evaluation of testability measures for test generation (logic circuits)
Efficient Design Optimization for Diffractive Deep Neural Networks
A fast three-dimensional process simulator OPUS/3D with access to two-dimensional simulation results
Gate-Sizing-Based Single V dd Test for Bridge Defects in Multivoltage Designs
An edge-based heuristic for Steiner routing
An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)
The fault dropping problem in concurrent event-driven simulation
Fast Thermal Simulation of FinFET Circuits Based on a Multiblock Reduced-Order Model
Test generation and concurrent error detection in current-mode A/D converters
Efficient net extraction for restricted orientation designs [VLSI layout]
Board-Level Functional Fault Diagnosis Using Artificial Neural Networks, Support-Vector Machines, and Weighted-Majority Voting
Two methods to improve the performance of Monte Carlo simulations of ion implantation in amorphous targets
Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption
Dynamic frequency scaling with buffer insertion for mixed workloads
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation
WARD: Wear Aware RAID Design Within SSDs
RE-Specter: Examining the Architectural Features of Configurable CNN With Power Side-Channel
On Reducing Scan Shift Activity at RTL
Error bounds for capacitance extraction via window techniques
Bridging the Pragmatic Gaps for Mixed-Criticality Systems in the Automotive Industry
EI-NK: A Robust Exponential Integrator Method With Singularity Removal and Newton-Raphson Iterations for Transient Nonlinear Circuit Simulation
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems
A cost-effective design for testability: clock line control and test generation using selective clocking
Formulating SoC test scheduling as a network transportation problem
Low-pass filter for computing the transition density in digital circuits
Unsupervised Two-Stage Root-Cause Analysis for Integrated Systems
New Targets for Diagnostic Test Generation
Verification of relations between synchronous machines
Parameters for point-defect diffusion and recombination
Efficient reconfiguration algorithms for degradable VLSI/WSI arrays
Analysis and methodology for multiple-fault diagnosis
Fault Group Pattern Matching With Efficient Early Termination for High-Speed Redundancy Analysis
Experience of Data Analytics in EDA and Test - Principles, Promises, and Challenges
Statistical Criticality Computation Using the Circuit Delay
Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints
Scan to Nonscan Conversion via Test Cube Analysis
EDA challenges facing future microprocessor design
FSSA: Fast Steady-State Algorithm for the Analysis of Mixed Analog/Digital Circuits
An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns
Gated clock routing for low-power microprocessor design
vFlash: Virtualized Flash for Optimizing the I/O Performance in Mobile Devices
BSIM plus: an advanced SPICE model for submicron MOS VLSI circuits
On the diagnostic properties of linear feedback shift registers
Fault Tolerant Network on Chip Switching With Graceful Performance Degradation
Markovian analysis of large finite state machines
An efficient algorithm for performance-optimal FPGA technology mapping with retiming
Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits
TeMACLE: A Technology Mapping-Aware Area-Efficient Standard Cell Library Extension Framework
Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures
Optimality Study of Logic Synthesis for LUT-Based FPGAs
Accelerating On-Device DNN Training Workloads via Runtime Convergence Monitor
Efficient Pipelining of Synchronous Dataflow Graphs Via Graph Conversion
Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs
DRAM Bender: An Extensible and Versatile FPGA-Based Infrastructure to Easily Test State-of-the-Art DRAM Chips
ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis
LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator
An Effective Formulation of Coupled Electromagnetic-TCAD Simulation for Extremely High Frequency Onward