yusuke1997/dblp-id-title huggingface dataset:
Stability test of multidimensional discrete-time systems via sum-of-squares decomposition
Radix-3, times, 3 Algorithm for The 2-D Discrete Hartley Transform
Design and Verification of a Switchable Opamp for Switched-Capacitor Integrators
Design of Observers for Positive Systems With Delayed Input and Output Information
Averaging technique in flash analog-to-digital converters
Effect of Clock Duty-Cycle Error on Two-Channel Interleaved ΔΣ DACs
Two-Stage Neural Observer for Mechanical Systems
A Self-Resonant Two-Coil Wireless Power Transfer System Using Open Bifilar Coils
High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm
Chaos-Based Turbo Systems in Fading Channels
A Two-Parameter Calibration Technique Tracking Temperature Variations for Current Source Mismatch
Domino-Logic-Based ADC for Digital Synthesis
An 18.7-Gb/s 60-GHz OOK Demodulator in 65-nm CMOS for Wireless Network-on-Chip
A Capacitance-to-Frequency Converter With On-Chip Passivated Microelectrodes for Bacteria Detection in Saline Buffers Up to 575 MHz
A High Performance and Energy-Efficient Cold Data Eviction Algorithm for 3D-TSV Hybrid ReRAM/MLC NAND SSD
Compensation Method for Multistage Opamps With High Capacitive Load Using Negative Capacitance
Stabilization of Nonlinear Systems via Periodically Intermittent Control
An Improved Gauss-Seidel Algorithm and Its Efficient Architecture for Massive MIMO Systems
Optimal Polygonal L 1 Linearization and Fast Interpolation of Nonlinear Systems
A Frequency Model of a Continuously Driven Clocked CMOS Comparator
Sharp Corner/Edge Recognition in Domestic Environments Using RGB-D Camera Systems
100-MHz Low-Phase-Noise Microprocessor Temperature-Compensated Crystal Oscillator
A Time-Interleaved DeltaSigma-DAC Architecture Clocked at the Nyquist Rate
Recombination of Envelope and Phase Paths in Wideband Polar Transmitters
Frequency-Shift Induced by Colored Noise in Nonlinear Oscillators
Optimum nMOS/pMOS Imbalance for Energy Efficient Digital Circuits
A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the Presence of Variations
A Low Overhead, Within-a-Cycle Adaptive Clock Stretching Circuit With Wide Operating Range in 40-nm CMOS
A New DAC Mismatch Shaping Technique for Sigma-Delta Modulators
The Lin-Bose Problem
A Low-Power Deep Neural Network Online Learning Processor for Real-Time Object Tracking Application
Efficiency Optimization for Burst-Mode Multilevel Radio Frequency Transmitters
Comparison of Bandpass SigmaDelta Modulator Coding Efficiency With a Periodic Signal Model
Analysis and Design of an 8.5-Gb/s/Link Multi-Drop Bus Using Energy-Equipartitioned Transmission Line Couplers
Opportunities and Challenges of Tunnel FETs
An 8-bit 120-MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification
A 92%-Efficiency Battery Powered Hybrid DC-DC Converter for IoT Applications
An Open Loop Digitally Controlled Hybrid Supply Modulator Achieving High Efficiency for Envelope Tracking With Baseband up to 200-MHz
Global Stabilization of Switched Feedforward Nonlinear Time-Delay Systems Under Asynchronous Switching
HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning
A 9-Bit 10-MHz 28-µW SAR ADC Using Tapered Bit Periods and a Partially Interdigitated DAC
An Advanced Bootstrap Circuit for High Frequency, High Area-Efficiency and Low EMI Buck Converter
Improved Digital Background Calibration of Time-Interleaved Pipeline A/D Converters
On Brayton and Moser's missing stability theorem
Tuning of Multiple Parameters With a BIST System
Stability Analysis of AC Microgrids With Constant Power Loads Based on Popov's Absolute Stability Criterion
A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling
High-Efficiency Millimeter-Wave Energy-Harvesting Systems With Milliwatt-Level Output Power
Noise Analysis and Minimization in Bang-Bang Digital PLLs
Wordlength Optimization of Linear Time-Invariant Systems With Multiple Outputs Using Geometric Programming
A Variation-Tolerant MRAM-Backed-SRAM Cell for a Nonvolatile Dynamically Reconfigurable FPGA
Blind Frequency-Selective I/Q Mismatch Compensation Using Subband Processing
Equilibrium analysis of cellular neural networks
Jump resonance: a feedback viewpoint and adaptive circuit solution for low-power active analog filters
Analog Frontend for Tribo-Current-Based Fly-Height Sensor for Magnetic Hard Disk Drive
An Area-Efficient 8-Bit Single-Ended ADC With Extended Input Voltage Range
Tuning Range Extension of a Transformer-Based Oscillator Through Common-Mode Colpitts Resonance
Adjacent Channel Interference Cancellation in FDM Transmissions
Phase-Separated DCSK: A Simple Delay-Component-Free Solution for Chaotic Communications
WHT and Matrix Decomposition-Based Approximated IDCT Architecture for HEVC
A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth
Phase Coherent Frequency Hopping in Direct Digital Synthesizers and Phase Locked Loops
Characterization Techniques for High Speed Oversampled Data Converters
Joint Detection and Decoding for MIMO Systems Using Convolutional Codes: Algorithm and VLSI Architecture
Event-Triggered Master-Slave Synchronization With Sampled-Data Communication
Switched Current Integrating Sampler for Time Interleaved ADCs
TSK-based decision feedback equalizer using an evolutionary algorithm applied to QAM communication systems
A Sub-1ppm/°C Current-Mode CMOS Bandgap Reference With Piecewise Curvature Compensation
Analysis of Class-E Based RF Power Amplifiers Using Harmonic Modeling
A Compressed Sensing Analog-to-Information Converter With Edge-Triggered SAR ADC Core
Solving Large-Scale Hybrid Circuit-Antenna Problems
A Method of Creating the High-Voltage Circuit Model of Metal-Oxide Varistor for the Simulation of Square Pulse Forming
A 0.7-2.5 GHz, 61% EIRP System Efficiency, Four-Element MIMO TX System Exploiting Integrated Power-Relaxed Power Amplifiers and an Analog Spatial De-Interleaver
Harmonic Signal Rejection Schemes of Polyphase Downconverters
Interleaved Buck Converters Based on Winner-Take-All Switching
A blind source separation based method for speech encryption
Miniaturized Resonator and Bandpass Filter for Silicon-Based Monolithic Microwave and Millimeter-Wave Integrated Circuits
A 16-Core Processor With Shared-Memory and Message-Passing Communications
A Low-Overhead Interference Canceller for High-Mobility STBC-OFDM Systems
The tiling phenomenon in ΣΔ modulation
Distortion Analysis Using Volterra Series and Linearization Technique of Nano-Scale Bulk-Driven CMOS RF Amplifier
Remarks on n -D Polynomial Matrix Factorization Problems
Output Tracking Control for Fractional-Order Positive Switched Systems With Input Time Delay
Global Uniform Synchronization With Estimated Error Under Transmission Channel Noise
A neural network with O(N) neurons for ranking N numbers in O(1/N) time
Observer-Based Control of 2-D Markov Jump Systems
A Packaged Noise-Canceling High-Gain Wideband Low Noise Amplifier
Optimal Design of All-Pass Variable Fractional-Delay Digital Filters
Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression
Synchronization Conditions for Multiagent Systems With Intrinsic Nonlinear Dynamics
Co-Design of Matching Sub-Networks to Realize Broadband Symmetrical Doherty With Configurable Back-Off Region
A Reachability-Based Method for Large-Signal Behavior Verification of DC-DC Converters
Charge Balance Analysis and State Transition Analysis of Hysteretic Voltage Mode Switching Converters
Dynamic Load Modulation With a Reconfigurable Matching Network for Efficiency Improvement Under Antenna Mismatch
Design of Two-Dimensional Zero-Phase FIR Digital Filter by McClellan Transformation and Interval Global Optimization
A High-Performance and Energy-Efficient TCAM Design for IP-Address Lookup
A statistical analysis of the affine projection algorithm for unity step size and autoregressive inputs
An Ultra-Low-Power 4.7mA-Rx 22.4mA-Tx Transceiver Circuit in 65-nm CMOS for M2M Satellite Communications
A 2.2-GHz Configurable Direct Digital Frequency Synthesizer Based on LUT and Rotation
Low-voltage CMOS circuits for analog iterative decoders
Realizations of a Special Class of Admittances With Strictly Lower Complexity Than Canonical Forms
Full 360 circ Vector-Sum Phase-Shifter for Microwave System Applications
A High-Efficiency Low-Profile Zero-Voltage Transition Synchronous Non-Inverting Buck-Boost Converter With Auxiliary-Component Sharing
Analysis and Design for a Novel Single-Stage High Power Factor Correction Diagonal Half-Bridge Forward AC-DC Converter
Relationship Between Smith Normal Form of Periodicity Matrices and Sampling of Two-Dimensional Discrete Frequency Distributions With Tiling Capability
An On-Chip Transformer-Based Self-Startup Hybrid SIDITO Converter for Thermoelectric Energy Harvesting
A Circuit Model of Hysteresis and Creep
Improved approximate QR-LS algorithms for adaptive filtering
A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes
A 3x blind ADC-based CDR for a 20 dB loss channel
A Low-Power 2.4-GHz Receiver Front End With a Lateral Current-Reusing Technique
Memristor Crossbar for Adaptive Synchronization
A Frequency Synchronization Method for a Self-Oscillating PWM Signal Generator
A Sub-10 mV Power Converter With Fully Integrated Self-Start, MPPT, and ZCS Control for Thermoelectric Energy Harvesting
A 20-GS/s 5-b SiGe ADC for 40-Gb/s Coherent Optical Links
Receiver channel with resonance-based timing detection for a laser range finder
Critical stability constraints for discrete-time linear systems
Delay-Dependent Exponential Stability of Neural Networks With Variable Delay: An LMI Approach
Decision Feedback Equalizers Using the Back-Gate Feedback Technique
An Adaptive ELD Compensation Technique Using a Predictive Comparator
Modeling of a MOS Ultralow Voltage Astable Multivibrator for Energy Harvesting
Converting a Three-Stage Pseudoclass-AB Amplifier to a True-Class-AB Amplifier
Cascaded Form Sparse FIR Filter Design
A 65-81 GHz CMOS Dual-Mode VCO Using High Quality Factor Transformer-Based Inductors
Low-Power and Low-Phase-Noise $G_{m}$ -Enhanced Current-Reuse Differential Colpitts VCO
An Ultralow-Power Low-Noise CMOS Biopotential Amplifier for Neural Recording
Enhanced Stability Caused by a One-Cycle Delay in a Digital Current-Mode Controlled Buck Converter
Efficient Uncertainty Quantification for the Periodic Steady State of Forced and Autonomous Circuits
A Time-Efficient Automatic Circuit Approximation Method
Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter
Exploiting the high-frequency performance of low-voltage low-power SC filters
Double-Binary Circular Turbo Decoding Based on Border Metric Encoding
Parameter Derivation of Type-2 Discrete-Time Phase-Locked Loops Containing Feedback Delays
On the Implicit Anti-Aliasing Feature of Continuous-Time Cascaded Sigma-Delta Modulators
An Equalizer Adaptation Algorithm to Reduce Jitter in Binary Receivers
Theoretical Analysis of Noise Figure for Modulated Wideband Converter
Investigation of phase noise of ring oscillators with time-varying current and noise sources by time-scaling thermal noise
Analyzing the Effect of Clock Jitter on Self-Oscillating Sigma Delta Modulators
Energy-Efficient Hadamard-Based SATD Hardware Architectures Through Calculation Reuse
Performance Analysis of Nonlinear-Predictive-Filter-Based Chaotic Synchronization
A Two-Stage Fully Differential Inverter-Based Self-Biased CMOS Amplifier With High Efficiency
Wide Range, Process and Temperature Compensated Voltage Controlled Current Source
A Highly Compact 2.4-GHz Passive 6-bit Phase Shifter With Ambidextrous Quadrant Selector
An Ultra-Wide-Band 0.4-10-GHz LNA in 0.18-μm CMOS
Optimizing Hardware Accelerated General Matrix-Matrix Multiplication for CNNs on FPGAs
A Compact High-Performance Programmable-Gain Analog Front End for HomePlug AV2 Communication in 0.18- $\mu \text{m}$ CMOS
Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns
A Fully-Integrated Wireless Bondwire Accelerometer With Closed-loop Readout Architecture
A High-Speed DSP Engine for First-Order Hold Digital Phase Modulation in 28-nm CMOS
An Inverted Ring Oscillator Noise-Shaping Time-to-Digital Converter With In-Band Noise Reduction and Coherent Noise Cancellation
A Distortion-Compensated Charge Transfer Amplifier for a 1.66-MHz Cyclic Pipeline ADC
Fault Tolerance in Transform-Domain Adaptive Filters Operating With Real-Valued Signals
NAND Flash Memory/ReRAM Hybrid Unified Solid-State-Storage Architecture
A New Model of Frequency Delay in Power Systems
Digital Predistortion Parameter Identification for RF Power Amplifiers Using Real-Valued Output Data
Decision Tree and Random Forest Implementations for Fast Filtering of Sensor Data
A Scalable Low-Power Reconfigurable Accelerator for Action-Dependent Heuristic Dynamic Programming
Periodic Event-Triggered Consensus With Quantization
A 12 mV Input, 90.8% Peak Efficiency CRM Boost Converter With a Sub-Threshold Startup Voltage for TEG Energy Harvesting
A Flexible and Customizable Architecture for the Relaxation Labeling Algorithm
Focal-Plane Spatially Oversampling CMOS Image Compression Sensor
A Low-Power Incremental Delta-Sigma ADC for CMOS Image Sensors
A Wireless-Powered IR-UWB Transmitter for Long-Range Passive RFID Tags in 90-nm CMOS
Multicarrier Faster-Than-Nyquist Transceivers: Hardware Architecture and Performance Analysis
Online Learning for Multimodal Data Fusion With Application to Object Recognition
Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM
Optimal Coefficient Quantization in Optimal-NTF Δ!Σ Modulators
Feedback control of limit cycles: a switching control strategy based on nonsmooth bifurcation theory
Compact Extended Industrial Range CMOS Current References
Design of a Low-Power Coprocessor for Mid-Size Vocabulary Speech Recognition Systems
A New Capacitance Measuring System for Capacitive Sensor for Moving Target Detection
A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise
Two new canonic single-CFOA oscillators with single resistor controls
Corrections to "LMI Approach for Global Periodicity of Neural Networks With Time-Varying Delays"
Nanopower CMOS Relaxation Oscillators With Sub-100 ppm°C Temperature Coefficient
Analysis and Modeling of the Phase Detector Hysteresis in Bang-Bang PLLs
Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor
Comprehensive Analysis of Distortion in the Passive FET Sample-and-Hold Circuit
Event-Triggered Fault Detection and Isolation of Discrete-Time Systems Based on Geometric Technique
Sequential Correlated Level Shifting: A Switched-Capacitor Approach for High-Accuracy Systems
Near Field Resonator Isolation System: Theory to Implementation
Minimum description length criterion for modeling of chaotic attractors with multilayer perceptron networks
Correction to Section V-B of "Contraction Theory and the Master Stability Function: Linking Two Approaches to Study Synchronization in Complex Networks"
Efficient Digit-Serial KA-Based Multiplier Over Binary Extension Fields Using Block Recombination Approach
CMOS implementation of nonlinear spectral-line timing recovery in digital data-communication systems
Robust Output Regulation in Discrete-Time Singular Systems With Actuator Saturation and Uncertainties
Improved design of digital fractional-order differentiators using fractional sample delay
Efficient FPGA Implementation of Address Generator for WiMAX Deinterleaver
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network
Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction
A Low-Power Digit-Based Reconfigurable FIR Filter
VLSI Designs for Joint Channel Estimation and Data Detection in Large SIMO Wireless Systems
Two-Channel Quincunx QMF Banks Using Two-Dimensional Digital Allpass Filters
Fall Detection Using Standoff Radar-Based Sensing and Deep Convolutional Neural Network
A Power-Scalable Channel-Adaptive Wireless Receiver Based on Built-In Orthogonally Tunable LNA
A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel
A Digital-Based Analog Differential Circuit
Sigma-Delta Modulators: Tutorial Overview, Design Guide, and State-of-the-Art Survey
Fast Adaptive Finite-Time Voltage Regulation Control Algorithm for a Buck Converter System
Lattice-Based Cryptoprocessor for CCA-Secure Identity-Based Encryption
FIR, Allpass, and IIR Variable Fractional Delay Digital Filter Design
A new design approach for solving linear quadratic nash games of multiparameter singularly perturbed systems
Feedforward Interference Cancellation in Radio Receiver Front-Ends
Model Reduction Via Limited Frequency Interval Gramians
Fundamental Energy Limits of Digital Phased Arrays
Bit-Error-Rate Estimation for High-Speed Serial Links
Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator
A Novel Memristor-Based Circuit Implementation of Full-Function Pavlov Associative Memory Accorded With Biological Feature
Matching the Power, Voltage, and Size of Biological Systems: A nW-Scale, 0.023-mm 3 Pulsed 33-GHz Radio Transmitter Operating From a 5 kT/q-Supply Voltage
A Single-Reference Parasitic-Matching Sensing Circuit for 3-D Cross Point PCM
An Improved H INFINITY Filter Design for Systems With Time-Varying Interval Delay
A prediction fusion method for reconstructing spatial temporal dynamics using support vector machines
Design-Oriented Analysis of Circuits With Equality Constraints
Guest Editorial Special Issue on the 2020 ISICAS: A CAS Journal Track Symposium
The First Ever Real Bistable Memristors - Part I: Theoretical Insights on Local Fading Memory
On the Error-Free Realization of a Scaled DCT Algorithm and Its VLSI Implementation
Speed-Up Technique by Pre-Charging Load Capacitor in a SC Residue Circuit
Ramp Noise Projection in CMOS Image Sensor Single-Slope ADCs
A Dual-Layer Method for Transient and Permanent Error Co-Management in NoC Links
Low Noise ZVS Switch Sharing Multichannel Switching Amplifier for Magnetic Bearing Applications
A Low-Phase-Noise CMOS Quadrature Voltage-Controlled Oscillator Using a Self-Injection-Coupled Technique
Self-Tuning Electrostatic Energy-Harvester IC
A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters
A necessary condition for power flow Jacobian singularity based on branch complex flows
Quadrature Sampling for Built-In Analog/RF IC Spectrum Test
Low-Blind-Period Differential Sampler for High-Speed Serial Link Receivers
An Implementation of Fast-Locking and Wide-Range 11-bit Reversible SAR DLL
Cryptanalyzing an Encryption Scheme Based on Blind Source Separation
A 220-MHz Bondwire-Based Fully-Integrated KY Converter With Fast Transient Response Under DCM Operation
Improved Spatiotemporal Noise Reduction for Very Low-Light Environments
A Systematic Methodology for Constructing Hyperchaotic Systems With Multiple Positive Lyapunov Exponents and Circuit Implementation
Performance Analysis of the CS-DCSK/BPSK Communication System
Novel allpass filter configuration employing single OTRA
Accelerated Dual-Path Asynchronous Circuit
A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling
Tunable CMOS Delay Gate With Improved Matching Properties
Two High-Performance Adaptive Filter Implementation Schemes Using Distributed Arithmetic
Dual-Stacked Current Recycling Linear Regulators With 48% Power Saving for Biomedical Implants
A Resistorless CMOS Voltage Reference Based on Mutual Compensation of V T and V TH
Near Optimal Control Based on the Tensor-Product Technique
A 0.5 V 10-bit 3 MS/s SAR ADC With Adaptive-Reset Switching Scheme and Near-Threshold Voltage-Optimized Design Technique
Robustness of Interdependent Power Grids and Communication Networks: A Complex Network Perspective
A Direct Fast Feedback Current Driver Using an Inverting Amplifier for High-Quality AMOLED Displays
Direct Synthesis Technique for Dual-Passband Filters: Superposition Approach
Design and Multiplierless Realization of Maximally Flat Sharpened-CIC Compensators
A 3.54 nJ/bit-RX, 0.671 nJ/bit-TX Burst Mode Super-Regenerative UWB Transceiver in 0.18-µm CMOS
On the l 2 - l ∞ and H ∞ Performances of the Continuous-Time Deadbeat H 2 FIR Filter
High Average-Efficiency Multimode RF Transmitter Using a Hybrid Quadrature Polar Modulator
Nearly Exact Analytical Formulation of the DNL Yield of the Digital-to-Analog Converter
System-Level Optimization of Switched-Capacitor VRM and Core for Sub/Near-V t Computing
Stability Test for Complex Matrices Over the Complex Unit Circumference via LMIs and Applications in 2D Systems
Low Overhead Architectures for OMP Compressive Sensing Reconstruction Algorithm
Analysis of frequency divider RTD circuits
A regulated body-driven CMOS current mirror for low-voltage applications
Performance optimization of critical nets through active shielding
Analysis and Design of Class DE Amplifier With Nonlinear Shunt Capacitances
A New Simultaneous Multislope ADC Architecture for Array Implementations
A Low-Error Energy-Efficient Fixed-Width Booth Multiplier With Sign-Digit-Based Conditional Probability Estimation
Embedded Analog Nonvolatile Memory With Bidirectional and Linear Programmability
A 800 Mbps and 12.37 ps Jitter Bidirectional Mixed-Voltage I/O Buffer With Dual-Path Gate-Tracking Circuit
Adaptive Observers With Persistency of Excitation for Synchronization of Chaotic Systems
Bifurcation Analysis on a Multimachine Power System Model
Linear Time-Variant Modeling and Analysis of All-Digital Phase-Locked Loops
Class-E 2 DC-DC Converter With Basic Class-E Inverter and Class-E ZCS Rectifier for Capacitive Power Transfer
Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands
Median Filter Architecture by Accumulative Parallel Counters
Current-Based Resonant Power Delivery With Multi-Cycle Switching for Extended-Range Inductive Power Transmission
Robust MIMO FIR Filter Design With Time-Domain Envelope Constraints via Pi -Sharing Theory
A Sub-µW/Channel, 16-Channel Seizure Detection and Signal Acquisition SoC Based on Multichannel Compressive Sensing
An Analog Front-End Chip With Self-Calibrated Input Impedance for Monitoring of Biosignals via Dry Electrode-Skin Interfaces
Mismatch Shaping Techniques to Linearize Charge Pump Errors in Fractional-N PLLs
Time-Domain 1/f Noise Analysis of a Charge-Redistribution Track-and-Hold Circuit
A Low-Power Parallel Architecture for Linear Feedback Shift Registers
Stability Analysis of Delay Neural Networks With Impulsive Effects
A Systolic Array Based GTD Processor With a Parallel Algorithm
An SRAM-Based PUF With a Capacitive Digital Preselection for a 1E-9 Key Error Probability
Event-Triggered Control for Consensus Problem in Multi-Agent Systems With Quantized Relative State Measurements and External Disturbance
Robustness Assessment and Enhancement of Power Grids From a Complex Network's Perspective Using Decision Trees
Architecture and FPGA Design of Dichotomous Coordinate Descent Algorithms
3-D IIR filtering using decimated DFT-polyphase filter bank structures
Analysis and Design of a Core-Size-Scalable Low Phase Noise LC-VCO for Multi-Standard Cellular Transceivers
A Counterexample to " Positive Realness Preserving Model Reduction With H infty Norm Error Bounds"
Fully Parallel Circular-Shift Rotation Network for Communication Standards
Interpreting Frame Transformations in AC Systems as Diagonalization of Harmonic Transfer Functions
A Spectral-Correlation-Based Blind Calibration Method for Time-Interleaved ADCs
Design Issues and Implementations for Floating-Point Divide-Add Fused
Revision and improvement of a Theorem for robust synchronization of nonidentical Lur'e systems
Second-Order Balanced Truncation for Passive-Order Reduction of RLCK Circuits
A 25-Gb/s 270-mW Time-to-Digital Converter-Based 8× Oversampling Input-Delayed Data-Receiver in 45-nm SOI CMOS
Fixed-point error analysis of CORDIC processor based on the variance propagation formula