yusuke1997/dblp-id-title huggingface dataset:
A fully integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection
Extension of the common-mode range of bipolar input stages beyond the supply rails of operational amplifiers and comparators
A quad-band 8PSK/GMSK polar transceiver
A single-chip universal digital satellite receiver with 480-MHz IF input
A Time-Interleaved Resonant Voltage Mode Wireless Power Receiver With Delay-Based Tracking Loops for Implantable Medical Devices
A 9-bit, 14 μW and 0.06 mm 2 Pulse Position Modulation ADC in 90 nm Digital CMOS
Performance of CMOS differential circuits
A 1.7-3.6 GHz 20 MHz-Bandwidth Channel-Selection N-Path Passive-LNA Using a Switched-Capacitor-Transformer Network Achieving 23.5 dBm OB-IIP₃ and 3.4-4.8 dB NF
A digital interpolation filter chip with 32 programmable coefficients for 80 MHz sampling frequency
Introduction to the Special Issue on the IEEE 2007 Custom Integrated Circuits Conference
A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB
Analysis and design of an optimally coupled 5-GHz quadrature LC oscillator
Ultra-Low-Voltage 20-GHz Frequency Dividers Using Transformer Feedback in 0.18-µm CMOS Process
SLiMDO: A Single-Link Multi-Domain-Output Isolated DC-DC Converter With Passive Magnetic Flux Sharing for Local Energy Distribution and Rx Behavior Sensing-Based Global Power Modulation
A 0.24-μm 2.0-V 1T1MTJ 16-kb nonvolatile magnetoresistance RAM with self-reference sensing scheme
A 1 W 104 dB SNR Filter-Less Fully-Digital Open-Loop Class D Audio Amplifier With EMI Reduction
Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS
Energy consumption modeling and optimization for SRAM's
A Single-Ended Fully Integrated SiGe 77/79 GHz Receiver for Automotive Radar
Effects of substrate resistances on LNA performance and a bondpad structure for reducing the effects in a silicon bipolar technology
Low-Power CMOS Vision Sensor for Gaussian Pyramid Extraction
A Vocabulary Forest Object Matching Processor With 2.07 M-Vector/s Throughput and 13.3 nJ/Vector Per-Vector Energy for Full-HD 60 fps Video Object Recognition
250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS
Comments on 'A compact thermal noise model for the investigation of soft error rates in MOS VLSI digital circuits'
A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS
A 28-GHz SiGe up-conversion mixer using a series-connected triplet for higher dynamic range and improved IF port return loss
A flexible gate array architecture for high-speed and high-density applications
Speed and power scaling of SRAM's
An ultralow-power UHF transceiver integrated in a standard digital CMOS process: architecture and receiver
Merged CMOS/bipolar current switch logic (MCSL)
Introduction to the Special Section on the 2016 Asian Solid-State Circuits Conference (A-SSCC 2016)
A Time-Resolved, Low-Noise Single-Photon Image Sensor Fabricated in Deep-Submicron CMOS Technology
A High-Voltage-Compliant 86% Peak Efficiency Current-Mode Stimulator With Dynamic Voltage Supply for Implantable Medical Devices
A Configurable 12-237 kS/s 12.8 mW Sparse-Approximation Engine for Mobile Data Aggregation of Compressively Sampled Physiological Signals
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI
5T SRAM With Asymmetric Sizing for Improved Read Stability
A temperature-stabilized SOI voltage reference based on threshold voltage difference between enhancement and depletion NMOSFET's
Reducing MOSFET 1/f noise and power consumption by switched biasing
A Physical Unclonable Function With Bit Error Rate × 10 -8 Based on Contact Formation Probability Without Error Correction Code
Characterizing the Impact of RTN on Logic and SRAM Operation Using a Dual Ring Oscillator Array Circuit
A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13 μm CMOS
InP HBT/Si CMOS-Based 13-b 1.33-Gsps Digital-to-Analog Converter With > 70-dB SFDR
A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization
Corrections to "Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping" [Sep 10 1770-1780]
A wide-band class-B video output driver
A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding
Adaptive Comparator Bias-Current Control of 0.6 V Input Boost Converter for ReRAM Program Voltages in Low Power Embedded Applications
A low-voltage folded-switching mixer in 0.18-μm CMOS
A figure of merit for the high-frequency noise behavior of bipolar transistors
ILAC: an automated layout tool for analog CMOS circuits
Millimeter-Scale Node-to-Node Radio Using a Carrier Frequency-Interlocking IF Receiver for a Fully Integrated 4 $\times$ 4 $\times$ 4 mm 3 Wireless Sensor Node
Correction to "6-k$Omega$43-Gb/s Differential Transimpedance-Limiting Amplifier With Auto-Zero Feedback and High Dynamic Range"
SiGe differential transimpedance amplifier with 50-GHz bandwidth
A 10-ps resolution, process-insensitive timing generator IC
Broadband mm-Wave Current/Voltage Sensing-Based VSWR-Resilient True Power/Impedance Sensor Supporting Single-Ended Antenna Interfaces
Introduction to the Special Issue on the 2003 IEEE Bipolar/BiCMOS Circuits and Technology Meeting
A Pipelined Point Cloud Based Neural Network Processor for 3-D Vision With Large-Scale Max Pooling Layer Prediction
A 50-Gb/s Multicarrier Transmitter Using DAC-Based Polar Drivers in 22-nm FinFET
A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation
The design of CMOS continuous-time VHF current and voltage-mode lowpass filters with Q-enhancement circuits
Millimeter-Wave Quadrature Mixed-Mode Transmitter With Distributed Parasitic Canceling and LO Leakage Self-Suppression
Simulating the complexity of regular VLSI layout
On-chip ramp generators for mixed-signal BIST and ADC self-test
A 27.9-mW 802.15.4/4z 1T2R Transceiver With FIR-Embedded Quadrature Hybrid Correlation and AoA Localization
Embedded anti-aliasing in switched-capacitor ladder filters with variable gain and offset compensation
A 3-V, 10-100-MHz continuous-time seventh-order 0.05° equiripple linear phase filter
A 1.25-gb/s burst-mode receiver for GPON applications
Nucleic Acid Extraction, Amplification, and Detection on Si-Based Microfluidic Platforms
A novel low-voltage content-addressable-memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques
Analysis and Design of Small-Signal Polar Transmitters for Cellular Applications
A K-Band Full 360° Phase Shifter Using Novel Non-Orthogonal Vector Summing Method
100-Gb/s 2 7 -1 and 54-Gb/s 2 11 -1 PRBS generators in SiGe bipolar technology
A 2-GHz analog-to-digital delta-sigma modulator for CDMA receivers with 79-dB signal-to-noise ratio in 1.23-MHz bandwidth
A micropower analog circuit implementation of hidden Markov model state decoding
Jitter optimization based on phase-locked loop design parameters
A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration
A 3-ns range, 8-ps resolution, timing generator LSI utilizing Si bipolar gate array
A 76- to 81-GHz Multi-Channel Radar Transceiver
A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology
A Three-Level Boost Converter With Full-Range Auto-Capacitor-Compensation Pulse Frequency Modulation
Design and Implementation of Reference-Free Drift-Cancelling CMOS Magnetic Sensors for Biosensing Applications
SPAID: an architectural synthesis tool for DSP custom applications
A Scalable, 2.9 mW, 1 Mb/s e-Textiles Body Area Network Transceiver With Remotely-Powered Nodes and Bi-Directional Data Communication
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W
A 2.4-GHz low-IF receiver for wideband WLAN in 6-μm CMOS-architecture and front-end
Implicit DC-DC downconversion through charge-recycling
A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection
A low-voltage 5.1-5.8-GHz image-reject receiver with wide dynamic range
Dual-Mode CMOS Doherty LTE Power Amplifier With Symmetric Hybrid Transformer
A Light-Field Image Sensor in 180 nm CMOS
A Field-Programmable Analog Array of 55 Digitally Tunable OTAs in a Hexagonal Lattice
Design optimization of low-power high-performance DSP building blocks
Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus
A 60-GHz Outphasing Transmitter in 40-nm CMOS
A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI
A Reconfigurable Single-Inductor Multi-Stage Hybrid Converter for 1-Cell Battery Chargers
A Low Energy Injection-Locked FSK Transceiver With Frequency-to-Amplitude Conversion for Body Sensor Applications
A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4-ppm/ ° C From -20 °C to 125 °C
Power-speed product of an optical flip-flop memory with optical feedback
A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device
Low-voltage low-power LVDS drivers
A fully integrated low-IF CMOS GPS radio with on-chip analog image rejection
A fully differential class-AB switched-current integrator for signal processing
A Modular 32-site wireless neural stimulation microsystem
An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC-DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS
1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs
Introduction to the Special Issue on the 2007 Symposium on VLSI Circuits
Computation sharing programmable FIR filter for low-power and high-performance applications
Variable Off-Time Control Loop for Current-Mode Floating Buck Converters in LED Driving Applications
A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation
A 0.25 μ m InP DHBT 200 GHz+ Static Frequency Divider
A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS
A 22-nm FDSOI CMOS Low-Noise Active Balun Achieving p-p Output Swing Over 0.01-5.4-GHz for Direct RF Sampling Applications
A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture
A direct conversion receiver with an IP2 calibrator for CDMA/PCS/GPS/AMPS applications
Scalable Parasitic Charge Redistribution: Design of High-Efficiency Fully Integrated Switched-Capacitor DC-DC Converters
A new high-speed periodic-threshold comparator for use in a Josephson A/D converter
A 20 mW 3.24mm 2 Fully Integrated GPS Radio for Location Based Services
A single-chip quad-band (850/900/1800/1900 MHz) direct conversion GSM/GPRS RF transceiver with integrated VCOs and fractional-n synthesizer
A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting
A 4 Gbits/s GaAs 16:1 multiplexer/1:16 demultiplexer LSI chip
A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs
Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters
A current-based reference-generation scheme for 1T-1C ferroelectric random-access memories
A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders
Operational amplifier with 1-V rail-to-rail multipath-driven output stage
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS
A 0.2-mW 2-Mb/s Digital Transceiver Based on Wideband Signaling for Human Body Communications
Top-down pass-transistor logic design
Retraction of Papers With Falsified Information
A transistorless-current-mode static RAM architecture
A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS
An Amorphous-Silicon Operational Amplifier and Its Application to a 4-Bit Digital-to-Analog Converter
A Multimode Vision Sensor With Temporal Contrast Pixel and Column-Parallel Local Binary Pattern Extraction for Dynamic Depth Sensing Using Stereo Vision
A 1.9 GHz low-voltage silicon bipolar receiver front-end for wireless personal communications systems
A Low-Power Digital IC Design Inside the Wireless Endoscopic Capsule
A Bulk Acoustic Wave (BAW) Based Transceiver for an In-Tire-Pressure Monitoring Sensor Node
A simple approach to modeling cross-talk in integrated circuits
A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique
Concepts and methods in optimization of integrated LC VCOs
Programmable CMOS switched-capacitor biquad using quasi-passive algorithmic DAC's
Design of a differential distributed amplifier and oscillator using close-packed interleaved transmission lines
High-speed, low-switching noise CMOS memory data output buffer
A 15-b resolution 2-MHz Nyquist rate ΔΣ ADC in a 1-μm CMOS technology
A 0.92-pJ/b PAM-4 and 0.61-pJ/b PAM-6 224-Gb/s DAC-Based Transmitter in 3-nm FinFET
An experimental 1-Mbit cache DRAM with ECC
A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS
A very low-noise CMOS preamplifier for capacitive sensors
A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management
An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing
Low-Power Dynamic Memory Word Line Decoding for Static Random Access Memories
A 28-nm 142-mW Motion-Control SoC for Autonomous Mobile Robots
A wafer-scale-level system integrated LSI containing eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array
Parallel Versus Serial: Design of an Optical Receiver With Integrated Blue Photodetectors and Digitally Tunable Low-End Cutoff Frequency for MicroLED-Based Parallel Interchip Communication
A High-Efficiency Wireless Power Transfer System Under Wide Coupling Coefficient Range Based on Phase Shift and Near-Zero-Time Detection
A 0.004-mm 2 3.65-mW 7-Bit 2-GS/s Single-Channel GRO-Based Time-Domain ADC Incorporating Dead-Zone Elimination and On-Chip Folding-Offset Calibration in 28-nm CMOS
A Wide-Load-Range Constant-Charge-Auto-Hopping Control Single-Inductor-Dual-Output Boost Regulator With Minimized Cross-Regulation
A 70-Mbit/s (RZ) 16*16 crosspoint switch for ternary-encoded signals
mm-Wave Mixer-First Receiver With Selective Passive Wideband Low-Pass Filtering
A 500-MHz 16*16 complex multiplier using self-aligned gate GaAs heterostructure FET technology
A 20.7-43.8-GHz Low Power Reconfigurable ×2/× 3 Frequency Multiplier for Multiple 5G-mm-Wave Bands
A Highly Linear Broadband CMOS LNA Employing Noise and Distortion Cancellation
A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer
A Distortion Compensating Flash Analog-to-Digital Conversion Technique
10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture
A 0.039 mm 2 Inverter-Based 1.82 mW 68.6~ dB-SNDR 10 MHz-BW CT-ΣΔ-ADC in 65 nm CMOS Using Power- and Area-Efficient Design Techniques
60 GHz Single-Chip Front-End MMICs and Systems for Multi-Gb/s Wireless Communication
A fully integrated V-band PLL MMIC using 0.15-μm GaAs pHEMT technology
A Feed-Forward Power-Supply Noise Cancellation Technique for Single-Ended Class-D Audio Amplifiers
A Single-Chip CMOS UHF RFID Reader Transceiver for Chinese Mobile Applications
A Light-Load-Efficient 11/1 Switched-Capacitor DC-DC Converter With 94.7% Efficiency While Delivering 100 mW at 3.3 V
Process variation in embedded memories: failure analysis and variation aware architecture
Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor
A Total-Power Radiometer Front End in a 0.25-µ BiCMOS Technology With Low 1/f-Corner
A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing
C-band GaAs FET power amplifiers with 70-W output power and 50% PAE for satellite communication use
Silicon-germanium BiCMOS HBT technology for wireless power amplifier applications
A simple subcircuit extension of the BSIM3v3 model for CMOS RF design
A four-antenna receiver in 90-nm CMOS for beamforming and spatial diversity
A 90-nm CMOS 5-Mbps Crystal-Less RF-Powered Transceiver for Wireless Sensor Network Nodes
An Inductorless Bias-Flip Rectifier for Piezoelectric Energy Harvesting
Using active components to perform voltage division in digital-to-analog conversion
A Wide-Bandwidth Ultrasound Receiver and On-Chip Ultrasound Transmitter for Ultrasound Capsule Endoscopy
A dual-mode sensing scheme of capacitor-coupled EEPROM cell
A variable-frequency parallel I/O interface with adaptive power-supply regulation
A Single-Temperature Trimming Technique for MOS-Input Operational Amplifiers Achieving 0.33 μ V/°C Offset Drift
A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-Linearity Dynamic VTC
A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications
A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiver
100-MHz serial access architecture for 4-Mb field memory
A Biomedical Sensor Interface With a sinc Filter and Interference Cancellation
A median peak detecting analog signal processor for hard disk drive servo
A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire
A Low THD, Low Power, High Output-Swing Time-Mode-Based Tunable Oscillator Via Digital Harmonic-Cancellation Technique
3-Gb/s High-Speed True Random Number Generator Using Common-Mode Operating Comparator and Sampling Uncertainty of D Flip-Flop
ECL-CMOS and CMOS-ECL interface in 1.2- mu m CMOS for 150-MHz digital ECL data transmission systems
An 8-bit 2-Gsample/s folding-interpolating analog-to-digital converter in SiGe technology
A 6 mW, 5, 000-Word Real-Time Speech Recognizer Using WFST Models
A programmable integrated digital controller for switching converters with dual-band switching and complex pole-zero compensation
Corrections to "A Highly Linear and Efficient 28-GHz PA With a Pₛₐₜ of 23.2 dBm, P₁ dB of 22.7 dBm, and PAE of 35.5% in 65-nm Bulk CMOS"
A 600-MHz VLIW DSP
An ultra low power adaptive wavelet video encoder with integrated memory
MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor Using 1.4-zJ/op Unshunted Superconductor Josephson Junction Devices
A 17-ns 4-Mb CMOS DRAM
A 4-GHz effective sample rate integrated test core for analog and mixed-signal circuits
A Trimming-Free 3-in-1 Multi-Mode Passive Switched-Capacitor Amplifier With an Absolute Logarithmic Error of 0.5 dB up to 200 ° C
Accurate Characterization of Integrated Continuous-Time Filters
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces
A stereo multibit ΣΔ DAC with asynchronous master-clock interface
A 65-nm 8-to-3-b 1.0-0.36-V 9.1-1.1-TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Swarm Robotics
A 40.68-MHz Active Rectifier With Cycle-Based On-/Off-Delay Compensation for High-Current Biomedical Implants
A General Theory of Injection Locking and Pulling in Electrical Oscillators - Part II: Amplitude Modulation in $LC$ Oscillators, Transient Behavior, and Frequency Division
A 2.45-GHz 0.13-µm CMOS PA With Parallel Amplification
AIMMI: Audio and Image Multi-Modal Intelligence via a Low-Power SoC With 2-MByte On-Chip MRAM for IoT Devices
A Frequency-Division Transceiver for Long-Range Neural Signal Recording From Multiple Subjects
Erratum to "A 1-V 140-μW 88-dB Audio Sigma-Delta Modulator in 90-nm CMOS"
A Battery-Powered Wireless Ion Sensing System Consuming 5.5 nW of Average Power
A CMOS 5 nV/√Hz 74-dB-Gain-Range 82-dB-DR Multistandard Baseband Chain for Bluetooth, UMTS, and WLAN
Cyclostationary noise analysis of large RF circuits with multitone excitations
A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications
An embedded 0.8 V/480 μW 6b/22 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique
An Actively Detuned Wireless Power Receiver With Public Key Cryptographic Authentication and Dynamic Power Allocation
VLSI Architecture of Line-Based Lifting Wavelet Transform for Motion JPEG2000
A 300-MHz fixed-delay tree search-DFE analog CMOS disk-drive read channel
A High-Efficiency 142-182-GHz SiGe BiCMOS Power Amplifier With Broadband Slotline-Based Power Combining Technique
A low-current Ku-band GaAs monolithic image rejection down-converter
Design of SOI CMOS operational amplifiers for applications up to 300°C
A 15-Channel Orthogonal Code Chopping Instrumentation Amplifier for Area-Efficient, Low-Mismatch Bio-Signal Acquisition
A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications
An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell
A Wide-Lock-In-Range and Low-Jitter 12-14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop
2-V/100-ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and nonrelaxation reference cell
A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver
A Fully Integrated 320 GHz Coherent Imaging Transceiver in 130 nm SiGe BiCMOS
A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI with a 160-kb CAM
Introduction to the signal processing section
A 77-GHz Hybrid TDM-MIMO Phased-Array Radar With 186-m Detection Range and 3-cm Range Resolution
A versatile Si-bipolar driver circuit with high output voltage swing for external and direct laser modulation in 10 Gb/s optical-fiber links
A self-trimming 14-b 100-MS/s CMOS DAC
A CMOS multichannel 10-Gb/s transceiver
A Sub-µs Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support
DepFiN: A 12-nm Depth-First, High-Resolution CNN Processor for IO-Efficient Inference
A Scalable BEV Perception Processor for Image/Point Cloud Fusion Applications Using CAM-Based Universal Mapping Unit
The effects of a ground shield on the characteristics and performance of spiral inductors
An 802.11ba-Based Wake-Up Radio Receiver With Wi-Fi Transceiver Integration
5-GHz 32-bit integer execution core in 130-nm dual-V T CMOS
An experimental 16-Mbit DRAM with reduced peak-current noise
A 2-V pp 80-200-MHz fourth-order continuous-time linear phase filter with automatic frequency tuning
A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links
A 2.4-GHz-BW 59.7-dB-Range 0.39-dB-Error dB-Linear VGA Featuring -40 °C~110 °C and ±10%-Supply PVT Robustness in 40-Nm CMOS
A 30/35 GHz Dual-Band Transmitter for Phased Arrays in Communication/Radar Applications
Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9× Lower Energy/Access
A Battery-Free Neural-Recording Chip Achieving 5.5 cm Fully-Implanted Depth by Galvanically-Switching Passive Body Channel Communication
A 2-in-1 Temperature and Humidity Sensor With a Single FLL Wheatstone-Bridge Front-End
Precise analog synapse for Kohonen feature maps
Digitally controlled oscillator
A 15-ns 32*32-b CMOS multiplier with an improved parallel structure
A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)
A Wideband ΔΣ Digital-RF Modulator for High Data Rate Transmitters
A Nyquist Rate SAR ADC Employing Incremental Sigma Delta DAC Achieving Peak SFDR = 107 dB at 80 kS/s
A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving
A 200 mW, 1 Msample/s, 16-b pipelined A/D converter with on-chip 32-b microcontroller
Multigigahertz voltage-controlled oscillators in advanced silicon bipolar technology
A 90.7-nW Vibration-Based Condition Monitoring Chip Featuring a Digital Compute-in-Memory- Based DNN Accelerator Using an Ultra-Low-Power 13T-SRAM Cell
Standing wave oscillators utilizing wave-adaptive tapered transmission lines
A 32-b RISC/DSP microprocessor with reduced complexity
A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement
An Incremental Step Sensing MPPT Based SI-SIDO Energy Harvester With >99% Peak MPPT Efficiency for an Input Power Range of 30 μW to 33 mW