yusuke1997/dblp-id-title huggingface dataset:
Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz
A 1-Gb/s, 0.7-μm CM+ OS optical receiver with full rail-to-rail output swing
A novel approach to controlled programming of tunnel-based floating-gate MOSFETs
A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth
A comprehensive CAD system for high-performance 300 K-circuit ASIC logic chips
A 5-V AC-Powered CMOS Filter-Selectivity Booster for POTS/ADSL Splitter Size Reduction
A 1-21-GHz, 1.95-3.1-dB NF Ultra-Wideband LNA With Gₘ-Assisted-Feedback Noise Suppression Achieving 140-Gb/s Data Rate in 40-nm CMOS
An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures
A 0.75-3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR With a Deadzone-Compensated Frequency Detector
A 5.6 μ A Wide Bandwidth, High Power Supply Rejection Linear Low-Dropout Regulator With 68 dB of PSR Up To 2 MHz
Analysis and design of high-speed and low-power CMOS PLAs
A Hybrid Boost Converter With Cross-Connected Flying Capacitors
AM-AM and AM-PM Distortion in D-Band BiCMOS Vector-Interpolation Phase Shifters
A 2-GHz 1.6-mW phase-locked loop
A 0.5-ms 47.5-nJ Resistor-to-Digital Converter for Resistive BTEX Sensor Achieving 0.1-to-5 ppb Resolution
A Single Li-Ion Battery Powered Buck Converter With >90% Efficiency Over 10-μA to 500-mA Loading Range by Utilizing Compensator-Based Built-In Mode Tracking Technology
A 200 µW Eight-Channel EEG Acquisition ASIC for Ambulatory EEG Systems
A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <-80 dBc IM3 up to 1 GHz in 65 nm CMOS
Design of a switched-capacitor filter for a mobile telephone receiver
A 256-Mb DRAM with 100 MHz serial I/O ports for storage of moving pictures
A 10 bit, 300 MS/s Nyquist Current-Steering Power DAC With 6 V PP Output Swing
Guest Editorial 2020 Custom Integrated Circuits Conference
Energy-Delay Optimization of 64-Bit Carry-Lookahead Adders With a 240 ps 90 nm CMOS Design Example
A 6.5-8.1-GHz Communication/Ranging VWB Transceiver for Secure Wireless Connectivity With Enhanced Bandwidth Efficiency and ΔΣ Energy Detection
An 8-Gb/s simultaneous bidirectional link with on-die waveform capture
A four-processor building block for SIMD processor arrays
A silicon bipolar transmitter front-end for 802.11a and HIPERLAN2 wireless LANs
An Efficient SSHI Interface With Increased Input Range for Piezoelectric Energy Harvesting Under Variable Conditions
A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL
A D-Band Concurrent 20-Beam MIMO Transmitter Array With a Four-Element Joint Static/Dynamic Beam-Multiplication Beamformer
A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder
An 0.8-μm CMOS mixed analog-digital integrated audiometric system
Accurate dB-Linear Variable Gain Amplifier With Gain Error Compensation
A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks
A Successive-Approximation Switched-Capacitor DC-DC Converter With Resolution of V IN /2 N for a Wide Range of Input and Output Voltages
Ku-Band 70-/30-W-Class Internally Matched GaN Power Amplifiers With Low IMD3 Over a Wide Offset Frequency Range of Up To 400 MHz
Analysis and Design of a Full-Duplex Two-Element MIMO Circulator-Receiver With High TX Power Handling Exploiting MIMO RF and Shared-Delay Baseband Self-Interference Cancellation
A Dynamically Biased Multiband 2G/3G/4G Cellular Transmitter in 28 nm CMOS
A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling
A 5.6 ppm/°C Temperature Coefficient, 87-dB PSRR, Sub-1-V Voltage Reference in 65-nm CMOS Exploiting the Zero-Temperature-Coefficient Point
An analog VLSI neural network with on-chip perturbation learning
Far-Field On-Chip Antennas Monolithically Integrated in a Wireless-Powered 5.8-GHz Downlink/UWB Uplink RFID Tag in 0.18-μm Standard CMOS
Low-Power Approaches to High-Speed Current-Steering Digital-to-Analog Converters in 0.18-µm CMOS
Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC)
Oscillatory metastability in homogeneous and inhomogeneous flip-flops
Radiation Tolerant Multi-Bit Flip-Flop System With Embedded Timing Pre-Error Sensing
Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations
A Spur-and-Phase-Noise-Filtering Technique for Inductor-Less Fractional-N Injection-Locked PLLs
A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks
A 2.4 mA Quiescent Current, 1 W Output Power Class-D Audio Amplifier With Feed-Forward PWM-Intermodulated-Distortion Reduction
A 177 Mb/s VLSI implementation of the International Data Encryption Algorithm
60 GHz CMOS Amplifiers Using Transformer-Coupling and Artificial Dielectric Differential Transmission Lines for Compact Design
An experimental large-capacity semiconductor file memory using 16-levels/cell storage
A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems
A systems approach to custom VLSI for a digital color imaging system
A design technique for a 60 GHz-bandwidth distributed baseband amplifier IC module
21.5-dBm power-handling 5-GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with depletion-layer-extended transistors (DETs)
Guest Editorial 2023 Custom Integrated Circuits Conference
A 50-Gb/s PAM4 Si-Photonic Transmitter With Digital-Assisted Distributed Driver and Integrated CDR in 40-nm CMOS
Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping
Rank-order filter design with a sampled-analog multiple-winners-take-all core
27-GHz bandwidth high-speed monolithic integrated optoelectronic photoreceiver consisting of a waveguide fed photodiode and an InAlAs/InGaAs-HFET traveling wave amplifier
Correction to "An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and - 98 dB THD" [Aug 09 2202-2211]
A 368 × 184 Optical Under-Display Fingerprint Sensor Comprising Hybrid Arrays of Global and Rolling Shutter Pixels With Shared Pixel-Level ADCs
A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration
A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time/Discrete-Time Cascaded ΣΔ Modulator
A 23-to-29 GHz Transconductor-Tuned VCO MMIC in 0.13 µm CMOS
SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor
A 70-86-GHz Deep-Noise-Canceling LNA With Dual-Stage Noise Cancellation Using Asymmetric Compensation Transformer and 4-to-1 Hybrid-Phase Combiner
A 24-30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas
A 2-V 10.7-MHz CMOS limiting amplifier/RSSI
Design of Adaptive Multimode RF Front-End Circuits
A 0.7-3 GHz GaAs QPSK/QAM direct modulator
A Versatile ±25-A Shunt-Based Current Sensor With ±0.25% Gain Error From -40 °C to 85 °C
112-Gb/s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channels
A 2.3 GHz 2.8 mW Sampling ΔΣ PLL Achieving -110 dBc/Hz In-Band Phase Noise and 500 MHz FMCW Chirp
A 0.2-μm, 1.8-V, SOI, 550-MHZ, 64-b PowerPC microprocessor with copper interconnects
A 22-Gb/s Time-Interleaved Low-Power Optical Receiver With a Two-Bit Integrating Front End
A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface
Low-power InP-HEMT switch ICs integrating miniaturized 2×2 switches for 10-Gb/s systems
An Energy-Scalable Accelerator for Blind Image Deblurring
A 19 nV/√Hz Noise 2-µ: V Offset 75-/micro;A Capacitive-Gain Amplifier With Switched-Capacitor ADC Driving Capability
A 3-V CMOS low-distortion class AB line driver suitable for HDSL applications
A Class-D Amplifier With Pulse Code Modulated (PCM) Digital Input for Digital Hearing Aid
A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme
A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management
Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor
A Sub-fs-FoM Digital LDO Using PMOS and NMOS Arrays With Fully Integrated 7.2-pF Total Capacitance
An ultra-low-power-consumption high-speed GaAs quasi-differential switch flip-flop (QD-FF)
A Synthesis-Based Bandwidth Enhancement Technique for CMOS Amplifiers: Theory and Design
A pipelined 50-MHz CMOS 64-bit floating-point arithmetic processor
A Photovoltaic Dynamic Vision Sensor
A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS
A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process
Circuit techniques in a 266-MHz MMX-enabled processor
1-1-1 MASH Δ Σ Time-to-Digital Converters With 6 ps Resolution and Third-Order Noise-Shaping
A Self-Duty-Cycled and Synchronized UWB Pulse-Radio Receiver SoC With Automatic Threshold-Recovery Based Demodulation
A 1-3 GHz Delta-Sigma-Based Closed-Loop Fully Digital Phase Modulator in 45-nm CMOS SOI
A 12-bit 320-MSample/s current-steering CMOS D/A converter in 0.44 mm 2
A 2.4 GHz Wideband Open-Loop GFSK Transmitter With Phase Quantization Noise Cancellation
A 13.56-MHz Wireless Power and Data Transfer System With Current-Modulated Energy-Reuse Back Telemetry and Energy-Adaptive Voltage Regulation
A Constant Energy-Per-Cycle Ring Oscillator Over a Wide Frequency Range for Wireless Sensor Nodes
A Programmable SIMD Vision Chip for Real-Time Vision Applications
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance
InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s
Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques
Quasi-complementary BiCMOS for sub-3-V digital circuits
A High-Efficiency Wide Output Range Reconfigurable Capacitive-Sigma DC-DC Converter
Interface Electronics for a CMOS Electrothermal Frequency-Locked-Loop
A Compact Millimeter-Wave Reconfigurable Dual-Band LNA With Image-Rejection in 28-nm Bulk CMOS for 5G Applications
A 15-ns 4-Mb CMOS SRAM
A Dual-Inductor Quad-Path Hybrid Buck (2L4PHB) Converter With Reduced Inductor Current
Silicon complexity for maximum likelihood MIMO detection using spherical decoding
A 200-MHz complex number multiplier using redundant binary arithmetic
A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios
A plastic packaged 10 Gb/s BiCMOS clock and data recovering 1: 4-demultiplexer with external VCO
A cyclic A/D converter that does not require ratio-matched components
A 300 GHz CMOS Transmitter With 32-QAM 17.5 Gb/s/ch Capability Over Six Channels
A High-PSRR Reconfigurable Class-AB/D Audio Amplifier Driving a Hands-Free/Receiver 2-in-1 Loudspeaker
A novel multi-input floating-gate MOS four-quadrant analog multiplier
An optoelectronic CMOS memory circuit for parallel detection and storage of optical data
A 0.25-µm CMOS 1.9-GHz PHS RF Transceiver With a 150-kHz Low-IF Architecture
A Blind Baud-Rate ADC-Based CDR
A Versatile, Low Power, High Performance BiCMOS MIMO/Diversity Direct Conversion Transceiver IC for WiBro/WiMAX (802.16e)
Complete SOC Transceiver in 0.18 µm CMOS Using Q-Enhanced Filtering, Sub-Sampling and Injection Locking
A Scalable 5-15 Gbps, 14-75 mW Low-Power I/O Transceiver in 65 nm CMOS
An Inductor-Less Noise-Cancelling Broadband Low Noise Amplifier With Composite Transistor Pair in 90 nm CMOS Technology
Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS
A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC
A Time-Interleaved 2 nd -Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation
A stereo asynchronous digital sample-rate converter for digital audio
Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs
Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS
Automatic and continuous offset compensation of MOS operational amplifiers using floating-gate transistors
A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC Operations
A 1 GHz Bandwidth Low-Pass ΔΣADC With 20-50 GHz Adjustable Sampling Rate
Overview for the Special Section on the 2007 Radio Frequency Integrated Circuits Symposium
A 30 µW 30 fps 110 × 110 Pixels Vision Sensor Embedding Local Binary Patterns
A monotonic digitally controlled delay element
IRIS: An Energy-Efficient Spatial Computing SoC for Real-Time Interactive Rendering and Modeling With Surface-Aware 3-D Gaussian Splatting
A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects
An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 μ m CMOS
A modular T-mode design approach for analog neural network hardware implementations
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers
An ECG-on-Chip With 535 nW/Channel Integrated Lossless Data Compressor for Wireless Sensors
Crosstalk-Aware PWM-Based On-Chip Links With Self-Calibration in 65 nm CMOS
A Low-Stimulus-Scattering Pixel-Sharing Sub-Retinal Prosthesis SoC With Time-Based Photodiode Sensing and Per-Pixel Dynamic Voltage Scaling
A 5-ns 1-Mb ECL BiCMOS SRAM
Direct 48-/1-V GaN-Based DC-DC Power Converter With Double Step-Down Architecture and Master-Slave AO 2 T Control
High-speed CMOS analog Viterbi detector for 4-PAM partial-response signaling
A 1/2.5 inch VGA 400 fps CMOS Image Sensor With High Sensitivity for Machine Vision
A Low-Power Fully Implantable 15-Channel Retinal Stimulator Chip
A High-Power Low-Distortion GaAs HBT Power Amplifier for Mobile Terminals Used in Broadband Wireless Applications
A 27-39-GHz VSWR-Resilient Compact True Power and Gain Sensor With Built-In Sensing Error Compensation for Integrated Power Amplifiers
A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers
A 40 nm CMOS E-Band Transmitter With Compact and Symmetrical Layout Floor-Plans
An Integrated Stimulator With DC-Isolation and Fine Current Control for Implanted Nerve Tripoles
A Fully Integrated, 290 pJ/bit UWB Dual-Mode Transceiver for cm-Range Wireless Interconnects
An Inductive Loading Simultaneous Noise and Input Matching Technique With Current Reuse for Low-Power LNA
A -10 to -20-V Inverting Buck-Boost Drive GaN Driver With Sub-1-μA Leakage Current V th Tracking Technique for 20-MHz Depletion-Mode GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistors
Analysis, design, and optimization of InGaP-GaAs HBT matched-impedance wide-band amplifiers with multiple feedback loops
Boost DC-DC Converter With Fast Reference Tracking (FRT) and Charge-Recycling (CR) Techniques for High-Efficiency and Low-Cost LED Driver
A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM
100 GHz+ Gain-Bandwidth Differential Amplifiers in a Wafer Scale Heterogeneously Integrated Technology Using 250 nm InP DHBTs and 130 nm CMOS
3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications
A compact low-power BiCMOS log-domain filter
Circuit behavior modeling and compact testing performance evaluation
A 1.2-GIPS/W microprocessor using speed-adaptive threshold-voltage CMOS with forward bias
A 100-MHz 64-tap FIR digital filter in 0.8- mu m BiCMOS gate array
A 25 Gb/s 5.8 mW CMOS Equalizer
An interference-robust receiver for ultra-wideband radio in SiGe BiCMOS technology
DC modeling and characterization of AlGaAs/GaAs heterojunction bipolar transistors for high-temperature applications
A Chopping Switched-Capacitor RF Receiver With Integrated Blocker Detection
Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference
Metastability in CMOS library elements in reduced supply and technology scaled applications
A Simultaneous Bidirectional Single-Ended Coaxial Link With 24-Gb/s Forward and 312.5-Mb/s Back Channels
256-Mb DRAM circuit technologies for file applications
Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance
Gallium-arsenide buffer store components for Gbit/s optical-fiber transmission systems
A voltage overscaled low-power digital filter IC
Low-power 1/2 frequency dividers using 0.1- mu m CMOS circuits built with ultrathin SIMOX substrates
Fully Integrated GaN-on-Silicon Gate Driver and GaN Switch With Temperature-Compensated Fast Turn-on Technique for Achieving Switching Frequency of 50 MHz and Slew Rate of 118.3 V/Ns
A Frequency Synthesizer With Optimally Coupled QVCO and Harmonic-Rejection SSBmixer for Multi-Standard Wireless Receiver
A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET
Integrated Wideband Self-Interference Cancellation in the RF Domain for FDD and Full-Duplex Wireless
A 402-output TFT-LCD driver IC with power control based on the number of colors selected
An 0.8-μm high-voltage IC using a newly designed 600-V lateral p-channel dual-action device on SOI
Circuit models and applications of the superconducting field-effect transistor
A 28 GHz Hybrid PLL in 32 nm SOI CMOS
An Efficient Mixed-Signal 2.4-GHz Polar Power Amplifier in 65-nm CMOS Technology
High-speed architecture for a programmable frequency divider and a dual-modulus prescaler
Broadband GaAs MESFET and GaN HEMT resistive feedback power amplifiers
A Novel 100 MHz-45 GHz Input-Termination-Less Distributed Amplifier Design With Low-Frequency Low-Noise and High Linearity Implemented With A 6 Inch 0.15~ μm GaN-SiC Wafer Process Technology
Complementary current-mirror logic
Architecture and circuit design of a 6-GOPS signal processor for QAM demodulator applications
A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues
A 650-MHz, IA-32 microprocessor with enhanced data streaming for graphics and video
A 3.3-V power adaptive 1244/622/155 Mbit/s transceiver for ATM, SONET/SDH
Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs
A 550-MSample/s 8-Tap FIR digital filter for magnetic recording read channels
A Reconfigurable Single-Stage Asymmetrical Full-Wave Step-Down Rectifier for Bidirectional Device-to-Device Wireless Fast Charging
Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations
Op amp combining precision, high speed, and high output current drive for +or-5-V power supply operation
All-Digital Outphasing Modulator for a Software-Defined Transmitter
A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit
Design and Analysis of a W-Band SiGe Direct-Detection-Based Passive Imaging Receiver
Design and Analysis of a Programmable Receiver Front End With Time-Interleaved Baseband Analog-FIR Filtering
Design of Sub-10-μW Sub-0.1% THD Sinusoidal Current Generator IC for Bio-Impedance Sensing
Enabling Energy-Efficient Homomorphic Encryption Evaluation via eDRAM-Based In-Situ Computing in an Edge Processor
Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing
Adaptive Blocker Rejection Continuous-Time ΔΣ ADC for Mobile WiMAX Applications
Low Phase NoiseG m -Boosted Differential Gate-to-Source Feedback Colpitts CMOS VCO
Controlling substrate currents in junction-isolated ICs
A 0.2-1.45-GHz Subsampling Fractional-N Digital MDLL With Zero-Offset Aperture PD-Based Spur Cancellation and In Situ Static Phase Offset Detection
A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors
UNPU: An Energy-Efficient Deep Neural Network Accelerator With Fully Variable Weight Bit Precision
A Dual-Path Transformer-Based Multiband Power Amplifier for mm-Wave 5G Applications
A High Data-Rate Energy-Efficient Interference-Tolerant Fully Integrated CMOS Frequency Channelized UWB Transceiver for Impulse Radio
A low-power 2.5-GHz 90-nm level 1 cache and memory management unit
Frequency-Hopped Quadrature Frequency Synthesizer in 0.13-mum Technology
A 9-ns 1-Mbit CMOS SRAM
A 19-bit low-power multibit sigma-delta ADC based on data weighted averaging
A CMOS switched transconductor mixer
A vertically integrated tool for automated design of ΣΔ modulators
Digital Circuit Design Trends
Design of Dual Lower Bound Hysteresis Control in Switched-Capacitor DC-DC Converter for Optimum Efficiency and Transient Speed in Wide Loading Range for IoT Application
An adaptive PLL tuning system architecture combining high spectral purity and fast settling time
The implementation of the Itanium 2 microprocessor
512-Mb PROM with a three-dimensional array of diode/antifuse memory cells
A 43-Gb/s full-rate-clock 4: 1 multiplexer in InP-based HEMT technology
A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation
A test circuit for measurement of clocked storage element characteristics
A Three-Fine-Level Buck-Boost Hybrid Converter Achieving Half-V IN -Stress on All Switches and Fast Transient Response
A 818-4094 TOPS/W Capacitor-Reconfigured Analog CIM for Unified Acceleration of CNNs and Transformers
A 400-MT/s 6.4-GB/s multiprocessor bus interface
A low-power, high-speed, current-feedback op-amp with a novel Class AB high current output stage
An all-digital phase-locked loop for high-speed clock generation
Analysis and Design of RF CMOS Attenuators
A 94-GHz 4TX-4RX Phased-Array FMCW Radar Transceiver With Antenna-in-Package
The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory
Special applications of the voting model for bridging faults
Analog CMOS realization of fuzzy logic membership functions
A 3-to-40-V Automotive-Use GaN Driver With Active Bootstrap Balancing and V SW Dual-Edge Dead-Time Modulation Techniques
A 58.6 mW 30 Frames/s Real-Time Programmable Multiobject Detection Accelerator With Deformable Parts Models on Full HD 1920×1080 Videos
A 3.96-μm, 124-dB Dynamic-Range, Digital-Pixel Sensor With Triple- and Single-Quantization Operations for Monochrome and Near-Infrared Dual-Channel Global Shutter Operation
A 250 mV, 352 μ W GPS Receiver RF Front-End in 130 nm CMOS
HermesE: A 96-Channel Full Data Rate Direct Neural Interface in 0.13 µm CMOS
Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme
A 10 mV-Input Boost Converter With Inductor Peak Current Control and Zero Detection for Thermoelectric and Solar Energy Harvesting With 220 mV Cold-Start and -14.5 dBm, 915 MHz RF Kick-Start
Corrections to "Precision Passive-Charge-Sharing SAR ADC: Analysis, Design, and Measurement Results"
A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface
A Wideband W-Band Receiver Front-End in 65-nm CMOS
0.13-µm CMOS Phase Shifters for X-, Ku-, and K-Band Phased Arrays
A 5-V Dynamic Class-C Paralleled Single-Stage Amplifier With Near-Zero Dead-Zone Control and Current-Redistributive Rail-to-Rail Gm-Boosting Technique
A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS
Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories
A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms
A Micro Inertial Energy Harvesting Platform With Self-Supplied Power Management Circuit for Autonomous Wireless Sensor Nodes
Analog timing recovery for a noise-predictive decision-feedback equalizer
Design of a Temperature-Aware Low-Voltage SRAM With Self-Adjustable Sensing Margin Enhancement for High-Temperature Applications up to 300 °C
Integrated 105 dB SNR, 0.0031% THD+N Class-D Audio Amplifier With Global Feedback and Digital Control in 55 nm CMOS