yusuke1997/dblp-id-title huggingface dataset:
Guest Editors' Introduction: Hot Chips Turns 20
A Network Processor-Based, Content-Aware Switch
Memristor: Remembrance of Things Past
Motorola's Silver Quill Program
M7: Oracle's Next-Generation Sparc Processor
AltiVec Extension to PowerPC Accelerates Media Processing
Managing the Transition from Complexity to Elegance: Design Convergence
The Vision Behind MLPerf: Understanding AI Inference Performance
Sharing Incentives and Fair Division for Multiprocessors
Insiders, Outsiders, and an Existentialist
Evaluating InfiniBand Performance with PCI Express
Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge
Security Verification via Automatic Hardware-Aware Exploit Synthesis: The CheckMate Approach
News: Intel's earnings double in quarter; tiny bubbles key in future liquid-cooled systems; chip diet tests Cisco's resolve; Intel to release machine learning libraries; and proposal in to fit eight Alpha cores onto a chip
Standards And The Market
Cache-Conscious Thread Scheduling for Massively Multithreaded Processors
Itanium Processor Microarchitecture
Technical Design
Special Issue on Emerging System Interconnects
Collecting patent infringement damages on unpatented products
The Computer-aided Programming System - A Friendly Programming Environment
COM and DCOM - Microsoft's vision for distributed objects [Book Reviews]
Rigel: A 1, 024-Core Single-Chip Accelerator Architecture
The Z80000 Microprocessor
There's Always a Bigger Fish: A Clarifying Analysis of a Machine-Learning-Assisted Side-Channel Attack
A Network of Platforms
A QVGA-Size Pixel-Parallel Image Processor for 1, 000-fps Vision
A 4-Gbps Uncompressed Wireless HD A/V Transceiver Chipset
Fuzzy logic microcontroller
Google and Apple Signed a Deal
Fault Tolerance in Process Control: An Overview And Examples of European Products
Validating Trace-Driven Microarchitectural Simulations
Competition Policy for Innovative Industries
PEPPHER: Efficient and Productive Usage of Hybrid Computing Systems
BlitzCoin: A Decentralized Hardware Solution for Power Management of Highly Heterogeneous Systems on Chip
Very Large-Scale Systems and Some History
A participant's perspective
Processor architecture considerations for embedded controller applications
How coinvention shapes our market
Intel Alder Lake CPU Architectures
Microbenchmark Performance Comparison of High-Speed Cluster Interconnects
A Sampling Method Focusing on Practicality
System verification using multilevel concurrent simulation
The increasingly important interconnect
A Benchmark Characterization of the EEMBC Benchmark Suite
A High-Performance FPGA-Based Fuzzy Processor Architecture for Medical Diagnosis
High-Performance Throughput Computing
NanoBridge-Based FPGA in High-Temperature Environments
Apple Macintosh's energy consumption
Secure Architectures
Forewords by Celebrities
Special Issue on Hot Interconnects
The WearARM Modular, Low-Power Computing Core
Forecasting commercial change
Guest Editor's Introduction: Advanced Dram Technology
Anatomy of a Portable Digital Mediaprocessor
Top Picks from the 2011 Computer Architecture Conferences
HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces
A Performance Study of Mutual Exclusion/Synchronization Mechanisms in an IEEE 796 Bus Multiprocessor
Binary-Decision-Based Programmable Controllers
Thread Cluster Memory Scheduling
Resource Management for Software-Defined Radio Clouds
A History of Microprocessor Development at Intel
Architecture Design of Versatile Recognition Processor for Sensornet Applications
Machine Learning for Systems
Hardware-Software Co-Design for Real-Time Latency-Accuracy Navigation in Tiny Machine Learning Applications
A Radio Network for Monitoring and Diagnosing Computer Systems
Mixed-Signal Approximate Computation: A Neural Predictor Case Study
Pensando Distributed Services Architecture
An Integrated Workstation for the Visually Handicapped
Novel Mixed Codes for Multiple-Cell Upsets Mitigation in Static RAMs
Near-DRAM Acceleration with Single-ISA Heterogeneous Processing in Standard Memory Modules
Power7: IBM's Next-Generation Server Processor
Enabling Scalable High-Performance Systems with the Intel Omni-Path Architecture
Developing New Computer Architectures
CAN for Critical Embedded Automotive Networks
Guest Editor's Introduction: Stepping Into the Future
Advances in Microprocessor Cache Architectures Over the Last 25 Years
Guest Editor's Introduction: Hot Interconnects 10--Thinking beyond the Internet
Special Series on Harsh Chips [Guest editors' introduction]
Putting Design into an Introductory Logic Design Course
Patents: To file or not to file?
Emerging ADAS Thermal Reliability Needs and Solutions
Special Issue on Interconnects for Chiplet Integration Technologies
Myrinet communication
Top Picks in Computer Architecture from Conferences in 2018
A Review of Wisconsin Alumni Research Foundation v. Apple - Part IV
MLPerf: An Industry Standard Benchmark Suite for Machine Learning Performance
Designing the TFP microprocessor
West Coast Federal Appeals Court Upholds Chip Protection Act Violation Finding
Near-Memory Data Services
Top Picks Ignite Innovation
The best patents of all
Ultra-Low-Power Processors
Reliability, Theme Issues, and Plagiarism
JAZiO Signal-Switching Technology: A Low-Cost Digital I/O for High-Speed Applications
SCALPS: Smart card for limited payment systems
Accelerating ML Recommendation With Over 1, 000 RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip
Review of Patents Issued to Computer Architecture Companies in 2021 - Part II
Special Issue on Compiling for Accelerators
Power Evaluation of a Handheld Computer
Architectural Support for Cognitive Processing
A tracking clock recovery receiver for 4-Gbps signaling
Efficient Randomized Algorithms for Input-Queued Switch Scheduling
Microcode Processing: Positioning and Directions
Online Check and Recovery Techniques for Dependable Embedded Processors
FabScalar: Automating Superscalar Core Design
Performance Assessment of Emerging Memories Through FPGA Emulation
Patching Processor Design Errors with Programmable Hardware
War of the words: intellectual property laws and standardization
Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs
A Java-enabled evolution
Implementing Neon: a 256-bit graphics accelerator
Designing for a gigahertz [guTS integer processor]
A High-Throughput Network Processor Architecture for Latency-Critical Applications
The μ Project: An Experience with a Multimicroprocessor System
The Kremlin Oracle for Sequential Code Parallelization
3-D Chips! Chips are Getting Denser and Taller Than Ever!!
DVL-Lossy: Isolating Congesting Flows to Optimize Packet Dropping in Lossy Data-Center Networks
FX!32 a profile-directed binary translator
An Advanced Optimizer for the IA-64 Architecture
10 A Four-Terabit Packet Switch Supporting Long Round-Trip Times
Wireless access and electrical markets: Becoming similar?
"On the Fly" CRC-16 Byte-wise Calculation for 8088-based Computers
Thread-Based Virtual Duplex Systems in Embedded Environments
A Multiprocessor Interface
Hardware-Assisted Fault Isolation: Going Beyond the Limits of Software-Based Sandboxing
Reducing the Soft-Error Rate of a High-Performance Microprocessor
Yale N. Patt Receives the Inaugural IEEE B. Ramakrishna Rau Award
SH4 RISC multimedia microprocessor
Domain Specialization Is Generally Unnecessary for Accelerators
Developing the GX graphics accelerator architecture
Special Issue on Quantum Computing
Power-Management Features of R-Mobile U2, an Integrated Application Processor and Baseband Processor
Architecture of the Pentium microprocessor
AsAP: A Fine-Grained Many-Core Platform for DSP Applications
T-Engine: The Open, Real-Time Embedded-Systems Platform
Guest Editors' Introduction: Developing Interconnect Technology
Toward Postquantum Security for Embedded Cores
The TX1 32-bit microprocessor: performance analysis, and debugging support
Fused Architecture for Dense and Sparse Matrix Processing in TensorFlow Lite
Comments on 'A comparison of RISC architectures' by R.S. Piepho and W.S. Wu
Ethernet for High-Performance Data centers: On the New IEEE Datacenter Bridging Standards
MicroUnity's MediaProcessor architecture
Scalable and Efficient Fine-Grained Cache Partitioning with Vantage
A Binary Translation Framework for Automated Hardware Generation
Retargetable Optimizing Compilers for Quantum Accelerators via a Multilevel Intermediate Representation
Toward Dynamic Precision Scaling
Energy-Aware Computing
Rome to Milan, AMD Continues Its Tour of Italy
On-Device Tiny Machine Learning for Anomaly Detection Based on the Extreme Values Theory
IP-Related Refusals to Deal-Part 2: Pretext and Misconduct as Standards
Performance Implications of Nonuniform Device Topologies in Scalable Heterogeneous Architectures
Accelerating Neural Network Inference With Processing-in-DRAM: From the Edge to the Cloud
Building on 35 Years toward a Vibrant Future
UltraSPARC-II/: expanding the boundaries of a system on a chip
Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache
Avoiding the legal mire [legal aspects of standards]
Simulating Whole Supercomputer Applications
Understanding Portability of a High-Level Programming Model on Contemporary Heterogeneous Architectures
Sonic Millip3De: An Architecture for Handheld 3D Ultrasound
Designing for parallel fuzzy computing
SimFlex: Statistical Sampling of Computer System Simulation
Top Picks, Columnists, and Artists
Fault-Tolerant Design of the IBM Power6 Microprocessor
Balancing Specialized Versus Flexible Computation in Brain-Computer Interfaces
Efficient, Scalable Congestion Management for Interconnection Networks
Special Issue on Hot Interconnects 29
Chicken Little Predictions
A Landscape of the New Dark Silicon Design Regime
Join a Standards Group and See the World
Five strategies for overcoming obviousness
Vertical Processing Systems: A Survey
"Designer" Logic And Symbols with Logic Cell Arrays
Speculative Decoding on the SN40L Reconfigurable Dataflow Unit
Addressing Workload Variability in Architectural Simulations
Cached DRAM for ILP Processor Memory Access Latency Reduction
A Vector Processor Based on One-Bit Microprocessors
Characterizing and Efficiently Accelerating Multimodal Generation Model Inference
Interconnect Design for Heterogeneous Integration of Chiplets in the AMD Instinct MI300X Accelerator
A new hierarchical disk architecture
uGEMM: Unary Computing for GEMM Applications
ΔNN: Power-Efficient Neural Network Acceleration Using Differential Weights
Micro-Cobol: A Data Processing Language for Microprocessor Systems
Engineering Support System User Requirements
Using Bulk Built-in Current Sensors to Detect Soft Errors
Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation
SpecHLS: Speculative Accelerator Design Using High-Level Synthesis
Evaluating Overheads of Multibit Soft-Error Protection in the Processor Core
Fat Caches for Scale-Out Servers
AVIO: Detecting Atomicity Violations via Access-Interleaving Invariants
Replica management for fault-tolerant systems
Denver: Nvidia's First 64-bit ARM Processor
Real-Time Object Recognition with Neuro-Fuzzy Controlled Workload-Aware Task Pipelining
Implementing degradable processing arrays
BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28-nm CMOS
Rock: A High-Performance Sparc CMT Processor
Storage in the power PC
Shifting register windows
The Impact of Dynamically Heterogeneous Multicore Processors on Thread Scheduling
Second-sourcing CPUs - Emulation, Ethics, And Electropolitics
Bridging Python to Silicon: The SODA Toolchain
Networking standards and russell's revisionism (review of, "Open standards and the digital age: history, ideology, and networks, russel, a.; 2014)[book review]
AMD Ryzen 7040 Series
Patent Claims Revisited: Examiners and Trolls
The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future
UltraSparc I: a four-issue processor supporting multimedia
Hung up on AT&T
The message-driven processor: a multicomputer processing node with efficient mechanisms
Accelerator Integration for Open-Source SoC Design
The PowerPC user instruction set architecture
Cintia: a neuro-fuzzy real-time controller for low-power embedded systems
The 68040 processor. I. Design and implementation
Large-Scale Cost-Effective Packaging
Designing the PowerPC 60X bus
Application-Specific IC Design Technologies - A System Designer's Overview
A Multimicrocomputer-based Structure for Computer Networking
Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors
Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance
A Next-Generation Cryogenic Processor Architecture
A fine-grain architecture for relational database aggregation operations
FFT Implementation Alternatives in Advanced Measurement Systems
Figure-ground segregation using an analog VLSI chip
Temperature-Aware Computer Systems: Opportunities and Challenges
3D Integration for Introspection
Accelerating Deep Learning Using Interconnect-Aware UCX Communication for MPI Collectives
Optical correlators for space applications: prospects and problems
A Single-Shot Generalized Device Placement for Large Dataflow Graphs
Pricing Internet Access (Micro Economics)
Localized Congestion Control in Advanced Switching Interconnects
CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM
Context-Sensitive Decoding: On-Demand Microcode Customization for Security and Energy Management
Top Picks from the 2013 Computer Architecture Conferences
UCIe Standard: Enhancing Die-to-Die Connectivity in Modern Packaging
HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms
Temperature Variation Characterization and Thermal Management of Multicore Architectures
Micro law-sweat equity investments
Optimized Solution to Accelerate in Hardware an Intra H.264/SVC Video Encoder
Puss in Boots: Formalizing Arm's Virtual Memory System Architecture
Applying Anticipatory Text Selection in a Writing Aid for People with Severe Motor Impairment
On-Chip Interconnection Architecture of the Tile Processor
A general-purpose CMOS associative processor IC and system
Memory Channel Network for PCI
Optimizing NVMe Storage for Large-Scale Deployment: Key Technologies and Strategies in Alibaba Cloud
Color processing in digital cameras
IEEE 1394: status and growth path
SeaStar Interconnect: Balanced Bandwidth for Scalable Performance
Range Translations for Fast Virtual Memory
Temporal Computing With Superconductors
An Incoming World of Decoupling Siliconomy
Energy Scavenging with Shoe-Mounted Piezoelectrics
ArchExplorer for Automatic Design Space Exploration
A fuzzy controller with an optimized defuzzification algorithm
Appropriate and inappropriate legal protection of user interfaces and screen displays. V. How different forms of copyright protection interact with policy
Harsh Chips, but a Grateful Good-Bye
A birthday even a curmudgeon could love
Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation
IP-related Refusals to Deal: Part 2 1/2: A Postscript
From the Editor in Chief: Welcome A-Board
Dark Silicon [Guest editors' introduction]
Cachet: Low-Overhead Integrity Verification on Metadata Cache in Secure Nonvolatile Memory Systems
Hardware Partitioning for Big Data Analytics
Design Validation of Embedded Dependable Systems
Kernel-to-User-Mode Transition-Aware Hardware Scheduling
The transputer T414 instruction set
Uncertain<T>: Abstractions for Uncertain Hardware and Software
Server Engineering Insights for Large-Scale Online Services
A Golden-Free Approach to Detect Trojans in COTS Multi-PCB Systems
Six Infrastructure Trends
The FTT-CAN Protocol for Flexibility in Safety-Critical Systems
Moore Meets Malthus in Multiples
A Wireless Network in MosquitoNet
Micro law-glitches left in software copyright system
System effects of interprocessor communication latency in multicomputers
Engineering Support System Software
The TigerSHARC DSP Architecture
Interaction Cost: For When Event Counts Just Don't Add Up
A Scalable High-Performance Computing Solution for Networks on Chips
Beyond Wires: The Future of Interconnects
SOI Technology for Future High-Performance Smart Cards
Composition of Experts on the SN40L Reconfigurable Dataflow Unit
An Open RF-Digital Interface for Software-Defined Radios
Informal Standards Groups
E-Booster: A Field-Programmable Gate Array-Based Accelerator for Secure Tree Boosting Using Additively Homomorphic Encryption
Hierarchical Coding of Microcomputers for High-Level Architecture
Computer Architecture: Challenges and Opportunities for the Next Decade
The future will soon be here
Loihi: A Neuromorphic Manycore Processor with On-Chip Learning
Virtual prototyping of embedded microcontroller-based DSP systems
MP3 Optimization Exploiting Processor Architecture and using Better Algorithms
Understanding Acceleration Opportunities at Hyperscale
The Xbox One System on a Chip and Kinect Sensor
Steve Jobs and the Economics of One Entrepreneur
Smart Agriculture and Smart Memories
Polarized Routing for Large Interconnection Networks
Message-routing systems for transputer-based multicomputers
Low-Precision Hardware Architectures Meet Recommendation Model Inference at Scale
A fixed-point DSP for graphics engines
Express Virtual Channels with Capacitively Driven Global Links
Speculative Synchronization: Programmability and Performance for Parallel Codes
AAI Asks FTC to Investigate RAND Issues Concerning Digital TV Standard
CXL-GPU: Pushing GPU Memory Boundaries with the Integration of CXL Technologies
Silicon MEMS Oscillators for High-Speed Digital Systems
Performance analysis and validation of the picoJava processor
A comparison of RISC architectures
SyncLink: high-speed DRAM for the future
Developing the WTL3170/3171 Sparc floating-point coprocessors
ReLeQ : A Reinforcement Learning Approach for Automatic Deep Quantization of Neural Networks
Exploring Trends to Ride Artificial Intelligence's Explosive Growth Trajectory
2016 Maurice Wilkes Award Given to Timothy Sherwood
Word Processing with On-Line Script Recognition
Multicore: The View from Europe
Systems for Very Large-Scale Computing
Issues and Trends in High-Performance Processor Cores
Packet-switched optical networks
The Next Challenge
Special Issue on Mobile Systems
Licensing IP embodied in standards, Part 2
Bespoke Processors for Applications with Ultra-Low Area and Power Constraints
MicroLaw-protecting hardware against competition by copyrighting it as a compilation of data
TRUSS: A Reliable, Scalable Server Architecture
Volta: Performance and Programmability
Token Coherence: A New Framework for Shared-Memory Multiprocessors
Emerging System Interconnects Enabling More Opportunities Than Ever!
Alternative Computing Designs and Technologies
Not a mellifluous march to maturity
A reconfigurable fuzzy neural network with in-situ learning
Hardware requirements for neural network pattern classifiers: a case study and implementation
Compression Analysis for BlueField-2/-3 Data Processing Units: Lossy and Lossless Perspectives
Future Directions in Computer Architecture Research
Energy-Efficient Parallel Interconnects for Chiplet Integration
An Introduction to the V-System
Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability
Assessing Fast Network Interfaces
SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization
Model-Based System Development: An Approach to Building X-by-Wire Applications
Architectures within the ESPRIT SPAN project
RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures
A Disaggregated Memory System for Deep Learning
The ADSP-2100 DSP Microprocessor
Analog VLSI system for active drag reduction
The Cordic Magnification Function
Approximate Fair Allocation of Link Bandwidth
All Bilski Briefs Filed and Case Set for Oral Argument
The MAJC Architecture: A Synthesis of Parallelism and Scalability
A digital signal processor with IEEE floating-point arithmetic
The Pax parallel computer
Archetypes of Risky Decisions
MRCA 2.0: An Area-Optimized Multigrained Reconfigurable Cryptographic Accelerator for Securing Blockchain-Based Internet of Things Systems
From Block to Byte: Transforming PCIe Solid-State Devices With Compute Express Link Memory Protocol and Instruction Annotation
Programmable DDRx Controllers
Summer Cleanup
Trends in low-cost, high-performance substrate technology
Circuits and Architectures for In-Memory Computing-Based Machine Learning Accelerators
Hidden Potential Within Video Game Consoles
With New Memories Come New Challenges
High-Quality Fault Resiliency in Fat Trees
Looking Back, Looking Ahead
Living in the Era of Impatience
So many books
Celebrating Chips and Architectures [Guest Editor's Introduction]
Enjoy These Top Picks, While You Work From Home!
Multiplexed buses: the endian wars continue
Simulating a function of visual peripheral processes with an analog VLSI network
Markets for Technology
Jumping on Bandwagons
Robust On-Chip Communication
A Performance Analysis of MC68020-based Systems
MBus: A System Integration Bus for the Modular Microscale Computing Class
Prefix Segregation Scheme for a TCAM-Based IP Forwarding Engine
Broadcom mediaDSP: A Platform for Building Programmable Multicore Video Processors
Who Invented Hyperlinks? (Micro Law)
Division and square root: choosing the right implementation
Derek Chiou
Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake
A Big Payoff
A Hierarchical Test Methodology for Systems on Chip
A Comparison of Single-Ended, NRZ Unidirectional Signaling and Single-Ended, NRZ Simultaneous-Bidirectional Signaling for Die-to-Die Links
Web Search for a Planet: The Google Cluster Architecture
The Alpha 21264 microprocessor
Quantum Computers for High-Performance Computing
Special Issue on Top Picks From the 2023 Computer Architecture Conferences
Text-to-speech conversion on a personal computer
Supplemental Cryptographic Hardware for Smart Cards
Dealing with globalization
A System Executive for Real-Time Microcomputer Programs
Has the Time for EMT Finally Come?
Big Changes [Micro Review]
Varifocal Storage: Dynamic Multiresolution Data Storage
The Memristive Boltzmann Machines
Xtensa: A Configurable and Extensible Processor
A Microcomputer-based Control System for a Three-Joint Robot Arm
Using heavy-ion radiation to validate fault-handling mechanisms
High-Throughput Programmable Cryptocoprocessor
Compute-Enabled CXL Memory Expansion for Efficient Retrieval Augmented Generation
The Oracle Sparc T5 16-Core Processor Scales to Eight Sockets
3D graphics processor chip set
The Intel IA-64 Compiler Code Generator
Private Returns on Technology Adoption
Cool Chips
How Many VAXes Fit in the Palms of Your Hands?
Surviving the Slump, Building the Future
Performance Characterizations and Usage Guidelines of Samsung CMM-H
Design Tradeoffs in CXL-Based Memory Pools for Public Cloud Platforms
A Polymorphous Computing Fabric
Dynamic Capacity Service for Improving CXL Pooled Memory Efficiency
Starfire: extending the SMP envelope
Computer architecture research: Shifting priorities and newer challenges
BugNet: Recording Application-Level Execution for Deterministic Replay Debugging
Hardware approaches to cache coherence in shared-memory multiprocessors, Part 1
On-Device Customization of Tiny Deep Learning Models for Keyword Spotting With Few Examples
A pipelined interface for high floating-point performance with precise exceptions
System Green
Parallel Fiber-Optic SCI Links
Computer analysis of the myoelectric signal
Ink Jet Printing of Japanese Kanji Characters
The 80387 And Its Applications
Sirius Implications for Future Warehouse-Scale Computers
A safe, accurate intravenous infusion control system
Peripheral hardware and a hands-on multitasking lab
Cascade Lake: Next Generation Intel Xeon Scalable Processor
Deep submicron microprocessor design issues
Top Picks From the 2020 Computer Architecture Conferences
An ASIC chip set for parallel fuzzy database mining
A Low-Cost Distributed Architecture for Telecommunicaion Systems
Novel Composable and Scaleout Architectures Using Compute Express Link
Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads