yusuke1997/dblp-id-title huggingface dataset:
A Comparative Study Between Static and Dynamic Sleep Signal Generation Techniques for Leakage Tolerant Designs
Sensing circuit for on-line detection of delay faults
A variable-radix digit-serial design methodology and its application to the discrete cosine transform
Low-power and area-efficient FIR filter implementation suitable for multiple taps
Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches
Efficient VLSI for Lempel-Ziv compression in wireless data communication networks
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM
Highly Available Packet Buffer Design With Hybrid Nonvolatile Memory
Resolution of Diagnosis Based on Transition Faults
COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits
Speeding Up PEEC Partial Inductance Computations Using a QR-Based Algorithm
Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction
A 50-MHz dB-linear programmable-gain amplifier with 98-dB dynamic range and 2-dB gain steps for 3 V power supply
Guest Editorial Introduction to the Special Issue on the 1995 IEEE ASIC Conference
Achieving Theoretical Limit of SFDR in Pipelined ADCs
FTQLS: Fault-Tolerant Quantum Logic Synthesis
Approximate Memory Compression
Memory-Hierarchical and Mode-Adaptive HEVC Intra Prediction Architecture for Quad Full HD Video Decoding
A Predictive and Accurate Interconnect Density Function: The Core of a Novel Interconnect-Centric Prediction Engine
Fast Performance Analysis for NoCs With Weighted Round-Robin Arbitration and Finite Buffers
A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator
Transition Fault Simulation Considering Broadside Tests as Partially-Functional Broadside Tests
Parallel and Serial Computation in Nanomagnet Logic: An Overview
Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes
Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage
Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores
A Low Error and High Performance Multiplexer-Based Truncated Multiplier
A system for production use of high-level synthesis
Electrical Characterization for Intertier Connections and Timing Analysis for 3-D ICs
Analysis of dual-V T SRAM cells with full-swing single-ended bit line sensing for on-chip cache
An R2R-DAC-Based Architecture for Equalization-Equipped Voltage-Mode PAM-4 Wireline Transmitter Design
On Efficient Retiming of Fixed-Point Circuits
On-line test for fault-secure fault identification
Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach
Improving System-Level Lifetime Reliability of Multicore Soft Real-Time Systems
Write Variation Aware Buffer Assignment for Improved Lifetime of Non-Volatile Buffers in On-Chip Interconnects
S 3 A-NPU: A High-Performance Hardware Accelerator for Spiking Self-Supervised Learning With Dynamic Adaptive Memory Optimization
A digit-serial multiplier for finite field GF(2 m )
Alternative Architectures Toward Reliable Memristive Crossbar Memories
Low Flicker Dimmable Multichannel LED Driver With Matrix-Style DPWM and Precise Current Matching
Concurrent error detection and fault-tolerance in linear analog circuits using continuous checksums
Accelerating Unstructured Sparse DNNs via Multilevel Partial Sum Reduction and PE Array-Level Load Balancing
Design of a CNN Accelerator for Multitask EEG Signal Classification Based on RISC-V
Parallel On-Chip Power Distribution Network Analysis on Multi-Core-Multi-GPU Platforms
Design of Ternary Logic Combinational Circuits Based on Quantum Dot Gate FETs
Implementation of Compact Polyphase Channel-Select Filters for Multistandard Broadcasting
Cascade and LC Ladder-Based Filter Realizations Using Synchronous Time-Mode Signal Processing
An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC
A Fast Cross-Layer Dynamic Power Estimation Method by Tracking Cycle-Accurate Activity Factors With Spark Streaming
A Search Algorithm for the Worst Operation Scenario of a Cross-Point Phase-Change Memory Utilizing Particle Swarm Optimization
Diagnosis Framework for Locating Failed Segments of Path Delay Faults
Characterization of the Proximity Effect From Tungsten TSVs on 130-nm CMOS Devices in 3-D ICs
Stability of On-Chip Power Delivery Systems With Multiple Low-Dropout Regulators
A 56-Gb/s, 6.3-pJ/bit PAM-4 DFB Laser Driver Incorporating Asymmetric Equalization and Integrated CDR in 28 nm CMOS
A Low-Complexity Hybrid Readout Circuit for Lidar Receiver
A Fault-Tolerant Technique Using Quadded Logic and Quadded Transistors
Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation
Utilizing Circuit Structure for Scan Chain Diagnosis
Gate oxide leakage current analysis and reduction for VLSI circuits
Design and optimization of dual-threshold circuits for low-voltage low-power applications
A compositional model for the functional verification of high-level synthesis results
Working-zone encoding for reducing the energy in microprocessor address buses
A 2.4-GHz -33-dBm Sensitivity Battery-Free RF Energy Harvesting System With 17-dB Input Power Range
Application of instruction analysis/scheduling techniques to resource allocation of superscalar processors
ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits
A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
Power-delay characteristics of CMOS adders
Minimization of switching activities of partial products for designing low-power multipliers
A Low-Power PAM4 Receiver With an Adaptive Variable-Gain Rectifier-Based Decoder
Timing Yield Slack for Timing Yield-Constrained Optimization and Its Application to Statistical Leakage Minimization
Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis
Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues
Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects
New Architectural Design of CA-Based Codec
Large Delay Analog Trojans: A Silent Fabrication-Time Attack Exploiting Analog Modalities
Energy-Aware Interconnect Resource Reduction Through Buffer Access Manipulation for Data-Centric Applications
A nonseparable VLSI architecture for two-dimensional discrete periodized wavelet transform
Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches
A Generic Dynamic Responding Mechanism and Secure Authentication Protocol for Strong PUFs
Digital Predistortion for Wide Dynamic Power Range Quadrature Switched-Capacitor Power Amplifiers Using Self-Adaptive Residual LSTM Neural Network
A 12.5-Gb/s Near-Ground Transceiver Employing a MaxEye Algorithm-Based Adaptation Technique
Cerebron: A Reconfigurable Architecture for Spatiotemporal Sparse Spiking Neural Networks
CINELL: An Energy-Efficient Compute-In/Near-Memory eDRAM Processor for Sparse Transformer-Based Large Language Models
Exploring the 3-D Integrability of Perpendicular Nanomagnet Logic Technology
Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problem
A Novel Robust and Low-Leakage SRAM Cell With Nine Carbon Nanotube Transistors
Figures of merit to characterize the importance of on-chip inductance
Unifying simulation and execution in a design environment for FPGA systems
Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems
High-Performance Elliptic Curve Scalar Multiplication Architecture Based on Interleaved Mechanism
ARCHGEN: Automated synthesis of analog systems
A Resistor-Based Sub-1-V CMOS Smart Temperature Sensor for VLSI Thermal Management
An architectural co-synthesis algorithm for distributed, embedded computing systems
Integrated Power and Clock Distribution Network
Design and Implementation of Encryption/Decryption Architectures for BFV Homomorphic Encryption Scheme
Sleepy Stack Leakage Reduction
A Flexible and Efficient Real-Time ORB-Based Full-HD Image Feature Extraction Accelerator
Complexity Analysis and Efficient Implementations of Bit Parallel Finite Field Multipliers Based on Karatsuba-Ofman Algorithm on FPGAs
Polymorphic Configuration Architecture for CGRAs
An Algorithm-Centric Energy-Aware Design Methodology
High-Frequency CMOS Active Inductor: Design Methodology and Noise Analysis
IR-Drop Aware Clustering Technique for Robust Power Grid in FPGAs
A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations
A 9.6-nW Wake-Up Timer With RC-Referenced Subharmonic Locking Using Dual Leakage-Based Oscillators
A Study of the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-Based Neuromorphic Systems
Vector-Matrix Multiply and Winner-Take-All as an Analog Classifier
RTHS: A Low-Cost High-Performance Real-Time Hardware Sorter, Using a Multidimensional Sorting Algorithm
Multimode power modeling and maximum-likelihood estimation
Static Test Data Volume Reduction Using Complementation or Modulo- M Addition
Reducing Wire and Energy Overheads of the SMART NoC Using a Setup Request Network
Interstice: Inverter-Based Memristive Neural Networks Discretization for Function Approximation Applications
Noise constrained transistor sizing and power optimization for dual Vs t domino logic
A Two-Stage CMOS Amplifier With High Degree of Stability for All Capacitive Loads
High-Speed Architectures for Parallel Long BCH Encoders
Speed/Area-Efficient ECC Processor Implementation Over GF(2 m ) on FPGA via Novel Algorithm-Architecture Co-Design
Run-Time Management for Multicore Embedded Systems With Energy Harvesting
A 28-nm Cascode Current Mirror-Based Inconsistency-Free Charging-and-Discharging SRAM-CIM Macro for High-Efficient Convolutional Neural Networks
Design of Efficient Content Addressable Memories in High-Performance FinFET Technology
System-level power-performance tradeoffs for reconfigurable computing
Corrections to "Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" [May 10 689-696]
Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
Reducing power by optimizing the necessary precision/range of floating-point arithmetic
Novel Circuit-Level Model for Gate Oxide Short and its Testing Method in SRAMs
Sub-1-V BGR and POR Hybrid Circuit With 2.25-μA Current Dissipation and Low Complexity
An Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAM
SCAR: Power Side-Channel Analysis at RTL Level
A 4th-Order 4-Bit Continuous-Time ΔΣ ADC Based on Active-Passive Integrators With a Resistance Feedback DAC
Exploiting Memory Soft Redundancy for Joint Improvement of Error Tolerance and Access Efficiency
Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area
TCAD-Assisted Capacitance Extraction of FinFET SRAM and Logic Arrays
Energy minimization for real-time systems with (m, k)-guarantee
Resource Optimization in Polyphase-Filter STFT Based on Time-Multiplexed Constant Multiplication
Instruction-based system-level power evaluation of system-on-a-chip peripheral cores
A Flexible Architecture for Precise Gamma Correction
A Hybrid Domain and Pipelined Analog Computing Chain for MVM Computation
One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique
An Adaptive Mechanism for Designing Efficient Snoop Filters
A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide Voltage-Range SRAMs
Three-Dimensional nand Flash for Vector-Matrix Multiplication
Iris Biometrics for Embedded Systems
A Novel High-Throughput FFT Processor With a Block-Level Pipeline for 5G MIMO OFDM Systems
A New Self-Healing Methodology for RF Amplifier Circuits Based on Oscillation Principles
A Sensitivity Analysis of Power Signal Methods for Detecting Hardware Trojans Under Real Process and Environmental Conditions
Application Mapping and Scheduling for Network-on-Chip-Based Multiprocessor System-on-Chip With Fine-Grain Communication Optimization
High-Throughput Low-Power Area-Efficient Outphasing Modulator Based on Unrolled and Pipelined Radix-2 CORDIC
Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesis
Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon Codes
A low-power adder operating on effective dynamic data ranges
SRAM BL Predriven Write Operation With Row and Voltage Auto-Tracking Replica BL in Resistance-Dominated Technology Nodes
Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs
Multilevel reverse most-significant carry computation
A DAC With an Impedance Attenuator and Distortion Analysis Using Volterra Series
A Mesh-Structured Scalable IPsec Processor
Energy Efficient Approximate Arithmetic for Error Resilient Neuromorphic Computing
High-Speed Compute-Efficient Bandit Learning for Many Arms
Realistic scalability of noise in dynamic circuits
M2M: A Fine-Grained Mapping Framework to Accelerate Multiple DNNs on a Multi-Chiplet Architecture
Power-Up Sequence Control for MTCMOS Designs
Understanding the Potential and the Limits of Germanium pMOSFETs for VLSI Circuits From Experimental Measurements
A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect
F-DNA: Fast Convolution Architecture for Deconvolutional Network Acceleration
A Sub-0.9-ps Static Phase Offset 500 MHz Delay-Locked Loop With a Large Gain Phase Detector
Parallel and Scalable Transient Simulator for Power Grids via Waveform Relaxation (PTS-PWR)
An Adaptive PAM-4 Analog Equalizer With Boosting-State Detection in the Time Domain
Driver modeling and alignment for worst-case delay noise
Vulnerability Analysis of Trivium FPGA Implementations
A Low Area Overhead NBTI/PBTI Sensor for SRAM Memories
Understanding the Effect of Process Variations on the Delay of Static and Domino Logic
An electromigration and thermal model of power wires for a priori high-level reliability prediction
A Pay-Per-ISE RISC-V Processor With Hardware-Assisted Orthogonal Obfuscation
Write Order-Based Garbage Collection Scheme for an LBA Scrambler Integrated SSD
A bus energy model for deep submicron technology
Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic
Power-Supply Noise Reduction Using Active Inductors in Mixed-Signal Systems
Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI
ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs
Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks
Fast Power- and Slew-Aware Gated Clock Tree Synthesis
Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node
FleXilicon Architecture and Its VLSI Implementation
A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL
MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications
NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing
Iterative Linear Interpolation Based on Fuzzy Gradient Model for Low-Cost VLSI Implementation
BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural Networks
A Low Overhead High Test Compression Technique Using Pattern Clustering With $n$-Detection Test Support
Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units
Fully Monolithic Cellular Buck Converter Design for 3-D Power Delivery
Recursive Approach to the Design of a Parallel Self-Timed Adder
Achieving Energy Efficiency for Near-Threshold Circuits Through Postfabrication Calibration and Adaptation
Sleep switch dual threshold Voltage domino logic with reduced standby leakage current
Area-Efficient Pipeline Architecture for Serial Real-Valued Fast Fourier Transform
Correction to "A Digitally Programmable Delay Element: Design and Analysis"
A Second-Order Noise Shaping SAR ADC With Parallel Multiresidual Integrator
A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise
Power-Efficient Analog Hardware Architecture of the Learning Vector Quantization Algorithm for Brain Tumor Classification
An integrated technology CAD system for process and device designers
The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout
A 30-W 90% Efficiency Dual-Mode Controlled DC-DC Controller With Power Over Ethernet Interface for Power Device
A 1.2-V Piecewise Curvature-Corrected Bandgap Reference in 0.5 μ m CMOS Process
Asymptotically Linear Analysis and Gate Probability Allocation Schemes in Probabilistic Circuits
On the Efficacy of Through-Silicon-Via Inductors
An overview of the competitive and adversarial approaches to designing dynamic power management strategies
Unlimited Vector Processing for Wireless Baseband Based on RISC-V Extension
Power Network Optimization Based on Link Breaking Methodology
Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay
Reduction of coupling effects by optimizing the 3-D configuration of the routing grid
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction
Combined data-driven and event-driven scheduling technique for fast distributed cosimulation
An Integrated Approach to Thermal Management in High-Level Synthesis
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
Analog Automatic Test Pattern Generation for Quasi-Static Structural Test
On the Resiliency of Protected Masked S-Boxes Against Template Attack in the Presence of Temperature and Aging Misalignments
A 1-GS/s 12-bit Single-Channel Pipelined ADC in 28-nm CMOS With Input-Split Fully Differential Ring Amplifier
A 10-Gb/s 20-ps Delay-Range Digitally Controlled Differential Delay Element in 45-nm SOI CMOS
Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems
A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS
Performance Evaluation and Optimization of HBM-Enabled GPU for Data-Intensive Applications
Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors
Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip
Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU
ADDLL for Clock-Deskew Buffer in High-Performance SoCs
Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design
Formal Performance Analysis for Faulty MIMO Hardware
SPICED+: Syntactical Bug Pattern Identification and Correction of Trojans in A/MS Circuits Using LLM-Enhanced Detection
On concurrent error location and correction of FFT networks
Novel Probabilistic Combinational Equivalence Checking
Time-Based All-Digital Technique for Analog Built-in Self-Test
Multilevel hypergraph partitioning: applications in VLSI domain
Guest Editorial Introduction to the Special Issue on the Eighth IEEE International Symposium on System Synthesis
An Active Silicon Interposer With Low-Power Hybrid Wireless-Wired Clock Distribution Network for Many-Core Systems
The Triptych FPGA architecture
Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network
Operation-Dependent Frequency Scaling Using Desynchronization
Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation
An Area/Power-Efficient ΔΣ Modulator Based on Dynamic-Boost Inverter for Multichannel Sensor Applications
Energy-Aware Adaptive Multi-Exit Neural Network Inference Implementation for a Millimeter-Scale Sensing System
Design of Low-Cost and High-Accurate 8-bit Logarithmic Floating-Point Arithmetic Circuits
Stochastic Networked Computation
Exact memory size estimation for array computations
mwJFS: A Multiwrite-Mode Journaling File System for MLC NVRAM Storages
A Bidirectional Nonlinearly Coupled QVCO With Passive Phase Interpolation for Multiphase Signals Generation
Power-aware operating systems for interactive systems
Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis
Estimating architectural resources and performance for high-level synthesis applications
A survey of power estimation techniques in VLSI circuits
Compiler-directed scratch pad memory optimization for embedded multiprocessors
A Dynamic Leakage and Slew Rate Compensation Circuit for 40-nm CMOS Mixed-Voltage Output Buffer
Differential BiCMOS logic circuits: fault characterization and design-for-testability
Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs
A Gain-Controlled, Low-Leakage Dickson Charge Pump for Energy-Harvesting Applications
Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style
A Design of Autonomous Error-Tolerant Architectures for Massively Parallel Computing
Golden-Chip-Free Hardware Trojan Detection Through Quiescent Thermal Maps
Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs
A 200-V Half-Bridge Monolithic GaN Power IC With High-Speed Level Shifter and dV S /dt Noise Immunity Enhancement Structure
SoC with an integrated DSP and a 2.4-GHz RF transmitter
Initialization-Based Test Pattern Generation for Asynchronous Circuits
Multispectral Transmission Map Fusion Method and Architecture for Image Dehazing
A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory
Nonrandom Device Mismatch Considerations in Nanoscale SRAM
A Linearity-Improved 8-bit 320-MS/s SAR ADC With Metastability Immunity Technique
Low-Precision Mixed-Computation Models for Inference on Edge
A Novel Two-Stage Timing Mismatch Calibration Technique for Time-Interleaved ADCs
ADC/DAC-Free Analog Acceleration of Deep Neural Networks With Frequency Transformation
Constructions of Memoryless Crosstalk Avoidance Codes Via ${\cal C}$ -Transform
RHT_NoC: A Reconfigurable Hybrid Topology Architecture for Chiplet-Based Multicore System
A Dual-Multiplication-Mode and Reconfigurable Digital Compute-in-Memory Macro Using Precharge-Controlled 4T1C eDRAM
A software/reconfigurable hardware SAT solver
A high-density and low-power charge-based Hamming network
Low-Complexity High-Throughput QR Decomposition Design for MIMO Systems
Microarchitecture Configurations and Floorplanning Co-Optimization
A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control
A programmable temperature monitoring device for tagging small fish: a prototype chip development
Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits
Mapping Spiking Neural Networks to Neuromorphic Hardware
Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance
Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors
Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns
Tunneling-Based Cellular Nonlinear Network Architectures for Image Processing
A Low-Cost and Triple-Node-Upset Self-Recoverable Latch Design With Low Soft Error Rate
A Multiple-Radix MAP-Decoder Microarchitecture and Its ASIC Implementation for Energy-Efficient and Variable-Throughput Applications
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits
Design of FPGA interconnect for multilevel metallization
Design of Temperature-Aware Low-Voltage 8T SRAM in SOI Technology for High-Temperature Operation (25 %C-300 %C)
VLSI implementation of discrete wavelet transform
An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs
A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads
ReAdapt-II: Energy-Quality Optimizations for VLSI Adaptive Filters Through Automatic Reconfiguration and Built-In Iterative Dividers