yusuke1997/dblp-id-title huggingface dataset:
A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System
New associate editor
A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology
A High Common-Mode Transient Immunity GaN-on-SOI Gate Driver With Quad-Drive Control Technique for High dV/dt 1700-V SiC Power Switch
MRAM Cell Technology for Over 500-MHz SoC
A Resistor-Based Temperature Sensor With a 0.13 pJ $\cdot$ K2 Resolution FoM
SAW-Less Direct RF Transmitter With Multimode Noise Shaping and Tri-Level Time-Approximation Filter
Introduction to the Special Section on the 26th Bipolar/BiCMOS Circuits and Technology Meeting
A Constant-Energy-Packet-Extraction-Based MPPT Technique With 98% Average Extraction Efficiency for Wide Range Generic Ambient Energy Scavenging Supporting 1000 × Source Resistance Range
A robust 8F 2 ferroelectric RAM cell with depletion device (DeFeRAM)
A ULP Long-Range Active-RF Tag With Automatically Calibrated Antenna-TRX Interface
Design of a High Performance 2-GHz Direct-Conversion Front-End With a Single-Ended RF Input in 0.13 µm CMOS
Low-power dividerless frequency synthesis using aperture phase detection
A 25-MHz Four-Phase SAW Hysteretic Control DC-DC Converter With 1-Cycle Active Phase Count
Video CMOS power buffer with extended linearity
A 3 , ˟, 3.8 Gb/s Four-Wire High Speed I/O Link Based on CDMA-Like Crosstalk Cancellation
Surfing Pipelines: Theory and Implementation
A 46.6 μg/√Hz Single-Chip Accelerometer Exploiting a DTC-Assisted Chopper Amplifier
A neuro-stimulus chip with telemetry unit for retinal prosthetic device
Dual-modulus 127/128 FOM enhanced prescaler design in 0.35-μm CMOS technology
A 134-Pixel CMOS Sensor for Combined Time-of-Flight and Optical Triangulation 3-D Imaging
Editorial New Associate Editor
A broadband low-noise front-end amplifier for ultra wideband in 0.13-μm CMOS
A 5.8-Gb/s Adaptive Integrating Duobinary DFE Receiver for Multi-Drop Memory Interface
17 GHz RF Front-Ends for Low-Power Wireless Sensor Networks
CHIMERA: A Field-Programmable Mixed-Signal IC With Time-Domain Configurable Analog Blocks
A macro analysis of soft errors in static RAMs
A Single-Chip 10-Band WCDMA/HSDPA 4-Band GSM/EDGE SAW-less CMOS Receiver With DigRF 3G Interface and +90 dBm IIP2
Circuit modeling of bipolar transistors for BiCMOS
A 14-b 20-Msamples/s CMOS pipelined ADC
Low-Power 2.4-GHz Transceiver With Passive RX Front-End and 400-mV Supply
A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link
C3SRAM: An In-Memory-Computing SRAM Macro Based on Robust Capacitive Coupling Computing Mechanism
A Broadband Stacked Power Amplifier in 45-nm CMOS SOI Technology
K/Ka-Band Hybrid-Packaged Four-Element Four-Beam Phased-Array Transmitter and Receiver Front-Ends With Optimized Beamforming Passive Networks
Introduction to the Special Issue on the Third IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)
A 1.2-V 37-38.5-GHz Eight-Phase Clock Generator in 0.13-µm CMOS Technology
A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier
A "divide and conquer" technique for implementing wide dynamic range continuous-time filters
SNAP: An Efficient Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference
110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock
A High-Q Resonant Inductive Link Transmit Driver With Adaptive-Predictive Phase-Continuous Tuning and Deviation Frequency Calibration for Enhanced FSK/PSK Modulation and Power Transfer
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop
TIMAQ: A Time-Domain Computing-in-Memory-Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs
A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica
A dynamic scaling FFT processor for DVB-T applications
A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism
Practical modeling for circuit simulation
A fingerprint sensor based on the feedback capacitive sensing scheme
A Self-Resonant Boost Converter for Photovoltaic Energy Harvesting With a Tracking Efficiency >90% Over an Ultra-Wide Source Range
A 390-GHz Outphasing Transmitter in 28-nm CMOS
Post-Si Programmable ESD Protection Circuit Design: Mechanisms and Analysis
MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip
Two bandpass active filters with reduced sensitivities
A 71.5-dB SNDR 475-MS/s Ringamp-Based Pipelined SAR ADC With On-Chip Bit-Weight Calibration
A Single BJT Bandgap Reference With Frequency Compensation Exploiting Mirror Pole
An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB
A Wideband Energy-Efficient Multi-Mode CMOS Digital Transmitter
Behavior analysis of CMOS D flip-flops
The multi-tanh principle: a tutorial overview
A Millimeter-Wave Polarization-Division-Duplex Transceiver Front-End With an On-Chip Multifeed Self-Interference-Canceling Antenna and an All-Passive Reconfigurable Canceller
A very-high-slew-rate CMOS operational amplifier
A Charge-Domain Fractional-N ADPLL Based on Charge-Steering Sampling
An Oversampling SAR ADC With DAC Mismatch Error Shaping Achieving 105 dB SFDR and 101 dB SNDR Over 1 kHz BW in 55 nm CMOS
An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC
A Sub-nW 93% Peak Efficiency Buck Converter With Wide Dynamic Range, Fast DVFS, and Asynchronous Load-Transient Control
A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier
A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers
Guest Editorial IEEE 2024 BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium
A 0.06 mm 2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS
A 0.28 THz Power-Generation and Beam-Steering Array in CMOS Based on Distributed Active Radiators
A Digital CMOS Architecture for a Micro-Hotplate Array
An Ultrasound ASIC With Universal Energy Recycling for >7-m All-Weather Metamorphic Robotic Vision
Ultrasonic Wake-Up With Precharged Transducers
0.5-μm CMOS circuits for demodulation and decoding of an OFDM-based digital TV signal conforming to the European DVB-T standard
A BiCMOS low-distortion 8-MHz low-pass filter
Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs
Design and Analysis of Harmonic Rejection Mixers With Programmable LO Frequency
A 200-MHz sub-mA RF front end for wireless hearing aid applications
A Blocker-Tolerant, Noise-Cancelling Receiver Suitable for Wideband Wireless Applications
A low leakage SRAM macro with replica cell biasing scheme
A 21 nV/√ Hz Chopper-Stabilized Multi-Path Current-Feedback Instrumentation Amplifier With 2 µ V Offset
An analytical maximum toggle frequency expression and its application to optimizing high-speed ECL frequency dividers
A design for high noise rejection in a pseudodifferential preamplifier for hard disk drives
A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-μm CMOS
A Sub-Baud-Rate Wireline Receiver With One-Tap DFE
A 15-mW fully integrated I/Q synthesizer for Bluetooth in 0.18-μm CMOS
Quality assurance and upgrade of analog characteristics by fast mismatch analysis option in network analysis environment
A 45 K-gate HEMT array with 35-ps DCFL and 50-ps BDCFL gates
A Bridge-Less Hybrid SSHI Rectifier With High Efficiency Over Wide Load Range for Piezoelectric Energy Harvesting
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier
Subthreshold-current reduction circuits for multi-gigabit DRAM's
A 2.4-GHz dual-mode 0.18-μm CMOS transceiver for Bluetooth and 802.11b
A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution
Energy dissipation in general purpose microprocessors
Power amplifier PAE and ruggedness optimization by second-harmonic control
InP HBT IC Technology for Terahertz Frequencies: Fundamental Oscillators Up to 0.57 THz
Enhanced write performance of a 64-mb phase-change random access memory
Millimeter-Wave Receiver With Non-Uniform Time-Approximation Filter
Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor
A highly linear and efficient differential CMOS power amplifier with harmonic control
A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator
Addition to "Design and Implementation of an Untrimmed MOSFET-Only 10-bit A/D Converter with -79-dB THD"
Features and Design Constraints for an Optimized SC Front-End Circuit for Capacitive Sensors With a Wide Dynamic Range
A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information
A Digital Polar Transmitter With DC-DC Converter Supporting 256-QAM WLAN and 40-MHz LTE-A Carrier Aggregation
Guest Editorial Introduction to the Special Section on the 2024 IEEE International Solid-State Circuits Conference (ISSCC)
A 12-b ENOB 2.5-MHz BW VCO-Based 0-1 MASH ADC With Direct Digital Background Calibration
An LCD column driver using a switch capacitor DAC
A 28-GHz Four-Channel Beamforming Front-End IC With Dual-Vector Variable Gain Phase Shifters for 64-Element Phased Array Antenna Module
Ultracompact reflective-type phase shifter MMIC at C-band with 360° phase-control range for smart antenna combining
High-Resolution Millimeter-Wave Digitally Controlled Oscillators With Reconfigurable Passive Resonators
Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference
A 0.47-1.6 mW 5-bit 0.5-1 GS/s Time-Interleaved SAR ADC for Low-Power UWB Radios
Full-Duplex Crystalless CMOS Transceiver With an On-Chip Antenna for Wireless Communication in a Hybrid Engine Controller Board
A baseband processor for impulse ultra-wideband communications
A 28.8 Mb/s 4 × 4 MIMO 3G CDMA receiver for frequency selective channels
A single-chip narrow-band frequency-domain excisor for a Global Positioning System (GPS) receiver
A Hybrid Multi-Path CMOS Magnetic Sensor With 76 ppm/°C Sensitivity Drift and Discrete-Time Ripple Reduction Loops
A 6-20 GHz Adaptive SiGe Image Reject Mixer for a Self-Healing Receiver
A Multiband Mobile Analog TV Tuner SoC With 78-dB Harmonic Rejection and GSM Blocker Detection in 65-nm CMOS
A 200-MHz 15-mW BiCMOS sample-and-hold amplifier with 3 V supply
A 56-Gb/s 50-mW NRZ Receiver in 28-nm CMOS
Design-Oriented Analysis for Miller Compensation and Its Application to Multistage Amplifier Design
Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register
Syn-STELLAR: An EM/Power SCA-Resilient AES-256 With Synthesis-Friendly Signature Attenuation
A 7.5-GHz Subharmonic Injection-Locked Clock Multiplier Featuring a 120× Multiplying Factor and 92.3-fs RMS Jitter Including Reference Spur
A 12-nm High-Density Energy-Efficient 1-Mb 2R2W Scratchpad With Local Blocks for Neural Network Applications
A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution
Energy Efficient Startup of Crystal Oscillators Using Stepwise Charging
Erratum to "A 7-bit 1.15-GS/s 2.6-bit/Cycle Asynchronous SAR ADC Using Comparator Decision Skip Technique With Background Offset Calibration"
Erratum to "A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting"
A 56-GS/s 8-bit Time-Interleaved ADC With ENOB and BW Enhancement Techniques in 28-nm CMOS
Design and fabrication of a high-dynamic-range image sensor in TFA technology
A 30.2-µ Vrms Horizontal Streak Noise 8.3-Mpixel 60-Frames/s CMOS Image Sensor With Skew-Relaxation ADC and On-Chip Testable Ramp Generator for Surveillance Camera
A Direct-Sampling Pulsed Time-of-Flight Radar With Frequency-Defined Vernier Digital-to-Time Converter in 65 nm CMOS
A bipolar low-voltage quarter-square multiplier with a resistive-input based on the bias offset technique
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology
A DC to 1-GHz differential monolithic variable-gain amplifier
A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction
Active-pull-down nonthreshold logic BiCMOS circuits for high-speed low-power applications
Introduction to the Special Section on the 2017 IEEE BCTM and IEEE CSICS Conferences
1-to-4 Analog Demultiplexer With up to 128 GS/s for Interleaving of Bandwidth-Limited Digitizers in Wireline and Optical Receivers
A 93.4% Peak Efficiency C LOAD -Free Multi-Phase Switched-Capacitor DC-DC Converter Achieving a Fast DVS up to 222.5 mV/ns
C-Transformer: An Energy-Efficient Homogeneous DNN-Transformer/SNN-Transformer Processor for Large Language Models
A Variation-Tolerant Continuous-Time Ising Machine With eDRAM-Based Spin Interaction and Leaked Negative Feedback Annealing
Start-up and frequency stability in high-frequency oscillators
A 325F 2 Physical Unclonable Function Based on Contact Failure Probability With Bit Error Rate < 0.43 ppm After Preselection With 0.0177% Discard Ratio
An Auto-Zero-Stabilized Voltage Buffer With a Quiet Chopping Scheme and Constant Sub-pA Input Current
Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adders
A flip-flop sensor array with on-spot A/D conversion
A 1.4-µW 24.9-ppm/°C Current Reference With Process-Insensitive Temperature Compensation in 0.18-µm CMOS
A 4-Mb CMOS SRAM with a PMOS thin-film-transistor load cell
An Ultra-Low-Power Polarity-Coincidence Feedback Time-Delay-to-Digital Converter for Sound-Source Localization
An Anti-Aliasing-Filter-Assisted 3rd-Order VCO-Based CTDSM With NS-SAR Quantizer
A communication scheme for analog VLSI perceptive systems
Flying-Domain DC-DC Power Conversion
A Burst-Mode Bit-Synchronization IC With Large Tolerance for Pulse-Width Distortion for Gigabit Ethernet PON
An LC-Based Clock Buffer With Tunable Injection Locking
Low-power dynamic termination scheme using NMOS diode clamping
A 128-Pixel System-on-a-Chip for Real-Time Super-Resolution Terahertz Near-Field Imaging
A 50 GHz broad-band monolithic GaAs/AlAs resonant tunneling diode trigger circuit
The Design of All-Digital Polar Transmitter Based on ADPLL and Phase Synchronized ΔΣ Modulator
A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer
A 380 MHz Direct Digital Synthesizer/Mixer With Hybrid CORDIC Architecture in 0.25 µm CMOS
Digital to RF Wideband Multi-Standard Multi-Path Transmitter
Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation
High Power Terahertz and Millimeter-Wave Oscillator Design: A Systematic Approach
A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling
A 0.69-Noise-Efficiency-Factor 55× -Preamp-Gain Dynamic Comparator With a Stacking FIA
A low-swing clock double-edge triggered flip-flop
A 0.8-mW 5-bit 250-MS/s Time-Interleaved Asynchronous Digital Slope ADC
Ultra Low-Energy Relaxation Oscillator With 230 fJ/cycle Efficiency
Programmable switched-capacitor bump equalizer architecture
A 6-ns 256-kb BiCMOS TTL SRAM
Introduction to the memory section
A rail-to-rail ping-pong op-amp
A 0.38-mW 200-kHz-BW Digital-Intensive Single-Opamp Fourth-Order Continuous-Time Delta-Sigma Modulator With Third-Order Digital Noise Coupling in 28-nm CMOS
A new model for thermal channel noise of deep-submicron MOSFETs and its application in RF-CMOS design
A 21-mW 8-b 125-MSample/s ADC in 0.09-mm 2 0.13-μm CMOS
Dual-Source Energy-Harvesting Interface With Cycle-by-Cycle Source Tracking and Adaptive Peak-Inductor-Current Control
eDRAM-CIM: Reconfigurable Charge Domain Compute-In-Memory Design With Embedded Dynamic Random Access Memory Array Realizing Adaptive Data Converters
An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS
Design and characterization of analog VLSI neural network modules
A 15-Gb/s Sub-Baud-Rate Digital CDR
A High-Efficiency 12/1-V Dual-Path Series-Capacitor Converter With Low V⋅A Metric and Full Duty Range
A 0.7- μ m BiCMOS Electrostatic Energy-Harvesting System IC
A 2.4-GHz Low-Power All-Digital Phase-Locked Loop
A Battery-Free 217 nW Static Control Power Buck Converter for Wireless RF Energy Harvesting With ά-Calibrated Dynamic On/Off Time and Adaptive Phase Lead Control
A 12.5 Gb/s Si bipolar IC for PRBS generation and bit error detection up to 25 Gb/s
A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology
5-GHz Oscillator Array With Reduced Flicker Up-Conversion in 0.13-$muhboxm$CMOS
A self-calibrating Hall sensor IC with direction detection
Low-Power CMOS Equalizer Design for 20-Gb/s Systems
A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique
A 94.4% Peak Efficiency Coupled-Inductor Hybrid Step-Up Converter With Load-Independent Output Voltage Ripple
A 200-μW Interface for High-Resolution Eddy-Current Displacement Sensors
1.5-V high-performance SC filters in BiCMOS technology
A 48-16-MHz CMOS SC decimation filter
A 0.9 V 0.4-6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration
A Fully Integrated 60-GHz CMOS Transceiver Chipset Based on WiGig/IEEE 802.11ad With Built-In Self Calibration for Mobile Usage
Timing verification of dynamic circuits
A flash memory technology with quasi-virtual ground array for low-cost embedded applications
Widely Tunable 4th Order Switched G m -C Band-Pass Filter Based on N-Path Filters
Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC
Radiation Tolerance Techniques for a 1.6 Gb/s, 8 K and 4 K Low-Density Parity-Check Encoder
A Cross-Coupled Hybrid Switched-Capacitor Buck Converter With Extended Conversion Range and Enhanced DCR Loss Reduction
A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure
Input waveform slope effects in CMOS delays
An agile ISM band frequency synthesizer with built-in GMSK data modulation
A Commutated-LC RF Broadband Delay Circuit
Ultrafast compact 32-bit CMOS adders in multiple-output domino logic
Frequency and Power Scaling in mm-Wave Colpitts Oscillators
A 65-nm RRAM Compute-in-Memory Macro for Genome Processing
A Multiphase Buck Converter With a Rotating Phase-Shedding Scheme For Efficient Light-Load Control
A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference
A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable reference bit-line voltage scheme using a fatigue-free reference capacitor
Low-Capacitance and Charge-Shared Match Lines for Low-Energy High-Performance TCAMs
A 12-Gb/s Multichannel I/O Using MIMO Crosstalk Cancellation and Signal Reutilization in 65-nm CMOS
An 8.62-μW 75-dB DR SoC Fully Integrated SoC for Spoken Language Understanding
Phase-correcting feedback system for class E power amplifier
Design and performance testing of a 2.29-GB/s Rijndael processor
Latched CMOS differential logic (LCDL) for complex high-speed VLSI
A 4.5-mW Closed-Loop $\Delta\Sigma$ Micro-Gravity CMOS SOI Accelerometer
High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing
A 0.45 mV/V Line Regulation, 0.6 V Output Voltage, Reference-Integrated, Error Amplifier-Less LDO With a 5-Transistor Regulation Core
A 3.8-mW 1.9-mΩ/√Hz Electrical Impedance Tomography IC With High Input Impedance and Loading Effect Calibration for 3-D Early Breast Cancer Detect System
A 3-V 4.25-Gb/s Laser Driver with 0.4-V Output Voltage Compliance
Self-calibrated quadrature generator for WLAN multistandard frequency synthesizer
A 121.7-dB DR and -109.0-dB THD+N Filterless Digital-Input Class-D Amplifier With an HV IDAC Using Tri-Level Unit Cells
A 44-GHz-high IP3 InP HBT MMIC amplifier for low DC power millimeter-wave receiver applications
An approximation to the factor K in the Toh-Ko-Meyer MOS engineering model
A 22-24 GHz4-Element CMOS Phased Array With On-Chip Coupling Characterization
A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband Circuitry
A 265-GHz CMOS Reflectarray With 98×98 Elements for 1°-Wide Beam Forming and High-Angular-Resolution Radar Imaging
A Fully Digital 8 × 16 SiPM Array for PET Applications With Per-Pixel TDCs and Real-Time Energy Output
An Ultra-Low-Cost High-Performance Bluetooth SoC in 0.11-µm CMOS
An all-analog expandable neural network LSI with on-chip backpropagation learning
A high-performance very low-voltage current sense amplifier for nonvolatile memories
Drift-Compensated Magnetic Biosensors Using Concurrent Dual-Frequency Oscillators
Fully differential ADC with rail-to-rail common-mode range and nonlinear capacitor compensation
A 65-dB-SNDR Pipelined SAR ADC Using PVT-Robust Capacitively Degenerated Dynamic Amplifier
A single-chip digitally calibrated 5.15-5.825-GHz 0.18-μm CMOS transceiver for 802.11a wireless LAN
On the temperature dependence of hysteresis effect in floating-body partially depleted SOI CMOS circuits
A 1.16-V 5.8-to-13.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference Circuit With a Shared Offset-Cancellation Method for Internal Amplifiers
Logic circuits using resonant-tunneling hot-electron transistors (RHETs)
A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR
A CMOS bandgap reference without resistors
A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories
A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS
A 0.05-mm 2 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS
A Four-Channel BiCMOS Transmitter for a Quantum Magnetometer Based on Nitrogen-Vacancy Centers in Diamond
A 195 mW/152 mW Mobile Multimedia SoC With Fully Programmable 3-D Graphics and MPEG4/H.264/JPEG
CMOS high-frequency switched-capacitor filters for telecommunication applications
Power efficient charge pump in deep submicron standard CMOS technology
Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop
A 0.8-μm CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links
An enhanced technique for simulating short-circuit power dissipation
A Multi-Sensor and Parallel Processing SoC for Miniaturized Medical Instrumentation
A Monolithically-Integrated Optical Receiver in Standard 45-nm SOI
Wideband 240-GHz Transmitter and Receiver in BiCMOS Technology With 25-Gbit/s Data Rate
A Current Re-Use Quadrature RF Receiver Front-End for Low Power Applications: Blixator Circuit
An Energy Measurement Frontend With Integrated Adaptive Background Accuracy Monitoring of the Full System Including the Current and Voltage Sensors
A 69-V CMOS DC/DC converter for ISDN applications
A Digitally Assisted Multiplexed Neural Recording System With Dynamic Electrode Offset Cancellation via an LMS Interference-Canceling Filter
An on-chip ESD protection circuit with low trigger voltage in BiCMOS technology
Monolithic feedback low noise X-band amplifiers using 0.5-μm GaAs MESFETs: comparative theoretical study and experimental characterization
A 74.8 mW Soft-Output Detector IC for 8 , ˟, 8 Spatial-Multiplexing MIMO Communications
A 30-MHz mixed analog/digital signal processor
Vocell: A 65-nm Speech-Triggered Wake-Up SoC for 10- $\mu$ W Keyword Spotting and Speaker Verification
A CCD/CMOS-based imager with integrated focal plane signal processing
A 240 GHz Fully Integrated Wideband QPSK Receiver in 65 nm CMOS
A 502-GOPS and 0.984-mW Dual-Mode Intelligent ADAS SoC With Real-Time Semiglobal Matching and Intention Prediction for Smart Automotive Black Box System
A 93.3% Peak-Efficiency Self-Resonant Hybrid-Switched-Capacitor LED Driver in 0.18-µm CMOS Technology