yusuke1997/dblp-id-title huggingface dataset:
On-Chip Optical Technology in Future Bus-Based Multicore Designs
AI and Memory Wall
Dedicated digital fuzzy hardware
Guest Editors' Introduction: Accelerator Architectures
The Design And Implementation of the MC68851 Paged Memory Management Unit
Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration
Insights from the 2016 Eckert-Mauchly Award Recipient
Floating-point processors join forces in parallel processing architectures
Top Picks from Hot Interconnects 2011: Petascale Network Architectures
Single Sourcing Mount Fuji
TeraPHY: A Chiplet Technology for Low-Power, High-Bandwidth In-Package Optical I/O
Artificial Intelligence at the Edge: Designs and Architectures for Pervasive Intelligence
Standing on Solid Ground
A Reduced High-Level-Language Instruction Set
A Revolution? How Do You Know?
Inventions and the creative process
Single-Threaded vs. Multithreaded: Where Should We Focus?
FTC and Apple Sue Qualcomm for Cell Phone Standardization Skullduggery, Part 4
A Coarse-Grained Array Accelerator for Software-Defined Radio Baseband Processing
MicroLaw-appropriate and inappropriate legal protection of user interfaces and screen displays. II. Technical aspects of screen design raising legal policy issues
Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Hardware
Editor in Chief's Message: Truly "hot" chips - Do we still care?
FTC and Apple Sue Qualcomm for Cell Phone Standardization Skullduggery, Part 3: Determining SEP Reasonable Royalty
Technology Policy Dilemmas in the New Administration
Energy-Efficient Video Processing for Virtual Reality
Image processing by neural networks
Legislating Entrepreneurship: An Oxymoron?
Trading Off Cache Capacity for Low-Voltage Operation
Challenges and Promising Results in NoC Prototyping Using FPGAs
Bringing NoCs to 65 nm
JN: OS for an embedded Java network computer
Quantum Codesign
Per-Thread Cycle Accounting
Electronic-System Design in the Automobile Industry
A Programmable Approach to Neural Network Compression
Rethinking Flash in the Data Center
Microcomputer Peripherals Status and Trends
Shortfalls, Downturns, and Recessions (Micro Economics)
HPVM: Hardware-Agnostic Programming for Heterogeneous Parallel Systems
A constant-time parallel sorting algorithm and its optical implementation
The Ampos Multiprocessor - A Computer System for Laboratory Use
The HP PA-8000 RISC CPU
Low-Latency Communication Over ATM Networks Using Active Messages
Guest Editors' Introduction: Cutting-Edge Designs
A fault-tolerant multiprocess controller for magnetic bearings
The Power PC 601 microprocessor
An Agile Approach to Building RISC-V Microprocessors
The Sun Fireplane Interconnect
Guest Editors' Introduction: Hot Chips 18
The XMOS Architecture and XS1 Chips
Multi-GPU DGEMM and High Performance Linpack on Highly Energy-Efficient Clusters
Limits of Parallelism and Boosting in Dim Silicon
Economic Dependencies in Integrated Circuits
Programmable vision processor/controller for flexible implementation of current and future image compression standards
In-Memory Intelligence
Learning Hardware Using Multiple-Valued Logic, Part 1: Introduction and Approach
Centip3De: A 64-Core, 3D Stacked Near-Threshold System
Integrated microarchitectures
Superconductor Computing for Neural Networks
Improved Thermal Management with Reliability Banking
The Proposed IEEE 855 Microprocessor Operating Systems Interface Standard
Guest Editor's Edtroduction: Unorthodox Computer Architectures
Knights Landing: Second-Generation Intel Xeon Phi Product
Standard setting in the United States: public and private sector roles
Management of TinyML-Enabled Internet of Things Devices
Amalgams for improved electronics interconnection
The GigaRing Channel
ILLIXR: An Open Testbed to Enable Extended Reality Systems Research
Klessydra-T: Designing Vector Coprocessors for Multithreaded Edge-Computing Cores
Portable electronic storage systems
Organization of the Motorola 88110 superscalar RISC microprocessor
A Latency Processing Unit: A Latency-Optimized and Highly Scalable Processor for Large Language Model Inference
Toward Developing High-Performance RISC-V Processors Using Agile Methodology
FPGA-Accelerated Quantum Computing Emulation and Quantum Key Distillation
The TX16: A Highly Programmable Multi-microprocessor Architecture
Special Issue on Top Picks From the 2024 Computer Architecture Conferences
Energy-Secure System Architectures (ESSA): A Workshop Report
FT-Matrix: A Coordination-Aware Architecture for Signal Processing
Privacy by Memory Design: Visions and Open Problems
Toward FPGA-Based HPC: Advancing Interconnect Technologies
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies
Guest Editors' Introduction: Public-Key Security Systems
Looking briefly back, and then forward..
Hardware-Assisted Security in Electronic Control Units: Secure Automotive Communications by Utilizing One-Time-Programmable Network on Chip and Firewalls
V830R/AV: embedded multimedia superscalar RISC processor
Photonic Interconnects for Exascale and Datacenter Architectures
Did ML Chips Heat Up the Chip Design Arena?
Montecito: A Dual-Core, Dual-Thread Itanium Processor
Top Picks [Guest editors' introduction]
Editor in Chief's Message: New Challenges and Burning Issues
Slouching Toward a Dystopian Internet
A Mobile Semantic Lidar SLAM Processor With Artificial-Intelligence-Based 3-D Perception and Spatiotemporal-Aware Computing
2D silicon/ferroelectric liquid crystal spatial light modulators
A Microprocessor-based Cryptoprocessor
Refueling: Preventing Wire Degradation due to Electromigration
VulHunter: Toward Discovering Vulnerabilities in Android Applications
Inflation and Technology Markets
Aquabolt-XL HBM2-PIM, LPDDR5-PIM With In-Memory Processing, and AXDIMM With Acceleration Buffer
The Milestones That Define Arm's Past, Present, and Future
Dog Days for Broadband
Scaling Semantic Graph Databases in Size and Performance
Dynamic Multicore Resource Management: A Machine Learning Approach
Fast, Flexible High-Level Synthesis from OpenCL using Reconfiguration Contexts
Reflections and Research Advice Upon Receiving the 2019 Eckert-Mauchly Award
Applying fuzzy logic to codesign partitioning
The Next Chapter at Google
Ubiquitous Spatial-Information Services Using Cell Phones
Coping with Latency in SOC Design
Patents on selling via the Net-really?
Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1
A Fast Analog Front-End Processor for Digital Imaging Systems
Time-Triggered Architecture: A Consistent Computing Platform
The GPU Computing Era
Power-Efficient Error Tolerance in Chip Multiprocessors
Thoughts on the Top Picks Selections
Interview With Ronnie Chatterji, Coordinator for the Creating Helpful Incentives to Produce Semiconductors and Science Act
FS 2 : A Fast, Scalable, and Flexible Switching System for Emerging Interconnects
The Microarchitecture of DOJO, Tesla's Exa-Scale Computer
Review of Patents Issued to Computer Architecture Companies in 2021 [Micro Law]
Developing a 0.18-micron CMOS process
Contiguitas: The Pursuit of Physical Memory Contiguity in Data Centers
Is there a silicon way to intelligence?
Top Picks from 2021 Computer Architecture Conferences!
Using Hardware to Configure a Load-Balanced Switch
Reconfigurable Computing, 3D Integration, and Recognizing Leaders in our Field
Electronic Scanners with Speech Output - A Communication System for the Physically Handicapped And Mentally Retarded
Can We Trust Undervolting in FPGA-Based Deep Learning Designs at Harsh Conditions?
Software Standards for the Multicore Era
An Executive for Task-driven Multimicrocomputer Systems
A Bunch-of-Wires (BoW) Interface for Interchiplet Communication
Bebop Bytes Back: An Unconventional Guide To Computers
Compute Express Link Topology-Aware and Expander-Driven Prefetching: Unlocking Solid-State Drive Performance
Cognitive Computing Safety: The New Horizon for Reliability / The Design and Evolution of Deep Learning Workloads
μITRON for small-scale embedded systems
New Applications and Demands
Darwin: A Genomics Coprocessor
The AMD "Zen 2" Processor
An Era of Error
The Middle-Aged Microprocessor
The Irony of Public Funding
Advanced manufacturing equipment: a vertical batch furnace for 300-mm wafer processing
FTC Piles onto Rambus' Standardization Skullduggery
E-business Infrastructure
Real-Time Operating Systems for Small Microcontrollers
Hierarchical discrete-event simulation on hypercube architectures
Parallelism-Aware Batch Scheduling: Enabling High-Performance and Fair Shared Memory Controllers
Conformance testing of VMEbus and Multibus II products
FPGA-Based Near-Memory Acceleration of Modern Data-Intensive Applications
Marvell ThunderX3: Next-Generation Arm-Based Server Processor
Big Chips
Universal Graph-Based Scheduling for Quantum Systems
A Beam-and-Ball Controller Prototype
A Scheduler ASIC for a Programmable Packet Switch
Embedded Multicore Processors and Systems
A RISC architecture with two-size, overlapping register windows
Design and implementation trade-offs in the Clipper C400 architecture
EOLE: Toward a Practical Implementation of Value Prediction
A parallel, scalable, microprocessor-based database computer for performance gains and capacity growth
ASP: a cost-effective parallel microcomputer
Co-Design and System for the Supercomputer "Fugaku"
Exploiting Dark Fluorophore States to Implement Resonance Energy Transfer Pre-Charge Logic
A microprogrammable list processor for personal computers
Digital Dark Matter
Design and Integration: Chip- and System-Level Challenges
Modular fault-tolerant Boolean n-cubes
The Aftermath of the Dyn DDOS Attack
Programmable multichip modules
Giving Text Analytics a Boost
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits
Free-p: A Practical End-to-End Nonvolatile Memory Protection Mechanism
Advancing Tiny Machine Learning Operations: Robust Model Updates in the Internet of Intelligent Vehicles
The Tail at Amazon Web Services Scale
An analog processor architecture for a neural network classifier
Micro Review: More on old themes
Micro Law-the first chip-layout copying case
An advanced database accelerator
Revisiting the Sequential Programming Model for the Multicore Era
Inside the Cerebras Wafer-Scale Cluster
A low-power network for on-line diagnosis of heart patients
Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies - Part IV: Claims
Visual IoT: Ultra-Low-Power Processing Architectures and Implications
FinalFilter: Asserting Security Properties of a Processor at Runtime
How does processor MHZ relate to end-user performance? I. Pipelines and functional units
Transparent authentication and confidentiality for stream sockets
Guest Editors' Introduction: Hot Chips 17
GaAs microprocessors and digital systems: an overview of R&D efforts
Wireless network extension using mobile IP
Nanoscale Resonance Energy Transfer-Based Devices for Probabilistic Computing
Towards General-Purpose Acceleration: Finding Structure in Irregularity
Data Movement Accelerator Engines on a Prototype Power10 Processor
IBM's ES/9000 Model 982's fault-tolerant design for consolidation
Workload characterization: A key aspect of microarchitecture design
Designing, packaging, and testing a 300-MHz, 115 W ECL microprocessor
Hardware-software codesign of embedded systems
A parallel unification machine
An Application-Specific Coprocessor for High-Speed Cellular Logic Operations
Newcache: Secure Cache Architecture Thwarting Cache Side-Channel Attacks
Synthesizing Legacy String Code for FPGAs Using Bounded Automata Learning
Guest Editor's Introduction: Application-Specific Processors
Guest Editor's Introduction: Wearable Information Devices
Hot Chips 16: Power, Parallelism, and Memory Performance
The AMD Opteron Northbridge Architecture
BRAIN: A Low-Power Deep Search Engine for Autonomous Robots
Designing a Crossbar Scheduler for HPC Applications
The MC6809 In DMA Mode on the IEEE-488 Bus
Reinventing Entrepreneurial Inventing for the 21st Century
Near-Memory Processing in Action: Accelerating Personalized Recommendation With AxDIMM
Guest Editors' Introduction: Hot Interconnects 12
Interaction of multichip module substrates with high-density connectors
IEEE P1014 - A Standard for the High-Performance VME Bus
Efficient Language-Guided Reinforcement Learning for Resource-Constrained Autonomous Systems
A neural network accelerator for image analysis
Uncertainty, prediction, and the unexpected
A PC-based digital speech spectrograph
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies - Part VIII: Patent Families
ANSI's role in standards development
Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor
CGPA: Coarse-Grained Pruning of Activations for Energy-Efficient RNN Inference
Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability
SerialExpress-a high performance workstation interconnect
Pulse stream VLSI neural networks
The Quadrics Network: High-Performance Clustering Technology
How To [3 books reviewed]
The MC68332 microcontroller
Toward Disaggregated and Heterogenous AI Systems
Play and learning in the digital future
On the edge. Regression testability
Let play monopoly [computing industry]
Programming Models for Hybrid FPGA-CPU Computational Components: A Missing Link
Special Memories From My Favorite TI Microprocessor Design Project
Software Architects
The Basic Fault-tolerant System
A Digital Signal Generator
Persistent Memory Security Threats to Interprocess Isolation
Challenging Search Engines and Pop-Ups Under Copyright Law: Part 2
System Considerations in the Design of the Am29000
A Real-Time Software Platform for the Cell Processor
Low-Power, High-Performance Architecture of the PWRficient Processor Family
IBM RISC System/6000: architecture and performance
Navigating the Seismic Shift of Post-Moore Computer Systems Design
MetaE2RL: Toward Meta-Reasoning for Energy-Efficient Multigoal Reinforcement Learning With Squeezed-Edge You Only Look Once
Performance trade-offs for microprocessor cache memories
Accelerating Phylogenetics Using FPGAs in the Cloud
Co-Design of Interchiplet, Package, and System Interconnect Protocols
A New Peripheral for Three-Dimensional Computer Input
Datacenter-Scale Analysis and Optimization of GPU Machine Learning Workloads
Specializing a Planet's Computation: ASIC Clouds
Proprietary versus Open Instruction Sets
Embedded SRAM and Cortex-M0 Core Using a 60-nm Crystalline Oxide Semiconductor
Accurate Unix benchmarking: art, science, or black magic?
Systems programming in Java
Using Simple Tools to Evaluate Complex Architectural Trade-offs
Steep-Slope Devices: From Dark to Dim Silicon
Cool Chips, Mobile Devices, Memory, and IEEE Micro Going Digital
Generating reliable embedded processors
Access Recent Books And Articles on microcomputing
2018 Maurice Wilkes Award Given to Gabriel Loh
Optimizing Data-Center TCO with Scale-Out Processors
Upgrading, catching up, and shooting for par [PC market economics]
Authenticating Network-Attached Storage
Year-end cleanup
News: Intel expands advanced 300-mm wafer production; IBM claims world's smallest computer circuits; IEEE 802.11b chip market growth; Samsung extends system LSI commitment; light-emitting silicon; new gas sensors
The Metaflow architecture
An Interconnect Architecture for Networking Systems on Chips
Preserving Virtual Memory by Mitigating the Address Translation Wall
The Motorola DSP56000 Digital Signal Processor
The Development of Reliabililty in Industrial Control Systems
Single-chip H.324 videoconferencing
How to write a patent
SARC Coherence: Scaling Directory Cache Coherence in Performance and Power
The 82460GX Sever/Workstation Chip Set
Using building blocks to design analog neuro-fuzzy controllers
Increasing Utilization in Modern Warehouse-Scale Computers Using Bubble-Up
ITT CAP - Toward a Personal Supercomputer
Fuzzy rule-based systems on general-purpose processors
Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA
Special Issue on Top Picks From the 2021 Computer Architecture Conferences
A model for the high-level description and simulation of VLSI networks
EyeCoD: Eye Tracking System Acceleration via FlatCam-Based Algorithm and Hardware Co-Design
SpeedLog: a generic log service supporting efficient node-crash recovery
Automated Full-System Power Characterization
The IEEE Softwae Engineering Stanldards Process
Special Issue on Artificial Intelligence, Edge, and Internet of Things for Smart Agriculture
Automating Stressmark Generation for Testing Processor Voltage Fluctuations
DeNovoND: Efficient Hardware for Disciplined Nondeterminism
A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience
Offloading Collective Operations to Programmable Logic
Micro News 350-GHz transistor; New high-performance benchmarks
Recent Advances and New Avenues in Hardware-Level Reliability Support
The POWER Processor Family: A Historical Perspective From the Viewpoint of Presilicon Modeling
Using Asymmetric Single-ISA CMPs to Save Energy on Operating Systems
Personal Computers Aid the Handicapped
Guest Editor's Introduction: Computer Architecture Education
FerroElectronics for Edge Intelligence
ML-HW Co-Design of Noise-Robust TinyML Models and Always-On Analog Compute-in-Memory Edge Accelerator
Flexible Hardware Acceleration for Instruction-Grain Lifeguards
Power- and Energy-Aware Computing
NePSim: A Network Processor Simulator with a Power Evaluation Framework
Reflections from the 2013 Eckert-Mauchly Award Recipient
The Modiac Multiprocessor - A 286-based Design Giovanni Neri And Tullio Salmon Cinotti University of Bologna
Memristive Accelerators for Dense and Sparse Linear Algebra: From Machine Learning to High-Performance Scientific Computing
It has bugs, but the games are out of this world [DP industry]
Compiling C on a multiple-stack architecture
Communications consolidation after an era of no restraints
A unified tool for fuzzy/neural network systems
Adversarial Attacks Against Machine Learning-Based Resource Provisioning Systems
Neuromorphic Near-Sensor Computing: From Event-Based Sensing to Edge Learning
Implementing precise interruptions in pipelined RISC processors
(Re)Designing Data-Centric Data Centers
Toward a Local Network Standard
Guest Editors' Introduction: Hot Chips 21
A Self-Repairing Execution Unit for Microprogrammed Processors
Address Translation for Throughput-Oriented Accelerators
A 33-GW Pilgrimage to the Promised Land of Agent Workforce
2013 Maurice Wilkes Award Given to Parthasarathy (Partha) Ranganathan
Integrating Nonelectronic Components into Electronic Microsystems
The 50 Year History of the Microprocessor as Five Technology Eras
Setting standards on the information superhighway
Where the Frontier Thrives: Bricks, Mix, and Zip
Guest Editors' Introduction: Trends and Directions in Microelectronics
A Performance Study of a Microcomputer-Implemented FSK Receiver
Statistical Simulation: Adding Efficiency to the Computer Designer's Toolbox
A VLSI Architecture for Software Structure: The Intel 8086
Horus: Large-Scale Symmetric Multiprocessing for Opteron Systems
DNNDaSher: A Compiler Framework for Dataflow Compatible End-to-End Acceleration on IBM AIU
Camp development: the art of building a market through standards
Federal Appeals Court Sees Potential Antitrust Violation in Standardization Skullduggery
Which Industries Use the Internet?
Implementing a DSP-based Petri-net simulation tool
Building Real Computer Systems
Scale-Out Networking in the Data Center
A high-speed, reconfigurable fuzzy logic controller
Validation-based development of dependable systems
Goldstrike 1: CoinTerra's First-Generation Cryptocurrency Mining Processor for Bitcoin
Pre-Silicon Modeling and Analysis: Impact On Real Design
Lifetime Reliability: Toward an Architectural Solution
Effective Implementation of a Parallel Language on a Multiprocessor
Top Picks from the 2016 Computer Architecture Conferences
Reconfiguring one-time programmable FPGAs
Neural networks-extraordinary variation
Toward a Standardized Representation for Deep Learning Collective Algorithms
Datawave: a single-chip multiprocessor for video applications
An Intelligent Braille Display Device
Classifying Packets with Hierarchical Intelligent Cuttings
A Review of Wisconsin Alumni Research Foundation v. Apple - Part I
h²ECU: A High-Performance and Heterogeneous Electronic Control Unit for Automated Driving
Resolution of data and control-flow dependencies in the PowerPC 601
A Hardware Algol Machine
VLSI architectures for neural networks
MASSC: a generic architecture for multiapplication smart cards
Heterogeneous Computing [Guest editors' introduction]
Experimentation with hypercube database engines
FTC Sues N-Data for Violating Standards Commitment to IEEE
Digital video coding techniques for US high-definition TV
Usable Software And Documentation [Book Review]
US vs. Microsoft (again)-the browser war
High-Speed Datacenter Interconnects [Guest editors' introduction]
The IA-64 Itanium Processor Cartridge
Online Code Layout Optimizations via OCOLOS
Biology and Systems Interactions
A Parallel Neural Processor for Real-Time Applications
Yin-Yang: Programming Abstractions for Cross-Domain Multi-Acceleration
MUTABOR, a coprocessor supporting memory management in an object-oriented architecture
The Cache and Codec Model for Storing and Manipulating Data
Towards an Assembly Language Stanldard
Unix and the Am29000 microprocessor
A Solid Past, A Vital Future
Hot Chips 26 [Guest editors' introduction]
A Review of Wisconsin Alumni Research Foundation v. Apple - Part VII
Enabling Full Associativity with Memristive Address Decoder
Special Issue on Commercial Products 2021
Access-Mode Predictions for Low-Power Cache Design
Micro law: patenting computerized methods of doing business
Posix/Unix standards: foundation for 21st century growth
Top Picks from 2013
Exploiting Offload-Enabled Network Interfaces
Perceived-Color Approximation Transforms for Programs that Draw
Parallel CRC generation
From Colocation to Exfiltration: Practical Cache Side-Channel Attacks in the Modern Public Cloud
Memristors and More
Thoughts on Winning the 2014 Eckert-Mauchly Award
Virtual-Memory-Mapped Network Interfaces
Guest Editors' Introduction: Top Picks from the 2008 Computer Architecture Conferences
Verifying Correct Microarchitectural Enforcement of Memory Consistency Models
The TMS320C30 floating-point digital signal processor
Virtual memory in contemporary microprocessors
On the edge-evaluating shielded twisted-pair cable
An Overview of the 9900 Microprocessor Family
Analog Computing in a Modern Context: A Linear Algebra Accelerator Case Study
Recent Patents for Leading Computer Architecture Companies
Physical Synthesis with Clock-Network Optimization for Large Systems on Chips
Justice Department Agrees IEEE's New RAND Policy Isn't Price Fixing
Analog-digital technologies for mixed-signal processing: The driving force to success for the European industry
Cuenet - A Distributed Computing Facility
Upgrading, catching up, and shooting for par [Micro Economics]
Tales of the Tail: Past and Future
A Microprocessor-based Hypercube Supercomputer
ReMAP: A Reconfigurable Architecture for Chip Multiprocessors
Hot Chips 29
Argus: An End-to-End Framework for Accelerating CNNs on FPGAs
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies - Part VI: Relationship Between Prosecution Time and Claims
A Unique Microprcessor Instruction Set
FTC turns back challenge on patent coverage
Micro Law: An End to the Rambus Skullduggery Saga
Enterprise-Class Multilevel Cache Design: Low Latency, Huge Capacity, and High Reliability
Mining streams of short text for analysis of world-wide event evolutions
Entity alignment via graph neural networks: a component-level study
Exploiting detected visual objects for frame-level video filtering
A computationally efficient and lightweight model for high-accuracy OCT image classification
Fine-grained probability counting for cardinality estimation of data streams