yusuke1997/dblp-id-title huggingface dataset:
Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS
A Dual-Polarization Silicon-Photonic Coherent Transmitter Supporting 552 Gb/s/wavelength
Self-Regulated Reconfigurable Voltage/Current-Mode Inductive Power Management
20 Gb/s digital SSIs using AlGaAs/GaAs heterojunction bipolar transistors for future optical transmission systems
Envelope Tracking Supply Modulator with Trellis-Search-Based Switching and 160-MHz Capability
Flip-Chip Aperture Coupled D-Band Active Radiator Tiles in 22-nm CMOS FDSOI
A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC With PVT Tracking and Speed-Enhanced Techniques
An 8 Bit 4 GS/s 120 mW CMOS ADC
A Compact Switched-Capacitor Regulated Charge Pump Power Supply
A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array
Cognitive Radio Design Challenges and Techniques
Blind Calibration Algorithm for Nonlinearity Correction Based on Selective Sampling
A switched capacitor circuit simulator: AWEswit
A 50-64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology
A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS
Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s
A 51-pJ/Pixel 33.7-dB PSNR 4× Compressive CMOS Image Sensor With Column-Parallel Single-Shot Compressive Sensing
The architectures and design of a 20-MHz real-time DSP chip set
On fault probabilities and yield models for VLSI neural networks
Issue logic for a 600-MHz out-of-order execution microprocessor
Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits
A 10 MHz Bandwidth, 70 dB SNDR Continuous Time Delta-Sigma Modulator With Digitally Improved Reconfigurable Blocker Rejection
Analysis and Design of a CMOS Phase-Tunable Injection-Coupled LC Quadrature VCO (PTIC-QVCO)
Introduction to the Special Issue on the ISSCC2004
A Compact, Highly-Digital Sensor-Fusion-Based Joint V dd -Temperature Sensor for SoC Thermal Management
Physical design of testable CMOS digital integrated circuits
High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications
A Passive Switched-Capacitor Finite-Impulse-Response Equalizer
High-performance embedded SOI DRAM architecture for the low-power supply
An evaluation of MOS interface-trap charge pump as an ultralow constant-current generator
Micropower CMOS temperature sensor with digital output
True Random Number Generator With a Metastability-Based Quality Control
All Digital Spread Spectrum Clock Generator for EMI Reduction
A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization
A Differential Digitally Controlled Crystal Oscillator With a 14-Bit Tuning Resolution and Sine Wave Outputs for Cellular Applications
A 23-ns 256 K EPROM with double-layer metal and address transition detection
A wide-band class AB monolithic power amplifier
G-band (140-220-GHz) InP-based HBT amplifiers
A Miniature 2 mW 4 bit 1.2 GS/s Delay-Line-Based ADC in 65 nm CMOS
PQPU: A 4.4-μJ/Op 69.4-kOPS Agile Post-Quantum Crypto-Processor Across Multiple Mathematical Problems
A Sensing Noise Compensation Bit Line Sense Amplifier for Low Voltage Applications
A Wireless IC for Time-Share Chemical and Electrical Neural Recording
A 6800-µm 2 Resistor-Based Temperature Sensor With ±0.35 °C (3 σ) Inaccuracy in 180-nm CMOS
A Frequency-Locked Oscillator Using Complex RC Impedance IQ-Balancing
1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus
An analytical threshold voltage and subthreshold current model for short-channel MESFETs
Adaptive supply serial links with sub-1-V operation and per-pin clock recovery
A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS
A 1 GHz Digital Channel Multiplexer for Satellite Outdoor Unit
Write and Read Frequency-Based Word-Line Batch V TH Modulation for 2-D and 3-D-TLC NAND Flash Memories
A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS
Low-Power High-Efficiency Class D Audio Power Amplifiers
A robust smart power bandgap reference circuit for use in an automotive environment
Backside optical emission diagnostics for excess I DDQ
An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode
A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET
A 1-V CMOS switched-opamp switched-capacitor pseudo-2-path filter
A Multi-Core Series-Resonance CMOS Oscillator
An 8-bit 100-MHz CMOS linear interpolation DAC
Implementation of high peak-current IGBT gate drive circuits in VLSI compatible BiCMOS technology
A 200-MHz CMOS x/sin(x) digital filter for compensating D/A converter frequency response distortion
A -124-dBm Sensitivity Interference-Resilient Direct-Conversion Duty-Cycled Wake-Up Receiver Achieving 0.114 mW at 1.966-s Wake-Up Latency
A highly versatile beamforming ASIC for application in broad-band fixed wireless access systems
A 1.59 Gpixel/s Motion Estimation Processor With -211 to +211 Search Range for UHDTV Video Encoder
A 6-ns cycle 256-kb cache memory and memory management unit
Compact ka-band bi-directional amplifier for low-cost electronic scanning array antenna
A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS
An ISI-Resilient Data Encoding for Equalizer-Free Wireline Communication - Dicode Encoding and Error Correction for 24.2-dB Loss With 2.56 pJ/bit
A Narrowband Multi-Channel 2.4 GHz MEMS-Based Transceiver
CMOS magnetic-field sensor system
10-Gbps, 5.3-mW Optical Transmitter and Receiver Circuits in 40-nm CMOS
A Configurable High-Side/Low-Side Driver With Fast and Equalized Switching Delay
Multipurpose high-coding-gain 0.8- mu m BiCMOS VLSIs for high-speed multilevel trellis-coded modulation
Platform Architecture for Solar, Thermal, and Vibration Energy Combining With MPPT and Single Inductor
4×25 Gb/s Transceiver With Optical Front-end for 100 GbE System in 65 nm CMOS Technology
A Regulation-Free Sub-0.5-V 16-/24-MHz Crystal Oscillator With 14.2-nJ Startup Energy and 31.8-µW Steady-State Power
MISIMO: A Multi-Input Single-Inductor Multi-Output Energy Harvesting Platform in 28-nm FDSOI for Powering Net-Zero-Energy Systems
A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL
A Gesture Classification SoC for Rehabilitation With ADC-Less Mixed-Signal Feature Extraction and Training Capable Neural Network Classifier
A new compensation technique for resistive level shifters
A High Conversion Ratio and 97.4% High Efficiency Three-Switch Boost Converter With Duty-Dependent Charge Topology for 1.2-A High Driving Current and 20% Reduction of Inductor DC Current in MiniLED Applications
A 1.5-V full-swing bootstrapped CMOS large capacitive-load driver circuit suitable for low-voltage CMOS VLSI
Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC)
A 450-mV Single-Fuel-Cell Power Management Unit With Switch-Mode Quasi-V 2 Hysteretic Control and Automatic Startup on 0.35-µm Standard CMOS Process
CMOS THz-ID: A 1.6-mm² Package-Less Identification Tag Using Asymmetric Cryptography and 260-GHz Far-Field Backscatter Communication
Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning
Interconnect and substrate modeling and analysis: an overview
Loop-based design and reconfiguration of wafer-scale linear arrays with high harvest rates
Introduction to the Special Issue on the 2018 Symposium on VLSI Circuits
A Nonuniform Sampling Lifetime Estimation Technique for Luminescent Oxygen Measurements for Biomedical Applications
A 36 fps SXGA 3-D Display Processor Embedding a Programmable 3-D Graphics Rendering Engine
A 5.8 GHz 1 V Linear Power Amplifier Using a Novel On-Chip Transformer Power Combiner in Standard 90 nm CMOS
8.3 M-Pixel 480-fps Global-Shutter CMOS Image Sensor with Gain-Adaptive Column ADCs and Chip-on-Chip Stacked Integration
A 5.8 nW CMOS Wake-Up Timer for Ultra-Low-Power Wireless Applications
A fully operational 1 kb variable threshold Josephson RAM
A Differential Flip-Flop With Static Contention-Free Characteristics in 28 nm for Low-Voltage, Low-Power Applications
A 4 Mb LV MOS-Selected Embedded Phase Change Memory in 90 nm Standard CMOS Technology
Design of a sense circuit for low-voltage flash memories
A Time-Resolved Four-Tap Lock-In Pixel CMOS Image Sensor for Real-Time Fluorescence Lifetime Imaging Microscopy
A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's
A Fully Integrated 490-GHz CMOS Receiver Adopting Dual-Locking Receiver-Based FLL
A study of phase noise in CMOS oscillators
A 1-V integrated current-mode boost converter in standard 3.3/5-V CMOS technologies
A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO
A 0.5-V 560-kHz 18.8-fJ/Cycle On-Chip Oscillator With 96.1-ppm/°C Steady-State Stability Using a Duty-Cycled Digital Frequency-Locked Loop
A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques
Triple-Mode, Hybrid-Storage, Energy Harvesting Power Management Unit: Achieving High Efficiency Against Harvesting and Load Power Variabilities
A VLSI architecture of JPEG2000 encoder
A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology
0.5- mu m 2 M-transistor BiPNMOS channelless gate array
IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm 2 CIM-SRAM With Multi-Bit Analog Batch-Normalization
Inverting Buck-Boost DC-DC Converter for Mobile AMOLED Display Using Real-Time Self-Tuned Minimum Power-Loss Tracking (MPLT) Scheme With Lossless Soft-Switching for Discontinuous Conduction Mode
A 2.5-GHz Dynamic Performance-Enhanced Nonlinear DAC-Based Direct-Digital Frequency Synthesizer in 65-nm CMOS Process
CMOS four-quadrant multiplier using bias feedback techniques
Response surface methodology: a modeling tool for integrated circuit designers
A Wideband PLL-Based G/FSK Transmitter in 0.18 µm CMOS
A Low-Energy Inductive Coupling Transceiver With Cm-Range 50-Mbps Data Communication in Mobile Device Applications
The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture
AM suppression with low AM-PM conversion with the aid of a variable-gain amplifier
Asynchronous transfer mode switching LSI chips with 10-Gb/s serial I/O ports
A Dynamically High-Impedance Charge-Pump-Based LDO With Digital-LDO-Like Properties Achieving a Sub-4-fs FoM
A 10∼15-bit 60-MS/s Floating-Point ADC With Digital Gain and Offset Calibration
A Highly Efficient and Linear Power Amplifier for 28-GHz 5G Phased Array Radios in 28-nm CMOS
A 0.25-μm CMOS 0.9-V 100-MHz DSP core
Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping
A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range
Correction to "Distributed Parametric Resonator: A Passive CMOS Frequency Divider" [Sep 10 1834-1844]
Machine Learning Assisted Side-Channel-Attack Countermeasure and Its Application on a 28-nm AES Circuit
Improvement of soft-error rate in MOS SRAMs
A Delta-Sigma Pulse-Width Digitization Technique for Super-Regenerative Receivers
A 135-mW 1.70TOPS Sparse Video Sequence Inference SoC for Action Classification
Comments on '18-GHz 1/8 dynamic frequency divider using Si bipolar technologies (and reply)
A Triboelectric Energy-Harvesting Interface With Scalable Multi-Chip-Stacked Bias-Flip and Daisy-Chained Synchronous Signaling Techniques
A 126-μW cochlear chip for a totally implantable system
New Associate Editor [Ken Suyama]
Authors' Response [to comments on "On the self-generation of electrical soliton pulses"]
A 250-MHz monolithic voltage-controlled oscillator with low temperature coefficient
A 50-Gb/s High-Sensitivity (-9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18-µm SiGe BiCMOS Technology
Double-edge-triggered D-flip-flops for high-speed CMOS circuits
A 0.8 V Intelligent Vision Sensor With Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification
Correction to "exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design"
A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-μm CMOS
A pipelined associated memory implemented in VLSI
An 8-Bit, 40-Instructions-Per-Second Organic Microprocessor on Plastic Foil
An Energy Efficient 32-nm 20-MB Shared On-Die L3 Cache for Intel® Xeon® Processor E5 Family
Continuous-Time ΔΣ Modulators With Improved Linearity and Reduced Clock Jitter Sensitivity Using the Switched-Capacitor Return-to-Zero DAC
A 43 nW, 32 kHz, ±4.2 ppm Piecewise Linear Temperature-Compensated Crystal Oscillator With ΔΣ-Modulated Load Capacitance
PLL Fractional Spur's Impact on FSK Spectrum and a Synthesizable ADPLL for a Bluetooth Transmitter
In-pixel autoexposure CMOS APS
Design of tapered buffers with local interconnect capacitance
Bootstrapped pad protection structure
Large-Scale Sensing System Combining Large-Area Electronics and CMOS ICs for Structural-Health Monitoring
A Real-Time Speech Enhancement Processor for Hearing Aids in 28-nm CMOS
An SC-Parallel-Inductor Hybrid Buck Converter With Reduced Inductor Voltage and Current
CMOS Transconductors With Continuous Tuning Using FGMOS Balanced Output Current Scaling
Short Channel Output Conductance Enhancement Through Forward Body Biasing to Realize a 0.5 V 250 µW 0.6-4.2 GHz Current-Reuse CMOS LNA
A Reconfigurable Ultrasound Transceiver ASIC With 24×40 Elements for 3-D Carotid Artery Imaging
A 0.9-V 60-µW 1-Bit Fourth-Order Delta-Sigma Modulator With 83-dB Dynamic Range
Low-Power Wideband Analog Channelization Filter Bank Using Passive Polyphase-FFT Techniques
A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input
A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI
A 42 nJ/Conversion On-Demand State-of-Charge Indicator for Miniature IoT Li-Ion Batteries
A Stacked CMOS Image Sensor With Array-Parallel ADC Architecture
DC to 10-GHz mixer and amplifier GaAs IC's for coherent optical heterodyne receiver
A Modular 1 mm 3 Die-Stacked Sensing Platform With Low Power I 2 C Inter-Die Communication and Multi-Modal Energy Harvesting
Comments on 'A MOS implementation of totally self-checking checker for the 1-out-of-3 code'
A Low-Power Backscatter Modulation System Communicating Across Tens of Meters With Standards-Compliant Wi-Fi Transceivers
A 1.8-V 6.9-mW 120-fps 50-Channel Capacitive Touch Readout With Current Conveyor AFE and Current-Driven $\Delta \Sigma $ ADC
A Phased-Array Transceiver With 2-Dimension Continuously Auto Link-Tracking Operation and Time Division Modulator
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm
Design of 4-kbit*4-layer optically coupled three-dimensional common memory for parallel processor system
An Implantable Neuromorphic Sensing System Featuring Near-Sensor Computation and Send-on-Delta Transmission for Wireless Neural Sensing of Peripheral Nerves
A 100 dB Dynamic-Range CMOS Vision Sensor With Programmable Image Processing and Global Feature Extraction
A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques
New insight into subharmonic oscillation mode of GaAs power amplifiers under severe output mismatch condition
A sub-1-dB NF±2.3-kV ESD-protected 900-MHz CMOS LNA
Analysis and characterization of BiCMOS for high-speed digital logic
Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS
An Autonomous Piezoelectric Energy Harvesting IC Based on a Synchronous Multi-Shot Technique
A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling
A Wideband Sliding Digital-IF Quadrature Digital Transmitter for Multimode NB-IoT/BLE Applications
A Programmable Impedance Matching Circuit for Voiceband Modems
A Wideband 20 to 28 GHz Signal Generator MMIC With 30.8 dBm Output Power Based on a Power Amplifier Cell With 31% PAE in SiGe
A 2.5-V active low-pass filter using all-n-p-n Gilbert cells with a 1-V p-p range
40-mm 2 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory
An AC Input Inductor-Less LED Driver for Efficient Lighting and Visible Light Communication
Jitter Characteristic in Charge Recovery Resonant Clock Distribution
A 64 × 64-Pixels Digital Silicon Photomultiplier Direct TOF Sensor With 100-MPhotons/s/pixel Background Rejection and Imaging/Altimeter Mode With 0.14% Precision Up To 6 km for Spacecraft Navigation and Landing
A Calibration-Free 12-bit 50-MS/s Full-Analog SAR ADC With Feedback Zero-Crossing Detectors
The complementary Darlington-a novel current source for ICs
A 25Gbaud PAM-4 Linear Burst-Mode Receiver With Analog Gain- and Offset Control in 0.25μm SiGe: C BiCMOS
A remark on carry-free binary multiplication
A subharmonically injected LC delay line oscillator for 17-GHz quadrature LO generation
CMOS Camera With In-Pixel Temporal Change Detection and ADC
A Digital RF Transmitter With Background Nonlinearity Correction
A 3-bit soft-decision IC for powerful forward error correction in 10-Gb/s optical communication systems
A single-chip bipolar AGC amplifier with large dynamic range for optical-fiber receivers operating up to 3 Gbit/s
Portless SRAM - A High-Performance Alternative to the 6T Methodology
A Leakage Current Replica Keeper for Dynamic Circuits
Evolver: A Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning
Verification techniques for substrate coupling and their application to mixed-signal IC design
A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System
A 90-nm Power Optimization Methodology With Application to the ARM 1136JF-S Microprocessor
Noise-shaping techniques applied to switched-capacitor voltage regulators
A stable high-order delta-sigma modulator with an FIR spectrum distributor
Hysteresis prediction in autonomous microwave circuits using commercial software: application to a Ku-band MMIC VCO
A 200-V high-voltage amplifier using a parasitic field-oxide transistor for voltage feedback
A Highly Accurate and Sensitive mmWave Displacement-Sensing Doppler Radar With a Quadrature-Less Edge-Driven Phase Demodulator
5-31-Hz 188- $\mu$ W Light-Sensing Oscillator With Two Active Inductors Fully Integrated on Plastic
A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits
A Patient-Specific Closed-Loop Epilepsy Management SoC With One-Shot Learning and Online Tuning
A 4.6-GHz 54.5-fs rms PLL-XO Co-Design Featuring a Pulse-Injection XO Driver
A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration
A 3-V, 0.35-μm CMOS Bluetooth receiver IC
A Low-Noise Design Technique for High-Speed CMOS Optical Receivers
A Smart Hardware Security Engine Combining Entropy Sources of ECG, HRV, and SRAM PUF for Authentication and Secret Key Generation
A 1.5-V full-swing BiCMOS logic circuit
Introduction to the Special Issue on the 2009 IEEE International Solid-State Circuits Conference
A design for a minimum Hamming-distance search using asynchronous digital techniques
A high-swing, high-impedance MOS cascode circuit
A 3.5-GHz PLL for fast low-IF/zero-IF LO switching in an 802.11 transceiver
A direct digital synthesizer with an on-chip D/A-converter
A self-learning neural network chip with 125 neurons and 10 K self-organization synapses
Small-signal MMIC amplifiers with bridged T-coil matching networks
A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS
Digitally Equalized CMOS Transmitter Front-End With Integrated Power Amplifier
A TDMA Neural Recording SoC With IIR-RLS Adaptive Filters for 83.4 dB Artifact Suppression Across 256 Channels
EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage
A Reconfigurable 28-/37-GHz MMSE-Adaptive Hybrid-Beamforming Receiver for Carrier Aggregation and Multi-Standard MIMO Communication
A 2.4 GHz CMOS sub-sampling mixer with integrated filtering
A 10 Gb/s Linear Burst-Mode Receiver in 0.25 µm SiGe: C BiCMOS
I/Q mismatch compensation using adaptive decorrelation in a low-IF receiver in 90-nm CMOS process
An analog neural computer with modular architecture for real-time dynamic computations
The Effect of the System Specification on the Optimal Selection of Clocked Storage Elements
A zero-overhead self-timed 160-ns 54-b CMOS divider
Random access analog memory for early vision
Bandwidth enhancement of transimpedance amplifier by a capacitive-peaking design
Design and Implementation of the POWER6 Microprocessor
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop
A 10.2 Mbps Pulse Harmonic Modulation Based Transceiver for Implantable Medical Devices
High-density central I/O circuits for CMOS
Transimpedance preamplifier with 70-dB AGC range in fine-line NMOS
A 65-nm CMOS 1.75-15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer
A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture
Single-Photon Synchronous Detection
Power-efficient metastability error reduction in CMOS flash A/D converters
Low-Power Successive Approximation Converter With 0.5 V Supply in 90 nm CMOS
A CMOS nested-chopper instrumentation amplifier with 100-nV offset
A Full-Duplex Receiver With True-Time-Delay Cancelers Based on Switched-Capacitor-Networks Operating Beyond the Delay-Bandwidth Limit
Zero-Crossing Detector Based Reconfigurable Analog System
A 4 × 32 Gb/s 1.8 pJ/bit Collaborative Baud-Rate CDR With Background Eye-Climbing Algorithm and Low-Power Global Clock Distribution
A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller
A Bluetooth 5 Transceiver With a Phase-Tracking RX and Its Corresponding Digital Baseband in 40-nm CMOS
A 10.8-14.5-GHz Eight-Phase 12.5%-Duty-Cycle Nonoverlapping LO Generator With Automatic Phase-and-Duty-Cycle Calibration
A 0.18-μm CMOS front-end processor for a Blu-Ray Disc recorder with an adaptive PRML
A Low-Spur and Low-Jitter Fractional Output Divider With Self-Adaption Frequency Filtering Technique
High-speed low-power charge-buffered active-pull-down ECI circuit
An Energy-Efficient Mobile Vertex Processor With Multithread Expanded VLIW Architecture and Vertex Caches
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method
A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control
Analysis and Design of an Audio Continuous-Time 1-X FIR-MASH Delta-Sigma Modulator
A multiple-crystal interface PLL with VCO realignment to reduce phase noise
Design and Implementation of a D-Band Bidirectional Common-Gate Amplifier in 45-nm RFSOI
A comprehensive delay model for CMOS inverters
A speed-enhanced DRAM array architecture with embedded ECC
Design of a 300-mV 2.4-GHz Receiver Using Transformer-Coupled Techniques
Histogram-equalization-based adaptive image sensor for real-time vision
A Rail-to-Rail Input NS-Pipelined-SAR ADC With Self-Boosted Input Impedance and Reused Residue Amplifier for Biosignal Acquisition
An integrated 200-W class-D audio amplifier
A Low Power Tunable Delay Element Suitable for Asynchronous Delays of Burst Information
A bipolar four-quadrant analog quarter-square multiplier consisting of unbalanced emitter-coupled pairs and expansions of its input ranges
Generalized translinear circuit principle
A multichannel pipeline analog-to-digital converter for an integrated 3-D ultrasound imaging system
Design considerations and implementation of a programmable high-frequency continuous-time filter and variable-gain amplifier in submicrometer CMOS
A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m 2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS
A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion
A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-μm CMOS transceiver for 802.11a/b/g wireless LAN
A 10-b 100-Msample/s pipelined subranging BiCMOS ADC