yusuke1997/dblp-id-title huggingface dataset:
Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits
An analog GFSK modulator in 0.35-μm CMOS
A 1.8-V 128-Mb 125-MHz multilevel cell flash memory with flexible read while write
A 16-Channel Patient-Specific Seizure Onset and Termination Detection SoC With Impedance-Adaptive Transcranial Electrical Stimulator
Design of CMOS tapered buffer for minimum power-delay product
A 28-Gb/mm 2 4XX-Layer 1-Tb 3-b/Cell WF-Bonding 3D-nand Flash With 5.6-Gb/s/Pin IOs
A 3.3 V 625 kHz switched-current multiplier
A Highly Integrated Distributed Mixer Receiver for Low-Power Wireless Radios
A Low-Power Baseband ASIC for an Energy-Collection IR-UWB Receiver
A PWM signal processing core circuit based on a switched current integration technique
Design, measurement and analysis of CMOS polysilicon TFT operational amplifiers
0.021-μm 2 High-Density SRAM in Intel 18A RibbonFET Technology With PowerVia Backside Power Delivery
A stable programming pulse generator for single power supply flash memories
A 0.18-$muhbox m$CMOS Analog Min-Sum Iterative Decoder for a (32, 8) Low-Density Parity-Check (LDPC) Code
A Time Domain Artificial Intelligence Radar System Using 33-GHz Direct Sampling for Hand Gesture Recognition
Over-100-Gb/s 1: 2 Demultiplexer Based on InP HBT Technology
A 1984-Pixels, 1.26 nW/Pixel Retinal Prosthesis Chip With Time-Domain In-Pixel Image Processing and Bipolar Stimulating Electrode Sharing
High-speed low-power direct-coupled complementary push-pull ECL circuit
An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier
A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme
Fast adders using enhanced multiple-output domino logic
256×256 CMOS active pixel sensor camera-on-a-chip
A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS
A 0.8- mu m advanced single-poly BiCMOS technology for high-density and high-performance applications
An IEEE 802.15.6 Standard Compliant 2.5 nJ/Bit Multiband WBAN Transmitter Using Phase Multiplexing and Injection Locking
A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme
A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS
Design and Implementation of a Hybrid, ADC/DAC-Free, Input-Sparsity-Aware, Precision Reconfigurable RRAM Processing-in-Memory Chip
A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI
Off-the-Line Primary Side Regulation LED Lamp Driver With Single-Stage PFC and TRIAC Dimming Using LED Forward Voltage and Duty Variation Tracking Control
26-42 GHz SOI CMOS low noise amplifier
A Low-Power High-BW PAM4 VCSEL Driver With Three-Tap FFE in 12-nm CMOS FinFET Process
An Agile, Ultra-Wideband Pulse Radio Transceiver With Discrete-Time Wideband-IF
Hierarchical yield estimation of large analog integrated circuits
A high-efficiency CMOS voltage doubler
A 2.4-GHz 6.4-mW Fractional-N Inductorless RF Synthesizer
NURIP: Neural Interface Processor for Brain-State Classification and Programmable-Waveform Neurostimulation
A 167- μW 71.7-dB SFDR 2.4-GHz BLE Receiver Using a Passive Quadrature Front End, a Double- Sided Double-Balanced Cascaded Mixer, and a Dual-Transformer-Coupled Class-D VCO
A novel A/D converter using resonant tunneling diodes
A programmable CORDIC chip for digital signal processing applications
Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits
Implementation of switch network logic in SOI
Extraction method of the base series resistances in bipolar transistor in presence of current crowding
A 3.4 W Digital-In Class-D Audio Amplifier in 0.14µm CMOS
A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion
A Partially Feedback NSSAR Embedded Third-Order Delta-Sigma Modulator With Gain-Boosted Two-Stage FIAs
Programmable time-multiplexed switched-capacitor variable equalizer for arbitrary frequency response realizations
A silicon-bipolar amplifier for 10 Gbit/s with 45 dB gain
An adaptive analog noise-predictive decision-feedback equalizer
A Third-Order Quasi-Elliptic N-Path Filter With Enhanced Linearity Through Clock Boosting
High-voltage power delivery through charge recycling
A 285-MHz pipelined MAP decoder in 0.18-μm CMOS
A 16 , ˟ 16 Pixel Distance Sensor With In-Pixel Circuitry That Tolerates 150 klx of Ambient Light
Intermodulation distortion in current-commutating CMOS mixers
A 22.3-nW, 4.55 cm 2 Temperature-Robust Wake-Up Receiver Achieving a Sensitivity of -69.5 dBm at 9 GHz
A Dual-Loop Synthesizer With Fast Frequency Modulation Ability for 77/79 GHz FMCW Automotive Radar Applications
General algorithms for a simplified addition of 2's complement numbers
A New Approach to Low-Power and Low-Latency Wake-Up Receiver System for Wireless Sensor Nodes
An ECL-compatible GaAs SCFL design method
Analysis and Design of a 260-MHz RF Bandwidth +22-dBm OOB-IIP3 Mixer-First Receiver With Third-Order Current-Mode Filtering TIA
A low supply voltage high PSRR voltage reference in CMOS process
An 8-bit multitask micropower RISC core
Actively Multiplexed μECoG Brain Implant System With Incremental-ΔΣ ADCs Employing Bulk-DACs
A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links
A Class-G Voltage-Mode Doherty Power Amplifier
A fully integrated on-chip DC-DC conversion and power management system
A 1.5-V 900-MHz monolithic CMOS fast-switching frequency synthesizer for wireless applications
An Energy-Efficient 15-Bit Capacitive-Sensor Interface Based on Period Modulation
Measurement and Analysis of Current Noise in Chopper Amplifiers
Dual Active-Capacitive-Feedback Compensation for Low-Power Large-Capacitive-Load Three-Stage Amplifiers
BiCMOS adjustable linear current mirror
A 2.4 GHz Multi-Channel FBAR-based Transmitter With an Integrated Pulse-Shaping Power Amplifier
A single-chip 16-bit 25-ns real-time video/image signal processor
A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications
Merged BiCMOS logic to extend the CMOS/BiCMOS performance crossover below 2.5-V supply
Tail current noise suppression in RF CMOS VCOs
Correction on "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme" [Aug 09 2222-2232]
A High-Frequency Three-Level Buck Converter With Real-Time Calibration and Wide Output Range for Fast-DVS
A still-image encoder based on adaptive resolution vector quantization featuring needless calculation elimination architecture
Automatic verification of library-based IC designs
A Reflectionless Receiver With Absorptive IF Amplifier and Dual-Path Noise-Canceling LNA
A broad-bandwidth mixed analog/digital integrated circuit for the measurement of complex impedance
Design and analysis of CMOS analog signal processing circuits by means of a graphical MOST model
A Laser-Forwarded Coherent Transceiver in 45-nm SOI CMOS Using Monolithic Microring Resonators
A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS
Switched-current circuit design issues
A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK automatically calibrated Σ-Δ frequency synthesizer
A 24.8-μW Biopotential Amplifier Tolerant to 15-V PP Common-Mode Interference for Two-Electrode ECG Recording in 180-nm CMOS
A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link
Single-ended SRAM with high test coverage and short test time
A High-Throughput Maximum a Posteriori Probability Detector
A 23-ns 1-Mb BiCMOS DRAM
A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS
A Sub-GHz Multi-ISM-Band ZigBee Receiver Using Function-Reuse and Gain-Boosted N-Path Techniques for IoT Applications
1310/1550 nm Optical Receivers With Schottky Photodiode in Bulk CMOS
A low-power transponder IC for high-performance identification systems
Low Flicker Noise, Odd-Phase Master LO Active Mixer Using a Low Switching Frequency Scheme
A 30-ns 256-Mb DRAM with a multidivided array structure
Low standby power state storage for sub-130-nm technologies
A CMOS 0.25-μm continuous-time FIR filter with 125 ps per tap delay as a fractionally spaced receiver equalizer for 1-gb/s data transmission
A micropower centroiding vision processor
A novel class of complementary folded-cascode opamps for low voltage
A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects
Switched-capacitor bandpass delta-sigma A/D modulation at 10.7 MHz
A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects
A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI
A 10-GS/s NRZ/Mixing DAC With Switching-Glitch Compensation Achieving SFDR >64/50 dBc Over the First/Second Nyquist Zone
On-die termination resistors with analog impedance control for standard CMOS technology
A 42.2-Gb/s 4.3-pJ/b 60-GHz Digital Transmitter With 12-b/Symbol Polarization MIMO
Two-level pipelined systolic array graphics engine
An Intrinsically Linear Multi-Rate Continuous-Time Zoom ADC Achieving 97.4-dB DR and 105.7-dB SFDR in 50-kHz Signal Bandwidth
Design techniques for silicon compiler implementations of high-speed FIR digital filters
An 88-fJ/40-MHz [0.4 V]-0.61-pJ/1-GHz [0.9 V] Dual-Mode Logic 8 × 8 bit Multiplier Accumulator With a Self-Adjustment Mechanism in 28-nm FD-SOI
A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory
A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS
Calculation of critical charge of bipolar memory circuits
A Mutual Capacitance Touch Readout IC With 64% Reduced-Power Adiabatic Driving Over Heavily Coupled Touch Screen
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links
A 70 nm 16 Gb 16-Level-Cell NAND flash Memory
A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications
An analog front-end chip set employing an electro-optical mixed design on SPICE for 5-Gb/s/ch parallel optical interconnection
Optimization of phase-locked loop performance in data recovery systems
Highly efficient xDSL line drivers in 0.35-μm CMOS using a self-oscillating power amplifier
A 1.75-GHz highly integrated narrow-band CMOS transmitter with harmonic-rejection mixers
A generalized tanh law MOSFET model and its applications to CMOS inverters
Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio
Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface
Pulse-density modulation technique in VLSI implementations of neural network algorithms
Magnetic Relaxation Detector for Microbead Labels
A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response
A Self-Oscillating Boosting Amplifier With Adaptive Soft Switching Control for Piezoelectric Transducers
High-speed sensing techniques for ultrahigh-speed SRAMs
An Efficient Inductive Rectifier Based Piezo-Energy Harvesting Using Recursive Pre-Charge and Accumulation Operation
MATIA: a programmable 80 WμW/frame CMOS block matrix transform imager architecture
Analog line driver with adaptive impedance matching
A low-phase-noise 0.004-ppm/step DCXO with guaranteed monotonicity in the 90-nm CMOS process
A 100-MHz 2-D discrete cosine transform core processor
A 220-GHz Energy-Efficient High-Data-Rate Wireless ASK Transmitter Array
Efficient Wideband mmW Transceiver Front End for 5G Base Stations in 22-nm FD-SOI CMOS
A high-performance CMOS-SOI antenna switch for the 2.5-5-GHz band
A single poly EEPROM cell structure for use in standard CMOS processes
An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage
Design techniques for single-low-V DD CMOS systems
On-Chip Voltage Down Converter to Improve SRAM Read/Write Margin and Static Power for Sub-Nano CMOS Technology
A Low-Power Embedded SRAM for Wireless Applications
CMOS folding A/D converters with current-mode interpolation
A 13-dB IIP3 improved low-power CMOS RF programmable gain amplifier using differential circuit transconductance linearization for various terrestrial mobile D-TV applications
A two-path bandpass ΣΔ modulator for digital IF extraction at 20 MHz
A 33 MHz 70 dB-SNR Super-Source-Follower-Based Low-Pass Analog Filter
A 28-MHz wideband switched-capacitor bandpass filter with transmission zeros for high attenuation
Low-noise, low-distortion CMOS AM wide-band amplifiers matching a capacitive source
A 10 bit SAR ADC With Data-Dependent Energy Reduction Using LSB-First Successive Approximation
The Parity protected, multithreaded register files on the 90-nm itanium microprocessor
Miller and noise effects in a synchronizing flip-flop
A 100-GS/s Four-to-One Analog Time Interleaver in 55-nm SiGe BiCMOS
Design of Components and Circuits Underneath Integrated Inductors
An Energy-Efficient Time-Domain Asynchronous 2 b/Step SAR ADC With a Hybrid R-2R/C-3C DAC Structure
A 4-Path 42.8-to-49.5 GHz LO Generation With Automatic Phase Tuning for 60 GHz Phased-Array Receivers
Scaling of digital BiCMOS circuits
A silicon bipolar decision circuit operating up to 15 Gb/s
A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications
A 1-V 5.2-GHz CMOS synthesizer for WLAN applications
A 23
A 16-μA interface circuit for a capacitive flow sensor
A fourth-order bandpass delta-sigma modulator with reduced numbers of op amps
A Cool, Sub-0.2 dB Noise Figure GaN HEMT Power Amplifier With 2-Watt Output Power
A 6.7-fF/μm 2 bias-independent gate capacitor (BIGCAP) with digital CMOS process and its application to the loop filter of a differential PLL
A dynamically reconfigurable SIMD processor for a vision chip
Embedded 5 V-to-3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS technology
An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin
Digital-domain calibration of multistep analog-to-digital converters
Uniform-phase uniform-amplitude resonant-load global clock distributions
A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory
A 260 MHz IF Sampling Bit-Stream Processing Digital Beamformer With an Integrated Array of Continuous-Time Band-Pass ΔΣ Modulators
Integrated Power Management for Battery-Indifferent Systems With Ultra-Wide Adaptation Down to nW
A 1-GHz BiCMOS RF front-end IC
A 43-Gb/s full-rate clock transmitter in 0.18-μm SiGe BiCMOS technology
Margin Elimination Through Timing Error Detection in a Near-Threshold Enabled 32-bit Microcontroller in 40-nm CMOS
A 470- μ W, 102.6-dB DR, 20-kHz BW Calibration-Free ΔΣ Modulator With SFDR in Excess of 110 dBc Using an Intrinsically Linear 13-Level DAC
Low-power programmable gain CMOS distributed LNA
An outline font rendering processor with an embedded RISC CPU for high-speed hint processing
A positive-feedback transconductance amplifier with applications to high-frequency, high-Q CMOS switched-capacitor filters
A Differential Data-Aware Power-Supplied (D 2 AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications
The twin-transistor noise-tolerant dynamic circuit technique
Low-power logic styles: CMOS versus pass-transistor logic
MOSFET-only switched-capacitor circuits in digital CMOS technology
A self-calibrating delay-locked delay line with shunt-capacitor circuit scheme
Multiple-Ramp Column-Parallel ADC Architectures for CMOS Image Sensors
A Continuous-Time Delta-Sigma Modulator Using a Modified Instrumentation Amplifier and Current Reuse DAC for Neural Recording
A 5-GHz BiCMOS RFIC front-end for IEEE 802.11a/HiperLAN wireless LAN
High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters
A BER-Suppressed PUF With an Amplification of Process Mismatch Effect in an Oscillator Collapse Topology
An integrated direct-coupled 10-Gb/s driver for common-cathode VCSELs
A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro
A 20F 2 /Bit Current-Integration-Based Differential nand-Structured PUF for Stable and V/T Variation-Tolerant Low-Cost IoT Security
A monolithically integrated HEMT-HBT low noise high linearity variable gain amplifier
A Low-Power Digital DLL-Based Clock Generator in Open-Loop Mode
A 2.4-GHz CMOS transceiver for Bluetooth
Fully integrated 2.2-mW CMOS front end for a 900-MHz wireless receiver
A 9-V-Tolerant Stacked-Switched-Capacitor Stimulation System With Level-Adaptive Switch Control and Rapid Stimulus-Synchronized Charge Balancing for Implantable Devices
A high IIP2 downconversion mixer using dynamic matching
A VLSI analog computer/digital computer accelerator
New DRAM noise generation under half-V cc precharge and its reduction using a transposed amplifier
A JFET-CMOS radiation-tolerant charge-sensitive preamplifier
A Wideband Full-Duplex Receiver With Multi-Domain Self-Interference Cancellation Based on Capacitor Stacking Delay and Delay Compensation in Cancellers
Implementation of a learning Kohonen neuron based on a new multilevel storage technique
An insect vision-based motion detection chip
A Standardized 20-Tb/s Bandwidth Scalable Heterogeneous 2.5-D System Supporting Assembly Time Workload-Dependent Chiplet Configurations
Laser Voltage Probing Attack Detection With 100% Area/Time Coverage at Above/Below the Bandgap Wavelength and Fully-Automated Design
Design considerations of IGBT's in resonant converter applications
Introduction to the Special Issue on the 2016 Symposium on VLSI Circuits
A Nonuniform Sparse 2-D Large-FOV Optical Phased Array With a Low-Power PWM Drive
On-chip ESD protection design by using polysilicon diodes in CMOS process
An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories
A noise cancellation technique in active RF-CMOS mixers
Isolator-Less Near-Field RFID Reader for Sub-Cranial Powering/Data Link of Millimeter-Sized Implants
Electronically Temperature Compensated Silicon Bulk Acoustic Resonator Reference Oscillators
A Miniature Multinuclei NMR/MRI Platform With a High-Voltage SOI ASIC
A 44-MHz wideband switched-capacitor bandpass filter using double-sampling pseudo-two-path techniques
High-frequency fully differential filter using operational amplifiers without common-mode feedback
Bidirectional Peripheral Nerve Interface With 64 Second-Order Opamp-Less ΔΣ ADCs and Fully Integrated Wireless Power/Data Transmission
A 2.5-V 14-bit ΣΔ CMOS SOI capacitive accelerometer
A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band
A CMOS Imager With Focal Plane Compression Using Predictive Coding
4- and 13-GHz tuned amplifiers implemented in a 0.1-μm CMOS technology on SOI, SOS, and bulk substrates
On-chip test circuit for measuring substrate and line-to-line coupling noise
A 1-V 46-ns 16-Mb SOI-DRAM with body control technique
A low-power IDCT macrocell for MPEG-2 MP@ML exploiting data distribution properties for minimal activity
A signal-processing CMOS image sensor using a simple analog operation
A 0.0021 mm 2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS
An all-digital low-power IF GPS synchronizer
A family of user-programmable peripherals with a functional unit architecture
A high dynamic range current-mode amplifier for computed tomography
A 26-Gb/s 140-GHz OOK CMOS Transmitter and Receiver Chipset for High-Speed Wireless and Dielectric Waveguide Communication
High power and high speed InP DHBT driver IC's for laser modulation
A 50-112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS
A Precision Capacitance-to-Digital Converter With 16.7-bit ENOB and 7.5-ppm/°C Thermal Drift
Sub-Sampling Direct RF-to-Digital Converter With 1024-APSK Modulation for High Throughput Polar Receiver
A Fast T&H Overcurrent Detector for a Spinning Hall Current Sensor With Ping-Pong and Chopping Techniques
A 1.5-μW Fully-Integrated Keyword Spotting SoC in 28-nm CMOS With Skip-RNN and Fast-Settling Analog Frontend for Adaptive Frame Skipping
A power-efficient channel coder/decoder chip for GSM terminals
CMOS Distributed Active Power Combiners and Splitters for Multi-Antenna UWB Beamforming Transceivers
A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBT limiting amplifier
An Ultra-Low-Power Fully-Static Contention-Free Flip-Flop With Complete Redundant Clock Transition and Transistor Elimination
A Translinear, Log-Domain FPAA on Standard CMOS Technology
A 10 ns hybrid number system data execution unit for digital signal processing systems
Statistical leakage current reduction in high-leakage environments using locality of block activation in time domain
Metamorphic HEMT MMICs and Modules for Use in a High-Bandwidth 210 GHz Radar
Octave-Tuning Dual-Core Folded VCO Leveraging a Triple-Mode Switch-Less Tertiary Magnetic Loop
Jitter in ring oscillators
A Compact and Ultra-Low-Power 32-kHz Conduction-Angle-Adaptive Crystal Oscillator
A low-power switched-capacitor variable gain amplifier
80-MHz bandpass ΔΣ modulators for multimode digital IF receivers
A 76-81 GHz 2×8 MIMO Radar Transceiver With Broadband Fast Chirp Generation and 16-Antenna-in-Package Virtual Array
A Sub-mW Fractional-N ADPLL With FOM of -246 dB for IoT Applications
1-W 3.3-16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller
An accurate CMOS sample-and-hold circuit
Design and Analysis of an 8 mW, 1 GHz Span, Passive Spectrum Scanner With >+31 dBm Out-of-Band IIP3 Using Periodically Time-Varying Circuit Components
Guest Editorial 2019 Custom Integrated Circuits Conference
A 28 nm CMOS Dual-Band Concurrent WLAN and Narrow Band Transmitter With On-Chip Feedforward TX-to-TX Interference Cancellation Path for Low Antenna-to-Antenna Isolation in IoT Devices
A 20-Gb/s 0.13-μm CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer
A Low-IF/Zero-IF Reconfigurable Analog Baseband IC With an I/Q Imbalance Cancellation Scheme
A 95% Peak Efficiency Modified KY Converter With Improved Flying Capacitor Charging in DCM for IoT Applications
A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication
A 10000 frames/s CMOS digital pixel sensor
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application
Ultralow-power GaAs MESFET MSI circuits using two-phase dynamic FET logic
A second-order double-sampled delta-sigma modulator using additive-error switching
Superharmonic injection-locked frequency dividers
70-MHz 2- mu m CMOS bit-level systolic array median filter
An Interleaved Full Nyquist High-Speed DAC Technique
A variable threshold voltage inverter for CMOS programmable logic circuits
A fast-hopping single-PLL 3-band MB-OFDM UWB synthesizer
A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier
An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing
Driving source-line cell architecture for sub-1-V high-speed low-power applications
Miniaturized, 0.01 mm 2 , Resistor-Based Thermal Sensor With an Energy Consumption of 0.9 nJ and a Conversion Time of 80 µs for Processor Applications
Generation of Accurate Reference Current for Data Sensing in High-Density Memories by Averaging Multiple Pairs of Dummy Cells
The impact of device type and sizing on phase noise mechanisms
Comments on 'Totally self-checking CMOS circuit design for breaks and stuck-on faults'
A new CMOS NAND logic circuit for reducing hot-carrier problems
A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier
A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization
A Single-Phase Contention- and Redundant Transition-Free Flip-Flop With Improved DQ Latency
An IDDQ sensor for concurrent timing error detection