yusuke1997/dblp-id-title huggingface dataset:
A 3-V continuous-time filter with on-chip tuning for IS-95
A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories
An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller
A 1-V micropower log-domain integrator based on FGMOS transistors operating in weak inversion
Silicon-based distributed voltage-controlled oscillators
220-GHz Solid-State Power Amplifier Modules
A 7-nm FinFET 1.2-TB/s/mm 2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver
A 2-GHz quadrature hybrid implemented in CMOS technology
A 0.18-$muhbox m$CMOS Selective Receiver Front-End for UWB Applications
Introduction to the Special Section on the 2018 Asian Solid-State Circuits Conference (A-SSCC)
Ultra-Wideband Switched-Capacitor Delays and Circulators - Theory and Implementation
Introduction to the Special Issue on the 2023 Symposium on VLSI Circuits
A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O Transceiver in 65 nm CMOS
A single-ended 12-bit 20 Msample/s self-calibrating pipeline A/D converter
Comments on "A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter"
A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM
A 230-GHz High-Power and Wideband Coupled Standing Wave VCO in 65-nm CMOS
A 10-Gb/s silicon bipolar IC for PRBS testing
A 0.028-mm 2 32 -MHz RC Frequency Reference With an Inaccuracy of ±900 ppm From -40 ∘ C to 125 ∘ C and ±1600 ppm After Accelerated Aging
Temperature dependence of Q and inductance in spiral inductors fabricated in a silicon-germanium/BiCMOS technology
Broadband Active Load-Modulation Power Amplification Using Coupled-Line Baluns: A Multifrequency Role-Exchange Coupler Doherty Amplifier Architecture
A Battery-Input Three-Mode Buck-Boost Hybrid DC-DC Converter With 97.6% Peak Efficiency
A Sierpinski Space-Filling Clock Tree Using Multiply-by-3 Fractal-Coupled Ring Oscillators
A 0.25-0.4-V, Sub-0.11-mW/GHz, 0.15-1.6-GHz PLL Using an Offset Dual-Path Architecture With Dynamic Charge Pumps
A 10-b 75-MSPS subranging A/D converter with integrated sample and hold
A Thermistor-Based Temperature Sensor for a Real-Time Clock With ± 2 ppm Frequency Stability
Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band
A new MMIC sampling phase detector design for space applications
A Current and Temperature Limiting System in a 7-nm Hexagon™ Compute Digital Signal Processor
Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's
A 48-MHz Differential Crystal Oscillator With 168-fs Jitter in 28-nm CMOS
A progressive scan CCD image sensor for DSC applications
A BiCMOS Ultra-Wideband 3.1-10.6-GHz Front-End
Ultra-Low-Power and Compact-Area Analog Audio Feature Extraction Based on Time-Mode Analog Filterbank Interpolation and Time-Mode Analog Rectification
High-Efficiency WCDMA Envelope Tracking Base-Station Amplifier Implemented With GaAs HVHBTs
Integrated circuits for a real-time large-vocabulary continuous speech recognition system
A Cryogenic Broadband Sub-1-dB NF CMOS Low Noise Amplifier for Quantum Applications
Co-Design of a CMOS Rectifier and Small Loop Antenna for Highly Sensitive RF Energy Harvesters
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor
A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs
A low-power high-performance SiGe BiCMOS 802.11a/b/g transceiver IC for cellular and bluetooth Co-existence applications
A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI
Dynamic Guardband Features of the IBM z17 System
A 2.72-fJ/Conversion-Step 13-bit SAR ADC With Wide Common-Mode Complementary Split Pre-Amplifier Comparator and Grounded-Finger CDAC
An 82-107.6-GHz Integer-N ADPLL Employing a DCO With Split Transformer and Dual-Path Switched-Capacitor Ladder and a Clock-Skew-Sampling Delta-Sigma TDC
A multiplexer-based architecture for high-density, low-power gate arrays
A dual-mode 802.11b/bluetooth radio in 0.35-μm CMOS
Power Noise in TSV-Based 3-D Integrated Circuits
All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles
A Digitally Enhanced Dynamically Reconfigurable Analog Platform for Low-Power Signal Processing
Design and Analysis of Actively-Deskewed Resonant Clock Networks
An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC With Dual-Path Time-Assisted Residue Generation Scheme
A 22-kHz multibit switched-capacitor sigma-delta D/A converter with 92 dB dynamic range
A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations
A VLSI chip set for a multiprocessor workstation. II. A memory management unit and cache controller
A Nonvolatile 2-Mbit CBRAM Memory Core Featuring Advanced Read and Program Control
A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme
A monolithic GaAs low power L-band successive detection logarithmic amplifier
A unique MMIC broadband power amplifier approach
A Low Power, Scalable, DAC Architecture for Liquid Crystal Display Drivers
A 14-nA, Highly Efficient Triple-Output Thermoelectric Energy Harvesting System Based on a Reconfigurable TEG Array
A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator
A pseudologarithmic rectifier using unbalanced bias MFMOS differential pairs
Four Channel, 40 ps Resolution, Fully Integrated Time-to-Amplitude Converter for Time-Resolved Photon Counting
Experimental comparison of substrate noise coupling using different wafer types
Transformer-Based Uneven Doherty Power Amplifier in 90 nm CMOS for WLAN Applications
Piezoelectric Energy Harvesting Interface Using Self-Bias-Flip Rectifier and Switched-PEH DC-DC for MPPT
Diode-biased AC-coupled ECL-to-CMOS interface circuit
Highly integrated three-dimensional MMIC technology applied to novel masterslice GaAs- and Si-MMICs
Broad-band SiGe MMICs for phased-array radar applications
A 0.5-to-3 GHz Software-Defined Radio Receiver Using Discrete-Time RF Signal Processing
STICKER-T: An Energy-Efficient Neural Network Processor Using Block-Circulant Algorithm and Unified Frequency-Domain Acceleration
A 1.2 GFLOPS neural network chip for high-speed neural network servers
A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC
A high temperature precision amplifier
A Full-Duplex Single-Chip Transceiver With Self-Interference Cancellation in 0.13 µm SiGe BiCMOS for Electron Paramagnetic Resonance Spectroscopy
A fully digital, energy-efficient, adaptive power-supply regulator
NECTAR: a knowledge-based environment to enhance SPICE
An Optimized Driver for SiC JFET-Based Switches Enabling Converter Operation With More Than 99% Efficiency
A 300°C dynamic-feedback instrumentation amplifier
An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm 2
CMOS Impedance Analyzer for Nanosamples Investigation Operating up to 150 MHz With Sub-aF Resolution
Study of BiCMOS logic gate configurations for improved low-voltage performance
A low logic depth complex multiplier using distributed arithmetic
Development of a new type of self-scanned electron image sensing integrated circuit
120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs
Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement
An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS
CMOS high-speed dual-modulus frequency divider for RF frequency synthesis
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains
Combined Linear and Δ-Modulated Switch-Mode PA Supply Modulator for Polar Transmitters
A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits
A BiCMOS analog front-end circuit for an FDM-based ADSL system
VLSI implementation of a variable-length pipeline scheme for data-driven processors
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS"
A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances
A 20-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Jitter Immunity Improved Full Clock Period SCR (FSCR) DAC and High-Speed DWA
A CCD/CMOS focal-plane array edge detection processor implementing the multiscale veto algorithm
Large-Scale SRAM Variability Characterization in 45 nm CMOS
A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme
A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC
A Four-Camera VGA-Resolution Capsule Endoscope System With 80-Mb/s Body Channel Communication Transceiver and Sub-Centimeter Range Capsule Localization
A Quadrature Switched Capacitor Power Amplifier
A Real-Time Image-Feature-Extraction and Vector-Generation VLSI Employing Arrayed-Shift-Register Architecture
1-V DTMOS-Based Class-AB Operational Amplifier: Implementation and Experimental Results
Bandwidth enhancement for transimpedance amplifiers
A 1.7-V adjustable I/O interface for low-voltage fast SRAMs
A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP
Si-analog IC's for 20 Gb/s optical receiver
A Process-Scalable Ultra-Low-Voltage Sleep Timer With a Time-Domain Amplifier and a Switch-Less Resistance Multiplier
CV-CIM: A Hybrid Domain Xor-Derived Similarity-Aware Computation-in-Memory Supporting Cost-Volume Construction
Erratum to "A Flying-Inductor Hybrid DC-DC Converter for 1-Cell and 2-Cell Smart-Cable Battery Chargers"
An offset-canceling low-noise lock-in architecture for capacitive sensing
A 79 pJ/b 80 Mb/s Full-Duplex Transceiver and a 42.5µW 100 kb/s Super-Regenerative Transceiver for Body Channel Communication
Subthreshold, Varactor-Driven CMOS Floating-Gate Current Memory Array With Less Than 150-ppm/°K Temperature Sensitivity
Very-high-speed InP/InGaAs HBT ICs for optical transmission systems
A polar modulator transmitter for GSM/EDGE
A 1.8∼3.2-GHz fully differential GaAs MESFET PLL
Introduction to the Special Issue on the 2013 IEEE Custom Integrated Circuits Conference
An 11 GHz 3-V SiGe voltage controlled oscillator with integrated resonator
A 1.75-GHz polar modulated CMOS RF power amplifier for GSM-EDGE
Sequence-Coded Multilevel Signaling for High-Speed Interface
A study of phase noise in colpitts and LC-tank CMOS oscillators
A 48-V Wide-V in 9-25-MHz Resonant DC-DC Converter
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%
An Ultrasonic Driver Array in Metal-Oxide Thin-Film Technology Using a Hybrid TFT-Si DLL Locking Architecture
A Magnetically Tuned Quadrature Oscillator
Towards an analog system design environment
A GSM-Based Clock-Harvesting Receiver With -87 dBm Sensitivity for Sensor Network Wake-Up
HGRP: A 181-μ W Real-Time Hand Gesture Recognition Processor Based on Bi-Directional Convolution and Iteration-Free Feature Clustering
A DC-to-108-GHz CMOS SOI Distributed Power Amplifier and Modulator Driver Leveraging Multi-Drive Complementary Stacked Cells
Integrated circuit technology options for RFICs-present status and future directions
Analog Front End of 50-Gb/s SiGe BiCMOS Opto-Electrical Receiver in 3-D-Integrated Silicon Photonics Technology
Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially Enhance Hardware Security of Large-Scale CPU Clusters
A 1-V heterogeneous reconfigurable DSP IC for wireless baseband digital signal processing
A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS
An IF-to-Baseband ΣΔ Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range
High-Efficiency Millimeter-Wave Single-Ended and Differential Fundamental Oscillators in CMOS
Robust design of rail-to-rail CMOS operational amplifiers for a low power supply voltage
An Active-Matrix OLED Driver CMOS IC With Compensation of Non-Uniform Routing-Line Resistances in Ultra-Thin Panel Bezel
A CMOS multiparameter biochemical microsensor with temperature control and signal interfacing
SESOMP: A Scalable and Energy-Efficient Self-Organizing Map Processor for IoT Devices
Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead
A high-density data-path generator with stretchable cells
A 0.065-mm 2 19.8-mW Single-Channel Calibration-Free 12-b 600-MS/s ADC in 28-nm UTBB FD-SOI Using FBB
Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation
A Continuous-Grain Silicon-System LCD With Optical Input Function
A novel all-digital PLL with software adaptive filter
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
An experimental BiCMOS video 10 bit ADC
A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V TH Read-Port, and Offset Cell VDD Biasing Techniques
A 128×128 120 dB 15 µs Latency Asynchronous Temporal Contrast Vision Sensor
A micropower class-AB CMOS log-domain filter for DECT applications
CRFF: A Static Contention-Free 23T Flip-Flop With Three Clock Load Transistors for Ultra-Low-Power Applications
A 0.25-μm, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bit microprocessor
An Efficient Piezoelectric Energy Harvesting Interface Circuit Using a Sense-and-Set Rectifier
A Fully Configurable Non-Linear Mixed-Signal Interface for Multi-Sensor Analytics
An 11.1 Gbps Analog PRML Receiver for Electronic Dispersion Compensation of Fiber Optic Communications
A 500-nA sixth-order bandpass SC filter
Characterization of GaAs MESFET gate capacitances
A 28-nm 16-kb Aggregation and Combination Computing-in-Memory Macro With Dual-Level Sparsity Modulation and Sparse-Tracking ADCs for GCNs
A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization
A Millimeter-Wave Non-Magnetic Passive SOI CMOS Circulator Based on Spatio-Temporal Conductivity Modulation
Monolithic integration of 5-Gb/s optical receiver block for short distance communication
A 3.3-V, 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme
Non-Linear CNN-Based Read Channel for Hard Disk Drive With 30% Error Rate Reduction and Sequential 200-Mbits/s Throughput in 28-nm CMOS
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS
DDJ-Adaptive SAR TDC-Based Timing Recovery for Multilevel Signaling
Comparison of CMOS and BiCMOS 1-Mbit DRAM performance
Zen: An Energy-Efficient High-Performance × 86 Core
A 14-bit delta-sigma ADC with 8×OSR and 4-MHz conversion bandwidth in a 0.18-μm CMOS process
A Fully Integrated MIMO Multiband Direct Conversion CMOS Transceiver for WLAN Applications (802.11n)
A 50-66-GHz Phase-Domain Digital Frequency Synthesizer With Low Phase Noise and Low Fractional Spurs
THz Prism: One-Shot Simultaneous Localization of Multiple Wireless Nodes With Leaky-Wave THz Antennas and Transceivers in CMOS
GaAs two-phase dynamic FET logic: a low-power logic family for VLSI
An ADSL-RT full-rate analog front end IC with integrated line driver
A 1.2-ns HEMT 64-kb SRAM
A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μA rms Input Noise in 22 nm FinFET CMOS
A low-power 16×16-b parallel multiplier utilizing pass-transistor logic
X-band HBT VCO with high-efficiency CB buffer amplifier
PROXIMA: PROlog eXecutIon MAchine
Low-power monolithic RF peak detector analysis
An Eight-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor
A Low-Noise Fractional- ${N}$ Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications
Design of a CMOS buffered switch for a Gigabit ATM switching network
A Simultaneous Dual-Carrier Transformer-Coupled Passive Mixer-First Receiver Front-End Supporting Blocker Suppression
A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration
Design Considerations of High- Frequency-Reference Fractional- N PLL: Architecture and Nonidealities
A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier
A 3.3 GHz Spread-Spectrum Clock Generator Supporting Discontinuous Frequency Modulations in 28 nm CMOS
A 3 THz CMOS Image Sensor
Reply to "Comments on the optimum CMOS tapered buffer problem"
An integrated 150-V pp , 12-V/ns, class-AB CRT-driving amplifier
A new cryogenic CMOS readout structure for infrared focal plane array
A Fully-Integrated Wideband Digital Polar Transmitter With 11-bit Digital-to-Phase Converter in 40nm CMOS
Dynamic voltage and frequency management for a low-power embedded microprocessor
A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM
A Fully Integrated 4 × 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 µm CMOS SOI Technology
30-Gb/s 1.11-pJ/bit Single-Ended PAM-3 Transceiver for High-Speed Memory Links
A 124-dB Dynamic-Range SPAD Photon-Counting Image Sensor Using Subframe Sampling and Extrapolating Photon Count
A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface
A 170 MHz RF front-end for ERMES pager applications
An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector
An interpolative bandpass converter on a 1.2- mu m BiCMOS analog/digital array
A 1.2 GSample/s Double-Switching CMOS THA With -62 dB THD
MDSP-II: a 16-bit DSP with mobile communication accelerator
A Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis
A high-speed clamped bit-line current-mode sense amplifier
Pixel noise suppression via SoC management of tapered reset in a 1920×1080 CMOS image sensor
A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs
A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector
A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC
High-performance standard cell library and modeling technique for differential advanced bipolar current tree logic
A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC
A physically based compact model of partially depleted SOI MOSFETs for analog circuit simulation
A unified turbo/Viterbi channel decoder for 3GPP mobile wireless in 0.18-μm CMOS
Novel area-time efficient static CMOS totally self-checking comparator
A 3-V, 2%-mW multibit current-mode ΣΔ DAC with 100 dB dynamic range
Matching properties of MOS transistors
An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage
A Highly Linear Two-Stage Amplifier Integrated Circuit Using InGaP/GaAs HBT
A 1.5-V direct digital synthesizer with tunable delta-sigma modulator in 0.13-μm CMOS
A Self-Tuning Resonant-Inductive-Link Transmit Driver Using Quadrature Symmetric Delay Trimmable Phase-Switched Fractional Capacitance
A System-on-Chip EPC Gen-2 Passive UHF RFID Tag With Embedded Temperature Sensor
A 200-mW, 3.3-V, CMOS color camera IC producing 352×288 24-b video at 30 frames/s
CMOS T/R Switch Design: Towards Ultra-Wideband and Higher Frequency
A Highly Integrated Hybrid DC-DC Converter With nH-Scale IPD Inductors
A secondary cache controller design for a high-end microprocessor
A feedback-type BiCMOS logic gate
Low-power MOS integrated filter with transconductors with spoilt current sources
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration
A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS
A 2.4-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-Noise and Low-Spur Performance
An Implantable 64-Channel Wireless Microsystem for Single-Unit Neural Recording
A Smart Contact Lens Controller IC Supporting Dual-Mode Telemetry With Wireless-Powered Backscattering LSK and EM-Radiated RF Transmission Using a Single-Loop Antenna
Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices
An input-free V T extractor circuit using a two-transistor differential amplifier
An above IC MEMS RF switch
A 600-MHz median-type digital filter on GaAs
A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage
500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC
A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization
250-MHz BiCMOS super-high-speed video signal processor (S-VSP) ULSI
Analysis and Design of a Foam-Cladded PMF Link With Phase Tuning in 28-nm CMOS
Limitations, innovations, and challenges of circuits and devices into a half micrometer and beyond
A 2.7-V CMOS dual-mode baseband filter for PDC and WCDMA
A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS
Design of a wide-band frequency synthesizer based on TDC and DVC techniques
An Intrinsically Linear Wideband Polar Digital Power Amplifier
A 16-mW, 120-dB linear switched-capacitor delta-sigma modulator with dynamic biasing
A 40-Gb/s SiGe-BiCMOS MZM Driver With 6-V p-p Output and On-Chip Digital Calibration
Pulsed current-mode signaling for nearly speed-of-light intrachip communication
Fully Integrated Switched-Inductor-Capacitor Voltage Regulator With 0.82-A/mm 2 Peak Current Density and 78% Peak Power Efficiency
A Time-Domain SAR Smart Temperature Sensor With Curvature Compensation and a 3σ Inaccuracy of -0.4°C ∼ +0.6°C Over a 0°C to 90°C Range
A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS
A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications
A 65-mW, 10-bit, 40-Msample/s BiCMOS Nyquist ADC in 0.8 mm 2
Dyamond: Compact and Efficient 1T1C DRAM IMC Accelerator With Bit Column Addition for Memory-Intensive AI
A 220-mm 2 , four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance
A 2-GS/s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC
A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping ΔΣ TDC
64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay
Patent Abstracts
A Threshold Implementation-Based Neural Network Accelerator With Power and Electromagnetic Side-Channel Countermeasures
RAC-NAF: A Reconfigurable Analog Circuitry for Nonlinear Activation Function Computation in Computing-in-Memory
A Power-Efficient Single-Mode Buck-Boost DC-DC Converter With Bilaterally Symmetrical Hybrid Topology
A 2-dB noise figure 900-MHz differential CMOS LNA
Erratum to "A DC-100 GHz Active Frequency Doubler With a Low-Voltage Multiplier Core"
Noise in distributed MESFET preamplifiers
An analog CMOS front-end for a D2-MAC TV decoder
A 130.7-mm 2 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology
1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS
Efficient symbolic computation of approximated small-signal characteristics of analog integrated circuits
A 6.7-MFLOPS floating-point coprocessor with vector/matrix instructions
A 10-b, 500-MSample/s CMOS DAC in 0.6 mm 2
A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode
An All-Digital Fully Integrated Inductive Buck Regulator With A 250-MHz Multi-Sampled Compensator and a Lightweight Auto-Tuner in 130-nm CMOS
A performance-driven placement tool for analog integrated circuits
A 0.8-dB NF ESD-Protected 9-mW CMOS LNA operating at 1.23 GHz [for GPS receiver]
External Capacitor-Less Low Drop-Out Regulator With 25 dB Superior Power Supply Rejection in the 0.4-4 MHz Range
A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration
A 312-GHz CMOS Injection-Locked Radiator With Chip-and-Package Distributed Antenna
Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication
Switch Bootstrapping for Precise Sampling Beyond Supply Voltage
A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS