yusuke1997/dblp-id-title huggingface dataset:
Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVs
Analytical Solutions for Distributed Interconnect Models - Part I: Step Input Response of Finite and Semi-Infinite Lines
Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method
Loop based design for wafer scale systems
A Dedicated Monitoring Infrastructure for Multicore Processors
From real-time emulation to ASIC integration for image processing applications
Low-power on-chip communication based on transition-aware global signaling (TAGS)
Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods
Unlocking the True Potential of 3-D CPUs With Microfluidic Cooling
Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs
An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data-Index Decoupling Workflow
Efficient Error Detection Schemes for ECSM Window Method Benchmarked on FPGAs
Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions
IPOCIM: Artificial Intelligent Architecture Design Space Exploration With Scalable Ping-Pong Computing-in-Memory Macro
Predictive Thermal Management for Energy-Efficient Execution of Concurrent Applications on Heterogeneous Multicores
Free Razor: A Novel Voltage Scaling Low-Power Technique for Large SoC Designs
An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing
Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits
Automated Phase-Noise-Aware Design of RF Clock Distribution Circuits
ElastiStore: Flexible Elastic Buffering for Virtual-Channel-Based Networks on Chip
A Parallel and Incremental Extraction of Variational Capacitance With Stochastic Geometric Moments
Analysis of blocking dynamic circuits
IMCRYPTO: An In-Memory Computing Fabric for AES Encryption and Decryption
High-Performance ECC Scalar Multiplication Architecture Based on Comb Method and Low-Latency Window Recoding Algorithm
On circuit clustering for area/delay tradeoff under capacity and pin constraints
Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits
A Fast Settling Fractional-N DPLL With Loop-Order Switching
ReTern: Exploiting Natural Redundancy and Sign Transformations for Enhanced Fault Tolerance in Compute-in-Memory-Based Ternary LLMs
Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters
EA-Based LDE-Aware Fast Analog Layout Retargeting With Device Abstraction
Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process
An Area and Energy-Efficient Systolic Array Accelerator Architecture for Deep Neural Networks Using Stochastic Computing
CRC-Based Error Detection Constructions for FLT and ITA Finite Field Inversions Over GF(2 m )
A Method to Reduce the Effect on Image Quality Caused by Resistance of Column Bus
Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA
Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation
An RF-DC Converter IC With On-Chip Adaptive Impedance Matching and 307- μW Peak Output Power for Health Monitoring Applications
A Fully Integrated 10-V Pulse Driver Using Multiband Pulse-Frequency Modulation in 65-nm CMOS
A Fully Digital Semirotational Frequency Detection Algorithm for Bang-Bang CDRs
Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation
A High-Speed 2-bit/Cycle SAR ADC With Time-Domain Quantization
Comparative Analysis of Simultaneous Switching Noise Effects in MWCNT Bundle and Cu Power Interconnects in CNTFET-Based Ternary Circuits
Algorithm and Architecture Design of FAST-C Image Corner Detection Engine
An Energy-Efficient Four-Channel Interface ASIC for IRFPAs With Optimized Resistor-Sharing Technique Achieving 88.1-dB SNDR
A Low-Pass Filter Bandwidth Adaptation Technique for Phase Interpolators
Energy-Efficient Pedestrian Detection System: Exploiting Statistical Error Compensation for Lossy Memory Data Compression
Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion
All-Synthesizable Current-Mode Transmitter Driver for USB2.0 Interface
Lossless Neural Network Model Compression Through Exponent Sharing
LVDCSL: a high fan-in, high-performance, low-voltage differential current switch logic family
Formal Verification of Architectural Power Intent
Insights Into Tunnel FET-Based Charge Pumps and Rectifiers for Energy Harvesting Applications
Thermomechanical Stress-Aware Management for 3-D IC Designs
Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits
Fast Configurable-Cache Tuning With a Unified Second-Level Cache
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter
IP Protection of Mesh NoCs Using Square Spiral Routing
Power Delivery Design, Signal Routing, and Performance of On-Chip Cobalt Interconnects in Advanced Technology Nodes
A Neuromorphic Approach to Path Planning Using a Reconfigurable Neuron Array IC
High-performance carry chains for FPGA's
Detecting Hardware Trojans in PCBs Using Side Channel Loopbacks
Miniaturization Strategy for Directional Couplers Based on Through-Silicon Via Insertion and Neuro-Transfer Function Modeling Method
Design of VHDL-based totally self-checking finite-state machine and data-path descriptions
Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares
Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM
Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions
Low-power arithmetic for the processing of video signals
An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability
Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter
Low Phase Noise Ku-Band VCO With Optimal Switched-Capacitor Bank Design
In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands
A Fast and Reliable Cross-Point Three-State/Cell ReRAM
Mitigating the Impact of Process Variation on the Performance of 3-D Integrated Circuits
A 60-Mode High-Throughput Parallel-Processing FFT Processor for 5G/4G Applications
A new maximal diagnosis algorithm for interconnect test
An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis
Falcon: A Fused-Layer Accelerator With Layer-Wise Hybrid Inference Flow for Computational Imaging CNNs
An 8-Bit 4-GS/s Single-Channel Two-Step ADC Featuring Non-Symmetrical Pipeline Timing and Hybrid-Loop Amplifier
Erratum to "Efficient VLSI Implementation of 2 n Scaling of Signed Integer in RNS {2 n -1, 2 n , 2 n +1}"
Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications
Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects
A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS
Network-on-Chip-Enabled Multicore Platforms for Parallel Model Predictive Control
Nonscaling Adders and Subtracters for Stochastic Computing Using Markov Chains
Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis
Using the Gate-Bulk Interaction and a Fundamental Current Injection to Attenuate IM3 and IM2 Currents in RF Transconductors
Analysis and Design of Unified Architectures for Zero-Attraction-Based Sparse Adaptive Filters
Reliability Analysis and Optimization of Power-Gated ICs
Probability-Driven Multibit Flip-Flop Integration With Clock Gating
RTA: A Reconfigurable Transformer Accelerator Exploiting Sparsity via Low-Bit-Width Prediction
A 57-71-GHz Beamforming Front-End With 6.6-dB NF and 13.9-dBm OP 1 dB Using a Low-Loss Switchable Triple-Coil Transformer
Optimal and heuristic algorithms for solving the binding problem
A 13.56-MHz CMOS Active Rectifier With a Voltage Mode Switched-Offset Comparator for Implantable Medical Devices
A DPS array with programmable resolution and reconfigurable conversion time
Temperature-Insensitive Dual- V th Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence
Energy-Efficient Time-Based Adaptive Encoding for Off-Chip Communication
Adaptable Approximate Multiplier Design Based on Input Distribution and Polarity
Low-Power Snoop Architecture for Synchronized Producer-Consumer Embedded Multiprocessing
AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction
Application of STD to latch-power estimation
Device-Aware Yield-Centric Dual-V t Design Under Parameter Variations in Nanoscale Technologies
On-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB)
Sparsification of Dense Capacitive Coupling of Interconnect Models
Gradual-N-Justification (GNJ) to Reduce False-Positive Hardware Trojan Detection in Gate-Level Netlist
High-Current Drivability Fibonacci Charge Pump With Connect-Point-Shift Enhancement
Source Code Error Detection in High-Level Synthesis Functional Verification
Exploiting Same Tag Bits to Improve the Reliability of the Cache Memories
Fast Bit Screening of Automotive Grade EEPROMs - Continuous Improvement Exercise
Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop
Gain-Cell Embedded DRAM Under Cryogenic Operation - A First Study
Continuous-Time Hybrid ΔΣ Modulators for Sub-μW Power Multichannel Biomedical Applications
Switching Activity as a Test Compaction Heuristic for Transition Faults
Supply-Noise Interactions Among Submodules Inside a Charge-Pump PLL
ABS: Accumulation Bit-Width Scaling Method for Designing Low-Precision Tensor Core
A 20.5-nW Resistor-Less Bandgap Voltage Reference With Self-Biased Compensation for Process Variations
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs
High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations
Rethinking the Wirelength Benefit of 3-D Integration
Countering Side-Channel Attacks With a Dynamic S-Box Based on Affine Transformations and Gold Sequences
Single Exact Single Approximate Adders and Single Exact Dual Approximate Adders
Buried Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Logic Circuits Under Aggressive Voltage Scaling
Logical Effort for CMOS-Based Dual Mode Logic Gates
A Novel Peak Power Supply Noise Measurement and Adaptation System for Integrated Circuits
Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs
A Calibratable Detector for Invasive Attacks
High Throughput Spatial Convolution Filters on FPGAs
Signal Processing With Direct Computations on Compressively Sensed Data
A Colpitts CMOS Quadrature VCO Using Direct Connection of Substrates for Coupling
Embedded DRAM-Based Memory Customization for Low-Cost FFT Processor Design
Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy
Application-Guided Power Gating Reducing Register File Static Power
An Efficient 1.4-GS/s 10-bit Timing-Skew-Free Time-Interleaved SAR ADC With a Centralized Sampling Frontend
A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G
Interstratum Connection Design Considerations for Cost-Effective 3-D System Integration
The Dependence of BTI and HCI-Induced Frequency Degradation on Interconnect Length and Its Circuit Level Implications
135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder
Lifetime Reliability-Aware Digital Synthesis
Matrix Codes for Reliable and Cost Efficient Memory Chips
366-kS/s 1.09-nJ 0.0013-${\rm mm}^{2}$ Frequency-to-Digital Converter Based CMOS Temperature Sensor Utilizing Multiphase Clock
Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme
Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications
Trigger-Centric Loop Mapping on CGRAs
An All-Digital Gigahertz Class-S Transmitter in a 65-nm CMOS
A Fast-Locking All-Digital Deskew Buffer With Duty-Cycle Correction
The Siemens high-level synthesis system CALLAS
TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors
Asynchronous gate-diffusion-input (GDI) circuits
An activity-driven encoding scheme for power optimization in microprogrammed control unit
Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating
Novel Interpolation and Polynomial Selection for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding
Page Type-Aware Data Migration Technique for Read Disturb Management of NAND Flash Memory
A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology
Metal Layer Sharing: A Routing Optimization Technique for Monolithic 3D ICs
Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays
NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients
Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System
High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis
Instruction buffering for nested loops in low-power design
Wiring requirement and three-dimensional integration technology for field programmable gate arrays
Synthesis and Analysis of Design-Dependent Ring Oscillator (DDRO) Performance Monitors
Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension
Predictive system shutdown and other architectural techniques for energy efficient programmable computation
A 6-mW, 70.1-dB SNDR, and 20-MHz BW Continuous-Time Sigma-Delta Modulator Using Low-Noise High-Linearity Feedback DAC
The Design of High-Performance Dynamic Asynchronous Pipelines: High-Capacity Style
An HLA-Based Distributed Cosimulation Framework in Mixed-Signal System-on-Chip Design
Pragmatic Integration of an SRAM Row Cache in Heterogeneous 3-D DRAM Architecture Using TSV
Online Fault Tolerance Technique for TSV-Based 3-D-IC
SCARE: Side Channel Attack on In-Memory Computing for Reverse Engineering
A 2.56-Gb/s Serial Wireline Transceiver That Supports an Auxiliary Channel in 65-nm CMOS
A Continuous-Time Replication Strategy for Efficient Multicast in Asynchronous NoCs
On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses
Evaluation of energy consumption in RC ladder circuits driven by a ramp input
A Holistic Analysis of Circuit Performance Variations in 3-D ICs With Thermal and TSV-Induced Stress Considerations
A Digital FP CIM Macro With Cascaded Row-Elimination for Exponent Comparison and In-Memory Mantissa Sparsity Detection
The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style
Implementation of Multiple-Step Quantized STDP Based on Novel Memristive Synapses
On the design of fast, easily testable ALU's
A Compact and Accurate Gaussian Variate Generator
Novel Nonlinear Function Shift Method for Generating Multiscroll Attractors Using Memristor-Based Control Circuit
Power-Efficient VLSI Architecture of a New Class of Dyadic Gabor Wavelets for Medical Image Retrieval
A true single-phase energy-recovery multiplier
A High-Speed Dynamic Element Matching Decoder With Integrated Background Calibration Control
Test Pattern Generation and Critical Path Selection in the Presence of Statistical Delays
Test generation and scheduling for layout-based detection of bridge faults in interconnects
A low-power reduced swing global clocking methodology
A Time-Efficient CMOS-Memristive Programmable Circuit Realizing Logic Functions in Generalized AND-XOR Structures
Mapping Loop Structures Onto Parametrized Hardware Pipelines
Temporarily Fine-Grained Sleep Technique for Near- and Subthreshold Parallel Architectures
VADER: Voltage-Driven Netlist Pruning for Cross-Layer Approximate Arithmetic Circuits
A 0.09-pJ/Bit Logic-Compatible Multiple-Time Programmable (MTP) Memory-Based PUF Design for IoT Applications
Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design
Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder
Rank Metric Decoder Architectures for Random Linear Network Coding With Error Control
Energy scalable system design
A Stagger-Tuned Transimpedance Amplifier
Investigation into micropipeline latch design styles
A Low Voltage All-Digital On-Chip Oscillator Using Relative Reference Modeling
Efficient VLSI Implementation of $2^{{n}}$ Scaling of Signed Integer in RNS ${\{2^{n}-1, 2^{n}, 2^{n}+1\}}$
ISARA: An Island-Style Systolic Array Reconfigurable Accelerator Based on Memristors for Deep Neural Networks
A 1.28-μW Heart-Rate SoC Achieving 99.68% QRS Detection Accuracy for Long-Term Continuous Cardiac Monitoring Applications
Block-based multiperiod dynamic memory design for low data-retention power
Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation
Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation
High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic
FPGA Design for Timing Yield Under Process Variations
Managing power consumption in networks on chips
A Multi-Model Engine for High-Level Power Estimation Accuracy Optimization
Modeling subthreshold SOI logic for static timing analysis
Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices
Low-latency architectures for high-throughput rate Viterbi decoders
Energy-efficient skewed static logic with dual Vt: design and synthesis
Fault-Duration And-Location Aware CED Technique With Runtime Adaptability
Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture
Improved Step-GRAND: Low-Latency Soft-Input Guessing Random Additive Noise Decoding
Design of flexible GF(2 m ) elliptic curve cryptography processors
High-speed architectures for Reed-Solomon decoders
A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations
CMOS Charge Pump With No Reversion Loss and Enhanced Drivability
Measuring Deep Metastability and Its Effect on Synchronizer Performance
Average-8T Differential-Sensing Subthreshold SRAM With Bit Interleaving and 1k Bits Per Bitline
Towards Process Variation-Aware Power Gating
A study of the use of local interconnect in CMOS leaf cell design
Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process
Voltage-pulse driven harmonic resonant rail drivers for low-power applications
Feedbacks in QCA: A Quantitative Approach
Design of an S-ECIES Cryptoprocessor Using Gaussian Normal Bases Over GF(2 m )
GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures
A 2.5-MHz BW, 75-dB SNDR Noise-Shaping SAR ADC With a 1st-Order Hybrid EF-CIFF Structure Assisted by Unity-Gain Buffer
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding
A Generalized Conflict-Free Memory Addressing Scheme for Continuous-Flow Parallel-Processing FFT Processors With Rescheduling
Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow
Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes
NoD: A Neural Network-Over-Decoder for Edge Intelligence
Theoretical analysis of word-level switching activity in the presence of glitching and correlation
An Analog CVNS-Based Sigmoid Neuron for Precise Neurochips
A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses
A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue
Electrical and optical clock distribution networks for gigascale microprocessors
A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain
Post-Placement Interconnect Entropy
Digital Error Corrector for Phase Lead-Compensated Buck Converter in DVS Applications
Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O
Path Unselection for Path Delay Fault Test Generation
A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip
Variation-Aware System-Level Power Analysis
Quaternary Logic Lookup Table in Standard CMOS
An Efficient Training Accelerator for Transformers With Hardware-Algorithm Co-Optimization
Optimal Sigma Delta Modulator Architectures for Fractional- N Frequency Synthesis
Control for Power Gating of Wires
Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement
Post Silicon Power/Performance Optimization in the Presence of Process Variations Using Individual Well-Adaptive Body Biasing
Reduced Power Transition Fault Test Sets for Circuits With Independent Scan Chain Modes
Critical paths in circuits with level-sensitive latches
ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM
A Leakage Compensation Design for Low Supply Voltage SRAM
A Post-Bond ILV Test Method in Monolithic 3-D ICs
A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop
Energy Budget Approximations for Battery-Powered Systems With a Fixed Schedule of Active Intervals
Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing
A Twofold Clock and Voltage-Based Detection Method for Laser Logic State Imaging Attack
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND
Probability-based approach to rectilinear Steiner tree problems
Fully coupled dynamic electro-thermal simulation
A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Optimization
Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance
Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design
A Low Phase-Lag Self-Powered SECE Interface Circuit for Pressure-Type Piezoelectric Energy-Harvesting Compatible With COTS Pressure Sensors
A Model for Supply Voltage and Temperature Variation Effects on Synchronizer Performance
Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation
Modeling and Detection of Hotspot in Shaded Photovoltaic Cells
A 0.2-2.6 GHz Reconfigurable Receiver Using RF-Gain-Adapted Impedance Matching and Gm-Separated IQ-Leakage Suppression Structure in 40-nm CMOS
Thermal Performance Analysis of Mempool RISC-V Multicore SoC
FunState-an internal design representation for codesign
Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product
Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm
Design of a Stochastic Computing Architecture for the Phansalkar Algorithm
Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]
Multiobjective Optimization of Class-F Oscillators
An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating
A 0.1-pJ/b and ACF <0.04 Multiple-Valued PUF for Chip Identification Using Bit-Line Sharing Strategy in 65-nm CMOS
A Fully Integrated Point-of-Load Digital System Supply With PVT Compensation
Comparative Evaluation of Layout Density in 3T, 4T, and MT FinFET Standard Cells
MERIT: Tensor Transform for Memory-Efficient Vision Processing on Parallel Architectures
A High-Speed FPGA Implementation of an RSD-Based ECC Processor
A 24- μW 12-bit 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS
An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction
Design of Low-Complexity Quantized Compressive Sensing Using Measurement Predictive Coding
High-Speed Recursion Architectures for MAP-Based Turbo Decoders