yusuke1997/dblp-id-title huggingface dataset:
Search pruning techniques in SAT-based branch-and-bound algorithmsfor the binate covering problem
Bitwidth cognizant architecture synthesis of custom hardwareaccelerators
Crosstalk alleviation for dynamic PLAs
On achieving complete fault coverage for sequential machines
Techniques for calculating currents and voltages in VLSI power supply networks
A heuristic algorithm for ordering the columns in one-dimensional logica arrays
Timing optimization by gate resizing and critical path identification
Leakage power bounds in CMOS digital technologies
Retiming DAGs [direct acyclic graph]
Noise Adaptive Quantum Circuit Mapping Using Reinforcement Learning and Graph Neural Network
A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits
Automatic Design of Droplet-Based Microfluidic Ring Networks
Tinkertoy: Build Your Own Operating Systems for IoT Devices
Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs
On river routing with minimum number of jogs
Efficient 3-D simulation of complex structures
Optimizing Discharge Efficiency of Reconfigurable Battery With Deep Reinforcement Learning
Static timing analysis for level-clocked circuits in the presence of crosstalk
Assume-Guarantee Distributed Synthesis
Gate-level power estimation using tagged probabilistic simulation
Design of Testable CMOS Logic Circuits Under Arbitrary Delays
DiffPattern-Flex: Efficient Layout Pattern Generation via Discrete Diffusion
Timing-Driven Flow-Channel Network Construction for Continuous-Flow Microfluidic Biochips
Testing of Flow-Based Microfluidic Biochips: Fault Modeling, Test Generation, and Experimental Demonstration
Wavesched: a novel scheduling technique for control-flow intensive designs
Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique
Hierarchical Wire Routing
Value-sensitive automatic code specialization for embedded software
Designing Heterogeneous Embedded Network-on-Chip Platforms With Users in Mind
CMP Fill Synthesis: A Survey of Recent Studies
Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal Flow
Exact Timing Analysis for Asynchronous Circuits With Multiple Periods
Implementation of VLSI self-testing by regularization
GAAS: An Efficient Group Associated Architecture and Scheduler Module for Sparse CNN Accelerators
Prerouting Timing Prediction Across Different Technology Nodes
Accelerating Real-Valued FFT on CPU-FPGA Platforms
Model-Based Virtual Prototype Acceleration
Block Convolution: Toward Memory-Efficient Inference of Large-Scale CNNs on FPGA
Estimate and Recompute: A Novel Paradigm for Approximate Computing on Data Flow Graphs
Template-Free Symbolic Performance Modeling of Analog Circuits via Canonical-Form Functions and Genetic Programming
A Heterogeneous CNN Compilation Framework for RISC-V CPU and NPU Integration Based on ONNX-MLIR
Transient Simulation of Distributed Networks Using Delay Extraction Based Numerical Convolution
MISNAN-a physically based continuous MOSFET model for CAD applications
A multiparameter moment-matching model-reduction approach for generating geometrically parameterized interconnect performance models
Hardware Assisted Buffer Protection Mechanisms for Embedded RISC-V
A Two-Dimensional Integrated Process Simulator: SPIRIT-I
On the integration of partitioning and global routing for rectilinear placement problems
An Open-Source Framework for FPGA Emulation of Analog/Mixed-Signal Integrated Circuit Designs
Interconnect layout optimization under higher order RLC model forMCM designs
VariPar: Variation-Aware Workload Partitioning in Chiplet-Based DNN Accelerators
Frequency-Domain Simulation of Ring Oscillators With a Multiple-Probe Method
Automotive Electrical and Electronic Architecture Security via Distributed In-Vehicle Traffic Monitoring
Analysis and Design of Weakly Coupled LC Oscillator Arrays Based on Phase-Domain Macromodels
Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010
Data Placement and Duplication for Embedded Multicore Systems With Scratch Pad Memory
SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information
Adapting B + -Tree for Emerging Nonvolatile Memory-Based Main Memory
HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection
Belling the CAD: Toward Security-Centric Electronic System Design
Iterative remapping for logic circuits
An Efficient Deep Learning Accelerator Architecture for Compressed Video Analysis
LightNAS: On Lightweight and Scalable Neural Architecture Search for Embedded Platforms
Area optimization of delay-optimized structures using intrinsic constraint graphs
Accuracy-Guaranteed Bit-Width Optimization
A Hardware Generator for SORN Arithmetic
Modeling of Threshold Voltage Shift by Neighboring Transistors for Macaroni Channel MOSFETs in Series
PASTEL: Parasitic Matching-Driven Placement and Routing of Capacitor Arrays With Generalized Ratios in Charge-Redistribution SAR-ADCs
Global optimization approach for architectural synthesis
Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets
Efficient Execution of Stream Graphs on Coarse-Grained Reconfigurable Architectures
OWARU: Free Space-Aware Timing-Driven Incremental Placement With Critical Path Smoothing
Efficient Gröbner Basis Reductions for Formal Verification of Galois Field Arithmetic Circuits
Specification-driven test generation for analog circuits
Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters
Editorial: Routing in Microelectronics
Local Transformations via Cube Operations
Test Signal Development and Analysis for OFDM Systems RF Front-End Parameter Extraction
Diagnosis of Optical Lithography Faults With Product Test Sets
Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine
An efficient output phase assignment for PLA minimization
Fast and accurate timing characterization using functionalinformation
Using a multiple storage quad tree on a hierarchical VLSI compaction scheme
Hardware/software partitioning for multifunction systems
Symbolic timing analysis of asynchronous systems
A pragmatic approach to integrated process/device/circuit simulation for IC technology development
Impact of Local Interconnects on Timing and Power in a High Performance Microprocessor
RANC: Reconfigurable Architecture for Neuromorphic Computing
Eff-ECC: Protecting GPGPUs Register File With a Unified Energy-Efficient ECC Mechanism
A Parametric EDA Method for Coplanar Waveguide Channel Recognition and Air-Bridge Construction in Quantum Chip Design
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis
An object oriented approach to CAD tool control [VLSI]
An Accelerator for High Efficient Vision Processing
A Halting Algorithm to Determine the Existence of the Decoder
Remembering Richard [Obituary, Richard A.Newton]
Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance
Design-for-testability for path delay faults in large combinational circuits using test points
Securing Approximate Computing Systems via Obfuscating Approximate-Precise Boundary
DeepNVM++: Cross-Layer Modeling and Optimization Framework of Nonvolatile Memories for Deep Learning
AutoModel: Automatic Synthesis of Models From Communication Traces of SoC Designs
How circuit size affects parallelism
Estimating implementation bounds for real time DSP application specific circuits
A Multiscale Simulation Approach for Germanium-Hole-Based Quantum Processor
Analysis of the influence of register file size on energyconsumption, code size, and execution time
Switching Activity of Faulty Circuits in Presence of Multiple Transition Faults
Monte Carlo simulations of high energy electrons and holes in Si-n-MOSFET's
CKTSO: High-Performance Parallel Sparse Linear Solver for General Circuit Simulations
Simultaneous Generation of Functional and Low-Power Non-Functional Broadside Tests
Accurate Simulation of High-Gain MMIC Amplifiers With Microstrip-Type Transistors
AOS: An Automated Overclocking System for High-Performance CNN Accelerator Through Timing Delay Measurement on FPGA
Towards a heterogeneous simulation kernel for system-level models: a SystemC kernel for synchronous data flow models
SeFAct2: Selective Feature Activation for Energy-Efficient CNNs Using Optimized Thresholds
Efficient Hierarchical Performance Modeling for Analog and Mixed-Signal Circuits via Bayesian Co-Learning
LSCD: A Low-Storage Clone Detection Protocol for Cyber-Physical Systems
Combining Static and Dynamic Load Balance in Parallel Routing for FPGAs
Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction
Test scheduling for core-based systems using mixed-integer linearprogramming
Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences
Area-Efficient Barrett Modular Multiplication With Optimized Karatsuba Algorithm
The Science of Guessing in Collision-Optimized Divide-and-Conquer Attacks
A graph theoretic approach for synthesizing very low-complexityhigh-speed digital filters
Skewed Flip-Flop and Mixed-V t Gates for Minimizing Leakage in Sequential Circuits
A novel methodology for the design of application-specificinstruction-set processors (ASIPs) using a machine description language
Accelerating Architectural Simulation Via Statistical Techniques: A Survey
Achievable-Rate-Aware Retention-Error Correction for Multi-Level-Cell NAND Flash Memory
Discretization of flux densities in device simulations using optimum artificial diffusivity
Multipath Bound for DAG Tasks
ADVIS: A Software Package for the Design of Systolic Arrays
A SVM Surrogate Model-Based Method for Parametric Yield Optimization
A Heterogeneous Simulation and Modeling Framework for Automation Systems
Routability-driven floorplanner with buffer block planning
A physically based mobility model for numerical simulation of nonplanar devices
Memristive Circuit Implementation of Context-Dependent Emotional Learning Network and Its Application in Multitask
Calculating the effects of linear dependencies in m-sequences used as test stimuli
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models
A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques
Exact and approximate algorithms for the extension of embedded processor instruction sets
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques
Logic optimization and equivalence checking by implication analysis
Application-Dependent Delay Testing of FPGAs
A New Heuristic for N-Dimensional Nearest Neighbor Realization of a Quantum Circuit
Time-Triggered Scheduling for Nonpreemptive Real-Time DAG Tasks Using 1-Opt Local Search
An MILP Encoding for Efficient Verification of Quantized Deep Neural Networks
A Practical Highly Paralleled ReRAM-Based DNN Accelerator by Reusing Weight Pattern Repetitions
A Data-Driven Verilog-A ReRAM Model
HARM: A Hint-Based Assertion Miner
Post-Silicon Failing-Path Isolation Incorporating the Effects of Process Variations
Denoise on Sensor: A Near-Sensor Compute-in-Memory Macro for Visual Perception Denoising via Concatnation-Eliminating
A precorrected-FFT method for electrostatic analysis of complicated 3-D structures
Activity-driven clock design
SITAR-an efficient 3-D simulator for optimization of nonplanar trench structures
Modeling Bidirectional Switches for Enabling Logic Equivalence Checking in a Transistor-Level Programmable Fabric
On-Chip Codeword Generation to Cope With Crosstalk
GASPAD: A General and Efficient mm-Wave Integrated Circuit Synthesis Method Based on Surrogate Model Assisted Evolutionary Algorithm
Test Metrics Model for Analog Test Development
A High-Resolution Method for Quantum Confinement Transport Simulations in MOSFETs
FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture
Accelerated dynamic learning for test pattern generation in combinational circuits
Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors
Testing Cyber-Physical Systems Using a Line-Search Falsification Method
Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation
TCEC: Temperature and Energy-Constrained Scheduling in Real-Time Multitasking Systems
Efficient power profiling for battery-driven embedded system design
CTFE: A High-Efficient Heterogeneous Cryptographic CGRA for Diverse Security Applications
Efficient Extraction of Frequency-Dependent Substrate Parasitics Using Direct Boundary Element Method
An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures
A Method to Construct Low Delay Single Error Correction Codes for Protecting Data Bits Only
POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent
Aggressive Fine-Grained Power Gating of NoC Buffers
Performance computation for precharacterized CMOS gates with RC loads
Prism-SSD: A Flexible Storage Interface for SSDs
Modeling Multiple-Input Switching in Timing Analysis Using Machine Learning
Saving Energy of RRAM-Based Neural Accelerator Through State-Aware Computing
Global Routing for Gate Array
Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation
Classifying Data Blocks at Subpage Granularity With an On-Chip Page Table to Improve Coherence in Tiled CMPs
A new symbolic technique for control-dependent scheduling
Pin-Accessible Legalization for Mixed-Cell-Height Circuits
Gate sizing to radiation harden combinational logic
Activity-Driven Task Allocation in Energy-Constrained Heterogeneous GPUs Systems
Harmonia: A Unified Architecture for Efficient Deep Symbolic Regression
Toward the Predictability of Dynamic Real-Time DNN Inference
2-D Modeling of Dual-Gate MOSFET Devices Using Quintic Splines
Time-domain simulation of uniform and nonuniform multiconductor lossy lines by the method of characteristics
Segment Delay Learning From Quantized Path Delay Measurements
Optimal circuit clustering for delay minimization under a more general delay model
Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping
Workload Change Point Detection for Runtime Thermal Management of Embedded Systems
Automated Design Debugging With Maximum Satisfiability
Power Optimization for Universal Hash Function Data Path Using Divide-and-Concatenate Technique
A Hybrid Test Scheme for Automotive IC in Multisite Testing
Balancing Security and Efficiency: System-Informed Mitigation of Power-Based Covert Channels
Thermal-Aware Task Scheduling for Energy Minimization in Heterogeneous Real-Time MPSoC Systems
Adaptive Multidimensional Parallel Fault Simulation Framework on Heterogeneous System
SIERA: a unified framework for rapid-prototyping of system-level hardware and software
Extension of the VR discretization scheme for velocity saturation
Neural Network Classifier-Based OPC With Imbalanced Training Data
A Linear-Time Routing Algorithm for Convex Grids
TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model
Comprehensive Side-Channel Power Analysis of XTS-AES
A fast and low-cost testing technique for core-based system-chips
FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow
ReaDy: A ReRAM-Based Processing-in-Memory Accelerator for Dynamic Graph Convolutional Networks
A heuristic single-row router minimizing interstreet crossings
Fast and exact transistor sizing based on iterative relaxation
Simulating the Electrical Behavior of Integrated Circuit Devices in the Presence of Thermal Interactions
Post-processing of clock trees via wiresizing and buffering for robust design
Arithmetic built-in self-test for DSP cores
FPGA Pipeline Synthesis Design Exploration Using Module Selection and Resource Sharing
Bus-driven floorplanning
HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems
MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures
Analysis of Frequency-Dependent Interconnects Using Integrated Congruence Transform
QuCTS - Single-Flux Quantum Clock Tree Synthesis
Multilayer Memristive Neural Network Circuit Based on Online Learning for License Plate Detection
Horae: A Hybrid I/O Request Scheduling Technique for Near-Data Processing-Based SSD
GPU-Accelerated Simulation of Small Delay Faults
A linear-time algorithm for routing in a convex grid
Real-Time Scheduling of Conditional DAG Tasks With Intra-Task Priority Assignment
On Modeling and Detecting Trojans in Instruction Sets
Rapid Detailed Temperature Estimation for Highly Coupled IC Interconnect
TSV-Cluster Defect Tolerance Using Tree-Based Redundancy for Yield Improvement of 3-D ICs
Fusion-Catalyzed Pruning for Optimizing Deep Learning on Intelligent Edge Devices
A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects
Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment
Relationship Between Entropy and Test Data Compression
NEWERTRACK: ML-Based Accurate Tracking of In-Mouth Nutrient Sensors Position Using Spectrum-Wide Information
A parallel branch and bound algorithm for test generation
Macro Model of Advanced Devices for Parasitic Extraction
Compaction-Based Custom LSI Layout Design Method
Experiences with concurrent fault simulation of diagnostic programs
Characterizing VeSFET-Based ICs With CMOS-Oriented EDA Infrastructure
Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging
Detecting Hardware Trojans Using Combined Self-Testing and Imaging
Fast and Accurate Prediction of the Steady-State Throughput of Multicore Processors Under Thermal Constraints
Simulation and Design Analysis of (A1Ga)As/GaAs MODFET Integrated Circuits
Augmented Cross-Entropy-Based Joint Temperature Optimization of Real-Time 3-D MPSoC Systems
METER: Measuring Test Effectiveness Regionally
Design automation with mixtures of proof strategies for propositional logic
Supervised Learning Enhanced Quantum Circuit Transformation
SF-SGL: Solver-Free Spectral Graph Learning From Linear Measurements
Switch-level simulation and the pass transistor EXOR gate
An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs
Simulation of arsenic in situ doping with polysilicon CVD and its application to high aspect ratio trenches
Theory and algorithms for face hypercube embedding
Multiple-Population Moment Estimation: Exploiting Interpopulation Correlation for Efficient Moment Estimation in Analog/Mixed-Signal Validation
FASCINET: A Fully Automated Single-Board Computer Generator Using Neural Networks
Piecewise linear model for transmission line with capacitive loading and ramp input
Low-Cost Shuffling Countermeasures Against Side-Channel Attacks for NTT-Based Post-Quantum Cryptography
Single and Variable-State-Skip LFSRs: Bridging the Gap Between Test Data Compression and Test Set Embedding for IP Cores
Physically Aware Affinity-Driven Multiplier Implementation
Machine Learning for Noise Sensor Placement and Full-Chip Voltage Emergency Detection
Full-chip, three-dimensional shapes-based RLC extraction
Broadband Symmetric Doherty Power Amplifier With Enhanced Back-Off Range Using Multiparameters Optimization Method
Adaptive Differential Wearing for Read Performance Optimization on High-Density nand Flash Memory
Optimum and heuristic algorithms for an approach to finite state machine decomposition
Diagnosis of Multiple Scan Chain Timing Faults
Testing Ternary Content Addressable Memories With Comparison Faults Using March-Like Tests
EASTER: Learning to Split Transformers at the Edge Robustly
A delay distribution methodology for the optimal systolic synthesis of linear recurrence algorithms
Test and Yield Loss Reduction of AI and Deep Learning Accelerators
Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels
ARCTIC: Approximate Real-Time Computing in a Cache-Conscious Multicore Environment
Integer programming based topology selection of cell-level analog circuits
On controlling perturbation due to repeaters during quadratic placement
DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning Algorithm
A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance
Empirical evaluation of multilevel logic minimization tools for a lookup-table-based field-programmable gate array technology
Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning
An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement
A Failure Recovery Protocol for Software-Defined Real-Time Networks
Network-flow-based multiway partitioning with area and pin constraints
A constructive genetic algorithm for gate matrix layout problems
Differential Evolution Algorithm With Asymmetric Coding for Solving the Reliability Problem of 3D-TLC CT Flash-Memory Storage Systems
Corner-Stitching-Based Multilayer Obstacle-Avoiding Component-to-Component Rectilinear Minimum Spanning Tree Construction
Efficient Computation of the Max-Plus Semantics of Synchronous Dataflow Graphs
The Opacity of Real-Time Automata
A study of a hybrid phase-pole macromodel for transient simulation of complex interconnects structures
Efficient Discovery of Actual Causality Using Abstraction Refinement
A Sufficient Response Time Analysis Considering Angular Phases Between Rate-Dependent Tasks
Planar-DME: a single-layer zero-skew clock tree router
Automatic Design for Testability Via Testability Measures
A New Approach to Hierarchical and Statistical Timing Simulations
Problems in Precision Modeling of the MOS Transistor for Analog Applications
A fast pseudo-Boolean constraint solver
Asymmetric and Adaptive Error Correction in STT-MRAM
A Case of Lightweight PUF Constructions: Cryptanalysis and Machine Learning Attacks
Diagnosis of Multiple-Voltage Design With Bridge Defect
Snap-3D: A Constrained Placement-Driven Physical Design Methodology for High Performance 3-D ICs
Evaluation of FONOS FDSOI FET for Synapse-Inspired Artificial Neural Network
A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs
Modeling and analysis of crosstalk noise in coupled RLC interconnects
Enhanced Built-In Self-Diagnosis and Self-Repair Techniques for Daisy-Chain Design in MEDA Digital Microfluidic Biochips
The Floating Random Walk Method With Symmetric Multiple-Shooting Walks for Capacitance Extraction
Incorporating DRAM access modes into high-level synthesis
FlexFL: Heterogeneous Federated Learning via APoZ-Guided Flexible Pruning in Uncertain Scenarios
ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing
Memory management for embedded network applications
Interconnect sizing and spacing with consideration of couplingcapacitance
Toward a Formal and Quantitative Evaluation Framework for Circuit Obfuscation Methods
Adaptation of Biochemical Protocols to Handle Technology-Change for Digital Microfluidics
A Streaming Dataflow Engine for Sparse Matrix-Vector Multiplication Using High-Level Synthesis
Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability
Efficient control state-space search
Improved Interval-Based Characterization of Fixed-Point LTI Systems With Feedback Loops
The Promise and Challenge of Stochastic Computing
A Computational Approach for the Diagnosability of Dynamical Circuits
Discretization problem for multidimensional current flow
Endurance-Aware Allocation of Data Variables on NVM-Based Scratchpad Memory in Real-Time Embedded Systems
A unified approach to reduce SOC test data volume, scan power and testing time
An error indicator and automatic adaptive meshing for electrostatic boundary element simulations