yusuke1997/dblp-id-title huggingface dataset:
A Semi-Analytical Thermal Modeling Framework for Liquid-Cooled ICs
DBP: Distributed Power Budgeting for Many-Core Systems in Dark Silicon
Efficient Reconfiguration Algorithm With Flexible Rerouting Schemes for Constructing 3-D VLSI Subarrays
PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning
Circuit simplification for the symbolic analysis of analogintegrated circuits
Corrections to "Quadratic Backward Propagation of Variance for Nonlinear Statistical Circuit Modeling" [Sep 09 1428-1432]
Thorough testing of any multiport memory with linear tests
PUF-Based Fuzzy Authentication Without Error Correcting Codes
Electromigration Study for Multiscale Power/Ground Vias in TSV-Based 3-D ICs
Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms
LFSR-Based Generation of Multicycle Tests
Generation of Multi-Cycle Broadside Tests
Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources
Storage-Based Logic Built-in Self-Test With Multicycle Tests
Computation of Intermodulation Distortion in RF Circuits Using Single-Tone Moments Analysis
Training Data Poisoning in ML-CAD: Backdooring DL-Based Lithographic Hotspot Detectors
Hydrone: Reconfigurable Energy Storage for UAV Applications
Improving the efficiency of BDD-based operators by means of partitioning
A Unified Design Flow to Automatically Generate On-Chip Monitors During High-Level Synthesis of Hardware Accelerators
GNN-Based Timing Prediction in Prerouting Stage With Multitask Learning Strategy
Optimization of Data-Flow Computations Using Canonical TED Representation
Discrete Choice in the Presence of Numerical Uncertainties
An efficient algorithm for constrained encoding and its applications
Static test compaction for synchronous sequential circuits based on vector restoration
Fully Dynamic Switch-Level Simulation of CMOS Circuits
High-Precision Short-Term Lifetime Prediction in TLC 3-D NAND Flash Memory as Hot-Data Storage
Automated design management using traces
Robust Simulation Methodology for Surface-Roughness Loss in Interconnect and Package Modelings
Synthesizing Complementary Circuits Automatically
Guest Editorial Leveraging Design Automation Techniques for Cyber-Physical System Design
Approx-T: Design Methodology for Approximate Multiplication Units via Taylor-Expansion
CAPLET: A Highly Parallelized Field Solver for Capacitance Extraction Using Instantiable Basis Functions
Low Area-Overhead Low-Entropy Masking Scheme (LEMS) Against Correlation Power Analysis Attack
Insertion Loss-Aware Routing Analysis and Optimization for a Fat-Tree-Based Optical Network-on-Chip
A statistical methodology for the design of high-performance CMOScurrent-steering digital-to-analog converters
Passivity-Preserving Model Reduction Using Dominant Spectral-Zero Interpolation
Diagnosis of Integrated Circuits With Multiple Defects of Arbitrary Characteristics
MB ast -Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design
Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems
Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips
LOT: Logic Optimization with Testability. New transformations for logic synthesis
Simulation Paths for Quantum Circuit Simulation With Decision Diagrams What to Learn From Tensor Networks, and What Not
Implicit computation of compatible sets for state minimization of ISFSMs
Numerical modeling of a micromachined thermal conductivity gas pressure sensor
An Analytical Approach for Error PMF Characterization in Approximate Circuits
Machine Learning-Based Read Access Yield Estimation and Design Optimization for High-Density SRAM
qSwitch: Dynamical Off-Chip Bandwidth Allocation Between Local and Remote Accesses
High Volume Diagnosis in Memory BIST Based on Compressed Failure Data
Timing- and crosstalk-driven area routing
On the quality of accumulator-based compaction of test responses
A utility-based integrated system for process simulation
H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks
Toward Fully Automated Machine Learning for Routability Estimator Development
Reliability-Aware Synthesis With Dynamic Device Mapping and Fluid Routing for Flow-Based Microfluidic Biochips
Protecting Combinational Logic Synthesis Solutions
Instiller: Toward Efficient and Realistic RTL Fuzzing
Multiobjective Optimization in Logic Synthesis Based on TB-RM Dual Logic
Automatic modeling of switch-level networks using partial orders [MOS circuits]
A QoS-QoR Aware CNN Accelerator Design Approach
Test efficiency analysis of random self-test of sequential circuits
Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings
STDP-Based Pruning of Connections and Weight Quantization in Spiking Neural Networks for Energy-Efficient Recognition
An Application-Specific Design Methodology for On-Chip Crossbar Generation
Concurrent transient fault simulation for analog circuits
A simulation framework for energy-consumption analysis of OS-driven embedded applications
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners
Combating Stealthy Thermal Covert Channel Attack With Its Thermal Signal Transmitted in Direct Sequence Spread Spectrum
Flexible Inverse Design of Microwave Filter Customized on Demand With Wavelet Transform Deep Learning
Iterative Methods in Semiconductor Device Simulation
On the exploration of the solution space in analog placement with symmetry constraints
An Esterel compiler for large control-dominated systems
Design of a Host Interface Logic for GC-Free SSDs
A unified lower bound estimation technique for high-level synthesis
First-Order Incremental Block-Based Statistical Timing Analysis
Probabilistic design of integrated circuits with correlated input parameters
LASIC: Layout Analysis for Systematic IC-Defect Identification Using Clustering
A lower bound on channel density after global routing
Theorems for identifying undetectable faults in partial-scan circuits
An Improved Two-Step Attack on Lattice-Based Cryptography: A Case Study of Kyber
MSV-Driven Floorplanning
Computation of steady-state CMOS latchup characteristics
Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement
Boolean Analysis of MOS Circuits
Adaptive Mode Transformation for Wear Leveling in Nonvolatile FPGAs
OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine-Learning Tasks in Logic Synthesis
Reducing Microfluidic Very Large-Scale Integration (mVLSI) Chip Area by Seam Carving
A Multiagent Reinforcement Learning-Assisted Cache Cleaning Scheme for DM-SMR
An efficient algorithm to search for minimal closed covers in sequential machines
Fast Online Reconstruction for SSD-Based RAID-5 Storage Systems
OCC: An Automated End-to-End Machine Learning Optimizing Compiler for Computing-In-Memory
Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking
Optimization of High-Efficiency GaN Load Modulated Balanced Amplifier for Integrated Sensing and Communication Applications
A Novel Table-Based Approach for Design of FinFET Circuits
Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability
A High-Performance RDMA NIC With Ultrahighly Scalable Connections
Functional Test Generation Using Efficient Property Clustering and Learning Techniques
A GPU-Accelerated Framework for Path-Based Timing Analysis
An algorithm for functional reconfiguration of fixed-size arrays
PipeRoute: a pipelining-aware router for reconfigurable architectures
An approximation algorithm for the via placement problem
ALFANS: Multilevel Approximate Logic Synthesis Framework by Approximate Node Simplification
A transient noise model for frequency-dependent noise sources
A global wiring paradigm for deep submicron design
Global routing with crosstalk constraints
A Ranking Algorithm for MOS Circuit Layouts
Timing verification of sequential dynamic circuits
Blade-DA: Click-Based Asynchronous Resilient Circuit With Dynamic Delay Adjustment
OSSP-PTA: An Online Stochastic Stepping Policy for PTA on Reinforcement Learning
Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective
Self-Adapting Channel Allocation for Multiple Tenants Sharing SSD Devices
A Robust Test Architecture for Low-Power AI Accelerators
A Lifetime Reliability-Constrained Runtime Mapping for Throughput Optimization in Many-Core Systems
A submicrometer MOS transistor I-V model for circuit simulation
Criticality-Aware Negotiation-Driven Scrubbing Scheduling for Reliability Maximization in SRAM-Based FPGAs
Garbage Collection for Low Performance Variation in NAND Flash Storage Systems
Skydiver: A Spiking Neural Network Accelerator Exploiting Spatio-Temporal Workload Balance
Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design
Automatic synthesis of extended burst-mode circuits. I.(Specification and hazard-free implementations)
On over-the-cell channel routing with cell orientations consideration
SPICE Modeling for Small Geometry MOSFET Circuits
SC-GC-LDPC for nand Flash Memory: Construction and Decoding
A High-Throughput and Arbitrary-Distribution Pattern Generator for the Constrained Random Verification
A faster algorithm for rubber-band equivalent transformation for planar VLSI layouts
Analog Power-Down Synthesis
FPGA Technology Mapping With Adaptive Gate Decomposition
TRaX: A Multicore Hardware Architecture for Real-Time Ray Tracing
Combinatorial optimization by stochastic evolution
Delay-Driven and Antenna-Aware Layer Assignment in Global Routing Under Multitier Interconnect Structure
Simple frequency-domain analysis of MOSFET-includingnonquasi-static effect
Efficient Board-Level Functional Fault Diagnosis With Missing Syndromes
Transient analysis of diode switching circuits using asymptotic waveform evaluation
Design of large embedded CMOS PLAs for built-in self-test
Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling
Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics
Low-power system-level design of VLSI packet switching fabrics
Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach
Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis
Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors
CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits
Design Automation for Continuous-Flow Lab-on-a-Chip Systems: A One-Pass Paradigm
Transition density: a new measure of activity in digital circuits
Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints
Automatic rectangle-based adaptive mesh generation without obtuse angles
Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip
The intertool profile interchange format: a technology CAD environment approach [semiconductor technology]
SmartQCache: Fast and Precise Pulse Control With Near-Quantum Cache Design on FPGA
Capacitance Extraction With Provably Good Absorbing Boundary Conditions
High-reliability, low-energy microarchitecture synthesis
SIMPL-2: (SIMulated Profiles from the Layout-Version 2)
IronMan-Pro: Multiobjective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network-Based Modeling
Multiobjective optimization of VLSI interconnect parameters
Inductive fault analysis of surface-micromachined MEMS
Globally Functional Transparent-Scan Sequences
Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA
CURIOUS: Efficient Neural Architecture Search Based on a Performance Predictor and Evolutionary Search
Finding Deterministic Solution From Underdetermined Equation: Large-Scale Performance Variability Modeling of Analog/RF Circuits
Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults
Runtime Techniques to Mitigate Soft Errors in Network-on-Chip (NoC) Architectures
QuST: Optimizing Quantum Neural Network Against Spatial and Temporal Noise Biases
An Outlook on Design Technologies for Future Integrated Systems
Statistics associated with spatial fault simulation used for evaluating integrated circuit yield enhancement
DÉJÀ VU: An Entropy Reduced Hash Function for VLSI Layout Databases
Performance-driven simultaneous placement and routing for FPGA's
Switch-Electrical Segmented Waveform Relaxation for Digital MOS VLSI and Its Acceleration on Parallel Computers
ErrorTracer: design error diagnosis based on fault simulation techniques
Convex Piecewise-Linear Modeling Method for Circuit Optimization via Geometric Programming
A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors
TALk: A Temperature-Aware Leakage Minimization Technique for Real-Time Systems
Tailor: a layout system based on trapezoidal corner stitching
Scan Shift Power of Functional Broadside Tests
Statistical Timing Analysis: From Basic Principles to State of the Art
Computer-Aided Optimization of DNA Array Design and Manufacturing
Reinforcement-Learning-Based Test Point Insertion for Power-Safe Testing in Monolithic 3-D ICs
An Omega(k 2 ) lower bound for area optimization of spiral floorplans
Crosstalk reduction for VLSI
DRAM-Based Acceleration of Open Modification Search in Hyperdimensional Space
Pragmatic Memory-System Support for Intermittent Computing Using Emerging Nonvolatile Memory
Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem
RePlAce: Advancing Solution Quality and Routability Validation in Global Placement
Compositional Performance Verification of Network-on-Chip Designs
A general and flexible switchbox router: CARIOCA
Combining Control and Data Abstraction in the Verification of Hybrid Systems
Global and local congestion optimization in technology mapping
A stochastic model to predict the routability of field-programmable gate arrays
Untrusted Code Compartmentalization for Bare Metal Embedded Devices
Topological Approach to Symbolic Pole-Zero Extraction Incorporating Design Knowledge
NVM-Based FPGA Block RAM With Adaptive SLC-MLC Conversion
Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups
Test Response Compaction via Output Bit Selection
Compact modeling of on-chip ESD protection devices using Verilog-A
One-Sided Net Untangling With Internal Detours for Bus Routing
Retention Correlated Read Disturb Errors in 3-D Charge Trap NAND Flash Memory: Observations, Analysis, and Solutions
Two-dimensional transient analysis of a collector-up ECL inverter
Energy and Performance Optimization of Demand Paging With OneNAND Flash
Automatic extraction of circuit models from layout artwork for a BiCMOS technology
Performance Benefits of Monolithically Stacked 3-D FPGA
Multiple distributions for biased random test patterns
Techniques for the creation of digital watermarks in sequentialcircuit designs
Chemical-Mechanical Polishing-Aware Application-Specific 3D NoC Design
Fine granularity clustering-based placement
On particle-mesh coupling in Monte Carlo semiconductor device simulation
Goal-oriented decomposition of switching functions
Circuit performance modeling by means of fuzzy logic
SIMPAR: A Versatile Technology Independent Parameter Extraction Program Using a New Optimized Fit-Strategy
Probabilistic crosstalk delay estimation for ASICs
Testability analysis of analog systems
Synthesis of Cyberphysical Digital-Microfluidic Biochips for Real-Time Quantitative Analysis
Inductance and Resistance Calculations in Three-Dimensional Packaging Using Cylindrical Conduction-Mode Basis Functions
Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets
Assertion Aware Sampling Refinement: A Mixed-Signal Perspective
Simulation of Critical IC-Fabrication Steps
Shared-PIM: Enabling Concurrent Computation and Data Flow for Faster Processing-in-DRAM
Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links
A New Pipelined Output Data Reducer of BOST for Improved Parallelism
Multistack optimization for data-path chip layout
Efficient implementation of a planar clock routing with thetreatment of obstacles
A Neural Network-Based Cognitive Obfuscation Toward Enhanced Logic Locking
Restructuring and logic minimization for testable PLA
Timing optimization for multisource nets: characterization andoptimal repeater insertion
Empirical model of MOSFET breakdown voltages
Real-Time Error Recovery in Cyberphysical Digital-Microfluidic Biochips Using a Compact Dictionary
Area Optimization of Timing Resilient Designs Using Resynthesis
Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks
Hierarchical Symbol-Based Health-Status Analysis Using Time-Series Data in a Core Router System
A convex programming approach for generating guaranteed passive approximations to tabulated frequency-data
Solving the net matching problem in high-performance chip design
Allocation of multiport memories in data path synthesis
Automatic Variable-Width Routing for VLSI
MSA: A Novel App Development Framework for Transparent Multiscreen Support on Android Apps
NIM-X: A Noise Index Model-Based X-Filling Technique to Overcome the Power Supply Switching Noise Effects on Path Delay Test
DAMO: Deep Agile Mask Optimization for Full-Chip Scale
Routability-Driven Placement and White Space Allocation
Post-Placement Power Optimization With Multi-Bit Flip-Flops
Boolean matching for incompletely specified functions
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector
Analog IC Variability Bound Estimation Using the Cornish-Fisher Expansion
SAFARI: Automatic Synthesis of Fault-Attack Resistant Block Cipher Implementations
Automated Design Debugging With Abstraction and Refinement
Composable Behavioral Models and Schematic-Based Simulation of Electrokinetic Lab-on-a-Chip Systems
Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores
Fast postplacement optimization using functional symmetries
GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning
Wordlength optimization for linear digital signal processing
Spanning graph-based nonrectilinear steiner tree algorithms
nZESPA: A Near-3D-Memory Zero Skipping Parallel Accelerator for CNNs
SLS-a fast switch-level simulator [for MOS]
Exploring FPGA Routing Architecture Stochastically
Exact calculation of synchronizing sequences based on binary decision diagrams
Reachability Analysis of Linear Hybrid Systems via Block Decomposition
Optimal retiming of level-clocked circuits using symmetric clock schedules
Generalized Power-Delay Metrics in Deep Submicron CMOS Designs
Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management
A High-Performance, Conflict-Free Memory-Access Architecture for Modular Polynomial Multiplication
Pin assignment for multi-FPGA systems
A new approach to the simulation of the coupled point defects and impurity diffusion
An Iterated Local Search Methodology for the Qubit Mapping Problem
Comparison of temperature models for the drain current of MESFET's
On-line testing of statically and dynamically scheduled synthesized systems
DasAtom: A Divide-and-Shuttle Atom Approach to Quantum Circuit Transformation
Application-Aware NoC Design for Efficient SDRAM Access
FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis
Routability-Driven Macro Placement Engine for Modern FPGAs With Complex Cascade Shape and Region Constraints
Bounds on signal delay in RC mesh networks
Timing Analysis and Performance Improvement of MOS VLSI Designs
Optimal Greedy Algorithm for Many-Core Scheduling
On Near-Maximum-Length Galois Nonlinear Feedback Shift Registers
MIS: A Multiple-Level Logic Optimization System
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs
Tardis: Coverage-Guided Embedded Operating System Fuzzing
Block-level 3-D Global Routing With an Application to 3-D Packaging
X-CGRA: An Energy-Efficient Approximate Coarse-Grained Reconfigurable Architecture
Pitfalls of hierarchical fault simulation
Hardware-Friendly 3-D CNN Acceleration With Balanced Kernel Group Sparsity
Reducing Transistor Count in CMOS Logic Design Through Clustering and Library-Independent Multiple-Output Logic Synthesis
An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations
NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map
Design rewiring using ATPG
Efficient Spatial Pattern Analysis for Variation Decomposition Via Robust Sparse Regression
On masking of redundant faults in synchronous sequential circuits with design-for-testability logic
Cross Layer Design Using HW/SW Co-Design and HLS to Accelerate Chaining in Genomic Analysis
Sparsity Turns Adversarial: Energy and Latency Attacks on Deep Neural Networks
Reliable State Retention-Based Embedded Processors Through Monitoring and Recovery
Scheduling and Fluid Routing for Flow-Based Microfluidic Laboratories-on-a-Chip
Program Phase-Aware Dynamic Voltage Scaling Under Variable Computational Workload and Memory Stall Environment
Tradeoff Performance and Energy Efficiency by Optimizing the Data Flow for PIM Architectures
A new triple-layer OTC channel router
Circuit Learning: From Decision Trees to Decision Graphs
Enabling Efficient Sparse Multiplications on GPUs With Heuristic Adaptability
CONT: a concurrent test generation system
A Permeation Router
Constraint analysis for DSP code generation
Spectral-based multiway FPGA partitioning
Computer Simulation of Impurity Diffusion in Semiconductors by the Monte Carlo Method
Heuristics-Aided Tightness Evaluation of Analytical Bounds in Networks-on-Chip
Pipeline vectorization
On automatic-verification pattern generation for SoC withport-order fault model
Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit Designs
Satisfaction of input and output encoding constraints
A parallel built-in self-diagnostic method for embedded memoryarrays
On Using On-Chip Clock Tuning Elements to Address Delay Degradation Due to Circuit Aging
Creator: new advanced concepts in concurrent simulation
Splitter-Aware Multiterminal Routing With Length-Matching Constraint for RSFQ Circuits
A Method for Improving Cascode-Switch Macro Wirability
Min-cut placement with global objective functions for large scale sea-of-gates arrays
Area-Oriented Resubstitution For Networks of Look-Up Tables
Fabricatable Interconnect and Molecular QCA Circuits
Tiny Phase-Error Monitor for Fault and Soft-Error-Tolerant DLL to Support Graceful Degradation and Module-Level Testing
An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration
Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures
Utilizing Predictors for Efficient Thermal Management in Multiprocessor SoCs
Custom-instruction synthesis for extensible-processor platforms
Automatic generation of synthetic sequential benchmark circuits
Design of reconfigurable composite microsystems based on hardware/software codesign principles
An improved analytical short-channel MOSFET model valid in all regions of operating for analog/digital circuit simulation
Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
Design of MOS networks in single-rail input logic for incompletely specified functions
Routing in general junctions
A Network Comparison Algorithm for Layout Verification of Integrated Circuits
Improving symbolic reachability analysis by means of activityprofiles
Source-Level Performance, Energy, Reliability, Power and Thermal (PERPT) Simulation
Complex instruction and software library mapping for embedded software using symbolic algebra