yusuke1997/dblp-id-title huggingface dataset:
Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors
LithoExp: Explainable Two-stage CNN-based Lithographic Hotspot Detection with Layout Defect Localization
BDD-based logic synthesis for LUT-based FPGAs
Efficient partial scan cell gating for low-power scan-based testing
SIMTAM: Generation Diversity Test Programs for FPGA Simulation Tools Testing Via Timing Area Mutation
Zero cost indexing for improved processor cache performance
A Deterministic-Path Routing Algorithm for Tolerating Many Faults on Very-Large-Scale Network-on-Chip
Runtime Fault Localization in Deep Neural Network Accelerators
Dimension-reducible Boolean functions based on affine spaces
Multi-Fidelity Surrogate-Based Optimization for Electromagnetic Simulation Acceleration
A study of row-based area-array I/O design planning in concurrent chip-package design flow
Effective decap insertion in area-array SoC floorplan design
In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches
Flexible and Tradeoff-Aware Constraint-Based Design Space Exploration for Streaming Applications on Heterogeneous Platforms
Flexible Droplet Routing in Active Matrix-Based Digital Microfluidic Biochips
Forming N-detection test sets without test generation
Data and memory optimization techniques for embedded systems
Least Upper Delay Bound for VBR Flows in Networks-on-Chip with Virtual Channels
Critical-path-aware high-level synthesis with distributed controller for fast timing closure
Object-oriented cosynthesis of distributed embedded systems
Confidence analysis for defect-level estimation of VLSI random testing
Energy-aware Scheduling of Workflow Applications Towards Schedule Length Optimization in Heterogeneous Distributed Embedded Systems
Repair of FPGA-Based Real-Time Systems With Variable Slacks
Parameterized architecture-level dynamic thermal models for multicore microprocessors
POEM: Performance Optimization and Endurance Management for Non-volatile Caches
Postplacement voltage assignment under performance constraints
DYNASCORE: DYNAmic Software COntroller to Increase REsource Utilization in Mixed-Critical Systems
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks
General technology mapping for field-programmable gate arrays based on lookup tables
Performance-Driven Assignment of Buffered I/O Signals in Area-I/O Flip-Chip Designs
High-level library mapping for memories
Hmap: a fast mapper for EPGAs using extended GBDD hash tables
Empirical Guidelines for Deploying LLMs onto Resource-constrained Edge Devices
Efficient techniques for transition testing
A Fault-Aware Toolchain Approach for FPGA Fault Tolerance
SystemC-AMS Thermal Modeling for the Co-simulation of Functional and Extra-Functional Properties
TransNet: Minimally Supervised Deep Transfer Learning for Dynamic Adaptation of Wearable Systems
Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing
BLAS: Block-level adaptive striping for solid-state drives
Machine Learning Assisted Circuit Sizing Approach for Low-Voltage Analog Circuits with Efficient Variation-Aware Optimization
Reconfigurable Network-on-Chip Security Architecture
POSE: a parallel object-oriented synthesis environment
Inferencing on Edge Devices: A Time- and Space-aware Co-scheduling Approach
Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic
An Efficient Execution Framework of Two-Part Execution Scenario Analysis
Accurate Analysis and Prediction of Enterprise Service-Level Performance
CALM: Contention-Aware Latency-Minimal Application Mapping for Flattened Butterfly On-Chip Networks
ILP-based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design
Security Analysis of Arbiter PUF and Its Lightweight Compositions Under Predictability Test
Simultaneous reference allocation in code generation for dual data memory bank ASIPs
Breaking the Design and Security Trade-off of Look-up-table-based Obfuscation
Logic transformation for low-power synthesis
Directed Test Generation for Activation of Security Assertions in RTL Models
A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing
Path delay fault testing using test points
An Algorithmic Approach to Formally Verify an ECC Library
An Elastic Mixed-Criticality Task Model and Early-Release EDF Scheduling Algorithms
Making Aging Useful by Recycling Aging-induced Clock Skew
Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing
Dynamic power management for multidomain system-on-chip platforms: An optimal control approach
Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching
Logic synthesis and circuit customization using extensive external don't-cares
A data acquisition methodology for on-chip repair of embedded memories
Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation
Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation
A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications
Methods for power optimization in SOC-based data flow systems
COPE: Reducing Cache Pollution and Network Contention by Inter-tile Coordinated Prefetching in NoC-based MPSoCs
Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip
How to efficiently implement dynamic circuit specialization systems
SPMCloud : Towards the Single-Chip Embedded ScratchPad Memory-Based Storage Cloud
LHS: LLM Assisted Efficient High-level Synthesis of Deep Learning Tasks
An efficient method for analyzing on-chip thermal reliability considering process variations
Auxiliary Variables in Temporal Specifications: Semantic and Practical Analysis for System-Level Requirements
Word-length optimization for differentiable nonlinear systems
Locality-Driven Parallel Static Analysis for Power Delivery Networks
Retiming-based factorization for sequential logic optimization
Thermal-Sensor-Based Occupancy Detection for Smart Buildings Using Machine-Learning Methods
ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method
Scan-based attacks on linear feedback shift register based stream ciphers
Security-Aware Design Methodology and Optimization for Automotive Systems
Applying reinforcement learning to learn best net to rip and re-route in global routing
Thermal Management for FPGA Nodes in HPC Systems
Constructing and exploiting linear schedules with prescribed parallelism
Locality-Aware Network Utilization Balancing in NoCs
Robust Design Space Modeling
A Constructive Approach for Threshold Function Identification
Symbolic Analyses of Dataflow Graphs
Directed test generation for validation of multicore architectures
Secure and Flexible Trace-Based Debugging of Systems-on-Chip
A Comprehensive BIST Solution for Polar Transceivers Using On-Chip Resources
Efficiently scheduling runtime reconfigurations
On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs
Hierarchical Dynamic Thermal Management Method for High-Performance Many-Core Microprocessors
Tutorial: Compiling concurrent languages for sequential processors
A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications
Simplifying the design and automating the verification of pipelines with structural hazards
A Survey of Research in Large Language Models for Electronic Design Automation
A noniterative equivalent waveform model for timing analysis in presence of crosstalk
EDA-Copilot: A RAG-Powered Intelligent Assistant for EDA Tools
Incremental hierarchical memory size estimation for steering of loop transformations
LBNoC: Design of Low-latency Router Architecture with Lookahead Bypass for Network-on-Chip Using FPGA
A Survey on Approximate Multiplier Designs for Energy Efficiency: From Algorithms to Circuits
Boundary-Functional Broadside and Skewed-Load Tests
Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing
Transition-overhead-aware voltage scheduling for fixed-priority real-time systems
Energy-aware variable partitioning and instruction scheduling for multibank memory architectures
A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian Relaxation
Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems
Differential Write-Conscious Software Design on Phase-Change Memory: An SQLite Case Study
Optimal Pattern Retargeting in IEEE 1687 Networks: A SAT-based Upper-Bound Computation
ACM Transactions on Design Automation of Electronic Systems (TODAES) special section call for papers: Parallel CAD: Algorithm design and programming
Power optimization of technology-dependent circuits based on symbolic computation of logic implications
SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects
Security Evaluation of State Space Obfuscation of Hardware IP through a Red Team-Blue Team Practice
Assertion-Based Validation using Clustering and Dynamic Refinement of Hardware Checkers
Coverage-directed observability-based validation for embedded software
Analog/RF Post-silicon Tuning via Bayesian Optimization
Graph Neural Networks for High-Level Synthesis Design Space Exploration
Ordered Escape Routing with Consideration of Differential Pair and Blockage
Runtime Identification of Hardware Trojans by Feature Analysis on Gate-Level Unstructured Data and Anomaly Detection
Speeding-up heuristic allocation, scheduling and binding with SAT-based abstraction/refinement techniques
Special Section: Integrating Dataflow, Embedded Computing and Architecture
Power and Area Efficiency NoC Router Design for Application-Specific SoC by Using Buffer Merging and Resource Sharing
Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops
Translating Test Responses to Images for Test-termination Prediction via Multiple Machine Learning Strategies
Test Compression for Launch-on-Capture Transition Fault Testing
A Scenario-Based DVFS-Aware Hybrid Application Mapping Methodology for MPSoCs
An Efficient False Path-Aware Heuristic Critical Path Selection Method with High Coverage of the Process Variation Space
Optimization of polynomial datapaths using finite ring algebra
Reconfigurable Battery Systems: A Survey on Hardware Architecture and Research Challenges
Introduction to special issue: Novel paradigms in system-level design
System-Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow
WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture
DTGx2: Dual Target Diagnostic Test Generation
Bio-chemical Assay Locking to Thwart Bio-IP Theft
CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells
Implementing an Application-Specific Instruction-Set Processor for System-Level Dynamic Program Analysis Engines
Efficient Layout Hotspot Detection via Neural Architecture Search
A circuit level fault model for resistive bridges
On the completeness of the polymorphic gate set
Analysis and minimization of power-transmission loss in locally daisy-chained systems by local energy buffering
Compiler Optimization for Reducing Leakage Power in Multithread BSP Programs
Reduction design for generic universal switch blocks
You Only Need Non-Hotspot: An Unsupervised Training-Free Method for Layout Hotspot Detection
System-level throughput analysis for process variation aware multiple voltage-frequency island designs
Area-Aware Decomposition for Single-Electron Transistor Arrays
Series-parallel functions and FPGA logic module design
Concurrency-oriented verification and coverage of system-level designs
Optimized Implementation of Multirate Mixed-Criticality Synchronous Reactive Models
Cut Optimization for Redundant Via Insertion in Self-Aligned Double Patterning
SoCDAL: System-on-chip design AcceLerator
A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs
Computation and communication refinement for multiprocessor SoC design: A system-level perspective
Reducing instruction bit-width for low-power VLIW architectures
Interactive Visual Performance Space Exploration of Operational Amplifiers with Differentiable Neural Network Surrogate Models
TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems
Fault Localization Scheme for Missing Gate Faults in Reversible Circuits
Array Size Computation under Uniform Overlapping and Irregular Accesses
ILP models for simultaneous energy and transient power minimization during behavioral synthesis
A hardware platform for efficient worm outbreak detection
Double-Shift: A Low-Power DNN Weights Storage and Access Framework based on Approximate Decomposition and Quantization
Optimized 3D Network-on-Chip Design Using Simulated Allocation
Energy Efficient Error Resilient Multiplier Using Low-power Compressors
Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design
Formal Verification and Debugging of Precise Interrupts on High Performance Microprocessors
Integrated test of interacting controllers and datapaths
An optimal clock period selection method based on slack minimization criteria
MAESTRO - Holistic Actor-Oriented Modeling of Nonfunctional Properties and Firmware Behavior for MPSoCs
MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark
ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction
Efficiently Managing the Impact of Hardware Variability on GPUs' Streaming Processors
CoVerPlan: A Comprehensive Verification Planning Framework Leveraging PSS Specifications
Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology
Error-Correcting Sample Preparation with Cyberphysical Digital Microfluidic Lab-on-Chip
Congestion reduction during placement with provably good approximation bound
Binary synthesis
FixRTL: Auto-correction of Multiple RTL Bugs by a New Feature Burst Clustering Algorithm and Mutation
The optimization of kEP-SOPs: Computational complexity, approximability and experiments
Approximate Energy-Efficient Encoding for Serial Interfaces
Proof-Carrying Hardware via Inductive Invariants
HEANA : A Hybrid Time-Amplitude Analog Optical Accelerator with Flexible Dataflows for Energy-Efficient CNN Inference
Optimal river routing with crosstalk constraints
Introspection: A register transfer level technique for cocurrent error detection and diagnosis in data dominated designs
IMPRoVED: Integrated Method to Predict PostRouting setup Violations in Early Design Stages
LLM-assisted Bug Identification and Correction for Verilog HDL
Writeback-Aware LLC Management for PCM-Based Main Memory Systems
Hierarchical Ensemble Reduction and Learning for Resource-constrained Computing
System-Level Observation Framework for Non-Intrusive Runtime Monitoring of Embedded Systems
Optimal clock period FPGA technology mapping for sequential circuits
Technology mapping and architecture evalution for k/m -macrocell-based FPGAs
Dynamically Determined Preferred Values and a Design-for-Testability Approach for Multiplexer Select Inputs under Functional Test Sequences
Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining
Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures
Address code generation for DSP instruction-set architectures
Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder
Capacity-Aware Wash Optimization with Dynamic Fluid Scheduling and Channel Storage for Continuous-Flow Microfluidic Biochips
Multiharmonic Small-Signal Modeling of Low-Power PWM DC-DC Converters
A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration
Efficient Attacks on Strong PUFs via Covariance and Boolean Modeling
Functional design for testability of control-dominated architectures
MNFTL: An Efficient Flash Translation Layer for MLC NAND Flash Memory
PeaCE: A hardware-software codesign environment for multimedia embedded systems
Prefetching for improved bus wrapper performance in cores
Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes
MCMCF-Router: Multi-capacity Ordered Escape Routing Algorithms for Grid/Staggered Pin Array
Algorithmic aspects of hardware/software partitioning
DRAGON: Dynamic Recurrent Accelerator for Graph Online Convolution
Design theory and implementation for low-power segmented bus systems
Implementing the scale vector-thread processor
Revisiting automated physical synthesis of high-performance clock networks
Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs
SecureTVM: A TVM-based Compiler Framework for Selective Privacy-preserving Neural Inference
Design Automation Algorithms for the NP-Separate VLSI Design Methodology
Test vector decomposition-based static compaction algorithms for combinational circuits
Rectilinear block placement using B * -trees
Employing circadian rhythms to enhance power and reliability
Diagnostic simulation of stuck-at faults in sequential circuits using compact lists
Dynamic programming-based runtime thermal management (DPRTM): An online thermal control strategy for 3D-NoC systems
Switching Predictive Control Using Reconfigurable State-Based Model
On the fundamental limitations of transformational design
Avoiding Data Inconsistency in Energy Harvesting Powered Embedded Systems
Transfer Learning Enabled Modeling Paradigm for PVT-aware Circuit Performance Estimation
On the hardware-software partitioning problem: System modeling and partitioning techniques
Virtuoso: Energy- and Latency-aware Streamlining of Streaming Videos on Systems-on-Chips
Design of energy-efficient, adaptable throughput systems at near/sub-threshold voltage
Optimal test access architectures for system-on-a-chip
Integrated Resource Allocation and Binding in Clock Mesh Synthesis
Scan-BIST based on cluster analysis and the encoding of repeating sequences
Discrete sizing for leakage power optimization in physical design: A comparative study
Board-level multiterminal net routing for FPGA-based logic emulation
Synthesis of skewed logic circuits
Instinctive Assistive Indoor Navigation using Distributed Intelligence
Reliability-Driven Power/Ground Routing for Analog ICs
Security in Automotive Networks: Lightweight Authentication and Authorization
Accelerating UNISIM-Based Cycle-Level Microarchitectural Simulations on Multicore Platforms
Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs
Partitioning and Data Mapping in Reconfigurable Cache and Scratchpad Memory-Based Architectures
Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits
SEDONUT: A Single Event Double Node Upset Tolerant SRAM for Terrestrial Applications
RedPIM: An Efficient PIM Accelerator Design with Reduced Analog-to-Digital Conversions
Optimal simultaneous module and multivoltage assignment for low power
Techniques for scalable and effective routability evaluation
DCW: A Reactive and Predictable Programming Framework for LET-Based Distributed Real-Time Systems
MoDAF: A Multi-objective Divide-and-Conquer Parameter Tuning Framework for CGRAs
UST/DME: a clock tree router for general skew constraints
Reliable crosstalk-driven interconnect optimization
Security of Electrical, Optical, and Wireless On-chip Interconnects: A Survey
DARP-MP: Dynamically Adaptable Resilient Pipeline Design in Multicore Processors
Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs
Security-Aware Obfuscated Priority Assignment for Automotive CAN Platforms
Introduction to the Special Issue on Approximate Systems
SUPERB: Simulator utilizing parallel evaluation of resistive bridges
ECO cost measurement and incremental gate sizing for late process changes
Wages: The Worst Transistor Aging Analysis for Large-scale Analog Integrated Circuits via Domain Generalization
EF-Train: Enable Efficient On-device CNN Training on FPGA through Data Reshaping for Online Adaptation or Personalization
Quality-Enhanced OLED Power Savings on Mobile Devices
Towards Fine-Grained Online Adaptive Approximation Control for Dense SLAM on Embedded GPUs
Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic
Constrained polygon transformations for incremental floorplanning
Optimization of 3D Digital Microfluidic Biochips for the Multiplexed Polymerase Chain Reaction
Estimation of state line statistics in sequential circuits
Machine Learning Approach for Fast Electromigration Aware Aging Prediction in Incremental Design of Large Scale On-chip Power Grid Network
Concurrent testing of digital microfluidics-based biochips
Module placement for fault-tolerant microfluidics-based biochips
Removal of SAT-Hard Instances in Logic Obfuscation Through Inference of Functionality
Von Neumann hybrid cellular automata for generating deterministic test sequences
Multi-Objective Optimization for Safety-Related Available E/E Architectures Scoping Highly Automated Driving Vehicles
Dynamic state traversal for sequential circuit test generation
On bottleneck analysis in stochastic stream processing
Reuse analysis of indirectly indexed arrays
Datapath Combinational Equivalence Checking With Hybrid Sweeping Engines and Parallelization
The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells
A Survey and Perspective on Artificial Intelligence for Security-Aware Electronic Design Automation
A verification system for transient response of analog circuits
Predicting Memory Compiler Performance Outputs Using Feed-forward Neural Networks
Resource sharing among mutually exclusive sum-of-product blocks for area reduction
PSCaps: High-Performance Pose-Sensitive Layout Hotspot Detector based on CapsNet
SOC test architecture design for efficient utilization of test bandwidth
EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling
Unveiling Cross-checking Opportunities in Verilog Compilers
ChatDSE: A Zero-Shot Microarchitecture Design Space Explorer Powered by GPT4.0
Partitioning parameterized 45-degree polygons with constraint programming
T-trees: A tree-based representation for temporal and three-dimensional floorplanning
CMAPS: a cosynthesis methodology for application-oriented parallel systems
DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout
Context-aware Data Augmentation for Hardware Code Fault localization
High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors
MEDUSA: A Multi-Resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing
Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization
On-chip ESD Protection Design Methodologies by CAD Simulation
Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers
The survivability of design-specific spare placement in FPGA architectures with high defect rates
Toward Effective Reliability Requirement Assurance for Automotive Functional Safety
Low-power skewed-load tests based on functional broadside tests
A methodology and algorithms for the design of hard real-time multitasking ASICs
A Novel Rule Mapping on TCAM for Power Efficient Packet Classification
Hybrid nonvolatile disk cache for energy-efficient and high-performance systems
FastCFI: Real-time Control-Flow Integrity Using FPGA without Code Instrumentation
40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications
A New Unicast-Based Multicast Scheme for Network-on-Chip Router and Interconnect Testing
Lowering Minimum Supply Voltage for Power-Efficient Cache Design by Exploiting Data Redundancy
Analysis and optimization of distributed real-time embedded systems