yusuke1997/dblp-id-title huggingface dataset:
Review-based recommendation of attractive sentences in a novel for effective browsing
Case-based reasoning approach for utilisation of past remarks as advice for collaborative learning
A RESTful web service to estimating time requirements for web forms
The development of a course recommendation system for e-learning students
MOSSA: a morpho-semantic knowledge extraction system for Arabic information retrieval
Software engineers' information behaviour and implicit relevance indicators
Design and collection of ontological metadata for enhancing interoperability of language resources
A weighted-graph-based approach for diversifying search results
Paper-to-reviewer assignment, based on expertise degree of reviewers and relevance degree between reviewers and papers
Determining the semantic orientation of opinion words using typed dependencies for opinion word senses and SentiWordNet scores from online product reviews
Evaluation of network construction exercise system LiNeS on the basis of heterogeneous and distributed virtual machine network composition function
CAFE: Collaboration Aimed at Finding Experts
A remote lecturing system offering complementary non-verbal information in lectures
Composition method of folk-tales based on STRIPS-like framework
Localised topic information extraction for summarisation using syntactic sequences
A user-concept matrix clustering algorithm for efficient next page prediction
A new spatio-temporal prediction approach based on aggregate queries
Approximately processing aggregate range queries on remote spatial databases
A 150 MHz 0.6 μm BiCMOS superscalar microprocessor
A BiCMOS dynamic carry lookahead adder circuit for VLSI implementation of high-speed arithmetic unit
The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process
A 90-ns one-million erase/program cycle 1-Mbit flash memory
A 40 nm 16-Core 128-Thread SPARC SoC Processor
An 802.11a/b/g/n Digital Fractional-N PLL With Automatic TDC Linearity Calibration for Spur Cancellation
A µNMR CMOS Transceiver Using a Butterfly-Coil Input for Integration With a Digital Microfluidic Device Inside a Portable Magnet
A 201.4 GOPS 496 mW Real-Time Multi-Object Recognition Processor With Bio-Inspired Neural Perception Engine
System integration of optical devices and analog CMOS amplifiers
Noise-margin limitations on gallium-arsenide VLSI
SRAM Cell Stability: A Dynamic Perspective
A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source
New dynamic flip-flops for high-speed dual-modulus prescaler
A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC
Design, implementation and evaluation of a high-speed integrated Hamming neural classifier
A 2.4-mm 2 130-mW MMSE-Nonbinary LDPC Iterative Detector Decoder for 4×4 256-QAM MIMO in 65-nm CMOS
An inherently linear and compact MOST-only current division technique
The New CMC Standard Compact MOS Model PSP: Advantages for RF Applications
A fast parallel squarer based on divide-and-conquer
Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data
Fully Integrated 94-GHz Dual-Polarized TX and RX Phased Array Chipset in SiGe BiCMOS Operating up to 105 °C
A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC
5-10 Gb/s 70 mW Burst Mode AC Coupled Receiver in 90-nm CMOS
An accurate center frequency tuning scheme for 450-KHz CMOS G m -C bandpass filters
A 92%-Efficiency Inductor-Charging Switched-Capacitor Stimulation System With Level-Adaptive Duty Modulation and Offset Charge Balancing
A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling
A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM
A reprogrammable EDGE baseband and multimedia handset SoC with 6-mbit embedded DRAM
A fully integrated low-noise 1-GHz frequency synthesizer design for mobile communication application
iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor
A 175 Ms/s, 6 b, 160 mW, 3.3 V CMOS A/D converter
Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability
An efficient maximum-redundancy radix-8 SRT division and square-root method
A 97.3-dB SNR Bioimpedance AFE With -84-dB THD Segmented- ΔΣ M Sinusoidal Current Generator and Passing-Through Instrumentation Amplifier
A 3.9-kHz Frame Rate and 61.0-dB SNR Analog Front-End IC With 6-bit Pressure and Tilt Angle Expressions of Active Stylus Using Multiple-Frequency Driving Method for Capacitive Touch Screen Panels
InP-HBT optoelectronic integrated circuits for photonic analog-to-digital conversion
A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications
A Sub-100 Fs RMS jitter 20 GHz Fractional-N Analog PLL With a BAW Resonator Based On-Chip 2.5 GHz Reference
A Mode-Matching ΣΔ Closed-Loop Vibratory Gyroscope Readout Interface With a 0.004°/s/√Hz Noise Floor Over a 50 Hz Band
CMOS active pixel sensor star tracker with regional electronic shutter
Design of an image edge detection filter using the Sobel operator
A novel self-oscillating HEMT-HBT cascode VCO-mixer using an active tunable inductor
A 4-ns BiCMOS translation-lookaside buffer
Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion
A Triple-Mode Balanced Linear CMOS Power Amplifier Using a Switched-Quadrature Coupler
Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL
Asynchronous cross-pipelined multiplier
Multiemitter BiCMOS logic circuit family
A Four-Phase Buck Converter With Capacitor-Current-Sensor Calibration for Load-Transient-Response Optimization That Reduces Undershoot/Overshoot and Shortens Settling Time to Near Their Theoretical Limits
A 66 µW 86 ppm° C Fully-Integrated 6 MHz Wienbridge Oscillator With a 172 dB Phase Noise FOM
A highly linear CMOS G m -C bandpass filter with on-chip frequency tuning
An 80-Msample/s video switched-capacitor filter using a parallel biquadratic structure
A BiCMOS programmable continuous-time filter using image-parameter method synthesis and voltage-companding technique
A safe single-phase clocking scheme for CMOS circuits
Low-voltage dynamic BiCMOS CLA circuit with carry skip using novel full-swing logic
A 60-GHz OOK Receiver With an On-Chip Antenna in 90 nm CMOS
100000-pixel, 120-dB imager in TFA technology
A High-Frequency Clock Distribution Network Using Inductively Loaded Standing-Wave Oscillators
True color 1024×768 microdisplay with analog in-pixel pulsewidth modulation and retinal averaging offset correction
A 0.8-V accurately tuned linear continuous-time filter
A 165-Gb/s 4: 1 Multiplexer in InP DHBT Technology
A 190-GHz VCO With 20.7% Tuning Range Employing an Active Mode Switching Block in a 130 nm SiGe BiCMOS
A Broadband Mixed-Signal CMOS Power Amplifier With a Hybrid Class-G Doherty Efficiency Enhancement Technique
A 0.5-V, 440-µW Frequency Synthesizer for Implantable Medical Devices
A 0.7 cm 2 , 3.5 GHz, -31 dBm Sensitivity Battery-Free 5G Energy-Harvester Backscatterer With 20 s Cold-Start Wake-Up Time for IoT-Enabled Warehouses
An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture
A CDMA Dual-Band Zero-IF Receiver With Integrated LNAs and VCOs in an Advanced SiGe BiCMOS Process
A 0.25-27-Gb/s PAM4/NRZ Transceiver With Adaptive Power CDR and Jitter Analysis
A 249-Mpixel/s HEVC Video-Decoder Chip for 4K Ultra-HD Applications
A Double Sensing Scheme With Selective Bitline Voltage Regulation for Ultralow-Voltage Timing Speculative SRAM
SleepTalker: A ULV 802.15.4a IR-UWB Transmitter SoC in 28-nm FDSOI Achieving 14 pJ/b at 27 Mb/s With Channel Selection Based on Adaptive FBB and Digitally Programmable Pulse Shaping
An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector
An SOI structure for flash A/D converter
A 65 nm CMOS Inductorless Triple Band Group WiMedia UWB PHY
An IEEE 1451 standard transducer interface chip with 12-b ADC, two 12-b DAC's, 10-kB flash EEPROM, and 8-b microcontroller
An ECL gate with improved speed and low power in a BiCMOS process
A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface
Systematic capacitance matching errors and corrective layout procedures
53 Gbps Native GF(2 4 ) 2 Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors
A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture
A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology
A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS
A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies
A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver
The Path to the Software-Defined Radio Receiver
An Ultralow-Power Receiver for Wireless Sensor Networks
A 3.4-µW Object-Adaptive CMOS Image Sensor With Embedded Feature Extraction Algorithm for Motion-Triggered Object-of-Interest Imaging
A 780-950 MHz, 64-146 µW Power-Scalable Synchronized-Switching OOK Receiver for Wireless Event-Driven Applications
An experimental 4 Mb flash EEPROM with sector erase
An adjustment-free single-chip video signal processing LSI for VHS VCR's
A Multifrequency Passive Sensing Tag With On-Chip Temperature Sensor and Off-Chip Sensor Interface Using EPC HF and UHF RFID Technology
Cancellation of OpAmp Virtual Ground Imperfections by a Negative Conductance Applied to Improve RF Receiver Linearity
Varactor characteristics, oscillator tuning curves, and AM-FM conversion
A 420-GHz Sub-5-μm Range Resolution TX-RX Phase Imaging System in 40-nm CMOS Technology
Log domain filtering for RF applications
A low voltage SRAM for embedded applications
A Low-Power SRAM Using Bit-Line Charge-Recycling
An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros
A 12-to-1-1.8-V Hybrid DC-DC Converter With a Charge Converging Phase for Inductor Current Reduction
Cell and circuit design for single-poly EPROM
Toward Temperature Tracking With Unipolar Metal-Oxide Thin-Film SAR C-2C ADC on Plastic
A 0.1-nW-1- $\mu$ W Energy-Efficient All-Dynamic Versatile Capacitance-to-Digital Converter
A Multistep Multistage Fifth-Order Incremental Delta Sigma Analog-to-Digital Converter for Sensor Interfaces
SMIV: A 16-nm 25-mm² SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators
A custom-designed receiver-stimulator chip for an advanced multiple-channel hearing prosthesis
A 9-mm 2 Ultra-Low-Power Highly Integrated 28-nm CMOS SoC for Internet of Things
Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis
A 4.7 T/11.1 T NMR Compliant 50 nW Wirelessly Programmable Implant for Bioartificial Pancreas In Vivo Monitoring
A 10-b 125-MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources
Sub-nW Wake-Up Receivers With Gate-Biased Self-Mixers and Time-Encoded Signal Processing
A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes
A p-well GaAs MESFET technology for mixed-mode applications
A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology
Millimeter-Wave Series Power Combining Using Sub-Quarter-Wavelength Baluns
Design considerations of high-dynamic-range wide-band amplifiers in BiCMOS technology
Stacking Isolated SC Cores for High-Voltage Wide Input Range Monolithic DC-DC Conversion
A technique for real-time measurement of Nth-order derivatives d N V/dI N
An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices
New Associate Editor
Dual-Loop System of Distributed Microregulators With High DC Accuracy, Load Response Time Below 500 ps, and 85-mV Dropout Voltage
A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs
A 170-GHz Fully Integrated Single-Chip FMCW Imaging Radar with 3-D Imaging Capability
A physical alpha-power law MOSFET model
Parallel-path digital-to-analog converters for Nyquist signal generation
Yield and speed optimization of a latch-type voltage sense amplifier
Message From the Outgoing Editor-in-Chief
A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines
A 0.31-THz Orbital-Angular-Momentum (OAM) Wave Transceiver in CMOS With Bits-to-OAM Mode Mapping
A 64-b microprocessor with multimedia support
A 0.155-, 0.622-, and 2.488-Gb/s automatic bit-rate selecting clock and data recovery IC for bit-rate transparent SDH systems
An Integrated Linear Regulator With Fast Output Voltage Transition for Dual-Supply SRAMs in DVFS Systems
A low-power DCT core using adaptive bitwidth and arithmetic activity exploiting signal correlations and quantization
Modeling and analysis of substrate coupling in integrated circuits
A 3 V GSM codec
Subranging BJT-Based CMOS Temperature Sensor With a ±0.45 °C Inaccuracy (3σ) From -50 °C to 180 °C and a Resolution-FoM of 7.2 pJ·K² at 150 °C
An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators
Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks
A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB
A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS
A GaAs MMIC chip-set for mobile communications using on-chip ferroelectric capacitors
A GaAs four-quadrant analog multiplier circuit
A Pitch-Matched Low-Noise Analog Front-End With Accurate Continuous Time-Gain Compensation for High-Density Ultrasound Transducer Arrays
A double-sampling pseudo-two-path bandpass ΔΣ modulator
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management
A 7-ns/850-mW GaAs 4-kb SRAM with little dependence on temperature
A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS
A 30 ppm < 80 nJ Ring-Down-Based Readout Circuit for Resonant Sensors
HUNBN, a 16-nm Digital In-Memory-Compute SoC for Edge CNN Application Achieving 24 TOPs/W (4b) at System Level
A Quad-Mode Structure-Reconfigurable Regulating Rectifier With Shared-Inductor DC-DC Energy Recycling in a Wireless Power Receiver
A 900-MHz Direct Delta-Sigma Receiver in 65-nm CMOS
Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI
Immediate Calibration of Operational Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling
A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration
Interference Robust Detector-First Near-Zero Power Wake-Up Receiver
A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance
A 128-pixel CMOS image sensor with integrated analog nonvolatile memory
A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions
Frequency-Translational Quadrature-Hybrid Receivers for Very-Low-Noise, Frequency-Agile, Scalable Inter-Band Carrier Aggregation
Novel level-identifying circuit for flash multilevel memories
A 10-MHz Green-Mode Automatic Reconfigurable Switching Converter for DVS-Enabled VLSI Systems
A 72-Channel Resistive-and-Capacitive Sensor-Interface Chip With Noise-Orthogonalizing and Pad-Sharing Techniques
A 250-MHz single-chip multiprocessor for audio and video signal processing
A Micropower Chopper - CDS Operational Amplifier
Two novel fully complementary self-biased CMOS differential amplifiers
Wireless Clock Distribution System Using an External Antenna
The stabilized reference-line (SRL) technique for scaled DRAMs
A low-power 22-bit incremental ADC
A 234-261-GHz 55-nm SiGe BiCMOS Signal Source with 5.4-7.2 dBm Output Power, 1.3% DC-to-RF Efficiency, and 1-GHz Divided-Down Output
Low-power CMOS continuous-time filters
Novel high speed circuit structures for BiCMOS environment
An architecture of high-performance frequency and phase synthesis
N-delta and differential average signal processors: detailing of their signal and noise response
Area-efficient CMOS charge pumps for LCD drivers
Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs
A 6.5-μW 10-kHz BW 80.4-dB SNDR G m -C-Based CT ∆∑ Modulator With a Feedback-Assisted G m Linearization for Artifact-Tolerant Neural Recording
Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs
A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing
Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET
A 7T-SRAM With Data-Write Technique by Capacitive Coupling
A 28-nm 8-28-GHz Eight-Phase Clock Generator Using an Injection-Locked Dual-Feedback Ring Oscillator
An Electronic Dispersion Compensation Transceiver for 10- and 28-Gb/s Directly Modulated Lasers-Based Optical Links
Battery-less Tri-band-Radio Neuro-monitor and Responsive Neurostimulator for Diagnostics and Treatment of Neurological Disorders
A 280 µW Dynamic Zoom ADC With 120 dB DR and 118 dB SNDR in 1 kHz BW
ATM in B-ISDN communication systems and VLSI realization
A 1-V operating 256-kb full-CMOS SRAM
Trends in megabit DRAM circuit design
A single-chip optical sensor with analog memory for motion detection
A CMOS bandgap reference circuit with sub-1-V operation
A self-calibrating single-chip CMOS camera with logarithmic response
Analysis of the Influence of Substrate on the Performance of On-Chip MOS Decoupling Capacitors
An 11 GS/s 1.1 GHz Bandwidth Interleaved ΔΣ DAC for 60 GHz Radio in 65 nm CMOS
A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS
A Resonant Global Clock Distribution for the Cell Broadband Engine Processor
A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables
A feedforward technique with frequency-dependent current mirrors for a low-voltage wideband amplifier
A 0.9-μA Quiescent Current High PSRR Low Dropout Regulator Using a Capacitive Feed-Forward Ripple Cancellation Technique
Class-D CMOS Oscillators
A 1.2-V Dynamic Bias Latch-Type Comparator in 65-nm CMOS With 0.4-mV Input Noise
A 230-260-GHz Wideband and High-Gain Amplifier in 65-nm CMOS Based on Dual-Peak $G_{{\mathrm{max}}}$ -Core
A 2.4-GHz Full-Duplex Transceiver With Broadband, Linearity-Enhanced, and Long-Delay Spread Self-Interference Cancellation
Robustly testable static CMOS parity trees derived from binary decision diagrams
A low-power low-noise ultrawide-dynamic-range CMOS imager with pixel-parallel A/D conversion
Measurements and analysis of PLL jitter caused by digital switching noise
A Fully Isolated Delta-Sigma ADC for Shunt Based Current Sensing
A high-gain monolithic D-band InP HEMT amplifier
A 512 16-b bit-serial sorter chip
A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus
A Hybrid Single-Inductor Bipolar-Output DC-DC Converter With Floating Negative Output for AMOLED Displays
Secure Satellite Communication Digital IF CMOS Q-Band Transmitter and K-Band Receiver
A 26 μ W 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios
A 9-kbit associative memory for high-speed parallel processing applications
An Analog Front-End for a Multifunction Sensor Employing a Weak-Inversion Biasing Technique With 26 nVrms, 25 aCrms, and 19 fArms Input-Referred Noise
A rail-to-rail input/output CMOS power amplifier
A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS
A 40 mW 3 Gb/s Self-Compensated Differential Transimpedance Amplifier With Enlarged Input Capacitance Tolerance in 0.18 µm CMOS Technology
CMOS chip for invasive ultrasound imaging
A superconducting tracking A/D converter
An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput
A 77-GHz 8RX3TX Transceiver for 250-m Long-Range Automotive Radar in 40-nm CMOS Technology
A Proactive Droop Mitigation Technique Using Dual-Proportional-Derivative Controller Based on Current and Voltage Prediction
A Type-I Sub-Sampling PLL With a 100×100 µm 2 Footprint and -255-dB FOM
A high-IP3 RF receiver chip set for mobile radio base stations up to 2 GHz
A Continuously and Widely Tunable 5 dB-NF 89.5 dB-Gain 85.5 dB-DR CMOS TV Receiver With Digitally-Assisted Calibration for Multi-Standard DBS Applications
CIMFormer: A Systolic CIM-Array-Based Transformer Accelerator With Token-Pruning-Aware Attention Reformulating and Principal Possibility Gathering
A static power saving TTL-to-CMOS input buffer
A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications
A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance
A 1.5 V full-swing BiCMOS dynamic logic gate circuit suitable for VLSI using low-voltage BiCMOS technology
The first IA-64 microprocessor
A 3.8-µW 1.5-NEF 15-GΩ Total Input Impedance Chopper Stabilized Amplifier With Auto-Calibrated Dual Positive Feedback in 110-nm CMOS
A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth
A low-phase-noise and low-power multiband CMOS voltage-controlled oscillator
Development of highly dense four-stage flat-gain 1-W 6-18-GHz MMIC power amplifier chip
A time-based energy-efficient analog-to-digital converter
A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology
Design and Characterization of a <4-mW/Qubit 28-nm Cryo-CMOS Integrated Circuit for Full Control of a Superconducting Quantum Processor Unit Cell
A flexible redundancy technique for high-density DRAMs
A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging
An 8.93 TOPS/W LSTM Recurrent Neural Network Accelerator Featuring Hierarchical Coarse-Grain Sparsity for On-Device Speech Recognition
A 5-MHz IF digital FM demodulator
A μ-NMC-Δ-IMC Heterogeneous STT-MRAM Compute-in-Memory Macro Using Δ-Clamping Bit Reduction for Noise-Tolerant Bayesian Neural Networks
A single-power-supply 10-b video BiCMOS sample-and-hold IC
Capacitively-Coupled CMOS VCSEL Driver Circuits
A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer
A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS
Correction to "A 40-Gb/s Clock and Data Recovery Circuit in 0.18μm CMOS Technology"
A 40 nm CMOS Derivative-Free IF Active-RC BPF With Programmable Bandwidth and Center Frequency Achieving Over 30 dBm IIP3
A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking
Noise and power reduction in filters through the use of adjustable biasing
InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers
A 25-ns 4-Mbit CMOS SRAM with dynamic bit-line loads
A 184-μW Error-Tolerant Real-Time Hand Gesture Recognition System With Hybrid Tiny Classifiers Utilizing Edge CNN
A large V DS data retention test pattern for DRAM's
Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique
Compact high-frequency output buffer for testing of analog CMOS VLSI circuits
A deep-submicrometer analog-to-digital converter using focused-ion-beam implants
A novel frequency-independent third-order intermodulation distortion cancellation technique for BJT amplifiers
A Single-Chip CMOS Bluetooth v2.1 Radio SoC
Introduction to the Special Section on the 2017 RFIC Symposium