yusuke1997/dblp-id-title huggingface dataset:
Guest Editors' Introduction: Hot Chips 14 - Innovation in the Face of Uncertain Economics
OHIO: Enhancing RDMA Scalability in Alltoall With Optimized Communication Overlap
Using Intradisk Parallelism to Build Energy-Efficient Storage Systems
MOPED: Accelerating Data Communication on Future CMPs
Standardization and Competitive Advantage
What GPU Computing Means for High-End Systems
Unifying Spatial Accelerator Compilation With Idiomatic and Modular Transformations
Guest Editor's Introduction: The PowerPC in Perspective
Resistive Ternary Content Addressable Memory Systems for Data-Intensive Computing
Roomware-Moving Toward Ubiquitous Computers
Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics
The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs
Look-Ahead Architecture Adaptation to Reduce Processor Power Consumption
The Velox Transactional Memory Stack
Performance Evaluation of the Cray X1 Distributed Shared-Memory Architecture
The Scramble After Breakthrough
A Futurebus interface from off-the-shelf parts
Utilizing Dark Silicon to Save Energy with Computational Sprinting
The IMS T800 Transputer
The Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems
Architectural Implications of Nanoscale-Integrated Sensing and Computing
2015 International Symposium on Computer Architecture Influential Paper Award
Processor Design in 3D Die-Stacking Technologies
Challenging search engines and pop-ups under copyright law--Part 3
Advanced Camera Technologies for Broadcasting
Symptoms of Healthy Innovativeness
Architecture of the Scalable Communications Core's Network on Chip
Special Issue on COOL Chips
Too Much Internet Backbone?
An interactive fuzzy CAD tool
A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum
Systems technologies for silicon auditory models
Emerging Hot Chips and Systems
The microprocessor's impact on society
Meta-assemblers
Get to market faster with FPGAs [Micro view]
A General Methodology on Designing Acyclic Channel Dependency Graphs in Interconnection Networks
Editor in Chief's Message: Saving power-Lessons from embedded systems
Not in Name Alone: A Memristive Memory Processing Unit for Real In-Memory Processing
How VLIWs Were Adopted as Digital Signal Processors
The anatomy of foresight traps
Motorola's 88000 family architecture
Environmentally Sustainable Computing
Resilient Chip Multiprocessors with Mixed-Grained Reconfigurability
The Laplace Microarchitecture for Tracking Data Uncertainty
Path2SL: Leveraging InfiniBand Resources to Reduce Head-of-Line Blocking in Fat Trees
Exploration of Bitflip's Effect on Deep Neural Network Accuracy in Plaintext and Ciphertext
Microprocessor memory management units
Fifty Years of the International Symposium on Computer Architecture: A Data-Driven Retrospective
Standardization skullduggery update: UMTS standard
From Monsoon to StarT-Voyager: University-Industry Collaboration
Hot Chips-hot Stuff
Tiered Cache-Sharing Service for Virtual Machine Images Based on Memory Pool
Beginnings and Endings (EIC Message)
Guest Editors' Introduction: Red Hot Chili Papers
Spillovers, Bottlenecks, and More Invention After Invention
Software and Copyright Law: Court Judgments Remain Unpredictable
Enabling Portable Optimizations of Data Placement on GPU
Safety-Related Challenges and Opportunities for GPUs in the Automotive Domain
A New Definition for High-Performance Computing
Aggressive Business Tactics: Are There Limits?
Supporting NUMA-Aware I/O in Virtual Machines
Tydi: An Open Specification for Complex Data Structures Over Hardware Streams
UB-Mesh: A Hierarchically Localized nD-FullMesh Data Center Network Architecture
Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments
VRTX: A Real-Time Operating System for Embedded Microprocessor Applications
Software Demand, Hardware Supply
Intel 870: A Building Block for Cost-Effective, Scalable Servers
Wireless Commercial Breakthrough
Future SOC Possibilities
KiloCore: A Fine-Grained 1, 000-Processor Array for Task-Parallel Applications
Atari's ANTIC: My Favorite Microprocessor
A New Challenge (EIC Message)
Persistent Memory: Abstractions, Abstractions, and Abstractions
Radio Frequency Identification and the Electronic Product Code
Is mousetrapping unfair?
Processor implementations using queues
MEDIA: A successful European cooperation in microelectronics
Configurable Network Protocol Accelerator (COPA)
High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors
Increasing Throughput of In-Memory DNN Accelerators by Flexible Layerwise DNN Approximation
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies - Part XI: Patent Families
Don't call it a highway!
Data Marshaling for Multicore Systems
Assessing RJSCs In High-Level Language Support
Misapplied Metaphors in AI Policy
Accelerating Image-Sensor-Based Deep Learning Applications
The Ride Before the Fall
India China hurdle computing obstacles [DP industry]
Transnational electronic systems and patent infringement
Best Papers From Hot Chips 32
Structured Programming Can Be Applied to Microprocessors-Even by Novices
Hot Chips 23
Assessing Processor Sustainability Using the First-Order FOCAL Carbon Model
Adapting curriculum materials for different course sequences
Micro Economics: Soccer Mom Messaging Is the Poetry of Our Age
Low-Power, Real-Time Object-Recognition Processors for Mobile Vision Systems
Multitasking Parallel Method for High-End Embedded Appliances
MicroStandards Special Feature: A Comparison of 32-Bit Buses
BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs
Energy-Efficient Graphics and Multimedia in 28-nm Carrizo Accelerated Processing Unit
TCAM Architecture for IP Lookup Using Prefix Properties
Beyond Traditional Microprocessors for Geoscience High-Performance Computing Applications
Guest Editor's Introduction: Top Picks from the Computer Architecture Conferences of 2009
Accelerating Chip Design With Machine Learning
Hot Interconnects 26
The Future of Architectural Simulation
Accelerating multimedia with enhanced microprocessors
Verifying the FM9801 microarchitecture
VLSI accelerators for large database systems
The Advancing Technology of Motorola's Microprocessors and Microcomputers
Hardware-Enforced Comprehensive Memory Safety
POD: A 3D-Integrated Broad-Purpose Acceleration Layer
Hardware Atomicity: An Effective Abstraction for Reliable Software Speculation
You're Invited to a Party! (How To Hold a Collaborative IP-Development Session)
Using the Memory Channel Network
The Alpha 21364 Network Architecture
Hot Chips 28
The Motorola MC68020
ECP: Improving the Accuracy of Congesting-Packets Identification in High-Performance Interconnection Networks
Implementing Streaming SIMD Extensions on the Pentium III Processor
Amazon's One-Click Patent Loses Its Teeth (Micro Law)
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips
Motivating Security-Aware Energy Management
Virtuous Cycles
Using optical space-frequency analysis for real-time pattern recognition
Hot Interconnects 27
Is Moore's Law Slowing Down? What's Next?
Teaching Design in a Computer Architecture Course
Special Issue on Environmentally Sustainable Computing
Using OS Observations to Improve Performance in Multicore Systems
Guest Editors' Introduction: Energy-Efficient Design
Understanding and Characterizing Communication Characteristics for Distributed Transformer Models
The 2014 Top Picks in Computer Architecture
Transactional Memory: An Overview
MOSFET technology for low-voltage/low-power applications
The Internet of Things Revolution
Cache Coherence for GPU Architectures
Supporting Moderate Data Dependency, Position Dependency, and Divergence in PIM-Based Accelerators
The Challenges of Wearable Computing: Part 2
Hot Chips and Remembering a Pioneer
The NS32081 Floating-point Unit
Guest Editors' Introduction: Hot Chips 19
Scaling the Energy Proportionality Wall with KnightShift
MicroView
Guest Editor's Introduction: Introducing the Itanium Processors
SH-5: The 64-Bit SuperH Architecture
Guest Editor's Introduction: Critical Embedded Automotive Networks
IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors
Transactional Execution: Toward Reliable, High-Performance Multithreading
Cooperation: Japan's new watchword? [software industry]
Haswell: The Fourth-Generation Intel Core Processor
Non-Speculative Load Reordering in Total Store Ordering
CMOS technology trends and economics
2012 International Symposium on Computer Architecture Influential Paper Award
Client-server computing on Shrimp
Introducing the MICRO Test of Time Awards: Concept, Process, 2014 Winners, and the Future
Micro News: Moving into the 90-nm chip market; PowerPC runs at up to 2.5 GHz
Decoupled Control and Data Processing for Approximate Near-Threshold Voltage Computing
AMD Fusion APU: Llano
Phase-Change Technology and the Future of Main Memory
Transmitter equalization for 4-Gbps signaling
M32R/D-integrating DRAM and microprocessor
Java Use in Mobile Information Devices: Introducing JTRON
Free Software without a Free Lunch or Free Beer
Realization of Gmicro/200
Quantum Computing and the Design of the Ultimate Accelerator
Data Cache and Direct Memory Access in Programming Mediaprocessors
A tutorial on CRC computations
Supreme Court to Hear Semiconductor Chip Patent "Exhaustion" Case
ImplantBench: Characterizing and Projecting Representative Benchmarks for Emerging Bioimplantable Computing
IBM z10: The Next-Generation Mainframe Microprocessor
xDSPcore: A Compiler-Based Configurable Digital Signal Processor
Tuple Pruning Using Bloom Filters for Packet Classification
EDIF: The Standard for Workstation Intercommunication
IBM zEC12: The Third-Generation High-Frequency Mainframe Microprocessor
Profiling a Warehouse-Scale Computer
Memories From IBM 370 to ARM
Can Software Be Tied to Hardware? Part II
An Energy-Aware Debugger for Intermittently Powered Systems
Emerging Memory Technologies
Four nightmares for net neutrality
NetFPGA SUME: Toward 100 Gbps as Research Commodity
A Software-Configurable Processor Architecture
Interconnect Opportunities for Gigascale Integration
Data Communication in Systems with Heterogeneous Timing
The IBM Blue Gene/Q Compute Chip
Microcomputers, Slotcars, and Education
Failure Tolerant Training With Persistent Memory Disaggregation Over CXL
Optimization and Benchmark of Cryptographic Algorithms on Network Processors
Server Designs for Warehouse-Computing Environments
Data Center Power and Energy Management: Past, Present, and Future
Leaking Secrets Through Compressed Caches
Cascading content-addressable memories
Project tools (Micro Reviews)
Kunpeng 920: The First 7-nm Chiplet-Based 64-Core ARM SoC for Cloud Services
Maintaining I/O Data Coherence in Embedded Multicore Systems
Guest Editor's Introduction: Radio Frequency Identification and Noncontact Smart Cards
A Fast Entry Path into User Microcode on the VAX-11/780
Dark Silicon and the End of Multicore Scaling
Xbox 360 System Architecture
MITI's real world computing program
Scaling with Design Constraints: Predicting the Future of Big Chips
A High-Level-Language Programmable Controller, Part I-A Controller for Structured Microprogramming
The Architecture of a Capability-Based Microprocessor System
Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design
Parallel Programming Models for Heterogeneous Multicore Architectures
Digital camera system on a chip
AnySP: Anytime Anywhere Anyway Signal Processing
Discovering and Exploiting Program Phases
Commercial Products
A Reconfigurable Parallel Processor with Microprogram Control
Artificial Intelligence and the Jevons Paradox
Analyzing the Monolithic Integration of a ReRAM-Based Main Memory Into a CPU's Die
The paradox of commodities
Neurocontrol for lateral vehicle guidance
MangoBoost Alice: Extremely Fast, Seamless, and Versatile FPGA-Accelerated DPU Solutions
Did the Price of the Internet Drop?
Unconscious Meaning
Galapagos: A Full Stack Approach to FPGA Integration in the Cloud
NVIDIA Hopper H100 GPU: Scaling Performance
Designing Efficient Heterogeneous Memory Architectures
Early History of Texas Instrument's Digital Signal Processor
BTRON: THE Business-oriented Operating System
Technology Policy and the Trump Administration
SWAP: Parallelization through Algorithm Substitution
Prospects for Reconfigurable Systems
Pentium FDIV flaw-lessons learned
TCN-CUTIE: A 1, 036-TOp/s/W, 2.72-µJ/Inference, 12.2-mW All-Digital Ternary Accelerator in 22-nm FDX Technology
IOCost: Block Input-Output Control for Containers in Datacenters
Net access-divvying up the pie [Copyright and the Internet]
Mathematical software: Plod
An Advanced Communication Protocol for the Proposed IEEE 896 Futurebus
Samsung M3 Processor
Implementing Sparc in ECL
The Paradox of Technological Déjà Vu
European activities for EDA standardization
Developing diffractive optics for optical computing
A Safety-First Approach to Memory Models
An earful about Zvi's e-mail
Managing Development
Toward advanced parallel processing: exploiting parallelism at task and instruction levels
Outsourcing and climbing a value chain
Guest Editor's Introduction: Hot Interconnects 11 - Solving Network Bottlenecks
High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V&V
Guest Editors' Introduction: Hot Chips 12
Optically interconnected multicomputers using inverted-graph topologies
Forming, funding, and operating standard-setting consortia
Spider: a high-speed network interconnect
10-Gigabit Ethernet Connectivity for Computer Servers
Toward Dark Silicon in Servers
Hot Chips 30
Exploring Large-Scale CMP Architectures Using ManySim
Can We Stop Software Theft?
Information flow in digital metal-oxide semiconductor circuits
Loop-Directed Mothballing: Power Gating Execution Units Using Runtime Loop Analysis
A Terabit Multiservice Switch
Micro Review: Life and Work
The Challenges of Wearable Computing: Part 1
Scalable Load and Store Processing in Latency-Tolerant Processors
System on a Chip: Changing IC Design Today and in the Future
Serving DNNs in Real Time at Datacenter Scale with Project Brainwave
Wire-OR Logic on Transmission Lines
An associative accelerator for large databases
Monolithic 3-D Integration
The Memory Stick
Heterogeneity in Response to the Power Wall
On Architectural Support for Systems Security
Leakage Power Analysis and Reduction for Nanoscale Circuits
Systematically testing a real-time operating system
Virtual Logical Qubits: A Compact Architecture for Fault-Tolerant Quantum Computing
Designing Programmable Accelerators for Sparse Tensor Algebra
Disassembling object code: a misdeed
Connecting Will Be Commonplace
Uncomfortable Economic Waters
Introduction to ITRON the Industry-oriented Operating System
Impact of Parameter Variations on Circuits and Microarchitecture
Mapping High-Level Syntax And Structure into Assembly Language
The PowerPC 604 RISC microprocessor
Customizing the Branch Predictor to Reduce Complexity and Energy Consumption
The Scalable Coherent Interface and related standards projects
Not a Young and Restless Market
The Mips R10000 superscalar microprocessor
Real-time implementation of the Newton-Euler equations of motion on the NEC μPD77230 DSP
A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM
System-Level Performance Metrics for Multiprogram Workloads
Microprocessor Advances and the Mainframe Legacy
Sparc64 X: Fujitsu's New-Generation 16-Core Processor for Unix Servers
A Chip Multithreaded Processor for Network-Facing Workloads
Arcane Facts and New Words: Expanding Your Creative Talent
Memory Subsystems in High-End Routers
Temperature-Resilient RRAM-Based In-Memory Computing for DNN Inference
The Price is Not Right
Cohesion: An Adaptive Hybrid Memory Model for Accelerators
Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training
AMD Instinct MI300X: A Generative AI Accelerator and Platform Architecture
Redesigning File Systems for Nonvolatile Main Memory
A Communication-Centric Approach for Designing Flexible DNN Accelerators
A Taxonomy of ML for Systems Problems
A proposed standard for extending high-level languages for microprocessors - IEEE Task P755
Rinda: a relational database processor with hardware specialized for searching and sorting
Making Systems
Predicting and precluding problems with memory latency
Visual inspection in industrial manufacturing
Going Vertical: The Future of Electronics
Vision assistance in scenes with extreme contrast
A Facility for Simulating Multiprocessors
Software fault tolerance in architectures with hierarchical protection levels
The market and computer technology
Computing With COOL Chips
2017 International Symposium on Computer Architecture Influential Paper Award
An Ultra Small Individual Recognition Security Chip
To have and to have not [techno-haves and have-nots]
Photonic NoCs: System-Level Design Exploration
Unified Collective Communication: A Unified Library for CPU, GPU, and DPU Collectives
Fault Tolerance in Regular Network Architectures
A Comparative Security Analysis of Current and Emerging Technologies
ERIDANUS: Efficiently Running Inference of DNNs Using Systolic Arrays
"Hot" and "Cool" chips [Guest Editor's Introduction]
An Intelligent RAM with Serial I/Os
The Modular Multiprocessor-A Model for Laboratory Instrument Design
Introduction to the NS16000 Architecture
Building Maze Solutions with Computational Dreaming
Ultra Low-Energy SRAM Design for Smart Ubiquitous Sensors
MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings
RST cache memory design for a highly coupled multiprocessor system
Spine-Free Networks for Large Language Model Training
Underclocked Software Prefetching: More Cores, Less Energy
Challenges in processor modeling and validation [Guest Editors?? introduction]
Research and development needs for advanced vehicle control systems
High-speed electrical signaling: overview and limitations
Internationalization support in Java
Accelerating Silent Witness Storage
I-DVFS: Instantaneous Frequency Switch During Dynamic Voltage and Frequency Scaling
Redefining the Role of the CPU in the Era of CPU-GPU Integration
Sorting and Searching using Ternary CAMs
A Review of Wisconsin Alumni Research Foundation v. Apple - Part VI
Ivy Bridge Server: A Converged Design
Guest Editors' Introduction: High-Performance Interconnects
Micro economics: contrasting opinions about convergence
Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers
Alice v. CLS Bank: Are US Business-Method and Software Patents Doomed? Part 2
Artificial Intelligence Best Practices in Smart Agriculture
The iCore 520-MHz Synthesizable CPU Core
ARM996HS: The First Licensable, Clockless 32-Bit Processor Core
MEMTI: Optimizing On-Chip Nonvolatile Storage for Visual Multitask Inference at the Edge
Future WAN Telecommunications
Godson-3: A Scalable Multicore RISC Processor with x86 Emulation
OpenPiton at 5: A Nexus for Open and Agile Hardware Design
Shrink-wrap license restrictions-preempted?
Gate-Level Information-Flow Tracking for Secure Architectures
UltraSPARC-III: designing third-generation 64-bit performance
Efficient Spatial Processing Element Control via Triggered Instructions
Creating Foundations for Secure Microarchitectures With Data-Oblivious ISA Extensions
Designing an asynchronous processor using Petri nets
Guest Editors' Introduction: Computer Architecture Simulation and Modeling
Guest Editorial: Media processing: a new design target
Putting Faulty Cores to Work
Hot Interconnects and Debates on Computer Architecture Research Directions
The Balance multiprocessor system
Special Issue on The Past, Present, and Future of Warehouse-Scale Computing
Compiling for Vector Extensions With Stream-Based Specialization
A High-Level-Language Programmable Controller
Standardization and Coordination
Power-Conscious Design of the Cell Processor's Synergistic Processor Element
Bulldozer: An Approach to Multithreaded Compute Performance
An integrated functional performance simulator
OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs
Is Gatoring Unfair or Illegal?
PVCoherence: Designing Flat Coherence Protocols for Scalable Verification
Pandemics and the Dismal Technology Economy
FTC and Apple Sue Qualcomm for Cell Phone Standardization Skullduggery: Part 1
TCP Splitter: A TCP/IP Flow Monitor in Reconfigurable Hardware
Development of an ASIC set for signal processing
Overclocking in Immersion-Cooled Datacenters
On-Chip Interconnection Networks of the TRIPS Chip
Organized for Cycles of Change
The Non-Death of Paper
Runahead Execution: An Effective Alternative to Large Instruction Windows
Maximizing Interconnect Bandwidth and Efficiency in Nonvolatile Memory, Express-Based Key-Value Solid-State Devices With Fine-Grained Value Transfer
Accelerating Genomic Data Analytics With Composable Hardware Acceleration Framework
Tiny Tera: a packet switch core
The Tron Project
Hot Chips 22
Reliable Computing with Ultra-Reduced Instruction Set Coprocessors
A Review of Wisconsin Alumni Research Foundation v. Apple - Part II
A new PC parallel interface standard [IEEE Std 1284-1994]
Triggers, Transmissions, and Adjustments
Micro Law
Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching
A Hardware-Software Blueprint for Flexible Deep Learning Specialization
Designing for Responsiveness with Computational Sprinting
Navigating Applications Development in Generative AI
Motorola MC68332: One of the First True SoCs
Micro-RISC architecture for the wireless market
A Hardware/Software Co-Design Vision for Deep Learning at the Edge
The Virtual Interface Architecture
OMI's Collaborative Approach
Miscellany [Book reviews]
Architectural Risk
Shortages of Integrated Circuits
Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express 6.0 and Compute Express Link 3.0
Virtual reality in Japan
EOS: a real-time operating system adapts to application architectures
Efficient Real-Time Fine-Grained Concurrency on Low-Cost Microcontrollers
A Multilevel Computing Architecture for Embedded Multimedia Applications
Mosaic Pages: Big TLB Reach With Small Pages
AFAN: tool for optimizing fuzzy controllers
Using STEAM for Thermal Simulation of Storage Systems
Sparcle: an evolutionary processor design for large-scale multiprocessors
Special Issue on Hot Interconnects 31
Sustainable AI Processing at the Edge
MicroScope: Enabling Microarchitectural Replay Attacks
The TMS34010: an embedded microprocessor
IPC Considered Harmful for Multiprocessor Workloads
What I Missed
Pod-racing: bulk-bitwise to floating-point compute in racetrack memory for machine learning at the edge
Distributed fault tolerance: lessons from Delta-4
Eliminating Redundant Computation and Exposing Parallelism through Data-Triggered Threads
CMOS options for single chip applications
Engineering Support Systems for Engineering Managers
Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors
Inside Project Brainwave's Cloud-Scale, Real-Time AI Processor
Aérgia: A Network-on-Chip Exploiting Packet Latency Slack
Fault tolerance in highly parallel hardware systems
Guest Editors' Introduction: Cool Chips
CogniServe: Heterogeneous Server Architecture for Large-Scale Recognition
Die Stacking Is Happening
Direct RAMbus technology: the new main memory standard
Year 2000, Windows 98, Help!
Charles R. (Chuck) Moore (1961 - 2012)
Hot Chips 27
Special Issue on Contemporary Industry Products 2024
DeepTools: Compiler and Execution Runtime Extensions for RaPiD AI Accelerator
Active Guardband Management in Power7+ to Save Energy and Maintain Reliability
Unveiling the Hardware and Software Implications of Microservices in Cloud and Edge Systems
Advice for Investigators
European trends in library development
GPUs and the Future of Parallel Computing
Virtual network transport protocols for Myrinet
ITRON-MP: an adaptive real-time kernel specification for shared-memory multiprocessor systems