yusuke1997/dblp-id-title huggingface dataset:
Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5~µs
DiTTO: A Distance Adaptive Over 100-mW Wireless Power Transfer System With 1.695-Mb/s Uplink Telemetry and a Shared Inductor Two-Output Regulating Rectification
A high bandwidth constant g m and slew-rate rail-to-rail CMOS input circuit and its application to analog cells for low voltage VLSI systems
Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis
A Sub-1-V Low-Noise Bandgap Voltage Reference
Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies
Analog circuit design optimization based on symbolic simulation and simulated annealing
A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs
A 2.4-GHz CMOS Power Amplifier With an Integrated Antenna Impedance Mismatch Correction System
A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers
A programmable VLSI architecture for computing multiplication and polynomial evaluation modulo a positive integer
Effect of Substrate Contact Shape and Placement on RF Characteristics of 45 nm Low Power CMOS Devices
Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture
A 108 dB SNR, 1.1 mW Oversampling Audio DAC With A Three-level DEM Technique
Introduction to the Special Issue on the IEEE Bipolar/BiCMOS Circuits and Technology Meeting
A 12-GS/s 12-b 4× Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized Input Buffer
A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS
A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging
A High Modulation Bandwidth, 110 GHz Power-DAC Cell for IQ Transmitter Arrays With Direct Amplitude and Phase Modulation
A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor
A high-precision current-mode WTA-MAX circuit with multichip capability
A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer
Comparison frequency doubling and charge pump matching techniques for dual-band ΔΣ fractional-N frequency synthesizer
40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS
High-speed high-precision CMOS analog rank order filter with O(n) complexity
A Si 1.8 GHz RLC filter with tunable center frequency and quality factor
Integrated Class-D Audio Amplifier With 95% Efficiency and 105 dB SNR
A Hybrid Magnetic Current Sensor With a Multiplexed Ripple-Reduction Loop
A -91 dB THD+N, Class-D Piezoelectric Speaker Driver Using Dual Voltage/Current Feedback for Resistor-Less LC Resonance Damping
Transistor noise in SiGe HBT RF technology
A Wide-Load-Range and High-Slew Capacitor-Less NMOS LDO With Adaptive-Gain Nested Miller Compensation and Pre-Emphasis Inverse Biasing
A 10-b Two-Stage DAC with an Area-Efficient Multiple-Output Voltage Selector and a Linearity-Enhanced DAC-Embedded Op-Amp for LCD Column Driver ICs
On configurable oversampled A/D converters
An array processor for general purpose digital image compression
Analysis and Design of a Low-Loss 1-10 GHz Capacitive Stacking N-Path Filter/Mixer
A three-axis micromachined accelerometer with a CMOS position-sense interface and digital offset-trim electronics
A 1.1-/0.9-nA Temperature-Independent 213-/565-ppm/°C Self-Biased CMOS-Only Current Reference in 65-nm Bulk and 22-nm FDSOI
A CMOS Electrochemical Biochip With 32 × 32 Three-Electrode Voltammetry Pixels
A Three-Level Boost Converter With Fully State-Based Phase Selection Technique for High-Speed V CF Calibration and Smooth Mode Transition
An IF Bandpass Filter Based on a Low Distortion Transconductor
A 1.05-A/m Minimum Magnetic Field Strength Single-Chip, Fully Integrated Biometric Smart Card SoC Achieving 792.5-ms Transaction Time With Anti-Spoofing Fingerprint Authentication
A 24µW, Batteryless, Crystal-free, Multinode Synchronized SoC "Bionode" for Wireless Prosthesis Control
A 122-GHz SiGe-Based Signal-Generation Chip Employing a Fundamental-Wave Oscillator With Capacitive Feedback Frequency-Enhancement
Design of High-Resolution Continuous-Time Delta-Sigma Data Converters With Dual Return-to-Open DACs
A 600-dpi capacitive fingerprint sensor chip and image-synthesis technique
A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL
A 80-MHz bandpass ΔΣ modulator for a 100-MHz IF receiver
A Sub-0.8-pJ/bit Universal Soft-Detection Decoder Using ORBGRAND
An 80-Gb/s 2 31 -1 pseudorandom binary sequence generator in SiGe BiCMOS technology
A 5.6 nV/ √Hz Chopper Operational Amplifier Achieving a 0.5 μV Maximum Offset Over Rail-to-Rail Input Range With Adaptive Clock Boosting Technique
CACTI: an enhanced cache access and cycle time model
A current direction sense technique for multiport SRAM's
Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier
High-performance differential VCO based on Armstrong oscillator topology
A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS
Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range"
A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design
A 10-bit 200-MS/s CMOS parallel pipeline A/D converter
A Silicon-Germanium Receiver for X-Band Transmit/Receive Radar Modules
A Low-Energy Crystal-Less Double-FSK Sensor Node Transceiver for Wireless Body-Area Network
An 85-MHz fourth-order programmable IIR digital filter chip
Compact Thermal-Diffusivity-Based Temperature Sensors in 40-nm CMOS for SoC Thermal Monitoring
A 1920 $\times$ 1080 25-Frames/s 2.4-TOPS/W Low-Power 6-D Vision Processor for Unified Optical Flow and Stereo Depth With Semi-Global Matching
Broadband 240-GHz Radar for Non-Destructive Testing of Composite Materials
A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning
A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping
A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications
Design and implementation of a 3D-LSI image sensing processor
A study of injection locking and pulling in oscillators
A 72.9-dB SNDR 20-MHz BW 2-2 Discrete-Time Resolution-Enhanced Sturdy MASH Delta-Sigma Modulator Using Source-Follower-Based Integrators
A Wireless Multi-Channel Peripheral Nerve Signal Acquisition System-on-Chip
A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture
InP DHBT technology and design methodology for high-bit-rate optical communications circuits
40-Gb/s amplifier and ESD protection circuit in 0.18-μm CMOS technology
A 100 Mb/s multi-LAN crosspoint chip set for cable management
A Continuous-Time Sturdy-MASH ΔΣ Modulator in 28 nm CMOS
Trimming analog circuits using floating-gate analog MOS memory
A Power-Harvesting Pad-Less Millimeter-Sized Radio
An Eight-Element 140-GHz Wafer-Scale IF Beamforming Phased-Array Receiver With 64-QAM Operation in CMOS RFSOI
1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs
A single-chip fingerprint sensor and identifier
Design techniques for VHF/UHF high-Q tunable bandpass filters using simple CMOS inverter-based transresistance amplifiers
A Sub-nW Single-Supply 32-kHz Sub-Harmonic Pulse Injection Crystal Oscillator
A high-resolution burst-mode laser transmitter with fast and accurate level monitoring for 1.25 Gb/s upstream GPONs
High-performance crystal oscillator circuits: theory and application
A Low Power Light Weight Wireless Multichannel Microsystem for Reliable Neural Recording
A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications
A Broadband CMOS Frequency Tripler Using a Third-Harmonic Enhanced Technique
Analysis and reduction of sense-amplifier offset
A monolithic 4-bit 2-Gsps resonant tunneling analog-to-digital converter
A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS
A 200-GHz Power Amplifier With 18.7-dBm P sat in 45-nm CMOS SOI: A Model-Based Large-Signal Approach on Cascaded Series-Connected Power Amplification
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC
A 10 mm 3 Inductive Coupling Radio for Syringe-Implantable Smart Sensor Nodes
Frequency-independent equivalent-circuit model for on-chip spiral inductors
A nA-Range Area-Efficient Sub-100-ppm/°C Peaking Current Reference Using Forward Body Biasing in 0.11- μ m Bulk and 22-nm FD-SOI
A 187-dB FoM S Power-Efficient Second-Order Highpass ΔΣ Capacitance-to-Digital Converter
GSM transceiver front-end circuits in 0.25-μm CMOS
A 32.75-Gb/s Voltage-Mode Transmitter With Three-Tap FFE in 16-nm CMOS
A D-Band OOK Transmitter With 50-GHz Bandwidth Achieving 32-Gbps Data Rate in 28-nm CMOS
Injection-Locked CMOS Frequency Doublers for μ -Wave and mm-Wave Applications
A Three-Wafer-Stacked Hybrid 15-MPixel CIS + 1-MPixel EVS With 4.6-GEvent/s Readout, In-Pixel TDC, and On-Chip ISP and ESP Function
A high-performance SI memory cell
Wideband VCO With Simultaneous Switching of Frequency Band, Active Core, and Varactor Size
Implementation of Initial-On ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology
FlashMAC: A Time-Frequency Hybrid MAC Architecture With Variable Latency-Aware Scheduling for TinyML Systems
A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET
Amorphous silicon thin film transistor circuit integration for organic LED displays on glass and plastic
Low-Phase-Noise Wideband Mode-Switching Quad-Core-Coupled mm-wave VCO Using a Single-Center-Tapped Switched Inductor
A 230-nW 10-s time constant CMOS integrator for an adaptive nerve signal amplifier
A 2.5D Integrated Voltage Regulator Using Coupled-Magnetic-Core Inductors on Silicon Interposer
100-MHz monolithic low-pass filters with transmission zeros using NIC integrators
Analog Building Blocks for Organic Smart Sensor Systems in Organic Thin-Film Transistor Technology on Flexible Plastic Foil
Low-power 1: 16 DEMUX and one-chip CDR with 1: 4 DEMUX using InP-InGaAs heterojunction bipolar transistors
An analytical threshold voltage and subthreshold current model for short-channel AlGaAs/GaAs MODFETs
A 77.3-dB SNDR 62.5-kHz Bandwidth Continuous-Time Noise-Shaping SAR ADC With Duty-Cycled G m -C Integrator
A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM
Exponential curvature-compensated BiCMOS bandgap references
A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM
A fully integrated CMOS receiver front-end for optic Gigabit Ethernet
A 0.2-2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55-448.6 ns Programmable Delay Range and 330 ns/mm 2 Area Efficiency
A packaged 1.1-GHz CMOS VCO with phase noise of -126 dBc/Hz at a 600-kHz offset
Low-Frequency Noise Phenomena in Switched MOSFETs
A simple on-chip repetitive sampling setup for the quantification of substrate noise
A micromachined low-power temperature-regulated bandgap voltage reference
A CMOS analog front-end circuit for an FDM-based ADSL system
A monolithic 2.3-Gb/s 100-mW clock and data recovery circuit in silicon bipolar technology
256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers
CMOS wideband amplifiers using multiple inductive-series peaking technique
A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS
10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology
A 7.2 GSa/s, 14 Bit or 12 GSa/s, 12 Bit Signal Generator on a Chip in a 165 GHz f T BiCMOS Process
A Supply Voltage Control Method for Performance Guaranteed Ultra-Low-Power Microcontroller
A 56-GHz Fractional-N PLL With 110-fs Jitter
A 2.06-zF rms Resolution Lock-In Amplifier With SAR-Assisted Parasitic and Baseline Capacitance Compensation
A "digital" 6-bit ADC in 0.25-μm CMOS
A 65 nm CMOS Digital Phase Imager for Time-Resolved Fluorescence Imaging
Fast up/down counters using identical cascaded modules
A 16-Mb Toggle MRAM With Burst Modes
A 219-to-231 GHz Frequency-Multiplier-Based VCO With ~3% Peak DC-to-RF Efficiency in 65-nm CMOS
A 178.9-dB FoM 128-dB SFDR VCO-Based AFE for ExG Readouts With a Calibration-Free Differential Pulse Code Modulation Technique
An integrated analog sensor for automatic alignment
A Power Optimized Continuous-Time ΔΣ ADC for Audio Applications
A design for high-speed low-power CMOS fully parallel content-addressable memory macros
A 1.8-mW CMOS ΣΔ modulator with integrated mixer for A/D conversion of IF signals
Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM
A CT 2-2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction
PCS/W-CDMA dual-band MMIC power amplifier with a newly proposed linearizing bias circuit
Errata for "Design and Analysis of a Programmable Receiver Front End Based on Baseband Analog-FIR Filtering Using an LPTV Resistor"
An AND-type match-line scheme for high-performance energy-efficient content addressable memories
A CMOS implementation of FitzHugh-Nagumo neuron model
A Capacitive Stacking Mixer-First Receiver With Higher Order Capacitive Feedback
A Si bipolar 28-GHz dynamic frequency divider
A 5-Gb/s OEIC with voltage-up-converter
A bitline leakage compensation scheme for low-voltage SRAMs
An RF-Powered FDD Radio for Neural Microimplants
A 6.75-8.25-GHz -250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier
Introduction to the Special Section on the 2020 Asian Solid-State Circuits Conference (A-SSCC)
A 32-Site 4-Channel High-Density Electrode Array for a Cochlear Prosthesis
Design and optimization of CMOS RF power amplifiers
The effects of oxide traps on the large-signal transient response of analog MOS circuits
Analysis and Design of Wideband I/Q CMOS 100-200 Gb/s Modulators
A four-phase handshaking asynchronous static RAM design for self-timed systems
A 20-μs Turn-On Time, 24-kHz Resolution, 1.5-100-MHz Digitally Programmable Temperature-Compensated Clock Generator
A Millimeter-Wave (23-32 GHz) Wideband BiCMOS Low-Noise Amplifier
A Noise Reconfigurable All-Digital Phase-Locked Loop Using a Switched Capacitor-Based Frequency-Locked Loop and a Noise Detector
A low-jitter 125-1250-MHz process-independent and ripple-poleless 0.18-μm CMOS PLL based on a sample-reset loop filter
A radiation-hard AGC stabilized SOS crystal oscillator
Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example
A 320 MHz CMOS triple 8 bit DAC with on-chip PLL and hardware cursor
Rotary traveling-wave oscillator arrays: a new clock technology
A 3×60Gb/s Transmitter/Repeater Front-End With 4.3V PP Single-Ended Output Swing in a 28nm UTBB FD-SOI Technology
Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS
Design Aspects of Single-Ended and Differential SiGe Low-Noise Amplifiers Operating Above f max /2in Sub-THz/THz Frequencies
A 265 V RMS Mains Interface Integrated in 0.35 µm CMOS
InP HBT driver circuit optimization for high-speed ETDM transmission
In Vitro Multi-Functional Microelectrode Array Featuring 59 760 Electrodes, 2048 Electrophysiology Channels, Stimulation, Impedance Measurement, and Neurotransmitter Detection Channels
8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew
Analysis and Design of Coupled Inductive Bridges for Magnetic Sensing Applications
Sensitivity Degradation in a Tri-Band GSM BiCMOS Direct-Conversion Receiver Caused by Transient Substrate Heating
A 1.54-pJ/b 64-Gb/s 16-QAM Intradyne Coherent Optical Receiver in 28-nm CMOS
On the leverage of high-f T transistors for advanced high-speed bipolar circuits
A 500-megabyte/s data-rate 4.5 M DRAM
A V-Band CMOS VCO With an Admittance-Transforming Cross-Coupled Pair
Cryo-CMOS Dual-Qubit Homodyne Reflectometer Array With Degenerate Parametric Amplification
A 0.1-1.5 GHz 8-bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection
A highly integrated 40-MIPS (peak) 64-b RISC microprocessor
A 50-MS/s (35 mW) to 1-kS/s (15 μW) power scaleable 10-bit pipelined ADC using rapid power-on opamps and minimal bias current variation
A Fully-Integrated Efficient CMOS Inverse Class-D Power Amplifier for Digital Polar Transmitters
Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode
A Column-Row-Parallel ASIC Architecture for 3-D Portable Medical Ultrasonic Imaging
A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS
The impact of scaling down to deep submicron on CMOS RF circuits
A Fully Integrated Transformer-Coupled Power Detector With 5 GHz RF PA for WLAN 802.11ac in 40 nm CMOS
A fully integrated VCO at 2 GHz
Flexible test mode approach for 256-Mb DRAM
A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode
Analysis and Design of Wideband Injection-Locked Ring Oscillators With Multiple-Input Injection
An 8.5-11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC
Influence of novel MOS varactors on the performance of a fully integrated UMTS VCO in standard 0.25-μm CMOS technology
A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy
A novel dynamic memory cell with internal voltage gain
A GaN Switchless-Class-G-Doherty-Continuum Power Amplifier With 140% Fractional Bandwidth
A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback
A clock distribution network for microprocessors
A 0.4-1.0 GHz, 47 MHop/s Frequency-Hopped TXR Front End With 20 dB In-Band Blocker Rejection
Frequency Tuning of Wide Temperature Range CMOS LC VCOs
An 800-MHz monolithic GaAs HBT serrodyne modulator
A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs
High-Voltage CMOS Active Pixel Sensor
A low-power small-area ±7.28-ps-jitter 1-GHz DLL-based clock generator
Design of High-Linearity Mixer-First Receivers for mm-Wave Digital MIMO Arrays
LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta Sigma Modulators
Single-chip design of bit-error-correcting stack decoders
5.5-V I/O in a 2.5-V 0.25-μm CMOS technology
A Fully Integrated Multilevel Synchronized-Switch-Harvesting-on-Capacitors Interface for Generic PEHs
Introduction to the Special Issue on the 2018 IEEE International Solid-State Circuits Conference (ISSCC)
An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications
Correction to "A Channel-Select Filter With Agile Blocker Detection and Adaptive Power Dissipation"
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces
A Time-Approximation Filter for Direct RF Transmitter
A 667 MHz Logic-Compatible Embedded DRAM Featuring an Asymmetric 2T Gain Cell for High Speed On-Die Caches
A Probabilistic Compute Fabric Based on Coupled Ring Oscillators for Solving Combinatorial Optimization Problems
A Column-Parallel On-Programming Pixel-Current Readout Embedded in an OLED Display Driver IC
An Over-60 dB True Rail-to-Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain
A Novel CMOS High-Power Terahertz VCO Based on Coupled Oscillators: Theory and Implementation
Constant-G m rail-to-rail common-mode range input stage with minimum CMRR degradation
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
A 60 V Auto-Zero and Chopper Operational Amplifier With 800 kHz Interleaved Clocks and Input Bias Current Trimming
A 6.78-MHz Wireless Power and Data Transfer System Achieving Simultaneous 48.6% End-to-End Efficiency and 4.0-Mb/s Forward Data Delivery With Interference-Free Rectifier
A 0.45-0.7 V 1-6 Gb/s 0.29-0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation
A 12.8-GS/s Time-Interleaved Sub-Sampling ADC Front End With 38-GHz Input Bandwidth and >39-dB SNDR for 1-32 GHz in 22-nm FDSOI
Enabling Online GaN Power Device Self-Health Monitoring With Analog SGD Supervised Learning and T J -Independent Precursor Measurement
A low-voltage, low quiescent current, low drop-out regulator
Guest Editorial IEEE 2022 BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium
A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS
A 300-μW 1.9-GHz CMOS oscillator utilizing micromachined resonators
A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC
Integrated overcurrent protection system for class-D audio power amplifiers
A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor
A quasi-matrix ferroelectric memory for future silicon storage
Feedback FET logic: a robust, high-speed low-power GaAs logic family
A 300-MHz quadrature direct digital synthesizer/mixer in 0.25-μm CMOS
A 376-μW per-Channel, Drift-Tolerant Translocation Recording Frontend With Event Detection for Nanopore Sensor Arrays
A D-Band Joint Radar-Communication CMOS Transceiver
A Pseudo-Virtual Ground Feedforwarding Technique Enabling Linearization and Higher Order Noise Shaping in VCO-Based ΔΣ Modulators
Design of a 32 bit microprocessor, TX1
A Fully Integrated CMOS Fluorescence Biochip for DNA and RNA Testing
A 32-Gb MLC NAND Flash Memory With Vth Endurance Enhancing Schemes in 32 nm CMOS
A 170-MHz CMOS pixel processor for windowing graphics
An 8-bit 200-MHz BiCMOS comparator
Eliminating inductive noise of external chip interconnections
Transforming bit-serial communication circuits into fast parallel VLSI implementations
Influence of device parameters on the switching speed of BiCMOS buffers
A Single-Stage Dual-Output Regulating Rectifier With Hysteretic Current-Wave Modulation
A highly integrated multifunction macro synthesizer chip (MMSC) for applications in 2-18 GHz synthesized sources
400-MHz random column operating SDRAM techniques with self-skew compensation
Frequency-scalable SiGe bipolar RF front-end design
Quasi-Resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking System for Dynamic Voltage-Frequency Scaling Systems
A 0.02 mm 2 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad
A Ka-Band Doherty-Like Non-Load Modulated Power Amplifier
Fully Integrated Frequency Reference With 1.7 ppm Temperature Accuracy Within 0-80°C
Introduction to the Special Section on the 2019 IEEE International Solid-State Circuits Conference (ISSCC)
Design of Low-Loss Transmission Lines in Scaled CMOS by Accurate Electromagnetic Simulations
A 12-ENOB Second-Order Noise-Shaping SAR ADC With PVT-Insensitive Voltage- Time-Voltage Converter
An X-band high-efficiency MMIC power amplifier with 20-dB return losses
A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device
A virtual clock enhancement method for DDS using an analog delay line
CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power A/D converters
A 32 × 128 SPAD-257 TDC Receiver IC for Pulsed TOF Solid-State 3-D Imaging
A Digitally Corrected 5-mW 2-MS/s SC Delta Sigma ADC in 0.25- μ m CMOS With 94-dB SFDR
A low-power 128-MHz VCO for monolithic PLL ICs
A 7-GHz 1.8-dB NF CMOS low-noise amplifier
A 14-bit, 10-Msamples/s D/A converter using multibit ΣΔ modulation
Series-resonant VHF micromechanical resonator reference oscillators
A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier
Two-phase boosted voltage generator for low-voltage DRAMs
Processor Energy-Performance Range Extension Beyond Voltage Scaling via Drop-In Methodologies
3-D Capacitive Interconnections With Mono- and Bi-Directional Capabilities