yusuke1997/dblp-id-title huggingface dataset:
The existence of a 2-factor in K 1, n -free graphs with large connectivity and large edge-connectivity
A characterization of well-covered graphs that contain neither 4- nor 5-cycles
Graph properties, graph limits, and entropy
Irredundance in inflated graphs
Subdivisions of oriented cycles in digraphs with large chromatic number
3-edge-connected embeddings have few singular edges
On the Circular Chromatic Number of Graph Powers
Extremal graphs in connectivity augmentation
A digraph represented by a family of boxes or spheres
Elementary proof of a counting formula for acyclic bipartite tournaments
Strong arc decompositions of split digraphs
Fragments in k critical n -connected graphs
A new sufficient condition for hamiltonian graphs
On-line and first fit colorings of graphs
Metric characterizations of proper interval graphs and tree-clique graphs
A note on Goldberg's conjecture on total chromatic numbers
A polynomial time algorithm recognizing link trees
Maximizing H -Colorings of a Regular Graph
A note on maximal triangle-free graphs
Perfect Matchings of Regular Bipartite Graphs
Antimagic Labeling of Regular Graphs
Uniformly 3-connected graphs
Local and global average degree in graphs and multigraphs
A Strengthening on Consecutive Odd Cycles in Graphs of Given Minimum Degree
A canonical representation of trivalent hamiltonian graphs
A note on the last new vertex visited by a random walk
A new upper bound for the harmonious chromatic number
Star Edge Coloring of Some Classes of Graphs
Constructions of covering triangulations with folds
Hypohamiltonian Planar Cubic Graphs with Girth 5
On Stahl's conjectures about the region distributions of bouquets
Edge-arc-disjoint paths in semicomplete mixed graphs
Threshold characterization of graphs with dilworth number two
Complete minors and average degree: A short proof
Facial non-repetitive edge-coloring of plane graphs
On the minimal genus of 2-complexes
Acyclic List Edge Coloring of Graphs
Hamilton decompositions of complete multipartite graphs with any 2-factor leave
Nonseparable graphs with a given number of cycles
Graphs without four-cycles
On the number of star-shaped classes in optimal colorings of Kneser graphs
Characterizing subgraphs of Hamming graphs
A Characterization of Graphs with No Octahedron Minor
Circular chromatic index of type 1 Blanusa snarks
On hamiltonian-connected graphs
$d$ -connectivity of the random graph with restricted budget
Graphs with constant link and small degree or order
Degree Conditions for Matchability in 3-Partite Hypergraphs
Stars and bonds in crossing-critical graphs
On the existence of special depth first search trees
Kempe equivalence of 4-critical planar graphs
Non-traceability of large connected claw-free graphs
Coverability of graph by three odd subgraphs
Chromatic neighborhood sets
A new graph parameter to measure linearity
On the Crossing Number of Kn without Computer Assistance
The independence number condition for the existence of a spanning f -tree
The Maximum Number of Dominating Induced Matchings
Treewidth of Cartesian Products of Highly Connected Graphs
The value of the Ramsey number r (3, 8)
Finding a subdivision of a prescribed digraph of order 4
Cataloging graphs by generating them uniformly at random
A note on mixed graphs and directed splitting off
Hamiltonian graphs involving distances
On several variations of the turan and ramsey numbers
Arithmetic graphs
A short proof of Kuratowski's graph planarity criterion
The maximum valency of regular graphs with given order and odd girth
Strong cliques in vertex-transitive graphs
On weighted sublinear separators
On the inclusion chromatic index of a graph
Extending colorings of locally planar graphs
Extremal H -Colorings of Graphs with Fixed Minimum Degree
Degree criteria and stability for independent transversals
Hamiltonian cycles in k -partite graphs
Vertex-disjoint cycles of the same length in tournaments
Degree conditions for 2-factors
List circular coloring of trees and cycles
Seven criteria for integer sequences being graphic
Hypergraph Anti-Ramsey Theorems
On the probability that a random subtree is spanning
On graphs with subgraphs having large independence numbers
On the Decay of Crossing Numbers of Sparse Graphs
Covering hypergraphs are Eulerian
A Short Proof That χ Can be Bounded ε Away from Δ + 1 toward ω
A short proof of a theorem on Hamiltonian graphs
New results on rectilinear crossing numbers and plane embeddings
Some sufficient conditions for the existence of a 1-factor
On unavoidable hypergraphs
Bipartite labeling of trees with maximum degree three
Distributing vertices on Hamiltonian cycles
Minimum Power Dominating Sets of Random Cubic Graphs
Connectivity and separating sets of cages
On a Poset of Trees II
The linear arboricity of planar graphs of maximum degree seven is four
Decomposing graphs with girth at least five under degree constraints
Anti-magic graphs via the Combinatorial NullStellenSatz
Cochromatic Number and the Genus of a Graph
Counting 5-connected planar triangulations
On q -trees
Total colorings of planar graphs with large maximum degree
Bounds on vertex colorings with restrictions on the union of color classes
The size of strength-maximal graphs
Embedding Factorizations for 3-Uniform Hypergraphs
C5 ${C}_{5}$ is almost a fractalizer
When the cartesian product of two directed cycles is hypo-Hamiltonian
Closures, cycles, and paths
Antimagic Labeling of Cubic Graphs
On the characterization of path graphs
Rainbow powers of a Hamilton cycle in G n,p
The genus of Petersen powers
Decomposing and Clique-Coloring (Diamond, Odd-Hole)-Free Graphs
Balanced coloring of bipartite graphs
Graphs with given odd sets and the least number of vertices
An Asymptotic Version of the Multigraph 1-Factorization Conjecture
Star chromatic index of subcubic multigraphs
Graphs with unique maximal clumpings
Strict majority functions on graphs
Independence number and clique minors
On Bipartite Biregular Large Graphs Derived From Difference Sets
Series-parallel graphs: A logical approach
Number of Subgraphs and Their Converses in Tournaments and New Digraph Polynomials
Coloring edges of embedded graphs
Ramsey numbers of large books
Steiner type problems for digraphs that are locally semicomplete or extended semicomplete
On the toroidal thickness of graphs
On linear vertex-arboricity of complementary graphs
Dominating induced matchings in graphs containing no long claw
From the Coxeter Graph to the Klein Graph
Subgraphs and well-quasi-ordering
Local and mean k -Ramsey numbers for complete graphs
Extremal graphs for the k-flower
Tutte's 5-flow conjecture for the projective plane
Spanning triangulations in graphs
Nearly acyclic graphs are reconstructible
Non-Hamiltonian Cycles in Tournaments
In praise of paul erdös on his seventieth
Path covers of weighted graphs
The λ-complete multigraphs
Flexibility of planar graphs of girth at least six
Coloring all directed paths in a symmetric tree, with an application to optical networks
Independence number, connectivity, and r-factors
On antimagic directed graphs
Interval bigraphs and circular arc graphs
A Combined Logarithmic Bound on the Chromatic Index of Multigraphs
Contractions and hamiltonian line graphs
Generating even triangulations of the projective plane
Edge clique cover of claw-free graphs
An improvement on the maximum number of k?dominating independent sets
Cycles and paths in semicomplete multipartite digraphs, theorems, and algorithms: a survey
Toughness and longest cycles in 2-connected planar graphs
Naji's characterization of circle graphs
Totally symmetric colored graphs
Augmenting the Edge-Connectivity of a Hypergraph by Adding a Multipartite Graph
A density bound for triangle-free 4-critical graphs
Regular Graphs, Eigenvalues and Regular Factors
Hamilton connectivity of line graphs and claw-free graphs
Induced odd cycle packing number, independent sets, and chromatic number
Survey of results on the maximum genus of a graph
Hall's theorem for hypergraphs
The extremal function for K 9 = minors
Lower Bounds on the Size of Maximum Independent Sets and Matchings in Hypergraphs of Rank Three
The average order of a connected induced subgraph of a graph and union-intersection systems
Clique-coloring some classes of odd-hole-free graphs
Restricted unimodular chordal graphs
A precolouring extension of Vizing's theorem
The minimum number of Hamilton cycles in a Hamiltonian threshold graph of a prescribed order
Cycle-Saturated Graphs with Minimum Number of Edges
Radius, girth and minimum degree
Minimum Degree and Dominating Paths
On minimal strong blocks
Shifting paths to avoidable ones
Atoll decompositions of graphs
Lower bounds and upper bounds for chromatic polynomials
Factorization of regular multigraphs into regular graphs
Lower bounds on size and independence in K 4 -free graphs
Toward Cereceda's conjecture for planar graphs
Basilica: New canonical decomposition in matching theory
On the number of maximal independent sets: From Moon-Moser to Hujter-Tuza
Star coloring planar graphs from small lists
A ½-transitive graph of valency 4 with a nonsolvable group of automorphisms
On minimal 5-chromatic triangle-free graphs
Ramsey numbers of the quadrilateral versus books
Ramsey theory for graph connectivity
Guest Editors' Introduction: Advances in Rapid Prototyping of Digital Systems
From the Editor in Chief: Twenty years!
IDDQ Testing: Issues Present and Future
Celebrating Three Decades of IEEE/ACM International Symposium on Low Power Electronics and Design
Interview With Yao-Wen Chang
Resistance Characterization for Weak Open Defects
Built-in self-test of a CMOS ALU
Will Chips of the Future Learn How to Feel Pain and Cure Themselves?
Why projects are late
Guest Editors' Introduction: Benchmarking for Design and Test
Data Reorganization and Prefetching of Pointer-Based Data Structures
SynFull-RTL: Evaluation Methodology for RTL NoC Designs
Guest Editors' Introduction: Design and Management of Mobile Platforms: From Smartphones to Wearable Devices
CATNAP-Sim: A Comprehensive Exploration and a Nonvolatile Processor Simulator for Energy Harvesting Systems
A Fully Automated and Configurable Cost-Aware Framework for Adaptive Functional Diagnosis
Deep-Submicron Noise
Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure
Guest Editor's Introduction: The Reuse of Complex Architectures
Medical Cyber-Physical Systems: The Early Years
DATE 2009 Workshop on 3D Integration
From the EIC: Smart and Autonomous Systems
Changing times in the RF world
Defect Oriented Testing for Analog/Mixed-Signal Designs
Guest Editors' Introduction: Stochastic Computing for Neuromorphic Applications
Testing NASA's 3D-Stack MCM Space Flight Computer
Soft Error Mitigation Using Transmission Gate With Varying Gate and Body Bias
In-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking
The Third Millennium's Test Dilemma
A Cautionary Tale About Detecting Malware Using Hardware Performance Counters and Machine Learning
Developing Great Products for the Immersive Computing Era
A Data-Based Detection Method Against False Data Injection Attacks
System-on-a-Chip Cosimulation and Compilation
A Methodology for Synthesis of Data Path Circuitse
A Novel Transition Fault ATPG That Reduces Yield Loss
Guest Editors' Introduction: Circuits and Systems for VLSI IoT Devices
Long-Term Thermal Overstressing of Computers
Optical Contactless Probing: An All-Silicon, Fully Optical Approach
From the EIC: Special Issue on Image Processing, Correspondsing Hardware Architectures, and EDA Tools
How Secure Are Printed Circuit Boards Against Trojan Attacks?
Scalable Spin-Transfer Torque RAM Technology for Normally-Off Computing
Test Technology Tc Newsletter
IC Design Capability Conversion from Mainframe to Workstation Environment
A Platform to Analyze DDR3 DRAM's Power and Retention Time
DFT for Delay Fault Testing of High-Performance Digital Circuits
Throughput advantages of asynchronous prober control
The Last Byte: The Internet of People
Exploiting Multiple Mahalanobis Distance Metrics to Screen Outliers From Analog Product Manufacturing Test Responses
Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms
Managing Security in FPGA-Based Embedded Systems
A Highly Fault-Efficient SAT-Based ATPG Flow
Applying Testability Analysis for Integrated Diagnostics
A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security
EDLAB: A Benchmark for Edge Deep Learning Accelerators
Test Technology TC Newsletter
Modeling and Analysis of Parametric Yield under Power and Performance Constraints
Modeling Low-k Dielectric Breakdown to Determine Lifetime Requirements
New Products Test
Recap of the 2016 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED 2016)
Making the Best of Those Extra Transistors
Challenges and Solutions for Late- and Post-Silicon Design
Designing circuits with partial scan
Conference Report from the 2019 International Symposium on Low Power Electronics and Design (ISLPED)
Cyber-Physplical Systems for Medical Apications
MIND: An inside Look at an Expert System for Electronic Diagnosis
Implementation of a Self-Timed Segmented Bus
Mixed-Signal Test Bus, Embedded Core Test Efforts Advance
Efficient Global Optimization of Analog Circuits Using Predictive Response Surface Models on Discretized Design Space
Context-Aware Intelligence in Resource-Constrained IoT Nodes: Opportunities and Challenges
The Impact of Multiple Failure Modes on Estimating Product Field Reliability
Analysis and Optimization of Power Grids
Automatically Assessing MPEG Coding Fidelity
A Quality-Driven Design Approach for NoCs
Guest Editors' Introduction: Confronting the Hardware Trustworthiness Problem
Using GPUs to Accelerate CAD Algorithms
A Procedure for Alternate Test Feature Design and Selection
A Two-Input, One-Output Bit-Scalable Architecture for Fuzzy Processors
Driving the $5 Billion Innovation Engine at Intel: An Interview with Patrick P. Gelsinger, Digital Enterprise Group Senior Vice President and General Manager, Intel
Guest Editor's Introduction: Microprocessor Testing Today
Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD)
Hardware Accelerators for Digital Signature Algorithms Dilithium and FALCON
Analyzing and Diagnosing Interconnect Faults in Bus-Structured Systems
Recent Technology Advances of Emerging Memories
Training Data Sets: The Source of Our Woes?
Design Automation Technical Committee Newsletter
Design-for-Testability of On-Chip Control in mVLSI Biochips
Single-Event Coupling Soft Errors in Nanoscale CMOS Circuits
The Last Byte: I Have Met the IoT Security Enemy and He Is Us
Secure and Resilient Industrial Control Systems
Guest Editors' Introduction: Low-Power VLSI Design
New Products Design
An Analysis of Industrial SRAM Test Results - A Comprehensive Study on Effectiveness and Classification of March Test Algorithms
Autonomous Systems Design: Charting a New Discipline
A Novel Graph-Coloring-Based Solution for Low-Power Scan Shift
DAC 97 Panel: Next-Generation HDLs
Power-Driven Challenges in Nanometer Design
Timing Accuracy in Modern ATE
Standards and Collaboration Perspectives: Yesterday, Today, and Tomorrow [Perspectives]
Advances in Design and Test of Monolithic 3-D ICs
Computer-Aided-Design Research at the GE Microelectronics Center
Standards: The P1685 IP-XACT IP Metadata Standard
Predicting the future of information technology and society [The Road Ahead]
Alpha 21164 Testability Strategy
Guest Editors' Introduction: Exploring Synergies for Design Verification
Learning Your Lock: Exploiting Structural Vulnerabilities in Logic Locking
A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors
Accelerating the Pace of R&D in Asia
Machine Learning and Algorithms: Let Us Team Up for EDA
Guest Editors' Introduction: Promises and Challenges of Novel Interconnect Technologies
TTTC 10th Anniversary
LORES-2: A Logic Reorganization System
Seamless Hardware-Software Integration in Reconfigurable Computing Systems
Built-In Self-Test/Repair Methodology for Multiband RF-Interconnected TSV 3D Integration
Guest Editors' Introduction: The Evolution of RFIC Design and Test
Circuit-Level Considerations for Mixed-Signal Programmable Components
Call for Articles
Dynamic Specification Testing and Diagnosis of High-Precision Sigma-Delta ADCs
DAC Highlights
A textbook with two target audiences
TinyML - From Efficient Edge Inference to On-Device Intelligence
Statistical Fault Analysis
Adaptive and Resilient Circuits for Dynamic Variation Tolerance
Codec Testing Using Synchronized Analog And Digital Signals
Testing Real-Time Systems With Runtime Enforcement
A D&T Roundtable: System-on-Chip Specification and Modeling Using C++: Challenges and Opportunities
Cost-Driven Ranking of Memory Elements for Partial Intrusion
An Efficient VLSI Switch-Box Router
Guest Editors' Introduction: Progress in Test Compression
Fully Microstrip Three-Port Circuit Bandpass NGD Design and Test
Panel Summaries
Implementing a Built-In Self-Test PLA Design
This Stuff Is Great - Am I Right?
Fault-Secure Parity Prediction Booth Multipliers
Economic Analysis of the HOY Wireless Test Methodology
High-Accuracy Flush-and-Scan Software Diagnostic
Clock and Power Gating with Timing Closure
Adding value to design and test through education: What are the challenges?
Guest Editorial: Special Issue on Self-Aware Systems on Chip
Time-Bomb HLS Trojan for Performance Degradation Payload
On-Chip Jitter Learning for PLL
DATC Newsletter
Standards, Interoperability, and Innovation in a Disaggregated IC Industry
Concurrent checking for logic [review of "New Methods of Concurrent Checking (Goessel, M., et al; 2008)]
PROUD: a sea-of-gates placement algorithm
A Digital-Microfluidic Approach to Chip Cooling
An Automatic Netlist-to-Schematic Generator
A D&T Roundtable
Guest Editor's Introduction: ITC Examines How Test Helps the Fittest Survive
Soft and Hard Error-Correction Techniques in STT-MRAM
Recursive TMR: Scaling Fault Tolerance in the Nanoscale Era
A D&T Roundtable: Test Resource Partitioning
Hybrid Verification of Protocol Bridges
Benchmarking Engineering Workstations
ISLPED 2021: The 25th Anniversary!
A Many-Ported and Shared Memory Architecture for High-Performance ADAS SoCs
PowerPC 603, A Microprocessor for Portable Computers
Modeling the Unmodelable: Algorithmic Fault Diagnosis
Leveraging Generative AI for Rapid Design and Verification of a Vector Processor SoC
D&T Elevated to Bimonthly
Test at Gbps: Megaproblem or micromanagement?
Microprocessor Architecture Design with ATLAS
Reliability Challenges and System Performance at the Architecture Level
Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research
Aging and Cost Optimal Residential Charging for Plug-In EVs
We need more standards like IEEE 1500
The Olympus Synthesis System
CASS Brings Publishing to Its DAC Partnership
Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC-TSI)
ACID: Automatic Sort-Map Classification for Interactive Process Diagnosis
Versatile Transition-Time Monitoring for Interconnects via Distributed TDC
New test paradigms for yield and manufacturability
Autonomous Design Space Exploration of Computing Systems for Sustainability: Opportunities and Challenges
Generating Tests for Delay Faults in Nonscan Circuits
Combining Negative Binomial and Weibull Distributions for Yield and Reliability Prediction
An Introduction to Switch-Level Modeling
Boundary Scan Test Standards
Quo Vadis Test? The Past, the Present, and the Future: No Longer a Necessary Evil
Trends in Silicon-On-Silicon Multichip Modules
Building an Open-Source DNA Assembler Device
TTTC recognizes test visionary's lifetime contribution
A D&T Roundtable: Test Benchmarking
EIC Message: The Neglected Community
Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream
Guest Editors' Introduction: Big Innovations in Small Packages
Hardware Accelerators in Computational Biology: Application, Potential, and Challenges
Test Development for Second-Generation ColdFire Microprocessors
Introduction to High-Level Synthesis
P1532, WAVES, and a New Initiative
For Safety's Sake: We Need a New Hardware-Software Contract!
Physical Techniques for Chip-Backside IC Debug in Nanotechnologies
Executing IJTAG: Are Vectors Enough?
Developing Parallel EDA Tools [The Last Byte]
Simulation Model to Predict BER Based on S-Parameters of High-Speed Interconnects
Silicon Lifecycle Management (SLM): Requirements, Trends, and Opportunities
Recap of the 61st ACM/IEEE Design Automation Conference (DAC61): The "Chips to Systems Conference"
Report on DATE 2018 in Dresden, Germany
Achieving IDDQ/ISSQ Production Testing with QuiC-Mon
Self-Testing the Motorola MC6804P2
Upgrade/Downgrade: Efficient and Secure Legacy Electronic System Replacement
Area-Efficient LFSR-Based Stochastic Number Generators With Minimum Correlation
Future Engineering Curricula: Balancing Domain Competence with CPS Readiness
A Built-In Parametric Timing Measurement Unit
Design Space Exploration of Parallel Embedded Architectures for Native Clifford Algebra Operations
Chemical and Biological Applications of Digital-Microfluidic Devices
Analog Circuit Fault Diagnosis Based on Sensitivity Computation and Functional Testing
Executing Data Integration Effectively and Efficiently Near the Memory
Robust Methods for Deep-Learning Training
Modeling a Verification Test System for Mixed-Signal Circuits
IEEE Design & Test of Computers 1996 Annual Index, Volume 13
A Look at Asynchronous Design and Photonic Network-on-a-Chip (PNoC)
EOC: Electronic Building Blocks for Embedded Systems
Infrastructure IP design for repair in nanometer technologies
Guest Editors' Introduction: SBCCI 2018
Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems
Special Issue on Postquantum Cryptography for Internet of Things
Automotive Functional Safety Assurance by POST with Sequential Observation
My Friendly Orange Glow
Survey of Scan Chain Diagnosis
Guest Editors' Introduction: Special Issue on Time-Critical Systems Design Part II
The 2023 Networks-on-Chip (NOCS) Symposium
Flexibility and Programmability
Guest Editors' Introduction: Special Issue on Smart and Autonomous Systems for Sustainability
Thermal Modeling and Validation of a Real-World Mobile AP
Fast Solvers for Molecular Science and Engineering
Instruction Scheduler Generation for Retargetable Compilation
The Impact of Ferroelectric FETs on Digital and Analog Circuits and Architectures
A Backlight Power Management Framework for Battery-Operated Multimedia Systems
Guest Editors' Introduction: Process Variation and Stochastic Design and Test
A Generic Virtual Bus for Hardware Simulator Composition
Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era
The 28th IEEE European Test Symposium
A Design Flow for Micromachined Electromechanical Systems
Looking into the Crystal Ball: From Transistors to the Smart Earth
A D&T Special Report: Defining ATLAS 2000
Yield Learning Through Physically Aware Diagnosis of IC-Failure Populations
All about getting it
The Challenges of Self-Test
Scan-Based Speed-Path Debug for a Microprocessor
Speeding Up Physical Synthesis with Transactional Timing Analysis
Comparing System-Level Power Management Policies
Guest Editor's Introduction: Hardware-Software Codesign
A built-in test module for fault isolation
The Memory Shuffle
An Optimized Test During Burn-In for Automotive SoC
Training Binarized Neural Networks Using Ternary Multipliers
CEDA Currents
Improving Analog and RF Device Yield through Performance Calibration
Conceptual Prototyping of Scalable Embedded DSP Systems
Tackling variability and reliability challenges
Coordinated Self-Tuning Thermal Management Controller for Mobile Devices
Using CAD Tools in the Design of CRISP
1995 Asian Test Symposium carves a niche
Heat Dissipation Capability of a Package-on-Package Embedded Wafer-Level Package
Test research in Japan
SMART and FAST: Test Generation for VLSI Scan-Design Circuits
Discovering CAN Specification Using On-Board Diagnostics
Bad Design Inside of You
Who Cares about System Verification?
Off-Chip Memory Encryption and Integrity Protection Based on AES-GCM in Embedded Systems
Guest Editorial: ITC 20th Anniversary