yusuke1997/dblp-id-title huggingface dataset:
Open-loop power-stage transfer functions relevant to current-mode control of boost PWM converter operating in CCM
Optimized waveform relaxation methods for RC type circuits
A Novel Architecture for Elementary-Check-Node Processing in Nonbinary LDPC Decoders
Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs
Direct recursive structures for computing radix-r two-dimensional DCT/IDCT/DST/IDST
An Interface Circuit With Wide Dynamic Range for Differential Capacitive Sensing Applications
Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking - Part II: Non-Constant Input
One-tap wideband I/Q compensation for zero-IF filters
Modelling and Verification of Nonlinear Electromechanical Coupling in Micro-Scale Kinetic Electromagnetic Energy Harvesters
Design of Low-Voltage Integrated Step-up Oscillators with Microtransformers for Energy Harvesting Applications
Inductorless Wideband CMOS Low-Noise Amplifiers Using Noise-Canceling Technique
Capacitive Energy Conversion With Circuits Implementing a Rectangular Charge-Voltage Cycle Part 2: Electromechanical and Nonlinear Analysis
On Loss Mechanisms of Complex Switched Capacitor Converters
A burst-mode word-serial address-event link-I: transmitter design
Reducing Energy of Approximate Feature Extraction in Heterogeneous Architectures for Sensor Inference via Energy-Aware Genetic Programming
High-Efficiency Wireless Power Transfer for Biomedical Implants by Optimal Resonant Load Transformation
Experimental Validation of SPICE Modeling Diffraction Effects in a Pulse-Echo Ultrasonic System
An improved pipelined MSB-first add-compare select unit structure for Viterbi decoders
EEG-based drowsiness estimation for safety driving using independent component analysis
Design and Implementation of Grid Multiwing Butterfly Chaotic Attractors From a Piecewise Lorenz System
Improved First-Order Time-Delay Tanlock Loop Architectures
Frequency Synthesizer With Dual Loop Frequency and Gain Calibration
Generalized Semi-Analytical Design Methodology of Class-E Outphasing Power Amplifier
Tree-Structured DEM DACs with Arbitrary Numbers of Levels
Trajectory-based optimal linearization for nonlinear autonomous vector fields
Wideband Digital Predistortion Using Spectral Extrapolation of Band-Limited Feedback Signal
Watermark detection for noisy interpolated images
A New Variable Forgetting Factor-Based Bias-Compensated RLS Algorithm for Identification of FIR Systems With Input Noise and Its Hardware Implementation
Chosen plaintext attack on a cryptosystem with discretized skew tent map
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems - ISICAS 2020
Comparator Metastability in the Presence of Noise
Time Domain Processing Techniques Using Ring Oscillator-Based Filter Structures
Double-High-Pass-Filter-Based Electrical-Recording Front-Ends and Fluorescence-Recording Front-Ends for Monitoring Multimodal Neural Activity
Bandwidth Enhancement of Doherty Power Amplifier Using Modified Load Modulation Network
Phase Reconfigurable Microwave Power Divider
A 53 dB Ω~7-GHz Inductorless Transimpedance Amplifier and a 1-THz+ GBP Limiting Amplifier in 0.13-µm CMOS
A 4×4 MIMO-OFDM Baseband Receiver With 160 MHz Bandwidth for Indoor Gigabit Wireless Communications
All-MOS ASK Demodulator for Low-Frequency Applications
PPV-Based Modeling and Event-Driven Simulation of Injection-Locked Oscillators in SystemVerilog
Analyzing Oscillations for an N-node Recurrent Neural Networks Model With Time Delays and General Activation Functions
Using CAD Tool for Substrate Parasitic Modeling in Smart Power Technology
Analytical Synthesis of the Digitally Programmable Voltage-Mode OTA-C Universal Biquad
Composite Behavior of Multiple Memristor Circuits
Ultra-Sub-Threshold Operation of Always-On Digital Circuits for IoT Applications by Use of Schmitt Trigger Gates
Electrothermal Analysis With Nonconvective Boundary Conditions
Variable Fractional Delay FIR Filter Design with a Bicriteria and Coefficient Relationship
Semi-blind identification of ARMA systems using a dynamic-based approach
An Autofocus Sensor With Global Shutter Using Offset-Free Frame Memory
Observability of Multi-Agent Systems With Switching Topology
A Cost-Effective Preamble-Assisted Engine With Skew Calibrator for Frequency-Dependent I/Q Imbalance in 4, ×, 4 MIMO-OFDM Modem
Optimal PWM Control of Switched-Capacitor DC-DC Power Converters via Model Transformation and Enhancing Control Techniques
800-nA Process-and-Voltage-Invariant 106-dB PSRR PTAT Current Reference
Evolutionary design of 2-dimensional recursive filters via the computer language GENETICA
Undershoot-Less Open-Loop Soft-Start Strategy for Digital-Controlled Power Converters Based on an Error-ADC and Initial Duty Ratio Estimator
Real-Time Independent Vector Analysis for Convolutive Blind Source Separation
Analysis and architecture design of variable block-size motion estimation for H.264/AVC
How to Make Analog-to-Information Converters Work in Dynamic Spectrum Environments With Changing Sparsity Conditions
A Class of SIC Circuits: Theory and Application in BIST Design
Cluster Synchronization of Linearly Coupled Complex Networks Under Pinning Control
Improved Algorithms and Implementations for Integer to τ NAF Conversion for Koblitz Curves
Robust controller for a full-bridge rectifier using the IDA approach and GSSA modeling
A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding
Timing Reliability Improvement of Master-Slave Flip-Flops in the Presence of Aging Effects
Synchronizing a Weighted and Weakly-Connected Kuramoto-Oscillator Digraph With a Pacemaker
H ∞ Filtering for Neutral Systems With Mixed Delays and Multiplicative Noises
Transformer-Coupled Power Amplifier Stability and Power Back-Off Analysis
Reconstruction of band-limited periodic nonuniformly sampled signals through multirate filter banks
A Digitally Programmable CMOS Feedback ASIC for Highly Stable MEMS-Referenced Oscillators
General Characterization Method and a Fast Load-Charge-Preserving Switching Procedure for the Stepwise Adiabatic Circuits
A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC
Nonlinear Analysis of PLL Damping Characteristics in Weak-Grid-Tied Inverters
A Low-Power Hybrid Adaptive CORDIC
Two CMOS Current Feedback Operational Amplifiers
Complex Blind Source Extraction From Noisy Mixtures Using Second-Order Statistics
Frequency-domain characterization of sliding mode control of an inverter used in DSTATCOM application
A Unified Solution for Super-Regenerative Systems With Application to Correlator-Based UWB Transceivers
Quasi-Adiabatic Logic Arrays for Silicon and Beyond-Silicon Energy-Efficient ICs
Canceling the ISI Due to Finite S/H Bandwidth in a Circular Buffer Forward Equalizer
A Noise-Immune High-Speed Readout Circuit for In-Cell Touch Screen Panels
Dithering Loopback-Based Prediction Technique for Mixed-Signal Embedded System Specifications
Generalized Series-Parallel RLC Synthesis Without Minimization for Biquadratic Impedances
Modeling and Design of Multilevel Bang-Bang CDRs in the Presence of ISI and Noise
Parameter Identification of Chaotic and Hyper-Chaotic Systems Using Synchronization-Based Parameter Observer
A 0.34 mm 2 1 Gb/s Non-Coherent UWB Receiver Architecture With Pulse Enhancement and Double PLL Clock/Data Packet Recovery
Sampled-Data Modeling for PCM and ZVS Controlled Critical Conduction Mode (CrCM) Active Clamp Flyback (ACF) Converter at Variable Switching Frequency
A Standalone FPGA-Based Miner for Lyra2REv2 Cryptocurrencies
An ultralow-power switched opamp-based 10-B integrated ADC for implantable biomedical applications
Alias-Component Matrices of Multirate Systems
Approximating Noncausal IIR Digital Filters Having Arbitrary Poles, Including New Hilbert Transformer Designs, Via Forward/Backward Block Recursion
A 0.0071-mm 2 10.8ps pp -Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis
On the Design of the Triple-Resonance Interstage Network
A K-Band UWB Low-Noise CMOS Mixer With Bleeding Path G m -Boosting Technique
On Engineering Education, Superposition, and Commutativity
A Numerical Methodology for the Analysis of Switched-Capacitor Filters Taking Into Account Non-Ideal Effects of Switches and Amplifiers
A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS
New Results and Techniques for Computation of Stored Energy in Lossless/All-Pass Systems
High Step-Up Gain DC-DC Converter With Switched Capacitor and Regenerative Boost Configuration for Solar PV Applications
A novel CMOS operational transconductance amplifier based on a mobility compensation technique
Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters
Analog Circuits to Implement Repetitive Controllers for Tracking and Disturbance Rejection of Periodic Signals
Design of Low-Power Direct-Conversion RF Front-End With a Double Balanced Current-Driven Subharmonic Mixer in 0.13 µm CMOS
Coupling Strength Allocation for Synchronization in Complex Networks Using Spectral Graph Theory
Digitally Assisted Feedforward Compensation of Cartesian-Feedback Power-Amplifier Systems
A High-Throughput Radix-16 FFT Processor With Parallel and Normal Input/Output Ordering for IEEE 802.15.3c Systems
New Sufficient Conditions for Global Robust Stability of Delayed Neural Networks
Optimization of MOS amplifier performance through channel length and inversion level selection
Fully Synthesizable Low-Area Digital-to-Analog Converter With Graceful Degradation and Dynamic Power-Resolution Scaling
A New Decomposition Algorithm for Threshold Synthesis and Generalization of Boolean Functions
Estimating Thermal Noise in $\Delta\Sigma$ ADCs Composed of Switched Capacitor Integrators
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique
An Asynchronous Delta-Modulator Based A/D Converter for an Electronic System Prototyping Platform
High-Efficiency Fully CMOS VCO Rectifier for Microwatt Resonant Wireless Power Transfer
CNN-Based Hybrid-Order Texture Segregation as Early Vision Processing and Its Implementation on CNN-UM
A Fully Digital Time-Domain Smart Temperature Sensor Realized With 140 FPGA Logic Elements
Ultralow Power Injection-Locked GFSK Receiver for Short-Range Wireless Systems
Fast detection of instability in sigma-delta modulators based on unstable embedded limit cycles
Guest Editorial - ISCAS 2007
A New Clock Phase Calibration Method in High-Speed and High-Resolution DACs
Effect of Mismatch on the Reliability of ON/OFF-Programmable CNNs
A 0.12-0.4 V, Versatile 3-Transistor CMOS Voltage Reference for Ultra-Low Power Systems
Digital Background Calibration Techniques for Pipelined ADC Based on Comparator Dithering
Design and Performance Analysis of a Differentially Spatial Modulated Chaos Shift Keying Modulation System
Fully Integrated, 100-mV Minimum Input Voltage Converter With Gate-Boosted Charge Pump Kick-Started by LC Oscillator for Energy Harvesting
Comments on "A Novel Compression and Encryption Scheme Using Variable Model Arithmetic Coding and Coupled Chaotic System"
Modeling nonlinear wave digital elements using the Lambert function
Stability Analysis and Control of Nonlinear Phenomena in Boost Converters Using Model-Based Takagi-Sugeno Fuzzy Approach
Lyapunov Conditions for Stability of Stochastic Impulsive Switched Systems
Random Sampling With Iterative Recovery for Millimeter-Wave Imaging Systems
A Programmable 34 nW/Channel Sub-Threshold Signal Band Power Extractor on a Body Sensor Node SoC
A Highly Synthesizable 0.5-to-1.0-V Digital Low-Dropout Regulator With Adaptive Clocking and Incremental Regulation Scheme
Linear Analysis of the Vectorial Network Model
Nonlinear State Feedback Design With a Guaranteed Stability Domain for Locally Stabilizable Unstable Quadratic Systems
Digital Multiplierless Realization of Two-Coupled Biological Hindmarsh-Rose Neuron Model
High Performance Control Design for Dynamic Voltage Scaling Devices
Distortion in single-, two- and three-stage amplifiers
Synthesizable Memory Arrays Based on Logic Gates for Subthreshold Operation in IoT
Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology
A computationally efficient nonuniform FIR digital filter bank for hearing aids
Sliding-Mode Control of Memristive Chua's Systems via the Event-Based Method
Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter
Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic
A 0.0054-mm 2 Frequency-to-Current Conversion-Based Fractional Frequency Synthesizer in 32 nm Utilizing Deep Trench Capacitor
Event-Triggering Containment Control for a Class of Multi-Agent Networks With Fixed and Switching Topologies
Reconfigurable RF Dispersive Delay Circuits by Stepped Impedance Shunt Stubs
A 0.36 pJ/bit, 0.025 mm 2 , 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology
Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies
An Iterative Detection and Decoding Receiver for LDPC-Coded MIMO Systems
Mechanical Contact-Less Computational Speed Sensing Approach of PWM Operated PMDC Brushed Motor: A Slotting-Effect and Commutation Phenomenon Incorporated Semi-Analytical Dynamic Model-Based Approach
A Study on Pre-Inverse Adaptive System Based on Estimation of Minimum-Phase and Allpass Transfer Function
Free Binary Decision Diagram-Based Synthesis of Compact Crossbars for In-Memory Computing
Correction to "Iterative Least Squares Design of DC-Leakage Free Paraunitary Cosine Modulated Filter Banks"
Perfect recovery and sensitivity analysis of time encoded bandlimited signals
Analysis of Non-Uniform Polar Quantisers in a Sigma Delta Transmitter Architecture
Monotonic Wide-Range Digitally Controlled Oscillator Compensated for Supply Voltage Variation
A Ripple-Based Design-Oriented Approach for Predicting Fast-Scale Instability in DC-DC Switching Power Supplies
Maximizing Power-System Loadability in the Presence of Multiple Binding Complementarity Constraints
Analog Circuit Implementation of a Variable Universe Adaptive Fuzzy Logic Controller
A Comparative Analysis of Phase-Domain ADC and Amplitude-Domain IQ ADC
Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers
On the ultimate limits of chaos-based asynchronous DS-CDMA-I: basic definitions and results
Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current
Markov-jump-system-based secure chaotic communication
Energy-Efficient Anti-Flocking Control for Mobile Sensor Networks on Uneven Terrains
An FPGA-Based Transient Error Simulator for Resilient Circuit and System Design and Evaluation
Analysis and Modeling of a Gain-Boosted N-Path Switched-Capacitor Bandpass Filter
A Memristor-Based Spiking Neural Network With High Scalability and Learning Efficiency
Iterative Graph-Based Filtering for Image Abstraction and Stylization
A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration
Multimode G m - C Channel Selection Filter for Mobile Applications in 1-V Supply Voltage
A Multi-Folded MCML for Ultra-Low-Voltage High-Performance in Deeply Scaled CMOS
Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems
Analytical Approach for Numerical Accuracy Estimation of Fixed-Point Systems Based on Smooth Operations
All-Digital Background Calibration of a Successive Approximation ADC Using the "Split ADC" Architecture
Comparative Studies of Common Fix-Frequency Controls for Reference Tracking and Enhancement by End-Point Prediction
7.9 pJ/Step Energy-Efficient Multi-Slope 13-bit Capacitance-to-Digital Converter
Analysis and Design of Two-Port N-Path Bandpass Filters With Embedded Phase Shifting
A 0.36-V 5-MS/s Time-Mode Flash ADC With Dickson-Charge-Pump-Based Comparators in 28-nm CMOS
Reduced-complexity transform-domain adaptive algorithm with selective coefficient update
Exact and numerically stable closed-form expressions for potential coefficients of rectangular conductors
A 50-Gb/s 10-mW Analog Equalizer Using Transformer Feedback Technique in 65-nm CMOS Technology
An LTV Analysis of the Frequency Translational Noise-Cancelling Receiver
Theory of Injection-Locked Oscillator Phase Noise
Push-Pull Class-E M Power Amplifier for Low Harmonic-Contents and High Output-Power Applications
Novel Radiation Hardening Read/Write Circuits Using Feedback Connections for Spin-Orbit Torque Magnetic Random Access Memory
Effects of Random Delay Errors in Continuous-Time Semi-Digital Transversal Filters
Design and Implementation of a Baseband WCDMA Dual-Antenna Mobile Terminal
Rational Polynomial Chaos Expansions for the Stochastic Macromodeling of Network Responses
Design of Fractional Delay Filter Using Hermite Interpolation Method
Analysis of error in the fixed-point implementation of two-dimensional discrete wavelet transforms
Optimal Control and Stabilization for Networked Control Systems With Packet Dropout and Input Delay
Delay-Dependent H infty Filtering of Piecewise-Linear Systems With Time-Varying Delays
Convergent Dynamics of Nonreciprocal Differential Variational Inequalities Modeling Neural Networks
BIRA With Optimal Repair Rate Using Fault-Free Memory Region for Area Reduction
A 12-Bit Time-Interleaved 400-MS/s Pipelined ADC With Split-ADC Digital Background Calibration in 4, 000 Conversions/Channel
Event-Based $H_{\infty}$ Fault Detection for Buck Converter With Multiplicative Noises Over Network
Computation of the exact cramer-rao lower bound for 2-D ARMA parameter Estimation-I: the quarter-plane case
Modelling and Control for Bounded Synchronization in Multi-Terminal VSC-HVDC Transmission Networks
A Novel 0.8-V 79-nW CMOS-Only Voltage Reference With -55-dB PSRR @ 100 Hz
A Heterogeneous Multicore System on Chip for Energy Efficient Brain Inspired Computing
Global Robust Stability and Synchronization of Networks With Lorenz-Type Nodes
Very small FPGA application-specific instruction processor for AES
Analytical Synthesis of Current-Mode High-Order Single-Ended-Input OTA and Equal-Capacitor Elliptic Filter Structures With the Minimum Number of Components
A Discrete-Time FFT Processor for Ultrawideband OFDM Wireless Transceivers: Architecture and Behavioral Modeling
An Analytical Approach for Quantifying Clock Jitter Effects in Continuous-Time Sigma-Delta Modulators
Sparse Undetectable Sensor Attacks Against Cyber-Physical Systems: A Subspace Approach
Frequency Limited Model Reduction Techniques for Discrete-Time Systems
Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS
A 10.7-MHz sixth-order SC ladder filter in 0.35-μm CMOS technology
Comprehensive Background Calibration of Time-Interleaved Analog-to-Digital Converters
A High-Speed Energy-Efficient Segmented Prequantize and Bypass DAC for SAR ADCs
A Majority-Based Imprecise Multiplier for Ultra-Efficient Approximate Image Multiplication
Integrated Reciprocal Conversion With Selective Direct Operation for Energy Harvesting Systems
Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits
CMOS-Based Phase Fluorometric Oxygen Sensor System
All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM
A UWB Impulse-Radio Timed-Array Radar With Time-Shifted Direct-Sampling Architecture in 0.18-µm CMOS
A Multi-Kernel Multi-Code Polar Decoder Architecture
Improved Global Robust Stability Criteria for Delayed Neural Networks
Toward a Circuit Theory of Communication
A 120 pJ/bit ΔΣ-Based 2.4-GHz Transmitter Using FIR-Embedded Digital Power Amplifier
Modular Structure of Compact Model for Memristive Devices
RX-Band Noise Reduction in All-Digital Transmitters With Configurable Spectral Shaping of Quantization and Mismatch Errors
First Order Mem-Circuits: Modeling, Nonlinear Oscillations and Bifurcations
Hairpin Resonators in Varactor-Tuned Microstrip Bandpass Filters
Leader Following of Nonlinear Agents With Switching Connective Network and Coupling Delay
Theoretical Foundations of Memristor Cellular Nonlinear Networks: A DRM 2 -Based Method to Design Memcomputers With Dynamic Memristors
A Deterministic Low-Complexity Approximate (Multiplier-Less) Technique for DCT Computation
Energy-Efficient Hardware Architecture of Self-Organizing Map for ECG Clustering in 65-nm CMOS
Exploring the Advantages of Single-Ended-Input CMOS Self-Biased Amplifiers
Expected Value and Variance of the Indirect Time-of-Flight Measurement With Dead Time Afflicted Single-Photon Avalanche Diodes
High Conversion Ratio DC-DC Converters With Reduced Switch Stress
An All-Digital On-Chip Peak-to-Peak Jitter Measurement Circuit With Automatic Resolution Calibration for High PVT-Variation Resilience
A Novel Generalized Hardware-Efficient Neuron Model Based on Asynchronous CA Dynamics and Its Biologically Plausible On-FPGA Learnings
Real-Time Low-Power FPGA Architecture for Stereo Vision
An 11 b 7 ps Resolution Two-Step Time-to-Digital Converter With 3-D Vernier Space
Towards Analog Memristive Controllers
An Ultra-Compact Low Power Self-Capacitive Touch Screen Readout IC Embedding Reconfigurable Noise Immunity and Current-Driven Capacitance Compensation
Adaptive Synchronization of a Class of Uncertain Complex Networks Against Network Deterioration
Area-Delay-Energy Efficient VLSI Architecture for Scalable In-Place Computation of FFT on Real Data
Hybrid Structures for Low-Complexity Variable Fractional-Delay FIR Filters
A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS
A 2.4-GHz Mid-Field CMOS Wireless Power Receiver Achieving 46% Maximum PCE and 163-mW Output Power
Adaptive EEG-Based Alertness Estimation System by Using ICA-Based Fuzzy Neural Networks
A Genetic Algorithm for the Estimation of Nonidealities in Continuous-Time Sigma-Delta Modulators
Robust Dichotomy Analysis and Synthesis With Application to an Extended Chua's Circuit
A 10-Bit 200-kS/s 1.76- $\mu$ W SAR ADC With Hybrid CAP-MOS DAC for Energy-Limited Applications
An Adaptive Pulse-Triggered Flip-Flop for a High-Speed and Voltage-Scalable Standard Cell Library
Design of a Tunable Anti-Aliasing Filter for Multistandard RF Subsampling GNSS Receivers
Analytical Solution of Circuits Employing Voltage- and Current-Excited Memristors
Page-Based Dynamic Partitioning Scheduling for LDPC Decoding in MLC NAND Flash Memory
Corrections to "A Universal Architecture for Designing Efficient Modulo 2 n+1 Multipliers"
Design and Fabrication of Flow-Based Edge Detection Memristor Crossbar Circuits 1
A Practical Implementation of a Floating Memristor-Less Meminductor Emulator
A Novel Universal Interface for Constructing Memory Elements for Circuit Applications
Galvanically Isolated DC-DC Converter Using a Single Isolation Transformer for Multi-Channel Communication
Petrel: Power and Timing Attack Resistant Elliptic Curve Scalar Multiplier Based on Programmable GF(p) Arithmetic Unit
Least-Squares and Minimax Design of Polynomial Impulse Response FIR Filters for Reconstruction of Two-Periodic Nonuniformly Sampled Signals
A Variable Step-Size Robust Saturation Algorithm Against Impulsive Noises
Design of Minimum-Phase Filters Using Optimization
On the Implementation of the Linearly Constrained Minimum Variance Beamformer
Code-width testing-based compact ADC BIST circuit
Investigation of Inverse Class-E Power Amplifier at Sub-Nominal Condition for Any Duty Ratio
A semi-digital delay-locked loop using an analog-based finite state machine
A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation
Lorentzian Based Adaptive Filters for Impulsive Noise Environments
Analog Decoder Performance Degradation Due to BJTs' Parasitic Elements
An Optimized Logarithmic Converter With Equal Distribution of Relative Errors
Bounded Selective Spanning With Extended Fast Enumeration for MIMO-OFDM Systems Detection
Theoretical Analysis of Highly Linear Tunable Filters Using Switched-Resistor Techniques
Comparison of the Frequency Compensation Techniques for CMOS Two-Stage Miller OTAs