yusuke1997/dblp-id-title huggingface dataset:
An MOS transistor model for analog circuit design
A 10-Gb/s eye-opening monitor IC for decision-guided adaptation of the frequency response of an optical receiver
A 0.5-μm CMOS T/R switch for 900-MHz wireless applications
An X-Band Radar Transceiver MMIC with Bandwidth Reduction in 0.13 µm SiGe Technology
A Power-and-Area Efficient 10 × 10 Gb/s Bootstrap Transceiver in 40 nm CMOS for Referenceless and Lane-Independent Operation
A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth
An elastic pipeline mechanism by self-timed circuits
Digitally-Controlled Polar Transmitter Using a Watt-Class Current-Mode Class-D CMOS Power Amplifier and Guanella Reverse Balun for Handset Applications
Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers
3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor
Minimization of the mechanical-stress-induced inaccuracy in bandgap voltage references
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration
Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits
A 29-Gb/mm 2 1-Tb 3-b/Cell 3-D Flash Memory With CMOS Direct Bonded Array (CBA) Technology
A Parallel Sliding-IF Receiver Front-End With Sub-2-dB Noise Figure for 5-6-GHz WLAN Carrier Aggregation
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator
Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology
A high-speed 850-nm optical receiver front-end in 0.18-μm CMOS
A 1-GS/s 6-8-b Cryo-CMOS SAR ADC for Quantum Computing
Silicon-Based Ultra-Wideband Beam-Forming
A 10-Gb/s Adaptive Parallel Receiver With Joint XTC and DFE Using Power Detection
KiloCore: A 32-nm 1000-Processor Computational Array
Design and Analysis of Enhanced Mixer-First Receivers Achieving 40-dB/decade RF Selectivity
A reconfigurable parallel signature analyzer for concurrent error correction in DRAM
A 6-Bit 1.6-GS/sLow-Power Wideband Flash ADC Converter in 0.13-µm CMOS Technology
Digital Approaches to ISI-Mitigation in High-Resolution Oversampled Multi-Level D/A Converters
A Bias-Flip Rectifier With Duty-Cycle-Based MPPT for Piezoelectric Energy Harvesting
digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture
A Deterministic Digital Background Calibration Technique for VCO-Based ADCs
A 0.38 THz Fully Integrated Transceiver Utilizing a Quadrature Push-Push Harmonic Circuitry in SiGe BiCMOS
An analog/digital interface for cellular telephony
A Fully Integrated Digital Low-Dropout Regulator Based on Event-Driven Explicit Time-Coding Architecture
50-GHz-bandwidth baseband amplifiers using GaAs-based HBTs
A 600-MS/s DAC With Over 87-dB SFDR and 77-dB Peak SNDR Enabled by Adaptive Cancellation of Static and Dynamic Mismatch Error
A 12-b 10-GS/s Interleaved Pipeline ADC in 28-nm CMOS Technology
Equivalent circuit modeling of static substrate thermal coupling using VCVS representation
A 1.17-Megapixel CMOS Image Sensor With 1.5 A/D Conversions per Digital CDS Pixel Readout and Four In-Pixel Gain Steps
AlInAs/GaInAs HBT IC technology
Totally self-checking CMOS circuit design for breaks and stuck-on faults
A CMOS continuous-time G m -C filter for PRML read channel applications at 150 Mb/s and beyond
A 450 fs 65-nm CMOS Millimeter-Wave Time-to-Digital Converter Using Statistical Element Selection for All-Digital PLLs
A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver
A direct-conversion receiver IC for WCDMA mobile systems
A 2 × 112 Gb/s/pin Single-Ended Crosstalk Cancellation Transceiver With 31-dB Loss Compensation in 28-nm CMOS
Symbolic pole/zero calculation using SANTAFE
8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices
A 1.8-GHz Near-Field Dielectric Plethysmography Heart-Rate Sensor With Time-Based Edge Sampling
A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier
An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET
A pW-Power Hz-Range Oscillator Operating With a 0.3-1.8-V Unregulated Supply
A CMOS readout amplifier for instrumentation applications
A Precision CMOS Amplifier Using Floating-Gate Transistors for Offset Cancellation
A 70-Mb/s variable-rate 1024-QAM cable receiver IC with integrated 10-b ADC and FEC decoder
A class-B output buffer for flat-panel-display column driver
0.56 V, -20 dBm RF-Powered, Multi-Node Wireless Body Area Network System-on-a-Chip With Harvesting-Efficiency Tracking Loop
A multicarrier GMSK modulator with on-chip D/A converter for base stations
A Fully-Integrated 77-GHz FMCW Radar Transceiver in 65-nm CMOS Technology
AC-and DC-powered subnanosecond 1-kbit Josephson cache memory design
A Single-Trim CMOS Bandgap Reference With a 3Sigma Inaccuracy of ± 0.15% From - 40°C to 125°C
A unified model for injection-locked frequency dividers
EM and substrate coupling in silicon RFICs
A Sub-mm 3 Ultrasonic Free-Floating Implant for Multi-Mote Neural Recording
Millimeter-wave CMOS design
A fully differential CMOS line driver for ISDN
SPIM: a pipelined 64*64-bit iterative multiplier
An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop
A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction
A single-chip CMOS APS camera with direct frame difference output
BiCMOS circuit technology for a high-speed SRAM
Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication
A 60-GHz 8-Way Phased-Array Front-End With T/R Switching and Calibration-Free Beamsteering in 28-nm CMOS
A 1-GS/s 11-b Time-Interleaved SAR ADC With Robust, Fast, and Accurate Autocorrelation-Based Background Timing-Skew Calibration
A design environment for high-throughput low-power dedicated signal processing systems
A CMOS low-noise and low-power charge sampling integrated circuit for capacitive detector/sensor interfaces
Power partition and emitter size optimization for bipolar ECL circuit
A monolithic power op amp
A detailed analysis of CMOS SRAM's with gate oxide short defects
Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications
A Harmonic-Mixing PLL Architecture for Millimeter-Wave Application
A 144-MHz Fully Integrated Resonant Regulating Rectifier With Hybrid Pulse Modulation for mm-Sized Implants
The Experimental Demonstration of a SASP-Based Full Software Radio Receiver
A CMOS voltage reference based on weighted ΔV GS for CMOS low-dropout linear regulators
A VLSI chip set for a multiprocessor workstation. I. An RISC microprocessor with coprocessor interface and support for symbolic processing
A 0.8-V BJT-Based Temperature Sensor With an Inaccuracy of ±0.4 °C (3σ) From -40 °C to 125 °C in 22-nm CMOS
Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz
Optimization-based transistor sizing
76- to 81-GHz CMOS Built-In Self-Test With 72-dB C/N and Less Than 1 ppm Frequency Tolerance for Multi-Channel Radar Applications
A 4-GHz Low-Power, Multi-User Approximate Zero-IF FM-UWB Transceiver for IoT
InAlAs/InGaAs HBT X-band double-balanced upconverter
Multiplexer/demultiplexer IC technology for 100 Gb/s fiber-optic transmission
An improved latching pulse design for dynamic sense amplifiers
High-Breakdown, High-f max Multiport Stacked-Transistor Topologies for the W-Band Power Amplifiers
A mixed-signal array processor with early vision applications
A Hybrid LED Driver With Improved Efficiency
Analysis and Design of a Power-Scalable Continuous-Time FIR Equalizer for 10 Gb/s to 25 Gb/s Multi-Mode Fiber EDC in 28 nm LP CMOS
Switched-current 3-bit CMOS 4.0-MHz wideband random signal generator
A GMSK modulator using a ΔΣ frequency discriminator-based synthesizer
A single-chip video ghost canceller
A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS
A 640×512 CMOS image sensor with ultrawide dynamic range floating-point pixel-level ADC
Multibit oversampled Sigma Delta A/D converters as front end for CD players
A CMOS image sensor with a simple fixed-pattern-noise-reduction technology and a hole accumulation diode
An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s
A 14-Gops programmable motion estimator for H.26X video coding
A Minimally Invasive 64-Channel Wireless μECoG Implant
An Inverse-Class-F CMOS Oscillator With Intrinsic-High-Q First Harmonic and Second Harmonic Resonances
Silicon bipolar laser driving IC for 5 Gb/s and 45-mA modulation current and its application in a demonstrator system
A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems
A Low-Jitter and Low-Spur Charge-Sampling PLL
Offset compensation in comparators with minimum input-referred supply noise
A burst-mode receiver for 1.25-Gb/s ethernet PON with AGC and internally created reset signal
A 16×16 nonvolatile programmable analog vector-matrix multiplier
A 64-Mb DRAM with meshed power line
A High-Linearity and Low-EMI Multilevel Class-D Amplifier
Voltage limiters for DRAMs with substrate-plate-electrode memory cells
A wide-range delay-locked loop with a fixed latency of one clock cycle
Low-voltage fully differential switched-current filters
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET
A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching
A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines
15-GHz fully integrated nMOS switches in a 0.13-μm CMOS process
A 0.12 mm 2 7.4 μ W Micropower Temperature Sensor With an Inaccuracy of ± 0.2°C (3 Sigma ) From - 30°C to 125°C
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC
A Rel-12 2G/3G/LTE-Advanced 2CC Transmitter
Erratum to "A 66 µW 86 ppm°C Fully-Integrated 6 MHz Wienbridge Oscillator With a 172 dB Phase Noise FOM" [Jul 09 1990-2001]
A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS
A 2.7-V 900-MHz CMOS LNA and mixer
A 2-GS/s 8-bit Non-Interleaved Time-Domain Flash ADC Based on Remainder Number System in 65-nm CMOS
An 833-MHz 1.5-W 18-Mb CMOS SRAM with 1.67 Gb/s/pin
A laser control chip combining a power regulator and a 622-Mbit/s modulator
A Low-Power CMOS SAW-Less Quad Band WCDMA/HSPA/HSPA+/1X/EGPRS Transmitter
Static noise margin variation for sub-threshold SRAM in 65-nm CMOS
A CMOS 6-b, 200 MSample/s, 3 V-supply A/D converter for a PRML read channel LSI
An over-110-GHz InP HEMT flip-chip distributed baseband amplifier with inverted microstrip line structure for optical transmission system
A 56-Gb/s PAM-4 VCSEL Transmitter With Piecewise Compensation Scheme in 40-nm CMOS
A high-precision VLSI winner-take-all circuit for self-organizing neural networks
A CMOS pulse-width modulator/pulse-amplitude modulator for four-quadrant analog multipliers
Comparison of current-switched logic gates for high-speed communications applications
A 78.2-dB Dynamic Range Shunt-Based Current Sensor for BLDC Motor Control With 2.75-μs Conversion Time and 0.4-mm² Active Area
A low-power high-PSRR current-mode microphone preamplifier
A 12-bit integrated analog front end for broadband wireline networks
An Ultrasound Imaging System With On-Chip Per-Voxel RX Beamfocusing for Real-Time Drone Applications
A 93.6-dB SNDR Fully Dynamic CT-DT Noise-Shaping SAR ADC With Closed-Loop Capacitively Coupled Two-Stage FIA
Parametric Mismatch Characterization for Mixed-Signal Technologies
Design of reliable VLSI circuits using simulation techniques
Broadband GaN MMIC Doherty Power Amplifier Using Continuous-Mode Combining for 5G Sub-6 GHz Applications
An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally Spaced Voltage Comparators
Navion: A 2-mW Fully Integrated Real-Time Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones
A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand"
A GHz MOS adaptive pipeline technique using MOS current-mode logic
High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA
A framework to evaluate technology and device design enhancements for MOS integrated circuits
A Low Phase Noise Oscillator Principled on Transformer-Coupled Hard Limiting
A Quadrature Digital Power Amplifier With Hybrid Doherty and Impedance Boosting for Complex Domain Power Back-Off Efficiency Enhancement
A 120-mm 2 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed
A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR
An RMS-DC converter based on the dynamic translinear principle
An Energy-Efficient Biomedical Signal Processing Platform
Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell
A 0.5-μ V rms 12-μ W Wirelessly Powered Patch-Type Healthcare Sensor for Wearable Body Sensor Network
A 0.18-µm CMOS Array Sensor for Integrated Time-Resolved Fluorescence Detection
A 6.5-GHz energy-efficient BFSK modulator for wireless sensor applications
A 2-MHz 9-45-V Input High-Efficiency Three-Switch ZVS Step-Up/-Down Hybrid Converter
Circuit for monitoring BJT RF performance using DC measurements
Noise-shaping sense amplifier for MRAM cross-point arrays
A new waveform-reshaping circuit: an alternative approach to Schmitt trigger
A self-tuning DVS processor using delay-error detection and correction
A Calibration-Free Energy-Efficient IC for Link-Adaptive Real-Time Energy Storage Optimization of CM Inductive Power Receivers
High-linearity continuous-time filter in 5-V VLSI CMOS
Analysis and design of a 1.8-GHz CMOS LC quadrature VCO
MOS current gain cells with electronically variable gain and constant bandwidth
Low-voltage pulsewidth control loops for SOC applications
A 65-nm Digital Stochastic Compute-in-Memory CNN Processor With 8-bit Precision
A high slew-rate CMOS amplifier for analog signal processing
A 1.6-GHz dual modulus prescaler using the extended true-single-phase-clock CMOS circuit technique (E-TSPC)
A 2.048 Mb/s Full-Duplex Free-Space Optical Transceiver IC for a Real-Time In Vivo Brain-Computer Interface Mouse Experiment Under Social Interaction
Error-Prediction LDPC and Error-Recovery Schemes for Highly Reliable Solid-State Drives (SSDs)
A high-speed median circuit
Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method
A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications
Notice of Violation of IEEE Publication Principles: A multi-rate 9.953-12.5-GHz 0.2-μm SiGe BiCMOS LC oscillator using a resistor-tuned varactor and a supply pushing cancellation circuit
A Wideband Linear I/Q-Interleaving DDRM
A 12 pJ/Pixel Analog-to-Information Converter Based 816 × 640 Pixel CMOS Image Sensor
A 128 × 128 SPAD Motion-Triggered Time-of-Flight Image Sensor With In-Pixel Histogram and Column-Parallel Vision Processor
A CMOS Class-D Line Driver Employing a Phase-Locked Loop Based PWM Generator
A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications
A Chain-Weaver Balanced Power Amplifier With an Embedded Impedance/Power Sensor
Design and Analysis of a 4.2 mW 4 K 6-8 GHz CMOS LNA for Superconducting Qubit Readout
An Interference-Resilient Bit-Level Duty-Cycled ULP Receiver Leveraging a Dual-Chirp Modulation
A Fully-Integrated Switched-Capacitor Step-Down DC-DC Converter With Digital Capacitance Modulation in 45 nm CMOS
A 2.7 mW/Channel 48-1000 MHz Direct Sampling Full-Band Cable Receiver
An ultrawideband CMOS low-noise amplifier for 3.1-10.6-GHz wireless receivers
A 27-mW 3.6-gb/s I/O transceiver
A 14-bit 1.8-V 20-mW 1-mm 2 CMOS DAC
A 0.458-pJ/bit 24-Gb/s/pin Capacitively Driven PAM-4 Transceiver With PAM-Based Crosstalk Cancellation for High-Density Die-to-Die Interfaces
A CMOS 21 952-Pixel Multi-Modal Cell-Based Biosensor With Four-Point Impedance Sensing for Holistic Cellular Characterization
A Digital-Sampling PLL With a Second-Order Noise Shaping SAR ADC Phase Detector
Design of Wide-Tuning-Range Millimeter-Wave CMOS VCO With a Standing-Wave Architecture
An 86% Efficiency 12 µW Self-Sustaining PV Energy Harvesting System With Hysteresis Regulation and Time-Domain MPPT for IOT Smart Nodes
A 50-ns 256 K CMOS split-gate EPROM
A 60-Frames/s CMOS Image Sensor With Pixelwise Conversion Gain Modulation and Self-Triggered ADCs for Per-Frame Adaptive DCG-HDR Imaging
SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration
A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application
A finite-mesh technique for laser trimming of thin-film resistors
A Si bipolar 5-Gb/s 8:1 multiplexer and 4.2-Gb/s 1:8 demultiplexer
A 50-Mbit/s CMOS monolithic optical receiver
An 8-b Josephson digital signal processor
Enhancing microprocessor immunity to power supply noise with clock-data compensation
1.04 GBd low EMI digital video interface system using small swing serial link technique
A 90-GHz InP-HEMT lossy match amplifier with a 20-dB gain using a broadband matching technique
A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme
A 26 W 97%-Efficiency Fast-Settling Dimmable LED Driver With Dual-nMOS-Sensing Based Glitch-Tolerant Synchronous Current Control for High-Brightness Solid-State Lighting Applications
A 64-Tile 2.4-Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute
Low Power Wideband Receiver and Transmitter Chipset for mm-Wave Imaging in SiGe Bipolar Technology
A BiCMOS front-end system with binary delay line for capacitive detector read-out
A temperature-stable CMOS variable-gain amplifier with 80-dB linearly controlled gain range
A 45 µW Injection-Locked FSK Wake-Up Receiver With Frequency-to-Envelope Conversion for Crystal-Less Wireless Body Area Network
A 37.5-45 GHz Superharmonic-Coupled QVCO With Tunable Phase Accuracy in 28 nm CMOS
High-speed, low-power BiCMOS comparator using a pMOS variable load
A 64-Gb/s 4-PAM Transceiver Utilizing an Adaptive Threshold ADC in 16-nm FinFET
A 44.2-TOPS/W CNN Processor With Variation-Tolerant Analog Datapath and Variation Compensating Circuit
Integration Trends in Monolithic Power ICs: Application and Technology Challenges
An Efficient Deep-Learning-Based Super-Resolution Accelerating SoC With Heterogeneous Accelerating and Hierarchical Cache
Synthesizing embedded speed-optimized architectures
A modeling approach for ΣΔ fractional-N frequency synthesizers allowing straightforward noise analysis
An IR-UWB IEEE 802.15.4z Compatible Coherent Asynchronous Polar Transmitter in 28-nm CMOS
A Noise-Immunity-Enhanced Analog Front-End for $36\times64$ Touch-Screen Controllers With 20- $\text{V}_{\text{PP}}$ Noise Tolerance at 100 kHz
A 1-V 140-μW 88-dB audio sigma-delta modulator in 90-nm CMOS
A 100 MHz 82.4% Efficiency Package-Bondwire Based Four-Phase Fully-Integrated Buck Converter With Flying Capacitor for Area Reduction
A 28-W, -102.2-dB THD+N Class-D Amplifier Using a Hybrid ΔΣM-PWM Scheme
Low-Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital CMOS
A 12V/24V-to-1V PWM-Controlled DSD Converter With Delay-Insensitive and Dual-Phase Charging Techniques for Fast Transient Responses
A Near-Optimum Dynamic Voltage Scaling (DVS) in 65-nm Energy-Efficient Power Management With Frequency-Based Control (FBC) for SoC System
A 0.7-V MOSFET-only switched-opamp ΣΔ modulator in standard digital CMOS technology
A High Dynamic Range 128 × 120 3-D Stacked CMOS SPAD Image Sensor SoC for Fluorescence Microendoscopy
7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS
A 150 GHz Amplifier With 8 dB Gain and +6 dBm P sat in Digital 65 nm CMOS Using Dummy-Prefilled Microstrip Lines
Cosmic-ray soft error rate characterization of a standard 0.6-μm CMOS process
A reset-free anti-harmonic delay-locked loop using a cycle period detector
BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics
Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off
A 5.94-μm Pixel-Pitch 25.2-Mpixel 120-Frames/s Full-Frame Global Shutter CMOS Image Sensor With Pixel-Parallel 14-bit ADC
Introduction to the Special Issue on the 40th European Solid-State Circuits Conference (ESSCIRC)
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction
A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems
A Sub-50-fs rms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm
Cascadable one/two-dimensional digital convolver
A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register
A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
Latchup-free ESD protection design with complementary substrate-triggered SCR devices
An analytical equation for the oscillation frequency of high-frequency ring oscillators
Weak Cell Detection in Deep-Submicron SRAMs: A Programmable Detection Technique
Current sensing differential logic: a CMOS logic for high reliability and flexibility
A CMOS V-I converter with 75-dB SFDR and 360-μW power consumption
A 15-bit 140-µW Scalable-Bandwidth Inverter-Based ΔΣ Modulator for a MEMS Microphone With Digital Output
A 900-Mb/s CMOS data recovery DLL using half-frequency clock
A 50-MHz CMOS variable gain amplifier for magnetic data storage systems
Integrated Cold Start of a Boost Converter at 57 mV Using Cross-Coupled Complementary Charge Pumps and Ultra-Low-Voltage Ring Oscillator
A 15 MHz 20 mW BiCMOS switched-capacitor biquad operating with 150 Ms/s sampling frequency
An Interferer-Tolerant CMOS Code-Domain Receiver Based on N-Path Filters
A 120-GHz Class-F Frequency Doubler With 7.8-dBm P OUT in 55-nm Bulk CMOS
A 4/7 kHz audio bandwidth selectable digital phone interface (DPI) chip with on-chip analog functions and modem
A CMOS 510 K-transistor single-chip token-ring LAN controller (TRC) compatible with IEEE802.5 MAC protocol
On-Chip Supply Noise Regulation Using a Low-Power Digital Switched Decoupling Capacitor Circuit
PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm
A mixed-signal BiCMOS front-end signal processor for high-temperature applications
A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE
A Monolithic Capacitor-Current-Controlled Hysteretic Buck Converter With Transient-Optimized Feedback Circuit
A 0.4 V 63 µW 76.1 dB SNDR 20 kHz Bandwidth Delta-Sigma Modulator Using a Hybrid Switching Integrator
High-speed CMOS circuit technique
An Automotive-Use Battery-to-Load GaN-Based Switching Power Converter With Anti-Aliasing MR-SSM and In-Cycle Adaptive ZVS Techniques
MOS varactors with n- and p-type gates and their influence on an LC-VCO in digital CMOS
Multi-Drive Stacked-FET Power Amplifiers at 90 GHz in 45 nm SOI CMOS
A 3.3-mW ΣΔ modulator for UMTS in 0.18-μm CMOS with 70-dB dynamic range in 2-MHz bandwidth
An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration
A 1.25-GHz Fully Integrated DC-DC Converter Using Electromagnetically Coupled Class-D LC Oscillators
A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory