yusuke1997/dblp-id-title huggingface dataset:
An identity-based dynamic group signature scheme for reputation evaluation systems
A DSP based board for neural network simulation
rShare: Alleviating long startup on the Cloud-rendering platform through de-systemization
Edge-enabled IAM for IoTs with edge-based access management and context-driven syncservice
Reducing disk I/O times using anticipatory movements of the disk head
An implementation-directed design method for microcontroller software
A Distributed PTX Virtual Machine on Hybrid CPU/GPU Clusters
A parallel architecture for real-time video coding
An external data structure tool for pascal
Memory latency consideration for load sharing on heterogeneous network of workstations
Bringing pervasive embedded networks to the service cloud: A lightweight middleware approach
Efficient local memory sequence generation for data parallel programs using permutations
UAV-assisted dependency-aware computation offloading in device-edge-cloud collaborative computing based on improved actor-critic DRL
A blockchain-based dynamic and traceable data integrity verification scheme for smart homes
Stepwise decomposition in controlpath synthesis
A survey of hardware architectures for generative adversarial networks
Session B1: Design and testing of real-time systems
Early design stage exploration of fixed-length block structured architectures
Performance of reconfigurable architectures for image-processing applications
Chain or DAG? Underlying data structures, architectures, topologies and consensus in distributed ledger technology: A review, taxonomy and research issues
Markovian and analytical models for multiple bus multiprocessor systems with memory blockings
A dynamic binary translation system in a client/server environment
Spike Algorithm with savings for strictly diagonal dominant tridiagonal systems
Scheduling energy consumption-constrained workflows in heterogeneous multi-processor embedded systems
A table-driven system controller with multi-way branching
Compositional power-aware real-time scheduling with discrete frequency levels
Reusability-aware cache memory sharing for chip multiprocessors with private L2 caches
ECASS: Edge computing based auxiliary sensing system for self-driving vehicles
Determining effective multiprocessor scheduling policies for repetitive real-time tasks
Issues in the design and implementation of a distributed operating system for a network of transputers
An interactive environment for hardware/software system design at the specification level
Looping adjacent nodes on multistage interconnection networks
Minimizing write operation for multi-dimensional DSP applications via a two-level partition technique with complete memory latency hiding
A protocol for resource locking and deadlock detection in a multi-user environment
Global microcode compaction - a performance evaluation by simulation
Transputer model of the human peripheral hearing system
An effectively instrumentable life cycle model: A layer and view approach to software systemeering
A bit-serial VLSI architecture for the 2-D discrete cosine transform
Tests for global EDF schedulability analysis
The architecture of a Gaussian mixture Bayes (GMB) robot position estimation system
Privacy-preserving statistical analysis over multi-dimensional aggregated data in edge computing-based smart grid systems
Assessing systems adaptability to a product family
Reducing Errors and Powers in LPDDR for DNN Inference: A Compression and IECC-Based Approach
Open-architecture system based on a reconfigurable hardware-software multi-agent platform for CNC machines
On-chip short-time interval measurement system for high-speed signal timing characterization
LODAP: On-device incremental learning via lightweight operations and data pruning
MMDA: Multidimensional and multidirectional data aggregation for edge computing-enhanced IoT
On the relative performance merits of hypercube and hypermesh networks
A robust defense for spiking neural networks against adversarial examples via input filtering
Odd-even, compare-exchange parallel sorting
Design space exploration of reliable networked embedded systems
Efficient load-and-contention-aware scheduling for 5G-TSN integrated networks
Interest spaces: A unified interest-based dissemination framework for opportunistic networks
Saving register-file static power by monitoring instruction sequence in ROB
False history filtering for reducing hardware overhead of FPGA-based LZ77 compressor
An application of functional decomposition in ROM-based FSM implementation in FPGA devices
MIAT Efficient analysis of adaptive variable-rate tasks
Internet and the electronic classroom
Beyond VABlock: Improving Transformer workloads through aggressive prefetching
Analysing value substitution and confidence estimation for value prediction
Geometric transformations for optimum VLSI layout placement
A reliability model for multiprocessor networks with degradable nodes
Exploring AADL verification tool through model transformation
An extended-UIO-based method for protocol conformance testing
A capacity sharing and stealing strategy for open real-time systems
High performance and energy efficient inference for deep learning on multicore ARM processors using general optimization techniques and BLIS
A qualitative cybersecurity analysis of time-triggered communication networks in automotive systems
Is it worth the energy? An in-depth study on the energy efficiency of data augmentation strategies for finetuning-based low/few-shot object detection
A transputer-based accelerator for multilevel digital simulation
Cost-optimal dynamic data replication for distributed database systems: DYVO
Hybrid fault diagnosability using the comparison-based approach
FTSC: Fault-tolerant scheduling and control co-design for distributed real-time system
Software life cycle management based on a phase distinction method
A snooping cache coherency protocol for hierarchically organized multiprocessors
A soft multi-core architecture for edge detection and data analysis of microarray images
State machine replication in containers managed by Kubernetes
Program chairman's introduction
Synthesis of an intelligent environment for object recognition using tactile data
Process programming using graphical objects
PC-Rimst - a tool for validating concurrent program designs
A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths
Architectural differences of efficient sequential and parallel computers
Software process maturity and certification
Digital signature with cryptographic reverse firewalls
An efficient DM switchbox router
Session D4: VLSI design and routing
Improving energy efficiency for flash memory based embedded applications
LiDAR localization using position-encoded landmarks without point cloud maps
Design space exploration for high-level synthesis of multi-threaded applications
Massively parallel execution of logic programs: A static approach
Dual-Mode Execution Environment for active network
Service vulnerability scanning based on service-oriented architecture in Web service environments
Distributed active objects: A methodological proposal and tool for distributed programming with transputer systems
Removing bias from the judgment day: A Ravenscar-based toolbox for quantitative comparison of EDF-to-RM uniprocessor scheduling
Session B4: VLSI synthesis
Modeling of optimal load balancing strategy using queueing theory
FSbrain: An intelligent I/O performance tuning system
A versatile Kernel proposal for a multimicroprocessor system environment
A shared memory architecture for parallel cyclic reference counting
A framework for supporting the development of verifiably safe medical best practice guideline systems
ReT-FTS: Re-transmission-based fault-tolerant scheduling in TSN
A QoS-guaranteed online user data deployment method in edge cloud computing environment
Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling
Dynamic reuse of subroutine results
Automatic reconfigurable transputer networks - A new direction in parallel processing for robotic applications
Mean-field reinforcement learning for decentralized task offloading in vehicular edge computing
Design control in a high level synthesis system
Dynamically reconfigurable multi-transputer systems with serial bus control
Secure auditing and deduplication with efficient ownership management for cloud storage
IDERES: Intrusion detection and response system using machine learning and attack graphs
Blockchain-based decentralized data dissemination scheme in smart transportation
Exploiting partial replication in unbalanced parallel loop scheduling on multicomputer
Specification, detection, and treatment of STRIDE threats for software components: Modeling, formal methods, and tool support
Design space exploration of embedded systems: A view from diverse domains
A reference architecture for cooperative driving
Special issue: Design and optimization for embedded and real-time computing systems and applications
Cooperative computation offloading and resource allocation for delay minimization in mobile edge computing
Stochastic modelling of a high speed, short packet length, slotted ring with finite queueing capacity
How useful are complex instructions? A case study using the M68000
An analytical performance model for the Spidergon NoC with virtual channels
A fault tolerant routing algorithm based on cube algebra for hypercube systems
A revocable multi-authority fine-grained access control architecture against ciphertext rollback attack for mobile edge computing
Session G3: Database systems
The interactive space-time scheduler
Education of real-time systems engineers
Coded worn block mechanism to reduce garbage collection in SSD
Formalization of continuous Fourier transform in verifying applications for dependable cyber-physical systems
A transputer network for a device simulator
SIPA: An activity-planning system
Performance comparison of signature-based multikey access methods
Application aware Scalable Architecture for GPGPU
Identifying irreducible loops in the Instrumentation Point Graph
Oberon: A system for workstations
ADCIM: scalable construction of approximate digital compute-in-memory MACRO for energy-efficient attention computation
Specification and verification of dynamic evolution of software architectures
Windowed active sampling for reliable neural learning
An automatic energy consumption characterization of processors using ArchC
Towards Linux based safety systems - A statistical approach for software execution path coverage
A new concept for chip architecture design - Interactive architecture compilation from system specification to register-transfer algorithms
Finding the best compromise in compiling compound loops to Verilog
JSA WATERS 2011
A platform-based SoC design and implementation of scalable automaton matching for deep packet inspection
Fast evaluation of design alternatives - a new approach for exploratory chip design
gkDtree: A group-based parallel update kd-tree for interactive ray tracing
Microprocessor design for embedded system
A survey on cybersecurity attacks and defenses for unmanned aerial systems
A portable model for predicting the size and execution time of programs
SparkNoC: An energy-efficiency FPGA-based accelerator using optimized lightweight CNN for edge computing
Bridging TSN and 5G networks: Prototype design and evaluation for real-time embedded systems
Calculation of dense trajectory descriptors on a heterogeneous embedded architecture
A nonlinear predistortion technique for radio channels: Algorithms and implementation problems
NDE system for railway wheel inspection in a standard FPGA
Dynamic Task Mapping and Scheduling with Temperature-Awareness on Network-on-Chip based Multicore Systems
Efficient and provably secure multi-receiver signcryption scheme using implicit certificate in edge computing
The IRCAM signal processing workstation - An environment for research in real-time musical signal processing and performance
MKSS: An Effective Multi-authority Keyword Search Scheme for edge-cloud collaboration
An integrated framework for the design of distributed programming environments
Optimizing the data placement and scheduling on multi-port DWM in multi-core embedded system
Efficient algorithms for task mapping on heterogeneous CPU/GPU platforms for fast completion time
Bus network assisted drone scheduling for sustainable charging of wireless rechargeable sensor network
Microelectronics: the VLSI-/370 microprocessor I
Extending Kernighan-Lin partitioning heuristic for application mapping onto Network-on-Chip
Controller and architecture co-design of wireless cyber-physical systems
Case studies for self-organization in computer science
Special issue on Reliable Software Technologies (AEiC2021)
Highly accurate and efficient evaluation of randomising set index functions
A global-energy-aware virtual machine placement strategy for cloud data centers
A thread synchronization model for the PREEMPT_RT Linux kernel
Filter-based deep-compression with global average pooling for convolutional networks
DIP : Distributed Diagnosis Protocol
A traceable and revocable broadcast encryption scheme for preventing malicious encryptors in Medical IoT
Low-latency service function chain migration in edge-core networks based on open Jackson networks
Register-interconnect optimization in data path synthesis
Evaluation of transient errors in GPGPUs for safety critical applications: An effective simulation-based fault injection environment
Tight necessary feasibility analysis for recurring real-time tasks on a multiprocessor
A fault detection model for edge computing security using imbalanced classification
Microcontrol architectures with sequencing firmware and modular microcode development tools
Supporting adaptive routing in IBA switches
On the efficiency of vector computers with private cache memories
Experimental evaluation of slack management in real-time control systems: Coordinated vs. self-triggered approach
32-Bit microprocessor architectures and extended abstract machines for high level languages
Mixed level test generation for high fault coverage
SIMD architecture on FPGA for scientific computing aboard a space instrument
An empirical study of genetic operators in genetic algorithms
Pulse slimming in magnetic recording using digital signal processing techniques
ASP-based optimized mapping in a simulink-to-MPSoC design flow
Temporal partitioning of data flow graph for dynamically reconfigurable architecture
HeterScale: A hierarchical task scheduling framework for intelligent edge collaboration in IIOT
Justifying reliability claims for a fault-detecting parallel architecture
New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs
Efficient large-scale heterogeneous debugging using dynamic tracing
Predictable and optimized single-path code for predicated processors
Parallel address calculation sorting on a network of transputers
A DSP processor with a powerful set of elementary arithmetic operations based on cordic and CCM algorithms
Energy efficient mixed task handling on real-time embedded systems using FreeRTOS
Synthesis of systolic architectures using the SYS 3 system
A verifiable efficient federated learning method based on adaptive Boltzmann selection for data processing in the internet of things
A technology description method for generalized layout / circuit relations
A reuse base for real-time software specifications
Parallel processing: Fault Tolerance II
On hardware for generating routes in Kautz digraphs
Inter: An inexpensive inter-procedural register allocator
ADHD fMRI short-time analysis method for edge computing based on multi-instance learning
Secure Routing Framework for Mitigating Time-Delay Trojan Attack in System-on-Chip
A Machine Learning-Based Intrusion Detection Framework with Labeled Dataset Generation for IEEE 802.1 Time-Sensitive Networking
Electric vehicle charging network security: A survey
The inner product processor
Low learning-cost offline strategies for EDP optimization of parallel applications
Segmentation of cylindrical parts stored in a bin
Prenaut: Design space exploration for embedded symmetric multiprocessing with various on-chip architectures
DELTA: Deadline aware energy and latency-optimized task offloading and resource allocation in GPU-enabled, PiM-enabled distributed heterogeneous MEC architecture
A new architecture for efficient hybrid representation of terrains
Memory protection in embedded systems
BR-FEEL: A backdoor resilient approach for federated edge learning with fragment-sharing
On the interfacing between QEMU and SystemC for virtual platform construction: Using DMA as a case
FedMQ+: Towards efficient heterogeneous federated learning with multi-grained quantization
WaaS (Wireless-as-a-Sensor): Conception, design and implementation on mobile platforms
The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research
Light-weight AI and IoT collaboration for surveillance video pre-processing
Performance evaluation of a new design-tool for microprocessor transient fault recovery
Mixed hierarchical-functional fault models for targeting sequential cores
Algorithm/architecture solutions to improve beyond uniform quantization in embedded DNN accelerators
Analysis of network processing workloads
Non-preemptive and SRP-based fully-preemptive scheduling of real-time Software Transactional Memory
Computer aided evalution of simulation results, the Simueva program package
Network computing with SONiC
A VLSI implementation of polymorphic-torus architecture
Timing verification for the VLSI-/370 microprocessor
An efficient GPU-accelerated inference engine for binary neural network on mobile phones
An integrated development system for the MC68705 single chip computer
Model-driven business process security requirement specification
Designing layout-timing independent quantum-dot cellular automata (QCA) circuits by global asynchrony
An efficient multi-task learning CNN for driver attention monitoring
Precise contention-aware performance prediction on virtualized multicore system
Secure communication in microcomputer bus systems for embedded devices
Intel i860 versus Digital Signal Processors (DSP)
An empirical model to estimate power consumption in GaAs DCFL/SDCFL circuits
Minimizing energy consumption of collaborative deployment and task offloading in two-tier UAV edge computing networks
A stability-considered density-adaptive routing protocol in MANETs
From structural RT description tio floor plan
ECTM: A network-on-chip communication model to combine task and message schedulability analysis
Learning automata-based virtual backoff algorithm for efficient medium access in vehicular ad hoc networks
Reachability analysis -based validation of embedded systems
Matching algorithms and architectures
Dataflow formalisation of real-time streaming applications on a Composable and Predictable Multi-Processor SOC
Explicit fault modeling and hierarchical test pattern generation in the KARATE system
Distrusting cores by separating computation from isolation
A portable, efficient inter-core communication scheme for embedded multicore platforms
Building real-time parallel task systems on multi-cores: A hierarchical scheduling approach
MACFI: A multi-authority access control scheme with efficient ciphertext and secret key size for fog-enhanced IoT
An efficient parallel-network packet pattern-matching approach using GPUs
Efficient Cache Resizing policy for DRAM-based LLCs in ChipMultiprocessors
Vehicle data management with specific wear-levelling and fault tolerance for hybrid DRAM-NVM memory
Special issue on cluster computing
A GSPN based methodology for the evaluation of concurrent applications in distributed plant automation systems
CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism
Improving energy efficiency of mobile devices by characterizing and exploring user behaviors
Optimized implementation of OpenCL kernels on FPGAs
Energy-aware fault-tolerant scheduling for imprecise mixed-criticality systems with semi-clairvoyance
MBBNet: An edge IoT computing-based traffic light detection solution for autonomous bus
Methodologies and tools for the design space exploration of embedded systems
Erratum to "Bandwidth constrained smoothing for multimedia streaming with scheduling support" [Journal of Systems Architecture 48 (2003) 353-366]
An instruction systolic array implementation of the two-dimensional Fast Fourier Transform
Optimizing the EDP of OpenMP applications via concurrency throttling and frequency boosting
A survey on intrusion detection and prevention in wireless ad-hoc networks
PUA-KE: Practical User Authentication with Key Establishment and its Application in Implantable Medical Devices
Area and power-efficient innovative congestion-aware Network-on-Chip architecture
Towards the development of a mathematician's assistant
A perfomability approach to the cost minimization of a class of gracefully degrading computer systems
Reliable and energy optimized WSN design for a train application
CMOS layout generation for improved testability
A survey on unmanned aerial systems cybersecurity
Pen-based recognizing of handprinted characters
Global approach to assignment and scheduling of complex behaviors based on HCDG and constraint programming
Parallelism extraction from sequential programs for VLSI applications
Cloud security in the age of adaptive adversaries: A game theoretic approach to hypervisor-based intrusion detection
A distributed message authentication scheme with reputation mechanism for Internet of Vehicles
CoAxNN: Optimizing on-device deep learning with conditional approximate neural networks
A bus-monitor unit for fault-tolerant system configurations
Improving the computational efficiency of modular operations for embedded systems
BIFS: A filing system for multiprocessor based systems
Exploiting vectorization in high level synthesis of nested irregular loops
PLANNER 4: A simulator to design packet switching data network
VLSI testing and testability
Parset: A language construct for system independent parallel programming on distributed systems
Multi-policy-aware MapReduce resource allocation and scheduling for smart computing cluster
RT-level synthesis
A scalable VLSI speed/area tunable sorting network
Performance evaluation of switching networks
Similarity-based deduplication and secure auditing in IoT decentralized storage
An improved algorithm for evaluation of the product of an exponential function with an error function complement
Two-processor monitoring system for airplanes
Hybrid functional- and instruction-level power modeling for embedded and heterogeneous processor architectures
DBDAA: Dual blockchain and decentralized identifiers assisted anonymous authentication for building IoT
Automatic performance analysis of hybrid MPI/OpenMP applications
Artificial neural network realization with programmable logic circuit
CADTM: A database transaction manager for coordinating design activities in CAD environments
An overview of the sysedit chip design environment
Real-time intelligent on-device monitoring of heart rate variability with PPG sensors
Implementation of Given's Rotation processors for DSP real-time applications
Introduction to the special issue on reconfigurable cyber-physical and embedded system design
FPGA based real-time on-road stereo vision system
Fault-tolerant data acquisition network: Implementation of a prototype
Heterogeneous schema integration method for multidatabase system
An offloading method using decentralized P2P-enabled mobile edge servers in edge computing
Enhancing a control graph based HDL for performance evaluation of simulated architectures
Integrated core selection and mapping for mesh based Network-on-Chip design with irregular core sizes
Embedded system for contrast enhancement in low-vision
Compiling for massively parallel architectures: a perspective
Exact response time analysis of fixed priority systems based on sporadic servers
Exploring the design space of multiprocessor synchronization protocols for real-time systems
Energy efficient backup overloading schemes for fault tolerant scheduling of real-time tasks