yusuke1997/dblp-id-title huggingface dataset:
Solving difficult instances of Boolean satisfiability in the presence of symmetry
Circuit placement on arbitrarily shaped regions using the self-organization principle
Three-Input Gates for Logic Synthesis
Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis
Quantitative Performance Evaluation of Uncertainty-Aware Hybrid AADL Designs Using Statistical Model Checking
Circuit Reliability Analysis Using Symbolic Techniques
Gaussian Fitness Functions for Optimizing Analog CMOS Integrated Circuits
A Composite Two-Dimensional Process/Device Simulation System (TOPMODE) and its Application for Total Process Designing in Submicron VLSI MOS Device Phase
Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction
Fast and Inexpensive High-Level Synthesis Design Space Exploration: Machine Learning to the Rescue
Platform-based design for an embedded-fingerprint-authentication device
BERN-NN-IBF: Enhancing Neural Network Bound Propagation Through Implicit Bernstein Form and Optimized Tensor Operations
Sequential equivalence checking based on structural similarities
Multiphase BIST: a new reseeding technique for high test-data compression
Canonical symbolic analysis of large analog circuits withdeterminant decision diagrams
High-Level Asynchronous Concepts at the Interface Between Analog and Digital Worlds
MoRS: An Approximate Fault Modeling Framework for Reduced-Voltage SRAMs
Accelerating Dynamic Time Warping With Memristor-Based Customized Fabrics
MCAM: Memductance Components Adaptive Model for Efficient Modeling of Memductance of Memristive Devices for Neuromorphic Circuits and Systems
Corner stitching for simple rectilinear shapes [VLSI layouts]
An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization
A Physical-Location-Aware X-Filling Method for IR-Drop Reduction in At-Speed Scan Test
Register binding-based RTL power management for control-flow intensive designs
Provably good global buffering by generalized multiterminalmulticommodity flow approximation
A Contamination Aware Droplet Routing Algorithm for the Synthesis of Digital Microfluidic Biochips
GLFSR-a new test pattern generator for built-in-self-test
Cost-efficient Acceleration of Hardware Trojan Detection Through Fan-Out Cone Analysis and Weighted Random Pattern Technique
Restructuring of square processor arrays by built-in self-repair circuit
Personalized Neural Network for Patient-Specific Health Monitoring in IoT: A Metalearning Approach
Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits
A layout synthesis methodology for array-type analog blocks
The schema-based approach to workflow management
Voltage-Stacked Power Delivery Systems: Reliability, Efficiency, and Power Management
Efficiently computing communication complexity for multilevel logic synthesis
Timing constraints for domino logic gates with timing-dependent keepers
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting
The state reduction of nondeterministic finite-state machines
Hierarchical test pattern generation: a cost model and implementation
A unified approach to the synthesis of fully testable sequential machines
ARISTOTLE: Feature Engineering for Scalable Application-Level Post-Silicon Debugging
Hardware and Software Co-Design for Optimized Decoding Schemes and Application Mapping in NVM Compute-in-Memory Architectures
Matching Critical Analog Circuit Components Up To Third-Order Gradients for All Possible Exact Matching Ratios
Analog IC design automation. I. Automated circuit generation: new concepts and methods
Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits
Increasing FPGA Accelerators Memory Bandwidth With a Burst-Friendly Memory Layout
Switching activity generation with automated BIST synthesis forperformance testing of interconnects
Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction
OpenTimer v2: A New Parallel Incremental Timing Analysis Engine
On Minimizing Analog Variation Errors to Resolve the Scalability Issue of ReRAM-Based Crossbar Accelerators
Sensor-Based Time Speculation in the Presence of Timing Variability
Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays
Static Scheduling of Moldable Streaming Tasks With Task Fusion for Parallel Systems With DVFS
Reliable Inversion in GF(2 8 ) With Redundant Arithmetic for Secure Error Detection of Cryptographic Architectures
Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits
Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture
Enhancing Reliability and Security: A Configurable Poisoning PUF Against Modeling Attacks
Multicycle Tests With Constant Primary Input Vectors for Increased Fault Coverage
Effective Wire Models for X-Architecture Placement
On Constrained Pin-Mapping for FPGA-PCB Codesign
Migrating Assertions From Dense to Discrete Time
Preplacement Net Length and Timing Estimation by Customized Graph Neural Network
Efficient Batched Inference in Conditional Neural Networks
Compact test sets for high defect coverage
Entropy-driven parity-tree selection for low-overhead concurrent error detection in finite state machines
PASGCN: An ReRAM-Based PIM Design for GCN With Adaptively Sparsified Graphs
Analysis and Prevention of MCAS-Induced Crashes
SWIFT: Switch-Level Fault Simulation on GPUs
Low-Cost Characterization and Calibration of RF Integrated Circuits through I - Q Data Analysis
The path-status graph with application to delay fault simulation
Carbon Nanotube Robust Digital VLSI
Computer-Aided Design of One-Dimensional MOSFET Impurity Profiles
Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis
Keynote: A Disquisition on Logic Locking
A Depletion-Mode MOSFET Model for Circuit Simulation
Mitigating Computation Errors of In-RRAM Computing Through Network Retraining With IR-Drop and Data Allocation Effects
ARA-RCIV: Identifying Reliability-Critical Input Vectors of Logic Circuits Based on the Association Rules Analysis Approach
Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency
Real-Time Robust Video Object Detection System Against Physical-World Adversarial Attacks
Process Variation and Temperature-Aware Full Chip Oxide Breakdown Reliability Analysis
Independent and Interdependent Latch Setup/Hold Time Characterization via Newton-Raphson Solution and Euler Curve Tracking of State-Transition Equations
Crosstalk-Aware Automatic Topology Customization and Optimization for Wavelength-Routed Optical NoCs
Extraction of SPICE BJT model parameters in BIPOLE3 using optimization methods
RF-PSF: A CNN-Based Process Distinction Method Using Inadvertent RF Signatures
Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories
NoCFuzzer: Automating NoC Verification in UVM
Tail Latency Optimization for LDPC-Based High-Density and Low-Cost Flash Memory Devices
Analytical device modeling for MOS analog IC's based on regularization and Bayesian estimation
Reliability-Driven Energy-Efficient Task Scheduling for Multiprocessor Real-Time Systems
ISOP+: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design
Design Space Exploration Acceleration Through Operation Clustering
Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping
Fast Acceleration Strategies for XOR-Based Erasure Codes
Telescopic units: a new paradigm for performance optimization of VLSI designs
A 2.5 approximation algorithm for the multi-via assignment problem
Improving Fault Tolerance for Reliable DNN Using Boundary-Aware Activation
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration
Refinement-based synthesis of continuous-time analog filters through successive domain pruning, plateau search, and adaptive sampling
RTL-ConTest: Concolic Testing on RTL for Detecting Security Vulnerabilities
Small-signal analysis of MESFET including the energy conservation equation
TCSE: A Target Cell States Elimination Coding Strategy for Highly Reliable Data Storage Based on 3-D nand Flash Memory
Digitally Assisted Mixed-Signal Circuit Security
Improved Range Analysis in Fixed-Point Polynomial Data-Path
Quantum Circuit Transformation Based on Simulated Annealing and Heuristic Search
Automatic 2-D and 3-D simulation of parasitic structures insmart-power integrated circuits
Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates
Mixed element trees: a generalization of modified octrees for the generation of meshes for the simulation of complex 3-D semiconductor device structures
A new global router using zero-one integer linear programming techniques for sea-of-gates and custom logic arrays
VisSched: An Auction-Based Scheduler for Vision Workloads on Heterogeneous Processors
Scalability Analysis of Memory Consistency Models in NoC-Based Distributed Shared Memory SoCs
Multielectrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization
A Two-Stage Integer Linear Programming-Based Droplet Routing Algorithm for Pin-Constrained Digital Microfluidic Biochips
A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach
Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults - From Device to Circuit Level
ROVER: RTL Optimization via Verified E-Graph Rewriting
Combining problem reduction and adaptive multistart: a new technique for superior iterative partitioning
A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse
A File-Oriented Fast Secure Deletion Strategy for Shingled Magnetic Recording Drives
Tensor Optimization for High-Level Synthesis Design Flows
Hardware-Supported Patching of Security Bugs in Hardware IP Blocks
Time-domain thermal noise simulation of switched capacitor circuitsand delta-sigma modulators
INEAD: Intermediate Node Evaluation-Based Attack Detection for Secure Approximate Computing Systems
Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design
Match and Replace: A Functional ECO Engine for Multierror Circuit Rectification
Delay prediction from resistance-capacitance models of general MOS circuits
High-Speed Adder Design Space Exploration via Graph Neural Processes
Development of a C infinity -continuous small-signal model for a MOS transistor in normal operation
Graph-Based Subfield Scheduling for Electron-Beam Photomask Fabrication
Network flow techniques for dynamic voltage scaling in hard real-time systems
Testing of core-based systems-on-a-chip
Analog RF Circuit Sizing by a Cascade of Shallow Neural Networks
Bus Assignment Considering Flexible Escape Routing for Layer Minimization in PCB Designs
Design Tools for Intelligent Silicon Compilation
Properties First - Correct-By-Construction RTL Design in System-Level Design Flows
Postlayout logic restructuring using alternative wires
Less Traces Are All It Takes: Efficient Side-Channel Analysis on AES
Parameter Extraction for Statistical IC Process Characterization
Low-power scan testing and test data compression forsystem-on-a-chip
Toward Hardware-Efficient Optical Neural Networks: Beyond FFT Architecture via Joint Learnability
Hierarchical approach to "atomistic" 3-D MOSFET simulation
Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization
A Point Transformer Accelerator With Distribution-Aware Heuristic Distance Calculation
DSAV: A Deep Sparse Acceleration Framework for Voxel-Based 3-D Object Detection
FCNNLib: A Flexible Convolution Algorithm Library for Deep Learning on FPGAs
Exploitation of Hierarchy in Analyses of Integrated Circuit Artwork
A Scalable and Adaptable ILP-Based Approach for Task Mapping on MPSoC Considering Load Balance and Communication Optimization
GNN4REL: Graph Neural Networks for Predicting Circuit Reliability Degradation
Training-Free Stuck-At Fault Mitigation for ReRAM-Based Deep Learning Accelerators
Timing-driven placement for regular architectures
Massively parallel simulation algorithms for grid-based analog signal processors
Behavioral to structural translation in a bit-serial silicon compiler
An Advanced BIRA for Memories With an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer
Optimal algorithms for planar over-the-cell routing problems
Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification
A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA)
Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs
DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training
A Fast Method to Estimate Through-Bump Current for Power Delivery Verification
Biochemistry Synthesis on a Cyberphysical Digital Microfluidics Platform Under Completion-Time Uncertainties in Fluidic Operations
ELight: Toward Efficient and Aging-Resilient Photonic In-Memory Neurocomputing
Non-quasi-static modeling/implementation of BJT current crowding for seminumerical mixed-mode device/circuit simulation
RaPC: Raw Bit Error Rate Aware Polar Coding for 3-D nand Flash Memory
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores
An Efficient Methodology for Mapping Quantum Circuits to the IBM QX Architectures
Active timing multilevel fault-simulation with switch-level accuracy
Design and Analysis of Silicon Photonics Wave Guides Using Symbolic Methods
Energy-Aware Partitioned Scheduling of Imprecise Mixed-Criticality Systems
Layout driven synthesis of multiple scan chains
Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics
Exploiting Oscillator Arrays As Randomness Sources for Cryptographic Applications
Synthesis of Tamper-Resistant Pin-Constrained Digital Microfluidic Biochips
MARS: Matching-Driven Analog Sizing
Real-Time Detection of Power Analysis Attacks by Machine Learning of Power Supply Variations On-Chip
iTRIM: I/O-Aware TRIM for Improving User Experience on Mobile Devices
Efficient Data Extraction Circuit for Posit Number System: LDD-Based Posit Decoder
Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions
Circuits for pseudoexhaustive test pattern generation
ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction
A Practical Regularization Technique for Modified Nodal Analysis in Large-Scale Time-Domain Circuit Simulation
Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations
Cellular automata-based test pattern generators with phase shifters
Sneak Path Free Reconfiguration With Minimized Programming Steps for Via-Switch Crossbar-Based FPGA
On the interplay between meshing and discretization inthree-dimensional diffusion simulation
Analysis of strategies for constructive general block placement
Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection
Efficient 3-D Processor Array Reconfiguration Algorithms Based on Bucket Effect
Procrustes 1 : Power Constrained Performance Improvement Using Extended Maximize-Then-Swap Algorithm
Extraction of functional regularity in datapath circuits
On clustering for maximal regularity extraction
Rigorous thermodynamic treatment of heat generation and conduction in semiconductor device modeling
Neural Network-Based Control of Forced-Convection and Thermoelectric Coolers
Memristor Model Optimization Based on Parameter Extraction From Device Characterization Data
Design for Manufacturing With Emerging Nanolithography
Reverse short-channel effect due to lateral diffusion of point-defect induced by source/drain ion implantation
Analytical Heterogeneous Die-to-Die 3-D Placement With Macros
Static Analysis of Transaction-Level Communication Models
Blocks: Challenging SIMDs and VLIWs With a Reconfigurable Architecture
An Automatic Routing Scheme for General Cell LSI
Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout
Unsupervised Two-Stage Root-Cause Analysis With Transfer Learning for Integrated Systems
FCRoute: A Fast FPGA Connection Router Using Soft Routing-Space Pruning Algorithm
Temperature Dependence of the Taylor Series Coefficients and Intermodulation Distortion Characteristics of GaN HEMT
IDAP: a tool for high-level power estimation of custom array structures
Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction for Designs in Advanced Technology Nodes With Consolidated Practical Applicability and Sustainability
Estimation of Analog Parametric Test Metrics Using Copulas
Algorithms in FastImp: a fast and wide-band impedance extraction program for complicated 3-D geometries
A table lookup FET model for accurate analog circuit simulation
Energy Management of Applications With Varying Resource Usage on Smartphones
TREAD-M3D: Temperature-Aware DNN Accelerators for Monolithic 3-D Mobile Systems
Yield optimization for nondifferentiable density functions using convolution techniques
Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST
ACER: An Agglomerative Clustering Based Electrode Addressing and Routing Algorithm for Pin-Constrained EWOD Chips
Efficient frequency-domain simulation technique for short-channel MOSFET
Generation of Effective 1-Detect TDF Patterns for Detecting Small-Delay Defects
On the implementation of efficient channel filters for wideband receivers by optimizing common subexpression elimination methods
Some remarks on terminology in spectral techniques for logic design: Walsh transform and Hadamard matrices
Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization
Dynamic and static load balancing for solving block bordered circuit equations on multiprocessors
Morphling: A Reconfigurable Architecture for Tensor Computation
m-Inductive Property of Sequential Circuits
A comprehensive signature analysis scheme for oscillation-test
Test data compression based on input-output dependence
9-Input Threshold Function Identification Using a New Necessary Condition of Threshold Function
Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications
Semiconductor Device Simulation at NTT
Exploring Spin-Transfer-Torque Devices for Logic Applications
Test set compaction for combinational circuits
Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM
Clock skew minimization during FPGA placement
X-Masking for Deterministic In-System Tests
Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors
Delay-optimal clustering targeting low-power VLSI circuits
Similarity-Aware CNN for Efficient Video Recognition at the Edge
Compact Modeling of Phase-Locked Loop Frequency Synthesizer for Transient Phase Noise and Jitter Simulation
CHORD: a modular semiconductor device simulation development tool incorporating external network models
Multiway VLSI circuit partitioning based on dual net representation
Secure and Efficient Exponentiation Architectures Using Gaussian Normal Basis
Intermittent-Aware Distributed Concurrency Control
One-Shot Online Testing of Deep Neural Networks Based on Distribution Shift Detection
Minimizing production test time to detect faults in analog circuits
A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver
Synthesis of hazard-free multilevel logic under multiple-input changes from binary decision diagrams
Stacking Signal TSV for Thermal Dissipation in Global Routing for 3-D IC
Exact and Approximate Solutions for the Gate Matrix Layout Problem
VISTA: A VLSI CAD System
Swallow: A Versatile Accelerator for Sparse Neural Networks
Automated synthesis of phase shifters for built-in self-testapplications
Computer-aided redesign of VLSI circuits for hot-carrier reliability
A Homogeneous FeFET-Based Time-Domain Compute-in-Memory Fabric for Matrix-Vector Multiplication and Associative Search
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA
A new methodology for two-dimensional numerical simulation of semiconductor devices
Efficient Positive-Real Balanced Truncation of Symmetric Systems Via Cross-Riccati Equations
Toward an Analysable, Scalable, Energy-Efficient I/O Virtualization for Mixed-Criticality Systems
Built-In Test for Hidden Delay Faults
Control Flow Integrity Based on Lightweight Encryption Architecture
A simplified means for computation for interconnect distributed capacitances and inductances
Matching-based algorithm for FPGA channel segmentation design
Board-level boundary scan: regaining observability with an additional IC
Efficient Encodings for Scalable Exploration of Cyber-Physical System Architectures
Layout Decomposition Approaches for Double Patterning Lithography
Pattern-Mining for Behavioral Synthesis
Dual-V th Independent-Gate FinFETs for Low Power Logic Circuits
Statistical Hardware Design With Multimodel Active Learning
Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees
MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper
A time-based model for investigating parallel logic-level simulation
A System for Designing, Simulating, and Testing High Performance VLSI Signal Processors
A postprocessing algorithm for crosstalk-driven wire perturbation
A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults
Multiple Patterning Layout Decomposition Considering Complex Coloring Rules and Density Balancing
Acceleration of trace-based fault simulation of combinational circuits
Synthesis of one-dimensional linear hybrid cellular automata
Computing Minimal Debugging Windows in Failure Traces of AMS Assertions
SPICE models for flicker noise in n-MOSFETs from subthreshold tostrong inversion
DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory
Fanout optimization using bipolar LT-trees
Cross point assignment with global rerouting for general-architecture designs
Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology
Addressing a New Class of Reliability Threats in 3-D Network-on-Chips
QuantTPM: Efficient Mixed-Precision Quantization Framework for Tractable Probabilistic Models
Application of scan hardware and software for debug and diagnostics in a workstation environment
Determination of Floquet Exponents for Small-Signal Analysis of Nonlinear Periodic Circuits
GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine
POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints
Separable codes for detecting unidirectional errors
Perspectives on technology and technology-driven CAD
IC Protection Against JTAG-Based Attacks
FedComp: A Federated Learning Compression Framework for Resource-Constrained Edge Computing Devices
A bipartition-codec architecture to reduce power in pipelinedcircuits
Wafer Topography-Aware Optical Proximity Correction
An efficient heuristic approach to solve the unate covering problem
An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting
Concurrent Task Scheduling and Dynamic Voltage and Frequency Scaling in a Real-Time Embedded System With Energy Harvesting
Nonrectangular shaping and sizing of soft modules for floorplan-design improvement
Representing large cell maps
Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters
Mathematical Modeling Analysis of Strong Physical Unclonable Functions
Applying a robust heteroscedastic probabilistic neural network toanalog fault detection and classification
VirSoC: Automatic Synthesis of Virtual System-on-Chip Environments
Scheduling blocks of hierarchical compiled simulation of combinational circuits