yusuke1997/dblp-id-title huggingface dataset:
An RF-Energy Harvester and IR-UWB Transmitter for Ultra-Low-Power Battery-Less Biosensors
Cancellation of second-order intermodulation distortion and enhancement of IIP2 in common-source and common-emitter RF transconductors
A Reconfigurable Wilkinson Power Divider With Flexible Tuning Range Configuration
Improved Quasi-Newton Adaptive-Filtering Algorithm
Low-Complexity Multiternary Digit Multiplier Design in CNTFET Technology
Efficient Partial-Parallel Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes
Cortical Models Onto CMOL and CMOS - Architectures and Performance/Price
Comments on "Analysis of the Bridged T-coil Circuit Using the Extra-Element Theorem"
Multiple Lyapunov Functions Approach for Consensus of One-Sided Lipschitz Multi-Agents Over Switching Topologies and Input Saturation
A comparison of hardware implementations of the biorthogonal 9/7 DWT: convolution versus lifting
Systematic Design of a Transimpedance Amplifier With Specified Electromagnetic Out-of-Band Interference Behavior
An Untrimmed BJT-Based Temperature Sensor With Dynamic Current-Gain Compensation in 55-nm CMOS Process
Comments on "Stability Analysis of a Class of Nonlinear Fractional-Order Systems"
Active Interface for Piezoelectric Harvesters Based on Multi-Variable Maximum Power Point Tracking
Efficient Progressive Radiance Estimation Engine Architecture and Implementation for Progressive Photon Mapping
A 1.8 µW -65 dB THD ECG Acquisition Front-End IC Using a Bandpass Instrumentation Amplifier With Class-AB Output Configuration
Fully Digital BPSK Demodulator and Multilevel LSK Back Telemetry for Biomedical Implant Transceivers
A Theoretical Study of the Quantization Noise in Split Delta-Sigma ADCs
Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators
Micropower Class-AB VGA With Gain-Independent Bandwidth
Further refinement on LMI-based digital redesign: delta-operator approach
Perfect Decomposition Narrow-Band FIR Filter Banks
A Simplified Transistor-Based Analog Predistorter for a GaN Power Amplifier
A 21.66 Gbps Nonbinary LDPC Decoder for High-Speed Communications
Coreness and $h$ -Index for Weighted Networks
Recurrently Decomposable 2-D Convolvers for FPGA-Based Digital Image Processing
High-Resolution SAR ADC With Enhanced Linearity
A CMOS V-Band PLL With a Harmonic Positive Feedback VCO Leveraging Operation in Triode Region for Phase-Noise Improvement
An Energy-Efficient BTB Lookup Scheme for Embedded Processors
A 7.1-GHz 0.7-mW Programmable Counter With Fast EOC Generation in 65-nm CMOS
A Time-Domain Resolution Improvement of an RF-DAC
A 3.125-Gbit/s Parallel Optical Receiver in 0.13-μm CMOS With Direct Crosstalk Power Penalty Measurement Capability
Reliable H INFINITY Fuzzy Control for a Class of Discrete-Time Nonlinear Systems Using Multiple Fuzzy Lyapunov Functions
Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM
Modeling of voltage output charge-pump phase frequency detector in tuning loops
A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems
A Low-Complexity Maximum Likelihood Detector for the Spatially Modulated Signals: Algorithm and Hardware Implementation
Simple Design of Detector in the Presence of Frequency Offset for IEEE 802.15.4 LR-WPANs
Attraction Region Seeking for Power Grids
Stochastic Modeling of Nonlinear Circuits via SPICE-Compatible Spectral Equivalents
Dirac Structures in Pseudo-Gradient Systems With an Emphasis on Electrical Networks
A Digital Nonautonomous Chaotic Oscillator Suitable for Information Transmission
SPICE Behavioral Model of the Tunneling Field-Effect Transistor for Circuit Simulation
Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems
A Multilevel Class-D CMOS Power Amplifier for an Out-Phasing Transmitter With a Nonisolated Power Combiner
Digital Processing of Single-Carrier Cyclic Prefixed Frequency Channelized Receiver for Serial Links
Tunable Linear MOS Resistors Using Quasi-Floating-Gate Techniques
A Stochastic Sampled-Data Approach to Distributed H infty Filtering in Sensor Networks
Model Order Reduction of Time-Delay Systems Using a Laguerre Expansion Technique
A 104- to 112.8-GHz CMOS Injection-Locked Frequency Divider
Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array
Nanopower OTAs With Improved Linearity and Low Input Offset Using Bulk Degeneration
Low-Power Asynchronous NCL Pipelines With Fine-Grain Power Gating and Early Sleep
A Low Power Content Addressable Memory Using Low Swing Search Lines
Second-Order Consensus Seeking in Multi-Agent Systems With Nonlinear Dynamics Over Random Switching Directed Networks
Compact Electrothermal Macromodeling of Photovoltaic Modules
Effect of Offset Mismatch in Time-Interleaved ADC Circuits on OFDM-BER Performance
Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop
Accurate Shielded Interconnect Delay Estimation by Reconfigurable Ring Oscillator
Efficient Parallel Architecture for Linear Feedback Shift Registers
A Universal Method of Linear Approximation With Controllable Error for the Efficient Implementation of Transcendental Functions
Upper and Lower Bounds for the Maximum Number of Frequencies That Can Be Generated by a Class of Fractional Oscillators
A Simple Histogram-Based Capacitor Mismatch Calibration in SAR ADCs
Weighted Partitioning for Fast Multiplierless Multiple-Constant Convolution Circuit
A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers
Measurement and Reduction of ISI in High-Dynamic-Range 1-bit Signal Generation
A Normalized Least Mean Squares Algorithm With a Step-Size Scaler Against Impulsive Measurement Noise
State and Disturbance Observer-Based Integral Sliding Mode Controlled Boost DC-DC Converters
A new sigma-delta modulator architecture for testing using digital stimulus
Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation
A 10-Bit 200 MS/s Capacitor-Sharing Pipeline ADC
Efficient and Secure Non-Coherent OFDM-Based Overlapped Chaotic Chip Position Shift Keying System: Design and Performance Analysis
Continuous-Time Sigma-Delta Modulator With a Fast Tracking Quantizer and Reduced Number of Comparators
A Symbolic Dynamics Approach to Trellis-Coded Chaotic Modulation
Compact Constant Weight Coding Engines for the Code-Based Cryptography
Concept of LIF Neuron Circuit for Rate Coding in Spike Neural Networks
WLS Design of Sparse FIR Digital Filters
Kuijk Bandgap Voltage Reference With High Immunity to EMI
Three-Stage CMOS OTA for Large Capacitive Loads With Efficient Frequency Compensation Scheme
Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture
An Analysis of Phase Noise in Realigned VCOs
Quantization of FIR filters under a total integer cost constraint
High-Throughput Low-Complexity Systolic Montgomery Multiplication Over GF(2 m ) Based on Trinomials
A 0.42-V Input Boost dc-dc Converter With Pseudo-Digital Pulsewidth Modulation
Synthesis of Cascaded Lossless Commensurate Lines
High-Performance Three-Stage Single-Miller CMOS OTA With No Upper Limit of C L
An Adaptive Reconfigurable Active Voltage Doubler/Rectifier for Extended-Range Inductive Power Transmission
Design of Efficient BCD Adders in Quantum-Dot Cellular Automata
Global asymptotic stability and global exponential stability of delayed cellular neural networks
Modular Design of High-Efficiency Hardware Median Filter Architecture
Novel Data Pre-Distorter for APSK Signals in Solid-State Power Amplifiers
Modeling Harmonic Distortions Caused by Nonlinear Op-Amp DC Gain for Switched-Capacitor Sigma-Delta Modulators
DT Modeling of Clock Phase-Noise Effects in LP CT DeltaSigma ADCs With RZ Feedback
Innovative DOA Estimation Algorithm Based on Lyapunov Theory
Accounting for Input Limitation in the Control of Buck Power Converters
Progressive Scaled STT-RAM for Approximate Computing in Multimedia Applications
A 9-Gbit/s Serial Transceiver for On-Chip Global Signaling Over Lossy Transmission Lines
Signature Testing of Analog and RF Circuits: Algorithms and Methodology
The Nyquist Criterion: A Useful Tool for the Robust Design of Continuous-Time SigmaDelta Modulators
An Innovation Approach to H ∞ Fixed-Lag Smoothing for Descriptor Systems
An N-Path Filter Design Methodology With Harmonic Rejection, Power Reduction, Foldback Elimination, and Spectrum Shaping
Equivalent Circuits for the PNS2 Sampling Scheme
Integer-N PLLs Verification Methodology: Large Signal Steady State and Noise Analysis
Consensus of Switched Multiagent Systems
A Switched Capacitor Voltage Converter With Exponentially Sized Capacitor Banks for Wide Load Range
Improved SQNR and MSA in Incremental ΔΣ Modulators by Using a Recuperation Phase
Design of mM-W Fully Integrated CMOS Standing-Wave VCOs Using Low-Loss CPW Resonators
A Differential 2R Crosspoint RRAM Array With Zero Standby Current
A 1.5-pJ/bit, 9.04-Mbit/s Carrier-Width Demodulator for Data Transmission Over an Inductive Link Supporting Power and Data Transfer
Catastrophic Bifurcation in Three-Phase Voltage-Source Converters
Harvesting Energy From Aviation Data Lines: Implementation and Experimental Results
A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment
VLSI Design of Diminished-One Modulo 2 n +1 Adder Using Circular Carry Selection
A Low-Power Ternary CAM With Positive-Feedback Match-Line Sense Amplifiers
Volterra Models for Digital PWM and Their Inverses
A Study on the Design Parameters for MEMS Oscillators Incorporating Nonlinearities
Blind identification of autoregressive system using chaos
On Existence of Equilibria of Multi-Port Linear AC Networks With Constant-Power Loads
72 dB SNR, 240 Hz Frame Rate Readout IC With Differential Continuous-Mode Parallel Architecture for Larger Touch-Screen Panel Applications
Energy Optimization for Data Allocation With Hybrid SRAM+NVM SPM
Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids
In-Memory Low-Cost Bit-Serial Addition Using Commodity DRAM Technology
A 1.62 Gb/s-2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection
G-Band Injection-Locked Frequency Dividers Using π-type LC Networks
Fast convergent pipelined adaptive DFE architecture using post-cursor processing filter technique
A Simple Quasi-Static Compact Model of Bipolar ReRAM Memristive Devices
A 77-dB Dynamic Range Low-Power Variable-Gain Transimpedance Amplifier for Linear LADAR
Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links - A Tutorial
Stability Analysis of a Class of Nonlinear Fractional-Order Systems
Minimum Weighted Frobenius Norm Discrete-Time FIR Filter With Embedded Unbiasedness
A Digitally Assisted Dual-Input Dual-Band Doherty Power Amplifier With Enhanced Efficiency and Linearity
Infrastructure Circuits for Lifetime Improvement of Ultra-Low Power IoT Devices
Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition
Real-Time Light Field Denoising Using a Novel Linear 4-D Hyperfan Filter
Pinning Synchronization of Complex Switching Networks With a Leader of Nonzero Control Inputs
A 100-W Doherty Power Amplifier With Super-Octave Bandwidth
Synchronization in On-Off Stochastic Networks: Windows of Opportunity
A 37-40-GHz Low-Phase-Imbalance CMOS Attenuator With Tail-Capacitor Compensation Technique
Construction of Lossless Ladder Networks With Simple Lumped Elements Connected Via Commensurate Transmission Lines
A Spike-Latency Model for Sonar-Based Navigation in Obstacle Fields
A 2.4 GHz CMOS Class-F Power Amplifier With Reconfigurable Load-Impedance Matching
Discrete-Dopant-Induced Timing Fluctuation and Suppression in Nanoscale CMOS Circuit
QSN - A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders
A Novel STT-MRAM Cell With Disturbance-Free Read Operation
A -89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique
Improved RNS FIR filter architectures
The First Ever Real Bistable Memristors - Part II: Design and Analysis of a Local Fading Memory System
Extraction of Poles and Zeros of an RC Circuit With Roots on the Real Axis
Overcoming the Effect of the Summation-Node Parasitic Pole in an Analog Equalizer
A Fixed-Frequency Quasi-${\rm V}^{2}$ Hysteretic Buck Converter With PLL-Based Two-Stage Adaptive Window Control
A New CMOS Active Transformer QPSK Modulator With Optimal Bandwidth Control
Hyperbolic CORDIC-Based Architecture for Computing Logarithm and Its Implementation
Direct Synthesis of Parallel-Connected Symmetrical Two-Port Filters
Predicting data-dependent jitter
A High-Speed Range-Matching TCAM for Storage-Efficient Packet Classification
A Versatile Variable Rate LDPC Codec Architecture
Analysis of Least Stochastic Entropy Adaptive Filters for Noncircular Gaussian Signals
Gain, Signal-to-Noise Ratio and Power Optimization of Envelope Detector for Ultra-Low-Power Wake-Up Receiver
A Magnetic Feedback Method for Low-Voltage CMOS LNA Reverse-Isolation Enhancement
Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits
Chaotic Cryptography Using Augmented Lorenz Equations Aided by Quantum Key Distribution
Study of Injection Locking With Amplitude Perturbation and Its Effect on Pulling of Oscillator
Algorithmic ADC Offset Compensation by Nonwhite Data Chopping: System Model and Basic Theoretical Results
A 2.24-mW, 61.8-dB SNDR, 20-MS/s Pipelined ADC With Charge-Pump-Based Dynamic Biasing for Power Reduction in Op Amp Sharing
Wave-Based Analysis of Large Nonlinear Photovoltaic Arrays
A High-Linearity Pipelined ADC With Opamp Split-Sharing in a Combined Front-End of S/H and MDAC1
All-Digital Quadrature Detection With TAD for Radio-Controlled Clocks/Watches
A Compact Switchable Filtering Diplexer Based on Reused L-Shaped Resonator
Latency Analysis and Architecture Design of Simplified SC Polar Decoders
A Cell Classifier for RRAM Process Development
A Quadrature Charge-Domain Sampling Mixer With Embedded FIR, IIR, and N-Path Filters
RSNS-to-Binary Conversion
Coexistence of chaos-based and conventional digital communication systems of equal bit rate
A low-latency asynchronous shift register
An N-Path Enhanced-Q Tunable Filter With Reduced Harmonic Fold Back Effects
A Subspace Multiuser Beamforming Algorithm for the Downlink in Mobile Communications
Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology
Design of High-Order Type-II Delay-Locked Loops With a Fast-Settling-Zero-Overshoot Step Response and Large Jitter-Rejection Capabilities
Robust H ∞ control of singular impulsive systems with uncertain perturbations
USER-SMILE: Ultrafast Stimulus Error Removal and Segmented Model Identification of Linearity Errors for ADC Built-in Self-Test
A 97% Maximum Efficiency Fully Automated Control Turbo Boost Topology for Battery Chargers
Class-AB Fully Differential Voltage Followers
Genetic-Algorithm-Based Method for Optimal Analog Test Points Selection
Statistical Analysis for Pattern-Dependent Simultaneous Switching Outputs (SSO) of Parallel Single-Ended Buffers
A Functionality-Based Runtime Relocation System for Circuits on Heterogeneous FPGAs
A Suitable Hardware Realization for the Cohen Class Distributions
Analysis of Mutually Injection-Locked Oscillators for Differential Resonant Sensing
Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique
An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations
Design of FIR digital filters with prescribed flatness and peak error constraints using second-order cone programming
Optimization of the Quantized Coefficients for DDFS Utilizing Polynomial Interpolation Methods
A scalable and programmable simplicial CNN digital pixel processor architecture
A 60-GHz 1-V Supply Band-Tunable Power Amplifier in 65-nm CMOS
A Tuneable Active Inductor With High Dynamic Range for Band-Pass Filter Applications
Low-Loss Reconfigurable Phase Shifter in Gap-Waveguide Technology for mm-Wave Applications
Relaxed Multi-Instant Fuzzy State Estimation Design of Discrete-Time Nonlinear Systems and its Application: A Deep Division Approach
A K-Band 5G Phased Array RX Channel With 3.3-dB NF and 28.5-dB Gain in 130-nm SiGe
An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process
Broadband Parallel-Circuit Class-E Amplifier With Second Harmonic Control Circuit
An in-place architecture for the deblocking filter in H.264/AVC
Efficient Polynomial Basis Multipliers for Type-II Irreducible Pentanomials
A Low-Power ECoG/EEG Processing IC With Integrated Multiband Energy Extractor
A 0.0018-mm 2 153% Locking-Range CML-Based Divider-by-2 With Tunable Self-Resonant Frequency Using an Auxiliary Negative-g m Cell
Energy-Efficient Precharge-Free Ternary Content Addressable Memory (TCAM) for High Search Rate Applications
On-Chip Adaptive Circuits for Fast Media Processing
Spline neural networks for blind separation of post-nonlinear-linear mixtures
All-Digital Synchronization for SC/OFDM Mode of IEEE 802.15.3c and IEEE 802.11ad
New Stability Criterion for Fixed-Point State-Space Digital Filters With Generalized Overflow Arithmetic
Time Encoding Machines With Multiplicative Coupling, Feedforward, and Feedback
A MPPT Circuit With 25 µW Power Consumption and 99.7% Tracking Efficiency for PV Systems
On the Effect of Voigt Profile Oscillators on OFDM Systems
An Approximate Memory Architecture for Energy Saving in Deep Learning Applications
Linearized Analysis of a Digital Bang-Bang PLL and Its Validity Limits Applied to Jitter Transfer and Jitter Generation
Offset-Calibration With Time-Domain Comparators Using Inversion-Mode Varactors
Systematic Design Space Exploration of Floating-Point Expressions on FPGA
Passivity-Based Integral Sliding-Mode Control of Uncertain Singularly Perturbed Systems
A Novel Hardware-Efficient Asynchronous Cellular Automaton Model of Spike-Timing-Dependent Synaptic Plasticity
Energy Barrier Model of SRAM for Improved Energy and Error Rates
Super Class-AB OTAs With Adaptive Biasing and Dynamic Output Current Scaling
A 2-µW 45-nV/√Hz Readout Front End With Multiple-Chopping Active-High-Pass Ripple Reduction Loop and Pseudofeedback DC Servo Loop
An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver
Design of a Refresh-Controller for GC-eDRAM Based FIFOs
Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs
Recursive Geman-McClure Estimator for Implementing Second-Order Volterra Filter
Analysis and Design of a Wideband, Balun-Based, Differential Power Splitter at mm-Wave
Design and analysis of an adaptive transcutaneous power telemetry for biomedical implants
Indirect Programming of Floating-Gate Transistors
Finite Frequency Filtering Design for Uncertain Discrete-Time Systems Using Past Output Measurements
A Wide Load Range and High Efficiency Switched-Capacitor DC-DC Converter With Pseudo-Clock Controlled Load-dependent Frequency
Scalable architecture for word HMM-based speech recognition and VLSI implementation in complete system
On the Existence of Security Enhancing Converter Designs for Multi-Level Memories
A Recursive Blind Adaptive Identification Algorithm and Its Almost Sure Convergence
Linear-Phase VDF Design With Unabridged Bandwidth Control Over the Nyquist Band
Stochastic Synchronization of Complex Networks With Nonidentical Nodes Via Hybrid Adaptive and Impulsive Control
Initializing Dynamic Power System Simulations Using Eigenvalue Formulations of the Induction Machine and Power Flow Models
A Low-Cost MMSE-SIC Detector for the MIMO System: Algorithm and Hardware Implementation
High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology
Distributed SINR Fusion Estimation for a Class of Wireless Networks
A Wideband 2-5 GHz Noise Canceling Subthreshold Low Noise Amplifier
An Efficient VLSI Architecture for Nonbinary LDPC Decoders
Analysis of Parasitic Effects in Filamentary-Switching Memristive Memories Using an Approximated Verilog-A Memristor Model
Power system modeling for inverse problems
Finite-Time Consensus Tracking of Perturbed High-Order Agents With Relative Information by Integral Sliding Mode
Design of a Band-Stop Filter for a Space Shuttle Vehicle
Resource-Efficient Parallel Tree-Based Join Architecture on FPGA
High-Throughput Multifilter Interpolation Architecture for AV1 Motion Compensation
Enabling NAND Flash Memory Use Soft-Decision Error Correction Codes at Minimal Read Latency Overhead
Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms
An Approximate Closed-Form Transfer Function Model for Multiconductor Transmission Lines
A Digitally Modulated Class-E Polar Amplifier in 90 nm CMOS
Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs
Fundamental Modulation Limits for Minimum Switching Frequency Inband-Error-Free High-Efficiency Power Amplifiers
Jitter Suppression Techniques for High-Speed Sample-and-Hold Circuits
Power Performance Tradeoffs Using Adaptive Bit Width Adjustments on Resistive Associative Processors
A Timing-Driven Approach to Synthesize Fast Barrel Shifters
Octave Bandwidth Doherty Power Amplifier Using Multiple Resonance Circuit for the Peaking Amplifier
Design methodologies for high-performance noise-tolerant XOR-XNOR circuits
Multipage Read for nand Flash
An SVD Processor Based on Golub-Reinsch Algorithm for MIMO Precoding With Adjustable Precision
New Trinion and Quaternion Set-Membership Affine Projection Algorithms
A New Approach to the L(2, 1) -Labeling of Some Products of Graphs
A Matrix Pseudo-Inversion Lemma for Positive Semidefinite Hermitian Matrices and Its Application to Adaptive Blind Deconvolution of MIMO Systems
Time-Domain Experimentation of NGD ActiveRC-Network Cell
Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories
Blind Self-Calibration Technique for I/Q Imbalances and DC-Offsets
Improved Digital Average Voltage Control for Switching Converter With Capacitor Current Compensation
NGD Analysis of Turtle-Shape Microstrip Circuit
A 270-mV 6T SRAM Using Row-Based Dual-Phase V DD Control in 28-nm CMOS
Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders
A 255 MHz Programmable Gain Amplifier and Low-Pass Filter for Ultra Low Power Impulse-Radio UWB Receivers
Telegraphy equation from Weber's electrodynamics
Analytical Expressions for the Distortion of Asynchronous Sigma-Delta Modulators
Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits
A 200-Mbps∼2-Gbps continuous-rate clock-and-data-recovery circuit
A Low-Voltage-Driven High-Voltage SRAM Pixel Circuit for Power Reduction in a Digital Micro-Display Panel
Dual Push-Pull High-Speed Rail-to-Rail CMOS Buffer Amplifier for Flat-Panel Displays
Analysis and design of a low-voltage RF CMOS mixer
On the Noise Optimum of FET Broadband Transimpedance Amplifiers
A 0.009-1.4-GHz Frequency Synthesizer With Suppressed Transients During VCO Band Switching
A New Separable Two-dimensional Finite Impulse Response Filter Design With Sparse Coefficients
Fast and Accurate Time-Domain Simulations of Integer-N PLLs
Robust Adaptive Dynamic Programming for Large-Scale Systems With an Application to Multimachine Power Systems
A Dual-Band GNSS RF Front End With a Pseudo-Differential LNA
An Ultra-Low Power Energy Harvesting and Imaging (EHI) Type CMOS APS Imager With Self-Power Capability
A Resource-Limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications
A Low-Power 4-PAM Transceiver Using a Dual-Sampling Technique for Heterogeneous Latency-Sensitive Network-on-Chip
Application of generalized phasors to eigenvector and natural response computation of LTI circuits
Experimental Investigation of Recurrent Neural Network Fractional-Order Sliding Mode Control of Active Power Filter
DC-DC Buck Converter Using Analog Coarse-Fine Self-Tracking Zero-Current Detection Scheme
Lyapunov Method and Convergence of the Full-Range Model of CNNs