yusuke1997/dblp-id-title huggingface dataset:
Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters
A Low-Complexity Flexible Spectrum-Sensing Scheme for Mobile Cognitive Radio Terminals
A Decorrelating Design-for-Digital-Testability Scheme for Sigma-Delta Modulators
A Split Vector-Radix Algorithm for the 3-D Discrete Hartley Transform
Energy-Aware Design of Compressed Sensing Systems for Wireless Sensors Under Performance and Reliability Constraints
Modeling and Identification of Ultra-Wideband Analog Multipliers
Analysis and Optimization of Direct-Conversion Receivers With 25% Duty-Cycle Current-Driven Passive Mixers
Effective Resistance of a Two Layer Mesh
On the Dual-Frequency Impedance/Admittance Characteristic of Multisection Commensurate Transmission Line
A Design Approach for Power-Optimized Fully Reconfigurable Delta Sigma A/D Converter for 4G Radios
A Simplified Model for Passive-Switched-Capacitor Filters With Complex Poles
Non-Invasive Quadrature Modulator Balancing Method to Optimize Image Band Rejection
Towards an H.264/AVC HW/SW Integrated Solution: An Efficient VBSME Architecture
Characterizing the synchronizability of small-world dynamical networks
An Active-Frequency Compensation Scheme for CMOS Low-Dropout Regulators With Transient-Response Improvement
Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances
A Radio-Frequency Energy Harvesting Scheme for Use in Low-Power Ad Hoc Distributed Networks
Process and Temperature Compensation for RF Low-Noise Amplifiers and Mixers
Asynchronous Consensus of Multiple Double-Integrator Agents With Arbitrary Sampling Intervals and Communication Delays
Guest Editorial Special Section on the 2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014)
Using Machine Learning Techniques to Evaluate Multicore Soft Error Reliability
Closed-Form Analytical Equations for Amplitude and Frequency of High-Frequency CMOS Ring Oscillators
A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock
Realization of a Constant Phase Element and Its Performance Study in a Differentiator Circuit
A Modified Chaos-Based Joint Compression and Encryption Scheme
Design of Miniaturized On-Chip Bandpass Filters Using Inverting-Coupled Inductors in (Bi)-CMOS Technology
Harmonic Performance of Mixer-First Receivers With Circulant-Symmetric Basebands
An 8-bit Low-Cost String DAC With Gradient Errors Suppression to Achieve 16-bit Linearity
Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability
Voice Activity Detection Using Generalized Exponential Kernels for Time and Frequency Domains
A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy Saving
Lithography Options for the 32 nm Half Pitch Node and Beyond
On the Design of Low-Power Hybrids for Full Duplex Simultaneous Bidirectional Signaling Links
Dynamic State Estimation of Power Systems by $p$ -Norm Nonlinear Kalman Filter
A 93% Peak Efficiency Fully-Integrated Multilevel Multistate Hybrid DC-DC Converter
Partial Dynamic Element Matching Technique for Digital-to-Analog Converters Used for Digital Harmonic-Cancelling Sine-Wave Synthesis
A Recurrent Fuzzy Coupled Cellular Neural Network System With Automatic Structure and Template Learning
A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding
Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM
On the Evaluation of the Exact Output of a Switched Continuous-Time Filter and Applications
5-Gb/s Peak Detector Using a Current Comparator and a Three-State Charge Pump
An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator
Design of Compact Coupled-Line Complex Impedance Transformers With the Series Susceptance Component
A Novel Emulator for Discrete-Time MIMO Triply Selective Fading Channels
Injection-locked class-E oscillator
On the Dynamics of Regenerative Frequency Dividers
Experimental Analysis of Substrate Noise Effect on PLL Performance
Reconfigurable Hardware Architectures for Sequential and Hybrid Decoding
A 124 fJ/Bit Cascode Current Mirror Array Based PUF With 1.50% Native Unstable Bit Ratio
Suppression of Quantization-Induced Convergence Error in Pipelined ADCs With Harmonic Distortion Correction
Memristor-Based Circuit Design for Multilayer Neural Networks
A 0.6-V 9-bit 1-MS/s Charging Sharing SAR ADC With Judging-Window Switching Logic and Independent Reset Comparator for Power-Effective Applications
General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators
An Ultra-Low Voltage Level Shifter Using Revised Wilson Current Mirror for Fast and Energy-Efficient Wide-Range Voltage Conversion from Sub-Threshold to I/O Voltage
An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface
Pipelined Algorithm and Modular Architecture for Matrix Transposition
A modified architecture used for input matching in CMOS low-noise amplifiers
Design of Fixed-Frequency Pulsewidth-Modulation-Based Sliding-Mode Controllers for the Quadratic Boost Converter
Performance Analysis of Single-Frequency CW Signal-Based I/Q Regeneration in Five-Port Junction-Based Direct Receivers on Rayleigh Fading Channels
A novel noise-shaping DAC for multi-bit sigma-delta modulator
A Design-Oriented Soft Error Rate Variation Model Accounting for Both Die-to-Die and Within-Die Variations in Submicrometer CMOS SRAM Cells
Stability analysis of nonlinear power electronic systems utilizing periodicity and introducing auxiliary state vector
An Analog Programmable Multidimensional Radial Basis Function Based Classifier
A Least-Squares Filter Design Technique for the Compensation of Frequency Response Mismatch Errors in Time-Interleaved A/D Converters
An Efficient On-Chip Switched-Capacitor-Based Power Converter for a Microscale Energy Transducer
Blind Bi-Level Image Restoration With Iterated Quadratic Programming
A Metastability Error Detection and Reduction Technique for Partially Active Flash ADCs
An Efficient Spur-Aliasing-Free Spectral Calibration Technique in Time-Interleaved ADCs
Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design
IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array
Compact Transformer-Based Distributed Amplifier for UWB Systems
A Low-Jitter Polyphase-Filter-Based Frequency Multiplier With Phase Error Calibration
Revisiting spurious-free dynamic range of communication receivers
Analysis of Adaptive Digital Feedback Linearization Techniques
An analysis of charge-pump phase-locked loops
Passivity Test of Immittance Descriptor Systems Based on Generalized Hamiltonian Methods
On linear-phase FIR filters with variable bandwidth
Analysis of Class-F Power Amplifiers With a Second-Harmonic Input Voltage Manipulation
Radix-4 and Radix-8 Booth Encoded Multi-Modulus Multipliers
Delay Uncertainty Reduction by Gate Splitting
Design of a Robust Multi-Channel Timing Recovery System With Imperfect Channel State Information for 10GBASE-T
Observer-Based Adaptive Sampled-Data Event-Triggered Distributed Control for Multi-Agent Systems
Multiphysics Simulation of Biosensors Involving 3D Biological Reaction-Diffusion Phenomena in a Standard Circuit EDA Environment
A 0.3 V 10-bit SAR ADC With First 2-bit Guess in 90-nm CMOS
A Low Power Logic-Compatible Multi-Bit Memory Bit Cell Architecture With Differential Pair and Current Stop Constructs
Symmetric Three-Way Doherty Power Amplifier for High Efficiency and Linearity
Spectral Efficiency Maximization of Multiuser Massive MIMO Systems With Finite-Dimensional Channel via Control of Users' Power
On the Cross-Correlation Based Loop Gain Adaptation for Bang-Bang CDRs
A 200~µm by 100~µm Smart Submersible System With an Average Current Consumption of 1.3nA and a Compatible Voltage Converter
Memristor Crossbar Architecture for Synchronous Neural Networks
Kernel Affine Projection Sign Algorithms for Combating Impulse Interference
The Impact of LO Phase Noise in N-Path Filters
Analysis of Switching Circuits Through Incorporation of a Generalized Diode Reverse Recovery Model Into State Plane Analysis
A Low-Voltage and Low-Power Adaptive Switched-Current Sigma-Delta ADC for Bio-Acquisition Microsystems
A Modified CFOA and Its Applications to Simulated Inductors, Capacitance Multipliers, and Analog Filters
Macromodels for Static Virtual Ground Voltage Estimation in Power-Gated Circuits
Power Efficiency Comparisons of Interchip Optical Interconnect Architectures
Perceptron Implementation of Triple-Valued Logic Operations
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops
Improved Transient Current Feedforward Output Buffer for Fast and Compact Active-Matrix OLED Column Drivers
On the Partial Realization of Noncausal 2-D Linear Systems
Loss Mechanisms and Optimum Design Methodology for Efficient mm-Waves Class-E PAs
Biologically Inspired Spiking Neurons: Piecewise Linear Models and Digital Implementation
Synchronization in arrays of coupled nonlinear systems with delay and nonreciprocal time-varying coupling
A lumped scalable model for silicon integrated spiral inductors
Wireless Power Transfer System With High Misalignment Tolerance for Bio-Medical Implants
An Autocalibrated All-Digital Temperature Sensor for On-Chip Thermal Monitoring
24-GHz Injection-Locked Frequency Tripler With Third-Harmonic Quadrature Phase Generator
A Sub-Sampling-Assisted Phase-Frequency Detector for Low-Noise PLLs With Robust Operation Under Supply Interference
1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18- μħbox m CMOS Technology
An Improved DPA Countermeasure Based on Uniform Distribution Random Power Generator for IoT Applications
Negative Reactance Impacts Power Flow Convergence Using Conjugate Gradient Method
Direct RF Subsampling Receivers Enabling Impulse-Based UWB Signals for Breast Cancer Detection
A Volterra Series Nonlinear Model of the Sampling Distortion in Flash ADCs Due to Substrate Noise Coupling
The Bipartite Consensus for Multi-Agent Systems With Matrix-Weight-Based Signed Network
A model for μ-power rectifier analysis and design
An Area-Efficient On-Chip Memory System for Massive MIMO Using Channel Data Compression
A Systematic USFG Design Approach for Integrated Reconfigurable Switched-Capacitor Power Converters
A 5-GHz CMOS Frequency Synthesizer With an Injection-Locked Frequency Divider and Differential Switched Capacitors
A PVT-Independent Constant-G m Bias Technique Based on Analog Computation
Noise Figure of a Balanced Amplifier
Data Detection in Large Multi-Antenna Wireless Systems via Approximate Semidefinite Relaxation
A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3- muhboxm LTPS-TFT Technology
Settling Time Optimization for Three-Stage CMOS Amplifier Topologies
Modeling the High-Frequency Degradation of Phase/Frequency Detectors
Simplifying the Design of ΣΔModulators Using FGMOS Transistors
Designing Hardware-Efficient Fixed-Point FIR Filters in an Expanding Subexpression Space
Reliable Sliding Mode Control of Fast Sampling Singularly Perturbed Systems: A Redundant Channel Transmission Protocol Approach
Noise and Chaos Contributions in Fast Random Bit Sequence Generated From Broadband Optoelectronic Entropy Sources
A 30-MHz Voltage-Mode Buck Converter Using Delay-Line-Based PWM Control
An Algorithm for AGC Optimization in MLSE Dispersion Compensation Optical Receivers
A micropower CMOS continuous-time filter with on-chip automatic tuning
A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC
Analysis and Comparison of High-Resolution GS/s Samplers in Advanced BiCMOS and CMOS
A High-Voltage-Enabled Class-D Polar PA Using Interactive AM-AM Modulation, Dynamic Matching, and Power-Gating for Average PAE Enhancement
Spur-Free MASH Delta-Sigma Modulation
Current-Steering Digital-to-Analog Converter With a High-PSRR Current Switch
Pulse Compression in Nondestructive Testing Applications: Reduction of Near Sidelobes Exploiting Reactance Transformation
A 6-Gbit/s Hybrid Voltage-Mode Transmitter With Current-Mode Equalization in 90-nm CMOS
Implementation of Memristive Neural Network With Full-Function Pavlov Associative Memory
Comparative Analysis of Shift Variance and Cyclostationarity in Multirate Filter Banks
On the Conversion Between Number Systems
An Overcomplete Stitching Algorithm for Time Decoding Machines
Modeling and Analysis of Passive Switching Crossbar Arrays
Predictive Controller Design of Networked Systems With Communication Delays and Data Loss
Influence of noise intensity on the spectrum of an oscillator
Spurs-Free Single-Bit-Output All-Digital Frequency Synthesizers With Forward and Feedback Spurs and Noise Cancellation
A Precision High-Voltage Current Sensing Circuit
An improved wavelet approach for finding steady-state waveforms of power electronics circuits using discrete convolution
Inductive Power Transfer Uplink Using Rectifier Second-Order Nonlinearity
Hash function based on chaotic tent maps
The Probe-Insertion Technique for the Detection of Limit Cycles in Power Systems
(M, p, k)-Friendly Points: A Table-Based Method to Evaluate Trigonometric Function
Processes of AM-PM Distortion in Large-Signal Single-FET Amplifiers
A pm 0.75-V Compact CMOS Class-AB Current-Mode Exponential Variable Gain Amplifier
Transformer-Based Tunable Matching Network Design Techniques in 40-nm CMOS
Dynamics and control of ZCZVT boost converters
SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing
Linear Systems With Medium-Access Constraint and Markov Actuator Assignment
Kinetic AC/DC Converter for Electromagnetic Energy Harvesting in Autonomous Wearable Devices
A Noise-Shaped Randomized Modulation for Switched-Mode DC-DC Converters
Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links
FPGA-Accelerated Hash Join Operation for Relational Databases
Optimization of the Power Transfer Through Human Body With an Auto-Tuning System Using a Synchronous Switched Capacitor
A Passive Mixer for a Wideband TV Tuner
A Novel Tuning Method for Impedance Matching Network Based on Linear Fractional Transformation
A Fully Integrated RF CMOS Front-End IC for Connectivity Applications
Design of Power-Efficient Configurable Booth Multiplier
Oscillator Noise: A Nonlinear Perturbative Theory Including Orbital Fluctuations and Phase-Orbital Correlation
Diophantine Frequency Synthesis for Fast-Hopping, High-Resolution Frequency Synthesizers
A 1-V 1.25-GS/S 8-Bit Self-Calibrated Flash ADC in 90-nm Digital CMOS
Clock-Logic Domino Circuits for High-Speed and Energy-Efficient Microprocessor Pipelines
Oversampled DFT-Modulated Biorthogonal Filter Banks: Perfect Reconstruction Designs and Multiplierless Approximations
Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method
Fast Output Voltage-Regulated PWM Buck Converter With an Adaptive Ramp Amplitude Control
A Loop Gain Optimization Technique for Integer-N TDC-Based Phase-Locked Loops
New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology
A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS
Memory-Reduced Non-Binary LDPC Decoding With Accumulative Bubble Check
Stochastic Event-Triggered Cubature Kalman Filter for Power System Dynamic State Estimation
A Low-Power Analog Delay Line Using a Current-Splitting Method for 3-D Ultrasound Imaging Systems
A 100-dB CMRR CMOS Operational Amplifier With Single-Supply Capability
A Low-Latency and Low-Complexity Point-Multiplication in ECC
Multidimensional vector radix FHT algorithms
Global Stabilization of the Discrete-Time Integrators System by Bounded Controls
Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation
Nonbinary LDPC Code Decoder Architecture With Efficient Check Node Processing
A Multi-Bit Incremental ADC Based on Successive Approximation for Low Noise and High Resolution Column-Parallel Readout Circuits
Model Order Reduction of Port-Hamiltonian Systems by Riemannian Modified Fletcher-Reeves Scheme
Design of an ESD-Protected Ultra-Wideband LNA in Nanoscale CMOS for Full-Band Mobile TV Tuners
Filter bank design for a subband adaptive filtering structure with critical sampling
Analysis and Design of Cyclic Switched-Capacitor DC-DC Converters
Synthesis of Bias-Scalable CMOS Analog Computational Circuits Using Margin Propagation
Modified Overlap Technique Using Fermat and Mersenne Transforms
A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors
Controller Designed via an Adaptive Reaching Law for DSMC Systems
Hybrid Integration of an Active Pixel Sensor and Microfluidics for Cytometry on a Chip
Robust High-Gain Amplifier Design Using Dynamical Systems and Bifurcation Theory With Digital Postprocessing Techniques
Single Underwater Image Restoration Using Adaptive Attenuation-Curve Prior
Toward an Ultralow-Power Onboard Processor for Tongue Drive System
3D-HEVC Bipartition Modes Encoder and Decoder Design Targeting High-Resolution Videos
Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes
Power Efficient and Reliable Nonvolatile TCAM With Hi-PFO and Semi-Complementary Driver
Improved Super-Regenerative Receiver Theory
A Self-Calibrated Cryogenic Current Cell for 4.2 K Current Steering D/A Converters
A Robust Frequency Tracking Loop for Energy-Efficient Crystalless WBAN Systems
An optimal design methodology for inductive power link with class-E amplifier
Defect Tolerance Based on Coding and Series Replication in Transistor-Logic Demultiplexer Circuits
Circuit Theoretic Classification of Parallel Connected DC-DC Converters
Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation
A W-Band Balanced Power Amplifier Using Broadside Coupled Strip-Line Coupler in SiGe BiCMOS 0.13-µm Technology
Robust Synchronization by Time-Varying Impulsive Control
Stabilization of DC Nanogrids Based on Non-Integer General Type-II Fuzzy System
A Nonlinearity-Compensated All-MOS Voltage-to-Current Converter
Applicability of Well-Established Memristive Models for Simulations of Resistive Switching Devices
IIR Digital Filter Design With New Stability Constraint Based on Argument Principle
A High Efficiency Orthogonally Switching Passive Charge Pump Rectifier for Energy Harvesters
Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding
Antenna-in-Package and Transmit-Receive Switch for Single-Chip Radio Transceivers of Differential Architecture
Maximizing the Power Conversion Efficiency of Ultra-Low-Voltage CMOS Multi-Stage Rectifiers
Noise and Nonlinearity Modeling of Active Mixers for Fast and Accurate Estimation
An Intelligent and Fast Controller for DC/DC Converter Feeding CPL in a DC Microgrid
Limit Cycles in a MEMS Oscillator
A Novel Approach to State and Unknown Input Estimation for Takagi-Sugeno Fuzzy Models With Applications to Fault Detection
A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current
Continuous Time Level Crossing Sampling ADC for Bio-Potential Recording Systems
A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture
Influence of Initial Conditions on the Fundamental Periods of LFSR-Dithered MASH Digital Delta-Sigma Modulators With Constant Inputs
Analysis of Chopped Integrators, and Its Application to Continuous-Time Delta-Sigma Modulator Design
A Capacitor-Less CMOS Active Feedback Low-Dropout Regulator With Slew-Rate Enhancement for Portable On-Chip Application
Gain Scheduling Synchronization Method for Quadratic Chaotic Systems
Digital Battery Management Unit With Built-In Resistance Compensation, Modulated Frequency Detection and Multi-Mode Protection for Fast, Efficient and Safe Charging
A Generalized Lower Bound on the Bit Error Rate of DCSK Systems Over Multi-Path Rayleigh Fading Channels
Ultrabroadband Linear Power Amplifier Using a Frequency-Selective Analog Predistorter
Finite-Time H ∞ State Estimation for Discrete Time-Delayed Genetic Regulatory Networks Under Stochastic Communication Protocols
A Low-Power Architecture for Punctured Compressed Sensing and Estimation in Wireless Sensor-Nodes
84-dB Range Logarithmic Digital-to-Analog Converter in CMOS 0.18- muhboxm Technology
Designing security for number sequences generated by means of the sawtooth chaotic map
Low-Power ASK Detector for Low Modulation Indexes and Rail-to-Rail Input Range
Frequency Limited Model Reduction Techniques With Error Bounds
Analytical Equivalent Circuit Extraction Procedure for Broadband Scalable Modeling of Three-Port Center-Tapped Symmetric On-Chip Inductors
Improved Stability Conditions for Switched Positive Linear Time-Varying Systems
Compact CMOS Analog Counter for SPAD Pixel Arrays
Reconfigurable and Memory-Efficient Cyclostationary Spectrum Sensor for Cognitive-Radio Wireless Networks
A Generic Model of Memristors With Parasitic Components
An Input-Feedforward Delta-Sigma Modulator With Relaxed Timing Constraints
A Low-Complexity L infty -Norm Adaptive Filtering Algorithm
On the stability of the pulsewidth-modulated C'uk converter
A 108 F 2 /Bit Fully Reconfigurable RRAM PUF Based on Truly Random Dynamic Entropy of Jitter Noise
High-Efficiency Differential RF Front-End for a Gen2 RFID Tag
An Efficient Implementation of the Agrawal Model for Lightning-Induced Voltage Calculations Using Circuit Simulation Software
40.68 MHz Digital On-Off Delay-Compensated Active Rectifier for WPT of Biomedical Applications
Set Stabilization of Boolean Control Networks With Impulsive Effects: An Event-Triggered Approach
A Resampling Method Based on Filter Designed by Window Function Considering Frequency Aliasing
Low-power log-MAP decoding based on reduced metric memory access
Mixing Drivers in Clock-Tree for Power Supply Noise Reduction
Analytical Description of the Frequency Response Function of the Generalized Higher Order Duffing Oscillator Model
A 3.77TOPS/W Convolutional Neural Network Processor With Priority-Driven Kernel Optimization
A Fully on-Chip Digitally Assisted LDO Regulator With Improved Regulation and Transient Responses
Low-Power CMOS Rectifier Design for RFID Applications
Optimization of Combined Power and Modeling Attacks on VR PUFs With Lagrange Multipliers
Synchronization of Complex Networks With Impulsive Control and Disconnected Topology
A 12-Bit 100-MS/s Pipelined-SAR ADC With PVT-Insensitive and Gain-Folding Dynamic Amplifier
I-DCSK: An Improved Noncoherent Communication System Architecture
Mono3D: Open Source Cell Library for Monolithic 3-D Integrated Circuits
Synchronization Analysis of Two Weakly Coupled Oscillators Through a PPV Macromodel
Use of Mirror Elements in the Active Device Synthesis by Admittance Matrix Expansion
A High-Performance and Secure TRNG Based on Chaotic Cellular Automata Topology
Calculation of Cycle Lengths in Higher Order Error Feedback Modulators With Constant Inputs
Efficient FPGA Implementation of Low-Complexity Systolic Karatsuba Multiplier Over GF(2 m ) Based on NIST Polynomials
Low-Power and Compact CMOS APS Circuits for Hybrid Cryogenic Infrared Fast Imaging
A Fused Floating-Point Four-Term Dot Product Unit
A 0.35V 90nA Quiescent Current Output-Capacitor-Less NMOS Low-Dropout Regulator Using a Coarse-Fine Charge-Pump Circuit
A Truly Low-Cost High-Efficiency ASK Demodulator Based on Self-Sampling Scheme for Bioimplantable Applications
Design of Reduced-Order Positive Linear Functional Observers for Positive Time-Delay Systems
A Novel Modulo 2 n -2 k -1 Adder for Residue Number System
Propagation Delay of an RC -Chain With a Ramp Input
Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences
Residential Power Forecasting Using Load Identification and Graph Spectral Clustering
Cost, Capacity, and Performance Analyses for Hybrid SCM/NAND Flash SSD
Family of fast linearly independent ternary arithmetic transforms