yusuke1997/dblp-id-title huggingface dataset:
HIPA: A hybrid load balancing method in SSDs for improved parallelism performance
Design of cache memories for dataflow architecture
An approach to minimal-time scheduling of micro-operations
An efficient convolutional neural network for small traffic sign detection
Privacy-preserving incentive mechanism for multi-leader multi-follower IoT-edge computing market: A reinforcement learning approach
An efficient identity-based signature scheme without bilinear pairing for vehicle-to-vehicle communication in VANETs
Day-Night architecture: Development of an ultra-low power RISC-V processor for wearable anomaly detection
OURS: Over- and Under-approximating Reachable Sets for analytic time-invariant differential equations
PACWON: A parallelizing compiler for workstations on a network
Specification using lotos on the test facility of a transmission system
ADAPT: An auxiliary storage data path toolkit
Glass: a graph-theoretical approach for global binding
IoT Device security through dynamic hardware isolation with cloud-Based update
Optimal computational resource pricing in vehicular edge computing: A Stackelberg game approach
A dynamically reconfigurable communication architecture for multicore embedded systems
Modeling distributed systems: Communication issues in Hermix
Efficient runtime slack management for EDF-VD-based mixed-criticality scheduling
Prism: An efficient file mapping mechanism across multiple namespaces in mobile systems
TS-ABOS-CMS: time-bounded secure attribute-based online/offline signature with constant message size for IoT systems
A configurable system-on-chip architecture for embedded and real-time applications: concepts, design and realization
Euromicro's close encounter of the arctic circle - in real time
Executing tree routing algorithms on a high-performance pattern associative router
Highly-Efficient Bulk Data Transfer for Structured Dissemination in Wireless Embedded Network Systems
Computerised telephone metering system
Compiler support for task scheduling in hierarchical execution models
A comparison of nonlinear predictive control techniques using neural network models
CMOS transistor faults and bridging faults: Testability by delay effects and overcurrents
Error correction and erasure codes for robust network steganography
A comparison of instruction memories from the WCET perspective
Fast post-quantum private set intersection from oblivious pseudorandom function for mobile social networks
PH-ORAM: An efficient persistent ORAM design for hybrid memory systems
A robust multispectral palmprint matching algorithm and its evaluation for FPGA applications
Transient fault recovery assessment in 8 and 16 bit microprocessor based controllers in embedded systems
A software engineering environment for distributed applications
BBS: A secure and autonomous blockchain-based big-data sharing system
A multiprocessor architecture for robot-arm control
Sound recognition and optimal neural network design
Issues in CPU-coprocessor communication and synchronization
Configurable parallel memory architecture for multimedia computers
Virtual Battery: A testing tool for power-aware software
Secure web services using two-way authentication and three-party key establishment for service delivery
AnoPas: Practical anonymous transit pass from group signatures with time-bound keys
A novel authentication scheme for edge computing-enabled Internet of Vehicles providing anonymity and identity tracing with drone-assistance
Verifying networks of processes that communicate via shared variables
Polymorphous fabric-based systems: Model, tools, applications
EDULAN, a tool for teaching synchronization
A more efficient public-key authenticated encryption scheme with keyword search
Implications of VHDL timing models on simulation and software synthesis
Real-time panorama video system using networked multiple cameras
Cache eviction for SSD-HDD hybrid storage based on sequential packing
Transparent checkpointing protocol for Posix.1b applications
A rational methodology for design of new computer structures
DUNIX: Distributed operating systems education via experimentation
Response modeling runtime schedulers for timing analysis of self-timed dataflow graphs
Multimicrocomputer implementation of three-dimensional neural networks
A VLSI synthesis tool for complementary output delta modulation FIR filters
An SGX-based online voting protocol with maximum voter privacy
A shortest path adaptive routing technique for minimizing path collisions in hybrid optical network-on-chip
ETS - a performance prediction tool for protocols specified in FDT Estelle
System level modelling and analysis of complex digital systems
Sensor attack detection based on active excitation response with uncertain delays
BSAF: A blockchain-based secure access framework with privacy protection for cloud-device service collaborations
A new cryptography system and its VLSI realization
ID-CEPPA: Identity-based Computationally Efficient Privacy-Preserving Authentication scheme for vehicle-to-vehicle communications
Compiling for time-predictability with dual-issue single-path code
A novel three-level architecture for large data warehouses
Hybrid Privacy Preserving Federated Learning Against Irregular Users in Next-Generation Internet of Things
A generalized fault-tolerant sorting algorithm on a product network
KAIST image computing system (KICS): A parallel architecture for real-time multimedia data processing
Activation and validation of the system specifications
Use of wavelet for image processing in smart cameras with low hardware resources
DreamCam: A modular FPGA-based smart camera architecture
FDAN: Fuzzy deep attention networks for driver behavior recognition
Multi-mode operator for SHA-2 hash functions
SEAL A simple language for prototyping action-event specifications
A high-level performance analysis of the IBM subsystem control block (SCB) architecture
Deriving cost functions from cell libraries and real ICs to allow real area-power-delay trade-off in early stages of logic synthesis
Massively parallel GPU computing for fast stereo correspondence algorithms
Efficient implementation of reduce-scatter in MPI
A reconfiguration algorithm for wafer-scale integration of systolic arrays
An efficient and secure certificateless searchable encryption scheme against keyword guessing attacks
Optimal sample length for efficient cache simulation
PMLS - A parallel multi-level VLSI simulator
Opening and keynote session
Design and implementation of a vehicle interface protocol using an IEEE 1394 network
Towards commoditized smart-camera design
A tamper resistant hardware accelerator for RSA cryptographic applications
Software design of distributed single-axis motion controllers for industrial applications
Automated derivation of protocols implementing intelligent network services
Case tool support for requirements capture and analysis
A fault tolerant control computer for the aspera plasma instrument of phobos spacecraft
Selecting profitable custom instructions for reconfigurable processors
Dependable parallel computer systems
CURATING: A multi-objective based pruning technique for CNNs
An environment for parallel programming in PASCAL
A comprehensive review of nature inspired routing algorithms for fixed telecommunication networks
Session G2: Parallel processing: Fault tolerance I
A microprogram-based 3-D image generation system using the Am29300 family
Data loss recovery for power failure in flash memory storage systems
Level-2 cache for high performance /390 μ-processors
Partially shared cache and adaptive replacement algorithm for NoC-based many-core systems
Memory power optimization of Java-based embedded systems exploiting garbage collection information
MobileFBP: Designing portable reconfigurable applications for heterogeneous systems
GPU Energy optimization based on task balance scheduling
SIRENA: SparsIty-REpetition aware Nibble-based hardware Accelerator for convolutional neural networks
Performance aspects of Ada tasking in embedded systems
Toward a structured approach to expert system development
An engine signal simulator
Branch optimization of the TOOBSIE2 RISC-processor and classification
A simple switching system for transputer links
An efficient critical path tracing algorithm for sequential circuits
A data flow numerical processing operator
A space allocation and reuse strategy for PCM-based embedded systems
A methodology for the evaluation of multiprocessor non-preemptive allocation policies
A parallel algorithm for the Jacobian matrix of a manipulator
Increasing hardware data prefetching performance using the second-level cache
Simulation-based HW/SW co-exploration of the concurrent execution of HEVC intra encoding algorithms for heterogeneous multi-core architectures
Session D2: Software engineering: Formal methods I
The architecture of RIG: A RISC for image generation in a multi-microprocessor environment
Petri nets in logic
Fine grain pipeline architecture for high performance phase-based optical flow computation
Fault tolerance for highly parallel computers
Coordinated atomic actions as a technique for implementing distributed gamma computation
Parallel compressive sampling matching pursuit algorithm for compressed sensing signal reconstruction with OpenCL
Making specifications executable - Using IPTES Meta-IV
TTAs: Missing the ILP complexity wall
Modified straight division: A computer implementation of multiple-precision division
Acoustic-based 2-D target tracking with constrained intelligent edge device
Formal domain-driven system development in Event-B: Application to interactive critical systems
Automated memory-aware application distribution for Multi-processor System-on-Chips
TOPSIS inspired Budget and Deadline Aware Multi-Workflow Scheduling for Cloud computing
RICO: A low power repetitive iteration CORDIC for DSP applications in portable devices
Low-level-vision in an autonomous mobile robot
ReTiF: A declarative real-time scheduling framework for POSIX systems
A cross-layer fault propagation analysis method for edge intelligence systems deployed with DNNs
Exact schedulability tests for real-time scheduling of periodic tasks on unrelated multiprocessor platforms
A portable blind cloud storage scheme against compromised servers
Broadcasting in faulty hypercubes
Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems
Remote service discovery and binding architecture for soft real-time QoS in indoor location-based service
Developing graphical detection techniques for maintaining state estimation integrity against false data injection attack in integrated electric cyber-physical system
Protocol offload analysis by simulation
A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits
Online slack consolidation in global-EDF for energy consumption minimisation
Synergistic design of an application-oriented sparse directory on many-core embedded systems
Automatic implementation of programming languages using object oriented approach
IoT-RRHM: Provably secure IoT-based real-time remote healthcare monitoring framework
Security analysis of Pan et al.'s "Public-key authenticated encryption with keyword search achieving both multi-ciphertext and multi-trapdoor indistinguishability"
Accelaration mechanisms for computer performance enhancements
Rahasak - Scalable blockchain architecture for enterprise applications
Macintosh in the laboratory
NoC routing protocols - objective-based classification
Object-relationship diagrams for object-oriented modeling with concurrency feature
Improving R & D processes by an ISO 9001-based quality management system
Methodology for the model-driven development of service oriented IoT applications
Session G4: VLSI testing and modelling I
Tools for code optimization and system evaluation of the image processing system PAPRICA-3
Microcontroller software engineering
Using fundamental electrical theory for varying time quantum uni-processor scheduling
Maximising mobile user experience through self-adaptive content- and ambient-aware display brightness scaling
Evolutionary planning of virtualized cyber-physical compute and control clusters
A parallel approach to rule based systems
Scalable architecture for parallel distributed implementation of genetic programming on network of workstations
IDFG: An interactive applications specification model with phenomenological properties
Weapon classification and shooter localization using distributed multichannel acoustic sensors
DSPR: Secure decentralized storage with proof-of-replication for edge devices
Tightening the CRPD bound for multilevel non-inclusive caches
Semi-automatic guided synthesis of concurrent systems specifications
Improving branch divergence performance on GPGPU with a new PDOM stack and multi-level warp scheduling
Dynamic distribution of robot control components under hard realtime constraints - Modeling, experimental results and practical considerations
Code generation for Security and Stability Control System based on extended reactive component
Applications: Image and speech processing
Balancing memory-accessing and computing over sparse DNN accelerator via efficient data packaging
Microprocessor real-time emulation
DTS: Dynamic TDMA scheduling for Networked Control Systems
YOMNA - An efficient deadlock-free multicast wormhole algorithm in 2-D mesh multicomputers
Sub-optimal solutions to track detection problem using graph theoretic concepts
VPAMS: Verifiable and practical attribute-based multi-keyword search over encrypted cloud data
Parallel backtracking prolog engine
A quadratic programming approach to estimating the testability and coverage distributions of a VLSI circuit
The Patricia testability analysis tool
Inference framework supporting parallel execution across heterogeneous accelerators
Architectural design of a Safe Mission Manager for Unmanned Aircraft Systems
PB-NVM: A high performance partitioned buffer on NVDIMM
Secure pairing-free certificateless aggregate signcryption scheme for IoT
A generator for a number format conversion IC
JOET: Sustainable Vehicle-assisted Edge Computing for IoT devices
A software defined approach for common baseband processing
Trading computing power with ReGTime
A high-level coordinator in a distributed filestore architecture
Compressed tag architecture for low-power embedded cache systems
Synthesising an asynchronous DMA controller with Balsa
Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip
A study of the resetability of synchronous sequential circuits
Optimum RNS sign detection algorithm using MRC-II with special moduli set
A unified fault-tolerant routing scheme for a class of cluster networks
A safe distributed deadlock resolution algorithm
Graph management within the Fortport migration environment (including comments on the use of objectstore)
Efficiently tolerating failures in asynchronous real-time distributed systems
SimplMM: A simplified and abstract multicore hardware model for large scale system software formal verification
Analyzing composability of applications on MPSoC platforms
A cloud data deduplication scheme based on certificateless proxy re-encryption
File downloading oriented Roadside Units deployment for vehicular networks
Galatea neural VLSI architectures: Communication and control considerations
Improving evolutionary exploration to area-time optimization of FPGA designs
Cost analysis of interconnection networks
Symbolic forward/backward traversals of large finite state machines
Improving a time critical task execution time using an IPRESPS
On-chip hyperspectral image segmentation with fully convolutional networks for scene understanding in autonomous driving
Tracking and analysing social interactions in dairy cattle with real-time locating system and machine learning
An efficient algorithm for parametric WCET calculation
Utilising low level parallelism in general purpose code: the HARP project
A network of transputers to emulate a parallel symbolic processor
EPVD: An interactive protocol specification and validation environment in Estelle formal specification
Synthesis and optimization of image processing accelerators using domain knowledge
Short notes
ΓCMC: Fast lazy functional languages
Real-time scheduling with both preemption and nonpreemption requirements
Post-training quantization for re-parameterization via coarse & fine weight splitting
Task migration optimization for guaranteeing delay deadline with mobility consideration in mobile edge computing
Complete worst-case execution time analysis of straight-line hard real-time programs
Using versioned object-oriented data in programming languages
Real-time rate control of WebRTC video streams in 5G networks: Improving quality of experience with Deep Reinforcement Learning
Erratum to "Access region cache with register guided memory reference partitioning" [Journal of Systems Architecture 55 (2009) 434-445]
System architecture of a modular neural network using 400 simple processors
VLSI architectures for the computation of uniform B-spline curves
SEtSim: A modular simulation tool for switched Ethernet networks
Data path synthesis from a microcontroller instruction set specification in microsyn
A survey of architectural features of contemporary object storage systems
An inaudible voice attack to context-based device authentication in smart IoT systems
Efficiency measures for SOC concepts
A quantitative blind area risks assessment method for safe driving assistance
The design and implementation of a reconfigurable processor for problems of combinatorial computation
Performance analysis of tightly-coupled multiprocessor minicomputers
Efficient public-key searchable encryption against inside keyword guessing attacks for cloud storage
Relative performance measurement of 80386, 80286 and 8088 personal computer systems
Chained backplane communication architecture for scalable multiprocessor systems
An O(n 1/3 ) algorithm for distributed mutual exclusion
A survey of GaAs computer designs
Engineering SRAM-PUF on Arduino microcontroller
Intra-task device scheduling for real-time embedded systems
Architecture for a massively parallel database machine
CLPKM: A checkpoint-based preemptive multitasking framework for OpenCL kernels
Session B2: Processor Architecture II
A survey on techniques for improving Phase Change Memory (PCM) lifetime
Feedback for increased robustness of forwarding graphs in the cloud
The dining philosophers problem and its decentralisation
ZoomDB: Building cost-effective key-value store engine on ZNS SSD and SMR HDD
Design and optimization for embedded and real-time computing systems and applications
An algorithm for solving distributed termination problem
V-SAT: A visual specification and analysis tool for system-on-chip exploration
Auto-tuning for GPGPU applications using performance and energy model
On system diagnosis for transient fault situations
Period adaptation of real-time control tasks with fixed-priority scheduling in cyber-physical systems
Floating point micropipeline performance
Modeling and efficient solving of extra-functional properties for adaptation in networked embedded real-time systems
Parallel code generation for super-scalar architectures
Bandwidth of prioritized crossbar systems
EIKON: A software library for image processing applications
A semi-autonomous distributed blockchain-based framework for UAVs system
Automatic pattern generation for the electrical characterization of digital modules
Performance evaluation of a distributed architecture
Cycle calculus for hybrid systems
A survey of SRAM-based in-memory computing techniques and applications
Applications: Sensors and robotics
Music synthesis description with the data flow language lustre
Dual-mode floating-point adder architectures
Smart camera architecture
Minimizing temperature and energy of real-time applications with precedence constraints on heterogeneous MPSoC systems
On parallel solvers for sparse triangular systems
BDACD: Blockchain-based decentralized auditing supporting ciphertext deduplication
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design
Memory reservation and shared page management for real-time systems
A survey of deep learning techniques for vehicle detection from UAV images
Towards mutation testing of Reinforcement Learning systems
Hardware-oriented ant colony optimization
An efficient certificateless public key encryption scheme with authorized equality test in healthcare environments
Research on processing strategy for CPU-intensive application
Compiler-directed memory management for heterogeneous MPSoCs
Dynamic task allocation and scheduling with contention-awareness for Network-on-Chip based multicore systems
A graphics-only programming tool
DNNPipe: Dynamic programming-based optimal DNN partitioning for pipelined inference on IoT networks
Efficient module selections for finding highly acceptable designs based on inclusion scheduling
A general framework for extraction of VLSI pipeline structures
An OpenCL software compilation framework targeting an SoC-FPGA VLIW chip multiprocessor
An object-oriented kernel for distributed simulation of concurrent systems
Integrating intermediate code optimization with retargetable code generation
Formal verification of ASMs using MDGs
A scalable embedded JPEG 2000 architecture
Logic synthesis with constraints
Efficient smart-camera accelerator: A configurable motion estimator dedicated to video codec
Synthesis of programmable control structures for a simulation speed-up
PatternS: An intelligent hybrid memory scheduler driven by page pattern recognition
A fast method of protocol validation using reduced stable state exploration technique
Communications strategies in international banking
Automotive decentralized diagnosis based on CAN real-time analysis
Distributed fair DRAM scheduling in network-on-chips architecture
MaCACH: An adaptive cache-aware hybrid FTL mapping scheme using feedback control for efficient page-mapped space management
Efficient stereo matching on embedded GPUs with zero-means cross correlation
Efficient persistent memory file systems using virtual superpages with multi-level allocator
Controlling industrial processes with a dataflow industrial controller: A way to achieve better performances
An optimal domain-based reconfiguration algorithm for WSI processor arrays
Dynamic load balancing algorithm in a distributed system
A multi-thread approach reducing program execution time in a heterogeneous reconfigurable multi-processor architecture
Formal specification of basic mechanisms of a message passing kernel
IATS: Information-age aware task scheduling for vehicle-road-cloud cooperative systems
Computation-transferable authenticated key agreement protocol for smart healthcare
POPS: A tool for delay/power performance optimization
An ASIC design for edge detection in real time
Trace-based leakage energy optimisations at link time
Microelectronics: Processor architectures I
A multiprocessing system for the TMS32020
On the optimal mapping of fuzzy rules on standard micro-controllers
Lightweight anonymous authentication protocol for resource-constrained smart home devices based on elliptic curve cryptography
Design of the processing node of the PTAH 64 parallel computer
Supporting end-to-end data propagation delay analysis for TSN-based distributed vehicular embedded systems
Online user allocation in mobile edge computing environments: A decentralized reactive approach
Microprocessor system buses: A case study
The selection of expert system development environments
Proactive coordination for low-congestion multi-path datacenter networks
Efficient file fuzz testing using automated analysis of binary file format
A CAMAC crate controller for the IBM PC/XT family computers with built-in selftest features
A survey on mapping and scheduling techniques for 3D Network-on-chip
A revocable multi-authority attribute-based encryption scheme for fog-enabled IoT
A blockchain-based fine-grained data sharing scheme for e-healthcare system
Integrated analysis of reliability, power, and performance for IoT devices and servers
Worst-case traversal time analysis of TSN with multi-level preemption
Analysis and simulation of six bus arbitration protocols
Silicon-aware distributed switch architecture for on-chip networks
VLSI architecture research within the ESPRIT SPAN project