yusuke1997/dblp-id-title huggingface dataset:
A New Switched Capacitor 7L Inverter With Triple Voltage Gain and Low Voltage Stress
Design Techniques for a 30-ns Access Time 1.5-V 200-KB Embedded EEPROM Memory
A Model for Temperature Insensitive Trimmable MOSFET Current Sources
Development of an Ultralow-Power Injection-Locked PSK Receiver Architecture
HBP: improvement in BP algorithm for an adaptive MLP decision feedback equalizer
Uniform Stability of Discrete Delay Systems and Synchronization of Discrete Delay Dynamical Networks via Razumikhin Technique
Efficient Post-Processors for Improving Error-Correcting Performance of LDPC Codes
A 650-pJ/bit MedRadio Transmitter With an FIR-Embedded Phase Modulator for Medical Micro-Power Networks (MMNs)
Neural-Network-Based Robust Linearization and Compensation Technique for Sensors Under Nonlinear Environmental Influences
Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation
An accurate analysis of slew rate for two-stage CMOS opamps
A Low-Loss Image-Reject Mixer Using Source Follower Isolation Method for DRM/DAB Tuner Applications
Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement
A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition
Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs
Analytical Approach to the Study of Injection-Locked Frequency Dividers
Noise gain expressions for low noise second-order digital filter structures
An efficient locally pipelined FFT processor
Simple Autonomous Chaotic Circuits
Area-Efficient Prefilter Architecture for a CDMA Receiver
A 10-MHz BW 77.3-dB SNDR 640-MS/s GRO-Based CT MASH ΔΣ Modulator
Passivity and Finite-Gain Performance for Two-Dimensional Digital Filters: The FM LSS Model Case
A Novel CMOS OTA Based on Body-Driven MOSFETs and its Applications in OTA-C Filters
A Third-Order 9-Bit 10-MHz CMOS Delta Sigma Modulator With One Active Stage
An Inverter-Based Continuous Time Sigma Delta ADC With Latency-Free DAC Calibration
A Switching-Based Phase Noise Model for CMOS Ring Oscillators Based on Multiple Thresholds Crossing
Characterization of On-Chip Multiport Inductors for Small-Area RF Circuits
Determination of the impedance matching domain of impedance matching networks
Behavioral Modeling Methods for Switched-Capacitor Σ∆ Modulators
Distortion Modeling of Feedback Two-Stage Amplifier Compensated With Miller Capacitor and Nulling Resistor
An RLS Tracking and Iterative Detection Engine for Mobile MIMO-OFDM Systems
New Techniques for Rationalizing Orthogonal and Biorthogonal Wavelet Filter Coefficients
Split-Delta Background Calibration for SAR ADCs
Adaptive Tracking Control of Chaotic Systems With Applications to Synchronization
Distributed Robust Control for Linear Multiagent Systems With Intermittent Communications
Effective Resistance of Finite Two-Dimensional Grids Based on Infinity Mirror Technique
Steady-State Oscillations in Resonant Electrostatic Vibration Energy Harvesters
True random bit generation from a double-scroll attractor
0.9 V to 5 V Bidirectional Mixed-Voltage I/O Buffer With an ESD Protection Output Stage
Event Driven Modeling and Characterization of the Second Order Voltage Switched Charge Pump PLL
Performance Analysis of a Robust Photometer Circuit
Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding
Enhanced Linearity in FD-SOI CMOS Body-Input Analog Circuits - Application to Voltage-Controlled Ring Oscillators and Frequency-Based ΣΔ ADCs
A VHDL-AMS Simulation Environment for an UWB Impulse Radio Transceiver
Observed-Based Asynchronous Control of Linear Semi-Markov Jump Systems With Time-Varying Mode Emission Probabilities
Angular-Domain Massive MIMO Detection: Algorithm, Implementation, and Design Tradeoffs
Synchronization of Multi-Agent Systems With Time-Varying Control and Delayed Communications
Design and Optimization of Multipath Ring Oscillators
Synchronization in general complex delayed dynamical networks
Wideband Planar Phased Array Antenna Based on Artificial Magnetic Conductor Surface
Design Procedure of Quasi-Class-E Power Amplifier for Low-Breakdown-Voltage Devices
Energy Efficient Temporal Spatial Information Processing Circuits Based on STDP and Spike Iteration
Improved Sufficient Conditions for Global Asymptotic Stability of Delayed Neural Networks
An Automatic MEMS Gyroscope Mode Matching Circuit Based on Noise Observation
GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI
Scalable and Unified Digit-Serial Processor Array Architecture for Multiplication and Inversion Over GF( $2^{m}$ )
A 25-µW All-MOS Potentiostatic Delta-Sigma ADC for Smart Electrochemical Sensors
Statistical ADC Enhanced by Pipelining and Subranging
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS
A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit
Self-timed dynamically pipelined adaptive signal processing system: a case study of DLMS equalizer for read channel
A Low-Power and Small Chip-Area Multi-Rate Human Body Communication DPFSK Transceiver for Wearable Devices
A Non-Invasive Method for Estimating Circuit and Control Parameters of Voltage Source Converters
A High-Resolution UWB IR Superregenerative Receiver Front End With an SRD Quench Shaper
A Power and Area Efficient Architecture of a PRBS Generator With Multiple Outputs
An Area Efficient 1024-Point Low Power Radix-2 2 FFT Processor With Feed-Forward Multiple Delay Commutators
Distributed Adaptive Observer-Based Control for Output Consensus of Heterogeneous MASs With Input Saturation Constraint
An X-Band SiGe BiCMOS Triple-Cascode LNA With Boosted Gain and P 1dB
Robust Polynomial Reconstruction via Chinese Remainder Theorem in the Presence of Small Degree Residue Errors
An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS
Corrections to "A New Method for the Reduction of Crosstalk and Echo in Multiconductor Interconnections"
Reduction of Substrate Noise in Sub Clock Frequency Range
Machine Learning-Based Approach for Hardware Faults Prediction
Stability Analysis of the Coupled Synchronous Reluctance Motor Drives
A CMOS Instrumentation Amplifier With 90-dB CMRR at 2-MHz Using Capacitive Neutralization: Analysis, Design Considerations, and Implementation
SERAD: Soft Error Resilient Asynchronous Design Using a Bundled Data Protocol
Design of the processing core of a mixed-signal CMOS DTCNN chip for pixel-level snakes
A High Sensitivity Analog Front-end Circuit for Semi-Passive HF RFID Tag Applied to Implantable Devices
A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ
A 12b 180MS/s 0.068mm 2 With Full-Calibration-Integrated Pipelined-SAR ADC
M-DCSK-Based Chaotic Communications in MIMO Multipath Channels With No Channel State Information
A 3.6-to-1.8-V Cascode Buck Converter With a Stacked LC Filter in 65-nm CMOS
A Dual-Feedforward Carrier-Modulated Second-Order Class-D Amplifier With Improved THD
Dynamical Behaviors of Discretized Second-Order Terminal Sliding-Mode Control Systems
Singularity-induced bifurcations in lumped circuits
Consensus Control of a Class of Lipschitz Nonlinear Systems With Input Delay
Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits
Hardware Implementation of the Compressed Beamforming Weights Calculation for the Practical Wireless MIMO-OFDM Communication System
Generative Multi-Symbol Architecture of the Binary Arithmetic Coder for UHDTV Video Encoders
Adaptively Biased Output Cap-Less NMOS LDO With 19 ns Settling Time
Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection
An Efficient Algorithm for Optimally Reshaping the TP Model Transformation
A 33-GHz LNA for 5G Wireless Systems in 28-nm Bulk CMOS
A Revisit to Strictly Passive FIR Filtering
On the Coexistence of Multiple Limit Cycles in H-Bridge Wireless Power Transfer Systems With Zero Current Switching Control
A 750-MHz 6-b Adaptive Floating-Gate Quantizer in 0.35-μm CMOS
Filters With Decreased Passband Error
A Delay Spread Cancelling Waveform Characterizer for RF Power Amplifiers
Resource Allocation for Heterogeneous Traffic in Complex Communication Networks
H ∞ Model Reduction for Interval Frequency Negative Imaginary Systems
A generic approach to the theory of superregenerative reception
Continuous Output Feedback TSM Control for Uncertain Systems With a DC-AC Inverter Example
A Highly Linear 8-Bit M-2M Digital-to-Analog Converter for Neurostimulators
Area-efficient reed-solomon decoder design for optical communications
Optical Receiver With Widely Tunable Sensitivity in BiCMOS Technology
Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs
Design and Analysis of CMOS LNAs with Transformer Feedback for Wideband Input Matching and Noise Cancellation
A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation
A Novel Generalized PWC Neuron Model: Theoretical Analyses and Efficient Design of Bifurcation Mechanisms of Bursting
A varactor configuration minimizing the amplitude-to-phase noise conversion in VCOs
Quantum Computer Simulator Based on the Circuit Model of Quantum Computation
A very low-complexity space-time block decoder (STBD) ASIC for wireless systems
Real-Time Mitigation of Short-Range Leakage in Automotive FMCW Radar Transceivers
A 0.004-mm 2 Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor
A Wide-Voltage-Range Half-Path Timing Error-Detection System With a 9-Transistor Transition-Detector in 40-nm CMOS
A Polar-Transmitter Architecture Using Multiphase Pulsewidth Modulation
Logic Design on Mirrored Memristive Crossbars
Operation Limits for RTD-Based MOBILE Circuits
Design and Analysis of UHF Micropower CMOS DTMOST Rectifiers
Efficient Mapping of Boolean Functions to Memristor Crossbar Using MAGIC NOR Gates
Stability Analysis of Switched Positive Systems: A Switched Linear Copositive Lyapunov Function Method
Multistability in Networks With Self-Excitation and High-Order Synaptic Connectivity
A 0.55 V 1.1 mW Artificial Intelligence Processor With On-Chip PVT Compensation for Autonomous Mobile Robots
Theory of Flying-Adder Frequency Synthesizers - Part I: Modeling, Signals' Periods and Output Average Frequency
HUB Floating Point for Improving FPGA Implementations of DSP Applications
A Reconfigurable Narrow-Band MB-OFDM UWB Receiver Architecture
The generalized Rayleigh's quotient adaptive noise subspace algorithm: a householder transformation-based implementation
Digital IIR Integrator Design Using Richardson Extrapolation and Fractional Delay
A 16×16 CMOS Amperometric Microelectrode Array for Simultaneous Electrochemical Measurements
Multitone ACLR and Its Applications to Linear PA Design
Noise-shaping coding through bounding the frequency-weighted reconstruction error
Variations in Nanometer CMOS Flip-Flops: Part I - Impact of Process Variations on Timing
Thermal-Aware Clock Tree Design to Increase Timing Reliability of Embedded SoCs
A 0.05- to 10-GHz, 19- to 22-GHz, and 38- to 44-GHz Frequency Synthesizer for Software-Defined Radios in 0.13-µm CMOS Process
Compact Millimeter-Wave CMOS Wideband Three-Transmission-Zeros Bandstop Filter Using a Single Coupled-Line Unit
Ultra-Low-Energy Mixed-Signal IC Implementing Encoded Neural Networks
Bipartite Synchronization and Convergence Analysis for Network of Harmonic Oscillator Systems With Signed Graph and Time Delay
A Combined Circuit for Multiplication and Inversion in GF(2 m )
FPGA Implementation of Isotropic and Nonisotropic Fading Channels
An FPGA Implementation for Solving the Large Single-Source-Shortest-Path Problem
Design, Implementation, and Experimental Verification of 5 Gbps, 800 Mrad TID and SEU-Tolerant Optical Modulators Drivers
A 12-Bit Ratio-Independent Algorithmic A/D Converter for a Capacitive Sensor Interface
An Efficient Method for Evaluating Analog Circuit Performance Bounds Under Process Variations
Broad-Band Design Techniques for Transimpedance Amplifiers
Analysis of Inverse Class-E Power Amplifier at Subnominal Condition With 50% Duty Ratio
Decision-Directed Retention-Failure Recovery With Channel Update for MLC NAND Flash Memory
RC-RCD clamp circuit for ringing losses reduction in a flyback converter
A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time ΣΔ ADC for a Digital Closed-Loop Class-D Amplifier
A Multimode Cellular Radio
Stability Criteria for Impulsive Systems With Time Delay and Unstable System Matrices
An Improved Kalman Filter With Adaptive Estimate of Latency Probability
Analysis and Design Considerations of Integrated 3-Level Buck Converters
Power Amplifier With Load Impedance Sensing Incorporated Into the Output Matching Network
A VLSI Implementation of Barrel Distortion Correction for Wide-Angle Camera Images
Spectral Pattern Comparison Methods for Cancer Classification Based on Microarray Gene Expression Data
Passivity verification in delay-based macromodels of electrical interconnects
Low-Cost, High-Precision DAC Design Based on Ordered Element Matching
The flipped voltage follower: a useful cell for low-voltage low-power circuit design
On the measurement of common-mode rejection ratio
Low-Cost Implementation of Independent Component Analysis for Biomedical Signal Separation Using Very-Large-Scale Integration
Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE
Controlled One- and Multidimensional Modulations Using Chaotic Maps
Bias-Compensated Minimum Error Entropy Algorithms With Polynomial Sparsity Penalty Constraints
A High-Performance PLL With a Low-Power Active Switched-Capacitor Loop Filter
RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder
Circuits for a Cubic-Millimeter Energy-Autonomous Wireless Intraocular Pressure Monitor
Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer
l 2 - l ∞ Elimination of Overflow Oscillations in 2-D Digital Filters Described by Roesser Model With External Interference
A 2-MHz 60-W Zero-Voltage-Switching Synchronous Noninverting Buck-Boost Converter With Reduced Component Values
Exact Analysis of Frequency Splitting Phenomena of Contactless Power Transfer Systems
Data-Driven Distributed Coordinated Control for Cloud-Based Model-Free Multiagent Systems With Communication Constraints
Data-Dependent Statistical Memory Model for Passive Array of Memristive Devices
Jitter requirements of the sampling clock in software radio receivers
An Ultra-Low-Power Dual-Mode Automatic Sleep Staging Processor Using Neural-Network-Based Decision Tree
Modified register-exchange Viterbi decoder for low-power wireless communications
A 3-6-GHz Highly Linear I-Channel Receiver With Over +3.0-dBm In-Band P 1dB and 200-MHz Baseband Bandwidth Suitable for 5G Wireless and Cognitive Radio Applications
Robust highly linear high-frequency CMOS OTA with IM3 below - 70 dB at 26 MHz
Implementation of Supersingular Isogeny-Based Diffie-Hellman and Key Encapsulation Using an Efficient Scheduling
Performance Analysis of a Hybrid Incremental and Cyclic A/D Conversion Principle
Fixator-Norator Pairs Versus Direct Analytical Tools in Performing Analog Circuit Designs
Design and Analysis of a High Bandwidth Rectifying Regulator With PWM and PFM Modes
RF Wide-Band Bandpass Filter With Dynamic In-Band Multi-Interference Suppression Capability
A 6.84 Gbps/lane MIPI C-PHY Transceiver Bridge Chip With Level-Dependent Equalization
Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time
A Low-Power, High-Sensitivity, OOK-Super-Regenerative Receiver for WBANs
Achieving Monotonic Variation of Spectral Composition in DC-DC Converters Using Pulse Skipping Modulation
A -21.2-dBm Dual-Channel UHF Passive CMOS RFID Tag Design
Implementation of Low Power Programmable Flash ADC Using IDUDGMOSFET
i-SRAM: Interleaved Wordlines for Vector Boolean Operations Using SRAMs
Information Theoretic Approach to Complexity Reduction of FIR Filter Design
An adaptive impedance tuning CMOS circuit for ISM 2.4-GHz band
A Fast and Power-Area-Efficient Accumulator for Flying-Adder Frequency Synthesizer
Guest Editorial Special Issue on the IEEE LASCAS 2019 and the IEEE NEWCAS 2019
Switched Threshold-Based Fault Detection for Switched Nonlinear Systems With Its Application to Chua's Circuit System
Isolated Two-Transistor Zeta Converter With Reduced Transistor Voltage Stress
Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver
Incentivizing Honest Mining in Blockchain Networks: A Reputation Approach
An FPGA-Based Instrument for En-Masse RRAM Characterization With ns Pulsing Resolution
Mathematical Analysis of a Prime Modulus Quantizer MASH Digital Delta-Sigma Modulator
Analysis of PWM Z-Source DC-DC Converter in CCM for Steady State
A 576-Mbit/s 64-QAM 4 × 4 MIMO Precoding Processor With Lattice Reduction
A Low-Power Variable-Gain Amplifier With Improved Linearity: Analysis and Design
A Low-Power Low-Complexity Multi-Standard Digital Receiver for Joint Clock Recovery and Carrier Frequency Offset Calibration
Mixed-Domain Systems and Signal Processing Based on Input Decomposition
0.6-1.2 V, 0.22 pJ/bit True Random Number Generator Based on SAR ADC
An 88-dB Max-SFDR 12-bit SAR ADC With Speed-Enhanced ADEC and Dual Registers
High-Efficiency Rectifier With Wide Input Power Range Based on Power Recycling
Energy-Efficient Time-Domain Vector-by-Matrix Multiplier for Neurocomputing and Beyond
An Efficient Self-Powered Piezoelectric Energy Harvesting CMOS Interface Circuit Based on Synchronous Charge Extraction Technique
Efficient Subquadratic Space Complexity Architectures for Parallel MPB Single- and Double-Multiplications for All Trinomials Using Toeplitz Matrix-Vector Product Decomposition
Counterexamples to a Method for Identifying Hopf Bifurcations Without Eigenvalue Calculation
Generalized Two-Dimensional Kalman-Yakubovich-Popov Lemma for Discrete Roesser Model
A Dual-Mode Power Amplifier With On-Chip Switch Bias Control Circuits for LTE Handsets
A Self-Biased Current-Mode Amplifier With an Application to 10-bit Pipeline ADC
On Global Asymptotic Stability of Cohen-Grossberg Neural Networks With Variable Delays
Design procedure for two-stage CMOS operational amplifiers employing current buffer
Noise Reduction Technique Through Bandwidth Switching for Switched-Capacitor Amplifier
A Compact-Sized 9-Bit Switched-Current DAC for AMOLED Mobile Display Drivers
Reconfigurable Stateful nor Gate for Large-Scale Logic-Array Integrations
Characterizing the effects of the PLL jitter due to substrate noise in discrete-time delta-sigma modulators
A Low-Voltage 5-GHz Downconversion Mixer Employing A Second Harmonic Injection Linearization Technique
Design of Downlink Synchronization for Millimeter Wave Cellular System Based on Multipath Division Multiple Access
A Configurable Noise-Shaping Band-Pass SAR ADC With Two-Stage Clock-Controlled Amplifier
Low-Power, Low-Phase-Noise G m -Boosted 10-GHz VCO With Center-Tap Transformer and Stacked Transistor
Recursive Maximum Correntropy Learning Algorithm With Adaptive Kernel Size
Optimal design of spectrum constrained analog signal sets with correlation analysis
A Low Power and High Sensing Margin Non-Volatile Full Adder Using Racetrack Memory
A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth
Wide-Range Dynamic Power Management in Low-Voltage Low-Power Subthreshold SCL
An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection
Design strategies of cascaded CML gates
Synergistic Effects in Networked Epidemic Spreading Dynamics
The application of complex quantized feedback in integrated wireless receivers
Chaotic Characteristics Analysis and Circuit Implementation for a Fractional-Order System
Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM
A Multimode Transmultiplexer Structure
A Fast Switching Current Regulator Using Slewing Time Reduction Method for High Dimming Ratio of LED Backlight Drivers
Novel Folded-KES Architecture for High-Speed and Area-Efficient BCH Decoders
Combining Multipath and Single-Path Time-Interleaved Delta-Sigma Modulators
A Current Regulator for Inverter-Based Massively Column-Parallel ΔΣ ADCs
A 36-Gb/s 1.3-mW/Gb/s Duobinary-Signal Transmitter Exploiting Power-Efficient Cross-Quadrature Clocking Multiplexers With Maximized Timing Margin
A 1-mW 1.13-1.9 GHz CMOS LC VCO Using Shunt-Connected Switched-Coupled Inductors
Modeling the closed-current loop of PWM boost DC-DC converters operating in CCM with peak current-mode control
Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT
A Power-Efficient Digital Technique for Gain and Offset Correction in Slope ADCs
A 300-V LDMOS Analog-Multiplexed Driver for MEMS Devices
Cycle-Averaged Models of Cardiovascular Dynamics
A Novel Hybrid Spiking Neuron: Bifurcations, Responses, and On-Chip Learning
A Low-Power 0.6-V Quadrature VCO With a Coupling Current Reuse Technique
Process, Voltage and Temperature Compensation Technique for Cascode Modulated PAs
A 49-to-62 GHz Quadrature VCO With Bimodal Enhanced-Magnetic-Tuning Technique
Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SoC
Global Stabilization of Multiple Oscillator Systems by Delayed and Bounded Feedback
The method of double averaging: an approach for modeling power-factor-correction switching converters
Low power delta-sigma Modulator for ADSL applications in a low-Voltage CMOS technology
Phase Characteristics for the Stability of 2-D Quarter-Plane Recursive Digital All-Pass Filters
Signal folding in A/D converters
2-D Optimization Methodology for Reconfigurable Transmitters by Tunable Matching Networks
Ternary Walsh Transform and Its Operations for Completely and Incompletely Specified Boolean Functions
Synchronization Phenomena in Interconnected Power Electronic Systems
Affine-Projection-Like M-Estimate Adaptive Filter for Robust Filtering in Impulse Noise
Analog-to-Digital Conversion Using Noise Shaping and Time Encoding
A Reconfigurable Hybrid Low Dropout Voltage Regulator for Wide-Range Power Supply Noise Rejection and Energy-Efficiency Trade-Off
Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications
Synchronization of Coupled Nonlinear Dynamical Systems: Interplay Between Times of Connectivity and Integral of Lipschitz Gain
A Simple Ladder Realization of Maximally Flat Allpass Fractional Delay Filters
Noise Analysis for Comparator-Based Circuits
Vectored Implementation of Hierarchical 2 2n QAM
Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps
Resilient Filtering for Linear Time-Varying Repetitive Processes Under Uniform Quantizations and Round-Robin Protocols
Linear Quadratic Regulator of Discrete-Time Switched Linear Systems
Stability and Stabilization for Markovian Jump Time-Delay Systems With Partially Unknown Transition Rates
A 5-Gb/s Noise Optimized Receiver Using a Switched TIA for Wireless Optical Communications
Low-Cost Architecture of Modified Daubechies Lifting Wavelets Using Integer Polynomial Mapping
Blind Iterative Nonlinear Distortion Compensation Based on Thresholding
A Charge-Recycling Assist Technique for Reliable and Low Power SRAM Design
Efficient Precision-Adjustable Architecture for Softmax Function in Deep Learning
Guest Editorial Special Issue on ISCAS 2009
A Digital Capacitive MEMS Microphone for Speech Recognition With Fast Wake-Up Feature Using a Sound Activity Detector
A mixed time-frequency-domain approach for the analysis of a hysteretic oscillator
Type II, III, and IV Linear-Phase FIR Structures Based on Cardinal Filters
A Constant Frequency Output-Ripple-Voltage-Based Buck Converter Without Using Large ESR Capacitor
A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package
Design Considerations for Low-Distortion Filter and Oscillator ICs for Testing High-Resolution ADCs
Architecture of a Fully Pipelined Real-Time Cellular Neural Network Emulator