yusuke1997/dblp-id-title huggingface dataset:
Towards highly-concurrent leaderless state machine replication for distributed systems
Avoiding deadlock with a dual-port memory
Task level behavioral hardware description
Multi-layered scheduling of mixed-criticality cyber-physical systems
Power profiling and monitoring in embedded systems: A comparative study and a novel methodology based on NARX neural networks
Implementation and performance study of a hardware-VIA-based network adapter on Gigabit Ethernet
Profiling soft-core processor applications for hardware/software partitioning
MTU configuration for real-time switched Ethernet networks
A software-controlled prefetching mechanism for software-managed TLBs
A fast and accurate delay dependent method for switching estimation of large combinational circuits
Makespan-minimization workflow scheduling for complex networks with social groups in edge computing
Evaluating transport triggered architectures for scalar applications
MEX, a programming language that supports discrete event simulation
Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms
Garbage collection of multi-version indexed data on flash memory
PORCE: An efficient power off recovery scheme for flash memory
Performance and reliability optimization for high-density flash-based hybrid SSDs
Probablistic diagnosis in multiprocessor systems
A distributed multi-level model with dynamic replacement for the storage of smart edge computing
Parallel, distributed and network-based processing
Scheduling of time-constrained single-arm cluster tools with purge operations in wafer fabrications
Hardware transactional memory architecture with adaptive version management for multi-processor FPGA platforms
Hierarchical opto-electrical on-chip network for future multiprocessor architectures
Hardware resources contention-aware scheduling of hard real-time multiprocessor systems
Static scheduling techniques for dependent tasks on dynamically reconfigurable devices
A machine-vision quality inspection system for textile industries supported by parallel multitransputer architecture
Interface design and controller synthesis of digital systems in an object oriented environment
Transactional memories for multi-processor FPGA platforms
Design and implementation of a P2P communication infrastructure for WSN-based vehicular traffic control applications
Embedded multi-spectral image processing for real-time medical application
Nash equilibria in bandwidth allocation for non-cooperative peer-to-peer networks
Two-dimensional specification of queries in object-oriented databases
FPGA prototyping of emerging manycore architectures for parallel programming research using Formic boards
Analysis of worst-case backlog bounds for Networks-on-Chip
An automatic software generator in the design of reliable procedural programs
Automatic test pattern generation can be solved as a constraint satisfaction problem
Architecture of virtual edge data center with intelligent metadata service of a geo-distributed file system
Dynamic replication control scheme using logical configuration information: DYRECT
Data path structures and heuristics for testable allocation in high level synthesis
Communication Kernels - a high level synchronization primitive supporting error handling
OCEAN: A hardware and software tool for design of future smart cards
Cache isolation for virtualization of mixed general-purpose and real-time systems
Transputer network with flexible topology
An adaptive IoT platform on budgeted 3G data plans
Session F1: Digital signal processing
Validation of SPEC6 TM CFP95 traces for accurate performance evaluation of computer systems
Object oriented system analysis for VLSI
MULTIPLUS: A modular high-performance multiprocessor
A comprehensive survey on mobile crowdsensing systems
A stable transactional memory for building robust object oriented programs
Hardware reconfiguration of Transputer networks for distributed object-oriented programming
A multi-layer transputer network for efficient parallel execution of OCCAM programs
A variable round-robin arbiter for high speed buses and statistical multiplexers
LPPA-RCM: A lightweight privacy-preserving authentication scheme for road condition monitoring in fog-based VANETs
Coprocessor design for GaAs technology
UISER - a customizable software engineering environment for development-in-the-large
Performance evaluation of system architectures with validated input data
Reliability-aware scheduling for reducing system-wide energy consumption for weakly hard real-time systems
Anomaly detection in bitcoin information networks with multi-constrained meta path
A knowledge-based approach to VLSI-design in an open CAD-environment
An enhanced two-level adaptive multiple branch prediction for superscalar processors
Introduction to the special issue of the 16th ACM workshop on Adaptive and Reflective Middleware (ARM)
Replicating parallel simulation on heterogeneous clusters
Applications: Real time systems
Algorithms and architecture support of degree-based quantization for graph neural networks
Efficient access method for multi-dimensional complex objects in spatial databases: BR tree
Parallelizing compiler techniques
PVM communication performance over an ATM MAN
Control policies for interconected distributed systems via an HIPPI switch
A regular WSI-node architecture
Efficient parallel multiplier in shifted polynomial basis
Architectural support for operating systems: A popular RISC vs. a popular CISC
A fast prototype tool for parallel reactive systems
LG-RAM: Load-aware global resource affinity management for virtualized multicore systems
IPCAS: An improved conditional privacy-preserving certificateless aggregate signature scheme without bilinear pairing for VANETs
Fuzzy logic, neural networks and soft computing
Mixed static and dynamic reasoning in a formal system
An environment to develop parallel code for solving partial differential equations based-problems
Exploiting selective instruction reuse and value prediction in a superscalar architecture
Reconfigurable Network-on-Chip based Convolutional Neural Network Accelerator
Session K3: Keynote session
Constructing a domain dependent case-base for database schema design with case-based reasoning
X-Stream: Accelerating streaming segments on MPSoCs for real-time applications
GPUart - An application-based limited preemptive GPU real-time scheduler for embedded systems
Efficient DPA side channel countermeasure with MIM capacitors-based current equalizer
One-chip low-power multiprocessor
QoE-driven computation offloading for Edge Computing
Live nodes distribution in parallel branch and bound algorithms
Linked Block-based Multiversion B-Tree index for PCM-based embedded databases
Fault tolerant Web Services
Efficient heterogeneous signcryption scheme based on Edge Computing for Industrial Internet of Things
Dynamically reconfigurable heterogeneous multi-processor systems with transputer-controlled communication
Adding static data dependence collapsing to a high-performance instruction scheduler
ANAGNOSTIS - An automatic text reading system
Authentication in stealth distributed hash tables
Spatial skyline queries over incomplete data for smart cities
Smart-toy-edge-computing-oriented data exchange based on blockchain
ChipAI: A scalable chiplet-based accelerator for efficient DNN inference using silicon photonics
GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs
Reconfigurable on-chip interconnection networks for high performance embedded SoC design
Evaluation of stereo correspondence algorithms and their implementation on FPGA
Preliminary design of a parallel SIC architecture
The specification and design of atomic actions for fault tolerant concurrent software
Scenario-based run-time adaptive MPSoC systems
A Survey on Deep Transfer Learning to Edge Computing for Mitigating the COVID-19 Pandemic
LACT: Liveness-Aware Checkpointing to reduce checkpoint overheads in intermittent systems
An efficient real-time accelerator for high-accuracy DNN-based optical flow estimation in FPGA
Unicast-based fault-tolerant multicasting in wormhole-routed hypercubes
PFV2: Packet fragmentation with variable size and vigorous mapping in time-sensitive networking
GNSS spoofing detection for UAVs using Doppler frequency and Carrier-to-Noise Density Ratio
Fault tolerant multiple-bus interconnection networks
Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources
High efficiency solution of triangular system equations on a 2-D array of transputers
Multiple-path testing for cross site scripting using genetic algorithms
BeeFlow: Behavior tree-based Serverless workflow modeling and scheduling for resource-constrained edge clusters
CrowdLoc: Robust image indoor localization with edge-assisted crowdsensing
A federated deep learning framework for privacy preservation and communication efficiency
Fast computations for some matrix functions
V60 real-time operating system
Cloud-aided attribute-based encryption with efficient tracing and accountability auditing
Graph reductions and partitioning heuristics for multicore DAG scheduling
A novel frame preemption model in TSN networks
An efficient highly parallelized ReRAM-based architecture for motion estimation of HEVC
Write reconstruction for write throughput improvement on MLC PCM based main memory
HyBR: A Hybrid Bio-inspired Bee swarm Routing protocol for safety applications in Vehicular Ad hoc NETworks (VANETs)
Towards a model of human-cyber-physical automata and a synthesis framework for control policies
Reliability-aware core partitioning in chip multiprocessors
On-demand deployment for IoT applications
On the gap between schedulability tests and an automotive task model
Design and simulation using Petri-Nets of a parallel WHT multiprocessor system
An architectural design support environment for high-performance digital systems
A multi-objective LSM/NoC architecture co-design framework
Nonblocking two-phase commit protocol to avoid unnecessary transaction abort for distributed systems
A distributed simplex architecture for multi-agent systems
Constructing real-time multi-channel protocols
Designing a parallel object-oriented compiler target language (TOOL)
Parallel GEMM-based convolutions for deep learning on multicore ARM and RISC-V architectures
Co-synthesis of contention-free energy-efficient NOC-based real time embedded systems
An FPGA-based bit-level weight sparsity and mixed-bit accelerator for neural networks
Real time pipelined system design through simulated annealing
An efficient routing strategy to support process migration
Modeling and design of the multimedia subsystem of a distributed authoring environment
X-Nets: A visual formalism for system specification and analysis
Fair and size-scalable participant selection framework for large-scale mobile crowdsensing
A comparative evaluation of hybrid distributed shared-memory systems
T-CREST: Time-predictable multi-core architecture for embedded systems
Using CCS for the specification of inheritance
Expressing logical and temporal conditions in simulation environments: TPDL *
The SegBus platform - architecture and communication mechanisms
GPU implementation of the Frenet Path Planner for embedded autonomous systems: A case study in the F1tenth scenario
High-speed, low-leakage integrated circuits: An evolutionary algorithm perspective
An embedded implementation of the Common Language Infrastructure
Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing
Specifying and inheriting concurrent objects
Distributed learning dynamics of Multi-Armed Bandits for edge intelligence
Resource consumption-aware QoS in cluster-based VOD servers
An asynchronous approach to the RISC design of a micro-controller
Hierachical modeling and simulation of processor architectures
Object-oriented analysis and modeling with the ESAstation
On implementing computer networking on existing cable TV plants: Some interesting proposals
Performance analysis of hybrid disk array architectures to meet I/O requirements
Compositional real-time models
Efficient architectures for 3D HWT using dynamic partial reconfiguration
A behavioural simulator and its use for the validation of hypercube architectures
Concurrent error detection in parallel multipliers and complex arithmetic structures: Remarks on the use of the 3n code
Application-driven architectures
UTP semantics for the MCA ARMv8 architecture
Dynamic task offloading and resource allocation for energy-harvesting end-edge-cloud computing systems
Divide-and-conquer mapping of parallel programs onto hypercube computers
Co-programming: A tool for the development of software for massively parallel computers
Baldwinian learning utilizing genetic and heuristic algorithms for logic synthesis and minimization of incompletely specified data with Generalized Reed-Muller (AND-EXOR) forms
Communication compression techniques in distributed deep learning: A survey
Securing skeletal systems with limited performance penalty: The muskel
An intelligent sensor integrated preprocessing facility for neural networks
AucSwap: A Vickrey auction modeled decentralized cross-blockchain asset transfer protocol
Supporting soft real-time parallel applications on multiprocessors
Relating evolving business rules to software design
Conditional diagnosability of hypercubes under the comparison diagnosis model
Automated support for the formal specification and design of real-time systems
PARL: Page Allocation in hybrid main memory using Reinforcement Learning
Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation
A low latency energy efficient BFT based 3D NoC design with zone based routing strategy
A blockchain-based certificateless public key signature scheme for vehicle-to-infrastructure communication in VANETs
Implementing and checking timing constraints in real-time programs
Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture
Edge data integrity verification scheme supporting data dynamics and batch auditing
Monitoring and data recording system for the underground
Schedulability Performance Improvement via Task Split in Real-Time Systems
Towards decentralized system-level security for MPSoC-based embedded applications
Feasibility of decoupling memory management from the execution pipeline
An efficient numerical technique to calculate buffer statistics
On-line recognition of Korean characters using ART neural network and hidden Markov model
Adaptive weight-bit inversion for state error reduction for robust and efficient deep neural network inference using MLC NAND Flash
On the topological properties of the arrangement-star network
A safe-by-design programming language for wireless sensor networks
Performance analysis of synchronous multibuffered packet-switching networks
Special issue on networks on chip
Integrating model-based optimization and program transformation to generate efficient parallel programs
CAD for verified hardware design via category theory
A multi-microprocessor system for the control of robot welders
A new comparison-based scheme for multiprocessor fault tolerance
Modular array structure for non-restoring square root circuit
Implementing pattern-matching function definitions in CTDNet - a multiprocessor architecture
On evaluating the resource usage effectiveness of multi-tenant cloud storage
Segmenting endoscopic images using adaptive progressive thresholding: a hardware perspective
A highly-parallel system for real-time electronic measurements
Editorial to special issue on resource management for edge intelligence
A system for verification of interactive microprogram transformations
A cross-platform OpenVX library for FPGA accelerators
Offloading and system resource allocation optimization in TDMA based wireless powered mobile edge computing
An implementation of the SANE Virtual Processor using POSIX threads
E-Audit: Distinguishing and investigating suspicious events for APTs attack detection
Stable memory for a disk write cache
Software processes, assessment and ISO 9000-certification: A user's view
A DAISY architecture for abstract data type implementation in image processing
Preference-oriented partitioning for multiprocessor real-time systems
Tools for object-oriented SPMD programming
Algorithms for inference control
Design of TMS320C40 signal processors and programmable logic based prototyping environment of real-time machine vision architectures
Perceptual control architecture for cyber-physical systems in traffic incident management
Safeguarding user data privacy in online Large Language Model services
Efficient sizing and placement of distributed generators in cyber-physical power systems
A redesigned secure and efficient data transaction protocol for mobile payment system
Bio-inspired cryptosystem with DNA cryptography and neural networks
PQES: Post-quantum encryption and signature scheme based on FFT-accelerated polynomial ring lattice for IoT devices
Formal specification and documentation of microprocessor instruction sets
Journaling deduplication with invalidation scheme for flash storage-based smart systems
Tools for logic-based access to existing databases in distributed environment
Jellyfish dynamic routing protocol with mobile sink for location privacy and congestion avoidance in wireless sensor networks
Relational algebra as formalism for hardware design
VLSI-/370 microprocessor chip technology
Music processing at L.I.M
A petri net model for pipeline scheduling
System level design of telecom systems using formal model refinement: Applying the B method/language in practice
High-level power and performance estimation of FPGA-based soft processors and its application to design space exploration
A remote control and media-sharing system using smart devices
Multi-grain reconfigurable and scalable overlays for hardware accelerator composition
Software features of an extended single instruction machine
MOPTIC-SM: Sleep mode-enabled multi-optimized intermittent computing for transiently powered systems
Logic design using the PLAs with limited I/O pins and product terms
Dynamic computation scheduling for hybrid energy mobile edge computing networks
A risc central processing unit for a massivelly parallel architecture
The "Smart" simulation environment - A tool-set to develop new cache coherency protocols
Quality-effective repair of multichip module systems
Parallel updating algorithms for graph searching problems
A blockchain-based privacy-preserving auditable authentication scheme with hierarchical access control for mobile cloud computing
NLTSP: A cost model for tensor program tuning using nested loop trees
Exploring the boundaries of Ada syntax with functional-style iterators
Poly-ABE : A traceable and revocable fully hidden policy CP-ABE scheme for integrated demand response in multi-energy systems
Secure boot, trusted boot and remote attestation for ARM TrustZone-based IoT Nodes
Rethinking compact abating probability modeling for open set recognition problem in Cyber-physical systems
The synthesis of deadlock-free interprocess communications
A multiplayer online car racing virtual-reality game based on internet of brains
Real-time behavior monitoring for multi-processor systems
An architectural approach with separation of concerns to address extra-functional requirements in the development of embedded real-time software systems
Flexible and secure access control for EHR sharing based on blockchain
Development of process visualization systems: An object-oriented approach
Compact-disk image display and handling system
Microprogrammed implementation of a reduction machine
An exact comparison of global, partitioned, and semi-partitioned fixed-priority real-time multiprocessor schedulers
A coprocessor for implementing the LISP-dialect scheme
Operating system support for the management of hard real-time disk traffic
Efficient location privacy-preserving range query scheme for vehicle sensing systems
Towards a real-time IoT: Approaches for incoming packet processing in cyber-physical systems
CLD: - A novel approach to dynamic load balancing
An efficient multi-data owner cooperative resource sharing scheme against key regeneration in edge computing
Optimal data dependence chaining in parallel loops
Error retracing and fault localization techniques within Simueva, a system for evaluation of simulation results
Congestion-free embedding of 2(n-k) spanning trees in an arrangement graph
An object-manager for handling persistent data in Modula-2
Resource efficiency of the GigaNetIC chip multiprocessor architecture
Analysis and redesign of the 'TTC' and 'TTH' schedulers
Model checking of reconfigurable FPGA modules specified by Petri nets
Pflow: An end-to-end heterogeneous acceleration framework for CNN inference on FPGAs
Design of a high speed simulation tool for WAN using parallel processing
Moving target defense for the security and resilience of mixed time and event triggered cyber-physical systems
Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer
Packetization and routing analysis of on-chip multiprocessor networks
Structured precision skipping: Accelerating convolutional neural networks with budget-aware dynamic precision selection
A light weight kernel server
Transformers in source code generation: A comprehensive survey
A provably secure and lightweight authentication scheme for Internet of Drones for smart city surveillance
Distributed vector architectures
QBLKe: Host-side flash translation layer management for Open-Channel SSDs
Broadcast directory: A scalable cache coherent architecture for mesh-connected multiprocessors
A load-balanced acceleration method for small and irregular batch matrix multiplication on GPU
An efficient heterogeneous authenticated key agreement scheme for unmanned aerial vehicles
pdvPool: A real-time object-oriented multiprocessor system
How to secure autonomous mobile robots? An approach with fuzzing, detection and mitigation
The use of unmanned aerial vehicles and wireless sensor networks for spraying pesticides
An atomic commit protocol for gigabit-networked distributed database systems
A methodology for evaluating the performance of CISC computer systems under single and two-level cache environments
Verifiable decentralized identity-based meta-computing in Industrial Internet of Things (IIoT)
Stackelberg game-based task offloading and pricing with computing capacity constraint in mobile edge computing
Minimizing the maximum lateness in real-time computations with extended deadlines
Leveraging partial-refresh for performance and lifetime improvement of 3D NAND flash memory in cyber-physical systems
Quality control in textile industry via machine vision
Software development in server-oriented systems the HERMIX approach
A Survey on Task Offloading in Multi-access Edge Computing
Synthesis of control units in a design environment for chip architecture
AP-LET: Enabling deterministic Pub/Sub communication in AUTOSAR Adaptive
Quasi dynamic approach to layout compaction
A predictable hardware to exploit temporal reuse in real-time and embedded systems
Contention-aware optimal scheduling of real-time precedence-constrained task graphs on heterogeneous distributed systems
Attribute-based searchable encryption with decentralized key management for healthcare data sharing
Stride prefetching for the secondary data cache
Feature pyramid-based graph convolutional neural network for graph classification
A security policy hardening framework for Socio-Cyber-Physical Systems
Dynamically reconfigurable dataflow architecture for high-performance digital signal processing
A novel centralized coded caching scheme for edge caching basestation
Enabling Ada and OpenMP runtimes interoperability through template-based execution
Modeling and evaluating the time overhead induced by BER in COMA multiprocessors
Reconfigurable Networks on Chip: DRNoC architecture
Guest editorial: Special issue on design architecture and applications of smart embedded devices in internet of things
A lightweight online backup manager for energy harvesting powered nonvolatile processor systems
Scheduling and parallel operations on the transputer
Securing IIoT communications using OPC UA PubSub and Trusted Platform Modules
Self-adaptive corner detection on MPSoC through resource-aware programming