yusuke1997/dblp-id-title huggingface dataset:
Reducing virtual call overheads in a Java VM just-in-time compiler
A hardware mechanism for supporting range checks
Review of Introduction to computer architecture by Harld S. Stone
An architecture for elliptic curve cryptograph computation
Hardware support for program debuggers in a paged virtual memory
Selected Papers from the Symposium on Parallel Algorithms and Architectures
Fine-grain design space exploration for a cartographic SoC multiprocessor
SIGARCH business
SPEC CPU2006 sensitivity to memory page sizes
A mini-computer configuration for CAI: a systems engineering view
A novel effective address calculation mechanism for RISC microprocessors
A priority strategy on RISC for real-time multitasking software applications
The Camino Compiler infrastructure
Scalable dynamic binary instrumentation for Blue Gene/L
Regarding a device to help battering the RAM wall
Second bibliography on Cache memories
A wafer microcomputer
On structured data handling in parallel processing
Multilayered illiac network scheme
DSP architectures: past, present and futures
Logarithmic indices for multiprocessor evaluation
40 years later ... a new engine to handle an operating system infrastructure
Conjecture corner
Propagating constants past software to hardware peripherals in fixed-application embedded systems
Area-efficiency in CMP core design: co-optimization of microarchitecture and physical design
High-Level Synthesis Optimization for Blocked Floating-Point Matrix Multiplication
A middleware component supporting flexible user interaction for networked home appliances
A Case Study of FPGA Blokus Duo Solver by System-Level Design
Book review: Computation Structures by Stephen A Ward and Robert H. Halstead, Jr. (MIT Press or McGraw-Hill, 1990)
On the use of benchmarks for measuring system performance
Just what is an op-code?: or a universal computer design
Book Review: Alpha Implementations and Architecture by Dileep P. Bhandarkar
Disbursed control computer architecture
A class of replacement policies for medium and high-associativity structures
A case for the multithreaded processor architecture
Process exchange on the PR1ME family of computers
Session details: Book reviews
Customisable pipelined engine for intensity evaluation in multivariate hawkes point processes
Object-oriented computer architectures for new generation of applications
High efficiency MAC unit used in digital signal processing and elliptic curve cryptography
Towards an efficient, dedicated architecture for a Digital Geometric Image Transformer (DGIT)
Introduction to the Special Issue on Input/Output in Parallel Computer Systems
The case for the reduced instruction set computer
An evaluation of code space requirements and performance of various architectures
Considerations on the "figure of merit" technique for storage hierarchy design
Introduction to the special issue on the 2008 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'08)
The MC88110 implementation of precise exceptions in a superscalar architecture
A hardware/software framework for supporting transactional memory in a MPSoC environment
Optimal dimension of hypercubes for sorting
Bibliography and reading on CPU cache memories and related topics
MEmory performance: DEaling with applications, systems and architecture
Improving memory system performance with energy-efficient value speculation
Collective Communication on FPGA Clusters with Static Scheduling
Cost-Effective and High-Throughput Merge Network: Architecture for the Fastest FPGA Sorting Accelerator
Are multiport memories physically feasible?
Hardware-software co-design of embedded sensor-actuator networks
SPEC CPU2006 benchmark tools
Physical limitations of a computer
An improved conditional branching scheme for a single instruction computer architecture
Review of "Computer Design Development: Principal Papers by Earl E. Swartzlander, Jr., (ed)", Hayden Book Company, Inc., 1976
An improved index function for (D)FCM predictors
A cost-effective approach to implement a long instruction word microprrocessor
Reduced register saving/restoring in single-window register files
A reduced register file for RISC architectures
Systematic evaluation of workload clustering for extremely energy-efficient architectures
A sequencing-based taxonomy of I/0 systems and review of historical machines
Energy-efficient instruction scheduling utilizing cache miss information
An annotated bibliography on reduced instruction set computers
Entangled-Coupling
Preventing timing errors on register writes: mechanisms of detections and recoveries
Processor networks and interconnection networks without long wires (extended abstract)
Design of a high level language machine
Implementing microprogram storage with PLA's
Analysis of simulation-adapted SPEC 2000 benchmarks
Programming framework for clusters with heterogeneous accelerators
LRU-based column-associative caches
Semiconductor technology: trends and implications
Book review: Highly Parallel Computing by George Almasi and Allan Gotlieb (Benjamin/Cummings, 1989)
Overview of concert multilisp: a multiprocessor symbolic computing system
Using cache line coloring to perform aggressive procedure inlining
Ambiguous machine architecture and program efficiency
The control mechanism for the Myrias parallel computer system
Logic and conflict-free vector addresses
A compiler optimization paradigm for dynamic energy management
A methodology for performance evaluation of systems with large emulation code
Power profiling and optimization for heterogeneous multi-core systems
Extraction of massive instruction level parallelism
Dynamic RAM for on-chip instruction caches
On minimizing contention at semaphores
NPCryptBench: a cryptographic benchmark suite for network processors
An address gneration unit for array accessing
A review of Dynamic memories with enhanced data access by Harold S. Stone. IEEETC Vol. C-21, #4, p 359-386, April 1972
A combined register-stack architecture
A memory controller executing segment operations in time 0(1)
Performance characteristics of the SPEC OMP2001 benchmarks
A note on "Diagnosabilities of hypercubes under the pessimistic one-step diagnosis strategy"
AADC computer family architecture program
Completing an MIMD multiprocessor taxonomy
Modelling and performance evaluation of multiprocessors organization with shared memories
Time-sequenced DMA for multimedia computers
Hardware/software tradeoffs: a general design principle?
Translation buffer performance in a UNIX enviroment
The Flex architecture, a high speed graphics processor
An FPGA-based scalable simulation accelerator for tile architectures
War of the benchmark means: time for a truce
A reconfigurable Java accelerator with software compatibility for embedded systems
An overview of the A architecture for optimisation problems in a logic programming environment
Dynamically configurable shared CMP helper engines for improved performance
An overview of the PRISM project
Instruction-level parallelism from execution interlock collapsing
A case for shared instruction cache on chip multiprocessors running OLTP
Conference report: IEEE 1'st Int'l conference on neural networks
Usenet nuggets
Review of Microcomputer interfacing by G. Jack Lipovski. Lexington Books 1980
On sorting and load balancing on GPUs
Direct execution lisp and cell memory
Architectural innovation round: round #3
The case against stack-oriented instruction sets
The computing memory another distributed computer architecture
Book Reviews: Principles of Computer Systems by Gerald M. Karam & John C. Bryant: (Prentice Hall 1992)
Scalable directory architecture for distributed shared memory chip multiprocessors
Multitasking workload scheduling on flexible core chip multiprocessors
TUKI: a data flow processor
YACKOS on a shared-memory multiprocessor
An educational tool for testing hierarchical multilevel caches
NCBI BLASTP on the convey HC1-EX
Look-ahead branching hardware
Book review: The Impact of Vector and Parallel Architectures on the Gaussian Elimination Algorithm by Yves Robert (Manchester University Press and Halsted Press, 1991)
Energy-security tradeoff in a secure cache architecture against buffer overflow attacks
Evaluating the correspondence between training and reference workloads in SPEC CPU2006
Performance Analysis of the Multi-GPU System with ExpEther
Performance of various computers using standard linear equations software
Multiple instructions/operands per access to cache memory
VAX floating point: a solid foundation for numerical computation
A question of semantics
On a wideband fast fourier transform for a radio telescope
Out-of-order execution in sequentially consistent shared-memory systems
Performance variation across benchmark suites
Suggested enhancements to the Motorola MC68000
Low cost trace-driven memory simulation using SimPoint
A low-cost usage-based replacement algorithm for cache memories
Rivalling multiprocessor organization: a hardware/speed trade-off
CEDAR: a large scale multiprocessor
A combined compiler and architecture technique to control multithreaded execution of branches and loop iterations
Book review: Supercomputer Architectures by Paul B. Schneck (Kluwer Academic Publishers)
MPTLsim: a cycle-accurate, full-system simulator for x86-64 multicore architectures with coherent caches
Evolutionary computer architecture: the unidata 7.000 series
Efficient data sharing with conditional remote memory transfers
A Memory Profiling Framework for Stencil Computation on an FPGA Accelerator with High Level Synthesis
A simple architecture for constant time sorting machines
Interpreting benchmarks
PASTIS: a photonic arbitration with scalable token injection scheme
An introduction to CHDL (computer hardware description languages)
An alternative to branch prediction: pre-computed branches
On the potential of asynchronous pipelined processors
Subsetting the SPEC CPU2006 benchmark suite
The harmonic or geometric mean: does it really matter?
Cache performance for selected SPEC CPU2000 benchmarks
A trace-driven simulation methodology
Leakage-saving opportunities in mesh-based massive multi-core architectures
FPGA-based Volleyball Player Tracker
Computing in three dimensions
An experimental active memory based I/O subsystem
Intelligent memory: "a parallel processing concept"
Announcing the 2012 Edsger W. Dijkstra prize in distributed computing
Review of Processor architecture by S. H. Lavington. NCC Publications, Manchester 1976
An integrated development platform of a reconfigurable radio processor for software defined radio
A code-splitting algorithm
A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays
Book review: Optimizing FORTRAN Programs by C. F. Schofield (Halstead Press, 1989)
The design and development of a dynamic program behavior measurement tool for the Intel 8086/88
Software-based branch predication for AMD GPUs
ARPS: a new real-time computer
Towards guidelines for SIGARCH sponsored conferences
Introduction to routing in multicomputer networks
Architectural support for protecting user privacy on trusted processors
A coment on "A hardware unification unit: design and analysis, "
An efficient CELL library for lattice quantum chromodynamics
DR-nets: data-reconstruction networks for highly reliable parallel-disk systems
A graphical comparison of RISC processors
An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering for FPGA Debug
Massage-passing controllerr for a shared-memory multiprocessor
I/O potholes
On computer architecture, software portability & microprogramming
Comments on "the case for the reduced instruction set computer, " by Patterson and Ditzel
Hardware speedups in long integer multiplication
A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors
Software for neural networks
Breadth First Search on Cost-efficient Multi-GPU Systems
SIMD machines: do they have a significant future?
A forward-looking method of Cache memory control
Something old: the Gamma 60 the computer that was ahead of its time
High speed residue number system (RNS) based FIR filter using distributed arithmetic (DA)
Microprogramming with a content-addressable read-only-memory
A progress report on SPUR: February 1, 1987
Address and data register separation on the M68000 family
Working set prefetching for cache memories
FLIP-FLOP: a stack-oriented multiprocessing system
The implementation of an SVP many-core processor and the evaluation of its memory architecture
Review of Structured computer organization by Andrew S. Tanenbaum. Prentice-Hall 1976
Data interfaces versus control interfaces: a half-baked conjecture
Adding concurrency in python using a commercial processor's hardware transactional memory support
SP-NUCA: a cost effective dynamic non-uniform cache architecture
Correction to RAMpage ASPOLOS paper
Multiprocessor architectures for concurrent programs
Book review: Solving Problems on Concurrent Processors, Vol II: Software for Concurrent Processors by I. Angus, G. Fox, J. Kim, and D. Walker (Prentice-Hall, 1990)
On interprocess interaction in distributed architectures
Dynamic vectorization in the E2 dynamic multicore architecture
Exploiting the replication cache to improve performance for multiple-issue microprocessors
A restricted crossbar implementation and its applications
Optimal pipeline depth with pipeline stage unification adoption
A run-time reconfigurable system for adaptive high performance efficient computing
Multiprocessors with a serial multiport memory and a pseudo crossbar of serial links used s a processor-memeory switch
Book review: A VLSI Architecture for Concurrent Data Structures by William J. Dally (Kluwer 1988)
Mesh-based many-core performance under process variations: a core yield perspective
Optimization and precise exceptions in dynamic compilation
Three levels three dimensional compact coding
Secretary/Treasurer's Report
Preface to the Special Issue on Architectural Support for Operating Systems
Methodology for designing a computer architecture
More enhancements of the simplescalar tool set
Supercomputing: big bang or steady state growth?
The RASE (Rapid, Accurate Simulation Environment) for chip multiprocessors
An implementation independent approach to cache memories
A Tree Structured Architecture for semantic gap reduction
A modified architecture for high-density MRAM
Architectural and implementation issues for multithreading (panel session I)
Re-evaluation of the RISC I
Book review: Memory Storage Patterns in Parallel Processing by Mary A. Mace (Kluwer Academic Publishers, Boston, 1987, 139 pp.)
A discussion on calculating eigenvalues of real symmetric tridiagonal matrices on a GPU
The case for SRAM main memory
A biologically plausible real-time spiking neuron simulation environment based on a multiple-FPGA platform
Custom code generation for soft processors
A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation
Improving energy saving in hard real time systems via a modified dual priority scheduling
Technologies for low latency interconnection switches
Evolution of the Harris H-series computers and speculations on their future
Book review: Multiprocessor Performance by Erol Gelenbe (J. Wiley & Sons, Chichester, England)
Data threaded microarchitecture
Interface Based Memory Synthesis of Image Processing Applications in FPGA
Algorithms: Recent Highlights and Challenges
An overview of the Kyushu University reconfigurable parallel processor
Fair dynamic arbitration for a multiprocessor communications bus
Just a few more words on microprocessors of the future
Design of a distributed system support based on a centralized parallel bus
Method manipulation in an object-oriented processor
Some innovations in computer architecture
Superscalar vs. superpipelined machines
A lightweight streaming layer for multicore execution
Reducing stack usage in Java bytecode execution
CPU2006 working set size
Innovative architectures and commercial computers: a summary of the panel discussion at NCC 1981
Exploring the cache design space for large scale CMPs
A computer architecture with access control and cache option tags on individual instruction operands
An implementation of out-of-order execution system for acceleration of computational fluid dynamics on FPGAs
Structured machine design: an ongoing experiment
Hardware-modulated parallelism in chip multiprocessors
Microseqencer architecture supporting arbitrary branching up to 2m targets
Migration of long-running Tasks between Reconfigurable Resources using Virtualization
Register windows
A transputer T9000 family based architecture for parallel database machines
VCLEARIT: a VLSI CMOS circuit leakage reduction technique for nanoscale technologies
The Ultrasmall soft processor
Optimized on-chip pipelining of memory-intensive computations on the cell BE
Performance of various computers using standard linear equations software in a FORTRAN environment
The effect of compiler-flag tuning on SPEC benchmark performance
A new index mode for the VAX-11
Non-blocking programming on multi-core graphics processors: (extended asbtract)
Software-controlled on-chip memory for high-performance and low-power computing
Resources instead of cores?
Dissecting Cyclops: a detailed analysis of a multithreaded architecture
More on the use of stacks in the evaluation of expressions
Protecting cryptographic keys and computations via virtual secure coprocessing
Security in autonomic computing
Errata: A hardware support mechanism for scheduling resources in parallel machine environment: (from Proceedings of the 8th Annual Symposium on Computer Architecture, p. 57)
The predictability of load address
The LDF 100: a large grain dataflow parallel processor
ChipLock: support for secure microarchitectures
High performance MAC unit for DSP and cryptographic applications
Design and simulation of MAC unit using combinational circuit and adder
Architecture quality
Some remarks on direct execution computers
On the evaluation of expressions using accumulators, stacks and store-to-store instructions
Load-store optimization for software pipelining
Structured design for structured computer architecture
Performance evaluation of two operating systems
Qualitatively matching computer architecture with Turing machine
A study of MIPS programs
Review of Microprogramming primer by Harry Katzan, Jr. McGraw-Hill 1977
A new non-exact Aho-Corasick framework for ECG classification
Treasurer's report
Amdahl's law for predicting the future of multicores considered harmful
A rider to "A Question of Semantics"
Book review: Past, Present, Parallel: A Survey of Available Parallel Computing Systems by Arthur Trew & Greg Wilson (Eds.), (Springer-Verlag 1991)
Report on the panel: "how can computer architecture researchers avoid becoming the society for irreproducible results?"
Register windows and delay slots
Compilation of out-of-core data parallel programs for distributed memory machines
Multithreading decoupled architectures for complexity-effective general purpose computing
Efficient encoding of machine instructions
Recent doctoral dissertations of interest to SIGARCH
Constructing instruction traces from cache-filtered address traces (CITCAT)
A general framework to build new CPUs by mapping abstract machine code to instruction level parallel execution hardware
Energy saving through a simple load control mechanism
Using instruction block signatures to counter code injection attacks
Hardware support for software controlled multithreading
On the use of SPEC benchmarks in computer architecture research
The microprocessors of the future
Word length of a computer architecture definitions and applications
A survey of commercial parallel processors
ALITER: an asynchronous lightweight instrumentation tool for event recording
The Leopard workstation project
Fine-grain compensation method with consideration of trade-offs between computation and data transfer for power consumption
Exploiting memory affinity in OpenMP through schedule reuse
Architectural assistance to software debugging aids
A canonic interpretive program form for measuring "ideal" HLL architectures
Something new: the Intel MCS-4 micro computer set
Stack and RISC
Book review: Advanced Research in VLSI, edited by Charles L. Seitz (The MIT Press, Cambridge, MA, 1989, 373 pp.)
A massively parallel and distributed I/O subsystem
Off-Loading LET Generation to PEACH2: A Switching Hub for High Performance GPU Clusters
The protection of the processor status word of the PDP-11/60
Deterministic high-speed root-hashing automaton matching coprocessor for embedded network processor
Book review: High-Level Language Computer Architecture edited by Veljko Milutinovic (Computer Science Press, 1989)
The dataflow architecture: a suitable base for the implementation of expert systems
A RISC processor architecture with a versatile stack system
RISC versus CISC: a tale of two chips
SPLASH: Stanford parallel applications for shared-memory
Achieving the best performance on superscalar processors
FPGA-based Custom Computing Architecture for Large-Scale Fluid Simulation with Building Cube Method
On a "Counter - Example"
Multipliers for floating-point double precision and beyond on FPGAs
A case for uniform memory access multiprocessors
What is scalability?
The end of architecture
Novel Three-Dimensional Embedded FPGA Technology and Achitecture
PARSEC3.0: A Multicore Benchmark Suite with Network Stacks and SPLASH-2X
0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI
On the design of Always Compatible Instruction Set Architecture(ACISA)
Book review: Multiprocessors by D. Tabak (Prentice-Hall, 1990)
Errata for two publications
A recursively microcodable tagged architecture
An efficient synchronization technique for multiprocessor systems on-chip
Leakage energy reduction in cache memory by data compression
Data security-modified AES algorithm and its applications
FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels
A national trace collection and distribution resource
Amorphous computer system architecture: a preliminary look
A new high radix-2 r (r≥8) multibit recoding algorithm for large operand size (N≥32) multipliers
Hardware Resources: a generalizing view on computer architectures
Balancing disk access times in RAID5 disk arrays in degraded mode by conditionally prioritizing fork/join requests
Lightweight monitor for Java VM
The BLIZZARD computer architecture
Instruction looping, an extension to conditional execution
Long-latency branches: how much do they matter?
Computer design evaluation using programming language primitives
A reliable return address stack: microarchitectural features to defeat stack smashing
Parallel Genetic Algorithms on Multiple FPGAs
Review of Parallel execution of logic programs by John Conery. Kluwer Academic Publishers 1987
LFTHREADS: a lock-free thread library
Emerging opportunities for binary tools
100 GOPS vision processor for automotive applications
Preface to the Special issue on Neural Networks
PASM: a reconfigurable parallel system for image processing
Secure system architecture
Technical overview of the Renaissance Octobus system
Cache design with path balancing table, skewing and indirect tags
Introduction to the special issue on the 2006 workshop on design, analysis, and simulation of chip multiprocessors: (dasCMP'06)
GPU accelerated CAE using open solvers and the cloud
An architecture design system
Main frame computer trends
On non-numeric architecture
Is 32 bits of address too much?
Hitting the memory wall: implications of the obvious
Why specialized disks for composite operations may be unnecessary
Throughput in a counterflow pipeline processor
IOStone: a synthetic file system benchmark
Response to the collapsed LAN
Probabilistic memory disambiguation and its application to data speculation
Unified scalable shared memory architectures
Primitive based architectures
Instruction-path coprocessing to solve some RISC problems
Function level parallelism driven by data dependencies
The Wisconsin Wind Tunnel project: an annotated bibliography
Review of Computer system architecture by M. Morris Mano. Prentice-Hall 1976
Addressing operations for automatic data structure accessing
Cache memory for microprocessors
Letter to membership from incoming chairman (CAN, Oct. 73)