yusuke1997/dblp-id-title huggingface dataset:
FastRoute: An Efficient and High-Quality Global Router
On-Chip Power Minimization Using Serialization-Widening with Frequent Value Encoding
Simulation of Optoelectronic Devices
Improved Switching Energy Reduction Approach in Low-Power SAR ADC for Bioelectronics
VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards
Generalized Inclusive Forms - New Canonical Reed-Muller Forms Including Minimum ESOPs
Resonant Tunneling in the Quantum Hydrodynamic Model
Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs
Electron Transport Using the Quantum Corrected Hydrodynamic Equations
Block-Level Logic Extraction from CMOS VLSI Layouts
Selected Papers from the International Mixed Signals Testing and GHz/Gbps Test Workshop
Integrated On-Line and Off-Line Error Detection Mechanisms in the Coding Theory Framework
Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor
Automatic Test Timing Assignment for RAMs Using Linear Programming
Consistent Hydrodynamic and Monte-Carlo Simulation of SiGe HBTs Based on Table Models the Relaxation Times
Application of Dynamic Supply Current Monitoring to Testing Mixed-Signal Circuits
Self-consistent Full-band Modeling of Quantum Semiconductor Nanostructures
Integrated VCOs for Medical Implant Transceivers
A Fast Algorithm for the Study of Wave-packet Scattering at Disordered Interfaces
Operational and Test Performance in the Presence of Built-in Current Sensors
Monte Carlo Simulations of High Field Transport in Electroluminescent Devices
Simplex Algorithm for Band Structure Calculation of Noncubic Symmetry Semiconductors: Application to III-nitride Binaries and Alloys
A SiGe BiCMOS Instrumentation Channel for Extreme Environment Applications
High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling
Optical and Electronic Properties of Semiconductor 2D Nanosystems: Self-consistent Tight-binding Calculations
Word-serial Architectures for Filtering and Variable Rate Decimation
A VLSI Design for Implementation of Transform Domain Adaptive Filters
Computation Reordering: A Novel Transformation for Low Power DSP Synthesis
The Chapman-Enskog Expansion and the Quantum Hydrodynamic Model for Semiconductor Devices
Low Power Design for ASIC Cores
A Signature-Based Power Model for MPSoC on FPGA
An ILP Formulation for Minimizing the Number of Feedthrough Cells in a Standard Cell Placement
Modeling of Poly-Silicon Carrier Transport with Explicit Treatment of Grains and Grain Boundaries
Molecular Wire Interconnects: Chemical Structural Control, Resonant Tunneling and Length Dependence
Greedy Segmented Channel Router
Optimizing Energy During Systems Synthesis of Computer Intensive Realtime Applications
Total Dielectric Function Approach to the Electron Boltzmann Equation for Scattering from a Two-Dimensional Coupled Mode System
Parallel Computation for Electronic Waves in Quantum Corrals
Numerical Studies of Miniband Conduction in Quasi-One-Dimensional Superlattices
Weighted Transition Based Reordering, Columnwise Bit Filling, and Difference Vector: A Power-Aware Test Data Compression Method
Soft Sphere Model for Electron Correlation and Scattering in the Atomistic Modelling of Semiconductor Devices
A Novel Scan Architecture for Low Power Scan-Based Testing
The Single Row Routing Problem Revisited: A Solution Based on Genetic Algorithms
Recent Advances in Device Simulation Using Standard Transport Models
Low-Area Wallace Multiplier
Advanced VLSI Design Methodologies for Emerging Industrial Multimedia and Communication Applications
Topologically Rectangular Grids in the Parallel Simulation of Semiconductor Devices
The Coupled Optoelectronic Problems of Quantum Well Laser Operation
Corrections to the Capacitance between Two Electrodes Due to the Presence of Quantum Confined System
An Effective Solution to the Linear Placement Problem
CAD for Gigascale SoC Design and Verification Solutions
Distributed and Parallel Demand Driven Logic Simulation Algorithms
Execution of VHDL Models Using Parallel Discrete Event Simulation Algorithms
Minimizing Spurious Switching Activities with Transistor Sizing
On Generating Optimal Signal Probabilities for Random Tests: A Genetic Approach
Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation
Choice of a High-Level Fault Model for the Optimization of Validation Test Set Reused for Manufacturing Test
STD Architecture: A Practical Approach to Test M-Bits Random Access Memories
Numerically Absorbing Boundary Conditions for Quantum Evolution Equations
Self-checking Synchronous FSM Network Design with Low Overhead
Quantum Transport Modeling of Current Noise in Quantum Devices
Power Considerations in Banked CAMs: A Leakage Reduction Approach
Smooth Quantum Hydrodynamic Model Simulation of the Resonant Tunneling Diode
Investigating Memory System Energy Behavior Using Software and Hardware Optimizations
An Evaluation of Parallel Synchronous and Conservative Asynchronous Logic-Level Simulations
The Response of the Hydrodynamic Model to Heat Conduction, Mobility, and Relaxation Expressions
Signature Analysis for Test Responses of Sequential Circuits
Tabu Search: A Meta Heuristic for Netlist Partitioning
Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs
A Novel Time Synchronization Method for Dynamic Reconfigurable Bus
3D Simulations of Ultra-small MOSFETs with Real-space Treatment of the Electron - Electron and Electron-ion Interactions
Monte Carlo Calibrated Drift-Diffusion Simulation of Short Channel HFETs
Inflow Boundary Conditions in Quantum Transport Theory
A Synthesizable VHDL Model of the Exact Solution for Three-dimensional Hyperbolic Positioning System
Calculation of Transport Parameters of SiO 2 Polymorphs
Wave Pipelining Using Self Reset Logic
Spherical Harmonic Modeling of a 0.05 μm Base BJT: A Comparison with Monte Carlo and Asymptotic Analysis
Energy-Efficient Hardware Architectures for the Packet Data Convergence Protocol in LTE-Advanced Mobile Terminals
Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations
Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip
Electron-LA Phonon Interaction in a Quantum Dot
9T Full Adder Design in Subthreshold Region
Accurate Power Estimation for Sequential CMOS Circuits Using Graph-based Methods
CONTANGO: Integrated Optimization of SoC Clock Networks
Design Methodology of a 32-bit Arithmetic Logic Unit with an Adaptive Leaf-cell Based Layout Technique
A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays
Low Complexity Submatrix Divided MMSE Sparse-SQRD Detection for MIMO-OFDM with ESPAR Antenna Receiver
3D Parallel Finite Element Simulation of In-Cell Breakdown in Lateral-Channel IGBTs
Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects
2-D Simulation of Quantum Effects in Small Semiconductor Devices Using Quantum Hydrodynamic Equations
Digital Noise Generator Design Using Inverted 1D Tent Chaotic Map
Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method
A Systematic Approach to Reduce the System Bus Load and Power in Multimedia Algorithms
On SPARC LEON-2 ISA Extensions Experiments for MPEG Encoding Acceleration
Monte Carlo Study of the Lateral Distribution of Gate Current Density Along the Channel of Submicron LDD MOSFET's
A New Method for Low Power Design of Two-Level Logic Circuits
Monte Carlo Simulations of Impact Ionization Feedback in MOSFET Structures
Partitionable Bus-based String-matching Algorithm for Run-length Coded Strings With VLDCs
Investigation of Various Mesh Architectures With Broadcast Buses for High-Performance Computing
Simultaneous Switching Noise Minimization Technique Using Dual Layer Power Line Mutual Inductors
Quantum Transport Simulation of the DOS function, Self-Consistent Fields and Mobility in MOS Inversion Layers
Monte Carlo and hydrodynamic simulation of a one dimensional n + - n - n + silicon diode
FPGA Fault Tolerant Arithmetic Logic: A Case Study Using Parallel-Prefix Adders
MOMENTS: The Modular Monte Carlo Environment for Charge Transport Simulation, Overview and Applications
Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool
A Low-Voltage Floating-Gate MOS Biquad
Quantum Transport in Open Nanostructures
Power Analysis of a 32-bit Embedded Microcontroller
Analytic I-V Model for Single-Electron Transistors
A Novel Path Delay Fault Simulator Using Binary Logic
Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture
Fast Inner Product Computation on Short Buses
FSM Decomposition and Functional Verification of FSM Networks
Geometric Design Rule Check of VLSI Layouts in Distributed Computing Environment
Discrete Transparent Boundary Conditions for General Schrödinger-type Equations
Improved Quantization Error Compensation Method for Fixed-Width Booth Multipliers
Performance and Wirability Driven Layout for Row-Based FPGAs
Hydrodynamic Device Simulation with New State Variables Specially Chosen for a Block Gummel Iterative Approach
An Embedded Low Transistor Count 8-bit Analog-to-digital Converter Using a Binary Searching Method
TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing
A Noise-shaping Accelerometer Interface Circuit for Two-chip Implementation
Calibration of a One Dimensional Hydrodynamic Simulator with Monte Carlo Data
On the Use of an Algebraic Signature Analyzer for Mixed-Signal Systems Testing
Deep-submicron Placement Minimizing Crosstalk
Antirandom Testing: A Distance-Based Approach
Monte Carlo Modeling of Wurtzite and 4H Phase Semiconducting Materials
A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips
An Efficient Multi-Core SIMD Implementation for H.264/AVC Encoder
Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies
On Ensuring Multilayer Wirability by Stretching Layouts
A Video Specific Instruction Set Architecture for ASIP design
Buffer Planning for IP Placement Using Sliced-LFF
A Stochastic D/A Converter Based on a Cellular Automaton Architecture
A Novel Net Weighting Algorithm for Power and Timing-Driven Placement
Formulation of a Self-Consistent Model for Quantum Well pin Solar Cells: Dark Behavior
Optimal Testing and Design of Adders
Energy Efficient Signaling in Deep-submicron Technology
A Greedy Algorithm for Over-The-Cell Channel Routing
FPGA-Based Software Implementation of Series Harmonic Compensation for Single Phase Inverters
Conditional Disconnection Probability in Star Graphs
Particle-based Full-band Approach for Fast Simulation of Charge Transport in Si, GaAs, and InP
An Integrated Hardware Array for Very High Speed Logic Simulation
Simulation of Drastic Lag Phenomena in GaAs-Based FETs for Large Voltage Swing
Self-Consistent Calculations of the Ground State and the Capacitance of a 3D Si/SiO 2 Quantum Dot
Design of Smart Power-Saving Architecture for Network on Chip
Simulation of Biological Ionic Channels by Technology Computer-Aided Design
PARTIF: Interactive System-level Partitioning
Numerical Examination of Photon Recycling as an Explanation of Observed Carrier Lifetime in Direct Bandgap Materials
Signal Strength Based Switching Activity Modeling and Estimation for DSP Applications
Crypto-Stego-Real-Time (CSRT) System for Secure Reversible Data Hiding
About the Editor in Chief and the Guest Editor
Self-Healing Many-Core Architecture: Analysis and Evaluation
A 0.6-V to 1-V Audio Delta-Sigma Modulator in 65 nm CMOS with 90.2 dB SNDR at 0.6-V
Flexible Architecture of Ultra-Low-Power Current-Mode Interleaved Successive Approximation Analog-to-Digital Converter for Wireless Sensor Networks
Ensemble Monte Carlo and Full-Wave Electrodynamic Models Implemented Self-Consistently on a Parallel Processor Using Perfectly Matched Layer Boundary Conditions
A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection
Advanced VLSI Architecture Design for Emerging Digital Systems
Reconfigurable Architectures for System Level Applications of Adaptive Computing
Simulated Annealing Approach to Crosstalk Minimization in Gridded Channel Routing
Power-Driven Global Routing for Multisupply Voltage Domains
Writing Research Software in a Large Group for the NEMO Project
Electron Transport In One-Dimensional Magnetic Superlattices
An Efficient Algorithm for the Calculation of Generalized Adding and Arithmetic Transforms From Disjoint Cubes of Boolean Functions
Single-Electron Memories
Maximum Entropy Principle within A Total Energy Scheme for Hot-carrier Transport in Semiconductor Devices
High-Level Graphical Abstraction in Digital Design
Design and Characterization of the Next Generation Nanowire Amplifiers
Shedding Physical Synthesis Area Bloat
Technology Mapping for FPGA Using Generalized Functional Decomposition
Possible Wireless Single-Electron Logic Biased by Electric Field
Low Power VLSI Implementation of the DCT on Single Multiplier DSP Processors
Hydrodynamic (HD) Simulation of N -Channel MOSFET's with a Computationally Efficient Inversion Layer Quantization Model
Two-dimensional Placement Using Tabu Search
Efficient Silicon Device Simulation with the Local Iterative Monte Carlo Method
A Chip for a Routing Table Based on a Novel Modified Trie Algorithm
Linking Behavioral, Structural, and Physical Models of Hardware
Graphical Design Techniques for Fixed-point Multiplication
Monte Carlo Simulation of HEMT based on Self-Consistent Method
Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints
Switch-level Differential Fault Simulation of MOS VLSI Circuits
A Fast and Accurate Method of Power Estimation for Logic Level Networks
An Algorithm Visualization Tool on the Reconfigurable Mesh
Fast and Near-Optimal Timing-Driven Cell Sizing under Cell Area and Leakage Power Constraints Using a Simplified Discrete Network Flow Algorithm
Quantum Corrections to the 'Atomistic' MOSFET Simulations
Advantages of Semiconductor Device Simulator Combining Electromagnetic and Electron Transport Models
Spectral Interpretation and Applications of Decision Diagrams
Monte Carlo Analysis of Anisotropy in the Transport Relaxation Times for the Hydrodynamic Model
SPIN - A Schrödinger-Poisson Solver Including Nonparabolic Bands
A New Characterization Method for Delay and Power Dissipation of Standard Library Cells
Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters
Distributed Algorithms for Three-dimensional Semiconductor Device Simulations
CLOTH MEASURE: A Software Tool for Estimating the Memory Requirements of Corner Stitching Data Structures
Power Efficient Hierarchical Scheduling for DSP Transformations
Combining Technology Mapping With Layout
A High-Throughput, High-Accuracy System-Level Simulation Framework for System on Chips
Quantum Networks: Dynamics of Open Nanostructures
Study of Electron Velocity Overshoot in NMOS Inversion Layers
Beating in the RHEED Intensity Oscillations during Surfactant Mediated GaAs Molecular Beam Epitaxy: Process Physics and Modeling
Phase Space Boundary Conditions and Quantum Device Transport
High Data Rate FinFET On-Off Keying Transmitter for Wireless Capsule Endoscopy
Timing Analysis and Optimization for DSM IC - Guest Editorial
Semiconductor Device Noise Computation Based on the Deterministic Solution of the Poisson and Boltzmann Transport Equations
Self-Checking Combinational Circuits with Unidirectionally Independent Outputs
Design of an Inter-plane Circuit for Clocked PLAs
A Multilevel Congestion-Based Global Router
Study on Possible Double Peaks in Cutoff Frequency Characteristics of AlGaAs/GaAs HBTs by Energy Transport Simulation
Optimization of FIBMOS Through 2D Silvaco ATLAS and 2D Monte Carlo Particle-based Device Simulations
Functional Testbench Qualification by Mutation Analysis
Error Immune Logic for Low-Power Probabilistic Computing
CADRE: A Low-power, Low-EMI DSP Architecture for Digital Mobile Phones
Dynamic Cancellation: Selecting Time Warp Cancellation Strategies at Runtime
On Mixed PTL/Static Logic for Low-power and High-speed Circuits
Boolean Matching Filters Based on Row and Column Weights of Reed-Muller Polarity Coefficient Matrix
Testability Synthesis for Jumping Carry Adders
Optimal Differential Routing based on Finite State Machine Theory
A High Level Synthesis System for VLSI Image Processing Applications
Special Issue on Digital Hardware Testing
Designing Interconnection Networks for Multi-level Packaging
Computation of the Spectral Density of Current Fluctuations in Bulk Silicon Based on the Solution of the Boltzmann Transport Equation
Design and Analysis of Digital Ratioed Compressors for Inner Product Processing
Trade-Off Considerations in Designing Efficient VLSI Feasible Interconnection Networks
Exploiting Sleep Mode for Memory Partitioning and Other Applications
Two Dimensional MESFET Simulation of Transients and Steady State with Kinetic Based Hydrodynamical Models
Hydrodynamic Device Modeling with Band Nonparabolicity
3D Parallel Monte Carlo Simulation of GaAs MESFETs
Power Optimization of Delay Constrained Circuits
Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits
International Conference on Electronics, Circuits, and Systems
Simulation of Widebandgap Multi-Quantum Well Light Emitting Diodes
Theory and Modeling of Lasing Modes in Vertical Cavity Surface Emitting Lasers
Absolute Difference and Low-Power Bus Encoding Method for LCD Digital Display Interfaces
A Modularized Noise Analysis Method with Its Application in Readout Circuit Design
Comparison of Iteration Schemes for the Solution of the Multidimensional Schrödinger-Poisson Equations
Hierarchy of Full Band Structure Models for Monte Carlo Simulation
Behavioral Simulation and Performance Evaluation of Multi-Processor Architectures
Density-functional Based Tight-binding Calculations on Thiophene Polymorphism
High-Field Hole Transport in Strained Si and SiGe by Monte Carlo Simulation: Full Band Versus Analytic Band Models
Statistical Enhancement of Terminal Current Estimation for Monte Carlo Device Simulation
Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications
Discretization of Anisotropic Convection-diffusion Equations, Convective M-matrices and their Iterative Solution
Three-dimensional Statistical Modeling of the Effects of the Random Distribution of Dopants in Deep Sub-micron nMOSFETs
A Low Complexity All-Digital Background Calibration Technique for Time-Interleaved ADCs
Embeddings into Hyper Petersen Networks: Yet Another Hypercube-Like Interconnection Topology
Automatic FSM Synthesis for Low-power Mixed Synchronous/Asynchronous Implementation
A New Self-Consistent 2D Device Simulator Based on Deterministic Solution of the Boltzmann, Poisson and Hole-Continuity Equations
A Study of Transconductance Degradation in HEMT Using a Self-consistent Boltzmann-Poisson-Schrödinger Solver
A New Length-Based Algebraic Multigrid Clustering Algorithm
Model-integrated Tools for the Design of Dynamically Reconfigurable Systems
A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures
Optimization of Fractional-N-PLL Frequency Synthesizer for Power Effective Design
Radix-2 α /4 β Building Blocks for Efficient VLSI's Higher Radices Butterflies Implementation
Reconfigurable Shift Switching Parallel Comparators
Carrier Thermal Conductivity: Analysis and Application to Submicron-Device Simulation
A Comparative Study of Synchronous Clocking Schemes for VLSI Based Systems
Segmented Routing for Speed-Performance and Routability in Field-Programmable Gate Arrays
Modular Scheme for Designing Special Purpose Associative Memories and Beyond
Cognitive Radio RF: Overview and Challenges
Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms
A Self-Reconfigurable Platform for the Implementation of 2D Filterbanks with Real and Complex-Valued Inputs, Outputs, and Filter Coefficients
An Approach for Self-Checking Realization of Interacting Finite State Machines
A Monte Carlo Study of Electron Transport in Silicon nMOSFET Inversion Layers
Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation
Abstract Architecture Representation Using VSPEC
Design of Finite Word Length Linear-Phase FIR Filters in the Logarithmic Number System Domain
An Instruction-Level Power Analysis Model with Data Dependency
SENECA: a New Program for the Analysis of Single-Electron Devices
2D Monte Carlo Simulation of Hole and Electron Transport in Strained Si
Interface Roughness Effects in Ultra-Thin Tunneling Oxides
Influence of BJT Transit Frequency Limit Relation to MOSFET Parameters on the Switching Speed of BiCMOS Digital Circuits
A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems
A New Approach based on Brownian Motion for the Simulation of Ultra-Small Semiconductor Devices
Modeling Nonlinear and Chaotic Dynamics in Semiconductor Device Structures
Quantum Kinetic Transport under High Electric Fields
Building Rectangular Floorplans-A Graph Theoretical Approach
A New HEMT Breakdown Model Incorporating Gate and Thermal Effects
Computational Performance Optimisation for Statistical Analysis of the Effect of Nano-CMOS Variability on Integrated Circuits
Minimization of k -Variable-Mixed-Polarity Reed-Muller Expansions
Analysis and Simulation of Extended Hydrodynamic Models: The Multi-Valley Gunn Oscillator and MESFET Symmetries
Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle
Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits
Moment Closure Hierarchies for the Boltzmann-Poisson Equation
Resolution of Resonances in a General Purpose Quantum Device Simulator (NEMO)
Time-Dependent Solution of a Full Hydrodynamic Model Including Convective Terms and Viscous Effect
Power Consumption Models for Decimation FIR Filters in Multistandard Receivers
SCOAP-based Testability Analysis from Hierarchical Netlists
Gate-Level Circuit Reliability Analysis: A Survey
Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm
A Multi-Terminal Net Router for Field-Programmable Gate Arrays
Transient Analysis of Silicon Devices Using the Hydrodynamic Model
A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture
A Generalized Finite Element Method for Hydrodynamic Modeling of Short-channel Devices
An Optimum Channel Routing Algorithm in the Knock-knee Diagonal Model
VLSI Design Special Issue on Semiconductor Device Modeling
A Time-Consistent Video Segmentation Algorithm Designed for Real-Time Implementation
Flexible LDPC Decoder Architectures
Faster and Energy-Efficient Signed Multipliers
VLSI Implementation of Hybrid Wave-Pipelined 2D DWT Using Lifting Scheme
The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks
Design of CMOS Tunable Image-Rejection Low-Noise Amplifier with Active Inductor
Finding Combined L 1 and Link Metric Shortest Paths in the Presence of Orthogonal Obstacles: A Heuristic Approach
On the Minimum Density Interconnection Tree Problem
An Initialization Technique for the Waveform-Relaxation Circuit Simulation
Scattered Packet Method for the Simulation of the Spatio-temporal Evolution of Local Perturbations
Robustness of Transmultiplexed Images
Investigation of the Local Force Approximation in Numerical Device Simulation by Full-band Monte Carlo Simulation
IWCE-7 Committees
Decomposition and Reduction: General Problem-Solving Paradigms
Partitioning Techniques for Built-In Self-Test Design
Using PDM on Multiport Memory Allocation in Data Path
A New Design Methodology for Two-Dimensional Logic Arrays
Clustering Network Modules with Different Implementations for Delay Minimization
Low Power Digital Multimedia Telecommunication Designs
Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation
Design a Bioamplifier with High CMRR