yusuke1997/dblp-id-title huggingface dataset:
TPPD: Targeted Pseudo Partitioning based Defence for cross-core covert channel attacks
NETMAP: An integrated system for building analog neural networks
Improving Efficiency and Lifetime of Logic-in-Memory by Combining IMPLY and MAGIC Families
Optimizing the performance of in-memory file system by thread scheduling and file migration under NUMA multiprocessor systems
Scheduling and power management in energy harvesting computing systems with real-time constraints
Some issues on management of application connection establishment
VLSI implementation of digit-serial arithmetic modules
An area-efficient VLSI implementation for programmable FIR filters based on a parameterized divide and conquer approach
A generalized approach to real-time, non-intrusive instrumentation and monitoring of standards-based distributed middleware
A worst case timing analysis technique for instruction prefetch buffers
An overview of interrupt accounting techniques for multiprocessor real-time systems
The algebraic data type specification language
Generation of firmwarecompilers
LAG-based schedulability analysis for preemptive global EDF scheduling with dynamic cache allocation
Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip
Coordinated management of hardware and software self-adaptivity
Lightweight asynchronous scheduling in heterogeneous reconfigurable systems
Preemptive transaction scheduling in hard real-time database systems
Task migration in n-dimensional wormhole-routed mesh multicomputers
The OTTER environment for resolution-based proof of hardware correctness
Queue assignment for fixed-priority real-time flows in time-sensitive networks: Hardness and algorithm
Algorithm-architecture co-design by example: a coprocessor for on-line arithmetic
An energy-efficient system on a programmable chip platform for cloud applications
Petri net-based analysis on object assignment in distributed object-oriented systems
Digital neural network system based in new concepts on the recall phase dynamics
An application of petri-nets in the control system of the FTC
URMILA: Dynamically trading-off fog and edge resources for performance and mobility-aware IoT services
Control store minimization on the design of microprogrammed controllers
Providing circuit service over a high speed deflection network
C2AADL_Reverse: A model-driven reverse engineering approach to development and verification of safety-critical software
IoTSim-Osmosis: A framework for modeling and simulating IoT applications over an edge-cloud continuum
Analysis of a shared-memory multiprocessor via a novel queuing model
Architecture and implementation method of real-time recovery in distributed systems
A case study for risk assessment in AR-equipped socio-technical systems
Active and passive virtual machine introspection on AMD and ARM processors
Transferable universal adversarial attack against 3D object detection with latent feature disruption
Some results in GaAs processor design using LSI integrated circuits
Packet priority assignment for wireless control systems of multiple physical systems
Integrated dynamic scheduling of hard and QoS degradable real-time tasks in multiprocessor systems
A voice spoofing detection framework for IoT systems with feature pyramid and online knowledge distillation
Efficient and accurate identification of missing tags for large-scale dynamic RFID systems
Constructive evaluation of computer architectures: A CAD approach
Bit-serial VLSI sorter with high reliability specifications
Secure service orchestration in open networks
An experimental analysis of event set algorithms for discrete event simulation
Anomaly detection based on multi-teacher knowledge distillation
Design and evaluation of access method for multi-dimensional objects in spatial databases
LNNet: Lightweight Nested Network for motion deblurring
CADL - A formal description language for parallel computer architectures
A transputer based implementation of the VOXAR project
Embedding trees in massively parallel computers
Allocation of precedence-constrained tasks to parallel processors for optimal execution
Parallel processing: Transputers I
Optimization of block-scaled integer GeMMs for efficient DNN deployment on scalable in-order vector processors
Hardware/Software Co-design for spike communication optimization: Leveraging neuron-level communication patterns
Formal verification and empirical analysis of rollback relaxation
Hierarchical partitioning algorithm for optimistic distributed simulation of DEVS models
Error detection in serial multipliers and in systolic arrays: An approach based upon A★N codes
A Maude-Based rewriting approach to model and verify Cloud/Fog self-adaptation and orchestration
A load balancing system for unix-based local area networks
MARTE profile extension for modeling dynamic power management of embedded systems
Multiple-path execution for chip multiprocessors
Hierarchical energy monitoring for task mapping in many-core systems
Real-time multimedia standards in DQDB
Improving schedulability and energy efficiency for window-constrained real-time systems with reliability requirement
Arco: A cost-effective and flexible hardware maze router
Configurable folded array for FIR filtering
gRemote: Cloud rendering on GPU resource pool based on API-forwarding
Session G1: Control applications
A lightweight key management scheme for key-escrow-free ECC-based CP-ABE for IoT healthcare systems
A low energy cache design for multimedia applications exploiting set access locality
A digital method of demodulation and filtering for angular errors in conical scan tracking radars
Hypercube structures with high-connectivity supporting nodes
Methods to improve performance of instruction prefetching through balanced improvement of two primary performance factors
Behavioral test generation for the selection of BIST logic
A survey on fault-tolerant application mapping techniques for Network-on-Chip
A secure data sharing scheme based on searchable public key encryption for authorized multi-receiver
A convertible neural processor supporting adaptive quantization for real-time neural networks
Comparative analysis of two different middleware approaches for reconfiguration of distributed real-time systems
Floating point acceleration in massively parallel architectures
More on rearrangeability of combined (2n
GAROS: Genetic algorithm-aided row-skipping for shift and duplicate kernel mapping in processing-in-memory architectures
Video action recognition with visual privacy protection based on compressed sensing
VOXEL based modeling and rendering irregular solids
A real-time perspective of service composition: Key concepts and some contributions
A survey on modeling and model-driven engineering practices in the embedded software industry
Robust communication-efficient decentralized learning with heterogeneity
Network-on-Chip virtualization in Chip-Multiprocessor Systems
Building an expert system for software quality evaluation
Formal conversion between LOTOS specification and Galileo nets
FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques
Microcomputer technique for optimum design of centrifugal pumps
Discovering the software process by means of stochastic workflow analysis
Autonomous temperature sensing for optical network-on-chip
Adaptive response time control for metadata matching in information dissemination systems
A construction database model
Cost-effective WDM broadcast-and-select networks for all-to-all transmission schedules
Session H1: Quality control
Modeling and formal verification of embedded systems based on a Petri net representation
Test strategy for indeterministic protocols
A real-time oriented system for vehicle detection
Concurrently self-checking structures for Fsms
Blockchain-enabled one-to-many searchable encryption supporting designated server and multi-keywords for Cloud-IoMT
Real-time specification using Petri nets
Design and performance analysis of the Practical Fat Tree Network using a butterfly network
Linear testability conditions for two-dimensional arrays
Inserting state restoration requests in systems of distributed processes
Secure content based image retrieval for mobile users with deep neural networks in the cloud
Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform
BRISC: A RISC biprocessor architecture dedicated to power applications
Multi-port abstraction layer for FPGA intensive memory exploitation applications
Communicating across parallel message-passing environments
PQ-PIM: A pruning-quantization joint optimization framework for ReRAM-based processing-in-memory DNN accelerator
Enhanced systolic array implementations of some graph problems
Advanced workstation cluster architectures for parallel computing
GHVSA: Graph-based high-dimensional vector search accelerator
The design of time-critical conversations
Simple transformation rules in the application of transputers to the physiological processing of speech
Scalability in real-time systems with end-to-end requirements
A novel 3-D FPGA architecture targeting communication intensive applications
An empirical study of automatic restructuring of vision programs for simd machines
Exploring energy efficiency of LSTM accelerators: A parameterized architecture design for embedded FPGAs
A survey and experimental analysis of checkpointing techniques for energy harvesting devices
Stochastic force sensing application in robotics
A revocable and comparable attribute-based signature scheme from lattices for IoMT
Two language levels for system programming
High level architectural synthesis: Precedence analysis and automatic cycle detection in data flow graphs
A Force-Directed Scheduling based architecture generation algorithm and design tool for FPGAs
On the merits of hypermeshes and tori with adaptive routing
Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms
Hardware/software partitioning aiming at fulfilment of real-time constraints
Computing the correct Increment of Induction Pointers with application to loop unrolling
A parallel computer based on simple DSP modules
Last level cache layout remapping for heterogeneous systems
Sokrates-SA - A formal method for specifying real-time systems
Autoware_Perf: A tracing and performance analysis framework for ROS 2 applications
A new approach to evaluating internal Xilinx FPGA resources
Rust-Shyper: A reliable embedded hypervisor supporting VM migration and hypervisor live-update
Motivations and measurements in an agile case study
DSSE-DMVS: A blockchain-based dynamic searchable symmetric encryption supporting multi-keyword queries and data deduplication
Architectural designs for a scalable reconfigurable IP router
Evolving good hierarchical decompositions of complex systems
A note on self-stabilizing articulation point detection
Asynchronous Process Simulator for Parallel Systems (APSPS) 1
Switch fabric architecture analysis for a scalable bi-directionally reconfigurable IP router
Enhancing the fuzzy set model for high quality document rankings
Trustworthy self-optimization for organic computing environments using multiple simultaneous requests
Efficient drone hijacking detection using two-step GA-XGBoost
Design method, fail-stop safety model, and embedded application
Usability study of a smart toy on students with intellectual disabilities
GTA: Generating high-performance tensorized program with dual-task scheduling
Reconciling chained and unchained transactional support for distributed systems
Exploiting equilateral-triangular architectures for VLSI systolic implementation
Contribution to the design of a CMOS image sensor with low-complexity video compression for wireless sensor networks
IOTSim: A simulator for analysing IoT applications
Dual and multiple token based approaches for load balancing
FSM fault models impact on test performances
Interconnect intellectual property for Network-on-Chip (NoC)
Utility-driven renewable energy sharing systems for community microgrid
Performance impact of run queue organization and synchronization on large-scale NUMA multiprocessor systems
On supporting rapid exploration of memory hierarchies onto FPGAs
LIMES - LearnIng Module EStimation
Predicting performance in multi-core systems with shared reconfigurable accelerators
A reconfigurable modular fault tolerant generalized Boolean n-cube network
WCET analysis of instruction cache hierarchies
Response-time analysis of mesh-based many-core systems
Partitioned algorithms for gaussian elimination on reconfigurable processor arrays
A memory footprint optimization framework for Python applications targeting edge devices
Synthesis of quaternary reversible/quantum comparators
Accurate and efficient processor performance prediction via regression tree based modeling
Special issue on design of embedded software and systems (SI: ICESS19)
PUMA: Hardware support for fault-tolerance and object-oriented programming
Verification methods for VHDL RTL-subroutines
An automatic computer vision system for blood analysis
Cube-connected-cubes network
Scheduling problems in general purpose massively parallel systems
Task allocation, migration and scheduling for energy-efficient real-time multiprocessor architectures
Schedulability analysis and stack size minimization for adaptive mixed criticality scheduling with semi-Clairvoyance and preemption thresholds
PET, a software monitoring toolkit for performance analysis of parallel embedded applications
Two-level branch prediction using neural networks
Scheduling length for switching element disjoint multicasting in Banyan-type switching networks
A survey on privacy preservation techniques for blockchain interoperability
Efficient control generation for mapping nested loop programs onto processor arrays
A design concept for verified concurrent controllers
Multiresolution analysis and denoising of computer performance evaluation data with the wavelet transform
Activity pre-scheduling for run-time optimization of grid workflows
Session E4: Hardware description languages
A flocking based algorithm for document clustering analysis
Scope-aware data cache analysis for OpenMP programs on multi-core processors
Runtime observation of functional safety properties in an automotive control network
Session D2: Fault tolerant parallel software
A design methodology for the correct specification of VLSI systems
Fully homomorphic encryption-based privacy-preserving scheme for cross edge blockchain network
A prototype rule-based system to schedule production for a job-shop
ClarifyNet: A high-pass and low-pass filtering based CNN for single image dehazing
VLSI-/370 microprocessor overview
Verification and validation of hierarchical CMOS gate array layouts
Design and development of industrial measurement system - Architecture and software
A case study in the migration of software to hardware using basics
mcfTRaptor: Toward unobtrusive on-the-fly control-flow tracing in multicores
MEALPY: An open-source library for latest meta-heuristic algorithms in Python
A general purpose communications shell for a network of transputers
A cache-aware DAG scheduling method on multicores: Exploiting node affinity and deferred executions
High level modeling and automated generation of heterogeneous SoC architectures with optimized custom reconfigurable cores and on-chip communication media
Low power high-performance smart camera system based on SCAMP vision sensor
Towards functional safety compliance of matrix-matrix multiplication for machine learning-based autonomous systems
Holistic schedulability analysis for distributed hard real-time systems
System level VLSI design
Testability of non-trivial CMOS faults under realistic conditions
An efficient and access policy-hiding keyword search and data sharing scheme in cloud-assisted IoT
Quantitative analysis of packet-processing applications regarding architectural guidelines for network-processing-engine development
High-speed parallel implementation of the statistical feature matrix method
Addressing mechanisms for VLIW and superscalar processors
Applying link stability estimation mechanism to multicast routing in MANETs
THAMON: Thermal-aware High-performance Application Mapping onto Opto-electrical network-on-chip
Corrigendum to "Reliability and Test Effort Analysis of Multi-Sensor Driver Assistance Systems" [Journal of Systems Architecture 85-86 (2018) 1-13]
Structured segment rescaling with Gaussian processes for parameter efficient ConvNets
Transforming logic simulator output to tester timing descriptions
The price of schedulability in cyclic workloads: The history-vs.-response-time-vs.-accuracy trade-off
Dynamic multi-granularity locking for coordinating cooperative activities
Session E2: Parallel program development
Utilization of parallelism in transputer-based real-time control systems
The impact of x86 instruction set architecture on superscalar processing
Hardware/software co-design of a real-time kernel based tracking system
Exploiting class hierarchy for effective parallelisation of processing in object-oriented database systems
SAGE: an automatic analyzing system for a new high-performance SoC architecture--processor-in-memory
A simulation-based system for testing real-time embedded software in the host environment
A methodology to design arbitrary failure detectors for distributed protocols
Special section on VHDL
Multiresolution image decomposition with wavelet transform
Introduction to the special issue on dependable cyber physical systems
Prolog on a RISC: Implementation and evaluation
Arbiter designs for multiprocessor interconnection networks
A small data cache for multimedia-oriented embedded systems
An ASIC implementation of a low power robust invisible watermarking processor
A distributed deadlock detection algorithm for the AND model
PASES: An energy-aware design space exploration framework for wireless sensor networks
Synthesis of decentralised controllers from high level description
Non-interactive set intersection for privacy-preserving contact tracing
Composable distributed real-time systems with deterministic network channels
Efficient SAT encoding scheme for schedulability analysis of non-preemptive tasks on multiple computational resources
Some observations on hierarchical, multiple-instruction-multiple-data computers
Safe and secure platooning of Automated Guided Vehicles in Industry 4.0
A software algorithm for the intelligent mixing of inputs to a tele-operated vehicle
Some practical considerations for the implementer of the SCI network
Scene-based non-uniformity correction: From algorithm to implementation on a smart camera
Evaluation of complexity for different layouts of butterfly networks
Session C3: Advances in object oriented design
Extended overlay architectures for heterogeneous FPGA cluster management
Robust authenticated key agreement protocol for internet of vehicles-envisioned intelligent transportation system
Guest Editorial: Special issue on parallel, distributed, and network-based processing in next-generation embedded systems
Performance analysis of video storage server under initial delay bounds
The memory hierarchy of the CHESS computer
Permutation routing in double-loop networks: design and empirical evaluation
A plane-based broadcast algorithm for multicomputer networks
Adaptive GTS allocation in IEEE 802.15.4 for real-time wireless sensor networks
Combinatorial performance modelling of toroidal cubes
The Delft test system
2nd International Workshop on Automotive Systems and Software Architectures (WASA) - Introduction to special section
Exploiting multi-way branches to boost superscalar processor performance
OCAP: On-device Class-Aware Pruning for personalized edge DNN models
SSW: A strictly sequential writing method for open-channel SSD
Computation of numerical algorithms with parametric floating point operators
A method of address tracing by firmware
An automatic distributed calendar and appointment system
Low-energy scheduling of imprecise mixed-criticality systems with standby-sparing
Power consumption estimation using statistical signal properties
Session H2: Evaluation of parallel systems
Balancing I/O and wear-out distribution inside SSDs with optimized cache management
PCHAN: A notion for dynamic resource management in distributed occam systems
Conditions for the convergence of evolutionary algorithms
Energy-cognizant scheduling for preference-oriented fixed-priority real-time tasks
A reusable load balancer for parallel search problems
Multi-objective uplink data transmission optimization for edge computing in UAV-assistant mobile wireless sensor networks
Deriving protocol specifications from service specifications including parameters
Facilitating hardware-aware neural architecture search with learning-based predictive models
ANDES: Evaluating mapping strategies with synthetic programs
Automated code generation of embedded real-time systems
On the analysis of occam real-time distributed computations
A hash-based post-quantum ring signature scheme for the Internet of Vehicles
SLO-aware colocation: Harvesting transient resources from latency-critical services
Session A2: Multiprocessor
Emotional robot control architecture implementation using FPGAs
A survey on hardware security of DNN models and accelerators
Glass, a language for analog and digital circuit description, and its environment
A+Store: An Asynchronous Parallel Compaction for Multi-NDP-Enabled Key-Value Store
A pipeline architecture for computing the Euler number of a binary image
Data aggregation framework for energy-efficient WirelessHART networks
VHDL( VHSIC Hardware Description Language)
A survey on FANET routing from a cross-layer design perspective
Move32int, a sea of gates realization of a high performance transport triggered architecture
An efficient and comprehensive scheduler on Asymmetric Multicore Architecture systems
Quantum ternary parallel adder/subtractor with partially-look-ahead carry
Deadline and activation time assignment for partitioned real-time application on multiprocessor reservations
A low-complexity microprocessor design with speculative pre-execution
On container vulnerabilities in edge computing: A fix-on-deployment approach
Quarter Load Threshold (QLT) flow control for wormhole switching in mesh-based Network-on-Chip
A comparative evaluation of hardware-only and software-only directory protocols in shared-memory multiprocessors
Managing real-time constraints through monitoring and analysis-driven edge orchestration
Intelligent Adjustment Forwarding: A compromise between end-to-end and hop-by-hop transmissions in VANET environments
Decentralized media streaming infrastructure (DeMSI): An adaptive and high-performance peer-to-peer content delivery network
FPGA implementation of high performance elliptic curve cryptographic processor over GF
A faster outsourced medical image retrieval scheme with privacy preservation
Subversion-resistant public-key searchable encryption for data sharing in IIoT
A hardware efficient systolic solution to the two-dimensional Discrete Fourier Transform
Gather/scatter hardware support for accelerating Fast Fourier Transform
Hardware-assisted mechanisms to enforce control flow integrity: A comprehensive survey
Hardware-assisted energy monitoring architecture for micro sensor nodes
IntMA: Dynamic Interaction-aware resource allocation for containerized microservices in cloud environments
Scheduling cooperative transactions in distributed database systems
Build real-time communication for hybrid dual-OS system
Stack filter: Reducing L1 data cache power consumption
A convolutional autoencoder architecture for robust network intrusion detection in embedded systems
A demand-driven macro-dataflow schema for distributed graph reduction on multiple G-machines
Estimators for logic minimization and implementation selection of finite state machines
Highly fault-tolerant cycle embeddings of hypercubes
Optimizing CAM-based instruction cache designs for low-power embedded systems
A hardware implementation of a modified DES-algorithm
Combining data prefetching with non-blocking loads to alleviate cache pollution effects
Microcomputer implementations of an object-oriented, multiprocessing database programming language
OpenCL implementation of a SLAM system on an SoC-FPGA