yusuke1997/dblp-id-title huggingface dataset:
LarQucut: A New Cutting and Mapping Approach for Large-sized Quantum Circuits in Distributed Quantum Computing (DQC) Environments
ModNEF : An Open Source Modular Neuromorphic Emulator for FPGA for Low-Power In-Edge Artificial Intelligence
An Efficient ReRAM-based Accelerator for Asynchronous Iterative Graph Processing
GraphSER: Distance-Aware Stream-Based Edge Repartition for Many-Core Systems
Dedicated Hardware Accelerators for Processing of Sparse Matrices and Vectors: A Survey
Object Intersection Captures on Interactive Apps to Drive a Crowd-sourced Replay-based Compiler Optimization
Dynamic microarchitectural adaptation using machine learning
A dynamic self-scheduling scheme for heterogeneous multiprocessor architectures
GNNPilot: A Holistic Framework for High-Performance Graph Neural Network Computations on GPUs
Integrating profile-driven parallelism detection and machine-learning-based mapping
TSN Cache: Exploiting Data Localities in Graph Computing Applications
Accelerating Video Captioning on Heterogeneous System Architectures
Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors
BullsEye : Scalable and Accurate Approximation Framework for Cache Miss Calculation
Concurrent JavaScript Parsing for Faster Loading of Web Apps
CODA: Enabling Co-location of Computation and Data for Multiple GPU Systems
Impact of Intrinsic Profiling Limitations on Effectiveness of Adaptive Optimizations
Fast Convolution Meets Low Precision: Exploring Efficient Quantized Winograd Convolution on Modern CPUs
High-performance Deterministic Concurrency Using Lingua Franca
LIGERO: A light but efficient router conceived for cache-coherent chip multiprocessors
CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories
Understanding and Mitigating Covert Channels Through Branch Predictors
Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories
Orchard: Heterogeneous Parallelism and Fine-grained Fusion for Complex Tree Traversals
An Optimizing Code Generator for a Class of Lattice-Boltzmann Computations
Fine-grain Quantitative Analysis of Demand Paging in Unified Virtual Memory
Dirty-Block Tracking in a Direct-Mapped DRAM Cache with Self-Balancing Dispatch
E 3 CC: A memory error protection scheme with novel address mapping for subranked and low-power memories
Efficient and Scalable Graph Parallel Processing With Symbolic Execution
All-gather Algorithms Resilient to Imbalanced Process Arrival Patterns
Hardware transactional memory with software-defined conflicts
LLOV: A Fast Static Data-Race Checker for OpenMP Programs
Ceiba: An Efficient and Scalable DNN Scheduler for Spatial Accelerators
Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage
The single-referent collector: Optimizing compaction for the common case
Enabling GPGPU Low-Level Hardware Explorations with MIAOW: An Open-Source RTL Implementation of a GPGPU
DCMI: A Scalable Strategy for Accelerating Iterative Stencil Loops on FPGAs
On How to Accelerate Iterative Stencil Loops: A Scalable Streaming-Based Approach
A Case For Intra-rack Resource Disaggregation in HPC
Improving Loop Dependence Analysis
Source Matching and Rewriting for MLIR Using String-Based Automata
A Two-Stage Degradation-Based Topology Reconfiguration Algorithm for Fault-Tolerant Multiprocessor Arrays
Compiler support for lightweight context switching
FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration
The Power-optimised Software Envelope
A Metric-Guided Method for Discovering Impactful Features and Architectural Insights for Skylake-Based Processors
Optimizing explicit data transfers for data parallel applications on the cell architecture
Iterative Compilation Optimization Based on Metric Learning and Collaborative Filtering
Characterizing and Understanding HGNN Training on GPUs
VGRIS: Virtualized GPU Resource Isolation and Scheduling in Cloud Gaming
EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors
Micro-Sector Cache: Improving Space Utilization in Sectored DRAM Caches
Architectural Support for Data-Driven Execution
Symmetry-Agnostic Coordinated Management of the Memory Hierarchy in Multicore Systems
ArmorAll: Compiler-based Resilience Targeting GPU Applications
Recovery code generation for general speculative optimizations
Spatiotemporal SIMT and Scalarization for Improving GPU Efficiency
Cost-aware Service Placement and Scheduling in the Edge-Cloud Continuum
Bones: An Automatic Skeleton-Based C-to-CUDA Compiler for GPUs
SEED: Speculative Security Metadata Updates for Low-Latency Secure Memory
TokenSmart: Distributed, Scalable Power Management in the Many-core Era
SWITCHES: A Lightweight Runtime for Dataflow Execution of Tasks on Many-Cores
PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM
ReSense: Mapping dynamic workloads of colocated multithreaded applications using resource sensitivity
Improving Energy Efficiency of Coarse-Grain Reconfigurable Arrays Through Modulo Schedule Compression/Decompression
Multiprogram Throughput Metrics: A Systematic Approach
Scheduling Language Chronology: Past, Present, and Future
The Forward Slice Core: A High-Performance, Yet Low-Complexity Microarchitecture
A compiler cost model for speculative parallelization
A memory-efficient pipelined implementation of the aho-corasick string-matching algorithm
Exploiting virtual registers to reduce pressure on real registers
Correct-by-Construction Parallelization of Hard Real-Time Avionics Applications on Off-the-Shelf Predictable Hardware
Inter-cluster communication in VLIW architectures
HPar: A practical parallel parser for HTML-taming HTML complexities for parallel parsing
Datapath and control for quantum wires
On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE
EA4RCA: Efficient AIE accelerator design framework for regular Communication-Avoiding Algorithm
Accelerating Parallel Structures in DNNs via Parallel Fusion and Operator Co-Optimization
Morphable DRAM Cache Design for Hybrid Memory Systems
Leveraging GPUs using cooperative loop speculation
Exploiting Parallelism Opportunities with Deep Learning Frameworks
Decoupling Data Supply from Computation for Latency-Tolerant Communication in Heterogeneous Architectures
gHyPart: GPU-friendly End-to-End Hypergraph Partitioner
Optimizing software runtime systems for speculative parallelization
Hardware-Accelerated Cross-Architecture Full-System Virtualization
C1C: A configurable, compiler-guided STT-RAM L1 cache
Gretch: A Hardware Prefetcher for Graph Analytics
FinPar: A Parallel Financial Benchmark
Static and Dynamic Frequency Scaling on Multicore CPUs
Tolerating memory latency through push prefetching for pointer-intensive applications
iSwap: A New Memory Page Swap Mechanism for Reducing Ineffective I/O Operations in Cloud Environments
Optimization Models for Three On-Chip Network Problems
SketchDLC: A Sketch on Distributed Deep Learning Communication via Trace Capturing
DPCS: Dynamic Power/Capacity Scaling for SRAM Caches in the Nanoscale Era
Accelerating an application domain with specialized functional units
Analysis of dependence tracking algorithms for task dataflow execution
Integer affine transformations of parametric ℤ-polytopes and applications to loop nest optimization
Generalized Task Parallelism
On-GPU Thread-Data Remapping for Branch Divergence Reduction
Comprehensive Evaluation and Opportunity Discovery for Deterministic Concurrency Control
Leveraging iterative applications to improve the scalability of task-based programming models on distributed systems
Making wide-issue VLIW processors viable on FPGAs
An Example of Parallel Merkle Tree Traversal: Post-Quantum Leighton-Micali Signature on the GPU
Band-Pass Prefetching: An Effective Prefetch Management Mechanism Using Prefetch-Fraction Metric in Multi-Core Systems
Tiling Optimizations for Stencil Computations Using Rewrite Rules in Lift
Improving System Energy Efficiency with Memory Rank Subsetting
Analysis of cache-coherence bottlenecks with hybrid hardware/software techniques
ReuseTracker: Fast Yet Accurate Multicore Reuse Distance Analyzer
CoolDC: A Cost-Effective Immersion-Cooled Datacenter with Workload-Aware Temperature Scaling
A System-Level Simulator for RRAM-Based Neuromorphic Computing Chips
A system architecture, processor, and communication protocol for secure implants
Fuse: Accurate Multiplexing of Hardware Performance Counters Across Executions
CARL: Compiler Assigned Reference Leasing
Environmental Condition Aware Super-Resolution Acceleration Framework in Server-Client Hierarchies
Data-Driven Concurrency for High Performance Computing
TRACED: A Temporal Graph Neural Networks-based Model for Data Prefetching
Significance-Aware Program Execution on Unreliable Hardware
MUA-Router: Maximizing the Utility-of-Allocation for On-chip Pipelining Routers
Performance Evaluation of Intel Optane Memory for Managed Workloads
CASHT: Contention Analysis in Shared Hierarchies with Thefts
Practical Software-Based Shadow Stacks on x86-64
Securing Branch Predictors with Two-Level Encryption
Energy Transparency for Deeply Embedded Programs
Informed Prefetching for Indirect Memory Accesses
Accelerating Nearest Neighbor Search in 3D Point Cloud Registration on GPUs
COVER: Alleviating Crash-Consistency Error Amplification in Secure Persistent Memory Systems
Evaluator-executor transformation for efficient pipelining of loops with conditionals
Mixed speculative multithreaded execution models
Layup: Layer-adaptive and Multi-type Intermediate-oriented Memory Optimization for GPU-based CNNs
Efficient liveness computation using merge sets and DJ-graphs
An Efficient GPU Cache Architecture for Applications with Irregular Memory Access Patterns
Efficient architectural design space exploration via predictive modeling
A Transactional Correctness Tool for Abstract Data Types
Optimizing Memory Translation Emulation in Full System Emulators
Early Address Prediction: Efficient Pipeline Prefetch and Reuse
Dynamic Memory Balancing for Virtualization
Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era
A Reconfiguration Algorithm for Power-Aware Parallel Applications
A Simple Model for Portable and Fast Prediction of Execution Time and Power Consumption of GPU Kernels
Dynamic Colocation Policies with Reinforcement Learning
Triple Engine Processor (TEP): A Heterogeneous Near-Memory Processor for Diverse Kernel Operations
A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures
Leveraging Value Equality Prediction for Value Speculation
Token tenure and PATCH: A predictive/adaptive token-counting hybrid
MaxPB: Accelerating PCM Write by Maximizing the Power Budget Utilization
SCP: Shared Cache Partitioning for High-Performance GEMM
Optimizing Indirect Branches in Dynamic Binary Translators
Automatic feature generation for machine learning-based optimising compilation
Decoupled Fused Cache: Fusing a Decoupled LLC with a DRAM Cache
Snug set-associative caches: Reducing leakage power of instruction and data caches with no performance penalties
Exploiting reuse locality on inclusive shared last-level caches
Agile C-states: A Core C-state Architecture for Latency Critical Applications Optimizing both Transition and Cold-Start Latency
JiuJITsu: Removing Gadgets with Safe Register Allocation for JIT Code Generation
Improving MLC PCM Performance through Relaxed Write and Read for Intermediate Resistance Levels
A scalable and near-optimal representation of access schemes for memory management
Delta-compressed caching for overcoming the write bandwidth limitation of hybrid main memory
List of Distinguished Reviewers ACM TACO 2014
BestSF: A Sparse Meta-Format for Optimizing SpMV on GPU
Improving WCET by applying a WC code-positioning optimization
System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System
Turn-based Spatiotemporal Coherence for GPUs
Online diagnosis of hard faults in microprocessors
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications
Unleashing Parallelism with Elastic-Barriers
Smart-DNN+: A Memory-efficient Neural Networks Compression Framework for the Model Inference
AIS: An Active Idleness I/O Scheduler to Reduce Buffer-Exhausted Degradation of Solid-State Drives
A Reusable Characterization of the Memory System Behavior of SPEC2017 and SPEC2006
Reducing instruction cache energy consumption using a compiler-based strategy
Flextended Tiles: A Flexible Extension of Overlapped Tiles for Polyhedral Compilation
WIPE: A Write-Optimized Learned Index for Persistent Memory
A Low-latency On-chip Cache Hierarchy for Load-to-use Stall Reduction in GPUs
NoCMsg: A Scalable Message-Passing Abstraction for Network-on-Chips
EchoBay: Design and Optimization of Echo State Networks under Memory and Time Constraints
Boosting timestamp-based transactional memory by exploiting hardware cycle counters
Cheetah: Accelerating Dynamic Graph Mining with Grouping Updates
Profile-guided floating- to fixed-point conversion for hybrid FPGA-processor applications
Quantifying Resource Contention of Co-located Workloads with the System-level Entropy
Hardware Fault Recovery for I/O Intensive Applications
Application-Specific Arithmetic in High-Level Synthesis Tools
Exceptionization : A Java VM Optimization for Non-Java Languages
Declarative Loop Tactics for Domain-specific Optimization
Adaptive timekeeping replacement: Fine-grained capacity management for shared CMP caches
Cppless: Single-Source and High-Performance Serverless Programming in C++
PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite
Efficient remote profiling for resource-constrained devices
On the simulation of large-scale architectures using multiple application abstraction levels
Falcon: A Graph Manipulation Language for Heterogeneous Systems
Partitioned Scheduling and Analysis for a Typed DAG Task on Heterogeneous Multi-Cores
Global Dead-Block Management for Task-Parallel Programs
Programming Heterogeneous Systems from an Image Processing DSL
Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping
Efficient hardware code generation for FPGAs
An Intelligent Scheduling Approach on Mobile OS for Optimizing UI Smoothness and Power
FPDetect: Efficient Reasoning About Stencil Programs Using Selective Direct Evaluation
Optimization of Triangular and Banded Matrix Operations Using 2d-Packed Layouts
Sensible Energy Accounting with Abstract Metering for Multicore Systems
HMTT: A hybrid hardware/software tracing system for bridging the DRAM access trace's semantic gap
Low I/O Intensity-aware Partial GC Scheduling to Reduce Long-tail Latency in SSDs
Understanding Silent Data Corruption in Processors for Mitigating its Effects
Evaluating Auto-Vectorizing Compilers through Objective Withdrawal of Useful Information
Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack Between QoS-Constrained Applications
Disjoint out-of-order execution processor
Easy, fast, and energy-efficient object detection on heterogeneous on-chip architectures
ATP: Achieving Throughput Peak for DNN Training via Smart GPU Memory Management
LIA: Latency-Improved Adaptive routing for Dragonfly networks
Finding good optimization sequences covering program space
Two-Level Hybrid Sampled Simulation of Multithreaded Applications
Dynamic QoS management for chip multiprocessors
Optimal DPM and DVFS for frame-based real-time systems
Exploiting the reuse supplied by loop-dependent stream references for stream processors
Adapting branch-target buffer to improve the target predictability of java code
The Polyhedral Model of Nonlinear Loops
ZNSFQ: An Efficient and High-Performance Fair Queue Scheduling Scheme for ZNS SSDs
Performance Tuning and Analysis for Stencil-Based Applications on POWER8 Processor
Using Barrier Elision to Improve Transactional Code Generation
ACTION: Adaptive Cache Block Migration in Distributed Cache Architectures
Abstracting access patterns of dynamic memory using regular expressions
SAQIP: A Scalable Architecture for Quantum Information Processors
Using machine learning to partition streaming programs
A decoupled local memory allocator
Managing SMT resource usage through speculative instruction window weighting
Formulating and implementing profiling over adaptive ranges
A SIMD optimization framework for retargetable compilers
TACO Reviewers 2012
Predicate-aware, makespan-preserving software pipelining of scheduling tables
Taming Flexible Job Packing in Deep Learning Training Clusters
Efficient Auto-Tuning of Parallel Programs with Interdependent Tuning Parameters via Auto-Tuning Framework (ATF)
ScaWL: Scaling k-WL (Weisfeiler-Lehman) Algorithms in Memory and Performance on Shared and Distributed-Memory Systems
Leveraging Strength-Based Dynamic Information Flow Analysis to Enhance Data Value Prediction
A transactional memory with automatic performance tuning
A Framework for Application-Guided Task Management on Heterogeneous Embedded Systems
PRISM: Strong Hardware Isolation-based Soft-Error Resilient Multicore Architecture with High Performance and Availability at Low Hardware Overheads
Exposing Memory Access Patterns to Improve Instruction and Memory Efficiency in GPUs
Symbolic Analysis for Data Plane Programs Specialization
CGCGraph: Efficient CPU-GPU Co-execution for Concurrent Dynamic Graph Processing
Managing Heterogeneous Datacenters with Tokens
MetaSys: A Practical Open-source Metadata Management System to Implement and Evaluate Cross-layer Optimizations
Accelerating Synchronization Using Moving Compute to Data Model at 1, 000-core Multicore Scale
Domain-Specific Multi-Level IR Rewriting for GPU: The Open Earth Compiler for GPU-accelerated Climate Simulation
Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor
Delay-on-Squash: Stopping Microarchitectural Replay Attacks in Their Tracks
Buddy SM: Sharing Pipeline Front-End for Improved Energy Efficiency in GPGPUs
SCALO: Scalability-Aware Parallelism Orchestration for Multi-Threaded Workloads
Maintaining performance on power gating of microprocessor functional units by using a predictive pre-wakeup strategy
GPU Performance vs. Thread-Level Parallelism: Scalability Analysis and a Novel Way to Improve TLP
Online Application Guidance for Heterogeneous Memory Systems
Performance Implications of Pipelining the Data Transfer in CPU-GPU Heterogeneous Systems
Contech: Efficiently Generating Dynamic Task Graphs for Arbitrary Parallel Programs
Beyond reuse distance analysis: Dynamic analysis for characterization of data locality potential
MasterPlan: A Reinforcement Learning Based Scheduler for Archive Storage
gPPM: A Generalized Matrix Operation and Parallel Algorithm to Accelerate the Encoding/Decoding Process of Erasure Codes
Predictable Thread Coarsening
HAIR: Halving the Area of the Integer Register File with Odd/Even Banking
MicroProf: Code-level Attribution of Unnecessary Data Transfer in Microservice Applications
Multiply-and-Fire: An Event-Driven Sparse Neural Network Accelerator
Triangle Dropping: An Occluded-geometry Predictor for Energy-efficient Mobile GPUs
Scratchpad Sharing in GPUs
SCIN-cache: Fast speculative versioning in multithreaded cores
Compiler techniques to improve dynamic branch prediction for indirect jump and call instructions
sFtree: A fully connected and deadlock-free switch-to-switch routing algorithm for fat-trees
ReNIC: Architectural extension to SR-IOV I/O virtualization for efficient replication
Tumbler: An Effective Load-Balancing Technique for Multi-CPU Multicore Systems
DarkCache: Energy-Performance Optimization of Tiled Multi-Cores by Adaptively Power-Gating LLC Banks
AVPP: Address-first Value-next Predictor with Value Prefetching for Improving the Efficiency of Load Value Prediction
Reducing DRAM row activations with eager read/write clustering
Stripe-schedule Aware Repair in Erasure-coded Clusters with Heterogeneous Star Networks
Checkpoint allocation and release
OpenStream: Expressiveness and data-flow compilation of OpenMP streaming programs
MAPS: Optimizing Massively Parallel Applications Using Device-Level Memory Abstraction
Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems
A 2 : Towards Accelerator Level Parallelism for Autonomous Micromobility Systems
Aggregate Flow-Based Performance Fairness in CMPs
CACF: A Novel Circuit Architecture Co-optimization Framework for Improving Performance, Reliability and Energy of ReRAM-based Main Memory System
The Next 700 Accelerated Layers: From Mathematical Expressions of Network Computation Graphs to Accelerated GPU Kernels, Automatically
OD-SGD: One-Step Delay Stochastic Gradient Descent for Distributed Training
Nested MIMD-SIMD Parallelization for Heterogeneous Microprocessors
MemHC: An Optimized GPU Memory Management Framework for Accelerating Many-body Correlation
Runtime energy consumption estimation for server workloads based on chaotic time-series approximation
Reliability-aware Garbage Collection for Hybrid HBM-DRAM Memories
DawnCC: Automatic Annotation for Data Parallelism and Offloading
Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks
On-the-fly structure splitting for heap objects
PAVER: Locality Graph-Based Thread Block Scheduling for GPUs
The Effects of Parameter Tuning in Software Thread-Level Speculation in JavaScript Engines
GOLDYLOC: Global Optimizations & Lightweight Dynamic Logic for Concurrency
Evaluation of Histogram of Oriented Gradients Soft Errors Criticality for Automotive Applications
Architecting Optically Controlled Phase Change Memory
SPCM: The Striped Phase Change Memory
Exploiting selective placement for low-cost memory protection
The Droplet Search Algorithm for Kernel Scheduling
Understanding fundamental design choices in single-ISA heterogeneous multicore architectures
Compiler-support for Critical Data Persistence in NVM
Compiler mitigations for time attacks on modern x86 processors
Supporting Superpages and Lightweight Page Migration in Hybrid Memory Systems
Optimizing Remote Communication in X10
Instruction packing: Toward fast and energy-efficient instruction scheduling
A lifetime optimal algorithm for speculative PRE
Automatic data allocation and buffer management for multi-GPU machines
GEVO: GPU Code Optimization Using Evolutionary Computation
Evaluating trace cache energy efficiency
Static analysis of the worst-case memory performance for irregular codes with indirections
On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments
A compiler framework for speculative optimizations
Building Heterogeneous Unified Virtual Memories (UVMs) without the Overhead
Reducing register pressure in SMT processors through L2-miss-driven early register release
Runtime Design Space Exploration and Mapping of DCNNs for the Ultra-Low-Power Orlando SoC
DisGCo: A Compiler for Distributed Graph Analytics
Cross-component energy management: Joint adaptation of processor and memory
Transactional Read-Modify-Write Without Aborts
Efficient Generation of Compact Execution Traces for Multicore Architectural Simulations
Poker: Permutation-Based SIMD Execution of Intensive Tree Search by Path Encoding
A Novel, Highly Integrated Simulator for Parallel and Distributed Systems
An Efficient Hybrid Deep Learning Accelerator for Compact and Heterogeneous CNNs
Abakus: Accelerating k -mer Counting with Storage Technology
An Optimized GPU Implementation for GIST Descriptor
A Neural Network Prefetcher for Arbitrary Memory Access Patterns
Power-performance considerations of parallel computing on chip multiprocessors
Shining Light on the Inter-procedural Code Obfuscation: Keep Pace with Progress in Binary Diffing
Could Compression Be of General Use? Evaluating Memory Compression across Domains
GenMatcher: A Generic Clustering-Based Arbitrary Matching Framework
LAPPS: Locality-Aware Productive Prefetching Support for PGAS