yusuke1997/dblp-id-title huggingface dataset:
A Computationally Efficient Compact Model for Ferroelectric Switching With Asymmetric Nonperiodic Input Signals
Physics-Based Electromigration Models and Full-Chip Assessment for Power Grid Networks
Toward Critical Flip-Flop Identification for Soft-Error Tolerance With Graph Neural Networks
An analytical approach to floorplanning for hierarchical building blocks layout [VLSI]
Renormalization group meshes and the discretization of TCAD equations
Low-Power Scan Testing for Test Data Compression Using a Routing-Driven Scan Architecture
Application-specific heterogeneous multiprocessor synthesis using extensible processors
A Model-Based-Random-Forest Framework for Predicting V t Mean and Variance Based on Parallel I d Measurement
Feasible Aggressor-Set Identification Under Constraints for Maximum Coupling Noise
Hardware Acceleration for Constraint Solving for Random Simulation
Are We There Yet? A Study on the State of High-Level Synthesis
Retiming and resynthesis: optimizing sequential networks with combinational techniques
Layout driven retiming using the coupled edge timing model
Fast Operation Mode Selection for Highly Efficient IoT Edge Devices
Hardware accelerators for timing simulation of VLSI digital circuits
Scalable Activation of Rare Triggers in Hardware Trojans by Repeated Maximal Clique Sampling
SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs
2-D mesh adaption and flux discretizations for dopant diffusion modeling
Improving DRAM Reliability Using a High Order Error Correction Code
Exploiting the Single-Symbol LLR Variation to Accelerate LDPC Decoding for 3-D nand Flash Memory
Estimation of Analog/RF Parametric Test Metrics Based on a Multivariate Extreme Value Model
Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring of Run-Time Stress
General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations
STRAIT: Self-Test and Self-Recovery for AI Accelerator
Reduction of power consumption in scan-based circuits during testapplication by an input control technique
CPSAA: Accelerating Sparse Attention Using Crossbar-Based Processing-In-Memory Architecture
Synthesis of robust delay-fault-testable circuits: practice
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages
Timing analysis of asynchronous systems using time separation of events
Frequency- and Time-Domain Yield Optimization of a Power Delivery Network Subject to Large Decoupling Capacitor Tolerances
In-Memory Set Operations on Memristor Crossbar
Weighted Quantization-Regularization in DNNs for Weight Memory Minimization Toward HW Implementation
Exploiting the Memory-Compute-Coupling Feature for CIM Accelerator Design Optimization
Bits-Ensemble: Toward Light-Weight Robust Deep Ensemble by Bits-Sharing
On multiterminal single bend wirability
A Framework for Accelerating Transformer-Based Language Model on ReRAM-Based Architecture
Parameterized Non-Gaussian Variational Gate Timing Analysis
Fault-Tolerant Distributed Deployment of Embedded Control Software
NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning
Congestion minimization during placement
Mixed-Crossing-Avoided Escape Routing of Mixed-Pattern Signals on Staggered-Pin-Array PCBs
Ulgen: A Runtime Assurance Framework for Programming Safe Cyber-Physical Systems
Functional Broadside Tests Under Broadcast Scan
Efficient Transient Analysis of Power Delivery Network With Clock/Power Gating by Sparse Approximation
A New Compact MOSFET Model Based on Artificial Neural Network With Unique Data Preprocessing and Sampling Techniques
DUPRFloor: Dynamic Modeling and Floorplanning for Partially Reconfigurable FPGAs
Methodologies for testing embedded content addressable memories
Post-Silicon Heat-Source Identification and Machine-Learning-Based Thermal Modeling Using Infrared Thermal Imaging
Synthesizing circuits from behavioural descriptions
Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis
ProMiSE: A High-Performance Programmable Hardware Monitor for High Security Enforcement of Software Execution
Exploring HW/SW Co-Design for Video Analysis on CPU-FPGA Heterogeneous Systems
Statistical timing verification for transparently latched circuits
Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions
Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns
An adaptive timing-driven placement for high performance VLSIs
Minimizing the number of paths in BDDs: Theory and algorithm
Strengthening Model Checking Techniques With Inductive Invariants
Application of statistical design and response surface methods to computer-aided VLSI device design II. Desirability functions and Taguchi methods
Early power estimation for VLSI circuits
Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures
STREAM: Stress and Thermal Aware Reliability Management for 3-D ICs
Mercury: Instruction Pipeline Aware Code Generation for Simulink Models
A hierarchical algorithm for one-dimensional gate assignment based on contraction of nets
Bound-Based Statistically-Critical Path Extraction Under Process Variations
Diagnosis of clustered faults and wafer testing
EOmesh: Combined Flow Balancing and Deterministic Routing for Reduced WCET Estimates in Embedded Real-Time Systems
A Systolic Design-Rule Checker
NDPGNN: A Near-Data Processing Architecture for GNN Training and Inference Acceleration
An implicit path-delay fault diagnosis methodology
A Lightweight True Random Number Generator for Root of Trust Applications
OATT: Outlier-Oriented Alternative Testing and Post-Manufacture Tuning of Analog/Mixed-Signal Circuits
High-level synthesis of ΔΣ Modulator topologies optimized for complexity, sensitivity, and power consumption
A Wavelet-Based Spatio-Temporal Heat Dissipation Model for Reordering of Program Phases to Produce Temperature Extremes in a Chip
Fast and Scaled Counting-Based Stochastic Computing Divider Design
Lower-bound performance estimation for the high-level synthesis scheduling problem
Return-limited inductances: a practical approach to on-chipinductance extraction
High-Performance Architecture for Binary-Tree-Based Finite State Machines
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits
Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions
NBTI and HCI Aging Prediction and Reliability Screening During Production Test
Optimization of state encoding in distributed circuits
The design of concurrent error diagnosable systolic arrays for band matrix multiplications
A hierarchical compiled code event-driven logic simulator
VAST: Virtually Associative Sector Translation for MLC Storage Systems
Don't-Care-Based Logic Optimization for Threshold Logic
EDT Bandwidth Management in SoC Designs
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
Monte Carlo simulation of silicon amorphization during ion implantation
A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis
Identification of Critical Executable Paths at the Architectural Level
Dynamic Approximation of JPEG Hardware
Domain characterization of transmission line models and analyses
Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction
The shadow algorithm: a scheduling technique for both compiled and interpreted simulation
CARLOS: an automated multilevel logic design system for CMOS semi-custom integrated circuits
Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring
RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique
Equivalent circuit model of resistive IC sensors derived with the box integration method
$2^{n}$ Pattern Run-Length for Test Data Compression
Thermal-Aware Design and Simulation Approach for Optical NoCs
Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing
Efficient Wakeup Scheduling Considering Both Resource Usage and Timing Budget for Power Gating Designs
NETOPT-a program for multiobjective design of linear networks
DNNVM: End-to-End Compiler Leveraging Heterogeneous Optimizations on FPGA-Based CNN Accelerators
MEDUSA - A Simulator for Modular Circuits
Parallel Fast Transform-Based Preconditioners for Large-Scale Power Grid Analysis on Graphics Processing Units (GPUs)
Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic
Generation of performance constraints for layout
Hypergraph partitioning with fixed vertices [VLSI CAD]
Wash Optimization and Analysis for Cross-Contamination Removal Under Physical Constraints in Flow-Based Microfluidic Biochips
IP-Tag: Tag-Based Runtime 3PIP Hardware Trojan Detection in SoC Platforms
A Full-Chip ESD Protection Circuit Simulation and Fast Dynamic Checking Method Using SPICE and ESD Behavior Models
Logic synthesis for field-programmable gate arrays
MaPart: An Efficient Multi-FPGA System-Aware Hypergraph Partitioning Framework
Defense Against On-Chip Trojans Enabling Traffic Analysis Attacks Based on Machine Learning and Data Augmentation
Global routing by new approximation algorithms for multicommodityflow
On shifting blocks and terminals to minimize channel density
Quantitative Timing Analysis for Cyber-Physical Systems Using Uncertainty-Aware Scenario-Based Specifications
Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars
SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing
A fast electron beam lithography simulator based on the Boltzmann transport equation
High-Speed Post-Layout Logic Simulation Using Quasi-Static Clock Event Evaluation
Data Representation Aware of Damage to Extend the Lifetime of MLC NAND Flash Memory
Temperature Effect Inversion-Aware Power-Performance Optimization for FinFET-Based Multicore Systems
McBOOLE: A New Procedure for Exact Logic Minimization
A hierarchical test pattern generation system based on high-level primitives
CHIPS: Custom Hardware Instruction Processor Synthesis
Numerical methods for the hydrodynamic device model: subsonic flow
Morphable Resistive Memory Optimization for Mobile Virtualization
Algorithmic Obfuscation for LDPC Decoders
PLADE: a two-stage PLA decomposition
Nonuniform Compressive Sensing via Ohmic Voltage Attenuation: A Memristive Crossbar Design Approach Leveraging Intrinsic Computation
YOR: a yield-optimizing routing algorithm by minimizing critical areas and vias
Charge Recycling in Power-Gated CMOS Circuits
A high-efficiency strongly self-checking asynchronous datapath
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks
An enhanced SPICE MOSFET model suitable for analog applications
Formal Verification of Integer Multiplier Circuits Using Binary Decision Diagrams
Design Exploration With Imprecise Latency and Register Constraints
Fixed-Priority Scheduling for Reliable and Energy-Aware (m, k)-Deadlines Enforcement With Standby-Sparing
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits
Net-Aware Critical Area Extraction for Opens in VLSI Circuits Via Higher-Order Voronoi Diagrams
In-Memory Computing Circuit Implementation of Complex-Valued Hopfield Neural Network for Efficient Portrait Restoration
Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits
Xplace: An Extremely Fast and Extensible Placement Framework
Acceleration-Aware Fine-Grained Channel Pruning for Deep Neural Networks via Residual Gating
Physically based simulation of electromigration-induced degradation mechanisms in dual-inlaid copper interconnects
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs
Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer Interconnection Architecture and Optimization Algorithms
Layout-Dependent Effects-Aware Analytical Analog Placement
A Logic Simulation Machine
ASC: a stream compiler for computing with FPGAs
SPARTA: A System Partitioning Aid
A probabilistic fault model for 'analog' faults in digital CMOS circuits
An Efficient Gate Library for Ambipolar CNTFET Logic
DeSpErate++: An Enhanced Design Space Exploration Framework Using Predictive Simulation Scheduling
Reachability-Based Robustness Verification and Optimization of SRAM Dynamic Stability Under Process Variations
A new approach to the design of built-in self-testing PLAs for high fault coverage
Techniques for minimizing power dissipation in scan and combinational circuits during test application
Automated synthesis of current-memory cells
Correction to "a two-stage solution approach to multidimensional periodic scheduling"
Consistent floorplanning with hierarchical superconstraints
Introduction of Architecturally Visible Storage in Instruction Set Extensions
Asymmetric Error Rates of Cell States Exploration for Performance Improvement on Flash Memory Based Storage Systems
Clock Sequences for Increasing the Fault Coverage of Functional Test Sequences
Design Analysis of GaAs Direct Coupled Field Effect Transistor Logic
K-SpecPart: Supervised Embedding Algorithms and Cut Overlay for Improved Hypergraph Partitioning
Test Application for Analog/RF Circuits With Low Computational Burden
Diagnosis of Board-Level Functional Failures Under Uncertainty Using Dempster-Shafer Theory
A non-quasi-static MOSFET model for SPICE-AC analysis
Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip
Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits
Enhanced Phase-Driven Q-Learning-Based DRM for Multicore Processors
GNN4HT: A Two-Stage GNN-Based Approach for Hardware Trojan Multifunctional Classification
Probabilistic Analysis of Power and Temperature Under Process Variation for Electronic System Design
Structural Characterization and Efficient Implementation Techniques for $A$-Stable High-Order Integration Methods
Orthonormal bandlimited Kautz sequences for global system modeling from piecewise rational models
Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic
The solution of a numerical problem encountered when adding a mobility model to a finite-element device simulator
Novel Error-Tolerant Voltage-Divider-Based Through-Silicon-Via Test Architecture
Self-Learning and Efficient Health-Status Analysis for a Core Router System
On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits
RegionSeeker: Automatically Identifying and Selecting Accelerators From Application Source Code
Adjustment-Based Modeling for Timing Analysis Under Variability
Complexity of the lookup-table minimization problem for FPGA technology mapping
On sampling algorithms in multilevel QR factorization method for magnetoquasistatic analysis of integrated circuits over multilayered lossy substrates
A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed I/O Links With Jitter and Parameter Variations
IC defect sensitivity for footprint-type spot defects
AttentionRC: A Novel Approach to Improve Locality Sensitive Hashing Attention on Dual-Addressing Memory
Accurate transient simulation of transmission lines with the skineffect
Automated Model Generation Algorithm for High-Level Fault Modeling
Parallel Accurate Minifloat MACCs for Neural Network Inference on Versal FPGAs
A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs
Synthesis of Integrated Passive Components for High-Frequency RF ICs Based on Evolutionary Computation and Machine Learning Techniques
Accelerating Electromigration Aging: Fast Failure Detection for Nanometer ICs
Mechanical Stress Aware Optimization for Leakage Power Reduction
Analysis of Performance Benefits of Multitier Gate-Level Monolithic 3-D Integrated Circuits
Analytical MOSFET Model with Easily Extracted Parameters
Novel algorithms for placement of rectangular covers for mask inspection in advanced lithography and other VLSI design applications
Two-Dimensional Numerical Analysis of Latchup in a VLSI CMOS Technology
Global optimization for digital MOS circuits performance
OCCOM-efficient computation of observability-based code coveragemetrics for functional verification
Method for the Computer-Aided Schematic Design and Simulation of Hydrogel-Based Microfluidic Systems
$O(mn)$ Time Algorithm for Optimal Buffer Insertion of Nets With $m$ Sinks
Quasi-three-dimensional modeling of bipolar transistor characteristics
A transitive closure algorithm for test generation
RFSIM: Reduced Fault Simulator
Grid-Based Framework for Routability Analysis and Diagnosis With Conditional Design Rules
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation
Analysis of MOSFET Capacitances and Their Behavior at Short-Channel Lengths Using an AC Device Simulator
A Quasi-Convex Optimization Approach to Parameterized Model Order Reduction
PTPS: Precision-Aware Task Partitioning and Scheduling for SpMV on CPU-FPGA Heterogeneous Platforms
Switch-Level Logic Simulation of Digital Bipolar Circuits
A Generic Sample Preparation Approach for Different Microfluidic Labs-on-Chips
A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design
Worst case crosstalk noise for nonswitching victims in high-speed buses
Order of Channels for Safe Routing and Optimal Compaction of Routing Area
LAXY: A Location-Based Aging-Resilient Xy-Yx Routing Algorithm for Network on Chip
LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS Technologies
CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance
An explicit method of numerical integration for the complete set of semiconductor device equations
Reverse Low-Power Broadside Tests
Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults
Early Analysis of Critical Faults: An Approach to Test Generation From Formal Specifications
Arbitrary convex and concave rectilinear block packing usingsequence-pair
Quad list quad trees: a geometrical data structure with improved performance for large region queries
Realistic Yield Simulation for VLSIC Structural Failures
A Thermal-Aware Physical Space Reallocation for Open-Channel SSD With 3-D Flash Memory
Multiple Storage Quad Trees: A Simpler Faster Alternative to Bisector List Quad Trees
Efficient via shifting algorithms in channel compaction
The design and implementation of a concurrent circuit simulation program for multicomputers
An automated and efficient substrate noise analysis tool
CHANCE: Capacitor Charging Management Scheme in Energy Harvesting Systems
C-Testability of Two-Dimensional Iterative Arrays
Mixed block placement via fractional cut recursive bisection
Secure and Low-Delay CAN-FD Communication in Embedded Microcontroller: A Cooperative Swapping Approach
EdgeCompress: Coupling Multidimensional Model Compression and Dynamic Inference for EdgeAI
Automated Design of Analog Circuits Using Reinforcement Learning
Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design
Functional area lower bound and upper bound on multicomponentselection for interval scheduling
Automatic Construction of Predictable and High-Performance Cache Coherence Protocols for Multicore Real-Time Systems
Variability-Aware Multilevel Integrated Spiral Inductor Synthesis
Post-Silicon Validation of Multiprocessor Memory Consistency
Isomorphism-Aware Identification of Custom Instructions With I/O Serialization
Analytical MOSFET model for quarter micron technologies
Constrained via minimization for systolic arrays
Hardware compilation of application-specific memory-access interconnect
An Efficient and Reliable Approach for Semiconductor Device Parameter Extraction
An Empirical Model for the Threshold Voltage of Enhancement NMOSFET's
Hierarchical buffered routing tree generation
Input-driven partitioning methods and application to synthesis on table-lookup-based FPGAs
TRO: An On-Chip Ring Oscillator-Based GHz Transient IR-Drop Monitor
Satisfiability-based test generation for nonseparable RTL controller-datapath circuits
SLS: An Advanced Symbolic Layout System for Bipolar and FET Design
On the design and implementation of a wafer yield editor
Mixed-Cell-Height Placement With Drain-to-Drain Abutment and Region Constraints
Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing
Rubik: A Hierarchical Architecture for Efficient Graph Neural Network Training
Error bound for reduced system model by Pade approximation via the Lanczos process
Accelerate SEU Simulation-Based Fault Injection With Spatio-Temporal Graph Convolutional Networks
Noise Companion State-Space Passive Macromodeling for RF/mm-Wave Circuit Design
COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems
Technology-portable analytical model for DSM CMOS inverter transition-time estimation
A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications
GORDIAN: VLSI placement by quadratic programming and slicing optimization
Dynamic Binary Translation of VLIW Codes on Scalar Architectures
A correctness criterion for asynchronous circuit validation and optimization
Defect-coupled diffusion at high concentrations
Bank on Compute-Near-Memory: Design Space Exploration of Processing-Near-Bank Architectures
A Statistical Framework for Post-Fabrication Oxide Breakdown Reliability Prediction and Management
Formal Probabilistic Timing Verification in RTL
CASA: Contention-Aware Scratchpad Memory Allocation for Online Hybrid On-Chip Memory Management
Geographical Data Structures Compared: A Study of Data Structures Supporting Region Queries
Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects
OPTI-Sim: Performing Optical Probing Simulation on Layout Design Files
Hierarchical synthesis of complex DSP functions using IRIS
Direct Sensitivity Analysis of Nonlinear Distortion in RF Circuits Using Multidimensional Moments
Noise-Aware Quantum Circuit Simulation With Decision Diagrams
Reinforcement Learning-Based Joint Reliability and Performance Optimization for Hybrid-Cache Computing Servers
Analysis of Phase Diffusion Process in Oscillators Due to White and Colored-Noise Sources
Second-order approximations for RLC trees
Efficient datapath merging for partially reconfigurable architectures
Weight Partitioning for Dynamic Fixed-Point Neuromorphic Computing Systems
Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints
PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators
Calculation of Generalized Polynomial-Chaos Basis Functions and Gauss Quadrature Rules in Hierarchical Uncertainty Quantification
An Automatic Optical Simulation-Based Lithography Hotspot Fix Flow for Post-Route Optimization
Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits - Part I
QANS: Toward Quantized Neural Network Adversarial Noise Suppression
Integrated Clock Mesh Synthesis With Incremental Register Placement
HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures
A formal approach to the scheduling problem in high level synthesis
A Low-Overhead Encoding Scheme to Extend the Lifetime of Nonvolatile Memories
OPASCA: Outer Product-Based Accelerator With Unified Architecture for Sparse Convolution and Attention
CapOS: Capacitor Error Resilience for Energy Harvesting Systems
Diagnosing realistic bridging faults with single stuck-at information
Fast Dual-Graph-Based Hotspot Filtering
Bias Busters: Robustifying DL-Based Lithographic Hotspot Detectors Against Backdooring Attacks
The Byzantine hardware fault model
On the Impact of Energy-Accuracy Tradeoff in a Digital Cellular Neural Network for Image Processing
Design of efficient BIST test pattern generators for delay testing
Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching