yusuke1997/dblp-id-title huggingface dataset:
Iesem: Integrated Environment for Software Evolution Management
An Empirical Study on Bugs in PHP
Synchronization of Uncertain Complex Dynamical Networks
Xml Schema Matching
A Software Reliability Model for Cloud-Based Software Rejuvenation Using Dynamic Fault Trees
A Combined Reference Model- and View-Based Approach to System Specification
Multi-Valued Constant Propagation Analysis for User Interface Reengineering
Security versus Compliance: An Empirical Study of the Impact of Industry Standards Compliance on Application Security
Smart Street Litter Detection and Classification Based on Faster R-CNN and Edge Computing
Software Defect Prediction Based on Cost-Sensitive Dictionary Learning
The Program System for Solving Optimal Control Problems with Phase Constraints
An Automated Hybrid Approach for Generating Requirements Trace Links
Automatic Documentation of [Mined] Feature Implementations from Source Code Elements and Use-Case Diagrams with the REVPLINE Approach
Theoretical Analysis and Experiment of A Novel Dep Chip With 3-D Silicon Electrodes
A Framework for the Evaluation of Real-time Specification Techniques
Automated Test Code Generation from Class State Models
Quantifying the effects of Aspectual Decompositions on Design by Contract Modularization: a Maintenance Study
A Tool to Automatically Map Implementation-based Testing Techniques to Classes
Software Architecture - Guest Editors' Introduction
Managing Concern Knowledge in Software Systems
Procedures and Algorithms for Continuous Integration in an Agile Specification Environment
Reliability Model for Component-Based Systems in COSMIC (a Case Study)
Design Level Hypothesis Testing Through Reverse Engineering Of Object-Oriented Software
Automated Generation of Test Trajectories for Embedded Flight Control Systems
Preservation of Class Invariants in Refactoring UML Models
Advancements in Call Graph Methodologies for Enhanced Program Comprehension
A Study of Cross-National Differences in Happiness Factors Using Machine Learning Approach
Feature Selection Method Based on Weighted Mutual Information for Imbalanced Data
Multi-Energy Complementary Scheduling Based on Interval Many-Objective Optimization of Power Grid for Sustainable Cloud Computing Center
A Framework for Tool-Based Software Architecture Reconstruction
Guest Editors' Introduction - Best Papers from SEKE'98
A Collaborative Approach for Minimal-Cost Monitor Deployment in Cloud Environment
Extension of a Simulation Software to Incorporate Quality-Related Factors in Investigations on Software Engineering Economics
An Evaluation of Model-Based Software Synthesis from Simulink Models for Embedded Video Applications
OdegVul: An Approach for Statement-Level Defect Prediction
A New Semantic-based Multi-Level Classification Approach for Activity Recognition Using Smartphones
Split Attention Pointer Network for Source Code Language Modeling
Guest Editor's Introduction: Induction Algorithms
On the Choice of the Best Test for Attribute Dependency in Programs for Learning from Examples
Hw/Sw Co-Design for Low Power Arithmetic and Logic Units
EVCS - A Complete Electronic Virtual Conference System
Addressing Non-Functional Properties in Feature Models: A Goal-Oriented Approach
Security Requirement Representation Method for Confidence of Systems and Networks
Machine Learning Techniques for Code Smells Detection: A Systematic Mapping Study
Authentication and Authorization Management in SOA with the Focus on RESTful Services
A Survey on Problem Formulations and (Meta)Heuristic-Based Solutions in Automated Assembly of Parallel Test Forms
Time Series Classification with Discrete Wavelet Transformed Data
A Version Management Framework for RDF Triple Stores
Conceptual Integrity Without Concepts
End-to-End Neural Video Compression: A Review
UP-GDBF: A 19.3 Gbps Error Floor Free 4KB LDPC Decoder for NAND Flash Applications
Hybrid Timing Error Detector for Baud Rate Multilevel Clock and Data Recovery
Wang Algebra: From Theory to Practice
Self-Reproducing Hidden Attractors in Fractional-Order Chaotic Systems Using Affine Transformations
A New Ultralow-Voltage Retention SRAM Cell Enhancing Noise Immunity
A Stable Digital Impedance Circuit Design Method for Resistive Source Impedances
A Time-to-Voltage Converter With Miller-Impedance Technique for Single-Photon Arrival Time-to-Digital Conversions
A Power Efficiency Enhancements of a Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks
Analog and Mixed Signal Circuit Design Techniques in Flexible Unipolar a-IGZO TFT Technology: Challenges and Recent Trends
Algorithm and VLSI Design for 1-Bit Data Detection in Massive MIMO-OFDM
BAG3++: An Extensible Generator Framework for Automated Layout-Aware AMS Design
Rate-Distortion Optimized Encoding for Deep Image Compression
A Proxy ADC Framework for Side-Channel Secure ADC Analysis
End-to-End Compression Towards Machine Vision: Network Architecture Design and Optimization
ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs
An Energy-Autonomous Power-and-Data Telemetry Circuit With Digital-Assisted-PLL-Based BPSK Demodulator for Implantable Flexible Electronics Applications
RECON: Resource-Efficient CORDIC-Based Neuron Architecture
Welcome to the 5th Volume of the Open Journal of Circuits and Systems
A Low-Power Streaming Speech Enhancement Accelerator for Edge Devices
High Throughput Arithmetic Computing Unit for BFV Homomorphic Encryption
A Control Method for Unbalanced Current in Grid Type Energy Storage Based on Negative Sequence Virtual Impedance
A Lightweight Hybrid Random Number Generator With Dynamic Entropy Injection
Editorial to the Special Section on Optimized Image/Video Coding Based on Deep Learning
PG-CAS: Pro-Active EM-SCA Probe Detection Using Switched-Capacitor-Based Patterned-Ground Co-Planar Capacitive Asymmetry Sensing
A Wireless Power Conversion Chain With Fully On-Chip Automatic Resonance Tuning System for Biomedical Implants
A Radar-Based System for Detection of Human Fall Utilizing Analog Hardware Architectures of Decision Tree Model
RF Analog Hardware Trojan Detection Through Electromagnetic Side-Channel
Homomorphic Evaluation Cluster Architecture for Fully Homomorphic Encryption
Guest Editorial Circuits and Systems for Flexible Electronics
Multichannel Many-Class Real-Time Neural Spike Sorting With Convolutional Neural Networks
An Integrated Fully Differential Current Amplifier With Frequency Compensation for Inductive Sensor Excitation
A 130 nm-SiGe-BiCMOS Low-Power Receiver Based on Distributed Amplifier Techniques for Broadband Applications From 140 GHz to 200 GHz
Generalized Mittag-Leffler Input Stability of the Fractional-Order Electrical Circuits
Circuits and Systems Issues in Power Electronics Penetrated Power Grid
A 2 Bit/Cell Tilting SRAM-Based PUF With a BER of 3.1E-10 and an Energy of 21 FJ/Bit in 65nm
Towards the Co-Simulation of Charge Qubits: A Methodology Grounding on an Equivalent Circuit Representation
Comparison of High-Order Programmable Mismatch Shaping Bandpass DEM Implementations Applicable to Nyquist-Rate D/A Converters
Analysis and Design of an Optimal Noise Estimation and Cancellation Filter in Wireline Communication
A Low-Loss T/R Module With Balanced Power Amplifier for High Antenna Impedance Tolerance
Thermal Heating in ReRAM Crossbar Arrays: Challenges and Solutions
Jammer Mitigation via Beam-Slicing for Low-Resolution mmWave Massive MU-MIMO
Influence of PVT Variation and Threshold Selection on OBT and OBIST Fault Detection in RFCMOS Amplifiers
Introduction to the Special Section on Smart Imaging
Deep Reinforcement Learning on FPGA for Self-Healing Cryogenic Power Amplifier Control
Correction to "Brain-Inspired Computing: Models and Architectures"
ASIC Current-Reuse Amplifier With MEMS Delta-E Magnetic Field Sensors
Bayesian Neural Networks for Identification and Classification of Radio Frequency Transmitters Using Power Amplifiers' Nonlinearity Signatures
A Complementary Ring Mixer Driven by a Single-Ended LO in 22-nm FD-SOI CMOS for K and Ka-Bands
A High-Efficiency Dual-Antenna RF Energy Harvesting System Using Full-Energy Extraction With Improved Input Power Response
NLU: An Adaptive, Small-Footprint, Low-Power Neural Learning Unit for Edge and IoT Applications
Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs
A Power Transistor Active Gate Driver With Two-Level Miller Plateau Detection and Driving Device Equalization Using 180-nm HV BCD Process
A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing
Electrical Impedance Tomography for Biomedical Applications: Circuits and Systems Review
Use of Negative Impedance Converters for Bandwidth Extension of Optical Transmitters
Polychronous Oscillatory Cellular Neural Networks for Solving Graph Coloring Problems
Nonlinear Fractional-Order Circuits and Systems: Motivation, A Brief Overview, and Some Future Directions
VLSI Architectures for Reed-Solomon Codes: Classic, Nested, Coupled, and Beyond
Inaugural Issue of the IEEE Open Journal of Circuits and Systems: Welcome Note
Novel and Optimal Luma Modification-Based Chroma Downsampling for Bayer Color Filter Array Images
Multi-Feature 360 Video Quality Estimation
Theoretical Analysis of Multi Integrating RX Front-Ends for Lossy Broad-Band Channels
Highly-Efficient Hardware Architecture for ML-KEM PQC Standard
A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s
Editorial: Where Are We Now and Where Do We Go From Here
Principle of Self-Support (PSS) and Its Extensions With Fractional Calculus and Event-Triggered Scheme
Analysis and Verilog-A Modeling of Floating-Gate Transistors
A 30-70MHz Delay-Line-Based Multiphase 50A 5.14 A/mm² Fully Integrated Voltage Regulator
A Small Tamper-Resistant Anti-Recycling IC Sensor With a Reused I/O Interface and DC Signalling
A Resistor-Less nW-Level Bandgap Reference With Fine-Grained Voltage and Temperature Coefficient Trims
Exploiting Neural-Network Statistics for Low-Power DNN Inference
Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based on Booth Multiplier and WALLACE Tree Adders
Channel Estimation for Advanced 5G/6G Use Cases on a Vector Digital Signal Processor
Double MAC on a Cell: A 22-nm 8T-SRAM-Based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline
A Generalized Active Voltage Balancing Circuit Implementation for Flying Capacitor 3-Level Switching-Mode DC-DC Converters
An Energy Efficient EdgeAI Autoencoder Accelerator for Reinforcement Learning
Codec-Simulation Network for Joint Optimization of Video Coding With Pre- and Post-Processing
Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability
Biologically-Inspired, Ultra-Low Power, and High-Speed Integrate-and-Fire Neuron Circuit With Stochastic Behavior Using Nanoscale Side-Contacted Field Effect Diode Technology
Ultralow-Voltage Retention SRAM With a Power Gating Cell Architecture Using Header and Footer Power-Switches
Class-CTA: Concept and Theoretical Analysis of a High Linearity and Efficiency Power Stage Architecture
Elementary Derivation of the Nyquist Criterion for Fractional-Order Feedback Systems
A Study of Out-of-Band Emission in Digital Transmitters Due to PLL Phase Noise, Circuit Non-Linearity, and Bandwidth Limitation
Synthesis-Free Trap Exchanges for LC Ladder Networks
Energy Efficiency of Uplink Cell-Free Massive MIMO With Transmit Power Control in Measured Propagation Channel
Sampling and Comparator Speed-Enhancement Techniques for Near-Threshold SAR ADCs
Improving Neural Network Fault Tolerance Against Weight Attack
RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training
New Year Editorial 2023
A High Efficient Cross-Coupled Active Rectifier by Using High Speed Switching Comparators for Wireless Power Receiver
Learning-Based Predictive Virtual Inertia Control for Frequency Regulation in Low Inertia Power Grids
Toward Intelligent Reconfigurable Wireless Physical Layer (PHY)
A Computer Vision-Based Framework for Snow Removal Operation Routing
A Review on Sub-0.21-V Ultra-Low-Supply-Voltage Analog-to-Digital Converters
Energy-Efficient Accelerator Design With Tile-Based Row-Independent Compressed Memory for Sparse Compressed Convolutional Neural Networks
An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI
Performance Prediction of Incremental ΔΣ ADCs
A Comparative Study of Dynamic Comparators for Low-Power Successive Approximation ADC
A Nearly Interference-Free and Depth-Resolution-Configurable Time-of-Flight System Based on a Mega-Pixel Vertical Avalanche Photodiodes CMOS Image Sensor
Hardware-Aware Design for Edge Intelligence
Context-Adaptive Inverse Quantization for Inter-Frame Coding
Nonlinear Analysis of Differential LC Oscillators and Injection Locked Frequency Dividers
Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique
Efficient Design of Zero-Phase Riesz Fractional Order Digital Differentiator Using Manta-Ray Foraging Optimisation for Precise Electrocardiogram QRS Detection
DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation
Low-Power On-Chip Energy Harvesting: From Interface Circuits Perspective
Interchannel Mismatch Calibration Techniques for Time-Interleaved SAR ADCs
Complex Synchronization Dynamics of Electronic Oscillators-Part I: A Time-Domain Approach via Phase-Amplitude Reduced Models
V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation
A 0.61-μJ/Frame Pipelined Wired-logic DNN Processor in 16-nm FPGA Using Convolutional Non-Linear Neural Network
Analysis and Experimental Validation of Large-Signal Linearization for Low-Power Complex OTA-C Filters
Computation of Graph Fourier Transform Centrality Using Graph Filter
A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier
Voltage Reference and Voltage Regulator for the Cryogenic Performance Evaluation of the 22nm FDSOI Technology
Analysis of Discrete-Time Integrating Amplifiers as an Alternative to Continuous-Time Amplifiers in Broadband Receivers
Impact of Frequency Heterogeneity on Mutually Synchronized Spatially Distributed 24 GHz PLLs
Systematic Design of Ring VCO-Based SNN - Translating Training Parameters to Circuits
A Brief Tutorial on Mixed Signal Approaches to Combat Electronic Counterfeiting
New Year Editorial
Droop-Controlled Bidirectional Inverter-Based Microgrid Using Cascade-Forward Neural Networks
IEEE Open Journal of Circuits and Systems: Special Section on ISICAS 2022
A Design of Fault-Tolerant Battery Monitoring IC for Electric Vehicles Complying With ISO 26262
Guest Editorial Introduction to the Special Section on Nonlinear Fractional-Order Circuits and Systems: Advanced Analysis and Effective Implementation
Self-Healing Router Approach for High-Performance Network-on-Chip
Editorial on the Special Section on the 2021 IEEE International Symposium on Integrated Circuits and Systems
Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS
Revolutionize 3D-Chip Design With Open3DFlow, an Open-Source AI-Enhanced Solution
A Detailed Model of the Switched-Resistor Technique
Circuit Simulation of Any Time-Domain Source on Fractional-Order Impedances by Use of the Haar Wavelet Transform, Case Study of the Skin Effect
Grant-Free Sparse Code Multiple Access for Uplink Massive Machine-Type Communications and Its Real-Time Receiver Design
Optimized Periodic ΣΔ Bitstreams for DC Signal Generation Used in Dynamic Calibration Applications
Review of Resonator's Q-Factor Measurement With Focus on Design of Analog and Mixed Circuits for In-Situ Measurement
A Low-Noise High-Gain Broadband Transformer-Based Inverter-Based Transimpedance Amplifier
A Test Setup for the Characterization of Lorentz-Force MEMS Magnetometers
Correction to "RECON: Resource-Efficient CORDIC-Based Neuron Architecture"
Low-Latency Burst Error Detection and Correction in Decision-Feedback Equalization
IGZO-TFT-PDK: Thin-Film Flexible Electronics Design Kit, Standard Cell and Design Methodology
A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications
Reversible Gates: A Paradigm Shift in Computing
A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology
A Temperature-Aware Framework on g m /I D -Based Methodology Using 180 nm SOI From -40 °C to 200 °C
Optimization of Quantized Analog Signal Processing Using Genetic Algorithms and μ-Law
Design of a High Efficiency Bi-Directional Four-Switch Buck-Boost Converter With HV Gate Driver for Multi-Cell Battery Power Bank Applications
Double-Channel Constant Voltage Output Design in Magnetically Coupled Wireless Power Transfer Systems With the Anti-Misalignment Capability
Massive Machine-Type Communication Pilot-Hopping Sequence Detection Architectures Based on Non-Negative Least Squares for Grant-Free Random Access
Evolving Flexible Sensors, Wearable and Implantable Technologies Towards BodyNET for Advanced Healthcare and Reinforced Life Quality
Guest Editorial Special Section on IEEE ICME 2020
Energy Consumption Modeling of 2-D and 3-D Decoder Circuits
Methodologies for Synthesizing and Analyzing Dynamic Dataflow Programs in Heterogeneous Systems for Edge Computing
AI-Enhanced Wide Supply Voltage Bandgap Voltage Reference Circuit With Multi-Objective Optimization for Automotive Applications
A Low-Rank CNN Architecture for Real-Time Semantic Segmentation in Visual SLAM Applications
An Efficient Filter-Bank Multi-Carrier System for High-Speed Wireline Applications
Self-Repairing Carry-Lookahead Adder With Hot-Standby Topology Using Fault-Localization and Partial Reconfiguration
MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI
A High-Frequency/Power Ratio Wilkinson Power Divider Based on Identical/Non-Identical Multi-T-Sections With Short-Circuited Stubs
Controlling Chaos for a Fractional-Order Discrete System
An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process
Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications
IQNet: Image Quality Assessment Guided Just Noticeable Difference Prefiltering for Versatile Video Coding
Comprehensive Mapping of Continuous/Switching Circuits in CCM and DCM to Machine Learning Domain Using Homogeneous Graph Neural Networks
A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects
AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design
Predicting Ventricular Defibrillation Results Using Learning Models: A Design Practice and Performance Analysis
A 45Gb/s Analog Multi-Tone Receiver Utilizing a 6-Tap MIMO-FFE in 22nm FDSOI
A Sub-mW Cortex-M4 Microcontroller Design for IoT Software-Defined Radios
Comparison and Design of Linear and Exponential Integrated Charge Pumps
FantastIC4: A Hardware-Software Co-Design Approach for Efficiently Running 4Bit-Compact Multilayer Perceptrons
Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices
A 672-nW, 670-nVrms ECG Acquisition AFE With Noise-Tolerant Heartbeat Detector
Performance Comparison of Baseband Signaling and Discrete Multi-Tone for Wireline Communication
Flexible Multi-Channel Analog-Frontend for Ultra-Low Power Environmental Sensing
Adaptive Control Technique for Portable Solar Powered EV Charging Adapter to Operate in Remote Location
Design Space Exploration of Single-Lane OFDM-Based Serial Links for High-Speed Wireline Communications
A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC
A 116 TOPS/W Spatially Unrolled Time-Domain Accelerator Utilizing Laddered-Inverter DTC for Energy-Efficient Edge Computing in 65 nm
A Companding Technique to Reduce Peak-to-Average Ratio in Discrete Multitone Wireline Receivers
A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories
L-Sort: On-Chip Spike Sorting With Efficient Median-of-Median Detection and Localization-Based Clustering
A Natively Fixed-Point Run-Time Reconfigurable FIR Filter Design Method for FPGA Hardware
Analysis and Design Methodology of RF Energy Harvesting Rectifier Circuit for Ultra-Low Power Applications
Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization
Physical Time-Varying Transfer Function as Generic Low-Overhead Power-SCA Countermeasure
Asymptotic Performance Limitations in Cyberattack Detection
A Vision System With 1-inch 17-Mpixel 1000-fps Block-Controlled Coded-Exposure Stacked-CMOS Image Sensor for Computational Imaging and Adaptive Dynamic Range Control
MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching
Synchronization and Channel Estimation Design for Multi-Stream MIMO System in Sub-Terahertz Channel Model
An Ultra-Wideband Reference Frequency Chirp Generator Utilizing Fractional Frequency Divider With High Linearity
Slimmer CNNs Through Feature Approximation and Kernel Size Reduction
Applicability of Hyperdimensional Computing to Seizure Detection
A 2D Chaotic Oscillator for Analog IC
An Efficient K-Best MIMO Detector for Large Modulation Constellations
Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs
Low-Voltage Gate-Leakage-Based Timer Using an Amplifier-Less Replica-Bias Switching Technique in 55-nm DDC CMOS
Special Issue on Selected Papers From APCCAS 2022
ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node Devices
Loop Dynamics Analysis of PAM-4 Mueller-Muller Clock and Data Recovery System
A Nano-Watt Dual-Output Subthreshold CMOS Voltage Reference
An Ultra-Low-Voltage Single-Crystal Oscillator-Timer (XO-Timer) Delivering 16-MHz and 32.258-kHz Clocks for Sub-0.5-V Energy-Harvesting BLE Radios in 28-nm CMOS
Special Section on Edge AI and Accelerators
An Efficient Selection-Based kNN Architecture for Smart Embedded Hardware Accelerators
Editorial on the Special Section on Algorithms, Circuits, and Systems for Signal Processing at the Edge
StrideHD: A Binary Hyperdimensional Computing System Utilizing Window Striding for Image Classification
Learned Image Compression With Separate Hyperprior Decoders
Application of Envelope-Following Techniques to the Shooting Method
Binary Classifiers for Data Integrity Detection in Wearable IoT Edge Devices
Brain-Inspired Computing: Models and Architectures
Automated Fixed-Point Precision Optimization for FPGA Synthesis
Deterministic Noise Analysis for Single-Stage Amplifiers by Extension of Indefinite Admittance Matrix
Hardware Efficient Speech Enhancement With Noise Aware Multi-Target Deep Learning
ANFIC: Image Compression Using Augmented Normalizing Flows
FBMC vs. PAM and DMT for High-Speed Wireline Communication
A Solution of the Two-Capacitor Problem Through its Similarity to Single-Electron Electronics
Editorial IEEE Open Journal of Circuits and Systems: Special Section on Advanced Power Electronics Techniques for Smart Grid Applications
SEKV-E: Parameter Extractor of Simplified EKV I-V Model for Low-Power Analog Circuits
Flexible PCB Failures From Dynamic Activity and Their Impacts on Bioimpedance Measurements: A Wearable Case Study
An Arbitrarily Reconfigurable Extreme Learning Machine Inference Engine for Robust ECG Anomaly Detection
Design and Implementation of an On-Demand Maximum-Likelihood Sequence Estimation (MLSE)
GC-Like LDPC Code Construction and its NN-Aided Decoder Implementation
Guest Editorial Circuits, Systems, and Algorithms for Beyond 5G and Toward 6G
Complex Synchronization Dynamics of Electronic Oscillators-Part II: Simulations and Validation of Phase-Amplitude Reduced Models
FPGA-Based Tensor Compressive Sensing Reconstruction Processor for Terahertz Single-Pixel Imaging Systems
Stability Boundaries of Wide-Input-Range COT Buck Converters With Ripple Compensation
Demonstrating Analog Inference on the BrainScaleS-2 Mobile System