yusuke1997/dblp-id-title huggingface dataset:
A Genetic Algorithm-Based Heuristic Method for Test Set Generation in Reversible Circuits
Efficient Test Compression Configuration Selection
SRAF Insertion via Supervised Dictionary Learning
Estimation of maximum currents in MOS IC logic circuits
Algorithms for hardware allocation in data path synthesis
Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power
Model-to-Circuit Cross-Approximation For Printed Machine Learning Classifiers
Layout Aware Optimization Methodology for SOT-MRAM Based on Technically Feasible Top-Pinned Magnetic Tunnel Junction Process
Newton waveform relaxation techniques for tightly coupled systems
Autonomous Multicycle Tests With Low Storage and Test Application Time Overheads
Performance Enhancement of SMR-Based Deduplication Systems
Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms
A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification
Optimization Approach to Accelerator Codesign
Fault Diagnosis for Leakage and Blockage Defects in Flow-Based Microfluidic Biochips
Efficient Methods for Large Resistor Networks
Process Variation-Aware Test for Resistive Bridges
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
Synthesis of arithmetic circuits considering layout effects
Variation-Aware Placement With Multi-Cycle Statistical Timing Analysis for FPGAs
Heterogeneous Behavioral Hierarchy Extensions for SystemC
RoSE-Opt: Robust and Efficient Analog Circuit Parameter Optimization With Knowledge-Infused Reinforcement Learning
MR: a new framework for multilevel full-chip routing
DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect
OASYS: a framework for analog circuit synthesis
Synthesis of power-managed sequential components based oncomputational kernel extraction
Efficient simulation of MOS circuits
Secure Randomized Checkpointing for Digital Microfluidic Biochips
A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs
Automatic generation of analytical models for interconnect capacitances
Numerically Convex Forms and Their Application in Gate Sizing
Minimum area layout of series-parallel transistor networks is NP-hard
Design and Experimental Evolution of Memristor With Only One VDTA and One Capacitor
A provably passive and cost-efficient model for inductive interconnects
Spintronic Memristor-Based Binarized Ensemble Convolutional Neural Network Architectures
Locality-Driven Parallel Power Grid Optimization
Statistical Thermal Profile Considering Process Variations: Analysis and Applications
Robust Boolean reasoning for equivalence checking and functional property verification
WATOPT -- An Optimizer for Circuit Applications
FSpiNN: An Optimization Framework for Memory-Efficient and Energy-Efficient Spiking Neural Networks
A General Framework for Hardware Trojan Detection in Digital Circuits by Statistical Learning Algorithms
Performance-driven channel pin assignment algorithms
Exploiting Parallelism for Improved Automation of Multidimensional Model Order Reduction
Para-Pipe: Exploiting Hierarchical Operator Parallelism of ML Computational Graphs on SoCs
TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits
The ADAM design planning engine
Reconfigurable and High-Efficiency Polynomial Multiplication Accelerator for CRYSTALS-Kyber
Thermal Models for Optical Circuit Simulation Using a Finite Cloud Method and Model Reduction Techniques
Control-Layer Routing and Control-Pin Minimization for Flow-Based Microfluidic Biochips
Optimum CMOS stack generation with analog constraints
DCR: Deterministic Crash Recovery for NAND Flash Storage Systems
Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits
Use of Computation-Unit Integrated Memories in High-Level Synthesis
HLock+: A Robust and Low-Overhead Logic Locking at the High-Level Language
Performance-driven high-level synthesis with bit-level chaining andclock selection
Many-Core Token-Based Adaptive Power Gating
Optimizing designs using the addition of deflection operations
Divergence and scheduling in functional level concurrent fault simulation
Efficient algorithms of wiring channels with movable terminals
WinDConv: A Fused Datapath CNN Accelerator for Power-Efficient Edge Devices
Synthesis for path delay fault testability via tautology-based untestability identification and factorization
Methodology for electromigration critical threshold design rule evaluation
Real-Time 3-D Thermal Simulation of Advanced Packages via Generative Adversarial Networks
SimDiff: Point Cloud Acceleration by Utilizing Spatial Similarity and Differential Execution
Improving Diagnosis Through Failing Behavior Identification
TurboMOR-RC: An Efficient Model Order Reduction Technique for RC Networks With Many Ports
Closing the gap: near-optimal Steiner trees in polynomial time
Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation
High-Speed Logic Simulation on Vector Processors
Faster maximum and minimum mean cycle algorithms for system-performance analysis
Prediction of analog performance parameters using fast transienttesting
Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process
REMAP: A Spatiotemporal CNN Accelerator Optimization Methodology and Toolkit Thereof
Quadratic Backward Propagation of Variance for Nonlinear Statistical Circuit Modeling
HORNET: A Cycle-Level Multicore Simulator
Specification-Guided Automated Debugging of CPS Models
LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults
Latent RAGE: Randomness Assessment Using Generative Entropy Models
Probability distribution of signal arrival times using Bayesian networks
MemMIMO: A Simulation Framework for Memristor-Based Massive MIMO Acceleration
A New Strategy for Simultaneous Escape Based on Boundary Routing
Handling the pin overhead problem of DFTs for high-quality and at-speed tests
Simulation of MOS Circuits by Decision Diagrams
Design and Blocking Analysis of Locking Protocols for Real-Time DAG Tasks Under Federated Scheduling
Boolean Gröbner Basis Reductions on Finite Field Datapath Circuits Using the Unate Cube Set Algebra
A Unified Framework for Period and Priority Optimization in Distributed Hard Real-Time Systems
eRDAC: Efficient and Reliable Remote Direct Access and Control for Embedded Systems
Efficient synthesis of OTA network for linear analog functions
Power-Performance Analysis of Networks-on-Chip With Arbitrary Buffer Allocation Schemes
GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks
An Extended Nonstrict Partially Ordered Set-Based Configurable Linear Sorter on FPGAs
Durable and Energy Efficient In-Memory Frequent-Pattern Mining
Synchronous logic synthesis: algorithms for cycle-time minimization
Hierarchical analysis of high frequency interconnect networks
Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations
Predicting system-level area and delay for pipelined and nonpipelined designs
Power Optimization With Power Islands Synthesis
Cellular automata-based pseudorandom number generators for built-in self-test
More Efficient Testing of Metal-Oxide Memristor-Based Memory
On the realizability and synthesis of delay-insensitive behaviors
Dedicated Instruction Set for Pattern-Based Data Transfers: An Experimental Validation on Systems Containing In-Memory Computing Units
Online Reset for Signal Temporal Logic Monitoring
Germanium- and Silicon-Nanotransistor Designs by Electrical and Thermal Self-Consistent Analysis
Multifrequency TAM design for hierarchical SOCs
Modular verification of timed circuits using automatic abstraction
PVoT: Reconfigurable Photovoltaic Array for Indoor Light Energy-Powered Batteryless Devices
A weighted random pattern test generation system
Energy-Efficient Datacenters
HPE: Hierarchical Page Eviction Policy for Unified Memory in GPUs
Aliasing in signature analysis testing with multiple input shift registers
An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators
On Cosimulating Multiple Abstraction-Level System-Level Models
Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead
Capacitive coupling noise in high-speed VLSI circuits
Reduced offsets for minimization of binary-valued functions
Testing and Enhancing Adversarial Robustness of Hyperdimensional Computing
SAMC: a code compression algorithm for embedded processors
Response-Time Analysis of Limited-Preemptive Sporadic DAG Tasks
An Efficient Single-Row Routing Algorithm
FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability
Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors
AMGIE-A synthesis environment for CMOS analog integrated circuits
Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits
Update Frequency-Directed Subpage Management for Mitigating Garbage Collection and DRAM Overheads
Balanced partitioning
Register File Power Reduction Using Bypass Sensitive Compiler
QHLS: An HLS Framework to Convert High-Level Descriptions to Quantum Circuits
RF Switched-Capacitor Power Amplifier Modeling
On modeling crosstalk faults
Exploring Efficient Hardware Accelerator for Learning-Based Image Compression
Comparison of statistical enhancement methods for Monte Carlo semiconductor simulation
Lexicographical expressions of Boolean functions with application to multilevel synthesis
PLATYPUS: A PLA Test Pattern Generation Tool
Sparse Tucker Tensor Decomposition on a Hybrid FPGA-CPU Platform
Pseudo-exhaustive built-in TPG for sequential circuits
DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography
Optimizing interacting finite state machines using sequential don't cares
Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics
Programmable Leakage Test and Binning for TSVs With Self-Timed Timing Control
A New 3-D Fuse Architecture to Improve Yield of 3-D Memories
On smoothing three-dimensional Monte Carlo ion implantation simulation results
Ghostbuster: A Software Approach for Reducing Ghosting Effect on Electrophoretic Displays
Defect-Oriented Testing of RF Circuits
Access-Time Minimization for the IJTAG Network Using Data Broadcast and Hardware Parallelism
Mixed-Cell-Height Legalization Considering Technology and Region Constraints
AdaPT: Fast Emulation of Approximate DNN Accelerators in PyTorch
Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants
A fast technique based on perfectly matched layers for the full-wave solution of 2-D dispersive microstrip lines
Time-Division Multiplexing for Testing DVFS-Based SoCs
An efficient algorithm for some multirow layout problems
An efficient algorithm for VLSI network partitioning problem using a cost function with balancing factor
Floating Random Walk-Based Capacitance Extraction for General Non-Manhattan Conductor Structures
Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation
On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug
Adjoint Sensitivity Analysis of Nonlinear Distortion in Radio Frequency Circuits
FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
Intermittent Computing Emulation of Ultralow-Power Processors: Evaluation of Backup Strategies for RISC-V
Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding
An Efficient Independent Read Scheme for Contemporary QLC SSDs
An Efficient Low-Power BIST for Automotive SoC With Periodic Pattern Type Selection
Advanced Functional Decomposition Using Majority and Its Applications
HardGBM: A Framework for Accurate and Hardware-Efficient Gradient Boosting Machines
Optimization of Multi-Target Sample Preparation On-Demand With Digital Microfluidic Biochips
Solution of the hydrodynamic device model using high-order nonoscillatory shock capturing algorithms
A submicron DC MOSFET model for simulation of analog circuits
Automatic Placement to Improve Capacitance Matching Using a Generalized Common-Centroid Layout and Spatial Correlation Optimization
Web-based IP evaluation and distribution using applets
EBIST: a novel test generator with built-in fault detection capability
The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method
Identifying Wafer-Level Systematic Failure Patterns via Unsupervised Learning
Swarm Intelligence-Based Task Scheduling for Enhancing Security for IoT Devices
Game Theoretic Feedback Control for Reliability Enhancement of EtherCAT-Based Networked Systems
Computer Aided Design of a Microscale Digitally Controlled Hydraulic Resistor
Fault-coverage analysis techniques of crosstalk in chip interconnects
System-Level Design Space Exploration for High-Level Synthesis Under End-to-End Latency Constraints
Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs
Yield enhancement of programmable ASIC arrays by reconfiguration of circuit placements
Approximate Logic Synthesis Using Boolean Matrix Factorization
An application-level synthesis methodology for multidimensional embedded processing systems
Adaptive Reduction of the Frequency Search Space for Multi-V dd Digital Circuits Using Variation Sensitive Ring Oscillators
Accelerating Gate Sizing Using Graphics Processing Units
Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon
LoCool: Fighting Hot Spots Locally for Improving System Energy Efficiency
Analog Circuit Design Knowledge Mining: Discovering Topological Similarities and Uncovering Design Reasoning Strategies
A Don't-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks
A Hierarchy-Based Distributed Algorithm for Layout Geometry Operations
A test methodology for wafer scale system
General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
Vertical Arbitration-Free 3-D NoCs
Online Soft-Error Vulnerability Estimation for Memory Arrays and Logic Cores
Fingerprinting techniques for field-programmable gate arrayintellectual property protection
Planting Fast-Growing Forest by Leveraging the Asymmetric Read/Write Latency of NVRAM-Based Systems
Transition reduction in memory buses using sector-based encoding techniques
A computationally efficient unified approach to the numerical analysis of the sensitivity and noise of semiconductor devices
Iterative algorithms for computing aliasing probabilities
Detection, Diagnosis, and Recovery From Clock-Domain Crossing Failures in Multiclock SoCs
Poor man's TBR: a simple model reduction scheme
SSSL: Secure Search Space Locking of Behavioral IPs
Dynamic Driver Supply Voltage Scaling for Organic Light Emitting Diode Displays
Lump Partitioning of IC Bipolar Transistor Models for High-Frequency Applications
Current-limited switch-level timing simulator for MOS logic networks
Intra-task voltage scheduling on DVS-enabled hard real-time systems
Automated Topology Synthesis of Analog Integrated Circuits With Frequency Compensation
Behavioral modeling and performance evaluation of microelectrofluidics-based PCR systems using SystemC
Model-Based Adaptation of Mixed-Criticality Multiservice Systems for Extreme Physical Environments
A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling
A Novel Implementation Methodology for Error Correction Codes on a Neuromorphic Architecture
Delay and current estimation in a CMOS inverter with an RC load
Digital Simulation with Multiple Logic Values
On covering distant minterms by the camp algorithm
PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method
Formal Guarantees for Localized Bug Fixes
Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space
Grid adaption near moving boundaries in two dimensions for IC process simulation
Rigorous three-dimensional photoresist exposure and development simulation over nonplanar topography
Corner-stitched tiles with curved boundaries [circuit layout]
GEM: A Generalized Memristor Device Modeling Framework Based on Neural Network for Transient Circuit Simulation
Enhancing Superset X-Canceling Method With Relaxed Constraints on Fault Observation
Table Lookup MOSFET Capacitance Model for Short-Channel Devices
Efficient Thermal Simulation for 3-D IC With Thermal Through-Silicon Vias
Exploiting communication complexity for multilevel logic synthesis
Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures
SPFD-based wire removal in standard-cell and network-of-PLA circuits
SMART: Graph Learning-Boosted Subcircuit Matching for Large-Scale Analog Circuits
Structural and behavioral synthesis for testability techniques
A New Two-Dimensional Silicon Oxidation Model
A Simulation-Guided Paradigm for Logic Synthesis and Verification
Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects
Dual Algorithms for Vectorless Power Grid Verification Under Linear Current Constraints
Graceful Performance Modulation for Power-Neutral Transient Computing Systems
Algorithms for an FPGA switch module routing problem with application to global routing
Adaptive meshing schemes for simulating dopant diffusion
Extended Sequential Logic for Synchronous Circuit Optimization and Its Applications
URBER: Ultrafast Rule-Based Escape Routing Method for Large-Scale Sample Delivery Biochips
The Outline Procedure in Pattern Data Preparation for Vector-Scan Electron-Beam Lithography
Run-Time Task Allocation Considering User Behavior in Embedded Multiprocessor Networks-on-Chip
MaizeRouter: Engineering an Effective Global Router
STBM: a fast algorithm to simulate I DDQ tests forleakage faults
B*-Sort: Enabling Write-Once Sorting for Nonvolatile Memory
Bounded Model Debugging
Intermittent-Friendly Neural Architecture Search: Demystifying Accuracy and Overhead Tradeoffs
BAMBI -- A Design Model for Power MOSFET's
FGNN2: A Powerful Pretraining Framework for Learning the Logic Functionality of Circuits
OPTiC: Optimizing Collaborative CPU-GPU Computing on Mobile Devices With Thermal Constraints
Improving the performance of parallel relaxation-based circuit simulators
JFET circuit simulation using SPICE implemented with an improved model
Probabilistic simulation for reliability analysis of CMOS VLSI circuits
Identification of redundant delay faults
Two NP-hard interchangeable terminal problems
Symmetry within the sequence-pair representation in the context ofplacement for analog design
An analysis of the wire-load model uncertainty problem
Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA)
USE: A Universal, Scalable, and Efficient Clocking Scheme for QCA
Synthesizing controllers from real-time specifications
ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs
Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes
Automated Testing Flow: The Present and the Future
A Probe-Based Harmonic Balance Method to Simulate Coupled Oscillators
Decision-Theoretic Design Space Exploration of Multiprocessor Platforms
Layout-Based Modeling and Mitigation of Multiple Event Transients
Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design
Accurate and Robust Malware Detection: Running XGBoost on Runtime Data From Performance Counters
New discretization scheme for two-dimensional semiconductor device simulation on triangular grid
Testing for multiple faults in domino-CMOS logic circuits
Area minimization of power distribution network using efficient nonlinear programming techniques
Enhanced and Efficient Guiding Template Design for Lamellar DSA With Graph Monomorphism
Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment
vmPTP: Precise Time Protocol for Inter-VM Communication in Embedded Virtualized Systems
Architecture Considerations for Stochastic Computing Accelerators
Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves
New approximation algorithms for routing with multiport terminals
Energy-Efficient DNN Inferencing on ReRAM-Based PIM Accelerators Using Heterogeneous Operation Units
Maximum-Utility Scheduling of Operation Modes With Probabilistic Task Execution Times Under Energy Constraints
Electronic System-Level Synthesis Methodologies
Error-Correcting Unordered Codes and Hardware Support for Robust Asynchronous Global Communication
LFSR-Based Test Generation for Path Delay Faults
Robust Estimation of Timing Yield With Partial Statistical Information on Process Variations
Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment
Toward accurate models of achievable routing
Synthesis of Reconfigurable Flow-Based Biochips for Scalable Single-Cell Screening
SmartHeating: On the Performance and Lifetime Improvement of Self-Healing SSDs
WCRT Analysis and Evaluation for Sporadic Message-Processing Tasks in Multicore Automotive Gateways
Clock skew verification in the presence of IR-drop in the powerdistribution network
Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits
Sobol Sequence Optimization for Hardware-Efficient Vector Symbolic Architectures
Direct Search Procedure for Functional Compaction With Improved Fault Coverage
Reliable Macromodel Generation for the Capacitance Extraction Based on Macromodel-Aware Random Walk Algorithm
SRNoC: An Ultra-Fast Configurable FPGA-Based NoC Simulator Using Switch-Router Architecture
A computer simulation model for simulating distortion in FETresistors
Multilevel circuit partitioning
Polynomial-Time T-Depth Optimization of Clifford+T Circuits Via Matroid Partitioning
On empty rooms in floorplan graphics: comments on a deficiency in two papers
Incremental Large-Scale Electrostatic Analysis
A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning
Design of Low-Complexity FIR Filters Based on Signed-Powers-of-Two Coefficients With Reusable Common Subexpressions
Scalable Verification of a Generic End-Around-Carry Adder for Floating-Point Units by Coq
Efficient Scheduling of Irregular Network Structures on CNN Accelerators
Algorithms for Maze Routing With Exact Matching Constraints
Heterogeneous FPGA-Based Cost-Optimal Design for Timing-Constrained CNNs
Geometric Programming Approach to Glitch Minimization via Gate Sizing
Parametric Critical Path Analysis for Event Networks With Minimal and Maximal Time Lags
Incorporating bottom-up design into hardware synthesis
A voltage dependent capacitance model including effects of manufacturing process variabilities on voltage coefficients
Retention-Aware Read Acceleration Strategy for LDPC-Based NAND Flash Memory
Obstacle-Avoiding Rectilinear Steiner Tree Construction: A Steiner-Point-Based Algorithm
The pseudoexhaustive test of sequential circuits
Analytical approaches to the combinatorial optimization in linear placement problems
Increasing the Efficiency of Simulation-Based Functional Verification Through Unsupervised Support Vector Analysis
Zero-aliasing space compaction using linear compactors with bounded overhead
A Bus-Encoding Scheme for Crosstalk Elimination in High-Performance Processor Design
HALTRAV: Design of a High-Performance and Area-Efficient Latch With Triple-Node-Upset Recovery and Algorithm-Based Verifications
Length-Matching-Constrained Region Routing in Rapid Single-Flux-Quantum Circuits
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs