yusuke1997/dblp-id-title huggingface dataset:
Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs
A design scheme for PLA-based control tables with reduced area and time-delay cost
An Interlayer Interconnect BIST and Diagnosis Solution for Monolithic 3-D ICs
Fast Online Synthesis of Digital Microfluidic Biochips
Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages
Tamper Resistant Reconfigurable Preamplifier Physical Unclonable Function With Self-Destruct
NBLG: A Robust Legalizer for Mixed-Cell-Height Modern Design
Pre-Silicon Bug Forecast
Changepoint-Based Anomaly Detection for Prognostic Diagnosis in a Core Router System
Design of Ultracompact Content Addressable Memory Exploiting 1T-1MTJ Cell
A timing-constrained simultaneous global routing algorithm
Interval graph algorithms for two-dimensional multiple folding of array-based VLSI layouts
Structural Macromodeling of Analog Circuits Through Model Decoupling and Transformation
Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations
The complexity of fault detection in MOS VLSI circuits
Calculation of contact currents in device simulation
Sparsity-Aware Intelligent Spatiotemporal Data Sensing for Energy Harvesting IoT System
Reproduction and Detection of Board-Level Functional Failure
AutoMap: Automatic Mapping of Neural Networks to Deep Learning Accelerators for Edge Devices
False coupling exploration in timing analysis
Effective enforcement of path-delay constraints inperformance-driven placement
Automatic Op-Amp Generation From Specification to Layout
Superscalar Time-Triggered Versatile-Tensor Accelerator
EOF: Efficient Built-In Redundancy Analysis Methodology With Optimal Repair Rate
Interpretability-Guided Defense Against Backdoor Attacks to Deep Neural Networks
A Fast SIE Solver With Cut Set Analysis and Terminals as Supernodes for Interconnects
Compact Lateral Thermal Resistance Model of TSVs for Fast Finite-Difference Based Thermal Analysis of 3-D Stacked ICs
Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring
Hierarchical test generation under architectural level functional constraints
Arch2End: Two-Stage Unified System-Level Modeling for Heterogeneous Intelligent Devices
Efficient Direct Boundary Element Method for Resistance Extraction of Substrate With Arbitrary Doping Profile
FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-Based In-Memory Computing
WinoNN: Optimizing FPGA-Based Convolutional Neural Network Accelerators Using Sparse Winograd Algorithm
Mobileware: Distributed Architecture With Channel Stationary Dataflow for MobileNet Acceleration
A multiobjective genetic approach for system-level exploration in parameterized systems-on-a-chip
Pattern-Aware Encoding for MLC PCM Storage Density, Energy Efficiency, and Performance Enhancement
Functional Criticality Analysis of Structural Faults in AI Accelerators
Time-efficient VLSI artwork analysis algorithms in GOALIE2
Hierarchical Cross-Entropy Optimization for Fast On-Chip Decap Budgeting
Detection of Hardware Trojans in Third-Party Intellectual Property Using Untrusted Modules
Hardware Constructions for Error Detection in WG-29 Stream Cipher Benchmarked on FPGA
Multicycle generalization. A new way to improve the convergence of waveform relaxation for circuit simulation
Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation
Efficient timing analysis for CMOS circuits considering data dependent delays
AntiDoteX: Attention-Based Dynamic Optimization for Neural Network Runtime Efficiency
Self-Compensating Design for Reduction of Timing and Leakage Sensitivity to Systematic Pattern-Dependent Variation
Improving the Diagnosability of Scan Chain Faults Under Transparent-Scan by Observation Points
Using Control Synthesis to Generate Corner Cases: A Case Study on Autonomous Driving
STOIC: state assignment based on output/input functions
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
Low-Power-Design Space Exploration Considering Process Variation Using Robust Optimization
Cycle-Based Decomposition of Markov Chains With Applications to Low-Power Synthesis and Sequence Compaction for Finite State Machines
Resource budgeting for Multiprocess High-level synthesis
Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs
A Reconfigurable Framework for Performance Enhancement With Dynamic FPGA Configuration Prefetching
Temperature-Aware Integrated DVFS and Power Gating for Executing Tasks With Runtime Distribution
An Extrapolated Yield Approximation Technique for Use in Yield Maximization
A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations
ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs
A Capacity Augmentation Bound for Real-Time Constrained-Deadline Parallel Tasks Under GEDF
Formal definitions of edge-based geometric design rules
A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion
Built-in sequential fault self-testing of array multipliers
Characterization of In-Cone Logic Locking Resiliency Against the SAT Attack
Modeling and Analysis of the LatestTime Message Synchronization Policy in ROS
Suspension-Aware Earliest-Deadline-First Scheduling Analysis
A STRIDE towards practical 3-D device simulation-numerical and visualization considerations
Constraint-based watermarking techniques for design IP protection
Library-Based Cell-Size Selection Using Extended Logical Effort
Integrated circuit design optimization using a sequential strategy
Fundamental CAD algorithms
Dynamic On-Chip Thermal Sensor Calibration Using Performance Counters
FlexFloat: A Software Library for Transprecision Computing
High-level synthesis of low-power control-flow intensive circuits
Runtime Malware Detection Using Embedded Trace Buffers
Minato: A Read-Disturb-Aware Dynamic Buffer Management Scheme for NAND Flash Memory
Tackling Resource Variations Through Adaptive Multicore Execution Frameworks
A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]
High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviors
A delay-based model for circuit parallelism
On the complexity of computing tests for CMOS gates
Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style
ERSA: Error Resilient System Architecture for Probabilistic Applications
ILLIADS: a fast timing and reliability simulator for digital MOS circuits
A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories
Algorithm Selection Framework for Legalization Using Deep Convolutional Neural Networks and Transfer Learning
maj-n Logic Synthesis for Emerging Technology
RBI: Simultaneous Placement and Routing Optimization Technique
Random pattern testability of memory address logic
State-Sensitive X-Filling Scheme for Scan Capture Power Reduction
DCS: Diagonal Coding Scheme for Enhancing the Endurance of SSD-Based RAID Arrays
An efficient approach to multilayer layer assignment with anapplication to via minimization
Functional Broadside Tests for Multistep Defect Diagnosis
Robust Secure Shield Architecture for Detection and Protection Against Invasive Attacks
Fast Pareto Front Exploration for Design of Reconfigurable Energy Storage
Delay and crosstalk simulation of high-speed VLSI interconnects with nonlinear terminations
A Cross-Layer Optimization Framework for Integrated Optical Switches in Data Centers
Techniques for Small-Signal Analysis of Semiconductor Devices
An interchange format for process and device simulation
MAP-SIM: A DNN-Specific Mapping Optimization Framework for Shared-Memory CPU-Systolic Array Architectures
Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks
An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata
Vulnerability-Aware Energy Optimization for Reconfigurable Caches in Multitasking Systems
Klotski v2: Improved DNN Model Orchestration Framework for Dataflow Architecture Accelerators
A complexity analysis of sequential ATPG
Analysis of interconnect networks using complex frequency hopping (CFH)
Circuit simulation by hierarchical waveform relaxation
A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model
Semisupervised Hotspot Detection With Self-Paced Multitask Learning
Optimal design of clock trees for multigigahertz applications
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags
Design and Multicorner Optimization of the Energy-Delay Product of CMOS Flip-Flops Under the Negative Bias Temperature Instability Effect
Grid quality and its influence on accuracy and convergence in device simulation
Combinatorial-Coding-Based High-Performance Microfluidic Control Multiplexer: Design, Synthesis, and Adaptation
Module implementation selection and its application to transistor placement
Test pattern generation and clock disabling for simultaneous test time and power reduction
Adaptive Paired Page Prebackup Scheme for MLC NAND Flash Memory
TDPP: 2-D Permutation-Based Protection of Memristive Deep Neural Networks
Intrinsic GaAs MESFET equivalent circuit models generated from two-dimensional simulations
Application of BEM to high-voltage junction termination
Delay-Bounded Intravehicle Network Routing Algorithm for Minimization of Wiring Weight and Wireless Transmit Power
Stochastic Analysis of Switched-Capacitor Circuits for Sampled Data Converters
UltraTrail: A Configurable Ultralow-Power TC-ResNet AI Accelerator for Efficient Keyword Spotting
A new nonlinear relaxation scheme for solving semiconductor device equations
Selection of Functional Test Sequences With Overlaps
Layout-aware scan chain synthesis for improved path delay fault coverage
Macromodeling of the Memristor in SPICE
A Feedback-Based Approach to DVFS in Data-Flow Applications
Adaptive ILT via Multi-Level Lithography Simulation
Error control schemes for on-chip communication links: the energy-reliability tradeoff
Nonscan design-for-testability techniques using RT-level design information
Reverse-order-restoration-based static test compaction for synchronous sequential circuits
Fast and Coherent Simulation with Zero Delay Elements
A new one-and-half layer channel routing algorithm based on assigning resources for CMOS gate array
A linear programming-based algorithm for floorplanning in VLSI design
A fast nonenumerative automatic test pattern generator for pathdelay faults
Efficient and Accuracy-Ensured Waveform Compression for Transient Circuit Simulation
AdaOPC 2.0: Enhanced Adaptive Mask Optimization Framework for via Layers
Constrained via minimization
Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability
Monte Carlo simulation of ion implantation into two- and three-dimensional structures
Robust Clock Tree Routing in the Presence of Process Variations
An improved Spice2 Zener diode model for soft-region simulation capability
Estimation of average switching activity in combinational logic circuits using symbolic simulation
Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction
Analog checkers with absolute and relative tolerances
A general-purpose two-dimensional process simulator-OPUS for arbitrary structures
Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs
Multiple signature analysis method using fault simulation
An Approximation Problem for the Multi-Via Assignment Problem
TSLA: A Task-Specific Learning Adaptation for Semantic Segmentation on Autonomous Vehicles Platform
Enabling Failure-Resilient Intermittent Systems Without Runtime Checkpointing
Multicore Mixed-Criticality Systems: Partitioned Scheduling and Utilization Bound
Adaptive Task-Based Intermittent Computing System With Parallel State Backup
Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs
Process-Resilient Fault-Tolerant Delay-Locked Loop Using TMR With Dynamic Timing Correction
A Low Latency and Compact GCD Design Using an Intelligent Seed-Selection Scheme of LL-PRNG
Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications
A Dataflow-Aware Network-on-Interposer for CNN Inferencing in the Presence of Defective Chiplets
Compact Modeling to Device- and Circuit-Level Evaluation of Flexible TMD Field-Effect Transistors
Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities
Architectural energy optimization by bus splitting
OSCAR: An Optimization Methodology Exploiting Spatial Correlation in Multicore Design Spaces
Models and algorithms for three-dimensional topography simulation with SAMPLE-3D
An Efficient Numerical Algorithm for Simulation of MOS Capacitance
MeXT-SE: A Design Tool to Transparently Generate Secure MPSoC
BDD-based synthesis of extended burst-mode controllers
Movie-an interactive environment for silicon compilation tools
A module generator for optimized CMOS buffers
Partitioning using second-order information and stochastic-gainfunctions
Multistage Charge Pump Design Methodology for Zero-Crossing-Based Amplifiers
Boosting User Experience via Foreground-Aware Cache Management in UFS Mobile Devices
Clock suppression techniques for synchronous circuits
Routing Techniques for Gate Array
Performance optimization using template mapping for datapath-intensive high-level synthesis
GM Plan: a gate matrix layout algorithm based on artificial intelligence planning techniques
A new grid-generation method for 2-D simulation of devices with nonplanar semiconductor surface
NASA: NVM-Assisted Secure Deletion for Flash Memory
NP-Separate: A New VLSI Design Methodology for Area, Power, and Performance Optimization
Scaling considerations of the constitutive equations in a 2-D finite element heterojunction simulator PRISM
Effect of improved lower bounds in dynamic BDD reordering
CaPUF: Cascaded PUF Structure for Machine Learning Resiliency
Reliability Analysis of Logic Circuits
Improving the Resolution of Single-Delay-Fault Diagnosis
Fast-OverlaPIM: A Fast Overlap-Driven Mapping Framework for Processing In-Memory Neural Network Acceleration
Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs
Constraint-Driven Test Scheduling for NoC-Based Systems
Toward Write Optimization for Skyrmion Racetrack Memory by Skyrmion Repermutation
Fault simulation of unconventional faults in CMOS circuits
SCV-GNN: Sparse Compressed Vector-Based Graph Neural Network Aggregation
An On-the-Fly Parameter Dimension Reduction Approach to Fast Second-Order Statistical Static Timing Analysis
Generating Test Patterns for Chiplet Interconnects With Optimized Effectiveness and Efficiency
Built-in self test for C-testable ILA's
The complexity of generalized retiming problems
Design Space Exploration for Phase Transition Material-Augmented MRAMs With Separate Read-Write Paths
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms
An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness
Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs
n-pass n-detection fault simulation and its applications
CodePM: Parity-Based Crash Consistency for Log-Free Persistent Transactional Memory
Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms
PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels
Capturing Post-Silicon Variations Using a Representative Critical Path
A pin permutation algorithm for improving over-the-cell channel routing
Wrapping Paths of Undetected Transition Faults With Two-Cycle Gate-Exhaustive Faults
Logic synthesis for engineering change
Fourier method modeling of semiconductor devices
Symbolic Compilation of PSL
Statistical Circuit Simulation Modeling of CMOS VLSI
Efficient Localization Methods for Passivity Enforcement of Linear Dynamical Models
Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling
A New Fail Address Memory Architecture for Cost-Effective ATE
MRIMA: An MRAM-Based In-Memory Accelerator
Device and circuit simulation of anomalous DX trap effects in DCFL and SCFL HEMT inverters
SMT Solver With Hardware Acceleration
Bridging the Gap From Vague Design Requirements to Feasible Structure: Deep Learning Model for Parameterized MEMS Sensor Design
Robust Simulation of Opto-Electronic Systems by Alternating Complex Envelope Representations
A physical parametric transistor model for CMOS circuit simulation
A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories
Boosting Latent Defect Coverage in Automotive Mixed-Signal ICs Using SVM Classifiers
On Acceleration of SAT-Based ATPG for Industrial Designs
A Highly Reliable Dual-Mode RRAM PUF With Key Concealment Scheme
Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment
Fault-Tolerant Networks-on-Chip Routing With Coarse and Fine-Grained Look-Ahead
HTs-GCN: Identifying Hardware Trojan Nodes in Integrated Circuits Using a Graph Convolutional Network
Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-Based DNN Accelerators
FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks
Hierarchical test generation and design for testability methods for ASPPs and ASIPs
Parallel Fuzzing of IoT Messaging Protocols Through Collaborative Packet Generation
Optimal State Assignment for Finite State Machines
Empirical Method Based on Neural Networks for Analog Power Modeling
Adaptive 3D-IC TSV Fault Tolerance Structure Generation
Evaluation of Binary Decision Diagrams Complexity Using Relative Arithmetic Width
Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors
Thermal-Aware Resource Management for Embedded Real-Time Systems
Multipumping Flexible DSP Blocks for Resource Reduction on Xilinx FPGAs
An Efficient Adaptive Importance Sampling Method for SRAM and Analog Yield Analysis
Locking Protocols for Parallel Real-Time Tasks With Semaphores Under Federated Scheduling
Thermodynamic Optimization of Block Placement
Trade-Offs for Threshold Implementations Illustrated on AES
Detailed Placement Algorithm for VLSI Design With Double-Row Height Standard Cells
ECO-System: Embracing the Change in Placement
Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement
Cut Redistribution With Directed-Self-Assembly Templates for Advanced 1-D Gridded Layouts
Challenges and Solutions in the Development of Automotive Systems
Thermal Sensor Placement for Multicore Systems Based on Low-Complex Compressive Sensing Theory
An enhanced power meter for SPICE2 circuit simulation
Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets
A Novel Wire-Density-Driven Full-Chip Routing System for CMP Variation Control
Improving Dependability of Distributed Real-Time Applications via Safety and Security Co-Design
Performance-Based Optical Proximity Correction Methodology
On the fault coverage of gate delay fault detecting tests
Macromodeling and Optimization of Digital MOS VLSI Circuits
Performance trade-offs in a parallel test generation/fault simulation environment
AC analysis of amorphous silicon devices
Easily Overlooked Vulnerability in Implementation: Practical Fault Attack on ECDSA Round Counter
Three-Dimensional Monte Carlo Simulations--Part I: Implanted Profiles for Dopants in Submicron Device
Stitch-Aware Routing for Multiple E-Beam Lithography
Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges
Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test
LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip
Common-Centroid Capacitor Layout Generation Considering Device Matching and Parasitic Minimization
Layer assignment for multichip modules
The STREAM Mechanism for CPS Security The Case of the Smart Grid
Implicit enumeration of strongly connected components and anapplication to formal verification
Quantum Circuit Placement
Device model approximation using 2 N trees
Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques
Modeling of the charge balance condition on floating gates and simulation of EEPROMs
A universal MOSFET mobility degradation model for circuit simulation
Classification and identification of nonrobust untestable path delay faults
Event suppression: improving the efficiency of timing simulation for synchronous digital circuits
Automated Generation of Benchmarks for Falsification of STL Specifications
Optimal FPGA mapping and retiming with efficient initial state computation
Timing analysis including clock skew
Computer-aided analysis of on-chip interconnects near semiconductorsubstrate for high-speed VLSI
SRAM Periphery Testing Using the Cell-Aware Test Methodology
SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput
A High-Performance and Scalable NVMe Controller Featuring Hardware Acceleration
A complement-based fast algorithm to generate universal test sets for multi-output functions
MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip
Limited Busy Periods in Response Time Analysis for Tasks Under Global EDF Scheduling
Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs
Critical area computation via Voronoi diagrams
SPFD: A new method to express functional flexibility
Fully Programmatic Automated Design Procedure of Comparators for Analog-to-Digital Converters
On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets
Global Routing With Timing Constraints
Provably good performance-driven global routing
On properties of algebraic transformations and the synthesis of multifault-irredundant circuits
Gauss-elimination-based generation of multiple seed-polynomial pairs for LFSR
A Self-Consistent Monte Carlo Particle Model to Analyze Semiconductor Microcomponents of any Geometry
Neuro-Ising: Accelerating Large-Scale Traveling Salesman Problems via Graph Neural Network Guided Localized Ising Solvers
A method for generating structurally aligned grids for semiconductor device simulation
A Fast and Near-Optimal Clustering Algorithm for Low-Power Clock Tree Synthesis
Variation Enhanced Attacks Against RRAM-Based Neuromorphic Computing System
GEAR: Graph-Evolving Aware Data Arranger to Enhance the Performance of Traversing Evolving Graphs on SCM
An adaptation of the interior point method for solving the global routing problem
Design Methods for Symmetric Function Generators Based on Threshold Elements
Two-dimensional modeling of ion implantation induced point defects
Supply and power optimization in leakage-dominant technologies
Circuit optimization using carry-save-adder cells
SCIMITAR: Stochastic Computing In-Memory In-Situ Tracking ARchitecture for Event-Based Cameras
On Optimizing Inter- and Intra-Chiplet Interconnection Topologies for Robust Multi-Chiplet Systems
SWiTEST: a switch level test generation system for CMOS combinational circuits
DiSC: A New Diagnosis Method for Multiple Scan Chain Failures
Path-Based Buffer Insertion
Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to on-chip computation times
QMDDs: Efficient Quantum Function Representation and Manipulation
Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs
Corrections to "A Bidirectional Deep Learning Approach for Designing MEMS Sensors"
PushPull: Short-Path Padding for Timing Error Resilient Circuits
A Robustness-Based Confidence Measure for Hybrid System Falsification
Parallel algorithms for VLSI circuit extraction
HALO: an efficient global placement strategy for standard cells
Synthesis of software programs for embedded control applications