yusuke1997/dblp-id-title huggingface dataset:
Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals
Fast Hybrid Karatsuba Multiplier for Type II Pentanomials
A Combo EMI Suppression Scheme for Multimode PSR Flyback Converter
Adaptive Power Control Technique on Power-Gated Circuitries
An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM
A Programmable SoC-Based Accelerator for Privacy-Enhancing Technologies and Functional Encryption
Leakage-Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology
High Dynamic Performance Current-Steering DAC Design With Nested-Segment Structure
Timing Analysis of Tasks on Runtime Reconfigurable Processors
Reduced Complexity Interpolation Architecture for Soft-Decision Reed-Solomon Decoding
VLSI-Efficient Scheme and FPGA Realization for Robotic Mapping in a Dynamic Environment
Improving the efficiency of Monte Carlo power estimation [VLSI]
Memory optimization of MAP turbo decoder algorithms
Subthreshold Operation of CAAC-IGZO FPGA by Overdriving of Programmable Routing Switch and Programmable Power Switch
A Highly-Integrated 3-8 GHz Ultra-Wideband RF Transmitter With Digital-Assisted Carrier Leakage Calibration and Automatic Transmit Power Control
Statistical estimation of average power dissipation using nonparametric techniques
Static-Linearity Enhancement Techniques for Digital-to-Analog Converters Exploiting Optimal Arrangements of Unit Elements
Automatic linearity and frequency response tests with built-in pattern generator and analyzer
Reconfigurable ECO Cells for Timing Closure and IR Drop Minimization
Dynamic Thermal Estimation Methodology for High-Performance 3-D MPSoC
Replicating Tag Entries for Reliability Enhancement in Cache Tag Arrays
Estimation of fault-free leakage current using wafer-level spatial information
A 10 b 50 MS/s Opamp-Sharing Pipeline A/D With Current-Reuse OTAs
A Source-Synchronous Double-Data-Rate Parallel Optical Transceiver IC
Embedded Memory Interface Logic and Interconnect Testing
Systolic Gaussian Normal Basis Multiplier Architectures Suitable for High-Performance Applications
A Digital LDO Regulator With a Self-Clocking Burst Logic for Ultralow Power Applications
NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators
Area Efficient 0.009-mm 2 28.1-ppm/°C 11.3-MHz ALL-MOS Relaxation Oscillator
A transaction-based unified architecture for simulation and emulation
Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest
Front-End Architecture Design for Low-Complexity 3-D Ultrasound Imaging Based on Synthetic Aperture Sequential Beamforming
Bridge Floating-Point Fused Multiply-Add Design
Wide-Locking Range Divide-by-3 Injection-Locked Frequency Divider Using Sixth-Order RLC Resonator
The Costs of Confidentiality in Virtualized FPGAs
Low-power design techniques for high-performance CMOS adders
The CSI multimedia architecture
Chip Aging and Transition Faults With High Switching Activities Under Scan-Based Tests
Landauer Clocking for Magnetic Cellular Automata (MCA) Arrays
Analysis and Design of Current Mode Class-D Power Amplifiers With Finite Feeding Inductors
Randomized Partially-Minimal Routing: Near-Optimal Oblivious Routing for 3-D Mesh Networks
An Area/Power-Efficient Noise-Shaping SAR ADC for Implantable Biosensor Applications Featuring a Unique Auxiliary Feedback Loop
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers
SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse
Behavioral Model for High-Speed SAR ADCs With On-Chip References
Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning
A Multiphase DLL With a Novel Fast-Locking Fine-Code Time-to-Digital Converter
Probing Assessment Framework and Evaluation of Antiprobing Solutions
CapCAM: A Multilevel Capacitive Content Addressable Memory for High-Accuracy and High-Scalability Search and Compute Applications
Exploring Warp Criticality in Near-Threshold GPGPU Applications Using a Dynamic Choke Point Analysis
Improving FPGA Performance for Carry-Save Arithmetic
Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies
Inductance model and analysis methodology for high-speed on-chip interconnect
Architectural and Circuit Design Techniques for Power Management of Ultra-Low-Power MCU Systems
Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations
Instruction buffering to reduce power in processors for signal processing
A VLSI Architecture and the FPGA Prototype for MPEG-2 Audio/Video Decoding
A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates
A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling
Fast and Flexible Hardware Support for ECC Over Multiple Standard Prime Fields
Systematic Simulation-Based Predictive Synthesis of Integrated Optical Interconnect
Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units
End-to-End Analysis of Integration for Thermocouple-Based Sensors Into 3-D ICs
Analysis and Implementation of a Minimum-Supply Body-Biased CMOS Differential Amplifier Cell
A Wide-Range Multiport LC-Ladder Oscillator and Its Applications to a 1.2-10.1 GHz PLL
Identifying Single-Event Transient Location Based on Compressed Sensing
Enhanced Postbond Test Architecture for Bridge Defects Between the TSVs
Test Pattern Generation of Relaxed n-Detect Test Sets
An Interference-Robust Reconfigurable Receiver With Automatic Frequency-Calibrated LNA in 65-nm CMOS
Functional Constraint Extraction From Register Transfer Level for ATPG
Analysis of signal probability in logic circuits using stochastic models
Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration
Application-Driven End-to-End Traffic Predictions for Low Power NoC Design
SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage
A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems
A 0.8-V, 2.55-GHz, 2.62-mW Charge-Pump PLL With High Spectrum Purity
Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM
Effect of the prefabricated routing track distribution on FPGA area-efficiency
Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits
Test Methodology for Defect-Based Bridge Faults
A reconfigurable multifunction computing cache architecture
An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction
Minimizing the required memory bandwidth in VLSI system realizations
Preponing Fault Detections for Test Compaction Under Transparent Scan
Tunable Multiprocess Mapping on Coarse-Grain Reconfigurable Architectures With Dynamic Frequency Control
Improved Analytical Delay Models for RC-Coupled Interconnects
Passive Noise Shaping in SAR ADC With Improved Efficiency
A Trace-Based Framework for Verifiable GALS Composition of IPs
Self-Timed Read and Write Operations in STT-MRAM
Hardware Variability-Aware Duty Cycling for Embedded Sensors
A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers
An Efficient Fault-Tolerance Design for Integer Parallel Matrix-Vector Multiplications
Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications
A built-in self-repair design for RAMs with 2-D redundancy
An Area-Efficient BIRA With 1-D Spare Segments
High Restore Yield NVSRAM Structures With Dual Complementary RRAM Devices for High-Speed Applications
Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs
IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores
Low-Cost On-Chip Clock Jitter Measurement Scheme
12-nm Stable Pre-Amplifier Physical Unclonable Function With Self-Destruct Capability
Test Compaction by Backward and Forward Extension of Multicycle Tests
Enhancing the Efficiency of Energy-Constrained DVFS Designs
A Dual-Output Step-Down Switched-Capacitor Voltage Regulator With a Flying Capacitor Crossing Technique for Enhanced Power Efficiency
Quantitative analysis and optimization techniques for on-chip cache leakage power
3-D IC Interconnect Capacitance Extraction Using Dual Discrete Geometric Methods With Prism Elements
An Analytical Latency Model for Networks-on-Chip
Incorporating Hot-Carrier Injection Effects Into Timing Analysis for Large Circuits
Enhancing ConvNets With ConvFIFO: A Crossbar PIM Architecture Based on Kernel-Stationary First-In-First-Out Dataflow
ABRM: Adaptive Beta -Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks
An SAR ADC Switching Scheme With MSB Prediction for a Wide Input Range and Reduced Reference Voltage
Case Study of Reliability-Aware and Low-Power Design
A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories
From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAs
A Secure Integrity Checking System for Nanoelectronic Resistive RAM
TINA: TMVP-Initiated Novel Accelerator for Lightweight Ring-LWE-Based PQC
A Secure-by-Design Hardware/Operating System as a Substrate for Trustworthy Computing
DBP-CIM: Energy-Efficient 8T SRAM-Based Diagonal-Block Parallel Computing-in-Memory With Compact Data Layout for Arithmetic Operations
Cross-Layer Optimization for Multilevel Cell STT-RAM Caches
Variation-Aware Voltage Level Selection
NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact
Parallel Stimulus Generation Based on Model Checking for Coherence Protocol Verification
Low-Cost Stochastic Number Generators for Stochastic Computing
A tree-matching chip
Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration
Low Power Unsupervised Anomaly Detection by Nonparametric Modeling of Sensor Statistics
Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations
An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation
Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers
A 2-GHz Bandwidth, Integrated Transimpedance Amplifier for Single-Photon Timing Applications
Toward Secure Microfluidic Fully Programmable Valve Array Biochips
Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method
Digit-Level Semi-Systolic and Systolic Structures for the Shifted Polynomial Basis Multiplication Over Binary Extension Fields
Strategy for power-efficient design of parallel systems
Quadrature direct digital frequency synthesizers using interpolation-based angle rotation
14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability
The Cat and Mouse in Split Manufacturing
Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance
Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management
A 110-nm CMOS 0.7-V Input Transient-Enhanced Digital Low-Dropout Regulator With 99.98% Current Efficiency at 80-mA Load
Multiloop Control for Fast Transient DC-DC Converter
System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs
Within-Die Delay Variation Measurement and Power Transient Analysis Using REBEL
A New Fast and Area-Efficient Adder-Based Sign Detector for RNS {2 n -1, 2 n , 2 n +1}
A 700-μm², Ring-Oscillator-Based Thermal Sensor in 16-nm FinFET
On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals
Algorithm and Architecture of an Efficient MIMO Detector With Cross-Level Parallel Tree-Search
Built-In Sensor for Signal Integrity Faults in Digital Interconnect Signals
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures
Sophon: A Time-Repeatable and Low-Latency Architecture for Embedded Real-Time Systems Based on RISC-V
Supply-Insensitive Digitally Controlled Delay Lines for 3-D IC Clock Synchronization Architectures
REMAP+: An Efficient Banking Architecture for Multiple Writes of Algorithmic Memory
Effective Uses of FPGAs for Brute-Force Attack on RC4 Ciphers
Scalable Digital CMOS Comparator Using a Parallel Prefix Tree
Deterministic Random Walk: A New Preconditioner for Power Grid Analysis
The COBRA-ABS high-level synthesis system for multi-FPGA custom computing machines
TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems
Graphical I DDQ Signatures Reduce Defect Level and Yield Loss
SOC test planning using virtual test access architectures
A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications
Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT
Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach
Design and implementation of a high-speed matrix multiplier based on word-width decomposition
Microarchitecture-level leakage reduction with data retention
Editorial: TVLSI Keynote Papers Enriching Our Transactions With Invited Contributions
Novel Architecture for Efficient FPGA Implementation of Elliptic Curve Cryptographic Processor Over ${\rm GF}(2^{163})$
A 3-D Cache With Ultra-Wide Data Bus for 3-D Processor-Memory Integration
Compiler-guided leakage optimization for banked scratch-pad memories
Efficient and Accurate ECO Leakage Optimization Framework With GNN and Bidirectional LSTM
Yield Enhancement of Face-to-Face Cu-Cu Bonding With Dual-Mode Transceivers in 3DICs
Hardware Implementation of Iterative Method With Adaptive Thresholding for Random Sampling Recovery of Sparse Signals
VLSI array algorithms and architectures for RSA modular multiplication
Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems
A Best-First Soft/Hard Decision Tree Searching MIMO Decoder for a 4 × 4 64-QAM System
Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit
Guest Editorial: Selected Papers From IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2024
A Chiplet Platform for Intelligent Radar/Sonar Leveraging Domain-Specific Reusable Active Interposer
Testability Evaluation for Local Design Modifications
A 25-GHz PLL Achieving 8-ns Phase-Shifting Time With Double-Path Modulation Scheme
Unifying mesh- and tree-based programmable interconnect
New Non-Volatile Memory Structures for FPGA Architectures
Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes
A BIST Circuit for DLL Fault Detection
An 8 bit 0.3-0.8 V 0.2-40 MS/s 2-bit/Step SAR ADC With Successively Activated Threshold Configuring Comparators in 40 nm CMOS
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST
Modeling and Layout Optimization for Tapered TSVs
Globally Constrained Locally Optimized 3-D Power Delivery Networks
IDWA: A Importance-Driven Weight Allocation Algorithm for Low Write-Verify Ratio RRAM-Based In-Memory Computing
Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC
A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler
On Using nMOS-pMOS-Type Cells in a Threshold-Voltage Compensated CMOS RF-DC Rectifier
Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
McPAT-Monolithic: An Area/Power/Timing Architecture Modeling Framework for 3-D Hybrid Monolithic Multicore Systems
High-level macro-modeling and estimation techniques for switching activity and power consumption
Variable precision arithmetic circuits for FPGA-based multimedia processors
Simplex FastICA: An Accelerated and Low Complex Architecture Design Methodology for $n$ D FastICA
Editorial Appointments for the 2013-2014 Term
A Monte Carlo approach for power estimation
Evaluation and Tradeoffs for Out-of-Order Execution on Reconfigurable Heterogeneous MPSoC
High-Endurance Hybrid Cache Design in CMP Architecture With Cache Partitioning and Access-Aware Policies
A network flow approach to memory bandwidth utilization in embedded DSP core processors
An Efficient SRAM Yield Analysis and Optimization Method With Adaptive Online Surrogate Modeling
Techniques for accurate performance evaluation in architecture exploration
Hybrid Stochastic Number and Its Neural Network Computation
Approximate Softmax Functions for Energy-Efficient Deep Neural Networks
Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications
Efficient Hardware Accelerator Based on Medium Granularity Dataflow for SpTRSV
Pseudo-Ramp Current Balance (PRCB) Technique With Offset Cancellation Control (OCC) in Dual-Phase DC-DC Buck Converter
A Novel Quantum-Dot Cellular Automata X-bit × 32-bit SRAM
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia
Power estimation for large sequential circuits
A High-SNR Projection-Based Atom Selection OMP Processor for Compressive Sensing
Fault-Tolerant Embedded-Memory Strategy for Baseband Signal Processing Systems
Direct Compare of Information Coded With Error-Correcting Codes
A μ-GA Oriented ANN-Driven: Parameter Extraction of 5G CMOS Power Amplifier
An Error Location and Correction Method for Memory Based on Data Similarity Analysis
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
A Calibration Technique for Bang-Bang ADPLLs Using Jitter Distribution Monitoring
A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase Interpolators
Modeling of Joule Heating Induced Effects in Multiwall Carbon Nanotube Interconnects
A Practical Logic Obfuscation Technique for Hardware Security
Accurate area and delay estimation from RTL descriptions
A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications
System-Level Leakage Variability Mitigation for MPSoC Platforms Using Body-Bias Islands
Segmented bus design for low-power systems
Cross-Coupled Current Conveyor Based CMOS Transimpedance Amplifier for Broadband Data Transmission
A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design
Hardware Trojan Detection Using Changepoint-Based Anomaly Detection Techniques
Partitioning algorithm to enhance pseudoexhaustive testing of digital VLSI circuits
Charge Pump Architectures Based on Dynamic Gate Control of the Pass-Transistors
A Time-Domain Frequency Analyzer Based on Goertzel Algorithm
Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip
Logic IP for Low-Cost IC Design in Advanced CMOS Nodes
Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison
Variation-Aware Variable Latency Design
Optimizing the Implementation of SEC-DAEC Codes in FPGAs
FPGA Implementation of Orthogonal Matching Pursuit for Compressive Sensing Reconstruction
Jitter Analysis of Polyphase Filter-Based Multiphase Clock in Frequency Multiplier
Design of an ASIP architecture for low-level visual elaborations
Design of minimal-level PLA self-testing checkers for m-out-of-n codes
Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)
Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows
Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs
Corrections to "GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis"
Data Block Partitioning Methods to Mitigate Stuck-At Faults in Limited Endurance Memories
A New Improved V-Square-Controlled Buck Converter With Rail-to-Rail OTA-Based Current-Sensing Circuits
Stochastic Computing Max & Min Architectures Using Markov Chains: Design, Analysis, and Implementation
ASP-SIFT: Using Analog Signal Processing Architecture to Accelerate Keypoint Detection of SIFT Algorithm
Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits
Architectural Support for Run-Time Validation of Program Data Properties
Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis
Symbolic Polynomial Maximization Over Convex Sets and Its Application to Memory Requirement Estimation
Dynamic Block-Wise Local Learning Algorithm for Efficient Neural Network Training
VLSI Characterization of the Cryptographic Hash Function BLAKE
A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs
Energy-Efficient Trace Reuse Cache for Embedded Processors
Spreading Operation Frequency Ranges of Memristor Emulators via a New Sine-Based Method
A Vector Processor for Mean Field Bayesian Channel Estimation
A 28-nm Dual-Mode Explicit Class-F₂₃ VCO With Low-Loss CM Return Path Achieving 70-400-kHz 1/f³ PN Corner Over 4.9-7.3-GHz TR
Activity-Driven Fine-Grained Clock Gating and Run Time Power Gating Integration
Systolic and Non-Systolic Scalable Modular Designs of Finite Field Multipliers for Reed-Solomon Codec
An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC
On the optimal reconfiguration of multipipeline arrays in the presence of faulty processing and switching elements
Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors
Precharge-Free, Low-Power Content-Addressable Memory
Enhancing Strong PUF Security With Nonmonotonic Response Quantization
On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures
Area-Efficient Parallel Multiplication Units for CNN Accelerators With Output Channel Parallelization
A Low-Power In-Memory Multiplication and Accumulation Array With Modified Radix-4 Input and Canonical Signed Digit Weights
Circuit Performance Shifts Due to Layout-Dependent Stress in Planar and 3D-ICs
Secure STT-MRAM Bit-Cell Design Resilient to Differential Power Analysis Attacks
A Variation-Aware Preferential Design Approach for Memory-Based Reconfigurable Computing
A reconfigurable VLSI coprocessing system for the block matching algorithm
Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect
Error Detection and Correction in SRAM Emulated TCAMs
High-Throughput Layered LDPC Decoding Architecture
Fourier Series Approximation for Max Operation in Non-Gaussian and Quadratic Statistical Static Timing Analysis
A Reconfigurable Cache for Efficient Use of Tag RAM as Scratch-Pad Memory
A 0.9-nW, 101-Hz, and 46.3-µV rms IRN Low-Pass Filter for ECG Acquisition Using FVF Biquads
ORION 2.0: A Power-Area Simulator for Interconnection Networks
Quasi-Static Assignment of Voltages and Optional Cycles in Imprecise-Computation Systems With Energy Considerations
Comparative Study of Various Latch-Type Sense Amplifiers
Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon Validation
System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection
An Efficient Hierarchical Banking Structure for Algorithmic Multiported Memory on FPGA
Exploiting Chiplet Integration Technology for Fast High-Capacity DRAM Modules
Leveraging Unused Resources for Energy Optimization of FPGA Interconnect
A Low-Power Class-AB Gm-Based Amplifier With Application to an 11-bit Pipelined ADC
Reconfigurable Signal Processing and DSP Hardware Generator for 5G and Beyond Transmitters
Computing Seeds for LFSR-Based Test Generation From Nontest Cubes
Fast and Effective Placement Refinement for Routability
AC-Plus Scan Methodology for Small Delay Testing and Characterization
An Adaptive Zero-Current Detector for Single-Inductor Multiple-Output DC-DC Converter With Full-Wave Current Sensor
A Multimode Configurable Physically Unclonable Function With Bit-Instability-Screening and Power-Gating Strategies