yusuke1997/dblp-id-title huggingface dataset:
A CMOS 1.2-V Hybrid Current- and Voltage-Mode Three-Way Digital Doherty PA With Built-In Phase Nonlinearity Compensation
A Hybrid Bidirectional Converter With Always-Half-Inductor Current Using Adaptive Target Current Tracking for USB-to-2-Cell Applications
A Low-Noise Area-Efficient Chopped VCO-Based CTDSM for Sensor Applications in 40-nm CMOS
Op-amps and startup circuits for CMOS bandgap references with near 1-V supply
A Blocker-Tolerant Non-Uniform Sub-Sampling Receiver With a Non-Uniform Discrete-Time FIR Filter
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme
P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation
An analytical CMOS inverter delay model including channel-length modulations
A 7.6-mW IR-UWB Receiver Achieving -17-dBm Blocker Resilience With a Linear RF Front-End
A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering
A 1.71-million transistor CMOS CPU chip with a testable cache architecture
A 0.7-5.7 GHz Reconfigurable MIMO Receiver Architecture for Analog Spatial Notch Filtering Using Orthogonal Beamforming
A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/D conversion
A Four-Way Series Doherty Digital Polar Transmitter at mm-Wave Frequencies
A two-chip 1.5-GBd serial link interface
A Benchmark of Cryo-CMOS Embedded SRAM/DRAMs in 40-nm CMOS
A CMOS rectifier-integrator for amplitude detection in hard disk servo loops
A 1.2-V Highly Linear Balanced Noise-Cancelling LNA in 0.13-µm CMOS
A 116 fps/74 mW Heterogeneous 3D-Media Processor for 3-D Display Applications
Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs
Power Optimized ADC-Based Serial Link Receiver
A 10-bit Resistor-Floating-Resistor-String DAC (RFR-DAC) for High Color-Depth LCD Driver ICs
A rate adaption coprocessor for terminal adapters and U-interface modems
MINOTAUR: A Posit-Based 0.42-0.50-TOPS/W Edge Transformer Inference and Training Accelerator
A Ultra-Wideband Amplitude Modulation (AM) Detector Using Schottky Barrier Diodes Fabricated in Foundry CMOS Technology
Active GHz clock network using distributed PLLs
A 0.56-2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2G-4G Multistandard Cellular Transceivers
20-40 Gb/s 0.2-μm GaAs HEMT chip set for optical data receiver
A 9.95-11.3-Gb/s XFP Transceiver in 0.13-$\mu{\hbox {m}}$ CMOS
A high-speed programmable CMOS interface system combining D/A conversion and FIR filtering
AIA: A Customized Multi-Core RISC-V SoC for Discrete Sampling Workloads in 16 nm
A multigigabit DRAM technology with 6F 2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse
X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs
Large-signal analysis of MOS varactors in CMOS -G m LC VCOs
Novel cell-AGC technique for burst-mode CMOS preamplifier with wide dynamic range and high sensitivity for ATM-PON system
A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation
An ultrahigh-speed GaAs MESFET operational amplifier
A Low-Noise Dual-Path Self-Interference Cancellation Architecture for Watt-Level TX Power Handling in Simultaneous Transmit and Receive
A 27 W Wireless Power Transceiver With Compact Single-Stage Regulated Class-E Architecture and Adaptive ZVS Control
An Energy-Efficient Miniaturized Intracranial Pressure Monitoring System
ALBA: a bipolar technology structured array for the design of high-order continuous-time filters
A Pen-Pressure-Sensitive Capacitive Touch System Using Electrically Coupled Resonance Pen
A Low-Noise Chopper Amplifier Designed for Multi-Channel Neural Signal Acquisition
Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering
Analysis and Correction of Noise Injection Due to Parallel-Output-Misalignment (POM) Effects in Ring-Type Time-to-Digital Converters (TDCs)
High-power monolithic AlGaN/GaN HEMT oscillator
A module generator for high-speed CMOS current output digital/analog converters
A Study of SiGe HBT Signal Sources in the 220-330-GHz Range
A 20-mA-receive, 55-mA-transmit, single-chip GSM transceiver in 0.25-μm CMOS
A 20 GS/s 5-Bit SiGe BiCMOS Dual-Nyquist Flash ADC With Sampling Capability up to 35 GS/s Featuring Offset Corrected Exclusive-Or Comparators
Transistor and circuit design for 100-200-GHz ICs
Low-Power Single-Loop and Dual-Loop AGCs for Bionic Ears
Investigation on low-voltage low-power silicon bipolar design topology for high-speed digital circuits
A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C
An 84 GHz Bandwidth and 20 dB Gain Broadband Amplifier in SiGe Bipolar Technology
A 144-Element Beam-Steerable Source Array With 9.1-dBm Radiated Power and 30.8-dBm Lensless EIPR at 675 GHz
A CMOS Image Sensor Based on Unified Pixel Architecture With Time-Division Multiplexing Scheme for Color and Depth Image Acquisition
A 90.2% Peak Efficiency Multi-Input Single-Inductor Multi-Output Energy Harvesting Interface With Double-Conversion Rejection Technique and Buck-Based Dual-Conversion Mode
Design and test of a 2-Gbit/s GaAs 16/8-bit MUX/DEMUX pair
A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology
A Dual-Channel High-Linearity Filtering-by-Aliasing Receiver Front-End Supporting Carrier Aggregation
A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO
CDMA mobile station modem ASIC
A 100 pJ/bit, (32, 8) CMOS Analog Low-Density Parity-Check Decoder Based on Margin Propagation
Precise CMOS current sample/hold circuits using differential clock feedthrough attenuation techniques
A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOS
A Wideband 77-GHz, 17.5-dBm Fully Integrated Power Amplifier in Silicon
A built-in self-test algorithm for row/column pattern sensitive faults in RAMs
Soft-defect detection (SDD) technique for a high-reliability CMOS SRAM
A 44.3-mW 62.4-fps Hyperspectral Image Processor for Spectral Unmixing in MAV Remote Sensing
A 5-V CMOS line controller with 16-b audio converters
A Scalable 1024-Channel Ultra-Low-Power Spike Sorting Chip With Event-Driven Detection and Spatial Clustering
A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops
A 1.0-GHz single-issue 64-bit powerPC integer processor
Integrated Inverse Class-F Silicon Power Amplifiers for High Power Efficiency at Microwave and mm-Wave
Ayaka: A Versatile Transformer Accelerator With Low-Rank Estimation and Heterogeneous Dataflow
Resolution-Related Design Considerations for a 120-GS/s 8-bit 2: 1 Analog Multiplexer in SiGe-BiCMOS Technology
ThunderBird: a complete standard cell layout package
A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration
2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read
A 32-A, 5-V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN nMOS Power Transistors
A constant slew rate Ethernet line driver
A Compact Photocurrent Recording IC With High-Linearity Dual PWM Buffered R-DACs
An Integrated CMOS Passive Self-Interference Mitigation Technique for FDD Radios
A programmable FIR digital filter using CSD coefficients
A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM
A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS
Sub- μ W Battery-Less and Oscillator-Less Wi-Fi Backscattering Transmitter Reusing RF Signal for Harvesting, Communications, and Motion Detection
Capacitive feedback technique for wide-band amplifiers
A 2.5-Gb/s 15-mW clock recovery circuit
An On-Chip Waveform Capturer and Application to Diagnosis of Power Delivery in SoC Integration
A Fully Integrated 0.13 µm CMOS Low-IF DBS Satellite Tuner Using Automatic Signal-Path Gain and Bandwidth Calibration
An 8-b 1.3-MHz successive-approximation A/D converter
A Fully Integrated 4:1 DC-DC Converter With Series Transmission and Parallel Reception Through Electromagnetically Coupled Class-D LC Oscillators
NAND Controller System With Channel Number Detection and Feedback for Power-Efficient High-Speed 3D-SSD
A wide-band tuning system for fully integrated satellite receivers
A Self-Tuning IoT Processor Using Leakage-Ratio Measurement for Energy-Optimal Operation
70-GHz Effective Sampling Time-Base On-Chip Oscilloscope in CMOS
An on-chip 96.5% current efficiency CMOS linear regulator using a flexible control technique of output current
A CMOS 5.37-mW 10-Bit 200-MS/s Dual-Path Pipelined ADC
A Charge Recycling Logic Data Links for Single- and Multiple-Channel I/Os
Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications
A Synchronous Piezoelectric-Electromagnetic Hybrid Energy Harvesting Platform With Coil-Sharing Scheme
A +10-dBm IIP 3 SiGe mixer with IM 3 cancellation technique
Tail Current-Shaping to Improve Phase Noise in LC Voltage-Controlled Oscillators
Introduction to the Special Issue on the 41st European Solid-State Circuits Conference (ESSCIRC)
A low-power microcontroller having a 0.5-μA standby current on-chip regulator with dual-reference scheme
A real-time motion estimation and compensation LSI with wide search range for MPEG2 video encoding
CMOS stress sensors on [100] silicon
A Range Image Sensor Based on 10-μm Lock-In Pixels in 0.18-μm CMOS Imaging Technology
Evolution of high-speed operational amplifier architectures
A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp
A 0-dB IL 2140±30 MHz bandpass filter utilizing Q-enhanced spiral inductors in standard CMOS
High-Efficiency Silicon-Based Envelope-Tracking Power Amplifier Design With Envelope Shaping for Broadband Wireless Applications
High-Q HF microelectromechanical filters
A Dual-Slope Capacitance-to-Digital Converter Integrated in an Implantable Pressure-Sensing System
A systolic VSLI chip for implementing orthogonal transforms
Bipolar circuit elements providing self-completion-indication
A 19.7 MHz, Fifth-Order Active-RCChebyshev LPF for Draft IEEE802.11n With Automatic Quality-Factor Tuning Scheme
A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation
Battery Voltage Supervisors for Miniature IoT Systems
Analysis and Measurement of Signal Distortion due to ESD Protection Circuits
High-speed dynamic reference voltage (DRV) CMOS/ECL interface circuits
A Baseline-Tracking Single-Channel I/Q Impedance Plethysmogram IC for Neckband-Based Blood Pressure and Cardiovascular Monitoring
A 2.4-GHz 0.25-μm CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b
An Intuitive Analysis of Phase Noise Fundamental Limits Suitable for Benchmarking LC Oscillators
Dynamic Element Matching to Prevent Nonlinear Distortion From Pulse-Shape Mismatches in High-Resolution DACs
Fast compensative design approach for the approximate squaring function
A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS
An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity
A 1.2-Mpixel Indirect Time-of-Flight Image Sensor With 4-Tap 3.5-μm Pixels for Peak Current Mitigation and Multi-User Interference Cancellation
A 2×70W Monolithic Five-Level Class-D Audio Power Amplifier in 180 nm BCD
A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces
A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm
A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons
A multistage amplifier technique with embedded frequency compensation
A 5-Gb/s Automatic Gain Control Amplifier With Temperature Compensation
A 2 K-word dictionary search processor (DISP) LSI with an approximate word search capability
A 1-V 13-mW Single-Path Frequency-Translating ΔΣ Modulator With 55-dB SNDR and 4-MHz Bandwidth at 225 MHz
A 72 dB DR, CT ΔΣ Modulator Using Digitally Estimated, Auxiliary DAC Linearization Achieving 88 fJ/conv-step in a 25 MHz BW
A Low-Power Continuously-Calibrated Clock Recovery Circuit for UHF RFID EPC Class-1 Generation-2 Transponders
An 800-MHz-6-GHz Software-Defined Wireless Receiver in 90-nm CMOS
An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application
110-120-GHz monolithic low-noise amplifiers
A 2.6-V, 44-MHz all-digital QPSK direct-sequence spread-spectrum transceiver IC [wireless LANs]
An 8-b ADC with over-Nyquist input at 300-Ms/s conversion rate
A Linear Multi-Mode CMOS Power Amplifier With Discrete Resizing and Concurrent Power Combining Structure
High-performance and power-efficient CMOS comparators
An intelligent multiplexer/driver integrated circuit for an implantable multichannel blood flowmeter
A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS
A 100 µW 128 × 64 Pixels Contrast-Based Asynchronous Binary Vision Sensor for Sensor Networks Applications
An Offset-Cancelling Discrete-Time Analog Computer for Solving 1-D Wave Equations
A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth
Trimming-Less Voltage Reference for Highly Uncertain Harvesting Down to 0.25 V, 5.4 pW
A 1 GHz CMOS analog front-end for a generalized PRML read channel
A 72-mW CMOS 802.11a direct conversion front-end with 3.5-dB NF and 200-kHz 1/f noise corner
Performance-optimized microstrip coupled VCOs for 40-GHz and 43-GHz OC-768 optical transmission
An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system
An 800-MHz Mixed- V T 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications
EQS Res-HBC: A 65-nm Electro-Quasistatic Resonant 5-240 μW Human Whole-Body Powering and 2.19 μW Communication SoC With Automatic Maximum Resonant Power Tracking
100-Mbit/s single-chip Q-VLMS MLSE equalizer LSI for TDMA mobile radio communications
Am improved tail current source for low voltage applications
A 3-10-GHz low-noise amplifier with wideband LC-ladder matching network
A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS
A 2.2 W, 80 MHz superscalar RISC microprocessor
16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors
Ultrawideband Distributed Amplifier With Positive Feedback and Intrastack Coupling
A 13-bit, 1.4-MS/s sigma-delta modulator for RF baseband channel applications
An analog front end for v.22bis modems
CMOS switched-op-amp-based sample-and-hold circuit
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM
A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation
Sub-µV rms -Noise Sub-µW/Channel ADC-Direct Neural Recording With 200-mV/ms Transient Recovery Through Predictive Digital Autoranging
A 76-Gbit/s 265-GHz CMOS Receiver With WR-3.4 Waveguide Interface
Attenuation-Predistortion Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Applications
A 200-MHz IF BiCMOS signal component separator for linear LINC transmitters
A 3-level asynchronous protocol for a differential two-wire communication link
A 2 µW 100 nV/rtHz Chopper-Stabilized Instrumentation Amplifier for Chronic Measurement of Neural Field Potentials
An mm-Wave Synthesizer With Robust Locking Reference-Sampling PLL and Wide-Range Injection-Locked VCO
An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing
A CMOS electrically configurable gate array
Monolithic 230-V RMS -to-12-V DC AC-DC Converter at 9 mW/mm 2 Enabled by a 31-325-V DC Input Range Capacitive Multi-Ratio DC-DC Converter
Adaptive Multi-Band Multi-Mode Power Amplifier Using Integrated Varactor-Based Tunable Matching Networks
A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os
IF-sampling fourth-order bandpass ΔΣ modulator for digital receiver applications
Comments on 'New monolithic switched-capacitor differentiators with good noise rejection'
A 10 000 fps CMOS Sensor With Massively Parallel Image Processing
A 2.8 GS/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS
Fully Integrated Inductor-Less Flipping-Capacitor Rectifier for Piezoelectric Energy Harvesting
Mismatch shaping for a current-mode multibit delta-sigma DAC
A Versatile Timing Microsystem Based on Wafer-Level Packaged XTAL/BAW Resonators With Sub-µW RTC Mode and Programmable HF Clocks
Analysis and Design of a Robust, Low-Power, Inductively Coupled LSK Data Link
A wide-band CMOS read amplifier for magnetic data storage systems
A 82-nW Chaotic Map True Random Number Generator Based on a Sub-Ranging SAR ADC
A 700- μ W Wireless Sensor Node SoC for Continuous Real-Time Health Monitoring
A single-chip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA
Transmitter Architectures Based on Near-Field Direct Antenna Modulation
CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications
High fan-in circuit design
A 10-bit 1026-Channel Column Driver IC With Partially Segmented Piecewise Linear Digital-to-Analog Converters for UHD TFT-LCDs With One Billion Color Display
A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter
A Bipolar-Output Switched-Capacitor DC-DC Boost Converter With Residual-Energy-Recycling Regulation and Low Dropout Post-Filtering Techniques
A low-power high-gain transresistance BiCMOS pulse amplifier for capacitive detector readout
A highly sensitive on-chip charge detector for CCD area image sensor
A 1-V programmable DSP for wireless communications [CMOS]
An integrated high resolution CMOS timing generator based on an array of delay locked loops
A low-power and compact CDMA matched filter based on switched-current technology
A 200-GHz Modulable Transceiver With 35-dB Tx On-Off Isolation and 16-Gb/s Code Rate for MIMO Radar in 130-nm SiGe Process
Analysis and design of CMOS fuzzy logic controller in current mode
A 3.3-V 800-nV rms noise, gain-programmable CMOS microphone preamplifier design using yield modeling technique
Delay analysis of series-connected MOSFET circuits
A BJT-Based Temperature-to-Digital Converter With a ±0.25 °C 3 σ-Inaccuracy From -40 °C to +180 °C Using Heater-Assisted Voltage Calibration
A Sub-nW 2.4 GHz Transmitter for Low Data-Rate Sensing Applications
Design Techniques for Continuous-Time ΔΣ Modulators With Embedded Active Filtering
A low-power ROM using charge recycling and charge sharing techniques
Time-Divided Spread-Spectrum Code-Based 400 fW-Detectable Multichannel fNIRS IC for Portable Functional Brain Imaging
A tunable pulse-shaping filter for use in a nuclear spectrometer system
A 112 Mb/s Full Duplex Remotely-Powered Impulse-UWB RFID Transceiver for Wireless NV-Memory Applications
A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration
A 0.4-mA-Quiescent-Current, 0.00091%-THD+N Class-D Audio Amplifier With Low-Complexity Frequency Equalization for PWM-Residual- Aliasing Reduction
Dual-Tap Computational Photography Image Sensor With Per-Pixel Pipelined Digital Memory for Intra-Frame Coded Multi-Exposure
Guest Editorial: Introduction to the Special Section on the 2023 Asian Solid-State Circuits Conference (A-SSCC)
All-N-logic high-speed true-single-phase dynamic CMOS logic
Design of Continuous-Time ΔΣ Modulators With Dual Switched-Capacitor Return-to-Zero DACs
A 1.7-dB Minimum NF, 22-32-GHz Low-Noise Feedback Amplifier With Multistage Noise Matching in 22-nm FD-SOI CMOS
A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS
An SP10T Switch With Reconfigurable Matching and Symmetrical Routing Topologies Functioning From DC to 18 GHz
Process-Invariant Current Source Design: Methodology and Examples
A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM
A 32-Unit 240-GHz Heterodyne Receiver Array in 65-nm CMOS With Array-Wide Phase Locking
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control
A power-efficient, low-distortion variable gain amplifier consisting of coupled differential pairs
µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS
A Feedforward Controlled Digital Low-Dropout Regulator With Weight Redistribution Algorithm and Body Voltage Control for Improving Line Regulation With 99.99% Current Efficiency and 0.5-mV Output Voltage Ripple
A 1.5 GHz highly linear CMOS downconversion mixer
A 2-Bit, 24 dBm, Millimeter-Wave SOI CMOS Power-DAC Cell for Watt-Level High-Efficiency, Fully Digital m-ary QAM Transmitters
A 22-dBA Digital Optical MEMS Microphone
A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit
A Sub-100 $\mu$ m-Range-Resolution Time-of-Flight Range Image Sensor With Three-Tap Lock-In Pixels, Non-Overlapping Gate Clock, and Reference Plane Sampling
A direct-conversion receiver for the 3G WCDMA standard
A 250-MHz wave pipelined adder in 2-μm CMOS
A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory
Optimization of buffer stages in bipolar VLSI systems
A switched-current sample-and-hold circuit
Analysis and Design of Integrated Active Cancellation Transceiver for Frequency Division Duplex Systems
A 2.3 μ W Wireless Intraocular Pressure/Temperature Monitor
A low local input 1.9 GHz Si-bipolar quadrature modulator with no adjustment
A 2.7-5.5 V, 0.2-1 W BiCMOS RF driver amplifier IC with closed-loop power control and biasing functions
A High-Efficiency Single-Mode Dual-Path Buck-Boost Converter With Reduced Inductor Current
A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
Dual-Mode Low-Drop-Out Regulator/Power Gate With Linear and On-Off Conduction for Microprocessor Core On-Die Supply Voltages in 14 nm
Design and Measurement of a CT ΔΣ ADC With Switched-Capacitor Switched-Resistor Feedback
A multibit delta-sigma audio DAC with 120-dB dynamic range
Introduction to the Special Section on the 2008 Asian Solid-State Circuits Conference (A-SSCC'08)
A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 °C
An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield
A 23.6-Mb/mm $^{2}$ SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications
Low-power logic circuit and SRAM cell applications with silicon on depletion Layer CMOS (SODEL CMOS) technology
An Energy-Efficient and High-Data-Rate IR-UWB Transmitter for Intracortical Neural Sensing Interfaces
Dynamic Waveform Shaping With Picosecond Time Widths
Radiation Hardening by Design of Asynchronous Logic for Hostile Environments
Analysis and Design of Low-Power Continuous-Time Delta-Sigma Modulator Using Negative-R Assisted Integrator
Notice of Violation of IEEE Publication Principles: A 12.5 Gb/s Electro-Absorption-Modulator Driver Using an Adaptive Compensated Push-Pull Emitter Follower and a Cascode Output Switch With Dynamic Headroom Allocation
The effect of varactor nonlinearity on the phase noise of completely integrated VCOs
Novel low-voltage low-power full-swing BiCMOS circuits
A 117-mm 2 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications
1-V power supply CMOS cascode amplifier
A Push-Push VCO With 13.9-GHz Wide Tuning Range Using Loop-Ground Transmission Line for Full-Band 60-GHz Transceiver
A Low-Power Fully Monolithic Subthreshold CMOS Receiver With Integrated LO Generation for 2.4 GHz Wireless PAN Applications
Analysis of coupling noise between adjacent bit lines in megabit DRAMs
A 455-Mb/s MR preamplifier design in a 0.8-μm CMOS process
A single-bit-line cross-point cell activation (SCPA) architecture for ultra-low-power SRAM's
A 2-Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60-GHz Short-Range Wireless Communication