yusuke1997/dblp-id-title huggingface dataset:
Low-power direct digital frequency synthesis for wireless communications
Principle and applications of an autocharge-compensated sample and hold circuit
An all-digital phase-locked loop (ADPLL)-based clock recovery circuit
An experimental study of testing techniques for bridging faults in CMOS ICs
A comparison of GaAs HJBT and silicon bipolar technologies for high-speed analog-to-digital converters
Correction to "A 15-Bit 40-MS/s CMOS Pipelined Analog-to-Digital Converter With Digital Background Calibration"
Analysis and Comparison of Logic Architectures for Digital Circuits in a-IGZO Thin-Film Transistor Technologies
0.2 V 8T SRAM With PVT-Aware Bitline Sensing and Column-Based Data Randomization
Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits
Multimedia extensions for a 550-MHz RISC microprocessor
An optoelectronic CMOS circuit implementing a simulated annealing algorithm
An 860-Mb/s (8158, 7136) Low-Density Parity-Check Encoder
A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS
Artificial neural networks using MOS analog multipliers
An eight-bit prefetch circuit for high-bandwidth DRAM's
A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range
Introduction to the Special Issue on the 34th ESSCIRC
A 4.4-µW Wake-Up Receiver Using Ultrasound Data
Reprogrammable Redundancy for SRAM-Based Cache V min Reduction in a 28-nm RISC-V Processor
Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm
A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS
A fully integrated, untrimmed CMOS instrumentation amplifier with submicrovolt offset
Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC)
CMOS image sensor with mixed-signal processor array
A 150-MHz direct digital frequency synthesizer in 1.25- mu m CMOS with -90-dBc spurious performance
A 2.92-µW Capacitance-to-Digital Converter With Differential Bondwire Accelerometer, On-Chip Air Pressure, and Humidity Sensor in 0.18-µm CMOS
A 65-nm CMOS I/Q RF Power DAC With 24- to 42-dB Third-Harmonic Cancellation and Up to 18-dB Mixed-Signal Filtering
A single-chip 900-MHz spread-spectrum wireless transceiver in 1-μm CMOS. I. Architecture and transmitter design
A Neural Network Training Processor With 8-Bit Shared Exponent Bias Floating Point and Multiple-Way Fused Multiply-Add Trees
A 16 b Multi-Step Incremental Analog-to-Digital Converter With Single-Opamp Multi-Slope Extended Counting
An Interface for Eddy-Current Displacement Sensors With 15-bit Resolution and 20 MHz Excitation
Low-power digital filtering using approximate processing
A 1.2.1 post-filter for color-difference interpolation of a MAC video signal
A 240-mW 2.1-GS/s 52-dB SNDR Pipeline ADC Using MDAC Equalization
An integrated CMOS RF synthesizer for 802.11a wireless LAN
48-GHz digital ICs and 85-GHz baseband amplifiers using transferred-substrate HBT's
Frequency-Independent Asymmetric Double-$pi $Equivalent Circuit for On-Chip Spiral Inductors: Physics-Based Modeling and Parameter Extraction
A Temperature- and Aging-Compensated RC Oscillator With ±1030-ppm Inaccuracy From40 °C to 85 °C After Accelerated Aging for 500 h at 125 °C
A 915 MHz 175 µW Receiver Using Transmitted-Reference and Shifted Limiters for 50 dB In-Band Interference Tolerance
A 75-µW, 16-Channel Neural Spike-Sorting Processor With Unsupervised Clustering
A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology
Study and Design of a Fast Start-Up Crystal Oscillator Using Precise Dithered Injection and Active Inductance
An Ultra-Low Phase Noise Class-F 2 CMOS Oscillator With 191 dBc/Hz FoM and Long-Term Reliability
Power-Efficient Design Techniques for mm-Wave Hybrid/Digital FDD/Full-Duplex MIMO Transceivers
An EMG Interface Comprising a Flexible a-IGZO Active Electrode Matrix and a 65-nm CMOS IC
MOS transistor modeling for RF IC design
A 1/3-in 410000-pixel CCD image sensor with feedback field-plate amplifier
A high-performance analog front-end 14-bit codec for 2.7-V digital cellular phones
Low-Voltage Super class AB CMOS OTA cells with very high slew rate and power efficiency
Always-On CMOS Image Sensor for Mobile and Wearable Devices
Low-power fully integrated 10-Gb/s SONET/SDH transceiver in 0.13-μm CMOS
Design of a low-distortion 22-kHz fifth-order Bessel filter
A 65 nm CMOS Wideband Radio Receiver With ΔΣ-Based A/D-Converting Channel-Select Filters
80-Mb/s QPSK and 72-Mb/s 64-QAM flexible and scalable digital OFDM transceiver ASICs for wireless local area networks in the 5-GHz band
A transistor-only current-mode Sigma Delta modulator
A 1-GHz 16-Element Four-Beam True-Time-Delay Digital Beamformer
A scalable instruction buffer and align unit for xDSPcore
Nanostructured CMOS Wireless Ultra-Wideband Label-Free PCR-Free DNA Analysis SoC
A 0.016 mm 2 , 2.4 GHz RF Signal Quality Measurement Macro for RF Test and Diagnosis
A 17 bit oversampling D-A conversion technology using multistage noise shaping
A Data-Compressive 1.5/2.75-bit Log-Gradient QVGA Image Sensor With Multi-Scale Readout for Always-On Object Detection
A single-chip 900-MHz spread-spectrum wireless transceiver in 1-μm CMOS. II. Receiver design
A low-power DS-CDMA RAKE receiver utilizing resource allocation techniques
A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks
Fully Integrated Optical Injection Locking With Schottky Photodiodes in 65-nm CMOS
A fine-line NMOS 3-Gbit/s 12 channel time-division multiplexer-demultiplexer chip set
A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques
A digital-to-analog converter based on differential-quad switching
A 256×256 compact CMOS image sensor with on-chip motion detection function
Multiple-valued radix-2 signed-digit arithmetic circuits for high-performance VLSI systems
A 100 × 80 Flash LiDAR Sensor With In-Pixel Zoom-Histogramming TDC and Self-Referenced Single-Slope ADC Based on Analog Counters
An 0.8-mm 2 9.6-mW Iterative Decoder for Faster-Than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65-nm CMOS
A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme
A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors
A High-Voltage Dual-Input Buck Converter With Bidirectional Inductor Current for Triboelectric Energy-Harvesting Applications
A CMOS Imager With Column-Level ADC Using Dynamic Column Fixed-Pattern Noise Reduction
A 1.5-1.9-GHz All-Digital Tri-Phasing Transmitter With an Integrated Multilevel Class-D Power Amplifier Achieving 100-MHz RF Bandwidth
A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology
A GaN-on-Si Gate Driver With Self-Pumped Drive Enhance and Short-Period Negative Voltage Techniques for Reduction of 14.7× Tailing Power Loss and 37% Reverse Conduction Loss
Constant-ratio-coupled multi-grain digital synchronizer with flexible input-output delay selection for versatility in low-power applications
Analytical Determination of MOSFET's High-Frequency Noise Parameters From NF 50 Measurements and Its Application in RFIC Design
A Multi-Mode 8k-MAC HW-Utilization-Aware Neural Processing Unit With a Unified Multi-Precision Datapath in 4-nm Flagship Mobile SoC
A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS
A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration
A 4-Mb low-temperature DRAM
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology
Erratum to "A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver"
A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops
Comments on the metastable behavior of mismatched CMOS latches
A 28-nm-CMOS Based 145-GHz FMCW Radar: System, Circuits, and Characterization
A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs
A single-chip CMOS optical microspectrometer with light-to-frequency converter and bus interface
2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking
An I/Q active balanced harmonic mixer with IM2 cancelers and a 45° phase shifter
Analysis and Design of a 20-MHz Bandwidth, 50.5-dBm OOB-IIP3, and 5.4-mW TIA for SAW-Less Receivers
Design and performance of multistage GaAs dynamic logic
Correction to "A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC"
Speed and accuracy enhancement techniques for high-performance switched-current comparators
Technology developments driving an evolution of cellular phone power amplifiers to integrated RF front-end modules
A micropower CMOS continuous-time low-pass filter
A Low-Power, Low-Voltage WBAN-Compatible Sub-Sampling PSK Receiver in 65 nm CMOS
Optimal usage of CMOS within a BiCMOS technology
A 10-GHz global clock distribution using coupled standing-wave oscillators
A 0.016-mm 2 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With > 0.95-MHz GBW
A 1.9-GHz Si-bipolar variable attenuator for PHS transmitter
An Energy-Efficient POSIT Compute-in-Memory Macro for High-Accuracy AI Applications
A 10 MHz Bandwidth, 2 mV Ripple PA Regulator for CDMA Transmitters
Always-On 12-nW Acoustic Sensing and Object Recognition Microsystem for Unattended Ground Sensor Nodes
A 6-Gb/s Inductively-Powered Non-Contact Connector With Rotatable Transmission Line Coupler and Interface Bridge IC
A CMOS time-to-digital converter with better than 10 ps single-shot precision
Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time
A Sub-mm 3 Wireless Neural Stimulator IC for Visual Cortical Prosthesis With Optical Power Harvesting and 7.5-kb/s Data Telemetry
Razor-Lite: A Light-Weight Register for Error Detection by Observing Virtual Supply Rails
Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register
High-Efficiency Class-E Power Amplifiers for mmWave Radar Sensors: Design and Implementation
All-Digital Circuits for Measurement of Spatial Variation in Digital Circuits
A 200-Ms/s 10-mW switched-capacitor filter in 0.5-μm CMOS technology
C 3 MLS: An Ultra-Wide-Range Energy-Efficient Level Shifter With CCLS/CMLS Hybrid Structure
OmniDRL: An Energy-Efficient Deep Reinforcement Learning Processor With Dual-Mode Weight Compression and Sparse Weight Transposer
Ion microbeam probing of sense amplifiers to analyze single event upsets in a CMOS DRAM
A 10-Gb/s Inductorless CMOS Limiting Amplifier With Third-Order Interleaving Active Feedback
A 24-GHz Fully Integrated CMOS Transceiver for FMCW Radar Applications
SIGFRED: a low-power DTMF and signaling frequency detector
A switched-current, switched-capacitor temperature sensor in 0.6-μm CMOS
Design and application of a GaAs digital RF memory chip
Conditional-capture flip-flop for statistical power reduction
A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving
A 31-µW, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS
A low-distortion BiCMOS seventh-order Bessel filter operating at 2.5 V supply
A 32-Mb chain FeRAM with segment/stitch array architecture
An 800-MHz 1-μm CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops
An approach to computer-aided specification
An Online-Spike-Sorting IC Using Unsupervised Geometry-Aware OSort Clustering for Efficient Embedded Neural-Signal Processing
Direct TOF Scanning LiDAR Sensor With Two-Step Multievent Histogramming TDC and Embedded Interference Filter
Performance comparison of driver configurations and full-swing techniques for BiCMOS logic circuits
Biasing circuit for high input swing operational amplifiers
A Low-Power Capacitive Charge Pump Based Pipelined ADC
Simple precision bias circuit for medium-power amplifiers
Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallel comparison and parity check functions
An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor
An Ultra-Wideband IF Millimeter-Wave Receiver With a 20 GHz Channel Bandwidth Using Gain-Equalized Transformers
An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory
Analysis and Design of a 30- to 220-GHz Balanced Cascaded Single-Stage Distributed Amplifier in 130-nm SiGe BiCMOS
Cryo-CMOS Voltage References for the Ultrawide Temperature Range From 300 K Down to 4.2 K
A 12-b 16-GS/s RF-Sampling Capacitive DAC for Multi-Band Soft Radio Base-Station Applications With On-Chip Transmission-Line Matching Network in 16-nm FinFET
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology
A 400-Msample/s, 6-b CMOS folding and interpolating ADC
A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector
A 52% Peak Efficiency > 1-W Isolated Power Transfer System Using Fully Integrated Transformer With Magnetic Core
Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS
Ultra-dynamic Voltage scaling (UDVS) using sub-threshold operation and local Voltage dithering
A quadrature data-dependent DEM algorithm to improve image rejection of a complex ΣΔ modulator
Microwatt Embedded Processor Platform for Medical System-on-Chip Applications
High-frequency characterization and modeling of distortion behavior of MOSFETs for RF IC design
A 70-mW 300-MHz CMOS continuous-time ΣΔ ADC with 15-MHz bandwidth and 11 bits of resolution
A 2.6 µW -1.2 mW Autonomous Electromagnetic Vibration Energy Harvester Interface IC with Conduction-Angle-Controlled MPPT and up to 95% Efficiency
CMOS Oscillators for Clock Distribution and Injection-Locked Deskew
A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer
Techniques to Extend Canary-Based Standby V DD Scaling for SRAMs to 45 nm and Beyond
HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis
30-100-MHz NPN-only variable-gain class-AB instantaneous companding filters for 1.2-V applications
Spatially Resolved Event-Driven 24 × 24 Pixels SPAD Imager With 100% Duty Cycle for Low Optical Power Quantum Entanglement Detection
Measurements and Analysis of Process Variability in 90nmCMOS
A 6 GHz 68 mW BiCMOS phase-locked loop
40-GHz transimpedance amplifier with differential outputs using InP-InGaAs heterojunction bipolar transistors
NMOS IC's for clock and data regeneration in gigabit-per-second optical-fiber receivers
A low-noise low-drift transducer ADC
Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster
Introduction to the Special Section on the 2015 Custom Integrated Circuits Conference
A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity
An Auto-Zero-Voltage-Switching Quasi-Resonant LED Driver With GaN FETs and Fully Integrated LED Shunt Protectors
High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories
A Pulsed UWB Transceiver in 65 nm CMOS With Four-Element Beamforming for 1 Gbps Meter-Range WPAN Applications
A low-power 416-lag 1.5-b 0.5-TMAC correlator in 0.6-μm CMOS
A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation
A Low-Phase-Noise Wide-Tuning-Range Oscillator Based on Resonant Mode Switching
Synchronous mirror delay for multiphase locking
A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC
A Hybrid Magnetic Current Sensor With a Dual Differential DC Servo Loop
A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network
A 1 × 400 Backside-Illuminated SPAD Sensor With 49.7 ps Resolution, 30 pJ/Sample TDCs Fabricated in 3D CMOS Technology for Near-Infrared Optical Tomography
A 0.6V 785-nW Multimodal Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring
A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS
Single-Inductor Quad-Output Switching Converter With Priority-Scheduled Program for Fast Transient Response and Unlimited Load Range in 40 nm CMOS Technology
A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache
State assignment for low power dissipation
Low-voltage DRAM sensing scheme with offset-cancellation sense amplifier
An 8-bit 2-ns monolithic DAC
Cancellation of crosstalk-induced jitter
A Fully Integrated Reconfigurable Switched-Capacitor DC-DC Converter With Four Stacked Output Channels for Voltage Stacking Applications
A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder
A 40-Gb/s Transimpedance Amplifier in 0.18-µm CMOS Technology
A Scalable CMOS Ising Computer Featuring Sparse and Reconfigurable Spin Interconnects for Solving Combinatorial Optimization Problems
A monolithic transformer coupled 5-W silicon power amplifier with 59% PAE at 0.9 GHz
Stuck-open testable scan-based CMOS sequential circuits
Introduction to the Special Issue on the 2015 Symposium on VLSI Circuits
A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET
40-Gb/s ICs for future lightwave communications systems
A 65 nm Wireless Image SoC Supporting On-Chip DNN Optimization and Real-Time Computation-Communication Trade-Off via Actor-Critical Neuro-Controller
A Reconfigurable DC-DC Converter for Maximum Thermoelectric Energy Harvesting in a Battery-Powered Duty-Cycling Wireless Sensor Node
A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique
An Energy-Efficient OOK Transceiver for Wireless Sensor Networks
SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application
Single-chip CMOS image sensor for mobile applications
A 22 V Compliant 56 ${\mu}$ W Twin-Track Active Charge Balancing Enabling 100% Charge Compensation Even in Monophasic and 36% Amplitude Correction in Biphasic Neural Stimulators
A 30-MHz-2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems
A 90 nm CMOS DSP MLSD Transceiver With Integrated AFE for Electronic Dispersion Compensation of Multimode Optical Fibers at 10 Gb/s
A 0.5-1 V, -68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOS
Design of an Always-On Deep Neural Network-Based 1- $\mu$ W Voice Activity Detector Aided With a Customized Software Model for Analog Feature Extraction
A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip
A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques
A High-Efficiency DC-DC Converter Using 2 nH Integrated Inductors
A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < -61dB at 2.8 GS/s With DEMDRZ Technique
LVDS I/O interface for Gb/s-per-pin operation in 0.35-μ/m CMOS
Fully integrated W-CDMA IF receiver and IF transmitter including IF synthesizer and on-chip VCO for UMTS mobiles
A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process
Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler
$V_rm DD$-Hopping Accelerators for On-Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time
An analog front-end signal processor for a 64 Mbits/s PRML hard-disk drive channel
A low-power BiCMOS switched-capacitor filter for audio codec applications
MOS oscillators with multi-decade tuning range and gigahertz maximum speed
A 118.4 GB/s Multi-Casting Network-on-Chip With Hierarchical Star-Ring Combined Topology for Real-Time Object Recognition
3D Ultrasonic Rangefinder on a Chip
A unified theory for mixed CMOS/BiCMOS buffer optimization
A Coupled-RTWO-Based Subharmonic Receiver Front End for 5G E-Band Backhaul Links in 28-nm Bulk CMOS
Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate
A multiband ΔΣ fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC
A 511-μW 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique
Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector
A CMOS Polar Class-G Switched-Capacitor PA With a Single High-Current Supply, for LTE NB-IoT and eMTC
A Batteryless Padless Crystalless 116 µm × 116 µm "Dielet" Near-Field Radio With On-Chip Coil Antenna
A RF to DC Voltage Conversion Model for Multi-Stage Rectifiers in UHF RFID Transponders
A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring
Impact of capacitor dielectric relaxation on a 14-bit 70-MS/s pipeline ADC in 3-V BiCMOS
Microfabricated thermal absolute-pressure sensor with on-chip digital front-end processor
A Fast SIMO Converter for Command-Directed IoT Nodes With State-Driven Priority Sequencing and Delay-Adjusted Fixed Window Hysteretic Control Using Constant Current-Peak Sequential DCM-CCM Operation
A Sub-THz Full-Duplex Phased-Array Transceiver With Self-Interference Cancellation and LO Feedthrough Suppression
An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance
Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking
General-purpose neural chips with electrically programmable synapses and gain-adjustable neurons
A 4 Gb/s 2-level to 2 Gsymbol/s 4-level converter GaAs IC for semiconductor optical amplifier QPSK modulators
A 108-114 GHz 4 × 4 Wafer-Scale Phased Array Transmitter With High-Efficiency On-Chip Antennas
A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling
A 480-MHz RISC microprocessor in a 0.12-μm L eff CMOS technology with copper interconnects
W-band InP HEMT MMICs using finite-ground coplanar waveguide (FGCPW) design
Fully Integrated Electronic-Photonic Ultrasound Receiver Array for Endoscopic Applications in a Zero-Change 45-nm CMOS-SOI Process
A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35-µm CMOS
A Josephson 10-b instruction 128-word ROM unit
A 76-MHz BiCMOS programmable logic sequencer
A 0.5-V 8-bit 10-Ms/s Pipelined ADC in 90-nm CMOS
A 130-nm 0.9-V 66-MHz 8-Mb (256K × 32) local SONOS embedded flash EEPROM
A Wideband Fully Integrated Software-Defined Transceiver for FDD and TDD Operation
A Wideband, Dual-Path, Millimeter-Wave Power Amplifier With 20 dBm Output Power and PAE Above 15% in 130 nm SiGe-BiCMOS
Standby power reduction using dynamic voltage scaling and canary flip-flop structures
A 13-bit 0.005-mm 2 40-MS/s SAR ADC With kT/C Noise Cancellation
An 800-MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8 μm CMOS
A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-μm digital CMOS
A Chopping-Free Single-Trim Bandgap Reference Using Amplifier With PTAT Offset
New capabilities of the CMOS inverter
Continuous-Time Input Pipeline ADCs
A High-Efficiency Envelope-Tracking Supply Modulator Using a Class-G Linear Amplifier and a Single-Inductor Dual-Input-Dual-Output Converter for 5G NR Power Amplifier
Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC
A 6 Gb/s 6 pJ/b 5 mm-Distance Non-Contact Interface for Modular Smartphones Using Two-Fold Transmission Line Coupler and High EMC Tolerant Pulse Transceiver
An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications
A Load-Adaptive Class-G Headphone Amplifier With Supply-Rejection Bandwidth Enhancement Technique
A 7.1-fJ/Conversion-Step 88-dB SFDR SAR ADC With Energy-Free "Swap To Reset"
A 12-b, 10-MHz, 250-mW CMOS A/D converter