yusuke1997/dblp-id-title huggingface dataset:
Probabilistic analysis of interconnect coupling noise
Modeling and Extraction of Causal Information in Analog Circuits
Mixed frequency/time domain analysis of nonlinear circuits
Unified 2-D X-Alignment for Improving the Observability of Response Compactors
Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros
Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection
A Block Interconnection Algorithm for Hierarchical Layout System
Nonlinear decision boundaries for testing analog circuits
Re-Meltrix: A Reconfigurable Processing-in-Memory Architecture Based on RRAM and Function Synthesis
EDF-Based Energy-Efficient Semi-Clairvoyant Scheduling With Graceful Degradation
Improved net merging method for gate matrix layout
IC test using the energy consumption ratio
UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing
ASCENT: Communication Scheduling for SDF on Bufferless Software-Defined NoC
Shared buffer implementations of signal processing systems usinglifetime analysis techniques
Linear gate assignment: a fast statistical mechanics approach
Data-Driven Feature Selection Framework for Approximate Circuit Design
A Variability-Aware Adaptive Test Flow for Test Quality Improvement
Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints
High-Level Synthesis for FPGAs: From Prototyping to Deployment
A general purpose device simulator coupling Poisson and Monte Carlo transport with applications to deep submicron MOSFETs
Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay Measurements
Dogleg Channel Routing is NP-Complete
Test set embedding for deterministic BIST using a reconfigurable interconnection network
Test generation for sequential circuits
A performance-driven logic emulation system: FPGA network design and performance-driven partitioning
A Customizable Framework for Application Implementation onto 3-D FPGAs
Accurate Interpolation of Library Timing Parameters Through Recurrent Convolutional Neural Network
A Parallel Processing Approach for Logic Module Placement
DFM Evaluation Using IC Diagnosis Data
On minimizing the number of L-shaped channels in building-block layout [VLSI]
Making Frequent-Pattern Mining Scalable, Efficient, and Compact on Nonvolatile Memories
A Recursive Partition-Based In-Memory SIMD Computation Scheduler for Memory Footprint Minimization
System-Level Signal Analysis Methodology for Optical Network-on-Chip Using Linear Model-Based Characterization
TALIPOT: Energy-Efficient DNN Booster Employing Hybrid Bit Parallel-Serial Processing in MSB-First Fashion
Collecting Data About Logic Simulation
On the characterization and efficient computation of hard-to-detect bridging faults
The Learnable Model-Based Genetic Algorithm for the IP Mapping Problem
Logic emulation with virtual wires
Path Predicate Abstraction for Sound System-Level Models of RT-Level Circuit Designs
Learning redesign knowledge circuit redesign
SPAR: a schematic place and route system
TUTOR: Training Neural Networks Using Decision Rules as Model Priors
Error Diluting: Exploiting 3-D nand Flash Process Variation for Efficient Read on LDPC-Based SSDs
A Novel SAT-Based Approach to the Task Graph Cost-Optimal Scheduling Problem
Techniques for area estimation of VLSI layouts
C compiler design for a network processor
Mining Hardware Assertions With Guidance From Static Analysis
A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations
Layout verification for mixed-domain integrated MEMS
Shift-Limited Sort: Optimizing Sorting Performance on Skyrmion Memory-Based Systems
Leakage and Aging Optimization Using Transmission Gate-Based Technique
Finite Element Approach Based Numerical Framework for Device Simulator
Scratch That (But Cache This): A Hybrid Register Cache/Scratchpad for GPUs
Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis
Multilevel global placement with congestion control
Detection of multiple faults in MOS circuits
RED: A ReRAM-Based Efficient Accelerator for Deconvolutional Computation
Modeling of gate oxide shorts in MOS transistors
GOURD: Tensorizing Streaming Applications to Generate Multi-Instance Compute Platforms
Timing Error Tolerant CNN Accelerator With Layerwise Approximate Multiplication
Constraint-Based Layout-Driven Sizing of Analog Circuits
Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements
A unified approach to variable voltage scheduling for nonideal DVS processors
PaRS: Parallel and Near-Optimal Grid-Based Cell Sizing for Library-Based Design
Reducing Interpolant Circuit Size Through SAT-Based Weakening
A study on global and local optimization techniques for TCAD analysis tasks
Performance driven spacing algorithms using attractive and repulsive constraints for submicron LSI's
Eva-CiM: A System-Level Performance and Energy Evaluation Framework for Computing-in-Memory Architectures
A Bloom-Filter-Based Unique Address Checking Approach for DAG-Based Blockchain Systems
Efficient and Scalable Post-Layout Optimization for Field-Coupled Nanotechnologies
Configuration compression for the Xilinx XC6200 FPGA
Spectral K-way ratio-cut partitioning and clustering
A BIST scheme for RTL circuits based on symbolic testabilityanalysis
A RISC-V Extended Infrastructure for CNNs Through Pipelined Computing and Data Dependence Optimization
Design Rule Violation Prediction at Sub-10-nm Process Nodes Using Customized Convolutional Networks
Fault testing for reversible circuits
Buffering Interconnect for Multicore Processor Designs
A Simple and Effective Heuristic Method for Threshold Logic Identification
Extending the Effective Throughput of NoCs With Distributed Shared-Buffer Routers
Algorithmic Aspects of Symbolic Switch Network Analysis
Newton-Raphson iteration speed-up algorithm for the solution of nonlinear circuit equations in general-purpose CAD programs
Victim Alignment in Crosstalk-Aware Timing Analysis
Memristor Modeling Using the Modified Nodal Analysis Approach
An Integrated Framework Toward Defect-Tolerant Logic Implementation Onto Nanocrossbars
Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults
A Multilabel Active Learning Framework for Microcontroller Performance Screening
High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators
Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint
Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems
Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs
A design-for-testability technique for register-transfer level circuits using control/data flow extraction
Combinational and sequential logic optimization by redundancy addition and removal
On computing the sizes of detected delay faults
Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects
Sensitivity Analysis of Lossy Multiconductor Transmission Lines Based on the Passive Method of Characteristics Macromodel
Optimizing Vertical Link Placement and Congestion Aware Dynamic Elevator Assignment for Partially Connected 3D-NoCs
Addendum to 'A kernel-finding state assignment algorithm for multi-level logic'
Body-voltage estimation in digital PD-SOI circuits and itsapplication to static timing analysis
SDS: An Optimal Slack-Driven Block Shaping Algorithm for Fixed-Outline Floorplanning
An Analytical Approach for Network-on-Chip Performance Analysis
Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits
DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained Reconfigurable Architectures
Computing Execution Times With Execution Decision Diagrams in the Presence of Out-of-Order Resources
New approaches in a 3-D one-carrier device solver
A Simulation Framework for Memristor-Based Heterogeneous Computing Architectures
Online Resource Management for Improving Reliability of Real-Time Systems on "Big-Little" Type MPSoCs
A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs
Single-Layer GNR Routing for Minimization of Bending Delay
Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes
Automatic Pipelining From Transactional Datapath Specifications
Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi Channel Lengths
lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) Complexity
Twin binary sequences: a nonredundant representation for general nonslicing floorplan
Low Cost EVM Testing of Wireless RF SoC Front-Ends Using Multitones
Hierarchical Verification of AMS Systems With Affine Arithmetic Decision Diagrams
Formal Feature Interpretation of Hybrid Systems
Synthesis of Application-Specific Fault-Tolerant Digital Microfluidic Biochip Architectures
A Unified Engine for Accelerating GNN Weighting/Aggregation Operations, With Efficient Load Balancing and Graph-Specific Caching
FSA: A Fine-Grained Systolic Accelerator for Sparse CNNs
RESIST: a recursive test pattern generation algorithm for path delay faults considering various test classes
Black-Box Test-Cost Reduction Based on Bayesian Network Models
The calculation of signal stable ranges in combinational circuits
MC-QDSNN: Quantized Deep Evolutionary SNN With Multidendritic Compartment Neurons for Stress Detection Using Physiological Signals
A Low-Cost Field-Programmable Pin-Constrained Digital Microfluidic Biochip
Don't care set specifications in combinational and synchronous logic circuits
Leveraging Write Heterogeneity of Phase Change Memory on Supporting Self-Balancing Binary Tree
Error Detection and Recovery for ECC: A New Approach Against Side-Channel Attacks
Efficient Layer Assignment of Bus-Oriented Nets in High-Speed PCB Designs
A Structured Visual Approach to GALS Modeling and Verification of Communication Circuits
Methodology for Distributed-ROM-Based Implementation of Finite State Machines
The Connection-Then-Credit Flow Control Protocol for Heterogeneous Multicore Systems-on-Chip
UniBuffer: Optimizing Journaling Overhead With Unified DRAM and NVM Hybrid Buffer Cache
Reducing Data TLB Power via Compiler-Directed Address Generation
Testing of scan circuits containing nonisolated random-logic legacycores
A neural network model for multilayer topological via minimization in a switchbox
STAR: An automatic data path allocator
Improving and Estimating the Precision of Bounds on the Worst-Case Latency of Task Chains
Explicit and implicit algorithms for binate covering problems
Locality-Based Encoder and Model Quantization for Efficient Hyper-Dimensional Computing
Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems
Low-Power Test Data Application in EDT Environment Through Decompressor Freeze
Support-Reducing Decomposition for FPGA Mapping
Weave: Abstraction and Integration Flow for Accelerators of Generated Modules
Near-Optimal Energy Management for Energy Harvesting IoT Devices Using Imitation Learning
Advanced Equivalence Checking for Quantum Circuits
A ULSI 2-D capacitance simulator for complex structures based on actual processes
Balancing Computation Loads and Optimizing Input Vector Loading in LSTM Accelerators
Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications
DETERRENT: Detecting Trojans Using Reinforcement Learning
Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run
A new FPGA detailed routing approach via search-based Booleansatisfiability
Exploiting Bit-Level Delay Calculations to Soften Read-After-Write Dependences in Behavioral Synthesis
A novel macromodel for power estimation in CMOS structures
On-Device Continual Learning With STT-Assisted-SOT MRAM-Based In-Memory Computing
Intrinsic response extraction for the removal of the parasiticeffects in analog test buses
Deeper Weight Pruning Without Accuracy Loss in Deep Neural Networks: Signed-Digit Representation-Based Approach
Improving test effectiveness of scan-based BIST by scan chain partitioning
Model checking on timed-event structures
From a Federated to an Integrated Automotive Architecture
SMALS: a novel database for two-dimensional object location
Fast Lithographic Mask Optimization Considering Process Variation
Biochip Synthesis and Dynamic Error Recovery for Sample Preparation Using Digital Microfluidics
Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints
Efficient Space Management Techniques for Large-Scale Interconnect Capacitance Extraction With Floating Random Walks
A framework for industrial layout generators
Validatable nonrobust delay-fault testable circuits via logic synthesis
Wire-sizing optimization with inductance consideration using transmission-line model
Control-Logic Synthesis of Fully Programmable Valve Array Using Reinforcement Learning
Cost-Constrained QoS Optimization for Approximate Computation Real-Time Tasks in Heterogeneous MPSoCs
PROOFS: a fast, memory-efficient sequential circuit fault simulator
Hierarchical VLSI Routing - An Approximate Routing Procedure
BOT-MICS: Bounding Time Using Analytics in Mixed-Criticality Systems
Test generation and verification for highly sequential circuits
Semi-Analytical Path Delay Variation Model With Adjacent Gates Decorrelation for Subthreshold Circuits
Hardware Trojan Detection Using Graph Neural Networks
New data-background sequences and their industrial evaluation for word-oriented random-access memories
Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator
Star test: the theory and its applications
Probabilistic Multiknob High-Level Synthesis Design Space Exploration Acceleration
Sensitivity Analysis for Device Design
S-parameter analysis of multiconductor, integrated circuit interconnect systems
Placement Refinement Strategies for Security Closure
FSMx-Ultra: Finite State Machine Extraction From Gate-Level Netlist for Security Assessment
Fast Machine-Learning-Driven Supply Noise-Aware Macromodeling for High-Speed Nonlinear Drivers
Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination
Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation
Synthesis of application specific instruction sets
Oscillation-Based Prebond TSV Test
A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash
Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage
Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based Partitioning
Checkpointing-Aware Loop Tiling for Energy Harvesting Powered Nonvolatile Processors
An Efficient On-Chip Test Generation Scheme Based on Programmable and Multiple Twisted-Ring Counters
Realization of Early-Exit Dynamic Neural Networks on Reconfigurable Hardware
Generating Scalable and Modular Macromodels for Microchannels Using the Galerkin-Based Technique
Resistorless Memristor Emulators: Floating and Grounded Using OTA and VDBA for High-Frequency Applications
Porosity-aware buffered Steiner tree construction
A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA
An improved method for computing a generalized spectral coefficient
An Anytime Algorithm for Generalized Symmetry Detection in ROBDDs
Closed-form delay and slew metrics made easy
Study of 3-D Line Edge Roughness (LER) in Vertical Channel Array Transistor for DRAM
Microfluidic Injector Models Based on Artificial Neural Networks
DFT for digital detection of analog parametric faults in SC filters
Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW
Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration Framework
Comparison of Algorithms for Frequency Domain Coupled Device and Circuit Simulation
Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution
LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach
AIoTML: A Unified Modeling Language for AIoT-Based Cyber-Physical Systems
Voltage-Aware Static Timing Analysis
Statistical Static Timing Analysis Considering Process Variation Model Uncertainty
Test responses compaction in accumulators with rotate carry adders
Optimizing Thermal Sensor Allocation for Microprocessors
A Data Base Driven Automated System for MOS Device Characterization, Parameter Optimization and Modeling
Scaling theory for fault stealing algorithms in large systolic arrays
Multilevel fixed-point-addition-based VLSI placement
Predicting potential performance for digital circuits
Automatic Generation of Peak-Power Traffic for Networks-on-Chip
Microwave Network-Assisted Analysis and Machine Learning-Assisted Synthesis of Arbitrarily Tapped Coils and Its Application to On-Chip Ultrawideband ESD Protection Circuits
Mapping for Maximum Performance on FPGA DSP Blocks
Layout-dependent fault analysis and test synthesis for CMOS circuits
Memory-Efficient On-Chip Network With Adaptive Interfaces
SiHGNN: Leveraging Properties of Semantic Graphs for Efficient HGNN Acceleration
Design and Utilization of Multiskewed Multibit Flip-Flop Cells for Timing Optimization: Design and Technology Co-Optimization Approach
Transistor-level estimation of worst-case delays in MOS VLSI circuits
An analytic Volterra-series-based model for a MEMS variable capacitor
Test Generation for Functionally Possible Subpaths
On Effective Through-Silicon Via Repair for 3-D-Stacked ICs
Chippe: a system for constraint driven behavioral synthesis
An analytical approach to floorplan design and optimization
Timing-driven partitioning-based placement for island style FPGAs
Variability-Aware, Discrete Optimization for Analog Circuits
Transparent In-Circuit Assertions for FPGAs
Behavioral transformation for algorithmic level IC design
Fast Timing-Model Independent Buffered Clock-Tree Synthesis
A directed search method for test generation using a concurrent simulator
Co-ViSu: Accelerating Video Super-Resolution With Codec Information Reuse
Bridging Fault Test Method With Adaptive Power Management Awareness
Automatic Retiming of Two-Phase Latch-Based Resilient Circuits
A proposed method for dynamic fitting of MOS model parameters
M²NAS: Joint Neural Architecture Optimization System With Network Transmission
CMOS op-amp sizing using a geometric programming formulation
High-Efficiency Green Function-Based Thermal Simulation Algorithms
Path-Directed Abstraction and Refinement for SAT-Based Design Debugging
The linearized performance penalty (LPP) method for optimization of parametric yield and its reliability
Heuristic Methods for Fine-Grain Exploitation of FDSOI
On crossing minimization problem
Multistage Enhanced Diagnosis With Fault Candidate Reduction
Symbolic FSM traversals based on the transition relation
Dual-V dd Buffer Insertion for Power Reduction
PcGC: A Parity-Check Garbage Collection for Boosting 3-D NAND Flash Performance
Cellular automata for efficient parallel logic and fault simulation
Deeploy: Enabling Energy-Efficient Deployment of Small Language Models on Heterogeneous Microcontrollers
A Hierarchical Standard Cell Approach for Custom VLSI Design
Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies
An analysis of the aliasing probability of multiple-input signature registers in the case of a 2 m -ary symmetric channel
Online Firmware Functional Validation Scheme Using Colored Petri Net Model
On the feasibility of synthesizing CAD software from specifications: generating maze router tools in ELF
Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip
iCTS: Iterative and Hierarchical Clock Tree Synthesis With Skew-Latency-Load Tree
Placement for reliability and routability of convectively cooled PWBs
Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice
Reducing Structural Bias in Technology Mapping
Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation
On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches
A Clock Tree Prediction and Optimization Framework Using Generative Adversarial Learning
Full-Chip Power Density and Thermal Map Characterization for Commercial Microprocessors Under Heat Sink Cooling
Integrating Heuristic and Machine-Learning Methods for Efficient Virtual Machine Allocation in Data Centers
Timeless Discretization of Magnetization Slope in the Modeling of Ferromagnetic Hysteresis
Reuse-Based Optimization for Prebond and Post-Bond Testing of 3-D-Stacked ICs
ExTest Scheduling and Optimization for 2.5-D SoCs With Wrapped Tiles
A note on computing a maximal planar subgraph using PQ-trees
The complexity of the inclusion operation on OFDD's
SecureVolt: Enhancing Deep Neural Networks Security via Undervolting
Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations
Sparse Linear Regression (SPLINER) Approach for Efficient Multidimensional Uncertainty Quantification of High-Speed Circuits
Effective Logic Synthesis for Threshold Logic Circuit Design
Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking
Analytical Characterization of End-to-End Communication Delays With Logical Execution Time
On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits
Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application
IR-Drop Management in FPGAs
Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages
Multilayer pin assignment for macro cell circuits
Statistical Timing Analysis in the Presence of Signal-Integrity Effects
TSV Replacement and Shield Insertion for TSV-TSV Coupling Reduction in 3-D Global Placement
Synchronous emulation of asynchronous circuits
Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms
A circuit simulation model for bipolar-induced breakdown in MOSFET
Asymptotically Optimal Circuit Depth for Quantum State Preparation and General Unitary Synthesis
NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints
Redundancy removal for sequential circuits without reset states
Energy-Optimal Speed Control of a Generic Device
Recurrence in Dense-Time AMS Assertions
Integrating variable-latency components into high-level synthesis
New Synthesis of One-Dimensional 90/150 Linear Hybrid Group Cellular Automata
Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems
A hybrid methodology for switching activities estimation
Toward Predictive Fault Tolerance in a Core-Router System: Anomaly Detection Using Correlation-Based Time-Series Analysis
STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits
O(n 2 ) algorithms for graph planarization
Fair-ZNS: Enhancing Fairness in ZNS SSDs Through Self-Balancing I/O Scheduling
Technology Independent Device Modeling for Simulation of Integrated Circuits for FET Technologies
Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG
New and improved BIST diagnosis methods from combinatorial Group testing theory
Making the Most of Scarce Input Data in Deep Learning-Based Source Code Classification for Heterogeneous Device Mapping
A Routing Approach to Reduce Glitches in Low Power FPGAs
Nonuniform Multilevel Analog Routing With Matching Constraints
Cross-Layer Codesign for Secure Cyber-Physical Systems
Optimal placement of power-supply pads and pins
Design of mixed-signal systems-on-a-chip
INCAME: Interruptible CNN Accelerator for Multirobot Exploration
On-line and off-line testing with shared resources: a new BIST approach
Test-point insertion: scan paths through functional logic
Performance optimization by interacting netlist transformations andplacement