yusuke1997/dblp-id-title huggingface dataset:
A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme
Efficient use of time and hardware redundancy for concurrent error detection in a 32-bit VLSI adder
Unipolar Organic Transistor Circuits Made Robust by Dual-Gate Technology
Fully Automated Hardware-Driven Clock-Gating Architecture With Complete Clock Coverage for 4 nm Exynos Mobile SOC
Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects
A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro
A 10-MHz 2-800-mA 0.5-1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes
A 0.9-V microcontroller for portable applications
A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects
A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis
Analytical drain current models for AlGaAs/GaAs MODFET's including subthreshold conduction
A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS
A 2.5-V sigma-delta modulator for broadband communications applications
A Family of 32 nm IA Processors
A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers
An Efficient Piezoelectric Energy Harvesting Interface Circuit Using a Bias-Flip Rectifier and Shared Inductor
Electrothermal simulation of integrated circuits
A Fully Integrated Electrostatic Charge Boosting Rectifier for Triboelectric Energy Harvesting
A cost-effective three-step hierarchical search block-matching chip for motion estimation
A Fully Autonomous Integrated Interface Circuit for Piezoelectric Harvesters
An 18-MS/s 76-dB SNDR Continuous-Time Δ Σ Modulator Incorporating an Input Voltage Tracking GmC Loop Filter
Single-ended to differential converter for multiple-stage single-ended ring oscillators
Multi-Purpose Fully Differential 61- and 122-GHz Radar Transceivers for Scalable MIMO Sensor Platforms
Correction To "Physical Modeling Of Lateral Scaling In Bipolar Transistors"
A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24-30-GHz Sliding-IF 5G Transceivers
An Outphase-Interleaved Switched-Capacitor Hybrid Buck Converter With Relieved Capacitor Inrush Current and C OUT -Free Operations
An 8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique
A 0.79 pJ/K-Gate, 83% Efficient Unified Core and Voltage Regulator Architecture for Sub/Near-Threshold Operation in 130 nm CMOS
A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver
KOAN/ANAGRAM II: new tools for device-level analog placement and routing
An 11 mm 2 , 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12µm CMOS
Dependence of current match on back-gate bias in weakly inverted MOS transistors and its modeling
A Closed-Loop EMI Regulated GaN Power Converter With In Situ EMI Sensing and Global Excess-Spectrum Modulation
A Reconfigurable Dual-Output Switched-Capacitor DC-DC Regulator With Sub-Harmonic Adaptive-On-Time Control for Low-Power Applications
NeuroFlare: An mm 3 -Scale Wireless Neural Interface Device With Simultaneous Neural Recording and Optical Stimulation
Fault-tolerant architecture in a cache memory control LSI
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture
A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations
Replica compensated linear regulators for supply-regulated phase-locked loops
R, G, B acquisition interface with line-locked clock generator for flat panel display
A 4.6-pJ/b 200-Gb/s Analog DP-QPSK Coherent Optical Receiver in 28-nm CMOS
Design and implementation of a 5×5 trits multiplier in a quasi-adiabatic ternary CMOS logic
A 2-GHz, 6-mW BiCMOS frequency synthesizer
Design and Analysis of Energy-Efficient Reconfigurable Pre-Emphasis Voltage-Mode Transmitters
Two-dimensional magnetic microsensor with on-chip signal processing for contactless angle measurement
An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS
Analysis and prevention of DRAM latch-up during power-on
A 1 mJ/Frame Unified Media Application Processor With Dynamic Analog-Digital Mode Reconfiguration for Embedded 3D-Media Contents Processing
A Fully On-Chip 80-pJ/b OOK Super-Regenerative Receiver With Sensitivity-Data Rate Tradeoff Capability
Author's Reply to Comments on "A Robust Single Phase Clocking for Low Power, High-Speed VLSI Applica
A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit
Comparison of silicon bipolar and GaAlAs/GaAs heterojunction bipolar technologies using a propagation delay expression
A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS
Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference
A CMOS oversampling D/A converter with a current-mode semidigital reconstruction filter
A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory
A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces
A 0.5-W 64-kilobyte snoopy cache memory with pseudo two-port operation
Si bipolar 14 Gb/s 1: 4-demultiplexer IC for system applications
A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer
A 0.6-W 10-Gb/s SONET/SDH bit-error-rate monitoring LSI
A 6-GHz Continuous-Time Bandpass ΔΣ ADC With Background Filter Calibration and -100 dBc IM3 for a Mixer-Less DAB Band III Receiver
A CMOS temperature-compensated current reference
Capacitive Proximity Communication With Distributed Alignment Sensing for Origami Biomedical Implants
A 65-nm CMOS Fluorescence Sensor for Dynamic Monitoring of Living Cells
Introduction to the Special Section on the 2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting
Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs
A high-speed sample-and-hold technique using a Miller hold capacitance
Implementation of iterative networks with CMOS differential logic
Design and implementation of a CMOS VCXO for FM stereo decoders
A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface
A Sub-Picosecond Resolution 0.5-1.5 GHz Digital-to-Phase Converter
Corrections to "Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation"
A 1-V 0.25-µW Inverter Stacking Amplifier With 1.07 Noise Efficiency Factor
A leakage reduction methodology for distributed MTCMOS
An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update
Nonlinear Shaping SC Oscillator With Enhanced Linearity
Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors
An acoustic charge transport digitally programmable transversal filter
Yield and reliability of MNOS EEPROM products
A 1-GSample/s 10-b full Nyquist silicon bipolar Track&Hold IC
Introduction to the Special Bio-Section of the 2017 International Solid-State Circuits Conference (ISSCC)
Differential current-mode sensing for efficient on-chip global signaling
A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique
A 2.6-GByte/s multipurpose chip-to-chip interface
Cross Feedforward Cascode Compensation for Low-Power Three-Stage Amplifier With Large Capacitive Load
A 1.12 pJ/b Inductive Transceiver With a Fault-Tolerant Network Switch for Multi-Layer Wearable Body Area Network Applications
A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC
A 40-μA/channel compensated 18-channel strain gauge measurement system for stress monitoring in dental implants
A Distributed Stubs Technique to Mitigate Flicker Noise Upconversion in a mm-Wave Rotary Traveling-Wave Oscillator
A 12-b 5-Msample/s two-step CMOS A/D converter
A low-power half-delay-line fast skew-compensation circuit
A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's
An Event-Driven Quasi-Level-Crossing Delta Modulator Based on Residue Quantization
Minimum Energy Tracking Loop With Embedded DC-DC Converter Enabling Ultra-Low-Voltage Operation Down to 250 mV in 65 nm CMOS
A 2.5-V BiCMOS comparator with current-mode interpolation
A 10 bit 20 MS/s 3 V supply CMOS A/D converter
A Noise-Cancelling Receiver Front-End With Frequency Selective Input Matching
A 7.2 mW 75.3 dB SNDR 10 MHz BW CT Delta-Sigma Modulator Using Gm-C-Based Noise-Shaped Quantizer and Digital Integrator
A low-power multi-bit ΣΔ modulator in 90-nm digital CMOS without DEM
A Switchless, Q-Band Bidirectional Transceiver in 0.12-µm SiGe BiCMOS Technology
Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication
A Miniaturized Single-Transducer Implantable Pressure Sensor With Time-Multiplexed Ultrasonic Data and Power Links
A -121.5-dB THD Class-D Audio Amplifier With 49-dB LC Filter Nonlinearity Suppression
A 12-b, 30-MS/s, 2.95-mW Pipelined ADC Using Single-Stage Class-AB Amplifiers and Deterministic Background Calibration
The design of rotation-invariant pattern recognition using the silicon retina
A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS
A G-Band Four-Element Butler Matrix in 0.13 µm SiGe BiCMOS Technology
A Sub-mW 2.4-GHz Active-Mixer-Adopted Sub-Sampling PLL Achieving an FoM of -256 dB
A 24-GHz Transmitter With On-Chip Dipole Antenna in 0.13-µm CMOS
A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit
On-Chip Measurement of Deep Metastability in Synchronizers
GANGLION-a fast field-programmable gate array implementation of a connectionist classifier
A 300 MHz digital double-sideband to single-sideband converter in 1 μm CMOS
A Wideband Noise-Canceling CMOS LNA With Enhanced Linearity by Using Complementary nMOS and pMOS Configurations
A 320 MFLOPS CMOS floating-point processing unit for superscalar processors
A 160-MHz analog front-end IC for EPR-IV PRML magnetic storage read channels
A 2.5-3.125-Gb/s quad transceiver with second-order analog DLL-based CDRs
A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM
A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization
A High-Resolution Solid-State LiDAR Sensor With Reconfigurable Histogramming Time-to-Digital Converter and Filter for Depth Refinement
An MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers
A Wireless and Batteryless 10-Bit Implantable Blood Pressure Sensing Microsystem With Adaptive RF Powering for Real-Time Laboratory Mice Monitoring
A CMOS HDSL2 analog front-end
A 4 ns Settling Time FVF-Based Fast LDO Using Bandwidth Extension Techniques for HBM3
An X- and Ku-Band Wideband Recursive Receiver MMIC With Gain-Reuse
A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8× Time-Domain Latch Interpolation
A 0.018% THD+N, 88-dB PSRR PWM Class-D Amplifier for Direct Battery Hookup
A CMOS Temperature Stabilized 2-D Mechanical Stress Sensor With 11-bit Resolution
A 3.8-ns 16 K BiCMOS SRAM
A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements
A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion mode input stage
2-μm, 1.6-mW gated-g m sampler with 72-dB SFDR for f s =160 Ms/s and f in =320.25 MHz
dAJC: A 2.02-mW 50-Mb/s Direct Analog to MJPEG Converter for Video Sensor Nodes Using Switched Capacitor MAC-Quantizer With Process Calibration
A 4-Mb 0.18-μm 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers
A 2.2-V operation, 2.4-GHz single-chip GaAs MMIC transceiver for wireless applications
A 1/2.7-in 2.96 MPixel CMOS Image Sensor With Double CDS Architecture for Full High-Definition Camcorders
1 V power supply, low-power consumption A/D conversion technique with swing-suppression noise shaping
A single-chip programmable platform based on a multithreaded processor and configurable logic clusters
Post-fabrication clock-timing adjustment using genetic algorithms
A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter
High-Sensitivity, Low-Power IR-UWB Radar Transceiver With Self-Interference Resistance for Child Presence Detection and Precision Positioning
A 4-6.4 GHz LC PLL With Adaptive Bandwidth Control for a Forwarded Clock Link
Design on ESD protection scheme for IC with power-down-mode operation
A Broadband Four-Way Parallel-Series Doherty Power Amplifier for 5G Communications
A 600 µW BAW-Tuned Quadrature VCO Using Source Degenerated Coupling
Introduction to the Special Issue on the IEEE 2003 Custom Integrated Circuits Conference
An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling
Ultra-low-Voltage high-performance CMOS VCOs using transformer feedback
Analysis and Design of a CMOS E-Band Frequency Quadrupler With Transformer-Based Harmonic Reflectors
A CMOS model for computer-aided circuit analysis and design
Introduction to the Special Section on the 2014 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium
Current-mode algorithmic analog-to-digital converters
A first-order current-steering sigma-delta modulator
An 85 dB DR 4 MHz BW Pipelined Noise-Shaping SAR ADC With 1-2 MASH Structure
A 70-MHz 32-b microprocessor with 1.0- mu m BiCMOS macrocell library
Design and Analysis of a Low Loss, Wideband Digital Step Attenuator With Minimized Amplitude and Phase Variations
A Passive-Mixer-First Acoustic-Filtering Superheterodyne RF Front-End
A single-chip optical CMOS detector with in-situ demodulating and integrating readout for next-generation optical storage systems
A Charge-Sharing IIR Filter With Linear Interpolation and High Stopband Rejection
3-D Capacitive Interconnections for Wafer-Level and Die-Level Assembly
Design techniques for high-throughput BiCMOS self-timed SRAMs
Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array
A 3 V 10 MHz pseudo-differential SC bandpass filter using gain enhancement replica amplifier
A Four-Channel Bidirectional D-Band Phased-Array Transceiver for 200 Gb/s 6G Wireless Communications in a 130-nm BiCMOS Technology
New Invited Paper Series
A 65-nm CMOS Wideband TDD Front-End With Integrated T/R Switching via PA Re-Use
A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea of gates
A charge-based neural Hamming classifier
A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS
A 20-Gb/s CMOS multichannel transmitter and receiver chip set for ultra-high-resolution digital displays
Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs
A 440-μW, 109.8-dB DR, 106.5-dB SNDR Discrete-Time Zoom ADC With a 20-kHz BW
An 8 Gb/s-64 Mb/s, 2.3-4.2 mW/Gb/s Burst-Mode Transmitter in 90 nm CMOS
A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications
TensorCIM: Digital Computing-in-Memory Tensor Processor With Multichip-Module-Based Architecture for Beyond-NN Acceleration
EPU: An Energy-Efficient Explainable AI Accelerator With Sparsity-Free Computation and Heat Map Compression/Pruning
A monolithic +or-5 1/2-digit BiMOS A/D converter
A 28-nm 239-bp/μJ Agile Pangenome Analysis Accelerator for Multi-Scheme Read Mapping
Program load adaptive voltage generator for flash memories
Area- and Power-Efficient Monolithic Buck Converters With Pseudo-Type III Compensation
An integrated time-to-digital converter with 30-ps single-shot precision
An AMOLED Pixel Circuit With a Compensating Scheme for Variations in Subthreshold Slope and Threshold Voltage of Driving TFTs
A Monolithically Integrable Reconfigurable Antenna Based on Large-Area Electronics
A 28-GHz monolithic integrated quadrature oscillator in SiGe bipolar technology
A Power-Efficient Wireless System With Adaptive Supply Control for Deep Brain Stimulation
A monolithic Sigma Delta A/D and D/A converter with filter for broad-band speech coding
Simple accurate expressions for planar spiral inductances
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing"
A 5-b 10-GSample/s a/D converter for 10-gb/s optical receivers
Current-Mode Full-Duplex Transceiver for Lossy On-Chip Global Interconnects
A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators - Analysis, Design, and Measurement Techniques
A Novel Wide-Temperature-Range, 3.9 ppm/°C CMOS Bandgap Reference Circuit
A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19-Gb/s decision circuit using a 0.2-μm GaAs MESFET
A 20-MHz sixth-order BiCMOS parasitic-insensitive continuous-time filter and second-order equalizer optimized for disk-drive read channels
Asynchronous 250-Mb/s optical receivers with integrated detector in standard CMOS technology for optocoupler applications
Integrated circuits for particle physics experiments
A Single-Stage Bipolar-Output Regulating Rectifier With Negligible Cross-Regulation for Wireless Display
A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS
A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers
Optical I/O Technology for Tera-Scale Computing
A 30-ns cycle time 4-Mb mask ROM
A low-voltage low-power voltage reference based on subthreshold MOSFETs
A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation
A low-power CMOS nine-channel 40-MHz binary detection system with self-calibrated 500-μV offset
A CMOS multichannel IC for pulse timing measurements with 1-mV sensitivity
A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology
A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application
An injection-locking scheme for precision quadrature generation
A 60-Gb/s 1.2-pJ/bit 1/4-Rate PAM-4 Receiver With a Jitter Compensation CDR
A 0.92-THz SiGe Power Radiator Based on a Nonlinear Theory for Harmonic Generation
180-nm CMOS Wideband Capacitor-Free Inductively Coupled Power Receiver and Charger
CMOS resistive fuses for image smoothing and segmentation
A compact bipolar class-HB output stage using 1-V power supply
On the design of unilateral dual-loop feedback low-noise amplifiers with simultaneous noise, impedance, and IIP3 match
A Low-Power WCDMA Transmitter With an Integrated Notch Filter
A 65 nm 2-Billion Transistor Quad-Core Itanium Processor
Reply to Comments on "A sinh Resistor and Its Application to tanh Linearization"
An Analog-Proportional Digital-Integral Multiloop Digital LDO With PSR Improvement and LCO Reduction
A delay-encoding-logic array processor for dynamic-programming matching of data sequences
A 750 mV Fully Integrated Direct Conversion Receiver Front-End for GSM in 90-nm CMOS
A Fully Dynamic Event-Driven Capacitive Sensor Interface Circuits Based on Self-Reconfigurable SAR Capacitance-to-Digital Conversion for High-Density Robotic Tactile Sensing
A low-power 20-GHz 52-dBΩ transimpedance amplifier in 80-nm CMOS
An 11-b 100-MS/s Fully Dynamic Pipelined ADC Using a High-Linearity Dynamic Amplifier
A 56-mW 23-mm 2 single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm 2 radio
Modeling and sizing for minimum energy operation in subthreshold circuits
An integrated continuous-time bipolar transconductor-capacitor filter
A single-chip MPEG-2 codec based on customizable media embedded processor
Sub-nW Microcontroller With Dual-Mode Logic and Self-Startup for Battery-Indifferent Sensor Nodes
A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC
30-Msamples/s programmable filter processor
A 300-GHz 52-mW CMOS Receiver With On-Chip LO Generation
A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic
A single-chip CMOS transceiver for 802.11a/b/g wireless LANs
A wide-band 10-b 20 Ms/s pipelined ADC using current-mode signals
A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture
Design and evaluation of a high-precision, fully tunable OTA-C bandpass filter implemented in GaAs MESFET technology
Introduction to the Special Issue on the 2006 Asian Solid-State Circuits Conference (A-SSCC'06)
A CMOS dual-channel, 100-MHz to 1.1-GHz transmitter for cable applications
A New Transceiver Architecture for the 60-GHz Band
A 2-D Mode-Switching Quad-Core Oscillator Using E-M Mixed-Coupling Resonance Boosting
A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system
A 0.00055% THD + N Class-D Audio Amplifier With Capacitive Feedforward PWM and Wide-Band Aliasing Reduction
A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers
A Clock-Phase Reuse Technique for Discrete-Time Bandpass Filters
Understanding linearity in wireless communication amplifiers
An Energy-Efficient Embedded Deep Neural Network Processor for High Speed Visual Attention in Mobile Vision Recognition SoC
A 60-GHz 144-Element Phased-Array Transceiver for Backhaul Application
A gigasample/second 5-b ADC with on-chip track and hold based on an industrial 1 mu m GaAs MESFET E/D process
Special Section on the 47th IEEE European Solid-State Circuits Conference (ESSCIRC)
Switched-Mode Operational Amplifiers and Their Application to Continuous-Time Filters in Nanoscale CMOS
A low-power analog motion estimation processor for digital video coding
TESTCHIP: a chip for weighted random pattern generation, evaluation, and test control
A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers
A fully asynchronous low-power error corrector for the DCC player
A Rail-to-Rail 12 MS/s 91.3 dB SNDR 94.1 dB DR Two-Step SAR ADC With Integrated Input Buffer Using Predictive Level-Shifting
Integrated high frequency low-noise current-mode optical transimpedance preamplifiers: theory and practice
A 3.5-6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH ΔΣ-TDC for Low In-Band Phase Noise
An Ultra-Low-Voltage Bit-Interleaved Synthesizable 13T SRAM Circuit
An 18-34-GHz dynamic frequency divider based on 0.2- mu m AlGaAs/GaAs/AlGaAs quantum-well transistors
A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays
A 60-ns 16-Mbit DRAM with a minimized sensing delay caused by bit-line stray capacitance
A 24.7 mW 65 nm CMOS SAR-Assisted CT ΔΣ Modulator With Second-Order Noise Coupling Achieving 45 MHz Bandwidth and 75.3 dB SNDR
An Integrated Ultra-Wideband Timed Array Receiver in 0.13µm CMOS Using a Path-Sharing True Time Delay Architecture
A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth
Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO
A 1-Gb DRAM for file applications
A 150 MS/s 133 µW 7 bit ADC in 90 nm Digital CMOS
A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control
A Single-Chip Ultra-Wideband Receiver With Silicon Integrated Antennas for Inter-Chip Wireless Interconnection
1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer
An Interference-Resilient BLE-Compatible Wake-Up Receiver Employing Single-Die Multi-Channel FBAR-Based Filtering and a 4-D Wake-Up Signature
A multichannel digital demodulator for LVDT/RVDT position sensors
The mirrored lateral SCR (MILSCR) as an ESD protection structure: design and optimization using 2-D device simulation
A 15-bit Linear 20-MS/s Pipelined ADC Digitally Calibrated With Signal-Dependent Dithering
Guest Editorial Special Issue on the 47th European Solid-State Circuits Conference (ESSCIRC)
A Low-Power 26-GHz Transformer-Based Regulated Cascode SiGe BiCMOS Transimpedance Amplifier