yusuke1997/dblp-id-title huggingface dataset:
A Cellular Multiband DTC-Based Digital Polar Transmitter With -153-dBc/Hz Noise in 14-nm FinFET
A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications
A GaAs MESFET Schottky diode barrier height reference circuit
Modeling substrate effects in the design of high-speed Si-bipolar ICs
Metastability of CMOS latch/flip-flop
A Fully Integrated 384-Element, 16-Tile, $W$ -Band Phased Array With Self-Alignment and Self-Test
A 0.9-V 0.5-μA rail-to-rail CMOS operational amplifier
Systematic Transistor and Inductor Modeling for Millimeter-Wave Design
An Edge 3-D Gaussian Splatting Processor Based on Shape-Aware Computation Architecture and Spatio-Temporal Gaussian Cache
AlGaAs/GaAs HBT IC's for high-speed lightwave transmission systems
A 3.6 μ s Latency Asynchronous Frame-Free Event-Driven Dynamic-Vision-Sensor
A 286 mm 2 256 Mb DRAM with ×32 both-ends DQ
A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR
Analog phase measuring circuit for digital CMOS ICs
Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC)
A differential built-in current sensor design for high-speed IDDQ testing
A programmable mixed-signal ASIC for power metering
A 10-b 800-MS/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration
A 300-MHz CMOS voltage-controlled ring oscillator
Realization of a three-valued logic built-in testing structure
A V-Band 2-Gb/s 6.5-dBm Low-Power Transmitter in CMOS With On-Chip Antenna and Consumption Adaptivity Down to 700 nW
A 1.0-4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control
Analysis and Design of Commutation-Based Circulator-Receivers for Integrated Full-Duplex Wireless
A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology
An intelligent subprocessor for hardware emulation with 20-MOPS performance
Highly integrated direct conversion receiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic range continuous-time ΣΔ ADC
Power Reduction Techniques for LDPC Decoders
Implementation and Application of Harmonic Reset Switching in Passive Mixers
A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs
Low-Loss Heterogeneous Integrations With High Output Power Radar Applications at W-Band
ALSYN: flexible rule-based layout synthesis for analog IC's
A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-μm CMOS process
Radio frequency digital-to-analog converter
A high current drive CMOS output stage with a tunable quiescent current limiting circuit
A 256-Mb multilevel flash memory with 2-MB/s program rate for mass storage applications
Unbalanced Power Amplifier: An Architecture for Broadband Back-Off Efficiency Enhancement
A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC
A CMOS Flash LiDAR Sensor With In-Pixel Zoom Histogramming Time-to-Digital Converters
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique
A versatile 3.3/2.5/1.8-V CMOS I/O driver built in a 0.2-μm, 3.5-nm Tox, 1.8-V CMOS technology
Comments on "Analog layout using ALAS!" [and reply]
A Low-Power Fast-Transient 90-nm Low-Dropout Regulator With Multiple Small-Gain Stages
A CMOS analog-digital audio processor for a portable radiotelephone
The importance of the non-quasi-static bipolar transistor model for circuit applications
An Analog Neuromorphic On-Chip Training System With IGZO TFT-Based 6T1C Synaptic Memory
Fully differential operational amplifiers with accurate output balancing
An Inside Body Power and Bidirectional Data Transfer IC Module Pair
In-Memory Computation of a Machine-Learning Classifier in a Standard 6T SRAM Array
Regular VLSI architectures for multiplication modulo (2 n +1)
A 19-to-45 GHz High-Efficiency Frequency Doubler Using Multi-Port Darlington Cell With Fundamental and Second-Harmonic Pole-Stagger in 55-nm CMOS
A switched-capacitor delta-sigma modulator with reduced sensitivity to op-amp gain
A Reconfigurable Capacitive Power Converter With Capacitance Redistribution for Indoor Light-Powered Batteryless Internet-of-Things Devices
Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card
Comments on "On the Self-Generation of Electrical Soliton Pulses"
A 4.25-Gb/s CMOS fiber channel transceiver with asynchronous tree-type demultiplexer and frequency conversion architecture
A 160 × 120 Pixel Analog-Counting Single-Photon Imager With Time-Gating and Self-Referenced Column-Parallel A/D Conversion for Fluorescence Lifetime Imaging
Clock buffer chip with multiple target automatic skew compensation
A CMOS photodiode array with in-pixel data acquisition system for computed tomography
A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing
A low-noise, 900-MHz VCO in 0.6-μm CMOS
RF front-end of direct conversion receiver RFIC for cdma-2000
Integrated transversal equalizers in high-speed fiber-optic systems
A Polar Phase-Tracking Receiver With Two-Point Injection Technique
An Integrated-Circuit Node for High-Spatiotemporal Resolution Time-Domain Near-Infrared Diffuse Optical Tomography Imaging Arrays
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage
An intelligent power amplifier MMIC using a new adaptive bias control circuit for W-CDMA applications
A CMOS large-swing low-distortion three-stage class AB power amplifier
CMOS stuck-open fault testability
An 80-Gb/s 44-mW Wireline PAM4 Transmitter
A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time ΔΣ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 µm CMOS
The Speed-Power Trade-Off in the Design of CMOS True-Single-Phase-Clock Dividers
Bipolar Transistor Excess Phase Modeling in Verilog-A
A 1.76-GHz 22.6-mW ΔΣ fractional-n frequency synthesizer
Analog Circuit Blocks for 80-GHz Bandwidth Frequency-Interleaved, Linear, Large-Swing Front-Ends
A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications
A 2.5-GHz four-phase clock generator with scalable no-feedback-loop architecture
Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs
A 1770-µm 2 Leakage-Based Digital Temperature Sensor With Supply Sensitivity Suppression in 55-nm CMOS
An integrated CMOS time interval measurement system with subnanosecond resolution for the WA-98 calorimeter
A Cryo-CMOS 800-MS/s 7-bit Charge-Injection SAR ADC With Only 4-fF Input Capacitance and 64-dB SFDR in 40-nm Bulk CMOS
A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS
A charge recycle refresh for Gb-scale DRAM's in file applications
A Low-Power 70-100-GHz Mixer-First RX Leveraging Frequency-Translational Feedback
A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With >70 dB SFDR up to 500 MHz
An Embeddable Multilevel-Cell Solid Electrolyte Memory Array
A DC-DC converter for short-channel CMOS technologies
A BiCMOS continuous-time filter for video signal processing applications
A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique
High-Power 150/245-GHz Fundamental Oscillators With 12.1/-2.54-dBm Peak Output Power for Phased Array Transceivers
An Energy-Efficient, High-Resolution kT/C-Noise- Canceled Pipelined-SAR Capacitance-to-Digital Converter With Incomplete-Settling-Based Correlated Level Shifting in 22-nm CMOS
A Terahertz Detector Array in a SiGe HBT Technology
Introduction to the Special Section on the 2018 IEEE BCICTS Conference
A full Nyquist 15 MS/s 8-b differential switched-current A/D converter
A Multi-Band 16-52-GHz Transmit Phased Array Employing 4 × 1 Beamforming IC With 14-15.4-dBm P sat for 5G NR FR2 Operation
A capacitive sensing integrated circuit for detection of micromotor critical angles
A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC
CODEC for echo-canceling, full-rate ADSL modems
Implementation of scalable power and area efficient high-throughput Viterbi decoders
A 1.8-V 6/9-GHz reconfigurable dual-band quadrature LC VCO in SiGe BiCMOS technology
Optimum Conditions for Efficient Second-Harmonic Power Generation in mm-Wave Harmonic Oscillators
A 346 µm 2 VCO-Based, Reference-Free, Self-Timed Sensor Interface for Cubic-Millimeter Sensor Nodes in 28 nm CMOS
A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping
A 10-b Ternary SAR ADC With Quantization Time Information Utilization
Synthesis techniques for CMOS folded source-coupled logic circuits
A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization
250 W HVHBT Doherty With 57% WCDMA Efficiency Linearized to -55 dBc for 2c11 6.5 dB PAR
Active CMOS Array Sensor for Time-Resolved Fluorescence Detection
A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter With 24-GHz Wireless Power and LO Transfer
A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing
A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links
A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers
A 3.3 V 6-Bit 100 kS/s Current-Steering Digital-to-Analog Converter Using Organic P-Type Thin-Film Transistors on Glass
A 65-nm Proactive Power Management Technique With Real-Time Machine Learning Engine for Droop Prediction and Mitigation on Microprocessors
A 1.6 Gbyte/s data transfer rate 8 Mb embedded DRAM
A reconfigurable wafer-scale memory
The impact of intrinsic device fluctuations on CMOS SRAM cell stability
A 0.68-THz Receiver With Third-Order Subharmonic Mixing in 65-nm CMOS
A Wideband IM3 Cancellation Technique for CMOS Π- and T-Attenuators
A data-path multiplier with automatic insertion of pipeline stages
A Two-Stage 12-1-V Converter Featuring Regulated Resonant SC Regulators and Collaborative Control Scheme
A Biofuel-Cell-Based Energy Harvester With 86% Peak Efficiency and 0.25-V Minimum Input Voltage Using Source-Adaptive MPPT
A 60-GHz Transceiver and Baseband With Polarization MIMO in 28-nm CMOS
Analysis and design of HBT Cherry-Hooper amplifiers with emitter-follower feedback for optical communications
A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range
A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS
A Low-Power Process-Scalable Super-Heterodyne Receiver With Integrated High-Q Filters
A 20 dBm Fully-Integrated 60 GHz SiGe Power Amplifier With Automatic Level Control
Technique for Integration of a Wireless Switch in a 2.4 GHz Single Chip Radio
A 118-mW Pulse-Based Radar SoC in 55-nm CMOS for Non-Contact Human Vital Signs Detection
An 18-GHz continuous-time Σ-Δ analog-digital converter implemented in InP-transferred substrate HBT technology
A 2.5 ppm/°C 1.05-MHz Relaxation Oscillator With Dynamic Frequency-Error Compensation and Fast Start-Up Time
A full code-patterns coverage high-speed embedded ROM using dynamic virtual guardian technique
0.18-μm CMOS Bluetooth analog receiver with -88-dBm sensitivity
A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC
A 56-Gb/s 8-mW PAM4 CDR/DMUX With High Jitter Tolerance
A 45-ns 16-Mbit DRAM with triple-well structure
Direct Digital Synthesizer With Sine-Weighted DAC at 32-GHz Clock Frequency in InP DHBT Technology
A low-voltage switched-current delta-sigma modulator
A 14-bit 100-Msample/s subranging ADC
An experimental DRAM with a NAND-structured cell
A real-time digital VCR encode/decode and MPEG-2 decode LSI implemented on a dual-issue RISC processor
Improved bipolar transistor performance in CMOS by novel use of parasitic collector resistance
An independently matched parameter SPICE model for GaAs MESFET's
An energy-efficient reconfigurable public-key cryptography processor
A 37-43.5-GHz Phase and Amplitude Detection Circuit With 0.049° and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD
A Low Power 6-bit Flash ADC With Reference Voltage and Common-Mode Calibration
A low oversampling ratio 14-b 500-kHz ΔΣ ADC with a self-calibrated multibit DAC
A Four-Element 500-MHz 40-mW 6-bit ADC-Enabled Time-Domain Spatial Signal Processor
A 256×256 CMOS differential passive pixel imager with FPN reduction techniques
A 160 Channel QAM Modulator With 4.6 Gsps 14 Bit DAC
Crosstalk and transient analyses of high-speed interconnects and packages
A Nanosecond-Transient Fine-Grained Digital LDO With Multi-Step Switching Scheme and Asynchronous Adaptive Pipeline Control
A 60-ns 16-Mb flash EEPROM with program and erase sequence controller
Correction to "A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC" [Nov 10 2250-2261]
VBIC95, the vertical bipolar inter-company model
Designing interconnection buses in VLSI and WSI for maximum yield and minimum delay
Blocking and desensitization in RF amplifiers
A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation
A 1.76 mW, 355-fps, Electrical Impedance Tomography System With a Simple Time-to-Digital Impedance Readout for Fast Neonatal Lung Imaging
Characterization of RF power BJT and improvement of thermal stability with nonlinear base ballasting
An All-Digital, $V_{\mathrm{MAX}}$ -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop
A UWB CMOS transceiver
A 5.9-GHz voltage-controlled ring oscillator in 0.18-μm CMOS
Hybrid NRZ/Multi-Tone Serial Data Transceiver for Multi-Drop Memory Interfaces
A 3.2-GHz second-order delta-sigma modulator implemented in InP HBT technology
Analysis and Optimization of Current-Driven Passive Mixers in Narrowband Direct-Conversion Receivers
A 2.71 nJ/Pixel Gaze-Activated Object Recognition System for Low-Power Mobile Smart Glasses
A Compact, Low-Power 40-GBit/s Modulator Driver With 6-V Differential Output Swing in 0.25- μ m SiGe BiCMOS
A 0.58-mm 2 2.76-Gb/s 79.8-pJ/b 256-QAM Message-Passing Detector for a 128 × 32 Massive MIMO Uplink System
A Capacitively Degenerated 100-dB Linear 20-150 MS/s Dynamic Amplifier
Robust SRAM Design via BIST-Assisted Timing-Tracking (BATT)
Temperature-compensation circuit techniques for high-density CMOS DRAMs
High power-added efficiency MMIC amplifier for 2.4 GHz wireless communications
Cut-and-paste customization of organic FET integrated circuit and its application to electronic artificial skin
0.5 V Start-Up 87% Efficiency 0.75 mm 2 On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration
A mm-Precise 60 GHz Transmitter in 40 nm CMOS for Discrete-Carrier Indoor Localization
Testing of a NORA CMOS serial-parallel multiplier
An architecture for electrically configurable gate arrays
An Edge Missing Compensator for Fast Settling Wide Locking Range Phase-Locked Loops
Design and implementation of an embedded 512-KB level-2 cache subsystem
Analysis and Design of a High Speed Continuous-time ΔΣ Modulator Using the Assisted Opamp Technique
Design and Analysis of a 90 nm mm-Wave Oscillator Using Inductive-Division LC Tank
High Efficiency D-Band Multiway Power Combined Amplifiers With 17.5-19-dBm Psat and 14.2-12.1% Peak PAE in 45-nm CMOS RFSOI
A 60-GHz CMOS receiver front-end
A 5-GHz 108-Mb/s 2 $\times$2 MIMO Transceiver RFIC With Fully Integrated 20.5-dBm ${\rm P}_{\rm 1dB}$ Power Amplifiers in 90-nm CMOS
Simple Statistical Analysis Techniques to Determine Optimum Sense Amp Set Times
A six-port 30-GB/s nonblocking router component using point-to-point simultaneous bidirectional signaling for high-bandwidth interconnects
A 12 bit 160 MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-Domain Proximity Detector
An Ultra-Low-Voltage 2.4-GHz Flicker-Noise-Free RF Receiver Front End Based on Switched-Capacitor Hybrid TIA With 4.5-dB NF and 11.5-dBm OIP3
Dynamic asynchronous logic for high-speed CMOS systems
CMOS monolithic mechatronic microsystem for surface imaging and force response studies
A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications
A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars
A Quantization Error Minimization Method Using DDS-DAC for Wideband Fractional-N Frequency Synthesizer
Dynamic Focusing of Large Arrays for Wireless Power Transfer and Beyond
Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier With Capacitor Reuse for Input Power Adaptation
A Self-Gating RF Energy Harvester for Wireless Power Transfer With High-PAPR Incident Waveform
An efficient charge recovery logic circuit
Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits
Current-temperature feedback effects in III-V heterojunction bipolar transistors
A Low-Power Dual-Frequency SIMO Buck Converter Topology With Fully-Integrated Outputs and Fast Dynamic Operation in 45 nm CMOS
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links
A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology
A 12 GHz 1.9 W Direct Digital Synthesizer MMIC Implemented in 0.18 µm SiGe BiCMOS Technology
An 88% Efficiency 0.1-300-µW Energy Harvesting System With 3-D MPPT Using Switch Width Modulation for IoT Smart Nodes
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS
An Isolated DC-DC Converter With Full-Duplex Communication Using a Single Pair of Transformers
Phase-Scalable CF-Cross-Connected-Based Hybrid DC-DC Converter With Auto VCF Balancing and Inactive CF Charging
Full-swing Schottky BiCMOS/BiNMOS and the effects of operating frequency and supply voltage scaling
A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme
A Fully-Integrated 71 nW CMOS Temperature Sensor for Low Power Wireless Sensor Nodes
A 1.12-1.91 mW/GHz 2.46-4.92 GHz Cascaded Clock Multiplier in 65 nm CMOS
A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme
A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna
SPARC64: a 64-b 64-active-instruction out-of-order-execution MCM processor
A 121.4-dB DR Capacitively Coupled Chopper Class-D Audio Amplifier
A 256 × 192 -Pixel Direct Time-of-Flight LiDAR Receiver With a Current-Integrating-Based AFE Supporting 240-m-Range Imaging
Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications
A Spectral-Scanning Nuclear Magnetic Resonance Imaging (MRI) Transceiver
SACHEM, a versatile DMT-based modem transceiver for ADSL
Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation"
A 225-μW Interference-Tolerant Receiver With Shared Wireless LO and Envelope-Tracking Mixer Achieving -104-dBm Sensitivity
A time-interleaved continuous-time ΔΣ modulator with 20-MHz signal bandwidth
A temperature sensor with single resistor set-point programming
An energy/security scalable encryption processor using an embedded variable voltage DC/DC converter
A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery
Jussi Ryynänen Introduction to the December Special Issue on the 2015 IEEE International Solid-State Circuits Conference
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration
Series-parallel association of FET's for high gain and high frequency applications
An easy-to-use mismatch model for the MOS transistor
A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing
Low-power CMOS digital design with dual embedded adaptive power supplies
A low-power 256-Mb SDRAM with an on-chip thermometer and biased reference line sensing scheme
A 77 GHz Frequency Doubling Two-Path Phased-Array FMCW Transceiver for Automotive Radar
Active Terahertz Imaging Using Schottky Diodes in CMOS: Array and 860-GHz Pixel
A high-speed multimodulus HBT prescaler for frequency synthesizer applications
An eighth-order bandpass ΔΣ modulator for A/D conversion in digital radio
A 1.8-V 22-mW 10-bit 30-MS/s Pipelined CMOS ADC for Low-Power Subsampling Applications
A 4-MHz CMOS continuous-time filter with on-chip automatic tuning
TranCIM: Full-Digital Bitline-Transpose CIM-based Sparse Transformer Accelerator With Pipeline/Parallel Reconfigurable Modes
A 12-b 1-GS/s 31.5-mW Time-Interleaved SAR ADC With Analog HPF-Assisted Skew Calibration and Randomly Sampling Reference ADC
A 3-V, 6-Bit C-2C Digital-to-Analog Converter Using Complementary Organic Thin-Film Transistors on Glass
A 0.4W-to-21W Fast-Transient Global-Search-Algorithm Based Integrated Photovoltaic Energy Harvester With 99% GMPPT Efficiency and 94% Power Efficiency
Comments on "A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth"
L/S-band 140-W push-pull power AlGaAs/GaAs HFET's for digital cellular base stations
A new DLL-based approach for all-digital multiphase clock generation
Current Reference Pre-Charging Techniques for Low-Power Zero-Crossing Pipeline-SAR ADCs
1-V Rail-to-Rail CMOS OpAmp With Improved Bulk-Driven Input Stage
A 22-bit Read-Out IC With 7-ppm INL and Sub-100-µHz 1/ f Corner for DC Measurement Systems
On the relationship between the CMRR or PSRR and the second harmonic distortion of differential input amplifiers
A 60 GHz Frequency Generator Based on a 20 GHz Oscillator and an Implicit Multiplier
A three-dimensional neural recording microsystem with implantable data compression circuitry
A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique
An Assessment of µ-Czochralski, Single-Grain Silicon Thin-Film Transistor Technology for Large-Area, Sensor and 3-D Electronic Integration
A Radiation-Hardened 15-22-GHz Frequency Synthesizer in 22-nm FinFET
A 0.1- mu A standby current, ground-bounce-immune 1-Mbit CMOS SRAM
A 14-bit 80-kHz sigma-delta A/D converter: modeling, design and performance evaluation
How to Keep Pushing ML Accelerator Performance? Know Your Rooflines!
Dynamically Adaptable Pipeline for Energy-Efficient Microarchitectures Under Wide Voltage Scaling
Injection-Locked Wideband FM Demodulation at IF
A Time-Domain-Controlled Current-Mode Buck Converter With Wide Output Voltage Range
A 2-Gb/s UWB Transceiver for Short-Range Reconfigurable FDD Wireless Networks
An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip
570-ps 13-mW Josephson 1-kbit NDRO RAM
A Broadband Low-Power Low-Noise Active Balun With Second-Order Distortion Cancellation
A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC
Ultrahigh-speed HEMT LSI technology for supercomputer
A High-Power and Scalable 2-D Phased Array for Terahertz CMOS Integrated Systems
An active charge cancellation system for switched-capacitor sensor interface circuits
Quaternary logic circuits in 2- mu m CMOS technology
A Fully Dynamic Multi-Mode CMOS Vision Sensor With Mixed-Signal Cooperative Motion Sensing and Object Segmentation for Adaptive Edge Computing
A 0.5-V 5.2-fJ/Conversion-Step Full Asynchronous SAR ADC With Leakage Power Reduction Down to 650 pW by Boosted Self-Power Gating in 40-nm CMOS
Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 V supply voltage regime
ULPAC: A Miniaturized Ultralow-Power Atomic Clock
High-Power Radiation at 1 THz in Silicon: A Fully Scalable Array Using a Multi-Functional Radiating Mesh Structure