yusuke1997/dblp-id-title huggingface dataset:
Directional Feature Field and Parallel Operations for Binary Images: Twisting Operation for Arbitrary Directional Propagation by 8-Neighbors
Extraction of the symmetric pairs of contour points as well as the medial axis from a planar figure by a method based on plane division
Built - in concurrent testing for semiconductor random access memories by concurrently testing cells on a word-line
A parallel branch-and-bound algorithm for integer linear programming and its implementation on a distributed multiprocessor
Handprinted numerals recognition by learning distance function
Automated extraction of cancer lesions with convergent fold patterns in double contrast x-ray images of the stomach
Development of virtual learning environment for discovery learning in school education
A comparison of color coordinate systems using color classification and image segmentation results of humans
A lossless coding scheme using adaptive predictors and arithmetic code optimized for each image
An object-oriented data model for multiple representation of object semantics
Compilation of dictionaries for semantic attribute analysis of television news captions
High-speed line detection method using hough transform in local area
Layered blind deconvolution with interband prediction
3-D object recognition and description: A method for the visually impaired using an invisible bar code
Optimum image restoration filters and generalized inverses of operators
Rendering intricately-shaped objects using view-dependent microfacets
A model of overt visual attention based on scale-space theory
A model of complex cell development by information separation
Speech recognition using hidden Markov models based on segmental statistics
A method for automatic generation of caricatured profile in PICASSO system
Automatic segmentation of liver region based on extracted blood vessels
Recognition of Coronary Arterial Stenosis Using Neural Network on DSA System
Instruction fetch and dispatch scheme with flag-in-cache/in-IBR
Efficient event communication algorithm and its evaluation for parallel logic simulation
Automatic closed-caption production system on TV programs for hearing-impaired people
Extraction of minimal decision algorithm using rough sets and genetic algorithm
Development of 3D graphics and VRML libraries for Web3D platform by using Java
Plan reuse in cooperative, distributed problem-solving
Effects of neuronal dynamics on memory storing in stimulus-response scheme model
Human reader: An advanced man-machine interface based on human images and speech
Characteristics measurement for three-dimensional surfaces based on multiple filtering
Equivalence of real-time DPDAs and discrete extended simple recurrent networks with some restrictions
Concept and construction of an interactive movie system
Restoration of degraded images with neural networks
A realtime model-based facial image synthesis based on multiprocessor network
Corner Detection and Curve Representation Using Cubic B-Splines
Children's speech recognition using elementary-school-student speech database
Image processing for computer-aided diagnosis of lung cancer by CT (LSCT)
Message routing latency-minimizing method in an ASIC design for distributed cooperative communication protocol processing
Edge surface detection with subvoxel accuracy from 3-d images
Keyframe animation of virtual humans via motion data learning
A family of projection learnings
Development of a PC-based real-time surgical simulator
RAMP: Research Accelerator for Multiple Processors
The MOD Keyboard
Inspection-Resistant Memory Architectures
Automatic Extraction of Coarse-Grained Data-Flow Threads from Imperative Programs
Hot Chips 33 and More!
Dedicated tools for microprocessor education
The antitrust ghost in the standard-setting machine
Microprocessor at 50: Looking Back and Looking Forward
Real-Time Computing And the Engineering Support System
Predicting Voltage Droops Using Recurring Program and Microarchitectural Event Activity
Parallelizing Sequential Code
Agile Hardware Development and Instrumentation With PyRTL
Analog VLSI synaptic matrices as building blocks for neural networks
Exploring Memory-Oriented Design Optimization of Edge AI Hardware for Extended Reality Applications
The GeForce 6800
Cryptography Efficient Permutation Instructions for Fast Software
A Brief History of Warehouse-Scale Computing
EasyRide: Active Transponders for a Fare Collection System
A Distributed System for Real-Time Applications
AMD Next-Generation "Zen 4" Core and 4th Gen AMD EPYC Server CPUs
Superscalar instruction execution in the 21164 Alpha microprocessor
Introducing Tobus: the system bus in the TRON architecture
The Fox and Shepherd Problem
Architecting Efficient Interconnects for Large Caches with CACTI 6.0
Leveraging Cache Management Hardware for Practical Defense Against Cache Timing Channel Attacks
Guest Editors' Introduction: Hot Chips 13
Image Recognition Accelerator Design Using In-Memory Processing
A Review of Wisconsin Alumni Research Foundation v. Apple - Part III
An Honest Policy Wonk
On Double Full-Stack Communication-Enabled Architectures for Multicore Quantum Computers
A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets
Imitation happens
Dark Silicon and Dangerous Predictions
The Open Internet Order
Performance-Directed Energy Management for Storage Systems
RTX on - The NVIDIA Turing GPU
Microprocessor at 50: A Time to Celebrate and Energize for the Future
Java security: present and near future
Fermi GF100 GPU Architecture
Practical Multidimensional Branch Prediction
Andy's acceleration and Moore's momentum
Limited bandwidth to affect processor design
Pattern-addressable memory
Reliability: Fallacy or Reality?
Special Issue on Hot Chips 2023
A Case for Specialized Processors for Scale-Out Workloads
Comprex: In-Network Compression for Accelerating IoT Analytics at Scale
Characterizing and Modeling Nonvolatile Memory Systems
Synchronization through Communication in a Massively Parallel Processor Array
A Cluster-Based Active Router Architecture
Voice Processors Based on the Human Hearing System
NetDistiller: Empowering Tiny Deep Learning via In Situ Distillation
Guest Editor's Introduction: Making Computers Invisible
Addressing the Gap Between Training Data and Deployed Environment by On-Device Learning
Building the virtual world
The Design Process for Google's Training Chips: TPUv2 and TPUv3
Synchronous, Low-Latency, Off-Module Interface for the IBM z16 Telum Processor
MicroStandards
Instruction Set Innovations for the Convey HC-1 Computer
An overview of the BTRON/286 specification
Spatial Sampling and Regression Strategies
Quantifying CO 2 Emission Reduction Through Spatial Partitioning in Deep Learning Recommendation System Workloads
Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches
Monza: An Energy-Minimal, General-Purpose Dataflow System-on-Chip for the Internet of Things
CHOP: Integrating DRAM Caches for CMP Server Platforms
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies - Part II: Prosecution Time and Effective Patent Term Length
Dynamically changing the logical behavior of the microcomputer interface
Optimizing Distributed DNN Training Using CPUs and BlueField-2 DPUs
The Hush-Hush Norm
An Implementable Parallel Scheduler for Input-Queued Switches
An All-Programmable 16-nm RFSoC for Digital-RF Communications
Sipping Matcha of Security: A Fireside Chat With Mengjia Yan
The drive to the year 2000
Microelectronics in mobile communications: a key enabler
Unbiased Quantized Congestion Notification for Scalable Server Fabrics
Effective Communication [review of ".....Trees, Maps, and Theorems: Effective Commuincation for Rational Minds" (Doumont, J.-L.; 2009)]
Effective Mimicry of Bélády's MIN Policy
Innovation or Notoriety?
A High-Speed Optical Multidrop Bus for Computer Interconnections
Designing for Discovery
SH3: high code density, low power
A Comparative Analysis of Loosely and Tightly Coupled Accelerator Architectures for Machine Learning
Hardware Security and Privacy: Threats and Opportunities
Court Dismisses "Copyright Champion's" Source Code Copyright Suit
Susan Eggers Receives Eckert-Mauchly Award for Outstanding Contributions to Computer Architecture
Routing Table Compaction in Ternary CAM
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies - Part VII: Relationship Between Prosecution Time and Claims
Resource Management on Multicore Systems: The ACTORS Approach
The Worlds I See: Curiosity, Exploration, and the Discovery at the Dawn of AI - Fei-Fei Li (New York, NY, USA: Flatiron Books, 2023, 336 pp.)
Voting and Economic Asymmetry
Improving the reliability and safety of automotive electronics
Entertainment and Edutainment
Spearmints: hardware support for performance measurements in distributed systems
A 160 Mpixel/s IDCT processor for HDTV
Acceleration of a Classic McEliece Postquantum Cryptosystem With Cache Processing
Uncovering the Security Implications of Cloud Multi-Tenancy with Bolt
High-Speed Packet Processing using Reconfigurable Computing
Advances in DRAM interfaces
Distributed Brain-Computer Interfacing With a Networked Multiaccelerator Architecture
Environment for PowerPC microarchitecture exploration
Toward Quantum Computation: A Five-Qubit Quantum Processor
Efficient Sampling Startup for SimPoint
PRO3: A Hybrid NPU Architecture
The HM-Nucleus: Distributed Kernel Design for the Homogeneous Multiprocessor
Practical and Scalable ML-Driven Cloud Performance Debugging With Sage
The SARC Architecture
The 2014 MICRO Test of Time Award Winners: From 1978 to 1992
Processor integration in a disk controller
AMD 3DNow! technology: architecture and implementations
The Stanford Hydra CMP
Vector Runahead for Indirect Memory Accesses
Can Software Be Tied to Hardware? Part I
Measuring the impact of microarchitectural ideas
An Advanced-Architectur CMOS/SOS Microprocessor
Antitrust Division Gives IEEE Standard Setters the Okay to Ask Patentees How RAND They Are
Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications
Adaptive Power Capping for Servers with Multithreaded Workloads
iWarp: a 100-MOPS, LIW microprocessor for multicomputers
Creative Destruction and Deconstruction
Strategic Pivot of Long-Standing x86 Rivals
IBM's Deep Blue Chess grandmaster chips
An Improved Model for a Microcomputer Component-The 6520 PIA
Hot chips and soggy software
VLSI technologies for artificial neural networks
Simultaneous and Heterogenous Multithreading: Exploiting Simultaneous and Heterogeneous Parallelism in Accelerator-Rich Architectures
Twin Datacenter Interconnection Topology
Architecting Storage for the Cloud Computing Era
The Gmicro/100 32-bit microprocessor
Configuration of the CTRON* Kernel
Pinnacle: IBM MXT in a Memory Controller Chip
Parallelization Strategies for DLRM Embedding Bag Operator on AMD CPUs
High performance RISC microprocessors
Hot Chips 34 and More!
RASSA: Resistive Prealignment Accelerator for Approximate DNA Long Read Mapping
Exploiting Interposer Technologies to Disintegrate and Reintegrate Multicore Processors
Hyperthreading Technology in the Netburst Microarchitecture
Accelerating Finite Field Arithmetic for Homomorphic Encryption on GPUs
Power4 System Design for High Reliability
Decoupled Compressed Cache: Exploiting Spatial Locality for Energy Optimization
IEEE Standards Development
What Does a Skunk Works Do?
Measuring What Matters: A Fireside Chat With Joel Emer
AMD XDNA NPU in Ryzen AI Processors
ISOBlue Avena: A Framework for Agricultural Edge Computing and Data Sovereignty
Reducing Transistor Variability for High Performance Low Power Chips
A Hardware-Accelerated System for Real-Time Worm Detection
Two Billion Devices and Counting
Medical Ultrasound Imaging: To GPU or Not to GPU?
Quality-of-Service-Aware Scheduling in Heterogeneous Data centers with Paragon
New Tools
Big Data [Guest editors' introduction]
FTC cracks down on spyware and PC hijacking, but not true lies
Presilicon modeling: challenges in the late CMOS era
A 16-Kbit Θ-search associative memory
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies - Part IX: Patent Families
The Combined Input-Output Queued Crossbar Architecture for High-Radix On-Chip Switches
A versatile ring-connected hypercube
Gordon: An Improved Architecture for Data-Intensive Applications
High-Performance Mixed-Low-Precision CNN Inference Accelerator on FPGA
Alphorn: a remote procedure call environment for fault-tolerant, heterogeneous, distributed systems
The Origin of Intel's Micro-Ops
Performance and Energy Implications of Many-Core Caches for Throughput Computing
Itanium 2 Processor Microarchitecture
Motivation for and Evaluation of the First Tensor Processing Unit
Prosecuting your patent
Hexagon DSP: An Architecture Optimized for Mobile Multimedia and Communications
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors
Formal Control Techniques for Power-Performance Management
Disaggregated Designs: Technology Challenges and Enablers
Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation
Realizing the V80 and its system support functions
Guest Editors' Introduction: On-Chip Interconnects for Multicores
A cost-effective RISC/DSP microprocessor for embedded systems
The Micon system for computer design
Hardware-software interactions on Mpact
Accelerating Critical Section Execution with Asymmetric Multicore Architectures
An Architecture for Analysis
Data Centers on Wheels: Emissions From Computing Onboard Autonomous Vehicles
ExHero: Execution History-Aware Error-Rate Estimation in Pipelined Designs
A 32-Bit, 200-MHz GaAs RISC for High-Throughput Signal Processing Environments
Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture
Guest Editors' Introduction: Datacenter-Scale Computing
Micro News
Cost-Sensitive Partitioning in an Architecture Synthesis System for Multicluster Processors
A Signal Processing Implementation for an IBM-PC-based Workstation
From TeAAL to FuseMax: Separation of Concerns for Attention Accelerator Design
PUNCH: Web Portal for Running Tools
Improved Control Acquisition Scheme for the IEEE 896 Futurebus
Special Issue on Cool Chips
Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor
Enhancing Model Parallelism in Neural Architecture Search for Multidevice System
IBM Power Edge of Network Processor: A Wire-Speed System on a Chip
IEEE Preventing Abuse of IEEE Standards Policy
Research Agenda: Spacetime Computation and the Neocortex
Unresolved Legal Questions about Patents and Standard Setting
Introduction to the Clipper Architecture
Last Chance: The Motorola Microprocessor Story
Fast Updating Algorithms for TCAMs
Distributed fault-tolerant real-time systems: the Mars approach
CXL-Enabled Enhanced Memory Functions
Distributed Deep Learning With GPU-FPGA Heterogeneous Computing
Hardware Architecture Considerations in the WE32100 Chip Set
Composable Building Blocks to Open Up Processor Design
A Case for Accelerating Software RTL Simulation
The μVP 64-bit vector coprocessor: a new implementation of high-performance numerical computation
Microprocessor at 50: Industry Leaders Speak
The Undergraduate Curriculum in Computer Architecture
Patenting software, revisited
Ties that bind: foreseeing foreclosure
Level-Independent Notation for Microcomputer Programs
A RISC processor for embedded applications within an ASIC
Computer Buses a Tutorial
Industrial economics and strategy: computing platforms
The 68040 processor. 2. Memory design and chip
Licensing IP embodied in standards
Evolutionary Benchmark Subsetting
The Broadband Revolution
Virtual Memory and the MC68010
AIDA: Associative In-Memory Deep Learning Accelerator
MMX technology extension to the Intel architecture
The AT&T WE32200 design challenge
Helper Threads via Virtual Multithreading
The Basics of Performance-Monitoring Hardware
Value-Based Deep-Learning Acceleration
In-Hardware Moving Compute to Data Model to Accelerate Thread Synchronization on Large Multicores
A Collaborative IP-Development Session
A Microcomputer-Based Laboratory Aid for Visually Impaired Students
Building Broadband as Economic Stimulus
NP-Click: A Productive Software Development Approach for Network Processors
Multiprocessors from a software perspective
TinyIREE: An ML Execution Environment for Embedded Systems From Compilation to Deployment
AMBA: enabling reusable on-chip designs
EMMA2: a high-performance hierarchical multiprocessor
COOL-NPU: Complementary Online Learning Neural Processing Unit
The Mips R4000 processor
Wearable Computing: One man's mission
A codesign approach for safety-critical automotive applications
What Kinds of Computer-Software-Related Advances (if Any) Are Eligible for Patents? Part II: The "Useful Arts" Requirement
Micro Review
New Blood, Cool Chips, and Heterogeneous Designs
MicroLaw
An ASIC methodology for mixed analog-digital simulation
Workload Reduction and Generation Techniques
High performance at affordable power
Implementation of the V60/V70 and its FRM function
Analog Neural Networks With Deep-Submicrometer Nonlinear Synapses
SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback
Attaining Single-Chip, High-Performance Computing through 3D Systems with Active Cooling
Introducing the IA-64 Architecture
No Rosetta Stone for Market Vitality
An analog VLSI implementation of Hopfield's neural network
Design Space Exploration for Real-Time Embedded Stream Processors
Guest Editors' Introduction: Top Picks from the Computer Architecture Conferences of 2007
3D Stacked Microprocessor: Are We There Yet?
The European Declarative System, database, and languages
Thinking about history and design
SP-CNN: A Scalable and Programmable CNN-Based Accelerator
The development of ATM standards and technology: a retrospective
Rethinking Digital Design: Why Design Must Change
Creating documents [book and software package review]
A case for intelligent RAM
Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences
Two-chip MPEG-2 video encoder
MicroReview
Desires And Aspirations of the Engineering Support System User
The Case for Embedded Networks on Chip on Field-Programmable Gate Arrays
Dynamic Architecture and LSI Modular Computer Systems
FuriosaAI RNGD: A Tensor Contraction Processor for Sustainable AI Computing
Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor
Sequence Controllers with Standard Hardware and Custom Firmware
Events And Interrupts in Tightly Coupled Multiprocessors
The Movidius Myriad Architecture's Potential for Scientific Computing
How to Write a Universal Cross-Assembler
picoJava-I: the Java virtual machine in hardware
CSIDC: Competing Students Design Real-World Systems
Memory, Memristors, and Atomristors
Cell Processor Low-Power Design Methodology
An Architectural Comparison of Contemporary 16-Bit Microprocessors
Cool Chips III
Achieving One Billion Key-Value Requests per Second on a Single Server
The Secret Life of Wally Madhavani
Lunar Lake an Intel Mobile Processor: SoC Architecture Overview (2024)
Fun and games and microcomputer interfacing [laboratory exercises]
IBM's S/390 G5 microprocessor design
Server Architecture From Enterprise to Post-Moore
Architectures for Bit-Split String Scanning in Intrusion Detection
XCRYPT: Accelerating Lattice-Based Cryptography With Memristor Crossbar Arrays
The iFlow Address Processor
Connectivity - More Needed Than Ever Before
IA-32 Processor with a Wide-Voltage-Operating Range in 32-nm CMOS
PCs, the Internet, and You
A Performance Study of 16-bit Microcomputer-Implemented FFT Algorithms
Introducing the FR500 Embedded Microprocessor
Near-Data Processing: Insights from a MICRO-46 Workshop
A General Heap Processor
Vicarious liability for infringement
Walking through the Energy-Error Pareto Frontier of Approximate Multipliers
Avoiding surprises: some thoughts on standards
Guest Editors' Introduction: Fault-Tolerant Embedded Systems
Patenting signals
Enough Variety and Diversity?
Back-End-of-Line Compatible Transistors for Monolithic 3-D Integration
Gatekeeping Economics
The AM 3 associative processor
Microdisplay Applications Reach the Mainstream
The Intel 80386 - Architecture And Implementation
Distributed Discretion by the Slice
Reshaping Future Computing Systems With Emerging Nonvolatile Memory Technologies
Energy Awareness and Uncertainty in Microarchitecture-Level Design
Microprocessors, Microcontrollers, and Systems in the New Millennium
An analog systolic neural processing architecture
A retinomorphic vision system
The Proposed IEEE 896 Futurebus - A Solution to the Bus Driving Problem
The biology of technology
Context (Micro Review)
Differentiated Platforms
A New Golden Age in Computer Architecture: Empowering the Machine-Learning Revolution
Interactions, Impacts, and Coincidences of the First Golden Age of Computer Architecture
Micro standards: IEEE std P1394
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies - Part III: Claims
Pervasive Technologies (Micro Review)
AOL: essential for sending junk e-mail?
RowPress Vulnerability in Modern DRAM Chips
Sparc T4: A Dynamically Threaded Server-on-a-Chip
MOSIS eyes the future
An Integrated Environment for Teaching Computer Architecture
Intelligence for Sale
Performance Left on the Table: An Evaluation of Compiler Autovectorization for RISC-V
The M5 Simulator: Modeling Networked Systems
Micro standards-organizing the corporate standards function
Digital Filter Implementation on 16-Bit Microcomputers
Communication versus Computation
Programming Strategies In the Game of Push-Over
Power Consumption Modeling and Characterization of the TI C6201
Commercial and Scientific Prototypes
Designing and implementing a fast crossbar scheduler
In Search of Perfect Computing (EIC Message)
Energy-Efficient Network Memory for Ubiquitous Devices
Parallel Block Vectors: Collection, Analysis, and Uses
Explorers and expanders, both early and late
Cryptographic smart cards
Two fast and high-associativity cache schemes
A back door to protecting look and feel? [micro law]
Memristor-Based Computing
Long-Term Workload Phases: Duration Predictions and Applications to DVFS
Does Academic Research Drive Industrial Innovation in Computer Architecture? - Analyzing Citations to Academic Papers in Patents
Flexible control for robot manipulators
Designing microprocessors with robust functionality and performance
Data Format and Bus Compatibility in Multiprocessors
The State of the Computer Architecture Field and Its Top Picks
Write Deduplication and Hash Mode Encryption for Secure Nonvolatile Main Memory
A configurable, virtual microprocessor system for instructional use in real-time, real-world studies
Ti-States: Power Management in Active Timing Margin Processors
An Architecture to Accelerate Computation on Encrypted Data
LiveHD: A Productive Live Hardware Development Flow
A general-purpose fuzzy inference processor
CPUs and GPUs: Who Owns the Future?
The IEC/IEEE Train Communication Network
Special Issue on Cache Coherent Interconnects and Resource Disaggregation Techniques
Texture Caches
Update on the antitrust ghost in the standard-setting machine
Byte-Wise CRC Calculations
Machine Learning Accelerators and More
A Single-Chip Multiprocessor for Smart Terminals
A survey of encryption standards
The Direction of Broadband Spillovers
Challenges and Opportunities for Extremely Energy-Efficient Processors
Innovations in a technology museum
Transformer: A New Paradigm for Building Data-Parallel Programming Models
End-to-End Cloud Application Cloning With Ditto
Software Design for Real-Time Multiprocessor VMEbus Systems
Micro Review: Twitter
Machine Learning for Systems, Biological Computing, and More
High-Performance Networks: A Focus on the Fiber Distributed Data Interface (FDDI) Standard
The P1073 medical information bus
Simultaneous bidirectional transceiver logic
Coming down the home stretch in the Rambus standardization skullduggery saga: To levy or not to levy royalties
An Empirical Analysis of the IEEE-1394 Serial Bus Protocol
Guest Editor?s Introduction: Systems on a Chip--The Next Electronic Frontier