yusuke1997/dblp-id-title huggingface dataset:
A 200-256-GS/s Current-Mode 4-Way Interleaved Sampling Front-End With Over 67-GHz Bandwidth Using a Slew-Rate Insensitive Clocking Scheme
A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
A CMOS subbandgap reference circuit with 1-v power supply voltage
5-60-GHz high-gain distributed amplifier utilizing InP cascode HEMTs
A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation
A set of four ICs in CMOS technology for a programmable hearing aid
A parallel structure for CMOS four-quadrant analog multipliers and its application to a 2-GHz RF downconversion mixer
Multi-Phase Clock Generation for Phase Interpolation With a Multi-Phase, Injection-Locked Ring Oscillator and a Quadrature DLL
A 128 Kbit SRAM With an Embedded Energy Monitoring Circuit and Sense-Amplifier Offset Compensation Using Body Biasing
A Variable-Gain Low-Noise Transimpedance Amplifier for Miniature Ultrasound Probes
A Wireless Hysteretic Controlled Wireless Power Transfer System With Enhanced Efficiency and Dynamic Response for Bioimplants
A VLSI CMOS delay oriented waveform converter for polyphase frequency synthesizer
A 100 W 5.1-Channel Digital Class-D Audio Amplifier With Single-Chip Design
Fully integrated wideband high-current rectifiers for inductively powered devices
A 110-to-130 GHz SiGe BiCMOS Doherty Power Amplifier With a Slotline-Based Power Combiner
A GSM-GPRS/UMTS FDD-TDD/WLAN 802.11a-b-g multi-standard carrier generation system
A 16-b 160-kHz CMOS A/D converter using sigma-delta modulation
A 0.6-mW 16-FSK Receiver Achieving a Sensitivity of -103 dBm at 100 kb/s
A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones
A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS
A 6 K GaAs gate array with fully functional LSI personalization
Low voltage performance of a microwave CMOS Gilbert cell mixer
A 5.2 GHz CMOS I/Q Modulator With Integrated Phase Shifter for Beamforming
An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver With Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer
An 80 mW 40 Gb/s 7-Tap T/2-Spaced Feed-Forward Equalizer in 65 nm CMOS
CMOS voltage reference based on gate work function differences in poly-Si controlled by conductivity type and impurity concentration
A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication
A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference
1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro
A Fully Integrated Digital Hearing Aid Chip With Human Factors Considerations
An 8-b 85-MS/s parallel pipeline A/D converter in 1- mu m CMOS
Design of Transformer-Based Boost Converter for High Internal Resistance Energy Harvesting Sources With 21 mV Self-Startup Voltage and 74% Power Efficiency
A 6 to 12-GHz Fractional-N Frequency Synthesizer With a Digital Technique to Counter Modulus-Dependent Feedback Divider Delays
A wide-dynamic-range, high-transimpedance Si bipolar preamplifier IC for 10-Gb/s optical fiber links
Track-and-Zoom Neural Analog-to-Digital Converter With Blind Stimulation Artifact Rejection
CMOS single-chip gas detection system comprising capacitive, calorimetric and mass-sensitive microsensors
Measurement of the local latch-up sensitivity by means of computer-controller scanning electron microscopy
A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS
A Very High Linearity Twin Phase Interpolator With a Low-Noise and Wideband Delta Quadrature DLL for High-Speed Data Link Clocking
A 0.20 mm 2 3 nW Signal Acquisition IC for Miniature Sensor Nodes in 65 nm CMOS
A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers
A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface
On the circuit analysis of the Schmitt trigger
A 150-GHz Single-to-Differential LNA Adopting Wideband G max -Cores Based on Single-Ended Compact Lumped L-C-L and Differential Coupled-Line Embedding Networks
A note on the graphical analysis of the Schmitt-trigger circuit
A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System
An Acoustic Signal Processing Chip With 142-nW Voice Activity Detection Using Mixer-Based Sequential Frequency Scanning and Neural Network Classification
A 1.5-GHz programmable divide-by-N GaAs counter
A logarithmic response CMOS image sensor with on-chip calibration
Oversampled pipeline A/D converters with mismatch shaping
A 0.4-V, 0.138-fJ/Cycle Single-Phase-Clocking Redundant-Transition-Free 24T Flip-Flop With Change-Sensing Scheme in 40-nm CMOS
An 847-955 Mb/s 342-397 mW Dual-Path Fully-Overlapped QC-LDPC Decoder for WiMAX System in 0.13 μ m CMOS
A single-chip pipelined 2-D FIR filter using residue arithmetic
A VLSI sequencer chip for ATM traffic shaper and queue manager
A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation
Low-Power Signal Component Separator for a 64-QAM 802.11 LINC Transmitter
A parallel vector-quantization processor eliminating redundant calculations for real-time motion picture compression
A High Accuracy and Ultra-Energy-Efficient Zero-Shot-Retraining Seizure Detection Processor
Inverter-Based Subthreshold Amplifier Techniques and Their Application in 0.3-V $\Delta\Sigma$ -Modulators
High-gain SiGe transimpedance amplifier array for a 12×10 Gb/s parallel optical-fiber link
A low-power integrated circuit for remote speech recognition
A 120×110 position sensor with the capability of sensitive and selective light detection in wide dynamic range for robust active range finding
A Low Power BAW Resonator Based 2.4-GHz Receiver With Bandwidth Tunable Channel Selection Filter at RF
SiGe Bipolar VCO With Ultra-Wide Tuning Range at 80 GHz Center Frequency
Noncomplementary BiCMOS logic and CMOS logic for low-voltage, low-power operation-a comparative study
A Low SIR Impulse-UWB Transceiver Utilizing Chirp FSK in 0.18 μm CMOS
A Wide-Tracking Range Clock and Data Recovery Circuit
100+ GHz static divide-by-2 circuit in InP-DHBT technology
The Xeon® Processor E5-2600 v3: a 22 nm 18-Core Product Family
A 60 GHz CMOS Full-Duplex Transceiver and Link with Polarization-Based Antenna and RF Cancellation
A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator
A 20-ns 256 K*4 FIFO memory
Introduction to the Special Issue on the 2006 Radio Frequency Integrated Circuits (RFIC) Symposium
A 5-nm 60-GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 35.2dB SNDR up to 32 GHz
Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture
A high-speed CMOS comparator with 8-b resolution
A CMOS "soft-switched" transconductor and its application in gain control and filters
A 54.4-90 GHz Low-Noise Amplifier in 65-nm CMOS
A divided/shared bit-line sensing scheme for ULSI DRAM cores
Analog circuit implementation on CMOS semi-custom arrays
The Blixer, a Wideband Balun-LNA-I/Q-Mixer Topology
A 1.2 V 114 mW Dual-Band Direct-Conversion DVB-H Tuner in 0.13 µm CMOS
A 64-fJ/Conv.-Step Continuous-Time Sigma Delta Modulator in 40-nm CMOS Using Asynchronous SAR Quantizer and Digital Delta Sigma Truncator
A 12.24-GHz MDLL With a 102-Multiplication Factor Using a Power-Gating-Based Ring Oscillator
Non-Magnetic CMOS Switched-Transmission-Line Circulators With High Power Handling and Antenna Balancing: Theory and Implementation
A Sub-0.2°hr Bias Drift Micromechanical Silicon Gyroscope With Automatic CMOS Mode-Matching
A D-Band Low-Power and High-Efficiency Frequency Multiply-by-9 FMCW Radar Transmitter in 28-nm CMOS
Crosstalk delay analysis of a 0.13-μm node test chip and precise gate-level simulation technology
A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device
A 280-GHz Schottky Diode Detector in 130-nm Digital CMOS
Switched-current signal processing for video frequencies and beyond
A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process
A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications
A CMOS self-regulating VCO with low supply sensitivity
A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor
A 1 Gb/s Mixed-Signal Baseband Analog Front-End for a 60 GHz Wireless Receiver
10- and 40-Gb/s forward error correction devices for optical communications
A Hybrid AMOLED Driver IC for Real-Time TFT Nonuniformity Compensation
A System Based on Capacitive Interfacing of CMOS With Post-Processed Thin-Film MEMS Resonators Employing Synchronous Readout for Parasitic Nulling
A self-learning digital neural network using wafer-scale LSI
187 MHz Subthreshold-Supply Charge-Recovery FIR
A chopped Hall sensor with small jitter and programmable "True Power-on" function
A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS
Introduction to the Special Section on the 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)
A 2.08-mW 64.4-dB SNDR 400-MS/s Pipelined- SAR ADC Using Mismatch and PVT Variation Tolerant Dynamically Biased Ring Amplifier in 8 nm
Variable supply-voltage scheme for low-power high-speed CMOS digital design
A self-biased feedback-controlled pull-down emitter follower for high-speed low-power bipolar logic circuits
Laser Voltage Probing Attack Detection via Leakage Shift Monitoring Without Dedicated Sensors at 4.35% Area Overhead
A Memory-Efficient IDMA Architecture Based on On-the-Fly Despreading
Combined In-Pixel Linear and Single-Photon Avalanche Diode Operation With Integrated Biasing for Wide-Dynamic-Range Optical Sensing
A 4th-Order Continuous-Time Delta-Sigma Modulator Using 6-bit Double Noise-Shaped Quantizer
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance
Introduction to the Special Section on the 2019 Asian Solid-State Circuits Conference (A-SSCC)
Automatic swing control in relaxation oscillators
A Thermal-Diffusivity-Based Frequency Reference in Standard CMOS With an Absolute Inaccuracy of ±0.1% From - 55°C to 125°C
Performance limitations of low-voltage regulators using only n-p-n transistors
A new MOSFET-C universal filter structure for VLSI
10-GHz Si bipolar amplifier and mixer ICs for coherent optical systems
Logic synthesis of race-free asynchronous CMOS circuits
A slew-rate controlled output driver using PLL as compensation circuit
A Low-Power, Linearized, Ultra-Wideband LNA Design Technique
An experimental coin-sized radio for extremely low-power WPAN (IEEE 802.15.4) application at 2.4 GHz
A Wideband Mode-Switching Quad-Core VCO Using Compact Multi-Mode Magnetically Coupled LC Network
Trimless high precision ratioed resistors in D/A and A/D converters
An Implantable Optical Stimulation Delivery System for Actuating an Excitable Biosubstrate
A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion
Introduction to the Special Issue on the 2007 Bipolar/BiCMOS Circuits and Technology Meeting
A 2.4-GHz, 27-dBm Asymmetric Multilevel Outphasing Power Amplifier in 65-nm CMOS
A video DSP with a macroblock-level-pipeline and a SIMD type vector-pipeline architecture for MPEG2 CODEC
An 8-bit 100-MHz full-Nyquist analog-to-digital converter
A Class-G Switched-Capacitor RF Power Amplifier
An integrated cortical layer for orientation enhancement
An LO Leakage Suppression Technique for Blocker-Tolerant Wideband Receivers With High-Q Selectivity at RF Input
An On-Die All-Digital Power Supply Noise Analyzer With Enhanced Spectrum Measurements
A 30.5 dBm 48% PAE CMOS Class-E PA With Integrated Balun for RF Applications
Concurrent error-detectable butterfly chip for real-time FFT processing through time redundancy
A Millimeter-Wave Three-Way Doherty Power Amplifier for 5G NR OFDM
A 100-MHz 4-Mb cache DRAM with fast copy-back scheme
A Flash-Based Non-Uniform Sampling ADC With Hybrid Quantization Enabling Digital Anti-Aliasing Filter
Pseudo Hysteretic Controlled Gap Time Modulated Isolated DC-DC Converter With Common-Mode Transient Immunity
A 7-Bit 18th Order 9.6 GS/s FIR Up-Sampling Filter for High Data Rate 60-GHz Wireless Transmitters
An accurate analytical BiCMOS delay expression and its application to optimizing high-speed BiCMOS circuits
A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link
Fractal capacitors
A Low Quiescent Current, Low THD+N Class-D Audio Amplifier With Area-Efficient PWM-Residual-Aliasing Reduction
Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration
A transition-encoded dynamic bus technique for high-performance interconnects
An oversampling converter for strain gauge transducers
A 1.5-V, 1.5-GHz CMOS low noise amplifier
A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers
A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training
90% write power-saving SRAM using sense-amplifying memory cell
A 10 b 50 MHz pipelined CMOS A/D converter with S/H
Analysis and improvements of accurate dynamic current mirrors
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor
A 29.12-TOPS/W Vector Systolic Accelerator With NAS-Optimized DNNs in 28-nm CMOS
Design and Analysis of a Fractional Frequency Synthesizer With <90-fs Jitter and <-103-dBc Spurious Tones Using Digital Spur Cancellation
A 45 nm CMOS-SOI Monolithic Photonics Platform With Bit-Statistics-Based Resonant Microring Thermal Tuning
Metamorphic HEMT MMICs and Modules Operating Between 300 and 500 GHz
A 2.4-GHz RF sampling receiver front-end in 0.18-μm CMOS
An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation
A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier
Harmonic distortion caused by capacitors implemented with MOSFET gates
A Pitch-Matched High-Frame-Rate Ultrasound Imaging ASIC for Catheter-Based 3-D Probes
A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications
A Compact D-Band Phase Shifter With 0.1-Degree Phase Resolution and Ultra-Low Phase Error in 65-nm CMOS
5.2/5.7-GHz 48-dB Image Rejection GaInP/GaAs HBT Weaver Down-Converter Using LO Frequency Quadrupler
A 228 μ W 750 MHz BPSK Demodulator Based on Injection Locking
Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems
Parallel testing of parametric faults in a three-dimensional dynamic random-access memory
An Energy-Efficient GAN Accelerator With On-Chip Training for Domain-Specific Optimization
Demodulators for a zero-IF Bluetooth receiver
A 13.56-MHz Single-Input Dual-Output Wireless Power and Data Transfer System for Bio-Implants
A 40-mW 55 Mb/s CMOS equalizer for use in magnetic storage read channels
Design techniques for high-frequency CMOS switched-capacitor filters using non-op-amp-based unity-gain amplifiers
A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/λ PAM-4 Optical Links
Low-power design of 8-b embedded CoolRisc microcontroller cores
11-bit Column-Parallel Single-Slope ADC With First-Step Half-Reference Ramping Scheme for High-Speed CMOS Image Sensors
Fully integrated SiGe VCOs with powerful output buffer for 77-GHz automotive Radar systems and applications around 100 GHz
A 10-b 40-Msample/s BiCMOS A/D converter
A Fully Integrated Nine-Ratio Switched-Capacitor Converter With Overlapped-Conversion-Ratio Modulation for IoT Applications
A 3.3-V CMOS adaptive analog video line driver with low distortion performance
Synthesis of control circuits in folded pipelined DSP architectures
A 10-GHz CMOS quadrature LC-VCO for multirate optical applications
A 140-GHz FMCW TX/RX-Antenna-Sharing Transceiver With Low-Inherent-Loss Duplexing and Adaptive Self-Interference Cancellation
33-GHz monolithic cascode AlInAs/GaInAs heterojunction bipolar transistor feedback amplifier
A Compact 10-b SAR ADC With Unit-Length Capacitors and a Passive FIR Filter
A 0.6-2.5-GBaud CMOS tracked 3 × oversampling transceiver with dead-zone phase detection for robust clock/data recovery
A study of hot-carrier-induced mismatch drift: a reliability issue for VLSI circuits
A 65.9-dB PSRR, Compact LNA Array for Correlated Noise Compression in High-Channel-Count Pitch-Matched Ultrasound ASICs
A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Multi-Lane Serial-Link Receivers
An adaptive line equalizer LSI for ISDN subscriber loops
A 4.5 mW CT Self-Coupled ΔΣ Modulator With 2.2 MHz BW and 90.4 dB SNDR Using Residual ELD Compensation
A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme
A 21-Gb/s Duobinary Transceiver for GDDR Interfaces With an Adaptive Equalizer
A Noise-Shaped VCO-Based Nonuniform Sampling ADC With Phase-Domain Level Crossing
A Dual-Output Thermoelectric Energy Harvesting Interface With 86.6% Peak Efficiency at 30 µW and Total Control Power of 160 nW
A 0.0046-mm 2 Two-Step Incremental Delta-Sigma Analog-to-Digital Converter Neuronal Recording Front End With 120-mVpp Offset Compensation
Cell height driven transistor sizing in a cell based static CMOS module design
A highly miniaturized front-end HIC for 1.9 GHz bands
A 2-GS/s 3-bit ΔΣ-modulated DAC with tunable bandpass mismatch shaping
C-DNN: An Energy-Efficient Complementary Deep-Neural-Network Processor With Heterogeneous CNN/SNN Core Architecture
A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET
A 0.3-V CMOS Biofuel-Cell-Powered Wireless Glucose/Lactate Biosensing System
A Low-Jitter and Compact-Area Fractional-N Digital PLL With Fast Multi-Variable Calibration Using the Recursive Least-Squares Algorithm
A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique
Hot-carrier-reliability design guidelines for CMOS logic circuits
A 65 nm 0.5 V DPS CMOS Image Sensor With 17 pJ/Frame.Pixel and 42 dB Dynamic Range for Ultra-Low-Power SoCs
A 400-Ms/s frequency translating bandpass sigma-delta modulator
An InGaP/GaAs Merged HBT-FET (BiFET) Technology and Applications to the Design of Handset Power Amplifiers
Impact of clock slope on true single phase clocked (TSPC) CMOS circuits
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter
A Low-Voltage Area-Efficient TSV I/O With QEC Realizing Data Rate up to 15 Gb/s for TSV Interface
Planar 200-GHz Transceiver Modules
A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity
A 76.9 ppm/K Nano-Watt PVT-Insensitive CMOS Voltage Reference Operating From 4 to 300 K for Integrated Cryogenic Quantum Interface
A 160-MHz analog equalizer for magnetic disk read Channel
A Fractional- N PLL With Space-Time Averaging for Quantization Noise Reduction
A 0.23-µg Bias Instability and 1-µg/√Hz Acceleration Noise Density Silicon Oscillating Accelerometer With Embedded Frequency-to-Digital Converter in PLL
An Ultra-Low-Noise Swing-Boosted Differential Relaxation Oscillator in 0.18-μm CMOS
Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs
A 150-MHz graphics rendering processor with 256-Mb embedded DRAM
An FIR-Embedded Noise Filtering Method for ΔΣ Fractional-N PLL Clock Generators
A 2x2 MIMO Tri-Band Dual-Mode Direct-Conversion CMOS Transceiver for Worldwide WiMAX/WLAN Applications
A 3.3-V, 15-bit, delta-sigma ADC with a signal bandwidth of 1.1 MHz for ADSL applications
Automated design of switched-current filters
Rail-to-Rail, Linear Hot-Electron Injection Programming of Floating-Gate Voltage Bias Generators at 13-Bit Resolution
Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices
A log-polar image sensor fabricated in a standard 1.2-μm ASIC CMOS process
A Noise-Efficient 36 nV/ $\surd $ Hz Chopper Amplifier Using an Inverter-Based 0.2-V Supply Input Stage
A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs
A 22.9-38.2-GHz Dual-Path Noise-Canceling LNA With 2.65-4.62-dB NF in 28-nm CMOS
A Band-Shifting Millimeter-Wave T/R Front-End Using Inductance-Mutation Transformer Technique for Multiband Phased-Array Transceivers
An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking
Analysis and Design of a Passive Switched-Capacitor Matrix Multiplier for Approximate Computing
A 32-channel charge readout IC for programmable, nonlinear quantization of multichannel detector data
A CMOS Time-to-Digital Converter (TDC) Based On a Cyclic Time Domain Successive Approximation Interpolation Method
On-Chip Links With Energy-Quality Tradeoff in Error-Resilient and Machine Learning Applications
Adaptive analog IF signal processor for a wide-band CMOS wireless receiver
V TH -hopping scheme to reduce subthreshold leakage for low-power processors
A 22-ng/ $\surd$ Hz 17-mW Capacitive MEMS Accelerometer With Electrically Separated Mass Structure and Digital Noise- Reduction Techniques
A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps
A direct-conversion receiver for DVB-H
A chip set for lossless image compression
An auto-gain control transimpedance amplifier with low noise and wide input dynamic range for 10-Gb/s optical communication systems
A High-Efficiency High-Power 170-176-GHz Frequency Stabilized Quadrature Radiator
Ring Amplifiers for Switched Capacitor Circuits
A 12-bit medium-time analog storage device in a CMOS standard process
A 300-GHz Fundamental Oscillator in 65-nm CMOS Technology
A novel SFG structure for C-T high-pass filters
A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design
A 10-GS/s 8-bit 2850-μm 2 Two-Step Time-Domain ADC With Speed and Efficiency Enhanced by the Delay-Tracking Pipelined-SAR TDC
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
Tunable N-Path Notch Filters for Blocker Suppression: Modeling and Verification
High gain-bandwidth differential distributed InP D-HBT driver amplifiers with large (11.3 V pp ) output swing at 40 Gb/s
A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications
IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems
A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET
A 13.56-MHz RFID System Based on Organic Transponders
A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs
An Embedded nand Flash-Based Compute-In-Memory Array Demonstrated in a Standard Logic Process
A 86 MHz-12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS
Digitally programmable gain control circuit for charge-domain signal processing
A 2.4-GHz 0.18-μm CMOS self-biased cascode power amplifier
A 500-MHz Bandwidth 7.5-mV pp Ripple Power-Amplifier Supply Modulator for RF Polar Transmitters
Variation-Tolerant Elastic Clock Scheme for Low-Voltage Operations
12 GHz clocked operation of ultralow power interband resonant tunneling diode pipelined logic gates
A step-down boosted-wordline scheme for 1-V battery-operated fast SRAM's
A Compact, ESD-Protected, SiGe BiCMOS LNA for Ultra-Wideband Applications
A class AB monolithic mixer for 900-MHz applications
A wideband low-noise variable-gain BiCMOS transimpedance amplifier
Large bandwidth BiCMOS operational amplifiers for SC video applications
A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS
A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS
A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD