yusuke1997/dblp-id-title huggingface dataset:
Efficient Implementation and Design of a New Single-Channel Electrooculography-Based Human-Machine Interface System
Cell Search in WCDMA Under Large-Frequency and Clock Errors: Algorithms to Hardware Implementation
Electrocardiographic signal compression using multiscale recurrent patterns
Statistical Characterization of Noise and Interference in NAND Flash Memory
Wide Tunning Range 60 GHz VCO and 40 GHz DCO Using Single Variable Inductor
Using Transmission Line Outage Data to Estimate Cascading Failure Propagation in an Electric Power System
On Enhancing Reliability of Weak PUFs via Intelligent Post-Silicon Accelerated Aging
K-band High-PAE Wide-Tuning-Range VCO Using Triple-Coupled LC Tanks
An Integrated Full-Wave CMOS Rectifier With Built-In Back Telemetry for RFID and Implantable Biomedical Applications
Simulation and Analysis of Random Decision Errors in Clocked Comparators
Optimal Single Constant Multiplication Using Ternary Adders
Cooperative Phenomena in Networks of Oscillators With Non-Identical Interactions and Dynamics
The Analysis and Application of Redundant Multistage ADC Resolution Improvements Through PDF Residue Shaping
Full MIMO Spatial Filtering Approach for Dynamic Range Reduction in Wideband Cognitive Radios
A Fast Passivity Test for Stable Descriptor Systems via Skew-Hamiltonian/Hamiltonian Matrix Pencil Transformations
A 0.1-1.5 GHz Harmonic Rejection Receiver Front-End With Phase Ambiguity Correction, Vector Gain Calibration and Blocker-Resilient TIA
Energy Autonomous Wireless Valve Leakage Monitoring System With Acoustic Emission Sensor
A Fully Integrated Low-Dropout Regulator With Differentiator-Based Active Zero Compensation
An Integrated 13.56-MHz RFID Tag in a Printed Organic Complementary TFT Technology on Flexible Substrate
Guest Editorial Special Issue on the 2018 ISICAS: A CAS Journal Track Symposium
A 4-MHz Digitally Controlled Voltage-Mode Buck Converter With Embedded Transient Improvement Using Delay Line Control Techniques
High-Efficiency E-Band Power Amplifiers and Transmitter Using Gate Capacitance Linearization in a 65-nm CMOS Process
Optimal Low Power Complex Filters
An 83.4% Peak Efficiency Single-Inductor Multiple-Output Based Adaptive Gate Biasing DC-DC Converter for Thermoelectric Energy Harvesting
Combined-Step-Size Normalized Subband Adaptive Filter With a Variable-Parametric Step-Size Scaler Against Impulsive Interferences
Pre-Energized Auxiliary Circuits for Very Fast Transient Loads: Coping With Load-Informed Power Management for Computer Loads
Comments on "Noise Performance of a Regulated Cascode Transimpedance Amplifier for Radiation Detectors"
Design and Analysis of Multistage Multiphase Switched-Capacitor Boost DC-AC Inverter
Circuit Design for Bias Compatibility in Novel FinFET-Based Floating-Body RAM
H ∞ Finite Memory Controls for Linear Discrete-Time State-Space Models
Linearization of Active Downconversion Mixers at the IF Using Feedforward Cancellation
Concurrent Dual-Band Class-F Load Coupling Network for Applications at 1.7 and 2.14 GHz
A Low-Cost VLC Implementation for MPEG-4
Design Procedure for Class E Switching Circuits Allowing Implicit Circuit Equations
A 4-b 7-µW Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation
Pipelined array-based FIR filter folding
An Adaptive Resolution Asynchronous ADC Architecture for Data Compression in Energy Constrained Sensing Applications
Fractional-Delay and Supersymmetric M th-Band Linear-Phase FIR Filters Utilizing Partially Symmetric and Antisymmetric Impulse Responses
A SPICE Model of the Ta 2 O 5 TaO x Bi-Layered RRAM
Configurable Architectures for Multi-Mode Floating Point Adders
Properties and experimental results of fastest linearly independent ternary arithmetic transforms
Current-Mode Monostable Multivibrators Using OTRAs
A Multi-Stable Memristor and its Application in a Neural Network
A Fast Integral Image Computing Hardware Architecture With High Power and Area Efficiency
Design Method of Class-F Power Amplifier With Output Power of -20 dBm and Efficient Dual Supply Voltage Transmitter
Complex Two-Parameter Bifurcation Diagrams of a Simple Oscillating Circuit
Implementation of Linear-Phase FIR Filters for a Rational Sampling-Rate Conversion Utilizing the Coefficient Symmetry
Digital Event-Based Control for Nonlinear Systems Without the Limit of ISS
A g m /I D -Based Noise Optimization for CMOS Folded-Cascode Operational Amplifier
High Selectivity Dual-Wideband Balun Filter Utilizing a Multimode T-line Loaded Middle-Shorted CSRR
A Versatile Time-Domain Approach to Simulate Oscillators in RF Circuits
Design and Implementation of High Throughput, Robust, Parallel M-QAM Demodulator in Digital Communication Receivers
Design of phase-controlled class E inverter with asymmetric circuit configuration
Phase-Rotator-Based All-Digital Phase-Locked Loop for a Spread-Spectrum Clock Generator
Analysis and Design of a Wide-Tuning-Range VCO With Quadrature Outputs
A Linear Phase Condition for Volterra Filters
On the Attenuation of DAC Aliases Through Multiphase Clocking
A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme
Multidimensional Adaptive Power Management for Low-Power Operation of Wireless Devices
FPGA-Based True Random Number Generation Using Programmable Delays in Oscillator-Rings
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain
A 28-nm FD-SOI CMOS Variable-Gain Amplifier With Body-Bias-Based DC-Offset Cancellation for Automotive Radars
A 7.92 Gb/s 437.2 mW Stochastic LDPC Decoder Chip for IEEE 802.15.3c Applications
Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms
Radix-8 Booth Encoded Modulo 2 n -1 Multipliers With Adaptive Delay for High Dynamic Range Residue Number System
ΔΣ Fractional-N PLL With Hybrid IIR Noise Filtering
LLR-Based Successive-Cancellation List Decoder for Polar Codes With Multibit Decision
Memristive Model for Synaptic Circuits
A DLL-Based Quadrature Clock Generator With a 3-Stage Quad Delay Unit Using the Sub-Range Phase Interpolator for Low-Jitter and High-Phase Accuracy DRAM Applications
Guaranteed-Cost Consensus for Singular Multi-Agent Systems With Switching Topologies
An asynchronous cellular logic network for trigger-wave image processing on fine-grain massively parallel arrays
New Parametric Discrete Fourier and Hartley Transforms, and Algorithms for Fast Computation
Periodic Event-Triggered Adaptive Control for Attitude Stabilization Under Input Saturation
General Dynamics of Pulsed Digital Oscillators
Design and Comparison of Very Low-Voltage CMOS Output Stages
An Adaptive Upper Threshold Based Gain Function for the ZA-PNLMS Algorithm
DOB Design for Nonminimum-Phase Delay Systems and Its Application in Multivariable MPC Control
Efficient selection of discriminative genes from microarray gene expression data for cancer diagnosis
Fully Integrated CMOS EME-Suppressing Current Regulator for Automotive Electronics
A Modular Multiplier Implemented With Truncated Multiplication
A Tutorial on GrÖbner Bases With Applications in Signals and Systems
High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations
Variation-Tolerant Architecture for Ultra Low Power Shared-L1 Processor Clusters
Tuning of High-Speed Telecommunication Filters, via I/O Cross-Correlation Evaluation
Design and implementation of n-scroll chaotic attractors from a general jerk circuit
Embedded Measurement of GHz Digital Signals With Time Amplification in CMOS
A Time-Mode Translinear Principle for Nonlinear Analog Computation
Continuum modeling of electromechanical dynamics in large-scale power systems
An Efficient SoC Test Technique by Reusing On/Off-Chip Bus Bridge
Using Rotator Transformations to Simplify FFT Hardware Architectures
A 4-muhboxW CMOS Front End for Particle Detection Applications
Scalable and modular memory-based systolic architectures for discrete Hartley transform
An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder
Lag Quasi-Synchronization of Coupled Delayed Systems With Parameter Mismatch
A compact gate-level energy and delay model of dynamic CMOS gates
A fully digital fast convergence algorithm for nonlinearity correction in multistage ADC
Contraction Theory and Master Stability Function: Linking Two Approaches to Study Synchronization of Complex Networks
A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture
A Voltage-Scalable Low-Power All-Digital Temperature Sensor for On-Chip Thermal Monitoring
A Fast and Compact Charger for an Li-Ion Battery Using Successive Built-In Resistance Detection
An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks
Efficient VLSI Implementations of Fast Multiplierless Approximated DCT Using Parameterized Hardware Modules for Silicon Intellectual Property Design
Rader-Brenner Algorithm for Computing New Mersenne Number Transform
A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS
Designing High-Speed Adders in Power-Constrained Environments
Energy Efficient Single-Ended 6-T SRAM for Multimedia Applications
Design of Modulated Filter Banks and Transmultiplexers With Unified Initial Solutions and Very Few Unknown Parameters
A 0.90-4.39-V Detection Voltage Range, 56-Level Programmable Voltage Detector Using Fine Voltage-Step Subtraction for Battery Management
Autonomous Event Driven Model of Second Order Voltage Switched Charge Pump PLL
Global Synchronization of Directional Networked Systems With Eventually Dissipative Nodes
Dual-Band Millimeter-Wave Quadrature LO Generation With a Common-Centroid Floorplan
A 15 µW 5.5 kS/s Resistive Sensor Readout Circuit with 7.6 ENOB
An Analytical Delay Model for Mechanical Stress Induced Systematic Variability Analysis in Nanoscale Circuit Design
A 9-bit 80 MS/s Successive Approximation Register Analog-to-Digital Converter With a Capacitor Reduction Technique
A Digital Envelope Combiner for Switching Power Amplifier Linearization
Optimal bus sizing in migration of processor design
FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network
The Origin of Nonlinear Phenomena in TCR-SVC Associated With Parametric Excitation of Intrinsic Oscillation and External Excitation
A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System
Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications
Fast Startup of LC VCOs Using Circuit Asymmetries
A 0.25-dB-Step, 68-dB-Dynamic Range Analog Baseband With Digitally Assisted DCOC and AGC for Multi-Standard TV Applications
Robust H 2 filtering for a class of systems with stochastic nonlinearities
A Nonlinear Acoustic Echo Canceller Using Sigmoid Transform in Conjunction With RLS Algorithm
A Novel Conflict-Free Parallel Memory Access Scheme for FFT Processors
PUF Sensor: Exploiting PUF Unreliability for Secure Wireless Sensing
A Novel Mixed-Signal Integrated Circuit Model for DNA-Protein Regulatory Genetic Circuits and Genetic State Machines
A 14-mW PLL-Less Receiver in 0.18-µm CMOS for Chinese Electronic Toll Collection Standard
Instantaneous Clockless Data Recovery and Demultiplexing
Design of a Switched-Capacitor DC-DC Converter With a Wide Input Voltage Range
An Affine Projection Adaptive Filtering Algorithm With Selective Regressors
Comparator Power Minimization Analysis for SAR ADC Using Multiple Comparators
The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM
Ultra-Low Power, Secure IoT Platform for Predicting Cardiovascular Diseases
High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming
Real-Time Depth From Focus on a Programmable Focal Plane Processor
Nonlinear adaptive bilinear filters for active noise control systems
A 40 nm CMOS I/O Pad Design With Embedded Capacitive Coupling Receiver for Non-Contact Wafer Probe Test
Optimal Step-Size Control of the Partitioned Block Frequency-Domain Adaptive Filter
An Investigation on Extraction of Material Parameters in Longitudinal Mode of FBAR
A Synchronous Multioutput Step-Up/Down DC-DC Converter With Return Current Control
Compact SIW Diplexers and Dual-Band Bandpass Filter With Wide-Stopband Performances
An 8-11 Gb/s Reference-Less Bang-Bang CDR Enabled by "Phase Reset"
Demystifying and Mitigating Code-Dependent Switching Distortions in Current-Steering DACs
Statistical properties of the LMS fourier analyzer in the presence of frequency mismatch
Oscillation-Based Slime Mould Electronic Circuit Model for Maze-Solving Computations
Sensitivity Analysis of Continuous-Time Δ Σ ADCs to Out-of-Band Blockers in Future SAW-Less Multi-Standard Wireless Receivers
Empirical frequency-domain optimal parameter estimate for black-box processes
The Design and Analysis of a CMOS Low-Power Large-Neighborhood CNN With Propagating Connections
Minimizing Coefficients Wordlength for Piecewise-Polynomial Hardware Function Evaluation With Exact or Faithful Rounding
Analysis of the Desired-Response Influence on the Convergence of Gradient-Based Adaptive Algorithms
Positive Realness and Absolute Stability Problem of Descriptor Systems
Toward an Efficient Multiview Display Processing Architecture for 3DTV
Filtering Power Amplifier With Wide Bandwidth Using Discriminating Coupling
Analysis and Design of I/Q Charge-Sharing Band-Pass-Filter for Superheterodyne Receivers
Variation-Tolerant Sensing Circuit for Spin-Transfer Torque MRAM
A 5-Gb/s Serial-Link Redriver With Adaptive Equalizer and Transmitter Swing Enhancement
Measurement of Intersymbol Interference Jitter by Fractional Oversampling for Adaptive Equalization
Delayless Extraction of Instantaneous Symmetrical Components in Power System Fault Conditions
Photovoltaic Sample-and-Hold Circuit Enabling MPPT Indoors for Low-Power Systems
A Differential Quantizer-Based Error Feedback Modulator for Analog-to-Digital Converters
Improved Cognitive Radio Receivers Using Timing Mismatch of Primary and Secondary Users
Analysis of Millimeter-Wave LC Oscillators Based on Two-Port Network Theory
A topological approach to the identification of critical measurements in power-system state estimation
A 0.5-V, 1.47- µW 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation
High Efficiency and Small Group Delay Variations 0.18- $\mu$ m CMOS UWB Power Amplifier
A Qualification Approach to DAC Mismatch-Shaping Methods
RC Distributed Circuits for Vibration Damping in Piezo-Electromechanical Beams
The Nearest-Instance-Centroid-Estimation Kernel Recursive Least Squares Algorithms
Linear bipolar OTAs based on a triple-tail cell employing exponential circuits
Balanced $(3+2\log n)\Delta G$ Adders for Moduli Set $\{{2}^{n+1}, 2^{n}+2^{n-1}-1, 2^{n+1}-1\}$
Diameter-Constrained Overlays With Faulty Links: Equilibrium, Stability, and Upper Bounds
A Note on "Global Robust Stability Criteria for Interval Delayed Neural Networks Via an LMI Approach"
VLSI Architectures for the 4-Tap and 6-Tap 2-D Daubechies Wavelet Filters Using Algebraic Integers
Fast 2-dimensional 4 × 4 forward integer transform implementation for H.264/AVC
A ZVS PWM inverter with active voltage clamping using the reverse recovery energy of the diodes
A Time-Variant Analysis of Fundamental 1/f 3 Phase Noise in CMOS Parallel LC -Tank Quadrature Oscillators
A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC
A System of Two Coupled Oscillators With a Continuously Controllable Phase Shift
Quantization Noise Suppression in Fractional-N PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider
Stability Criteria With Less LMI Variables for Neural Networks With Time-Varying Delay
Wireless Power Transfer System With ΣΔ-Modulated Transmission Power and Fast Load Response for Implantable Medical Devices
Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance
An Adaptive System for Optimal Solar Energy Harvesting in Wireless Sensor Network Nodes
Complex Discretization Behaviors of a Simple Sliding-Mode Control System
Low-Power Floating-Point Adaptive-CORDIC-Based FFT Twiddle Factor on 65-nm Silicon-on-Thin-BOX (SOTB) With Back-Gate Bias
Architectures for Maximum-Sequence-Length Digital Delta-Sigma Modulators
Feedback Biasing in Nanoscale CMOS Technologies
Feasibility of Analog Realization of a Sliding-Mode Observer: Application to Data Transmission
Dynamics and Stability Analysis of a Power System With a PMSG-Based Wind Farm Performing Ancillary Services
Design centering using an approximation to the constraint region
Cascaded Complex ADCs With Adaptive Digital Calibration for I/Q Mismatch
A 45-nm SOI CMOS Integrate-and-Dump Optical Sampling Receiver
An Ultra High Gain Quasi Z-Source Inverter Consisting Active Switched Network
A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers
A Nonlinear Switched State-Space Model for Capacitive RF DACs
A Low Power Frequency Tunable FSK Receiver Based on the N-Path Filter
High-Efficiency Power Amplifier Using an Active Second-Harmonic Injection Technique Under Optimized Third-Harmonic Termination
On the Existence of the Power Flow Solution in DC Grids With CPLs Through a Graph-Based Method
Analysis of Zeros in a Boost DC-DC Converter: State Diagram Approach
An Accurate Bandgap-Based Power-on-Detector in 14-nm CMOS Technology
A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces
An SRAM Reliability Test Macro for Fully Automated Statistical Measurements of V MIN Degradation
One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes
Highly Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 65-nm CMOS
Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer and Resistor
A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching
FPAA/Memristor Hybrid Computing Infrastructure
An Accurate DNA Sensing and Diagnosis Methodology Using Fabricated Silicon Nanopores
Memristive Biosensors Integration With Microfluidic Platform
A Flexible 500 MHz to 3.6 GHz Wireless Receiver with Configurable DT FIR and IIR Filter Embedded in a 7b 21 MS/s SAR ADC
Direct Antenna Modulation (DAM) for Enhanced Capacity Performance of Near-Field Communication (NFC) Link
High-Speed Low-Complexity Guided Image Filtering-Based Disparity Estimation
New Low Glitch and Low Power DET Flip-Flops Using Multiple C-Elements
Full Model and Characterization of Noise in Operational Amplifier
A Robust Bio-IA With Digitally Controlled DC-Servo Loop and Improved Pseudo-Resistor
A Low-Power 1-V Potentiostat for Glucose Sensors
"Split ADC" Calibration for All-Digital Correction of Time-Interleaved ADC Errors
A 0.4-V Supply Curvature-Corrected Reference Generator With 84.5-ppm/°C Average Temperature Coefficient Within -40 °C to 130 °C
Feedforward symbol timing recovery technique using two samples per symbol
Integrated SFCW Transceivers for UWB Breast Cancer Imaging: Architectures and Circuit Constraints
Methodology of Statistical RTS Noise Analysis With Charge-Carrier Trapping Models
Implementing Poincaré Sections for a Chaotic Relaxation Oscillator
Robust H ∞ Pinning Synchronization for Complex Networks With Event-Triggered Communication Scheme
NBTI/PBTI-Aware WWL Voltage Control for Half-Selected Cell Stability Improvement
Model Reduction for Optimized Online Compensation of Hysteresis and Creep in Piezoelectric Actuators
A-CACHE: Alternating Cache Allocation to Conduct Higher Endurance in NVM-Based Caches
Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs
Modeling Ionizing Radiation Effects in Solid State Materials and CMOS Devices
Stable computational dynamics for a class of circuits with O(N) interconnections capable of KWTA and rank extractions
Guest Editorial 2017 Special Issue on CASS Regional Flagship Conferences
Introduction to the Special Section on Energy-Harvesting/Scavenging Circuits and Systems
Efficient Reverse Converter Designs for the New 4-Moduli Sets 2 n -1, 2 n , 2 n +1, 2 2n + 1 -1 and 2 n -1, 2 n +1, 2 2n , 2 2n +1 Based on New CRTs
Design Considerations for a Direct RF Sampling Mixer
Block-Based Carry Speculative Approximate Adder for Energy-Efficient Applications
A Novel High-Pass Delta-Sigma Modulator-Based Digital-IF Transmitter With Enhanced Performance for SDR Applications
A Randomized Wrapped-Around Pulse Position Modulation Scheme for DC-DC Converters
A Phase-Domain All-Digital Phase-Locked Loop Architecture Without Reference Clock Retiming
A Time-Domain Band-Gap Temperature Sensor in SOI CMOS for High-Temperature Applications
Highly Efficient Analog Maximum Power Point Tracking (AMPPT) in a Photovoltaic System
A Mixed-Signal Technique for TX-Induced Modulated Spur Cancellation in LTE-CA Receivers
Direct Mismatch Characterization of Femtofarad Capacitors
Design and Implementation of Ultralow Current-Mode Amplifier for Biosensor Applications
On-Chip Compensation of Ring VCO Oscillation Frequency Changes Due to Supply Noise and Process Variation
Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm
A Unified Approach to Chaos Suppressing and Inducing in a Periodically Forced Family of Nonlinear Oscillators
Off-Resonance Oscillation, Phase Retention, and Orthogonality Modeling in Quadrature Oscillators
Lower Bounds for Constant Multiplication Problems
A 130 nm CMOS Power Management Unit With a Multi-Ratio Core SC DC-DC Converter for a Supercapacitor Power Supply
In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults
On Resistive Networks of Constant-Power Devices
A 132.6-GHz Phase-Locked Loop in 65 nm Digital CMOS
A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders
A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier
A Discrete-Time Digital-IF Interference-Robust Ultrawideband Pulse Radio Transceiver Architecture
A Reconfigurable IF to DC Sub-Sampling Receiver Architecture With Embedded Channel Filtering for 60 GHz Applications
On Pinning Synchronization of Directed and Undirected Complex Dynamical Networks
Analysis and Implementation of a Novel Leading Zero Anticipation Algorithm for Floating-Point Arithmetic Units
Update From the Editor-in-Chief
A Unified Framework of Stability Theorems for LTI Fractional Order Systems With 0 < α < 2
Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques
A time-delay jitter-insensitive continuous-time bandpass ΔΣ modulator architecture
Adaptive Filtering Under a Variable Kernel Width Maximum Correntropy Criterion
Robust and Lightweight Ensemble Extreme Learning Machine Engine Based on Eigenspace Domain for Compressed Learning
Digital background calibration for memory effects in pipelined analog-to-digital converters
An oversampled digital PWM linearization technique for digital-to-analog conversion
Design of Linear Phase FIR Filters in Subexpression Space Using Mixed Integer Linear Programming
A Photoacoustic-Surface-Acoustic-Wave Sensor for Ring-Stage Malaria Parasite Detection
Analysis and Design of Bang-Bang PD-Based Phase Noise Filter
Analog Memristive CAMs for Area- and Energy-Efficient Reconfigurable Computing
Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits
A Tunable SiGe BiCMOS Gain-Equalizer For X-Band Phased-Array RADAR Applications
Intermittent Phenomena in Switched Systems With High Coupling Strengths
Capacitor-Coupled Built-Off Self-Test in Analog and Mixed-Signal Embedded Systems
SPAD-Based Quantum Random Number Generator With an N t -Order Rank Algorithm on FPGA
High-Selectivity Tunable Balanced Bandpass Filter With Constant Absolute Bandwidth
A cascade boost-switched-capacitor-converter - two level inverter with an optimized multilevel output waveform
The Extension of the Gauss Approach for the Solution of an Overdetermined Set of Algebraic Non Linear Equations
Noisy Component Extraction (NoiCE)
A 4-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Stochastic Quantizer and Digital Accumulator
Parasitic-aware design and optimization of a CMOS RF power amplifier
Auto-Tuning Proportional-Type Synchronization Algorithm for DC Motor Speed Control Applications