yusuke1997/dblp-id-title huggingface dataset:
A 25-MHz Self-Referenced Solid-State Frequency Source Suitable for XO-Replacement
A 22nm, 10.8 μ W/15.1 μ W Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor
Stable high-order delta-sigma digital-to-analog converters
A CMOS Digitally Programmable Universal Current-Mode Filter
An 85-MHz-BW ASAR-Assisted CT 4-0 MASH $\Delta\Sigma$ Modulator With Background Half-Range Dithering-Based DAC Calibration in 28-nm CMOS
First Principles Optimization of Opto-Electronic Communication Links
Improved Offline Calibration of DAC Mismatch Errors in Delta-Sigma Data Converters
A Biquadratic Cell Based on the Flipped-Source-Follower Circuit
Efficient Reencoder Architectures for Algebraic Soft-Decision Reed-Solomon Decoding
A 400 mu W Hz-Range Lock-In A/D Frontend Channel for Infrared Spectroscopic Gas Recognition
Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance
Generalized Multivariate Rectangular Matrix PadÉ-Type Approximants
Digital Background Calibration in Pipelined ADCs Using Commutated Feedback Capacitor Switching
Reverse Group Consensus of Multi-Agent Systems in the Cooperation-Competition Network
Spatial Memoization: Concurrent Instruction Reuse to Correct Timing Errors in SIMD Architectures
Coordinate Rotation-Based Design Methodology for Square Root and Division Computation
Actively Compensating for Data Packet Disorder in Networked Control Systems
Two Tunable Frequency Duplexer Architectures for Cellular Transceivers
A novel compression and encryption scheme using variable model arithmetic coding and coupled chaotic system
Low-Cost Photoacoustic Tomography System Based on Multi-Channel Delay-Line Module
Reliable Output Feedback Control of Discrete-Time Fuzzy Affine Systems With Actuator Faults
A Subharmonically Injection-Locked PLL With Calibrated Injection Pulsewidth
An Unconstrained Architecture for Systematic Design of Higher Order SigmaDelta Force-Feedback Loops
A Study of BER-Optimal ADC-Based Receiver for Serial Links
A New Multistage Noise-Shaping Architecture
Soft-bit decoding of regular low-density parity-check codes
An Integrated Speed- and Accuracy-Enhanced CMOS Current Sensor With Dynamically Biased Shunt Feedback for Current-Mode Buck Regulators
A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer
2/3 and 1/2 Reconfigurable Switched Capacitor DC-DC Converter With 92.9% Efficiency at 62 mW/mm 2 Using Driver Amplitude Doubler
A Novel Hardware-Efficient Cochlea Model Based on Asynchronous Cellular Automaton Dynamics: Theoretical Analysis and FPGA Implementation
Rakeness-Based Compressed Sensing of Multiple-Graph Signals for IoT Applications
Optimization and Realization of a 315-MHz Low-Phase-Noise Voltage-Controlled SAW Oscillator
Resonant-Inductive Degeneration for Manifold Improvement of Phase Noise in Bipolar LC-Oscillators
LAS-NCS: A Laser-Assisted Spintronic Neuromorphic Computing System
A Matrix Pseudoinversion Lemma and Its Application to Block-Based Adaptive Blind Deconvolution for MIMO Systems
Phase-Error Measurement and Compensation in PLL Frequency Synthesizers for FMCW Sensors - II: Theory
Corrections to "Multiplierless, Folded 9/7-5/3 Wavelet VLSI Architecture" [Sep 07 770-774]
Reconfigurable Digital Front-End Hardware for Wireless Base-Station Transmitters: Analysis, Design and FPGA Implementation
World's Fastest FFT Architectures: Breaking the Barrier of 100 GS/s
An Innovative Fast Algorithm and Structure Design for Analysis and Synthesis Quadrature Mirror Filterbanks on the SBR in DRM
An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter
Single-Bit Digital Frequency Synthesis via Dithered Nyquist-Rate Sinewave Quantization
Corrections to "Two Reciprocal Power Theorems for Passive Linear Time-Invariant Multiports"
Efficient Decoder Design for Nonbinary Quasicyclic LDPC Codes
Corrections to "Sampling and Signal Reconstruction Circuits Performing Internal Antialiasing Filtering and Their Influence on the Design of Digital Receivers and Transmitters"
Wien-Type Oscillators: Evaluation and Optimization of Harmonic Distortion
A 0.7 V Relative Temperature Sensor With a Non-Calibrated $\pm 1~^{\circ}{\rm C}$ 3$\sigma$ Relative Inaccuracy
Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation
Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme
Property of Rational Functions Related to Band-Pass Transformation With Application to Symmetric Filters Design
Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure
An Integrated Discrete-Time Delay-Compensating Technique for Large-Array Beamformers
Generalized Analysis of High-Order Switch-RC N-Path Mixers/Filters Using the Adjoint Network
A Novel Approach to Design Low-Cost Two-Stage Frequency-Response Masking Filters
Model reduction of uncertain FIR discrete-time systems
A 0.13~µm CMOS Operational Schmitt Trigger R-to-F Converter for Nanogap-Based Nanosensors Read-Out
An Ultra-Low-Power Energy-Efficient Dual-Mode Wake-Up Receiver
Design of Time-Delay Chaotic Electronic Circuits
Automatic Substrate Switching Circuit for On-Chip Adaptive Power-Supply System
ERSUT: A Self-Healing Architecture for Mitigating PVT Variations Without Pipeline Flushing
Codes for Limited Magnitude Error Correction in Multilevel Cell Memories
CMOS Latch Using Quad for High-Speed Comparators
Improving Absolute Accuracy of Integrated Resistors With Device Diversification
New low-Voltage fully programmable CMOS triangular/trapezoidal function Generator circuit
A Streaming Motion Magnification Core for Smart Image Sensors
The Role of PLLs in Future Wireline Transmitters
Bandwidth-Enhanced High Current Efficiency Class-AB Buffer With Very Low Output Resistance
Linearity Enhancement Techniques in Radio Receiver Front-Ends
Bipartite Consensus in Networks of Agents With Antagonistic Interactions and Quantization
Exponential Synchronization of Complex Delayed Dynamical Networks With Switching Topology
Neuromodulation of Neuromorphic Circuits
A New Approach for the Design of Wideband Digital Integrator and Differentiator
A Flexible Hardware Architecture for Wavelet Packet Transform With Arbitrary Tree Structure
Analog Circuit Design Using Tunnel-FETs
Fast Bit Parallel-Shifted Polynomial Basis Multipliers in GF(2 n )
Energy and Error Analysis Framework for Approximate Computing in Mobile Applications
Experimental Investigation of Symmetry-Breaking in Ferroresonant Circuit
A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator
Combined-Step-Size Affine Projection Sign Algorithm for Robust Adaptive Filtering in Impulsive Interference Environments
Scaling Up In-Memory-Computing Classifiers via Boosted Feature Subsets in Banked Architectures
A 440-nA True Random Number Generator for Passive RFID Tags
Physically Unclonable Functions Using Foundry SRAM Cells
A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM
A Calibrated Phase and Amplitude Control System for a 1.9 GHz Phased-Array Transmitter Element
Low-Voltage Low-Power CMOS Rail-to-Rail Voltage-to-Current Converters
An Optically-Powered 432 MHz Wireless Tag for Batteryless Internet-of-Things Applications
Stabilization of Discrete-Time Systems With Multiple Actuator Delays and Saturations
Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style
Process-insensitive low-power design of switched-capacitor integrators
Neuromorphic Pitch Based Noise Reduction for Monosyllable Hearing Aid System Application
Nonlinear analysis of a cross-coupled quadrature harmonic oscillator
A Power-Area Efficient Geometry Engine With Low-Complexity Subdivision Algorithm for 3-D Graphics System
60-GHz CMOS Current-Combining PA With Adaptive Back-Off PAE Enhancement
A comment on "Globally exponential stability of neural networks with variable delays"
A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs
Analysis of the Signal Transfer and Folding in N-Path Filters With a Series Inductance
A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters
A Unifying Approach for Weighted and Diminished-1 Modulo 2 n+1 Addition
A High IIP2 Direct-Conversion Receiver Using Even-Harmonic Reduction Technique for Cellular CDMA/PCS/GPS Applications
Subthreshold CMOS Array for Generating a Gaussian Distribution of Currents
Optimizations of a Hardware Decoder for Deep-Space Optical Communications
Dissipativity of Singularly Perturbed Lur'e Systems
Self-Biased Unity-Gain Buffers With Low Gain Error
An Alternative Approach to Bode's Noise Theorem
Power-Supply and Substrate-Noise-Induced Timing Jitter in Nonoverlapping Clock Generation Circuits
Nonlinear Signal Classification in the Framework of High-Dimensional Shape Analysis in Reconstructed State Space
A Passivity-Preserving Frequency-Weighted Model Order Reduction Technique
On the Workload Dependence of Self-Heating in FinFET Circuits
Adaptive Blind Background Calibration of Polynomial-Represented Frequency Response Mismatches in a Two-Channel Time-Interleaved ADC
Time-Domain Synthesis of Continuous-Time Systems Based on Second-Order Cone Programming
Complementarity Model for Steady-State Analysis of Resonant LLC Power Converters
A Flexible and High Parallel Permutation Network for 5G LDPC Decoders
Fractional Frequency Synthesizers With Low Order Time-Variant Digital Sigma-Delta Modulator
A SIDIDO DC-DC Converter With Dual-Mode and Programmable-Capacitor-Array MPPT Control for Thermoelectric Energy Harvesting
Design Automation and Test Solutions for Digital Microfluidic Biochips
Equiripple Approximation of Half-Band FIR Filters
Silicon-Neuron Design: A Dynamical Systems Approach
All-Digital Frequency Synthesizer Using a Flying Adder
150-850 MHz High-Linearity Sine-wave Synthesizer Architecture Based on FIR Filter Approach and SFDR Optimization
Design of Tri-Band Balanced Filter With Wideband Common-Mode Suppression and Upper Stopband Using Square Ring Loaded Resonator
An Instant-Startup Jitter-Tolerant Manchester-Encoding Serializer/Deserializer Scheme for Event-Driven Bit-Serial LVDS Interchip AER Links
A New RNS based DA Approach for Inner Product Computation
Low-Harmonic Push-Pull Class-E Power Amplifier With a Pair of LC Resonant Networks
Bandwidth Compensation Technique for Digital PLL
A Study of Injection Locking in Dual-Band CMOS Frequency Dividers
A Hybrid Reducing Error Correcting Output Code for Lithology Identification
Performance Comparisons Between 7-nm FinFET and Conventional Bulk CMOS Standard Cell Libraries
Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space
Analysis and Specification of an IR-UWB Transceiver for High-Speed Chip-to-Chip Communication in a Server Chassis
MTJ-Based State Retentive Flip-Flop With Enhanced-Scan Capability to Sustain Sudden Power Failure
Theoretical Model of E n DP to Achieve Energy-Efficient SRAM
All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal
Bacterial Foraging Algorithm for Optimal Power Flow in Dynamic Environments
A general approach to waveform relaxation solutions of nonlinear differential-algebraic equations: the continuous-time and discrete-time cases
Fully Integrated High Voltage Pulse Driver Using Switched-Capacitor Voltage Multiplier and Synchronous Charge Compensation in 65-nm CMOS
A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications
Bias-Compensated Least Squares Identification of Distributed Thermal Models for Many-Core Systems-on-Chip
Inductorless DC/DC Converter for Aerospace Applications With Insulation Features
Efficient Look-Up-Table-Based Modeling for Robust Design of Σ∆ ADCs
A pure realization of loss-free resistor
Synchronization in Random Weighted Directed Networks
The Phase Characteristics for the Stability of 2-D Nonsymmetric Half-Plane Digital Allpass Filters
Low Complexity Generic VLSI Architecture Design Methodology for N th Root and N th Power Computations
A 400-nW 19.5-fJ/Conversion-Step 8-ENOB 80-kS/s SAR ADC in 0.18- muhboxm CMOS
Continuous-Time Coordination Algorithm for Distributed Convex Optimization Over Weight-Unbalanced Directed Networks
X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories
A positively self-feedbacked Hopfield neural network architecture for crossbar switching
A 3-Gb/s/ch Simultaneous Bidirectional Capacitive Coupling Transceiver for 3DICs
Filtering for Networked Stochastic Time-Delay Systems With Sector Nonlinearity
Boundary Scan Extension for Testing Distributed Reconfigurable Hardware Systems
A Low Voltage and Low Power 10-bit Non-Binary 2b/Cycle Time and Voltage Based SAR ADC
A 2.3 µW ECG-On-Chip for Wireless Wearable Sensors
Stabilizing Effects of Impulses in Delayed BAM Neural Networks
Globally Optimal Matching Networks With Lossy Passives and Efficiency Bounds
A Novel Digital Duty-Cycle Modulation Scheme for FPGA-Based Digital-to-Analog Conversion
25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections
Performance Limitation Analysis of Highly-Digital Time-Based Closed-Loop Sensor-to-Digital Converter Architectures
Memory-m Antipodal Processes: Spectral Analysis and Synthesis
Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits
A Compact and Low-Power CMOS Circuit for Fully Integrated NEMS Resonators
Fast- Frequency Offset Cancellation Loop Using Low-IF Receiver and Fractional-N PLL
Local Uniqueness for Nash Solutions of Multiparameter Singularly Perturbed Systems
Low-Voltage Current and Voltage Reference Design Based on the MOSFET ZTC Effect
Leakage effects in metal-connected floating-gate circuits
A Digital Golay-MPIC Time Domain Equalizer for SC/OFDM Dual-Modes at 60 GHz Band
Quantum switching and quantum merge sorting
Spurious-Free Dynamic Range of a Uniform Quantizer
A Low-Power, Wireless, Capacitive Sensing Frontend Based on a Self-Oscillating Inductive Link
A near real-time approach for convolutive blind source separation
1.5-V current-mode CMOS true RMS-DC converter based on class-AB transconductors
An Ultra-Low Power Binarized Convolutional Neural Network-Based Speech Recognition Processor With On-Chip Self-Learning
A Non-Linear Feedback Current Driver With Automatic Phase Compensation for Bioimpedance Applications
A connectivity based clustering algorithm with application to VLSI circuit partitioning
High-Order Mismatch-Shaping in Multibit DACs
Convergence Analysis of a Class of Nonsmooth Gradient Systems
Sinusoidal and Relaxation Oscillations in Source-Coupled Multivibrators
A K-Ka-Band Concurrent Dual-Band Single-Ended Input to Differential Output Low-Noise Amplifier Employing a Novel Transformer Feedback Dual-Band Load
Design-oriented estimation of thermal noise in switched-capacitor circuits
Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design
Closed-Form Critical Conditions of Instabilities for Constant On-Time Controlled Buck Converters
Quasi-orthogonal chaotic CDMA multi-user detection using optimal chaos synchronization
Optimal Fraction-Free Routh Tests for Complex and Real Integer Polynomials
Sampling and Reconstruction of Transient Signals by Parallel Exponential Filters
A Robust Channel Estimator for High-Mobility STBC-OFDM Systems
Dynamics of Task Allocation Based on Game Theory in Multi-Agent Systems
All-Digital High Resolution D/A Conversion by Dyadic Digital Pulse Modulation
1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS
Bitline Techniques With Dual Dynamic Nodes for Low-Power Register Files
Resource-Shared Crypto-Coprocessor of AES Enc/Dec With SHA-3
A CMOS Image Sensor for Multi-Level Focal Plane Image Decomposition
CMOS active-LC bandpass filters with coupled-inductor Q-enhancement and center frequency tuning
All-Digital Transmitter With a Mixed-Domain Combination Filter
A general-purpose processor-per-pixel analog SIMD vision chip
Calibrating Amplifiers Nonlinearity Using Comparator-Based ADCs
A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator
Double-Line Frequency Ripple Suppression of a Quasi-Single Stage AC-DC Converter
UWB CMOS Monocycle Pulse Generator
Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC
A Wideband Low-Noise Variable-Gain Amplifier With a 3.4 dB NF and up to 45 dB Gain Tuning Range in 130-nm CMOS
IIP2 Calibration by Injecting DC Offset at the Mixer in a Wireless Receiver
Correction to "Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter"
Detection and Correction Methods for Single Event Effects in Analog to Digital Converters
W-Band (92-100 GHz) Phased-Array Receive Channel With Quadrature-Hybrid-Based Vector Modulator
A Brief Introduction to Time-to-Digital and Digital-to-Time Converters
Minimum Power-Consumption Estimation in ROM-Based DDFS for Frequency-Hopping Ultralow-Power Transmitters
An Improved Stability Criterion for Digital Filters With Generalized Overflow Arithmetic and Time-Varying Delay
A 4-Channel 12-Bit High-Voltage Radiation-Hardened Digital-to-Analog Converter for Low Orbit Satellite Applications
Fractional Hilbert Transform Sampling Method and Its Filter Bank Reconstruction
A Low-Voltage Low-Power CMOS Analog Adaptive Equalizer for UTP-5 Cables
Design Methodology for Highly Reliable, High Performance ReRAM and 3-Bit/Cell MLC NAND Flash Solid-State Storage
A Resilient and Power-Efficient Automatic-Power-Down Sense Amplifier for SRAM Design
Analysis of Spectral Degradation and Error Compensation in 5G NR Digital Polar Transmitters
Still More on the 1/f 2 Phase Noise Performance of Harmonic Oscillators
On Finite-Time Stability of Linear Positive Differential-Algebraic Delay Equations
Optimal Synthesis of State-Estimate Feedback Controllers With Minimum l 2 -Sensitivity
A Multi-Class Objects Detection Coprocessor With Dual Feature Space and Weighted Softmax
Three-Layered Biased Memory Polynomial for Dynamic Modeling and Predistortion of Transmitters With Memory
Consensus of Multi-Agent Systems With Heterogeneous Input Saturation Levels
Blind Calibration of Timing Offsets for Four-Channel Time-Interleaved ADCs
Adaptive RFID Impedance Matching Based on Phase Difference for Oil Well Applications
Tunable SIW Bandpass Filters With Improved Upper Stopband Performance
Healing of DSP Circuits Under Power Bound Using Post-Silicon Operand Bitwidth Truncation
Hardware Implementation of an Improved Stochastic Computing Based Deep Neural Network Using Short Sequence Length
Realization of Multiple Transmission Zeroes for Bandpass Filters With Simple Inline Topology
Necessary and Sufficient Consensus Conditions of Descriptor Multi-agent Systems
A Self-Packaged Power Divider With Compact Size and Low Loss
Energy-Efficient Scheme for Multiple Scan-Chains BIST Using Weight-Based Segmentation
Monolithic Airflow Detection Chip With Automatic DC Offset Calibration
Improved Approach for Finite-Time Stability of Nonlinear Fractional-Order Systems With Interval Time-Varying Delay
Microstrip Tunable Diplexer With Separately-Designable Channels
Class-E MOSFET tuned power oscillator design procedure
Nonlinear feedback control of chaos in permanent magnet synchronous motor
A Wide-Band Fully-Integrated CMOS Ring-Oscillator PLL-Based Complex Dielectric Spectroscopy System
On the Minimum Number of States for Switchable Matching Networks
A Class of 1-Bit Multi-Step Look-Ahead Σ-Δ Modulators
Active Positive Sloped Equalizer for X-Band SiGe BiCMOS Phased Array Applications
Background Calibration With Piecewise Linearized Error Model for CMOS Pipeline A/D Converter
Reliability in Super- and Near-Threshold Computing: A Unified Model of RTN, BTI, and PV
A Generalized Combiner Synthesis Technique for Class-E Outphasing Transmitters
Quantization Noise Cancellation for FDC-Based Fractional-N PLLs
Mitigating Line Frequency Instability of Boost PFC Converter Under Proportional Outer-Voltage Loop With Additional Third Current-Harmonic Feedforward Compensation
Electronically Tunable Fully Integrated Fractional-Order Resonator
Low-Latency Unfolded-KES Architecture for Emerging Storage Class Memories
Implementation of Quantized-State System Models for a PLL Loop Filter Using Verilog-AMS
Noncausal IIR Fractional Hilbert Transformers With Equiripple or Flat Phase Response
Chaotic Oscillator-Based Binary Phase-Shift Keying
A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power
A critical analysis on global convergence of Hopfield-type neural networks
Gramian-Preserving Frequency Transformation and Its Application to Analog Filter Design
Background Calibration of Comparator Offsets in SHA-Less Pipelined ADCs
A Multibit Dual-Feedback CT DeltaSigma Modulator With Lowpass Signal Transfer Function
A Delta-Sigma Interface Circuit for Capacitive Sensors With an Automatically Calibrated Zero Point
Improved Delay-Dependent H infty Filtering Design for Discrete-Time Polytopic Linear Delay Systems
Wideband Techniques for Outphasing Power Amplifiers
Byte-Reconfigurable LDPC Codec Design With Application to High-Performance ECC of NAND Flash Memory Systems
Analytical Study of the Impacts of Stochastic Load Fluctuation on the Dynamic Voltage Stability Margin Using Bifurcation Theory
Low-Power Reconfigurable Processor Utilizing Variable Dual V DD
Characteristics of LNA Operation in Direct Delta-Sigma Receivers
An Interleaved Bi-Directional AC-DC Converter With Reduced Switches and Reactive Power Control
Power losses and efficiency of class-E power amplifier at any duty ratio
Understanding DC Behavior of Subthreshold CMOS Logic Through Closed-Form Analysis
Type-Based Group Delay Equalization Technique
On Die Bit Error Rate Estimator for NAND Flash Memory
Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses
Theory and Bandwidth Enhancement of Cascaded Double-Stage Distributed Amplifiers
Low-Complexity Echo and NEXT Cancellers for High-Speed Ethernet Transceivers
A Flexible Charge-Balanced Ratiometric Open-Loop Readout System for Capacitive Inertial Sensors
A 1-V 15-Bit Audio ΔΣ-ADC in 0.18 µm CMOS
Multi-Carrier Chaos Shift Keying: System Design and Performance Analysis
Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects
Understanding Early Indicators of Critical Transitions in Power Systems From Autocorrelation Functions
Nonlinear Tracking Controller for DC/DC Boost Converter Voltage Control Applications via Energy-Shaping and Invariant Dynamic Surface Approach
Implicit-Euler Implementation of Super-Twisting Observer and Twisting Controller for Second-Order Systems
Sampling and Reconstruction of Piecewise Constant Signals by Parallel CR -Network
Novel FEXT Cancellation and Equalization for High Speed Ethernet Transmission
A Phasor-Domain Study of Lock Range of Harmonic Oscillators With Multiple Injections
Transition Detector-Based Radiation-Hardened Latch for Both Single- and Multiple-Node Upsets
Dynamic Analysis of Digital Chaotic Maps via State-Mapping Networks
Exponential Stability, Semistability, and Boundedness of a Multi-ANF System
A 1-muhboxW 600- hboxppm/ circ hboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits
A Bio-Inspired Ultra-Energy-Efficient Analog-to-Digital Converter for Biomedical Applications
Robust Output Tracking of Delayed Boolean Networks Under Pinning Control
Multibit Delta-Sigma Modulator With Noise-Shaping Dynamic Element Matching
Continuous-time active-RC filter model for computer-aided design and optimization
Nonharmonic Injection-Locked Phase-Locked Loops With Applications in Remote Frequency Calibration of Passive Wireless Transponders
Continuous-time filter design optimized for reduced die area
Generating Grid Multiwing Chaotic Attractors by Constructing Heteroclinic Loops Into Switching Systems
Optimized Implementation of SIKE Round 2 on 64-bit ARM Cortex-A Processors
Concurrent Dual-Band Receiver Based on the Multi-Port Correlator for Wireless Applications
An Adaptive Denoising Algorithm for Improving Frequency Estimation and Tracking