yusuke1997/dblp-id-title huggingface dataset:
A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference
A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure
A Broadband Sensor Interface IC for Miniaturized Dielectric Spectroscopy From MHz to GHz
A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator
An arbitrary waveform stimulus circuit for visual prostheses using a low-area multibias DAC
A 14-32 GHz SiGe-BiCMOS Gilbert-Cell Frequency Doubler With Self-Adjusted Reduced Duty-Cycle Performance Enhancement
A 256×256 pixel smart CMOS image sensor for line-based stereo vision applications
220-GHz metamorphic HEMT amplifier MMICs for high-resolution imaging applications
A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC
A 0.0043-mm 2 0.3-1.2-V Frequency-Scalable Synthesized Fractional-N Digital PLL With a Speculative Dual-Referenced Interpolating TDC
Modeling, Design, and Verification for the Analog Front-End of a MEMS-Based Parallel Scanning-Probe Storage Device
Performance characteristics of SOI DRAM for low-power application
A CMOS transconductor with 80-dB SFDR up to 10 MHz
BodyWire: A 6.3-pJ/b 30-Mb/s -30-dB SIR-Tolerant Broadband Interference-Robust Human Body Communication Transceiver Using Time Domain Interference Rejection
A 600-MHz superscalar floating-point processor
A 3.5 V, 1.3 W GaAs power multi-chip IC for cellular phones
HERMES-Core - A 1.59-TOPS/mm 2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs
A 4.7-to-5.3-Gb/s Fault-Injection and Side-Channel Attack-Resistant AES-256 Engine Using Masked Isomorphic Composite Fields in Intel 4 CMOS
A Fully Integrated Buck Regulator With 2-GHz Resonant Switching for Low-Power Applications
A 24-GHz, +14.5-dBm fully integrated power amplifier in 0.18-μm CMOS
A Quantum Controller IC With DRAG Generation in 40-nm Cryo-CMOS for Scalable Superconducting Quantum Computing
A 10-MHz DAB Hysteretic Control Switching Power Converter for 5G IoT Power Delivery
50-Gb/s SiGe BiCMOS 4: 1 multiplexer and 1: 4 demultiplexer for serial communication systems
Content-addressable memory for VLSI pattern inspection
An integrated analog CMOS Viterbi detector for digital magnetic recording
A small chip size 2 W, 62% efficient HBT MMIC for 3 V PCN applications
A Low-Power GSM/EDGE/WCDMA Polar Transmitter in 65-nm CMOS
A VLSI grammar processing subsystem for a real-time large-vocabulary continuous speech recognition system
EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing
An RC Oscillator With Comparator Offset Cancellation
A double-sampling extended-counting ADC
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation
A clock feedthrough reduction circuit for switched-current systems
A 10-mA LDO With 16-nA IQ and Operating From 800-mV Supply
A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC
A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems
The Next Generation 64b SPARC Core in a T4 SoC Processor
A 1.9-mm-Precision 20-GHz Direct-Sampling Receiver Using Time-Extension Method for Indoor Localization
A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC
Generation of accurate on-chip time constants and stable transconductances
A 10-300-MHz IF-digitizing IC with 90-105-dB dynamic range and 15-333-kHz bandwidth
A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network
GaAs HBT 0.75-5 GHz multifunctional microwave-analog variable gain amplifier
A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller
A charge-trapping-based technique to design low-voltage BiCMOS logic circuits
A 16-Output 10-V Compliant Stimulator ASIC With Sub-10-nA Mismatch and Simultaneous ETI Sensing for Selective Neural Stimulation
A 20-W stereo class-D audio output power stage in 0.6-μm BCDMOS technology
Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue
Improving Linearity in CMOS Phase Interpolators
On the Design of Wideband Transformer-Based Fourth Order Matching Networks for E-Band Receivers in 28-nm CMOS
Active CMOS Sensor Array for Electrochemical Biomolecular Detection
A Resonant Current-Mode Wireless Power and Data Receiver for Loosely Coupled Implantable Devices
An Impedance and Multi-Wavelength Near-Infrared Spectroscopy IC for Non-Invasive Blood Glucose Estimation
A 0.85mm 2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD 2 Self-Suppression and Pulling Mitigation
A 40-Gb/s PAM-4 Transmitter Based on a Ring-Resonator Optical DAC in 45-nm SOI CMOS
A 1.8e - rms Temporal Noise Over 110-dB-Dynamic Range 3.4µm Pixel Pitch Global-Shutter CMOS Image Sensor With Dual-Gain Amplifiers SS-ADC, Light Guide Structure, and Multiple-Accumulation Shutter
Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits
A 12-bit intrinsic accuracy high-speed CMOS DAC
A Time-Interleaved SAR ADC With Bypass-Based Opportunistic Adaptive Calibration
A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage
A Monolithic 12.7 W/mm 2 , 92% Peak-Efficiency Switched-Capacitor DC-DC Converter Using CSCR-First Topology
Testing of differential cascade voltage switch (DCVS) circuits
A CMOS analog timing recovery circuit for PRML detectors
A low-power integrated tuner for cable telephony applications
A 1.5 GHz All-Digital Spread-Spectrum Clock Generator
An 8 GHz First-Order Frequency Synthesizer for Low-Power On-Chip Clock Generation
A 1.2- mu m CMOS current-controlled oscillator
A Methodology for Fast VSWR Protection Implemented in a Monolithic 3-W 55% PAE RF CMOS Power Amplifier
A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS
Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS
A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC
Time-of-Flight 3-D Imaging Pixel Structures in Standard CMOS Processes
Design of a built-in current sensor for I DDQ testing
A 0.18-µm CMOS SoC for a 100-m-Range 10-Frame/s 200 × 96-Pixel Time-of-Flight Depth Sensor
Spectral Breathing and Its Mitigation in Digital Fractional-N PLLs
Integrated circuits for data transmission over twisted-pair channels
A Switched-Capacitor RF Power Amplifier
A CMOS 1×-16× speed DVD write channel IC
An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC With <1.5-ps Uncalibrated Quantization Steps
Indirect Time-of-Flight CMOS Image Sensor With On-Chip Background Light Cancelling and Pseudo-Four-Tap/Two-Tap Hybrid Imaging for Motion Artifact Suppression
A 3-mW 1.0-GHz silicon-ECL dual-modulus prescaler IC
A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation
A high-frequency fully differential BiCMOS operational amplifier
A 4×64 pixel CMOS image sensor for 3-D measurement applications
A Low-Power CMOS Crystal Oscillator Using a Stacked-Amplifier Architecture
A static RAM chip with on-chip error correction
A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator
SiGe BiCMOS 3.3-V clock and data recovery circuits for 10-Gb/s serial transmission systems
Energy Efficient Monolithically Integrated 256 Gb/s Optical Transmitter With Autonomous Wavelength Stabilization in 45 nm CMOS SOI
A 10-Gb/s/ch, 0.6-pJ/bit/mm Power Scalable Rapid-ON/OFF Transceiver for On-Chip Energy Proportional Interconnects
A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance
A 2-V 2-GHz Si-bipolar direct-conversion quadrature modulator
An Ultra-High Input Impedance Analog Front End Using Self-Calibrated Positive Feedback
A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz
A 6.5-ns GaAs 20*20-b parallel multiplier with 67-ps gate delay
Sub-μWRComm: 415-nW 1-10-kb/s Physically and Mathematically Secure Electro-Quasi-Static HBC Node for Authentication and Medical Applications
A 110-MHz/1-Mb synchronous TagRAM
An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors
A 1.05 V 1.6 mW, 0.45°C 3σ Resolution ΣΔ Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process
A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Receiver and Antennas
A Reconfigurable and Extendable Single-Inductor Single-Path Three-Switch Converter for Indoor Photovoltaic Energy Harvesting
A 60-mW 200-MHz continuous-time seventh-order linear phase filter with on-chip automatic tuning system
A WCDMA/WLAN Digital Polar Transmitter With Low-Noise ADPLL, Wideband PM/AM Modulator, and Linearized PA
Design and Performance of a 600-W C -Band Amplifier Using Spatially Combined GaAs FETs for Satellite Communications
An audio ADC Delta-Sigma modulator with 100-dB peak SINAD and 102-dB DR using a second-order mismatch-shaping DAC
A 25-MS/s 14-b 200-mW ΣΔ Modulator in 0.18-μm CMOS
A 12-mW wide dynamic range CMOS front-end for a portable GPS receiver
A 3.9-μm pixel pitch VGA format 10-b digital output CMOS image sensor with 1.5 transistor/pixel
A fully balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector
Design of a Noncoherent 100-Gb/s 3-m Dual-Band PAM-4 Dielectric Waveguide Link in 28-nm CMOS
Two-dimensional 8×8 photoreceiver array and VCSEL drivers for high-throughput optical data links
High-density quaternary logic array chip for knowledge information processing systems
On-chip analog signal generation for mixed-signal built-in self-test
A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS
Resilient Self-V DD -Tuning Scheme With Speed-Margining for Low-Power SRAM
A 0.8 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for Time-Mode-Based Sigma Delta Modulator
A 65 nm Sub-V t Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter
Analysis and Design of High-Order QAM Direct-Modulation Transmitter for High-Speed Point-to-Point mm-Wave Wireless Links
A stabilization technique for phase-locked frequency synthesizers
Frequency limitations of a conventional phase-frequency detector
A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOS
A Resonant Current-Mode Wireless Power Receiver and Battery Charger With -32 dBm Sensitivity for Implantable Systems
A versatile high-speed bipolar charge-sensitive preamplifier for calorimeter applications
A 6-b 12-GSamples/s track-and-hold amplifier in InP DHBT technology
Ultra Fast Fixed-Frequency Hysteretic Buck Converter With Maximum Charging Current Control and Adaptive Delay Compensation for DVS Applications
A 14-bit 10- mu s subranging A/D converter with S/H
A 3-V fully differential distributed limiting driver for 40-Gb/s optical transmission systems
Electronic Temperature Compensation of Lateral Bulk Acoustic Resonator Reference Oscillators Using Enhanced Series Tuning Technique
The impact of NMOSFET hot-carrier degradation on CMOS analog subcircuit performance
A Fully Integrated Battery-Powered System-on-Chip in 40-nm CMOS for Closed-Loop Control of Insect-Scale Pico-Aerial Vehicle
A doughnut layout style for improved switching speed with CMOS VLSI gates
An 8.5-ns 112-b transmission gate adder with a conflict-free bypass circuit
A micropower programmable DSP using approximate signal processing based on distributed arithmetic
A 40-Gb/s Optical Transceiver Front-End in 45 nm SOI CMOS
A 3.58 nJ/Node Dual Cross Correlation Analog-Front-End Circuit With ADC for Mutual Capacitive Panel
Development of 60-GHz front-end circuits for a high-data-rate communication system
A 60-GHz Band 2 , ˟, 2 Phased-Array Transmitter in 65-nm CMOS
Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation
A Compute-in-Memory Annealing Processor With Interaction Coefficient Reuse and Sparse Energy Computation for Solving Combinatorial Optimization Problems
Introduction to 1998 Bipolar/BiCMOS Circuits and Technology Meeting
NeuralTree: A 256-Channel 0.227-μJ/Class Versatile Neural Activity Classification and Closed-Loop Neuromodulation SoC
Fully pipelined TSPC barrel shifter for high-speed applications
A GaN HEMT Class F Amplifier at 2 GHz With > 80% PAE
A MEMS Coriolis-Based Mass-Flow-to-Digital Converter for Low Flow Rate Sensing
Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO
A 6-Gb/s Wireless Inter-Chip Data Link Using 43-GHz Transceivers and Bond-Wire Antennas
A Low-EMI, High-DR Class-D Audio Amplifier With Double-Sided Voltage-Boosting Modulation
A new model for bipolar transistors at high current
An analog VLSI model of the jamming avoidance response in electric fish
Exploring Variability and Performance in a Sub-200-mV Processor
A 10-bit 50 MS/s Pipelined ADC With Capacitor-Sharing and Variable-g m Opamp
A 1 mA Ultra-Low-Power FHSS TX Front-End Utilizing Direct Modulation With Digital Pre-Distortion
Fixed-Switching-Frequency Background Capacitor-Current-Sensor Calibration for DC-DC Converters
Fully integrated voiceband codec in a standard digital CMOS technology
A 2.56-mm 2 718GOPS Configurable Spiking Convolutional Sparse Coding Accelerator in 40-nm CMOS
Ising-CIM: A Reconfigurable and Scalable Compute Within Memory Analog Ising Accelerator for Solving Combinatorial Optimization Problems
Comments on circuit models for MOSFET thermal noise
High-Voltage Analog System for a Mobile NAND Flash
A Continuous Time Multi-Bit Delta Sigma ADC Using Time Domain Quantizer and Feedback Element
A multi-level multi-phase charge-recycling method for low-power AMLCD column drivers
A Single-Chip Dual-Band CDMA2000 Transceiver in 0.13 µm CMOS
COMPAC: Compressed Time-Domain, Pooling-Aware Convolution CNN Engine With Reduced Data Movement for Energy-Efficient AI Computing
A 0.22 ps rms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter
An Accurate, Continuous, and Lossless Self-Learning CMOS Current-Sensing Scheme for Inductor-Based DC-DC Converters
A 14.8-μW Power and μ T rms Noise 3-D AC Magnetic Sensor in CMOS for Biomedical Applications
W-Band BPSK and QPSK Transceivers With Costas-Loop Carrier Recovery in 65-nm CMOS Technology
Trading speed for low power by choice of supply and threshold voltages
An Offset Compensated Charge Transfer Pre-Sensing Bitline Sense Amplifier
A Mixer Front End for a Four-Channel Modulated Wideband Converter With 62-dB Blocker Rejection
Frequency Switching in Dual-Resonance Oscillators
A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS
A 51.3-TOPS/W, 134.4-GOPS In-Memory Binary Image Filtering in 65-nm CMOS
A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth
A 4×112 Gb/s PAM-4 Silicon-Photonic Transmitter and Receiver Chipsets for Linear-Drive Co-Packaged Optics
A 400-MHz DA converter with a 4-bit color map for 2000-line display
An 8.6 mW 25 Mvertices/s 400-MFLOPS 800-MOPS 8.91 mm 2 Multimedia Stream Processor Core for Mobile Applications
A Near-Zero-Power Wake-Up Receiver Achieving -69-dBm Sensitivity
A 32×32-b adiabatic register file with supply clock generator
Design and Implementation of a Parallel Turbo-Decoder ASIC for 3GPP-LTE
Highly Integrated Guidewire Ultrasound Imaging System-on-a-Chip
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches
A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators
A 49-GHz preamplifier with a transimpedance gain of 52 dBΩ using InP HEMTs
Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors
Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design
A 10 b, 20 Msample/s, 35 mW pipeline A/D converter
Model for yield and manufacturing prediction on VLSI designs for advanced technologies, mixed circuitry, and memories
Compute SNDR-Boosted 22-nm MRAM-Based In-Memory Computing Macro Using Statistical Error Compensation
A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET
An Energy Recycling Envelope Tracking Supply Modulator Assisted by Small Cap Replica With 89.7% Efficiency and 37% Reduced Linear Amplifier Current for 150 MHz Bandwidth 5G New Radio RF Applications
Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC)
Sampled-data and continuous-time squarers in MOS technology
An adaptive checker for the fully differential analog code
An ultra-low-power, low-voltage electronic audio delay line for use in hearing aids
40-Gb/s high-power modulator driver IC for lightwave communication systems
A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage
High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs
A 1-V 24-GHz 17.5-mW phase-locked loop in a 0.18-μm CMOS process
Continuously variable gigahertz phase-shifter IC covering more than one frequency decade
An 86 mW 98GOPS ANN-Searching Processor for Full-HD 30 fps Video Object Recognition With Zeroless Locality-Sensitive Hashing
An architecture for a configurable mixed-signal device
A 360-fs-Time-Resolution 7-bit Stochastic Time-to-Digital Converter With Linearity Calibration Using Dual Time Offset Arbiters in 65-nm CMOS
Low-voltage high-speed switched-capacitor circuits without voltage bootstrapper
Terahertz Even-Order Subharmonic Mixer Using Symmetric MOS Varactors
Correction to "A 1 MHz Bandwidth, 6 GHz 0.18 μ m CMOS Type-I Delta Sigma Fractional-N Synthesizer for WiMAX Applications" [Dec 09 3244-3252]
An Embedded Stream Processor Core Based on Logarithmic Arithmetic for a Low-Power 3-D Graphics SoC
A rad-hard, low-noise, high-speed, BiFET charge preamplifier for warm liquid calorimetry in the SSC
A low-power, low-cost bipolar GPS receiver chip
Forward body bias for microprocessors in 130-nm technology generation and beyond
A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization
Programmable 2D linear filter for video applications
Frequency-Domain-Multiplexing Single-Wire Interface and Harmonic-Rejection-Based IF Data De-Multiplexing in Millimeter-Wave MIMO Arrays
RXO-LDPC: A Physics-Inspired Relaxation Oscillator-Based Solver Leveraging Six-Body Spin Interactions for Soft Decoding of LDPC Codes
A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS
A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion
A 2 dB NF Receiver With 10 mA Battery Current Suitable for Coexistence Applications
A broadband high-voltage SLIC for a splitter- and transformerless combined ADSL-Lite/POTS linecard
A Noise Circulating Oscillator
An object position and orientation IC with embedded imager
Simulating the current mirror with a self-heating BJT model
Shunting neural network photodetector arrays in analog CMOS
STS-768 multiplexer with full-rate output data retimer in InP HBT
A continuous-time ΣΔ ADC with increased immunity to interferers
An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage
A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery
Nanowatt Acoustic Inference Sensing Exploiting Nonlinear Analog Feature Extraction
A highly efficient CMOS line driver with 80-dB linearity for ISDN U-interface applications
A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques
A 1.2-A Dual-Output SC DC-DC Regulator With Continuous Gate-Drive Modulation Achieving ≤0.01-mV/mA Cross Regulation
A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability
A 375 × 365 high-speed 3-D range-finding image sensor using row-parallel search architecture and multisampling technique
A Pitch-Matched Transceiver ASIC With Shared Hybrid Beamforming ADC for High-Frame-Rate 3-D Intracardiac Echocardiography
0.13µm SiGe BiCMOS Technology Fully Dedicated to mm-Wave Applications
Phase Error Calibration Technique for Rotary Traveling Wave Oscillators
A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator
A 1.3-GOPS parallel DSP for high-performance image-processing applications
A 32*32-bit multiplier using multiple-valued MOS current-mode circuits
Introduction to the Special Section on the 2018 Custom Integrated Circuits Conference
An experimental 295 MHz CMOS 4K⨉256 SRAM using bidirectional read/write shared sense amps and self-timed pulsed word-line drivers
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays
Broad bandwidth transformer coupled differential amplifiers for high dynamic range
A 28-nm 28.8-TOPS/W Attention-Based NN Processor With Correlative CIM Ring Architecture and Dataflow-Reshaped Digital-Assisted CIM Array
A carry-free 54b×54b multiplier using equivalent bit conversion algorithm
A Reconfigurable Architecture Using a Flexible LO Modulator to Unify High-Sensitivity Signal Reception and Compressed-Sampling Wideband Signal Detection
Micromachined high-Q inductors in a 0.18-μm copper interconnect low-k dielectric CMOS process
A third-order multistage sigma-delta modulator with reduced sensitivity to nonidealities
A 65 nm 1 Gb 2b/cell NOR Flash With 2.25 MB/s Program Throughput and 400 MB/s DDR Interface
A CMOS 4.35-mW +22-dBm IIP3 Continuously Tunable Channel Select Filter for WLAN/WiMAX Receivers
A Broadband CMOS RF Front End for Direct Sampling Satellite Receivers
A Time-Domain Accuracy-Boosted Temperature Compensated Crystal Oscillator
An eight-user UMTS channel unit Processor for 3GPP base station applications
A fully bypassed six-issue integer datapath and register file on the Itanium-2 microprocessor
A very low-power CMOS mixed-signal IC for implantable pacemaker applications
An Energy Harvesting 2×2 60 GHz Transceiver With Scalable Data Rate of 38-2450 Mb/s for Near-Range Communication
A low-power baseband receiver IC for frequency-hopped spread spectrum communications
A wide-band, low-power, high slew rate voltage-feedback operational amplifier
A TTD-Based Fast Precise Localization Enabled by Passive-Active Signal Combiner With Negative-Capacitance Stabilized RAMP
A 3.2-V operation single-chip dual-band AlGaAs/GaAs HBT MMIC power amplifier with active feedback circuit technique
A fully integrated SOC for 802.11b in 0.18-μm CMOS
MOS charge pumps for low-voltage operation
An automatic temperature compensation of internal sense ground for subquarter micron DRAM's
Power and Area Minimization for Multidimensional Signal Processing
Circuit techniques for CMOS low-power high-performance multipliers
A 13.5-mW 185-Msample/s ΔΣ modulator for UMTS/GSM dual-standard IF reception
An Ultra-Thin Flexible CMOS Stress Sensor Demonstrated on an Adaptive Robotic Gripper
High-frequency CML clock dividers in 0.13-μm CMOS operating up to 38 GHz
A 15-Channel Digital Active Electrode System for Multi-Parameter Biopotential Measurement
Clock-deskew buffer using a SAR-controlled delay-locked loop
A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces
A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier
Extended Dynamic Range From a Combined Linear-Logarithmic CMOS Image Sensor
20-GHz low-noise amplifier with active balun in a 0.25-μm SiGe BICMOS technology
CMOS Doherty Amplifier With Variable Balun Transformer and Adaptive Bias Control for Wireless LAN Application
GaAs prescalers and counters for fast-settling frequency synthesizers
A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture
A 400 K-transistor CMOS sea-of-gates array with continuous track allocation