yusuke1997/dblp-id-title huggingface dataset:
Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits
Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming
A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package
VLSI implementation of a 100-μW multirate FSK receiver
A VTC/TDC-Assisted 4× Interleaved 3.8 GS/s 7b 6.0 mW SAR ADC With 13 GHz ERBW
A Low-Power Wideband Transmitter Front-End Chip for 80 GHz FMCW Radar Systems With Integrated 23 GHz Downconverter VCO
An Interface ASIC for MEMS Vibratory Gyroscopes With a Power of 1.6 mW, 92 dB DR and 0.007°/s/√Hz Noise Floor Over a 40 Hz Band
A unified submicrometer MOS transistor charge/capacitance model for mixed-signal IC's
A Fully Energy-Autonomous Temperature-to-Time Converter Powered by a Triboelectric Energy Harvester for Biomedical Applications
A 2.4-GHz 16-Phase Sub-Sampling Fractional-N PLL With Robust Soft Loop Switching
A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication
A 250-MHz-2-GHz wide-range delay-locked loop
IC reliability simulation
A 65 nm CMOS 30 dBm Class-E RF Power Amplifier With 60% PAE and 40% PAE at 16 dB Back-Off
A comparative study on the various monolithic low noise amplifier circuit topologies for RF and microwave applications
A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting ISO26262 ASIL B Standard
A sub-10-ps multiphase sampling system using redundancy
A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications
A fast locking and low jitter delay-locked loop using DHDL
A Wireless, Multicolor Fluorescence Image Sensor Implant for Real-Time Monitoring in Cancer Therapy
A 24-GHz CMOS front-end
1440 × 1080 pixel, 30 frames per second motion-JPEG 2000 codec for HD-movie transmission
A Continuous-Time Capacitance-to-Digital Converter for Floating-Target Displacement Sensing
A 90-nm CMOS 5-GHz Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise Cancellation
Transconductance amplifier structures with very small transconductances: a comparative design approach
A 78.5-dB SNDR Radiation- and Metastability-Tolerant Two-Step Split SAR ADC Operating Up to 75 MS/s With 24.9-mW Power Consumption in 65-nm CMOS
An efficient and flexible architecture for high-density gate arrays
Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC)
A Time-Interleaved Multimode ΔΣ RF-DAC for Direct Digital-to-RF Synthesis
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition
A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory
An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology
55-nm SiGe BiCMOS Distributed Amplifier Topologies for Time-Interleaved 120-Gb/s Fiber-Optic Receivers and Transmitters
A 48-Port FCC-Compliant 10GBASE-T Transmitter With Mixed-Mode Adaptive Echo Canceller
An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore Cluster
In Situ SRAM Static Stability Estimation in 65-nm CMOS
A second-order semidigital clock recovery circuit based on injection locking
A 54000-gate ECL array with substrate power supply
A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic
CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differentiaI-resistance devices
A 24-b 50-ns digital image signal processor
SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS
A 1.8 dB NF Blocker-Filtering Noise-Canceling Wideband Receiver With Shared TIA in 40 nm CMOS
Bipolar Microwave RMS Power Detectors
A Dual-Frequency Thermal Energy Harvesting Interface With Real-Time-Calculation ZCD
Two-Dimensions Vernier Time-to-Digital Converter
A high-slew integrator for switched-capacitor circuits
An analog DFE for disk drives using a mixed-signal integrator
A dynamic voltage scaled microprocessor system
Loop-based interconnect modeling and optimization approach for multigigahertz clock network design
A 28.8-mW Accelerator IC for Dark Channel Prior-Based Blind Image Deblurring
A Compact Wideband CMOS Low Noise Amplifier With Gain Flatness Enhancement
Digital FIR filters for high speed PRML disk read channels
A Dual-Loop Eight-Channel ECG Recording System With Fast Settling Mode for 12-Lead Applications
A Combined Series-Parallel Hybrid Envelope Amplifier for Envelope Tracking Mobile Terminal RF Power Amplifier Applications
An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback
A bipolar ECL static RAM using polysilicon-diode loaded memory cell
A video digital signal processor with a vector-pipeline architecture
An area model for on-chip memories and its application
A Beyond-1-Tb/s Coherent Optical Transmitter Front-End Based on 110-GHz-Bandwidth 2: 1 Analog Multiplexer in 250-nm InP DHBT
Design techniques for high-performance full-CMOS OTA-RC continuous-time filters
CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks
10+ gb/s 90-nm CMOS serial link demo in CBGA package
A 1-1-1-1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs
A Micropower Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer
A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS
SiGe-HBT-based 54-gb/s 4: 1 multiplexer IC with full-rate clock for serial communication systems
A 5-GHz direct-conversion CMOS transceiver
A 1.3-V 5-mW fully integrated tunable bandpass filter at 2.1 GHz in 0.35-μm CMOS
Content-addressable memory (CAM) circuits and architectures: a tutorial and survey
Parametric yield prediction of complex, mixed-signal IC's
An Energy-Efficient Deep Convolutional Neural Network Training Accelerator for In Situ Personalization on Smart Devices
A 0.8nV/⎷Hz CMOS preamplifier for IC-magneto-resistive read elements
Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter
A Harmonic-Selective Multi-Band Wireless Receiver With Digital Harmonic Rejection Calibration
A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications
A Passive W-Band Imaging Receiver in 65-nm Bulk CMOS
A Blocker-Tolerant Inductor-Less Wideband Receiver With Phase and Thermal Noise Cancellation
A 2 Gb/s Bi-Directional Inter-Chip Data Transceiver With Differential Inductors for High Density Inductive Channel Array
A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology
High-frequency characterization of on-chip digital interconnects
Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS
High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's
Extraction and modeling of self-heating and mutual thermal coupling impedance of bipolar transistors
An 8-Channel Scalable EEG Acquisition SoC With Patient-Specific Seizure Classification and Recording Processor
NB-IoT and GNSS All-In-One System-On-Chip Integrating RF Transceiver, 23-dBm CMOS Power Amplifier, Power Management Unit, and Clock Management System for Low Cost Solution
A 10-Gb/s, 0.03-mm 2 , 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology
A SiGe PA with dual dynamic bias control and memoryless digital predistortion for WCDMA handset applications
A Self-Calibration SCPA With Storage Capacitor Array Supporting 64-/256-/1024-QAM
An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC
Digital-IF WCDMA handset transmitter IC in 0.25-μm SiGe BiCMOS
Correction to "An IF Bandpass Filter Based on a Low Distortion Transconductor" [Dec 10 2634-2646]
A Self-Calibrated On-Chip Phase-Noise Measurement Circuit With -75 dBc Single-Tone Sensitivity at 100 kHz Offset
Reliability Characterization and Modeling Solution to Predict Aging of 40-nm MOSFET DC and RF Performances Induced by RF Stresses
Dynamic power optimization of active filters with application to zero-IF receivers
A Neuromorphic Chip Optimized for Deep Learning and CMOS Technology With Time-Domain Analog and Digital Mixed-Signal Processing
A Wideband RF Mixing-DAC Achieving IMD < -82 dBc Up to 1.9 GHz
An analog synchronous mirror delay for high-speed DRAM application
A Monolithic Resonant Switched-Capacitor Voltage Regulator With Dual-Phase Merged-LC Resonator
A 2.5-nW Radio Platform With an Internal Wake-Up Receiver for Smart Contact Lens Using a Single Loop Antenna
A Command-Aware Hybrid LDO With Ultra-Small Voltage Droop and Fast Settling Time for Power-Supply-Induced Jitter Mitigation in HBM Interfaces
IDDQ testing on a custom automotive IC
A CMOS OTA for HF filters with programmable transfer function
High-throughput asynchronous datapath with software-controlled voltage scaling
Amorphous silicon shift register for addressing output drivers
A Fast-Transient 500-mA Digitally Assisted Analog LDO With 30-μ V/mA Load Regulation and 0.0073-ps FoM in 65-nm CMOS
A 1.8-nW, -73.5-dB PSRR, 0.2-ms Startup Time, CMOS Voltage Reference With Self-Biased Feedback and Capacitively Coupled Schemes
An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor
A cascaded continuous-time ΣΔ Modulator with 67-dB dynamic range in 10-MHz bandwidth
An Injection Frequency-Locked Loop - Autonomous Injection Frequency Tracking Loop With Phase Noise Self-Calibration for Power-Efficient mm-Wave Signal Sources
Analysis and equalization of data-dependent jitter
Anti-blocker design techniques for MOSFET-C filters for direct conversion receivers
A sinh resistor and its application to tanh linearization
A 75.3-dB SNDR 24-MS/s Ring Amplifier-Based Pipelined ADC Using Averaging Correlated Level Shifting and Reference Swapping for Reducing Errors From Finite Opamp Gain and Capacitor Mismatch
A 125-600-MHz IF 75-dB DR Partially Time-Interleaved Bandpass DSM Based on Passive N-Path Filters
Physical design of testable VLSI: techniques and experiments
A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory
A Dual-Inductor Ladder Buck Converter for Li-Ion Battery-Operated Sub-Volt SoCs
A 25-GHz emitter degenerated LC VCO
Analysis of BiCMOS buffer for input voltages with finite rise time
Low-power clock-deskew buffer for high-speed digital circuits
A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator
A 16TX/16RX 60 GHz 802.11ad Chipset With Single Coaxial Interface and Polarization Diversity
A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS
An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Code-Counter-Based Offset Calibration
A single-chip 5-V 2400-b/s modem
A Fully-Integrated, Short-Range, Low Data Rate FM-UWB Transmitter in 90 nm CMOS
A bridge circuit for the characterization of electrically programmable elements
A monolithic GaAs-on-Si receiver front end for optical interconnect systems
A 0.3-to-1-GHz IoT Transmitter Employing Pseudo-Randomized Phase Switching Modulator and Single-Supply Class-G Harmonic Rejection PA
Improved RF Devices for Future Adaptive Wireless Systems Using Two-Sided Contacting and AlN Cooling
A 2.5-10-Gb/s CMOS transceiver with alternating edge-sampling phase detection for loop characteristic stabilization
A CMOS analog continuous-time delay line with adaptive delay-time control
Design of 1.8-mW PLL-Free 2.4-GHz Receiver Utilizing Temperature-Compensated FBAR Resonator
A 10-bit 205-MS/s 1.0-mm 2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications
A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process
On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs
A bipolar population counter using wave pipelining to achieve 2.5* normal clock frequency
A CMOS oversampling bandpass cascaded D/A converter with digital FIR and current-mode semi-digital filtering
On the design and characterization of femtoampere current-mode circuits
A novel power-off mode for a battery-backup DRAM
Circuit techniques for large CSEA SRAMs
A 345 mW Heterogeneous Many-Core Processor With an Intelligent Inference Engine for Robust Object Recognition
On the amplitude and phase errors of quadrature LC-tank CMOS oscillators
A 300-μW 2.4-GHz PVT-Insensitive Subthreshold Reference-Based LNA
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity
Dual-threshold voltage techniques for low-power digital circuits
A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector
MOSFET modeling for analog circuit CAD: problems and prospects
An image processing IC for backprojection and spatial histogramming in a pipelined array
A Low-Area and Fully Nonlinear 10-Bit Column Driver With Low-Voltage DAC and Switched-Capacitor Amplifier for Active-Matrix Displays
A 10-Gb/s high-isolation, 16×16 crosspoint switch implemented with AlGaAs/GaAs HBT's
A current-folded up-conversion mixer and VCO with center-tapped inductor in a SiGe-HBT technology for 5-GHz wireless LAN applications
A scaleable, statistical SPICE Gummel-Poon model for SiGe HBTs
Analysis and design of high-performance asynchronous sigma-delta Modulators with a binary quantizer
A Computing-in-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI
Design of submicrometer CMOS differential pass-transistor logic circuits
A 1.5-V 75-dB dynamic range third-order G m -C filter integrated in a 0.18-μm standard digital CMOS process
NTL with complementary emitter-follower driver: a high-speed low-power push-pull logic circuit
A Variation-Resilient Microprocessor With a Two-Level Timing Error Detection and Correction System in 28-nm CMOS
A 0.7V 24µA Hybrid OTA Driving 15 nF Capacitive Load With 1.46 MHz GBW
Class-AB high-swing CMOS power amplifier
A 10 mW Bluetooth Low-Energy Transceiver With On-Chip Matching
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs
A 16-b D/A converter with increased spurious free dynamic range
Potential and modeling of 1-μm SOI CMOS operational transconductance amplifiers for applications up to 1 GHz
Digitally adjustable resistors in CMOS for high-performance applications
A Single-Inductor Switching DC-DC Converter With Five Outputs and Ordered Power-Distributive Control
A 17-mW 0.66-mm 2 direct-conversion receiver for 1-Mb/s cable replacement
Resonant-Clock Latch-Based Design
A pixel-parallel image processor using logic pitch-matched to dynamic memory
On-die droop detector for analog sensing of power supply noise
A high-linearity 50- Omega CMOS differential driver for ISDN applications
Analog synthesis of nonlinear functions based on fuzzy logic
IC/microfluidic hybrid system for magnetic manipulation of biological cells
Comments on "A 100-MHz 100 dB operational amplifier with multipath nested Miller compensation structure" [and reply]
A Highly Linear Receiver Using Parallel Preselect Filter for 5G Microcell Base Station Applications
A 16-Mb MRAM featuring bootstrapped write drivers
Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance
Reference Oversampling PLL Achieving -256-dB FoM and -78-dBc Reference Spur
An Integrated ISFETs Instrumentation System in Standard CMOS Technology
A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces
DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications
An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter
A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter
Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency
Design and Test of a 175-Mb/s, Rate-1/2 (128, 3, 6) Low-Density Parity-Check Convolutional Code Encoder and Decoder
A 1024-QAM Analog Front-End for Broadband Powerline Communication Up to 60 MHz
A single-chip 2B1Q U-interface transceiver
A tiny, high-speed, wide-band, voltage-feedback amplifier stable with all capacitive load
MACC-SRAM: A Multistep Accumulation Capacitor-Coupling In-Memory Computing SRAM Macro for Deep Convolutional Neural Networks
A 167-Processor Computational Platform in 65 nm CMOS
Breakdown in millimeter-wave power InP HEMTs: a comparison with GaAs PHEMT's
A self-terminating low-voltage swing CMOS output driver
Product applications and technology directions with SiGe BiCMOS
A 2-V CMOS cellular transceiver front-end
RoboVisio: A Micro-Robot Vision Domain-Specific SoC for Autonomous Navigation Enabling Fully-on-Chip Intelligence via 2-MB eMRAM
A 13.3-Mb/s 0.35-μm CMOS analog turbo decoder IC with a configurable interleaver
A Multiphase Switched Capacitor Power Amplifier
An ISI Scrambling Technique for Dynamic Element Matching Current-Steering DACs
Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit
A self-calibration technique for monolithic high-resolution D/A converters
A 1.54-mm 2 , 264-GHz Wake-Up Receiver With Integrated Cryptographic Authentication for Ultra-Miniaturized Platforms
Introduction to the Special Issue on the 2014 Symposium on VLSI Circuits
Self-powered signal processing using vibration-based power generation
A Phase-Modulation Phase-Shifting Phased-Array Transmitter With Phase Self-Calibration and Deep PBOs Efficiency Enhancement
A BiCMOS time interval digitizer based on fully-differential, current-steering circuits
500-Mb/s nonprecharged data bus for high-speed DRAM's
A Low-Power Blocker-Tolerant Wideband Receiver With Bias-Tunable Mixer and Effective Switch Resistance Compensation
A Wake-Up Receiver With a Multi-Stage Self-Mixer and With Enhanced Sensitivity When Using an Interferer as Local Oscillator
A Multimodal CMOS MEA for High-Throughput Intracellular Action Potential Measurements and Impedance Spectroscopy in Drug-Screening Applications
A 0.6-V Dynamic Biasing Filter With 89-dB Dynamic Range in 0.18-µm CMOS
A Shock-Optimized SECE Integrated Circuit
A Polyphase Multipath Technique for Software-Defined Radio Transmitters
A 2.4 Gb/s receiver and a 1: 16 demultiplexer in one chip using a super self-aligned selectively grown SiGe base (SSSB) bipolar transistor
A 100×100 pixel silicon retina for gradient extraction with steering filter capabilities and temporal output coding
A 0.07-mm 2 162-mW DAC Achieving >65 dBc SFDR and < -70 dBc IM3 at 10 GS/s With Output Impedance Compensation and Concentric Parallelogram Routing
A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation technique
A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits
An 8.5 mW Continuous-Time ΔΣ Modulator With 25 MHz Bandwidth Using Digital Background DAC Linearization to Achieve 63.5 dB SNDR and 81 dB SFDR
A 100-m Range 10-Frame/s 340,x,96-Pixel Time-of-Flight Depth Sensor in 0.18-µm CMOS
A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture
A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme
Self-Convergent Trimming SRAM True Random Number Generation With In-Cell Storage
A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET
A Dither-Less All Digital PLL for Cellular Transmitters
A dynamic three-state memory cell for high-density associative processors
A 4-40 V Wide Input Range Boost Converter With the Protection Re-Cycling Technique for 200 W High Power LiDAR System in a Long-Distance Object Detection
A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing
A 0.186-pJ per Bit Latch-Based True Random Number Generator Featuring Mismatch Compensation and Random Noise Enhancement
50 mV-Input Batteryless Boost Converter for Thermal Energy Harvesting
An image-rejecting mixer and vector filter with 55-dB image rejection over process, temperature, and transistor mismatch
An Analysis of 1/f 2 Phase Noise in Bipolar Colpitts Oscillators (With a Digression on Bipolar Differential-Pair LC Oscillators)
Digital In-Memory Compute for Machine Learning Applications With Input and Model Security
A high-speed 128-kb MRAM core for future universal memory applications
A 70-μW 1.35-mm 2 Wireless Sensor With 32 Channels of Resistive and Capacitive Sensors and Edge-Encoded PWM UWB Transceiver
An Integrated Dual-Side Series/Parallel Piezoelectric Resonator-Based DC-DC Converter
A new wide-band input compensation for packaged analog and digital multigigabit IC's
A 900-MHz dual-conversion low-IF GSM receiver in 0.35-μm CMOS
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes
Design for velocity saturated, short-channel CMOS drivers with simultaneous switching noise and switching time considerations
A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS
Fractional-N DPLL-Based Low-Power Clocking Architecture for 1-14 Gb/s Multi-Standard Transmitter
A 65-nm Humanoid Robot System-on-Chip Using Time-Domain 3-D Footstep Planning and Mixed-Signal ZMP Gait Scheduler With Inverse Kinematics
Development of MMIC-based modules for multichannel RF/optical subcarrier multiplexed communications applications
A single-V t low-leakage gated-ground cache for deep submicron
A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs
A monolithic CMOS 2368±30 MHz transformer based Q-enhanced series-C coupled resonator bandpass filter
A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic
A 12.6 mW, 573-2901 kS/s Reconfigurable Processor for Reconstruction of Compressively Sensed Physiological Signals
Experimental investigation of the minimum signal for reliable operation of DRAM sense amplifiers
A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization
200-MHz superscalar RISC microprocessor
An Energy Efficient V PP Generator With Fast Ramp-Up Time for Mobile DRAM
A 2.1-MHz crystal oscillator time base with a current consumption under 500 nA
A wide-range and fast-locking all-digital cycle-controlled delay-locked loop
A Wideband Receiver Employing PWM-Based Harmonic Rejection Downconversion
Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment
All-MOS voltage-to-current converter
High-gain transimpedance amplifier in InP-based HBT technology for the receiver in 40-Gb/s optical-fiber TDM links
A 1 K×1 K high dynamic range CMOS image sensor with on-chip programmable region-of-interest readout
Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits
±CIM SRAM for Signed In-Memory Broad-Purpose Computing From DSP to Neural Processing
A field programmable analog array for CMOS continuous-time OTA-C filter applications
A wide-band RF front-end for multiband multistandard high-linearity low-IF wireless receivers
Low-power BiCMOS op-amp with integrated current-mode charge pump
A 10 Gb/s BiCMOS adaptive cable equalizer
A Fully Digital Delay Line Based GHz Range Multimode Transmitter Front-End in 65-nm CMOS
A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique
An integrated 200-MHz 3.3-V BiCMOS class-IV partial-response analog Viterbi decoder
A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs
A Low-Jitter Fractional-N Digital PLL Using a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial-Based LMS Calibration
A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations