yusuke1997/dblp-id-title huggingface dataset:
A Programmable and Configurable Mixed-Mode FPAA SoC
Timing-Based Placement Considering Uncertainty Due to Process Variations
A Framework for Layout-Dependent STI Stress Analysis and Stress-Aware Circuit Optimization
Adaptive Floating-Gate Circuit Enabled Large-Scale FPAA
Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis
On-Chip SOC Test Platform Design Based on IEEE 1500 Standard
Low-power digital systems based on adiabatic-switching principles
A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI
A 0.4-mW, 4.7-ps Resolution Single-Loop ΔΣ TDC Using a Half-Delay Time Integrator
Three-Dimensional Chips Can Be Cool: Thermal Study of VeSFET-Based 3-D Chips
Quasi-Static Voltage Scaling for Energy Minimization With Time Constraints
Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks
Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor
Product-Term-Based Synthesizable Embedded Programmable Logic Cores
Computing in Memory With Spin-Transfer Torque Magnetic RAM
History Index of Correct Computation for Fault-Tolerant Nano-Computing
Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers
A Two-Stage Large-Capacitive-Load Amplifier With Multiple Cross-Coupled Small-Gain Stages
Using dynamic cache management techniques to reduce energy in general purpose processors
MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip
Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient Applications
An Efficient Fast Switching Procedure for Stepwise Capacitor Chargers
Efficient exponentiation using weakly dual basis
The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators
Design of Power and Area Efficient Approximate Multipliers
A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing
Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization
Gate sizing for constrained delay/power/area optimization
Diagnosis of Logic Circuits Using Compressed Deterministic Data and On-Chip Response Comparison
Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed
In-Memory Transposable Multibit Multiplication Based on Diagonal Symmetry Weight Block
Special Section on Low-Power Electronics and Design
High-Performance NB-LDPC Decoder With Reduction of Message Exchange
A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects
Relaxed K-Best MIMO Signal Detector Design and VLSI Implementation
Multiple-parameter CMOS IC testing with increased sensitivity for I DDQ
A Utilitarian Approach to Variation Aware Delay, Power, and Crosstalk Noise Optimization
Domino logic with variable threshold voltage keeper
Digitally Controlled Pulse Width Modulator for On-Chip Power Management
Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for Heterogeneous 3-D SoCs
Approximate arithmetic coding for bus transition reduction in low power designs
A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures
Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems
A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding
Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead
On Database-Free Authentication of Microelectronic Components
RF Power Management via Energy-Adaptive Modulation for Self-Powered Systems
Crosstalk-Canceling Multimode Interconnect Using Transmitter Encoding
A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective
A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS
Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes
Guest Editorial: Special Section on Asynchronous Circuits and Systems
Analog Probe Module (APM) for Enhanced IC Observability: From Concept to Application
Multibit Content Addressable Memory Design and Optimization Based on 3-D nand-Compatible IGZO Flash
Temperature-Centric Reliability Analysis and Optimization of Electronic Systems Under Process Variation
Fast Analysis of Time Interval Error in Current-Mode Drivers
High performance level conversion for dual V DD design
Hardware Trojan Detection Through Chip-Free Electromagnetic Side-Channel Statistical Analysis
Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM
A Low-Power Low-Cost Design of Primary Synchronization Signal Detection
A 0.6-V Power-Efficient Active-RC Analog Low-Pass Filter With Cutoff Frequency Selection
0.84 ps Resolution Clock Skew Measurement via Subsampling
Security Evaluation of Balanced 1-of- n Circuits
Design and Optimization of Inductive-Coupling Links for 3-D-ICs
Wearout Resilience in NoCs Through an Aging Aware Adaptive Routing Algorithm
Runtime Resonance Noise Reduction with Current Prediction Enabled Frequency Actuator
A General Construction and Encoder Implementation of Polar Codes
The Configurable Hybrid Precoding Processor for Bit-Stream-Based mmWave MIMO Systems
Variation-Aware Reliable Many-Core System Design by Exploiting Inherent Core Redundancy
Statistical Leakage Estimation Based on Sequential Addition of Cell Leakage Currents
SRAM-Based Unique Chip Identifier Techniques
HYDRA: Heterodyne Crosstalk Mitigation With Double Microring Resonators and Data Encoding for Photonic NoCs
High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters
High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder
Efficiency, Stability, and Reliability Implications of Unbalanced Current Sharing Among Distributed On-Chip Voltage Regulators
Eliminating Minimum Implant Area Violations With Design Quality Preservation
A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design
Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage
Novel Low Overhead Post-Silicon Self-Correction Technique for Parallel Prefix Adders Using Selective Redundancy and Adaptive Clocking
A Model Splitting Approach to Improve Reliability and Accuracy for Alternate Test of Analog/Mixed-Signal Circuits
Accurate Timing and Noise Analysis of Combinational and Sequential Logic Cells Using Current Source Modeling
On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits
BF PUF: A Modeling Attack-Resistant Strong PUF Based on Bent Functions
A Three-Stage Comparator and Its Modified Version With Fast Speed and Low Kickback
Power-efficient flexible processor architecture for embedded applications
A 0.7-pJ/b 12.5-Gb/s Reference-Less Subsampling Clock and Data Recovery Circuit
A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random Access Memory
A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme
Information Storage Bit-Flipping Decoder for LDPC Codes
Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes
Optimizing FPGA Logic Circuitry for Variable Voltage Supplies
A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors
A Provably High-Probability White-Space Satisfaction Algorithm With Good Performance for Standard-Cell Detailed Placement
A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13-µm CMOS
Collaborative Multiobjective Global Routing
Thermal-Aware Design Method for Laser Group Control in Nanophotonic Interconnects
A Power-Efficient and Self-Adaptive Prediction Engine for H.264/AVC Decoding
Optimum and heuristic synthesis of multiple word-length architectures
Analog Circuit Design Using Symbolic Math Toolboxes: Demonstrative Examples
Task Migrations for Distributed Thermal Management Considering Transient Effects
Rate-optimal DSP synthesis by pipeline and minimum unfolding
Programmable active memories: reconfigurable systems come of age
Fully Digital, Standard-Cell-Based Multifunction Compute-in-Memory Arrays for Genome Sequencing
On Continuing DNN Accelerator Architecture Scaling Using Tightly Coupled Compute-on-Memory 3-D ICs
Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS
Characterization of Single-Electron Tunneling Transistors for Designing Low-Power Embedded Systems
Multivoltage Aware Resistive Open Fault Model
Automatic Test Stimulus Generation for Diagnosis of RF Transceivers Using Model Parameter Estimation
Reconfigurable Accelerator for the Word-Matching Stage of BLASTN
Efficient Synchronization for Embedded On-Chip Multiprocessors
A Near-Threshold Spiking Neural Network Accelerator With a Body-Swapping-Based In Situ Error Detection and Correction Technique
Parasitic-Aware Design of Integrated DC-DC Converters With Spiral Inductors
A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design
A Two-Dimensional Associative Processor
Modular design methodologies for image processing architectures
Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolutional Codes
A Case Study of Hardware/Software Partitioning of Traffic Simulation on the Cray XD1
Novel Magnetic Burn-In for Retention and Magnetic Tolerance Testing of STTRAM
A Single Ring-Oscillator-Based Test Structure for Timing Characterization of Dynamic Circuit
An Uncooled Microbolometer Infrared Imager With a Shutter-Based Successive-Approximation Calibration Loop
CVNS Synapse Multiplier for Robust Neurochips With On-Chip Learning
Battery-powered digital CMOS design
Delay testing of partially depleted silicon-on-insulator (PD-SOI) circuits
Guest editorial - system-level interconnect prediction
Beyond Rail-to-Rail Compliant Current Sources for Mismatch-Insensitive Voltage-to-Time Conversion
Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing
An Energy-Efficient High Resolution Vision Transformer Processor Exploiting Token Similarity Beyond Token Merging
Three Steps to the Thermal Noise Death of Moore's Law
An architecture and compiler for scalable on-chip communication
Low-power instruction bus encoding for embedded processors
Implementing Homomorphic Encryption-Based Logic Locking in System-On-Chip Designs
Microarchitecture-level power management
A Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks
Speech Processing on a Reconfigurable Analog Platform
A Special-Purpose Architecture for Solving the Breakpoint Median Problem
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template
MTTF Enhancement Power-C4 Bump Placement Optimization
Identification of Delay Measurable PDFs Using Linear Dependency Relationships
TCG: A transitive closure graph-based representation for general floorplans
A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine
ECOS: Stable Matching Based Metal-Only ECO Synthesis
An Efficient Two-Stage Pipelined Compute-in-Memory Macro for Accelerating Transformer Feed-Forward Networks
Potential Critical Path Selection Based on a Time-Varying Statistical Timing Analysis Framework
Design and Implementation of an Ultralow-Energy FFT ASIC for Processing ECG in Cardiac Pacemakers
Scalable Effort Hardware Design
8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing
A Refinement-Based Compositional Reasoning Framework for Pipelined Machine Verification
A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform
A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels
Soft-Start Method With Small Capacitor Charged by Pulse Current and Gain-Degeneration Error Amplifier for On-Chip DC-DC Power Converters
An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics
Achieving High-Performance On-Chip Networks With Shared-Buffer Routers
Time and Area Optimized Testing of Automotive ICs
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses
Overcoming Computational Errors in Sensing Platforms Through Embedded Machine-Learning Kernels
An I/O Efficient Model Checking Algorithm for Large-Scale Systems
UDSM Trends Comparison: From Technology Roadmap to UltraSparc Niagara2
A fast on-chip profiler memory using a pipelined binary tree
OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks
Algorithm-Driven Architectural Design Space Exploration of Domain-Specific Medical-Sensor Processors
Analysis and Optimization of Sense-and-Set Piezoelectric Energy Harvesting Interface Circuits
A Space Reuse Strategy for Flash Translation Layers in SLC NAND Flash Memory Storage Systems
Postbond Test of Through-Silicon Vias With Resistive Open Defects
Demystifying Iddq Data With Process Variation for Automatic Chip Classification
SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation
Fuzzy-based CMOS circuit partitioning in built-in current testing
SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model
Passivity Compensation Algorithm for Method-of-Characteristics-Based Multiconductor Transmission Line Interconnect Macromodels
A Reconfigurable Built-In Self-Test Scheme for the Evaluation Circuits of Digital SRAM-IMC Architectures
X-Align: Improving the Scan Cell Observability of Response Compactors
Bandwidth Adaptive Hardware Architecture of K-Means Clustering for Video Analysis
A Fast Locking-in and Low Jitter PLLWith a Process-Immune Locking-in Monitor
Provably Good Max-Min- m -Neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication
Novel Bio-Inspired Approach for Fault-Tolerant VLSI Systems
A Method to Extend Orthogonal Latin Square Codes
LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection
Soft digital signal processing
Efficient Execution of Temporal Convolutional Networks for Embedded Keyword Spotting
Incremental Fault Analysis: Relaxing the Fault Model of Differential Fault Attacks
A 3.6-mW 50-MHz PN Code Acquisition Filter via Statistical Error Compensation in 180-nm CMOS
Design of Sequential Elements for Low Power Clocking System
PITIA: an FPGA for throughput-intensive applications
Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing
A Printed Camouflaged Cell Against Reverse Engineering of Printed Electronics Circuits
IOLock: An Input/Output Locking Scheme for Protection Against Reverse Engineering Attacks
Voltage Reference With Linear-Temperature-Dependent Power Consumption
A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC
The Mesochronous Dual-Clock FIFO Buffer
Efficient CODEC Designs for Crosstalk Avoidance Codes Based on Numeral Systems
Properties of Digital Switching Currents in Fully CMOS Combinational Logic
Chaotic Encrypted Polar Coding Scheme for General Wiretap Channel
A 2-D Predistortion Based on Profile Inversion for Fully Digital Cartesian Transmitter
Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume
Efficient Soft Cancelation Decoder Architectures for Polar Codes
High-Efficiency Customized Coarse-Grained Dynamically Reconfigurable Architecture for JPEG2000
Optimum and heuristic transformation techniques for simultaneous optimization of latency and throughput
Hardware-Efficient, On-the-Fly, On-Implant Spike Sorter Dedicated to Brain-Implantable Microsystems
Circuit Modeling and Analysis of Memristor Crossbar Array-Based SNN With Spike-Mapping STDP Implementation
Low-Complexity Digit-Level Systolic Gaussian Normal Basis Multiplier
CVA6 RISC-V Virtualization: Architecture, Microarchitecture, and Design Space Exploration
Preprocessing of the Physical Leakage Information to Combine Side-Channel Distinguishers
On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors
A 128-Gbps Pipelined SM4 Circuit With Dual DPA Attack Countermeasures
Design and Applications of Approximate Circuits by Gate-Level Pruning
Flexible-Assignment Calibration Technique for Mismatch-Constrained Digital-to-Analog Converters
Inter-Tier Process-Variation-Aware Monolithic 3-D NoC Design Space Exploration
ATM switching architectures for wafer-scale integration
Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement
Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation
CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models
Enhancing Reliability of Analog Neural Network Processors
Power complexity of multiplexer-based optoelectronic crossbar switches
A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique
Fast Binary Counters Based on Symmetric Stacking
Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis
A micropower low-voltage multiplier with reduced spurious switching
An Energy and Performance Exploration of Network-on-Chip Architectures
Exploring the diversity of multimedia systems
Enabling High-Performance SMART NoC Architectures Using On-Chip Wireless Links
Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm
Energy-efficient issue queue design
A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase-Frequency-Error Compensation
Thermal-ADI - a linear-time chip-level dynamic thermal-simulation algorithm based on alternating-direction-implicit (ADI) method
A Performance-Aware MOSFET Threshold Voltage Measurement Circuit in a 65-nm CMOS
Dual-Rail Precharge Logic-Based Side-Channel Countermeasure for DNN Systolic Array
Resource Efficient Metering Scheme for Protecting SoC FPGA Device and IPs in IoT Applications
Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnects
Efficient Register Renaming and Recovery for High-Performance Processors
A Parallel Digital VLSI Architecture for Integrated Support Vector Machine Training and Classification
Robust RTL power macromodels
A Fully Synthesized 77-dB SFDR Reprogrammable SRMC Filter Using Digital Standard Cells
Accelerating Convolutional Neural Network With FFT on Embedded Hardware
A 75-Gb/s/mm 2 and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm
Design Obfuscation Through 3-D Split Fabrication With Smart Partitioning
SPIDER: Sizing-Priority-Based Application-Driven Memory for Mobile Video Applications
Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design
A Methodology for Transistor-Efficient Supergate Design
An Open-Loop VCO-ADC Based on a Linearized Current Control Technique
Noise Coupling Models in Heterogeneous 3-D ICs
A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck
Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing
A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache
STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies
LSM-Based Hotspot Prediction and Hotspot-Aware Routing in NoC-Based Neuromorphic Processor
A Novel Programmable Parallel CRC Circuit
A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits: A High-Speed FFE SST Transmitter Example
A Nanopower EEG Low-Pass Filter Using Current-Sharing Vertical Differential Pairs
Design and Implementation of Approximate DCT Architecture in Quantum-Dot Cellular Automata
A 100-mA, 99.11% Current Efficiency, 2-mV pp Ripple Digitally Controlled LDO With Active Ripple Suppression
Efficient Integer Frequency Offset Estimation Architecture for Enhanced OFDM Synchronization
Low Latency and Energy Efficient Scalable Architecture for Massive NoCs Using Generalized de Bruijn Graph
Reliable low-power digital signal processing via reduced precision redundancy
Architecture Design of a Memory Subsystem for Massive MIMO Baseband Processing
10-bit 100-MS/s Pipelined ADC Using Input-Swapped Opamp Sharing and Self-Calibrated V/I Converter
CASSER: A Closed-Form Analysis Framework for Statistical Soft Error Rate
Combinatorial Algorithms for Fast Clock Mesh Optimization
Cryptographic Accelerators for Digital Signature Based on Ed25519
Correction to "statistical clock skew modeling with data delay variations"
SMBHA: A System-Level Multicore BGV Hardware Accelerator Based on FPGA
Scan Test of Die Logic in 3-D ICs Using TSV Probing
Performance-oriented technology mapping for LUT-based FPGA's
EqualWrites: Reducing Intra-Set Write Variations for Enhancing Lifetime of Non-Volatile Caches
Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms
Synthesis of timed asynchronous circuits
Low-power MIMO signal processing
Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits
A 1-V, 16.9 ppm/ $^{\circ}$ C, 250 nA Switched-Capacitor CMOS Voltage Reference
Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique
FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations
A 43.6-dB SNDR 1-GS/s 3.2-mW SAR ADC With Background-Calibrated Fine and Coarse Comparators in 28-nm CMOS
Empirical models for net-length probability distribution and applications
A Time-Aware Fault Tolerance Scheme to Improve Reliability of Multilevel Phase-Change Memory in the Presence of Significant Resistance Drift
A 5-mm 2 , 4.7-μW Convolutional Neural Network Layer Accelerator for Miniature Systems
On-Chip Thermal Profiling to Detect Malicious Activity: System-Level Concepts and Design of Key Building Blocks
Exact moment matching model of transmission lines and application to interconnect delay estimation
ROPAD: Enhancing the Digital Ring Oscillator Probing Attempt Detector for Protecting Irregular Data Buses
Design automation with the TSPC circuit technique: a high-performance wave digital filter
A Processing Path Dispatcher in Network Processor MPSoCs
A Simplified Yield Model for SRAM Repair in Advanced Technology
Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors
Master-Slave Match Line Design for Low-Power Content-Addressable Memory
Upscale Layer Acceleration on Existing AI Hardware
Design and Implementation of Reconfigurable Asynchronous Pipelines
A 13-bit 8-kS/s Δ-Σ Readout IC Using ZCB Integrators With an Embedded Resistive Sensor Achieving 1.05-pJ/Conversion Step and a 65-dB PSRR
SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-Power SRAMs
Fine-Grained Fast Field-Programmable Gate Array Scrubbing
Fully Reused VLSI Architecture of FM0/Manchester Encoding Using SOLS Technique for DSRC Applications
A VLSI inner product macrocell
Scalable Multigigabit Pattern Matching for Packet Inspection
A Mixed-Mode Acceleration via Sparsity-Adjustable Pruning for Balancing Computation Density in Lightweight CNNs
BDD decomposition for delay oriented pass transistor logic synthesis
Product Code Schemes for Error Correction in MLC NAND Flash Memories
Design and Characterization of a Multilevel DRAM
Boostable Repeater Design for Variation Resilience in VLSI Interconnects
Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias
Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences
Efficient Neuromorphic Hardware Through Spiking Temporal Online Local Learning
Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration
A Processor-In-Memory Architecture for Multimedia Compression
An Area-Efficient Systolic Array Redundancy Architecture for Reliable AI Accelerator
Bias Temperature Instability Mitigation via Adaptive Cache Size Management
Prebond Testing of Weak Defects in TSVs
A 6-bit 2.5-GS/s Time-Interleaved Analog-to-Digital Converter Using Resistor-Array Sharing Digital-to-Analog Converter