yusuke1997/dblp-id-title huggingface dataset:
A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects
Fault detection and classification in linear integrated circuits: an application of discrimination analysis and hypothesis testing
SPICE-based mixed-mode S-parameter calculations for four-port and three-port circuits
Incremental Layer Assignment Driven by an External Signoff Timing Engine
Storage-Based Built-In Self-Test for Gate-Exhaustive Faults
Modular SOC testing with reduced wrapper count
Resource Management for Improving Soft-Error and Lifetime Reliability of Real-Time MPSoCs
Test Generation for Flow-Based Microfluidic Biochips With General Architectures
FAMOS: an efficient scheduling algorithm for high-level synthesis
A fast transistor-chaining algorithm for CMOS cell layout
Error Model Guided Joint Performance and Endurance Optimization for Flash Memory
An analysis of system level power management algorithms and theireffects on latency
Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits
COMPOSITE -- A Complete Modeling Program of Silicon Technology
Scalable Compact Modeling for On-Chip Passive Elements with Correlated Parameter Extraction and Adaptive Boundary Compression
Error Tolerance in Server Class Processors
On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors
A discretization scheme that allows coarse grid-spacing in finite-difference process simulation
Comment on "On Optimal Hyperuniversal and Rearrangeable Switch Box Designs"
Memory Partitioning for Parallel Multipattern Data Access in Multiple Data Arrays
A Deterministic Embedded End-System Tightly Coupled With TSN Schedule
Design of high-performance system-on-chips using communication architecture tuners
Shrinking wide compressors [BIST]
An Architecture-Level CPU Modeling Framework for Power and Other Design Qualities
Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis
Comments on "Filling algorithms and analyses for layout density control"
A Lightweight Nonlinear Methodology to Accurately Model Multicore Processor Power
OCMAS: Online Page Clustering for Multibank Scratchpad Memory
Electrothermal Simulation and Optimal Design of Thermoelectric Cooler Using Analytical Approach
Efficient Algorithms for Channel Routing
FairLight: Fairness-Aware Autonomous Traffic Signal Control With Hierarchical Action Space
Harnessing Unipolar Threshold Switches for Enhanced Rectification
Wideband passive multiport model order reduction and realization of RLCM circuits
On Refining Row-Based Detailed Placement for Triple Patterning Lithography
Improved force-directed scheduling in high-throughput digital signal processing
Distributed Deep Learning Optimization of Heat Equation Inverse Problem Solvers
Toward Fast Heterogeneous Virtual Prototypes: Increasing the Solver Efficiency in SystemC AMS
A Cross-Layer Framework for Temporal Power and Supply Noise Prediction
Logic Restructuring Using Node Addition and Removal
Efficient Parametric Yield Estimation Over Multiple Process Corners via Bayesian Inference Based on Bernoulli Distribution
EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations
A Numerical Solution of Poisson's Equation with Application to C-V Analysis of III-V Heterojunction Capacitors
A New Approach to Modeling Multiport Systems From Frequency-Domain Data
Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICs
Analysis of Velocity Saturation and Other Effects on Short-Channel MOS Transistor Capacitances
Accelerating Large-Scale Graph Neural Network Training on Crossbar Diet
CPS Oriented Control Design for Networked Surveillance Robots With Multiple Physical Constraints
Optimal min-area min-cut replication in partitioned circuits
Hardware-Friendly Delayed-Feedback Reservoir for Multivariate Time-Series Classification
FUZYE: A Fuzzy c -Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms
Reductions in quality caused by uneven fault coverage of different areas of an integrated circuit
Symbolic modeling of periodically time-varying systems usingharmonic transfer matrices
In-Route Pin Access-Driven Placement Refinement for Improved Detailed Routing Convergence
A circuit disassembly technique for synthesizing symbolic layouts from mask descriptions
Assignment of Vertical-Links to Routers in Vertically-Partially-Connected 3-D-NoCs
NRC: A Nibble Remapping Coding Strategy for NAND Flash Reliability Extension
Energy management using buffer memory for streaming data
Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks
Comments on "Test efficiency analysis of random self-test of sequential circuits"
STATION: State Encoding-Based Attack-Resilient Sequential Obfuscation
Minimal buffer insertion in clock trees with skew and slew rate constraints
NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints
Determining the Zeros and Poles of Linear Circuit Networks Using Function Approximation
A parallel algorithm for channel routing problems [VLSI]
SWAP: A Server-Scale Communication-Aware Chiplet-Based Manycore PIM Accelerator
Rethinking Latency-Aware DNN Design With GPU Tail Effect Analysis
Resilient Architectures via Collaborative Design: Maximizing Commodity Processor Performance in the Presence of Variations
A hexagonal array machine for multilayer wire routing
Application of statistical design and response surface methods to computer-aided VLSI device design
Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits
Low-Rank Quantum State Preparation
BIST-Based Fault Diagnosis for Read-Only Memories
Construction of Realistic Place-and-Route Benchmarks for Machine Learning Applications
A layout modification approach to via minimization
SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis
Compact Instruction Set Extensions for Kyber
An analysis of the probabilistic behavior of linear feedback signature registers
Modeling and Analysis of Image Dependence and Its Implications for Energy Savings in Error Tolerant Image Processing
A 3-D Split Manufacturing Approach to Trustworthy System Development
LESS-MICS: A Low Energy Standby-Sparing Scheme for Mixed-Criticality Systems
The Y architecture for on-chip interconnect: analysis and methodology
Hybrid Pass/Fail and Full Fail Data for Reduced Fail Data Volume
Multicycle Tests With Fault Detection Test Data for Improved Logic Diagnosis
Conflict-Free Parallel Data Access Technology for Matrix Calculation in Memory System of ASIP of 5G/6G Macro Base Stations
Rescuing RRAM-Based Computing From Static and Dynamic Faults
Assembling 2-D Blocks Into 3-D Chips
Wire space estimation and routability analysis
On the optimization of heterogeneous MDDs
CAMEL: Physically Inspired Crosstalk-Aware Mapping and Gate Scheduling for Frequency-Tunable Quantum Chips
Optimal routing of two rectangular blocks
Complete Security Solution for Practical Quantum Network Coding
Attack-Aware Detection and Defense to Resist Adversarial Examples
Switchbox routing by stepwise reshaping
Highly vectorizable fault simulation on the Cray X-MP supercomputer
ssr HLShbox-ssr pg: High-Level Synthesis of Power-Gated Circuits
Optimizing Training Efficiency and Cost of Hierarchical Federated Learning in Heterogeneous Mobile-Edge Cloud Computing
Processor array design with FPGA area constraint
Interactive Analog Layout Editing With Instant Placement and Routing Legalization
A Boundary Integral Equation Approach to Oxidation Modeling
Device Array Layout Synthesis With Nonlinear Gradient Compensation for a High-Accuracy Current-Steering DAC
Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement
A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems
CASPHAr: Cache-Managed Accelerator Staging and Pipelining in Heterogeneous System Architectures
TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC
LATICS: A Low-Overhead Adaptive Task-Based Intermittent Computing System
Minimum area joining of compacted cells
Geometric Pattern Match Using Edge Driven Dissected Rectangles and Vector Space
VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems
Eh?Predictor: A Deep Learning Framework to Identify Detailed Routing Short Violations From a Placed Netlist
Automatic Asset Identification for Assertion-Based SoC Security Verification
A Memristive Synapse Control Method to Generate Diversified Multistructure Chaotic Attractors
Nonintrusive Data-Driven Model Order Reduction for Circuits Based on Hammerstein Architectures
Sequential faults and aliasing
Low-power buffered clock tree design
SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism
CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design
Timed circuit verification using TEL structures
Defect-Tolerant Design and Optimization of a Digital Microfluidic Biochip for Protein Crystallization
Auto-Tuning CNNs for Coarse-Grained Reconfigurable Array-Based Accelerators
Synthesis of Multiplexed Biofluidic Microchips
High-Level Synthesis for Designing Multimode Architectures
Augmentation of SPICE for simulation of circuits containingresonant tunneling diodes
MOS 2 : an efficient MOnte Carlo Simulator for MOS devices
Sequential Equivalence Checking for Clock-Gated Circuits
Data-flow transformations for critical path time reduction in high-level DSP synthesis
Efficient Rare Failure Analysis Over Multiple Corners via Correlated Bayesian Inference
MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes
Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems
Toward Automated ECOs in FPGAs
A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVM
Hydrodynamic simulation of impact-ionization effects in p-n junctions
Simulation and modeling of p-n-p-n optical switches
Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction
OPASYN: a compiler for CMOS operational amplifiers
An efficient test vector compression scheme using selective Huffman coding
Semiconductor device simulation using adaptive refinement and flux upwinding
System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints
Wavelet Adaptivity for 3-D Device Simulation
Multicore Architectures With Dynamically Reconfigurable Array Processors for Wireless Broadband Technologies
pGRASS-Solver: A Graph Spectral Sparsification-Based Parallel Iterative Solver for Large-Scale Power Grid Analysis
A fast algorithm for area minimization of slicing floorplans
Closed-Form Capacitance Network Compact Model and Monte Carlo Analysis of the GIDL-Assisted Potential Growth in 3-D NAND Flash String
Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards
DiMO-CNN: Deep Learning Toolkit-Accelerated Analytical Modeling and Optimization of CNN Hardware and Dataflow
NCache: A Machine-Learning Cache Management Scheme for Computational SSDs
Learning-Based Power/Performance Optimization for Many-Core Systems With Extended-Range Voltage/Frequency Scaling
Context-Aware Graceful Degradation for Mixed-Criticality Scheduling in Autonomous Systems
Optimum design of IC power/ground nets subject to reliability constraints
An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding
A complete model of E 2 PROM memory cells for circuit simulations
SD-PUF: Spliced Digital Physical Unclonable Function
Iterative Diagnosis Approach for ECC-Based Memory Repair
Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability
Systematic and Automated Multiprocessor System Design, Programming, and Implementation
AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA
On-Chip Trust Evaluation Utilizing TDC-Based Parameter-Adjustable Security Primitive
Characterizing the Effect of Deadline Misses on Time-Triggered Task Chains
Critical area computation for missing material defects in VLSIcircuits
Hardware Compilation from an RTL to a Storage Logic Array Target
Analytical Modeling of Multiple Co-Existing Inaccuracies in RF Controlling Circuits for Superconducting Quantum Computing
Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Based on Cross-Interlocking
Reliable Hardware Architectures for Cryptographic Block Ciphers LED and HIGHT
Hardware Trojan Insertion in Finalized Layouts: From Methodology to a Silicon Demonstration
Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs
FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency
A Meyer-Like Approach for the Transient Analysis of Digital MOS IC's
A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs)
Theory and Analysis for Optimization of On-Chip Thermoelectric Cooling Systems
Observability Analysis on HDL Descriptions for Effective Functional Validation
A Built-In Self-Repair With Maximum Fault Collection and Fast Analysis Method for HBM
Effective iterative techniques for fingerprinting design IP
Modern Floorplanning Based on B * -Tree and Fast Simulated Annealing
Scaling Up Modulo Scheduling for High-Level Synthesis
An End-to-End In-Memory Computing System Based on a 40-nm eFlash-Based IMC SoC: Circuits, Toolchains, and Systems Co-Design Framework
Symbolic minimization of multilevel logic and the input encoding problem
Reducing Test Execution Cost of Integrated, Heterogeneous Systems Using Continuous Test Data
Fast batch incremental netlist compilation hierarchical schematics
An Integrated Logic Design Environment Based on Behavioral Description
Pitfalls in delay fault testing
Don't Care Computation and De Morgan Transformation for Threshold Logic Network Optimization
Aging Capacitor Supported Cache Management Scheme for Solid-State Drives
Online Training and Inference System on Edge FPGA Using Delayed Feedback Reservoir
Buried-channel MOSFET model for SPICE
Converting Flip-Flop to Clock-Gated 3-Phase Latch-Based Designs Using Graph-Based Retiming
SLIDER: Simulation of Layout-Injected Defects for Electrical Responses
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
Partial-scan delay fault testing of asynchronous circuits
Four-bend top-down global routing
An Analytical Placer for VLSI Standard Cell Placement
Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration
Accurate crosstalk noise modeling for early signal integrity analysis
A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel
Combinational automatic test pattern generation for acyclic sequential circuits
Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning
Small-Signal Analysis of Oscillators Using Generalized Multitime Partial Differential Equations
SHORTFINDER: a graphical CAD tool for locating net-to-net shorts in VLSI chip layouts
Graceful Register Clustering and Rebanking for Power and Timing Balancing
The User Interface and Implementation of an IC Layout Editor
Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach
STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment
Optimal algorithms for bubble sort based non-Manhattan channel routing
Timing models for gallium arsenide direct-coupled FET logic circuits
Algorithms for simultaneous escape routing and Layer assignment of dense PCBs
2-D CA variation with asymmetric neighborship for pseudorandom number generation
Design of Side-Channel-Resistant Power Monitors
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors
Highly Efficient Test Architecture for Low-Power AI Accelerators
A Database Approach to Communication in VLSI Design
Synthesis of nonzero clock skew circuits
Near-optimal critical sink routing tree constructions
Sibling-substitution-based BDD minimization using don't cares
Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination
A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach
On the Repair of Redundant RAM's
Three-dimensional nonequilibrium interface conditions for electron transport at band edge discontinuities
An Efficient EM-Based Synthesis Technique for Single-Band and Dual-Band Waveguide Filters
Field Programmable Stateful Logic Array
Knight: Optimizing Code Generation for Simulink Models With Loop Reshaping
Multiprocessor System-on-Chip (MPSoC) Technology
Pair-Bit Errors Aware LDPC Decoding in MLC NAND Flash Memory
An SMT Based Method for Optimizing Arithmetic Computations in Embedded Software Code
Multilevel verification of MOS circuits
Popularity-Based Online Scaling for RAID Systems Under General Settings
Learning Transfer-Based Adaptive Energy Minimization in Embedded Systems
Design and Experimentation of Inductorless Low-Pass NGD Integrated Circuit in 180-nm CMOS Technology
A New Necessary Condition for Threshold Function Identification
Chip Level Modeling of LSI Devices
A cell-based hierarchical pitchmatching compaction using minimal LP
ASYL: A Rule-Based System for Controller Synthesis
Iterative Probabilistic Performance Prediction for Multi-Application Multiprocessor Systems
Computing the area versus delay trade-off curves in technology mapping
DA PUF for IoT Security with 0.02% BER at 0.96 to 1.44 V and -40 °C to 125 °C
On the verification of sequential equivalence
An evaluation of parallel simulated annealing strategies with application to standard cell placement
Signal Delay in RC Tree Networks
SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips
Partially Specified Output Response for Reduced Fail Data Volume
Escaped Boundary Pins Routing for High-Speed Boards
Majority Logic Circuit Minimization Using Node Addition and Removal
Aging-Aware Critical Path Selection via Graph Attention Networks
SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm
Comments on "Handling soft modules in general nonslicing floorplan using Lagrangian relaxation"
FACT: a framework for applying throughput and power optimizing transformations to control-flow-intensive behavioral descriptions
EDF-VD Scheduling of Flexible Mixed-Criticality System With Multiple-Shot Transitions
GRASS: Graph Spectral Sparsification Leveraging Scalable Spectral Perturbation Analysis
A new class of iterative Steiner tree heuristics with good performance
Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices
Minimum buffered routing with bounded capacitive load for slew rate and reliability control
Enforcing Passivity of Parameterized LTI Macromodels via Hamiltonian-Driven Multivariate Adaptive Sampling
Edge separability-based circuit clustering with application to multilevel circuit partitioning
On VHV-routing in channels with irregular boundaries
Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation
Obstacle-Aware Clock-Tree Shaping During Placement
Stack-Size Sensitive On-Chip Memory Backup for Self-Powered Nonvolatile Processors
Information Entropy-Based Leakage Profiling
RBNN: Memory-Efficient Reconfigurable Deep Binary Neural Network With IP Protection for Internet of Things
Tangential vector finite elements for semiconductor device simulation
Improved deterministic test pattern generation with applications to redundancy identification
Tolerance Assignment for IC Selection Tests
WARM: Workload-Aware Reliability Management in Linux/Android
Contention-Aware Routing for Thermal-Reliable Optical Networks-on-Chip
A new testing method for EEPLA
On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling
Topological Structure and Physical Layout Co-Design for Wavelength-Routed Optical Networks-on-Chip
Sequential Circuits Synthesis for Rapid Single Flux Quantum Logic Based on Finite State Machine Decomposition
Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs
Analytical models for crosstalk excitation and propagation in VLSI circuits
Diagnosis of Malicious Bitstreams in Cloud Computing FPGAs
Critical path selection for delay fault testing based upon a statistical timing model
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
A general hierarchical circuit modeling and simulation algorithm
Time-Domain Orthogonal Finite-Element Reduction-Recovery Method for Electromagnetics-Based Analysis of Large-Scale Integrated Circuit and Package Problems
EMT: Elegantly Measured Tanner for Key-Value Store on SSD
VLSI Simulation and Data Abstractions
Efficient test access mechanism optimization for system-on-chip
Improved Launch for Higher TDF Coverage With Fewer Test Patterns
Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator
A DVFS-Weakly Dependent Energy-Efficient Scheduling Approach for Deadline-Constrained Parallel Applications on Heterogeneous Systems
Mixed-mode PISCES-SPICE coupled circuit and device solver
Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs"
MAPD: An FPGA-Based Real-Time Video Haze Removal Accelerator Using Mixed Atmosphere Prior
Using statecharts for hardware description and synthesis
An Efficient Hardware Design for Accelerating Sparse CNNs With NAS-Based Models
On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology
Substrate Current Modeling for Circuit Simulation
Some Modifications to Newton's Method for the Determination of the Steady-State Response of Nonlinear Oscillatory Circuits
Compiler-Based Techniques to Secure Cryptographic Embedded Software Against Side-Channel Attacks
Using Dummy Bridging Faults to Define Reduced Sets of Target Faults
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains
A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design
Compiler of Reed-Solomon Codec for 400-Gb/s IEEE 802.3bs Standard
Efficient N:M Sparse DNN Training Using Algorithm, Architecture, and Dataflow Co-Design
Easily testable gate-level and DCVS multipliers
STRAUSS: Spectral Transform Use in Stochastic Circuit Synthesis
Automated Controller and Sensor Configuration Synthesis Using Dimensional Analysis
Efficient test solutions for core-based designs
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors
Verification of timed circuits with failure-directed abstractions
Efficient Statistical Model Checking of Hardware Circuits With Multiple Failure Regions
Temperature-Aware Persistent Data Management for LSM-Tree on 3-D NAND Flash Memory
On Legalization of Die Bonding Bumps and Pads for 3-D ICs
On the Construction of Optimal Obstacle-Avoiding Rectilinear Steiner Minimum Trees
Verification of Camera-Based Autonomous Systems
Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees
A multi-probe approach for MCM substrate testing
FCDM: A Methodology Based on Sensor Pattern Noise Fingerprinting for Fast Confidence Detection to Adversarial Attacks
Efficient Non-Monte-Carlo Yield Estimation
Pin Assignment Optimization for Multi-2.5D FPGA-Based Systems With Time-Multiplexed I/Os
Correction to "An Approach for Multilevel Logic Optimization Targeting Low Power"
A Fast FPGA Connection Router Using Prerouting-Based Parallel Local Routing Algorithm
Physically Unclonable and Reconfigurable Computing System (PURCS) for Hardware Security Applications
Improvements to Statistical Characterization and Modeling, and a Caution to be Aware of Spurious Correlation in Statistical Simulation
A Numerically Efficient Formulation for Time-Domain Electromagnetic-Semiconductor Cosimulation for Fast-Transient Systems
An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs
OPIMA: Optical Processing-in-Memory for Convolutional Neural Network Acceleration