yusuke1997/dblp-id-title huggingface dataset:
Collaborative operating system and compiler power management for real-time applications
Security on FPGAs: State-of-the-art implementations and attacks
Simultaneous hardware and time redundancy with online task scheduling for low energy highly reliable standby-sparing system
Parametrised Modal Interface Automata
Low-energy off-chip SDRAM memory systems for embedded applications
TBES: Template-Based Exploration and Synthesis of Heterogeneous Multiprocessor Architectures on FPGA
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems
A TCAM-based Caching Architecture Framework for Packet Classification
Global Optimization of Fixed-Priority Real-Time Systems by RTOS-Aware Control-Flow Analysis
An efficient B-tree layer implementation for flash-memory storage systems
A Construction Kit for Efficient Low Power Neural Network Accelerator Designs
Generalized Weakly Hard Schedulability Analysis for Real-Time Periodic Tasks
MaxTracker: Continuously Tracking the Maximum Computation Progress for Energy Harvesting ReRAM-based CNN Accelerators
Verifying Stochastic Hybrid Systems with Temporal Logic Specifications via Model Reduction
A stochastic bitwidth estimation technique for compact and low-power custom processors
BTMonitor: Bit-time-based Intrusion Detection and Attacker Identification in Controller Area Network
Register Blocking: A Source-to-Source Analytical Modelling Approach for Affine Loop Kernels
Custom architecture for multicore audio beamforming systems
Fault Modeling in Discrete Event Systems Using Petri Nets
Joint WCET and Update Activity Minimization for Cyber-Physical Systems
Minimizing Stack and Communication Memory Usage in Real-Time Embedded Applications
Memory-Constrained Vectorization and Scheduling of Dataflow Graphs for Hybrid CPU-GPU Platforms
GPUrpc: Exploring Transparent Access to Remote GPUs
Predictive Monitoring with Logic-Calibrated Uncertainty for Cyber-Physical Systems
Static strands: Safely exposing dependence chains for increasing embedded power efficiency
Reducing branch predictor leakage energy by exploiting loops
Aggressive Energy Reduction for Video Inference with Software-only Strategies
XploreNAS : Explore Adversarially Robust and Hardware-efficient Neural Architectures for Non-ideal Xbars
Application-Level Evaluation of IEEE 802.1AS Synchronized Time and Linux for Distributed Real-Time Systems
MultiNets: A system for real-time switching between multiple network interfaces on mobile devices
Nonutilization bounds and feasible regions for arbitrary fixed-priority policies
Temporal Robustness of Temporal Logic Specifications: Analysis and Control Design
Video search and indexing with reinforcement agent for interactive multimedia services
Reordering Functions in Mobiles Apps for Reduced Size and Faster Start-Up
Exploiting Approximate MLC-PCM in Low-Power Embedded Systems
Cryptographic Engineering a Fast and Efficient SIKE in FPGA
Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls
Axiom: DTLS-Based Secure IoT Group Communication
Polar: Function Code Aware Fuzz Testing of ICS Protocol
Synergy: An HW/SW Framework for High Throughput CNNs on Embedded Heterogeneous SoC
ReconOS: Multithreaded programming for reconfigurable computers
Task scheduling: A control-theoretical viewpoint for a general and flexible solution
Designing Parameterizable Hardware IPs in a Model-Based Design Environment for High-Level Synthesis
Dynamic voltage scheduling with buffers in low-power multimedia applications
Dynamic delay-constrained minimum-energy dissemination in wireless sensor networks
ReachNN: Reachability Analysis of Neural-Network Controlled Systems
Robust Cause-Effect Chains with Bounded Execution Time and System-Level Logical Execution Time
A theory of robust omega-regular software synthesis
Timing analysis for preemptive multitasking real-time systems with caches
Improving Variational Autoencoder based Out-of-Distribution Detection for Embedded Real-time Applications
Counterexample Guided Abstraction Refinement for Polyhedral Probabilistic Hybrid Systems
A transformational perspective into the core of an abstract class loader for the SSP
Editorial: Fence Itself Grazing the Field - Security from the Sentries
Performance Modeling of Computer Vision-based CNN on Edge GPUs
Automatic Segmentation and Recognition in Body Sensor Networks Using a Hidden Markov Model
Access pattern-based memory and connectivity architecture exploration
Improving the Performance of Hybrid Caches Using Partitioned Victim Caching
A Cache-Based Flash Translation Layer for TLC-Based Multimedia Storage Devices
An analytical model for on-chip interconnects in multimedia embedded systems
THERMOS: Thermally-Aware Multi-Objective Scheduling of AI Workloads on Heterogeneous Multi-Chiplet PIM Architectures
Fast multidimension multichoice knapsack heuristic for MP-SoC runtime management
Modeling Distributed Real-Time Systems in TIOA and UPPAAL
A Compact and Parallel Swap-Based Shuffler Based on Butterfly Network and Its Complexity Against Side Channel Analysis
Hardware/software IP integration using the ROSES design environment
Attack-tolerant localization via iterative verification of locations in sensor networks
Early DSE and Automatic Generation of Coarse-grained Merged Accelerators
GPU-like on-chip system for decoding LDPC codes
Sensitivity of cache replacement policies
A study on parallelizing XML path filtering using accelerators
An Efficient UAV Hijacking Detection Method Using Onboard Inertial Measurement Unit
Communication Optimizations for Multithreaded Code Generation from Simulink Models
Low Overhead CS-Based Heterogeneous Framework for Big Data Acceleration
Iterational retiming with partitioning: Loop scheduling with complete memory latency hiding
A Unified Programmable Edge Matrix Processor for Deep Neural Networks and Matrix Algebra
Cool-Cache: A compiler-enabled energy efficient data caching framework for embedded/multimedia processors
Application-specific service technologies for commodity operating systems in real-time environments
A truly two-dimensional systolic array FPGA implementation of QR decomposition
Managing the Performance/Error Tradeoff of Floating-point Intensive Applications
Artistic image generation for emerging multimedia services by impressionist manner
A Closed-Loop Controller to Ensure Performance and Temperature Constraints for Dynamic Applications
A packet-switched network architecture for reconfigurable computing
Design and optimization of distributed sensing coverage in wireless sensor networks
Designing High-Performance and Thermally Feasible Multi-Chiplet Architectures Enabled by Non-Bendable Glass Interposer
Diwall: A Lightweight Host Intrusion Detection System Against Jamming and Packet Injection Attacks
A design flow for partially reconfigurable hardware
Addressing network-on-chip router transient errors with inherent information redundancy
Special issue on compilers, architecture, and synthesis for embedded systems
DPReF: Decentralized Key Generation Using Physical-Related Functions
Analysis and Scheduling of a Battery-Less Mixed-Criticality System with Energy Uncertainty
Prediction Modeling for Application-Specific Communication Architecture Design of Optical NoC
DyPO: Dynamic Pareto-Optimal Configuration Selection for Heterogeneous MpSoCs
Special issue on power-aware embedded computing
A robust seamless communication architecture for next-generation mobile terminals on multi-CPU SoCs
Energy efficient DVS schedule for fixed-priority real-time systems
The CURE: Cluster Communication Using Registers
Optimization of task allocation and priority assignment in hard real-time distributed systems
Optimizing Deep Learning Inference on Embedded Systems Through Adaptive Model Selection
Accelerated Fire Detection and Localization at Edge
CIMFlow: Modelling Dataflow in Cross-Layer Compute-in-Memory Deep Learning Accelerators
Half-Wits: Software Techniques for Low-Voltage Probabilistic Storage on Microcontrollers with NOR Flash Memory
Area-efficient convolutional deinterleaver for mobile TV receiver
A Lightweight Cryptographic Protocol with Certificateless Signature for the Internet of Things
Exploiting synchronous and asynchronous DVS for feedback EDF scheduling on an embedded platform
On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches
ECAx: Balancing Error Correction Costs in Approximate Accelerators
Specification Mining and Robust Design under Uncertainty: A Stochastic Temporal Logic Approach
Closed-loop-based self-adaptive Hardware/Software-Embedded systems: Design methodology and smart cam case study
A split-mask countermeasure for low-energy secure embedded systems
Robust Design and Validation of Cyber-physical Systems
Feasibility of semiring-based timing constraints
Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs
Sample Essentiality and Its Application to Modeling Attacks on Arbiter PUFs
HMDS: A Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems
SA-EAST: Security-Aware Efficient Data Transmission for ITS in Mobile Heterogeneous Cloud Computing
Timing Analysis of Synchronous Programs using WCRT Algebra: Scalability through Abstraction
Feasibility of Fork-Join Real-Time Task Graph Models: Hardness and Algorithms
Quantized Sparse Training: A Unified Trainable Framework for Joint Pruning and Quantization in DNNs
A system-level infrastructure for multidimensional MP-SoC design space co-exploration
Optimal Checkpointing Strategy for Real-time Systems with Both Logical and Timing Correctness
Self-configuring localization systems: Design and Experimental Evaluation
Efficient Automated Code Partitioning for Microcontrollers with Switchable Memory Banks
Guest Editorial for Special Issue Application of Concurrency to System Design
An Efficient and Flexible Stochastic CGRA Mapping Approach
SPMPool: Runtime SPM Management for Memory-Intensive Applications in Embedded Many-Cores
Editorial: Embedded, Cyber-Physical, Hybrid..
CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching
GNNmap: A Scalable Framework for GNN Deployment through Co-Optimized Graph Partitioning and Mapping
Exploring Inevitable Waypoints for Unsolvability Explanation in Hybrid Planning Problems
Management and optimization for nonvolatile memory-based hybrid scratchpad memory on multicore embedded processors
Rigorous rental memory management for embedded systems
The Perfect Getaway: Using Escape Analysis in Embedded Real-Time Systems
Cross-Layer Opportunistic Scheduling for Device-to-Device Video Multicast Services
Consistency vs. Availability in Distributed Cyber-Physical Systems
A passivity approach for model-based compositional design of networked control systems
Unified Medium Access Control Architecture for Resource-Constrained Machine-to-Machine Devices
Introduction to the two special issues on memory
A Vector-Length Agnostic Compiler for the Connex-S Accelerator with Scratchpad Memory
An approximation algorithm for scheduling on heterogeneous reconfigurable resources
Towards Efficient Multi-Frame Clustering in Response Time Analysis for Large Object Communication
Model-Based Design of Correct Controllers for Dynamically Reconfigurable Architectures
Elon: Enabling efficient and long-term reprogramming for wireless sensor networks
Securing Pacemakers Using Runtime Monitors over Physiological Signals
Analyzing and Visualizing Jump Performance Using Wireless Body Sensors
Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems
A Sliding Window Phase-Only Correlation Method for Side-Channel Alignment in a Smartphone
Beyond Cache Attacks: Exploiting the Bus-based Communication Structure for Powerful On-Chip Microarchitectural Attacks
Green-Energy-Powered Cognitive Radio Networks: Joint Time and Power Allocation
RAD-FS: Remote Timing and Power SCA Security in DVFS-augmented Ultra-Low-Power Embedded Systems
Code Generation for Neural Networks Based on Fixed-point Arithmetic
Simulating Reconfigurable Multiprocessor Systems-on-Chip with MPSoCSim
Hardware Architectures for Embedded Speaker Recognition Applications: A Survey
PredATW: Predicting the Asynchronous Time Warp Latency For VR Systems
Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs
Time-Series Forecasting and Sequence Learning Using Memristor-based Reservoir System
Timekeepers: ML-Driven SDF Analysis for Power-Wasters Detection in FPGAs
EACAN: Reliable and Resource-Efficient CAN Communications
Software thread integration for embedded system display applications
Message blinding method requiring no multiplicative inversion for RSA
Introduction to the Special Section on ESTIMedia'08
Formal Model-Based Synthesis of Application-Specific Static RTOS
Safety and Progress for Distributed Cyber-Physical Systems with Unreliable Communication
Autonomous OA Removal in Real-Time from Single Channel EEG Data on a Wearable Device Using a Hybrid Algebraic-Wavelet Algorithm
A hard real-time capable multi-core SMT processor
SystemC/C-based model-driven design for embedded systems
Miniaturized wireless ECG monitor for real-time detection of epileptic seizures
Exploiting Approximation for Run-time Resource Management of Embedded HMPs
Synthesis of application-specific highly efficient multi-mode cores for embedded systems
Analog In-memory Circuit Design of Polynomial Multiplication for Lattice Cipher Acceleration Application
A network congestion-aware memory subsystem for manycore
Fusing statecharts and java
Scalable precision cache analysis for real-time software
Telomere: Real-Time NAND Flash Storage
Loops in esterel
Secure reconfiguration of software-defined radio
3D CV Descriptor on Parallel Heterogeneous Platforms
Faster Implementation of Ideal Lattice-Based Cryptography Using AVX512
Automatic Update of Indoor Location Fingerprints with Pedestrian Dead Reckoning
An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems
Minimal placement of bank selection instructions for partitioned memory architectures
Quality/Latency-Aware Real-time Scheduling of Distributed Streaming IoT Applications
LARK: A Lightweight Authenticated ReKeying Scheme for Clustered Wireless Sensor Networks
A Load-Balancing Divide-and-Conquer SVM Solver
Why Data Deletion Fails? A Study on Deletion Flaws and Data Remanence in Android Systems
MxU: Towards Predictable, Flexible, and Efficient Memory Access Control for the Secure IoT
Introduction to the special section on ESTIMedia'11
A reliable gateway for in-vehicle networks based on LIN, CAN, and FlexRay
Adaptive wear-leveling algorithm for PRAM main memory with a DRAM buffer
Near optimal rate selection for wireless control systems
Optimized and Scalable Co-Processor for McEliece with Binary Goppa Codes
Performance Analysis of Reconfigurations in Adaptive Real-Time Streaming Applications
Free Rider: A Source-Level Transformation Tool for Retargeting Platform-Specific Intrinsic Functions
Interrupt handler migration and direct interrupt scheduling for rapid scheduling of interrupt-driven tasks
Cache-Related Preemption Delay Analysis for Multilevel Noninclusive Caches
Software-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory
Introduction to the Special Issue on Formal Methods and Models for System Design
Lightweight Implementations of NIST P-256 and SM2 ECC on 8-bit Resource-Constraint Embedded Device
Partitioned instruction cache architecture for energy efficiency
Trinity: Enabling Self-Sustaining WSNs Indoors with Energy-Free Sensing and Networking
Cross-layer customization for rapid and low-cost task preemption in multitasked embedded systems
A Hardware-Efficient Architecture for Accurate Real-Time Disparity Map Estimation
Link-time compaction and optimization of ARM executables
JOM: A Joint Operation Mechanism for NAND Flash Memory
Multicopy Cache: A Highly Energy-Efficient Cache Architecture
A retargetable framework for instruction-set architecture simulation
Quantitative Analysis of Systems Using Game-Theoretic Learning
Deep Q-Learning-Based Mobile Charger Path Planning in Wireless Powered Communication Networks
Adaptive Source-Level Data Assignment to Dual Memory Banks
DC4CD: A Platform for Distributed Computing on Constrained Devices
Editorial: Embedded everywhere for everyone
Hardware Trojan Detection using Transition Probability with Minimal Test Vectors
A Constructive State-based Semantics and Interpreter for a Synchronous Data-flow Language with State Machines
AppAxO : Designing Application-specific Approximate Operators for FPGA-based Embedded Systems
Memory-Efficient Mixed-Precision Implementations for Robust Explicit Model Predictive Control
AMP: Total Variation Reduction for Lossless Compression via Approximate Median-based Preconditioning
Guest Editorial: Special Issue on Virtual Prototyping of Parallel and Embedded Systems (ViPES)
Reconfigurable System-on-Chip Architectures for Robust Visual SLAM on Humanoid Robots
Coverage Preservation with Rapid Forwarding in Energy-Harvesting Wireless Sensor Networks for Critical Rare Events
Global and Partitioned Multiprocessor Fixed Priority Scheduling with Deferred Preemption
One-Step Look-Ahead Maximally Permissive Deadlock Control of AMS by Using Petri Nets
Exploiting Page Correlations for Write Buffering in Page-Mapping Multichannel SSDs
Efficient digit-serial normal basis multipliers over binary extension fields
LiSP: A lightweight security protocol for wireless sensor networks
Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system
Modeling and Analysis of TinyOS Sensor Node Firmware: A CSP Approach
Persistent Clocks for Batteryless Sensing Devices
RDF: A Reconfigurable Dataflow Model of Computation
Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers
Security challenges in embedded systems
An approach to manage reconfigurations and reduce area cost in hard real-time reconfigurable systems
Unified Testing and Security Framework for Wireless Network-on-Chip Enabled Multi-Core Chips
ARES: Persistently Secure Non-Volatile Memory with Processor-transparent and Hardware-friendly Integrity Verification and Metadata Recovery
Configurable memory security in embedded systems
System-level memory management based on statistical variability compensation for frame-based applications
Look-up the Rainbow: Table-based Implementation of Rainbow Signature on 64-bit ARMv8 Processors
An optimal memory allocation scheme for scratch-pad-based embedded systems
TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based Multicores
Toward Next Generation Quantum-Safe eIDs and eMRTDs: A Survey
Weakly Hard Schedulability Analysis for Fixed Priority Scheduling of Periodic Real-Time Tasks
A Scriptable Standard-Compliant Reporting and Logging Framework for SystemC
Using memory profile analysis for automatic synthesis of pointers code
Tractable schedulability analysis and resource allocation for real-time multimodal systems
Cache persistence analysis: Theory and practice
Editorial: Special issue on design challenges for many-core processors
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation
FlowPaP and FlowReR: Improving Energy Efficiency and Performance for STT-MRAM-Based Handheld Devices under Read Disturbance
A Java Processor IP Design for Embedded SoC
Improving Invariant Mining via Static Analysis
Luthier: Bridging Auto-Tuning and Vendor Libraries for Efficient Deep Learning Inference
UBAR: User- and Battery-aware Resource Management for Smartphones
MobiSense: Mobile body sensor network for ambulatory monitoring
System-level approach to the design of a smart distributed surveillance system using systemj
SPIMulator: A Spintronic Processing-in-memory Simulator for Racetracks
Adaptive loop caching using lightweight runtime control flow analysis
Multi-objective Exploration for Practical Optimization Decisions in Binary Translation
Lazy Load Scheduling for Mixed-criticality Applications in Heterogeneous MPSoCs
A Discrete Partial Charging Enabled Dynamic Programming Strategy for Optimal Fixed-Route Electric Vehicle Charging
Design Space Exploration for Ultra-Low-Energy and Secure IoT MCUs
Temperature-Aware Data Allocation for Embedded Systems with Cache and Scratchpad Memory
An Efficient Technique of Application Mapping and Scheduling on Real-Time Multiprocessor Systems for Throughput Optimization
FFConv: An FPGA-based Accelerator for Fast Convolution Layers in Convolutional Neural Networks
Application-Focused Energy-Fidelity Scalability for Wireless Motion-Based Health Assessment
Formal Validation of a Deterministic MAC Protocol
Optimizing AES-GCM on 32-Bit ARM Cortex-M4 Microcontrollers: Fixslicing and FACE-Based Approach
Application of Logical Sub-networking in Congestion-aware Deadlock-free SDmesh Routing
Formal Synthesis of Neural Barrier Certificates for Continuous Systems via Counterexample Guided Learning
A Multiple-FPGA parallel computing architecture for real-time simulation of soft-object deformation
Accurate and fast system-level power modeling: An XScale-based case study
Probabilistic Temporal Logic Falsification of Cyber-Physical Systems
Coscheduling of processor voltage and control task period for energy-efficient control systems
Optimus: An Operator Fusion Framework for Deep Neural Networks
Will My Program Break on This Faulty Processor?: Formal Analysis of Hardware Fault Activations in Concurrent Embedded Software
HDLRuby: A Ruby Extension for Hardware Description and Its Translation to Synthesizable Verilog HDL
On Improving the Performance of Intra- and Inter-chiplet Interconnection Networks in Multi-chiplet Systems for Accelerating FHE Encrypted Neural Network Applications
RQNoC: A Resilient Quality-of-Service Network-on-Chip with Service Redirection
Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling
A framework for flexible scheduling in the RTSJ
Contract Embeddings for Layered Control Architectures
Proactive Stripe Reconstruction to Improve Cache Use Efficiency of SSD-Based RAID Systems
Block Walsh-Hadamard Transform-based Binary Layers in Deep Neural Networks
Testing Preorders for dMTS: Deadlock- and the New Deadlock-/DivergenceTesting
Reliability-Aware Adaptations for Shared Last-Level Caches in Multi-Cores
Safety verification of hybrid systems by constraint propagation-based abstraction refinement
NeuroTAP: Thermal and Memory Access Pattern-Aware Data Mapping on 3D DRAM for Maximizing DNN Performance
On the Limitations of Analyzing Worst-Case Dynamic Energy of Processing
Efficient Table-based Function Approximation on FPGAs Using Interval Splitting and BRAM Instantiation
Evolution Function Based Reach-Avoid Verification for Time-varying Systems with Disturbances
PredictNcool: Leakage Aware Thermal Management for 3D Memories Using a Lightweight Temperature Predictor
Domain-specific Hybrid Mapping for Energy-efficient Baseband Processing in Wireless Networks
Editorial: Need for Artifact Verified Articles in ACM Transactions
Dynamic Thermal Management of 3D Memory through Rotating Low Power States and Partial Channel Closure
Interactive Trace-Based Analysis Toolset for Manual Parallelization of C Programs
A Framework for Neural Network Architecture and Compile Co-optimization
Model-based Toolchain for Core Flight System (cFS) Embedded Systems
Data embedding in image-media using weight-function on modulo operations
LazyTick: Lazy and Efficient Management of Job Release in Real-Time Operating Systems
ACM TECS Special Issue on Embedded System Security Tutorials
Ferroelectric Memory Technology for Big Data Applications
ScorePlus: A Software-Hardware Hybrid and Federated Experiment Environment for Smart Grid
Device-Free Motion & Trajectory Detection via RFID
Introduction to the Special Issue on Modeling and Verification of Discrete Event Systems
Security in embedded systems: Design challenges
Hardware support for detecting illegal references in a multiapplication real-time Java environment
DNN Inference Acceleration Based on Adaptive Task Partitioning and Offloading in Embedded VEC
Attack-resilient Fusion of Sensor Data with Uncertain Delays
Federated Self-training for Semi-supervised Audio Recognition