yusuke1997/dblp-id-title huggingface dataset:
Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion
An Efficient Parallel Processor for Dense Tensor Computation
Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit
Stream Processor for Real-Time Inverse Tone Mapping of Full-HD Images
Generation of Mixed Test Sets for Transition Faults
VLSI Implementation of a Soft-Output Signal Detector for Multimode Adaptive Multiple-Input Multiple-Output Systems
A 7.4-9.2-GHz Fractional-N Differential Sampling PLL Based on Phase-Domain and Voltage-Domain Hybrid Calibration
Accurate Reliability Boundary Evaluation of Approximate Arithmetic Circuit
List-GRAND: A Practical Way to Achieve Maximum Likelihood Decoding
Net-based force-directed macrocell placement for wirelength optimization
A 1 GHz Equiripple Low-Pass Filter With a High-Speed Automatic Tuning Scheme
Fibonacci Codes for Crosstalk Avoidance
Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation
A Low-Noise Area-Efficient Column-Parallel ADC With an Input Triplet for a 120-dB High Dynamic Range CMOS Image Sensor
Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs
Simulation Bounds for Equivalence Verification of Polynomial Datapaths Using Finite Ring Algebra
Elixir: High-Throughput Cost-Effective Dual-Field Processors and the Design Framework for Elliptic Curve Cryptography
Compact Current Source Models for Timing Analysis Under Temperature and Body Bias Variations
Energy-Efficient Syndrome Calculation Architecture for BCH Decoders
Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits
A Digital Two-Stage Phase Noise Compensation and rCFO/rSCO Tracking Module for mmW Single Carrier Systems
Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems
A circuit-driven design methodology for video signal-processing datapath elements
Hardware Trojan Detection Using Reconfigurable Assertion Checkers
Interleaving buffer insertion and transistor sizing into a single optimization
Integrated Energy-Harvesting Photodiodes With Diffractive Storage Capacitance
Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications
Parallel high-throughput limited search trellis decoder VLSI design
High Rate Data Synchronization in GALS SoCs
PALS: Distributed Gradient Clocking on Chip
Subthreshold Dual Mode Logic
Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures
Comments on "Carry checking/parity prediction adders and ALUs"
Design and Implementation of Power-Efficient K-Best MIMO Detector for Configurable Antennas
A Full Digital Fractional- N TAF-FLL for Digital Applications: Demonstration of the Principle of a Frequency-Locked Loop Built on Time-Average-Frequency
ADC-Assisted Random Sampler Architecture for Efficient Sparse Signal Acquisition
Systematic Software-Based Self-Test for Pipelined Processors
Low-power clock distribution using multiple voltages and reduced swings
Error Probability Models for Voltage-Scaled Multiply-Accumulate Units
An RRAM-Based Computing-in-Memory Architecture and Its Application in Accelerating Transformer Inference
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
A 5-GS/s 6-Bit 15.07-mW Flash ADC With Partially Active Second-Stage Comparison and 2× Time-Domain Interpolation
A CMOS MEMS Audio Transducer Implemented by Silicon Condenser Microphone With Analog Front-End Circuits of Audio Codec
Functional Broadside Templates for Low-Power Test Generation
A Unified Graphics and Vision Processor With a 0.89 µW/fps Pose Estimation Engine for Augmented Reality
A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning
Area-Aware Cache Update Trackers for Postsilicon Validation
Time-Multiplexed Compressed Test of SOC Designs
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory
R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors
MCF: A Metamodeling-Based Component Composition Framework - Composing SystemC IPs for Executable System Models
Design of On-Chip Lightweight Sensors for Effective Detection of Recycled ICs
Random Test Generation With Input Cube Avoidance
Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers
A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's
Real-Time Architecture for a Robust Multi-Scale Stereo Engine on FPGA
Reduced-Complexity Decoder Architecture for Non-Binary LDPC Codes
A 0.1-6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS
Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips
Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise
Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation
Energy-Adaptive Dual-Field Processor for High-Performance Elliptic Curve Cryptographic Applications
Static Power Side-Channel Analysis - An Investigation of Measurement Factors
Fast Substrate Noise Aware Floorplanning for Mixed Signal SOC Designs
VLSI circuits for low-power high-speed asynchronous addition
A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time
A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT With Twiddle Factor Compression and Conflict-Free Access
A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices
A 3.1 Gb/s 8 × 8 Sorting Reduced K-Best Detector With Lattice Reduction and QR Decomposition
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory
A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing
Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells
Current-Reused 2.4-GHz Direct-Modulation Transmitter With On-Chip Automatic Tuning
Statistical Functional Yield Estimation and Enhancement of CNFET-Based VLSI Circuits
A Novel Pixel Design for AM-OLED Displays Using Nanocrystalline Silicon TFTs
Robust Multiple-Phase Switched-Capacitor DC-DC Power Converter With Digital Interleaving Regulation Scheme
Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications
A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies
An Overview of a Compiler for Mapping Software Binaries to Hardware
HRM: M-Term Heterogeneous Hybrid Blend Recursive Multiplier for GF(2 n ) Polynomial
Fast Sign Detection Algorithm for the RNS Moduli Set 2 n+1 -1, 2 n -1, 2 n
Power Mapping of Integrated Circuits Using AC-Based Thermography
Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels
Side-Channel Hardware Trojan for Provably-Secure SCA-Protected Implementations
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology
Exploiting Replicated Cache Blocks to Reduce L2 Cache Leakage in CMPs
An Experimental Power-Lines Model for Digital ASICs Based on Transmission Lines
IVF: Characterizing the Vulnerability of Microprocessor Structures to Intermittent Faults
Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes
A low-power charge-recycling ROM architecture
Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses
Decoupling capacitors for multi-voltage power distribution systems
Broad-Brush Compaction for Sequential Test Generation
Test-Friendly Data-Selectable Self-Gating (DSSG)
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating
RF Power Gating: A Low-Power Technique for Adaptive Radios
PATH: Performance-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors
A Resource-Efficient and High-Accuracy CORDIC-Based Digital Implementation of the Hodgkin-Huxley Neuron
Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis
Design and Synthesis of Self-Healing Memristive Circuits for Timing Resilient Processor Design
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse
Retargetable pipeline hazard detection for partially bypassed processors
Synthesis of initializable asynchronous circuits
Allocation of Always-On State Retention Storage for Power Gated Circuits - Steady-State- Driven Approach
A 360° Tunable Phase Shifter With Low Phase Error Based on Bandpass Networks in 0.25- μm GaN Technology
A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-V DD Assist and Bitline Leakage Compensation
28-GHz CMOS VCO With Capacitive Splitting and Transformer Feedback Techniques for 5G Communication
EGRA: A Coarse Grained Reconfigurable Architectural Template
Zero-aliasing space compaction of test responses using multiple parity signatures
A Voltage Monitoring IC With HV Multiplexer and HV Transceiver for Battery Management Systems
Metastable-Dither-Based Digital Background Calibration of Interstage Gain Nonlinearity in Pipelined SAR ADC
Prelayout interconnect yield prediction
Reducing power consumption of turbo-code decoder using adaptive iteration with variable supply voltage
Enhancing Memory BIST With an Optimized RTL-BIST IP Core: A Low-Power, High-Fault-Coverage Approach
Multimode Radix-4 SISO Kernel Design for Turbo/LDPC Decoding
The Impact of Aging on a Physical Unclonable Function
A Comprehensive Digital Calibration for Pipelined ADCs Using Cascaded Nonlinearity Correction
SRMC: A Multibit Memristor Crossbar for Self-Renewing Image Mask
Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing
The Design of a Micro Power Management System for Applications Using Photovoltaic Cells With the Maximum Output Power Control
On general zero-skew clock net construction
Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block
Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip
MULTIPAR: behavioral partition for synthesizing multiprocessor architectures
Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping
Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits
Temperature Sensing RRAM Architecture for 3-D ICs
High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme
A CORDIC processor for FFT computation and its implementation using gallium arsenide technology
Analog and Mixed-Signal Layout Automation Using Digital Place-and-Route Tools
Guest editorial: special issue on on-chip inductance in high-speed integrated circuits
A Quiescent 407-nA Output-Capacitorless Low-Dropout Regulator With 0-100-mA Load Current Range
A High-Throughput Low-Complexity Radix-2 4 -2 2 -2 3 FFT/IFFT Processor With Parallel and Normal Input/Output Order for IEEE 802.11ad Systems
Behavioral simulation for analog system design verification
A clock-tuning circuit for system-on-chip
A 24-40-GHz Broadband Beamforming TRX Front-End IC With Unified Phase and Gain Control for Multiband Phased Array Systems
Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology
Efficient Modular Adder Designs Based on Thermometer and One-Hot Coding
A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology
Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures
Test Set Development for Cache Memory in Modern Microprocessors
A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma-Delta Modulator Using Dynamically Biased Op Amp Sharing
Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects
BIST-Based Fault Diagnosis for PCM With Enhanced Test Scheme and Fault-Free Region Finding Algorithm
Peak power estimation of VLSI circuits: new peak power measures
Routing on field-programmable switch matrices
Static task-scheduling algorithms for battery-powered DVS systems
Buffer delay change in the presence of power and ground noise
An improved BJT-based silicon retina with tunable image smoothing capability
CSRO-Based Reconfigurable True Random Number Generator Using RRAM
A Dual-Mode Continuous-Time Sigma-Delta Modulator With a Reconfigurable Loop Filter Based on a Single Op-Amp Resonator
Blocker-Tolerant Inductor-Less Harmonic Selection Wideband Receiver Front-End for 5G Applications
55-100-GHz Enhanced Gilbert Cell Mixer Design in 22-nm FDSOI CMOS
A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder
A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design
Energy-Aware Flash Memory Management in Virtual Memory System
A High-Performance and High-Robustness Triple-Node-Upset Tolerant Latch Based on Redundant-Node Hardening
Design and Implementation of a Low-Complexity Symbol Detector for Sparse Channels
High-Performance Concatenation Decoding of Reed-Solomon Codes With SPC Codes
Analysis of the Impact of Process Variations and Manufacturing Defects on the Performance of Carbon-Nanotube FETs
A Reconfigurable Multiple Transform Selection Architecture for VVC
On Microarchitectural Mechanisms for Cache Wearout Reduction
Marmotini: A Weight Density Adaptation Architecture With Hybrid Compression Method for Spiking Neural Network
A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fs RMS Jitter, -258.7-dB FOM, and -75.17-dBc Reference Spur
OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs With Optimized Exponent/Mantissa Widths
A Reconfigurable FIR Filter Architecture to Trade Off Filter Performance for Dynamic Power Consumption
An Area-Energy-Efficient 64-2048 Point FFT With Approximate Plane-Fitting Complex Multipliers
Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache
Quantifying and enhancing power awareness of VLSI systems
Framework for Fast Memory Authentication Using Dynamically Skewed Integrity Tree
Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques
A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA Design
IcoNoClast: Tackling Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms
Dynamic memory management methodology applied to embedded telecom network systems
FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing
A BIST TPG for Low Power Dissipation and High Fault Coverage
System-Level Counterfeit Detection Using On-Chip Ring Oscillator Array
Recurrence-Aware Instruction Set Selection for Extensible Embedded Processors
Design of Reversible Synchronous Sequential Circuits Using Pseudo Reed-Muller Expressions
High-Efficiency Data Conversion Interface for Reconfigurable Function-in-Memory Computing
Analysis of resistive bridging fault detection in BiCMOS digital ICs
Write-Amount-Aware Management Policies for STT-RAM Caches
EDDQC: Enhanced Dynamical Distributing Quantum Compilation
A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories
A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic
Performance evaluation for application-specific architectures
Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating
Infection-Based Dead Page Prediction in Hybrid Memory Architecture
High-Speed and Low-Latency ECC Processor Implementation Over GF(2 m ) on FPGA
Poly-Si-Based Physical Unclonable Functions
RISC-V-Based Evaluation and Strategy Exploration of MRAM Triple-Level Hybrid Cache Systems
Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach
A High-Performance Dual-Topology CMOS Rectifier With 19.5-dB Power Dynamic Range for RF-Based Hybrid Energy Harvesting
A Power-On-Reset Circuit With Accurate Trigger-Point Voltage and Ultralow Typical Quiescent Current for Emerging Nonvolatile Memory
A 65-nm CMOS 10-GS/s 4-bit Background-Calibrated Noninterleaved Flash ADC for Radio Astronomy
Multidie 3-D Stacking of Memory Dominated Neuromorphic Architectures
Design Exploration of Fault-Tolerant Deep Neural Networks Using Posit Number Representation System
The interpretation and application of Rent's rule
HDL presynthesis optimizations using a tabular model
Low-Voltage, Full-Swing Voltage-Controlled Oscillator With Symmetrical Even-Phase Outputs Based on Single-Ended Delay Cells
A 578-TOPS/W RRAM-Based Binary Convolutional Neural Network Macro for Tiny AI Edge Devices
Impact of Random Dopant Fluctuations on the Timing Characteristics of Flip-Flops
Enabling Voltage Over-Scaling in Multiplierless DSP Architectures via Algorithm-Hardware Co-Design
Addressing Partitioning Issues in Parallel Circuit Simulation
Low-Complexity Distributed-Arithmetic-Based Pipelined Architecture for an LSTM Network
Expression equivalence checking using interval analysis
Board- and Chip-Aware Package Wire Planning
The Effect of Multi-Bit Correlation on the Design of Field-Programmable Gate Array Routing Resources
Integrated Algorithm for 3-D IC Through-Silicon Via Assignment
ASNA-Flow: An Efficient Asynchronous Neuromorphic Accelerator for Real-Time Event-Based Optical Flow
HarTBleed: Using Hardware Trojans for Data Leakage Exploits
Novel Shared Multiplier Scheduling Scheme for Area-Efficient FFT/IFFT Processors
A 0.75-2.5-GHz All-Digital RF Transmitter With Integrated Class-E Power Amplifier for Spectrum Sharing Applications in 5G Radios
Power Efficiency of S-Boxes: From a Machine-Learning-Based Tool to a Deterministic Model
Breaking Analog Locking Techniques
Design Optimizations for Tiled Partially Reconfigurable Systems
A Supply Noise-Insensitive Ring DCO With a Self-Biased Shunt Regulator Array in Wide-Range Digital PLL
Automatic generation of error control codes for computer applications
Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors
Resource Efficient Implementation of Low Power MB-OFDM PHY Baseband Modem With Highly Parallel Architecture
A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation
1-V Low-Power Programmable Rail-to-Rail Operational Amplifier With Improved Transconductance Feedback Technique
Design of a Practical Nanometer-Scale Redundant Via-Aware Standard Cell Library for Improved Redundant Via1 Insertion Rate
Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits
A Process-Tolerant, Low-Voltage, Inverter-Based OTA for Continuous-Time Σ-Δ ADC
Low-Complexity Parallel Chien Search Architecture Based on Vandermonde Matrix Decomposition
Binary Multiplication Using Hybrid MOS and Multi-Gate Single-Electron Transistors
LBA Scrambler: A NAND Flash Aware Data Management Scheme for High-Performance Solid-State Drives
Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems
True-Damage-Aware Enumerative Coding for Improving nand Flash Memory Endurance
Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability
Multicast-Aware High-Performance Wireless Network-on-Chip Architectures
A Novel Digital-Controlled Current-Mode Single-Inductor-Multiple-Output Buck Converter With Individual Output Overload Protection
Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics
Fault Diagnosis for Resistive Random Access Memory and Monolithic Inter-Tier Vias in Monolithic 3-D Integration
Resource Based Optimization for Simultaneous Shield and Repeater Insertion
A 40-nm Training-Inference STT-MRAM Near-Memory Computing Macro for Memory-Augmented Neural Network Acceleration
Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness
Scheduling tests for VLSI systems under power constraints
A Way-Filtering-Based Dynamic Logical-Associative Cache Architecture for Low-Energy Consumption
Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits
A 0.5 V 1.28-MS/s 4.68-fJ/Conversion-Step SAR ADC With Energy-Efficient DAC and Trilevel Switching Scheme
A Low-Power Forward and Reverse Body Bias Generator in CMOS 40 nm
Frequency-Tuning Negative-Conductance Boosted Structure and Applications for Low-Voltage Low-Power Wide-Tuning-Range VCO
Compatible cell connections for multifamily dynamic logic gates
81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC
An Area-Efficient and Low-Power Multirate Decoder for Quasi-Cyclic Low-Density Parity-Check Codes
Electromigration-Aware Local-Via Allocation in Power/Ground TSVs of 3-D ICs
Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests
MeNTT: A Compact and Efficient Processing-in-Memory Number Theoretic Transform (NTT) Accelerator
Modeling and Optimization of Memristor and STT-RAM-Based Memory for Low-Power Applications
A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist
A High-Precision On-Chip Path Delay Measurement Architecture
A High-Performance Transparent Memory Data Encryption and Authentication Scheme Based on Ascon Cipher
Scheduling constraint generation for communicating processes
ClaPIM: Scalable Sequence Classification Using Processing-in-Memory
Restoration-Based Procedures With Set Covering Heuristics for Static Test Compaction of Functional Test Sequences
Instruction-Based Self-Testing of Delay Faults in Pipelined Processors
Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect
Application of Fixator-Norator Pairs in Designing Active Loads and Current Mirrors in Analog Integrated Circuits
Wire Sizing and Spacing for Lithographic Printability and Timing Optimization
Visual Vocabulary Processor Based on Binary Tree Architecture for Real-Time Object Recognition in Full-HD Resolution
Bayesian Prediction-Based Energy-Saving Algorithm for Embedded Intelligent Terminal
Taming Spatiotemporal Chaos in Forced Memristive Arrays
Speculative Carry Generation With Prefix Adder
Managing Trace Summaries to Minimize Stalls During Postsilicon Validation
Heterogeneous Monolithic 3-D IC Designs: Challenges, EDA Solutions, and Power, Performance, Cost Tradeoffs
A Novel NAND Flash Memory Architecture for Maximally Exploiting Plane-Level Parallelism
UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations
An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits
Online BIST and BIST-based diagnosis of FPGA logic blocks
An Area-Efficient VLSI Architecture for High-Throughput Computation of the 2-D DWT
Controlling the Reliability of SRAM PUFs With Directed NBTI Aging and Recovery
A High-Speed Word Level Finite Field Multiplier in BBF 2 m Using Redundant Representation
A High-Performance On-Chip Bus (MSBUS) Design and Verification
A Twofold Lookup Table Architecture for Efficient Approximation of Activation Functions
Novel Optimized Designs of Modulo 2 n +1 Adder for Quantum Computing
2.4-GHz 10-Mb/s BFSK Embedded Transmitter With a Stacked-LC DCO for Wireless Testing Systems
A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration
Detector for MLC NAND Flash Memory Using Neighbor-A-Priori Information
Multidevice Collaborative Power Management Through Decentralized Knowledge Sharing
Factored Systolic Arrays Based on Radix-8 Multiplication for Machine Learning Acceleration
Design of a 32 b monolithic microprocessor based on GaAs HMESFET technology
A 10-μ s Transient Recovery Time Low-EMI DC-DC Buck Converter With Δ - Δ Modulator
A Programmable and Reconfigurable CMOS Analog Hopfield Network for NP-Hard Problems