yusuke1997/dblp-id-title huggingface dataset:
Development of IoT-Based Impedometric Biosensor for Point-of-Care Monitoring of Bone Loss
Survey and Analysis of Cyclostationary Signal Detector Implementations on FPGA
Decentralized Suppression Strategy of Common Ground Circulating Current Caused by Grounding Fault in PV Modules in Single-Phase PV Grid-Connected Systems
An Energy-Efficient Sleep Scheduling With QoS Consideration in 3GPP LTE-Advanced Networks for Internet of Things
Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue)
DPCM-Based Edge Prediction for Lossless Screen Content Coding in HEVC
MADS: A Framework for Design and Implementation of Adaptive Digital Predistortion Systems
Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing
Multi-Level Mapping of Nanocomputer Architectures Based on Hardware Reuse
Energy-Quality Scalable Integrated Circuits and Systems: Continuing Energy Scaling in the Twilight of Moore's Law
Converter-Gating: A Power Efficient and Secure On-Chip Power Delivery System
Minimal Realizations for Some Classes of Fractional Order Transfer Functions
Low-Power Scalable 3-D Face Frontalization Processor for CNN-Based Face Recognition in Mobile Devices
Quantum Cryptanalysis of Affine Cipher
MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine
3-D Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS
Operating Coupled VO₂-Based Oscillators for Solving Ising Models
Guest Editorial 2.5D/3D Chiplet Circuits and Systems, EDA, Advanced Packaging, and Test - Part I
A Single-MOSFET Analog High Resolution-Targeted (SMART) Multiplier for Machine Learning Classification
Data-Driven Distributed Online Learning Control for Islanded Microgrids
Programmable Metamaterials for Software-Defined Electromagnetic Control: Circuits, Systems, and Architectures
Bipolar Resistive RAM Based on HfO 2 : Physics, Compact Modeling, and Variability Control
TPE: A Hardware-Based TLB Profiling Expert for Workload Reconstruction
Syndrome-Enabled Unsupervised Learning for Neural Network-Based Polar Decoder and Jointly Optimized Blind Equalizer
Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects
A Systematic Approach for Implementing Fractional-Order Operators and Systems
To Spike or Not to Spike: A Digital Hardware Perspective on Deep Learning Acceleration
Objective Quality Assessment for Image Retargeting Based on Structural Similarity
Edge of Chaos Explains Prigogine's Instability of the Homogeneous
VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing
A Two-Tier System for On-Demand Streaming of 360 Degree Video Over Dynamic Networks
A Reconfigurable DT ΔΣ Modulator for Multi-Standard 2G/3G/4G Wireless Receivers
A Framework for Dynamic Stability Analysis of Power Systems With Volatile Wind Power
Optimizing Temporal Convolutional Network Inference on FPGA-Based Accelerators
SoftCharge: Software Defined Multi-Device Wireless Charging Over Large Surfaces
Investigating Packet Transmission From the Perspective of Complex Networks Composed of Chaotic Circuits
A Hybrid Strategy for the Discovery and Design of Photonic Structures
Automatic Fall Detection and Activity Classification by a Wearable Embedded Smart Camera
Low-Power MCU With Embedded ReRAM Buffers as Sensor Hub for IoT Applications
Fast and Robust Compressive Sensing Method Using Mixed Hadamard Sensing Matrix
Opportunities and Challenges of Using Plasmonic Components in Nanophotonic Architectures
Fractional Order Butterworth Filter: Active and Passive Realizations
Transfer Learning for Semi-Supervised Automatic Modulation Classification in ZF-MIMO Systems
Sticker-Type Hybrid Photoplethysmogram Monitoring System Integrating CMOS IC With Organic Optical Sensors
Dynamic Inertia Evaluation for type-3 Wind Turbines Based on Inertia Function
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture
Adaptive Security Control Against False Data Injection Attacks in Cyber-Physical Systems
Dynamic-HDC: A Two-Stage Dynamic Inference Framework for Brain-Inspired Hyperdimensional Computing
Quality and Error Robustness Assessment of Low-Latency Lightweight Intra-Frame Codecs for Screen Content Compression
A Reconfigurable Spatial Architecture for Energy-Efficient Inception Neural Networks
Attention-Based Activation Pruning to Reduce Data Movement in Real-Time AI: A Case-Study on Local Motion Planning in Autonomous Vehicles
Design and Applications of a 300-800 MHz Tunable Matching Network
A Perspective on Test Methodologies for Supervised Machine Learning Accelerators
Memristor Crossbar Tiles in a Flexible, General Purpose Neural Processor
Characterizing a Heterogeneous System for Person Detection in Video Using Histograms of Oriented Gradients: Power Versus Speed Versus Accuracy
On the Distribution of Clique-Based Neural Networks for Edge AI
Motion Compensation for an Unmanned Aerial Vehicle Remote Radar Life Sensor
QS-NAS: Optimally Quantized Scaled Architecture Search to Enable Efficient On-Device Micro-AI
Quantum Actin Automata and Three-Valued Logics
A Versatile Wireless Portable Monitoring System for Brain-Behavior Approaches
Guest Editorial: Integrated Devices, Circuits, and Systems for the 6G Era
EDAS: Enabling Fast Data Loading for GPU Serverless Computing
Towards Optimizing Learned Index for High Performance, Memory Efficiency and NUMA Awareness
Tolerating process variations in large, set-associative caches: The buddy cache
Performance scalability of decoupled software pipelining
Rethinking Memory Permissions for Protection Against Cross-Layer Attacks
Lock-Free High-performance Hashing for Persistent Memory via PM-aware Holistic Optimization
Locality-Aware Work Stealing Based on Online Profiling and Auto-Tuning for Multisocket Multicore Architectures
Efficient Cross-platform Multiplexing of Hardware Performance Counters via Adaptive Grouping
Seamlessly portable applications: Managing the diversity of modern heterogeneous systems
Design exploration of hybrid caches with disparate memory technologies
RATT-ECC: Rate Adaptive Two-Tiered Error Correction Codes for Reliable 3D Die-Stacked Memory
The design and implementation of heterogeneous multicore systems for energy-efficient speculative thread execution
Autotuning Runtime Specialization for Sparse Matrix-Vector Multiplication
Puppeteer: A Random Forest Based Manager for Hardware Prefetchers Across the Memory Hierarchy
Speculative return address stack management revisited
Compiler-Assisted Loop Hardening Against Fault Attacks
Practical Iterative Optimization for the Data Center
Lavender: An Efficient Resource Partitioning Framework for Large-Scale Job Colocation
PETRA: Persistent Transactional Non-blocking Linked Data Structures
Federation: Boosting per-thread performance of throughput-oriented manycore architectures
Byte-Select Compression
SG XL : Security and Performance for Enclaves Using Large Pages
Optimizing Control Transfer and Memory Virtualization in Full System Emulators
Accelerating In-Memory Database Selections Using Latency Masking Hardware Threads
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes
Practical exhaustive optimization phase order exploration and evaluation
Utilizing RF-I and intelligent scheduling for better throughput/watt in a mobile GPU memory system
A First Step Toward Using Quantum Computing for Low-level WCETs Estimations
Writeback-aware partitioning and replacement for last-level caches in phase change main memory systems
PLDS: Partitioning linked data structures for parallelism
Side-channel Timing Attack of RSA on a GPU
DAG-Order: An Order-Based Dynamic DAG Scheduling for Real-Time Networks-on-Chip
Configurable Multi-directional Systolic Array Architecture for Convolutional Neural Networks
Gem5-X: A Many-core Heterogeneous Simulation Platform for Architectural Exploration and Optimization
ApSpGEMM: Accelerating Large-scale SpGEMM with Heterogeneous Collaboration and Adaptive Panel
LargeGraph: An Efficient Dependency-Aware GPU-Accelerated Large-Scale Graph Processing
Cryptographic Software IP Protection without Compromising Performance or Timing Side-channel Leakage
Potamoi: Accelerating Neural Rendering via a Unified Streaming Architecture
On Predictable Reconfigurable System Design
Automatic code overlay generation and partially redundant code fetch elimination
GPU code generation for ODE-based applications with phased shared-data access patterns
SpecTerminator: Blocking Speculative Side Channels Based on Instruction Classes on RISC-V
Energy-Efficient Runtime Management of Heterogeneous Multicores using Online Projection
A Model-Based Software Solution for Simultaneous Multiple Kernels on GPUs
An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors
Leveraging the Hardware Resources to Accelerate cryo-EM Reconstruction of RELION on the New Sunway Supercomputer
Winols: A Large-Tiling Sparse Winograd CNN Accelerator on FPGAs
TACOMA: Server and workload management in internet data centers considering cooling-computing power trade-off and energy proportionality
SLOOP: QoS-Supervised Loop Execution to Reduce Energy on Heterogeneous Architectures
Address/Data Instruction Steering in Clustered General Purpose Processors
DynamAP: Architectural Support for Dynamic Graph Traversal on the Automata Processor
BridgeGC: An Efficient Cross-Level Garbage Collector for Big Data Frameworks
A Software Cache Partitioning System for Hash-Based Caches
The design, implementation, and evaluation of adaptive code unloading for resource-constrained devices
A New Memory-Disk Integrated System with HW Optimizer
A NUMA-Aware Version of an Adaptive Self-Scheduling Loop Scheduler
Fastensor: Optimise the Tensor I/O Path from SSD to GPU for Deep Learning Training
Efficient and effective misaligned data access handling in a dynamic binary translation system
PARALiA: A Performance Aware Runtime for Auto-tuning Linear Algebra on Heterogeneous Systems
The migration prefetcher: Anticipating data promotion in dynamic NUCA caches
RegCPython: A Register-based Python Interpreter for Better Performance
Pac-Sim: Simulation of Multi-threaded Workloads using Intelligent, Live Sampling
Bahurupi: A polymorphic heterogeneous multi-core architecture
Automatic Sublining for Efficient Sparse Memory Accesses
UMH: A Hardware-Based Unified Memory Hierarchy for Systems with Multiple Discrete GPUs
Fence Placement for Legacy Data-Race-Free Programs via Synchronization Read Detection
Reducing cache misses through programmable decoders
A Compile-Time Optimization Method for WCET Reduction in Real-Time Embedded Systems through Block Formation
DLAS: A Conceptual Model for Across-Stack Deep Learning Acceleration
An Instruction Inflation Analyzing Framework for Dynamic Binary Translators
Approximate graph clustering for program characterization
A performance and energy comparison of convolution on GPUs, FPGAs, and multicore processors
HAKV: A Hotness-Aware Zone Management Approach to Optimizing Performance of LSM-tree-based Key-Value Stores
Mapi-Pro: An Energy Efficient Memory Mapping Technique for Intermittent Computing
Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling
AIM: Energy-Efficient Aggregation Inside the Memory Hierarchy
Ephemera: Accelerating I/O-Intensive Serverless Workloads with a Harvested In-memory File System
Modeling the impact of permanent faults in caches
R-GPU: A Reconfigurable GPU Architecture
ReHarvest: An ADC Resource-Harvesting Crossbar Architecture for ReRAM-Based DNN Accelerators
Preventing STT-RAM Last-Level Caches from Port Obstruction
A-DFA: A Time- and Space-Efficient DFA Compression Algorithm for Fast Regular Expression Evaluation
MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing
Exploiting Bank Conflict-based Side-channel Timing Leakage of GPUs
Leveraging Transactional Execution for Memory Consistency Model Emulation
Symmetry in Software Synthesis
GRAM: A Framework for Dynamically Mixing Precisions in GPU Applications
Impact of high-level transformations within the ROCCC framework
Mechanistic Analytical Modeling of Superscalar In-Order Processor Performance
AOBO: A Fast-Switching Online Binary Optimizer on AArch64
Accelerating Intercommunication in Highly Parallel Systems
Network Interface Architecture for Remote Indirect Memory Access (RIMA) in Datacenters
Java object header elimination for reduced memory consumption in 64-bit virtual machines
Accuracy Bugs: A New Class of Concurrency Bugs to Exploit Algorithmic Noise Tolerance
Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors
Optimal register reassignment for register stack overflow minimization
Attack and Defense: Enhancing Robustness of Binary Hyper-Dimensional Computing
GenCNN: A Partition-Aware Multi-Objective Mapping Framework for CNN Accelerators Based on Genetic Algorithm
Reducing Minor Page Fault Overheads through Enhanced Page Walker
Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface
Optimizing Garbage Collection for ZNS SSDs via In-storage Data Migration and Address Remapping
Memory-level parallelism aware fetch policies for simultaneous multithreading processors
Volatile STT-RAM Scratchpad Design and Data Allocation for Low Energy
Unified control flow and data dependence traces
An approach toward profit-driven optimization
Making secure processors OS- and performance-friendly
POWAR: Power-Aware Routing in HPC Networks with On/Off Links
Power Efficient Hardware Transactional Memory: Dynamic Issue of Transactions
Camouflage: Utility-Aware Obfuscation for Accurate Simulation of Sensitive Program Traces
Compiler-directed scratchpad memory management via graph coloring
ISP Agent: A Generalized In-storage-processing Workload Offloading Framework by Providing Multiple Optimization Opportunities
BigLittleMCA: A Spatially-Optimal Tiled Hardware Accelerator for MCMC Image Processing
MST: Topology-Aware Message Aggregation for Exascale Graph Processing of Traversal-Centric Algorithms
Dynamic code duplication with vulnerability awareness for soft error detection on VLIW architectures
HeapCheck: Low-cost Hardware Support for Memory Safety
Spectral prefetcher: An effective mechanism for L2 cache prefetching
SLO-Aware Inference Scheduler for Heterogeneous Processors in Edge Platforms
A unified optimizing compiler framework for different GPGPU architectures
Overlapping Aware Data Placement Optimizations for LSM Tree-Based Store on ZNS SSDs
Fine-Grain Power Breakdown of Modern Out-of-Order Cores and Its Implications on Skylake-Based Systems
GPU Performance and Power Tuning Using Regression Trees
Memory Access Scheduling Based on Dynamic Multilevel Priority in Shared DRAM Systems
HEngine: A High Performance Optimization Framework on a GPU for Homomorphic Encryption
An analysis of on-chip interconnection networks for large-scale chip multiprocessors
PowerMorph: QoS-Aware Server Power Reshaping for Data Center Regulation Service
Applied inference: Case studies in microarchitectural design
Toward On-chip Network Security Using Runtime Isolation Mapping
xMeta: SSD-HDD-hybrid Optimization for Metadata Maintenance of Cloud-scale Object Storage
Deep Learning Workload Mapping Optimization on Jetson Platforms
Design of the Java HotSpot™ client compiler for Java 6
Techniques to improve performance in requester-wins hardware transactional memory
Sectored DRAM: A Practical Energy-Efficient and High-Performance Fine-Grained DRAM Architecture
Spiking Neural Networks in Spintronic Computational RAM
A Portable Optimization Engine for Accelerating Irregular Data-Traversal Applications on SIMD Architectures
Efficient Out-of-Order Execution of Guarded ISAs
A Joint SW/HW Approach for Reducing Register File Vulnerability
Low-Power High-Efficiency Video Decoding using General-Purpose Processors
Dynamic Shared SPM Reuse for Real-Time Multicore Embedded Systems
Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access
Reducing instruction fetch energy in multi-issue processors
Automatic parallelization of fine-grained metafunctions on a chip multiprocessor
Selecting representative benchmark inputs for exploring microprocessor design spaces
Joint Program and Layout Transformations to Enable Convolutional Operators on Specialized Hardware Based on Constraint Programming
Clustering-Based Selection for the Exploration of Compiler Optimization Sequences
PICO: A Presburger In-bounds Check Optimization for Compiler-based Memory Safety Instrumentations
Optimal trace scheduling using enumeration
When Prefetching Works, When It Doesn't, and Why
IBing: An Efficient Interleaved Bidirectional Ring All-Reduce Algorithm for Gradient Synchronization
Fast pattern-specific routing for fat tree networks
Lock-contention-aware scheduler: A scalable and energy-efficient method for addressing scalability collapse on multicore systems
Tyche: An Efficient and General Prefetcher for Indirect Memory Accesses
ARACHNE: Optimizing Distributed Parallel Applications with Reduced Inter-Process Communication
WADE: Writeback-aware dynamic cache management for NVM-based main memory system
PMGraph: Accelerating Concurrent Graph Queries over Streaming Graphs
Dynamic Process Migration Based on Block Access Patterns Occurring in Storage Servers
An integrated pseudo-associativity and relaxed-order approach to hardware transactional memory
Resistive GP-SIMD Processing-In-Memory
Block Cooperation: Advancing Lifetime of Resistive Memories by Increasing Utilization of Error Correcting Codes
Weaving Synchronous Reactions into the Fabric of SSA-form Compilers
SPIRIT: Scalable and Persistent In-Memory Indices for Real-Time Search
TL-plane-based multi-core energy-efficient real-time scheduling algorithm for sporadic tasks
Understanding Cache Compression
Virtual machine showdown: Stack versus registers
The accelerator store: A shared memory framework for accelerator-based systems
Maxine: An approachable virtual machine for, and in, java
Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory
Preallocation instruction scheduling with register pressure minimization using a combinatorial optimization approach
Dual-Page Checkpointing: An Architectural Approach to Efficient Data Persistence for In-Memory Applications
QoS-pro: A QoS-enhanced Transaction Processing Framework for Shared SSDs
Automatic and Portable Mapping of Data Parallel Programs to OpenCL for GPU-Based Heterogeneous Systems
Variable Liberalization
Autotuning Convolutions Is Easier Than You Think
ECS: Error-Correcting Strings for Lifetime Improvements in Nonvolatile Memories
A Case for a More Effective, Power-Efficient Turbo Boosting
RACER: Avoiding End-to-End Slowdowns in Accelerated Chip Multi-Processors
PCantorSim: Accelerating parallel architecture simulation through fractal-based sampling
SSD-SGD: Communication Sparsification for Distributed Deep Learning Training
MemTracker: An accelerator for memory debugging and monitoring
TornadoNoC: A lightweight and scalable on-chip network architecture for the many-core era
BPM/BPM+: Software-based dynamic memory partitioning mechanisms for mitigating DRAM bank-/channel-level interferences in multicore systems
Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis
Mobile-3DCNN: An Acceleration Framework for Ultra-Real-Time Execution of Large 3D CNNs on Mobile Devices
GiantVM: A Novel Distributed Hypervisor for Resource Aggregation with DSM-aware Optimizations
MiCOMP: Mitigating the Compiler Phase-Ordering Problem Using Optimization Sub-Sequences and Machine Learning
An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism
Predicting New Workload or CPU Performance by Analyzing Public Datasets
Precise automatable analytical modeling of the cache behavior of codes with indirections
Power Consumption Models for Multi-Tenant Server Infrastructures
Deconstructing iterative optimization
Improved bitwidth-aware variable packing
Distilling the essence of proprietary workloads into miniature benchmarks
An Optimized Framework for Matrix Factorization on the New Sunway Many-core Platform
Thread Tranquilizer: Dynamically reducing performance variation
An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures
Building and Optimizing MRAM-Based Commodity Memories
Implementing Dense Optical Flow Computation on a Heterogeneous FPGA SoC in C
RT-GNN: Accelerating Sparse Graph Neural Networks by Tensor-CUDA Kernel Fusion
CAVA: Using checkpoint-assisted value prediction to hide L2 misses
High-Performance Generalized Tensor Operations: A Compiler-Oriented Approach
Defragmentation of Tasks in Many-Core Architecture
Towards High Performance QNNs via Distribution-Based CNOT Gate Reduction
ULEEN: A Novel Architecture for Ultra-low-energy Edge Neural Networks
Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators
Aging-Aware Compilation for GP-GPUs
COER: A Network Interface Offloading Architecture for RDMA and Congestion Control Protocol Codesign
Integrated Mapping and Synthesis Techniques for Network-on-Chip Topologies with Express Channels
DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators
COBAYN: Compiler Autotuning Framework Using Bayesian Networks
Using Template Matching to Infer Parallel Design Patterns
DiagSim: Systematically Diagnosing Simulators for Healthy Simulations
Sabrewing: A lightweight architecture for combined floating-point and integer arithmetic
Inter-kernel Reuse-aware Thread Block Scheduling
Exploring Data Layout for Sparse Tensor Times Dense Matrix on GPUs
GraphAttack: Optimizing Data Supply for Graph Applications on In-Order Multicore Architectures
Decreasing the Miss Rate and Eliminating the Performance Penalty of a Data Filter Cache
SSA-based mobile code: Implementation and empirical evaluation
PS-TLB: Leveraging page classification information for fast, scalable and efficient translation for future CMPs
MH Cache: A Mult Stephen Jarvisi-retention STT-RAM-based Low-power Last-level Cache for Mobile Hardware Rendering Systems
LDAC: Locality-Aware Data Access Control for Large-Scale Multicore Cache Hierarchies
Hardware Performance Counter-Based Malware Identification and Detection with Adaptive Compressive Sensing
Zeroploit : Exploiting Zero Valued Operands in Interactive Gaming Applications
PIMSAB: A Processing-In-Memory System with Spatially-Aware Communication and Bit-Serial-Aware Computation
CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution Near In-Order Energy with Near Out-of-Order Performance
LD: Low-Overhead GPU Race Detection Without Access Monitoring
Exploring single and multilevel JIT compilation policy for modern machines
FLARES: An Aging Aware Algorithm to Autonomously Adapt the Error Correction Capability in NAND Flash Memories
Knowledge-Augmented Mutation-Based Bug Localization for Hardware Design Code
Service level agreement for multithreaded processors
MFFT: A GPU Accelerated Highly Efficient Mixed-Precision Large-Scale FFT Framework
Multi-objective Hardware-aware Neural Architecture Search with Pareto Rank-preserving Surrogate Models
Enhancing High-Throughput GPU Random Walks Through Multi-Task Concurrency Orchestration
VSim: Simulating multi-server setups at near native hardware speed
A Framework for Automated and Controlled Floating-Point Accuracy Reduction in Graphics Applications on GPUs
E-BATCH: Energy-Efficient and High-Throughput RNN Batching
Time- and space-efficient flow-sensitive points-to analysis
Endurance-aware cache line management for non-volatile caches
GraphPEG: Accelerating Graph Processing on GPUs
Device Hopping: Transparent Mid-Kernel Runtime Switching for Heterogeneous Systems
Deterministic Replay Using Global Clock
Section-Based Program Analysis to Reduce Overhead of Detecting Unsynchronized Thread Communication
GPU Fast Convolution via the Overlap-and-Save Method in Shared Memory