yusuke1997/dblp-id-title huggingface dataset:
A 70-Mb/s 100.5-dBm Sensitivity 65-nm LP MIMO Chipset for WiMAX Portable Router
A 101 dB PSRR, 0.0027% THD + N and 94% Power-Efficiency Filterless Class D Amplifier
0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability
The Outphasing RF Power Amplifier: A Comprehensive Analysis and a Class-B CMOS Realization
A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration
A Sub-nW 32-kHz Crystal Oscillator Architecture Based on a DC-Only Sustaining Amplifier
A Fully Integrated 0.27-THz Injection-Locked Frequency Synthesizer With Frequency-Tracking Loop in 65-nm CMOS
A 10.7-MHz self-calibrated switched-capacitor-based multibit second-order bandpass ΣΔ modulator with on-chip switched buffer
A Fast Fixed-Frequency Adaptive-On-Time Boost Converter With Light Load Efficiency Enhancement and Predictable Noise Spectrum
SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU
An 8-Shaped Antenna-Based Battery-Free Neural-Recording System Featuring 3 cm Reading Range and 140 pJ/bit Energy Efficiency
An 8-W 250-MHz to 3-GHz Decade-Bandwidth Low-Noise GaN MMIC Feedback Amplifier With > +51-dBm OIP3
A nonvolatile programmable solid-electrolyte nanometer switch
A high-swing CMOS telescopic operational amplifier
125-GHz Diode Frequency Doubler in 0.13-µm CMOS
A Duty-Cycled Integrated-Fluxgate Magnetometer for Current Sensing
4-Mb MOSFET-selected μtrench phase-change memory experimental chip
Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyond
Compact mm-Wave Ultra-Wideband and Low-Noise Phase Alternately Distributed Quasi-Circulators
A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs
An Energy-Efficient Reconfigurable Processor for Binary-and Ternary-Weight Neural Networks With Flexible Data Bit Width
Liquid Silicon: A Nonvolatile Fully Programmable Processing-in-Memory Processor With Monolithically Integrated ReRAM
A Pipeline SAR ADC With Second-Order Interstage Gain Error Shaping
A circuit technology for a self-refresh 16 Mb DRAM with less than 0.5 μA/MB data-retention current
A 0.65 THz Focal-Plane Array in a Quarter-Micron CMOS Process Technology
An 8-Gb/s/pin simultaneously bidirectional transceiver in 0.35-μm CMOS
A 1/1.8-inch 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change
A 96.9-dB-Resolution 109-μW Second-Order Robust Closed-Loop VCO-Based Sensor Interface for Multiplexed Single-Ended Resistance Readout in 180-nm CMOS
Zero th -Order Control of Boost DC-DC Converter With Transient Enhancement Scheme
An 80-Gb/s optoelectronic delayed flip-flop IC using resonant tunneling diodes and uni-traveling-carrier photodiode
A Low-Power, High CMRR Neural Amplifier System Employing CMOS Inverter-Based OTAs With CMFB Through Supply Rails
A 140 Mbit/s CMOS LSI framer chip for a broad-band ISDN local access system
CMOS gigabit-per-second switching
A 5 µW/Channel Spectral Analysis IC for Chronic Bidirectional Brain-Machine Interfaces
A 100-MHz 4-mW four-quadrant BiCMOS analog multiplier
1-Gword/s pseudorandom word generator
A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications
Capacitive coupling and quantized feedback applied to conventional CMOS technology
A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC
Highlights of the IEEE ISSCC 2014 Processors, Digital, Memory, Biomedical & Next-Generation Systems Technologies, and Imagers, MEMS, Medical & Displays Sessions
CMOS VCO and LNA Using Tuned-Input Tuned-Output Circuits
A CMOS WCDMA/WLAN Digital Polar Transmitter With AM Replica Feedback Linearization
Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS
A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking
Notice of Violation of IEEE Publication Principles: A 54 dBOmega + 42 dB 10 Gb/s SiGe transimpedance-limiting amplifier using bootstrap photodiode capacitance neutralization and vertical threshold adjustment
A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS Technology
Low-voltage low-power controllable preamplifier for electret microphones
TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS
A Programmable 0.7-2.7 GHz Direct ΔΣ Receiver in 40 nm CMOS
A 200-MHz 64-b dual-issue CMOS microprocessor
Design of a second-level cache chip for shared-bus multimicroprocessor systems
Introduction to the Special Section on the 2019 IEEE BCICTS Conference
A Self-Adjustable Clock Generator With Wide Dynamic Range in 28 nm FDSOI
High-speed CMOS continuous-time complex graphic equalizer for magnetic recording
A 4TX/4RX Pulsed Chirping Phased-Array Radar Transceiver in 65-nm CMOS for X-Band Synthetic Aperture Radar Application
A BiCMOS Dual-Band Millimeter-Wave Frequency Synthesizer for Automotive Radars
Design and Analysis of an Electrical Balance Duplexer With Independent and Concurrent Dual-Band TX-RX Isolation
A 3.125 Gb/s limit amplifier in CMOS with 42 dB gain and 1 μs offset compensation
A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics
Silicon Photonic Microring-Based 4 × 112 Gb/s WDM Transmitter With Photocurrent-Based Thermal Control in 28-nm CMOS
A new design of the CMOS full adder
A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS
100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology
A 3.3-V CMOS 10.7-MHz sixth-order bandpass ΣΔ modulator with 74-dB dynamic range
A 0.67-to-5.4 TSOPs/W Spiking Neural Network Accelerator With 128/256 Reconfigurable Neurons and Asynchronous Fully Connected Synapses
A 32-48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology
A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces
A 13.3 mW 500 Mb/s IR-UWB Transceiver With Link Margin Enhancement Technique for Meter-Range Communications
Introduction to the Special Issue on the 2008 Symposium on VLSI Circuits
A 146-mm 2 8-gb multi-level NAND flash memory with 70-nm CMOS technology
High-Speed Single-Ended Parallel Link Based on Three-Level Differential Encoding
An Energy-Efficient 3.7-nV/ $\surd$ Hz Bridge Readout IC With a Stable Bridge Offset Compensation Scheme
A multilevel QAM demodulator VLSI with wideband carrier recovery and dual equalizing mode
A 1-GHz logic circuit family with sense amplifiers
A floating-point cell library and a 100-Mflops image signal processor
A CMOS transconductance amplifier architecture with wide tuning range for very low frequency applications
Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS
A Mm-Wave Wideband MIMO RX With Instinctual Array-Based Blocker/Signal Management for Ultralow-Latency Communication
A GSM/EDGE/WCDMA Adaptive Series-LC Matching Network Using RF-MEMS Switches
A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS
Monolithic transformers for silicon RF IC design
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
A 90.4% Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer
A monolithic field segment photo sensor system
A Compact Low-Power 16 b SAR ADC Using Reservoir-Charge-Redistributed DAC and Configurable FIA-Based Comparator
An 18-Gb/s, Direct QPSK Modulation SiGe BiCMOS Transceiver for Last Mile Links in the 70-80 GHz Band
A One-Step-Packaged CMOS/Microfluidics Wireless Bio-Analyzer for Point-of-Care Diagnostics
Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference
A 16-Mbit/s adapter chip for the IBM token-ring local area network
A multibit sigma-delta ADC for multimode receivers
Closed-Loop Class-D Amplifier With Nonlinear Loop Integrators
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan
Three-stage large capacitive load amplifier with damping-factor-control frequency compensation
An Electro-Magnetic Energy Harvesting System With 190 nW Idle Mode Power Consumption for a BAW Based Wireless Sensor Node
XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks
Distributed Waveform Generator: A New Circuit Technique for Ultra-Wideband Pulse Generation, Shaping and Modulation
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing
A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme
A 0.5-V BLE Transceiver With a 1.9-mW RX Achieving -96.4-dBm Sensitivity and -27-dBm Tolerance for Intermodulation From Interferers at 6- and 12-MHz Offsets
Antenna Preprocessing and Element-Pattern Shaping for Multi-Band mmWave Arrays: Multi-Port Receivers and Antennas
Design Considerations for Interleaved ADCs
A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC
Corrections to "A Power-Efficient Switched-Capacitor Stimulating System for Electrical/Optical Deep-Brain Stimulation"
A Single-Pair Serial Link for Mobile Displays With Clock Edge Modulation Scheme
A 12-bit 150-MS/s Sub-Radix-3 SAR ADC With Switching Miller Capacitance Reduction
A Low Jitter Programmable Clock Multiplier Based on a Pulse Injection-Locked Oscillator With a Highly-Digital Tuning Loop
Design and optimization of buffer chains and logic circuits in a BiCMOS environment
A 94.7-dB Dynamic Range Fully Passive Switched-Capacitor Low-Pass Filter With Enhanced Selectivity
A 0.6 mW/Gb/s, 6.4-7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS
A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter
A 48-56 GHz >1 dBm-HB1dB Sub-Sampling Eight-Path-Filter Receiver With Fully-Integrated LO Generation and On-Chip Antenna
A rail-to-rail CMOS op amp
A 0.25 mm 2 -Resistor-Based Temperature Sensor With an Inaccuracy of 0.12 °C (3σ) From -55 °C to 125 °C
2.45 e-RMS Low-Random-Noise, 598.5 mW Low-Power, and 1.2 kfps High-Speed 2-Mp Global Shutter CMOS Image Sensor With Pixel-Level ADC and Memory
GaAs dynamic memory design
Design of a 32.7-GHz bandwidth AGC amplifier IC with wide dynamic range implemented in SiGe HBT
A Bio-Inspired Spiking Vision Chip Based on SPAD Imaging and Direct Spike Computing for Versatile Edge Vision
A Pseudo OFDM With Miniaturized FSK Demodulation Body-Coupled Communication Transceiver for Binaural Hearing Aids in 65 nm CMOS
A 6-bit, 0.2 V to 0.9 V Highly Digital Flash ADC With Comparator Redundancy
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction
A Chopper Current-Feedback Instrumentation Amplifier With a 1 mHz 1/f Noise Corner and an AC-Coupled Ripple Reduction Loop
A Wide Linear Dynamic Range Image Sensor Based on Asynchronous Self-Reset and Tagging of Saturation Events
On-Chip HV Bootstrap Gate Driving for GaN Compatible Power Circuits Operating Above 10 MHz
A Serrodyne Modulator-Based Fractional Frequency Synthesis Technique for Low-Noise, GHz-Rate Clocking
A 30 μ W Analog Signal Processor ASIC for Portable Biopotential Signal Monitoring
A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter
Analysis and Design of a 5 GS/s Analog Charge-Domain FFT for an SDR Front-End in 65 nm CMOS
A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications
ANP-I: A 28-nm 1.5-pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-0.1-μ J/Sample On-Chip Learning for Edge-AI Applications
A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation
A novel CMOS implementation of double-edge-triggered flip-flops
Introduction to the Special Section on the IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS 2008)
Low-voltage electronics for the stimulation of biological neural networks using fully complementary BiCMOS circuits
A 1.2 nJ/bit 2.4 GHz Receiver With a Sliding-IF Phase-to-Digital Converter for Wireless Personal/Body Area Networks
A Fully Integrated 0.13-µm CMOS Digital Low-IF DBS Satellite Tuner Using a Ring Oscillator-Based Frequency Synthesizer
Switched-current circuits in digital CMOS technology with low charge-injection errors
Introduction to the Special Section on the 2019 RFIC Symposium
A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM
A dynamically reconfigurable monolithic CMOS pressure sensor for smart fabric
Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications
Energy-Performance Tunable Logic
Correction to "Baseband and Audio Mixed-Signal Front-End IC for GSM/EDGE Applications" [Jun 06 1364-1379]
A Time-Domain Computing Accelerated Image Recognition Processor With Efficient Time Encoding and Non-Linear Logic Operation
Design and implementation of a general-purpose median filter unit in CMOS VLSI
High Area-Efficient DC-DC Converter With High Reliability Using Time-Mode Miller Compensation (TMMC)
A CMOS 4× speed DVD read channel IC
An asynchronous GaAs MESFET static RAM using a new current mirror memory cell
High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique
A monolithic positioning system
A Monolithic and Self-Referenced RF LC Clock Generator Compliant With USB 2.0
A Continuous-Time ADC/DSP/DAC System With No Clock and With Activity-Dependent Power Dissipation
A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage
A 3.0 V 40 Mb/s hard disk drive read channel IC
Ultrahigh-Speed Low-Power DACs Using InP HBTs for Beyond-100-Gb/s/ch Optical Transmission Systems
A CMOS MedRadio Transceiver With Supply-Modulated Power Saving Technique for an Implantable Brain-Machine Interface System
A VLSI fuzzy logic controller with reconfigurable, cascadable architecture
A 2.5 nJ/bit 0.65 V Pulsed UWB Receiver in 90 nm CMOS
An 85-GHz Power Amplifier Utilizing a Transformer-Based Power Combiner Operating Beyond the Self-Resonance Frequency
Yield optimization of analog ICs using two-step analytic modeling methods
A CMOS transconductance-C filter technique for very high frequencies
Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics
A Fifth-Order G m -C Continuous-Time ΔΣ Modulator With Process-Insensitive Input Linear Range
Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect
A variable gain amplifier with 50-dB control range for 900-MHz applications
A micropower logarithmic A/D with offset and temperature compensation
A 50-fA junction-isolated operational amplifier
CS-Audio: A 16 pJ/b 0.1-15 Mbps Compressive Sensing IC With DWT Sparsifier for Audio-AR
Guest Editorial: Introduction to the Special Section on the 2024 RFIC Symposium
A Broadband Class-AB Power Amplifier With Instantaneous Supply-Switching Efficiency Enhancement for Cable TV Application
A CMOS fully integrated antilarsen system for digital telephones
A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM
A Low-Cost and Low-Power CMOS Receiver Front-End for MB-OFDM Ultra-Wideband Systems
A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/°C CMOS-Only Current Reference in 0.11- μ m Bulk and 22-nm FD-SOI
Corrections to "Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time"
System-level design for test of fully differential analog circuits
A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier
A 56-65 GHz Injection-Locked Frequency Tripler With Quadrature Outputs in 90-nm CMOS
A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing
Correction to "A carry-free 54 b x 54 b multiplier using equivalent bit conversion algorithm"
A 900-MHz/1.8-GHz CMOS transmitter for dual-band applications
A knowledge-based test generator for standard cell and iterative array logic circuits
A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications
An implantable CMOS circuit interface for multiplexed microelectrode recording arrays
A Pre-Charge Tracking Technique in the 40 MHz High-Speed Switching 48-to-5 V GaN-Based DC-DC Buck Converter for Reducing Large Self-Commutation Loss and Achieving a High Efficiency of 95.4%
A Tri-Mode Compressed Analytics Engine for Low-Power AF Detection With On-Demand EKG Reconstruction
10 K-gate GaAs JFET sea of gates
A 1.5-V DRAM for battery-based applications
A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-µm CMOS for Medical Implant Devices
A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control
A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance
Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-Mb DRAM's
Single Miller capacitor frequency compensation technique for low-power multistage amplifiers
A Nonvolatile Flip-Flop-Enabled Cryptographic Wireless Authentication Tag With Per-Query Key Update and Power-Glitch Attack Countermeasures
Transit frequency of fast Si self-aligned bipolar transistors
A 3.3/2.5 V-Supply 2400 mV-Swing Single-Ended SiGe BiCMOS Driver With Programmable Preemphasis for 3 Gb/s Data Transmission Over 75 Ω Coaxial Cable
A 40-ps high electron mobility transistor 4.1 K gate array
An ELDC-Free 4th-Order CT SDM Facilitated by 2nd-Order NS CT-SAR and AC-Coupled Negative-R
Supply-Noise-Resilient Design of a BBPLL-Based Force-Balanced Wheatstone Bridge Interface in 130-nm CMOS
A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS
The state of the art of electrostatic discharge protection: physics, technology, circuits, design, simulation, and scaling
A 155-MHz clock recovery delay- and phase-locked loop
A Scaled Thermal-Diffusivity-Based 16 MHz Frequency Reference in 0.16 µm CMOS
High-speed CMOS I/O buffer circuits
Addition to "Monolithic transformers and their application in a differential CMOS RF low-noise amplifier"
Channel Selection at RF Using Miller Bandpass Filters
Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs)
A fully integrated CMOS DCS-1800 frequency synthesizer
A CMOS SPAD Line Sensor With Per-Pixel Histogramming TDC for Time-Resolved Multispectral Imaging
A reverse-voltage protection circuit for MOSFET power switches
Guest Editorial IEEE 2023 European Solid-State Circuits Conference
Comments on "A 64-point Fourier transform chip for video motion compensation using phase correlation"
A 0.5 mm 2 Power-Scalable 0.5-3.8-GHz CMOS DT-SDR Receiver With Second-Order RF Band-Pass Sampler
A Reconfigurable 40-to-67 dB SNR, 50-to-6400 Hz Frame-Rate, Column-Parallel Readout IC for Capacitive Touch-Screen Panels
Low-power Viterbi decoder for CDMA mobile terminals
A 640-Gb/s 4 × 4-MIMO D-Band CMOS Transceiver Chipset
Regenerative feedback repeaters for programmable interconnections
A Millimeter-Wave Four-Way Doherty Power Amplifier With Over-GHz Modulation Bandwidth
RF Transconductor Linearization Robust to Process, Voltage and Temperature Variations
A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface
A Sub-60-µA Multimodal Smart Biosensing SoC With >80-dB SNR, 35-µA Photoplethysmography Signal Chain
A 10.7-MHz CMOS SC radio IF filter using orthogonal hardware modulation
A 5.3-GB/s embedded SDRAM core with slight-boost scheme
A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing
Nonlinear analysis of noise in current-steering variable gain amplifiers
Correction to "Reconfigurable Processor for Energy-Efficient Computational Photography"
A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications
A Bio-Impedance Readout IC With Complex-Domain Noise-Correlated Baseline Cancellation
PCM telephony: reduced architecture for a D/A converter and filter combination
Circuit layout and yield
Measurements and analysis of SER-tolerant latch in a 90-nm dual-V T CMOS process
A 28-GHz, Multi-Beam, Decentralized Relay Array
A D-Band 120-GHz 2-D Scalable 4 × 4 Relay Array With Orthogonally Polarized On-Chip Antennas and In-Front-End Fast 2-D Angle-of-Arrival Detection
8-λ × 50 Gbps/λ Heterogeneously Integrated Si-Ph DWDM Transmitter
A Low-Noise 40-GS/s Continuous-Time Bandpass ΔΣ ADC Centered at 2 GHz for Direct Sampling Receivers
Area-Efficient Non-Binary LDPC Decoder With Column-Wise Trellis Min-Max Algorithm
Fully-Integrated On-Chip DC-DC Converter With a 450X Output Range
Bandwidth extension in CMOS with optimized on-chip inductors
Design and Analysis of a Programmable Receiver Front End Based on Baseband Analog-FIR Filtering Using an LPTV Resistor
Parametric formulation of CMOS latch-up as a function of chip layout parameters
A 250-kHz 94-dB double-sampling ΣΔ modulation A/D converter with a modified noise transfer function
A 0.32 THz SiGe 4x4 Imaging Array Using High-Efficiency On-Chip Antennas
An Ultrasonic Transducer Interface IC With Integrated Push-Pull 40 Vpp, 400 mA Current Output, 8-bit DAC and Integrated HV Multiplexer
Calculation of the soft error rate of submicron CMOS logic circuits
A 1.5 V 3.1 GHz-8 GHz CMOS Synthesizer for 9-Band MB-OFDM UWB Transceivers
Design procedures for a fully differential folded-cascode CMOS operational amplifier
A Low-Noise Low-Power Chopper Instrumentation Amplifier With Robust Technique for Mitigating Chopping Ripples
A 300-800 MHz Tunable Filter and Linearized LNA Applied in a Low-Noise Harmonic-Rejection RF-Sampling Receiver
A 65-nm CMOS Fully Integrated Transceiver Module for 60-GHz Wireless HD Applications
A 156-Mb/s CMOS optical receiver for burst-mode transmission
A CMOS mainframe processor with 0.5- mu m channel length
A 30-V row/column driver for flat-panel liquid crystal displays
A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques
A Self-Regulated and Reconfigurable CMOS Physically Unclonable Function Featuring Zero-Overhead Stabilization
50th Anniversary of the Journal
Virtual-ground sensing techniques for a 49-ns/200-MHz access time 1.8-V 256-Mb 2-bit-per-cell flash memory
Dynamic Polarization Control
High-temperature superconducting shift registers operating at up to 100 GHz
A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation
A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection
Design of G-Band Watt-Level GaN Power Amplifier With Multiband Large-Signal Impedance Correction and Circuit-Package Co-Design Technique
A fast Modulator for dynamic supply linear RF power amplifier
Correction to "A fully integrated 0.5 - 5.5-GHz CMOS distributed amplifier"
DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge
A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N 2
PCFL3: a low-power, high-speed, single-ended logic family
An accurate MESFET model for linear and microwave circuit design
The use of RTL descriptions in accurate timing verification and test generation (VLSI)
Guest Editorial Introduction to the Special section on the 2024 IEEE International Solid-State Circuits Conference (ISSCC)
A 114-dB 68-mW Chopper-stabilized stereo multibit audio ADC in 5.62 mm2
A +10 dBm BLE Transmitter With Sub-400 pW Leakage for Ultra-Low Duty Cycles
Design of a one-transistor-cell multiple-valued CAM
A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS
Low-Power Effective Memory-Size Expanded TCAM Using Data-Relocation Scheme
Low-power area-efficient high-speed I/O circuit techniques
A $192\times128$ Time Correlated SPAD Image Sensor in 40-nm CMOS Technology
A Low Noise Figure 1.2-V CMOS GPS Receiver Integrated as a Part of a Multimode Receiver
Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuit