yusuke1997/dblp-id-title huggingface dataset:
A Novel Low Power 1 GS/s S&H Architecture With Improved Analog Bandwidth
A new Monte Carlo circuit simulation paradigm with specific results for resistive networks
Minimum-Phase FIR Filter Design Using Real Cepstrum
Pipelined Architecture for a Radix-2 Fast Walsh-Hadamard-Fourier Transform Algorithm
Wide dynamic range snapshot APS for ultra low-power applications
Nonparametric identification of nonlinearities in block-oriented systems by orthogonal wavelets with compact support
Functional Read Enabling In-Memory Computations in 1Transistor - 1Resistor Memory Arrays
Probabilistic Approach for Yield Analysis of Dynamic Logic Circuits
CRITIC-Based Node Importance Evaluation in Skeleton-Network Reconfiguration of Power Grids
Probabilistic Spherical Detection and VLSI Implementation for Multiple-Antenna Systems
DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes
Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count
A design-oriented study of the nonlinear dynamics of digital bang-bang PLLs
A Subhertz Nanopower Low-Pass Filter
A Current-Accuracy-Enhanced Wide-Input-Range DC-DC LED Driver With Feedforward Synchronous Current Control
A Neutral-Type Delayed Projection Neural Network for Solving Nonlinear Variational Inequalities
Digital Fractional Order Savitzky-Golay Differentiator
Analysis and Design Techniques of CMOS Charge-Pump-Based Radio-Frequency Antenna-Switch Controllers
Asymptotic Cramér-Rao Bound for Noise-Compensated Autoregressive Analysis
Bang-Bang Control Class-D Amplifiers: Power-Supply Noise
Stabilization and Synchronization of Complex Dynamical Networks With Different Dynamics of Nodes Via Decentralized Controllers
A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes
A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS
Bootstrapped Driver and the Single-Event-Upset Effect
Design Procedure for Two-Stage CMOS Opamp With Flexible Noise-Power Balancing Scheme
A New Fast Algorithm for Discrete Fractional Hadamard Transform
A 2-Kb One-Time Programmable Memory for UHF Passive RFID Tag IC in a Standard 0.18 µm CMOS Process
Design of the Input Matching Network of RF CMOS LNAs for Low-Power Operation
Nonlinear Behaviors of Bandpass Sigma-Delta Modulators With Stable System Matrices
All-Digital Blind Background Calibration Technique for Any Channel Time-Interleaved ADC
Partial-Update L ∞ -Norm Based Algorithms
Efficient Solar Power Management System for Self-Powered IoT Node
Analysis and Design of Boolean Associative Memories Made of Resonant Oscillator Arrays
Optimal Design of Nearfield Wideband Beamformers Robust Against Errors in Microphone Array Characteristics
A Scalable Digitalized Buffer for Gigabit I/O
Design Method for Compact Multifunctional Reconfigurable Filtering Power Divider on a New Tunable Three-Port Multi-Mode Topology
Guest Editorial Special Issue on Multifunctional Circuits and Systems for Future Generations of Wireless Communications - I
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators
Characteristics of Single- and Multiple-Frequency Impedance Matching Networks
Leader-Following Consensus of Multi-Agent Systems With Switching Networks and Event-Triggered Control
An Efficient Linearization Scheme for a Digital Polar EDGE Transmitter
Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices
A Simple Circuit Approach to Reduce Delay Variations in Domino Logic Gates
Maximum Sequence Length MASH Digital Delta-Sigma Modulators
Novel Outphasing Power Amplifiers Designed With an Analytic Generalized Doherty-Chireix Continuum Theory
A 1.2-V 4.2- ppm°C High-Order Curvature-Compensated CMOS Bandgap Reference
Digital Equalization of a Polyphase Harmonic Mixer
Data Bus Inversion in High-Speed Memory Applications
Reduced-Complexity Key Equation Solvers for Generalized Integrated Interleaved BCH Decoders
Symbolic Framework for Linear Active Circuits Based on Port Equivalence Using Limit Variables
A Two-Dimensional Configurable Active Silicon Dendritic Neuron Array
Design of a Simultaneous Frequency- and Power-Dividing Ratio-Reconfigurable Quadrature Coupler With Simple Tuning Approach
Design and Analysis of an Always-ON Input-Biased pA-Current Sub-nW mV-Threshold Hysteretic Comparator for Near-Zero Energy Sensing
Fixed Time Synchronization Control for Bilateral Teleoperation Mobile Manipulator With Nonholonomic Constraint and Time Delay
Successive Approximation RF Reflectometer for Antenna Tuning in Cellular Handheld Devices
Self-Learning Hot Data Prediction: Where Echo State Network Meets NAND Flash Memories
Low-Complexity High-Order Vector-Based Mismatch Shaping in Multibit ΔΣ ADCs
A Quantum-Limited Highly Linear Monolithic CMOS Detector for Computed Tomography
Oscillator Phase Noise: A Geometrical Approach
Distributed Optimal Consensus Control Algorithm for Continuous-Time Multi-Agent Systems
Low-Cost Digital Detection of Parametric Faults in Cascaded SigmaDelta Modulators
Absolute stability of analytic neural networks: an approach based on finite trajectory length
Event-Triggered Modified Repetitive Control for Periodic Signal Tracking
Design Strategy for Step-Up Charge Pumps With Variable Integer Conversion Ratios
Static and Clocked Spintronic Circuit Design and Simulation With Performance Analysis Relative to CMOS
A CMOS analog front-end IC for portable EEG/ECG monitoring applications
Statistical Properties of First-Order Bang-Bang PLL With Nonzero Loop Delay
Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs
Modeling and Design of CMOS UHF Voltage Multiplier for RFID in an EEPROM Compatible Process
Decoupled dynamic ternary content addressable memories
Stochastic Synchronization of Complex Networks With Mixed Impulses
Complete Stability of Neural Networks With Nonmonotonic Piecewise Linear Activation Functions
Closed-Form Critical Conditions of Subharmonic Oscillations for Buck Converters
A 1.5 mW Programmable Acoustic Signal Processor for Hearing Assistive Devices With Speech Intelligibility Enhancement
Output Synchronization of Dynamical Networks with Incrementally-Dissipative Nodes and Switching Topology
Self-Validated Time-Domain Analysis of Linear Systems With Bounded Uncertain Parameters
Up-Conversion of Clock Phase Noise in Plesiochronous Data Links
A Computational Digital Pixel Sensor Featuring Block-Readout Architecture for On-Chip Image Processing
A Lattice Structure of Biorthogonal Linear-Phase Filter Banks With Higher Order Feasible Building Blocks
A low-power inverted ladder D/a converter
A Universal Mutator for Transformations Among Memristor, Memcapacitor, and Meminductor
A 40 nm Dual-Width Standard Cell Library for Near/Sub-Threshold Operation
Adaptive Pinning Control of Networks of Circuits and Systems in Lur'e Form
An Efficient Context-Based BPGC Scalable Image Coder
Robust Delay-Dependent H infty Control of Uncertain Time-Delay Systems With Mixed Neutral, Discrete, and Distributed Time-Delays and Markovian Switching Parameters
Incremental SAT-Based Correction of Gate Level Circuits by Reusing Partially Corrected Circuits
Convex Relaxations of Optimal Power Flow Problems: An Illustrative Example
A Temperature Compensated Triple-Path PLL With K VCO Non-Linearity Desensitization Capable of Operating at 77 K
General constructive representations for continuous piecewise-linear functions
A Power-Efficient 5.6-GHz Process-Compensated CMOS Frequency Divider
An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS
Implementation of a High-Precision and Wide-Range Time-to-Digital Converter With Three-Level Conversion Scheme
A 1-V 5-GHz Self-Bias Folded-Switch Mixer in 90-nm CMOS for WLAN Receiver
An adaptation procedure on envelope statistics for predistorter designs based on statistical modeling methods
Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications
Advanced Low-Noise X-Ray Readout ASIC for Radiation Sensor Interfaces
Multi-Functional Balanced-to-Unbalanced Filtering Power Dividers With Extended Upper Stopband
On-Chip Power-Grid Simulation Using Latency Insertion Method
A Single-Chip 60-V Bulk Charger for Series Li-Ion Batteries With Smooth Charge-Mode Transition
A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform
Pulse Phase Shift Based Low-Frequency Oscillation Suppression for PT Controlled CCM Buck Converter
Kron Reduction of Graphs With Applications to Electrical Networks
TEAM: ThrEshold Adaptive Memristor Model
Reliable Output Feedback Control for Piecewise Affine Systems With Markov-Type Sensor Failure
Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm
Octo-Band Bandpass Filter Based on Unequal-Width Cruciform Connected Resonator With Sharp Skirt
The Analytic Determination of the PPV for Second-Order Oscillators Via Time-Varying Eigenvalues
Low-Latency Reconfigurable Entropy Digital True Random Number Generator With Bias Detection and Correction
Fast DC-Bias Current Control of Dual Active Bridge Converters With Feedforward Compensation
An Algorithmic Approach for Signal Measurement Using Symbolic Dynamics of Tent Map
Switchable Filtering Circuit With Single- and Multi-Channel Operations
Linear Consequence-Based Fuzzy Parallel Distributed Compensation Type L 1 Adaptive Controller for Two Link Robot Manipulator
A High-Speed SDM-MIMO Decoder Using Efficient Candidate Searching for Wireless Communication
Fast and Efficient Search for All DC Solutions of PWL Circuits by Means of Oversized Polyhedra
A Direct Learning Adaptive Scheme for Power-Amplifier Linearization Based on Wirtinger Calculus
Fully Distributed Adaptive PI Controllers for Heterogeneous Linear Networks
Positive Realizations of Transfer Matrices With Real Poles
A 1.2-MHz 10-bit Continuous-Time Sigma-Delta ADC Using a Time Encoding Quantizer
Efficient Verification Against Undesired Operating Points for MOS Analog Circuits
An ARM-Based System-on-a-Programmable-Chip Architecture for Spoken Language Translation
Quantization Effects in an Analog-to-Information Front End in EEG Telemonitoring
General Top/Bottom-Plate Charge Recycling Technique for Integrated Switched Capacitor DC-DC Converters
Fast real-time convolution algorithm for microwave multiport networks with nonlinear terminations
Tunable Dual-Band Filter and Diplexer Based on Folded Open Loop Ring Resonators
A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme
ADP-Based Security Decentralized Sliding Mode Control for Partially Unknown Large-Scale Systems Under Injection Attacks
A 0.45-V Low-Power OOK/FSK RF Receiver in 0.18 μm CMOS Technology for Implantable Medical Applications
Modeling and Technique to Improve PSRR and PS-IMD in Analog PWM Class-D Amplifiers
Large-scale field-programmable analog arrays for analog signal processing
RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer
Electronically Tunable Doherty Power Amplifier for Multi-Mode Multi-Band Base Stations
VLSI Design for Convolutive Blind Source Separation
Rakeness-Based Design of Low-Complexity Compressed Sensing
Digitally Enhanced Wideband I/Q Downconversion Receiver With 2-Channel Time-Interleaved ADCs
A Sequential Constrained Least-Square Approach to Minimax Design of 2-D FIR Filters
Controller Synthesis for Positive Linear Systems With Bounded Controls
Topographical Field Map Analysis Tool for Designing Linear LC DCOs
Synthesis, Design, and Synchronization Analysis of Coupled Linear Electrical Networks
Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations
Lattice Structure Realization for The Design of 2-D Digital Allpass Filters With General Causality
A 0.6-V Delta-Sigma Modulator With Subthreshold-Leakage Suppression Switches
A Frequency-Translating Hybrid Architecture for Wide-Band Analog-to-Digital Converters
Energy Harvesting Using Substrate Photodiodes
Chaotic Encryption for 10-Gb Ethernet Optical Links
Designs of Discrete-Time Generalized Fractional Order Differentiator, Integrator and Hilbert Transformer
The determination of S-parameters from the poles of voltage-gain transfer function for RF IC design
A Study of Deterministic Jitter in Crystal Oscillators
A New PVT Compensation Technique Based on Current Comparison for Low-Voltage, Near Sub-Threshold LNA
Second and Third-Order Noise Shaping Digital Quantizers for Low Phase Noise and Nonlinearity-Induced Spurious Tones in Fractional-N PLLs
Enhanced detection-guided NLMS estimation of sparse FIR-modeled signal channels
Design of Multi-Plet Perfect Reconstruction Filter Banks Using Frequency-Response Masking Technique
Efficient ASK Data and Power Transmission by the Class-E With a Switchable Tuned Network
A low-voltage CMOS switch with a novel clock boosting scheme
A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits
Fingerprint Image Processing Acceleration Through Run-Time Reconfigurable Hardware
CMOS RF receiver system design: a systematic approach
An Analog Front-End IC Design for 320 × 240 Microbolometer Array Applications
Compact Analog Predistorter With Shape Tuning Capability Using Power-Dependent Impedance Matching Network
Technology Variability From a Design Perspective
On the Designs of Variable Fractional Hilbert Transformers
Coupling-Inductor-Based Hybrid mm-Wave CMOS SPST Switch
Non-Fragile Fault Alarm-Based Hybrid Control for the Attitude Quadrotor Model With Actuator Saturation
Hardware Efficient Low-Latency Architecture for High Throughput Rate Viterbi Decoders
ULPFA: A New Efficient Design of a Power-Aware Full Adder
Comparison of Pentacene and Amorphous Silicon AMOLED Display Driver Circuits
A Low-Power Delta-Sigma Modulator Using a Charge-Pump Integrator
Generalized Time- and Transfer-Constant Circuit Analysis
Enhanced Linear Iterative Detector for Massive Multiuser MIMO Uplink
A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation
Switched-Capacitor Boost-Buck Ladder Converters With Extended Voltage Range in Standard CMOS
A Novel Transmitter Architecture for Spectrally-Precoded OFDM
An Intuitive Current-Driven Passive Mixer Model Based on Switched-Capacitor Theory
Slewing Mitigation Technique for Switched Capacitor Circuits
Measured CMOS Switched High-Quality Capacitors in a Reconfigurable Matching Network
A Low-Power Dual-Injection-Locked RF Receiver With FSK-to-OOK Conversion for Biomedical Implants
Analysis and Design of N-Path Filter Offset Tuning in a 0.7-2.7-GHz Receiver Front-End
QBF-Based Post-Silicon Debug of Speed-Paths Under Timing Variations
Wideband 28-nm CMOS Variable-Gain Amplifier
Master-Slave Synchronization of Fourth-Order Lü Chaotic Oscillators via Linear Output Feedback
Design and analysis of an optimal controller for parallel multi-inverter systems
Security Analysis of a Distributed Networked System Under Eavesdropping Attacks
A 3-Lead ECG-on-Chip with QRS Detection and Lossless Compression for Wireless Sensors
Minimax Design of Low-Complexity Allpass Variable Fractional-Delay Digital Filters
A New Loss Compensation Technique for CMOS Distributed Amplifiers
Implications of Small Geometry Effects on g m /I D Based Design Methodology for Analog Circuits
Expansion and Compression of Analog Pulses by Bandwidth Scaling of Continuous-Time Filters
An Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MU-MIMO Systems
Analysis of a Fractional-Order Wireless Power Transfer System
A Digital Receiver Architecture for Bluetooth in 0.25- μm CMOS Technology and Beyond
Design Tradeoffs and Predistortion of Digital Cartesian RF-Power-DAC Transmitters
Modeling R-2R Segmented-Ladder DACs
Universal Set of CMOS Gates for the Synthesis of Multiple Valued Logic Digital Circuits
Output regulation of discrete-time piecewise-linear systems with application to controlling chaos
A 0.016 mm2 12 b Δ Σ SAR With 14 fJ/conv. for Ultra Low Power Biosensor Arrays
Nonlinear Analysis of Voltage-Controlled Oscillators: A Systematic Approach
Balanced filters with wideband common mode suppression using dual-mode ring resonators
Fast feedthrough logic: a high performance logic family for GaAs
A CMOS 3-D Imager Based on Single Photon Avalanche Diode
Reliable Resilient Finite-Time Control for Stabilization of Hyperchaotic Fractional-Order Systems
Numerical Approximation of the Maximum Power Consumption in DC-MGs With CPLs via an SDP Model
Tightness Conditions for Semidefinite Relaxations of Forms Minimization
Asymmetric Instability Conditions for Peak and Valley Current Programmed Converters at Light Loading
A DLL-Supported, Low Phase Noise Fractional-N PLL With a Wideband VCO and a Highly Linear Frequency Ramp Generator for FMCW Radars
Beamforming of Broad-Band Bandpass Plane Waves Using Polyphase 2-D FIR Trapezoidal Filters
Wideband TV White Space Transceiver Design and Implementation
High-Precision, Mixed-Signal Mismatch Measurement of Metal-Oxide-Metal Capacitors
Efficient FPGA Implementation of K-Nearest-Neighbor Search Algorithm for 3D LIDAR Localization and Mapping in Smart Vehicles
Steady-State Analysis of Phase-Locked Loops Using Binary Phase Detector
A Study of Loosely Coupled Coils for Wireless Power Transfer
Winner-Take-All-Based Visual Motion Sensors
Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops
Asynchronous Observer-Based Control for Exponential Stabilization of Markov Jump Systems
Least-Squares Design of FIR Filters Based on a Compacted Feedback Neural Network
Fault Detection for Nonlinear Systems With Multitone Sinusoidal Input
Efficient Implementation of a Threshold Modified Min-Sum Algorithm for LDPC Decoders
Synthesis of Leap-Frog Multiple-Loop Feedback OTA-C Filters
Design Solutions for Sample-and-Hold Circuits in CMOS Nanometer Technologies
Low- Cost Parallel FIR Filter Structures With 2-Stage Parallelism
A Low-Complexity Hardware for Deterministic Compressive Sensing Reconstruction
A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology
Frequency Domain Analysis of Superregenerative Receivers in the Linear and the Logarithmic Modes
Two-Dimensional Cartesian Memory Polynomial Model for Nonlinearity and I/Q Imperfection Compensation in Concurrent Dual-Band Transmitters
Optimized Design of N-Phase Passive Mixer-First Receivers in Wideband Operation
Reduced-order modeling via oblique projections on a bandlimited Kautz basis
Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators
A VCF Loss-Control Tuning Loop for Q -Enhanced LC Filters
Respiration and Heartbeat Rates Measurement Based on Autocorrelation Using IR-UWB Radar
Analysis and Design of Ultra-Large Dynamic Range CMOS Transimpedance Amplifier With Automatically-Controlled Multi-Current-Bleeding Paths
Frequency Triplexer for Ultra-Wideband Systems (6-9 GHz)
A 0.5-Hz High-Pass Cutoff Dual-Loop Transimpedance Amplifier for Wearable NIR Sensing Device
A Low-Dropout Regulator With Tail Current Control for DPWM Clock Correction
A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18-μm CMOS
A bandpass mismatch noise-shaping technique for Σ-Δ Modulators
A Spectrum-Sensing DPD Feedback Receiver With 30× Reduction in ADC Acquisition Bandwidth and Sample Rate
A CMOS/Thin-Film Fluorescence Contact Imaging Microsystem for DNA Analysis
Slow-Scale Instability of Single-Stage Power-Factor-Correction Power Supplies
Theoretical Analysis of Circuit Non-Idealities in a Passive Spectrum Scanner Based on Periodically Time-Varying Circuit Components
A Flexible Low Power DSP With a Programmable Truncated Multiplier
Automatic 3D Design for Efficiency Optimization of a Class E Power Amplifier
Output stage based high-resolution min/max and rank-order filters
Field-Free 3T2SOT MRAM for Non-Volatile Cache Memories
A Simple Floating Mutator for Emulating Memristor, Memcapacitor, and Meminductor
A Dynamic-Biased Resistor-Based CMOS Temperature Sensor With a Duty-Cycle-Modulated Output
Suppressing Epidemic Spreading by Imitating Hub Nodes' Strategy
A Low-Cost Serial Decoder Architecture for Low-Density Parity-Check Convolutional Codes
Reducing Lookup-Table Size in Direct Digital Frequency Synthesizers Using Optimized Multipartite Table Method
Modeling Oscillator Injection Locking Using the Phase Domain Response
Analytical Studies of Quasi Steady-State Model in Power System Long-Term Stability Analysis
A -40 dB EVM, 77 MHz Dual-Band Tunable Gain Sub-Sampling Receiver Front End in 65-nm CMOS
Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation
Design of Practical Broadband Matching Networks With Mixed Lumped and Distributed Elements
An Efficient and Reconfigurable Synchronous Neuron Model
Slotline-Based Balanced Filter With Ultra-Wide Stopband and High Selectivity
Survivor Path Processing in Viterbi Decoders Using Register Exchange and Traceforward
A Quadrature RC Oscillator With Noise Reduction by Voltage Swing Control
Algebraic Soft-Decision Decoder Architectures for Long Reed-Solomon Codes
Advancing Data Weighted Averaging Technique for Multi-Bit Sigma-Delta Modulators
Corrections to "Settling Time Optimization for Three-Stage CMOS Amplifier Topologies" [Dec 09 2569-2582]
A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO
Cooperative Wideband Spectrum Sensing Based on Sub-Nyquist Sparse Fast Fourier Transform
Low-power low-voltage CMOS A/D sigma-delta modulator for bio-potential signals driven by a single-phase scheme
In Situ Power Gating Efficiency Learner for Fine-Grained Self-Adaptive Power Gating
Exponential Stability of Impulsive Delayed Linear Differential Equations
A 0.12-mm 2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-µs Settling Time for Multi-ISM-Band ULP Radios
Analysis of the Rectifier Circuit Valid Down to Its Low-Voltage Limit
Truncated Binary Multipliers With Variable Correction and Minimum Mean Square Error
Vortex Search Algorithm for Optimal Power Flow Analysis in DC Resistive Networks With CPLs
A Single-Capacitor Bootstrapped Power-Efficient CMOS Driver
A 15-V Bidirectional Current Clamp Circuit for Integrated Patch Clamp Electrophysiology
Energy-Recovery Techniques to Reduce On-Chip Power Density in Molecular Nanotechnologies
MIMO systems properties preservation under SPR substitutions
Cooperative Output Regulation of Heterogeneous Multi-Agent Systems With Adaptive Edge-Event-Triggered Strategies
A PSRR Enhancing Method for GRO TDC Based Clock Generation Systems
A low-power low-voltage OTA-C sinusoidal oscillator with a large tuning range
Kernel Recursive Least Squares With Multiple Feedback and Its Convergence Analysis
MIMO Series-Series Feedback Amplifiers
Blind source extraction from convolutive mixtures in ill-conditioned multi-input multi-output channels
Towards Wave Digital Memcomputing With Physical Memristor Models
Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor
Faster Residue Multiplication Modulo 521-bit Mersenne Prime and an Application to ECC
Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution
A Novel Sourceline Voltage Compensation Circuit and a Wordline Voltage-Generating System for Embedded nor Flash Memory
A 5 Gbps 1.6 mW/G bps/CH Adaptive Crosstalk Cancellation Scheme With Reference-less Digital Calibration and Switched Termination Resistors for Single-Ended Parallel Interface
Parameter Identification of Delayed Under-Damped Systems Using On-Line Relay Autotuning
Conformational Molecular Switches for Post-CMOS Nanoelectronics
An Accurate Ultra-Compact I-V Model for Nanometer MOS Transistors With Applications on Digital Circuits
On the Complexity of Hybrid n-Term Karatsuba Multiplier for Trinomials
Application of Kalman Gain for Minimum Mean-Squared Phase-Error Bound in Bang-Bang CDRs
Reconfigurable SiGe Low-Noise Amplifiers With Variable Miller Capacitance
On the Excess Noise Factor Gamma of a FET Driven by a Capacitive Source