yusuke1997/dblp-id-title huggingface dataset:
A DPA Attack on IOA Data-Dependent Delay Countermeasure Based on an Inherent Tempo-Spatial Data Dependency
The Combination of High-Gain Sliding Mode Observers Used as Receivers in Secure Communication
An 18-Gb/s NRZ Transceiver With a Channel-Included 2-UI Impulse-Response Filtering FFE and 1-Tap DFE Compensating up to 32-dB Loss
Shifted-Frequency Analysis for EMTP Simulation of Power-System Dynamics
A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration
A Compact Fully Passive Loop Filter-Based Continuous Time ΔΣ Modulator for Multi-Channel Biomedical Applications
Intersignal Timing Skew Compensation of Parallel Links With Voltage-Mode Incremental Signaling
A Driving and Compensation Method for AMLED Displays Using Adaptive Reference Generator for High Luminance Uniformity
A Wide-Voltage-Range Transition-Detector With In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in 28 nm CMOS
An Efficient Neural Network Model for Solving the Absolute Value Equations
On the Noise Optimization of CMOS Common-Source Low-Noise Amplifiers
Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase
Single-/Dual-BPF Using Coupled-Line Stepped Impedance Resonators (CLSIR)
RF-Only Logic: an Area Efficient Logic Family for RF-Power Harvesting Applications
Pinning-Controllability Analysis of Complex Networks: An M-Matrix Approach
Time-of-Arrival Measurement Using Adaptive CMOS IR-UWB Range Finder With Scalable Resolution
Global synchronization and asymptotic stability of complex dynamical networks
Mutual Exclusion Sizing for Hoi Polloi
A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator
Voltage Stability Margin in DC Grids With CPLs: A Recursive Newton-Raphson Approximation
A 38- to 40-GHz Current-Reused Active Phase Shifter Based on the Coupled Resonator
Fundamental Properties of Non-Negative Impulse Response Filters
Reduction of phase noise in linear HBT amplifiers using low-frequency active feedback
A 28-30 GHz CMOS Reflection-Type Phase Shifter With Full 360° Phase Shift Range
Rigorous DC Solution of Partial Element Equivalent Circuit Models
Colored Subspace Analysis: Dimension Reduction Based on a Signal's Autocorrelation Structure
Synchronization of networks with prescribed degree distributions
Distributed Consensus of Multi-Agent Systems With Input Constraints: A Model Predictive Control Approach
A 1.6-V 25-µ A 5-ppm/°C Curvature-Compensated Bandgap Reference
Guest Editorial Special Section on the 2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015)
A High Efficiency AC/DC NVC-PSSHI Electrical Interface for Vibration-Based Energy Harvesters
A Low Walk Error Analog Front-End Circuit With Intensity Compensation for Direct ToF LiDAR
A Low-Power and Flexible Energy Detection IR-UWB Receiver for RFID and Wireless Sensor Networks
LAURA-NoC: Local Automatic Rate Adjustment in Network-on-Chips With a Simple DVFS
Design Optimization Considering Guiding Template Feasibility and Redundant Via Insertion for Directed Self-Assembly
A Power-Efficient Multipin ILP-Based Routing Technique
Theoretical Design and Circuit Implementation of Multidirectional Multi-Torus Chaotic Attractors
A dual voltage-frequency VLSI chip for image watermarking in DCT domain
A 1.5-V Current Mirror Double-Balanced Mixer With 10-dBm IIP3 and 9.5-dB Conversion Gain
Frequency-Selective Noise-Compensated Autoregressive Estimation
Mismatch Characterization of Small Metal Fringe Capacitors
Matching for Concurrent Harmonic Sensing in an M-Phase Mixer-First Receiver
Robust impulsive synchronization of uncertain dynamical networks
A Compact Substrate Integrated Waveguide Cavity-Backed Self-Triplexing Antenna
A W-Band 6-Bit Phase Shifter With 7 dB Gain and 1.35° RMS Phase Error in 130 nm SiGe BiCMOS
Morphological undecimated wavelet decomposition for fault location on power transmission lines
An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency
Flux-Charge Description of Circuits With Non-Volatile Switching Memristor Devices
Exponential Synchronization of Delayed Neural Networks With Discontinuous Activations
A 12-b 40-MS/s Calibration-Free SAR ADC
Hybrid Formulation of the Equation Systems of the 3-D PEEC Model Based on Graph Algorithms
A 4-Element 60-GHz CMOS Phased-Array Receiver With Beamforming Calibration
Global convergence of Lotka-Volterra recurrent neural networks with delays
Selectively Sampled Subharmonic-Free Digital Current Mode Control Using Direct Duty Control
Adaptive Multiple-Resolution CMOS Active Pixel Sensor
A 50-MHz-1-GHz 2.3-dB NF Noise-Cancelling Balun-LNA Employing a Modified Current-Bleeding Technique and Balanced Loads
A Fully Multiplexed First-Order Frequency-Planar Module for Fan, Beam, and Cone Plane-Wave Filters
Implementation Trade-Offs of Soft-Input Soft-Output MAP Decoders for Convolutional Codes
Design Considerations for Cascade Delta Sigma ADC's
A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX
A Pulse Frequency Modulation VCO-ADC in 40 nm
High Accuracy Knee Voltage Detection for Primary-Side Control in Flyback Battery Charger
Reliable Ultra-Low-Voltage Cache Design for Many-Core Systems
Event-Triggered Fuzzy Control of Repeated Scalar Nonlinear Systems and its Application to Chua's Circuit System
A Low-Voltage High-Precision Time-Domain Winner-Take-All Circuit
A Mixed-Loop CMOS Analog GFSK Modulator With Tunable Modulation Index
Non-Uniform Wavelet Sampling for RF Analog-to-Information Conversion
Design Fixed-Time Practical Distributed Average Tracking Algorithms for Nonlinear Signals With Bounded- and Lipschitz-Type Derivatives
Approximation of the Fractional-Order Laplacian s α as a Weighted Sum of First-Order High-Pass Filters
High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems
Gain-Cell Embedded DRAM-Based Physical Unclonable Function
0.9-V Class-AB Miller OTA in 0.35-µm CMOS With Threshold-Lowered Non-Tailed Differential Pair
An Ultra-Energy-Efficient Wide-Bandwidth Video Pipeline ADC Using Optimized Architectural Partitioning
Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier
Increasing Electrical Damping in Energy-Harnessing Transducers
Optimization of Noise Shaping Filter for Quantizer With Error Feedback
Small-World Regular Networks for Communication
Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform
A 70-mW ISDB-T Tuner for VHF and UHF Bands
A 0.5 V, 9-GHz Sub-Integer Frequency Synthesizer Using Multi-Phase Injection-Locked Prescaler for Phase-Switching-Based Programmable Division With Automatic Injection-Lock Calibration in 45-nm CMOS
A Fifth-Order 20-MHz Transistorized-LC-Ladder LPF With 58.2-dB SFDR, 68-µW/Pole/MHz Efficiency, and 0.13-mm 2 Die Size in 90-nm CMOS
Hybrid filtered error LMS algorithm: another alternative to filtered-x LMS
Low Computational Complexity, Low Power, and Low Area Design for the Implementation of Recursive DFT and IDFT Algorithms
A New Class of Digital Circuits for the Design of Entropy Sources in Programmable Logic
Quadratic Power Conversion for Power Electronics: Principles and Circuits
Linearization Techniques for CMOS Low Noise Amplifiers: A Tutorial
A 1.1-V Analog Multiplexer With an Adaptive Digital Clamp for CMOS Video Digitizers
Power harvesting and telemetry in CMOS for implanted devices
A Framework for the Lower Bound on the BER of DCSK Systems Over Multi-Path Nakagami-m Fading Channels
Novel Feedback Theory of Electric Circuits - Part II: Loop Invariants
A Low Power 12-bit 1-kS/s SAR ADC for Biomedical Signal Processing
Normalization and Multi-Valued Symbol Extraction From RO-PUFs for Enhanced Uniform Probability Distributions
Circuit and System Designs of Ultra-Low Power Sensor Nodes With Illustration in a Miniaturized GNSS Logger for Position Tracking: Part I - Analog Circuit Techniques
Waypoint Path Planning With Synaptic-Dependent Spike Latency
A 240-MHz Low-Pass Filter With Variable Gain in 65-nm CMOS for a UWB Radio Receiver
Indirect-Feedback Sigma-Delta Image Sensors: Theory, Modeling and Design
90 nm 32 times 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation
Estimation of an Initial Condition of Sigma-Delta Modulators via Projection Onto Convex Sets
Multi-User Hybrid MIMO at 60 GHz Using 16-Antenna Transmitters
CMOS Startup Charge Pump With Body Bias and Backward Control for Energy Harvesting Step-Up Converters
Selective Normalized Subband Adaptive Filter With Subband Extension
Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators
A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector
A Convex Combination of NLMS and ZA-NLMS for Identifying Systems With Variable Sparsity
A 10-GS/s 4-Bit Single-Core Digital-to-Analog Converter for Cognitive Ultrawidebands
Performance Enhancement of Colpitts Oscillators by Parasitic Cancellation
Trigonometric polynomial interpolation for timing recovery
An Amplitude Resolution Improvement of an RF-DAC Employing Pulsewidth Modulation
Dual-Metastability Time-Competitive True Random Number Generator
Security of public-key cryptosystems based on Chebyshev polynomials
Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM
A Novel Architecture of Delta-Sigma Modulator Enabling All-Digital Multiband Multistandard RF Transmitters Design
Nullcline-Based Design of a Silicon Neuron
The Role of Charge Pump Mismatch in the Generation of Integer Boundary Spurs in Fractional-N Frequency Synthesizers: Why Worse Can Be Better
Fully Configurable Capacitor-Less Oversampling DC Offset Cancellation for Direct Conversion Receivers
Analysis and Design of Mixed-Mode Operation for Noninverting Buck-Boost DC-DC Converters
A Low-Power Vision System With Adaptive Background Subtraction and Image Segmentation for Unusual Event Detection
Design and Analysis of 239 GHz CMOS Push-Push Transformer-Based VCO With High Efficiency and Wide Tuning Range
Evolution of substrate noise generation mechanisms with CMOS technology scaling
An Integrated System for Simultaneous, Multichannel Neuronal Stimulation and Recording
Variable Threshold-Based Selective Updating Algorithms in Feed-Forward Active Noise Control Systems
Low-Power LDPC-CC Decoding Architecture Based on the Integration of Memory Banks
Segmented Dynamic Element Matching for High-Resolution Digital-to-Analog Conversion
A Low-Power Programmable Bandpass Filter Section for Higher Order Filter Applications
CMOS Image Sensor for Lateral Flow Immunoassay Readers
Neural-network-based adaptive baseband predistortion method for RF power amplifiers
Front End Power Dissipation Minimization and Optimal Transmission Rate for Wireless Receivers
An Ultralow-Power Dual-Band UWB Impulse Radio
Porting and Scaling Strategies for Nanoscale CMOS RHBD
Dynamical effects of missed switching in current-mode controlled DC-DC converters
Theory and Implementation of a Load-Mismatch Protective Class-E PA System
Physical Modeling of MEMS Variable Inductor
Computing multivalued input-output Characteristics in the circuits containing bipolar transistors
Resonant converter with inherent short-circuit protection
Differential Chaos Shift Keying: A Robust Modulation Scheme for Power-Line Communications
Semiblind channel estimation and equalization for MIMO space-time coded OFDM
Performance of DCSK Cooperative Communication Systems Over Multipath Fading Channels
A digital power spectrum estimation method for the adaptation of high-speed equalizers
Inter-Wire Coupling Reduction Analysis of Bus-Invert Coding
Leader-Follower Bipartite Consensus of Linear Multiagent Systems Over a Signed Directed Graph
Demonstration of Uncoordinated Multiple Access in Optical Communications
Data-Driven Cooperative Output Regulation of Multi-Agent Systems via Robust Adaptive Dynamic Programming
A Novel CH5 Inverter for Single-Phase Transformerless Photovoltaic System Applications
Matrix-Interpolation-Based Parametric Model Order Reduction for Multiconductor Transmission Lines With Delays
Profile-Based Output Error Compensation for Approximate Arithmetic Circuits
Reconfigurable Frequency Response Masking Filters for Software Radio Channelization
A Gm-C Delta-Sigma Modulator With a Merged Input-Feedback Gm Circuit for Nonlinearity Cancellation and Power Efficiency Enhancement
A 60 dB Harmonic Rejection Mixer for Digital Terrestrial TV Tuner
Dual Band VCO Based on a High-Quality Factor Switched Interdigital Resonator for the Ku Band Using 180-nm CMOS Technology
Realization of modular multidimensional complex digital filters using GIC concept
FPGA-Based Implementation of Multiple Modes in Near Field Inductive Communication Using Frequency Splitting and MIMO Configuration
Hysteretic Control Embedded Boost Converter Operating at 25-MHz Switching
Utilizing Process Variations for Reference Generation in a Flash ADC
A 30-75 dBΩ 2.5 GHz 0.13-μm CMOS Receiver Front-End With Large Input Capacitance Tolerance for Short-Range Optical Communication
Circuit Theory in Projective Space and Homogeneous Circuit Models
40-nm CMOS Wideband High-IF Receiver Using a Modified Charge-Sharing Bandpass Filter to Boost Q-Factor
A Bounded and Discretized Nelder-Mead Algorithm Suitable for RFIC Calibration
Pole-Controlled Wideband 120 GHz CMOS Power Amplifier for Wireless Chip-to-Chip Communication in 40-nm CMOS Process
High-CMRR Current Amplifier Architecture and Its CMOS Implementation
Locking Range Derivations for Injection-Locked Class-E Oscillator Applying Phase Reduction Theory
Three-Level Cell Topology for a Multilevel Power Supply to Achieve High Efficiency Envelope Amplifier
Bandwidth Enhancement of Flip-Flops Using Feedback for High-Speed Integrated Circuits
Efficient FPGA Implementations of Pair and Triplet-Based STDP for Neuromorphic Architectures
1-to- $N$ Ring Power Combiners With Common Delta Ports
Symmetry-Breaking Bifurcation in Series-Parallel Load Resonant DC-DC Converters
A Broadband Doherty Power Amplifier With Hybrid Class-EFJ Mode
Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures
Partial identification of Lorenz system and its application to key space reduction of chaotic cryptosystems
Distributed Federated Kalman Filter Fusion Over Multi-Sensor Unreliable Networked Systems
Generation of Filter Bank-Based Multicarrier Waveform Using Partial Synthesis and Time Domain Interpolation
A Broadband Low-Power Millimeter-Wave CMOS Downconversion Mixer With Improved Linearity
A 10-Gb/s Reference-Less Baud-Rate CDR for Low Power Consumption With the Direct Feedback Method
Analysis of Imperfections on Performance of 4-Phase Passive-Mixer-Based High-Q Bandpass Filters in SAW-Less Receivers
Synchronization in Networks of Hindmarsh-Rose Neurons
Homogeneous Models of Nonlinear Circuits
An Analytic Circuit-Based Model for White and Flicker Phase Noise in LC Oscillators
On the Realization of 2-D Linear Systems With Recursively Computable Latent Variable Models
Direct frequency modulation of an ADPLL for bluetooth/GSM with injection pulling elimination
Low-voltage high-performance voltage-mode and current-mode WTA circuits based on flipped voltage followers
High-Efficiency Power Amplifier Employing Minimum-Power Harmonic Active Load Modulator
An Ultrafast Adaptively Biased Capacitorless LDO With Dynamic Charging Control
Gain and offset mismatch calibration in time-interleaved multipath A/D sigma-delta modulators
Dynamic MOS sigmoid array folding analog-to-digital conversion
Thresholding noise-free ordered mean filter based on Dempster-Shafer theory for image restoration
An Improved PWM Technique to Achieve Continuous Input Current in Common-Ground Transformerless Boost Inverter
Investigation of a Voltage-Mode Controller for a dc-dc Multilevel Boost Converter
Digital Background Calibration With Histogram of Decision Points in Pipelined ADCs
AW-SOM, an Algorithm for High-Speed Learning in Hardware Self-Organizing Maps
A 38 Gb/s to 43 Gb/s Monolithic Optical Receiver in 65 nm CMOS Technology
History Erase Effect in a Non-Volatile Memristor
On Frequency Detection Capability of Full-Rate Linear and Binary Phase Detectors
Comments on "A 16-bit 65-MS/s Pipeline ADC With 80-dBFS SNR Using Analog Auto-Calibration in SiGe SOI Complementary BiCMOS"
Weak Signal Estimation in Chaotic Clutter Using Model-Based Coupled Synchronization
Pinning Complex Networks by a Single Controller
Design of Real FIR Filters With Arbitrary Magnitude and Phase Specifications Using a Neural-Based Approach
Gain-Error Calibration of a Pipelined ADC in an Adaptively Equalized Baseband Receiver
Miller Theorem for Weakly Nonlinear Feedback Circuits and Application to CE Amplifier
Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits
Quantized Output Feedback Control for Stochastic Semi-Markov Jump Systems With Unreliable Links
An Adaptive Digital Front-End for Multimode Wireless Receivers
Unified Stability Criteria of Random Nonlinear Time-Varying Impulsive Switched Systems
Coexisting Fast-Scale and Slow-Scale Instability in Current-Mode Controlled DC/DC Converters: Analysis, Simulation and Experimental Results
A 2.2 µW, -12 dBm RF-Powered Wireless Current Sensing Readout Interface IC With Injection-Locking Clock Generation
All-Digital Adaptive Module for Automatic Background IIP2 Calibration in CMOS Downconverters With Fast Convergence
Low-Complexity Elliptic Curve Cryptography Processor Based on Configurable Partial Modular Reduction Over NIST Prime Fields
Tunable Block Floating-Point Quantizer With Fractional Exponent for Compressing Non-Uniformly Distributed Signals
Case Study of a Hybrid Optoelectronic Limiting Receiver
An Ultralow-Power Wake-Up Receiver Based on Direct Active RF Detection
Dual-Mode All-Digital Baseband Receiver With a Feed-Forward and Shared-Memory Architecture for Dual-Standard Over 60 GHz NLOS Channel
A 1.4-mW 14-MHz MEMS Oscillator Based on a Differential Adjustable-Bandwidth Transimpedance Amplifier and Piezoelectric Disk Resonator
Robust Variable Step-Size Reweighted Zero-Attracting Least Mean M-Estimate Algorithm for Sparse System Identification
The Theory of Special Noise Invariants
A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power
Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors
Series-Parallel Six-Element Synthesis of Biquadratic Impedances
Data-Driven Filtering for Nonlinear Systems With Bounded Noises and Quantized Measurements
Testable MUTEX Design
Beamspace Channel Estimation for Massive MIMO mmWave Systems: Algorithm and VLSI Design
On a new topology for the transconductance feedback amplifier
Phase-Encoding for On-Chip Signalling
On the Design of n th-Order Polyphase All-Pass Filters
Stabilization of Bilinear Systems Via Linear State-Feedback Control
Single-Inductor Dual-Input Dual-Output Battery-PV Hybrid System With 2-D Adaptive On-Time Control for Internet of Things
A 28GHz Reflective-Type Transmission-Line-Based Phase Shifter
Fast Algorithm and Low-Cost Hardware-Sharing Design of Multiple Integer Transforms for VC-1
A New Design Method of the Starting Block in Lattice Structure of Arbitrary-Length Linear Phase Paraunitary Filter Bank by Combining Two Polyphase Matrices
A 48 Gb/s PAM-4 Transmitter With 3-Tap FFE Based on Double-Shielded Coplanar Waveguide in 65-nm CMOS
A 1.45 GHz All-Digital Spread Spectrum Clock Generator in 65nm CMOS for Synchronization-Free SoC Applications
Nonvolatile Multilevel Resistive Switching Memory Cell: A Transition Metal Oxide-Based Circuit
Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC
Decoupling Minimax Design of Low-Complexity Variable Fractional-Delay FIR Digital Filters
A Study of the Impact of Delay Mismatch on Linearity of Outphasing Transmitters
Modeling and Understanding Ethereum Transaction Records via a Complex Network Approach
On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator
Corrections and Comments to "Model Reduction of Discrete Linear Systems Via Frequency-Domain Balanced Structure"
A V-Band CMOS VCO With Digitally-Controlled Inductor for Frequency Tuning
A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies
Analysis and Verification of DLL-Based GFSK Demodulator Using Multiple-IF-Period Delay Line
A High-Linearity, 17 ps Precision Time-to-Digital Converter Based on a Single-Stage Vernier Delay Loop Fine Interpolation
Low-Complexity Ultra-Wide-Band Communications
Complex-Valued Adaptive Filtering Based on the Random Fourier Features Method
Construction of Markov Partitions in PL1D Maps
Symbolic Nodal Analysis of Circuits Using Pathological Elements
A 1-16-Gb/s Wide-Range Clock/Data Recovery Circuit With a Bidirectional Frequency Detector
All-Digital Time-Domain Smart Temperature Sensor With an Inter-Batch Inaccuracy of -0.7~°C - +0.6~°C After One-Point Calibration
A 0.42-3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition
A 12-Bit 125-MS/s 2.5-Bit/Cycle SAR-Based Pipeline ADC Employing a Self-Biased Gain Boosting Amplifier
Power-Constrained Third-Order Active Notch Filter Applied in IR-LNA for UWB Standards
DT-CNN: An Energy-Efficient Dilated and Transposed Convolutional Neural Network Processor for Region of Interest Based Image Segmentation
Digital Predistortion for Power Amplifier Based on Sparse Bayesian Learning
Bandpass Filtering Doherty Power Amplifier With Enhanced Efficiency and Wideband Harmonic Suppression
Automated Framework for Time-Domain Piecewise-Linear Fitting Method Based on Digital Wave Processing of S-Parameters
A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration
Derivation of the Most Energy-Efficient Source Functions by Using Calculus of Variations
A Low-Noise Self-Oscillating Mixer Using a Balanced VCO Load
Digital Multiplierless Realization of Two Coupled Biological Morris-Lecar Neuron Model
Low-Latency Double Point Multiplication Architecture Using Differential Addition Chain Over $GF(2^m)$
Optimal Complexity Architectures for Pipelined Distributed Arithmetic-Based LMS Adaptive Filter
Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism
Multivaluedness in Networks: Theory
Global asymptotic stability of delayed Cohen-Grossberg neural networks
A 5.5-GHz 1-mW Full-Modulus-Range Programmable Frequency Divider in 90-nm CMOS Process
Identification of Dynamical Behavior of Pseudoperiodic Time Series by Network Community Structure
A High-Precision Compensated CMOS Bandgap Voltage Reference Without Resistors
Mismatch and dynamic modeling of current sources in current-steering CMOS D/A converters: an extended design procedure
A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13 µm CMOS
Current-Reuse Transformer-Coupled Oscillators With Output Power Combining for Galvanically Isolated Power Transfer Systems
Low-Complexity Welch Power Spectral Density Computation
The Stability and Continuity Behavior of the Spectral Factorization in the Wiener Algebra With Applications in Wiener Filtering
Non-Isolated Single-Inductor DC/DC Converter With Fully Reconfigurable Structure for Renewable Energy Applications
An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design
Analysis and synthesis of pHEMT class-E amplifiers with shunt inductor including ON-state active-device resistance effects
A CMOS Active- RC Low-Pass Filter With Simultaneously Tunable High- and Low-Cutoff Frequencies for IEEE 802.22 Applications
A CMOS Temperature Sensor With Versatile Readout Scheme and High Accuracy for Multi-Sensor Systems
Multi-Bound-Dependent Stability Criterion for Digital Filters With Overflow Arithmetics and Time Delay
A Low-Power Multicarrier-CDMA Downlink Baseband Receiver for Future Cellular Communication Systems
Analytical Synthesis of Low-Sensitivity High-Order Voltage-Mode DDCC and FDCCII-Grounded R and C All-Pass Filter Structures
Convergence Analysis of an Adaptive Algorithm With Output Power Constraints
On incremental sigma-delta modulation with optimal filtering
Reduced-Order Observer-Based Sliding Mode Control for Singular Markovian Jump System With Time-Varying Transition Rate