yusuke1997/dblp-id-title huggingface dataset:
Precision Passive-Charge-Sharing SAR ADC: Analysis, Design, and Measurement Results
Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs
Surface micromachined accelerometers
A Continuous-Time Zoom ADC for Low-Power Audio Applications
A 160 dB Equivalent Dynamic Range Auto-Scaling Interface for Resistive Gas Sensors Arrays
A 250-MHz skewed-clock pipelined data buffer
Design of Active N-Path Filters
Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC
A 53-Gbit/s Optical Receiver Frontend With 0.65 pJ/bit in 28-nm Bulk-CMOS
An unconditionally stable two-stage CMOS amplifier
A 128 × 128 pixel 120-dB dynamic-range vision-sensor chip for image contrast and orientation extraction
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]
A 19.8-mW Eddy-Current Displacement Sensor Interface With Sub-Nanometer Resolution
An ultralow-energy ADC for Smart Dust
A BiCMOS thermal head intelligent driver with density controllers for full-tone rendition printers
A 30 A 30 V DMOS motor controller and driver
Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS
A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging
1.4Gsearch/s 2-Mb/mm 2 TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%
Low-voltage ULSI design
A Fully Integrated 2.4-GHz IEEE 802.15.4-Compliant Transceiver for ZigBee™ Applications
A Fully Integrated 20-Gb/s Optoelectronic Transceiver Implemented in a Standard 0.13- $\mu{\hbox {m}}$ CMOS SOI Technology
Advanced architecture for a one-chip 16*16 digital switch
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance
Statistical design techniques for D/A converters
Low-power, high-gain, and high-linearity SiGe BiCMOS wide-band low-noise amplifier
Integrated continuous-time filter design - an overview
A 512-kb flash EEPROM embedded in a 32-b microcontroller
A 25-to-28 Gb/s High-Sensitivity (-9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects
A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI
An 802.11ax 4 × 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer
Multipath Wide-Bandwidth CMOS Magnetic Sensors
A 102.2-dB, 181.1-dB FoM Extended Counting Analog-to-Digital Converter With Capacitor Scaling
24-Bit 5.0 GHz Direct Digital Synthesizer RFIC With Direct Digital Modulations in 0.13 μ m SiGe BiCMOS Technology
ASIC Implementation of Soft-Input Soft-Output MIMO Detection Using MMSE Parallel Interference Cancellation
Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology
Absolute Value, 1% Linear and Lossless Current-Sensing Circuit for the Step-Down DC-DC Converters With Integrated Power Stage
A 3 Megapixel 100 Fps 2.8 µm Pixel Pitch CMOS Image Sensor Layer With Built-in Self-Test for 3D Integrated Imagers
Synchronous-mode evaluation of delays in CMOS structures
A 100-MS/s 8-b CMOS subranging ADC with sustained parametric performance from 3.8 V down to 2.2 V
An Ultra-Wideband Impulse-Radio Transceiver Chipset Using Synchronized-OOK Modulation
A 2.4-GHz, Sub-1-V, 2.8-dB NF, 475-µW Dual-Path Noise and Nonlinearity Cancelling LNA for Ultra-Low-Power Radios
A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL
Low-power current-mode 0.9-V voltage regulator
A 4-Port-Inductor-Based VCO Coupling Method for Phase Noise Reduction
Design of a 4-MHz analog integrated CMOS transconductance-C bandpass filter
Arithmetic Progression Switched-Capacitor DC-DC Converter Topology With Soft VCR Transitions and Quasi-Symmetric Two-Phase Charge Delivery
Millimeter-Wave Devices and Circuit Blocks up to 104 GHz in 90 nm CMOS
A pipeline A/D converter architecture with low DNL
A 60 mW Class-G Stereo Headphone Driver for Portable Battery-Powered Devices
A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC
A Symbol-Based Power-Tracking Supply Modulator Integrated With a 28-GHz CMOS PA for 5G FR2
Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V
A Global-Shutter CMOS Image Sensor With Readout Speed of 1-Tpixel/s Burst and 780-Mpixel/s Continuous
The use of stabilized CMOS delay lines for the digitization of short time intervals
A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator
A 0.0285-mm 2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR Without Reference and Separate FD Pulling Off an 8.2-Gb/s/μs Acquisition Speed of the PAM-4 Input in 28-nm CMOS
An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization
A variable gain RF front-end, based on a Voltage-Voltage feedback LNA, for multistandard applications
A 2.02-5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS
Smart sensor interface with A/D conversion and programmable calibration
Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver
MESFET MMIC Ka-band transmitter performance for high-volume system applications
A 1.544-Mb/s CMOS line driver for a 22.8- Omega load
A 14 mW 2.5 MS/s 14 bit ΣΔ Modulator Using Split-Path Pseudo-Differential Amplifiers
Comment on "A nonlinear CMOS analog cell for VLSI signal and information processing"
A Universal Modular Hybrid LDO With Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning
Offset compensating bit-line sensing scheme for high density DRAM's
The performance of source-coupled FET logic circuits that use GaAs MESFETs
A PWM Based Fully Integrated Digital Transmitter/PA for WLAN and LTE Applications
A tool towards integration of IC process, device, and circuit simulation
A Calibration-Free 13-Bit 10-MS/s Full-Analog SAR ADC With Continuous-Time Feedforward Cascaded Op-Amps
A 0.13 μm CMOS System-on-Chip for a 512 × 424 Time-of-Flight Image Sensor With Multi-Frequency Photo-Demodulation up to 130 MHz and 2 GS/s ADC
Correction to "Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA"
A very high precision 500-nA CMOS floating-gate analog voltage reference
A Time-Domain Current-Mode Buck Converter With a PI Compensator Incorporating an Infinite Phase Shift Delay Line
A Tri-Band Dual-Concurrent Wi-Fi 802.11be Transceiver Achieving -46 dB TX/RX EVM Floor at 7.1 GHz for a 4 K-QAM 320 MHz Signal
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process
A Delta Sigma-Modulated Sample and Average Common-Mode Feedback Technique for Capacitively Coupled Amplifiers in a 192-nW Acoustic Analog Front-End
Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops
A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-µm CMOS
Wideband Hybrid Envelope Tracking Modulator With Hysteretic-Controlled Three-Level Switching Converter and Slew-Rate Enhanced Linear Amplifier
A 65-nm Neuromorphic Image Classification Processor With Energy-Efficient Training Through Direct Spike-Only Feedback
A low-impedance open-bitline array for multigigabit DRAM
ReDCIM: Reconfigurable Digital Computing- In -Memory Processor With Unified FP/INT Pipeline for Cloud AI Acceleration
Design and Analysis of a 140-GHz T/R Front-End Module in 22-nm FD-SOI CMOS
A 4.5-mW 900-MHz CMOS receiver for wireless paging
Simulation techniques for mixed analog/digital circuits
Privacy Protection NAND Flash System With Flexible Data-Lifetime Control by In-3-D Vertical Cell Processing
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification
A Low-Power, Wide-Bandwidth, Three-Axis MEMS Accelerometer ASIC Using Beyond-Resonant-Frequency Sensing
A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive
A 10-Bit 500-MS/s 55-mW CMOS ADC
A four-channel digital signal processor in 1.2- mu m CMOS with on-chip D/A and A/D conversion serving four speech channels in a new-generation subscriber line circuit
Design and Analysis of Chopper Stabilized Injection-Locked Oscillator Sensors Employing Near-Field Modulation
A 130-nm triple-V t 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor
A 6.78-MHz Single-Stage Wireless Power Receiver Using a 3-Mode Reconfigurable Resonant Regulating Rectifier
A Polar Modulator Using Self-Oscillating Amplifiers and an Injection-Locked Upconversion Mixer
Future directions in microprocessor technology
A 3.2 ppm/°C Second-Order Temperature Compensated CMOS On-Chip Oscillator Using Voltage Ratio Adjusting Technique
Correction to "CMOS high-frequency switched-capacitor filters for telecommunication applications"
A 2-GHz wide-band direct conversion receiver for WCDMA applications
An Incremental-Charge-Based Digital Transmitter With Built-in Filtering
Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection
A Reflection-Mode N-Path Filter Tunable From 6 to 31 GHz
Wide-band integrated optical receiver with improved dynamic range using a current switch at the input
A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology
A curvature-corrected low-voltage bandgap reference
16-channel oversampled analog-to-digital converter
Cell libraries and assembly tools for analog/digital CMOS and BiCMOS application-specific integrated circuit design
A circuit level hot-carrier evaluation system
A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion technique
A 3.3-V, low-distortion ISDN line driver with a novel quiescent current control circuit
Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector
A 1.9-GHz single chip IF transceiver for digital cordless phones
Wandering Spur Suppression in a 4.9-GHz Fractional-N Frequency Synthesizer
A 70-mW seventh-order filter with 7-50 MHz cutoff frequency and programmable boost and group delay equalization
A 1.52-W Capacitor-Drop Sigma-Floating-SC AC/DC Converter for Grid Power to IoT Devices
A GaAs phase digitizing and summing system for microwave signal storage
A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers
A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator
Low-voltage coefficient capacitors for VLSI processes
A 160 ˟ 120-Pixels Range Camera With In-Pixel Correlated Double Sampling and Fixed-Pattern Noise Correction
SiGe Clock and Data Recovery System Based on Injection-Locked Oscillator for 100 Gbit/s Serial Data Link
A Dynamic Power Reduction Technique for Incremental $\Delta\Sigma$ Modulators
A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization
A Fully Integrated Digital Polar Transmitter With Single-Ended Doherty PA and DLL-Based Three-Segment Hybrid DTC in 28 nm CMOS
Fast & Energy Efficient Start-Up of Crystal Oscillators by Self-Timed Energy Injection
A 640-Mb/s 2048-bit programmable LDPC decoder chip
VERDI: an acoustically programmable and adjustable CMOS mixed-mode signal processor for hearing aid applications
A 5.58 nW Crystal Oscillator Using Pulsed Driver for Real-Time Clocks
A 16-Mb flash EEPROM with a new self-data-refresh scheme for a sector erase operation
On-Chip Condition-Adaptive Δ f 3 EMI Control for Switching Power ICs
A Low-Complexity FM-UWB Transmitter With Digital Reuse and Analog Stacking
Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators
A Multi-Path Inductor-First Inductor-on-Ground Switched-Capacitor Hybrid DC-DC Converter
A Mostly Digital VCO-Based CT-SDM With Third-Order Noise Shaping
A 19.2 GOPS mixed-signal filter with floating-gate adaptation
A Compact E-Band Load-Modulation Balanced Power Amplifier in 65-nm CMOS
A VLSI RISC with 20-MFLOPS peak, 64-bit floating-point unit
Multi-Mode Spatial Signal Processor With Rainbow-Like Fast Beam Training and Wideband Communications Using True-Time-Delay Arrays
A 540-MHz 10-b polar-to-Cartesian converter
A Compact Dual-Band Digital Polar Doherty Power Amplifier Using Parallel-Combining Transformer
Variable bit organization as a new test function for standard memories
Analysis of latchup and parasitic effects in merged BiCMOS structures
A 2-V 600-μA 1-GHz BiCMOS super-regenerative receiver for ISM applications
A 52-73-GHz LNA With Tri-Coupled Transformer for G m Boosting and Enhanced Noise Canceling
A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-μm CMOS
Mixed-signal quadrature demodulator with a multicarrier regeneration system
A Monolithic GaN-IC With Integrated Control Loop for 400-V Offline Buck Operation Achieving 95.6% Peak Efficiency
Steamroller Module and Adaptive Clocking System in 28 nm CMOS
A High DR, DC-Coupled, Time-Based Neural-Recording IC With Degeneration R-DAC for Bidirectional Neural Interface
Performance limits of mixed analog/digital circuits with scaled MOSFETs
A low glitch 10-bit 75-MHz CMOS video D/A converter
Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's
A 42-Gb/s Noise-Tolerant Single-Ended Clock-Referenced PAM3 Transceiver for Chiplet Interfaces
A 245-mA Digitally Assisted Dual-Loop Low-Dropout Regulator
A 25-30 GHz Fully-Connected Hybrid Beamforming Receiver for MIMO Communication
A 0.5-16.3 Gb/s Fully Adaptive Flexible-Reach Transceiver for FPGA in 20 nm CMOS
A 0.4 µg Bias Instability and 1.2 µg Hz Noise Floor MEMS Silicon Oscillating Accelerometer With CMOS Readout Circuit
Jitter transfer characteristics of delay-locked loops - theories and design techniques
Continuous-time common-mode feedback for high-speed switched-capacitor networks
Personal Inertial Navigation System Assisted by MEMS Ground Reaction Sensor Array and Interface ASIC for GPS-Denied Environment
A super-dynamic flip-flop circuit for broad-band applications up to 24 Gb/s utilizing production-level 0.2-μm GaAs MESFETs
ESD protection for CMOS output buffer by using modified LVTSCR devices with high trigger current
A 0.5 V Sub-Microwatt CMOS Image Sensor With Pulse-Width Modulation Read-Out
An X- and Ku-Band 8-Element Phased-Array Receiver in 0.18-µm SiGe BiCMOS Technology
A fully integrated 24-GHz phased-array transmitter in CMOS
Guest Editorial: Special Section on the 48th European Solid-State Circuits Conference (ESSCIRC)
An Ultra-Low-Power Dual-Polarization Transceiver Front-End for 94-GHz Phased Arrays in 130-nm InP HBT
A 20-MIPS sustained 32-bit CMOS microprocessor with high ratio of sustained to peak performance
85-to-127 GHz CMOS Signal Generation Using a Quadrature VCO With Passive Coupling and Broadband Harmonic Combining for Rotational Spectroscopy
Automated Hierarchical Cmos Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations
SYMCELL-a symbolic standard cell system
A low-power 8-b 1 3.5-MHz video CMOS ADC for visiophony ISDN applications
A dual-core 64-bit ultraSPARC microprocessor for dense server applications
A 3x9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O
An Integral Path Self-Calibration Scheme for a Dual-Loop PLL
A 137 dB Dynamic Range and 0.32 V Self-Powered CMOS Imager With Energy Harvesting Pixels
A 10-bit 400-MS/s 160-mW 0.13-μm CMOS dual-channel pipeline ADC without channel mismatch calibration
An oversampled multibit CMOS D/A converter for digital audio with 115-dB dynamic range
Active-RC Filters Using the Gm-Assisted OTA-RC Technique
A D -Band Digital Transmitter with 64-QAM and OFDM Free-Space Constellation Formation
A 53-to-75-mW, 59.3-dB HRR, TV-Band White-Space Transmitter Using a Low-Frequency Reference LO in 65-nm CMOS
Distributed Differential Oscillators for Global Clock Networks
A Low-Power 114-GHz Push-Push CMOS VCO Using LC Source Degeneration
Evolution on SoC Integration: GSM Baseband-Radio in 0.13 µm CMOS Extended by Fully Integrated Power Management Unit
A 200 MHz CMOS Q-enhanced LC bandpass filter
An 11-nW CMOS Temperature-to-Digital Converter Utilizing Sub-Threshold Current at Sub-Thermal Drain Voltage
A 4Ω 2.65W Class-D Audio Amplifier With Embedded DC-DC Boost Converter, Current Sensing ADC and DSP for Adaptive Speaker Protection
Fast low-power decoders for RAMs
A hybrid analog and digital VLSI neural network for intracardiac morphology classification
A 457 nW Near-Threshold Cognitive Multi-Functional ECG Processor for Long-Term Cardiac Monitoring
A 2.89 µW Dry-Electrode Enabled Clockless Wireless ECG SoC for Wearable Applications
Low-voltage double-sampled ΣΔ converters
New efficient designs for XOR and XNOR functions on the transistor level
A digitally controlled oscillator system for SAW-less transmitters in cellular handsets
Design of RF integrated circuits using SiGe bipolar technology
Scaling-CIM: eDRAM In-Memory-Computing Accelerator With Dynamic-Scaling ADC and Adaptive Analog Operation
Mixed digital/analog signal processing for a single-chip 2B1Q U-interface transceiver
BiCMOS current cell and switch for digital-to-analog converters
AsAP: An Asynchronous Array of Simple Processors
An analog VLSI implementation of a feature extractor for real time optical character recognition
CMOS-based microdisplay with calibrated backplane
A Low-Power Reflection-Coefficient Sensor for 28-GHz Beamforming Transmitters in 22-nm FD-SOI CMOS
Multi-Mode 60-GHz Radar Transmitter SoC in 45-nm SOI CMOS
A 10 Gb/s Inductorless AGC Amplifier With 40 dB Linear Variable Gain Control in 0.13 µm CMOS
RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance
Mixer-First MIMO Receiver With Reconfigurable Multi-Port Decoupling and Matching
A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface
A comprehensive submicrometer MOST delay model and its application to CMOS buffers
A 0.5-V 6.14- μW Trimming-Free Single-XO Dual-Output Frequency Reference With [5.1-nJ, 120- μs] XO Start-Up and [8.1-nJ, 200- μs] Successive-Approximation-Based RTC Calibration
A delta-sigma PLL for 14-b, 50 kSample/s frequency-to-digital conversion of a 10 MHz FM signal
An Autonomous Energy Harvesting Power Management Unit With Digital Regulation for IoT Applications
Area Efficient Integrated Gate Drivers Based on High-Voltage Charge Storing
A fully parallel 1-Mb CAM LSI for real-time pixel-parallel image processing
A wide input bandwidth 7-bit 300-MSample/s folding and current-mode interpolating ADC
A 965-Mb/s 1.0-μm standard CMOS twin-pipe serial/parallel multiplier
Pseudo-Continuous-Time Readout Circuit for a 300°s Capacitive 2-Axis Micro-Gyroscope
Palm NMR and 1-Chip NMR
A coupled sawtooth oscillator combining low jitter with high control linearity
A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture
A transversal equalizer with an increased adaptation speed and tracking capability
Data-dependent logic swing internal bus architecture for ultralow-power LSI's
A pseudo-CCM/DCM SIMO switching converter with freewheel switching
Physics- and process-based bipolar transistor modeling for integrated circuit design
An experimental 5-Gb/s 16*16 Si-bipolar crosspoint switch
Rail Clamp with Dynamic Time-Constant Adjustment
A 2.4 GHz 4 mW Integer-N Inductorless RF Synthesizer
A Miniaturized Wireless Neural Implant With Body-Coupled Power Delivery and Data Transmission
Compact sub-hertz OTA-C filter design with interface-trap charge pump
Digital 2-/3-Phase Switched-Capacitor Converter With Ripple Reduction and Efficiency Improvement
A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization
A sensitivity and linearity improvement of a 100-dB dynamic range CMOS image sensor using a lateral overflow integration capacitor
A 6.25-Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels
A 3.3-V 12-ns 16-Mb CMOS SRAM
A multigigahertz Josephson-semiconductor interface circuit using 77-K differential monolithic HEMT amplifier and 4.2-K JJ high-voltage driver for superconductor-semiconductor electronic hybrid systems
A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree
Distributed Parametric Resonator: A Passive CMOS Frequency Divider
A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference Decoupling Capacitor
A switched-capacitor filter silicon compiler
A power and area efficient CMOS clock/data recovery circuit for high-speed serial interfaces
A Current-Feedback Instrumentation Amplifier With 5 µV Offset for Bidirectional High-Side Current-Sensing
A 1.2-mW/Channel Pitch-Matched Transceiver ASIC Employing a Boxcar-Integration-Based RX Micro-Beamformer for High-Resolution 3-D Ultrasound Imaging
An 8T SRAM With On-Chip Dynamic Reliability Management and Two-Phase Write Operation in 28-nm FDSOI
A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory
A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS
A Polar-Modulation-Based Cryogenic Transmon Qubit State Controller in 28 nm Bulk CMOS for Superconducting Quantum Computing
A low-noise folded bit-line sensing architecture for multigigabit DRAM with ultrahigh-density 6F 2 cell [CMOS design]
A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters
A low-power direct digital synthesizer using a self-adjusting phase-interpolation technique
A CMOS analog multi-sinusoidal phase-locked-loop
High Speed and Low Energy Capacitively Driven On-Chip Wires
GaAs switched capacitor DC-to-DC converter
A GaAs HBT 16×16 10-Gb/s/channel crosspoint switch
A 25-Ms/s 8-bit CMOS A/D converter for embedded application
An RF-to-BB-Current-Reuse Wideband Receiver With Parallel N-Path Active/Passive Mixers and a Single-MOS Pole-Zero LPF
A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology
A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control
GaAs split phase dynamic logic
Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology
A 1.2 mW video-rate 2-D color subband decoder
Schottky merged BiCMOS structures
Accurate estimation of defect-related yield loss in reconfigurable VLSI circuits
A 4 × 4 Steerable 14-dBm EIRP Array on CMOS at 0.41 THz With a 2-D Distributed Oscillator Network
A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-μm digital CMOS process
A 475 mV, 4.9 GHz Enhanced Swing Differential Colpitts VCO With Phase Noise of -136 dBc/Hz at a 3 MHz Offset Frequency
A 15-bit 30-MS/s 145-mW three-step ADC for imaging applications
1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing
A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking
An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications
A 1 mm ×1 mm CGM System on Die Achieving 1.65-nA/mM In Vivo Resolution and 0-40-mM/L Detection Range With ΔΣ Backscatter Technique
A 2.4-GHz ZigBee Transmitter Using a Function-Reuse Class-F DCO-PA and an ADPLL Achieving 22.6% (14.5%) System Efficiency at 6-dBm (0-dBm) P out
Correction to "A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS" [Mar 11 660-668]
A high-speed halftoning processor for raster scanned images
A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver
A 20-b ± 40-mV Range Read-Out IC With 50-nV Offset and 0.04% Gain Error for Bridge Transducers
A fully integrated 2.4-GHz LC-VCO frequency synthesizer with 3-ps jitter in 0.18-μm standard digital CMOS copper technology
35-GHz static and 48-GHz dynamic frequency divider ICs using 0.2-μm AlGaAs/GaAs-HEMTs
A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling
Robust, Efficient Distributed Power Amplifier Achieving 96 Gbit/s With 10 dBm Average Output Power and 3.7% PAE in 22-nm FD-SOI
A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c