yusuke1997/dblp-id-title huggingface dataset:
A Temperature-to-Digital Converter Based on an Optimized Electrothermal Filter
A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor
A 32-word by 32-bit three-port bipolar register file implemented using a SiGe HBT BiCMOS technology
A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications
A 1.3 mW 48 MHz 4 Channel MIMO Baseband Receiver With 65 dB Harmonic Rejection and 48.5 dB Spatial Signal Separation
An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors
Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends
Addressing noise decoupling in mixed-signal IC's: power distribution design and cell customization
Improvement of Read Margin and Its Distribution by V TH Mismatch Self-Repair in 6T-SRAM With Asymmetric Pass Gate Transistor Formed by Post-Process Local Electron Injection
A unified single-phase clocking scheme for VLSI systems
High-density chain ferroelectric random access memory (chain FRAM)
A 1.0625 ~ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS
A Low-Flicker-Noise 30-GHz Class-F 23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path
A CDMA2000 zero-IF receiver with low-leakage integrated front-end
A 3.2-GHz 405 fs rms Jitter -237.2 dB FoM JIT Ring-Based Fractional-N Synthesizer
A Recursive Switched-Capacitor House-of-Cards Power Amplifier
A 0.45-THz 2-D Scalable Radiator Array With 28.2-dBm EIRP Using an Elliptical Teflon Lens
On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation
Pulling Mitigation in Wireless Transmitters
Integrated Quadrature Couplers and Their Application in Image-Reject Receivers
A GHz Spintronic-Based RF Oscillator
A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network
An MLSE Receiver for Electronic Dispersion Compensation of OC-192 Fiber Links
A Bidirectional USB Power Delivery Voltage-Regulating Cable
A 2-GHz Highly Linear Efficient Dual-Mode BiCMOS Power Amplifier Using a Reconfigurable Matching Network
High dynamic range InP HBT delta-sigma analog-to-digital converters
A Low-Noise Digital-to-Time Converter Exploiting Waveform of Integrated Crystal Oscillator
The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking
An InGaAs-InP HBT differential transimpedance amplifier with 47-GHz bandwidth
A Column Driver Architecture With Double Time-Division Multiplexing RDACs for TFT-LCD Applications
A 5-GS/s 7.2-ENOB Time-Interleaved VCO-Based ADC Achieving 30.5 fJ/cs
A Ka-Band InP HBT MMIC Power Amplifier With 19.8:1 IP3/P dc LFOM at 48 GHz
High Q inductors for wireless applications in a complementary silicon bipolar process
A replica technique for wordline and sense control in low-power SRAM's
Noise-Shaping Gain-Filtering Techniques for Integrated Receivers
A 2×56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS
A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture
A modular bit-serial architecture for large-constraint-length Viterbi decoding
A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic
W-band Scalable 2×2 Phased-Array Transmitter and Receiver Chipsets in SiGe BiCMOS for High Data-Rate Communication
Mobile-PBR: A 28-nm Energy-Efficient Rendering Processor for Photorealistic Augmented Reality With Inverse Rendering and Background Clustering
A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation
A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle
A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package
Design and Scaling of W-Band SiGe BiCMOS VCOs
A 39-GHz CMOS Bidirectional Doherty Phased- Array Beamformer Using Shared-LUT DPD With Inter-Element Mismatch Compensation Technique for 5G Base Station
A 10-GHz 8-b multiplexer/demultiplexer chip set for the SONET STS-192 system
A 7-bit 1.75-GS/s 6.9-fJ/conv.-step FoMw Loop-Unrolled Fully Asynchronous SAR ADC in 3-nm CMOS for a 224-Gb/s SerDes Receiver
A Differential Transmission Gate Design Flow for Minimum Energy Sub-10-pJ/Cycle ARM Cortex-M0 MCUs
Introduction to the Special Issue on the 2008 IEEE Custom Integrated Circuits Conference
A 760-nW, 180-nm CMOS Fully Analog Voice Activity Detection System for Domestic Environment
A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system
Diode-HBT-logic circuits monolithically integrable with ECl/CML circuits
A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput
An experimental 1.5-V 64-Mb DRAM
An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114
A 3.36-μm-Pitch SPAD Photon-Counting Image Sensor Using a Clustered Multi-Cycle Clocked Recharging Technique With an Intermediate Most-Significant-Bit Readout
A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels
SECOND: synthesis of elementary circuits on demand
A 0.6-V Zero-IF/Low-IF Receiver With Integrated Fractional-N Synthesizer for 2.4-GHz ISM-Band Applications
Design and Characterization of a 10-MHz GaN Gate Driver Using On-Chip Feed-Forward Gaussian Switching Regulation for EMI Reduction
An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs
A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS
Variable-taper CMOS buffers
A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET
A 200-MHz all-digital QAM modulator and demodulator in 1.2- mu m CMOS for digital radio applications
An 8×5 Gb/s Parallel Receiver With Collaborative Timing Recovery
A 30-b integrated logarithmic number system processor
2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing
A Bandwidth-Adaptive Preamplifier
High-frequency operation of quantum flux parametron (QFP) based shift registers and frequency prescalers
A multimode digital detector readout for solid-state medical imaging detectors
An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs
CMOS low-distortion high-frequency variable-gain amplifier
A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique
A CMOS 6-b, 400-MSample/s ADC with error correction
CMOS Silicon Physical Unclonable Functions Based on Intrinsic Process Variability
A Low Phase Noise and High FoM Distributed-Swing-Boosting Multi-Core Oscillator Using Harmonic-Impedance-Expanding Technique
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS
A CMOS transconductor with multidecade tuning using balanced current scaling in moderate inversion
On the Design of mm-Wave Self-Mixing-VCO Architecture for High Tuning-Range and Low Phase Noise
Current-mode CMOS multiple-valued logic circuits
Self-calibration techniques for a second-order multibit sigma-delta modulator
High power DPDT antenna switch MMIC for digital cellular systems
Introduction to the January Special Issue on the 2016 IEEE International Solid-State Circuits Conference
A 150 GHz Lens-Free Large FoV Regenerative 2 × 2 Transceiver Array With 31% DC-to-EIRP Efficiency and -70 dBm Sensitivity for a 70 cm Bidirectional Peer-to-Peer Link
A 130- μ W, 64-Channel Neural Spike-Sorting DSP Chip
Design and implementation of real-time 3-D image sensor with 640 × 480 pixel resolution
A Blocker-Tolerant RF Front End With Harmonic-Rejecting N-Path Filter
A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration
The Quadrature LC Oscillator: A Complete Portrait Based on Injection Locking
A 90 nm CMOS, 6µW Power-Proportional Acoustic Sensing Frontend for Voice Activity Detection
A 1.08-nW/kHz 13.2-ppm/°C Self-Biased Timer Using Temperature-Insensitive Resistive Current
A 56-Gb/s PAM-4 Transmitter/Receiver Chipset With Nonlinear FFE for VCSEL-Based Optical Links in 40-nm CMOS
1.23-pJ/bit 25-Gb/s Inductor-Less Optical Receiver With Low-Voltage Silicon Photodetector
An Asynchronous Analog Self-Powered CMOS Sensor-Data-Logger With a 13.56 MHz RF Programming Interface
A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider
PIN-preamp module and CDR-DMUX constituting a receiver for short-haul links up to 3.5 Gb/s
An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write
A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET
A 3.3-V single power supply 16-Mb nonvolatile virtual DRAM using a NAND flash memory technology
Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA
A monolithic surface micromachined accelerometer with digital output
A CMOS low-distortion fully differential power amplifier with double nested Miller compensation
A class of multiprocessors for real-time image and multidimensional signal processing
Analysis of pulse propagation on high-speed VLSI chips
Time resolution of NMOS sampling switches used on low-swing signals
A 1.8-pJ/b, 12.5-25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
A Skew-Free 10 GS/s 6 bit CMOS ADC With Compact Time-Domain Signal Folding and Inherent DEM
A106nW 10 b 80 kS/s SAR ADC With Duty-Cycled Reference Generation in 65 nm CMOS
A Super-Resolution Mixed-Signal Doherty Power Amplifier for Simultaneous Linearity and Efficiency Enhancement
A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS
2-GHz/2-mW and 12-GHz/30-mW dual-modulus prescalers in silicon bipolar technology
A low-power ASIC design for cell search in the W-CDMA system
A Portable CMOS-Based Spin Resonance System for High-Resolution Spectroscopy and Imaging
A voltage-controlled duty-cycle oscillator
A Low-Phase-Noise Wide-Tuning-Range Mode-Switching Oscillator Using Multi-Magnetic-Coupling and Active-Source-Degenerating Techniques
A Low-Power Radiation-Hardened Ka-Band CMOS Phased-Array Receiver for Small Satellite Constellation
A 158-mW 360-MHz BW 68-dB DR Continuous-Time 1-1-1 Filtering MASH ADC in 40-nm CMOS
A Wide-Input-Range Low-Profile Adaptive Delay Compensated Hysteretic LED Driver With Enhanced Current Accuracy
A Leakage-Current-Recycling Phase-Locked Loop in 65 nm CMOS Technology
A Fully Integrated UHF-Band CMOS Receiver With Multi-Resolution Spectrum Sensing (MRSS) Functionality for IEEE 802.22 Cognitive Radio Applications
A computational image sensor with adaptive pixel-based integration time
A Low-Power Speech Recognizer and Voice Activity Detector Using Deep Neural Networks
11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications
A new charge pump without degradation in threshold voltage due to body effect [memory applications]
A low-power backward equalizer for DFE read-channel applications
A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS
A 10-mW two-channel fully integrated system-on-chip for eddy-current position sensing [in biomedical devices]
An autonomous SRAM with on-chip sensors in an 80-nm double stacked cell technology
A 120 dB Dynamic Range 400 mW Class-D Speaker Driver With Fourth-Order PWM Modulator
A 94 GHz mm-Wave-to-Baseband Pulsed-Radar Transceiver with Applications in Imaging and Gesture Recognition
A Multi-Band RF Transmitter Employing a Transformer-Based N-Path Switched-Capacitor Modulator for CIM 3 Suppression
An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS
A 28-nm Software-Defined Accelerator Chip With Circuit-Pipeline Scaling and Intrinsic Physical Unclonable Function Enabling Secure Configuration
A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation
An experimental high-density DRAM cell with a built-in gain stage
Cell-based CMOS sensor and actuator arrays
Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications
A 1.25 ps Resolution 8b Cyclic TDC in 0.13 µm CMOS
A Quad-Band GSM/GPRS/EDGE SoC in 65 nm CMOS
A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology
Circuits to reduce distortion in the diode-bridge track-and-hold
A 2 × Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery
Split-Array, C-2C Switched-Capacitor Power Amplifiers
A 510-pW 32-kHz Crystal Oscillator With High Energy-to-Noise-Ratio Pulse Injection
Low-power SRAM design using half-swing pulse-mode techniques
An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration
A 1.4-m $\Omega$ -Sensitivity 94-dB Dynamic-Range Electrical Impedance Tomography SoC and 48-Channel Hub-SoC for 3-D Lung Ventilation Monitoring System
Delta-sigma modulation in fractional-N frequency synthesis
A 2.4 GHz ZigBee Receiver Exploiting an RF-to-BB-Current-Reuse Blixer + Hybrid Filter Topology in 65 nm CMOS
A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface
A SAW-Less Tunable RF Front End for FDD and IBFD Combining an Electrical-Balance Duplexer and a Switched-LC N-Path LNA
Measurement and Analysis of Inductive Coupling Noise in 90 nm Global Interconnects
A 1.5 V, 4.1 mW dual-channel audio delta-sigma D/A converter
A Two-Phase Switching Hybrid Supply Modulator for RF Power Amplifiers With 9% Efficiency Improvement
A Ka-Band Doherty-Like LMBA for High-Speed Wireless Communication in 28-nm CMOS
A 120-MHz-1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling
A 1-GS/s 6-Bit Two-Channel Two-Step ADC in 0.13-µm CMOS
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer
A 12-Bit 31.1- $\mu$ W 1-MS/s SAR ADC With On-Chip Input-Signal-Independent Calibration Achieving 100.4-dB SFDR Using 256-fF Sampling Capacitance
Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test
A Single-Chip Optical Phased Array in a Wafer-Scale Silicon Photonics/CMOS 3D-Integration Platform
A cm-Scale 2.4-GHz Wireless Energy Harvester With NanoWatt Boost Converter and Antenna-Rectifier Resonance for WiFi Powering of Sensor Nodes
A Process-Variation-Tolerant On-Chip CMOS Thermometer for Auto Temperature Compensated Self-Refresh of Low-Power Mobile DRAM
A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet
A 5.6 GHz to 11.5 GHz DCO for Digital Dual Loop CDRs
ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET
A 13.56-MHz Primary Driver With Fractional Capacitance Auto-Tuning Loop for Wireless-Powered Implantable Medical Devices
On-Chip Combined C-V/I-V Characterization System in 45-nm CMOS Technology
A SiGe BiCMOS burst-mode 155-Mb/s receiver for PON
A Variation-Tolerant Sub-200 mV 6-T Subthreshold SRAM
Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS
Deep-Learning-Based Inverse-Designed Millimeter-Wave Passives and Power Amplifiers
A Duty-Cycle Switching 30-Gb/s Burst-Mode CDR With 1.6-ns Locking Time in 28-nm CMOS
A 0.5-V R-MOSFET-C Filter Design Using Subthreshold R-MOSFET Resistors and OTAs With Cross-Forward Common-Mode Cancellation Technique
A Wide Tuning Range G m -C Filter for Multi-Mode CMOS Direct-Conversion Wireless Receivers
MMIC family for DBS down-converter with pulse-doped GaAs MESFETs
Linearized Dual-Band Power Amplifiers With Integrated Baluns in 65 nm CMOS for a 2 , ˟ , 2 802.11n MIMO WLAN SoC
22-29 GHz Ultra-Wideband CMOS Pulse Generator for Short-Range Radar Applications
An 8-Bit Flash Analog-to-Digital Converter in Standard CMOS Technology Functional From 4.2 K to 300 K
A 60 MBd, 480 Mb/s, 256 QAM decision-feedback equalizer in 1.2 mu m CMOS
Introduction to the Special Section on the 2015 Radio Frequency Integrated Circuits Symposium
A capacitance model for GaAs MESFETs
A 20 Gb/s 1: 4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 µm CMOS Technology
In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security
2-GHz RF front-end circuits in CMOS/SIMOX operating at an extremely low voltage of 0.5 V
Multivalued SRAM cell using resonant tunneling diodes
A Sub-5mW Monolithic CMOS-MEMS Thermal Flow Sensing SoC With ±6 m/s Linear Range
A multiresolution 100-GOPS 4-Gpixels/s programmable smart vision sensor for multisense imaging
Fast-Lock Hybrid PLL Combining Fractional-N and Integer-N Modes of Differing Bandwidths
An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme
An 84.7% Efficiency 100-MHz Package Bondwire-Based Fully Integrated Buck Converter With Precise DCM Operation and Enhanced Light-Load Efficiency
Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET
A Fractional-N Counter-Assisted DPLL With Parallel Sampling ILFD
PLA design for single-clock CMOS
Measurement and Analysis of PD-SOI Static Latches Based on Bistable-Gated-Bipolar Device
A Broadband CMOS RF Front-End for Universal Tuners Supporting Multi-Standard Terrestrial and Cable Broadcasts
A 40-Mpixel/s bit block transfer graphics processor
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling
A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction
Output Impedance Shaping for Frequency Compensation of MOS Audio Power Amplifiers
A Monolithic 5.7 A/mm 2 91% Peak Efficiency Scalable Multistage Modular Switched Capacitor Voltage Regulator for Base Die Vertical Power Delivery in 3D-ICs
A 184 mW Fully Integrated DVB-H Tuner With a Linearized Variable Gain LNA and Quadrature Mixers Using Cross-Coupled Transconductor
A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL
Noise in current-commutating CMOS mixers
A 0.25-μm CMOS quad-band GSM RF transceiver using an efficient LO frequency plan
An Ultralow Power System on Chip for Automatic Sleep Staging
A Low-Power Compact IEEE 802.15.6 Compatible Human Body Communication Transceiver With Digital Sigma-Delta IIR Mask Shaping
A Sub-0.5 Electron Read Noise VGA Image Sensor in a Standard CMOS Process
A 3.07 mW 30 MHz-BW 73.2 dB-SNDR Time- Interleaved Noise-Shaping SAR ADC With Self-Coupling Second-Order Error-Feedforward
A multiple-dimensional multiple-state SRAM cell using resonant tunneling diodes
A 224 Gb/s 3 pJ/bit 40 dB Insertion Loss Transceiver in 3-nm FinFET CMOS
Analysis and optimization of BiCMOS digital circuit structures
A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process
Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors
A Performance-Aware Low-Quiescent Headphone Amplifier in 65-nm CMOS
An AC-Coupled 1st-Order Δ-ΔΣ Readout IC for Area-Efficient Neural Signal Acquisition
A 1 V 5 mA Multimode IEEE 802.15.6/Bluetooth Low-Energy WBAN Transceiver for Biotelemetry Applications
Efficient Energy Harvesting With Electromagnetic Energy Transducers Using Active Low-Voltage Rectification and Maximum Power Point Tracking
A direct digital synthesizer with 100-MHz output capability
Energy-Efficient Reconfigurable SRAM: Reducing Read Power Through Data Statistics
The design of sigma-delta modulation analog-to-digital converters
A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer
A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V VDDmin
New full-voltage-swing BiCMOS buffers
Dual-Carrier Aggregation Receiver With Reconfigurable Front-End RF Signal Conditioning
A Low-Power Integrated x86-64 and Graphics Processor for Mobile Computing Devices
Design of a process-tolerant cell library for regular structures using symbolic layout and hierarchical compaction
A stereo audio sigma-delta A/D-converter
Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM
A Fully Integrated, Low-Noise, Cost-Effective Single-Crystal-Oscillator-Based Clock Management IC in 28-nm CMOS
Guest Editorial Introduction to the Special Section on the 2020 IEEE BCICTS Conference
10-Gb/s modulator drivers with local feedback networks
An EDGE/GSM Quad-Band CMOS Power Amplifier
5-GHz CMOS radio transceiver front-end chipset
High-performance 1-Gb-NAND flash memory with 0.12-μm technology
Memory at VLSI Circuits Symposium
A 33-ns 64-Mb DRAM
A DSP for DCT-based and wavelet-based video codecs for consumer applications
A fast single-chip implementation of 8192 complex point FFT
A low-power 128×1-bit GaAs FIFO for ATM packet switcher
A 3-nm FinFET 27.6-Mbit/mm 2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking
A 120-MHz BW, 122-dBFS SFDR CTΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme
An Auto-Calibrated Resistive Measurement System With Low Noise Instrumentation ASIC
Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm
A 0.8-2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass ΣΔ ADC in 0.13 µm CMOS
A Single-Inductor 0.35 µm CMOS Energy-Investing Piezoelectric Harvester
A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24-71-GHz Utilizing Harmonic-Selection Technique With 36-dB Inter-Band Blocker Tolerance for 5G NR
An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for Securing Internet-of-Things Applications
A 15.4-ENOB, Fourth-Order Truncation-Error-Shaping NS-SAR-Nested ΔΣ Modulator With Boosted Input Impedance and Range for Biosignal Acquisition
FLAG: a flexible layout generator for analog MOS transistors
A mixed-mode ESD protection circuit simulation-design methodology
A highly integrated dual-band multimode wireless LAN transceiver
A 27-MHz/54-MHz 11-mW MPEG-4 video decoder LSI for mobile applications
Novel principle for vector modulator-based phase shifters operating with only one control voltage
A CMOS floating-point vector-arithmetic unit
An EMI Resisting LIN Driver in 0.35-micron High-Voltage CMOS
Multilevel design and verification of hardware/software systems
SOUL: An Energy-Efficient Unsupervised Online Learning Seizure Detection Classifier
A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS
A broad-band tunable CMOS channel-select filter for a low-IF wireless receiver
A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment
A 15-GHz monolithic two-modulus prescaler
Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell
An improved high-performance logic gate using series diode and resistor loads for ECL/CML applications
A mm-Wave Power-Harvesting RFID Tag in 90 nm CMOS
Pole-Converging Intrastage Bandwidth Extension Technique for Wideband Amplifiers
Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability
A fault-tolerant array processor designed for testability and self-reconfiguration
A 4.9-7.1-GHz High-Efficiency Post-Matching GaN Front-End Module for Wi-Fi 7 Application
An 8-bit microcomputer with analog subsystems for implantable biomedical application
Design of CMOS circuits for stuck-open fault testability
A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback
New directions in semicustom arrays
A robust analog interface system for submicron CMOS video DSP
Integrated Receiver Including Both Receiver Channel and TDC for a Pulsed Time-of-Flight Laser Rangefinder With cm-Level Accuracy
Realization of transmission-gate conditional-sum (TGCS) adders with low latency time
Mitigation of Oscillator Pulling in SoCs