yusuke1997/dblp-id-title huggingface dataset:
A 1-2-MHz 150-400-V GaN-Based Isolated DC-DC Bus Converter With Monolithic Slope-Sensing ZVS Detection
A 28-GHz CMOS Direct Conversion Transceiver With Packaged 2 × 4 Antenna Array for 5G Cellular System
An integrated controller for tunnel sensors
An Optically Addressed Nanowire-Based Retinal Prosthesis With Wireless Stimulation Waveform Control and Charge Telemetering
A Watt-Level Quadrature Class-G Switched-Capacitor Power Amplifier With Linearization Techniques
An active resistor network for Gaussian filtering of images
Identification of DRAM sense-amplifier imbalance using hot-carrier evaluation
A 115-135-GHz 8PSK Receiver Using Multi-Phase RF-Correlation-Based Direct-Demodulation Method
A 20 Gb/s CMOS Optical Receiver With Limited-Bandwidth Front End and Local Feedback IIR-DFE
Jitter analysis of high-speed sampling systems
Introduction to the Special Issue on the 46th European Solid-State Circuits Conference (ESSCIRC)
A Compact 20-24-GHz Sub-Sampling PLL With Charge-Domain Bandwidth Control Scheme
Cell-plate line connecting complementary bit-line (C 3 ) architecture for battery-operated DRAMs
NeuGPU: An Energy-Efficient Neural Graphics Processing Unit for Instant Modeling and Real-Time Rendering on Mobile Devices
A Current-Mode, Dual Slope, Integrated Capacitance-to-Pulse Duration Converter
A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture
A 52 mW Full HD 160-Degree Object Viewpoint Recognition SoC With Visual Vocabulary Processor for Wearable Vision Applications
Transient analysis of the CMOS-like a-Si:H TFT inverter circuit
An AC-Coupled Instrumentation Amplifier Achieving 110-dB CMRR at 50 Hz With Chopped Pseudoresistors and Successive-Approximation-Based Capacitor Trimming
Memory system reliability improvement through associative cache redundancy
Comments on 'Using cache mechanisms to exploit nonrefreshing DRAM's for on-chip memories'
Message from the Incoming Editor-in-Chief
A 0.83-2.5-GHz continuously tunable quadrature VCO
An experimental study on substrate coupling in bipolar/BiCMOS technologies
A Discrete-Time Audio ΔΣ Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode
A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries
A 10-nW 12-bit accurate analog storage cell with 10-aA leakage
A fully integrated high-performance FM stereo decoder
A Multi(bio)sensor Acquisition System With Integrated Processor, Power Management, 8×8 LED Drivers, and Simultaneously Synchronized ECG, BIO-Z, GSR, and Two PPG Readouts
60-GHz SOI CMOS traveling-wave amplifier with NF below 3.8 dB from 0.1 to 40 GHz
A magnetic power and communication interface for a CMOS integrated circuit
A 9-ns, 1.4-gigabyte/s, 17-ported CMOS register file
A high-speed CMOS circuit for 1.2-Gb/s 16*16 ATM switching
A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM's
Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator
A programmable artificial retina
A Four-Channel, ±36 V, 780 kHz Piezo Driver Chip for Structural Health Monitoring
300-GHz Band 160-Gb/s InP-HEMT Differential Front End With High LO Leakage Rejection
A 1-V 1.8-MHz CMOS switched-opamp SC filter with rail-to-rail output swing
A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS
A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy
A 71-to-86-GHz 16-Element by 16-Beam Multi-User Beamforming Integrated Receiver Sub-Array for Massive MIMO
A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS
A fully integrated 0.5-5.5 GHz CMOS distributed amplifier
Multilevel differential encoding with precentering for high-speed parallel link transceiver
A Current-Mode Display Driver IC Using Sample-and-Hold Scheme for QVGA Full-Color AMOLED Displays
A 6.78-MHz Wireless Power Transfer System With Inherent Wireless Phase Shift Control Without Feedback Data Sensing Coil
A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS
A CMOS line driver for ADSL central office applications
Analog neural programmable optimizers in CMOS VLSI technologies
DF-LNPU: A Pipelined Direct Feedback Alignment-Based Deep Neural Network Learning Processor for Fast Online Learning
A dual-page programming scheme for high-speed multigigabit-scale NAND flash memories
A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs
A 0.8-V 82.9- $\mu$ W In-Ear BCI Controller IC With 8.8 PEF EEG Instrumentation Amplifier and Wireless BAN Transceiver
A low-power microprocessor based on resonant energy
A Single-Input RF Energy-Harvesting Interface With Compensated-CEPE Control and 3-D Hill-Climbing MPPT Achieving -28.5-dBm Sensitivity
A 10-bit 250-MS/s binary-weighted current-steering DAC
1.2-V CMOS op-amp with a dynamically biased output stage
A 550- $\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS
A 1.2 V Reactive-Feedback 3.1-10.6 GHz Low-Noise Amplifier in 0.13 µm CMOS
Millimeter-Wave Integrated Circuits in 65-nm CMOS
An 84-dB-SNDR Low-OSR Fourth-Order Noise-Shaping SAR With an FIA-Assisted EF-CRFF Structure and Noise-Mitigated Push-Pull Buffer-in-Loop Technique
DPTL 4-b carry lookahead adder
A 1.9-GHz-band GaAs direct-quadrature modulator IC with a phase shifter
The CMOS carry-forward adders
Linear Current-Mode Active Pixel Sensor
A 10 Mb frame buffer memory with Z-compare and A-blend units
Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS
A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design
Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification
A Feedforward Noise Reduction Technique in Capacitive MEMS Accelerometer Analog Front-End for Ultra-Low-Power IoT Applications
A direct-conversion receiver for 900 MHz (ISM band) spread-spectrum digital cordless telephone
A 4900- $\mu$ m 2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition
A 16-Mb CMOS SRAM with a 2.3- mu m 2 single-bit-line memory cell
Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference
A ±1.5-V, 4-MHz CMOS continuous-time filter with a single-integrator based tuning
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator
A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure
Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions
A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power
A Light-Tolerant Wireless Neural Recording IC for Motor Prediction With Near-Infrared-Based Power and Data Telemetry
Design and Analysis of Varactor-Less Interpolative-Phase-Tuning Millimeter-Wave LC Oscillators with Multiphase Outputs
A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS
A 140 dB-CMRR Current-Feedback Instrumentation Amplifier Employing Ping-Pong Auto-Zeroing and Chopping
A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors
An Efficiency-Enhanced Hybrid Supply Modulator With Single-Capacitor Current-Integration Control
NCMOS: a high performance CMOS logic
Built-in current testing
A 10-b 70-MS/s CMOS D/A converter
1-V rail-to-rail operational amplifiers in standard CMOS technology
Twisted bit-line architectures for multi-megabit DRAMs
A static memory cell based on the negative resistance of the gate terminal of p-n-p-n devices
An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture
A 900-MHz fully integrated SOI power amplifier for single-chip wireless transceiver applications
A 15-b 1-Msample/s digitally self-calibrated pipeline ADC
An Energy Efficient Full-Frame Feature Extraction Accelerator With Shift-Latch FIFO in 28 nm CMOS
Correction to "A 0.016 mm 2 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load With >0.95-MHz GBW"
Development of a GaAs monolithic surface acoustic wave integrated circuit
CCD focal-plane image reorganization processors for lossless image compression
A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links
MMIC LNAs for Radioastronomy Applications Using Advanced Industrial 70 nm Metamorphic Technology
A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS
A Symmetric Modified Multilevel Ladder PMIC for Battery-Connected Applications
Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps
A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFET
Wide-band CMOS low-noise amplifier exploiting thermal noise canceling
A Wideband Power Detection System Optimized for the UWB Spectrum
A 10-b 50-MHz CMOS D/A converter with 75- Omega buffer
Very low-voltage digital-audio ΔΣ modulator with 88-dB dynamic range using local switch bootstrapping
A 110-MHz 84-dB CMOS programmable gain amplifier with integrated RSSI function
An experimental single-chip data flow CPU
A Low-Voltage 1 Mb FRAM in 0.13 µm CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin
An Ultralow-Power Triaxial MEMS Accelerometer With High-Voltage Biasing and Electrostatic Mismatch Compensation
Dynamic threshold pass-transistor logic for improved delay at lower power supply voltages
A 16×622 Mb/s ATM switch: PRELUDE switch architecture integrated into a 6-million transistor monochip
A 1.57-GHz RF front-end for triple conversion GPS receiver
A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier
A low-voltage 5.1-5.8-GHz image-reject downconverter RF IC
High-Scalability CMOS Quantum Magnetometer With Spin-State Excitation and Detection of Diamond Color Centers
A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver
A Fully Integrated Delta Sigma ADC in Organic Thin-Film Transistor Technology on Flexible Plastic Foil
A 54-GHz distributed amplifier with 6-V PP output for a 40-Gb/s LiNbO 3 modulator driver
A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end
A 0.5-V Sub-10-μW 15.28-mΩ/√Hz Bio-Impedance Sensor IC With Sub-1° Phase Error
A 60 kb/s-10 Mb/s Adaptive Frequency Hopping Transceiver for Interference-Resilient Body Channel Communication
A Fully Integrated Multi-CPU, Processor Graphics, and Memory Controller 32-nm Processor
A 2.8 μs Response Time 95.1% Efficiency Hybrid Boost Converter With RHP Zero Elimination for Fast-Transient Applications
Automatic V T extractors based on an n*n 2 MOS transistor array and their application
CMOS readout electronics for operation at cryogenic temperatures
Fully Synthesizable Unified True Random Number Generator and Cryptographic Core
SODS: a new CMOS differential-type structure
A 0.5-V 12-bit SAR ADC Using Adaptive Time-Domain Comparator With Noise Optimization
1.2-V Low-Power Multi-Mode DAC+Filter Blocks for Reconfigurable (WLAN/UMTS, WLAN/Bluetooth) Transmitters
Energy-Efficient Full-Swing Logic Circuits With Unipolar TFTs on Flexible Substrates
A 25-31-GHz Compact True Power Detector With >33-dB Dynamic Range and Intrinsic Phase Offset Compensation in 40-nm Bulk CMOS
170 GHz SiGe-BiCMOS Loss-Compensated Distributed Amplifier
An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS
Threshold voltage mismatch and intra-die leakage current in digital CMOS circuits
Industrial application of heterostructure device simulation
An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques
Piezoelectric micro-power generation interface circuits
Predicted propagation delay of Si/SiGe heterojunction bipolar ECL circuits
Message from the Outgoing Editor-in-Chief
Guest Editorial Introduction to the Special Issue on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)
CMOS technology-year 2010 and beyond
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface
Pass-transistor asynchronous sequential circuits
A CW 4-W Ka-band power amplifier utilizing MMIC multichip technology
A CMOS chip for individual cell manipulation and detection
A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function
Catena: A Near-Threshold, Sub-0.4-mW, 16-Core Programmable Spatial Array Accelerator for the Ultralow-Power Mobile and Embedded Internet of Things
Image-motion detection using analog VLSI
A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller
Design considerations for very-high-speed Si-bipolar IC's operating up to 50 Gb/s
12.8-ps 1.0-mW charge-buffered active pull-down NTL circuit
A CMOS RISC CPU designed for sustained high performance on large applications
A distributed globally replaceable redundancy scheme for sub-half-micron ULSI memories and beyond
Yield and matching implications for static RAM memory array sense-amplifier design
A 1.1 GHz Fifth Order Active-LC Butterworth Type Equalizing Filter
A 4-μa quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications
Stacked inductors and transformers in CMOS technology
A 2.7-V, 200-kHz, 49-dBm, stopband-IIP3, low-noise, fully balanced gm-C filter IC
350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS
A 44-mm 2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller
Accurate on-chip interconnect evaluation: a time-domain technique
A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme
A 103 fJ/b/dB, 10-26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement
Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI
A highly flexible sea-of-gates structure for digital and analog applications
An improved SPICE model for high-frequency noise of BJTs and HBTs
Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier
A 3.3-V, 500-Mb/s/ch parallel optical receiver in 1.2-μm GaAs technology
A 2.4-GHz RF Fractional-N Synthesizer With BW = 0.25f REF
A 4×45 Gb/s Two-Tap FFE VCSEL Driver in 14-nm FinFET CMOS Suitable for Burst Mode Operation
A power-efficient audio amplifier combining switching and linear techniques
A Hybrid Single-Inductor Bipolar-Output Converter With a Concise PWM Control for AMOLED Displays
A 57.5-90.1-GHz Magnetically Tuned Multimode CMOS VCO
A Low-Jitter Fractional- N Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC
Substrate coupling in a high-gain 30-Gb/s SiGe amplifier-modeling, suppression, and measurement
Built-in testable error detection and correction
A 2 MHz 12-100 V 90% Efficiency Self-Balancing ZVS Reconfigurable Three-Level DC-DC Regulator With Constant-Frequency Adaptive-On-Time V 2 Control and Nanosecond-Scale ZVS Turn-On Delay
A Charge-Multiplication CMOS Image Sensor Suitable for Low-Light-Level Imaging
A 14-port 3.8-ns 116-word 64-b read-renaming register file
A 372 μW 10 kHz-BW 109.2 dB-SNDR Nested Delta-Sigma Modulator Using Hysteresis-Comparison MSB-Pass Quantization
A 12 Gb/s 0.9 mW/Gb/s Wide-Bandwidth Injection-Type CDR in 28 nm CMOS With Reference-Free Frequency Capture
Equalization of Third-Order Intermodulation Products in Wideband Direct Conversion Receivers
A 4-Element Digital Modulated Polar Phased-Array Transmitter With Phase Modulation Phase-Shifting
A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters
A 13.9-nA ECG Amplifier Achieving 0.86/0.99 NEF/PEF Using AC-Coupled OTA-Stacking
A low-power, area-efficient digital filter for decimation and interpolation
High-bit-rate low-power decision circuit using InP-InGaAs HBT technology
1.5 mu m CMOS gate arrays with analog/digital macros designed using common base arrays
0.293-mm 2 Fast Transient Response Hysteretic Quasi-V 2 DC-DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35-µm CMOS
A new low-power GaAs two-single-port memory cell
Power Amplifier Protection by Adaptive Output Power Control
A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology
E-Band Frequency Sextupler With >35 dB Harmonics Rejection Over 20 GHz Bandwidth in 55 nm BiCMOS
Design Optimization for Integrated Neural Recording Systems
An All-Digital Edge Racing True Random Number Generator Robust Against PVT Variations
Multiloop High-Power-Supply-Rejection Quadrature Ring Oscillator
A 320 mW 342 GOPS Real-Time Dynamic Object Recognition Processor for HD 720p Video Streams
A V O -Hopping Reconfigurable RGB LED Driver With Automatic Δ V O Detection and Predictive Peak Current Control
A 384-Site Chip Platform for Biochemical Applications With Individual Site Precision Temperature Control
A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link
300-GHz-Band 120-Gb/s Wireless Front-End Based on InP-HEMT PAs and Mixers
Silicon bipolar chipset for SONET/SDH 10 Gb/s fiber-optic communication links
A 2T1C Embedded DRAM Macro With No Boosted Supplies Featuring a 7T SRAM Based Repair and a Cell Storage Monitor
Erratum to "A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System-on-Chip"
Multilevel optimization in the design of a high-performance GaAs microcomputer
A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors
A monolithic GaAs receiver for optical interconnect systems
Analysis of on-chip spiral inductors using the distributed capacitance model
A 90-MHz 16-Mb system integrated memory with direct interface to CPU
A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage
A 110 MHz 350 mW 0.6 μm CMOS 16-state generalized-target Viterbi detector for disk drive read channels
CMOS DNA Sensor Array With Integrated A/D Conversion Based on Label-Free Capacitance Measurement
A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency
Subtractive Photonics in Bulk CMOS
High-speed low-power cross-coupled active-pull-down ECL circuit
A 6.3 µW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 µV Offset
A PLL clock generator with 5 to 110 MHz of lock range for microprocessors
A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications
A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications
Design methodology of embedded DRAM with virtual-socket architecture
A wide-band linear amplitude modulator for polar transmitters based on the concept of interleaving delta modulation
A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS
A 250-Mbit/s CMOS crosspoint switch
An optimum CMOS switched-capacitor antialiasing decimating filter
Single Transformer-Based Compact Doherty Power Amplifiers for 5G RF Phased-Array ICs
A balanced 0.9- mu m CMOS transconductance-C filter tunable over the VHF range
A 10-bit wide-band CMOS direct digital RF amplitude modulator
A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips
A CMOS Fingerprint System-on-a-Chip With Adaptable Pixel Networks and Column-Parallel Processors for Image Enhancement and Recognition
Yield optimization in large RAM's with hierarchical redundancy
A tunable switched-capacitor programmable N-path tone receiver and generator
A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS
Design of a Dual W- and D-Band PLL
A 2×2 analog memory implemented with a special layout injector
A time-to-voltage converter and analog memory for colliding beam detectors
Active GaAs MMIC band-pass filters with automatic frequency tuning and insertion loss control
A SiGe BiCMOS Transmitter/Receiver Chipset With On-Chip SIW Antennas for Terahertz Applications
A 32-bank 256-Mb DRAM with cache and TAG
A 28-nm Energy-Efficient Sparse Neural Network Processor for Point Cloud Applications Using Block-Wise Online Neighbor Searching
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control
High-performance direct digital frequency synthesizers in 0.25 μm CMOS using dual-slope approximation
A Sub-cm 3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications
A 10 Gb/s, 6 V p-p , Digitally Controlled, Differential Distributed Amplifier MZM Driver
A sub-1 mA 1.5-GHz silicon bipolar dual modulus prescaler
A Closed-Loop ΣΔ Interface for a High-Q Micromechanical Capacitive Accelerometer With 200 ng/√Hz Input Noise Density
Progress and Challenges Towards Terahertz CMOS Integrated Circuits
A 25-Gb/s Avalanche Photodetector-Based Burst-Mode Optical Receiver With 2.24-ns Reconfiguration Time in 28-nm CMOS
Guest Editorial Introduction to the Special Section on the 2023 RFIC Symposium
A 10-MHz Current-Mode AOT Boost Converter With Dual-Ramp Modulation Scheme and Translinear Loop-Based Current Sensor for WiFi IoT Applications
A High-Resolution Pipelined-SAR ADC Using Cyclically Charged Floating Inverter Amplifier
A 12 MHz data cycle 4 Mb DRAM with pipeline operation
A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes
A 20-GHz PLL With 20.9-fs Random Jitter
High-Efficiency Ultrasound Energy Harvesting Interface With Auto-Calibrated Timing Control From -25 °C to 85 °C
A Si bipolar 1.4-GHz time space switch LSI for B-ISDN
Voltage Mode Doherty Power Amplifier
A 400-GHz Efficient Radiator and OOK Transceiver for Multi-Gb/s Wireless Communication in Silicon
A 113-dB DSD audio ADC using a density-modulated dithering scheme
High-frequency nonlinearity analysis of common-emitter and differential-pair transconductance stages
DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm
An Ultra-Low Power Fully Integrated Energy Harvester Based on Self-Oscillating Switched-Capacitor Voltage Doubler
Design of a low-power 10 Gb/s Si bipolar 1: 16-demultiplexer IC
A 1-V high-speed MTCMOS circuit scheme for power-down application circuits
A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector
Carrizo: A High Performance, Energy Efficient 28 nm APU
Efficient generation of pre-silicon MOS model parameters for early circuit design
High-dynamic-range VGA with temperature compensation and linear-in-dB gain control
Integrated Pop-Click Noise Suppression, EMI Reduction, and Short-Circuit Detection for Class-D Audio Amplifiers
A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs
A monolithic quad line driver for industrial applications
Power rail logic: a low power logic style for digital GaAs circuits
A four-channel CMOS codec filter circuit "SICOFI-4"
A fully integrated SiGe receiver IC for 10-Gb/s data rate
An Area-Efficient 10-Bit Source-Driver IC With LSB-Stacked LV-to-HV-Amplify DAC for Mobile OLED Displays
A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier
A 1-nA 4.5-nW 289-ppm/°C Current Reference Using Automatic Calibration
Design of a Compact Low-Power Sub-2.4-GHz Transceiver for Medical Band Applications