yusuke1997/dblp-id-title huggingface dataset:
A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator
A Resonant Switched-Capacitor IC and Embedded System for Sub-Module Photovoltaic Power Management
A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver
A 200 MHz 13 mm 2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme
An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors
Design of a bipolar 10-MHz programmable continuous-time 0.05 degrees equiripple linear phase filter
A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC
A Low-Power Low-Cost Fully-Integrated 60-GHz Transceiver System With OOK Modulation and On-Board Antenna Assembly
A SAW-Less 2.4-GHz Receiver Front-End With 2.4-mA Battery Current for SoC Coexistence
Digital-compatible high-performance operational amplifier with rail-to-rail input and output ranges
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die
A new architecture for the NVRAM-an EEPROM backed-up dynamic RAM
A Wide-Input-Range Efficiency-Enhanced Synchronous Integrated LED Driver With Adaptive Resonant Timing Control
A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802.11b/Bluetooth receiver
An Improved Active Decoupling Capacitor for "Hot-Spot" Supply Noise Reduction in ASIC Designs
A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS
A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications
A 14-b linear capacitor self-trimming pipelined ADC
A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers
An LTPS-TFT-Based Large-Area PPG Readout Circuits With Improved Linearity and Robustness for Flexible Healthcare Ring
A 1.2-A Buck-Boost LED Driver With On-Chip Error Averaged SenseFET-Based Current Sensing Technique
High-speed sensing scheme for CMOS DRAMs
1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD
A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN
GaAs trickle transistor dynamic logic
OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers
A Power-Efficient Clock and Data Recovery Circuit in 0.18 µm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication
An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback
ED-MPIM: An Energy-Efficient Event-Driven Smart Vision SoC With High-Linearity and Reconfigurable MRAM PIM
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise
64-Channel UWB Wireless Neural Vector Analyzer SOC With a Closed-Loop Phase Synchrony-Triggered Neurostimulator
A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider
A 120-dB Dynamic Range CMOS Image Sensor With Programmable Power Responsivity
Periodically Time-Varying Noise Cancellation for Filtering-by-Aliasing Receiver Front Ends
A full bit prefetch DRAM sensing circuit
A 90 nm CMOS V-Band Low-Noise Active Balun With Broadband Phase-Correction Technique
A robust CMOS compander
A Complementary Switched MOSFET Architecture for the 1/f Noise Reduction in Linear Analog CMOS ICs
A straightforward parallel-in, serial-out filter with a junction charge-coupled device and an integrated clock driver
A Reconfigurable Spectrum-Compressing Receiver for Non-Contiguous Carrier Aggregation in CMOS SOI
A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation
A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry
Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains
A 28-nm 75-fs rms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction
A fully integrated 0.13-μm CMOS mixed-signal SoC for DVD player applications
A Multireference PLL: Theory and Implementation
A Bio-Inspired Active Radio-Frequency Silicon Cochlea
A 4-GHz clock system for a high-performance system-on-a-chip design
A 4.3-GHz VCO with 2-GHz tuning range and low phase noise
A supply-noise-insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter
Built-in current sensor for ΔI DDQ testing
Simultaneously Broadband and Back-Off Efficient mm-Wave PAs: A Multi-Port Network Synthesis Approach
A Robust High Speed Serial PHY Architecture With Feed-Forward Correction Clock and Data Recovery
A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering
Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era
A 0.35-μm CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code
Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs
A 3-V 4-GHz nMOS voltage-controlled oscillator with integrated resonator
A low-noise low-offset capacitive sensing amplifier for a 50-μg√Hz monolithic CMOS MEMS accelerometer
A VSWR-protected silicon bipolar RF power amplifier with soft-slope power control
A 45-ns 64-Mb DRAM with a merged match-line test architecture
Design and Characterization of a 28-nm Bulk-CMOS Cryogenic Quantum Controller Dissipating Less Than 2 mW at 3 K
Four-Channel Differential Lock-in Amplifiers With Autobalancing Network for Stimulated Raman Spectroscopy
A Differential Optical Receiver With Monolithic Split-Microring Photodetector
A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS
A ±50-mV Linear-Input-Range VCO-Based Neural-Recording Front-End With Digital Nonlinearity Correction
A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications
A 0.46-mm 2 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS
A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core
A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers
A 0.7 V Single-Supply SRAM With 0.495 µm 2 Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme
A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy
A fault-tolerant associative memory with high-speed operation
Low-noise tape preamplifier with new self-biasing architecture
A 1.3 nJ/b IEEE 802.11ah Fully-Digital Polar Transmitter for IoT Applications
A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s
A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique
A 3.3-V, 10-b, 25-MSample/s two-step ADC in 0.35-μm CMOS
Electrothermal simulation and design of integrated circuits
A fast multispeed comma-free Reed-Solomon decoder for W-CDMA applications using foldable systolic array architecture
CMOS RF Biosensor Utilizing Nuclear Magnetic Resonance
CMOS Microflow Cytometer for Magnetic Label Detection and Classification
A 0.9 V 96 µW Fully Operational Digital Hearing Aid Chip
A Low-Power Bidirectional Link With a Direct Data-Sequencing Blind Oversampling CDR
A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application
A 1.9-GHz silicon receiver with monolithic image filtering
High-Density Redox Amplified Coulostatic Discharge-Based Biosensor Array
A 512-Pixel, 51-kHz-Frame-Rate, Dual-Shank, Lens-Less, Filter-Less Single-Photon Avalanche Diode CMOS Neural Imaging Probe
Introduction to the Special Issue on the 33rd European Solid-State Circuits Conference (ESSCIRC 2007)
RF Filter Synthesis Based on Passively Coupled N-Path Resonators
A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-μm CMOS
Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories
A W-Band TX/RX Chipset With 2.4-GHz LO Synchronization Enabling Full Scalability for FMCW Radar
Breaking the Performance Tradeoffs in N-Path Mixer-First Receivers Using a Second-Order Baseband Noise-Canceling TIA
A 10-bit 20-MHz two-step parallel A/D converter with internal S/H
Design and application of pipelined dynamic CMOS ternary logic and simple ternary differential logic
A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme
Virtual damping and Einstein relation in oscillators
A sub-130-nm conditional keeper technique
A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection
A 5-V-only operation 0.6- mu m flash EEPROM with row decoder scheme in triple-well structure
A 1.95 GHz Sub-1 dB NF, +40 dBm OIP3 WCDMA LNA Module
A 40 V 10 W 93%-Efficiency Current-Accuracy-Enhanced Dimmable LED Driver With Adaptive Timing Difference Compensation for Solid-State Lighting Applications
An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator
A High Data-Rate Energy-Efficient Triple-Channel UWB-Based Cognitive Radio
A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode
A GaAs up converter integrated circuit for a double conversion cable TV "set-top" tuner
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization
A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS
A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology
Low-Power High-Linearity Mixer-First Receiver Using Implicit Capacitive Stacking With 3× Voltage Gain
A 2.5-20 kS/s In-Pixel Direct Digitization ECoG Front End With Submillisecond Stimulation Artifact Recovery
A Bidirectional Neural Interface Circuit With Active Stimulation Artifact Cancellation and Cross-Channel Common-Mode Noise Suppression
A 300-MS/s 14-bit digital-to-analog converter in logic CMOS
A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS
Three-dimensional MMIC technology for low-cost millimeter-wave MMICs
A 336-neuron, 28 K-synapse, self-learning neural network chip with branch-neuron-unit architecture
A production ready, 6-18-GHz, 5-b phase shifter with integrated CMOS compatible digital interface circuitry
A 1.2-V 8.3-nJ CMOS Humidity Sensor for RFID Applications
A dynamically allocated CMOS dual-LIFO register stack
A 16-GHz ultra-high-speed Si-SiGe HBT comparator
SiGe driver circuit with high output amplitude operating up to 23 Gb/s
A 1.8-GHz instruction window buffer for an out-of-order microprocessor core
Low-power bandgap references featuring DTMOSTs
An 800-MOPS, 110-mW, 1.5-V, parallel DSP for mobile multimedia processing
Low Phase Noise Wide Tuning Range N-Push Cyclic-Coupled Ring Oscillators
A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS
A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers
CMOS continuous-time current-mode filters for high-frequency applications
A novel CMOS magnetic field sensor array
A 2.37-Gb/s 284.8 mW Rate-Compatible (491, 3, 6) LDPC-CC Decoder
A CMOS low-power multiple 2.5-3.125-Gb/s serial link macrocellfor high IO bandwidth network ICs
Feedforward compensation techniques for high-frequency CMOS amplifiers
A Multilevel Read and Verifying Scheme for Bi-NAND Flash Memories
A 1 V 103 dB 3rd-Order Audio Continuous-Time ΔΣ ADC With Enhanced Noise Shaping in 65 nm CMOS
A 14 ns 256 K*1 CMOS SRAM with multiple test modes
0.5-V Low- V T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays
Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits
A 2D CMOS microfluxgate sensor system for digital detection of weak magnetic fields
Fast Power Transient Management for OC-192 WDM Add/Drop Networks
A BW-Extended Fourth-Order Gain-Boosted N-Path Filter Employing a Switched gₘ-C Network
Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH
Exploiting Approximate Feature Extraction via Genetic Programming for Hardware Acceleration in a Heterogeneous Microprocessor
A 14-nm 0.14-ps rms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration
The effect of logic block architecture on FPGA performance
A Six-Phase Harmonic-Rejection Digital Transmitter
A configurable convolution chip with programmable coefficients
A Fully Integrated IEEE 802.15.4/4z-Compliant UWB System-on-Chip RF Transceiver Supporting Precision Positioning in a CMOS 28-nm Process
A 2.7-V GSM RF transceiver IC
A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance
Dual-Photodiode Differential Receivers Achieving Double Photodetection Area for Gigabit-Per-Second Optical Wireless Communication
Improved architectures for the add-compare-select operation in long constraint length Viterbi decoding
A 16-kB 65-nm GC-eDRAM Macro With Internal Bias Voltage Generation Providing Over 100-μs Retention Time
An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode
An Embedded 65 nm CMOS Remote Temperature Sensor With Digital Beta Correction and Series Resistance Cancellation Achieving an Inaccuracy of 0.4 ° C (3σ) From - 40 ° C to 130 ° C
A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS
Design issues in CMOS differential LC oscillators
A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy
Micropower low-voltage analog filter in a digital CMOS process
Block-decoded sense-amplifier driver for high-speed sensing in DRAM's
LOG-CIM: An Energy-Efficient Logarithmic Quantization Computing-In-Memory Processor With Exponential Parallel Data Mapping and Zero-Aware 6T Dual-WL Cell
Low-Power BiCMOS Optical Receiver With Voltage-Controlled Transimpedance
A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines
Outphasing Class-E Power Amplifiers: From Theory to Back-Off Efficiency Improvement
Energy consumption in multilective and boundary VLSI computations
A Fully Row/Column-Parallel MRAM in-Memory Computing Macro With Memory-Resistance Boosting and Weighted Multi-Column ADC Readout
An 8-bit 20.7 TOPS/W Multilevel Cell ReRAM Macro With ADC-Assisted Bit-Serial Processing
FlexSpin: A CMOS Ising Machine With 256 Flexible Spin Processing Elements With 8-b Coefficients for Solving Combinatorial Optimization Problems
A micropower-compatible time-multiplexed SC speech spectrum analyzer design
An analog front end for full-duplex digital transceivers working on twisted pairs
A new transponder architecture with on-chip ADC for long-range telemetry applications
A 200-MHz CMOS phase-locked loop with dual phase detectors
A Digital Envelope Modulator for a WLAN OFDM Polar Transmitter in 90 nm CMOS
A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS
A 140-mV Variation-Tolerant Deep Sub-Threshold SRAM in 65-nm CMOS
Physical Layer Security Through Directional Modulation With Spatio-Temporal Millimeter-Wave Transmitter Arrays
A comparison of systolic architectures for matrix multiplication
Design Considerations for a Low-Power Fully Integrated MMIC Parametric Upconverter in SiGe BiCMOS
A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band
A Dual-Antenna Phased-Array UWB Transceiver in 0.18-$\mu{\hbox {m}}$ CMOS
Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20-W/Ch Transmitter, and a 128 × 128 SPAD Receiver With SNR-Based Pixel Binning and Resolution Upscaling
A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0.35- μ m SiGe BiCMOS
A CMOS field-programmable analog array
3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias
Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 μ m HV-CMOS Technology
A 1-µW 10-bit 200-kS/s SAR ADC With a Bypass Window for Biomedical Applications
A SAR ADC With a MOSCAP-DAC
A 5-GHz CMOS wireless LAN receiver front end
A high-speed direct frequency synthesizer
Fully analogue LMS adaptive notch filter in BICMOS technology
Fully Integrated Frequency-Tuning Switched-Capacitor Rectifier for Piezoelectric Energy Harvesting
A mm-Wave Signal Generation and Background Phase Alignment Technique for Scalable Arrays
Automating the design of asynchronous sequential logic circuits
Low-Power Race-Free Programmable Logic Arrays
Accurate Array-Based Measurement for Subthreshold-Current of MOS Transistors
Reverse-voltage protection methods for CMOS circuits
Intermodulation Distortion in CMOS Attenuators and Switches
Notice of Violation of IEEE Publication Principles: A 3.3 V 12.5 Gb/s 0.2 µm SiGe BiCMOS Laser Diode Driver Using Bias Current Modulation Cancellation
A 55-nm, 1.0-0.4V, 1.25-pJ/MAC Time-Domain Mixed-Signal Neuromorphic Accelerator With Stochastic Synapses for Reinforcement Learning in Autonomous Mobile Robots
SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration
EdgeDiff: Energy-Efficient Multi-Modal Few-Step Diffusion Model Accelerator Using Mixed-Precision and Reordered Group Quantization
A programmable focal-plane MIMD image processor chip
A Time-Resolved NIR Lock-In Pixel CMOS Image Sensor With Background Cancelling Capability for Remote Heart Rate Detection
Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's
A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs
A UWB-IR Transmitter With Digitally Controlled Pulse Generator
Shumbler: a 155 Mb/s BiCMOS synchronous multiplexer chip for a broad-band customer premises network
A 2.17-mW Acoustic DSP Processor With CNN-FFT Accelerators for Intelligent Hearing Assistive Devices
VLSI system design for automotive control
A Low-Jitter and Wide-Frequency-Range D-Band Frequency Synthesizer With a Subsampling PLL and a Harmonic-Boosting Frequency Multiplier
A 232-Channel Epiretinal Stimulator ASIC
A 180 MHz 0.8 mu m BiCMOS modular memory family of DRAM and multiport SRAM
A high-speed low-power JFET pull-down ECL circuit
A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20 MS/s and 54-dB S/N at 30 MS/s
Laser Radar Receiver Channel With Timing Detector Based on Front End Unipolar-to-Bipolar Pulse Shaping
A 6-GHz 16-kB L1 cache in a 100-nm dual-V T technology using a bitline leakage reduction (BLR) technique
A 0.13-μm CMOS 5-Gb/s 10-m 28AWG cable transceiver with no-feedback-loop continuous-time post-equalizer
Fully-Integrated High-Conversion-Ratio Dual-Output Voltage Boost Converter With MPPT for Low-Voltage Energy Harvesting
Direct-coupled distributed baseband amplifier IC's for 40-Gb/s optical communication
An 80-Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTs
A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator
A 100-mW 4×10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects
A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor
A 32-µW 1.83-kS/s Carbon Nanotube Chemical Sensor System
A CMOS image sensor with analog two-dimensional DCT-based compression circuits for one-chip cameras
A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links
A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2-D/3-D Partial Differential Equations
A design technique for a high-gain, 10-GHz class-bandwidth GaAs MESFET amplifier IC module
114 MFLOPS logarithmic number system arithmetic unit for DSP applications
11.6-GHz 1:4 regenerating demultiplexer with bit-rotation control and 6.1-GHz auto-latching phase-aligner ICs using AlGaAs/GaAs HBT technology
A 110-dB-THD, 18-mW DAC using sampling of the output and feedback to reduce distortion
A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell
Co-Integration of an RF Energy Harvester Into a 2.4 GHz Transceiver
Hawkeye: A Point Cloud Neural Network Processor With Virtual Pillar and Quadtree-Based Workload Management for Real-Time Outdoor BEV Detection
A 0.65-V 12-16-GHz Sub-Sampling PLL With 56.4-fs rms Integrated Jitter and -256.4-dB FoM
A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme
Erratum "A wide-band linear amplitude modulator for polar transmitters based on the concept of interleaving delta modulation"
A CMOS smart temperature sensor with a 3σ inaccuracy of ±0.1°C from -55°C to 125°C
A 4.1-mW 10-MHz Fourth-Order Source-Follower-Based Continuous-Time Filter With 79-dB DR
A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio
A Sub-1-V, 10 ppm/°C, Nanopower Voltage Reference Generator
An 86.71875-GHz RF Transceiver for 57.8125-Gb/s Plastic Waveguide Links With a CDR-Assisted Carrier Synchronization Technique in 28-nm CMOS
A 0.5-V 125-MHz 256-Kb 22-nm SRAM With 10-aJ/bit Active Energy and 10-pW/bit Shutdown Power
Logic synthesis and circuit modeling of a programmable logic gate based on controlled quenching of series-connected negative differential resistance devices
A 0.61-μW Fully Integrated Keyword-Spotting ASIC With Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN
A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS
A sophisticated analysis procedure for an MMIC phase shifter
A CMOS 0.8-μm transistor-only 1.63-MHz switched-current bandpass ΣΔ modulator for AM signal A/D conversion
Introduction to the Special Issue on the IEEE 2012 Custom Integrated Circuits Conference
A Fully Integrated Switched-Capacitor-Based AC-DC Converter for a 120 V RMS Mains Interface
A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage
A 75 µ W Real-Time Scalable Body Area Network Controller and a 25 µW ExG Sensor IC for Compact Sleep Monitoring Applications
98.7% Efficiency 1200-48 V LLC Converter Using Triple Step-Down Converter With One-Inductor Technique Compliant With EVSE Level 1
A high-density NAND EEPROM with block-page programming for microcomputer applications
A 10-Gb/s 16: 1 multiplexer and 10-GHz clock synthesizer in 0.25-μm SiGe BiCMOS
A BJT-Based Temperature-to-Digital Converter With ±60 mK (3~σ) Inaccuracy From -55 °C to +125 °C in 0.16-μm CMOS
Correction to "A 70-Mb/s Variable-Rate 1024-QAM Cable Receiver IC with Integrated 10-b ADC and FEC Decoder"
A 0.13 µm CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture
Voltage Level Detection for Near-V TH Computing
A 300 MHz monolithic video current driver for high-resolution CRT applications
A Front-End ASIC With Receive Sub-array Beamforming Integrated With a 32 × 32 PZT Matrix Transducer for 3-D Transesophageal Echocardiography
NRZ timing recovery technique for band-limited channels
A fully integrated CMOS PM radio receiver for wristwatch calibration
Modeling and measurement of substrate coupling in Si-bipolar IC's up to 40 GHz
A 70-100 GHz Direct-Conversion Transmitter and Receiver Phased Array Chipset Demonstrating 10 Gb/s Wireless Link
A CMOS gyrator low-IF filter for a dual-mode Bluetooth/ZigBee transceiver
High-bit-rate, high-input-sensitivity decision circuit using Si bipolar technology
An 11000-fuse electrically erasable programmable logic device (EEPLD) with an extended macrocell
A 700-Mb/s/pin CMOS signaling interface using current integrating receivers
Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS
A PNP-Based Temperature Sensor With Continuous-Time Readout and ±0.1 ∘ C (3σ) Inaccuracy From -55 ∘ C to 125 ∘ C
A third-order sigma-delta modulator with extended dynamic range
A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop