yusuke1997/dblp-id-title huggingface dataset:
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips
Tianhe-1A Interconnect and Message-Passing Services
Architecture for a Hardware-Based, TCP/IP Content-Processing System
A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications
Piton: A Manycore Processor for Multitenant Clouds
Selected Research from Hot Chips 24
Practical High-Throughput Crossbar Scheduling
Twenty Years of the Commercial Internet, Part 2
SymbiFlow and VPR: An Open-Source Design Flow for Commercial and Novel FPGAs
Pulse arithmetic in VLSI neural networks
Attacking complexity
The Modern Digital Operating Model
Effective VLSI processor architectures for HLL computers: the RISC approach
Decentralized NIC-Switching Architecture Using SR-IOV PCI Express Network Device
A Delay Model for Router Microarchitectures
International Standards: Why Do Them?
Architecture of the TRON VLSI CPU
SPARC64 XII: Fujitsu's Latest 12-Core Processor for Mission-Critical Servers
Big Chips and Beyond
Guest Editor's Introduction: Existential Architectures: The Metaphysics of Computer Design
Seek and Show
Multimedia LSI accelerator with embedded DRAM
Energy-Efficient Thread-Level Speculation
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies - Part XII: Patent Families
Status Report on the P896 Backplane Bus
Explaining Booms, Busts, and Errors
Microarchitecture Patents Over Time and Interesting Early Microarchitecture Patents
Leveraging Wire Properties at the Microarchitecture Level
Implications of the Power Wall: Dim Cores and Reconfigurable Logic
DNPU: An Energy-Efficient Deep-Learning Processor with Heterogeneous Multi-Core Architecture
The Queuing-First Approach for Tail Management of Interactive Services
RDMA Congestion Control: It Is Only for the Compliant
Performance in the New Millennium
The MIPS R3010 floating-point coprocessor
Blurring the Lines between Memory and Computation
ATLAS I: implementing a single-chip ATM switch with backpressure
The Crash in Competitive Telephony
Low-Power Automatic Speech Recognition Through a Mobile GPU and a Viterbi Accelerator
Mathematical Software in Basic Evaluation of Definite Integrals
The Heidelberg Polyp System
The Revolution in Spectrum Allocation
Looking Forward to Bright New Beginnings
Microprocessor Design Issues: Thoughts on the Road Ahead
An Open Approach to Autonomous Vehicles
Recent Advances in Compute-in-Memory Support for SRAM Using Monolithic 3-D Integration
Intel Wins in Four Decades, but AMD Catches Up
Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim
Evaluating Sensor Data Quality in Internet of Things Smart Agriculture Applications
Standards Intellectual Property Licensing
Nonblocking DRAM Refresh
Operating Systems for the Micronet Network Computer
A Novel STT-RAM-Based Hybrid Cache for Intermittently Powered Processors in IoT Devices
Race Logic: Abusing Hardware Race Conditions to Perform Useful Computation
Cell Multiprocessor Communication Network: Built for Speed
Prototype Competition and Breakthroughs
Communication Profiling and Characterization of Deep-Learning Workloads on Clusters With High-Performance Interconnects
How Much Apache?
A Smart Digital-Readout Circuit for a Capacitive Microtransducer
Measuring Architectural Vulnerability Factors
The Hot Chips Renaissance
Heterogeneous Computing Meets Near-Memory Acceleration and High-Level Synthesis in the Post-Moore Era
AuRORA: A Full-Stack Solution for Scalable and Virtualized Accelerator Integration
Web concerns [legal aspects]
Containerized In-Storage Processing and Computing-Enabled Solid-State Drive Disaggregation
A Hardware Syntactic Analysis Processor
The "power" of communication
Performance And Availability in a Network File Server
Low-power multimedia RISC
SODA: A High-Performance DSP Architecture for Software-Defined Radio
Making Machine Learning More Energy Efficient by Bringing It Closer to the Sensor
Bleeding-Edge Mass Market Standards
The bleeding edge
PyMTL3: A Python Framework for Open-Source Hardware Modeling, Generation, Simulation, and Verification
Virtualized ECC: Flexible Reliability in Main Memory
Structured Design for Testability in Semicustom VLSI
Mica: A Wireless Platform for Deeply Embedded Networks
Relyzer: Application Resiliency Analyzer for Transient Faults
Ten Years of Top Picks
Developing highly reliable software
FTC and Apple Sue Qualcomm for Cell Phone Standardization Skullduggery, Part 2: Apple's Claims
Large Market on the Horizon
Efficient Construction of Aliasing-Free Compaction Circuitry
History of IBM Z Mainframe Processors
A Novel Processor Architecture with Exact Tag-Free Pointers
An Advanced Educational Microprocessor System
The Aladdin Approach to Accelerator Design and Modeling
Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories
A Cordic Processor for Laser Trimming
Hardware/Software Cost Analysis of Interrupt Processing Strategies
AsmDB: Understanding and Mitigating Front-End Stalls in Warehouse-Scale Computers
StrongARMing portable communications
A Proposed Radix- and Word-length-independent Standard for Floating-point Arithmetic
Coherency Hub Design for Multisocket Sun Servers with CoolThreads Technology
UAV-Assisted Joint Wireless Power Transfer and Data Collection Mechanism for Sustainable Precision Agriculture in 5G
R3TOS-Based Autonomous Fault-Tolerant Systems
Moore's Law and Ultra-Low-Power Processors
Micro Evolution
Research Challenges for On-Chip Interconnection Networks
Sally A. McKee
It's not enough to be right [copyright]
Larrabee: A Many-Core x86 Architecture for Visual Computing
Practical Online Reinforcement Learning for Microprocessors With Micro-Armed Bandit
Using Dataflow to Optimize Energy Efficiency of Deep Neural Network Accelerators
Video RAMs: structure and applications
Designing a Multicore and Multiprocessor Individual-Based Simulation Engine
Learning Hardware Using Multiple-Valued Logic, Part 2: Cube Calculus and Architecture
Compiler challenges with RISCs
On the Feasibility of Attribute-Based Encryption on Internet of Things Devices
Economic Growth from Technical Advance
Top Picks from the 2015 Computer Architecture Conferences
Special Issue on Security and Privacy-Preserving Execution Environments
Growth From Breadth and Depth
Tuning the Pentium Pro microarchitecture
Implementation and performance of the fast Hartley transform
Iterative Modulo Scheduling
Temperature-Aware Architecture: Lessons and Opportunities
A Benchmark Comparison of 32-bit Microprocessors
Sparc64 XIfx: Fujitsu's Next-Generation Processor for High-Performance Computing
A high-speed analog neural processor
Adaptive History-Based Memory Schedulers for Modern Processors
MicroStandards - P961 working group formed
The Engineering Workstation And the Engineering Support System - Present Status, Future Directions
Digital watermarks: Shedding light on the invisible
Networks on Chip with Provable Security Properties
SLDRAM: high-performance, open-standard memory
Architecting Noisy Intermediate-Scale Quantum Computers: A Real-System Study
Enabling Sustainable Cloud Computing With Low-Carbon Server Design
A benchmark tutorial
Merging data converters and DSPs for mixed-signal processors
Dream chip 1: a timed priority queue
Special Issue on TinyML
Scalar Vector Runahead: Removing the Shackles of Indirect Memory Chains on In-Order Cores
TCP Switching: Exposing Circuits to IP
Architectural CO 2 Footprint Tool: Designing Sustainable Computer Systems With an Architectural Carbon Modeling Tool
Editor-in-Chief's Message: Adapting Old Paradigms to Meet New Challenges
Understanding and Characterizing Side Channels Exploiting Phase-Change Memories
AutoML for Architecting Efficient and Specialized Neural Networks
PACMAN: Attacking ARM Pointer Authentication With Speculative Execution
Strategies for Mapping Algorithms to Mediaprocessors for High Performance
From Cool Chips to Hot Interconnects
Analog nonlinear function synthesis
SMT: Software-Defined Memory Tiering for Heterogeneous Computing Systems With CXL Memory Expander
Manuals and guest reviews [Micro review]
Northbridge Architecture of AMD's Griffin Microprocessor Family
Performance Pathologies in Hardware Transactional Memory
The design of the 88000 RISC family
Accelerating Video-Mining Applications Using Many Small, General-Purpose Cores
Designing a custom DSP circuit using VHDL
CHIPKIT: An Agile, Reusable Open-Source Framework for Rapid Test Chip Development
Maintaining Statistics Counters in Router Line Cards
Developing a parallel-readout optical-disk system
Kaya for Computer Architects: Toward Sustainable Computer Systems
A History of Calculating Machines
Cache Memory Design for Internet Processors
Vector Unit Architecture for Emotion Synthesis
An Overview of Time-Based Computing with Stochastic Constructs
Derek de Solla Price and the Antikythera Mechanism: An Appreciation
Qualcomm Oryon CPU in Snapdragon X Elite: Micro-Architecture and Design
DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing
On the edge-analysis of transactions and computers
LastLayer: Toward Hardware and Software Continuous Integration
A Review of Wisconsin Alumni Research Foundation v. Apple - Part V
CPUs, GPUs, and Hybrid Computing
Standardization: art or discipline?
Introducing cool chips
The Prevailing View
Digital Public Goods
Implementing Domain-Specific Languages for Heterogeneous Parallel Computing
Fuzzy-logic-based analog design tools
Variation-tolerant design
A Full HD Multistandard Video Codec for Mobile Applications
The D30V/MPEG multimedia processor
21st-Century Microprocessors
The DSP32C: AT&Ts second generation floating point digital signal processor
Explicit Communication and Synchronization in SARC
ECIM: Exponent Computing in Memory for an Energy-Efficient Heterogeneous Floating-Point DNN Training Processor
ReconOS: An Operating System Approach for Reconfigurable Computing
Comprehensive Circuit Failure Prediction for Logic and SRAM Using Virtual Aging
Software Development Patterns
Special report: Supercomputing-the view from Japan
Intel's 80960: an architecture optimized for embedded control
A Case for Studying DRAM Issues at the System Level
Wagging Wikipedia's long tail
Nuts and Bolts
Flexible Approximate Computing for Mitigating Branch Divergence in GPUs
Productive and Healthy Debate
Emerging Technologies for Quantum Computing
A Fault-Tolerant Multimicroprocessor-Based Computer System for Space-Based Signal Processing
Self-Reconfigurable Embedded Systems on Low-Cost FPGAs
Soil Fertility Monitoring With Internet of Underground Things: A Survey
Where Did the Internet Go?
One of the Last Updates on Rambus Standardization Skullduggery
Two Sides to Scale
Connecting the Home With a Phone Line Network Chip Set
The Range of Linus' Law
Mathematical Microprocessor Software: A x Comparison
Breaking Virtual Memory Protection and the SGX Ecosystem with Foreshadow
Automated Algorithmic Error Resilience Based on Outlier Detection
The 2019 Top Picks in Computer Architecture
Applying the μBTRON bus to a music LAN
The Odd Couple: Hardware and Software
From Mainframes to Microprocessors
Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion
Earning Stripes in Medical Machine Learning
The Arm Morello Evaluation Platform - Validating CHERI-Based Security in a High-Performance System
Displays for electronic imaging
Chip-package codesign for high-frequency circuits and systems
Multibug: Interative Debugging in Distributed Systems
EIC's Message: General-purpose versus application-specific processors
InfiniBridge: An InfiniBand Channel Adapter with Integrated Switch
Transistency Models: Memory Ordering at the Hardware-OS Interface
Hot Interconnects 23
Habana Labs Purpose-Built AI Inference and Training Processor Architectures: Scaling AI Training Systems Using Standard Ethernet With Gaudi Processor
The Xbox Series X System Architecture
Toward Approximate Computing for Coarse-Grained Reconfigurable Architectures
Personal Effectiveness
An Energy-Efficient Programmable Mixed-Signal Accelerator for Machine Learning Algorithms
Java and the PAS process
Heterogeneous Distributed Shared Memory for Lightweight Internet of Things Devices
Ultra-Performance Pascal GPU and NVLink Interconnect
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies - Part V: References
Building Broadband Ahead of Digital Demand
A Top-Down Approach to Architecting CPI Component Performance Counters
Design of Programmable Analog Calculation Unit by Implementing Support Vector Regression for Approximate Computing
Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays
A logical design tool for relational databases
Asynchronous Interconnect for Synchronous SoC Design
Broadcast-Enabled Massive Multicore Architectures: A Wireless RF Approach
EIC's Message: Chip-level microarchitecture trends
Imagine: Media Processing with Streams
The Xbox One X Scorpio Engine
Ginkgo: A Learned-Index Enhanced Tiered Memory System
Holiday Reading
Kilo-Instruction Processors: Overcoming the Memory Wall
Myrinet: A Gigabit-per-Second Local Area Network
Making Standards Simple
An efficient scheme for interprocessor communication using dual-ported RAMs
An operating system for a fault-tolerant multiprocessor controller
XiangShan: An Open Source Project for High-Performance RISC-V Processors Meeting Industrial-Grade Standards
Security and Our Reader Survey
Embedded control problems, Thumb, and the ARM7TDMI
My Computer Journey
Synergistic Processing in Cell's Multicore Architecture
A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches
Designing the MPC105 PCI bridge/memory controller
The AMD 400-G Adaptive SmartNIC System on Chip: A Technology Preview
The Efficient Digital Implementation of Subtractive Music Synthesis
Federal Circuit Speaks Out on Determining RAND Royalties for Standards
TNet: A Reliable System Area Network
CMOS Photonics for High-Speed Interconnects
Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power
Micro Web and uRAP
A Microprocessor-controlled Message Display System
A Hardware Memory Race Recorder for Deterministic Replay
Arbitration and Control Acquisition in the Proposed IEEE 896 Futurebus
An associative processing module for a heterogeneous vision architecture
Cost-Efficient Dragonfly Topology for Large-Scale Systems
Hot Chips in an Increasingly Diverse Microprocessor Landscape
The Microprocessor Universal Format for Object Modules
Transforming Binary Code for Low-Power Embedded Processors
ETA: Experience with an Intel Xeon Processor as a Packet Processing Engine
Baking the Data Layer [Micro Economics]
The Hardware Security Behind Azure Sphere
Photonic Network-on-Wafer for Multichiplet GPUs
Efficient Situational Scheduling of Graph Workloads on Single-Chip Multicores and GPUs
The Intel 376 family for embedded processor applications
The TMS390C602A floating-point coprocessor for Sparc systems
Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth
Top Picks From Year 2020
Top Picks from the 2017 Computer Architecture Conferences
More standardization skullduggery
Capturing images with digital still cameras
A Throughput-Optimized Optical Network for Data-Intensive Computing
Fault-Tolerant Adaptive Scheduling for Embedded Real-Time Systems
Challenging search engines under copyright law: Part 1
A Microcomputer-based Model Robot System with Pulse-Width Modulation Control
NVIDIA Tesla: A Unified Graphics and Computing Architecture
The cache DRAM architecture: a DRAM with an on-chip cache memory
Fault Tolerance Achieved in VLSI
Looking Forward to Upcoming Themes
Intel Atom C2000 Processor Family: Power-Efficient Datacenter Processing
Optisim: A System Simulation Methodology for Optically Interconnected HPC Systems
Writing the claims for a patent
Temperature-Aware On-Chip Networks
Sega Dreamcast: creating a unified entertainment world
QsNetII: Defining High-Performance Network Design
Megacells
The 15-Billion-Dollar Broadband Bonus
Niagara: A 32-Way Multithreaded Sparc Processor
Chain: A Delay-Insensitive Chip Area Interconnect
Can Subthreshold and Near-Threshold Circuits Go Mainstream?
Hardware Designs for Security in Ultra-Low-Power IoT Systems: An Overview and Survey
Corrections to "Countering Load-to-Use Stalls in the NVIDIA Turing GPU"
The Long Arc Behind Bill Gates' Wealth
Bobcat: AMD's Low-Power x86 Processor
Smart Network Interfaces for Advanced Automotive Applications
Quantum Computing and More!
Reg-TuneV2: A Hardware-Aware and Multiobjective Regression-Based Fine-Tuning Approach for Deep Neural Networks on Embedded Platforms
IP-Related Refusals to Deal. Part 1: Updating the Intel-Intergraph Controversy
Speculative Incoherent Cache Protocols
Using term rewriting systems to design and verify processors
LSFQ: A Low-Bit Full Integer Quantization for High-Performance FPGA-Based CNN Acceleration
The Use and Abuse of SPEC: An ISCA Panel
Agile and Open-Source Hardware
Guest Editor's Introduction - Java's Open Future
Reducing system cost with software modems
Better Branch Prediction Through Prophet/Critic Hybrids
Operating Systems Research for Reconfigurable Computing
Compute Substrate for Software 2.0
Guest Editors' Introduction: Micro's Top Picks from Microarchitecture Conferences
Codesign of architectures for automotive powertrain modules
The Path to Powering Intelligence
Near-Data Processing [Guest editors' introduction]
Tolerating Cache-Miss Latency with Multipass Pipelines
A 5-GHz Mesh Interconnect for a Teraflops Processor
NVIDIA A100 Tensor Core GPU: Performance and Innovation
Microvias: the next generation of substrates and packages
Appropriate and inappropriate legal protection of user interfaces and screen displays. I
Ten Open Questions for Techno-Optimists
A Case for NOW (Networks Of Workstations)
Debunking the productivity paradox
Designing and Managing Data centers Powered by Renewable Energy
Hardware and Software Symbiosis Helps Smart Card Evolution
Reliability-Aware Microarchitecture Design
Extending the Frontier of Quantum Computers With Qutrits
Bank Runs Without the Wisdom of the Crowds
Monitoring InfiniBand Networks to React Efficiently to Congestion
Designing and programming the emotion engine
Accelerator Architectures A Ten-Year Retrospective
Beyond Efficiency: Scaling AI Sustainably
Agile Hardware Design
Decoupled Vector Runahead for Prefetching Nested Memory-Access Chains
The Problem of Evaluating CPU-GPU Systems with 3D Visualization Applications
Scalable Heterogeneous CPU-GPU Computations for Unstructured Tetrahedral Meshes
HASE DLX Simulation Model
Electrical modeling and simulation challenges in chip-package codesign
Congestion on the Last Mile
Guest Editors' Introduction: Reliability-Aware Microarchitecture
Calm Economics
Associative processors and memories: a survey
The Value of Free in GDP
Breaking the Address Translation Wall by Accelerating Memory Replays
The Medfield Smartphone: Intel Architecture in a Handheld Form Factor
Microcontroller design advantages for portable computing
The PTO on software patents
The zEnterprise 196 System and Microprocessor
Security Refresh: Protecting Phase-Change Memory against Malicious Wear Out
Innovation at the Edges
Content providers: "I was framed" [copyright]
Standards Give You Control
Microprocessors at 25
A fuzzy partitioning system
Performance and the i860 microprocessor
Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer
The Renesas Automotive Story in the History of the Microprocessor
Managing the Transition from Complexity to Elegance: Knowing When You Have a Problem
Cache performance of the SPEC92 benchmark suite
Helix: Making the Extraction of Thread-Level Parallelism Mainstream
Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue
Preparing for multimedia terminals
A Test, Debug, and Silicon Lifecycle Management Architecture for a UCIe-Based Open Chiplet Ecosystem
Automatic Assembler Source Translation from the Z80 to the MC6809
Reverse engineering for future compatibility
Digitally Assisted Analog Circuits
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface
Challenges and Opportunities for Autonomous Micro-UAVs in Precision Agriculture
Achieving Exascale Capabilities through Heterogeneous Computing
Kilo TM: Hardware Transactional Memory for GPU Architectures
Hardware approaches to cache coherence in shared-memory multiprocessors. 2
SimWattch: Integrating Complete-System and User-Level Performance and Power Simulators
The proposed SSBLT standard doubles the VME64 transfer rate
Insider Privileges
Markets, standards, and the information infrastructure
PurpleDrop: A Digital Microfluidics-Based Platform for Hybrid Molecular-Electronics Applications
Corsair: An In-Memory Computing Chiplet Architecture for Inference-Time Compute Acceleration
A Mobile DNN Training Processor With Automatic Bit Precision Search and Fine-Grained Sparsity Exploitation
Pygmalion: ESPRIT II project 2059, neurocomputing
Challenges in cross-development [single chip microprocessors]
The High Cost of a Cheap Lesson
Flying IoT: Toward Low-Power Vision in the Sky
An Augmented Reality Processor with a Congestion-Aware Network-on-Chip Scheduler
A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform
Repetitive stress injuries
The EMU10K1 digital audio processor
Falling Through the Cracks at Microsoft
Guest Editors' Introduction: Network Processors for Future High-End Systems and Applications
The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor
Protecting industrial property rights
Characterizing the Cell EIB On-Chip Network
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs
The diamond-wafer paradox: A modern mystery
Artificial-Intelligence-Enhanced Ultrasound Flow Imaging at the Edge
Bridging the Ethernet-Ethernot Performance Gap
A Low-Latency and Low-Power Approach for Coherency and Memory Protocols on PCI Express 6.0 PHY at 64.0 GT/s With PAM-4 Signaling
Mathematical Software in Basic Dint: Data Integration
Superscalar instruction issue
Amore Address Mapping with Overlapped Rotating Entries
Exploiting Workload Parallelism for Performance and Power Optimization in Blue Gene
Power Side-Channel Attacks in Negative Capacitance Transistor
What is patentable?
2013 International Symposium on Computer Architecture Influential Paper Award
Scheduling for reactive real-time systems
Software-Hardware Codesign for Efficient Neural Network Acceleration
An Evaluation of 8085-based Multiprocessing on a Timeshared Bus
Per-Instruction Cycle Stacks Through Time-Proportional Event Analysis
New Jersey federal court holds Qualcomm's unFRANDly acts no antitrust violation
A Logic-on-Memory Processor-System Design With Monolithic 3-D Technology
The eTRON Wide-Area Distributed-System Architecture for E-Commerce
8 Bits in an IoT World: Legacy Chips Simplify Advanced Architecture Interfaces
Twenty Years of the Commercial Internet, Part 1
PCs Take a Page From Xbox With Pluton
Real SIPs
Transactional Memory: The Hardware-Software Interface
Ubiquitous clicks and complements
Behind the Buzz of Behavioral Data
Working On The Web
The V.42bis standard for data-compressing modems
A Fast Integer Binary Logarithm of Large Arguments
Guest Editors' Introduction: Solving Interconnection Problems
Generating Systolic Array Accelerators With Reusable Blocks
Calisto: A Low-Power Single-Chip Multiprocessor Communications Platform
Hierarchical Temporal Memory on the Automata Processor
What Made Us Stronger: An Inside Look Back at the History of AMD Microprocessor Development
The Design of a DC/AC Inverter with the MC68HC11 Microcomputer
Motorola's MC68HC11: Definition and Design of a VLSI Microprocessor
Accelerating the Accelerator Memory Interface with Access-Execute and Dataflow
Efficient Multimatch Packet Classification and Lookup with TCAM
Revizor: Testing Black-Box CPUs Against Speculation Contracts
Why Inventors are not Famous
PC Stat Packages
The microprocessor today
Enabling Artificial Intelligence Supercomputers With Domain-Specific Networks