yusuke1997/dblp-id-title huggingface dataset:
A 7.9-GHz Transformer-Feedback Quadrature Oscillator With a Noise-Shifting Coupling Network
A digital background calibration technique for time-interleaved analog-to-digital converters
Inductorless, Widely Tunable N-Path Shekel Circulators Based on Harmonic Engineering
Sub-mW Current Re-Use Receiver Front-End for Wireless Sensor Network Applications
Introduction to the Special Section on the 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC)
A high-speed digital neural network chip with low-power chain-reaction architecture
Low-Power 32-bit Dual-MAC 120 µW/MHz 1.0 V icyflex1 DSP/MCU Core
Design of ESD power protection with diode structures for mixed-power supply systems
The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4
A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer
A 7.1 mW 1 GS/s ADC With 48 dB SNDR at Nyquist Rate
Guest Editorial Introduction to the Special Section on the 2020 RFIC Symposium
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface
Analytic and iterative transit-time models for VLSI MOSFETs in strong inversion
A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR
A Software-Defined Always-On System With 57-75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC
A fully integrated multiband MIMO WLAN transceiver RFIC
A Current-Mode, Low Out-of-Band Noise LTE Transmitter With a Class-A/B Power Mixer
A 700-kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications
Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters
A Breakdown Voltage Multiplier for High Voltage Swing Drivers
A fully integrated analog front-end macro for cable modem applications in 0.18-μm CMOS
A high-speed shuffle bus for VLSI arrays
A 0.26-nJ/node, 400-kHz Tx Driving, Filtered Fully Differential Readout IC With Parasitic RC Time Delay Reduction Technique for 65-in 169×97 Capacitive-Type Touch Screen Panel
Latch-up testing in CMOS IC's
A general theory of phase noise in electrical oscillators
A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration
Clock and Synchronization Networks for a 3 GHz 64 Bit ARMv8 8-Core SoC
Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements
An Indirect ToF Sensor With In-Pixel Adaptive ΔΣ -Scheme for Background Light Rejection and Floating Diffusion Mismatch Cancellation
Highly Reliable and Low Power SSD Using Asymmetric Coding and Stripe Bitline-Pattern Elimination Programming
A 65 nm CMOS Quadrature Balanced Switched-Capacitor Power Amplifier for Full- and Half-Duplex Wireless Operation
A high-dynamic-range integrated continuous-time bandpass filter
A 0.025-mm 2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure
A ±1-g dual-axis linear accelerometer in a standard 0.5-μm CMOS technology for high-sensitivity applications
A 723-MHz 17.2-mW CMOS programmable counter
A high resolution multibit sigma-delta modulator with individual level averaging
A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System
A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme
A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS
Analog/RF Built-in-Self-Test Subsystem for a Mobile Broadcast Video Receiver in 65-nm CMOS
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor
A 0.53-THz Subharmonic Injection-Locked Phased Array With 63-µW Radiated Power in 40-nm CMOS
A 1.8-V digital-audio sigma-delta modulator in 0.8-μm CMOS
A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement
A 12-bit 3.125 MHz Bandwidth 0-3 MASH Delta-Sigma Modulator
Design Techniques for a Mixed-Signal I/Q 32-Coefficient Rx-Feedforward Equalizer, 100-Coefficient Decision Feedback Equalizer in an 8 Gb/s 60 GHz 65 nm LP CMOS Receiver
A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS
A 0.39-mm 2 Stacked Standard-CMOS Humidity Sensor Using a Charge-Redistribution Correlated Level Shifting Floating Inverter Amplifier and a VCO-Based Zoom CDC
A 0.5-1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator
A 354F 2 Leakage-Based Physically Unclonable Function With Lossless Stabilization Through Remapping for Low-Cost IoT Security
A G m -C low-pass filter for zero-IF mobile applications with a very wide tuning range
A new asynchronous pipeline scheme: application to the design of a self-timed ring divider
An all-digital analog-to-digital converter with 12-μV/LSB using moving-average filtering
High-voltage-tolerant I/O buffers with low-voltage CMOS process
A compact thermal noise model for the investigation of soft error rates in MOS VLSI digital circuits
A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx
40-Gb/s circuits built from a 120-GHz f T SiGe technology
A MEMS-Based Optical Scanning System for Precise, High-Speed Neural Interfacing
0.4-V logic-library-friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme
A 9.6-mW/Ch 10-MHz Wide-Bandwidth Electrical Impedance Tomography IC With Accurate Phase Compensation for Early Breast Cancer Detection
Low-OSR Over-Ranging Hybrid ADC Incorporating Noise-Shaped Two-Step Quantizer
A programmable clock generator that uses noise shaping and its application in switched-capacitor filters
Fully integrated CMOS power amplifier design using the distributed active-transformer architecture
A Calibration-Free Fractional-N Analog PLL With Negligible DSM Quantization Noise
A Cascode Miller-Compensated Three-Stage Amplifier With Local Impedance Attenuation for Optimized Complex-Pole Control
An accurate quality factor tuning scheme for IF and high-Q continuous-time filters
A Non-Coherent DPSK Data Receiver With Interference Cancellation for Dual-Band Transcutaneous Telemetries
A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-μm CMOS
An ULV PWM CMOS Imager With Adaptive-Multiple-Sampling Linear Response, HDR Imaging, and Energy Harvesting
S/370 sign-magnitude floating-point adder
An Energy-Efficient All-Digital UWB Transmitter Employing Dual Capacitively-Coupled Pulse-Shaping Drivers
16-Mb synchronous DRAM with 125-Mbyte/s data rate
Ultrahigh efficiency obtained with GaAs-on-insulator MESFET technology
A high-speed sensing scheme for 1T dynamic RAMs utilizing the clamped bit-line sense amplifier
A Broadband 300 GHz Power Amplifier in a 130 nm SiGe BiCMOS Technology for Communication Applications
A low-power wide dynamic range envelope detector
A CMOS-only micro touch pointer
High-Rejection RF Code Domain Receivers for Simultaneous Transmit and Receive Applications
S2ADC: A 12-bit, 1.25-MS/s Secure SAR ADC With Power Side-Channel Attack Resistance
A low-power chipset for a portable multimedia I/O terminal
A 0.13 μm CMOS front-end, for DCS1800/UMTS/802.11b-g with multiband positive feedback low-noise amplifier
A 65-nm Energy-Efficient Interframe Data Reuse Neural Network Accelerator for Video Applications
A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface
Introducing Our Sister Publication: IEEE Solid-State Circuits Letters
A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells
A 9 μ A, Addressable Gen2 Sensor Tag for Biosignal Acquisition
A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA
A 2/3-in 2 million pixel STACK-CCD HDTV imager
A compact, high-gain, 2-20-GHz MMIC amplifier
A Multi-Carrier QAM Transceiver for Ultra-Wideband Optical Communication
On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR
A - 244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique
A high-speed parallel sensing architecture for multi-megabit flash E 2 PROMs
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS
A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme
Application of a 3000-gate GaAs array in the development of a gigahertz digital test system
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS
A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS
A DSP-based hearing instrument IC
New techniques for high-frequency RMS-to-DC conversion based on a multifunctional V-to-I convertor
A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC
A Fully Row/Column-Parallel In-Memory Computing Macro in Foundry MRAM With Differential Readout for Noise Rejection
Distributed Injection-Locked Frequency Dividers
Flying-Adder Fractional Divider Based Integer-N PLL: 2nd Generation FAPLL as On-Chip Frequency Generator for SoC
Single-Chip 3072-Element-Channel Transceiver/128-Subarray-Channel 2-D Array IC With Analog RX and All-Digital TX Beamformer for Echocardiography
Impedance Adapting Compensation for Low-Power Multistage Amplifiers
Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference
A 65-nm, 1-A Buck Converter With Multi-Function SAR-ADC-Based CCM/PSK Digital Control Loop
The effects of BJT self-heating on circuit behavior
Architecture and design of a 500-MHz gallium-arsenide processing element for a parallel supercomputer
Highly parallel collision detection processor for intelligent robots
Internal voltage generator for low voltage, quarter-micrometer flash memories
A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS
A 622-Mb/s Mixed-Mode BPSK Demodulator Using a Half-Rate Bang-Bang Phase Detector
A 1.94 to 2.55 GHz, 3.6 to 4.77 GHz Tunable CMOS VCO Based on Double-Tuned, Double-Driven Coupled Resonators
A 0.5-V 1-Msps Track-and-Hold Circuit With 60-dB SNDR
A 3-V monolithic SiGe HBT power amplifier for dual-mode (CDMA/AMPS) cellular handset applications
A Millimeter-Wave Mutual-Coupling-Resilient Double-Quadrature Transmitter for 5G Applications
A 7 ps Jitter 0.053 mm 2 Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC
An image signal multiprocessor on a single chip
Capacitive Power Management Circuit for Micropower Thermoelectric Generators With a 1.4 µA Controller
Baseband to 140-GHz SiGe HBT and 100-GHz InP DHBT Broadband Triple-Stacked Distributed Amplifiers With Active Bias Terminations
A 2-GHz CMOS image-reject receiver with LMS calibration
A 12-bit, 1-MHz, two-step flash ADC
A Battery-to-3.4 V Hybrid Buck-Boost Converter With Always Reduced Conduction Loss
Linearization Through Dithering: A 50 MHz Bandwidth, 10-b ENOB, 8.2 mW VCO-Based ADC
A high-resolution time interpolator based on a delay locked loop and an RC delay line
A 1.2-6 Gb/s, 4.2 pJ/Bit Clock & Data Recovery Circuit With High Jitter Tolerance in 0.14 µm CMOS
Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access
A CMOS Passive LPTV Nonmagnetic Circulator and Its Application in a Full-Duplex Receiver
A Sub-2 W Low Power IA Processor for Mobile Internet Devices in 45 nm High-k Metal Gate CMOS
Spatial Interferer Rejection in a Four-Element Beamforming Receiver Front-End With a Switched-Capacitor Vector Modulator
A 4-Element Phased-Array System With Simultaneous Spatial- and Frequency-Domain Filtering at the Antenna Inputs
Active compensation of operational transconductance amplifier filters using partial positive feedback
A Low-Power CMOS Receiver for 5 GHz WLAN
A 5-6-GHz bipolar quadrature-phase Generator
Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration
A Configurable Successive-Cancellation List Polar Decoder Using Split-Tree Architecture
Substrate-aware mixed-signal macrocell placement in WRIGHT
Circuit techniques for a 1.8-V-only NAND flash memory
A 40-GHz Mirrored-Cascode Differential Transimpedance Amplifier in 65-nm CMOS
Analysis and simulation of spectral regrowth in radio frequency power amplifiers
A Complete 256-Electrode Retinal Prosthesis Chip
Low-power on-chip supply voltage conversion scheme for ultrahigh-density DRAMs
An Architecture for Large-Area Sensor Acquisition Using Frequency-Hopping ZnO TFT DCOs
A 100 MHz Hybrid Supply Modulator With Ripple-Current-Based PWM Control
Compact modeling of the influence of emitter stored charge on the high frequency small signal AC response of bipolar transistors using quasi-static parameters
Integrated Synthetic Fourth-Order $Q$ -Enhanced Bandpass Filter With High Dynamic Range, Tunable Frequency, and Fractional Bandwidth Control
A Monolithic High-Efficiency 2.4-GHz 20-dBm SiGe BiCMOS Envelope-Tracking OFDM Power Amplifier
A High-Voltage Generator and Multiplexer for Electrostatic Actuation in Programmable Matter
Built-in test of CMOS state machines with realistic faults: a system perspective
Design of digital filters for advanced telecommunications ASIC's using a special-purpose silicon compiler
The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning
Clock generation and distribution for the first IA-64 microprocessor
A 3.3-V ISDN U-interface line driver with a new I Q -control circuit
A variable range bi-phasic current stimulus driver circuitry for an implantable retinal prosthetic device
Equalization and FEC techniques for optical transceivers
A 60 pW g m C Continuous Wavelet Transform Circuit for Portable EEG Systems
A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation
A 43-97-GHz Mixer-First Front-End With Quadrature Input Matching and On-Chip Image Rejection
A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI
A Linear High-Efficiency Millimeter-Wave CMOS Doherty Radiator Leveraging Multi-Feed On-Antenna Active Load Modulation
Resistive interpolation biasing: a technique for compensating linear variation in an array of MOS current sources
A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver
A 1-V 450-nW Fully Integrated Programmable Biomedical Sensor Interface Chip
A 1.2-V 2.87-μ W 94.0-dB SNDR Discrete-Time 2-0 MASH Delta-Sigma ADC
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications
A Spurious-Free Switching Buck Converter Achieving Enhanced Light-Load Efficiency by Using a ΔΣ-Modulator Controller With a Scalable Sampling Frequency
A Piecewise Linear 10 Bit DAC Architecture With Drain Current Modulation for Compact LCD Driver ICs
Analog CMOS implementation of high frequency least-mean square error learning circuit
Design and Analysis of a Self-Oscillating Class D Audio Amplifier Employing a Hysteretic Comparator
1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-μm CMOS
Dynamic Quadrant Swapping Scheme Implemented in a Post Conversion Block for I, Q Mismatch Reduction in a DQPSK Receiver
A 12-Bit, 300-MS/s Single-Channel Pipelined-SAR ADC With an Open-Loop MDAC
An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65 nm
Simultaneous switching ground noise calculation for packaged CMOS devices
A regulated charge pump with small ripple voltage and fast start-up
Complementary Constant-g m Biasing of Nauta-Transconductors in Low-Power g m -C Filters to ±2% Accuracy Over Temperature
Perspective on BiCMOS VLSIs
A 15-GHz monolithic low-phase-noise VCO using AlGaAs/GaAs HBT technology
A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators
A second-order high-resolution incremental A/D converter with offset and charge injection compensation
Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and V TH -Tuned Oscillator With Fixed Charge Programming
A Dual-Polarization Silicon-Photonic Coherent Receiver Front-End Supporting 528 Gb/s/Wavelength
A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current
A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file
A Sub-nW/kHz Relaxation Oscillator With Ratioed Reference and Sub-Clock Power Gated Comparator
A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Transmitter and Local LO-Path Phase Shifting
Design of a 10.56-Gb/s 64-QAM Polar Transmitter at 60 GHz in 28-nm CMOS
A 0.13 µm 8 Mb Logic-Based Cu x Si y O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction
A 60 µW 60 nV/√Hz Readout Front-End for Portable Biopotential Acquisition Systems
A Predistortion-Less Digital MIMO Transmitter With DTC-Based Quadrature Imbalance Compensation
High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology
A 50-Gb/s PAM-4 Silicon-Photonic Transmitter Incorporating Lumped-Segment MZM, Distributed CMOS Driver, and Integrated CDR
A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling
An IEEE 802.15.4/4z Coherent Quadrature Hybrid Correlation UWB Receiver in 65-nm CMOS
A Broadband Noise-Canceling CMOS LNA for 3.1-10.6-GHz UWB Receivers
A 2.5-GHz BiCMOS transceiver for wireless LAN's
Defect-tolerant hierarchical sorting networks for wafer-scale integration
Implicit Common-Mode Resonance in LC Oscillators
A Single-Duty-Cycled Buck-Boost Converter Achieving Low Output Ripple and Seamless Mode Transition
An SRAM-Based Reconfigurable Cognitive Computation Matrix for Sensor Edge Applications
An Inductive Voltage-/Current-Mode Integrated Power Management With Seamless Mode Transition and Energy Recycling
An iPWM Line-Coding-Based Wireline Transceiver With Clock -Domain Encoding for Compensating Up To 27-dB Loss While Operating at 0.5-to-0.9 V and 3-to-16 Gb/s in 65-nm CMOS
Design of a 4-W Envelope Tracking Power Amplifier With More Than One Octave Carrier Bandwidth
FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm 2 Analog Compute-in-Memory Macro
The design and implementation of a low-power clock-powered microprocessor
A 1.9-GHz CMOS VCO with micromachined electromechanically tunable capacitors
A 148-GHz Radiator Using a Coupled Loop Oscillator With a Quad-Feed Antenna in 22-nm FD-SOI
Guest Editorial 2022 Custom Integrated Circuits Conference
A Reed-Solomon product-code (RS-PC) decoder chip for DVD applications
A CMOS 10-gb/s power-efficient 4-PAM transmitter
A single chip iΔ-Σ ADC with a built-in variable gain stage and DAC with a charge integrating subconverter for a 5 V 9600-b/s modem
KISS-16V2: a one-chip ASIC DSP solution for GSM
A portable digital DLL for high-speed CMOS interface circuits
A VLIW processor with reconfigurable instruction set for embedded applications
A 10-bit pipelined switched-current A/D converter
An 82-mW ΔΣ-Based Filter-Less Class-D Headphone Amplifier With -93-dB THD+N, 113-dB SNR, and 93% Efficiency
A comparison of gold and superconductors used as air-bridge and microstrip interconnects for high-speed VLSI
Reduced implementation of D-type DET flip-flops
Low-latency, high-speed numerically controlled oscillator using progression-of-states technique
An 18 b 12.5 MS/s ADC With 93 dB SNR
Mixed analog/digital, FIR/IIR realization of a linear-phase lowpass filter
Performance and V dd scaling in deep submicrometer CMOS
A 5.2 mW Self-Configured Wearable Body Sensor Network Controller and a 12 μ W Wirelessly Powered Sensor for a Continuous Health Monitoring System
Modeling frequency dependence of GaAs MESFET characteristics
Investigation of very fast and high-current transients in digital bipolar IC's using both a new compact model and a device simulator
A 90-nm variable frequency clock system for a power-managed itanium architecture processor
A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration
A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis
An Area- and Energy-Efficient Multimode FFT Processor for WPAN/WLAN/WMAN Systems
Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers
Beamformer With Constant-Gm Vector Modulators and Its Spatial Intermodulation Distortion
Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors
A 23-40-GHz Phased-Array Receiver Using 14-Bit Phase-Gain Manager and Wideband Noise-Canceling LNA
A 54-MHz CMOS programmable video signal processor for HDTV applications
Analysis, design, and optimization of spiral inductors and transformers for Si RF ICs
A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS
Overview for the Special Section on the 2008 Radio Frequency Integrated Circuits Symposium
Wideband Mixed-Domain Multi-Tap Finite-Impulse Response Filtering of Out-of-Band Noise Floor in Watt-Class Digital Transmitters
A 5-mW 6-Gb/s Quarter-Rate Sampling Receiver With a 2-Tap DFE Using Soft Decisions
A four-input beam-forming downconverter for adaptive antennas
Light Source Position Measurement Technique Applicable in SOI Technology
A 72-GS/s 9b Time-Interleaved Pipeline-SAR ADC Achieving 55.3/49.3-dB SFDR at 20-GHz/Nyquist Inputs in 16-nm FinFET
A Low-Power VGA Vision Sensor With Embedded Event Detection for Outdoor Edge Applications
A 4.78 mm 2 Fully-Integrated Neuromodulation SoC Combining 64 Acquisition Channels With Digital Compression and Simultaneous Dual Stimulation
A WSI approach towards defect/fault-tolerant reconfigurable serial systems
Even harmonic double-balanced active mixer for use in direct conversion receivers
Guest Editorial Message From the Outgoing Editor-in-Chief
A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission
On the use of Nauta's transconductor in low-frequency CMOS g m -C bandpass filters
Low-frequency noise in UHV/CVD epitaxial Si and SiGe bipolar transistors
Heterodyne Phase Locking: A Technique for High-Speed Frequency Division
A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder
An 8.29 mm 2 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 µm CMOS Process
Millimeter-Wave SiGe Radiometer Front End With Transformer-Based Dicke Switch and On-Chip Calibration Noise Source
Single-Chip W-band SiGe HBT Transceivers and Receivers for Doppler Radar and Millimeter-Wave Imaging
A 2-mm 2 0.1-5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS
A multimode 0.3-200-kb/s transceiver for the 433/868/915-MHz bands in 0.25-μm CMOS
Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay
A 110/230 V AC and 15-400 V DC 0.3 W Power-Supply IC With Integrated Active Zero-Crossing Buffer
A 4-91-GHz traveling-wave amplifier in a standard 0.12-μm SOI CMOS microprocessor technology
A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS
A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC
Direct 12V/24V-to-1V Tri-State Double Step-Down Power Converter With Online V CF Rebalancing and In-Situ Precharge Rate Regulation
A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces
A CMOS Batcher and Banyan chip set for B-ISDN packet switching
A fully integrated SONET OC-48 transceiver in standard CMOS
Design and analysis of DC-to-14-GHz and 22-GHz CMOS cascode
SAW-Less Analog Front-End Receivers for TDD and FDD
A high-resolution synchronous mirror delay using successive approximation register