yusuke1997/dblp-id-title huggingface dataset:
Analysis of Clock Jitter in Continuous-Time Sigma-Delta Modulators
Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers
Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution
A Charge-Based Low-Power High-SNR Capacitive Sensing Interface Circuit
An Efficient Low-Latency Point-Multiplication Over Curve25519
A Novel Iterative Reliability-Based Majority-Logic Decoder for NB-LDPC Codes
T-S fuzzy controllers for nonlinear interconnected systems with multiple time delays
Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation
Interreciprocity in Linear Periodically Time-Varying Networks With Sampled Outputs
A unified approach to the design of PWM-based sliding-mode voltage controllers for basic DC-DC converters in continuous conduction mode
Ultrasonic Time Delay Difference Estimation With Analytic Signals and a Model System
In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers
Low-Complexity Binary Morphology Architectures With Flat Rectangular Structuring Elements
A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter
On Diagnosing the Aging Level of Automotive Semiconductor Devices
Sub-Nanoampere One-Shot Single Electron Transistor Readout Electrometry Below 10 Kelvin
Time-Skew Estimation for Random Sampling Sequence Time-Interleaved ADCs
A 1-µs Ramp Time 12-bit Column-Parallel Flash TDC-Interpolated Single-Slope ADC With Digital Delay-Element Calibration
Wideband Multi-Mode CMOS VCO Design Using Coupled Inductors
A Concurrent Dual-Band Uneven Doherty Power Amplifier with Frequency-Dependent Input Power Division
Inherently Accurate Attenuation-Based Digital Calibration of ADC
Modeling Valance Change Memristor Device: Oxide Thickness, Material Type, and Temperature Effects
Robust Kalman Filtering for Discrete-Time Systems With Measurement Delay
Phase Noise and Noise Induced Frequency Shift in Stochastic Nonlinear Oscillators
Baseband Superregenerative Amplification
A 22-to-47 GHz 2-Stage LNA With 22.2 dB Peak Gain by Using Coupled L-Type Interstage Matching Inductors
Noise Weighting in the Design of ΔΣ Modulators (With a Psychoacoustic Coder as an Example)
Low-Power Receivers for Wireless Capacitive Coupling Transmission in 3-D-Integrated Massively Parallel CMOS Imager
I/Q Imbalance Calibration Method for 5G Ultra-Wideband Transceivers
Model Predictive Control Equalization for High-Speed I/O Links
MWSCAS Guest Editorial Special Issue Based on the 62nd International Midwest Symposium on Circuits and Systems
Open DNN Box by Power Side-Channel Attack
Modeling of Resistance in FinFET Local Interconnect
Phase-Shift-Free M-Phase Spreading Sequences of Markov Chains
ANOVA Kernel Kalman Filter for Multi-Objective Grid Integrated Solar Photovoltaic-Distribution Static Compensator
A 5 Gb/s Transmitter With a TDR-Based Self-Calibration of Preemphasis Strength
Ask Less, Get More: Side-Channel Signal Hiding, Revisited
A High Temperature Frequency Signal Conditioning Unit for Aeronautical Rotating Systems
A 5.1-to-7.3 mW, 2.4-to-5 GHz Class-C Mode-Switching Single-Ended-Complementary VCO Achieving >190 dBc/Hz FoM
K-Band Dual-Mode Receiver CMOS IC for FMCW/UWB Radar
A Signal-Perturbation-Free Transmit Scheme for MIMO-OFDM Channel Estimation
Exponential H INFINITY Filter Design for Discrete Time-Delay Stochastic Systems With Markovian Jump Parameters and Missing Measurements
A 40-Gb/s 2 11 -1 PRBS With Distributed Clocking and a Trigger Countdown Output
Power and Conjugately Matched High Band UWB Power Amplifier
Two-variable polynomials: intersecting zeros and stability
Hysteresis Switching Control of the Ćuk Converter
Improved Swing Equation and Its Properties in Synchronous Generators
Analysis and Design of Singly Terminated Transmission-Line FIR Adaptive Equalizers
Order Statistics and Optimal Selection of Unit Elements in DACs to Enhance the Static Linearity
X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function Design
Digital Laguerre filter design with maximum passband-to-stopband energy ratio subject to peak and Group delay constraints
An Intra-Iterative Interference Cancellation Detector for Large-Scale MIMO Communications Based on Convex Optimization
Bias-Compensated MCCC Algorithm for Widely Linear Adaptive Filtering With Noisy Data
Current Feedback Compensation Circuit for 2T1C LED Displays: Analysis and Evaluation
Negative Impedance Converter With Reduced Nonideal Gain and Parasitic Impedance Effects
A switched-current sensing architecture for a four-state per cell magnetic tunnel junction MRAM
Robust Near-Threshold Design With Fine-Grained Performance Tunability
A New Class of Reciprocal-Orthogonal Parametric Transforms
Two Phase (Reconfigurable) Inverting Switched Capacitor Converter for Micro Power Applications and its Accurate Equivalent Resistance Calculation
Area-Efficient Subquadratic Space-Complexity Digit-Serial Multiplier for Type-II Optimal Normal Basis of GF(2 m ) Using Symmetric TMVP and Block Recombination Techniques
An 80 MHz Bandwidth and 26.8 dBm OOB IIP3 Transimpedance Amplifier With Improved Nested Feedforward Compensation and Multi-Order Filtering
Digitally Controlled Current-Mode DC-DC Converter IC
A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter
A 80 mW 40 Gb/s Transmitter With Automatic Serializing Time Window Search and 2-tap Pre-Emphasis in 65 nm CMOS Technology
Efficient VLSI Architecture for Soft-Decision Decoding of Reed-Solomon Codes
A 6-bit Current-Steering DAC With Compound Current Cells for Both Communication and Rail-to-Rail Voltage-Source Applications
Robust schur stability with polynomial parameters
Short-term Optimized Spread Spectrum Clock Generator for EMI Reduction in Switching DC/DC Converters
Approximation of complex IIR bandpass filters without arithmetic symmetry
On the generation of higher order chaotic oscillators via passive coupling of two identical or nonidentical sinusoidal oscillators
Corrections to Optimized Waveform Relaxation Methods for Longitudinal Partitioning of Transmission Lines [Aug 09 1732-1743]
Multitone Feedback Through Demodulating Log Detector for Detection of Spurious Emissions in Software Radio
Quasi Rail-to-Rail Very Low-Voltage OPAMP With a Single pMOS Input Differential Pair
A 6.0-13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS
A Self-Powered Power Conditioning IC for Piezoelectric Energy Harvesting From Short-Duration Vibrations
Joint DOA Estimation and Source Signal Tracking With Kalman Filtering and Regularized QRD RLS Algorithm
A CMOS single-chip wireless solution with an adaptive purity-control scheme against ISM-band interferences
Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process
Relaxation Oscillator With Dynamic Comparator and Slope-Boosting Technique
A Charge Balancing 1450 um 2 PNP-Based Thermal Sensor for Dense Thermal Monitoring
Design of a Millimeter-Wave CMOS Radiation Oscillator With an Above-Chip Patch Antenna
Data and Hardware Efficient Design for Convolutional Neural Network
Multi-Rate DEM With Mismatch-Noise Cancellation for DCOs in Digital PLLs
A 7-MHz Integrated Peak-Current-Mode Buck Regulator With a Charge-Recycling Technique
Robust D -Stability for a Class of Complex Singularly Perturbed Systems
A new method for the reduction of crosstalk and echo in multiconductor interconnections
Parallel Hybrid Stochastic-Binary-Based Neural Network Accelerators
Computation of the Area of Memristor Pinched Hysteresis Loop
Computing Timing Jitter From Phase Noise Spectra for Oscillators and Phase-Locked Loops With White and 1/f Noise
A Multichip Pulse-Based Neuromorphic Infrastructure and Its Application to a Model of Orientation Selectivity
A CMOS Low-Dropout Regulator With Current-Mode Feedback Buffer Amplifier
Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement
Novel Solutions of a Delta-Sigma-Based Rectifying Encoder
A Low-Power Continuous-Time Delta-Sigma Modulator Using a Resonant Single Op-Amp Third-Order Loop Filter
Semi-Iterative Analog Turbo Decoding
Exploiting Machine Learning Against On-Chip Power Analysis Attacks: Tradeoffs and Design Considerations
On the Number of System Separations in Electric Power Systems
A Two-Stage Switched-Capacitor Integrator for High Gain Inverter-Like Architectures
Exponentially Fitted Cubature Kalman Filter With Application to Oscillatory Dynamical Systems
Local Robustness of Hopf Bifurcation Stabilization
A Transceiver Front-End for Ultra-Wide-Band Applications
Maximally Flat Filter Functions With the Maximum Number of Transmission Zeros Having Maximal Multiplicity
Extended-Bandwidth Negative Impedance Converters by Nested Networks
XNOR-based double-edge-triggered flip-flop for two-phase pipelines
Behavioral Modeling for Calibration of Pipeline Analog-To-Digital Converters
Unbiased Finite-Memory Digital Phase-Locked Loop
Design of High-Speed Register Files Using SiGe HBT BiCMOS Technology
A 2.3-mW 0.01-mm 2 1.25-GHz Quadrature Signal Corrector With 1.1-ps Error for Mobile DRAM Interface in 65-nm CMOS
On the Remarkable Performance of the Series-Resonance CMOS Oscillator
A Low-Cost High-Speed Neuromorphic Hardware Based on Spiking Neural Network
A 0.3-1.2 V Schottky-Based CMOS ZTC Voltage Reference
Design and Implementation of a Low-Latency Modular Multiplication Algorithm
A Novel Terahertz Ballistic Deflection Transistor Travelling Wave Amplifier System
Compact Mixed-Signal Convolutional Neural Network Using a Single Modular Neuron
Toward Practical Code-Based Signature: Implementing Fast and Compact QC-LDGM Signature Scheme on Embedded Hardware
Area-Time-Power Efficient FFT Architectures Based on Binary-Signed-Digit CORDIC
Signal-Folding for Range-Enhanced Acquisition and Reconstruction
Design of double-sampling ΣΔ modulation A/D converters with bilinear integrators
A Low-Cost VLSI Architecture for Fault-Tolerant Fusion Center in Wireless Sensor Networks
On Sampled-Data Control for Master-Slave Synchronization of Chaotic Lur'e Systems
RF HBT oscillators with low-phase noise and high-power performance utilizing a (λ/4±δ) open-stubs resonator
New Receding Horizon FIR Estimator for Blind Smart Sensing of Velocity via Position Measurements
Learning Separable Dictionaries for Sparse Tensor Representation: An Online Approach
A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector
High-Input and Low-Output Impedance Voltage-Mode Universal Biquadratic Filter Using DDCCs
A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs
Optical Manipulation of Biological Cells With a Robot-Tweezers System: A Stochastic Control Approach
Flow Distribution for Electric Vehicles Under Nodal-Centrality-Based Resource Allocation
Low-Complexity Multiplierless Constant Rotators Based on Combined Coefficient Selection and Shift-and-Add Implementation (CCSSI)
Adaptive Beamforming and Recursive DOA Estimation Using Frequency-Invariant Uniform Concentric Spherical Arrays
Tunable continuous-time bandpass ΣΔ modulators with fractional delays
Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement
Delta-Sigma FDC Based Fractional-N PLLs
Selective State Retention Power Gating Based on Gate-Level Analysis
Observer-Based Fault Estimation for Discrete-Time Nonlinear Systems and Its Application: A Weighted Switching Approach
An All-MOSFET Voltage Reference With -50-dB PSR at 80 MHz for Low-Power SoC Design
Bandwidth Enhancement of On-Chip Transformers Using Negative Capacitance
Charge-Based Distortion Analysis of Nanoscale MOSFETs
A GPU-Accelerated Web-Based Synthesis Tool for CT Sigma-Delta Modulators
High-Efficiency Current-Regulated Charge Pump for a White LED Driver
A 12-Bit 100-MS/s Subrange SAR ADC With a Foreground Offset Tracking Calibration Scheme
(Co)content in Circuits With Memristive Elements
Charge-Controlled Oscillators and Their Application in Frequency Synthesis
A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications
Calibration of DAC Mismatch Errors in ΣΔ ADCs Based on a Sine-Wave Measurement
A Phasor-Based Analysis of Sinusoidal Injection Locking in LC and Ring Oscillators
A 0.6-V Quadrature VCO With Enhanced Swing and Optimized Capacitive Coupling for Phase Noise Reduction
Optically-Clocked Instruction Set Extensions for High Efficiency Embedded Processors
Finite-Time Consensus for Second-Order Multi-Agent Systems With Input Saturation
Ultra-Low-Power Error Correction Circuits: Technology Scaling and Sub-V T Operation
High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism
Controllability of Deep-Coupling Dynamical Networks
Guided-Processing Outperforms Duty-Cycling for Energy-Efficient Systems
An On-Sensor Bit-Serial Column-Parallel Processing Architecture for High-Speed Discrete Fourier Transform
Time-Domain Simulation of Nonlinear Circuits Through Implicit Runge-Kutta Methods
A Low-Power Pilot-DAC Based Column Parallel 8b SAR ADC With Forward Error Correction for CMOS Image Sensors
A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors
Secure Path Balanced BDD-Based Pre-Charge Logic for Masking
A General Analytical Tool for the Design of Vibration Energy Harvesters (VEHs) Based on the Mechanical Impedance Concept
A Transmitter Architecture Based on Delta-Sigma Modulation and Switch-Mode Power Amplification
A New Polytopic Approximation Method for Networked Systems With Time-Varying Delay
A 6.4-Gb/s Voltage-Mode Near-Ground Receiver With a One-Tap Data and Edge DFE
H∞ Control for Switched Systems Based on Dynamic Event-Triggered Strategy and Quantization Under State-Dependent Switching
Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters
A Low-Spur and Intrinsically Aligned IL-PLL With Self-Feedback Injection Locked RO and Pseudo-Random Injection Locked Technique
New Mixed-Mode Design Methodology for High-Efficiency Outphasing Chireix Amplifiers
A Verilog Piecewise-Linear Analog Behavior Model for Mixed-Signal Validation
Sample-and-Hold Asynchronous Sigma-Delta Time Encoding Machine
Systematic Analysis of Quadrature VCO With Capacitive Source Degeneration Coupling and Spontaneous Transconductance Matching Techniques
Power-Efficient VLSI Realization of a Complex FSM for H.264/AVC Bitstream Parsing
Self-Biased Logarithmic Photoreceptor With Low Settling Time
An Efficient Control Point Insertion Technique for Leakage Reduction of Scaled CMOS Circuits
High-Throughput Digit-Level Systolic Multiplier Over GF(2 m ) Based on Irreducible Trinomials
A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator
A spur-reduction technique for a 5-GHz frequency synthesizer
Global robust stability analysis of neural networks with multiple time delays
Reducing the Power Consumption of Fault Tolerant Registers Through Hybrid Protection
Topology Derivation and Analysis of Integrated Multiple Output Isolated DC-DC Converters With Stacked Configuration for Low-Cost Applications
A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read and Write Stability
Design of QCA-Serial Parallel Multiplier (QSPM) With Energy Dissipation Analysis
Progress update and a look ahead
Prediction of the Spectrum of a Digital Delta-Sigma Modulator Followed by a Polynomial Nonlinearity
A 2.4-GHz Extended-Range Type-I SigmaDelta Fractional-N Synthesizer With 1.8-MHz Loop Bandwidth and -110-dBc/Hz Phase Noise
Tracking Analysis of Gaussian Kernel Signed Error Algorithm for Time-Variant Nonlinear Systems
A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique
(4+2 log n)ΔG Parallel Prefix Modulo-(2 n -3) Adder via Double Representation of Residues in [0, 2]
Implementation of a pixel-level snake algorithm on a CNNUM-based chip set architecture
An Efficient Multirate LDPC-CC Decoder With a Layered Decoding Algorithm for the IEEE 1901 Standard
Semi-global stabilization of a class of uncertain nonlinear systems by linear output feedback
A Low-Power, Process-and- Temperature- Compensated Ring Oscillator With Addition-Based Current Source
An Analog-Node Model for VHDL-Based Simulation of RF Integrated Circuits
Bitstream-Driven Built-In Characterization for Analog and Mixed-Signal Embedded Circuits
An efficient ΔΣ ADC architecture for low oversampling ratios
Low-Power Widely Tunable Gm-C Filter Employing an Adaptive DC-blocking, Triode-Biased MOSFET Transconductor
A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver With Phase-Difference-Modulation Signaling for Highly Reflective Interconnects
A New Cost-Aware Sensitivity-Driven Algorithm for the Design of FIR Filters
Cort-X II: The Low-Power Element Design for a Dynamic Neural Network
A 2.5-GHz eight-phase VCO in SiGe BiCMOS technology
Delta-Sigma Encoder for Low-Power Wireless Bio-Sensors Using Ultrawideband Impulse Radio
Electromechanical-Filter-Based Bandpass Sigma-Delta Modulator
Minimax Design of IIR Digital Filters Using SDP Relaxation Technique
Very Sensitive Low-Noise Active-Reset CMOS Image Sensor With In-Pixel ADC
A 2.2 mW, 40 dB Automatic Gain Controllable Low Noise Amplifier for FM Receiver
A Two-Stage ADC Architecture With VCO-Based Second Stage
Noise and Sensitivity in RF Envelope Detection Receivers
A Calibration Technique for Pipelined ADCs Using Self-Measurement and Histogram-Based Test Methods
A High Efficiency FLL-Assisted Current-Controlled DC-DC Converter Over Light-Loaded Range
A 1.2 V 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN
A High-Performance Scalable Shared-Memory SVD Processor Architecture Based on Jacobi Algorithm and Batcher's Sorting Network
On the Modeling and Linearization of a Concurrent Dual-Band Transmitter Exhibiting Nonlinear Distortion and Hardware Impairments
Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits
Analysis of Errors in a Comparator-Based Switched-Capacitor Biquad Filter
Gene Lethality Detection and Characterization via Topological Analysis of Regulatory Networks
A Single-Stage LED Driver With High-Performance Primary-Side-Regulated Characteristic
1/f noise synthesis model in discrete-time for circuit simulation
Subthreshold Operation of a Monolithically Integrated Strained-Si Current Mirror at Low Temperatures
An Efficient Polarity Detection Technique for Thermoelectric Harvester in L-based Converters
Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies
180-nm 85%-Efficient Inductively Coupled Switched Resonant Half-Bridge Power Receiver
A Chaotic Peak Current-Mode Boost Converter for EMI Reduction and Ripple Suppression
Observer Design for Discrete-Time Nonlinear Systems Using the Stability Radii Theory
An 8-Channel Varactor-Less 28-GHz Front End With 7-Bit Resolution 340° RTPS for 5G RF Beamformers
Boosted CMOS APS Pixel Readout for Ultra Low-Voltage and Low-Power Operation
Improved Analog Filter Design by Random Search
A Low Phase Noise, High Phase Accuracy Quadrature LC-VCO With Dual-Tail Current Biasing to Insert Reconfigurable Phase Delay
Advanced Quenching Techniques for Super-Regenerative Radio Receivers
A Low-Jitter Spread Spectrum Clock Generator Using FDMP
Continuous-Time Time-Stretched Analog-to-Digital Converter Array Implemented Using Virtual Time Gating
Single-electron tunneling transistor implementation of periodic symmetric functions
A 1.15 TOPS/W Energy-Efficient Capsule Network Accelerator for Real-Time 3D Point Cloud Segmentation in Mobile Environment
A Wide-Range Low-Power PLL-Based PI Multiphase Generator Using an Adaptive Frequency Tracking Technique
De-Correlated Improved Adaptive Exponential FLAF-Based Nonlinear Adaptive Feedback Cancellation for Hearing Aids
On Stability of a Class of Switched Nonlinear Systems Subject to Random Disturbances
Formal Synthesis of Circuits With Minimum Noise Figure Using Linear Matrix Inequalities
A Zero Voltage Switching Topology for Non-Inverting Buck-Boost Converter
A Dynamic Random Graph Model for Diameter-Constrained Topologies in Networked Systems
A New Nonlinear Global Placement for FPGAs: The Chaotic Place
A Multigigahertz Multimodulus Frequency Divider in 90-nm CMOS
A New Power Combining and Outphasing Modulation System for High-Efficiency Power Amplification
A Transient-Enhanced Output-Capacitorless LDO With Fast Local Loop and Overshoot Detection
Efficient Mutually Orthogonal Golay Complementary Set-Based Zero-Correlation Zone Sequence Set Correlator
A High-Speed Successive-Cancellation Decoder for Polar Codes Using Approximate Computing
A wavelet view of small-world networks
Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing
An Energy-Efficient Hierarchical Architecture for Time-Interleaved SAR ADC
Analysis and Implementation of a 0.9-V Voltage-Controlled Oscillator With Low Phase Noise and Low Power Dissipation
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement
Charge-Withheld Converter-Reshuffling: A Countermeasure Against Power Analysis Attacks
Digital Predistortion Using Adaptive Basis Functions
Design Considerations for Traveling-Wave Modulator-Based CMOS Photonic Transmitters
A P&O MPPT With a Novel Analog Power-Detector for WSNs Applications
Generalized WLS Method for Designing All-Pass Variable Fractional-Delay Digital Filters
OTA linearity enhancement technique for high frequency applications with IM3 below -65 dB
An online cellular probabilistic self-organizing map for static and dynamic data sets
Finite-Time Containment Control for Second-Order Multiagent Systems Under Directed Topology
Digital-to-Time Synthesizers: Separating Delay Line Error Spurs and Quantization Error Spurs
Analysis of Functional Oxide based Selectors for Cross-Point Memories
Low-Voltage digitally controlled fully differential current conveyor
A Circuit-Based Learning Architecture for Multilayer Neural Networks With Memristor Bridge Synapses
A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process
An FPGA-Based Cloud System for Massive ECG Data Analysis
An Electronically Fine-Tunable Multi-Input-Single-Output Universal Filter
Current Feedback Linearization Applied to Oscillator Based ADCs
Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique
Guest Editorial Special Section on Blind Signal Processing and Its Applications
Realizability of Fractional-Order Impedances by Passive Electrical Networks Composed of a Fractional Capacitor and RLC Components
Enhancing Pinning Controllability of Complex Networks Through Link Rewiring
Bandwidth Enhancement With Low Group-Delay Variation for a 40-Gb/s Transimpedance Amplifier
Neural Network for Solving Constrained Convex Optimization Problems With Global Attractivity
A 60 GHz Drain-Source Neutralized Wideband Linear Power Amplifier in 28 nm CMOS
Laser Diode Current Driver With (1-t/T) -1 Time Dependence in 0.35-µm BiCMOS Technology for Quantum Random Number Generators
Power Extracted From Piezoelectric Harvesters Driven by Non-Sinusoidal Vibrations
CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction
A New Hand-Held Microsystem Architecture for Biological Analysis
8fJ/Step Bandpass ADC With Digitally Assisted NTF Re-Configuration
Filtering for bimodal systems: the case of unknown switching statistics
Low-Density Codes Based on Chaotic Systems for Simple Encoding
A Compact Rail-to-Rail Class-AB CMOS Buffer With Slew-Rate Enhancement
A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission
MOS Translinear Principle for All Inversion Levels
A Generic Nano-Watt Power Fully Tunable 1-D Gaussian Kernel Circuit for Artificial Neural Network
Using the weak inversion region to optimize input stage design of CMOS op amps
Modeling Random Clock Jitter Effect of High-Speed Current-Steering NRZ and RZ DAC
Analysis and Design of Regenerative Comparators for Low Offset and Noise