yusuke1997/dblp-id-title huggingface dataset:
Prescribed Performance Fuzzy Adaptive Output Feedback Control for Nonlinear MIMO Systems in a Finite Time
Fuzzy neural network in case-based diagnostic system
Possibilistic Fuzzy Linear Temporal Logic and Its Model Checking
Learning Large-Scale Fuzzy Cognitive Maps Based on Compressed Sensing and Application in Reconstructing Gene Regulatory Networks
Bias-Corrected Intuitionistic Fuzzy C-Means With Spatial Neighborhood Information Approach for Human Brain MRI Image Segmentation
A PC-based evaluation and control system for gas-liquid chromatography
Interpolation in the eXtended Classifier System: An architectural perspective
Lifetime improvement through adaptive reconfiguration for nonvolatile FPGAs
A rotating laser range finder and attached data interpretation for use in an autonomous mobile robot
Strategies for scheduling optional tasks in intelligent real-time environments
Analysis of large ATM switches using a platform-independent simulation environment
Dynamic-weighted simplex strategy for learning enabled cyber physical systems
Analysis of failure data collected from a TMR microprocessor controller
Thermal-aware global real-time scheduling and analysis on multicore systems
On hardware-trojan-assisted power budgeting system attack targeting many core systems
Parallel processing: Array processors I
On the performance of multicomputer interconnection networks
An approach to the evaluation of microcomputer operating systems with respect to real-time issues
A mixed implementation of a real-time system
Automated normalization tool
An intelligent disk controller - A processor system for file management and querry functions
Resource-efficient routing and scheduling of time-constrained streaming communication on networks-on-chip
Expressing survivability considerations in mixed-criticality scheduling theory
Scheduling and analysis of real-time task graph models with nested locks
Energy optimization for deadline-constrained parallel applications on multi-ECU embedded systems
Hardware architecture for voxelization-based volume rendering of unstructured grids
A new cache architecture based on temporal and spatial locality
Data-driven barrier certificate generation using deep learning and symbolic regression
A vectorized superminicomputer, VAX-11/700 with vector processing
Genetic algorithm for embedding a complete graph in a hypercube with a VLSI application
Lists processing for artificial intelligence applications
ALERT: A lightweight defense mechanism for enhancing DNN robustness against T-BFA
Data clustering on hybrid classical-quantum NISQ architecture with generative-based variational and parallel algorithms
Exploiting intra-chip locality for multi-chip GPUs via two-level shared L1 cache
L-Heron: An open-source load-aware online scheduler for Apache Heron
Integration of a hardware module for tracing local variables in real-time software
Energy-efficient acceleration of convolutional neural networks using computation reuse
Algorithms and tools for VLSI design
Evaluation of a sparc architecture with harvard bus and branch target cache
A generic hardware architecture to support the system level synthesis of digital systems
Software quality management
An associative string processor architecture for parallel processing applications
Efficient CUDA stream management for multi-DNN real-time inference on embedded GPUs
Maintaining cache coherency in a multisystem data sharing environment
Hierarchical star: a new two level interconnection network
Initial evaluation of a parallel associative processor IXM2
Rapid functional modelling and simulation of coarse grained reconfigurable array architectures
Enabling PoCL-based runtime frameworks on the HSA for OpenCL 2.0 support
Polychronous modeling, analysis, verification and simulation for timed software architectures
DS 2 IS: Dictionary-based segmented inversion scheme for low power dynamic bus design
Enhanced-functionality multipliers
dMCLAEKS: Pairing-free designated-tester multi-recipient certificateless authenticated encryption with keyword search for concealing search patterns
Efficient Reservation-based Fault-Tolerant Scheduling for IEEE 802.1Qbv Time-Sensitive Networking
A schema version model for complex objects in object-oriented databases
ISG-SLAS: Secure and lightweight authentication and key agreement scheme for industrial smart grid using fuzzy extractor
Power saving and fault-tolerance in real-time critical embedded systems
A system for estimation of numerical stability for matrix operations in systolic arrays
Two-dimensional parallel system diagnostic
TrustDedup: Secure data deduplication for IoT based on end-edge-cloud collaboration
Knowledge bases for digital circuit understanding
Federated time persistency in intermittently powered IoT systems
On the use of process migration in distributed systems
IRO: Integrity-Reliability enhanced Ring ORAM
Joint compressing and partitioning of CNNs for fast edge-cloud collaborative intelligence for IoT
A business process monitor for a mobile phone recharging system
A storage structure for nested relations using signatures
Vertically-partitioned parallel signature file method
Web computing framework
IoT Manager: An open-source IoT framework for smart cities
Distributed simulation of computer networks
μScope: Evaluating storage stack robustness against SSD's latency variation
Circuit yield optimization by analyzing performance statistics
Race-to-halt energy saving strategies
Model-based platform-specific co-design methodology for dynamically partially reconfigurable systems with hardware virtualization and preemption
A survey on Attribute-Based Signatures
ENREM: An efficient NFA-based regular expression matching engine on reconfigurable hardware for NIDS
TSB: A DVS algorithm with quick response for general purpose operating systems
A flexible transputer network for numerical applications
Dynamic protocol configuration for multimedia networks
Performance evaluation in image processing with GAPP array processor
Design and analysis of static memory management policies for CC-NUMA multiprocessors
Optimizing data permutations in structured loads/stores translation and SIMD register mapping for a cross-ISA dynamic binary translator
Performance of simultaneous multithreaded multimedia-enhanced processors for MPEG-2 video decompression
I DDQ data analysis using neighbor current ratios
A parallel processor for the dynamic characterization of A/D converters
VFBoost-MO: Scable vertical federated gradient boosting decision tree for multi-class problem
Product-closed networks
Maximizing reliability of distributed computing system with task allocation using simple genetic algorithm
TriOS operating system
Improving in-memory file system reading performance by fine-grained user-space cache mechanisms
Scale-CIM: Precision-scalable computing-in-memory for energy-efficient quantized neural networks
Parallel algorithms for SIMD computers
Authentication Techniques and Methodologies used in Wireless Body Area Networks
Toy-IoT-Oriented data-driven CDN performance evaluation model with deep learning
A new NAND-type flash memory package with smart buffer system for spatial and temporal localities
Toward automated support for object-oriented modelling
Using Xen and KVM as real-time hypervisors
Clustering scheduling for hardware tasks in reconfigurable computing systems
A reliability enhanced video storage architecture in hybrid SLC/MLC NAND flash memory
Accelerating DNNs from local to virtualized FPGA in the Cloud: A survey of trends
CamoDroid: An Android application analysis environment resilient against sandbox evasion
Theory and application of non-group cellular automata for message authentication
Memory testing in a massively parallel machine
Studies of the SEMATECH IDDq test data
Introduction to the special issue on "Embedded Artificial Intelligence and Smart Computing"
A dual-index Boolean retrieval scheme with dynamic and revocable attribute-based policies
An abstract description generator for the reliability analysis in the design of real time systems
Hydra: Hybrid-model federated learning for human activity recognition on heterogeneous devices
A model for assessing the performance of a local area network employing Technical Office Protocol (TOP) as part of map/top network in a Computer Integrated Manufacturing (CIM) research project, for the transmission of real time interactive speech
Differentially private stochastic gradient descent via compression and memorization
Input/mapping precision controllable digital CIM with adaptive adder tree architecture for flexible DNN inference
FastHand: Fast monocular hand pose estimation on embedded systems
Log-time delay consideration on mesh with multiple buses
Early prediction of reliability and availability of combined hardware-software systems based on functional failures
On an efficient VLSI architecture for the multirate additive synthesis of musical tones
An architectural application framework for evolving distributed systems
Dynamic cohesion measures for object-oriented software
SHC-DP: Software-hardware collaborative in-network data placement for hybrid storage systems
Model-based documentation of dynamicity constraints for collaborative cyber-physical system architectures: Findings from an industrial case study
An automotive case study on the limits of approximation for object detection
RPC-MPKET: Location-based revocable encryption with ciphertext equality test for multi-user Internet of Vehicles
General decomposition of incompletely specified sequential machines with multi-state behavior realization
Building a dependable system from a legacy application with CORBA
Multiprocessor flight data acquisition system
MPPNL - A Petri Net based Language to design fine-grained parallel machines and debug their software
Special Issue on: Design Automation for Embedded Ubiquitous Computing Systems (DAEUCS)
EDF scheduling for distributed systems built upon the IEEE 802.1AS clock - A theoretical-practical comparison
SSBAS-FA: A secure sealed-bid e-auction scheme with fair arbitration based on time-released blockchain
An improved lightweight and privacy preserving authentication scheme for smart grid communication
Effectiveness of bridging in multiprotocol LANS
DeMas: An efficient method for malicious samples detection and mitigation in cloud-based systems
On the formal specification and verification of digital circuits
Functional decomposition with an efficient input support selection for sub-functions based on information relationship measures
From specification to implementation of a real-time system
The design and utility of the ML-RSIM system simulator
Parallelized sub-resource loading for web rendering engine
Memory-processor co-scheduling of AECR-DAG real-time tasks on partitioned multicore platforms with scratchpads
Optimizing data structures at the modeling level in embedded multimedia
Virtuoso: A virtual single processor programming system for distributed real-time applications
Embedded software debugging using virtual filesystem abstractions
PROMIDS: A PROtotype multi-rIng data flow system for functional programming languages
Applying inherent capabilities of quantum-dot cellular automata to design: D flip-flop case study
Using a role scheme to derive software project metrics
Probability based timing verification
Approximate prefix coding for system-on-a-chip programs
Guest editorial: Workshop on Reconfigurable Computing
Specification and coordination of long-running design activities for CAD environments
Timing analysis of processing chains with data refreshing in ROS 2
Cost and makespan scheduling of workflows in clouds using list multiobjective optimization technique
A model for service-oriented communication systems
Logic controllers design methods using advanced PLDS
Customization methodology for implementation of streaming aggregation in embedded systems
A naive approach to software structure validation
The role of languages in the design-trajectory
Application machines: An approach to realizing understandable systems
Towards Efficient On-Chip Communication: A Survey on Silicon Nanophotonics and Optical Networks-on-Chip
Performance analysis of a multiprocessor machine based on data flow principles
High-performance hard-input LDPC decoding on multi-core devices for optical space links
Design considerations on a VLSI Prolog interpreter
Time-predictable task-to-thread mapping in multi-core processors
DEOS - A dynamically extendible object-oriented system
Post-synthesis back-annotation of timing information in behavioral VHDL
BoostTM: Best-effort performance guarantees in best-effort hardware transactional memory for distributed manycore architectures
Real time Cepstrum computation based on an Advanced CORDIC processor
Hot spot analysis within the FortPort migration tool for parallel platforms
Acceleration of circuit simulation on a parallel transputer workstation
PCTE - The kernel of software engineering environments
ompTG: From OpenMP Programs to Task Graphs
Specific data structure intended for the implementation of high level ISO standards: Associated algorithms and dedicated hardware
Exact and efficient advanced loop interchange
When foresight pruning meets zeroth-order optimization: Efficient federated learning for low-memory devices
Deriving protocol specifications from service specifications including multirendezvous
The design of a multiparadigm programming language: I
Modelling real-time applications based on resource reservations
ZNS-Cleaner: Enhancing lifespan by reducing empty erase in ZNS SSDs
Reformulating the direct convolution for high-performance deep learning inference on ARM processors
A unified execution model for multiple computation models of streaming applications on a composable MPSoC
Multi-client functional encryption for set intersection with non-monotonic access structures in federated learning
Facilitating composition and increasing object reusability by means of an event-driven object-oriented development
Minimizing accumulative memory load cost on multi-core DSPs with multi-level memory
An approach to fault-tolerant allocation of concurrent communicating processes in multiprocessor architectures and hardware dimensioning
EMVS: Embedded Multi Vector-core System
A new magnitude function for fast numbers comparison in the residue number system
A RISC prolog machine architecture
StorStack: A full-stack design for in-storage file systems
Strategies for solving the Boolean satisfiability problem using binary decision diagrams
Session F2: Parallel architectures I
Limited carry-in technique for real-time multi-core scheduling
Parallel Applications
An efficient mapping of Boltzmann machine computations onto distributed-memory multiprocessors
Fault-tolerant message routing in the extended hypercube
Architectural design of an RISC processor for programmable logic controllers
An intelligent assistive driving solution based on smartphone for power wheelchair mobility
Efficient approaches for constructing a massively parallel processing system
Comprehensible and dependable self-learning self-adaptive systems
Semantic Attribute-Based Access Control: A review on current status and future perspectives
ASI Instrumentation
Parallel object system support on transputer-based architectures
Computing models in designing
DReP: Deep ReLU pruning for fast private inference
STAFF: A flash driver algorithm minimizing block erasures
Two-level pipelined systolic arrays for matrix-vector multiplication
The ClassiC programming language and design of synchronous concurrent object oriented languages
An accurate and fast CSMA/CD simulator
Menu and graphic driven human interfaces for high level debuggers
Blockchain-enabled multi-authorization and multi-cloud attribute-based keyword search over encrypted data in the cloud
Adaptive subflow allocation for multipath data transmission in mobile edge networks
Untraceable blockchain-assisted authentication and key exchange in medical consortiums
Techniques to increase the schedulable utilization of cache-based preemptive real-time systems
Quality-driven design in the system-on-a-chip era: Why and how?
Quantum-safe identity-based designated verifier signature for BIoMT
Lightweight batch authentication and key agreement scheme for IIoT gateways
Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks
Managing safety and mission completion via collective run-time adaptation
MPSoC based on Transport Triggered Architecture for baseband processing of an LTE receiver
Checkpointing and recovery in a pipeline of transputers
Lightweight multi-layered de-identification architecture: Secure client selection in federated learning
TAO: A hierarchical design representation for high level synthesis of hardware systems
Optimization of a Time-to-Digital Converter and a coincidence map algorithm for TOF-PET applications
Attacking vision-based perception in end-to-end autonomous driving models
MAPPS: A VLSI multiprocessor for the execution of production system programs
A transformation strategy for process partitioning in hierarchical concurrent process networks
Efficient use of parallel libraries on heterogeneous Networks of Workstations
A language coprocessor for the interpretation of threaded coded
A sorting procesxsor for microcomputers
The meaning and role of value in scheduling flexible real-time systems
Video transmission adaptation on mobile devices
A selective protection scheme of applications using asymmetrically reliable caches
Measuring and simulating an 802.3 CSMA/CD LAN
A three-tier middleware architecture supporting bidirectional location tracking of numerous mobile nodes under legacy WSN environment
Analysis of multithreaded architectures - A case study
Reliability of disk file organisation for microcomputers
A graphical simulator for programmable logic controllers based on Petri nets
Using MAST for modeling and response-time analysis of real-time applications with GPUs
Lightweight and anonymous certificateless signcryption scheme for multi-receiver
Hardware security platform for multicast communications
Optimization techniques in building expert systems
The performance evaluation of a knowledge-based information retrieval system
Characteristics and requirements of semi-custom design tools
TRA-PS: Accountable data Pub/Sub service with fast and fine-grained controllable subscription
Blockchain-assisted handover authentication for intelligent telehealth in multi-server edge computing environment
A new indexing scheme supporting multi-attribute database applications: MAX
The COIN model for concurrent computation and its implementation
Towards fault adaptive routing in metasurface controller networks
Real-time scheduling for multi-object tracking tasks in regions with different criticalities
A system architecture for high-speed deep packet inspection in signature-based network intrusion prevention
Two versions of architectures for dynamic implied addressing mode
A scheduling algorithm for autonomous driving tasks on mobile edge computing servers
Supporting logical execution time in multi-core POSIX systems
A multi-transputer based audio computer with MIDI and analogue interfaces
Data-driven power modeling and monitoring via hardware performance counter tracking
Improving live migration efficiency in QEMU: An eBPF-based paravirtualized approach
A VLSI - CAD system for efficient design of CMOS/390 processors
VIDGCN: Embracing input data diversity with a configurable graph convolutional network accelerator
Conditional execution: an approach for eliminating the basic block barriers
On the architectural support for logical machine systems
Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs
Design of a large-scale Gbit/s MAN using a cyclic reservation-based MAC protocol
Workload-aware harmonic partitioned scheduling for fixed-priority probabilistic real-time tasks on multiprocessors
Special issue on nature-inspired applications and systems
GNNBoost: Accelerating sampling-based GNN training on large scale graph by optimizing data preparation
Reputation-based service provisioning for vehicular fog computing
Computational logic unit for a microprogrammed data acquisition system: an evaluation prototype
A contract-based semantics and refinement for hybrid Simulink block diagrams
A scala based framework for developing acceleration systems with FPGAs
Synchronous VS asynchronous reconfiguration of Memory Bandwidth Management Schemes: A comparative analysis
Evaluating the energy consumption and the silicon area of on-chip interconnect architectures
Connectionist model description: A case study
ArchNet: A data hiding design for distributed machine learning systems
Empirical model-based performance prediction for application mapping on multicore architectures
Specification-based program slicing and its applications
A general real-time decoder based on AMD 2900 devices
Dependable flight control system by data diversity and self-checking components
Applications IO profiling and analysis for smart devices
A VLSI architecture for 3-D self-organizing map based color quantization and its FPGA implementation
ProckStore: An NDP-empowered key-value store with asynchronous and multi-threaded compaction scheme for optimized performance
A flexible architecture for real-time speech recognition
Content-based image retrieval algorithm acceleration in a low-cost reconfigurable FPGA cluster
A profile-guided synergistic computation framework for Halide
vSimilar: A high-adaptive VM scheduler based on the CPU pool mechanism
Branch target buffers: WCET analysis framework and timing predictability
Rounding error in the computation of opposite sign floating point number parametric addition: a case study
URPR-1: A single-chip VLIW architecture
OpenMP-based parallelization on an MPCore multiprocessor platform - A performance and power analysis
Support for partial run-time reconfiguration of platform FPGAs
Design-time methodology for optimizing mixed-precision CPU architectures on FPGA
A global approach to improve conditional hardware reuse in high-level synthesis
DNN pruning with principal component analysis and connection importance estimation
Blockchain-based privacy-preserving public key searchable encryption with strong traceability
A transputer-based extended hypercube
Coevolving functions in genetic programming
A heuristic algorithm for real-time application allocation to multimicrocomputer
NETPLAN: A rule based system to design packet switching data networks
Run-time mapping algorithm for dynamic workloads using association rule mining
Has Europe learnt enough?
Real-time embedded software for multi-core platforms
Accurate power modeling of modern mobile application processors
Efficient two-party SM2 signing protocol based on secret sharing
A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port
Parallel custom instruction identification for extensible processors
Neural networks definition algorithm
Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems
An experiment in tool integration: The DDBG parallel and distributed debugger
Mitigating service-oriented attacks using context-based trust for smart cities in IoT networks
Blockchain-assisted multi-keyword fuzzy search encryption for secure data sharing
BUAKA-CS: Blockchain-enabled user authentication and key agreement scheme for crowdsourcing system
FPGA implementations of elliptic curve cryptography and Tate pairing over a binary field
Using transputers in a robot programming and control system
Computer modelling of single sludge systems for the computer aided design and control of activated sludge processes
A CP-ABE-based access control scheme with cryptographic reverse firewall for IoV
Bridging the gap between formal verification and schedulability analysis: The case of robotics
Gradient descent algorithm for the optimization of fixed priorities in real-time systems
ESampler: Boosting sampling of satisfying assignments for Boolean formulas via derivation
A monitoring-aware network-on-chip design flow
Guest editorial: Special issue on modeling, verification and testing of dependable critical systems
Guidance for optimization-based synthesis tools
IRPL: An energy efficient routing protocol for wireless sensor networks