yusuke1997/dblp-id-title huggingface dataset:
Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches
Modeling impact ionization in a BJT by means of spherical harmonics expansion of the Boltzmann transport equation
Redundancy identification and removal in combinational circuits
Application-specific clustered VLIW datapaths: early exploration on a parameterized design space
Formulation of the Obreshkov-Based Transient Circuit Simulator in the Presence of Nonlinear Memory Elements
Optimum positioning of interleaved repeaters in bidirectional buses
Performance and power effectiveness in embedded processors customizable partitioned caches
Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers
Compressible area fill synthesis
The crossing distribution problem [IC layout]
NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators With 3-D Stacked-DRAM
A Survey of Automated Techniques for Formal Software Verification
Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic Biochips
Simulation of spatial fault distributions for integrated circuit yield estimations
A New Paradigm for FPGA Placement Without Explicit Packing
FEATS: Framework for Explorative Analog Topology Synthesis
Permissible functions for multioutput components in combinational logic optimization
The Role of Semiconductor Device Diameter and Energy-Band Bending in Convergence of Picard Iteration for Gummel's Map
A new ATPG technique (MultiDetect) for testing of analog macros in mixed-signal circuits
Optimizing Data Placement for Hybrid SRAM+Racetrack Memory SPM in Embedded Systems
A Reliability-Aware Address Mapping Strategy for NAND Flash Memory Storage Systems
Approximation-Aware Task Deployment on Heterogeneous Multicore Platforms With DVFS
Optimizing Worst Case Data Freshness in RF-Powered Networked Embedded Systems
A Resistance Calculation Algorithm and Its Application to Circuit Extraction
ReD: A Reliable and Deadlock-Free Routing for 2.5-D Chiplet-Based Interposer Networks
Stochastic Guarantees for Adaptive Energy Harvesting Systems
Pin-3D: Effective Physical Design Methodology for Multidie Co-Optimization in Monolithic 3-D ICs
An efficient nonquasi-static diode model for circuit simulation
Software Workarounds for Hardware Errors: Instruction Patch Synthesis
SaaP: Rearchitect SoC-as-a-Processor to Orchestrate Hardware Heterogeneity
elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs
A Comprehensive Memory Management Framework for CPU-FPGA Heterogenous SoCs
Power- and Endurance-Aware Neural Network Training in NVM-Based Platforms
Workload-Aware Adaptive Power Delivery System Management for Many-Core Processors
Testing Resistive Opens and Bridging Faults Through Pulse Propagation
3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability
Using functional fault simulation and the difference fault model to estimate implementation fault coverage
GreenCool: An Energy-Efficient Liquid Cooling Design Technique for 3-D MPSoCs Via Channel Width Modulation
Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators
Modeling phosphorus diffusion in three dimensions
PowerSyn: A Logic Synthesis Framework With Early Power Optimization
A Switch-Level Timing Verifier for Digital MOS VLSI
A cell-based approach to performance optimization of fanout-free circuits
SAFE: A Scalable Homomorphic Encryption Accelerator for Vertical Federated Learning
A Reliable Model Parameter Extraction Method Applied to AlGaN/GaN HEMTs
SPICE Modeling in Verilog-A for Photo-Response in UTC-Photodiodes Targeting Beyond-5G Circuit Design
Design and application of an optimizing XROM silicon compiler
A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits
Empirical and theoretical studies of the simulated evolution method applied to standard cell placement
An interpolated flux scheme for cellular automaton device simulation
Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm
A comprehensive approach to the partial scan problem using implicitstate enumeration
Simulation-Based Diagnostic Model for Automatic Testability Analysis of Analog Circuits
Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACs
Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping
Compositional Probabilistic Analysis of Temporal Properties Over Stochastic Detectors
A Hierarchical Timing Simulation Model
MONTE: A Program to Simulate the Heterojunction Devices in Two Dimensions
Caphammer: Exploiting Capacitor Vulnerability of Energy Harvesting Systems
Retiming-based timing analysis with an application to mincut-based global placement
Exact algorithms for output encoding, state assignment, and four-level Boolean minimization
Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement
Simultaneous Guiding Template Optimization and Redundant via Insertion for Directed Self-Assembly
NPU Thermal Management
Scheduling and control generation with environmental constraints based on automata representations
A method for pseudo-exhaustive test pattern generation
Indirect test architecture for SoC testing
Provably Fast and Near-Optimum Gate Sizing
Logic Partitioning for Minimizing Gate Arrays
Statistical Sampling-Based Parametric Analysis of Power Grids
An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis
Compact Models for Memristors Based on Charge-Flux Constitutive Relationships
From logic to symbolic layout for gate matrix
Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS
Delay-fault diagnosis using timing information
Searching for Bugs Using Probabilistic Suspect Implications
Functional vector generation for HDL models using linearprogramming and Boolean satisfiability
MaskedHLS: Domain-Specific High-Level Synthesis of Masked Cryptographic Designs
A novel hierarchical approach for proximity effect correction in electron beam lithography
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core Processors
Fixing Design Errors With Counterexamples and Resynthesis
Fast Mask Optimization Under Process Variation Using Guided Local Search on Quadratic Programming
Path-delay-fault testable nonscan sequential circuits
Temperature dependence modeling for MOS VLSI circuit simulation
Correction to "Boundary single-layer routing with movable terminals"
Obstacle-Avoiding Open-Net Connector With Precise Shortest Distance Estimation
From C/C++ Code to High-Performance Dataflow Circuits
Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation
Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture
Optimal joint module-selection and retiming with carry-save representation
Efficient handling of operating range and manufacturing linevariations in analog cell synthesis
Robust Identification of Thermal Models for In-Production High-Performance-Computing Clusters With Machine Learning-Based Data Selection
Extraction and use of neural network models in automated synthesis of operational amplifiers
PauliForest: Connectivity-Aware Synthesis and Pauli-Oriented Qubit Mapping for Near-Term Quantum Simulation
Statistical timing analysis under spatial correlations
VISTA-user interface, task level, and tool integration
Space compaction for multiple-output circuits
A Virtualization-Assisted Full-System Simulation Approach for the Verification of System Intercomponent Interactions
Overcome the GC-Induced Performance Variability in SSD-Based RAIDs With Request Redirection
Arithmetic transforms for compositions of sequential and imprecise datapaths
Estimating the Number of Extra Tests During Iterative Test Generation for Single-Cycle Gate-Exhaustive Faults
EveCheck: An Event-Driven, Scalable Algorithm for Coherent Shared Memory Verification
Automating the Design of Asynchronous Logic Control for AMS Electronics
Model-adaptable MOSFET parameter-extraction method using an intermediate model
Therminator 2: A Fast Thermal Simulator for Portable Devices
Smaller Together: Groupwise Encoding of Sparse Neural Networks
Adaptive Granularity Progressive LDPC Decoding for NAND Flash Memory
Memristor-Based Attention Network for Online Real-Time Object Tracking
Modeling and Optimization Techniques for Yield-Aware SRAM Post-Silicon Tuning
Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs
SoBS-X: Squeeze-Out Bit Sparsity for ReRAM-Crossbar-Based Neural Network Accelerator
Semi-Tensor Product-Based Exact Synthesis for Logic Rewriting
Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning
Skew Management of NBTI Impacted Gated Clock Trees
Timing ECO Optimization Via Bézier Curve Smoothing and Fixability Identification
Memory-Computing Decoupling: A DNN Multitasking Accelerator With Adaptive Data Arrangement
A Fast High-Level Event-Driven Thermal Estimator for Dynamic Thermal Aware Scheduling
A Preconditioned Hierarchical Algorithm for Impedance Extraction of Three-Dimensional Structures With Multiple Dielectrics
An efficient heterogeneous tree multiplexer synthesis technique
On the detectability of CMOS floating gate transistor faults
Single-Layer Routing for VLSI: Analysis and Algorithms
An NoC Simulator That Supports Deflection Routing, GPU/CPU Integration, and Co-Simulation
Concurrent test for digital linear systems
On Input Generators for Cyber-Physical Systems Falsification
An Energy-Efficient Inference Engine for a Configurable ReRAM-Based Neural Network Accelerator
Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits
Crosstalk-Aware Domino-Logic Synthesis
Pushing the Limit of PFA: Enhanced Persistent Fault Analysis on Block Ciphers
Projection-based approaches for model reduction of weakly nonlinear, time-varying systems
Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications
Multilevel circuit clustering for delay minimization
Floating Random Walk Capacitance Solver Tackling Conformal Dielectric With On-the-Fly Sampling on Eight-Octant Transition Cubes
Parasitic-Aware Common-Centroid Binary-Weighted Capacitor Layout Generation Integrating Placement, Routing, and Unit Capacitor Sizing
On Development of Reliable Machine Learning Systems Based on Machine Error Tolerance of Input Images
FASY: a fuzzy-logic based tool for analog synthesis
A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration
Analytical Eye-Diagram Determination for the Efficient and Accurate Signal Integrity Verification of Single Interconnect Lines
A Formal Approach to Power Optimization in CPSs With Delay-Workload Dependence Awareness
GIRD: A Green IR-Drop Estimation Method
A Partial Page Cache Strategy for NVRAM-Based Storage Devices
A unified MOSFET channel charge model for device modeling in circuit simulation
Mortar-FP8: Morphing the Existing FP32 Infrastructure for High-Performance Deep Learning Acceleration
On the k-layer planar subset and topological via minimization problems
Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification
Model Reduction and Simulation of Nonlinear Circuits via Tensor Decomposition
State-of-Charge Estimation of Supercapacitors in Transiently-Powered Sensor Nodes
NICSLU: An Adaptive Sparse Matrix Solver for Parallel Circuit Simulation
Ripple: A Robust and Effective Routability-Driven Placer
On the acceleration of flow-oriented circuit clustering
Synthesis and Optimization of Multilevel Logic under Timing Constraints
SlackHammer: Logic Synthesis for Graceful Errors Under Frequency Scaling
Comments on 'A module generator for optimized CMOS buffers'
PathDriver+: Enhanced Path-Driven Architecture Design for Flow-Based Microfluidic Biochips
PEPPR-DWS on FPGA: Elevating Universal Parallelism and Precision Through Pulse-Enhanced Push-Relabel and Diffusion Wave Search
Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling
Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths
Optimizing program disturb fault tests using defect-based testing
A Synthesis Tool for CMOS RF Low-Noise Amplifiers
Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains
An improved branch and bound algorithm for exact BDD minimization
Evaluation and optimization of replication algorithms for logic bipartitioning
Interaction semantics of a symbolic layout editor for parameterized modules
A numerical model for two-dimensional transient simulation of amorphous silicon thin-film transistors
Automatic Selection of Process Corner Simulations for Faster Design Verification
A Novel Approach to Design SAR-ADC: Design Partitioning Method
Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks
Reconfiguration of VLSI arrays by covering
DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads
Realization-independent ATPG for designs with unimplemented blocks
Extending the Lifetime of MEDA Biochips by Selective Sensing on Microelectrodes
Re-CATA: Real-Time and Flexible Accelerator Design Framework for On-Device Codec Avatars
Pseudorandom testing for mixed-signal circuits
TEMT: A Transient Electronic-Magnetic-Thermal-Coupled Simulation Framework for STT-MTJs
The efficient solution of integer programs for hierarchical global routing
A small-signal MOSFET model for radio frequency IC applications
Optimizing Energy in Non-Preemptive Mixed-Criticality Scheduling by Exploiting Probabilistic Information
Quantitative Masking Strength: Quantifying the Power Side-Channel Resistance of Software Code
Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs
A Simulation Model for Schottky Diodes in GaAs Integrated Circuits
Sampling in Thermal Simulation of Processors: Measurement, Characterization, and Evaluation
Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories
Efficient simulation of coupled circuit-field problems: generalized Falk method
Manufacturability Enhancement With Dummy via Insertion for DSA-MP Lithography Using Multiple BCP Materials
Techniques for multilayer channel routing
Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization
On squashing hierarchical designs [VLSI]
Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation
DS-LFSR: a BIST TPG for low switching activity
Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications
Verified Train Controllers for the Federal Railroad Administration Train Kinematics Model: Balancing Competing Brake and Track Forces
Microprocessor power estimation using profile-driven program synthesis
Fault simulation of parametric bridging faults in CMOS IC's
SPIRAL+: Efficient Signal-Power Integrity Co-Analysis for Interchiplet Links Validation
A Library for Combinational Circuit Verification Using the HOL Theorem Prover
Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation
Computation of drain and substrate currents in ultra-short-channel nMOSFET's using the hydrodynamic model
Implications of Analytical Investigations About the Semiconductor Equations on Device Modeling Programs
A Fast Exploration Procedure for Analog High-Level Specification Translation
AEM-PCB Reverser: Circuit Schematic Generation in PCB Reverse Engineering Using Reinforcement Learning Based on Aesthetic Evaluation Metric
On the design of fast large fan-in CMOS multiplexers
SeMo: Service-Oriented and Model-Based Software Framework for Cooperating Robots
A Bridge-Based Compression Algorithm for Topological Quantum Circuits
Statistical method for the analysis of interconnects delay insubmicrometer layouts
PYFS-a statistical optimization method for integrated circuit yield enhancement
Schwarz-Christoffel transformation for the simulation of two-dimensional capacitance [VLSI circuits]
A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm
Process compilation of thin film microdevices
Algorithms for an Advanced Fault Simulation System in MOTIS
Determining the steady-state output of nonlinear oscillatory circuits using multiple shooting
Employing Scaled Sigma Sampling for Efficient Estimation of Rare Event Probabilities in the Absence of Input Domain Mapping
Towards Overhead-Free Interface Theory for Compositional Hierarchical Real-Time Systems
A sensitivity-based approach to analyzing signal delay uncertainty of coupled interconnects
Linear Time Electromigration Analysis Based on Physics-Informed Sparse Regression
Efficient Production Binning Using Octree Tessellation in the Alternate Measurements Space
Defect-Aware High-Level Synthesis Targeted at Reconfigurable Nanofabrics
A robust over-the-cell channel router
System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes
DESCNet: Developing Efficient Scratchpad Memories for Capsule Network Hardware
An Offline Method for Designing Adaptive Routing Based on Pressure Model
Integrating LSM Trees With Multichip Flash Translation Layer for Write-Efficient KVSSDs
An approach to construct pre-conditioning matrices for block iteration of linear equations
On Efficient LHS-Based Yield Analysis of Analog Circuits
Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach
NEAT: Nonlinearity Aware Training for Accurate, Energy-Efficient, and Robust Implementation of Neural Networks on 1T-1R Crossbars
A portable parallel algorithm for logic synthesis using transduction
Massively parallel switch-level simulation: a feasibility study
Effective free space management for cut-based placement via analytical constraint generation
Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection
Fast Aging-Aware Timing Analysis Framework With Temporal-Spatial Graph Neural Network
3D-ICE 3.0: Efficient Nonlinear MPSoC Thermal Simulation With Pluggable Heat Sink Models
A Modified Newton Method for the Steady-State Analysis
PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction
Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles
AirNN: A Featherweight Framework for Dynamic Input-Dependent Approximation of CNNs
Accounting thermal noise in mathematical models of quasi-homogeneous regions in silicon devices
An MILP-Based Performance Analysis Technique for Non-Preemptive Multitasking MPSoC
Escape Routing for Staggered-Pin-Array PCBs
Coupling algorithms for mixed-level circuit and device simulation
Numerical Conformal Mapping for Treatment of Geometry Problems in Process Simulation
Design and Analysis of Optimization Method for Ultra-Wideband PA Based on Improved MOEA/D Algorithm Using Mixed Objective Function
OpenMPL: An Open-Source Layout Decomposer
Analysis of propagation delays in high-speed VLSI circuits using a distributed line model
Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction Under Output Constraint
An Artificial Neural Network Assisted Optimization System for Analog Design Space Exploration
Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip
McDRAM: Low Latency and Energy-Efficient Matrix Computations in DRAM
Time- and Frequency-Domain Analysis of Linear Switched-Capacitor Networks Using State Charge Variables
A Modeling Attack Resistant Deception Technique for Securing Lightweight-PUF-Based Authentication
Theoretical Fundamentals of Gate Level Information Flow Tracking
GREDA: A Fast and More Accurate Gate Reliability EDA Tool
Multiagent Based Reinforcement Learning (MA-RL): An Automated Designer for Complex Analog Circuits
Exploring the Potential Benefits of Alternative Quantum Computing Architectures
Analysis of distributed resistance effects in MOS transistors
A Time-Domain Oscillator Envelope Tracking Algorithm Employing Dual Phase Conditions
Translation Validation of High-Level Synthesis
A problem independent parallel implementation of simulated annealing: models and experiments
A Locality-Aware Compression Scheme for Highly Reliable Embedded Systems
A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators
ClipFormer: Key-Value Clipping of Transformers on Memristive Crossbars for Write Noise Mitigation
Efficient techniques for accurate modeling and simulation ofsubstrate coupling in mixed-signal IC's
Diffusion-Based Placement Migration With Application on Legalization
A boundary element method for modeling viscoelastic flow in thermal oxidation
Tree-Based Clock Distribution of Multiple-Stage Pipelined Architecture in Rapid Single-Flux-Quantum Circuits
Micropreemption synthesis: an enabling mechanism for multitask VLSI systems
Hier-RTLMP: A Hierarchical Automatic Macro Placer for Large-Scale Complex IP Blocks
Analytical modeling of dual-gate HFET's
Supervised Learning Based Power Management for Multicore Processors
High-Performance Routing at the Nanometer Scale
Self-Supervised On-Device Federated Learning From Unlabeled Streams
QuantHD: A Quantization Framework for Hyperdimensional Computing
Intelligent Hotspot Prediction for Network-on-Chip-Based Multicore Systems
Model-based dummy feature placement for oxide chemical-mechanicalpolishing manufacturability
A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors
Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout
An approach for multilevel logic optimization targeting low power
GNN-Cap: Chip-Scale Interconnect Capacitance Extraction Using Graph Neural Network
Adaptive Test With Test Escape Estimation for Mixed-Signal ICs
Improving Transformer Inference Through Optimized Nonlinear Operations With Quantization-Approximation-Based Strategy
New Hardware and Power Efficient Sporadic Logarithmic Shifters for DSP Applications
Efficient generation of diagonal constraints for 2-D mask compaction
Oxpecker: Leaking Secrets via Fetch Target Queue
IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation
Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation
Reconfigurable and Low-Complexity Accelerator for Convolutional and Generative Networks Over Finite Fields
Power Aware Placement of On-Chip Voltage Regulators
Coexisting Hyperchaos in a Memristive Neuromorphic Oscillator
On Diagnosis of Timing Failures in Scan Architecture
Deterministic and Probabilistic Diagnostic Challenge Generation for Arbiter Physical Unclonable Function
Alleviating Hot Data Write Back Effect for Shingled Magnetic Recording Storage Systems
DeepTrain: A Programmable Embedded Platform for Training Deep Neural Networks
Efficient Proximity Effect Correction Using Fast Multipole Method With Unequally Spaced Grid for Electron Beam Lithography
Logic Synthesis for Interpolant Circuit Compaction
LES: a layout expert system
Delay Insertion Method in Clock Skew Scheduling
Digraph Relaxation for 2-Dimensional Placement of IC Blocks
Hierarchical Temporal Memory Features with Memristor Logic Circuits for Pattern Recognition
AxOSpike: Spiking Neural Networks-Driven Approximate Operator Design
A new dynamic test vector compaction for automatic test pattern generation
Fitness Prediction Techniques for Scenario-Based Design Space Exploration
Fast 3-D Thermal Simulation for Integrated Circuits With Domain Decomposition Method
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random L eff Variation
Mixed analog/digital hardware synthesis of artificial neural networks
Bounding Variable Values and Round-Off Effects Using Handelman Representations
Three-Dimensional Monte Carlo Simulations--Part II: Recoil Phenomena
Optimal Performance-Aware Cooling on Enterprise Servers