yusuke1997/dblp-id-title huggingface dataset:
Board Test and the Product Life Cycle: Get Wise to Board Test
Pulse-Width-Modulating Biosignal ADC for Rapid ASIC Design and IP Core Reuse
Design for reliability and robustness
Inductive Fault Analysis of MOS Integrated Circuits
Planned Unobsolescence
TTTC News
Side Channels of Cyber-Physical Systems: Case Study in Additive Manufacturing
Decreasing Test Qualification Time in AMS and RF Systems
IEEE Design & Test of Computers: 1997 Annual Index, Volume 14
Variation and Reliability in FPGAs
VHDL-200X: The Next Revision
Design and Test of Digital Logic DNA Systems
Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers
A Hardware-Software Codesign Methodology for DSP Applications
A Rule-Based Design-for-Testability Rule Checker
Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch
IEEE CASS becomes D&T Copublisher
Erratum to "Ethical Design of Computers: From Semiconductors to IoT and Artificial Intelligence"
Applying IEEE Test Standards to Multidie Designs
TTTC Reports on Recent Standards Activities
Are IEEE-1500-Compliant Cores Really Compliant to the Standard?
Design and Test of Energy-Efficient, High-Performance, and Secure Computing Technologies via Accelerators
Guest Editors' Introduction: The True State of the Art of ESL Design
East-West Design & Test Workshop
Frequency Domain Testing of ADCs
Addressing Functional Safety Challenges in Autonomous Vehicles with the Arm TCL S Architecture
Seamless Test of Digital Components in Mixed-Signal Paths
Variability-Aware Parametric Yield Estimation for Analog/Mixed-Signal Circuits: Concepts, Algorithms, and Challenges
A Behavioral Fault Simulator for Ideal
Formally Verifying Transfer Functions of Linear Analog Circuits
ITC 2006 panels
Bugs, moths, grasshoppers, and whales
56th Design Automation Conference Report
Book Reviews: NoC, NoC ... Who's there?
Design for Verification?
How Much Logic Should Go in an FPGA Logic Block?
A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace Applications
Runtime Reconfiguration Techniques for Efficient General-Purpose Computation
Asynchronous Design - Part 1: Overview and Recent Advances
A Layered Adaptive Verification Platform for Simulation, Test, and Emulation
An On-Chip Self-Repair Calculation and Fusing Methodology
Fast Fault Simulation for Nonlinear Analog Circuits
IEEE P1647 and P1800: Two approaches to standardization and language design
The fate of stacking
Increasing Test Accuracy by Varying Driver Slew Rate
Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores
Adaptive Approximate Computing in Arithmetic Datapaths
A New Framework for Designing: Built-in Test Multichip Modules with Pipelined Test Strategy
Binary Forward-Only Algorithms
Inventions: A Result of Risk-Taking, Diversity, and Holistic Thinking - An interview with Bernard S. Meyerson, IBM Fellow, Vice President, and Chief Technologist of IBM's System Technology Group
Supporting cost-effective innovation
Survey on Education for Cyber-Physical Systems
Exploring Silicon Nanophotonics in Throughput Architecture
All About Liquid Scan Chains - and More [review of "Digital Microfluidic Biochips: Design Automation and Optimization" (Chakrabarty, K. and Xu, T.; 2010)]
Design Version Management
Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology and Electronic Design Automation for IC System Design, Verification, and Testing
Defect and Error Tolerance in the Presence of Massive Numbers of Defects
An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs
Parallel simulated annealing: accuracy vs. speed in placement
Multisynchronous and Fully Asynchronous NoCs for GALS Architectures
The Road Ahead: The significance of packaging
Quantifying Design Quality Through Design Experiments
An Integrated Environment for Technology Closure of Deep-Submicron IC Designs
Review of Millimeter-Wave MMIC Mixers
Roundtable: Adding Reconfigurable Logic to SOC Designs
Energy-Monitoring Tool for Low-Power Embedded Programs
Surrogate Model-Based Self-Calibrated Design for Process and Temperature Compensation in Analog/RF Circuits
Design illiteracy
Mixed Criticality Systems - A History of Misconceptions?
D&T to greet new EIC
A Sensor-Assisted Self-Authentication Framework for Hardware Trojan Detection
Source-Synchronous Testing of Multilane PCI Express and HyperTransport Buses
Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP
Philadelphia Section Honors Grace Hopper
Embedded Memories for the Future
WEAVER: A Knowledge-Based Routing Expert
Automotive Virtual In-sensor Analytics for Securing Vehicular Communication
First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration
Exploiting Parallelism by Data Dependency Elimination: A Case Study of Circuit Simulation Algorithms
Battery-Driven Dynamic Power Management
Guest Editors' Introduction: System IC Design Challenges beyond 32 nm
Conventional Tests for Approximate Scan Logic
Using Approximate Circuits Against Hardware Trojans
IC Reliability and Test: What Will Deep Submicron Bring?
Efficient Self-Recovering ASIC Design
Layout Proximity Effects and Modeling Alternatives for IC Designs
A Reconfiguration-Based Defect-Tolerant Design Paradigm for Nanotechnologies
Algorithmic Concurrent Error Detection in Complex Digital-Processing Systems
Multisensing System for Parkinson's Disease Stage Assessment Based on FPGA-Embedded Serial SVM Classifier
Keeping current with silicon and systems technology in the mid-90s
On Hardware-Aware Design and Optimization of Edge Intelligence
A Clock Sweeping Technique for Detecting Hardware Trojans Impacting Circuits Delay
FaCT-LSTM: Fast and Compact Ternary Architecture for LSTM Recurrent Neural Networks
Comparative Study of Authenticated Encryption Targeting Lightweight IoT Applications
Subword Switching Activity Minimization to Optimize Dynamic Power Consumption
Test Algorithms for Double-Buffered Random Access and Pointer-Addressed Memories
Hardware-Software Approaches to In-Circuit Emulation for Embedded Processors
CMOS Circuits with Subvolt Supply Voltages
Designing and Implementing an Architecture with Boundary Scan
A BIST and Boundary-Scan Economics Framework
A Survey on Architecture Advances Enabled by Emerging Beyond-CMOS Technologies
Using Presilicon Knowledge to Excite Nonlinear Failure Modes in Large Mixed-Signal Circuits
Design of Mixed-Signal Systems With Asynchronous Control
Self-Checking Design in Eastern Europe
Secure Interposer-Based Heterogeneous Integration
Retention Testing Methodology for STTRAM
Test Strategy for the PowerPC 750 Microprocessor
Being Learned
A Fail-Safe Interlocking System for Railways
3D Chip Stack Technology Using Through-Chip Interconnects
Going 3D: Silicon and D&T
From the Editor in Chief: Full Circle?
From Classical Algorithms to AI: Evolving Trends in VLSI Physical Design Automation
Guest Editor's Introduction: Microprocessors Lead the Way in Complex Design
Guest Editors' Introduction: Hardware Accelerators for Data Centers
Benchmarking Benchmarking
New Directions in Analog/Mixed-Signal Design and Test
VHDL fault injection questioned
Test Strategies and Marriage Partners
George learns test
ZeNA: Zero-Aware Neural Network Accelerator
From the EIC: Time-Critical Systems Design
Coverage Metrics for Functional Validation of Hardware Designs
Design of ₌׀₌ Shape Stub-Based Negative Group Delay Circuit
IEEE Std 1500 Enables Modular SoC Testing
Embracing Stochasticity to Enable Neuromorphic Computing at the Edge
Estimating the Impact of Methodology on Analog Integrated Circuit Design Time
Designing Custom Arithmetic Data Paths with FloPoCo
Silent Data Corruption by 10× Test Escapes Threatens Reliable Computing
Design and Test of Crab-Shaped Negative Group Delay Circuit
1993 Editorial Calendar
Plug-and-Play IDDQ Testing for Test Fixtures
Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities
Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache
DAC 50th Anniversary Keynote
Testing: It's not just pass/fail anymore
Realistic built-in self-test for static RAMs
TTTC technical forum honoring Sudhakar M. Reddy
Low-Power, Resilient Interconnection with Orthogonal Latin Squares
A Highly Integrated Hardware/Software Co-Design and Co-Verification Platform
Formal Verification: Current Use and Future Perspectives
Built-In Self-Test Techniques
Report on the 2024 Embedded Systems Week (ESWEEK)
EDIF: A Mechanism for the Exchange of Design Information
The Last Byte: The HLS tipping point
Toward Standardized Vulnerability Assessment of Advanced Packaging Against Probing Attacks
Impact of Thermal Gradients on Clock Skew and Testing
Provably Secure Sequential Obfuscation for IC Metering and Piracy Avoidance
The 2022 Symposium on Integrated Circuits and Systems Design (SBCCI 2022)
Workloads of the Future
Challenges and Opportunities in VLSI IoT Devices and Systems
From the EIC: Circuits and Systems for VLSI IoT Devices
VHDL - The Language
Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test
Sensitivity Analysis of Critical Parameters in Board Test
Test Data Volume Comparison: Monolithic vs. Modular SoC Testing
Test: Wisdom From the Giants, Visions for the Future - Part 2
A Survey and Taxonomy of GALS Design Styles
Digital Analog Design: Enabling Mixed-Signal System Validation
High-Level Dataflow Transformations Using Taylor Expansion Diagrams
Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning
System Specification Experiments on a Common Benchmark
Mixed-Signal SoCs With In Situ Self-Healing Circuitry
A Survey of Hybrid Techniques for Functional Verification
Online Testing Approach for Very Deep-Submicron ICs
Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy
From the Editor in Chief: A "Powerful" Issue!
CUSHAW2-GPU: Empowering Faster Gapped Short-Read Alignment Using GPU Computing
Which tester is right for your MCM?
Hot Topics at HLDVT 02
Huge Storage Capacity
Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters
The Art of Certifying Analog/Mixed-Signal Circuits
Report on the 38th ACM/IEEE International Conference on Computer-Aided Design (ICCAD 2019)
Still Making Noise: Improving Deep- Learning-Based Side- Channel Analysis
50 Years of DAC Moments
Roundtable: Machine Learning for Embedded Systems: Hype or Lasting Impact?
The 2021 Asia and South Pacific Design Automation Conference (ASPDAC)
ITC 97 Panel Sessions
Run-Time Adaptive Power-Aware Reliability Management for Manycores
A D&T Roundtable: Are Single-Chip Multiprocessors in Reach?
Saving Power in the Control Path of Embedded Processors
Special Issue on Wearable IoT Devices for Reliable Mobile Health Applications
D&T News
Technology for IP Reuse and Portability
Guest Editors' Introduction: Design and Testing of Millimeter-Wave/Subterahertz Circuits and Systems
Roundtable: Envisioning the Future for Multiprocessor SoC
Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation
Being Connected
ITC 2003 Roundtable: Design for Manufacturability
Extending OPMISR beyond 10x Scan Test Efficiency
A 2.5-D Memory-Logic Integration With Data-Pattern-Aware Memory Controller
Time-Critical Systems Design: A Survey
AnyBoard: An FPGA-Based, Reconfigurable System
Trusted Analog/Mixed- Signal/RF ICs: A Survey and a Perspective
On-Chip Testing Techniques for RF Wireless Transceivers
How do we train today's students to become tomorrow's engineers?
The electronic workstation-an overview
Design of a Low-Noise UWB Transceiver SiP
Simplifying Sequential Circuit Test Generation
Roundtable: Design and CAD Challenges for Leading-Edge Multimedia Designs
System-on-Chip Design: Impact on Education and Research
Absolute Energy Routing and Real-Time Power Monitoring for Grid-Connected Distribution Networks
A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection
A Supercomputer Workstation for VLSI CAD
The Challenges of Nanotechnology and Gigacomplexity
Ideas: a tool for VLSI CAD
Three-Input NPN Class Gate Library for Atomic Silicon Quantum Dots
Organizational Dynamics: Understanding the Impact of Organizational Structure in Team Productivity
2005 IEEE East-West Design and Test Workshop
Stacking chips in 3D
Verification-Purpose Operating System for Microprocessor System-Level Functions
A Methodology for Debugging ASIC Prototypes in the Field
Abstraction and Standardization in Hardware Design
Built-in Self Testing of Embedded Memories
Functionally Testable Path Delay Faults on a Microprocessor
An approach that will NoC your SoCs off!
Toward Attention-Based TinyML: A Heterogeneous Accelerated Architecture and Automated Deployment Flow
Efficient Aspect Verification and Debugging of High-Performance Microprocessor Designs
Simulation-Based Analysis of Dielectrophoretic Field Flow Fractionation Devices
TTCC Newsletter
An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC
Self-Awareness in Systems on Chip, Part II
Book Reviews: Plumbing the Depths of Leakage
Mitigating Speculative Execution Attacks via Context-Sensitive Fencing
Boundary scan with built-in self-test
Design for Testability in Hardware-Software Systems
From the EIC: Robust Machine Learning
Streaming Access to ADCs and DACs for Mixed-Signal ATPG
Using March Tests to Test SRAMs
Circuits to Systems: Codesigning Efficient AI Hardware
Real-time Hardware Implementation of ARM CoreSight Trace Decoder
Dark Silicon, Antiparallelism, and Too Much Work
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII
Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification
1994 Annual Index: Authors and Subjects
Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach
Report on the 2020 Embedded Systems Week (ESWEEK): A Virtual Event during a Pandemic, September 20-25
Guest Editors' Introduction: Digitally Enhanced Wireless Transceivers
Power Delivery Performance of Probe Test Systems for Semiconductor Wafers
Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection
A Review of Hardware Acceleration for Computational Genomics
On Deploying Scan Chains for Data Storage in Test Compression Environment
A synthesis environment for designing DSP systems
FPGAs, Programming Models, and Kit Cars
An Efficient Signature Computation Method
Hardware-Software Codesign Using Processor Synthesis
An Introduction to High-Level Synthesis
Guest Editors' Introduction: East Meets West
From the EIC: Building and verifying hardware at a higher level of abstraction
The Council on Electronic Design Automation: Creation, Growth, and Future
Conquering Noise in Deep-Submicron Digital ICs
Design & Test Education in Asia
Logic Synthesis for Manufacturability
Author Guidelines IEEE Design & Test
Cross-Layer Design and Design Automation for In-Memory Computing Based on Nonvolatile Memory Technologies
Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects
With pick and shovel through our data
Large Power Division Ratio Branch-Line Coupler With Differential Through and Differential to Single-Ended Coupling
SURF: Rubber-Band Routing System for Multichip Modules
A D&T Roundtable: Relative Effectiveness of Tests
Special Issue on the 2023 International Symposium on Networks-on-Chip (NOCS 2023)
TYLOR: TDC-Based Low-Overhead Synthesizable Power SCA Countermeasure on FPGAs
A Look at Trojan Attack, Pruning, and Dependability
Applying the Model-View-Controller Paradigm to Adaptive Test
An Integrated Design Automation System for VLSI Circuits
CPU-FPGA Coscheduling for Big Data Applications
edAttack: Hardware Trojan Attack on On-Chip Packet Compression
Guest Editors' Introduction: Implantable Medical Devices
D&T: 15th Year in Service
Comprehensive Static Characterization of Vertical Electrostatically Actuated Polysilicon Beams
Guest Editors' Introduction: Biochips and Integrated Biosensor Platforms
Image Processing Techniques for Wafer Defect Cluster Identification
Variability and Reliability Awareness in the Age of Dark Silicon
Design and Analysis of a Transversal Filter RFIC in SiGe Technology
SmartPatch: A Self-Powered and Patchable Cumulative UV Irradiance Meter
Optimizing Power in ASIC Behavioral Synthesis
Roads not taken
Detecting Pediatric Foot Deformities Using Plantar Pressure Measurements: A Semisupervised Approach
Design and Self-Test for Switched-Current Building Blocks
Guest Editors' Introduction: Board Test
The Fairchild Sentry 50 Tester: Establishing New ATE Performance Limits
IEEE Design & Test of Computers Annual Index, Volume 12
Computing in the Real World
Turbo1500: Core-Based Design for Test and Diagnosis
Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC
Runtime Protection of Real-time Critical Control Applications against Known Threats
Operational Life Testing of Electronic Components
Controlling Aging in Timing-Critical Paths
Hierarchical Test Integration Methodology for 3-D ICs
SCC20 Reports on Recent Standards Activities
Universal Fault Diagnosis for Lookup Table FPGAs
From the EIC
Dealing with Obsolete Parts
Good Enough Computing
Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits
Efficient SoC Security Monitoring: Quality Attributes and Potential Solutions
SoC Security Evaluation: Reflections on Methodology and Tooling
DFT Expert: designing testable VLSI circuits
Test counting: a tool for VLSI testing
A Retargetable Embedded In-Circuit Emulation Module for Microprocessors
Time-Division-Multiplexed Test Delivery for NoC Systems
A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs
Wireless Interconnect and the Potential for Carbon Nanotubes
A Novel Simulation Fault Injection Method for Dependability Analysis
Guest Editors' Introduction: Top Papers from the 2015 International Test Conference
Test Consideration for Nanometer-Scale CMOS Circuits
Very Low Cost Testers: Opportunities and Challenges
Testing Multimedia Transmission Systems
Statistical Methods for Detecting Recycled Electronics: From ICs to PCBs and Beyond
The Physics of Event-Driven IoT Systems
Guest Editors' Introduction: Defect-Oriented Diagnosis for Very Deep-Submicron Systems
Value-Added Defect Testing Techniques
2003 Annual Index IEEE Design & Test of Computers Volume 20
An Industrial Evaluation of DRAM Tests
In-Stream Correlation-Based Division and Bit-Inserting Square Root in Stochastic Computing
Special Issue on Testability and Dependability of Artificial Intelligence Hardware
Lynn Conway: Two Remembrances
FALCON: An FPGA Emulation Platform for Domain-Specific SoCs (DSSoCs)
DASC standards track IP-based design trends
From the EIC: Special Issue on VTS
Silicon Lifecycle Management
Toward Silicon-Based Cognitive Neuromorphic ICs - A Survey
Design and Test of an Integrated Cryptochip
Research in Design Automation for VLSI Layout
Fast Pass-Transistor Simulation for Custom MOS Circuits
Attacks and Defenses for JTAG
A 100-MIPS GaAs Asynchronous Microprocessor
Embedded Robustness IPs for Transient-Error-Free ICs
VLSI, MCM, and WSI: A Design Comparison
The Future: Plug and Pray?
Integrated Flow-Control Codesign Methodology for Flow-Based Microfluidic Biochips
Diverse Double Modular Redundancy: A New Direction for Soft-Error Detection and Correction
A D&T Roundtable: Synthesis for Testability
Developing Architectural Platforms: A Disciplined Approach
Policies and procedures - who needs them?
Electronic System, Platform, and Package Codesign
A D&T Roundtable: Design for Manufacturability
Embedded Tools for a Configurable and Customizable DSP Architecture
Guest Editors' Introduction: Near-Memory and In-Memory Processing
Testability and Dependability of AI Hardware: Survey, Trends, Challenges, and Perspectives
1992 Annual Index: Complete Subject/Author Listing
Testing Logic-Intensive Memory ICs on Memory Testers
Dynamic Functional Testing for VLSI Circuits
Software Development for High-Performance, Reconfigurable, Embedded Multimedia Systems
An Evaluation of Asynchronous Stacks
Built-In Self-Testing RAM: A Practical Alternative
A Model and Methodology for Hardware-Software Codesign
Exploiting Domain Knowledge in IC Cell Layout
Formal Verification of VHDL Descriptions in the Prevail Environment
Design for Test With Unreliable Memories by Restoring the Beauty of Randomness
Automated Diagnosis in Testing and Failure Analysis
Overview of 3-D Architecture Design Opportunities and Techniques
Jitter Testing for Gigabit Serial Communication Transceivers
Numerical Data Representations for FPGA-Based Scientific Computing
An FPGA for Implementing Asynchronous Circuits
Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs
Guest Editors' Introduction: Stressing the Fundamentals
A Minimalist Approach to VHDL Logic Modeling
Is This a System?
Multiplication Circuit Architecture for Error- Tolerant CNN-Based Keywords Speech Recognition
On-chip networks: Two sides of the same coin
Optimizing Multiple EDA Tools within the ASIC Design Flow
Anomaly Detection and Health-Status Analysis in a Core Router System
The Future of Automotive Design and the Road to Get There
System Complexity and Integrated Diagnostics
Yield of Black Swans
Spectre Returns! Speculation Attacks Using the Return Stack Buffer
ITC 2003 panels: Part 1
Techniques for Synthesis of Analog Integrated Circuits
Reconfigurable Architecture for Autonomous Self-Repair
An Empirical Set of Metrics for Embedded Systems Testing
Transitional Phones
Hierarchical Layout Verification
Delay Defect Characteristics and Testing Strategies
Voltage-Driven Building Block for Hardware Belief Networks
New ECC for Crosstalk Impact Minimization
Guest Editors' Introduction: Microprocessor Test and Verification
Lessons learned from hacking a car
Minimizing FPGA Interconnect Delays
The Joy of Scheduling
Lessons and Experiences with High-Level Synthesis
The Newer Colossus
Learning and Practice of the Property Specification Language
ISLPED 2023: International Symposium on Low-Power Electronics and Design
A Systematic Approach to Memory Test Time Reduction
A Value System for Switch-Level Modeling
Guest Editor's Introduction: Evolving Methods for Detecting and Handling Reliability Defects
Metamodeling: An Emerging Representation Paradigm for System-Level Design
The Search for Alternative Computational Paradigms
ERIN: Energy-Aware Resource-Provisioning Framework for CPU-FPGA Multitenant Environment
Improving Defect Detection in Static-Voltage Testing
A D&T Roundtable: Testing Mixed Logic and DRAM Chips
Introducing Hardware-Based Intelligence and Reconfigurability on Industrial IoT Edge Nodes
Engineering Applied to Societal Problems: A New Outlook
Mitigating the Memory Bottleneck With Approximate Load Value Prediction
2019 DAC Roundtable
Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below
Guest Editors' Introduction: Machine Intelligence at the Edge
Three-Dimensional Integrated Circuits
Automating Wave-Pipelined Circuit Design
A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation
Optimal Energy Efficiency and Throughput on Partially Reversible Pipelined QCA Circuits
Crosstalk-Aware Placement
Build Your Own EV: A Rapid Energy-Aware Synthesis of Electric Vehicles
EDA and Quantum Computing: a symbiotic relationship?
Using Formal Specifications for Functional Validation of Hardware Designs
SCC20 attracts IEC participation
Millimeter-Wave Wireless Interconnect for 3-D SIC Testing
Multidimensional Test Escape Rate Modeling
Leveraging Software Configuration Management in Automated RTL Design Debug
Reliability Implications of Bias-Temperature Instability in Digital ICs
Efficient Sequential Test Generation Based on Logic Simulation
A statistical model for delay-fault testing
A Case Study in Design Space Exploration: The Tosca Environment Applied to a Telecommunication Link Controller
Guest Editors' Introduction: Computing in the Dark Silicon Era
Message From the Steering Committee
Base 1 logic: A method for environmentally friendly PC design
Thousand-Core Chips [Roundtable]
VHDL: Toward a Unified View of Design
Guest Editors' Introduction: SBCCI 2021