yusuke1997/dblp-id-title huggingface dataset:
A 0.08%/V 32.3-ppm/°C 36.6-kHz Unregulated Current-Reuse Ring Oscillator With VGS-Ratio-Based Compensation Using One-Type-Only Resistor
A 400-MHz processor for the conversion of rectangular to polar coordinates in 0.25-μm CMOS
Alignment-Independent Chip-to-Chip Communication for Sensor Applications Using Passive Capacitive Signaling
A 1/4-inch 330 K square pixel progressive scan CMOS active pixel image sensor
Nonlinear transmission lines for pulse shaping in silicon
A Single-Trim Frequency Reference System With 0.7 ppm/°C From -63 °C to 165 °C Consuming 210 μW at 70 MHz
A 28-nm 19.9-to-258.5-TOPS/W 8b Digital Computing-in-Memory Processor With Two-Cycle Macro Featuring Winograd-Domain Convolution and Macro-Level Parallel Dual-Side Sparsity
A 2× load/store pipe for a low-power 1-GHz embedded processor
A Sub-μW Energy-Performance-Aware IoT SoC With a Triple-Mode Power Management Unit for System Performance Scaling, Fast DVFS, and Energy Minimization
5.6 Mb/mm 2 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology
A novel transistor model for simulating avalanche-breakdown effects in Si bipolar circuits
A multipage cell architecture for high-speed programming multilevel NAND flash memories
A 1.8-V GPIO With Design-Technology-Reliability Co-Optimization in Sub-3-nm GAA-NS Technology
A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control
A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver
Comments on "Comments on "A General Theory of Phase Noise in Electrical Oscillators""
An Implantable 455-Active-Electrode 52-Channel CMOS Neural Probe
Comment on Corrections to "A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier"
A Supply Pushing Reduction Technique for LC Oscillators Based on Ripple Replication and Cancellation
kNOT: A 2-D Distributed Network-on-Textile Architecture With Direct Die-to-Yarn Integration of 0.6 × 2.15 mm 2 SoC and bySPI Chiplets for Wearable Computing
A Hybrid ToF Image Sensor for Long-Range 3D Depth Measurement Under High Ambient Light Conditions
A Rel-12 2G/3G/LTE-Advanced 3CC Cellular Receiver
SORTCHIP: a VLSI implementation of a hardware algorithm for continuous data sorting
Design and Measurement Techniques for an 80 Gb/s 1-Tap Decision Feedback Equalizer
A low-power PLA for a signal processor
A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL
A Reconfigurable Non-Uniform Power-Combining V-Band PA With +17.9 dBm P sat and 26.5% PAE in 16-nm FinFET CMOS
A 5-GHz fully integrated full PMOS low-phase-noise LC VCO
A Highly Digital 143.2-dB DR Sub-1° Phase Error Impedance Monitoring IC With Pulsewidth Modulation Frontend
A Distributed Low-Noise Amplifier for Broadband Linearization of a Silicon Photonic Mach-Zehnder Modulator
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing
Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS
Design of a 0.9 V 2.45 GHz Self-Testable and Reliability-Enhanced CMOS LNA
A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme
An Ultra-Low-Jitter Fast-Hopping Fractional-N PLL With LC DTC and Hybrid-Proportional Paths
A Compact 19.7- to 43.8-GHz Power Amplifier With 20.3-dBm Psat and 35.5% PAE in 28-nm Bulk CMOS
A Parallel-SSHI Rectifier for Piezoelectric Energy Harvesting of Periodic and Shock Excitations
100-GHz high-gain InP MMIC cascode amplifier
An Active Transmitter Leakage Suppression Technique for CMOS SAW-Less CDMA Receivers
A Terahertz Molecular Clock on CMOS Using High-Harmonic-Order Interrogation of Rotational Transition for Medium-/Long-Term Stability Enhancement
Dummy transistor compensation of analog MOS switches
A 56-Gb/s PAM-4 Receiver Using Time-Based LSB Decoder and S/H Technique for Robustness to Comparator Voltage Variations
Low-power 2K-cell SDFL gate array and DCFL circuits using GaAs self-aligned E/D MESFETs
A 0.5 V PWM CMOS Imager With 82 dB Dynamic Range and 0.055% Fixed-Pattern-Noise
A 1.5 nW, 32.768 kHz XTAL Oscillator Operational From a 0.3 V Supply
Design techniques for high-speed, high-resolution comparators
A 0.65-mW-to-1-W Photovoltaic Energy Harvester With Irradiance-Aware Auto-Configurable Hybrid MPPT Achieving >95% MPPT Efficiency and 2.9-ms FOCV Transient Time
Design of Three-Stage Class-AB 16ΩHeadphone Driver Capable of Handling Wide Range of Load Capacitance
A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits
A 0.18-V 382-µW Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS
An $E$ -Band Power Amplifier With 26.3% PAE and 24-GHz Bandwidth in 22-nm FinFET CMOS
Physical timing modeling for bipolar VLSI
A 1-V 6-b 50-MSamples/s current-interpolating CMOS ADC
A 1.6-GHz CMOS PLL with on-chip loop filter
A 28 nm 128-kb Exponent- and Mantissa-Computation-In-Memory Dual-Macro for Floating-Point and INT CNNs
50-Gb/s 4-b multiplexer/demultiplexer chip set using InP HEMTs
Analog to Sequence Converter-Based PAM-4 Receiver With Built-In Error Correction
Bandwidth-Enhanced Oversampling Successive Approximation Readout Technique for Low-Noise Power-Efficient MEMS Capacitive Accelerometer
A 1 k-Pixel Video Camera for 0.7-1.1 Terahertz Imaging Applications in 65-nm CMOS
Impedance boosting techniques based on BiCMOS technology
A Low-Power High-PSRR Clock-Free Current-Controlled Class-D Audio Amplifier
Class-C PA-VCO Cell for FSK and GFSK Transmitters
Correction to "A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS"
Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication
An 8-b, 40 msamples/s switched-current-mode track-and-hold circuit on a BiCMOS sea-of-gates array
CMOS mixers and polyphase filters for large image rejection
A CMOS ultra-wideband impulse radio transceiver for 1-mb/s data communications and ±2.5-cm range finding
An enhanced adaptive Q-tuning scheme for a 100-MHz fully symmetric OTA-based bandpass filter
A 23 mW, 73 dB Dynamic Range, 80 MHz BW Continuous-Time Delta-Sigma Modulator in 20 nm CMOS
A self-timed divider using a new fast and robust pipeline scheme
Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck-Boost Switched-Capacitor DC-DC Converters
An 81-MHz IF receiver in CMOS
A 35 Mb/s mixed-signal decision-feedback equalizer for disk drives in 2-μm CMOS
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS
A Phase-Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology
A bipolar integrated continuous-time filter with optimized dynamic range
A Wide-Bandwidth 2.4 GHz ISM Band Fractional-N PLL With Adaptive Phase Noise Cancellation
A 27 $\mu \text{W}$ 0.06 mm2 Background Resonance Frequency Tuning Circuit Based on Noise Observation for a 1.71 mW CT- $\Delta \Sigma $ MEMS Gyroscope Readout System With 0.9 °/h Bias Instability
Corrections to "a high-swing CMOS telescopic operational amplifier"
Low Bit-Depth ADCs for Multi-bit Quanta Image Sensors
A programmable intraocular CMOS pressure sensor system implant
Mixed static and domino logic on the CMOS gate forest
A novel ASIC design approach based on a new machine paradigm
iMCU: A 28-nm Digital In-Memory Computing-Based Microcontroller Unit for TinyML
A 78.4 dB Photo-Sensitivity Dynamic Range, 285 T Ω Hz Transimpedance Bandwidth Product BiCMOS Optical Sensor for Optical Storage Systems
A 0.18-µm CMOS Balanced Amplifier for 24-GHz Applications
Correction to "A 2000-Volumes/s 3-D Ultrasound Probe With Monolithically-Integrated 23 × 23-mm 2 4096-Element CMUT Array"
A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery
A 1.2-W single-chip MPEG2 MP@ML video encoder LSI including wide search range (H±288, V: ±96) motion estimation and 81-MOPS controller
Sub-μW Auto-Calibration Bandgap Voltage Reference With 1σ Inaccuracy of ± 0.12% Within - 40°C to 120°C
Threshold-voltage balance for minimum supply operation [LV CMOS chips]
A Dynamic Vision Sensor With 1% Temporal Contrast Sensitivity and In-Pixel Asynchronous Delta Modulator for Event Encoding
A 180-mV subthreshold FFT processor using a minimum energy design methodology
A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device
A 15-Gb/s PAM-3 Transceiver With Hybrid Equalization and Time-Domain Decoder for High-Bandwidth-Memory Interfaces
A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 µm CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit
Novel switched current source for increasing output signal edge steepness of current switches without generating large overshoot
A Fast Startup CMOS Crystal Oscillator Using Two-Step Injection
A single-chip VHF and UHF receiver for radio paging
Introduction to the Special Issue on the 37th European Solid-State Circuits Conference (ESSCIRC)
Introducing BrowZine, a Tablet and Phone-Based Reader for the JSSC
CMOS Image Sensor With Per-Column ΣΔ ADC and Programmable Compressed Sensing
A Single-Pin Antenna Interface RF Front End Using a Single-MOS DCO-PA and a Push-Pull LNA
The delay vernier pattern generation technique
A 12-to-1 Flying Capacitor Cross-Connected Buck Converter With Inserted D > 0.5 Control for Fast Transient Response
Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise
A low-cost, 300-MHz, RISC CPU with attached media processor
A 2-V, low distortion, 1-GHz CMOS up-conversion mixer
A 50-GHz Phase-Locked Loop in 0.13-µm CMOS
A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations
A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation
A CMOS Thermistor-Embedded Continuous-Time Delta-Sigma Temperature Sensor With a Resolution FoM of 0.65 pJ°C 2
An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management
A digital adaptive beamforming QAM demodulator IC for high bit-rate wireless communications
A multistep A/D converter family with efficient architecture
An IR-UWB CMOS Transceiver for High-Data-Rate, Low-Power, and Short-Range Communication
A low distortion bipolar mixer for low voltage direct up-conversion and high IF systems
Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector
Design considerations and implementation of a DSP-based car-radio IF Processor
An 80-mVpp Linear-Input Range, 1.6- $\text{G}\Omega $ Input Impedance, Low-Power Chopper Amplifier for Closed-Loop Neural Recording That Is Tolerant to 650-mVpp Common-Mode Interference
A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS
A 0.025-0.45 W 60%-Efficiency Inductive-Coupling Power Transceiver With 5-Bit Dual-Frequency Feedforward Control for Non-Contact Memory Cards
Low-voltage swing logic circuits for a Pentium® 4 processor integer core
A 25-Gb/s 5-mW CMOS CDR/Deserializer
A Passive Wideband Noise-Canceling Mixer-First Architecture With Shared Antenna Interface for Interferer-Tolerant Wake-Up Receivers and Low-Noise Primary Receivers
An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer
A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch
VLSI implementation of MIMO detection using the sphere decoding algorithm
A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching
A broad-band amplifier using GaAs/GaAlAs heterojunction bipolar transistors
A Short Range, Low Data Rate, 7.2 GHz-7.7 GHz FM-UWB Receiver Front-End
A 200 MHz register-based wave-pipelined 64 M synchronous DRAM
A CMOS serial link for fully duplexed data communication
A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
A 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generation
A wide-band GaAs monolithic spiral quadrature hybrid and its circuit applications
A Nyquist-rate delta-sigma A/D converter
High-speed CMOS adder and multiplier modules for digital signal processing in a semicustom environment
A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line
A special-purpose content addressable memory chip for real-time image processing
A CMOS oversampled DAC with multi-bit semi-digital filtering and boosted subcarrier SNR for ADSL central office modems
A 100-Gbps Fault-Injection Attack-Resistant AES-256 Engine With 99.1%-99.99% Error Coverage in Intel 4 CMOS
A 120-145 GHz Heterodyne Receiver Chipset Utilizing the 140 GHz Atmospheric Window for Passive Millimeter-Wave Imaging Applications
A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip
140 Gb/s Serializer Using Clock Doublers in 90 nm SiGe Technology
Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate
1/4-inch 2-mpixel MOS image sensor with 1.75 transistors/pixel
A Recursive N-Path Switched-Capacitor Rectifier for Piezoelectric Energy Harvesting
E-Band Multi-Phase LC Oscillators With Rotated-Phase-Tuning Using Implicit Phase Shifters
An 18 V Input 10 MHz Buck Converter With 125 ps Mixed-Signal Dead Time Control
A 16-bit 12-GS/s Single-/Dual-Rate DAC With a Successive Bandpass Delta-Sigma Modulator Achieving <-67-dBc IM3 Within DC to 6-GHz Tunable Passbands
Wavelength Locking of a Si Ring Modulator Using an Integrated Drop-Port OMA Monitoring Circuit
Mixed-Order Correlated Dual-Loop Sturdy MASH CT-ΔΣ Modulator With Distributed Signal Feed-In and VCO Quantizer
A 0.9-V 1T1C SBT-based embedded nonvolatile FeRAM with a reference voltage scheme and multilayer shielded bit-line structure
A Compact 90-180 GHz, 15-18 dBm Power Amplifier With Novel Self-Shielding Load-Open Balun and Broadband Fourth-Order LC Ladder Power Combiner in 28-nm CMOS
A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder
A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration
A 1 TOPS/W Analog Deep Machine-Learning Engine With Floating-Gate Storage in 0.13 µm CMOS
Integrated sensor and range-finding analog signal processor
An Output Bandwidth Optimized 200-Gb/s PAM-4 100-Gb/s NRZ Transmitter With 5-Tap FFE in 28-nm CMOS
Integrated complementary HBT microwave push-pull and Darlington amplifiers with p-n-p active loads
A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-V MIN Applications
A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices
A silicon bipolar 4-bit 1-Gsample/s full Nyquist A/D converter
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation
A Dynamic Zoom ADC With 109-dB DR for Audio Applications
A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect
A voltage compensated series-gate bipolar circuit operating at sub-2 V
A dual 4-bit 2-Gs/s full Nyquist analog-to-digital converter using a 70-ps silicon bipolar technology with borosenic-poly process and coupling-base implant
A single-chip 2.4-Gb/s CMOS optical receiver IC with low substrate cross-talk preamplifier
A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel Delta Sigma ADC Architecture
A 1.57-GHz fully integrated very low-phase-noise quadrature VCO
A Low-Power BiCMOS 4-Element Phased Array Receiver for 76-84 GHz Radars and Communication Systems
High Efficiency WCDMA Power Amplifier With Pulsed Load Modulation (PLM)
Computer-aided design of a BPSK spread-spectrum chip set
A 9-bit 500-MS/s 2-bit/cycle SAR ADC With Error-Tolerant Interpolation Technique
On-Chip Two-Tone Synthesizer Based on a Mixing-FIR Architecture
On the operation of cascode gain stages
Open/folded bit-line arrangement for ultra-high-density DRAM's
Synchronization circuit performance
A DC-to-12.5 Gb/s 9.76 mW/Gb/s All-Rate CDR With a Single LC VCO in 90 nm CMOS
Transmitter Linearization by Beamforming
A 220-GHz Sliding-IF Quadrature Transmitter and Receiver Chipset for High Data Rate Communication in 0.13-µm SiGe BiCMOS
On the Self-Generation of Electrical Soliton Pulses
Introduction to the Special Issue on the 2013 IEEE International Solid-State Circuits Conference
Opening the terahertz window with integrated diode circuits
A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy
A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology
A high-density dual-port memory cell operation and array architecture for ULSI DRAMs
A 76-mm 2 8-Mb chain ferroelectric memory
A high-selectivity continuous-time GaAs balanced filter
A 0.1-µm 1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation
Applications for GaAs and silicon integrated circuits in next generation wireless communication systems
A third-order ΔΣ modulator using second-order noise-shaping dynamic element matching
A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS
Background Noise and Process-Variation-Tolerant Sub-Microwatt Keyword Spotting Hardware Featuring Spike-Domain Division-Based Energy Normalization
A Fully Integrated Single-Ended 1.5-15-Hz Low-Pass Filter With Linear Tuning Law
An Integrated 256-Channel Epiretinal Prosthesis
A new structure of the 2-D silicon retina
Optimized test circuits for SER characterization of a manufacturing process
A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications
A 13.56 MHz Wireless Power Transfer System With Reconfigurable Resonant Regulating Rectifier and Wireless Power Control for Implantable Medical Devices
A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a
Highly testable design of BiCMOS logic circuits
A Noise-Cancelling Receiver Resilient to Large Harmonic Blockers
Introduction to the Special Section on the 2011 Asian Solid-State Circuits Conference (A-SSCC)
A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation
Doubly balanced dual-gate CMOS mixer
A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS
A flexible module library for custom DSP applications in a multiprocessor environment
A 2 GS/s Frequency-Folded ADC-Based Broadband Sampling Receiver
A CMOS Temperature Sensor With a Voltage-Calibrated Inaccuracy of ±0.15°C (3σ) From -55°C to 125°C
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS
A 20-GHz 1.9-mW LNA Using g m -Boost and Current-Reuse Techniques in 65-nm CMOS for Satellite Communications
An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips
Noise Reduction in CMOS Circuits Through Switched Gate and Forward Substrate Bias
T-PIM: An Energy-Efficient Processing-in-Memory Accelerator for End-to-End On-Device Training
A 5-10 GHz octave-band AlGaAs/GaAs HBT-Schottky diode down-converter MMIC
CMOS Single-Chip Electronic Compass With Microcontroller
An integrated silicon bipolar receiver subsystem for 900-MHz ISM band applications
A CMOS transistor-only 8-b 4.5-Ms/s pipelined analog-to-digital converter using fully-differential current-mode circuit techniques
A Switchable-Order G m -C Baseband Filter With Wide Digital Tuning for Configurable Radio Receivers
A 14 bit 200 MS/s DAC With SFDR > 78 dBc, IM3 < - 83 dBc and NSD < - 163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping
An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage
Design of fault diagnosable and repairable PLA's
Efficiency improvement in charge pump circuits
A 10-MHz Signal Bandwidth Cartesian Loop Transmitter Capable of Off-Chip PA Linearization
In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution
A Class-G Supply Modulator and Class-E PA in 130 nm CMOS
A 195 mW, 9.1 MVertices/s Fully Programmable 3-D Graphics Processor for Low-Power Mobile Devices
A ternary content addressable search engine
A Power-Efficient Two-Channel Time-Interleaved ΣΔ Modulator for Broadband Applications
A 0.791 mm 2 On-Chip Self-Aligned Comparator Controller for Boost DC-DC Converter Using Switching Noise Robust Charge-Pump
A Q-band monolithic balance resistive HEMT mixer using CPW/slotline balun
A monolithic current-mode CMOS DC-DC converter with on-chip current-sensing technique
Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits
A multimode PCM transceiver chip for 1.544-Mbit/s digital telecommunications
A 10.4 mW Electrical Impedance Tomography SoC for Portable Real-Time Lung Ventilation Monitoring System
A third-order ΣΔ modulator in 0.18-μm CMOS with calibrated mixed-mode integrators
Wide-Band RF Front End for SAW-Less Receivers Employing Active Feedback and Far Out-of-Band Blocker Rejection Circuit
A 10-Gb/s True Random Number Generator Using ML-Resistant Middle Square Method
High-Speed and Low-Power Design Techniques for TCAM Macros
Addition to "Development of a GaAs monolithic surface acoustic wave integrated circuit"
A LDO Regulator With Weighted Current Feedback Technique for 0.47 nF-10 nF Capacitive Load
A CCD programmable image processor and its neural network applications
A CMOS differential buffer amplifier with accurate gain and clipping control
Measurement of MOS current mismatch in the weak inversion region
A Wirelessly Powered Reconfigurable FDD Radio With On-Chip Antennas for Multi-Site Neural Interfaces
Compact, High Impedance and Wide Bandwidth Detectors for Characterization of Millimeter Wave Performance
Enhancing Efficiency in Piezoelectric Energy Harvesting: Collaborative-Flip Synchronized Switch Harvesting on Capacitors Rectifier and Multioutput DC-DC Converters Utilizing Shared Capacitors
A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale DVFS
A 65-nm CMOS 2×2 MIMO Multi-Band LTE RF Transceiver for Small Cell Base Stations
Design of low-voltage CMOS continuous-time filter with on-chip automatic tuning
Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters With 91% Peak Efficiency
A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET
Concurrent Design Analysis of High-Linearity SP10T Switch With 8.5 kV ESD Protection
Optimizing MOS transistor mismatch
Programmable analog vector-matrix multipliers
A 2-V 1.9-GHz Si down-conversion mixer with an LC phase shifter
Millimeter-wave voltage-controlled oscillators in 0.13-μm CMOS technology
A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features
A Multi-Gigabit CPFSK Polymer Microwave Fiber Communication Link in 40 nm CMOS
Relation Between Delay Line Phase Noise and Ring Oscillator Phase Noise
Power IC with EEPROM programmable switch mode regulators
GaAs ICs for high-speed signal processing
A one-wire approach for skew-compensating clock distribution based on bidirectional techniques
Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops
A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding
A 49.8-mm² IR-UWB Transmitter With Co-Designed Power Amplifier and Antenna for Neural Implants With Extended Transmission Range
Fully Integrated Switch-LNA Front-End IC Design in CMOS: A Systematic Approach for WLAN
A multibit test trigger circuit for megabit SRAMs
A Monolithic O-Band Coherent Optical Receiver for Energy-Efficient Links
Integrated Self-Adaptive and Power-Scalable Wideband Interference Cancellation for Full-Duplex MIMO Wireless
A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers