yusuke1997/dblp-id-title huggingface dataset:
A 5-to-8-GHz Wideband Miniaturized Dielectric Spectroscopy Chip With $I/Q$ Mismatch Calibration in 65-nm CMOS
SCARe: An SRAM-Based Countermeasure Against IC Recycling
Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond
Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems
A 64-Gb/s PAM-4 Optical Receiver With Amplitude/Phase Correction and Threshold Voltage/Data Level Calibration
SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation
An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications
Low-Complexity Distributed Arithmetic-Based Architecture for Inner-Product of Variable Vectors
Fast Scaling in the Residue Number System
An On-Chip Dynamically Obfuscated Wrapper for Protecting Supply Chain Against IP and IC Piracies
A Cost-Effective Fault Tolerance Technique for Functional TSV in 3-D ICs
Low-power realization of FIR filters on programmable DSPs
Current-Mode Triline Transceiver for Coded Differential Signaling Across On-Chip Global Interconnects
Threshold logic circuit design of parallel adders using resonant tunneling devices
Formal Modeling of Network-on-Chip Using CFSM and its Application in Detecting Deadlock
Hybrid Protection of Digital FIR Filters
Securet3d: An Adaptive, Secure, and Fault-Tolerant Aware Routing Algorithm for Vertically-Partially Connected 3D-NoC
A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic
An efficient VLSI architecture for 2-D wavelet image coding with novel image scan
Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing
Toeplitz Matrix Approach for Binary Field Multiplication Using Quadrinomials
CGADL: An Architecture Description Language for Coarse-Grained Reconfigurable Arrays
Path delay fault simulation of sequential circuits
Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems
FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^{m})$ and Their Applications in Trinomial Multipliers
Energy-Harvesting Circuits With a High-Efficiency Rectifier and a Low Temperature Coefficient Bandgap Voltage Reference
Partial Parity Cache and Data Cache Management Method to Improve the Performance of an SSD-Based RAID
VLSI Design of a Depth Map Estimation Circuit Based on Structured Light Algorithm
Scheduling of Data Access for the Radix-2k FFT Processor Using Single-Port Memory
Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI
A CAM with mixed serial-parallel comparison for use in low energy caches
Graph-Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP
A 65 nm Cryptographic Processor for High Speed Pairing Computation
A Flip-Flop for the DPA Resistant Three-Phase Dual-Rail Pre-Charge Logic Family
Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling
Synthesis of Fredkin-Toffoli reversible networks
Eliminating Synchronization Latency Using Sequenced Latching
An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC
A design system for on-chip oversampling A/D interfaces
Energy- and time-efficient matrix multiplication on FPGAs
Statistical clock skew modeling with data delay variations
Energy-efficient soft error-tolerant digital signal processing
Energy Consumption in RC Tree Circuits
RETA-AD: A Reconfigurable and Efficient Transformer Accelerator for Autonomous Driving
A CMOS Readout Circuit for Resistive Tactile Sensor Array Using Crosstalk Suppression and Nonuniformity Compensation Techniques
Performance and Security Analysis of Parameter-Obfuscated Analog Circuits
Design of a dynamic pipelined architecture for fuzzy color correction
Study on a Low-Complexity ECG Compression Scheme With Two-Tier Sensors
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization
High-Speed Implementation of ECC Scalar Multiplication in GF(p) for Generic Montgomery Curves
CROA: Design and Analysis of the Custom Rotary Oscillatory Array
Are Proximity Attacks a Threat to the Security of Split Manufacturing of Integrated Circuits?
3-D Compact Marchand Balun Design Based on Through-Silicon via Technology for Monolithic and 3-D Integration
Energy-aware wireless systems with adaptive power-fidelity tradeoffs
The design of an SRAM-based field-programmable gate array. I. Architecture
An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization
Design and Analysis of Approximate 4-2 Compressors for High-Accuracy Multipliers
Leakage current reduction in CMOS VLSI circuits by input vector control
An asynchronous ternary logic signaling system
Design, analysis, and evaluation of concurrent checking sorting networks
A modified Booth algorithm for high radix fixed-point multiplication
Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms
Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal Dependence
Mitigating the Impact of Variability on Chip-Multiprocessor Power and Performance
A Temperature Compensated Ring Oscillator With LC-Based Period Error Detection
An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits
Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation
A Highly Unified Reconfigurable Multicore Architecture to Speed Up NTT/INTT for Homomorphic Polynomial Multiplication
Compact NOI Nanodevice Simulation
Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches
Guest Editorial Securing IoT Hardware: Threat Models and Reliable, Low-Power Design Solutions
Memory power models for multilevel power estimation and optimization
A low power turbo/Viterbi decoder for 3GPP2 applications
Energy Optimized Subthreshold VLSI Logic Family With Unbalanced Pull-Up/Down Network and Inverse Narrow-Width Techniques
Design Methodologies for Yield Enhancement and Power Efficiency in SRAM-Based SoCs
Predictive Techniques for Projecting Test Data Volume Compression
An On-Chip Technique to Detect Hardware Trojans and Assist Counterfeit Identification
Microprocessor Aging Analysis and Reliability Modeling Due to Back-End Wearout Mechanisms
MMV: A Metamodeling Based Microprocessor Validation Environment
Mixed-Signal Computing for Deep Neural Network Inference
PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices
Survey and Analysis of Delay-Locked Loops Used in DRAM Interfaces
High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes
Nonideal battery and main memory effects on CPU speed-setting for low power
An area-saving decoder structure for ROMs
Power Scheduling With Active RC Power Grids
Computation of lower bounds for switching activity using decision theory
A 380-μW Electrochemical Impedance Measurement System for Protein Sensing
A Very Linear Low-Pass Filter with Automatic Frequency Tuning
A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector
A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors
Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device
Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders
EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control
Design Considerations for Reconfigurable Delay Circuit to Emulate System Critical Paths
SIXOR: Single-Cycle In-Memristor XOR
MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing
A High-Throughput Subspace Pursuit Processor for ECG Recovery in Compressed Sensing Using Square-Root-Free MGS QR Decomposition
Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance
A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition
A Novel Single-Inductor Dual-Input Dual-Output DC-DC Converter With PWM Control for Solar Energy Harvesting System
Thermal Optimization of Hybrid Cryogenic Computing Systems
Code Compression for VLIW Embedded Systems Using a Self-Generating Table
VLSI Architecture for Layered Decoding of QC-LDPC Codes With High Circulant Weight
Improving the Linearity and Power Efficiency of Active Switched-Capacitor Filters in a Compact Die Area
Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique
Minitaur, an Event-Driven FPGA-Based Spiking Network Accelerator
Tunnel FETs for Ultra-Low Voltage Digital VLSI Circuits: Part II-Evaluation at Circuit Level and Design Perspectives
Low-power encodings for global communication in CMOS VLSI
Guest Editorial Special Section on Configurable Computing Design- I: High-Level Reconfiguration
Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits
Thermal Simulator for Advanced Packaging and Chiplet-Based Systems
A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource Allocation
A Fourth-Order Tunable Bandwidth G m -C Filter for ECG Detection Achieving -7.9 dBV IIP3 Under a 0.5 V Supply
FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies
FPGA Based on Integration of CMOS and RRAM
Preweighted Linearized VCO Analog-to-Digital Converter
Hi-NeRF: A Multicore NeRF Accelerator With Hierarchical Empty Space Skipping for Edge 3-D Rendering
An RISC-V PPA-Fusion Cooperative Optimization Framework Based on Hybrid Strategies
An Intrinsic and Database-Free Authentication by Exploiting Process Variation in Back-End Capacitors
Stochastic Circuit Design and Performance Evaluation of Vector Quantization for Different Error Measures
Ultralow-Energy Variation-Aware Design: Adder Architecture Study
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)
Characterization and modeling of run-time techniques for leakage power reduction
The memory/logic interface in FPGAs with large embedded memory arrays
An adaptive message passing environment for water scale systems
Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops
Fast floorplanning for effective prediction and construction
Clustering for Processing Rate Optimization
A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation
Evaluation of Leakage Reduction Alternatives for Deep Submicron Dynamic Nonuniform Cache Architecture Caches
PUF-CIM: SRAM-Based Compute-In-Memory With Zero Bit-Error-Rate Physical Unclonable Function for Lightweight Secure Edge Computing
GreenTPU: Predictive Design Paradigm for Improving Timing Error Resilience of a Near-Threshold Tensor Processing Unit
Camouflaged Logic Gates Using Threshold-Voltage-Defined Memory Cells
Design of low-error fixed-width modified booth multiplier
Memory-Augmented Neural Networks on FPGA for Real-Time and Energy-Efficient Question Answering
Custom Networks-on-Chip Architectures With Multicast Routing
FEC-Aided Decision Feedback Blind Mismatch Calibration of TIADCs in Wireless Time-Varying Channel Environments
VLSI Architecture of Arithmetic Coder Used in SPIHT
Special section on the 2001 International Conference on Computer Design (ICCD)
On metrics for comparing interconnect estimation methods for FPGAs
A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories
A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable for 10-Gb/s I/O Links
A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture
Automatic Floorplanning and Standalone Generation of Bitstream-Level IP Cores
An Adaptive Maintain Power Signature (MPS) Scheme With Reusable Current Generator for Powered Device (PD)
An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory
A 600-mA, Fast-Transient Low-Dropout Regulator With Pseudo-ESR Technique in 0.18- m CMOS Process
Reliability-Aware Runtime Adaption Through a Statically Generated Task Schedule
Magnetic Domain-Wall Racetrack Memory-Based Nonvolatile Logic for Low-Power Computing and Fast Run-Time-Reconfiguration
PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration
Run-Time Reconfiguration of Expandable Cache for Embedded Systems
Interests and Limitations of Technology Scaling for Subthreshold Logic
Assertions for Protecting Mixed-Signal Latency Contracts in Power Management
An OOK and Binary FSK Reconfigurable Dual-Band Noncoherent IR-UWB Receiver Supporting Ternary Signaling
Testable Designs of Multiple Precharged Domino Circuits
Pausible clocking-based heterogeneous systems
An efficient BIST method for distributed small buffers
Energy and Lifetime Optimizations for Dark Silicon Manycore Microprocessor Considering Both Hard and Soft Errors
Bus-invert coding for low-power I/O
Exploiting Process Variability in Voltage/Frequency Control
Thermal-Constrained Task Scheduling on 3-D Multicore Processors for Throughput-and-Energy Optimization
Design Methodology for Global Resonant H-Tree Clock Distribution Networks
Accuracy Improvement of Energy Prediction for Solar-Energy-Powered Embedded Systems
Design and Low-Complexity Implementation of Matrix-Vector Multiplier for Iterative Methods in Communication Systems
High-throughput LDPC decoders
Mixed signal integrated circuits based on GaAs HEMTs
An efficient graph algorithm for FSM scheduling
A Soft Iterative Receiver With Simplified EP Detection for Coded MIMO Systems
Variation-Tolerant Dynamic Power Management at the System-Level
Graph-Based Transistor Network Generation Method for Supergate Design
All Digital Energy Sensing for Minimum Energy Tracking
Fast Analytic Electromigration Analysis for General Multisegment Interconnect Wires
Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation
Data Remapping for Static NUCA in Degradable Chip Multiprocessors
Ground bounce in digital VLSI circuits
Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI
Improved a priori interconnect predictions and technology extrapolation in the GTX system
High-Performance Low-Power Carry Speculative Addition With Variable Latency
Recovery-Aware Proactive TSV Repair for Electromigration Lifetime Enhancement in 3-D ICs
Data Conversion With Subgate-Delay Time Resolution Using Cyclic-Coupled Ring Oscillators
Fast factorization architecture in soft-decision Reed-Solomon decoding
A Spurious and Oscillator Pulling Free CMOS Quadrature LO-Generator for Cellular NB-IoT
Graph-Based Sparsification and Synthesis of Dense Matrices in the Reduction of RLC Circuits
Minimizing the complexity of SRT tables
Design of Testable Reversible Sequential Circuits
A framework for reconfigurable computing: task scheduling and context management
High-Throughput Pattern Matching With CMOL FPGA Circuits: Case for Logic-in-Memory Computing
M 2 -ViT: Accelerating Hybrid Vision Transformers With Two-Level Mixed Quantization
Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip
Facial Biometric for Securing Hardware Accelerators
A technique for Improving dual-output domino logic
Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture
Area-efficient high-speed decoding schemes for turbo decoders
An All-MOSFET Sub-1-V Voltage Reference With a - 51 -dB PSR up to 60 MHz
Power estimation in adiabatic circuits: a simple and accurate model
A 20-V Pulse Driver Based on All-nMOS Charge Pump Without Reversion Loss and Overstress in 65-nm Standard CMOS Technology
Digitally Assisted Built-In Tuning Using Hamming Distance Proportional Signatures in RF Circuits
Harmonic-Summing Module of SKA on FPGA - Optimizing the Irregular Memory Accesses
Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder
A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump
Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization
Efficient Architecture for Soft-Input Soft-Output Sphere Detection With Perfect Node Enumeration
A Forwarded Clock Receiver Based on Injection-Locked Oscillator With AC-Coupled Clock Multiplication Unit in 0.13~µm CMOS
Inductive properties of high-performance power distribution grids
Power-Gated 9T SRAM Cell for Low-Energy Operation
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic
A Novel Architecture for Block Interleaving Algorithm in MB-OFDM Using Mixed Radix System
Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application
Exploring the Usage of Fast Carry Chains to Implement Multistage Ring Oscillators on FPGAs: Design and Characterization
Gbit/s lossless data compression hardware
A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters
Efficient Code Compression for Embedded Processors
Compact Test Generation With an Influence Input Measure for Launch-On-Capture Transition Fault Testing
Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear Arithmetic Codes
A 4 × 10 Gb/s Adaptive Optical Receiver Utilizing Current-Reuse and Crosstalk-Remove
Resource-Efficient SRAM-Based Ternary Content Addressable Memory
Data-Pattern-Aware Error Prevention Technique to Improve System Reliability
Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies
A Novel Prediction-Based Two-Tiered ECC for Mitigating SWD Errors in HBM
Low-Complexity Tone Reservation for PAPR Reduction in OFDM Communication Systems
AxPPA: Approximate Parallel Prefix Adders
Low-Energy Write Operation for 1T-1MTJ STT-RAM Bitcells With Negative Bitline Technique
Efficient simulation of nonuniform transmission lines using integrated congruence transform
Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology
Exploiting Inherent Error Resiliency of Deep Neural Networks to Achieve Extreme Energy Efficiency Through Mixed-Signal Neurons
A Cost-Effective Per-Pin ALPG for High-Speed Memory Testing
Checkpointing for Virtual Platforms and SystemC-TLM
Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings
Hardware-Accelerator Design by Composition: Dataflow Component Interfaces With Tydi-Chisel
A Self-Powered High-Efficiency Rectifier With Automatic Resetting of Transducer Capacitance in Piezoelectric Energy Harvesting Systems
A 9-Bit 70-MS/s Two-Stage SAR ADC With Passive Residue Transfer
Low Routing Complexity Multiframe Pipelined LDPC Decoder Based on a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput Applications
Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling
Self-Repairing SRAM Using On-Chip Detection and Compensation
An Electrical-Thermal Co-Simulation Model of Chiplet Heterogeneous Integration Systems
A 12-Bit Two-Step Single-Slope ADC With a Constant Input-Common-Mode Level Resistor Ramp Generator
Approximating Beyond the Processor: Exploring Full-System Energy-Accuracy Tradeoffs in a Smart Camera System
An Efficient Accelerator for Multiple Convolutions From the Sparsity Perspective
Energy management for battery-powered reconfigurable computing platforms
A Novel Delta Sigma Control System Processor and Its VLSI Implementation
A heuristic for decomposition in multilevel logic optimization
Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing
Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered Compares
Toward Self-Tunable Approximate Computing
A Multi-Resolution Fast Filter Bank for Spectrum Sensing in Military Radio Receivers
Sparse Vector-Matrix Multiplication Acceleration in Diode-Selected Crossbars
Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS
A Digitally Testable Sigma -Delta Modulator Using the Decorrelating Design-for-Digital-Testability
Power Consumption of Fault Tolerant Busses
Design of ultrahigh-speed low-voltage CMOS CML buffers and latches
Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures
GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering
Two-State Checkpointing for Energy-Efficient Fault Tolerance in Hard Real-Time Systems
Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply
Modified Booth algorithm for high radix fixed-point multiplication
Virtual Prototyper (ViPro): An SRAM Design Tool for Yield Constrained Optimization
Interconnect Lifetime Prediction for Reliability-Aware Systems
FARMER: Online-Learning-Based Workload Consolidation on Large FPGAs Accelerated With Dynamic Partial Reconfiguration
Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs
Pipelining with common operands for power-efficient linear systems
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering
Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing
Algorithm and Architecture Design of a Hardware-Efficient Frame Rate Upconversion Engine
Design Migration From Peripheral ASIC Design to Area-I/O Flip-Chip Design by Chip I/O Planning and Legalization
High performance low power array multiplier using temporal tiling
Efficient Design of a Hybrid Adder in Quantum-Dot Cellular Automata
Single- and Multi-core Configurable AES Architectures for Flexible Security
A Digital CMOS Parallel Counter Architecture Based on State Look-Ahead Logic
1-V 365-µW 2.5-MHz Channel Selection Filter for 3G Wireless Receiver in 55-nm CMOS
Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs
Reconfigurable Architecture for Network Flow Analysis
A Comparison of Automated RF Circuit Design Methodologies: Online Versus Offline Passive Component Design
An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic
Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System
The Transmogrifier-2: a 1 million gate rapid-prototyping system
Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection
Transition Skew Coding for Global On-Chip Interconnect
Streaming Dilated Convolution Engine
Technology mapping for high-performance static CMOS and pass transistor logic designs
A 270-mA Self-Calibrating-Clocked Output-Capacitor-Free LDO With 0.15-1.15V Output Range and 0.183-fs FoM
Trainable and Low-Cost SMO Pattern Classifier Implemented via MCMC and SFBS Technologies
A Pairwise Swap Enabled Randomized DEM Addressing Intersegment Mismatch for Current Steering Digital-to-Analog Converters
Comments on "A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula"
Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications
FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs
A Self-Calibrated Unified Voltage-and-Frequency Regulator System Design Based on Universal Logic Line Circuit
A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes
Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation
Low-Complexity Reliability-Based Message-Passing Decoder Architectures for Non-Binary LDPC Codes
Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs
Autoscan: a scan design without external scan inputs or outputs
Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus
A Hardware-Efficient Synchronization in L-DACS1 for Aeronautical Communications
A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC
Yield-Driven Near-Threshold SRAM Design
An Efficient Massive MIMO Detector Based on Approximate Expectation Propagation
An External Capacitor-Less Ultralow-Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power-Supply Rejection Over a Wide Range of Load Current
ASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits