yusuke1997/dblp-id-title huggingface dataset:
A Carrier-Independent Non-Data-Aided Real-Time SNR Estimator for M-PSK and D-MPSK Suitable for FPGAs and ASICs
VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture
Robust stability and stabilizability of uncertain linear hybrid systems with state delays
On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators
Decoder Design for RS-Based LDPC Codes
Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System
Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals
Low Complexity Implementation of Unified Systolic Multipliers for NIST Pentanomials and Trinomials Over GF(2 m )
A Stable Loss Control Feedback Loop for VCO Amplitude Tuning
Hyperchaotic spiking oscillators with periodic pulse-train input
An ARMA-Model-Based NTF Estimation on Continuous-Time ΔΣ Modulators
A 0.4-to-1 V Voltage Scalable ΔΣ ADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS
Nanopower, Sub-1 V, CMOS Voltage References With Digitally-Trimmable Temperature Coefficients
Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST
Multi-Mode Unrolled Architectures for Polar Decoders
A Generalized Model of Noise Driven Circuits with Application to Stochastic Resonance
Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation
A Novel Thresholding Methodology Using WSI EMD and Adaptive Homomorphic Filter
A Distributed Power Delivery Grid Based on Analog-Assisted Digital LDOs With Cooperative Regulation and IR-Drop Reduction
Output Group Synchronization for Networks of Heterogeneous Linear Systems Under Internal Model Principle
The effects of mismatch in Gm-C polyphase filters
Low-voltage-swing monolithic dc-dc conversion
A Reconfigurable Accelerator for Smith-Waterman Algorithm
A New Spectrum Sensing Method Using Output Analysis of the PFD
On the Static Resolution of Digitally Corrected Analog-to-Digital and Digital-to-Analog Converters With Low-Precision Components
Modeling and Mitigating Time-Dependent Variability From the Physical Level to the Circuit Level
Logic Obfuscation Through Enhanced Threshold Voltage Defined Logic Family
An Efficient Post-Processor for Lowering the Error Floor of LDPC Codes
Quantized Fuzzy Finite-Time Control for Nonlinear Semi-Markov Switching Systems
Optimal controller of a buck DC-DC converter using the uncertain load as stochastic noise
Exploiting Programmable Temperature Compensation Devices to Manage Temperature-Induced Delay Uncertainty
A Constant- g m Constant-Slew-Rate Rail-to-Rail Input Stage With Static Feedback and Dynamic Current Steering for VLSI Cell Libraries
Inter-Reciprocity Principles for Linear Network- Waveguides Systems Based on Generalized Scattering, Admittance and Impedance Matrices
Reliability Analysis of Large Circuits Using Scalable Techniques and Tools
Complete characterization of systems for simultaneous Lagrangian upsampling and fractional-sample delaying
A Frequency-Selective Broadband Low-Noise Amplifier With Double-Loop Transformer Feedback
A 5-Bit 500-MS/s Asynchronous Digital Slope ADC With Two Comparators
CMOS Transimpedance Amplifier for Gigabit-per-Second Optical Wireless Communications
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System
A Differential Approach for Obtaining Diagonal Volterra Kernels
H ∞ } Filtering for Nonlinear Singular Systems
A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on a Radix-2 Decimation-In-Frequency Algorithm
Method to Design General RNS Reverse Converters for Extended Moduli Sets
Spur-Suppression Techniques for Frequency Synthesizers
VLSI Block Placement With Alignment Constraints
The Design of Fast-Settling Three-Stage Amplifiers Using the Open-Loop Damping Factor as a Design Parameter
Harmonic-Based Nonlinearity Factorization of Switching Behavior in Up-Conversion Mixers
Design Approach for Ring Amplifiers
Multiple Pinch-Off Points in Memristive Equations: Analysis and Experiments
On the implementation of input-feedforward delta-sigma modulators
On MultiModuli residue number systems with moduli of forms r a , r b -1, r c +1
Available Transfer Capability Calculation Using a Smoothing Pointwise Maximum Function
Weight-Oriented Approximation for Energy-Efficient Neural Network Inference Accelerators
Similarity-Based and Sybil Attack Defended Community Detection for Social Networks
Frequency-domain modeling of integrated electromagnetic power passives by a generalized two-conductor transmission structure
Sliding-Mode Amplitude Control Techniques for Harmonic Oscillators
Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm
Ultralow-Power Electronics for Cardiac Monitoring
Novel Nonsingular Terminal Sliding Mode Control for Multi-Agent Tracking Systems With Application to Jerk Circuit
Synchronization of Complex Dynamical Networks With Time-Varying Delays Via Impulsive Distributed Control
Novel pseudo-exponential circuits
A Fully Serial-In Parallel-Out Digit-Level Finite Field Multiplier in 𝔽 2 m Using Redundant Representation
Analytical Phase-Noise Modeling and Charge Pump Optimization for Fractional-N PLLs
A Sub-500 mV Highly Efficient Active Rectifier for Energy Harvesting Applications
New object-oriented segmentation algorithm based on the CNN paradigm
An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops
A Robust and Scalable Constant- g m Rail-to-Rail CMOS Input Stage With Dynamic Feedback for VLSI Cell Libraries
A CMOS Integrated W-band Passive Imager
Systematic design of double-sampling ΣΔ A/D converters with a modified noise transfer function
An Inductorless DC-DC Converter for Energy Harvesting With a 1.2-µW Bandgap-Referenced Output Controller
All-Digital Transmitter Architecture Based on Two-Path Parallel 1-bit High Pass Filtering DACs
Single-stage electronic ballast with class-E rectifier as power-factor corrector
A Low-Power High-Data-Rate ASK IF Receiver With a Digital-Control AGC Loop
Least-Squares-Based Switching Structure for Lossless Image Coding
Variable Latency Speculative Han-Carlson Adder
Design of Low-Power Non-Binary LDPC Decoder Exploiting DRAM Refresh Rate Over-Scaling
A Low Power Localized 2T1R STT-MRAM Array With Pipelined Quad-Phase Saving Scheme for Zero Sleep Power Systems
Complex Floating Point - A Novel Data Word Representation for DSP Processors
Memory Efficient Decoder Architectures for Quasi-Cyclic LDPC Codes
A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS
Linear Equalization and PVT-Independent DC Wander Compensation for AC-Coupled PCIe 3.0 Receiver Front End
A 100-Gbps 4-Lane Transceiver for 47-dB Loss Copper Cable in 28-nm CMOS
Practical Realization of Tunable Fractional Order Parallel Resonator and Fractional Order Filters
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT
Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique
40-Gb/s 0.7-V 2: 1 MUX and 1: 2 DEMUX with Transformer-Coupled Technique for SerDes Interface
Chameleon: a dual-mode 802.11b/Bluetooth receiver system design
Noniterative WLS design of allpass variable fractional-delay digital filters
A 10.6 pJ⋅K 2 Resolution FoM Temperature Sensor Using Astable Multivibrator
Architecture and Implementation of a Low-Power LVDS Output Buffer for High-Speed Applications
Current Mode Image Sensor With Improved Linearity and Fixed-Pattern Noise
Nonideal Behavior of Analog Multipliers for Chaos Generation
One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation
Output Filter Aware Optimization of the Noise Shaping Properties of ΔΣ Modulators Via Semi-Definite Programming
Low-Power SiGe BiCMOS Transimpedance Amplifier for 25-GBaud Optical Links
Distributed Robust Synchronization of Dynamical Networks With Stochastic Coupling
A 10-MHz Bandwidth Two-Path Third-Order ΣΔ Modulator With Cross-Coupling Branches
Analysis of Resonance and Anti-Resonance Frequencies in a Wireless Power Transfer System: Analytical Model and Experiments
A High-Precision Time Skew Estimation and Correction Technique for Time-Interleaved ADCs
A Phase and Amplitude Tunable Quadrature LC Oscillator: Analysis and Design
Offset-Cancellation Sensing-Circuit-Based Nonvolatile Flip-Flop Operating in Near-Threshold Voltage Region
A 1.2-GHz Comparator With Adaptable Offset in 0.35- mum CMOS
A Gaussian Approximation of High-Order Distortion Spectrum in Broadband Amplifiers
Multi-Resolution Modeling of Power Electronics Circuits Using Model-Order Reduction Techniques
Adaptive Event-Triggered Predictive Control for Finite Time Microgrid
On the Signal Filtering Property of CT Incremental Sigma-Delta ADCs
Iterative method for the design of DFT filter Bank
Exploiting Sensitivity Enhancement in Micro-wave Planar Sensors Using Intermodulation Products With Phase Noise Analysis
Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio
Rejection of Nonharmonic Disturbances in Nonlinear Systems With Semi-Global Stability
A 280 Mb/s In-Vehicle LAN System Using Electromagnetic Clip Connector and High-EMC Transceiver
A 5 Gb/s Voltage-Mode Transmitter Using Adaptive Time-Based De-Emphasis
A Low-Power Implementation of Asynchronous 8051 Employing Adaptive Pipeline Structure
An Architecture to Accelerate Convolution in Deep Neural Networks
A frequency aliasing approach to chaos-based cryptosystems
A Mismatch-Immune 12-Bit SAR ADC With Completely Reconfigurable Capacitor DAC
Randomness Enhancement Using Digitalized Modified Logistic Map
Low-Complexity Tree Architecture for Finding the First Two Minima
Signal Encoding and Processing in Continuous Time Using a Cascade of Digital Delays
High Data Rate Discrete-Cosine-Spreading Aided M-Ary Differential Chaos Shift Keying Scheme With Low PAPR
40 nm CMOS Ultra-Low Power Integrated Gas Gauge System for Mobile Phone Applications
A High-Efficiency Split-Merge Charge Pump for Solar Energy Harvesting
A mixed-signal GFSK demodulator for Bluetooth
An FPGA-Based Unscented Kalman Filter for System-On-Chip Applications
Bias-and-Input Interchanging Technique for Cyclic/Pipelined ADCs With Opamp Sharing
Wiener's Analysis of the Discrete-Time Phase-Locked Loop With Loop Delay
An Efficient Multi-Standard LDPC Decoder Design Using Hardware-Friendly Shuffled Decoding
Modeling of V 2 Current-Mode Control
Linear Optimal Estimation for Discrete-Time Measurement Delay Systems With Multichannel Multiplicative Noise
An Improved High Linearity Active CMOS Mixer: Design and Volterra Series Analysis
System Design and Performance Analysis of Orthogonal Multi-Level Differential Chaos Shift Keying Modulation Scheme
A Fast Polar Code List Decoder Architecture Based on Sphere Decoding
An on-off Temporal Filter Circuit for Computing Motion Energy
PWL Current-Mode CMOS Exponential Circuit Based on Maximum Operator
A High Efficiency LCC-S Compensated WPT System With Dual Decoupled Receive Coils and Cascaded PWM Regulator
Tapered-Vth Approach for Energy-Efficient CMOS Buffers
A 3.1-4.8-GHz IR-UWB All-Digital Pulse Generator With Variable Channel Selection in 0.13-µm CMOS Technology
Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density
A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection
A 0.8-V 4.9-mW 1.2-GHz CMOS Fractional-N Frequency Synthesizer for UHF RFID Readers
Superior Execution Time Design of a Space/Spatial-Frequency Optimal Filter for Highly Nonstationary 2D FM Signal Estimation
Digital Multiplierless Realization of a Calcium-Based Plasticity Model
The Effect of Mismatches and Delay on the Quadrature Error of a Cross-Coupled Relaxation Oscillator
Power Analysis of One-Ports Under Periodic Multi-Sinusoidal Linear Operation
Integrated Output Matching Networks for Class-J/J -1 Power Amplifiers
High Precision Synthesis of a Richards Immittance Via Parametric Approach
256 × 8 SPAD Array With 256 Column TDCs for a Line Profiling Laser Radar
Perturbation analysis of nonlinear distortion in analog integrated circuits
High-performance error amplifier for fast transient DC-DC converters
A comparative study of sound localization algorithms for energy aware sensor network nodes
Symbolic Analysis of Analog Circuits By Boolean Logic Operations
An Extension of the Cayley-Hamilton Theorem to Different Orders Fractional Linear Systems and Its Application to Electrical Circuits
An Adaptive-Resolution Quasi-Level-Crossing Delta Modulator With VCO-Based Residue Quantizer
Modeling of the Electrical Conductivity of DNA
Extended Dissipative Control for Singularly Perturbed PDT Switched Systems and its Application
Robust Quasi-Newton Adaptive Filtering Algorithms
A Programmable Edge-Combining DLL With a Current-Splitting Charge Pump for Spur Suppression
Performance of an SIMO FM-DCSK Communication System
A Standard-Cell-Based All-Digital PWM Modulator With High Resolution and Spread- Spectrum Capability
Reducing Phase Noise in Multi-Phase Oscillators
Sampling-Induced Border Collision Bifurcation in a Voltage-Mode DPWM Synchronous Buck Converter
Split ADC Based Fully Deterministic Multistage Calibration for High Speed Pipeline ADCs
Dismantling and Vertex Cover of Network Through Message Passing
A Low Phase Noise and Wide Tuning Range Millimeter-Wave VCO Using Switchable Coupled VCO-Cores
Iterative Learning Control for Multi-Agent Systems With Finite-Leveled Sigma-Delta Quantization and Random Packet Losses
Efficient VLSI Architecture for Decimation-in-Time Fast Fourier Transform of Real-Valued Data
Highly Linear Tunable CMOS Gmhbox-C Low-Pass Filter
Analysis of the Σ-Δ pulsed digital oscillator for MEMS
Dynamical System Guided Mapping of Quantitative Neuronal Models Onto Neuromorphic Hardware
Regulated Common-Gate Transimpedance Amplifier Designed to Operate With a Silicon Photo-Multiplier at the Input
Global asymptotic stability and global exponential stability of neural networks with unbounded time-varying delays
High-Efficiency Class-E Power Amplifier With Shunt Capacitance and Shunt Filter
Desensitized Half-Band Filters
Power-Handling Capacity and Nonlinearity Analysis for Distributed Electronic Impedance Synthesizer
Sparse Adaptive Filtering by an Adaptive Convex Combination of the LMS and the ZA-LMS Algorithms
A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications
Power Management Analysis of Inductively-Powered Implants with 1X/2X Reconfigurable Rectifier
Flexible hardware-friendly digital architecture for 2-D separable convolution-based scaling
A Power-Efficient Configurable Low-Complexity MIMO Detector
A Defect Tolerance Scheme for Nanotechnology Circuits
A New Transform-Domain Regularized Recursive Least M-Estimate Algorithm for a Robust Linear Estimation
A Reconfigurable Multi-Transform VLSI Architecture Supporting Video Codec Design
An Unfolded Pipelined Polar Decoder With Hybrid Number Representations for Multi-User MIMO Systems
Corrections to "Design and Performance Analysis of a Unified, Reconfigurable HMAC-Hash Unit" [Dec 07 2683-2695]
An Active Matrix Micro-Pixelated LED Display Driver for High Luminance Uniformity Using Resistance Mismatch Compensation Method
Mixed K-Dissipativity and Stabilization to ISS for Impulsive Hybrid Systems
Universal Hardware for Systems With Acceptable Representations as Low Order Polynomials
Generic Wireless Power Transfer and Data Communication System Based on a Novel Modulation Technique
Closed-Form Design of CIC Compensators Based on Maximally Flat Error Criterion
Power Supply Noise in Analog Audio Class D Amplifiers
A Novel Digital-Intensive Hybrid Polar-I/Q RF Transmitter Architecture
An All-Digital Fast-Locking Programmable DLL-Based Clock Generator
Corrections to "LMI-based Approach for Asymptotically Stability Analysis of Delayed Neural Networks"
Reference-Adaptive CDSK: An Enhanced Version of Correlation Delay Shift Keying
A Submicrowatt Implantable Capacitive Sensor System for Biomedical Applications
A Near-Threshold Voltage Oriented Digital Cell Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS Process
A Linear Programming Based Tone Injection Algorithm for PAPR Reduction of OFDM and Linearly Precoded Systems
On an inviable approach for derivation of 2-D stability tests
Practical measurement of timing jitter contributed by a clock-and-data recovery circuit
A Darlington-Enhanced CMOS Oscillator Architecture
A Multi-Channel Low-Noise Analog Front End Circuit for Linear LADAR
A Power-Efficient Tunable Narrow-Band Digital Front End for Bandpass Sigma-Delta ADCs in Digital FM Receivers
A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta-Sigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation
A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s
Convergence analysis of the cascade second-order adaptive line equalizer
Lyapunov Theory-Based Multilayered Neural Network
Spatio-Temporal Bias-Tunable Readout Circuit for On-Chip Intelligent Image Processing
One-Shot Non-Intrusive Calibration Against Process Variations for Analog/RF Circuits
Controllability and reachability of 2-D positive systems: a graph theoretic approach
Broadband Fully Integrated GaN Power Amplifier With Minimum-Inductance BPF Matching and Two-Transistor AM-PM Compensation
A background timing-skew calibration technique for time-interleaved analog-to-digital converters
On Brune's Tests
Design of low-voltage MOSFET-only ΣΔ modulators in standard digital CMOS technology
Design Methodology for Domain Specific Parameterizable Particle Filter Realizations
Cascade Structure of Narrow Equiripple Bandpass FIR Filters
On the Maximum Efficiency of Systems Containing Multiple Sources
A Repetitive-Based Controller for a Power Factor Precompensator
Analysis and Design of Power Harvesting Circuits for Ultra-Low Power Applications
Advances in active-feedback frequency compensation with power optimization and transient improvement
256 × TDC Array With Cyclic Interpolators Based on Calibration-Free 2× Time Amplifier
Synchronization in Moving Pulse-Coupled Oscillator Networks
A Comparative Study of Loop Filter Alternatives in Second-Order High-Pass ΔΣ Modulators
Analysis, Design, Modeling, and Implementation of an Active Clamp HF Link Converter
A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications
Analysis and Design of a Low-Voltage, Low-Power, High-Precision, Class-AB Current-Mode Subthreshold CMOS Sample and Hold Circuit
A Switch-Resistance-Aware Dickson Charge Pump Model for Optimizing Clock Frequency
Nonlinear dynamical systems control using a new RNN temporal learning strategy
Hybrid ΣΔ modulators with adaptive calibration
An Ultra-Wideband Digitally Programmable Power Amplifier With Efficiency Enhancement for Cellular and Emerging Wireless Communication Standards
Full Passive UHF Tag With a Temperature Sensor Suitable for Human Body Temperature Monitoring
Broad-Band Odd-Number CMOS Prescalers With Quadrature/Symmetrical Outputs
A New Control Law Based on the Differential Flatness Principle for Multiphase Interleaved DC-DC Converter
RF CMOS low-phase-noise LC oscillator through memory reduction tail transistor
Linearization Technique for Source-Degenerated CMOS Differential Transconductors
Design and Analysis of Compressive Sensing-Based Lightweight Encryption Scheme for Multimedia IoT
A Fast, Sigma-Delta (Sigma Delta) Boost DC-DC Converter Tolerant to Wide LC Filter Variations
New Divider Design for Stochastic Computing
A Discrete-Time RF Signal-Processing Technique for Blocker-Tolerant Receivers With Wide Instantaneous Bandwidth
Analysis and Design of Integrated Voltage Regulators for Supply Noise Rejection During System-Level ESD
A 4.7-Gb/s Reconfigurable CMOS Imaging Optical Receiver Utilizing Adaptive Spectrum Balancing Equalizer
CORDIC-SNN: On-FPGA STDP Learning With Izhikevich Neurons
Design of a High-Throughput QC-LDPC Decoder With TDMP Scheduling
Subgradient-Based Neural Networks for Nonsmooth Convex Optimization Problems
How Can the Hysteresis Loop of the Ideal Memristor Be Pinched?
Digital Valley V 2 Control for Boost Converter With Fast Load-Transient Performance
A Predetermined LMS Digital Background Calibration Technique for Pipelined ADCs
A Look-Ahead Clock Gating Based on Auto-Gated Flip-Flops
Conditions for Existence of Equilibria of Systems With Constant Power Loads
A Laser-Trimmed Rail-to-Rail Precision CMOS Operational Amplifier
Cryptographic applications of Brahmagupta-Bhãskara equation
High-performance and simple CMOS interface circuit for differential capacitive sensors
Event-Driven Modeling of CDR Jitter Induced by Power-Supply Noise, Finite Decision-Circuit Bandwidth, and Channel ISI
A Low-Energy Machine-Learning Classifier Based on Clocked Comparators for Direct Inference on Analog Sensors
Wireless Power Transfer With Three-Ports Networks: Optimal Analytical Solutions
A Wide-Locking-Range Dual Injection-Locked Frequency Divider With an Automatic Frequency Calibration Loop in 65-nm CMOS
A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design
Projection Recurrent Neural Network Model: A New Strategy to Solve Maximum Flow Problem
Mitigation of "Horn Spurs" in a MASH-Based Fractional-N CP-PLL
Monolithic Low-Power 6-Gb/s Optical Transmitter for a Silicon HBT-Based Carrier Injection Electroabsorption Modulator
Automatic Tuning of Time Constants in Continuous-Time Delta-Sigma Modulators
A 0.8-V, 1-MS/s, 10-bit SAR ADC for Multi-Channel Neural Recording
A 0.008 mm 2 500 µW 469 kS/s Frequency-to-Digital Converter Based CMOS Temperature Sensor With Process Variation Compensation
SIBAM - Sign Inclusive Broken Array Multiplier Design for Error Tolerant Applications
Accurate modeling of noise in switched-C ΔΣ analog-to-digital converters
Adaptive Time-Interleaved ADC Offset Compensation by Nonwhite Data Chopping
Pulse frequency modulation based CMOS image sensor for subretinal stimulation
A 0.2 V 32-Kb 10T SRAM With 41 nW Standby Power for IoT Applications
High-Q Bandstop Filters Exploiting Acoustic-Wave-Lumped-Element Resonators (AWLRs)
A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator
Generalized Correntropy Induced Metric Memory-Improved Proportionate Affine Projection Sign Algorithm and Its Combination
Medium-Grain Cells for Reconfigurable DSP Hardware
Improving Architectures of Binary Signed-Digit CORDIC With Generic/Specific Initial Angles
Design of a CML Transceiver With Self-Immunity to EMI in 0.18-µm CMOS
A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized G m -C Biquad in 0.13-mu m CMOS
A 38 pJ/b Optimal Soft-MIMO Detector
Recursive Minimum Kernel Mixture Mean p-Power Error Algorithm Based on the Nyström Method
Process/Temperature Variation Tolerant Precision Signal Strength Indicator
Gastric Seed: Toward Distributed Ultrasonically Interrogated Millimeter-Sized Implants for Large-Scale Gastric Electrical-Wave Recording
Design of a power-reduction Viterbi decoder for WLAN applications
A CMOS 1.6 GHz Dual-Loop PLL With Fourth-Harmonic Mixing
SiGe Analog AGC Circuit for an 802.11a WLAN Direct Conversion Receiver
An Area and Energy Efficient Inner-Product Processor for Serial-Link Bus Architecture
Termination Sequence Generation Circuits for Low-Density Parity-Check Convolutional Codes
Global asymptotic stability of a class of neural networks with distributed delays
A Krein Space Approach to H ∞ Filtering of Discrete-Time Nonlinear Systems
An Efficient Method for Large-Scale Gate Sizing
Perfect Blind-Channel Shortening for Multicarrier Systems
Algorithms for a Sparse Reconfigurable Adaptive Filter and a Photonic Switch Architecture
Transformer-Based Dual-Mode Voltage-Controlled Oscillators
Two-Dimensional Antisymmetric Linear Phase Filter Bank Construction Using Symmetric Completion
A Subthreshold Buffer-Based Biquadratic Cell and its Application to Biopotential Filter Design