yusuke1997/dblp-id-title huggingface dataset:
DUCATI: High-performance Address Translation by Extending TLB Reach of GPU-accelerated Systems
ShuffleInfer: Disaggregate LLM Inference for Mixed Downstream Workloads
The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing
A Conflict-free Scheduler for High-performance Graph Processing on Multi-pipeline FPGAs
A case for a complexity-effective, width-partitioned microarchitecture
IR2VEC: LLVM IR Based Scalable Program Embeddings
Solving Sparse Assignment Problems on FPGAs
Designing a Tunable Nested Data-Parallel Programming System
DTAP: Accelerating Strongly-Typed Programs with Data Type-Aware Hardware Prefetching
Automated Fine-Grained CPU Provisioning for Virtual Machines
Design and Evaluation of an Ultra Low-power Human-quality Speech Recognition System
NEM-GNN: DAC/ADC-less, Scalable, Reconfigurable, Graph and Sparsity-Aware Near-Memory Accelerator for Graph Neural Networks
COWS for High Performance: Cost Aware Work Stealing for Irregular Parallel Loop
Improving Thread-level Parallelism in GPUs Through Expanding Register File to Scratchpad Memory
A Pressure-Aware Policy for Contention Minimization on Multicore Systems
Effective Transactional Memory Execution Management for Improved Concurrency
Memory-Side Protection With a Capability Enforcement Co-Processor
Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories
Bringing Parallel Patterns Out of the Corner: The P 3 ARSEC Benchmark Suite
Caliper: Interference Estimator for Multi-tenant Environments Sharing Architectural Resources
9Ring: A 3D-Stacked Memory-Based Accelerator for Flexible and Efficient Deep CNN Applications
API compilation for image hardware accelerators
Metric Selection for GPU Kernel Classification
Schedule Synthesis for Halide Pipelines through Reuse Analysis
Improving performance of nested loops on reconfigurable array processors
On the Anatomy of Predictive Models for Accelerating GPU Convolution Kernels and Beyond
CompEx++: Compression-Expansion Coding for Energy, Latency, and Lifetime Improvements in MLC/TLC NVMs
A Filtering Mechanism to Reduce Network Bandwidth Utilization of Transaction Execution
A Bimodal Scheduler for Coarse-Grained Reconfigurable Arrays
Simplifying Transactional Memory Support in C++
NUMA-Caffe: NUMA-Aware Deep Learning Neural Networks
Exploiting Dynamic Regular Patterns in Irregular Programs for Efficient Vectorization
Irregular Register Allocation for Translation of Test-pattern Programs
A Lock-free RDMA-friendly Index in CPU-parsimonious Environments
Simultaneous Multi-Layer Access: Improving 3D-Stacked Memory Bandwidth at Low Cost
Improving the Efficiency of GPGPU Work-Queue Through Data Awareness
The gradient-based cache partitioning algorithm
Comparative evaluation of memory models for chip multiprocessors
Hiding the misprediction penalty of a resource-efficient high-performance processor
TianheGraph: Topology-aware Graph Processing
Conflict Management in Vector Register Files
Mentor: A Memory-Efficient Sparse-dense Matrix Multiplication Accelerator Based on Column-Wise Product
Polyhedral parallelization of binary code
Understanding the behavior and implications of context switch misses
HAP: Hybrid-Memory-Aware Partition in Shared Last-Level Cache
A decoupled non-SSA global register allocation using bipartite liveness graphs
Matrix: Multi-Cipher Structures Dataflow for Parallel and Pipelined TFHE Accelerator
FluidCheck: A Redundant Threading-Based Approach for Reliable Execution in Manycore Processors
Data Deduplication Based on Content Locality of Transactions to Enhance Blockchain Scalability
Phronesis: Efficient Performance Modeling for High-dimensional Configuration Tuning
MINIME-GPU: Multicore Benchmark Synthesizer for GPUs
DCMA: Accelerating Parallel DMA Transfers with a Multi-Port Direct Cached Memory Access in a Massive-Parallel Vector Processor
Shift-CIM: In-SRAM Alignment To Support General-Purpose Bit-level Sparsity Exploration in SRAM Multiplication
RFVP: Rollback-Free Value Prediction with Safe-to-Approximate Loads
ReSA: Reconfigurable Systolic Array for Multiple Tiny DNN Tensors
Low Complexity Multiply-Accumulate Units for Convolutional Neural Networks with Weight-Sharing
Implementing branch-predictor decay using quasi-static memory cells
Memory-access-aware Safety and Profitability Analysis for Transformation of Accelerator-bound OpenMP Loops
XEngine: Optimal Tensor Rematerialization for Neural Networks in Heterogeneous Environments
Energy-Efficient Compilation of Irregular Task-Parallel Loops
An energy-efficient method of supporting flexible special instructions in an embedded processor with compact ISA
Energy-Performance Considerations for Data Offloading to FPGA-Based Accelerators Over PCIe
VLIW instruction scheduling for minimal power variation
WaFFLe: Gated Cache-Ways with Per-Core Fine-Grained DVFS for Reduced On-Chip Temperature and Leakage Consumption
The CRNS framework and its application to programmable and reconfigurable cryptography
Scenario-Aware Program Specialization for Timing Predictability
Static Prediction of Silent Stores
SimTrace: Exploiting Spatial and Temporal Sampling for Large-Scale Performance Analysis
The Effects of Granularity and Adaptivity on Private/Shared Classification for Coherence
Tiaozhuan: A General and Efficient Indirect Branch Optimization for Binary Translation
SLAP: Segmented Reuse-Time-Label Based Admission Policy for Content Delivery Network Caching
Maximizing Data and Hardware Reuse for HLS with Early-Stage Symbolic Partitioning
Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture for Manycore Systems
Hybrid type legalization for a sparse SIMD instruction set
IATAC: a smart predictor to turn-off L2 cache lines
Comprehensive Characterization of an Open Source Document Search Engine
Energy-efficient register caching with compiler assistance
Single-dimension software pipelining for multidimensional loops
SIMD-Matcher: A SIMD-based Arbitrary Matching Framework
Fast Crown Scheduling Heuristics for Energy-Efficient Mapping and Scaling of Moldable Streaming Tasks on Manycore Systems
Fair CPU time accounting in CMP+SMT processors
Merging path and gshare indexing in perceptron branch prediction
CAFFEINE: A Utility-Driven Prefetcher Aggressiveness Engine for Multicores
Register-Pressure-Aware Instruction Scheduling Using Ant Colony Optimization
Advancing Direct Convolution Using Convolution Slicing Optimization and ISA Extensions
Effective Loop Fusion in Polyhedral Compilation Using Fusion Conflict Graphs
Temperature-aware microarchitecture: Modeling and implementation
List of 2018 Distinguished Reviewers ACM TACO
Improving Computation and Memory Efficiency for Real-world Transformer Inference on GPUs
Versatility of extended subwords and the matrix register file
Dynamic warp formation: Efficient MIMD control flow on SIMD graphics hardware
MATOG: Array Layout Auto-Tuning for CUDA
Hardware-hardened Sandbox Enclaves for Trusted Serverless Computing
Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion
Polyhedral Specification and Code Generation of Sparse Tensor Contraction with Co-iteration
Making the Most of SMT in HPC: System- and Application-Level Perspectives
gCom: Fine-grained Compressors in Graphics Memory of Mobile GPU
Improving Hybrid FTL by Fully Exploiting Internal SSD Parallelism with Virtual Blocks
Four Metrics to Evaluate Heterogeneous Multicores
Maximizing Heterogeneous Processor Performance Under Power Constraints
Extending Moore's Law via Computationally Error-Tolerant Computing
FlexHM: A Practical System for Heterogeneous Memory with Flexible and Efficient Performance Optimizations
AG-SpTRSV: An Automatic Framework to Optimize Sparse Triangular Solve on GPUs
A low-complexity fetch architecture for high-performance superscalar processors
Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators
Locality-Aware CTA Scheduling for Gaming Applications
Cooperative Caching for GPUs
Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA
ReveNAND: A Fast-Drift-Aware Resilient 3D NAND Flash Design
ADAPT: A framework for coscheduling multithreaded programs
Flynn's Reconciliation: Automating the Register Cache Idiom for Cross-accelerator Programming
Extending the WCET Problem to Optimize for Runtime-Reconfigurable Processors
ApHMM: Accelerating Profile Hidden Markov Models for Fast and Energy-efficient Genome Analysis
Using in-flight chains to build a scalable cache coherence protocol
Building a Fast and Efficient LSM-tree Store by Integrating Local Storage with Cloud Storage
Managing Mismatches in Voltage Stacking with CoreUnfolding
MBZip: Multiblock Data Compression
CAIRO: A Compiler-Assisted Technique for Enabling Instruction-Level Offloading of Processing-In-Memory
Elastic Places: An Adaptive Resource Manager for Scalable and Portable Performance
EFGR: An Enhanced Fine Granularity Refresh Feature for High-Performance DDR4 DRAM Devices
Managing bounded code caches in dynamic binary optimization systems
OptiFX: Automatic Optimization for Convolutional Neural Networks with Aggressive Operator Fusion on GPUs
Improving Utilization of Dataflow Unit for Multi-Batch Processing
Ecmas+: Efficient Circuit Mapping and Scheduling for Surface Code Encoded Circuit on Quantum Cloud Platform
Exploring the limits of early register release: Exploiting compiler analysis
On Using the Roofline Model with Lower Bounds on Data Movement
Efficient Data Encoding for Convolutional Neural Network application
Dynamic memory interval test vs. interprocedural pointer analysis in multimedia applications
Task-RM: A Resource Manager for Energy Reduction in Task-Parallel Applications under Quality of Service Constraints
SMAUG: End-to-End Full-Stack Simulation Infrastructure for Deep Learning Workloads
Memory optimization of dynamic binary translators for embedded systems
Optimizing the SSD Burst Buffer by Traffic Detection
Bayesian Optimization for Efficient Accelerator Synthesis
Jointly Optimizing Job Assignment and Resource Partitioning for Improving System Throughput in Cloud Datacenters
Performance-aware thermal management via task scheduling
Yet Another Compressed Cache: A Low-Cost Yet Effective Compressed Cache
Performance and Power Prediction for Concurrent Execution on GPUs
Software-controlled fault tolerance
A Survey of General-purpose Polyhedral Compilers
Blaze-Tasks: A Framework for Computing Parallel Reductions over Tasks
Compiler and hardware support for reducing the synchronization of speculative threads
Evaluating placement policies for managing capacity sharing in CMP architectures with private caches
CIB-HIER: Centralized Input Buffer Design in Hierarchical High-radix Routers
ARI: Adaptive LLC-memory traffic management
Quality of service shared cache management in chip multiprocessor architecture
HopScotch: A Holistic Approach to Data Layout-Aware Mapping on NPUs for High-Performance DNN Inference
SynchroTrace: Synchronization-Aware Architecture-Agnostic Traces for Lightweight Multicore Simulation of CMP and HPC Workloads
Energy-efficient In-Memory Address Calculation
A Self-aware Resource Management Framework for Heterogeneous Multicore SoCs with Diverse QoS Targets
In-SRAM Parallel Data Shuffle
Designing a practical data filter cache to improve both energy efficiency and performance
Virtually split cache: An efficient mechanism to distribute instructions and data
Processor-Tracing Guided Region Formation in Dynamic Binary Translation
Automated Software Protection for the Masses Against Side-Channel Attacks
Hyperion: A Highly Effective Page and PC Based Delta Prefetcher
Boosting the Priority of Garbage: Scheduling Collection on Heterogeneous Multicore Processors
DELTA: Memory-Efficient Training via Dynamic Fine-Grained Recomputation and Swapping
Low-precision Logarithmic Number Systems: Beyond Base-2
RACE: An Efficient Redundancy-aware Accelerator for Dynamic Graph Neural Network
Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints
Measuring Microarchitectural Details of Multi- and Many-Core Memory Systems through Microbenchmarking
Fast modulo scheduler utilizing patternized routes for coarse-grained reconfigurable architectures
TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs
Bandwidth and Locality Aware Task-stealing for Manycore Architectures with Bandwidth-Asymmetric Memory
Algorithmic species: A classification of affine loop nests for parallel programming
Combining recency of information with selective random and a victim cache in last-level caches
Fast and efficient searches for effective optimization-phase sequences
WA-Zone: Wear-Aware Zone Management Optimization for LSM-Tree on ZNS SSDs
Revisiting memory management on virtualized environments
Minos: Architectural support for protecting control data
Acceleration of Parallel-Blocked QR Decomposition of Tall-and-Skinny Matrices on FPGAs
A hardware/software framework for instruction and data scratchpad memory allocation
D 2 Comp: Efficient Offload of LSM-tree Compaction with Data Processing Units on Disaggregated Storage
HRF-Relaxed: Adapting HRF to the Complexities of Industrial Heterogeneous Memory Models
SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads
MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams
Thread-Aware Adaptive Prefetcher on Multicore Systems: Improving the Performance for Multithreaded Workloads
Tuning the continual flow pipeline architecture with virtual register renaming
SHASTA: Synergic HW-SW Architecture for Spatio-temporal Approximation
SnsBooster: Enhancing Sampling-based μ Arch Evaluation Efficiency through Online Performance Sensitivity Analysis
SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs
Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory
MC-DeF: Creating Customized CGRAs for Dataflow Applications
Assessing the Impact of Compiler Optimizations on GPUs Reliability
SAL: Optimizing the Dataflow of Spin-based Architectures for Lightweight Neural Networks
MAPPER: Managing Application Performance via Parallel Efficiency Regulation*
SCORE: A Novel Scheme to Efficiently Cache Overlong ECCs in NAND Flash Memory
Time-Aware Spectrum-Based Bug Localization for Hardware Design Code with Data Purification
Efficient address remapping in distributed shared-memory systems
Layout-oblivious compiler optimization for matrix computations
Augur: Semantics-Aware Temporal Prefetching for Linked Data Structure
Generalizing neural branch prediction
A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints
LO-SpMM: Low-cost Search for High-performance SpMM Kernels on GPUs
AsynGraph: Maximizing Data Parallelism for Efficient Iterative Graph Processing on GPUs
Performance Optimization of the HPCG Benchmark on the Sunway TaihuLight Supercomputer
Koala: Efficient Pipeline Training through Automated Schedule Searching on Domain-Specific Language
TLB-pilot: Mitigating TLB Contention Attack on GPUs with Microarchitecture-Aware Scheduling
Efficient Cache Performance Modeling in GPUs Using Reuse Distance Analysis
Eliminating voltage emergencies via software-guided code transformations
Coherence Attacks and Countermeasures in Interposer-based Chiplet Systems
Benchmarking WebAssembly for Embedded Systems
A High Scalability Memory NoC with Shared-Inside Hierarchical-Groupings for Triplet-Based Many-Core Architecture
GraphService: Topology-aware Constructor for Large-scale Graph Applications
Refresh pausing in DRAM memory systems
ALP: Efficient support for all levels of parallelism for complex media applications
A Compiler Approach for Exploiting Partial SIMD Parallelism
Layer-Centric Memory Reuse and Data Migration for Extreme-Scale Deep Learning on Many-Core Architectures
Interaction cost and shotgun profiling
DxPU: Large-scale Disaggregated GPU Pools in the Datacenter
Effective management of multiple configurable units using dynamic optimization
LiteCON : An All-photonic Neuromorphic Accelerator for Energy-efficient Deep Learning
Performance Portability Across Heterogeneous SoCs Using a Generalized Library-Based Approach
Exploring the limits of GPGPU scheduling in control flow bound applications
Visual Program Manipulation in the Polyhedral Model
Approx-RM: Reducing Energy on Heterogeneous Multicore Processors under Accuracy and Timing Constraints
Achieving Tunable Erasure Coding with Cluster-Aware Redundancy Transitioning
Supports of Data Cache Division for Computational Solid-state Drives
Iterating Pointers: Enabling Static Analysis for Loop-based Pointers
ALEA: A Fine-Grained Energy Profiling Tool
A Black-box Monitoring Approach to Measure Microservices Runtime Performance
Energy-Proportional Photonic Interconnects
QuCloud+: A Holistic Qubit Mapping Scheme for Single/Multi-programming on 2D/3D NISQ Quantum Computers
Speeding up Iterative Polyhedral Schedule Optimization with Surrogate Performance Models
Perfect Reconstructability of Control Flow from Demand Dependence Graphs
Corrigendum: gECC: A GPU-based high-throughput framework for Elliptic Curve Cryptography
An Integrated Vector-Scalar Design on an In-Order ARM Core
Dataflow Tomography: Information Flow Tracking For Understanding and Visualizing Full Systems
Consequence-based Clustered Architecture
Reusing the Optimized Code for JavaScript Ahead-of-Time Compilation
SPX64: A Scratchpad Memory for General-purpose Microprocessors
Exploiting Hierarchical Locality in Deep Parallel Architectures
Schedule Synthesis for Halide Pipelines on GPUs
Benefits of selective packet discard in networks-on-chip
Scalable Energy Efficiency with Resilience for High Performance Computing Systems: A Quantitative Methodology
HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy
FlexSig: Implementing flexible hardware signatures
On Architectural Support for Instruction Set Randomization
An Accurate Cross-Layer Approach for Online Architectural Vulnerability Estimation
Deterministic finite automata characterization and optimization for scalable pattern matching
3D GNLM: Efficient 3D Non-Local Means Kernel with Nested Reuse Strategies for Embedded GPUs
Main Memory in HPC: Do We Need More or Could We Live with Less?
Compiler-Directed Power Management for Superscalars
DCSolver: Accelerating Sparse Iterative Solvers via Divide-and-Conquer on GPUs
Hadoop Extensions for Distributed Computing on Reconfigurable Active SSD Clusters
Implicit array bounds checking on 64-bit architectures
DeepZoning: Re-accelerate CNN Inference with Zoning Graph for Heterogeneous Edge Cluster
Tile size selection revisited
SIMPO: A Scalable In-Memory Persistent Object Framework Using NVRAM for Reliable Big Data Computing
SMT-Based Contention-Free Task Mapping and Scheduling on 2D/3D SMART NoC with Mixed Dimension-Order Routing
Improved loop tiling based on the removal of spurious false dependences
Rcmp: Reconstructing RDMA-Based Memory Disaggregation via CXL
Optimization of Sparse Matrix Computation for Algebraic Multigrid on GPUs
An architecture-independent instruction shuffler to protect against side-channel attacks
DEFCAM: A design and evaluation framework for defect-tolerant cache memories
The optimum pipeline depth considering both power and performance
Chameleon: Virtualizing idle acceleration cores of a heterogeneous multicore processor for caching and prefetching
Extension VM: Interleaved Data Layout in Vector Memory
SIMT-X: Extending Single-Instruction Multi-Threading to Out-of-Order Cores
EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults
Cross-Loop Optimization of Arithmetic Intensity for Finite Element Local Assembly
Topological Characterization of Hamming and Dragonfly Networks and Its Implications on Routing
Intercepting Functions for Memoization: A Case Study Using Transcendental Functions
Highly Efficient Self-checking Matrix Multiplication on Tiled AMX Accelerators
An efficient multicharacter transition string-matching engine based on the aho-corasick algorithm
Cache Exclusivity and Sharing: Theory and Optimization
Transparent Acceleration for Heterogeneous Platforms With Compilation to OpenCL
Pot: Deterministic Transactional Execution
Hardware-Assisted Thread and Data Mapping in Hierarchical Multicore Architectures
TEA+ : A Novel Temporal Graph Random Walk Engine with Hybrid Storage Architecture
Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network
Integer Linear Programming-Based Scheduling for Transport Triggered Architectures
Efficient Correction of Anomalies in Snapshot Isolation Transactions
TransCL: An Automatic CUDA-to-OpenCL Programs Transformation Framework
JavaScript Parallelizing Compiler for Exploiting Parallelism from Data-Parallel HTML5 Applications
Designing on-chip networks for throughput accelerators
Addressing thermal nonuniformity in SMT workloads
Block-aware instruction set architecture
Cooperative Software-hardware Acceleration of K-means on a Tightly Coupled CPU-FPGA System
Towards update-conscious compilation for energy-efficient code dissemination in WSNs
Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads
At the Locus of Performance: Quantifying the Effects of Copious 3D-Stacked Cache on HPC Workloads
MemSZ: Squeezing Memory Traffic with Lossy Compression
Adaptive Correction of Sampling Bias in Dynamic Call Graphs
YaConv: Convolution with Low Cache Footprint
Access Characteristic-Guided Remote Swapping Across Mobile Devices
A Cross-Platform SpMV Framework on Many-Core Architectures
Iterative Schedule Optimization for Parallelization in the Polyhedron Model
Polyhedral Search Space Exploration in the ExaStencils Code Generator
CesASMe and Staticdeps: static detection of memory-carried dependencies for code analyzers
SYRANT: SYmmetric resource allocation on not-taken and taken paths
The Art of Getting Deep Neural Networks in Shape
SAC: An Ultra-Efficient Spin-based Architecture for Compressed DNNs
Autovesk: Automatic Vectorized Code Generation from Unstructured Static Kernels Using Graph Transformations
Towards Enhanced System Efficiency while Mitigating Row Hammer
Extending Halide to Improve Software Development for Imaging DSPs
Preserving Addressability Upon GC-Triggered Data Movements on Non-Volatile Memory
DisIRer: Converting a retargetable compiler into a multiplatform binary translator
Unveiling and Evaluating Vulnerabilities in Branch Predictors via a Three-Step Modeling Methodology
FastPath_MP: Low Overhead & Energy-efficient FPGA-based Storage Multi-paths
Fine-grained DVFS using on-chip regulators
RaNAS: Resource-Aware Neural Architecture Search for Edge Computing
Cross-core Data Sharing for Energy-efficient GPUs
Improving Memory Efficiency in Heterogeneous MPSoCs through Row-Buffer Locality-aware Forwarding
TPRepair: Tree-based Pipelined Repair in Clustered Storage Systems
Reliability Analysis for Unreliable FSM Computations
A Relational Theory of Locality
FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler
RAGuard: An Efficient and User-Transparent Hardware Mechanism against ROP Attacks
Power gating strategies on GPUs
Object co-location and memory reuse for Java programs
Optimizing Small-Sample Disk Fault Detection Based on LSTM-GAN Model
Supporting Dynamic Program Sizes in Deep Learning-Based Cost Models for Code Optimization
Whole execution traces and their applications
Future execution: A prefetching mechanism that uses multiple cores to speed up single threads
Optimizing Convolutional Neural Networks on the Sunway TaihuLight Supercomputer
Polyhedral Compilation for Multi-dimensional Stream Processing
DeFT: Design space exploration for on-the-fly detection of coherence misses
Occam: Optimal Data Reuse for Convolutional Neural Networks
User-Assisted Store Recycling for Dynamic Task Graph Schedulers
Editorial: A Message from the Editor-in-Chief
Adaptive Contention Management for Fine-Grained Synchronization on Commodity GPUs
ITAP: Idle-Time-Aware Power Management for GPU Execution Units
An analysis of a resource efficient checkpoint architecture