yusuke1997/dblp-id-title huggingface dataset:
Beyond Address Mapping: A User-Oriented Multiregional Space Management Design for 3-D NAND Flash Memory
Massively parallel computation using a splitting-up operator method for three-dimensional device simulation
Efficient Additive Statistical Leakage Estimation
Calligrapher: a new layout-migration engine for hard intellectual property libraries
Automated design tool execution in the Ulysses design environment
1+1 <2: Efficient Automatic Standard Cell Sharing Between Digital VLSI Designs for Area Saving
Optimizing the Use of Behavioral Locking for High-Level Synthesis
Reconfigurable Constant Multiplication for FPGAs
Evaluation of Analog/RF Test Measurements at the Design Stage
Correlated Bayesian Model Fusion: Efficient High-Dimensional Performance Modeling of Analog/RF Integrated Circuits Over Multiple Corners
A Combined Power and Fault Analysis Attack on Protected Grain Family of Stream Ciphers
Binning Optimization for Transparently-Latched Circuits
Efficient Process Shift Detection and Test Realignment
Crosstalk noise control in an SoC physical design flow
Digital filter synthesis based on an algorithm to generate all minimal signed digit representations
Investigating Frequency Scaling, Nonvolatile, and Hybrid Memory Technologies for On-Chip Routers to Support the Era of Dark Silicon
RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs
Timely Error Detection for Effective Recovery in Light-Lockstep Automotive Systems
Delay-Driven Rectilinear Steiner Tree Construction
Bit-Flipping Schemes Upon MLC Flash: Investigation, Implementation, and Evaluation
Effective Robustness Analysis Using Bounded Model Checking Techniques
Effective software-based self-test strategies for on-line periodic testing of embedded processors
A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits
Energy-Efficient In-Memory Paging for Smartphones
Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm
Silica-Embedded Silicon Nanophotonic On-Chip Networks
Automated transformation of algorithms into register-transfer level implementations
Automated Synthesis of Safe Timing Behaviors for Requirements Models Using CCSL
Probabilistic Evaluation of Solutions in Variability-Driven Optimization
Inferno: Streamlining Verification With Inferred Semantics
Simulation-Based Bug Trace Minimization With BMC-Based Refinement
Direct synthesis of timed circuits from free-choice STGs
Varying Periods of In-Field Testing With Storage- and Counter-Based Logic Built-In Self-Test
Logic Synthesis for RRAM-Based In-Memory Computing
Streamlining Computational Lithography With Efficient Pattern Database
Impact of stress-induced backflow on full-chip electromigration risk assessment
Layout optimization of static CMOS functional cells
Don't care sequences and the optimization of interacting finite state machines
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning
A Polynomial Time Exact Algorithm for Overlay-Resistant Self-Aligned Double Patterning (SADP) Layout Decomposition
Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis
Energy-aware task scheduling with task synchronization for embedded real-time systems
Wire Retiming Problem With Net Topology Optimization
Contract-Based Hierarchical Modeling and Traceability of Heterogeneous Requirements
EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates
Parameterized Dataflow Scenarios
Time-Varying Root-Locus of Large-Signal LC Oscillators
CoTree: A Side-Channel Collision Tool to Push the Limits of Conquerable Space
A logic-to-logic comparator for VLSI layout verification
Performance prediction for adaptive quad tree graphical data structures
An Extension to Newton's Method in Device Simulators--On An Efficient Algorithm to Evaluate Small-Signal Parameters and to Predict Initial Guess
An automatic test pattern generator for minimizing switching activity during scan testing activity
A Best Balance Ratio Ordered Feature Selection Methodology for Robust and Fast Statistical Analysis of Memory Designs
An Integrated Layout-Synthesis Approach for Analog ICs
Cut and Forward: Safe and Secure Communication for FPGA System on Chips
Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing
Algorithm-driven synthesis of data conversion architectures
CNFET-Based High Throughput SIMD Architecture
A Low-Power Variation-Tolerant 7T SRAM With Enhanced Read Sensing Margin for Voltage Scaling
ToPoliNano: A CAD Tool for Nano Magnetic Logic
Localized Stability Checking and Design of IC Power Delivery With Distributed Voltage Regulators
On-Chip Self-Test Methodology With All Deterministic Compressed Test Patterns Recorded in Scan Chains
SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors
Local ratio cut and set covering partitioning for huge logic emulation systems
RDA: A Read-Request Driven Adaptive Allocation Scheme for Improving SSD Performance
Incremental layout placement modification algorithms
Postgrid Clock Routing for High Performance Microprocessor Designs
Maskara: Compilation of a Masking Countermeasure With Optimized Polynomial Interpolation
Microfluidic Design for Concentration Gradient Generation Using Artificial Neural Network
Potential Trigger Detection for Hardware Trojans
Realization and Hardware Implementation of Gating Units for Long Short-Term Memory Network Using Hyperbolic Sine Functions
A quadrisection-based combined place and route scheme for standard cells
Fashion: A Fast and Accurate Solution to Global Routing Problem
Smallest paths in simple rectilinear polygons
Test Stimulus Compression Based on Broadcast Scan With One Single Input
Model and solution strategy for placement of rectangular blocks in the Euclidean plane
Fast detection of data retention faults and other SRAM cell open defects
Delay analysis of CMOS gates using modified logical effort model
Macromodel Generation for BioMEMS Components Using a Stabilized Balanced Truncation Plus Trajectory Piecewise-Linear Approach
Mapping Nearest Neighbor Compliant Quantum Circuits Onto a 2-D Hexagonal Architecture
Shallow Quantum Circuit Implementation of Symmetric Functions With Limited Ancillary Qubits
A Formal Approach for Debugging Arithmetic Circuits
Space Compression Methods With Output Data Modification
Fast Constraints Tuning via Transfer Learning and Multiobjective Optimization
A Boolean Rule-Based Approach for Manufacturability-Aware Cell Routing
NeuroMap: Efficient Task Mapping of Deep Neural Networks for Dynamic Thermal Management in High-Bandwidth Memory
Improving Flash Memory Performance and Reliability for Smartphones With I/O Deduplication
Mining Global Constraints With Domain Knowledge for Improving Bounded Sequential Equivalence Checking
A Computationally Efficient Tensor Regression Network-Based Modeling Attack on XOR Arbiter PUF and Its Variants
A Bidirectional Deep Learning Approach for Designing MEMS Sensors
Constrained test generation for embedded synchronous sequential circuits with serial-input access
Reasoning about timing behavior of digital circuits using symbolic event propagation and temporal logic
Binarizing Weights Wisely for Edge Intelligence: Guide for Partial Binarization of Deconvolution-Based Generators
A fast algorithm for optimal buffer insertion
Fault diagnosis of VLSI circuits with cellular automata based pattern classifier
Memory performance prediction for high-performance microprocessors at deep submicrometer technologies
Dynamic Frequency Scaling Aware Opportunistic Through-Silicon-Via Inductor Utilization in Resonant Clocking
Three-dimensional defect sensitivity modeling for open circuits in ULSI structures
PETRA: Powerful Early Termination-Based Redundancy Analysis
Design Tools for Digital Microfluidic Biochips: Toward Functional Diversification and More Than Moore
An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits
A new algorithm for elimination of common subexpressions
On the nature and inadequacies of transport timing delay constructs in VHDL descriptions
An optimal Steiner tree algorithm for a net whose terminals lie on the perimeter of a rectangle
An Efficient Analysis Method for LTCC Ridge Waveguide Bandpass Filters via Database Searching
PROBE2.0: A Systematic Framework for Routability Assessment From Technology to Design in Advanced Nodes
Unleashing Network/Accelerator Co-Exploration Potential on FPGAs: A Deeper Joint Search
Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits
Monte Carlo Methods in Defects Migration -- Spontaneous Annealing of Damage Induced by Ion Implantation
Error-Oblivious Sample Preparation With Digital Microfluidic Lab-on-Chip
Performance Modeling for CNN Inference Accelerators on FPGA
A Memristive Spiking Neural Network Circuit With Selective Supervised Attention Algorithm
U-SWIM: Universal Selective Write-Verify for Computing-in-Memory Neural Accelerators
Automated Interface Refinement for Compositional Verification
Generation of equivalent circuits from physics-based devicesimulation
Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process
Accelerated Performance Evaluation of Fixed-Point Systems With Un-Smooth Operations
On the design of optimal counter-based schemes for test set embedding
Defining and Implementing a Multilevel Design Representation with Simulation Applications
Translation Validation of Information Leakage of Compiler Optimizations
Robust and Efficient Transistor-Level Envelope-Following Analysis of PWM/PFM/PSM DC-DC Converters
Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis
EBIO: An Efficient Block I/O Stack for NVMe SSDs With Mixed Workloads
Revisiting TRIM on High-Density Flash-Based Hybrid Storage Systems
Irredundant interacting sequential machines via optimal logic synthesis
A Hierarchical Performance Equation Library for Basic Op-Amp Design
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile
Partial Sum Quantization for Reducing ADC Size in ReRAM-Based Neural Network Accelerators
A numerical method to compute isotropic band models from anisotropic semiconductor band structures
ParaML: A Polyvalent Multicore Accelerator for Machine Learning
Modeling the Driver Load in the Presence of Process Variations
Two new techniques for unit-delay compiled simulation
Static Analysis of Register File Vulnerability
NOVA: state assignment of finite state machines for optimal two-level logic implementation
Ant Colony Optimization-Based Thermal-Aware Adaptive Routing Mechanism for Optical NoCs
Static scheduling of multidomain circuits for fast functional verification
Power Efficient High-Level Synthesis by Centralized and Fine-Grained Clock Gating
Knowledge-based functional specification of test and maintenance programs
An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults
Fully Dynamic Evaluation of Sequence Pair
Efficient Simulation of Power Grids
Rectilinear Steiner tree construction by local and global refinement
LEVAX: An Input-Aware Learning-Based Error Model of Voltage-Scaled Functional Units
Efficient Generation of Dilution Gradients With Digital Microfluidic Biochips
Algorithms for floorplan design via rectangular dualization
VLSI/PCB placement with obstacles based on sequence pair
Probabilistic manipulation of Boolean functions using free Boolean diagrams
A new approach to three- or four-layer channel routing
OMNI: A Framework for Integrating Hardware and Software Optimizations for Sparse CNNs
Statistical Viability Analysis for Detecting False Paths Under Delay Variation
A new algorithm for exact reduction of incompletely specified finite state machines
Robust Chip-Level Clock Tree Synthesis
Interconnect synthesis without wire tapering
Channel Routing for Microfluidic Devices: A Comprehensive and Accessible Design Tool
BIST hardware synthesis for RTL data paths based on testcompatibility classes
Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors
CMQ: Crossbar-Aware Neural Network Mixed-Precision Quantization via Differentiable Architecture Search
Batch-MOT: Batch-Enabled Real-Time Scheduling for Multiobject Tracking Tasks
TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations
PBS: Program Behavior-Aware Scheduling for High-Level Synthesis
Toward Smart Building Design Automation: Extensible CAD Framework for Indoor Localization Systems Deployment
Reasoning about the function and timing of integrated circuits with interval temporal logic
Scan-based BIST fault diagnosis
Statistical Integrated Circuit Design and Characterization
Efficient Arithmetic Block Identification With Graph Learning and Network-Flow
Design of minimum and uniform bipartites for optimum connection blocks of FPGA
A recursive technique for computing delays in series-parallel MOS transistor circuits
Co-Optimizing Storage Space Utilization and Performance for Key-Value Solid State Drives
Heterogeneous FPGA Architecture Using Threshold Logic Gates for Improved Area, Power, and Performance
Cheetah: An Accurate Assessment Mechanism and a High-Throughput Acceleration Architecture Oriented Toward Resource Efficiency
Erratum to "Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs"
A compact nonquasi-static MOSFET model based on the equivalent nonlinear transmission line
PATH: Evaluation of Boolean Logic Using Path-Based In-Memory Computing Systems
On Obtaining Maximum-Length Sequences for Accumulator-Based Serial TPG
Edisim: A Graphical Simulator Interface for LSI Design
Synchronization of Continuous Time and Discrete Events Simulation in SystemC
An ECO routing algorithm for eliminating coupling-capacitance violations
Schedulability Analysis for Coscheduling Real-Time Tasks on Multiprocessors
Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews
Estimating testing effectiveness of the circular self-test path technique
An Optimization-Aware Prerouting Timing Prediction Framework Based on Multimodal Learning
Fast Design Space Exploration of Nonlinear Systems: Part II
A general greedy channel routing algorithm
Theory and algorithms for state minimization of nondeterministic FSMs
A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders
Interconnect-aware low-power high-level synthesis
Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design
Structural FSM traversal
Reactant Minimization in Sample Preparation on Digital Microfluidic Biochips
Cryptensor: A Resource-Shared Co-Processor to Accelerate Convolutional Neural Network and Polynomial Convolution
A Fast Analysis Method of Multiphysics Coupling for 3-D Microsystem
A Taylor-Galerkin finite element method for the hydrodynamic semiconductor equations
Voltage-Island Partitioning and Floorplanning Under Timing Constraints
Preemptible I/O Scheduling of Garbage Collection for Solid State Drives
Fast effective heuristics for the graph bisectioning problem
Automatic Droplet Sequence Generation for Microfluidic Networks With Passive Droplet Routing
ReApprox-PIM: Reconfigurable Approximate Lookup-Table (LUT)-Based Processing-in-Memory (PIM) Machine Learning Accelerator
Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip
Device and circuit simulation of quantum electronic devices
A Scalable Buffer Queue Sizing Algorithm for Latency Insensitive Systems
Test set selection for structural faults in analog IC's
Retiming for wire pipelining in system-on-chip
Modeling nonlinear dynamics in analog circuits via root localization
SPAR: A New Test-Point Insertion Using Shared Points for Area Overhead Reduction
Cellular automata based deterministic self-test strategies for programmable data paths
SMART-P: rigorous three-dimensional process simulator on a supercomputer
Specializing CGRAs for Light-Weight Convolutional Neural Networks
Custom Multicache Architectures for Heap Manipulating Programs
Eliminating false positives in crosstalk noise analysis
On-chip power-supply network optimization using multigrid-based technique
The efficient simulation of coupled point defect and impurity diffusion
DELIGHT.SPICE: an optimization-based system for the design of integrated circuits
Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis
EMI: Energy Management Meets Imputation in Wearable IoT Devices
Analog IC design automation. II. Automated circuit correction by qualitative reasoning
VIGILANT: Vulnerability Detection Tool Against Fault-Injection Attacks for Locking Techniques
Counterexample Guided Neural Network Quantization Refinement
Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor
High Performance Lithography Hotspot Detection With Successively Refined Pattern Identifications and Machine Learning
An approach to the analysis and detection of crosstalk faults in digital VLSI circuits
High-Performance Two-Dimensional Finite Field Multiplication and Exponentiation for Cryptographic Applications
Functional test generation for synchronous sequential circuits
Guest Editorial Special Section on PAR-CAD: Parallel CAD Algorithms and CAD for Parallel Architectures/Systems
A Rerouting Scheme for Single-Layer Printed Wiring Boards
ADAM: a two dimensional, two-carrier MOSFET simulator based on generalized stream functions
Vespa: Logic-Level Constraint-Based Validation for Continuous-Flow Microfluidic Devices
A Compact Scheme of Reading and Writing for Memristor-Based Multivalued Memory
Three-Port Model of a Modern MOS Transistor in Millimeter Wave Band, Considering Distributed Effects
Reusing Hardware Performance Counters to Detect and Identify Kernel Control-Flow Modifying Rootkits
Analytical approach to layout generation of datapath cells
Modeling and Application of Multi-Port TSV Networks in 3-D IC
Neural Network-Based Thermal Simulation of Integrated Circuits on GPUs
Numerical modeling of two-dimensional device structures using Brandt's multilevel acceleration scheme: application to Poisson's equation
Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS
Secure Scan and Test Using Obfuscation Throughout Supply Chain
Optimal decoupling capacitor sizing and placement for standard-cell layout designs
GRIP: Global Routing via Integer Programming
STREAM: Toward READ-Based In-Memory Computing for Streaming-Based Processing for Data-Intensive Applications
An efficient method for generating exhaustive test sets
Drift reliability optimization in IC design: generalized formulation and practical examples
Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors
Semiconductor wafer representation for TCAD
Fast Identification of Custom Instructions for Extensible Processors
SOC Test Architecture and Method for 3-D ICs
On the Layering Problem of Multilayer PWB Wiring
A Hardware Architecture for Switch-Level Simulation
Theseus: Exploring Efficient Wafer-Scale Chip Design for Large Language Models
Three-Dimensional Device Simulator CADDETH with Highly Convergent Matrix Solution Algorithms
A Runtime Optimization Approach for FPGA Routing
Personalized Federated Learning With State-Adaptive IoT Device Scheduling in Mobile-Edge Computing
Estimation of dc Performance of a Lateral Power MOSFET Using Distributed Cell Model
A totally self-checking checker for Borden's code
When B-Tree Meets Skyrmion Memory: How Skyrmion Memory Affects an Indexing Scheme
Min-cut replication in partitioned networks
A High-Throughput Full-Dataflow MobileNetv2 Accelerator on Edge FPGA
Application of Artificial Neural Networks to Statistical Analysis and Nonlinear Modeling of High-Speed Interconnect Systems
Software-Based Self-Test for Small Caches in Microprocessors
ProVAT: An Automated Design and Analysis Framework for Process-Variation-Resilient Design of Silicon Photonic Microring Resonators
Fine-Grain Back Biasing for the Design of Energy-Quality Scalable Operators
Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs
Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction
An Automated Topology Synthesis Framework for Analog Integrated Circuits
PEPPER-a process simulator for VLSI
Modeling and extraction of interconnect capacitances for multilayer VLSI circuits
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design
Bayesian Model Fusion: Large-Scale Performance Modeling of Analog and Mixed-Signal Circuits by Reusing Early-Stage Data
On-Device Training of Fully Quantized Deep Neural Networks on Cortex-M Microcontrollers
Pole and zero sensitivity calculation in asymptotic waveform evaluation
Mex+Sync: Software Covert Channels Exploiting Mutual Exclusion and Synchronization
Unleashing the Power of Graph Spectral Sparsification for Power Grid Analysis via Incomplete Cholesky Factorization
Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations
An Efficient Extrapolation Method of Band-Limited S-Parameters for Extracting Causal Impulse Responses
Bounds on the number of slicing, mosaic, and general floorplans
Unconstrained-Activation Functional-Detection Scan-Based Tests
Secure Scan: A Design-for-Test Architecture for Crypto Chips
FASE: Energy Isolation Framework for Latency-Sensitive Applications in Intermittent Systems With Multiple Peripherals
TRouter: Thermal-Driven PCB Routing via Nonlocal Crisscross Attention Networks
CNN-Based Stochastic Regression for IDDQ Outlier Identification
Hybrid designs generating maximum-length sequences
Custom Floating-Point Unit Generation for Embedded Systems
Improving a nonenumerative method to estimate path delay fault coverage
An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools
Electronic design automation at the turn of the century: accomplishments and vision of the future
A novel geometric resizing technique for data conversion from CAD data to electron beam exposure data
On the use of random limited-scan to improve at-speed randompattern testing of scan circuits
BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture
On the complexity of connectivity binding
COMPACTEST: a method to generate compact test sets for combinational circuits
Minimizing wire length in floorplanning
Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)
Toward a Profitable Grid-Connected Hybrid Electrical Energy Storage System for Residential Use
System-Level Dynamic Thermal Management for High-Performance Microprocessors
SpikeSim: An End-to-End Compute-in-Memory Hardware Evaluation Tool for Benchmarking Spiking Neural Networks
Toward Building and Optimizing Trustworthy Systems Using Untrusted Components: A Graph-Theoretic Perspective
Buffer Sharing in Rendezvous Programs
Efficient Sample Preparation With Fully Programmable Valve Arrays
Tidal-Tree-Mem: Toward Read-Intensive Key-Value Stores With Tidal Structure Based on LSM-Tree
Functional Broadside Tests With Incompletely Specified Scan-In States
Decomposition-Based Vectorless Toggle Rate Computation for FPGA Circuits
An Initialization Process to Support Online Testing Based on Output Comparison for Identical Finite-State Machines
A genetic approach to standard cell placement using meta-genetic parameter optimization
Timed compiled-code functional simulation of embedded software for performance analysis of SOC design
An optimal test compression procedure for combinational circuits
Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits
On the efficiency of formal synthesis-experimental results
Multiobjective hypergraph-partitioning algorithms for cut and maximum subdomain-degree minimization
HopliteRT*: Real-Time NoC for FPGA
On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits
Energy-Constrained Data Freshness Optimization in Self-Powered Networked Embedded Systems