yusuke1997/dblp-id-title huggingface dataset:
Deterministic Shuffling Networks to Implement Stochastic Circuits in Parallel
GOP-Level Dynamic Thermal Management in MPEG-2 Decoding
Low-Complexity Sequential Searcher for Robust Symbol Synchronization in OFDM Systems
Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes
Hybrid Number Theoretic Transform Architecture for Homomorphic Encryption
An Ultralow-Power Real-Time Machine Learning Based fNIRS Motion Artifacts Detection
A Hybrid-Structured Lossless Compression-Decompression Engine for Intermediate Feature Maps in Vision Neural Networks
Application of Machine Learning for Optimization of 3-D Integrated Circuits and Systems
Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges
Temperature Sensitivity and Compensation on a Reconfigurable Platform
Power-On Reset Circuit in 180-nm CMOS With Brownout Detection, Stable Switching Points, Long Reset Pulse Duration, and Resilience to Switching Noise
Test Data Compression Using Selective Encoding of Scan Slices
A 1-MS/s 64-Channel Data Acquisition System With Full-Scale Input Range for Area-Sensitive Application Achieved 165.3-dB FoM S /Ch
Efficient FPGA Implementations of Point Multiplication on Binary Edwards and Generalized Hessian Curves Using Gaussian Normal Basis
Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power
Design of a Low-Power Analog Integrated Deep Convolutional Neural Network
ESPRESSO-SIGNATURE: a new exact minimizer for logic functions
Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs
Reconfigurable Hardware for High-Security/ High-Performance Embedded Systems: The SAFES Perspective
Nonvolatile CBRAM-Crossbar-Based 3-D-Integrated Hybrid Memory for Data Retention
Large-Scale Memristive Associative Memories
Mitigating Cross-Core Cache Attacks via Suspicious Traffic Detection
Design considerations for high-frequency crystal oscillators digitally trimmable to sub-ppm accuracy
LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter
Efficient Hardware Architecture of η T Pairing Accelerator Over Characteristic Three
Approximate SRAMs With Dynamic Energy-Quality Management
Black-Hat High-Level Synthesis: Myth or Reality?
Behavioral Modeling of Tunable I/O Drivers With Preemphasis Including Power Supply Noise
Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm
Efficient built-in redundancy analysis for embedded memories with 2-D redundancy
Low overhead fault-tolerant FPGA systems
A Parametric DFT Scheme for STT-MRAMs
RISE: RISC-V SoC for En/Decryption Acceleration on the Edge for Homomorphic Encryption
Accurate Linear Model for SET Critical Charge Estimation
MOUSETRAP: High-Speed Transition-Signaling Asynchronous Pipelines
Memristors for Secret Sharing-Based Lightweight Authentication
Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells
A 60-GHz Dual-Mode Distributed Active Transformer Power Amplifier in 65-nm CMOS
Programmable Daisychaining of Microelectrodes to Secure Bioassay IP in MEDA Biochips
TSV Prebond Test Method Based on Switched Capacitors
A Simple Floating MOS-Memristor for High-Frequency Applications
Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations
Uncertainty-Aware Dynamic Power Management in Partially Observable Domains
Automatic Constraint Based Test Generation for Behavioral HDL Models
A Single-Stage Direct-Conversion AC-DC Converter for Inductively Powered Application
Read Performance: The Newest Barrier in Scaled STT-RAM
Leakage-Power-Aware Scheduling With Dual-Threshold Voltage Design
NVLIM: MTJ and CMOS-Based Nonvolatile Latch Design With Protection Against Triple-Node-Upsets for Robust Computing
CMOS design of the tree arbiter element
An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design
A Capacitorless Flipped-Voltage-Follower-Based Low-Dropout Regulator Incorporating Adaptive-Compensation Buffer
Built-in Self-Detection/Correction Architecture for Motion Estimation Computing Arrays
Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization
EM Side-Channel Countermeasure for Switched-Capacitor DC-DC Converters Based on Amplitude Modulation
Single-Inductor-Multiple-Tier Regulation: TSV-Inductor-Based On-Chip Buck Converters for 3-D IC Power Delivery
Bus-switch coding for reducing power dissipation in off-chip buses
A Novel Asynchronous Pixel for an Energy Harvesting CMOS Image Sensor
Reconfigurable Routers for Low Power and High Performance
A Spatial and Temporal Locality-Aware Adaptive Cache Design With Network Optimization for Tiled Many-Core Architectures
ZoneDefense: A Fault-Tolerant Routing for 2-D Meshes Without Virtual Channels
Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning
Quantitative study of the impact of design and synthesis options on processor core performance
Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages
Structural analysis and generation of synthetic digital circuits with memory
The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures
Using a Device State Library to Boost the Performance of TCAD Mixed-Mode Simulation
On the Nonvolatile Performance of Flip-Flop/SRAM Cells With a Single MTJ
Supply Switching With Ground Collapse: Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS Circuits
A CMOS AFE Array With DC Input Current Cancellation for FMCW LiDAR
An MIV Fault Diagnosis Method Based on Signal Transmission Performance Analysis
A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks
Robust subthreshold logic for ultra-low power operation
ASSURE: RTL Locking Against an Untrusted Foundry
A Fast and Energy-Efficient Level Shifter With Complementary Output Buffer for Energy-Constrained Systems
Accurate Predictive Interconnect Modeling for System-Level Design
Design and Evaluation of Confidence-Driven Error-Resilient Systems
A Supply Voltage and Temperature Variation-Tolerant Relaxation Oscillator for Biomedical Systems Based on Dynamic Threshold and Switched Resistors
A Calibration-Free/DEM-Free 8-bit 2.4-GS/s Single-Core Digital-to-Analog Converter With a Distributed Biasing Scheme
A Three-Channel Package-Scale Galvanic Isolation Interface for Wide Bandgap Gate Drivers
A Progressive Performance Boosting Strategy for 3-D Charge-Trap NAND Flash
An FPGA Chip Identification Generator Using Configurable Ring Oscillators
CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis
A 10-Gb/s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations in 65-nm CMOS
Real-Time SSDLite Object Detection on FPGA
A hardware-efficient technique to implement a trellis code modulation decoder
Channel Estimator and Aliasing Canceller for Equalizing and Decoding Non-Cyclic Prefixed Single-Carrier Block Transmission via MIMO-OFDM Modem
Stream Processing Dual-Track CGRA for Object Inference
A "Flying-Adder" frequency synthesis architecture of reducing VCO stages
Unaligned Burst-Aware Memory Subsystem
Phase Distortion to Amplitude Conversion-Based Low-Cost Measurement of AM-AM and AM-PM Effects in RF Power Amplifiers
Machine-Learning-Based Self-Tunable Design of Approximate Computing
Embedded Transition Inversion Coding With Low Switching Activity for Serial Links
MPRTA: An Efficient Multilevel Parallel Mobile Accelerator for High-Performance Ray Tracing
A Single-Stage Low-Dropout Regulator With a Wide Dynamic Range for Generic Applications
Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level
MoE-Sched: Enabling Efficient FPGA Deployment of Mixture-of-Experts Vision Transformers via Coordinated Scheduling
Design and FPGA Implementation of Grid-Scroll Hamiltonian Conservative Chaotic Flows With a Line Equilibrium
Non-RAM-based architectural designs of wavelet-based digital systems based on novel nonlinear I/O data space transformations
Unrolled, Pipelined, and Stage-Folded Architectures for Encoding of Multi-Kernel Polar Codes
PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments
On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency Reduction
Efficient Designs of Multiported Memory on FPGA
Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing
Very Fast, High-Performance 5-2 and 7-2 Compressors in CMOS Process for Rapid Parallel Accumulations
A 5.4-mW 180-cm Transmission Distance 2.5-Mb/s Advanced Techniques-Based Novel Intrabody Communication Receiver Analog Front End
A practical methodology for the statistical design of complex logic products for performance
Postsilicon Trace Signal Selection Using Machine Learning Techniques
An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition
Sleep Mode Analysis and Optimization With Minimal-Sized Power Gating Switch for Ultra-Low ${V}_{\rm dd}$ Operation
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh
A 50-kHz BW, 84.6-dB SNDR Noise-Shaping SAR ADC With Capacitor-Mismatch-Error-Free Switching Scheme
A temporal bipartitioning algorithm for dynamically reconfigurable FPGAs
Area- and Power-Efficient Staircase Encoder Implementation for High-Throughput Fiber-Optical Communications
A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices
Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies
A Fast-Response Pseudo-PWM Buck Converter With PLL-Based Hysteresis Control
VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits
Hard-to-Detect Fault Analysis in FinFET SRAMs
Energy Aware Mapping for Reconfigurable Wireless MPSoCs
A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation
Reliable Architectures for Finite Field Multipliers Using Cyclic Codes on FPGA Utilized in Classic and Post-Quantum Cryptography
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations
A table masking countermeasure for low-energy secure embedded systems
Logic design error diagnosis and correction
Address-free memory access based on program syntax correlation of loads and stores
A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs
Transmission Coefficient Matrix Modeling of Spin-Torque-Based $n$ -Qubit Architecture
FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA
Design and Analysis of a 26-32-GHz 6-bit Passive Vector Modulation Phase Shifter for CMOS Bidirectional Transceiver
A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver
Equalization-Based Digital Background Calibration Technique for Pipelined ADCs
A solution methodology for exact design space exploration in a three-dimensional design space
High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm
Systolic Array Architectures for Sunar-Koç Optimal Normal Basis Type II Multiplier
MBSNTT: A Highly Parallel Digital In-Memory Bit-Serial Number Theoretic Transform Accelerator
A Study of 3-D Power Delivery Networks With Multiple Clock Domains
Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits
Fast Bit-Parallel Shifted Polynomial Basis Multiplier Using Weakly Dual Basis Over GF(2 m )
Asynchronous Sampling-Based Hybrid Equalizer
Static Test Compaction for Low-Power Test Sets by Increasing the Switching Activity
A structure-oriented power modeling technique for macrocells
Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication
Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits
A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method
A 24-30-GHz Four-Element Phased Array Transceiver With Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter for 5G Communication
Arbitrarily shaped rectilinear module placement using the transitive closure graph representation
Dynamic GPU Parallel Sparse LU Factorization for Fast Circuit Simulation
A framework for energy and transient power reduction during behavioral synthesis
Least-square estimation of average power in digital CMOS circuits
A 90-dB Omega 10-Gb/s Optical Receiver Analog Front-End in a 0.18µm CMOS Technology
Path Selection for Transition Path Delay Faults
Impact of III-V and Ge Devices on Circuit Performance
Diagnostic Test Point Insertion and Test Compaction
Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era
On methods to match a test pattern generator to a circuit-under-test
A 0.05-1.5-GHz PVT-Insensitive Digital-to-Time Converter for QKD Applications
A Sample-and-Hold-Based 453-ps True Time Delay Circuit With a Wide Bandwidth of 0.5-2.5 GHz in 65-nm CMOS
PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions
An Analytical Model Relating FPGA Architecture to Logic Density and Depth
Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults
Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of GF(2 m )
A Digital Frequency Multiplication Technique for Energy Efficient Transmitters
A 16-Core Voltage-Stacked System With Adaptive Clocking and an Integrated Switched-Capacitor DC-DC Converter
Exploring High-Throughput Computing Paradigm for Global Routing
VLSI implementation of low-power high-quality color interpolation processor for CCD camera
A 0.13-µm CMOS Current-Mode All-Pass Filter for Multi-GHz Operation
Scalable QoS-Aware Memory Controller for High-Bandwidth Packet Memory
Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes
VLSI-Assisted Nonrigid Registration Using Modified Demons Algorithm
Dynamic Power Management for the Iterative Decoding of Turbo Codes
Self-Repairing Digital System Based on State Attractor Convergence Inspired by the Recovery Process of a Living Cell
Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs
A 206 μW Vital Signs Monitoring System on Chip for Measuring Five Vitals
Eliminating Timing Errors Through Collaborative Design to Maximize the Throughput
A 0.45 V 147-375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures
Computing-in-Memory for Performance and Energy-Efficient Homomorphic Encryption
Hardware Architecture Based on Parallel Tiled QRD Algorithm for Future MIMO Systems
Calibration of Floating-Gate SoC FPAA System
Dynamic Reconfiguration of Thermoelectric Generators for Vehicle Radiators Energy Harvesting Under Location-Dependent Temperature Variations
A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor
Compacting Side-Channel Measurements With Amplitude Peak Location Algorithm
Low-Power and Compact Analog-to-Digital Converter Using Spintronic Racetrack Memory Devices
Conforming block inversion for low power memory
A Multilayer Framework Supporting Autonomous Run-Time Partial Reconfiguration
An efficient DMT modem for the G.LITE ADSL transceiver
VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems
Memory energy minimization by data compression: algorithms, architectures and implementation
Application and Product-Volume-Specific Customization of BEOL Metal Pitch
Avalanche: an environment for design space exploration and optimization of low-power embedded systems
Hybrid Monolithic 3-D IC Floorplanner
Incremental hardware estimation during hardware/software functional partitioning
Automatic delay correction method for IP block-based design of VLSI dedicated digital signal processing systems: theoretical foundations and implementation
An Optimized Low-Power VLSI Architecture for ECG/VCG Data Compression for IoHT Wearable Device Application
A Scalable MIMO Detector Processor With Near-ASIC Energy Efficiency
Statistical Framework for Designing On-Chip Thermal Sensing Infrastructure in Nanoscale Systems
Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations
32 Bit ×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler
Supply Noise Suppression by Triple-Well Structure
Fast Thermal Aware Placement With Accurate Thermal Analysis Based on Green Function
Pure Digital Scalable Mixed Entropy Separation Structure for Physical Unclonable Function and True Random Number Generator
A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique
A High-Efficiency, Wide Workload Range, Digital Off-Time Modulation (DOTM) DC-DC Converter With Asynchronous Power Saving Technique
Design and verification of SystemC transaction-level models
FISH: Fast Instruction SyntHesis for Custom Processors
Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies
A Low-Power Delay Buffer Using Gated Driver Tree
Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations
Charge-Recycling-Based Redundant Write Prevention Technique for Low-Power SOT-MRAM
Reconfigurable Systolic Array: From Architecture to Physical Design for NML
Runtime Power Management of Battery Electric Vehicles for Extended Range With Consideration of Driving Time
Comparator Power Reduction in Low-Frequency SAR ADC Using Optimized Vote Allocation
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits
Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM
Code Compression for Embedded Systems Using Separated Dictionaries
Efficient inductance extraction using circuit-aware techniques
Optimal interconnect diagnosis of wiring networks
A 64 ˟ 64 Pixels UWB Wireless Temporal-Difference Digital Image Sensor
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
Short-circuit power driven gate sizing technique for reducing power dissipation
A Time-Domain Reconfigurable Second-Order Noise Shaping ADC With Single Fan-Out Gated Delay Cells
A Linearity-Enhanced 10-Bit 160-MS/s SAR ADC With Low-Noise Comparator Technique
Architectural enhancements for network congestion control applications
432 nW per Channel 130 nV/rtHz ECG Acquisition Front End With Multifrequency Chopping
DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In
Fault Secure Encoder and Decoder for NanoMemory Applications
An Enhanced Canary-Based System With BIST for SRAM Standby Power Reduction
A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction
A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees
Global scheduling with code-motions for high-level synthesis applications
A Picowatt CMOS Voltage Reference Using Independent TC and Output Level Calibrations
Obfuscating DSP Circuits via High-Level Transformations
Modeling and comparing CMOS implementations of the C-element
Toward Reliable Onboard AI in Space: A Fault-Tolerant Soft GPU-Based System-on-Chip
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits
Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip
Moment models of general transmission lines with application to interconnect analysis and optimization
Design of SEU-Tolerant Turbo Decoders Implemented on SRAM-FPGAs
A Dynamic General Accelerator for Integer and Fixed-Point Processing
Effects of simultaneous switching noise on the tapered buffer design
A Scalable FPGA Architecture With Adaptive Memory Utilization for GEMM-Based Operations
A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector
Synthesis of hardware models in C with pointers and complex data structures
Selecting Functional Test Sequences for Defect Diagnosis
MARVLE: a VLSI chip for data compression using tree-based codes
Segmented Architecture for Successive Approximation Analog-to-Digital Converters
Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure
ATT-TA: A Cooperative Multiagent Deep Reinforcement Learning Approach for TSV Assignment in 3-D ICs
VLSI architectures for turbo codes
Searching for Spectrum Holes: A 400-800 MHz Spectrum Sensing System
System-level performance evaluation of three-dimensional integrated circuits
Two-Port PCM Architecture for Network Processing
PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks
PD/SOI SRAM performance in presence of gate-to-body tunneling current
Alternatives to Bicubic Interpolation Considering FPGA Hardware Resource Consumption
High-Entropy STT-MTJ-Based TRNG
A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing
Glitch-Free NAND-Based Digitally Controlled Delay-Lines
A High-Speed Low-Noise Comparator With Auxiliary-Inverter-Based Common Mode-Self-Regulation for Low-Supply-Voltage SAR ADCs
A 0.64 mm 2 Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction
Wave-pipelining: a tutorial and research survey
±0.25-V Class-AB CMOS Capacitance Multiplier and Precision Rectifiers
RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing
Design and Implementation of Time and Frequency Synchronization in LTE
System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip
An Algorithm for Improving the Throughput of Serial Low-Complexity Chase Soft-Decision Reed-Solomon Decoder
Impact of Bias Temperature Instability on Soft Error Susceptibility
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
Guest Editorial: Special Issue on the International Symposium on Integrated Circuits and Systems - ISICAS 2025
Nonlinear Multi-Error Correction Codes for Reliable MLC nand Flash Memories
Routability checking for three-dimensional architectures
Distributed On-Chip Switched-Capacitor DC-DC Converters Supporting DVFS in Multicore Systems
Ground Switching Load Modulation With Ground Isolation for Passive HF RFID Transponders
Automatic Test Generation for Combinational Threshold Logic Networks
A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration Tree
A 65-nm CMOS Downconverter-Less Clock Generator Architecture Using Voltage Stacking of Oscillator and Frequency Dividers for Scaling-Friendly IoTs
On Test Compaction of Broadside and Skewed-Load Test Cubes
Design Exploration of Quadrature Methods in Option Pricing
Wafer-Level Modular Testing of Core-Based SoCs
Discretized Network Flow Techniques for Timing and Wire-Length Driven Incremental Placement With White-Space Satisfaction
TiM-DNN: Ternary In-Memory Accelerator for Deep Neural Networks
Redundancy revisited
Adaptive delay estimation for partitioning-driven PLD placement
Adaptive Machine Learning-Based Proactive Thermal Management for NoC Systems
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses
An ultra-fast instruction set simulator
Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement
Routability of Network Topologies in FPGAs
Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops
A Reconfigurable Clock Polarity Assignment Flow for Clock Gated Designs
High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications
Effects of speculation on performance and issue queue design
Half-Rate Clock-Embedded Source Synchronous Transceivers in 130-nm CMOS