yusuke1997/dblp-id-title huggingface dataset:
Reducing leakage in a high-performance deep-submicron instruction cache
Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector
iEDCL: Streamlined, False-Error-Free Error Detection and Correction Scheme in a Near-Threshold Enabled 32-bit Processor
The Implementation of the Improved OMP for AIC Reconstruction Based on Parallel Index Selection
Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design
An Electrical Model for Nanometer CMOS Device Stress Effect in Design and Simulation of Analog Reference Circuits
Electromigration- and Parasitic-Aware ILP-Based Analog Router
Novel Class of Energy-Efficient Very High-Speed Conditional Push-Pull Pulsed Latches
An FPGA-Based Phase Measurement System
Homogeneous Stream Processors With Embedded Special Function Units for High-Utilization Programmable Shaders
A 3.7-nW 248-ppm/°C Subthreshold Self-Biased CMOS Current Reference
Minimizing the Maximum Processor Temperature by Temperature-Aware Scheduling of Real-Time Tasks
A Redundancy-Based Calibration Technique for High-Speed Digital-to-Analog Converters
A 2- μs Fast-Response Step-Up Converter With Efficiency-Enhancement Techniques Suitable for Cluster-Based Wireless Sensor Networks
ASIC and FPGA Implementation of the Gaussian Mixture Model Algorithm for Real-Time Segmentation of High Definition Video
A 12-Bit Current-Steering DAC With Unary- Splitting -Binary Segmented Architecture and Improved Decoding Circuit Topology
A combined gate replacement and input vector control approach for leakage current reduction
Unified VLSI systolic array design for LZ data compression
Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications
Radiation-Hard Field-Programmable Gate Arrays Configuration Technique Using Silicon on Sapphire
Single-Layer Delay-Driven GNR Nontree Routing Under Resource Constraint for Yield Improvement
Power Distribution Attacks in Multitenant FPGAs
A New VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm
Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Nonbinary LDPC Codes Over Subfields
Application Mapping Onto Manycore Processor Architectures Using Active Search Framework
A Monolithic Voltage-Scalable Fibonacci Switched-Capacitor DC-DC Converter With Intrinsic Parasitic Charge Recycling
Active Cache Emulator
Robust interfaces for mixed-timing systems
Multiple-Mode-Supporting Floating-Point FMA Unit for Deep Learning Processors
Bus encoding for total power reduction using a leakage-aware buffer configuration
Dual C- and S-Band CMOS VCO Using the Shunt Varactor Switch
A Wideband Blocker-Tolerant Receiver With Frequency-Translational Resistive Feedback
A Reconfigurable CMOS Stack Rectifier With 22.8-dB Dynamic Range Achieving 47.91% Peak PCE for IoT/WSN Application
CPU Architecture Based on a Hardware Scheduler and Independent Pipeline Registers
A 65 nm CMOS Analog Programmable Standard Cell Library for Mixed-Signal Computing
A game theoretic approach for power optimization during behavioral synthesis
Guest Editorial Special Section on System-on-Chip Integration: Challenges and Implications
All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate
Analyzing the Impact of Joint Optimization of Cell Size, Redundancy, and ECC on Low-Voltage SRAM Array Total Area
Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell
Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device
Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation
Diagnosis and correction of multiple logic design errors in digital circuits
Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application
A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm 2
Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic
RETRO: Reintroducing Tests for Improved Reverse Order Fault Simulation
Memristor MOS Content Addressable Memory (MCAM): Hybrid Architecture for Future High Performance Search Engines
Light-Weight On-Chip Structure for Measuring Timing Uncertainty Induced by Noise in Integrated Circuits
A Rail-to-Rail Transconductance Amplifier Based on Current Generator Circuits
Low-Power Diagnostic Test Sets for Transition Faults Based on Functional Broadside Tests
Estimating and Mitigating Aging Effects in Routing Network of FPGAs
A 2.56-GS/s 12-bit 8x-Interleaved ADC With 156.6-dB FoM S in 65-nm CMOS
Symbiote Coprocessor Unit - A Streaming Coprocessor for Data Stream Acceleration
Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield
Testing complex couplings in multiport memories
Design and Implementation of a CMOS 4-Bit 12-GS/s Data Acquisition System-On-Chip
Guest Editorial Special Section on Application Specific Processors
Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications
Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend
A 12-14.5-GHz 10.2-mW -249-dB FoM Fractional-N Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS
New Crosstalk Avoidance Codes Based on a Novel Pattern Classification
Middle terminal cell models for efficient over-the-cell routing in high-performance circuits
Extended Transparent-Scan
Decreased Effectiveness of On-Chip Decoupling Capacitance in High-Frequency Operation
Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling
A 7.1-mW K/K a -Band Mixer With Configurable Bondwire Resonators in 65-nm CMOS
Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base"
On the Analysis and the Mitigation of Power Supply Noise and Power Distribution Network Impedance Variation for Scan-Based Delay Testing Techniques
In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis
A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes
Reconfigurable All-Band RF CMOS Transceiver for GPS/GLONASS/Galileo/Beidou With Digitally Assisted Calibration
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{\mathrm {cm}}$ -Based Switching
Automatic Design of Reconfigurable Domain-Specific Flexible Cores
Optimal Overlapped Message Passing Decoding of Quasi-Cyclic LDPC Codes
EFFORT: A Comprehensive Technique to Tackle Timing Violations and Improve Energy Efficiency of Near-Threshold Tensor Processing Units
SCERPA Simulation of Clocked Molecular Field-Coupling Nanocomputing
Error Correction Encoding for Tightly Coupled On-Chip Buses
Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS
Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations
Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers
Code Compression and Decompression for Coarse-Grain Reconfigurable Architectures
Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I - Device-Circuit Interaction and Evaluation at Device Level
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator
Efficient network folding techniques for routing permutations in VLSI
An Approach for Adaptive DRAM Temperature and Power Management
Delay-Constrained GNR Routing for Layer Minimization
Micro-operation cache: a power aware frontend for variable instruction length ISA
Scalable Hardware Trojan Diagnosis
Fault Demotion Using Reconfigurable Slack (FaDReS)
SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards
STT-RAM Cache Hierarchy With Multiretention MTJ Designs
Power Side-Channel Leakage Assessment Framework at Register-Transfer Level
A 0.65-V, 500-MHz Integrated Dynamic and Static RAM for Error Tolerant Applications
Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction
A Sub-1-V 65-nm MOS Threshold Monitoring-Based Voltage Reference
Guest Editorial Special Section on Configurable Computing Design-II: Hardware Level Reconfiguration
RTN in Scaled Transistors for On-Chip Random Seed Generation
A syntax-directed translation for the synthesis of delay-insensitive circuits
On the design of low-voltage, low-power CMOS analog multipliers for RF applications
Implementing Multiphase Resonant Clocking on a Finite-Impulse Response Filter
Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms
Securing Emerging Nonvolatile Main Memory With Fast and Energy-Efficient AES In-Memory Implementation
Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention
A Test Chip for Characterization of the Series Association of MOSFETs
A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOS
Efficient Successive Cancellation Stack Decoder for Polar Codes
Efficient metrics and high-level synthesis for dynamically reconfigurable logic
Predictive-Flow-Queue-Based Energy Optimization for Gigabit Ethernet Controllers
Efficient Package Pin-Out Planning With System Interconnects Optimization for Package-Board Codesign
Parameterized RTL power models for soft macros
A High-Speed Low-Complexity Modified Radix -2 5 FFT Processor for High Rate WPAN Applications
System level hardware module generation
Toward an Energy-Efficient High-Voltage Compliant Visual Intracortical Multichannel Stimulator
A 5-/20-MHz BW Reconfigurable Quadrature Bandpass CT ΔΣ ADC With AntiPole-Splitting Opamp and Digital I/Q Calibration
An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz
A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs Architecture
A 100-mV-2.5-V Burst Mode Constant on-Time- Controlled Battery Charger With 92% Peak Efficiency and Integrated FOCV Technique
A 25-30-GHz RMS Error-Minimized 360° Continuous Analog Phase Shifter Using Closed-Loop Self-Tuning I/Q Generator
A 350-MS/s Continuous-Time Delta-Sigma Modulator With a Digitally Assisted Binary-DAC and a 5-Bits Two-Step-ADC Quantizer in 130-nm CMOS
Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels
A 1-V 4-mW Differential-Folded Mixer With Common-Gate Transconductor Using Multiple Feedback Achieving 18.4-dB Conversion Gain, +12.5-dBm IIP3, and 8.5-dB NF
TVLA*: Test Vector Leakage Assessment on Hardware Implementations of Asymmetric Cryptography Algorithms
Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver
A Check-and-Balance Scheme in Multiphase Delay-Locked Loop
Efficient statistical approach to estimate power considering uncertain properties of primary inputs
Interface optimization for concurrent systems under timing constraints
A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations
Application-Dependent Testing of FPGA Interconnect Network
A 65-nm CMOS Constant Current Source With Reduced PVT Variation
Efficiency Optimization of Silicon Photonic Links in 65-nm CMOS and 28-nm FDSOI Technology Nodes
A Generally Applicable Calibration Algorithm for Digitally Reconfigurable Self-Healing RFICs
Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links
Current-mode signaling in deep submicrometer global interconnects
Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing
A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs
A Comparative Analysis of Low Temperature and Room Temperature Circuit Operation
Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip
Correction to "design of synchronous and asynchronous variable-latency pipelined multipliers"
Write Assist Circuit to Cater Reliability and Floating Bit Line Problem of Negative Bit Line Assist Technique for Single or Multiport Static Random Access Memory
Fast and Reliable STT-MRAM Using Nonuniform and Adaptive Error Detecting and Correcting Scheme
REMOD: a new methodology for designing fault-tolerant arithmetic circuits
A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies
Estimation of FMAX and ISB in microprocessors
Predictive Application of PIDF and PPC for Interconnects' Crosstalk, TSV, and LER Issues in UDSM ICs and Nano-Systems
Reliable and fast reconfigurable hierarchical interconnection networks for linear WSI arrays
FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation
Backend Dielectric Reliability Full Chip Simulator
A Power-Efficient Spectrum-Sensing Scheme Using 1-Bit Quantizer and Modified Filter Banks
Estimating Information-Theoretical nand Flash Memory Storage Capacity and its Implication to Memory System Design Space Exploration
System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators
Corrections to "A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones"
WCET-Aware Re-Scheduling Register Allocation for Real-Time Embedded Systems With Clustered VLIW Architecture
On exploring inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms
Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits
A Synchronous 50% Duty-Cycle Clock Generator in 0.35- μ m CMOS
A 2.5 Gb/s ATM switch chip set
Duty-Cycle-Based Controlled Physical Unclonable Function
Corrections to "Enhancing Memory BIST With an Optimized RTL-BIST IP Core: A Low-Power, High-Fault-Coverage Approach"
High-Density SOT-MRAM Based on Shared Bitline Structure
A 152-mW Mobile Multimedia SoC With Fully Programmable 3-D Graphics and MPEG4/H.264/JPEG
A Comparative Study of the Effectiveness of CPU Consolidation Versus Dynamic Voltage and Frequency Scaling in a Virtualized Multicore Server
A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems
Scalable and Low-Cost NTT Architecture With Conflict-Free Memory Access Scheme
A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network
A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET
Improving a Ka-Band Integrated Balanced Power Amplifier Performance by Compensating Quadrature Hybrid Mismatch Effects
Performance-driven synthesis in controller-datapath systems
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements
Domain Wall Interconnections for NML
Low-power and high-quality signal transmission baseband LSIC for personal communications
A Pre-Activation, Golden IC Free, Hardware Trojan Detection Approach
Body-Bias-Driven Design Strategy for Area- and Performance-Efficient CMOS Circuits
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols
Energy-Efficient Logarithmic Square Rooter for Error-Resilient Applications
Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture
Amoeba: An Efficient and Flexible FPGA-Based Accelerator for Arbitrary-Kernel CNNs
Synthesis for logical initializability of synchronous finite-state machines
Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs
Machine Learning Prediction for Design and System Technology Co-Optimization Sensitivity Analysis
Crosstalk Noise in WDM-Based Optical Networks-on-Chip: A Formal Study and Comparison
Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base
Pipelining communications in large VLSI/ULSI systems
Reliability-Aware Design Flow for Silicon Photonics On-Chip Interconnect
A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling
TrustGuard: Standalone FPGA-Based Security Monitoring Through Power Side-Channel
Enhancing the Performance of Symmetric-Key Cryptography via Instruction Set Extensions
A C-testable carry-free divider
Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains
A Mobile 3-D Display Processor With A Bandwidth-Saving Subdivider
Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation
A Small Ripple and High-Efficiency Wordline Voltage Generator for 3-D nand Flash Memories
Parallel High-Order Envelope-Following Method for Fast Transient Analysis of Highly Oscillatory Circuits
Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs
A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications
BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture
Sequence-switch coding for low-power data transmission
Low-Complexity Interval Passing Algorithm and VLSI Architecture for Binary Compressed Sensing
Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System
An Ultralow-Power OOK/BFSK/DBPSK Wake-Up Receiver Based on Injection-Locked Oscillator
A survey of design techniques for system-level dynamic power management
A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis
A 25-GS/s 8-bit Current-Steering DAC With ADC-Based Duty-Cycle Detection in 40-nm CMOS
Expression-tree-based algorithms for code compression on embedded RISC architectures
SiMT-DSP: A Massively Multithreaded DSP Architecture
A 96-Gb/s 1.6-V ppd PAM-8 Transmitter With High-Swing and Low-Loading Cascaded Driver in 40-nm CMOS Technology
Distributed TSV Topology for 3-D Power-Supply Networks
A Buffer-in-Loop NS-SAR ADC With CDAC Sharing-Error Feedback Structure and kT/C Noise Cancellation in 0.18-μm CMOS Technology
Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs
Design of an Error Detection and Data Recovery Architecture for Motion Estimation Testing Applications
Through-Silicon Via Planning in 3-D Floorplanning
On the Sensitization Probability of a Critical Path Considering Process Variations and Path Correlations
Universal delay test sets for logic networks
Embedded Memories Fault-Tolerant Pre- and Post-Silicon Optimization
Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment
The selective extra stage butterfly
Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating
Test-decompression mechanism using a variable-length multiple-polynomial LFSR
Detect and Replace: Efficient Soft Error Protection of FPGA-Based CNN Accelerators
CMOS Full-Adders for Energy-Efficient Arithmetic Applications
Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses
Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits
Study of energy and performance of space-time decoding systems in concatenation with turbo decoding
3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits
Finite field inversion over the dual basis
Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint
Agile-X: A Structured-ASIC Created With a Mask-Less Lithography System Enabling Low-Cost and Agile Chip Fabrication
Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption
Built-in self-test (BIST) design of high-speed carry-free dividers
Dynamic Context Compression for Low-Power Coarse-Grained Reconfigurable Architecture
An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation
Design of a 20-mb/s 256-state Viterbi decoder
Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions
System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design
Low-Latency ECDSA Signature Verification - A Road Toward Safer Traffic
RTGEN-an algorithm for automatic generation of reservation tables from architectural descriptions
Exploring the Use of Emerging Nonvolatile Memory Technologies in Future FPGAs
Two New Techniques Integrated for Energy-Efficient TLB Design
From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding
Complementary Voltage to Time Converter With Optimized Voltage Scaling Circuit
Early Selection of Critical Paths for Reliable NBTI Aging-Delay Monitoring
A 2-24-GHz 360° Full-Span Differential Vector Modulator Phase Rotator With Transformer-Based Poly-Phase Quadrature Network
A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs
RSYN: a system for automated synthesis of reliable multilevel circuits
Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC
A Second-Order Continuous-Time Noise-Shaping SAR ADC With Ping-Pong DACs and G m -OTA-C Integrator
Prelayout estimation of individual wire lengths
A Scaling-Assisted Signed Integer Comparator for the Balanced Five-Moduli Set RNS 2 n -1, 2 n , 2 n + 1, 2 n+1 -1, 2 n-1 -1
CapsBeam: Accelerating Capsule Network-Based Beamformer for Ultrasound Nonsteered Plane-Wave Imaging on Field-Programmable Gate Array
Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence Pairs
Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA
Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization
A Low-Power Sensitive Integrated Sensor System for Thermal Flow Monitoring
CDelta IDDQ : Improving Current-Based Testing and Diagnosis Through Modified Test Pattern Generation
Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies
Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise
A 12.93-16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection
Design and realization of high-performance wave-pipelined 8×8 b multiplier in CMOS technology
On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard
A Spintronics Memory PUF for Resilience Against Cloning Counterfeit
A 40-nm 16-Mb Contact-Programming Mask ROM Using Dual Trench Isolation Diode Bitcell
Logic-in-Memory With a Nonvolatile Programmable Metallization Cell
Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors
A DfT Insertion Methodology to Scannable Q-Flop Elements
New Implementations of the WG Stream Cipher
RVSLH: Acceleration of Postquantum Standard SLH-DSA With Customized RISC-V Processor
Enhancing Utilization of SIMD-Like Accelerator for Sparse Convolutional Neural Networks
Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems
A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency
Enabling testability of fault-tolerant circuits by means of I DDQ -checkable voters
High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost
Fault-Tolerant Inverters for Reliable Photovoltaic Systems
Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through
Low-power data forwarding for VLIW embedded architectures
Optimizing Video Application Design for Phase-Change RAM-Based Main Memory
A 100-MS/s-5-GS/s, 13-5-bit Nyquist-Rate Reconfigurable Time-Domain ADC
A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation
20-Gb/s CMOS EA/MZ Modulator Driver With Intrinsic Parasitic Feedback Network
Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing
H 2 ONoC: A Hybrid Optical-Electronic NoC Based on Hybrid Topology
Hardware Designer's Guide to Fault Attacks
Fully Integrated 10-GHz Active Circulator and Quasi-Circulator Using Bridged-T Networks in Standard CMOS
Fast Design Optimization Through Simple Kriging Metamodeling: A Sense Amplifier Case Study
Profit Aware Circuit Design Under Process Variations Considering Speed Binning