yusuke1997/dblp-id-title huggingface dataset:
Modular Compilation of Hybrid Systems for Emulation and Large Scale Simulation
OnSRAM: Efficient Inter-Node On-Chip Scratchpad Management in Deep Learning Accelerators
A design methodology for application-specific networks-on-chip
ICNN: The Iterative Convolutional Neural Network
dMazeRunner: Executing Perfectly Nested Loops on Dataflow Accelerators
Introduction to the special section on wireless health systems
SEAMS: Self-Optimizing Runtime Manager for Approximate Memory Hierarchies
Evaluating Controlled Memory Request Injection for Efficient Bandwidth Utilization and Predictable Execution in Heterogeneous SoCs
A Framework for Supporting Adaptive Fault-Tolerant Solutions
A Scalable Algebraic Method to Infer Quadratic Invariants of Switched Systems
Efficient asynchronous event handling in the real-time specification for Java
Task Transition Scheduling for Data-Adaptable Systems
An Approach to the Systematic Characterization of Multitask Accelerated CNN Inference in Edge MPSoCs
Analysis of SystemC actor networks for efficient synthesis
High-Performance Implementation of the Identity-Based Signature Scheme in IEEE P1363 on GPU
TAB: Unified and Optimized Ternary, Binary, and Mixed-precision Neural Network Inference on the Edge
A Design-Time/Run-Time Application Mapping Methodology for Predictable Execution Time in MPSoCs
SLEXNet: Adaptive Inference Using Slimmable Early Exit Neural Networks
CaffePresso: Accelerating Convolutional Networks on Embedded SoCs
Lane Compression: A Lightweight Lossless Compression Method for Machine Learning on Embedded Systems
TinyM 2 Net-V2: A Compact Low-power Software Hardware Architecture for Multimodal Deep Neural Networks
Parallelizing load/stores on dual-bank memory embedded processors
Toward Customized Hybrid Fuel-Cell and Battery-powered Mobile Device for Individual Users
ANV-PUF: Machine-Learning-Resilient NVM-Based Arbiter PUF
Grasp-HGN: Grasping the Unexpected
Resource Synchronization and Preemption Thresholds Within Mixed-Criticality Scheduling
A Principled Approach to Secure Multi-core Processor Design with ReWire
Write activity reduction on non-volatile main memories for embedded chip multiprocessors
Scalable Binary Neural Network Applications in Oblivious Inference
Regime Inference for Sound Floating-Point Optimizations
Static resource models for code-size efficient embedded processors
On-Board Format-Independent Security of Functional Magnetic Resonance Images
Antlab: A Multi-Robot Task Server
Functional test generation using design and property decomposition techniques
No-Heap remote objects for distributed real-time Java
Formal Modeling of Hybrid System Based on Semi-continuous Colored Petri Net: A Case Study of Adaptive Cruise Control System
Fast exploration of bus-based communication architectures at the CCATB abstraction
Profiling and online system-level performance and power estimation for dynamically adaptable embedded systems
An FPGA-Based Architecture for High-Speed Compressed Signal Reconstruction
A Collaborative Energy-Aware Sensor Management System Using Team Theory
A Composable Monitoring System for Heterogeneous Embedded Platforms
Hephaestus: Codesigning and Automating 3D Image Registration on Reconfigurable Architectures
Contention-free executions for real-time multiprocessor scheduling
A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels
The worst-case execution-time problem - overview of methods and survey of tools
Thermal Management for 3D-Stacked Systems via Unified Core-Memory Power Regulation
SHARP: SHARing-Aware Cache Writeback byPass
A Workload-Balance-Aware Accelerator Enabling Dense-to-Arbitrary-Sparse Neural Networks
Experiences with context management in emergency medicine
A Retargetable MATLAB-to-C Compiler Exploiting Custom Instructions and Data Parallelism
Edge Intelligence: Concepts, Architectures, Applications, and Future Directions
Synthesis-guided Adversarial Scenario Generation for Gray-box Feedback Control Systems with Sensing Imperfections
Parameter Space Representation of Pareto Front to Explore Hardware-Software Dependencies
Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies
Winograd Convolution for Deep Neural Networks: Efficient Point Selection
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach
VecRA: A Vector-Aware Register Allocator for GPU Shader Processors
Cache coherence tradeoffs in shared-memory MPSoCs
Cache Locking Content Selection Algorithms for ARINC-653 Compliant RTOS
Editorial: Big Data, Internet of Things, Cybersecurity - A New Trinity of Embedded Systems Research
Deterministic Coordination across Multiple Timelines
CxDNN: Hardware-software Compensation Methods for Deep Neural Networks on Resistive Crossbar Systems
WasmAndroid: A Cross-Platform Runtime for Native Programming Languages on Android
Editorial: Embedded systems - more than methodology
Implementation of Partitioned Mixed-Criticality Scheduling on a Multi-Core Platform
A Granularity-Based Clustering Method for Reducing Write Amplification in Solid-State Drives
Exact Safety Verification of Hybrid Systems Based on Bilinear SOS Representation
Plug&Chip: A Framework for Supporting Rapid Prototyping of 3D Hybrid Virtual SoCs
Parametric Scheduler Characterization
Quality Estimation and Optimization of Adaptive Stereo Matching Algorithms for Smart Vehicles
Software thread integration for instruction-level parallelism
Optimizing Sparse Matrix Convolution on RISC-V Core: Custom Instructions for Embedded System
A Hybrid Genetic Algorithm for the Bottleneck Traveling Salesman Problem
Integrated Code Generation for Loops
Modular DFR: Digital Delayed Feedback Reservoir Model for Enhancing Design Flexibility
Toward Smart Embedded Systems: A Self-aware System-on-Chip (SoC) Perspective
Memory-Model-Aware Testing: A Unified Complexity Analysis
Energy Management for Fault-tolerant (m,k)-constrained Real-time Systems That Use Standby-Sparing
LeakyRand: An Efficient High-fidelity Covert Channel in Fully Associative Last-level Caches with Random Eviction
An Automated Security-Aware Approach for Design of Embedded Systems on MPSoC
Toward Object-oriented Modeling in SCCharts
Hardware Performance Counters: Ready-Made vs Tailor-Made
Efficient-Grad: Efficient Training Deep Convolutional Neural Networks on Edge Devices with Gradient Optimizations
Extended Instruction Exploration for Multiple-Issue Architectures
A Unified Approach to a Secure and Lightweight Mutual Authentication Protocol Using Pre-Characterized COTS SRAM ICs for IoT Applications
A Proven Translation from a UML State Machine Subset to Timed Automata
Evaluating Network Processors using NetBench
EAVE: Error-Aware Video Encoding Supporting Extended Energy/QoS Trade-offs for Mobile Embedded Systems
Introduction to the special section on ESTIMedia'10
Parallel SystemC Simulation for ESL Design
Synergistically Exploiting CNN Pruning and HLS Versioning for Adaptive Inference on Multi-FPGAs at the Edge
Mining Missing Assumptions from Counter-Examples
Parametric timing analysis and its application to dynamic voltage scaling
Special Issue on Open Hardware for Embedded System Security and Cryptography
Automatic rate desynchronization of embedded reactive programs
Deep network packet filter design for reconfigurable devices
Scratchpad-Memory Management for Multi-Threaded Applications on Many-Core Architectures
Data remapping for design space optimization of embedded memory systems
HLS-based High-throughput and Work-efficient Synthesizable Graph Processing Template Pipeline
Nucleus: Finding the Sharing Limit of Heterogeneous Cores
Techniques and Analysis for Mixed-criticality Scheduling with Mode-dependent Server Execution Budgets
Mapping Computations in Heterogeneous Multicore Systems with Statistical Regression on Program Inputs
Energy-Efficient Real-Time Scheduling of DAG Tasks
Automatic Parallelization of Multirate Block Diagrams of Control Systems on Multicore Platforms
Scheduling of synchronous data flow models onto scratchpad memory-based embedded processors
Error Detector Placement for Soft Computing Applications
Thermal-aware Adaptive Platform Management for Heterogeneous Embedded Systems
A Segmented Adaptive Router for Near Energy-Proportional Networks-on-Chip
An efficient, low-cost routing framework for convex mesh partitions to support virtualization
Coarse-Grained Task Parallelization by Dynamic Profiling for Heterogeneous SoC-Based Embedded System
Compact and Flexible FPGA Implementation of Ed25519 and X25519
Ensuring Secure Application Execution and Platform-Specific Execution in Embedded Devices
ViT4Mal: Lightweight Vision Transformer for Malware Detection on Edge Devices
SAGE: A Split-Architecture Methodology for Efficient End-to-End Autonomous Vehicle Control
Protecting Caches from Soft Errors: A Microarchitect's Perspective
Reflexes: Abstractions for integrating highly responsive tasks into Java applications
RT-ZooKeeper: Taming the Recovery Latency of a Coordination Service
Configuration and operation of networked control systems over heterogeneous WSANs
Demystifying Energy Consumption Dynamics in Transiently powered Computers
Interactive schedulability analysis
Secure routing based on distributed key sharing in large-scale sensor networks
Dynamic Cluster Head Selection in WSN
Editorial: Special issue on dynamically adaptable embedded systems
Killing Processes or Killing Flash? Escaping from the Dilemma Using Lightweight, Compression-Aware Swap for Mobile Devices
Efficient Schedulability Test for Dynamic-Priority Scheduling of Mixed-Criticality Real-Time Systems
Design of a High-Performance CDMA-Based Broadcast-Free Photonic Multi-Core Network on Chip
Hardware Performance Counter-Based Fine-Grained Malware Detection
Analysis and design of a hardware/software trusted platform module for embedded systems
DaCapo: An On-Device Learning Scheme for Memory-Constrained Embedded Systems
Data space-oriented tiling for enhancing locality
ATCN: Resource-efficient Processing of Time Series on Edge
A Hardware Pipeline with High Energy and Resource Efficiency for FMM Acceleration
Simulation-Driven Reachability Using Matrix Measures
Error-Aware Algorithm/Architecture Coexploration for Video Over Wireless Applications
The design of dynamically reconfigurable datapath coprocessors
Analyzing an embedded sensor with timed automata in uppaal
Quantifying the Information Leakage in Cache Attacks via Symbolic Execution
CAN Bus Intrusion Detection Based on Auxiliary Classifier GAN and Out-of-distribution Detection
Activation Map-based Knowledge Distillation for Real-time Cervical OCT Image Classification
Data-Driven Synchronization for Internet-of-Things Systems
Hybrid compilation and optimization for java-based digital TV platforms
Treble: Fast Software Updates by Creating an Equilibrium in an Active Software Ecosystem of Globally Distributed Stakeholders
On the Verification of Concurrent, Asynchronous Programs with Waiting Queues
Robust Reachable Set: Accounting for Uncertainties in Linear Dynamical Systems
Synthesis of Error-Recovery Protocols for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
On-device Prior Knowledge Incorporated Learning for Personalized Atrial Fibrillation Detection
Transmission power assignment with postural position inference for on-body wireless communication links
A Brief Comment on "A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs" [ACM Transactions on Embedded Computing Systems 12 (2013) Article 106]
Implementation strategy for downgraded flash-memory storage devices
Multi-Traffic Resource Optimization for Real-Time Applications with 5G Configured Grant Scheduling
Pacemaker control of heart rate variability: A cyber physical system perspective
Adaptive scheduling of real-time systems cosupplied by renewable and nonrenewable energy sources
Exploiting LDPC Syndrome for Multidimensional Hard-Decoding Read Retry on NAND Flash
MaPHeA: A Framework for Lightweight Memory Hierarchy-aware Profile-guided Heap Allocation
Design and Scaffolded Training of an Efficient DNN Operator for Computer Vision on the Edge
Scheduling refinement in abstract RTOS models
Domain-Specific Architectures: Research Problems and Promising Approaches
An Ultra-Low Energy Human Activity Recognition Accelerator for Wearable Health Applications
Semantics-preserving multitask implementation of synchronous programs
Physics-Driven Page Fault Handling for Customized Deception against CPS Malware
Mobile query services in a participatory embedded sensing environment
Robust implicit EDF: A wireless MAC protocol for collaborative real-time systems
System-Level Design Optimization for Security-Critical Cyber-Physical-Social Systems
Energy-efficient and high-performance software architecture for storage class memory
Throughput-memory footprint trade-off in synthesis of streaming software on embedded multiprocessors
Ultra-low-power adder stage design for exascale floating point units
Crenel-Interval-Based Dynamic Power Management for Periodic Real-Time Systems
Predictable and configurable component-based scheduling in the Composite OS
FPGA Stream-Monitoring of Real-time Properties
Hierarchical agent monitoring design approach towards self-aware parallel systems-on-chip
Shared heap management for memory-limited java virtual machines
Memory performance estimation of CUDA programs
System/network design-space exploration based on TLM for networked embedded systems
TH-iSSD: Design and Implementation of a Generic and Reconfigurable Near-Data Processing Framework
Runtime Adaptivity for Efficient Neural Network Inference on Autonomous Systems
Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling
A Write-Related and Read-Related DRAM Allocation Strategy Inside Solid-State Drives (SSDs)
Sound Mixed Fixed-Point Quantization of Neural Networks
Middleware for Distributed Applications in a LoRa Mesh Network
Code transformation and instruction set extension
RISE: An Automated Framework for Real-Time Intelligent Video Surveillance on FPGA
Harmonic Segment-Based Semi-Partitioning Scheduling on Multi-Core Real-Time Systems
Loop-Oriented Pointer Analysis for Automatic SIMD Vectorization
Optimizing rapidIO architectures for onboard processing
SAT-Reach: A Bounded Model Checker for Affine Hybrid Systems
Predicting the Long-Term Behavior of a Micro-Solar Power System
Efficient Elliptic Curve Cryptography for Embedded Devices
Design and Implementation of Warbler Family of Lightweight Pseudorandom Number Generators for Smart Devices
Detection of harmful schizophrenic statements in esterel
Cache partitioning for energy-efficient and interference-free embedded multitasking
Robust LFSR-based Scrambling to Mitigate Stencil Attack on Main Memory
A Robust Mechanism for Adaptive Scheduling of Multimedia Applications
iAware: Interaction Aware Task Scheduling for Reducing Resource Contention in Mobile Systems
A new efficient EDA tool design methodology
LiteHash: Hash Functions for Resource-Constrained Hardware
ZIP-CNN: Design Space Exploration for CNN Implementation within a MCU
Structured Proofs for Adversarial Cyber-Physical Systems
Minimising Access Conflicts on Shared Multi-Bank Memory
SENNA: Unified Hardware/Software Space Exploration for Parametrizable Neural Network Accelerators
Anonymous Split E-Cash - Toward Mobile Anonymous Payments
Compositional real-time scheduling framework with periodic model
Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions
RTPL: A Real-Time Communication Protocol for LoRa Network
Tutorial: Toward Robust Deep Learning against Poisoning Attacks
Secure and Lightweight Blockchain-based Truthful Data Trading for Real-Time Vehicular Crowdsensing
Honey, I Shrunk the ELFs: Lightweight Binary Tailoring of Shared Libraries
A New HW/SW Co-Design Approach for Monitored Systems-on-Chip Development
DLSeF: A Dynamic Key-Length-Based Efficient Real-Time Security Verification Model for Big Data Stream
Scabbard: An Exploratory Study on Hardware Aware Design Choices of Learning with Rounding-based Key Encapsulation Mechanisms
Guest Editorial for the Special Issue of ESWEEK 2016
Transient Fault Detection in Tensor Cores for Modern GPUs
Energy-Efficient Thread Assignment Optimization for Heterogeneous Multicore Systems
MemATr: An Efficient and Lightweight Memory-augmented Transformer for Video Anomaly Detection
Improving SDRAM access energy efficiency for low-power embedded systems
Compressing MIPS code by multiple operand dependencies
Improving SIMD Parallelism via Dynamic Binary Translation
Excluding Parallel Execution to Improve Global Fixed Priority Response Time Analysis
Modeling towards incremental early analyzability of networked avionics systems using virtual integration
On The Design and Application of Thermal Isolation Servers
Reachability Analysis of Sigmoidal Neural Networks
EMS-i: An Efficient Memory System Design with Specialized Caching Mechanism for Recommendation Inference
Computation of Minimal Siphons in Petri Nets by Using Binary Decision Diagrams
Compositional Learning and Verification of Neural Network Controllers
Optimal Priority Assignment to Control Tasks
Read Refresh Scheduling and Data Reallocation against Read Disturb in SSDs
Hardware Acceleration for Embedded Keyword Spotting: Tutorial and Survey
PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems
Mobile or FPGA? A Comprehensive Evaluation on Energy Efficiency and a Unified Optimization Framework
Formal Verification of Downtimeless System Evolution in Embedded Automation Controllers
TinyNS: Platform-aware Neurosymbolic Auto Tiny Machine Learning
Introduction to the special section on rigorous embedded systems design
Neural Abstraction-Based Controller Synthesis and Deployment
A polynomial algorithm for partitioning problems
R 3 : Reliable Over-the-Air Reprogramming on Computational RFIDs
Energy Modeling for the Bluetooth Low Energy Protocol
MORPHEUS: A heterogeneous dynamically reconfigurable platform for designing highly complex embedded systems
Let Coarse-Grained Resources Be Shared: Mapping Entire Neural Networks on FPGAs
Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis
A Model Checking Based Approach to Bounding Worst-Case Execution Time for Multicore Processors
Editorial: Special Section on CAPA'09
Randomized Instruction Injection to Counter Power Analysis Attacks
Heuristic search for adaptive, defect-tolerant multiprocessor arrays
Storage Optimization through Offset Assignment with Variable Coalescing
A real-time Java virtual machine with applications in avionics
More Is Less: Model Augmentation for Intermittent Deep Inference
Evaluating the Design of a VLIW Processor for Real-Time Systems
PRINT-SAFE: Printed Ultra-Low-Cost Electronic X-Design with Scalable Adaptive Fault Endurance
Thermal-aware Real-time Scheduling Using Timed Continuous Petri Nets
Multi-criteria Optimization of Real-time DAGs on Heterogeneous Platforms under P-EDF
SG-Float: Achieving Memory Access and Computing Power Reduction Using Self-Gating Float in CNNs
Verifying average dwell time of hybrid systems
XOR-Based Low-Cost Reconfigurable PUFs for IoT Security
Network-level Design Space Exploration of Resource-constrained Networks-of-Systems
ASTROLABE : A Rigorous Approach for System-Level Performance Modeling and Analysis
Exploring demand flexibility in heterogeneous aggregators: An LMP-based pricing scheme
Energy Conservation for Image Retrieval on Mobile Systems
How Flexible is Your Computing System?
A Highly Hardware Efficient ML-KEM Accelerator with Optimised Architectural Layers
Synchronized Shared Memory and Black-box Procedural Abstraction: Toward a Formal Semantics of Blech
Minimizing Test Suites with Unfoldings of Multithreaded Programs
BBB-CFI: Lightweight CFI Approach Against Code-Reuse Attacks Using Basic Block Information
Adaptive Task Allocation and Scheduling on NoC-based Multicore Platforms with Multitasking Processors
DNN Is Not All You Need: Parallelizing Non-neural ML Algorithms on Ultra-low-power IoT Processors
The Future of Real-Time Security: Latency-Optimized Lattice-Based Digital Signatures
Design Space Exploration for Secure IoT Devices and Cyber-Physical Systems
FT-DAG: An Efficient Full-Topology DAG Generator with Controllable Parameters
HiCH: Hierarchical Fog-Assisted Computing Architecture for Healthcare IoT
Real-time garbage collection for flash-memory storage systems of real-time embedded systems
FPGA placement using space-filling curves: Theory meets practice
Algorithm/Architecture Co-optimisation Technique for Automatic Data Reduction of Wireless Read-Out in High-Density Electrode Arrays
On the exploitation of loop-level parallelism in embedded applications
Verifying the Safety of Autonomous Systems with Neural Network Controllers
Golden Chip-Free Trojan Detection Leveraging Trojan Trigger's Side-Channel Fingerprinting
User-Centric Scheduling and Governing on Mobile Devices with big.LITTLE Processors
You Only Traverse Twice: A YOTT Placement, Routing, and Timing Approach for CGRAs
MC-ADAPT: Adaptive Task Dropping in Mixed-Criticality Scheduling
Real-Time Simulation Support for Runtime Verification of Cyber-Physical Systems
Learning to Train CNNs on Faulty ReRAM-based Manycore Accelerators
Providing Accountability in Heterogeneous Systems-on-Chip
Computationally Efficient DNN Mapping Search Heuristic using Deep Reinforcement Learning
Pruning-based, energy-optimal, deterministic I/O device scheduling for hard real-time systems
ForSyDe-Atom: Taming Complexity in Cyber Physical System Design with Layers
Transmission Adaptation for Battery-Free Relaying
A goal-oriented programming framework for grid sensor networks with reconfigurable embedded nodes
Using Criticality of GPU Accesses in Memory Management for CPU-GPU Heterogeneous Multi-Core Processors
Parallel Sparse Subspace Clustering via Joint Sample and Parameter Blockwise Partition
Stubborn Sets for Time Petri Nets
Robustness analysis for battery-supported cyber-physical systems
Software Hint-Driven Data Management for Hybrid Memory in Mobile Systems
L 2 C: Combining Lossy and Lossless Compression on Memory and I/O
A log buffer-based flash translation layer using fully-associative sector translation
FLIP2M: Flexible Intra-layer Parallelism and Inter-layer Pipelining for Multi-model AR/VR Workloads
An Investigation on Hardware-Aware Vision Transformer Scaling
A High-Speed Accelerator for Homomorphic Encryption using the Karatsuba Algorithm
Tiny instruction caches for low power embedded systems
Techniques for maintaining connectivity in wireless ad-hoc networks under energy constraints
A fast scalable automaton-matching accelerator for embedded content processors
Reconfigurable vertical profiling framework for the android runtime system
High-performance and low-energy buffer mapping method for multiprocessor DSP systems
Automatic Synthesis of Switching Controllers for Linear Hybrid Systems: Reachability Control
A multifrequency MAC specially designed for wireless sensor network applications
Embedding formal performance analysis into the design cycle of MPSoCs for real-time streaming applications
MTSS: Multitask stack sharing for embedded systems
Automatic compilation to a coarse-grained reconfigurable system-opn-chip
Formal specification and analysis of zeroconf using uppaalS
Test Generation for Hardware Trojan Detection Using Correlation Analysis and Genetic Algorithm
Online Learning for Orchestration of Inference in Multi-user End-edge-cloud Networks
Introduction to the special section on LCTES'11
Power management for energy-aware communication systems
NoC-based fault-tolerant cache design in chip multiprocessors
Power Side-channel Attack Resistant Circuit Designs of ARX Ciphers Using High-level Synthesis
HeterogeneousRTOS: A CPU-FPGA Real-Time OS for Fault Tolerance on COTS at Near-Zero Timing Cost
Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange and Encapsulation Protocols
Selective Subarray Isolation for Mitigating RowHammer Attack
Prepare: Power-Aware Approximate Real-time Task Scheduling for Energy-Adaptive QoS Maximization
Cooperative Coevolution-based Design Space Exploration for Multi-mode Dataflow Mapping