yusuke1997/dblp-id-title huggingface dataset:
Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures
Optimization Scheme to Minimize Reference Resistance Distribution of Spin-Transfer-Torque MRAM
Pico-Programmable Neurons to Reduce Computations for Deep Neural Network Accelerators
Parallel Interleavers Through Optimized Memory Address Remapping
Gate-Level Redundancy: A New Design-for-Reliability Paradigm for Nanotechnologies
Systematic Design of Loop Circuit Topologies Using C/I DS Methodology
Flexible ECC Management for Low-Cost Transient Error Protection of Last-Level Caches
Enabling a New Methodology of Neural Coding: Multiplexing Temporal Encoding in Neuromorphic Computing
10-315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation
VLSI considerations for TESH: a new hierarchical interconnection network for 3-D integration
AppAdapt: Opportunistic Application Adaptation in Presence of Hardware Variation
Portable, Flexible, and Scalable Soft Vector Processors
Scenario-oriented design for single-chip heterogeneous multiprocessors
Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM
HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer
Low-Complexity Multiplier for GF(2 m ) Based on All-One Polynomials
A Novel Nondestructive Read/Write Circuit for Memristor-Based Memory Arrays
Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations
COPIC: A Codesigned Accelerator for Efficient Octree-Based Learned Point Cloud Compression at Edge
A High-Performance SIKE Hardware Accelerator
Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication
Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation
High-speed CMOS switch designs for free-space optoelectronic MIN's
A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs
Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads
Optimization of Gate Voltage in Capacitive DC-DC Converters for Thermoelectric Energy Harvesting
Energy optimization of pipelined digital systems using circuit sizing and supply scaling
Self-Consistency and Consistency-Based Detection and Diagnosis of Malicious Circuitry
Hardware-Algorithm Codesigned Low-Latency and Resource-Efficient OMP Accelerator for DOA Estimation on FPGA
An Effective Combination of Power Scaling for H.264/AVC Compression
Block-oriented programmable design with switching network interconnect
Efficient On-Chip Crosstalk Avoidance CODEC Design
Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes for Spin Hall Effect MRAM Device
Sub 0.1-pJ/bit 14-Gb/s Receiver With Stack-Reduced Slicer Embedding One-Tap DFE for Low-Power Memory Interfaces
MTJ/CMOS-Based CLB Design for Low-Power and CPA-Resistant Secure Nonvolatile FPGA
Design of a Scalable and Programmable Sound Synthesizer
Flexible Low Complexity Uniform and Nonuniform Digital Filter Banks With High Frequency Resolution for Multistandard Radios
CEVGMM: Computationally Efficient Versatile Generic Memristor Model
Proof-Carrying Approximate Circuits
A 28 nm 16-kb Sign-Extension-Less Digital-Compute-in-Memory Macro With Extension-Friendly Compute Units and Accuracy-Adjustable Adder-Tree
VLSI Extreme Learning Machine: A Design Space Exploration
Resistive Threshold Logic
On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures
Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC Designs
A 3-5 GHz Current-Reuse g m -Boosted CG LNA for Ultrawideband in 130 nm CMOS
Constrained Asynchronous Ring Structures for Robust Digital Oscillators
Enabling Efficient Hybrid Systolic Computation in Shared-L1-Memory Manycore Clusters
Highly efficient, limited range multipliers for LUT-based FPGA architectures
MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits
Architecture and Design Flow for a Highly Efficient Structured ASIC
A Behavior Model of an On-Chip High Voltage Generator for Fast, System-Level Simulation
A 35-GHz TX and RX Front End With High TX Output Power for Ka-Band FMCW Phased-Array Radar Transceivers in CMOS Technology
Parallel Doubly Fed Symbol Timing Recovery Algorithm and FPGA Implementation for Burst Broadband Satellite Access
Design and Investigation of 7T2M-NVSRAM With Enhanced Stability and Temperature Impact on Store/Restore Energy
IEEE Standard 1500 Compatible Delay Test Framework
DASM: Data-Streaming-Based Computing in Nonvolatile Memory Architecture for Embedded System
A VLSI architecture for visible watermarking in a secure still digital camera (S 2 /DC) design (Corrected)*
A statistical study of defect maps of large area VLSI IC's
FSNoC: A Flit-Level Speedup Scheme for Network on-Chips Using Self-Reconfigurable Bidirectional Channels
A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit
A Compact Transregional Model for Digital CMOS Circuits Operating Near Threshold
Synchronization overhead in SOC compressed test
Novel Architecture for Lifting Discrete Wavelet Packet Transform With Arbitrary Tree Structure
On Efficient Implementation of Accumulation in Finite Field Over GF(2 m ) and its Applications
Efficient arithmetic using self-timing
NaPer: A TSV Noise-Aware Placer
A Predictably Low-Leakage ASIC Design Style
Editorial Appointments for the 2009-2010 Term
Leakage power analysis and reduction during behavioral synthesis
Proteus: A Pipelined NTT Architecture Generator
Toggle SOT-MRAM Architecture With Self-Terminating Write Operation
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation
A 0.3-V 8.5-μ a Bulk-Driven OTA
GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis
Scheduling battery usage in mobile systems
IEEE Standard 1500 Compliance Verification for Embedded Cores
A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI
Fast RC Reduction of Flip-Chip Power Grids Using Geometric Templates
Design and Analysis of Collective Pulse Oscillators
Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits
A Multilayer Approach to Designing Energy-Efficient and Reliable ReRAM Cross-Point Array System
Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link
A 4.447 mW at 100 MHz and 49.62% Uniqueness XNOR-XOR RO PUF ASIC Using 180-nm CMOS Process for IoT Security Applications
An Efficient High-Throughput Structured-Light Depth Engine
Low-Latency Successive-Cancellation List Decoders for Polar Codes With Multibit Decision
A 370-nW Bio-AFE With 2.9-μ Vrms Input Noise in an Octa-Channel System-in-Package for Multimode Bio-Signal Acquisition
Low-swing on-chip signaling techniques: effectiveness and robustness
A 10-bit Two-Stage R-DAC With Isolating Source Followers for TFT-LCD and AMOLED Column-Driver ICs
All-Digital Bandwidth Mismatch Calibration of TI-ADCs Based on Optimally Induced Minimization
A Systematic Design Methodology of Asynchronous SAR ADCs
An energy-aware active smart card
Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design
Voltage Setup Problem for Embedded Systems With Multiple Voltages
Extracting a Close-to-Minimum Multicycle Functional Broadside Test Set From a Functional Test Sequence
PWL-Based Architecture for the Logarithmic Computation of Floating-Point Numbers
Guest Editorial Special Section on the International Symposium on Circuits and Systems - ISCAS 2025
A 23-36.8-GHz Low-Noise Frequency Synthesizer With a Fundamental Colpitts VCO Array in SiGe BiCMOS for 5G Applications
Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations
A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register
HPR-Mul: An Area and Energy-Efficient High-Precision Redundancy Multiplier by Approximate Computing
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications
Retry-Based Synchronization for Online Testing of Identical Logic Blocks
A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors
Analysis and Design of Wideband GaAs Digital Step Attenuators
An Accumulator-Based Compaction Scheme For Online BIST of RAMs
Broadside and Functional Broadside Tests for Partial-Scan Circuits
Design Methodology for Voltage-Scaled Clock Distribution Networks
A 0.25-V 28-nW 58-dB Dynamic Range Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process
Low-Latency PAPR Reduction Architecture for Discrete Multitone Based on Approximate Midrange
Reliability of majority voting based VLSI fault-tolerant circuits
A review of 0.18-μm full adder performances for tree structured arithmetic circuits
Domain-Alternated Optimization for Passive Macromodeling
Variable-Pipeline-Stage Router
An on-chip march pattern generator for testing embedded memory cores
Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint
Novel HW Architecture Based on FPGAs Oriented to Solve the Eigen Problem
On the effectiveness of residue code checking for parallel two's complement multipliers
Posit Process Element for Using in Energy-Efficient DNN Accelerators
Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform
A Low-Power Ternary Content Addressable Memory With Pai-Sigma Matchlines
RF Specification Test Compaction Using Learning Machines
Framework for Multiple-Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization
Novel Wire Planning Schemes for Pin Minimization in Digital Microfluidic Biochips
Via-Minimization-Oriented Region Routing Under Length-Matching Constraints in Rapid Single-Flux-Quantum Circuits
A Hysteretic Switched-Capacitor DC-DC Converter With Optimal Output Ripple and Fast Transient Response
LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors
One-Sided Static Noise Margin and Gaussian-Tail-Fitting Method for SRAM
Design and Characterization of SEU Hardened Circuits for SRAM-Based FPGA
Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure
Cosimulation-based power estimation for system-on-chip design
TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages
Optimization of scannable latches for low energy
Ternary CAM Power and Delay Model: Extensions and Uses
New Approach to VLSI Buffer Modeling, Considering Overshooting Effect
Aging-Aware Instruction-Level Statistical Dynamic Timing Analysis for Embedded Processors
Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism
A Sub-1-V 100-mA OCL-LDO Regulator With Process-Temperature-Aware Design for Transient Sustainability
Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path
Enhancing Electromagnetic Analysis Using Magnitude Squared Incoherence
Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters
A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree
A built-in self-test method for diagnosis of synchronous sequential circuits
A Restore-Free Mode for MLC STT-RAM Caches
Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic
Efficient reconfigurable techniques for VLSI arrays with 6-port switches
Design and Implementation of Backtracking Wave-Pipeline Switch to Support Guaranteed Throughput in Network-on-Chip
A dynamic approach to controlling high-level synthesis CAD tools
A New Efficiency-Improvement Low-Ripple Charge-Pump Boost Converter Using Adaptive Slope Generator With Hysteresis Voltage Comparison Techniques
Cascode Cross-Coupled Stage High-Speed Dynamic Comparator in 65 nm CMOS
Electrical interconnects revitalized
Physical-Defect Modeling and Optimization for Fault-Insertion Test
Power Gating Aware Task Scheduling in MPSoC
CAD for nanometer silicon design challenges and success
A Robust Computing-in-Memory Macro With 2T1R1C Cells and Reused Capacitors for Successive-Approximation ADC
A Novel Parallel Feed-Forward Current Ripple Rejection (PFFCRR) Technique for High Load Current High PSRR nMOS LDOs
Power Yield Analysis Under Process and Temperature Variations
An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference
New Analytic Model of Coupling and Substrate Capacitance in Nanometer Technologies
LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology
VLSI systolic binary tree-searched vector quantizer for image compression
Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V
Techniques for energy-efficient communication pipeline design
An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses
Statistical timing analysis of combinational logic circuits
Efficient Homomorphic Convolution Designs on FPGA for Secure Inference
Analyzing the Inherent Reliability of Moderately Sized Magnetic and Electrostatic QCA Circuits Via Probabilistic Transfer Matrices
Research on Hardware Acceleration of Traffic Sign Recognition Based on Spiking Neural Network and FPGA Platform
Droplet Transportation in MEDA-Based Biochips: An Enhanced Technique for Intelligent Cross-Contamination Avoidance
Data-Dependent Operation Speed-Up Through Automatically Inserted Signal Transition Detectors for Ultralow Voltage Logic Circuits
Multiple Dice Working as One: CAD Flows and Routing Architectures for Silicon Interposer FPGAs
IMCA: An Efficient In-Memory Convolution Accelerator
Reducing SRAM Power Using Fine-Grained Wordline Pulsewidth Control
Automated Design of Reconfigurable Microarchitectures for Accelerators Under Wide-Voltage Scaling
A 32-GHz Nested-PLL-Based FMCW Modulator With 2.16-GHz Bandwidth in a 65-nm CMOS Process
CORDIC Designs for Fixed Angle of Rotation
Backward Interpolation Architecture for Algebraic Soft-Decision Reed-Solomon Decoding
A Fully Pipelined FPGA Architecture for Multiscale BRISK Descriptors With a Novel Hardware-Aware Sampling Pattern
A Timing-Aware Probabilistic Model for Single-Event-Upset Analysis
Beware the Dynamic C-Element
ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture
TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM
IRCA-TRNG: A Lightweight Dual-Ring Chaotic TRNG With Perturbation Refresh for High Throughput
Toward achieving energy efficiency in presence of deep submicron noise
Low-Cost Self-Test Techniques for Small RAMs in SOCs Using Enhanced IEEE 1500 Test Wrappers
Efficient Backside Power Delivery for High-Performance Computing Systems
A Fully Pipelined Architecture for the LOCO-I Compression Algorithm
Low-Cost Sorting Network Circuits Using Unary Processing
Fast fault translation
An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies
Sensitization Input Vector Impact on Propagation Delay for Nanometer CMOS ICs: Analysis and Solutions
Power estimation methods for analog circuits for architectural exploration of integrated systems
Vital-Sign Processing Receiver With Clutter Elimination Using Servo Feedback Loop for UWB Pulse Radar System
Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime
High-speed VLSI architectures for the AES algorithm
Racetrack Memory-Based Nonvolatile Storage Elements for Multicontext FPGAs
DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy
Layout techniques for FPGA switch blocks
Time-Encoded Values for Highly Efficient Stochastic Circuits
O 2 ABA: a novel high-performance predictable circuit architecture for the deep submicron era
A Transient-Enhanced Output-Capacitor-Free Low-Dropout Regulator With Dynamic Miller Compensation
On Noise Stability and Robustness of Adversarially Trained Networks on NVM Crossbars
Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors
Accurate computation of field reject ratio based on fault latency
Design of a CMOS System-on-Chip for Passive, Near-Field Ultrasonic Energy Harvesting and Back-Telemetry
An Energy-Efficient Neuromorphic Self-Attention Core Exploiting Dual Sparsity in Neurons and Spikes
Modeling Size Limitations of Resistive Crossbar Array With Cell Selectors
Design-Time Reliability Enhancement Using Hotspot Identification for RF Circuits
Practical Routability-Driven Design Flow for Multilayer Power Networks Using Aluminum-Pad Layer
Characterization of a Novel Nine-Transistor SRAM Cell
Efficient ORBGRAND Implementation With Parallel Noise Sequence Generation
A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator
Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs
Keelhaul: Processor-Driven Chip Connectivity and Memory Map Metadata Validator for Large Systems-on-Chip
A Timing-Dependent Power Estimation Framework Considering Coupling
Enabling Write-Reduction Multiversion Scheme With Efficient Dual-Range Query Over NVRAM
A temperature-insensitive self-recharging circuitry used in DRAMs
Modeling the Interdependences Between Voltage Fluctuation and BTI Aging
COAC: Cross-Layer Optimization of Accelerator Configurability for Efficient CNN Processing
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation
Smart Reliable Network-on-Chip
Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications
Efficient Implementation of Reconfigurable Warped Digital Filters With Variable Low-Pass, High-Pass, Bandpass, and Bandstop Responses
Period Jitter of Frequency-Locked Loops
Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis
Reversible Circuits: IC/IP Piracy Attacks and Countermeasures
Data Handling Limits of On-Chip Interconnects
Modeling a Set of Functional Test Sequences as a Single Sequence for Test Compaction
A 68-GHz Loss Compensated Distributed Amplifier Using Frequency Interleaved Technique in 65-nm CMOS Technology
Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs
Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials
Basic-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois Fields
Networked Power-Gated MRAMs for Memory-Based Computing
An Energy-Efficient Programmable Manycore Accelerator for Personalized Biomedical Applications
Buffer Controller-Based Multiple Processing Element Utilization for Dataflow Synthesis
Self-Shut-Off Pulsed Latches for Minimizing Sequencing Overhead
Low-Cost Pseudoasynchronous Circuit Design Style With Reduced Exploitable Side Information
Multiwire Phase Encoding: A Signaling Strategy for High-Bandwidth, Low-Power Data Movement
Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches
A Cooperative Management Scheme for Power Efficient Implementations of Real-Time Operating Systems on Soft Processors
Thresholding Decision-Directed Descent (T3D): A Tuning Solution for DDR5 DRAM DFEs
Reducing Cost of Yield Enhancement in 3-D Stacked Memories Via Asymmetric Layer Repair Capability
Active Mode Subclock Power Gating
Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS
Low-Power Programmable FPGA Routing Circuitry
CR-DRAM: Improving DRAM Refresh Energy Efficiency With Inter-Subarray Charge Recycling
Implementation of a CMOS LNA plus mixer for GPS applications with no external components
Highly regular, modular, and cascadable design of cellular automata-based pattern classifier
A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors
Cut-based functional debugging for programmable systems-on-chip
Analyzing the Vulnerabilities of External SDRAM on System-on-Chip Field Programmable Gate Array Devices
An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power
Statistical analysis of timing rules for high-speed synchronous VLSI systems
MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction
Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review
Emulation-Based Analysis of System-on-Chip Performance Under Variations
A Noise-Power-Area Optimized Biosensing Front End for Wireless Body Sensor Nodes and Medical Implantable Devices
On the Design of RNS Reverse Converters for the Four-Moduli Set ${\bf\{2^{\mmb n}+1, 2^{\mmb n}-1, 2^{\mmb n}, 2^{{\mmb n}+1}+1\}}$
Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures
An Efficient FPGA Implementation of Approximate Nearest Neighbor Search
A VLSI architecture for watermarking in a secure still digital camera (S 2 DC) design
Modeling technology impact on cluster microprocessor performance
A general framework for vertex orderings with applications to circuit clustering
Arithmetic-Based Binary-to-RNS Converter Modulo {2 n ±k} for jn-bit Dynamic Range
An Adaptive Equalizer With the Capacitance Multiplication for DisplayPort Main Link in 0.18-µm CMOS
A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM
Implementing Minimum-Energy-Point Systems With Adaptive Logic
Configurable VLSI Architecture for Deblocking Filter in H.264/AVC
Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline ADCs
Low-Power Correlation for IEEE 802.16 OFDM Synchronization on FPGA
HAVA: Heterogeneous Multicore ASIP for Multichannel Low-Bit-Rate Vocoder Applications
A Ripple Control Dual-Mode Single-Inductor Dual-Output Buck Converter With Fast Transient Response
ALADIN: a multilevel testability analyzer for VLSI system design
MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems
Compact On-Chip Half-Mode SIW-Based Dual-Band Bandpass Filter Using 3-D Stacked Inductors With Controllable Transmission Zero
Efficient Synchronization for Distributed Embedded Multiprocessors
A Universal Efficient Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders
Concurrent Error Detection in Reed-Solomon Encoders and Decoders
Design of multigigabit multiplexer-loop-based decision feedback equalizers
A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores
Efficient Memory-Addressing Algorithms for FFT Processor Design
A dictionary-based en/decoding scheme for low-power data buses
Detailed Characterization of Transceiver Parameters Through Loop-Back-Based BiST
Energy optimization of multilevel cache architectures for RISC and CISC processors
Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization
Dynamic Traffic Regulation in NoC-Based Systems
A low-power correlation-derivative CMOS VLSI circuit for bearing estimation
1.63 pJ/SOP Neuromorphic Processor With Integrated Partial Sum Routers for In-Network Computing
Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff
A System-Level Cosynthesis Framework for Power Delivery and On-Chip Data Networks in Application-Specific 3-D ICs
Clock-Skew Test Module for Exploring Reliable Clock-Distribution Under Process and Global Voltage-Temperature Variations
IPF: In-Place X-Filling Algorithm for the Reliability of Modern FPGAs
Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement
Performance Screening Using Functional Path Ring Oscillators