yusuke1997/dblp-id-title huggingface dataset:
Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits
Fully integrated CMOS fractional-N frequency divider for wide-band mobile applications with spurs reduction
An NMOS Digital LDO With NAND-Based Analog-Assisted Loop in 28-nm CMOS
A Configurable Transmitter Architecture for IEEE 802.11ac and 802.11ad Standards
A 300-nW Sensitive, 50-nA DC-DC Converter for Energy Harvesting Applications
Cancellation of Amplifier Offset and 1/f Noise: An Improved Chopper Stabilized Technique
A Robust 8-Bit Non-Volatile Computing-in-Memory Core for Low-Power Parallel MAC Operations
Lissajous Curve Methods for the Identification of Nonlinear Circuits: Calculation of a Physical Consistent Reactive Power
Far-Field RF-Powered Variable Duty Cycle Wireless Sensor Platform
An Analog On-Line Gain Calibration Loop for RF Amplifiers
Grid-Connected Photovoltaic Generation System
A family of zero-voltage and zero-current-switching (ZVZCS) three-level DC-DC converters with secondary-assisted regenerative passive snubber
A First-Order Tree-Structured DAC With Reduced Signal-Band Noise
Systematic Analysis of Interleaved Digital-to-Analog Converters
Low Hardware Complexity Pipelined Rank Filter
DCD-Based Recursive Adaptive Algorithms Robust Against Impulsive Noise
Dissipativity Enforcement via Perturbation of Para-Hermitian Pencils
A Flexible 18-Channel Multi-Hit Time-to-Digital Converter for Trigger-Based Data Acquisition Systems
Kernel Online Learning Algorithm With Scale Adaptation
Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes
An Analysis of a Near-End Crosstalk Cancelation System That Uses Adaptive Filters
Bernoulli Low-Pass Filters
Stability of Coupled Local Minimizers Within the Lagrange Programming Network Framework
A Network-Efficient Nonbinary QC-LDPC Decoder Architecture
Improving Load Range of Dual-Band Impedance Matching Networks Using Load-Healing Concept
A 90 nm-CMOS IR-UWB BPSK Transmitter With Spectrum Tunability to Improve Peaceful UWB-Narrowband Coexistence
A 1-to-1-kHz, 4.2-to-544-nW, Multi-Level Comparator Based Level-Crossing ADC for IoT Applications
Passive SC ΔΣ Modulator Based on Pipelined Charge-Sharing Rotation in 28-nm CMOS
Real-Time Embedded Machine Learning for Tensorial Tactile Data Processing
Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages
A Parallel Stochastic Number Generator With Bit Permutation Networks
Presilicon Circuit-Aware Linear Least Squares Spectral Analysis for Time-Based Data Converters
Control for stability and positivity: equivalent conditions and computation
A mesochronous pipelining scheme for high-performance digital systems
Two-Channel Parallelogram QMF Banks Using 2-D NSHP Digital All-Pass Filters
A 60 V Tolerance Transceiver With ESD Protection for FlexRay-Based Communication Systems
An Open-Loop Double-Carrier Simultaneous Wireless Power and Data Transfer System
Optical Receiver Using Noise Cancelling With an Integrated Photodiode in 40 nm CMOS Technology
Generation of a Family of Very High DC Gain Power Electronics Circuits Based on Switched-Capacitor-Inductor Cells Starting from a Simple Graph
A Low-Power Edge Detection Image Sensor Based on Parallel Digital Pulse Computation
Stochastic stability analysis of fuzzy hopfield neural networks with time-varying delays
Computation-Performance Optimization of Convolutional Neural Networks With Redundant Filter Removal
On the Global Convergence of a Class of Homotopy Methods for Nonlinear Circuits and Systems
Capacitive Energy Conversion With Circuits Implementing a Rectangular Charge-Voltage Cycle - Part 1: Analysis of the Electrical Domain
Modified Hysteretic Current Control (MHCC) for Improving Transient Response of Boost Converter
Widely Programmable High-Frequency Active RC Filters in CMOS Technology
Minimization of L 2 -sensitivity for state-space digital filters subject to L 2 -dynamic-range scaling constraints
A Random Linear Network Coding Accelerator in a 2.4GHz Transmitter for IoT Applications
Statistical Analysis of First-Order Bang-Bang Phase-Locked Loops Using Sign-Dependent Random-Walk Theory
Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications
A Class of Wide-Band Linear-Phase FIR Differentiators Using a Two-Rate Approach and the Frequency-Response Masking Technique
Hexagonal TSV Bundle Topology for 3-D ICs
Self-calibration of input-match in RF front-end circuitry
Effective Resistance of Two-Dimensional Truncated Infinite Mesh Structures
Event-Triggered Control of a Class of Nonlinear Systems on the Basis of Indefinite Lyapunov Theory
Self-Optimizing Wireless Networks on Structures
Self-Sampled All-MOS ASK Demodulator for Lower ISM Band Applications
Projective Synchronization of Driving-Response Systems and Its Application to Secure Communication
Quality Factor Analysis for Cross-Coupled LC Oscillators Using a Time-Varying Root Locus
Systematic Design of Supply Regulated LC -Tank Voltage-Controlled Oscillators
Braid Shielding Effectiveness Kron's Model via Coupled Cables Configuration
An Efficient Heterogeneous Memristive xnor for In-Memory Computing
A 16 Channel High-Voltage Driver with 14 Bit Resolution for Driving Piezoelectric Actuators
Phase Shifter-Relaxed and Control-Relaxed Continuous Steering Multiple Beamforming 4 × 4 Butler Matrix Phased Array
A Power-Saving Adaptive Equalizer With a Digital-Controlled Self-Slope Detection
Numerical method for determining the quantization error PDF of single-bit ΣΔ Modulators
Memristor Circuits: Bifurcations without Parameters
Time-Selective Sampling Receiver for Interference Rejection
A 100 MHz, 0.8-to-1.1 V, 170 mA Digital LDO With 8-Cycles Mean Settling Time and 9-Bit Regulating Resolution in 180-nm CMOS
Adaptive Semiblind Calibration of Bandwidth Mismatch for Two-Channel Time-Interleaved ADCs
Stability of Power Control in Multiple Coexisting Wireless Networks: ℒ 2 Small-Gain Perspective
A 0.55-V, 28-ppm/°C, 83-nW CMOS Sub-BGR With UltraLow Power Curvature Compensation
A Third-Order MASH $\Sigma \Delta $ Modulator Using Passive Integrators
Analysis of Wandering Spur Patterns in a Fractional-N Frequency Synthesizer With a MASH-Based Divider Controller
A 1-V-Input Switched-Capacitor Voltage Converter With Voltage-Reference-Free Pulse-Density Modulation
On the SFDR Upperbound in DDFS Utilizing Polynomial Interpolation Methods
Protocol and Fault Detection Design for Nonlinear Networked Control Systems
High-order electromechanical ΣΔ modulation in micromachined inertial sensors
VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture
Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency
Lightweight TRNG Based on Multiphase Timing of Bistables
A Soft-Charging-Based SC DC-DC Boost Converter With Conversion-Ratio-Insensitive High Efficiency for Energy Harvesting in Miniature Sensor Systems
A Digitally Interfaced Analog Correlation Filter System for Object Tracking Applications
Optimal Filtering for Systems With Multiple Packet Dropouts
Photovoltaic Energy Harvester With Fractional Open-Circuit Voltage Based Maximum Power Point Tracking Circuit
Exposure-Programmable CMOS Pixel With Selective Charge Storage and Code Memory for Computational Imaging
Reflectionless Filter Topologies Supporting Arbitrary Low-Pass Ladder Prototypes
Periodic Input Response of a Second-Order Digital Filter With Two's Complement Arithmetic
Design and Implementation of Grid Multiwing Hyperchaotic Lorenz System Family via Switching Control and Constructing Super-Heteroclinic Loops
Designing Observer-Type Controller for Containment of Discrete-Time Linear MASs Over Signed Graph
A 0.9-V Programmable Second-Order Bandpass Switched-Capacitor Filter for IoT Applications
Self-Biased Differential Rectifier With Enhanced Dynamic Range for Wireless Powering
A Novel Four-Dimensional Hyperchaotic Four-Wing System With a Saddle-Focus Equilibrium
A 100-Channel 1-mW Implantable Neural Recording IC
Nonlinear dynamics of first- and second-order log-domain circuits
An Accurate, Low-Voltage, CMOS Switching Power Supply With Adaptive On-Time Pulse-Frequency Modulation (PFM) Control
Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures
A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks
Event-Based Pixel Sensitive to Changes of Color and Brightness
Stress Relaxed Multiple Output High-Voltage Level Shifter
Design of Power Efficient Posit Multiplier
A Current-Density Centric Logical Effort Delay and Power Model for High-Speed CML Gates
Extraction of causal time-domain network parameters from their band-limited frequency-domain counterparts using rational functions
A Fully Integrated 150-GHz Transceiver Front-End in 65-nm CMOS
A Framework for Investigating the Performance of Chaotic-Map Truly Random Number Generators
Design of Multistage Decimation Filters Using Cyclotomic Polynomials: Optimization and Design Issues
Time-Oriented Synthesis for a WTA Continuous-Time Neural Network Affected by Capacitive Cross-Coupling
A Time-Domain 147fs rms 2.5 -MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction
A single-phase active power filter with one-cycle control under unipolar operation
Improvements in Light-Load Efficiency and Operation Frequency for Low-Voltage Current-Mode Integrated Boost Converters
Optimized Waveform Relaxation Methods for Longitudinal Partitioning of Transmission Lines
DRAM Yield Analysis and Optimization by a Statistical Design Approach
An Improved Signed Digit Representation Approach for Constant Vector Multiplication
A 12.5-fJ/Conversion-Step 8-Bit 800-MS/s Two-Step SAR ADC
LSB Dithering in MASH Delta-Sigma D/A Converters
A Fast JPEG2000 Encoder That Preserves Coding Efficiency: The Split Arithmetic Encoder
A Signomial Programming Approach for Binary Image Restoration by Penalized Least Squares
Distributed LC Resonant Clock Grid Synthesis
Calculation of Total Integrated Noise in Analog Circuits
Design, Analysis, and Experimentation of Chaotic Permanent Magnet DC Motor Drives for Electric Compaction
Boundary Constrained Control of Flexible String Systems Subject to Disturbances
Hybrid Precoding Processor for Millimeter Wave MIMO Communications
A Low-Noise RC-Based Phase Interpolator in 16-nm CMOS
A 4-Bit, 1.6 GS/s Low Power Flash ADC, Based on Offset Calibration and Segmentation
Robust Regularization for Normalized LMS Algorithms
Efficient Offline Outer/Inner DAC Mismatch Calibration in Wideband ΔΣ ADCs
Averaged Small-Signal Model of PWM DC-DC Converters in CCM Including Switching Power Loss
A Gaussian Pulse Generator for Millimeter-Wave Applications
A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-μm CMOS technology
IP Observer Design for Descriptor Linear Systems
Current-Mirror-Based Potentiostats for Three-Electrode Amperometric Electrochemical Sensors
Variations in Nanometer CMOS Flip-Flops: Part II - Energy Variability and Impact of Other Sources of Variations
Multiphase LC oscillators
Physically Unclonable Function Using an Initial Waveform of Ring Oscillators
Blind Adaptive Equalization of MIMO Systems: New Recursive Algorithms and Convergence Analysis
A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS
Guaranteed H ∞ Performance State Estimation of Delayed Static Neural Networks
An Iterative Analytical Solution for Calculating Maximum Power Point in Photovoltaic Systems Under Partial Shading Conditions
A Gray-Level Dependent Pre-Emphasis Column Driver With Fast Settling for Active-Matrix LCD Applications
A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
Low-Cost Hardware-Sharing Architecture of Fast 1-D Inverse Transforms for H.264/AVC and AVS Applications
A High-IIP3 Third-Order Elliptic Filter With Current-Efficient Feedforward-Compensated Opamps
Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths
Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators
Efficient Design Centering of High-Frequency Integrated Continuous-Time Filters
A 54.2-dB Current Gain Dynamic Range, 1.78-GHz Gain-Bandwidth Product CMOS VCCA 2
Novel Bit-Reordering Circuit for Continuous-Flow Parallel FFT Architectures
A Subthreshold Symmetric SRAM Cell With High Read Stability
Nano-Intrinsic True Random Number Generation: A Device to Data Study
Inductively Coupled 180-nm CMOS Charger With Adjustable Energy-Investment Capability
Low-Power Level Shifter for Multi-Supply Voltage Designs
Convergence Analysis of Deficient-Length Frequency-Domain Adaptive Filters
Evaluation of Gunshot Detection Algorithms
A 40-GHz Bandwidth Tapered Distributed LNA
Mean-square performance of the filtered-reference/ filtered-error LMS algorithm
Reconfigurable Quantization of Oversampled Signals Under Discrete-Time Filtering
Robust Optical Time-of-Flight Range Imaging Based on Smart Pixel Structures
Cryptographically secure substitutions based on the approximation of mixing maps
A 400 Mb/s∼2.5 Gb/s Referenceless CDR IC Using Intrinsic Frequency Detection Capability of Half-Rate Linear Phase Detector
A Robust Adaptive Power Line Interference Canceler VLSI Architecture and ASIC for MultichannelBiopotential Recording Applications
Constant Mismatch Loss Boundary Circles and Their Application to Optimum State Distribution in Adaptive Matching Networks
Ultra-Low Voltage Push-Pull Converter for Micro Energy Harvesting
In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning
An Electronically Tunable Linear or Nonlinear MOS Resistor
A Spatial Contrast Retina With On-Chip Calibration for Neuromorphic Spike-Based AER Vision Systems
Ultra-Low-Power Interface Chip for Autonomous Capacitive Sensor Systems
Continuous Nonsingular Terminal Sliding Mode Control of DC-DC Boost Converters Subject to Time-Varying Disturbances
Finite horizon H ∞ fixed-lag smoothing for time-varying continuous systems
Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture
4-Phase Interleaved Boost Converter With IC Controller for Distributed Photovoltaic Systems
A Systematic Approach to Bi-Directionally Nonlinearly Coupled Systems Design for the Generation of Complex Dynamical Behaviours
SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds
An Area Efficient Thermal Energy Harvester With Reconfigurable Capacitor Charge Pump for IoT Applications
Fixed-Order Piecewise-Affine Output Feedback Controller for Fuzzy-Affine-Model-Based Nonlinear Systems With Time-Varying Delay
Alias Rejection of Continuous-Time DeltaSigma Modulators With Switched-Capacitor Feedback DACs
Design Methodology for Phase-Locked Loops Using Binary (Bang-Bang) Phase Detectors
Pacemaker-Based Global Synchronization of Kuramoto Oscillators via Distributed Control
A PVT-Tolerant Injection-Locked Clock Multiplier With a Frequency Calibrator Using a Delay Time Detector
Fault Detection for Markovian Jump Systems With Sensor Saturations and Randomly Varying Nonlinearities
Discontinuous Map Analysis of a DC-DC Converter Governed by Pulse Skipping Modulation
Modeling, Evaluation, and Comparison of CRZ and RSD Redundant Architectures for Two-Step A/D Converters
Guest Editorial Special Section on 2010 IEEE Custom Integrated Circuits Conference (CICC 2010)
Time-Domain Model for Injection Locking in Nonharmonic Oscillators
The L(2, 1)-labeling and operations of graphs
Strong Injection Locking and Pulling in $LC$ Multiphase Oscillators With Multiple Injection Signals
Zero-Shot Object Detection With Attributes-Based Category Similarity
Motion estimation processor using mixed-signal approach
Efficient Implementation of 2 ˟ Oversampled Exponentially Modulated Filter Banks
Pixel Optimizations and Digital Calibration Methods of a CMOS Image Sensor Targeting High Linearity
Estimation of Aliasing Effects Due to Periodical Nonuniform Individual Sampling in High- Q Switched-Capacitor Filters
Reconfigurable RO-Path Delay Sensor
A Fast and Compact Analog Buffer Design for Active Matrix Liquid Crystal Displays Using Polysilicon Thin-Film Transistors
An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs
Synthesis of Narrowband Linear-Phase FIR Filters With a Piecewise-Polynomial Impulse Response
Implementation and Performance of DSP-Oriented Feedforward Power Amplifier Linearizer
A Phase Tunable Rotary Traveling Wave Oscillator: Analysis and Calibration
A subspace theory for differential chaos-shift keying
Minimax Design of IIR Digital Filters Using Iterative SOCP
A 200-Mb/s Data Rate 3.1-4.8-GHz IR-UWB All-Digital Pulse Generator With DB-BPSK Modulation
Realization Using the Fornasini-Marchesini Model for Implementations in Distributed Grid Sensor Networks
A 2.5-Gb/s Receiver PDIC With Low-Noise Integrated Charge Pump
A Low Energy-Noise 65nm CMOS Switched-Capacitor Resistive-Bridge Sensor Interface
Near Threshold Voltage Word-Line Voltage Injection Self-Convergence Scheme for Local Electron Injected Asymmetric Pass Gate Transistor 6T-SRAM
10-Gb/s 0.13-µm CMOS Inductorless Modified-RGC Transimpedance Amplifier
Space-Time Trellis-Coded OFDM Systems in Frequency-Selective Mobile Fading Channels
Economic LSTM Approach for Recurrent Neural Networks
A Wide Measurement Range and Fast Update Rate Integrated Interface for Capacitive Sensors Array
Energy and Latency Optimization in NEM Relay-Based Digital Circuits
New Approach to Realize Fractional Power in z-Domain at Low Frequency
Using Linear Relations Between Experimental Characteristics in Stiff Identification Problems of Linear Circuit Theory
Affine Projection Subband Adaptive Filter With Low Computational Complexity
Generalized Analytical Equations for Injected Ring Oscillator With RC-Load
A 10 GS/s 6 b Time-Interleaved Partially Active Flash ADC
A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control
A Simple Piecewise Model of Reset/Set Transitions in Bipolar ReRAM Memristive Devices
Spiking and Bursting in Josephson Junction
Constant-Resistance CMOS Input Sampling Switch for GSM/WCDMA High Dynamic Range Delta Sigma Modulators
Power Loss and Switching Noise Reduction Techniques for Single-Inductor Multiple-Output Regulator
An Accurate Automatic Quality-Factor Tuning Scheme for Second-Order LC Filters
A Fault-Tolerant Cache System of Automotive Vision Processor Complying With ISO26262
Self-latching operation of MOBILE circuits using series-connection of RTDs and transistors
Frequency Limitations of First-Order g m - RC All-Pass Delay Circuits
A Self-Disabled Sensing Technique for Content-Addressable Memories
Rakeness in the Design of Analog-to-Information Conversion of Sparse and Localized Signals
Impacts of Crest Factor Reduction and Digital Predistortion on Linearity and Power Efficiency of Power Amplifiers
VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications
A Low-Cost Audio Computer for Information Dissemination Among Illiterate People Groups
Analytical synthesis of high-order single-ended-input OTA-grounded C all-pass and band-reject filter structures
Maximum Operating Frequency of Class-E Amplifier at Any Duty Ratio
Design Space-Time Trellis-Coded Intercarrier Interference Parallel Cancelation Architectures for OFDM Systems
A 0.6-V 10-bit 200-kS/s Fully Differential SAR ADC With Incremental Converting Algorithm for Energy Efficient Applications
Scalability Analysis of SIMO Non-Radiative Resonant Wireless Power Transfer Systems Based on Circuit Models
Fully-Parallel Stochastic Decoder for Rate Compatible Modulation
Alternative SDRE Scheme for Planar Systems
A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm
General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs
Tracking Analysis of Minimum Kernel Risk-Sensitive Loss Algorithm Under General Non-Gaussian Noise
A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes
A Nonlinear Transient Analysis of Regenerative Frequency Dividers
Robust H 2 /H infty Global Linearization Filter Design for Nonlinear Stochastic Systems
Hardware-Efficient Implementation of Half-Band IIR Filter for Interpolation and Decimation
A LOG-Induced SSN-Tolerant Transceiver for On-Chip Interconnects in COG-Packaged Source Driver IC for TFT-LCD
High-Throughput Parallel SRAM-Based Hash Join Architecture on FPGA
A 1-V CMOS Current Reference With Temperature and Process Compensation
Direct All-Digital Frequency Synthesis Techniques, Spurs Suppression, and Deterministic Jitter Correction
Investigation on the Optimization Criteria for the Design of Variable Fractional Delay Filters
Dynamics and Traveling Waves in CNN Vector Disease Model
A Modified Oja-Xu MCA Learning Algorithm and Its Convergence Analysis
A Novel and Efficient Design for an RSA Cryptosystem With a Very Large Key Size
Varactor-Tuned Microstrip Bandpass Filter With Loop Hairpin and Combline Resonators
Simultaneous peak and average power minimization during datapath scheduling
Analysis and Design of a New Current-Source Output Load Resonant Converter With High Capability in Line and Load Regulation
A New Mechanism Producing Discrete Spurious Components in Fractional- N Frequency Synthesizers
A 50-V Isolation, 100-MHz, 50-mW Single-Chip Junction Isolated DC-DC Converter With Self-Tuned Maximum Power Transfer Frequency
Design of a Sample-Rate Converter From CD to DAT Using Fractional Delay Allpass Filter
A Theoretical Framework for Quality Estimation and Optimization of DSP Applications Using Low-Power Approximate Adders
Design and Stability Analysis of a Low-Voltage Subharmonic Cascode FET Mixer
A Min-Max Optimization Framework for Designing SigmaDelta Learners: Theory and Hardware
A Binary-Weighted Switching and Reconfiguration-Based Programmable Gain Amplifier
Robust cerebellar model articulation controller design for unknown nonlinear systems
Power System Dynamic Security Region and Its Approximations
On Dealing With the Charge Trapped in Floating- Gate MOS (FGMOS) Transistors
Clock-Jitter-Tolerant Wideband Receivers: An Optimized Multichannel Filter-Bank Approach
A Two-Step Sensing Circuit for the Hysteresis Loop Selector-Based Resistive Non-Volatile Memory Arrays
88-µ A 1-MHz Stray-Insensitive CMOS Current-Mode Interface IC for Differential Capacitive Sensors
A Unified Approach to Practical Consensus with Quantized Data and Time Delay
Enhanced phase noise modeling of fractional-N frequency synthesizers
Energy-Based L 2 Disturbance Attenuation Excitation Control of Differential Algebraic Power Systems
Thermal Compensation Method for CMOS Digital Integrated Circuits Using Temperature-Adaptive DC-DC Converter
Robust Filter for Linear Stochastic Partial Differential Systems via a Set of Sensor Measurements
Model Reduction Using Parameterized Limited Frequency Interval Gramians for 1-D and 2-D Separable Denominator Discrete-Time Systems
RNS-to-Binary Converters for Two Four-Moduli Sets {2 n -1, 2 n , 2 n +1, 2 n+1 -1} and {2 n -1, 2 n , 2 n +1, 2 n+1 +1}
A SiGe BiCMOS Eight-Channel Multidithering Sub-Microsecond Adaptive Controller
A 12.5-ENOB 10-kS/s Redundant SAR ADC in 65-nm CMOS
Maximizing the Signal-to-Alias Ratio in Non-Uniform Filter Banks for Acoustic Echo Cancellation
Optimizing Consistency-Based Design of Context-Sensitive Gene Regulatory Networks
A Programmable 0.8-V 10-bit 60-MS/s 19.2-mW 0.13-mu m CMOS ADC Operating Down to 0.5 V
Guest Editorial Special Issue on Multifunctional Circuits and Systems for Future Generations of Wireless Communications - II
Compact model generation for on-chip transmission lines
Low-Power Architecture and Circuit Techniques for High-Boost Wide-Band G m -C Filters
Improving local minima of columnar competitive model for TSPs
Unitary Precoders for ST-OFDM Systems Using Alamouti STBC
New Systolic Algorithm and Array Architecture for Prime-Length Discrete Sine Transform
Power Optimization of an 11.75-Gb/s Combined Decision Feedback Equalizer and Clock Data Recovery Circuit in 0.18-μm CMOS
Design of an On-Silicon-Interposer Passive Equalizer for Next Generation High Bandwidth Memory With Data Rate Up To 8 Gb/s
The Sampling Theorem With Constant Amplitude Variable Width Pulses