yusuke1997/dblp-id-title huggingface dataset:
A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization
AGD: Analytic Gradient Descent for Discrete Optimization in EDA and its Use to Gate Sizing
Verification and coverage of message passing multicore applications
vGreen: A System for Energy-Efficient Management of Virtual Machines
Fault Tolerance Technique Offlining Faulty Blocks by Heap Memory Management
Eh?Legalizer: A High Performance Standard-Cell Legalizer Observing Technology Constraints
A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions
MPSoC memory optimization using program transformation
QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks
SystemJ compilation using the tandem virtual machine approach
Register estimation in unscheduled dataflow graphs
Enabling multimedia using resource-constrained video processing techniques: A node-centric perspective
Cost-effective lifetime and yield optimization for NoC-based MPSoCs
Harnessing Machine Learning in Dynamic Thermal Management in Embedded CPU-GPU Platforms
System-scenario-based design of dynamic embedded systems
An Approximation Algorithm for Threshold Voltage Optimization
Crosstalk minimization in logic synthesis for PLAs
Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs
Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm
Electronics Supply Chain Integrity Enabled by Blockchain
A Framework for Validation of Synthesized MicroElectrode Dot Array Actuations for Digital Microfluidic Biochips
Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2
Resource-aware architectures for adaptive particle filter based visual target tracking
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization
Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification
E2HRL: An Energy-efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning
ZeroD-fender: A Resource-aware IoT Malware Detection Engine via Fine-grained Side-channel Analysis
Exploring time/resource trade-offs by solving dual scheduling problems with the ant colony optimization
On the construction of zero-deficiency parallel prefix circuits with minimum depth
CeMux: Maximizing the Accuracy of Stochastic Mux Adders and an Application to Filter Design
Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug
Power minimization in IC design: principles and applications
Complementary Synthesis for Encoder with Flow Control Mechanism
Word-length selection for power minimization via nonlinear optimization
A Learning-based Methodology for Scenario-aware Mapping of Soft Real-time Applications onto Heterogeneous MPSoCs
An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems
HW-SW emulation framework for temperature-aware design in MPSoCs
Data-driven Anomaly Detection with Timing Features for Embedded Systems
Datapath scheduling with multiple supply voltages and level converters
Simulation and sensitivity of linear analog circuits under parameter variations by Robust interval analysis
Placement Flow Study and Detailed Placement for Hybrid-Row-Height Designs
LDE-aware Analog Layout Migration with OPC-inclusive Routing
A note on "a mapping algorithm for computer-assisted exploration in the design of embedded systems"
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA
Formal verification of code motion techniques using data-flow-driven equivalence checking
A Dynamic Huffman Coding Method for Reliable TLC NAND Flash Memory
Memory access optimization in compilation for coarse-grained reconfigurable architectures
A probabilistic analysis of coverage methods
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators
Selective shielding technique to eliminate crosstalk transitions
Ultrafast Generative AI by Ultradense 3D Integration: A Case Study on LLM-based Edge Inference
Segmented channel routability via satisfiability
Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation
Enable Deep Learning on Mobile Devices: Methods, Systems, and Applications
Understanding SRAM Stability via Bifurcation Analysis: Analytical Models and Scaling Trends
PREASC: Automatic Portion Resilience Evaluation for Approximating SystemC-based Designs Using Regression Analysis Techniques
Worst-case Power Integrity Prediction Using Convolutional Neural Network
A compiler approach to managing storage and memory bandwidth in configurable architectures
Compiler optimization on VLIW instruction scheduling for low power
Parallel circuit simulation with adaptively controlled projective integration
Integrated Latch Placement and Cloning for Timing Optimization
Rate analysis for embedded systems
Multilevel Simulation of Nonfunctional Properties by Piecewise Evaluation
EBL Overlapping Aware Stencil Planning for MCC System
A Chisel Framework for Flexible Design Space Exploration through a Functional Approach
Two-Stage Layout Decomposition for Hybrid E-Beam and Triple Patterning Lithography
Decomposition of instruction decoders for low-power designs
Hierarchical partitioning of VLSI floorplans by staircases
Reducing DRAM Refresh Rate Using Retention Time Aware Universal Hashing Redundancy Repair
Call for papers ACM transactions on design automation of electronic systems (TODAES) special section on low-power electronics and design
WCPNet: Jointly Predicting Wirelength, Congestion and Power for FPGA Using Multi-Task Learning
Load Balanced PIM-Based Graph Processing
Structured Dynamic Precision for Deep Neural Networks Quantization
Lightning: Leveraging DVFS-induced Transient Fault Injection to Attack Deep Learning Accelerator of GPUs
Lens aberration aware placement for timing yield
Enhancing the Effectiveness of STLs for GPUs via Bounded Model Checking
Conditional Diagnosability of Cayley Graphs Generated by Transposition Trees under the PMC Model
ASP-Based Encoding Model of Architecture Synthesis for Smart Cameras in Distributed Networks
Dynamic data folding with parameterizable FPGA configurations
Electric Vehicle Optimized Charge and Drive Management
Sequential Routing-based Time-division Multiplexing Optimization for Multi-FPGA Systems
ReChannel: Describing and simulating reconfigurable hardware in systemC
Fine-grained Adaptive Testing Based on Quality Prediction
Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference
Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs
Thermal-aware 3D Symmetrical Buffered Clock Tree Synthesis
Cyber-Physical Co-Simulation Framework for Smart Cells in Scalable Battery Packs
Test compaction for small-delay defects using an effective path selection scheme
Effective techniques for the generalized low-power binding problem
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
The Unison algorithm: fast evaluation of Boolean expressions
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains
Robust Multi-Target Sample Preparation on MEDA Biochips Obviating Waste Production
Self Adaptive Logical Split Cache Techniques for Delayed Aging of NVM LLC
Exploring Soft-Error Robust and Energy-Efficient Register File in GPGPUs using Resistive Memory
Learning-based Phase-aware Multi-core CPU Workload Forecasting
ZoneTrace: Zone Monitoring Tool for F2FS on ZNS SSDs
Training PPA Models for Embedded Memories on a Low-data Diet
Disjunctive image computation for software verification
Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation
Efficient scheduling of conditional behaviors for high-level synthesis
A Novel Range Matching Architecture for Packet Classification Without Rule Expansion
Adaptive Test for RF/Analog Circuit Using Higher Order Correlations among Measurements
Clock Tree synthesis for TSV-based 3D IC designs
A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction
Energy- and Performance-Efficient Communication Framework for Embedded MPSoCs through Application-Driven Release Consistency
SystemCoDesigner - an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications
Test sequence generation for controller verification and test with high coverage
FH-OAOS: A Fast Four-Step Heuristic for Obstacle-Avoiding Octilinear Steiner Tree Construction
Serialized parallel code generation framework for MPSoC
A fuel-cell-battery hybrid for portable embedded systems
Search space definition and exploration for nonuniform data reuse opportunities in data-dominant applications
ECDSA Passive Attacks, Leakage Sources, and Common Design Mistakes
Improving Test and Diagnosis Efficiency through Ensemble Reduction and Learning
TCONMAP: Technology Mapping for Parameterised FPGA Configurations
ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation
Revisiting Routability-Driven Placement for Analog and Mixed-Signal Circuits
Component Fault Diagnosability of Hierarchical Cubic Networks
Static Mapping of Applications on Heterogeneous Multi-Core Platforms Combining Logic-Based Benders Decomposition with Integer Linear Programming
Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering
Concurrency-aware compiler optimizations for hardware description languages
SmartCap: Using Machine Learning for Power Adaptation of Smartphone's Application Processor
MicroFix: Using timing interpolation and delay sensors for power reduction
A Robust Newton Iteration Method for Mixed-Cell-Height Circuit Legalization Under Technology and Region Constraints
Compacting sequences with invariant transition frequencies
Radio frequency identification prototyping
Energy-Efficient and Quality-Assured Approximate Computing Framework Using a Co-Training Method
Design Flow and Methodology for Dynamic and Static Energy-constrained Scheduling Framework in Heterogeneous Multicore Embedded Devices
STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience
Custom topology rotary clock router with tree subnetworks
BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device-Based Biochips
Coordinated parallelizing compiler optimizations and high-level synthesis
Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
Functional verification of task partitioning for multiprocessor embedded systems
Area-driven Boolean bi-decomposition by function approximation
An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions
CPSim: Simulation Toolbox for Security Problems in Cyber-Physical Systems
Breakpoints and breakpoint detection in source-level emulation
Initializability analysis of synchronous sequential circuits
Towards the formal verification of cache coherency at the architectural level
On test data volume reduction for multiple scan chain designs
Gravity: Fast placement for 3-D VLSI
Clock skew scheduling with race conditions considered
Eh?Placer: A High-Performance Modern Technology-Driven Placer
Enhanced Watermarking for Paper-Based Digital Microfluidic Biochips
An Algorithm for Jointly Optimizing Quantization and Multiple Constant Multiplication
Probabilistic system-on-a-chip architectures
An in-place search algorithm for the resource constrained scheduling problem during high-level synthesis
Automatic Optimization of the VLAN Partitioning in Automotive Communication Networks
A fast algorithm for minimizing FPGA combinational and sequential modules
Process Independent Design Methodology for the Active RC and Single-Inverter-Based Rail Clamp
Architecting the Last-Level Cache for GPUs using STT-RAM Technology
A Compact High-Dimensional Yield Analysis Method using Low-Rank Tensor Approximation
The edge-based design rule model revisited
Prolonging Lifetime of PCM-Based Main Memories through On-Demand Page Pairing
Equivalence checking between behavioral and RTL descriptions with virtual controllers and datapaths
Optimization and Quality Estimation of Circuit Design via Random Region Covering Method
A PPA Study of Reinforced Placement Parameter Autotuning: Pseudo-3D vs. True-3D Placers
Root-Cause Analysis with Semi-Supervised Co-Training for Integrated Systems
Routable and Matched Layout Styles for Analog Module Generation
Two-dimensional Search Space for Extracting Broadside Tests from Functional Test Sequences
Constraint analysis for code generation: basic techniques and applications in FACTS
Towards Floating Point-Based AI Acceleration: Hybrid PIM with Non-Uniform Data Format and Reduced Multiplications
A Cross-level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors
CNNFlow: Memory-driven Data Flow Optimization for Convolutional Neural Networks
Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation
Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization
Power-safe application of tdf patterns to flip-chip designs during wafer test
DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs
Uncertainty-aware Energy Harvest Prediction and Management for IoT Devices
Hybrid Power Management for Office Equipment
Two-layer bus routing for high-speed printed circuit boards
On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches
SynergyFlow: An Elastic Accelerator Architecture Supporting Batch Processing of Large-Scale Deep Neural Networks
RASCv2: Enabling Remote Access to Side-Channels for Mission Critical and IoT Systems
AmLuCEP: Amalgamating LUT-based Compression and Adaptive Encoding Assisted Block Placement To Improve Lifetime of PCM-based Main Memories
Editorial: ACM Transactions on Design Automation of Electronics Systems and Beyond
Target Faults for Test Compaction Based on Multicycle Tests
Automatic Stage-form Circuit Reduction for Multistage Opamp Design Equation Generation
Time-Multiplexed FPGA Overlay Architectures: A Survey
Time-Triggered Scheduling of Mixed-Criticality Systems
A High Efficient and Scalable Obstacle-Avoiding VLSI Global Routing Flow
Intrinsic response for analog module testing using an analog testability bus
Optimizing computations for effective block-processing
2011 ACM TODAES best paper award
HWREx: AI-enabled Hardware Weakness and Risk Exploration and Storytelling Framework with LLM-assisted Mitigation Suggestion
Automatic Test Pattern Generation for Robust Quantum Circuit Testing
Order statistics for correlated random variables and its application to at-speed testing
Low-Power Hypercube Divided Memory FFT Engine Using 3D Integration
Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques
Stairway compaction using corner block list and its applications with rectilinear blocks
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
GANDSE: Generative Adversarial Network-based Design Space Exploration for Neural Network Accelerator Design
Recovering from Biased Distribution of Faulty Cells in Memory by Reorganizing Replacement Regions through Universal Hashing
Design and implementation of an efficient wear-leveling algorithm for solid-state-disk microcontrollers
A Hierarchical Technique for Statistical Path Selection and Criticality Computation
An adaptive cryptographic engine for internet protocol security architectures
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
Behavioral synthesis techniques for intellectual property protection
MEMS-IC Robustness Optimization Considering Electrical and Mechanical Design and Process Parameters
Layout-Aware Mixture Preparation of Biochemical Fluids on Application-Specific Digital Microfluidic Biochips
Layout-aware scan chain reorder for launch-off-shift transition test coverage
Algorithm-Hardware Co-design for Accelerating Depthwise Separable CNNs
Interrupt modeling for efficient high-level scheduler design space exploration
Fast Area Optimization Approach for XNOR/OR-based Fixed Polarity Reed-Muller Logic Circuits based on Multi-strategy Wolf Pack Algorithm
HLS-IRT: Hardware Trojan Insertion through Modification of Intermediate Representation During High-Level Synthesis
The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems
Efficient optimal design space characterization methodologies
Benchmarking and evaluating reconfigurable architectures targeting the mobile domain
Gate-level test generation for sequential circuits
Training Fixed-Point Classifiers for On-Chip Low-Power Implementation
Multithreaded Simulation for Synchronous Dataflow Graphs
A New Dynamic Countermeasure to Strengthen Design Obfuscation in FPGAs
Trade-offs in loop transformations
CmpCNN: CMP Modeling with Transfer Learning CNN Architecture
Theories and algorithms on single-detour routing for untangling twisted bus
Toward a Human-Readable State Machine Extraction
Placement of Digital Microfluidic Biochips via a New Evolutionary Algorithm
Partitioning sequential programs for CAD using a three-step approach
A Locality Optimizer for Loop-dominated Applications Based on Reuse Distance Analysis
A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks
Scalable Bandwidth Shaping Scheme via Adaptively Managed Parallel Heaps in Manycore-Based Network Processors
Cost minimization while satisfying hard/soft timing constraints for heterogeneous embedded systems
Synthesis of time-constrained multitasking embedded software
The exact channel density and compound design for generic universal switch blocks
Enhanced Compiler Technology for Software-based Hardware Fault Detection
Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology
An Improved MCTS Algorithm for Ordered Escape Routing of Differential Pair
HoPE: Hot-Cacheline Prediction for Dynamic Early Decompression in Compressed LLCs
Floorplan representations: Complexity and connections
Optimizing FPGA Routing with Explainable Co-Learning of Congestion and Wirelength
Area reduction by deadspace utilization on interconnect optimized floorplan
Specification and verification of pipelining in the ARM2 RISC microprocessor
An Effective Floorplan-Guided Placement Algorithm for Large-Scale Mixed-Size Designs
Parallel High-Level Synthesis Design Space Exploration for Behavioral IPs of Exact Latencies
C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
Combinational logic synthesis for LUT based field programmable gate arrays
A parallel branch-and-cut approach for detailed placement
Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems
Recent developments in high-level synthesis
Computation of Seeds for LFSR -Based n -Detection Test Generation
Measurement and analysis of sequential design processes
Improving PCM Endurance with a Constant-Cost Wear Leveling Design
Nanometer MOSFET Effects on the Minimum-Energy Point of Sub-45nm Subthreshold Logic - Mitigation at Technology and Circuit Levels
2009 ACM TODAES best paper award: Optimization of polynomial datapaths using finite ring algebra
Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures
A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts
Testing high-performance pipelined circuits with slow-speed testers
Exploring Large Language Models for Hierarchical Hardware Circuit and Testbench Generation
TROP: TRust-aware OPportunistic Routing in NoC with Hardware Trojans
Optimizing VLIW Instruction Scheduling via a Two-Dimensional Constrained Dynamic Programming
Architecture and Compiler Support for GPUs Using Energy-Efficient Affine Register Files
A Reconfigurable 7T SRAM Bit Cell for High Speed, Power Saving and Low Voltage Application
Towards Smarter Diagnosis: A Learning-based Diagnostic Outcome Previewer
Cross-point Resistive Memory: Nonideal Properties and Solutions
Designing secure systems on reconfigurable hardware
Technology mapping algorithms for domino logic
Systemization of Knowledge: Robust Deep Learning using Hardware-software co-design in Centralized and Federated Settings
Incremental Layer Assignment for Timing Optimization
Introduction to the special section on demonstrable software systems and hardware platforms II
Effective Fault Effects Evaluation for Permanent Faults in GPUs executing DNNs
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh
Worst-Case Response Time Analysis of a Synchronous Dataflow Graph in a Multiprocessor System with Real-Time Tasks
A codesign experiment in acoustic echo cancellation GMDF
Path Selection for Real-Time Communication on Priority-Aware NoCs
FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs
Minimum delay optimization for domino circuits - a coupling-aware approach
Evolution of synthetic RTL benchmark circuits with predefined testability
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization
Garbage Collection for Multiversion Index in Flash-Based Embedded Databases
Optimal time borrowing analysis and timing budgeting optimization for latch-based designs
Covering Test Holes of Functional Broadside Tests
Efficient equivalence checking of multi-phase designs using phase abstraction and retiming
Optimal Allocation of LDOs and Decoupling Capacitors within a Distributed On-Chip Power Grid
Design intent coverage revisited
A C2RTL Framework Supporting Partition, Parallelization, and FIFO Sizing for Streaming Applications
A Generalized Definition of Unnecessary Test Vectors in Functional Test Sequences
Event propagation for accurate circuit delay calculation using SAT
Interconnect customization for a hardware fabric
Call for papers: Verification issue and challenges with multicore systems
Warp Processors
PeaPaw: Performance and Energy-Aware Partitioning of Workload on Heterogeneous Platforms
DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems
Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip
Coverage-Directed Test Generation Automated by Machine Learning - A Review
SAT-based ATPG using multilevel compatible don't-cares
Layout Synthesis for Quantum Circuits Considering Toffoli Gate Decomposition
Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs
Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints
Using implications to choose tests through suspect fault identification
Robust and Low-Power Digitally Programmable Delay Element Designs Employing Neuron-MOS Mechanism
Compilers for leakage power reduction
Dynamic Adaptation Using Deep Reinforcement Learning for Digital Microfluidic Biochips
Circuit-simulated obstacle-aware Steiner routing
Knowledge- and Simulation-Based Synthesis of Area-Efficient Passive Loop Filter Incremental Zoom-ADC for Built-In Self-Test Applications
The New Digital Wave of Rationalization: A Loss of Autonomy
The Ethics of Astrobiology and the Cosmic Bet Argument
Human Implants: A Suggested Framework to Set Priorities
Towards a Socially Responsible Research (SRR) Charter in Engineering Sciences at CNRS level
The Problem of Time's Passage: Using Historical Arguments to Inform the Debate
Cyber-Terrorism and Ethical Journalism: A Need for Rationalism
Counsellors' Phenomenological Experiences of Working with Children or Young People who have been Cyberbullied: Using Thematic Analysis of Semi Structured Interviews
Societal Implications of Current and Emerging "Smart" Technologies