yusuke1997/dblp-id-title huggingface dataset:
Exploiting workload dynamics to improve SSD read latency via differentiated error correction codes
Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework
Runtime Slack Creation for Processor Performance Variability using System Scenarios
Introduction to the Special Issue on Embedded System Software/Tools
Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis
Express Read in MLC Phase Change Memories
Optimized wafer-probe and assembled package test design for analog circuits
A predictive decode filter cache for reducing power consumption in embedded processors
Introduction to the Special Issue on Machine Learning for CAD
An Energy-Efficient Inference Method in Convolutional Neural Networks Based on Dynamic Adjustment of the Pruning Level
Architecture customization of on-chip reconfigurable accelerators
A fast and scalable multidimensional multiple-choice knapsack heuristic
Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices
A scheduling algorithm for optimization and early planning in high-level synthesis
Bounded-skew clock and Steiner routing
PV-Aware Analog Sizing for Robust Analog Layout Retargeting with Optical Proximity Correction
Variation-aware multimetric optimization during gate sizing
An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications
Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs
Design of Synthesis-time Vectorized Arithmetic Hardware for Tapered Floating-point Addition and Subtraction
Adaptive Control-Logic Routing with Length Matching and Fault Tolerance for FPVA Biochips Using Deep Reinforcement Learning
Variation-Aware Global Placement for Improving Timing-Yield of Carbon-Nanotube Field Effect Transistor Circuit
IC power delivery: Voltage regulation and conversion, system-level cooptimization and technology implications
Heterogeneously tagged caches for low-power embedded systems with virtual memory support
Multi-Objective 3D Floorplanning with Integrated Voltage Assignment
Accurate modeling of substrate resistive coupling for floating substrates
Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System
Power minimization algorithms for LUT-based FPGA technology mapping
EWD: A metamodeling driven customizable multi-MoC system modeling framework
A design automation and power estimation flow for RFID systems
A BNF-based automatic test program generator for compatible microprocessor verification
Architecture-level power estimation and design experiments
A multiple bit upset tolerant SRAM memory
Model refinement for hardware-software codesign
Preface to Special Section on New Physical Design Techniques for the Next Generation of Integration Technology
Machine Learning for Congestion Management and Routability Prediction within FPGA Placement
Scalable Power Management Using Multilevel Reinforcement Learning for Multiprocessors
Reducing test cost of integrated, heterogeneous systems using pass-fail test data analysis
Environment modeling and language universality
Search-space Decomposition for System-level Design Space Exploration of Embedded Systems
Automated Iterative Pipelining for ASIC Design
Modeling and Simulation of Dynamic Applications Using Scenario-Aware Dataflow
Synthesis of Clock Networks with a Mode-Reconfigurable Topology
SoC Protocol Implementation Verification Using Instruction-Level Abstraction Specifications
Security Threat Analyses and Attack Models for Approximate Computing Systems: From Hardware and Micro-architecture Perspectives
ILP and heuristic techniques for system-level design on network processor architectures
Advanced And-Inverter Graph Decomposition Technique for Reducing Circuit Complexity
Low-Power and testable circuit synthesis using Shannon decomposition
Efficient Parasitic-aware g m / I D - based Hybrid Sizing Methodology for Analog and RF Integrated Circuits
Design-for-testability for multi-cycle broadside tests by holding of state variables
Introduction to the Special Section on Energy-Efficient AI Chips
A performance-driven IC/MCM placement algorithm featuring explicit design space exploration
ACM Journal on Emerging Technologies in Computing Systems
On Chip Reconfigurable CMOS Analog Circuit Design and Automation Against Aging Phenomena: Sense and React
Combinatorial techniques for mixed-size placement
Low-power resource binding by postsilicon customization
Instruction generation for hybrid reconfigurable systems
A Disturbance-Free Built-In Self-Test and Diagnosis Technique for DC-DC Converters
Obstacle-Avoiding Algorithm in X-Architecture Based on Discrete Particle Swarm Optimization for VLSI Design
A Variation-aware Hold Time Fixing Methodology for Single Flux Quantum Logic Circuits
DRDU: A data reuse analysis technique for efficient scratch-pad memory management
DeepPM: Predicting Performance and Energy Consumption of Program Binaries Using Transformers
Idle energy minimization by mode sequence optimization
GPlace3.0: Routability-Driven Analytic Placer for UltraScale FPGA Architectures
Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions
Remote Detection of Unauthorized Activity via Spectral Analysis
A Formal Approach to Incremental Converter Synthesis for System-on-Chip Design
Ensemble Reduction via Logic Minimization
Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation
Streaming Sorting Networks
Concept-based partitioning for large multidomain multifunctional embedded systems
Efficient One-pass Synthesis for Digital Microfluidic Biochips
An Application Adaptation Approach to Mitigate the Impact of Dynamic Thermal Management on Video Encoding
Low-power anti-aging zero skew clock gating
Advancing Hyperdimensional Computing Based on Trainable Encoding and Adaptive Training for Efficient and Accurate Learning
Analysis of FPGA/FPIC switch modules
Adapting to Varying Distribution of Unknown Response Bits
A novel differential scan attack on advanced DFT structures
Supporting Timing-related Metrics for Autonomous Driving Frameworks in CyberRT
Implication of Optimizing NPU Dataflows on Neural Architecture Search for Mobile Devices
Register file partitioning and recompilation for register file power reduction
N -Detection Test Sets for Circuits with Multiple Independent Scan Chains
Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling
Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems
Congestion prediction in early stages of physical design
Targeted random test generation for power-aware multicore designs
Timing Analysis of System Initialization and Crash Recovery for a Segment-Based Flash Translation Layer
Instruction-level test methodology for CPU core self-testing
A Hardware-Efficient Block Matching Algorithm and Its Hardware Design for Variable Block Size Motion Estimation in Ultra-High-Definition Video Encoding
Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator
ERfair Scheduler with Processor Suspension for Real-Time Multiprocessor Embedded Systems
Leakage reduction, delay compensation using partition-based tunable body-biasing techniques
A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignment
A practical dynamic single assignment transformation
Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM
A Compact Implementation of Salsa20 and Its Power Analysis Vulnerabilities
Compile-time area estimation for LUT-based FPGAs
Reducing energy consumption of multiprocessor SoC architectures by exploiting memory bank locality
Performance and power profiling for emulated Android systems
Fast and accurate processor models for efficient MPSoC design
High-Throughput Logic Timing Simulation on GPGPUs
On the Reliability and Tightness of GP and Exponential Models for Probabilistic WCET Estimation
Test Templates to Guide Test Generation for Single-Cycle Gate-Exhaustive Faults
Machine Learning Assisted PUF Calibration for Trustworthy Proof of Sensor Data in IoT
Synthesizing Optimal Switching Lattices
Enhanced Real-time Scheduling of AVB Flows in Time-Sensitive Networking
Remote Attestation via Self-Measurement
Strong Logic Obfuscation with Low Overhead against IC Reverse Engineering Attacks
Dataflow Model-based Software Synthesis Framework for Parallel and Distributed Embedded Systems
A comparative evaluation of multi-objective exploration algorithms for high-level design
An interactive codesign environment for domain-specific coprocessors
ILOSSS - Improved Logic Synthesis based on Several Stateful Logic Gates
Resource Sharing of Pipelined Custom Hardware Extension for Energy-Efficient Application-Specific Instruction Set Processor Design
Design of Ultra-Low Power Scalable-Throughput Many-Core DSP Applications
An index-based management scheme with adaptive caching for huge-scale low-cost embedded flash storages
Bus-based communication synthesis on system level
Analysis of RC interconnections under ramp input
TAAL: Tampering Attack on Any Key-based Logic Locked Circuits
Gate-Level Information Flow Tracking for Security Lattices
Introduction to special section on high-level design, validation, and test
High-throughput Near-Memory Processing on CNNs with 3D HBM-like Memory
Increasing the Fault Coverage of a Truncated Test Set
Low test application time resource binding for behavioral synthesis
NoC Application Mapping Optimization Using Reinforcement Learning
Noc-HMP: A Heterogeneous Multicore Processor for Embedded Systems Designed in SystemJ
FortiFix : A Fault Attack Aware Compiler Framework for Crypto Implementations
C-CIM: A Multi-Mode Convolution-Capable SRAM-CIM
Equivalent Faults under Launch-on-Shift (LOS) Tests with Equal Primary Input Vectors
A Deep Learning Framework for Solving Stress-based Partial Differential Equations in Electromigration Analysis
Scale & Cap: Scaling-Aware Resource Management for Consolidated Multi-threaded Applications
IP Protection and Supply Chain Security through Logic Obfuscation: A Systematic Overview
In-Scratchpad Memory Replication: Protecting Scratchpad Memories in Multicore Embedded Systems against Soft Errors
Fundamental Challenges Toward Making the IoT a Reachable Reality: A Model-Centric Investigation
Hardware Trojan Mitigation in Pipelined MPSoCs
Periodic Scan-In States to Reduce the Input Test Data Volume for Partially Functional Broadside Tests
Spatial locality exploitation for runtime reordering of JPEG2000 wavelet data layouts
CDTA: A Comprehensive Solution for Counterfeit Detection, Traceability, and Authentication in the IoT Supply Chain
A Cost-Effective Energy Optimization Framework of Multicore SoCs Based on Dynamically Reconfigurable Voltage-Frequency Islands
Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips
Built-In Self-Test and Test Scheduling for Interposer-Based 2.5D IC
An Effective Chemical Mechanical Polishing Fill Insertion Approach
A Power Optimization Approach for Large-scale RM-TB Dual Logic Circuits Based on an Adaptive Multi-Task Intelligent Algorithm
Performance-driven dynamic thermal management of MPSoC based on task rescheduling
A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis
Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory
Efficient list-approximation techniques for floorplan area minimization
Mitigating the effects of large multiple cell upsets (MCUs) in memories
Optimal Don't Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing
Reduced On-chip Storage of Seeds for Built-in Test Generation
A model-based extensible framework for efficient application design using FPGA
Introduction to the special section on adaptive power management for energy and temperature-aware computing systems
A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning Inference
Reducing the Complexity of Dataflow Graphs Using Slack-Based Merging
A Module-Level Configuration Methodology for Programmable Camouflaged Logic
Integrated Coherence Prediction: Towards Efficient Cache Coherence on NoC-Based Multicore Architectures
Fast poisson solvers for thermal analysis
Tunable FPGA Bitstream Obfuscation with Boolean Satisfiability Attack Countermeasure
An Open-Source ML-Based Full-Stack Optimization Framework for Machine Learning Accelerators
Architectural Supports to Protect OS Kernels from Code-Injection Attacks and Their Applications
Multicast Testing of Interposer-Based 2.5D ICs: Test-Architecture Design and Test Scheduling
Temperature-aware register reallocation for register file power-density minimization
Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes
Novel Adaptive Power-Gating Strategy and Tapered TSV Structure in Multilayer 3D IC
DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems
Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling
Parallel logic simulation on a network of workstations using parallel virtual machine
A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator
An algorithm for synthesis of large time-constrained heterogeneous adaptive systems
Enhanced PATRON: Fault Injection and Power-aware FSM Encoding Through Linear Programming
Low power realization of finite state machines - a decomposition approach
Low-Power Clock Tree Synthesis for 3D-ICs
Forced simulation: A technique for automating component reuse in embedded systems
Editorial for TODAES Special Issue on Internet of Things System Performance, Reliability, and Security
Design-for-Testability for Functional Broadside Tests under Primary Input Constraints
CoMETC: Coordinated management of energy/thermal/cooling in servers
Harnessing the Granularity of Micro-Electrode-Dot-Array Architectures for Optimizing Droplet Routing in Biochips
Revealing Cluster Hierarchy in Gate-level ICs Using Block Diagrams and Cluster Estimates of Circuit Embeddings
Optimal Allocation of Computation and Communication in an IoT Network
Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter
Improving FPGA-Based Logic Emulation Systems through Machine Learning
Shared recovery for energy efficiency and reliability enhancements in real-time applications with precedence constraints
Secure Assay Execution on MEDA Biochips to Thwart Attacks Using Real-Time Sensing
Introduction to the Special Section on High-level Synthesis for FPGA: Next-generation Technologies and Applications
FuzzRoute: A Thermally Efficient Congestion-Free Global Routing Method for Three-Dimensional Integrated Circuits
ESPSim: An Efficient Scalable Power Grid Simulator Based on Parallel Algebraic Multigrid
HSG-RAG: Hierarchical Knowledge Base Construction for Embedded System Development
Low-power TinyOS tuned processor platform for wireless sensor network motes
Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration
CRP2.0: A Fast and Robust Cooperation between Routing and Placement in Advanced Technology Nodes
Quantum Circuit Transformation: A Monte Carlo Tree Search Framework
Symbolic-Event-Propagation-Based Minimal Test Set Generation for Robust Path Delay Faults
Timing variation-aware scheduling and resource binding in high-level synthesis
Scheduling techniques for variable voltage low power designs
Clock buffer polarity assignment with skew tuning
Accelerating Graph Computations on 3D NoC-Enabled PIM Architectures
Generation of Transparent-Scan Sequences for Diagnosis of Scan Chain Faults
Runtime verification for multicore SoC with high-quality trace data
Fast placement approaches for FPGAs
Specification-driven directed test generation for validation of pipelined processors
Temporal floorplanning using the three-dimensional transitive closure subGraph
Energy-efficient datapath scheduling using multiple voltages and dynamic clocking
Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction
Multi-target Fluid Mixing in MEDA Biochips: Theory and an Attempt toward Waste Minimization
Behavioral synthesis of combinational logic using spectral-based heuristics
Auxiliary state machines + context-triggered properties in verification
Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient SIMD Soft Multiplier-divider
Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control
Code generation for fixed-point DSPs
Sensor-Aware Data Imputation for Time-Series Machine Learning on Low-Power Wearable Devices
Postplacement rewiring by exhaustive search for functional symmetries
Introduction to special issue on demonstrable software systems and hardware platforms
External memory layout vs. schematic
Online thermal control methods for multiprocessor systems
Optimization of Threshold Logic Networks with Node Merging and Wire Replacement
Frequent value encoding for low power data buses
Wavelet-based dynamic power management for nonstationary service requests
DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction
Experimental analysis of the fastest optimum cycle ratio and mean algorithms
Obstacle-Avoiding Wind Turbine Placement for Power Loss and Wake Effect Optimization
A Survey of Parametric Dataflow Models of Computation
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
Test chip experimental results on high-level structural test
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability
Deep Reinforcement Learning-based Mining Task Offloading Scheme for Intelligent Connected Vehicles in UAV-aided MEC
Rank-DSE: Neural Pareto Comparator of Microarchitecture Design Space Exploration
A Survey on Security of Digital Microfluidic Biochips: Technology, Attack, and Defense
Power reduction and power-delay trade-offs using logic transformations
A Tensor Network based Decision Diagram for Representation of Quantum Circuits
Layer Assignment of Escape Buses with Consecutive Constraints in PCB Designs
Performance-constrained voltage assignment in multiple supply voltage SoC floorplanning
Modular Neural Networks for Low-Power Image Classification on Embedded Devices
A MATLAB Vectorizing Compiler Targeting Application-Specific Instruction Set Processors
Ordering circuit establishment in multiplane NoCs
Three-dimensional Floorplan Representations by Using Corner Links and Partial Order
Emerging NVM: A Survey on Architectural Integration and Research Challenges
FaultDroid: An Algorithmic Approach for Fault-Induced Information Leakage Analysis
Autonomous hardware/software partitioning and voltage/frequency scaling for low-power embedded systems
Synthesis of saturation arithmetic architectures
DPTM: An Adaptive Scheduler Design Utilizing Timeslot Matching and Release Methods for Concurrent and Multi-task Interleaved Pipelining-oriented CGRA
Application-Specific Residential Microgrid Design Methodology
SPTA 2.0: Enhanced Scalable Parallel Track Assignment Algorithm with Two-Stage Partition Considering Timing Delay
Energy-aware Scheduling of Task Graphs with Imprecise Computations and End-to-end Deadlines
An Analytical Solution for Transient Electromigration Stress in Multisegment Straight-line Interconnects Based on a Stress-wave Model
Memory-Throughput Trade-off for CNN-Based Applications at the Edge
Reducing fault dictionary size for million-gate large circuits
XFM: An incremental methodology for developing formal models
Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation
Design Automation for Tree-based Nearest Neighborhood-aware Placement of High-speed Cellular Automata on FPGA with Scan Path Insertion
Test compaction techniques for assertion-based test generation
Selection of Critical Paths for Reliable Frequency Scaling under BTI-Aging Considering Workload Uncertainty and Process Variations Effects
NBTI-Aware Clustered Power Gating
FPGA-based hardware acceleration for Boolean satisfiability
Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory
Offline Washing Schemes for Residue Removal in Digital Microfluidic Biochips
Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control
Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective
On Fundamental Principles for Thermal-Aware Design on Periodic Real-Time Multi-Core Systems
An Improved Methodology for Resilient Design Implementation
A self-tuning design methodology for power-efficient multi-core systems
Transistor reordering for power minimization under delay constraint
A Multilevel Spectral Framework for Scalable Vectorless Power/Thermal Integrity Verification
High-level Synthesis Directives Design Optimization via Large Language Model
BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration
HDLdebugger: Streamlining HDL debugging with Large Language Models
An o ( min ( m , n )) parallel deadlock detection algorithm
Scrubbing Mechanism for Heterogeneous Applications in Reconfigurable Devices
MVP: An Efficient CNN Accelerator with Matrix, Vector, and Processing-Near-Memory Units
A memetic approach to the automatic design of high-performance analog integrated circuits
Energy Efficient Chip-to-Chip Wireless Interconnection for Heterogeneous Architectures
An event-based monitoring service for networks on chip
Securing Network-on-Chips against Trojan-Induced Packet Duplication Attacks
Diagnosability of Component-Composition Graphs in the MM* Model
Performance Analysis of CNN Inference/Training with Convolution and Non-Convolution Operations on ASIC Accelerators
Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime
Learning-Based, Fine-Grain Power Modeling of System-Level Hardware IPs
Timing Path-Driven Cycle Cutting for Sequential Controllers
Deflection routing in 3D network-on-chip with limited vertical bandwidth
Routability-driven Power/Ground Network Optimization Based on Machine Learning
Fast Simulation of Networks-on-Chip with Priority-Preemptive Arbitration
Ax-BxP: Approximate Blocked Computation for Precision-reconfigurable Deep Neural Network Acceleration
Multi-Stream Scheduling of Inference Pipelines on Edge Devices - a DRL Approach
Voltage-Based Covert Channels Using FPGAs
A Hardware/Software Cooperative Custom Register Binding Approach for Register Spill Elimination in Application-Specific Instruction Set Processors
Single-Event Multiple-Transient Characterization and Mitigation via Alternative Standard Cell Placement Methods
On the Restore Time Variations of Future DRAM Memory
A flexible datapath allocation method for architectural synthesis
SHAIP: Secure Hamming Distance for Authentication of Intrinsic PUFs
Rescuing ReRAM-based Neural Computing Systems from Device Variation
Performance bound analysis of analog circuits in frequency- and time-domain considering process variations
Clock-Tree-Aware Incremental Timing-Driven Placement
Dynamic Power Management in Large Manycore Systems: A Learning-to-Search Framework
A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs
MAB-BMC: A Formal Verification Enhancer by Harnessing Multiple BMC Engines Together
Ising-FPGA: A Spintronics-based Reconfigurable Ising Model Solver
Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing