yusuke1997/dblp-id-title huggingface dataset:
A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip
Electra: Eliminating the Ineffectual Computations on Bitmap Compressed Matrices
Worklist-Directed Prefetching
An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation
Infinity Stream: Enabling Transparent and Automated In-Memory Computing
DPWatch: A Framework for Hardware-Based Differential Privacy Guarantees
Enabling In-SRAM Pattern Processing With Low-Overhead Reporting Architecture
Characterizing and Understanding Defense Methods for GNNs on GPUs
DRACO: A Deduplicating FTL for Tangible Extra Capacity
MixDiT: Accelerating Image Diffusion Transformer Inference With Mixed-Precision MX Quantization
X-ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands
Constrained Energy Optimizationin Heterogeneous Platforms UsingGeneralized Scaling Models
Cache and Near-Data Co-Design for Chiplets
A Quantitative Analysis of Mamba-2-Based Large Language Model: Study of State Space Duality
Heavy Tails in Program Structure
DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator
CARB: A C-State Power Management Arbiter for Latency-Critical Workloads
A Case for a Value-Aware Cache
Locality-Aware GPU Register File
Measuring the Impact of Memory Errors on Application Performance
Centralized Adaptive Routing for NoCs
Scale-Model Simulation
Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching
Power-Efficient Accelerator Design for Neural Networks Using Computation Reuse
Enhancing the L1 Data Cache Design to Mitigate HCI
Cloud Server Benchmark Suite for Evaluating New Hardware Architectures
Context-Aware Set Dueling for Dynamic Policy Arbitration
Spatial Correlation and Value Prediction in Convolutional Neural Networks
CF-TUNE: Collaborative Filtering Auto-Tuning for Energy Efficient Many-Core Processors
Exploiting Low Entropy to Reduce Wire Delay
Architectural Security Regulation
Vertical Writes: Closing the Throughput Gap between Deeply Scaled STT-MRAM and DRAM
Zero-Copying I/O Stack for Low-Latency SSDs
Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors
Enabling Massive Multi-Threading with Fast Hashing
A Speculative Coherence Scheme using Decoupling Synchronization for Multiprocessor Systems
Pipelined Architecture for Multi-String Matching
PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM
Exploiting Internal Parallelism of Flash-based SSDs
B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors
DRAMA: Commodity DRAM Based Content Addressable Memory
DAEGEN: A Modular Compiler for Exploring Decoupled Spatial Accelerators
SMT Switch: Software Mechanisms for Power Shifting
Data-Aware Compression of Neural Networks
HINT: A Hardware Platform for Intra-Host NIC Traffic and SmartNIC Emulation
Thread-Sensitive Instruction Issue for SMT Processors
A Cross-Stack Approach Towards Defending Against Cryptojacking
LeakDiT: Diffusion Transformers for Trace-Augmented Side-Channel Analysis
GPU-NEST: Characterizing Energy Efficiency of Multi-GPU Inference Servers
DAMARU: A Denial-of-Service Attack on Randomized Last-Level Caches
On-Demand Dynamic Branch Prediction
A Data Prefetcher-Based 1000-Core RISC-V Processor for Efficient Processing of Graph Neural Networks
The Netflix Challenge: Datacenter Edition
Runtime-Assisted Global Cache Management for Task-Based Parallel Programs
BTB-X: A Storage-Effective BTB Organization
Beyond Fat-tree: Unidirectional Load--Balanced Multistage Interconnection Network
BRAWL: A Spintronics-Based Portable Basecalling-in-Memory Architecture for Nanopore Genome Sequencing
A Way-Halting Cache for Low-Energy High-Performance Systems
HeteroSim: A Heterogeneous CPU-FPGA Simulator
Reducing the Silicon Area Overhead of Counter-Based Rowhammer Mitigations
SmartSSD: FPGA Accelerated Near-Storage Data Analytics on SSD
Decoupled MapReduce for Shared-Memory Multi-Core Architectures
On Optimal Kernel Size for Integrated CPU-GPUs - A Case Study
Power Profiling of Modern Die-Stacked Memory
GCMS: A Global Contention Management Scheme in Hardware Transactional Memory
Demystifying multicore throughput metrics
Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions
TWiCe: Time Window Counter Based Row Refresh to Prevent Row-Hammering
Argus-G: Comprehensive, Low-Cost Error Detection for GPGPU Cores
MinneSPEC: A New SPEC Benchmark Workload for Simulation-Based Computer Architecture Research
Regression Prefetcher with Preprocessing for DRAM-PCM Hybrid Main Memory
High Performance, Energy Efficient Chipkill Correct Memory with Multidimensional Parity
A Scalable HW-Based Inline Deduplication for SSD Arrays
SoCurity: A Design Approach for Enhancing SoC Security
FPGA-Based AI Smart NICs for Scalable Distributed AI Training Systems
The Entangling Instruction Prefetcher
Old is Gold: Optimizing Single-Threaded Applications With ExGen-Malloc
On-Chip Message Passing Sub-System for Embedded Inter-Domain Communication
Hardware-Accelerated Kernel-Space Memory Compression Using Intel QAT
ScaleGPU: GPU Architecture for Memory-Unaware GPU Programming
PRR-PRR Dynamic Relocation
Decongest: Accelerating Super-Dense PCM Under Write Disturbance by Hot Page Remapping
Core Reliability: Leveraging Hardware Transactional Memory
Improving Performance on Tiered Memory With Semantic Data Placement
Performance Scalability Analysis of JavaScript Applications with Web Workers
NoHammer: Preventing Row Hammer With Last-Level Cache Management
CoreNap: Energy Efficient Core Allocation for Latency-Critical Workloads
HAD-TWL: Hot Address Detection-Based Wear Leveling for Phase-Change Memory Systems with Low Latency
Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core
Optically Connected Multi-Stack HBM Modules for Large Language Model Training and Inference
LA-LLC: Inter-Core Locality-Aware Last-Level Cache to Exploit Many-to-Many Traffic in GPGPUs
TRiM: Tensor Reduction in Memory
Exploring the Interaction Between Device Lifetime Reliability and Security Vulnerabilities
Probabilistic Prediction of Temporal Locality
Randomized Partially-Minimal Routing on Three-Dimensional Mesh Networks
Achieving Forward Progress Guarantee in Small Hardware Transactions
SmartIndex: Learning to Index Caches to Improve Performance
Improving Energy-Efficiency of Capsule Networks on Modern GPUs
A Cross-Layer Multicore Architecture to Tradeoff Program Accuracy and Resilience Overheads
AYUSH: A Technique for Extending Lifetime of SRAM-NVM Hybrid Caches
Architectural Implications of Graph Neural Networks
Low-Latency PIM Accelerator for Edge LLM Inference
CompressPoints: An Evaluation Methodology for Compressed Memory Systems
Runtime Support for Accelerating CNN Models on Digital DRAM Processing-in-Memory Hardware
CMA: A Reconfigurable Complex Matching Accelerator for Wire-Speed Network Intrusion Detection
A Coarse-Grained Reconfigurable Architecture for Compute-Intensive MapReduce Acceleration
ARSENAL: Architecture for Secure Non-Volatile Memories
Tuning Performance via Metrics with Expectations
Covert Channels on GPGPUs
Inter-Core Locality Aware Memory Scheduling
Exploring Core and Cache Hierarchy Bottlenecks in Graph Processing Workloads
PIMSim: A Flexible and Detailed Processing-in-Memory Simulator
SPAM: Streamlined Prefetcher-Aware Multi-Threaded Cache Covert-Channel Attack
A DSP-Based Precision-Scalable MAC With Hybrid Dataflow for Arbitrary-Basis-Quantization CNN Accelerator
Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling
Characterizing the Energy Consumption of Software Transactional Memory
Guard Cache: Creating Noisy Side-Channels
Performance and Fairness Improvement on CMPs Considering Bandwidth and Cache Utilization
WPC: Whole-Picture Workload Characterization Across Intermediate Representation, ISA, and Microarchitecture
A Methodology for Cognitive NoC Design
Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors
A Process-Variation Aware Technique for Tile-Based, Massive Multicore Processors
Initial Results on Fuzzy Floating Point Computation for Multimedia Processors
Smart Memory: Deep Learning Acceleration in 3D-Stacked Memories
Making a Better Use of Caches for GCN Accelerators with Feature Slicing and Automatic Tile Morphing
Nahalal: Cache Organization for Chip Multiprocessors
Hardware Acceleration for GCNs via Bidirectional Fusion
Thor: A Non-Speculative Value Dependent Timing Side Channel Attack Exploiting Intel AMX
Characterizing and Understanding End-to-End Multi-Modal Neural Networks on GPUs
Modeling Emerging Memory-Divergent GPU Applications
Timing Speculation in Multi-Cycle Data Paths
Microarchitectures for Managing Chip Revenues under Process Variations
Cache Replacement Policy Based on Expected Hit Count
Estimating CPI Stacks From Multiplexed Performance Counter Data Using Machine Learning
A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture
Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator
Multicore Resource Isolation for Deterministic, Resilient and Secure Concurrent Execution of Safety-Critical Applications
ZoneBuffer: An Efficient Buffer Management Scheme for ZNS SSDs
Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks
Accelerator Memory Reuse in the Dark Silicon Era
Multilevel Cache Modeling for Chip-Multiprocessor Systems
Inspex: Speculative Execution of Ready-to-Execute Loads in In-Order Cores
Characterization and Analysis of Deep Learning for 3D Point Cloud Analytics
DRAM-CAM: General-Purpose Bit-Serial Exact Pattern Matching
Shimmer: Implementing a Heterogeneous-Reliability DRAM Framework on a Commodity Server
Octopus: A Cycle-Accurate Cache System Simulator
Counter-Based Tree Structure for Row Hammering Mitigation in DRAM
Persistent Transactional Memory
SimpleSSD: Modeling Solid State Drives for Holistic System Simulation
Isolating Speculative Data to Prevent Transient Execution Attacks
Memory-Centric MCM-GPU Architecture
Ramulator: A Fast and Extensible DRAM Simulator
Amethyst: Reducing Data Center Emissions With Dynamic Autotuning and VM Management
Cache Impacts of Datatype Acceleration
Network-on-SSD: A Scalable and High-Performance Communication Design Paradigm for SSDs
MajorK: Majority Based kmer Matching in Commodity DRAM
Leveraging Heterogeneous Power for Improving Datacenter Efficiency and Resiliency
Overcoming Memory Capacity Wall of GPUs With Heterogeneous Memory Stack
RouteReplies: Alleviating Long Latency in Many-Chip-Module GPUs
The Jaseci Programming Paradigm and Runtime Stack: Building Scale-Out Production Applications Easy and Fast
Exploring KV Cache Quantization in Multimodal Large Language Model Inference
PIMsynth: A Unified Compiler Framework for Bit-Serial Processing-in-Memory Architectures
OASIS: Outlier-Aware KV Cache Clustering for Scaling LLM Inference in CXL Memory Systems
By-Software Branch Prediction in Loops
Request Reordering to Enhance the Performance of Strict Consistency Models
CIM: A Reliable Metric for Evaluating Program Phase Classifications
A Deep Q-Learning Approach for Dynamic Management of Heterogeneous Processors
Accelerating Graph Processing With Lightweight Learning-Based Data Reordering
Exploiting Locality to Improve Circuit-Level Timing Speculation
DCC: A Dependable Cache Coherence Multicore Architecture
A Pre-Silicon Approach to Discovering Microarchitectural Vulnerabilities in Security Critical Applications
SmaQ: Smart Quantization for DNN Training by Exploiting Value Clustering
A High-Bandwidth PCM-Based Memory System for Highly Available IP Routing Table Lookup
Architectural Implications of GNN Aggregation Programming Abstractions
Scalable LLVM-Based Accelerator Modeling in gem5
Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model
Efficient Memory Layout for Pre-Alignment Filtering of Long DNA Reads Using Racetrack Memory
Coordinated DVFS and Precision Control for Deep Neural Networks
Comparing Stochastic and Deterministic Computing
Decoupling Datacenter Storage Studies from Access to Large-Scale Applications
NoM: Network-on-Memory for Inter-Bank Data Transfer in Highly-Banked Memories
OpenMDS: An Open-Source Shell Generation Framework for High-Performance Design on Xilinx Multi-Die FPGAs
Efficient Execution of Bursty Applications
Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links
A Case for Memory-Centric HPC System Architecture for Training Deep Neural Networks
RAMBO: Resource Allocation for Microservices Using Bayesian Optimization
MOST: Memory Oversubscription-Aware Scheduling for Tensor Migration on GPU Unified Storage
Instruction Shuffle: Achieving MIMD-like Performance on SIMD Architectures
Stripes: Bit-Serial Deep Neural Network Computing
High-Performance Winograd Based Accelerator Architecture for Convolutional Neural Network
Resistive Computation: A Critique
Leveraging Hardware Caches for Memoization
Globally Adaptive Load-Balanced Routing on Tori
Breaking the Synchronization Bottleneck with Reconfigurable Transactional Execution
Characterization and Implementation of Radar System Applications on a Reconfigurable Dataflow Architecture
DeMM: A Decoupled Matrix Multiplication Engine Supporting Relaxed Structured Sparsity
Introducing the New Editor-in-Chief of IEEE Computer Architecture Letters
Restating the Case for Weighted-IPC Metrics to Evaluate Multiprogram Workload Performance
Improving GPU Multitasking Efficiency Using Dynamic Resource Sharing
ReDRAM: A Reconfigurable DRAM Cache for GPGPUs
SparseLeakyNets: Classification Prediction Attack Over Sparsity-Aware Embedded Neural Networks Using Timing Side-Channel Information
Characterizing and Understanding GCNs on GPU
Value Locality Based Approximation With ODIN
SVSoC: Speculative Vision Systems-on-a-Chip
Hybrid Remote Access Protocol
An FPGA-based In-Line Accelerator for Memcached
Rusty: Runtime System Predictability Leveraging LSTM Neural Networks
ADT: Aggressive Demotion and Promotion for Tiered Memory
WoperTM: Got Nacks? Use Them!
Dynamic Optimization of On-Chip Memories for HLS Targeting Many-Accelerator Platforms
LADIO: Leakage-Aware Direct I/O for I/O-Intensive Workloads
Analysis of Data Transfer Bottlenecks in Commercial PIM Systems: A Study With UPMEM-PIM
Contention-Aware GPU Thread Block Scheduler for Efficient GPU-SSD
SEMS: Scalable Embedding Memory System for Accelerating Embedding-Based DNNs
PreGNN: Hardware Acceleration to Take Preprocessing Off the Critical Path in Graph Neural Networks
Corollaries to Amdahl's Law for Energy
Block Unification IF-conversion for High Performance Architectures
Architecting Compatible PIM Protocol for CPU-PIM Collaboration
The Case for Dynamic Bias in Global Adaptive Routing
Near-Data Processing in Memory Expander for DNN Acceleration on GPUs
A Model for Scalable and Balanced Accelerators for Graph Processing
Non-Intrusive Persistence with a Backend NVM Controller
Fast Bulk Bitwise AND and OR in DRAM
Logic-Based Distributed Routing for NoCs
A Lightweight Memory Access Pattern Obfuscation Framework for NVM
L-DTC: Load-based Dynamic Throughput Control for Guaranteed I/O Performance in Virtualized Environments
Leveraging Approximation to Improve Datacenter Resource Efficiency
Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks
Performance Modeling and Bottleneck Analysis of EDGE Processors Using Dependence Graphs
LV: Latency-Versatile Floating-Point Engine for High-Performance Deep Neural Networks
A Case for Hardware Memoization in Server CPUs
Accelerating Concurrent Priority Scheduling Using Adaptive in-Hardware Task Distribution in Multicores
Approximate Multiplier Design With LFSR-Based Stochastic Sequence Generators for Edge AI
CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction
In-network cache coherence
Intra-Socket and Inter-Socket Communication in Multi-core Systems
IntervalSim++: Enhanced Interval Simulation for Unbalanced Processor Designs
Hardware-Implemented Lightweight Accelerator for Large Integer Polynomial Multiplication
A HW/SW Co-designed Programmable Functional Unit
Mitigating Power Contention: A Scheduling Based Approach
Operand Registers and Explicit Operand Forwarding
X-PPR: Post Package Repair for CXL Memory
Distributed Memory Integrity Trees
End-Point Congestion Filter for Adaptive Routing with Congestion-Insensitive Performance
Structured Combinators for Efficient Graph Reduction
A Case for Compressing Traces with BDDs
Disintermediated Active Communication
Inter-Temperature Bandwidth Reduction in Cryogenic QAOA Machines
Correct Wrong Path
A New Class of Covert Channels Exploiting Power Management Vulnerabilities
DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches
The Case for VLIW-CMP as a Building Block for Exascale
Partitioning Compute Units in CNN Acceleration for Statistical Memory Traffic Shaping
Towards High-Performance Bufferless NoCs with SCEPTER
MCsim: An Extensible DRAM Memory Controller Simulator
Efficient In-Memory Processing Using Spintronics
Migration in Single Chip Multiprocessors
Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER
Orbital Edge Computing: Machine Inference in Space
Peripheral Memory: A Technique for Fighting Memory Bandwidth Bottleneck
Accelerating LLM Inference via Dynamic KV Cache Placement in Heterogeneous Memory System
Hungarian Qubit Assignment for Optimized Mapping of Quantum Circuits on Multi-Core Architectures
Camulator: A Lightweight and Extensible Trace-Driven Cache Simulator for Embedded Multicore SoCs
Towards Scalable Analytics with Inference-Enabled Solid-State Drives
Efficiently Evaluating Speedup Using Sampled Processor Simulation
SLO-Aware GPU DVFS for Energy-Efficient LLM Inference Serving
A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM
Towards Improved Power Management in Cloud GPUs
A Partial Tag-Data Decoupled Architecture for Last-Level Cache Optimization
XLA-NDP: Efficient Scheduling and Code Generation for Deep Learning Model Training on Near-Data Processing Memory
FullPack: Full Vector Utilization for Sub-Byte Quantized Matrix-Vector Multiplication on General Purpose CPUs
Exploiting Intel AMX Power Gating
An Intermediate Language for General Sparse Format Customization
Refactored Design of I/O Architecture for Flash Storage
Design Space Exploration of Memory Controller Placement in Throughput Processors with Deep Learning
Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction
Probabilistic counter updates for predictor hysteresis and bias
DNA Pre-Alignment Filter Using Processing Near Racetrack Memory
RPPM: Rapid Performance Prediction of Multithreaded Applications on Multicore Hardware
From sequential programs to concurrent threads
Coding Last Level STT-RAM Cache for High Endurance and Low Power
Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units
The Accelerator Store framework for high-performance, low-power accelerator-based systems
CPU Accounting in CMP Processors
Optimizing Read-Once Data Flow in Big-Data Applications
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
vCache: Providing a Transparent View of the LLC in Virtualized Environments
FeSSD: A Fast Encrypted SSD Employing On-Chip Access-Control Memory
Epoch Profiles: Microarchitecture-Based Application Analysis and Optimization
MNCaRT: An Open-Source, Multi-Architecture Automata-Processing Research and Execution Ecosystem
Address Scaling: Architectural Support for Fine-Grained Thread-Safe Metadata Management
IDIO: Orchestrating Inbound Network Data on Server Processors
gem5-gpu: A Heterogeneous CPU-GPU Simulator
srNAND: A Novel NAND Flash Organization for Enhanced Small Read Throughput in SSDs
EgDiff: An Enhanced Global Load Value Predictor
Fine-Grained Scheduling in Heterogeneous-ISA Architectures
Stride Equality Prediction for Value Speculation
Towards an Accelerator for Differential and Algebraic Equations Useful to Scientists
Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications
Intelligent SSD Firmware for Zero-Overhead Journaling
MQSim-E: An Enterprise SSD Simulator
Characterizing and Understanding Distributed GNN Training on GPUs
A Hardware-Friendly Tiled Singular-Value Decomposition-Based Matrix Multiplication for Transformer-Based Models
Multicore DIMM: an Energy Efficient Memory Module with Independently Controlled DRAMs
Empirical Architectural Analysis on Performance Scalability of Petascale All-Flash Storage Systems
LINAC: A Spatially Linear Accelerator for Convolutional Neural Networks
FPGA-Accelerated Data Preprocessing for Personalized Recommendation Systems
Fold-PIM: A Cost-Efficient LPDDR5-Based PIM for On-Device SLMs
A Study of Memory Placement on Hardware-Assisted Tiered Memory Systems
Tulip: Turn-Free Low-Power Network-on-Chip
TeleVM: A Lightweight Virtual Machine for RISC-V Architecture
Energy Aware Persistence: Reducing the Energy Overheads of Persistent Memory
Revisiting Browser Performance Benchmarking From an Architectural Perspective
Multi-Stage CPI Stacks
DRAMSim2: A Cycle Accurate Memory System Simulator
Accelerators & Security: The Socket Approach
Fairness Metrics for Multi-Threaded Processors
Security Helper Chiplets: A New Paradigm for Secure Hardware Monitoring
MultiAmdahl: How Should I Divide My Heterogenous Chip?
Implementing Decay Techniques using 4T Quasi-Static Memory Cells
Priority-Based PCIe Scheduling for Multi-Tenant Multi-GPU Systems
Characterizing the System Overhead of Discrete Noise Generation for Differential Privacy
Accelerating Deep Reinforcement Learning via Phase-Level Parallelism for Robotics Applications
Set-Granular Regional Distributed Cooperative Caching
Bit-Level Load Balancing: A New Technique for Improving the Write Throughput of Deeply Scaled STT-MRAM
DVFaaS: Leveraging DVFS for FaaS Workflows
A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Open-Source Hardware Memory Protection Engine Integrated With NVMM Simulator
A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors
Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example
SSE: Security Service Engines to Accelerate Enclave Performance in Secure Multicore Processors
Determining Optimal Coherency Interface for Many-Accelerator SoCs Using Bayesian Optimization
A Low Power TLB Structure for Embedded Systems
A Flexible Hybrid Interconnection Design for High-Performance and Energy-Efficient Chiplet-Based Systems
An Overview of Static Pipelining
Disaggregated Speculative Decoding for Carbon-Efficient LLM Serving
Thread-Adaptive: High-Throughput Parallel Architectures of SLH-DSA on GPUs
Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline
Hardware Accelerated Reusable Merkle Tree Generation for Bitcoin Blockchain Headers
KSM: Online Application-Level Performance Slowdown Prediction for Spatial Multitasking GPGPU
CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults
pd-gem5: Simulation Infrastructure for Parallel/Distributed Computer Systems
Architecting Flash-based Solid-State Drive for High-performance I/O Virtualization
Semi-Coherent DMA: An Alternative I/O Coherency Management for Embedded Systems
Deep Partitioned Training From Near-Storage Computing to DNN Accelerators
Optimization of Application-Specific Memories
Toggle-Aware Compression for GPUs
UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development
A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems
Exploiting Direct Memory Operands in GPU Instructions
The Case for Domain-Specialized Branch Predictors for Graph-Processing
SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture
Cycle-Oriented Dynamic Approximation: Architectural Framework to Meet Performance Requirements
VMOR: Microarchitectural Support for Operand Access in an Interpreter
Enabling Cost-Efficient LLM Inference on Mid-Tier GPUs With NMP DIMMs