yusuke1997/dblp-id-title huggingface dataset:
Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems
Hybrid L2 NUCA Design and Management Considering Data Access Latency, Energy Efficiency, and Storage Lifetime
Guest Editorial: Special Section on Autonomous Intelligence for Security and Privacy Analytics
Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET
Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool
A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network
Wafer-level package interconnect options
An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management
The LOTTERYBUS on-chip communication architecture
Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization
A Semiblind Digital-Domain Calibration of Pipelined A/D Converters via Convex Optimization
Model Order Reduction Method for Large-Scale RC Interconnect and Implementation of Adaptive Digital PI Controller
ADC-Based Backplane Receiver Design-Space Exploration
Adaptive low-power address encoding techniques using self-organizing lists
A VLSI Circuit Emulation of Chemical Synaptic Transmission Dynamics and Postsynaptic DNA Transcription
Cost-Effective Enhancement on Both Yield and Reliability for Cache Designs Based on Performance Degradation Tolerance
Hardware Implementation of an OPC UA Server for Industrial Field Devices
A robust self-calibrating transmission scheme for on-chip networks
A Fast-Convergence Near-Memory-Computing Accelerator for Solving Partial Differential Equations
Stride 2 1-D, 2-D, and 3-D Winograd for Convolutional Neural Networks
Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction
STEAC: A Platform for Automatic SOC Test Integration
Efficient library characterization for high-level power estimation
Determining objective functions in systolic array designs
Assessment and Mitigation of Power Side-Channel-Based Cross-PUF Attacks on Arbiter-PUFs and Their Derivatives
TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs
A reconfigurable, power-efficient adaptive Viterbi decoder
Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router
Design of reconfigurable access wrappers for embedded core based SoC test
A 175.2-mW 4-Stage OTA With Wide Load Range (400 pF-12 nF) Using Active Parallel Compensation
Storage-Based Logic Built-In Self-Test With Partitioned Deterministic Compressed Tests
Mesh routing topologies for multi-FPGA systems
DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction
A Temperature Estimation Method Using the Ratio of Emitter-to-Base Voltages
A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing
A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM
Carry checking/parity prediction adders and ALUs
Maximizing throughput over parallel wire structures in the deep submicrometer regime
Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study
Substrate coupling in digital circuits in mixed-signal smart-power systems
An Energy-Efficient Deep Convolutional Neural Network Inference Processor With Enhanced Output Stationary Dataflow in 65-nm CMOS
Area-Delay Efficient Binary Adders in QCA
Variation-Aware Adaptive Voltage Scaling System
Design and Sensitivity Analysis of a New Current-Mode Sense Amplifier for Low-Power SRAM
Fast, Ring-Based Design of 3-D Stacked DRAM
Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology
Design and Analysis of Energy-Efficient and Reliable 3-D ReRAM Cross-Point Array System
Optimizing the Use of STT-RAM in SSDs Through Data-Dependent Error Tolerance
Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems
An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques
Diagnose Failures Caused by Multiple Locations at a Time
Dynamic Resource Management of Heterogeneous Mobile Platforms via Imitation Learning
Formal Modeling and Verification of PCHB Asynchronous Circuits
Approximation of Transcendental Functions With Guaranteed Algorithmic QoS by Multilayer Pareto Optimization
Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories
Efficient Compression-Based Line Buffer Design for Image/Video Processing Circuits
High-level synthesis of recoverable VLSI microarchitectures
Tracking On-Chip Age Using Distributed, Embedded Sensors
Low-Power and Area-Efficient Carry Select Adder
A Real-Time Object Detection Processor With xnor-Based Variable-Precision Computing Unit
Accelerating Recurrent Neural Networks: A Memory-Efficient Approach
A Reusable and Efficient Architecture for QC-LDPC Encoder With Less Expansion Factors
Hybrid Working Set Algorithm for SVM Learning With a Kernel Coprocessor on FPGA
Design and analysis of defect tolerant hierarchical sorting networks
Accurate Current Estimation for Interconnect Reliability Analysis
Physical resource binding for a coarse-grain reconfigurable array using evolutionary algorithms
Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs
Simulation Methodology and Evaluation of Through Silicon Via (TSV)-FinFET Noise Coupling in 3-D Integrated Circuits
A Universal Sequential Authentication Scheme for TAPC-Based Test Standards
Cost-Efficient SHA Hardware Accelerators
Low-Complexity Digit-Serial Multiplier Over $GF(2^{m})$ Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition
Power Optimized Transceivers for Future Switched Networks
Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding
A Low-Power 0.68-Gbps Data Communication System for Capacitive Digital Isolator With 1.9-ns Propagation Delay
A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops
Hardware Supported Task Scheduling on Dynamically Reconfigurable SoC Architectures
New degree computationless modified euclid algorithm and architecture for Reed-Solomon decoder
A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI)
Modeling of Energy Dissipation in RLC Current-Mode Signaling
PowerRush: An Efficient Simulator for Static Power Grid Analysis
Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics
Testing configurable LUT-based FPGA's
High-Utilization, High-Flexibility Depth-First CNN Coprocessor for Image Pixel Processing on FPGA
Highly Linear Low-Power Wireless RF Receiver for WSN
An Area-Efficient High-Resolution Segmented ΣΔ-DAC for Built-In Self-Test Applications
Reducing Power Dissipation in Memory Repair for High Fault Rates
The spring scheduling coprocessor: a scheduling accelerator
A Compound Timing Detection of Both Data Transition and Path Activation for Reliable In Situ Error Detection and Correction
A Scalable and Efficient Architecture for Binary Polynomial Multiplication in BIKE Utilizing Inter-/Inner-Wise Sparsity and Block-by-Block Pipeline
VLSI hardware for example-based learning
Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture
A Hybrid Scheme for On-Chip Voltage Regulation in System-On-a-Chip (SOC)
A Novel Time-Shared and LUT-Less Pipelined Architecture for LMS Adaptive Filter
A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering
Test data compression and test time reduction using an embedded microprocessor
A Low-Power Co-Processor to Predict Ventricular Arrhythmia for Wearable Healthcare Devices
Streaming Elements for FPGA Signal and Image Processing Accelerators
SoCCom: Automated Synthesis of System-on-Chip Architectures
Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices
An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs
A Process-Independent and Highly Linear DCO for Crowded Heterogeneous IoT Devices in 65-nm CMOS
An Embedded Architecture for DDR5 DFE Calibration Based on Channel Stimulus Inversion
Efficient shield insertion for inductive noise reduction in nanometer technologies
Improved Trace Buffer Observation via Selective Data Capture Using 2-D Compaction for Post-Silicon Debug
Guest Editorial Special Section on Design Verification and Validation
Modeling of Distributed RLC Interconnect and Transmission Line via Closed Forms and Recursive Algorithms
Applying Thermal Side-Channel Attacks on Asymmetric Cryptography
A Tri-Mode Reconfigurable Receiver for GNSS/NB-IoT/BLE With 68-dB HR3 and 60-dB IMRR in 28-nm CMOS
Power Efficient Class AB Op-Amps With High and Symmetrical Slew Rate
Enabling Dynamic Communication for Runtime Circuit Relocation
Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders
Understanding the Impact of Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations
pMOS Pass Gate Local Bitline SRAM Architecture With Virtual $V_{\mathrm{SS}}$ for Near-Threshold Operation
COBRA: a 100-MOPS single-chip programmable and expandable FFT
A Low Cost Calibrated DAC for High-Resolution Video Display System
Equivalent circuit model of on-wafer CMOS interconnects for RFICs
ICS: Interrupt-Based Channel Sneaking for Maximally Exploiting Die-Level Parallelism of NAND Flash-Based Storage Devices
Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips
Quasi-Adiabatic Clock Networks in 3-D Voltage Stacked Systems
Design of Nonvolatile and Multinode-Upset Recoverable Latches Based on Magnetic Tunnel Junction and CMOS
An 80× Analog-Implemented Time-Difference Amplifier for Delay-Line-Based Coarse-Fine Time-to-Digital Converters in 0.18-µm CMOS
Analysis and Optimization of Multisection Capacitive DACs for Mixed-Signal Processing
RegularRoute: An Efficient Detailed Router Applying Regular Routing Patterns
The Reconfigurable Instruction Cell Array
A Self-Calibration Method of a Pipeline ADC Based on Dynamic Capacitance Allotment
Implementation of Subthreshold Adiabatic Logic for Ultralow-Power Application
Deep Learning-Based Performance Testing for Analog Integrated Circuits
A 0.97 nJ/Conversion BJT-Based Temperature Sensor With a Low-Power Two-Stage Dynamic Comparator
Coordinating Binary Trait: Accurate and Lightweight Runtime On-Chip Power Meter Design
Automatic synthesis of FPGA channel architecture for routability and performance
Input Offset Estimation of CMOS Integrated Circuits in Weak Inversion
Discrete-time battery models for system-level low-power design
Guest editorial special issue on system synthesis
A BIRA for Memories With an Optimal Repair Rate Using Spare Memories for Area Reduction
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping
Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes
Hybrid Approximate Multipliers With Merits Balance for Digital Processing and Neural Networks
A compact physical via blockage model
The Low Area Probing Detector as a Countermeasure Against Invasive Attacks
Design and Analysis of High-Throughput Lossless Image Compression Engine Using VLSI-Oriented FELICS Algorithm
FA-STAC: An Algorithmic Framework for Fast and Accurate Coupling Aware Static Timing Analysis
Automatic Code Converter Enhanced PCH Framework for SoC Trust Verification
A Parameterized Programmable MIMO Decoding Architecture With a Scalable Instruction Set and Compiler
Interconnect accelerating techniques for sub-100-nm gigascale systems
High Performance and Area Efficient Flexible DSP Datapath Synthesis
Parallel VLSI design for a real-time video-impulse noise-reduction processor
An Interpolation-Free Fractional Motion Estimation Algorithm and Hardware Implementation for VVC
Embedded Deterministic Test Points
Reusing Trace Buffers as Victim Caches
10T SRAM Using Half-V DD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage
SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator
Concept, Design, and Implementation of Reconfigurable CORDIC
Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication Networks
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow
Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code
An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates
Dual-Layer Adaptive Error Control for Network-on-Chip Links
Performance-driven MCM partitioning through an adaptive genetic algorithm
Concurrent Path Selection Algorithm in Statistical Timing Analysis
Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
Taming Process Variations in CNFET for Efficient Last-Level Cache Design
Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations
Sharing of Compressed Tests Among Logic Blocks
Architectural power analysis: The dual bit type method
Dual-Level Adaptive Supply Voltage System for Variation Resilience
Fast Estimation of Timing Yield Bounds for Process Variations
Stateful Memristor-Based Search Architecture
Design for Testability of Sleep Convention Logic
Total Jitter of Delay-Locked Loops Due to Four Main Jitter Sources
Low Overhead Warning Flip-Flop Based on Charge Sharing for Timing Slack Monitoring
A Time-Domain Integration Comparison Scheme With Noise Immunity for Wake-Up Receivers
Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC
Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs
Through-Silicon Via-Based Capacitor and Its Application in LDO Regulator Design
3-D Digital Compute-in-Memory Benchmark With A5 CFET Technology: An Extension to Lookup-Table-Based Design
Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function
A 140 Mb/s to 1.96 Gb/s Referenceless Transceiver With 7.2 µs Frequency Acquisition Time
Low-Power Redundant-Transition-Free TSPC Dual-Edge-Triggering Flip-Flop Using Single-Transistor-Clocked Buffer
A Fast Heuristic Algorithm for Multidomain Clock Skew Scheduling
Scalable All-Analog LDOs With Reduced Input Offset Variability Using Digital Synthesis Flow in 65-nm CMOS
Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization
Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator
Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison
Bitline-Paired 2T SOT-MRAM Cell for Energy-Efficient Memory Operation
A Failure Prediction Strategy for Transistor Aging
Vibration Energy Scavenging System With Maximum Power Tracking for Micropower Applications
Crosstalk-Computing-Based Gate-Level Reconfigurable Circuits
A 0.9-V 33.7-ppm/°C 85-nW Sub-Bandgap Voltage Reference Consisting of Subthreshold MOSFETs and Single BJT
Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory
Timing Jitter Distribution and Power Spectral Density of a Second-Order Bang-Bang Digital PLL With Transport Delay Using Fokker-Planck Equations
Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming
A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata
Guest Editorial Memristive-Device-Based Computing
Speculative Lookahead for Energy-Efficient Microprocessors
Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices
A Global Bayesian Optimization Algorithm and Its Application to Integrated System Design
A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration
Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems
Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic
AVPGEN-A test generator for architecture verification
An Efficient Scaling-Free Folded Hyperbolic CORDIC Design Using a Novel Low-Complexity Power-of-2 Taylor Series Approximation
Statistical Leakage Estimation of Double Gate FinFET Devices Considering the Width Quantization Property
Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design
Impedance characteristics of power distribution grids in nanoscale integrated circuits
Power Delivery for Multicore Systems
Eleven Ways to Boost Your Synchronizer
Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs)
An Adaptive and Universal Timing Mismatch Estimation Method for TIADCs
Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization
From application descriptions to hardware in seconds: a logic-based approach to bridging the gap
High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding
Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow
A 1 mW-10 W, Over 86.4% Efficiency Tri-Mode Buck Converter With Ripple-Based Control for Mobile Applications
A Fully On-Chip PT-Invariant Transconductor
GH CORDIC-Based Architecture for Computing $N$ th Root of Single-Precision Floating-Point Number
Analytic termination metrics for pin-to-pin lossy transmission lines with nonlinear drivers
Multi-FPGA System With Unlimited and Self-Timed Wave-Pipelined Multiplexed Routing
High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques
Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors
Three-Dimensional Pipeline ADC Utilizing TSV/ Design Optimization and Memristor Ratioed Logic
Automatic Mode-Selected Energy Harvesting Interface With >80% Power Efficiency Over 200 nW to 10 mW
DLS: dynamic backlight luminance scaling of liquid crystal display
CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency
Compact Degradation Sensors for Monitoring NBTI and Oxide Degradation
Techniques for Improved Continuous and Discrete Tuning Range in Millimeter-Wave VCOs
Ant colony system application to macrocell overlap removal
Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays
Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits
Memristors Enabled Computing Correlation Parameter In-Memory System: A Potential Alternative to Von Neumann Architecture
Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology
Low-Overhead Triple-Node-Upset-Tolerant Latch Design in 28-nm CMOS
Thirty Two-Stage CMOS TDI Image Sensor With On-Chip Analog Accumulator
Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test
High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2 m )
Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor
A High-Speed Floating-Point Multiply-Accumulator Based on FPGAs
Runtime Leakage Minimization Through Probability-Aware Optimization
An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs
A Code Inversion Encoding Technique to Improve Read Margin of A Cross-Point Phase Change Memory
An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement
A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning
An asynchronous architecture for modeling intersegmental neural communication
Study of Injection Pulling of Oscillators in Phase-Locked Loops
A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM
Return Data Interleaving for Multi-Channel Embedded CMPs Systems
Current-Mode Synthetic Control Technique for High-Efficiency DC-DC Boost Converters Over a Wide Load Range
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay
Soft-Error-Immune Quadruple-Node-Upset Tolerant Latch Based on Polarity Design and Source-Isolation Technologies
Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields
A Training-Efficient Hybrid-Structured Deep Neural Network With Reconfigurable Memristive Synapses
Test Path Selection for Capturing Delay Failures Under Statistical Timing Model
Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors
Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under Process Variations
TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems
Scalable Packet Classification on FPGA
An Efficient Multimode Multiplier Supporting AES and Fundamental Operations of Public-Key Cryptosystems
Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise
Xpikeformer: Hybrid Analog-Digital Hardware Acceleration for Spiking Transformers
A Miniaturized Wideband Interdigital Bandpass Filter With High Out-Band Suppression Based on TSV Technology for W-Band Application
Compiler-Guided Parallelism Adaption Based on Application Partition for Power-Gated ILP Processor
Architectural Enhancement and System Software Support for Program Code Integrity Monitoring in Application-Specific Instruction-Set Processors
Performance and Energy Studies on NC-FinFET Cache-Based Systems With FN-McPAT
Padding of Multicycle Broadside and Skewed-Load Tests
Hierarchical finite-state machines and their use for digital control
A formal approach to context scheduling for multicontext reconfigurable architectures
Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines
T-VEMA: A Temperature- and Variation-Aware Electromigration Power Grid Analysis Tool
Area-time-power tradeoff in cellular arrays VLSI implementations
A Hierarchical Self-Repairing Architecture for Fast Fault Recovery of Digital Systems Inspired From Paralogous Gene Regulatory Circuits
Corrections Corrections to "A Wideband Blocker-Tolerant Receiver With Frequency-Translational Resistive Feedback"
A MIMD-based video signal processing architecture suitable for large area integration and a 16.6-cm 2 monolithic implementation
Testing Comparison and Delay Faults of TCAMs With Asymmetric Cells
Function-based compact test pattern generation for path delay faults
Signal Acquisition of High-Speed Periodic Signals Using Incoherent Sub-Sampling and Back-End Signal Reconstruction Algorithms
Energy-Efficient Digital Signal Processing via Voltage-Overscaling-Based Residue Number System
A Scalable High-Voltage Output Driver for Low-Voltage CMOS Technologies
A High-Performance SCNN Accelerator Using Parallel Sparsity Detection and Index-Oriented Computation Workflow
On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors
Efficient Statistical Timing Analysis Using Deterministic Cell Delay Models
Optimal Periodic Memory Allocation for Image Processing With Multiple Windows
Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers
A physical design tool for built-in self-repairable RAMs
A Hybrid Miller-Cascode Compensation for Fast Settling in Two-Stage Operational Amplifiers
Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor
PMOS-Only Sleep Switch Dual-Threshold Voltage Domino Logic in Sub-65-nm CMOS Technologies
Synthesis of application-specific memory designs
RosebudVirt: A High-Performance and Partially Reconfigurable FPGA Virtualization Framework for Multitenant Networks
A Low Complexity Online Learning Approximate Message Passing Detector for Massive MIMO
High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed-Solomon Codes