yusuke1997/dblp-id-title huggingface dataset:
Efficient and provably secure privacy-preserving two-factor authentication and key-agreement using blockchain and TEE for IoV environments
ORQ-ViT: Outlier resilient Post Training Quantization for vision transformers via outlier decomposition
Introduction to the special issues on embedded systems in applied computing
A scalable factory backbone for multiple independent time-sensitive networks
An experiment on PC-based automated extraction of electrical parameters for VLSI MOSFETs: Methods, algorithms, and implementation
Evaluating the impact of proactivity in the user experience of a context-aware restaurant recommender for Android smartphones
Balanced dual-stage repair for dependable embedded memory cores
A unified proof technique for verifying program correctness with big-step semantics
Efficient secure channel free identity-based searchable encryption schemes with privacy preserving for cloud storage service
Fault diagnosis for the generalized Boolean n-cube network
Algorithms for real-time scheduling of error-cumulative tasks based on the imprecise computation approach
Accelerating genetic algorithm computation in tree shaped parallel computer
LAKAF: Lightweight authentication and key agreement framework for smart grid network
Labeled rough partitions - a new general purpose representation for multiple-valued functions and relations
High level synthesis through folding of data flow graphs: Optimal intra-node scheduling
Datacenter optimization methods for Softwarized Network Services
An enhanced planned obsolescence attack by aging networks-on-chip
Leaf: An open-source cybersecurity training platform for realistic edge-IoT scenarios
Non-Volatile memory (NVM) technologies
Implementing a replicated service with group communication
Online stereo camera calibration for automotive vision based on HW-accelerated A-KAZE-feature extraction
High performance computing on networks of workstations through the exploitation of function parallelism
On guaranteeing hard real-time tasks
A lightweight verifiable trust based data collection approach for sensor-cloud systems
Priority-driven spatial resource sharing scheduling for embedded graphics processing units
Forward and backward secure updatable ElGamal encryption scheme for cloud storage
Session B: Signal - II
Exploring the performance of split data cache schemes on superscalar processors and symmetric multiprocessors
A public key encryption scheme based on a new variant of LWE with small cipher size
Debugging and monitoring highly parallel systems with grip
Remotely reconfigurable hardware-software platform with web service interface for automated video surveillance
Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip
REC: Enhancing fine-grained cache coherence protocol in multi-GPU systems
Resource allocation robustness in multi-core embedded systems with inaccurate information
Efficient parallel implementation of the hough transform on a distributed memory system
Guest editorial: Special issue on edge computing optimization and security
Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints
Exploration of trade-offs in the design of volatile STT-RAM cache
I2CSec: A secure serial Chip-to-Chip communication protocol
Modelling of digital circuits function and functional faults on register transfer level
ECG heartbeat classification in compressive domain for wearable devices
Security architecture for virtual organizations of business web services
Hardware/software support for adaptive work-stealing in on-chip multiprocessor
A design scheme for a reconfigurable accelerator implemented by single-flux quantum circuits
Measuring parallelism in algorithms
Virtual prototyping of PLC-based embedded system using object model of target and behavior model by converting RLL-to-statechart directly
On the design of IP routers Part 1: Router architectures
Synthesis of minimal multivalued decision diagrams
BANSIM: A new discrete-event simulator for wireless body area networks with deep reinforcement learning in Python
Heuristic task scheduling on heterogeneous UAVs: A combinatorial optimization approach
Low power data processing system with self-reconfigurable architecture
Concurrent, object-oriented program design in real-time systems
CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications
Virtualizing ARM VFP (Vector Floating-Point) with Xen-ARM
Object-oriented versus conventional software development: A comparative case study
PaLLOC: Pairwise-based low-latency online coordinated resource manager of last-level cache and memory bandwidth on multicore systems
Managing non-invasive measurement tools
Diprotalk: A tool for object-oriented design of distributed applications
At-scale evaluation of weight clustering to enable energy-efficient object detection
A combined fuzzy and classical PID controller
A parallel algorithm for constructing reduced visibility graph and its FPGA implementation
New response time analysis for global EDF on a multiprocessor platform
Analyzing the performance of persistent storage for fault-tolerant stateful fog applications
A multiprocessor architecture and its application to adaptive control
A data driven multiprocessor - Its architecture and performance evaluation
A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations
DDC: Delta driven computer, and μSyC: microprogrammable symbolic coprocessor
MIFS: A low overhead and efficient mixture file index management method in flash file system
A secure digital camera architecture for integrated real-time digital rights management
Distributed debugging: Network analysis tools
Reliability and test effort analysis of multi-sensor driver assistance systems
A new microarchitecture based on a RISC like structure but with a CISC like instruction set
CSL: A class specification language for object-oriented design
Efficient one-to-one sharing: Public key matchmaking encryption
Improved composite confidence mechanisms for a perceptron branch predictor
Parallel programming on a PC - a case study
A hierarchical architecture for time- and event-triggered real-time systems
A write-optimal and concurrent persistent dynamic hashing with radix tree assistance
Architecting reconfigurable component-based operating systems
Denial-of-Service attacks on PCI passthrough devices: Demonstrating the impact on network- and storage-I/O performance
A review of priority assignment in real-time systems
Modelling dynamic dependencies by functional database model
Efficient holistic timing analysis with low pessimism for rate-constrained traffic in TTEthernet
A microprocessor-based scheme for deriving sampling frequency
Software methodologies in VHDL code analysis
Session H4: Applications: Education II
Model-driven development for the seL4 microkernel using the HAMR framework
Letter from the editors-in-chief
Intrusion detection based on improved density peak clustering for imbalanced data on sensor-cloud systems
Incorporating job sizes in distributed load balancing
Microcomputer unit for control of distributed devices over computer networks
Storage capacity for EDF-ASAP algorithm in energy-harvesting systems with periodic implicit deadline hard real-time tasks
Role-based access control in DCOM
PROLOG as a formalism for VLSI design specification
Generalized and Scalable Offset-Based Response Time Analysis of Fixed Priority Systems
Controller network development - but how?!
Real-time systems education in computer science at Manchester University
OC-FP, An applicative language combination with occam and the algebra of processes
Design of a kernel for implementing communication protocols
Verifying security properties of internet protocol stacks: The split verification approach
Heuristic and neural algorithms for mapping tasks to a reconfigurable array
FPGA-based CNN accelerator using Convolutional Processing Element to reduce idle states
Designing efficient irregular networks for heterogeneous systems-on-chip
Efficient maximum reaction time analysis for data chains of real-time tasks in multiprocessor systems
Stripped mirroring RAID architecture
Definition and evaluation of a transputer-based architecture for image compression and reconstruction
Area-performance trade-off in floorplan generation of Application-Specific Network-on-Chip with soft cores
Configware and morphware going mainstream
Mapping iterative algorithims on regular processor arrays without using uniform recurrent equations
Global optimisation of fault-tolerant allocation of concurrent communicating processes in distributed environments
Hardware features of the static communication network of a parallel architecture
Transition-aware DVS algorithm for real-time systems using tree structure analysis
Temporal logic issues in music knowledge representation
Traffic analysis in a double grain Dataflow array processor
A multilevel hardware description language
Formalizing the design-trajectory of sequential machines
Platform synthesis and partitioning of real-time tasks for energy efficiency
TaintGuard: Preventing implicit privilege leakage in smart contract based on taint tracking at abstract syntax tree level
A non-invasive approach to product metrics collection
From transformations to methodology in parallel program development: A case study
Global EDF-based scheduling with laxity-driven priority promotion
Toward Linux-based safety-critical systems - Execution time variability analysis of Linux system calls
Support environment for the development of problem oriented concurrent systems
Deferred locking with shadow transaction for client-server DBMSs
SW/HW-partitioning of real-time embedded systems
Distributed computing using Java: A comparison of two server designs
Guiding assurance of architectural design patterns for critical applications
Notes on implementing a language for transputer networks
Future architecture of high performance workstations
A Survey and Taxonomy of FPGA-based Deep Learning Accelerators
The egoistic approach to parallel process migration into heterogeneous workstation network
An authenticated key agreement method for secure big data analytics in next-generation wireless networks-enabled smart farming
From systems to networks on chip: A promising research area in the Hardware/Software co-design
HashC: Making deep learning coverage testing finer and faster
A cascade implementation of digital systems
A new approach to the Population-Based Incremental Learning algorithm using virtual regions for task mapping on NoCs
Optimized implementation of synchronous models on industrial LTTA systems
VHDL/S - integrating statecharts, timing diagrams, and VHDL
C2QoS: Network QoS guarantee in vSwitch through CPU-cycle management
A compiler assisted wear leveling for morphable PCM in embedded systems
Translation of a query in OODBMS into a system of parallel tasks
Hierarchical adaptive Multi-objective resource management for many-core systems
An explicitly declared delayed-branch mechanism for a superscalar architecture
A Unix distributed application support suitable for mini and microcomputer based systems
EC-BAAS: Elliptic curve-based batch anonymous authentication scheme for Internet of Vehicles
An efficient and secure certificateless aggregate signature scheme
A review of sensory interactions between autonomous vehicles and drivers
SPMAC: Secure and privacy-preserving multi-authority access control for fog-enabled IoT cloud storage
TBVPAKE: An efficient and provably secure verifier-based PAKE protocol for IoT applications
An efficient task mapping algorithm with power-aware optimization for network on chip
Performance evaluation of hypermeshes and meshes with wormhole routing
Towards accuracy of role-based access control configurations in component-based systems
Session H3: Testing methods
Energy efficient path selection scheme for OFDMA-based two-hop cellular systems
Transformational design of digital circuits
Smart search space reduction for approximate computing: A low energy HEVC encoder case study
A CATV based metropolitan area network using distributed switching
Threaded prefetching: An adaptive instruction prefetch mechanism
G-NMP: Accelerating Graph Neural Networks with DIMM-based Near-Memory Processing
Towards a parallel inference machine: the APIM project
Issues in the implementation of Prolog, and their optimization
Models of computation for parallel discrete event simulation
Caiti: I/O transit caching for persistent memory-based block device
Using a serial cache for energy efficient instruction fetching
Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes
Connected component labeling for binary images on a reconfigurable mesh architecture
A systolic array exploiting the inherent parallelisms of artificial neural networks
Partition window assignment in hierarchically scheduled time-partitioned distributed real-time systems with multipath flows
Leaking your engine speed by spectrum analysis of real-Time scheduling sequences
Multiple precision square root using the Dwandwa square-root algorithm
Model checking of MARTE/CCSL time behaviors using timed I/O automata
Application of system semantics to VLSI for the transformational design of a parameterized booth multiplier module - a case study
A deadlock-free communication kernel for loop connected message passing computer architecture
Design techniques for low-power systems
Scalable hardware implementing high-radix Montgomery multiplication algorithm
An efficient architecture for designing reverse converters based on a general three-moduli set
A methodology for performance/energy consumption characterization and modeling of video decoding on heterogeneous SoC and its applications
A performance analysis of toroidal mesh networks
Session A4: Object orientied VLSI design
Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems
A new self-diagnosing approach based on petri nets and correlation graphs for fault management in wireless sensor networks
An operating system accelerator
Parallel algorithm for MSE estimation of 2-D noncasual image models
Efficient schedulability analysis of hierarchical EDF scheduling with resource sharing
JDap: Supporting in-memory data persistence in javascript using Intel's PMDK
An efficient, parallel-symmetric thinning algorithm and its hardware implementation
Challenges in real-time virtualization and predictable cloud computing
CMOS fault modeling, test generation and design for testability
A comprehensive reconfigurable computing approach to memory wall problem of large graph computation
Low power architectures for digital signal processing
Syntactic and semantic aspects of formal system description
Actors: A unifying model for parallel and distributed computing
Dynamic task mapping for Network-on-Chip based systems
A high level synthesis algorithm including control constraints
On the performance of distributed objects
An asynchronous checkpointing service
Modular architecture for custom-built systems oriented to real-time computer vision: Application to color recognition
Certificateless public auditing scheme with sensitive information hiding for data sharing in cloud storage
Session K2: Keynote session
Distributed intelligence and bus hierarchy system implementation for a highly intelligent workstation
An efficient static gesture recognizer embedded system based on ELM pattern recognition algorithm
An analytical model for hypercubes in the presence of multiple time-scale bursty traffic
A scalable single-chip multi-processor architecture with on-chip RTOS kernel
A survey of accelerator architectures for 3D convolution neural networks
On synthesizing cube and tree for parallel processing
Reverse serializability as a correctness criterion for optimistic concurrency control
Access control based privacy preserving secure data sharing with hidden access policies in cloud
Partitioned scheduling with safety-performance trade-offs in stochastic conditional DAG models
A preliminary evaluation of a massively parallel processor: GAPP
Wireless edge caching based on content similarity in dynamic environments
An investigation of binary CLA and ripple CMOS adder designs
Taking a closer look at memory interference effects in commercial-off-the-shelf multicore SoCs
Random number generation on microcomputers - State of the art
Efficiency analysis of artificial vs. Spiking Neural Networks on FPGAs
Microelectronics: Fault tolerance and reliability
A framework for static analysis and verification of low-level RTOS code
CRPIM: An efficient compute-reuse scheme for ReRAM-based Processing-in-Memory DNN accelerators
Linked or unlinked: A systematic review of linkable ring signature schemes
Guest editorial: Special issue on next generation AI approaches for intelligent internet of things
Session F3: System design
An anonymous and large-universe data-sharing scheme with traceability for medical cloud storage
Mixing floating- and fixed-point formats for neural network learning on neuroprocessors
Reducing tail latency with coding-based packet spraying in edge datacenters
Pattern recognition with fuzzy neural network
FLUX interconnection networks on demand
Fault tolerant aspects of a dynamic dataflow architecture - PATTSY
Fault-tolerant solutions for complex-numbers multipliers
Large scale wireless sensor networks with multi-level dynamic key management scheme
FPGA emulation methodology for fast and accurate power estimation of embedded processors
A hypermedia data model for public space and computer aided learning
Privacy-preserving multi-party deep learning based on homomorphic proxy re-encryption
SUPPLE: An efficient run-time support for non-uniform parallel loops
Processor array architectures for flexible approximate string matching
A software system for the generation of test data for Ada programs
Fault-tolerant real-time tasks scheduling with dynamic fault handling
From UML specifications to mapping and scheduling of tasks into a NoC, with reliability considerations
RISC: A resilient interconnection network for scalable cluster storage systems
Context-aware service roaming for heterogeneous embedded devices over cloud
Ster's multilevel programming model for distributed hard real-time systems
A survey and taxonomy of consensus protocols for blockchains
An agent based platform for task distribution in virtual environments
A regular interconnection network
A survey of FPGA and ASIC designs for transformer inference acceleration and optimization
A multi-queue TCP window control scheme with dynamic buffer allocation
Optimal load distribution in nondedicated heterogeneous cluster and grid computing environments
Improving cache performance with Full-Map Block Directory
Memory-efficient deep learning inference with incremental weight loading and data layout reorganization on edge systems
Reduction of task migrations and preemptions in optimal real-time scheduling for multiprocessors by using dynamic T-L plane
Fortport: An environment for the development of parallel fortran programs
A distributed bandwidth allocation algorithm for Gbit/s LANs
Corrigendum: Correction of Acknowledgment: An improved mechanism for flow rule installation in In-band SDN [Journal of Systems Architecture 96 (2019) 1-19]
Developing a reusable workflow engine
Design and implementation of a distributed real-time expert-system for fault diagnosis in modular manufacturing systems
Optimal placement of vertical connections in 3D Network-on-Chip
An ISDN primary rate interface for ethernet access
Doppel: A BFT consensus algorithm for cyber-physical systems with low latency
Let's design asynchronous VLSI systems
Interfacing the hardware API with a feature-based operating system family
The provision of flexibility in hiercrchical control systems
Iiistological image understanding by error backpropagation
Comments on "Sign detection in residue arithmetic units" [Journal of Systems Architecture 45 (1998) 251-258]
A novel hardware-oriented Kohonen SOM image compression algorithm and its FPGA implementation
Design of a DSP-based discrete variable structure controller with improved robustness
Retraction notice to ''Specification and Verification of Dynamic Evolution of Software Architectures" [SYSARC 56 (10) (2010) 523-533]
A data driven hybrid computer architecture
DFG: a graph based approach for algorithmic flow driven architecture synthesis
Real-time and distributed computing in emerging applications. Foreword by the general chairs of Reaction 2012
A survey on security and authentication in wireless body area networks
Experiment and enabled flow for GPGPU-Sim simulators with fixed-point instructions
A scheme for designing fault-tolerant microprogrammed processors using bit-slice chips
End-to-end timing analysis of cause-effect chains in automotive embedded systems
An object oriented logic simulator
Energy minimization for reliability-guaranteed real-time applications using DVFS and checkpointing techniques
Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits
SEDCPT: A secure and efficient Dynamic Searchable Encryption scheme with cluster padding assisted by TEE
Optimal bandwidth allocation and stability of high-speed networks for CSMA/CD protocols
Register allocation for write activity minimization on non-volatile main memory for embedded systems
A comparison of frameworks for cooperation is distributed image registration systems
A privilege-constrained sanitizable signature scheme for e-health systems
Siamese Transformer Network: Building an autonomous real-time target tracking system for UAV
Task to task communication and resource sharing in a geographically distributed network
Accelerating on-device visual task adaptation by exploiting hybrid sparsity in DNN training
Structure of a parallelizing compiler for the B-HIVE multicomputer
Public-key authenticated encryption with keyword search achieving both multi-ciphertext and multi-trapdoor indistinguishability
Combining mapping and partitioning exploration for NoC-based embedded systems
A unified link-layer fault-tolerant architecture for network-based many-core embedded systems
An improved algorithm for protocol validation by extended circular exploration
From image coding to multimedia: Algorithms and architectures for a revolution
Enhancing blockchain-based filtration mechanism via IPFS for collaborative intrusion detection in IoT networks
RDMA control support for fine-grain parallel computations
High level Petri net modelling and analysis of VME-based multiprocessors
Tuning the victim selection policy of Intel TBB
Joint task offloading and resource optimization in NOMA-based vehicular edge computing: A game-theoretic DRL approach
Speech recognizer optimization and real-time implementation on a multitransputer array
Fault behavior and testability of asynchronous CMOS circuits
MAP: Design and implementation of a mobile agents' platform
Short notes I
Special-issue on reconfigurable systems
Set associative address mapping to improve data throughput and reduce tail latency in SSDs
Efficient FPGA hardware development: A multi-language approach
GM-C: A graph multi-combinator machine
CuSora: Real-time software radio using multi-core graphics processing unit
Approaching encryption at ISDN speed using partial parallel modulus multiplication
A reconfigurable platform for evaluating the performance of QoS networks
Design of a high reliability self diagnosing computer using bit slice microprocessors
Energy-aware scheduling for dependent tasks in heterogeneous multiprocessor systems
A low-cost fault tolerant solution targeting commercial FPGA devices
An optimal allocation of memory buffers for complex multicore platforms
A trustworthy, fault-tolerant and scalable self-configuration algorithm for Organic Computing systems
An extended scheduling technique for software pipelining
Accurate extraction of interconnect capacitances by adaptive mixed F.E.M
The architecture of response-pipelined content addressable memories
Task scheduling with precedence and placement constraints for resource utilization improvement in multi-user MEC environment
A high-performance dataflow-centric optimization framework for deep learning inference on the edge