yusuke1997/dblp-id-title huggingface dataset:
Split-level precharge differential logic: a new type of high-speed charge-recycling differential logic
A double-level-V th select gate array architecture for multilevel NAND flash memories
Circuit and architecture trade-offs for high-speed multiplication
A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design
A voltage-controllable linear MOS transconductor using bias offset technique
Programmable switched-current wave analog filters
Josephson macrocell array
64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency
A 16-nm Always-On DNN Processor With Adaptive Clocking and Multi-Cycle Banked SRAMs
A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation
Low-phase-noise LC quadrature VCO using coupled tank resonators in a ring structure
A 286 MHz 64-b floating point multiplier with enhanced CG operation
A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology
A CMOS motion detector system for pointing devices
A 6-b, 4 GSa/s GaAs HBT ADC
A Nyquist-rate pipelined oversampling A/D converter
A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology
A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues
A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology
A 192-pW Voltage Reference Generating Bandgap- $V_{\text{th}}$ With Process and Temperature Dependence Compensation
A Modular Switched-Capacitor Chip-Stacking Drive Platform for kV-Level Electrostatic Actuators
An 8-16 Gb/s, 0.65-1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning
A high-frequency fifth order switched-current bilinear elliptic lowpass filter
High-Linearity Bottom-Plate Mixing Technique With Switch Sharing for N-path Filters/Mixers
Hybrid Temperature Sensor Network for Area-Efficient On-Chip Thermal Map Sensing
On-chip measurement of the jitter transfer function of charge-pump phase-locked loops
Design of Wide Tuning-Range CMOS VCOs Using Switched Coupled-Inductors
A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems
Low-voltage, low-power BiCMOS digital circuits
A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors
A 6.75 ns 16*16 bit multiplier in single-level-metal CMOS technology
A High-Speed Current-Mode Data Driver With Push-Pull Transient Current Feedforward for Full-HD AMOLED Displays
Comments on "Design issues in CMOS differential LC oscillators" [and reply]
A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS
A 900 MHz UHF RFID Reader Transceiver IC
CMOS Biosensor IC Focusing on Dielectric Relaxations of Biological Water With 120 and 60 GHz Oscillator Arrays
DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell
A 0.5-9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling
A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI
A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry
Design of Low-Voltage Highly Linear Switched-R-MOSFET-C Filters
The modeling, characterization, and design of monolithic inductors for silicon RF IC's
Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)
Design and Analysis of a 22.6-to-73.9 GHz Low-Noise Amplifier for 5G NR FR2 and NR-U Multiband/Multistandard Communications
Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density
A Third-Order DT ΔΣ Modulator Using Noise-Shaped Bi-Directional Single-Slope Quantizer
A 3.5 GHz Spread-Spectrum Clock Generator With a Memoryless Newton-Raphson Modulation Profile
A Reference-Free Capacitive-Discharging Oscillator Architecture Consuming 44.4 pW/75.6 nW at 2.8 Hz/6.4 kHz
A low-noise CMOS instrumentation amplifier for thermoelectric infrared detectors
Bitline GND sensing technique for low-voltage operation FeRAM
Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration
Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter
A dual high-current high-voltage driver
A 10-b 20-MS/s SAR ADC With DAC-Compensated Discrete-Time Reference Driver
A 3.3-Gb/s SPAD-Based Quantum Random Number Generator
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture
A 12.5-mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback
A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion
CMOS nonthreshold logic (NTL) and cascode nonthreshold logic (CNTL) for high-speed applications
A 134×132 4-Tap CMOS Indirect Time-of-Flight Range Imager Using In-Pixel Memory Array With 10 Kfps High-Speed Mode and High Precision Mode
New three-dimensional memory array architecture for future ultrahigh-density DRAM
A 1.9-GHz, 1-W CMOS class-E power amplifier for wireless communications
A fault-tolerant GaAs/CMOS interconnection network for scalable multiprocessors
CMOS SPAD Line Sensor With Fine-Tunable Parallel Connected Time-to-Digital Converters for Raman Spectroscopy
Introduction to the Special Issue on the 2017 Symposium on VLSI Circuits
A Low-Power, Low-EVM, SAW-Less WCDMA Transmitter Using Direct Quadrature Voltage Modulation
A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector
A 63% Efficiency 1.29-W Single-Link Multiple-Output (SLiMO) Isolated DC-DC Converter Using FPC Micro-Transformer With Local Voltage and Global Power Regulations
An IC for linearizing RF power amplifiers using envelope elimination and restoration
A parallel processing chip with embedded DRAM macros
A programmable 1.5 V CMOS class-AB operational amplifier with hybrid nested Miller compensation for 120 dB gain and 6 MHz UGF
A CMOS 1 Gb/s 5-Tap Fractionally-Spaced Equalizer
A 14 nm FinFET 128 Mb SRAM With V MIN Enhancement Techniques for Low-Power Applications
A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor
Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices
A data-transition look-ahead DFF circuit for statistical reduction in power consumption
A 15.2-ENOB 5-kHz BW 4.5-µW Chopped CT ΔΣ-ADC for Artifact-Tolerant Neural Recording Front Ends
An analytical access time model for on-chip cache memories
A 90-nm CMOS Threshold-Compensated RF Energy Harvester
A CMOS power amplifier with a novel output structure
Degradation-Resilient Design of a Self-Healing xDSL Line Driver in 90 nm CMOS
Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks
More on the$1/{\rm f}^{2}$Phase Noise Performance of CMOS Differential-PairLC-Tank Oscillators
A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM
A new resonant-tunnel diode-based multivalued memory circuit using a MESFET depletion load
A 140-Mb/s, 32-state, radix-4 Viterbi decoder
Wideband 2 to 6 GHz RF Front-End With Blocker Filtering
A 7.5-Gb/s One-Tap-FFE Transmitter With Adaptive Far-End Crosstalk Cancellation Using Duty Cycle Detection
Study of substrate noise and techniques for minimization
A Fully Integrated Wideband FM Transceiver for Low Data Rate Autonomous Systems
Smart-pixel cellular neural networks in analog current-mode CMOS technology
A Cryo-CMOS Wideband Quadrature Receiver With Frequency Synthesizer for Scalable Multiplexed Readout of Silicon Spin Qubits
A class-D vertical booster for CRT
A low-power 1 MHz, 25 mW 12-bit time-interleaved analog-to-digital converter
A 950-MHz rectifier circuit for sensor network tags with 10-m distance
A 300-MHz 115-W 32-b bipolar ECL microprocessor
"Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC
Testable design of BiCMOS circuits for stuck-open fault detection using single patterns
Concurrent Body-Coupled Powering and Communication ICs With a Single Electrode
A 375-mW Quadrature Bandpass$\Delta\Sigma$ADC With 8.5-MHz BW and 90-dB DR at 44 MHz
NeRF-Navi: An Energy-Efficient NeRF 3-D Path Planning Processor With Reconfigurable Approximate/Accurate Bit Offloading Core
Optimum degeneration for minimum mismatch in bipolar current sources
A 57 mW 12.5 µJ/Epoch Embedded Mixed-Mode Neuro-Fuzzy Processor for Mobile Real-Time Object Recognition
CIM-Spin: A Scalable CMOS Annealing Processor With Digital In-Memory Spin Operators and Register Spins for Combinatorial Optimization Problems
A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter
Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio
A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS
A Background Calibration Technique to Control the Bandwidth of Digital PLLs
Analysis, Modeling, and Design of a 2.45-GHz RF Energy Harvester for SWIPT IoT Smart Sensors
The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series
A 3.5-mV Input Single-Inductor Self-Starting Boost Converter With Loss-Aware MPPT for Efficient Autonomous Body-Heat Energy Harvesting
Two analog counters for neural network implementation
A Handheld High-Sensitivity Micro-NMR CMOS Platform With B-Field Stabilization for Multi-Type Biological/Chemical Assays
Monolithic transformers and their application in a differential CMOS RF low-noise amplifier
A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection
Correction to "A Sub- μ W Embedded CMOS Temperature Sensor for RFID Food Monitoring Application" [Jun 10 1246-1255]
Reconfigurable Receiver With Radio-Frequency Current-Mode Complex Signal Processing Supporting Carrier Aggregation
98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits
A Shoot-Through-Free 180-MHz Isolated Converter With PG-Downsized PA for Low EMI
A 209 K-transistor ECL gate array with RAM
A 13.2 b Optical Proximity Sensor System With 130 klx Ambient Light Rejection Capable of Heart Rate and Blood Oximetry Monitoring
A Local Random Variability Detector With Complete Digital On-Chip Measurement Circuitry
A high-frequency electronically tunable quadrature oscillator
A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter
Analog front end of an ECBM transceiver for ISDN
A 5.2 mW IEEE 802.15.6 HBC Standard Compatible Transceiver With Power Efficient Delay-Locked-Loop Based BPSK Demodulator
A 10-MHz Closed-Loop EMI-Regulated GaN Switching Power Converter Using Emulated Miller Plateau Tracking and Adaptive Strength Gate Driving
An analog beam-forming circuit for ultrasound imaging using switched-current delay lines
BiCMOS nonthreshold logic for high-speed low-power applications
A 300-MHz BiCMOS serial data transceiver
A fully asynchronous digital signal processor using self-timed circuits
A Wideband Low-Power Cryogenic CMOS Circulator for Quantum Applications
A 6.9-µm Pixel-Pitch Back-Illuminated Global Shutter CMOS Image Sensor With Pixel-Parallel 14-Bit Subthreshold ADC
Analysis and Design of a 2.9-mW 53.4-79.4-GHz Frequency-Tracking Injection-Locked Frequency Divider in 65-nm CMOS
Capacitorless Self-Clocked All-Digital Low-Dropout Regulator
A 91.15% Efficient 2.3-5-V Input 10-35-V Output Hybrid Boost Converter for LED-Driver Applications
Tunable high-frequency Gm-C filters
A 128 × 128 CMOS biosensor array for extracellular recording of neural activity
A 90 GHz Hybrid Switching Pulsed-Transmitter for Medical Imaging
Analysis and Design of a 54 GHz Distributed "Hybrid" Wave Oscillator Array With Quadrature Outputs
A Low-Power 2.4-GHz Current-Reused Receiver Front-End and Frequency Source for Wireless Sensor Network
A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design
EDITORIAL New Associate Editor
Introduction to the Special Bio-Section of the 2016 International Solid-State Circuits Conference (ISSCC)
The microarchitecture of the synergistic processor for a cell processor
A 19 dBm, 15 Gbaud, 9 bit SOI CMOS Power-DAC Cell for High-Order QAM W-Band Transmitters
A Batteryless Motion-Adaptive Heartbeat Detection System-on-Chip Powered by Human Body Heat
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment
Waveform degradation in VLSI interconnections
A Hybrid Switched-Capacitor Battery Management IC With Embedded Diagnostics for Series-Stacked Li-Ion Arrays
Digitally Assisted IIP2 Calibration for CMOS Direct-Conversion Receivers
A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter
Miniature 3-D inductors in standard CMOS process
A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter
A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad
A 98 mm 2 die size 3.3-V 64-Mb flash memory with FN-NOR type four-level cell
Race-free clocking of CMOS pipelines using a single global clock
A programmable analog neural network chip
Design of a neural-based A/D converter using modified Hopfield network
A 0.006 mm 2 1.2 µW Analog-to-Time Converter for Asynchronous Bio-Sensors
A 61-GHz SiGe Transceiver Frontend for Energy and Data Transmission of Passive RFID Single-Chip Tags With Integrated Antennas
A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator
A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35-μm CMOS
Design of fault-diagnosable and repairable folded PLAs for yield enhancement
Compact One-Transistor-N-RRAM Array Architecture for Advanced CMOS Technology
Low-Power Process and Temperature-Invariant Constant Slope-and-Swing Ramp-Based Phase Interpolator
Millimeter-wave low-noise and high-power metamorphic HEMT amplifiers and devices on GaAs substrates
A Micropower ΔΣ-Based Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer
CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation
A 65 nm General-Purpose Compute-in-Memory Processor Supporting Both General Programming and Deep Learning Tasks
Highly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End
Modular DR- and CMR-Boosted Artifact-Resilient EEG Headset With Distributed Pulse-Based Feature Extraction and Neuro-Inspired Boosted-SVM Classifier
Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS
A Si bipolar 21-GHz/320-mW static frequency divider
An Area-Efficient Microprocessor-Based SoC With an Instruction-Cache Transformable to an Ambient Temperature Sensor and a Physically Unclonable Function
A Low-Loss 50-70 GHz SPDT Switch in 90 nm CMOS
165-GHz Transceiver in SiGe Technology
A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates
Two mm-Wave Vector Modulator Active Phase Shifters With Novel IQ Generator in 28 nm FDSOI CMOS
A Q-Modulation Technique for Efficient Inductive Power Transmission
A 1.9-mW SVM Processor With On-Chip Active Learning for Epileptic Seizure Control
A Large Swing, 40-Gb/s SiGe BiCMOS Driver With Adjustable Pre-Emphasis for Data Transmission Over 75Ω Coaxial Cable
A 1 kbit Josephson random access memory using variable threshold cells
Ultrahigh-efficiency power amplifier for space radar applications
A 3 µW CMOS True Random Number Generator With Adaptive Floating-Gate Offset Cancellation
Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs
Floating-point datapaths with online built-in self speed test
A 48-860 MHz CMOS Low-IF Direct-Conversion DTV Tuner
A 2.5-V 14-bit, 180-mW Cascaded ΣΔ ADC for ADSL2+ Application
A 77-dB-DR 0.65-mW 20-MHz 5th-Order Coupled Source Followers Based Low-Pass Filter
A memory-based high-speed digital delay line with a large adjustable length
Field-Programmable LNAs With Interferer-Reflecting Loop for Input Linearity Enhancement
A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips
A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface
Testable switched-capacitor filters
A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture
A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a + 27.1 dBm WCDMA CMOS Power Amplifier
Challenges in the Cell-Based Design of Very-High-Speed SiGe-Bipolar ICs at 100 Gb/s
A Hybrid Buck-or-Boost Converter for Fast-Transient and Wide-Voltage-Range Applications With Continuous Output Delivery Current
A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme
A low-power 128-tap digital adaptive equalizer for broadband modems
39 000-Subexposures/s Dual-ADC CMOS Image Sensor With Dual-Tap Coded-Exposure Pixels for Single-Shot HDR and 3-D Computational Imaging
An ultralow-power UHF transceiver integrated in a standard digital CMOS process: transmitter
A 117.5-155-GHz SiGe ×12 Frequency Multiplier Chain With Push-Push Doublers and a Gilbert Cell-Based Tripler
A Fully-Integrated, Miniaturized (0.125 mm 2 ) 10.5 µW Wireless Neural Sensor
Area-efficient multichannel oversampled PCM voice-band coder
A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless Transmitters
A 64×64-Pixel CMOS Test Chip for the Development of Large-Format Ultra-High-Speed Snapshot Imagers
A 75-mW 128-MHz DS-CDMA baseband demodulator for high-speed wireless applications [LANs]
A large-signal very low-distortion transconductor for high-frequency continuous-time filters
A Low-Noise Quadrature VCO Based on Magnetically Coupled Resonators and a Wideband Frequency Divider at Millimeter Waves
A practical micropower programmable bandpass filter for use in bionic ears
A Hierarchical Self-Interference Canceller for Full-Duplex LPWAN Applications Achieving 52-70-dB RF Cancellation
A 2-V, 1.8-GHz BJT phase-locked loop
An FFE Transmitter Which Automatically and Adaptively Relaxes Impedance Matching
CMOS Technology Scaling Considerations for Multi-Gbps Optical Receivers With Integrated Photodetectors
A 0.5 V 55 µW 64×2 Channel Binaural Silicon Cochlea for Event-Driven Stereo-Audio Sensing
High-frequency high-Q BiCMOS current-mode bandpass filter and mobile communication application
Performance Limits, Design and Implementation of mm-Wave SiGe HBT Class-E and Stacked Class-E Power Amplifiers
A low-voltage regulator circuit with self-bias to improve accuracy
Analog Filter Design Using Ring Oscillator Integrators
A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 µm CMOS
A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR Analog Baseband Chain With Digital-Assisted DC-Offset Calibration for Ultra-Wideband
A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links
A DSP line equalizer VLSI for TCM digital subscriber-line transmission
A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS
Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors
Fully Integrated Wide Input Voltage Range Capacitive DC-DC Converters: The Folding Dickson Converter
Analysis and Design of an Ultra-Low-Power Bluetooth Low-Energy Transmitter With Ring Oscillator-Based ADPLL and 4 $\times$ Frequency Edge Combiner
Vertically integrated sensors for advanced imaging applications
A 10.1" 183-µW/electrode, 0.73-mm2/sensor High-SNR 3-D Hover Sensor Based on Enhanced Signal Refining and Fine Error Calibrating Techniques
A Single-Inductor Dual-Path Three-Switch Converter With Energy-Recycling Technique for Light Energy Harvesting
Fully parallel 30-MHz, 2.5-Mb CAM
A 9.7-nTᵣₘₛ, 704-ms Magnetic Biosensor Front-End for Detecting Magneto-Relaxation
An Envelope Tracking Supply Modulator Utilizing a GaN-Based Integrated Four-Phase Switching Converter and Average Power Tracking-Based Switch Sizing With 85.7% Efficiency for 5G NR Power Amplifier
A fully parallel vector-quantization processor for real-time motion-picture compression
Corrections to "A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization"
A 4.96-μW 15-bit Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC
On the relationship between PSRR and clock feedthrough in SC filters
Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing
A 50-MHz Pulse-Width Modulator Embodying Low-Loss Quasi-Dynamic Comparators for Very High-Frequency DC-DC Converters
A 50-MHz standard CMOS pulse equalizer for hard disk read channels
A BiCMOS wired-OR logic
A 22-mA 3.0-dB NF direct conversion receiver for 3G WCDMA
Erratum to "A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain"
A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems
A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell
Ganged CMOS: trading standby power for speed
A Fully Synthesizable All-Digital Dual-Loop Distributed Low-Dropout Regulator
A Time-Interleaved Ring-VCO with Reduced 1/f 3 Phase Noise Corner, Extended Tuning Range and Inherent Divided Output
A 10 kPixel CMOS Hall Sensor Array With Baseline Suppression and Parallel Readout for Immunoassays
Switched-Mode-Control Based Hybrid LDO for Fine-Grain Power Management of Digital Load Circuits
A Calibration-Free Pipelined-SAR ADC With Cross-Stage Gain-Mismatch Error Shaping and Inherent Noise Shaping
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations
A low-power segmented nonlinear DAC-based direct digital frequency synthesizer
A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion
Guest Editorial Introduction to the Special Issue on the 2024 Symposium on VLSI Circuits
A 52 µW Wake-Up Receiver With -72 dBm Sensitivity Using an Uncertain-IF Architecture
Erratum to "Evolver: a Deep Learning Processor With On-Device Quantization-Voltage-Frequency Tuning"
A CMOS gate array architecture for digital signal processing applications
A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture
A single-chip CMOS analog/digital mixed NTSC decoder
Gallium-arsenide process evaluation based on a RISC microprocessor example
A mm-Sized Implantable Medical Device (IMD) With Ultrasonic Power Transfer and a Hybrid Bi-Directional Data Link
Phase and amplitude pre-emphasis techniques for low-power serial links
Current-Mode Transceiver for Silicon Interposer Channel
A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet
An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors
Transistor-only frequency-selective circuits
A high-efficiency 4×20 W monolithic audio amplifier for automobile radios using a complementary D-MOS BCD technology
A 2.2 GHz Continuous-Time ΔΣ ADC With -102 dBc THD and 25 MHz Bandwidth
Introduction to the Special Section on the 2015 Bipolar/BiCMOS Circuits and Technology Meeting
GalEPR: A Galvanically Coupled Electron Paramagnetic Resonance Spectrometer for Deep Tissue Hypoxia Diagnosis
Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors
CTLE-Ising: A Continuous-Time Latch-Based Ising Machine Featuring One-Shot Fully Parallel Spin Updates and Equalization of Spin States
Erratum "A 1.1-V 270-μ a mixed-signal hearing aid chip"
Class-AB large-swing CMOS buffer amplifier with controlled bias current