yusuke1997/dblp-id-title huggingface dataset:
Improvements to Technology Mapping for LUT-Based FPGAs
Computer-Aided Design of a Switchable True Time Delay (TTD) Line With Shunt Open-Stubs
Physically rigorous modeling of internal laser-probing techniques for microstructured semiconductor devices
Comments on 'A method of fault simulation based on stem regions'
MULSAM: Multidimensional Attention With Hardware Acceleration for Efficient Intrusion Detection on Vehicular CAN Bus
An Efficient Two-Phase ILP-Based Algorithm for Precise CMOS RFIC Layout Generation
Improved EM Side-Channel Analysis Attack Probe Detection Range Utilizing Coplanar Capacitive Asymmetry Sensing
Design of General Flux-Controlled and Charge-Controlled Memristor Emulators Based on Hyperbolic Functions
Efficient Return Address Verification Based on Dislocated Stack
The Waveform Relaxation Method for Time-Domain Analysis of Large Scale Integrated Circuits
Assessing Layout Density Benefits of Vertical Channel Devices
BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation
A performance-aimed cell compactor with automatic jogs
Optimized reseeding by seed ordering and encoding
A unified approach to floorplan sizing and enumeration
DyPhase: A Dynamic Phase Change Memory Architecture With Symmetric Write Latency and Restorable Endurance
Lightweight, Integrated Data Deduplication for Write Stress Reduction of Mobile Flash Storage
Tri-HD: Energy-Efficient On-Chip Learning With In-Memory Hyperdimensional Computing
H 2 B: Crypto Hash Functions Based on Hybrid Ring Generators
Design Automation of Cyber-Physical Systems: Challenges, Advances, and Opportunities
Local State Space Analysis Leads to Better Partial Order Reduction
Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs
A Reconfigurable Hardware Architecture for Fractional Pixel Interpolation in High Efficiency Video Coding
An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble
An efficient and robust method for ring-oscillator simulation using the harmonic-balance method
SSCNAP: a program for symbolic analysis of switched capacitor circuits
Fast and Low Overhead Metadata Operations for NVM-Based File System Using Slotted Paging
Lossy transmission line simulation based on closed-form triangle impulse responses
Chip Substrate Resistance Modeling Technique for Integrated Circuit Design
Transition fault testing for sequential circuits
Single-probe traversal optimization for testing of MCM substrate interconnections
Maple-opt: a performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGAs
A fast algorithm for minimizing the Elmore delay to identified critical sinks
Iterative Search for Reconfigurable Accelerator Blocks With a Compiler in the Loop
Data Reuse for Accelerated Approximate Warps
Efficient Algorithms for Routing Interchangeable Terminals
SPARE - A Scalable Algorithm for Passive, Structure Preserving, Parameter-Aware Model Order Reduction
Memory-Aware Embedded Control Systems Design
A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis
Design and Modeling of Optimum Quality Spiral Inductors With Regularization and Debye Approximation
An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation
EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm
FABRICS II: A Statistically Based IC Fabrication Process Simulator
Antenna Avoidance in Layer Assignment
PROPTEST: a property-based test generator for synchronous sequential circuits
Convergence of Transverse Waveform Relaxation for the Electrical Analysis of Very Wide Transmission Line Buses
Adaptive Edge Offloading for Image Classification Under Rate Limit
GfXpress: A Technique for Synthesis and Optimization of GF(2 m ) Polynomials
Design of an Energy-Efficient Asynchronous NoC and Its Optimization Tools for Heterogeneous SoCs
Timing optimization on routed designs with incremental placementand routing characterization
ParSGCN: Bridging the Gap Between Emulation Partitioning and Scheduling
Channel routing by sorting
Automated Design Space Exploration for Optimized Deployment of DNN on Arm Cortex-A CPUs
A minimum-cost circulation approach to DSP address-code generation
A Meet-in-the-Middle Algorithm for Fast Synthesis of Depth-Optimal Quantum Circuits
High-Level Synthesis Design Space Exploration: Past, Present, and Future
Using lower bounds during dynamic BDD minimization
Nonoscillatory streamline upwind formulations for drift-diffusion equation
A limited exponential complexity algorithm for increasing the testability of digital circuits by testing-module insertion
A framework for testing special-purpose memories
Fork Path: Batching ORAM Requests to Remove Redundant Memory Accesses
Characterizing the LSI Yield Equation from Wafer Test Data
An efficient algorithm for finding multiple DC solutions based onthe SPICE-oriented Newton homotopy method
Reliable Architectures for Composite-Field-Oriented Constructions of McEliece Post-Quantum Cryptography on FPGA
Fast DRAM PUFs on Commodity Devices
Power profile manipulation: a new approach for reducing test application time under power constraints
Timing-driven partitioning and timing optimization of mixedstatic-domino implementations
Algorithms for optimizing, two-dimensional symbolic layout compaction
Gate-size optimization under timing constraints for coupling-noise reduction
A Speculative Computation Approach for Energy-Efficient Deep Neural Network
Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential Method With Adaptive Control
An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form
Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model
A Two-Variable Model for SAT-Based ATPG
A Simple Charge-Based Model for MOS Transistor Capacitances: A New Production Tool
ProMiner: Enhancing Locality, Parallelism, and Offloading for Graph Mining on Processing-in-Memory Systems
SAMSON2: An Event Driven VLSI Circuit Simulator
HDL-Based Synthesis System With Debugger for Current-Mode FPAA
A Comprehensive Evaluation of Integrated Circuits Side-Channel Resilience Utilizing Three-Independent-Gate Silicon Nanowire Field Effect Transistors-Based Current Mode Logic
Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures
Board-Level Functional Fault Identification Using Streaming Data
F-FM: Fixed-Outline Floorplanning Methodology for Mixed-Size Modules Considering Voltage-Island Constraint
A Robust Mixed-Size Legalization and Detailed Placement Algorithm
Importance Boundary Sampling for SRAM Yield Analysis With Multiple Failure Regions
A Generalized Residue Number System Design Approach for Ultralow-Power Arithmetic Circuits Based on Deterministic Bit-Streams
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction
Everything You Always Wanted to Know About Generalization of Proof Obligations in PDR
Cost Efficient Flip-Flop Designs With Multiple-Node Upset-Tolerance and Algorithm-Based Verifications
Gate Matrix Layout
Non-Monte Carlo Analysis of Low-Frequency Noise: Exposition of Intricate Nonstationary Behavior and Comparison With Legacy Models
Thread Carefully: Preventing Starvation in the ROS 2 Multithreaded Executor
DELFINES: Detecting Laser Fault Injection Attacks via Digital Sensors
Achieving Versatile and Simultaneous Cache Optimizations With Nonvolatile SRAM
On an Efficient CAD Implementation of the Distance Term in Pelgrom's Mismatch Model
Robust Optimization of Test-Access Architectures Under Realistic Scenarios
Totally self-checking checker designs for Bose-Lin, Bose, and Blaum codes
Detailed-Routing Algorithms for Dense Pin Clusters in Integrated Circuits
A Low Cost Partial Scan Approach Based on Balanced Sequential Graph Transformation
Testing Network-on-Chip Communication Fabrics
SEAL: User Experience-Aware Two-Level Swap for Mobile Devices
Design of Time-Mode PI Controller for Switched-Capacitor DC/DC Converter Using Differential Evolution Algorithm - A Design Methodology
Gradient Descent Using Stochastic Circuits for Efficient Training of Learning Machines
Deep Learning Strategies for Labeling and Accuracy Optimization in Microcontroller Performance Screening
Synthesis for testability techniques for asynchronous circuits
Leveraging Spatial Correlation for Sensor Drift Calibration in Smart Building
SPIDER: capacitance modelling for VLSI interconnections
A Table-Free Approximate Q-Learning-Based Thermal-Aware Adaptive Routing for Optical NoCs
Synthesis of quantum-logic circuits
Timing-driven logic bi-decomposition
The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits
Address assignment in DSP code generation - an integrated approach
How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance
Quasi-Static Control of Explicit Algorithms for Transient Analysis
Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual Synchronization
An Energy Efficient Residual Spiking Neural Network Accelerator With Ternary Spikes
Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing
Secure Delegated Variational Quantum Algorithms
A New Chessboard Placement and Sizing Method for Capacitors in a Charge-Scaling DAC by Worst-Case Analysis of Nonlinearity
Cost-free scan: a low-overhead scan path design
Correction to "interconnect synthesis without wire tapering"
Code Synthesis for Dataflow-Based Embedded Software Design
Advances in Computation of the Maximum of a Set of Gaussian Random Variables
Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique
Data-Driven Reliability Models of Quantum Circuit: From Traditional ML to Graph Neural Network
Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism
Verification and Synthesis of Clock-Gated Circuits
Modeling and simulation of broken connections in CMOS IC's
Deep H-GCN: Fast Analog IC Aging-Induced Degradation Estimation
An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing
Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical Building Blocks and Structural Homotopy
Energy-Quality-Time Optimized Task Mapping on DVFS-Enabled Multicores
Performance- and Energy-Aware Gait-Based User Authentication With Intermittent Computation for IoT Devices
Compressed Block-Decomposition Algorithm for Fast Capacitance Extraction
Enabling High-Dimensional Hierarchical Uncertainty Quantification by ANOVA and Tensor-Train Decomposition
EmPointMovSeg: Sparse Tensor-Based Moving-Object Segmentation in 3-D LiDAR Point Clouds for Autonomous Driving-Embedded System
Subtractive Router for Tree-Driven-Grid Clocks
Asymptotic waveform evaluation for transient analysis of 3-D interconnect structures
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices
Full-Chip Routing Considering Double-Via Insertion
CAMON: Low-Cost Silicon Photonic Chiplet for Manycore Processors
Underdesigned and Opportunistic Computing in Presence of Hardware Variability
Extended Nodal Analysis
An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture
Migration-Aware Loop Retiming for STT-RAM-Based Hybrid Cache in Embedded Systems
Simplified simulations of GaAs MESFET's with semi-insulating substrate compensated by deep levels
PHCG: Optimizing Simulink Code Generation for Embedded System With SIMD Instructions
Accurate Current Calculation in Two-Dimensional MOSFET Models
Reliability-Driven Software Transformations for Unreliable Hardware
Incorporating interconnect, register, and clock distribution delays into the retiming process
DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating
Efficient Regulation of Synthetic Biocircuits Using Droplet-Aliquot Operations on MEDA Biochips
Vector-restoration-based static compaction using random initial omission
Error Recovery in Cyberphysical Digital Microfluidic Biochips
Test sequences to achieve high defect coverage for synchronous sequential circuits
Efficient calculation of spectral coefficients and their applications
Efficient approximation of the time domain response of lossy coupled transmission line trees
PART: Programmable Array Testing Based on a Partitioning Algorithm
Profile-Driven Instruction Mapping for Dataflow Architectures
Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes
RLPlace: Using Reinforcement Learning and Smart Perturbations to Optimize FPGA Placement
PrePack: Predictive Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation
CaBaFL: Asynchronous Federated Learning via Hierarchical Cache and Feature Balance
Minimum fault coverage in memory arrays: a fast algorithm and probabilistic analysis
Optimal testing of VLSI analog circuits
Accelerate Safety Model Checking Based on Complementary Approximate Reachability
CMD: A Cache-Assisted GPU Memory Deduplication Architecture
Silicon Photonic Microring Resonators: A Comprehensive Design-Space Exploration and Optimization Under Fabrication-Process Variations
Quantum Circuit Simplification and Level Compaction
Modeling hysteretic current-voltage characteristics for resonant tunneling diodes
Time-Multiplexed 1687-Network for Test Cost Reduction
A General Control-Volume Formulation for Modeling Impact Ionization in Semiconductor Transport
BALBOA: a component-based design environment for system models
Hardware-optimal test register insertion
LT-RTPG: a new test-per-scan BIST TPG for low switching activity
TAIR: testability analysis by implication reasoning
Enhancing Analog IC Security Using Randomized Obfuscation Circuits
A Delay Line Circuit Design for Crosstalk Minimization Using Genetic Algorithm
Input Test Data Compression Based on the Reuse of Parts of Dictionary Entries: Static and Dynamic Approaches
A compiler-based approach for dynamically managing scratch-pad memories in embedded systems
Nonvolatile Write Buffer-Based Journaling Bypass for Storage Write Reduction in Mobile Devices
Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics
A Design Centering Algorithm for Nonconvex Regions of Acceptability
Test response compaction using multiplexed parity trees
A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks
Graph-Optimization Techniques for IC Layout and Compaction
Failure Triage in RTL Regression Verification
Bit-Flip Detection-Driven Selection of Trace Signals
Detecting Failures and Attacks via Digital Sensors
Variability-Aware Bulk-MOS Device Design
SENTINEL: Securing Indoor Localization Against Adversarial Attacks With Capsule Neural Networks
Manufacturing Cycle Time Optimization for Inkjet-Printed Electronics
Modeling and Simulation of Circuit-Level Nonidealities for an Analog Computing Design Approach With Application to EEG Feature Extraction
Optimal channel pin assignment
Multilevel spectral hypergraph partitioning with arbitrary vertex sizes
TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultralow Power Methods
Fast signature computation for BIST linear compactors
Efficient Built-In Self-Repair Techniques for Multiple Repairable Embedded RAMs
MemFlow: Memory-Driven Data Scheduling With Datapath Co-Design in Accelerators for Large-Scale Inference Applications
On Model Order Reduction and Exponential Integrator for Transient Circuit Simulation
Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values
Wire Sizing for Non-Tree Topology
Design-for-Manufacturability Assessment for Integrated Circuits Using RADAR
Probabilistic fault detection and the selection of measurements for analog integrated circuits
Abstraction-Guided Simulation Using Markov Analysis for Functional Verification
A Single Layer 3-D Touch Sensing System for Mobile Devices Application
Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects
MIDAS: Safeguarding IoT Devices Against Malware via Real-Time Behavior Auditing
Integrated Functional and Washing Routing Optimization for Cross-Contamination Removal in Digital Microfluidic Biochips
SpecWands: An Efficient Priority-Based Scheduler Against Speculation Contention Attacks
Ring generators - new devices for embedded test applications
Meta-Scanner: Detecting Fault Attacks via Scanning FPGA Designs Metadata
CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design
Design and Analysis of a Neural Network Inference Engine Based on Adaptive Weight Compression
Freezer: A Specialized NVM Backup Controller for Intermittently Powered Systems
Guest editorial: Special section on cross-domain physical optimization
Thermal Sensor Placement and Thermal Reconstruction Under Gaussian and Non-Gaussian Sensor Noises for 3-D NoC
Exploring the Potential of Low-Bit Training of Convolutional Neural Networks
Synthesis Procedure of Configurable Building Block-Based Linear and Nonlinear Analog Circuits
A charge conserving non-quasi-state (NQS) MOSFET model for SPICE transient analysis
REX-SC: Range-Extended Stochastic Computing Accumulation for Neural Network Acceleration
On the Fixed-Point Accuracy Analysis and Optimization of Polynomial Specifications
Moving Target Defense Through Approximation for Low-Power Neuromorphic Edge Intelligence
An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs
A Variant of Parallel Plane Sweep Algorithm for Multicore Systems
Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search
DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths
Experimental Verification and Analysis of the Acceleration Factor Model for 3-D nand Flash Memory
Prior-Boosted GRL: Microarchitecture Design Space Exploration via Graph Representation Learning
Genetic Placement
Synthesis of Monitors for Networked Systems With Heterogeneous Safety Requirements
Fine-Grained Structured Sparse Computing for FPGA-Based AI Inference
Accelerated and Reliable Analog Circuits Yield Analysis Using SMT Solving Techniques
Optimizing the Power Delivery Network in a Smartphone Platform
Symbolic analysis of switched-capacitor networks using compacted nodal analysis in the s-domain
iCheck: Progressive Checkpointing for Intermittent Systems
UrsaX: Integrating Block I/O and Message Transfer for Ultrafast Block Storage on Supercomputers
CircuitGTL: An Intelligent Circuit Design Methodology Across Electromagnetic Topologies With Graph Transfer Learning
A Memory Built-In Self-Repair Scheme Based on Configurable Spares
Fast Physics-Based Electromigration Analysis for Full-Chip Networks by Efficient Eigenfunction-Based Solution
Automatic layout recycling based on layout description and linear programming
Vectorized LU Decomposition Algorithms for Large-Scale Circuit Simulation
Sensitivity Analysis for Oscillators
Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs
Energon: Toward Efficient Acceleration of Transformers Using Dynamic Sparse Attention
COSA Plus: Enhanced Co-Operative Systolic Arrays for Attention Mechanism in Transformers
Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits - Part II
An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores
Exploiting the special structure of conflict and compatibility graphs in high-level synthesis
APIM: An Antiferromagnetic MRAM-Based Processing-In-Memory System for Efficient Bit-Level Operations of Quantized Convolutional Neural Networks
Robust Simulation of High-Q Oscillators Using a Homotopy-Based Harmonic Balance Method
CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation
Security Against Data-Sniffing and Alteration Attacks in IJTAG
Signature-Based SER Analysis and Design of Logic Circuits
Deviation-Based LFSR Reseeding for Test-Data Compression
Schematic array models for associative and non-associative memory circuits
Effective and Efficient Parallel Qubit Mapper
Berkeley reliability tools-BERT
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS
Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients
Restructuring WSI hexagonal processor arrays
XBarNet: Computationally Efficient Memristor Crossbar Model Using Convolutional Autoencoder
Optimizing Intratask Voltage Scheduling Using Profile and Data-Flow Information
Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States
Statistical Test Development for Analog Circuits Under High Process Variations
Calculation of Channeling Effects During Ion Implantation Using the Boltzmann Transport Equation
Theoretical and Experimental Analysis of a CSWPL Behavioral Model for Microwave GaN Transistors Including DC Bias Voltages
Hybrid System Falsification Under (In)equality Constraints via Search Space Transformation
ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules
A novel critical path heuristic for fast fault grading
Adaptive Layout Decomposition With Graph Embedding Neural Networks
Fault-Tolerant Training Enabled by On-Line Fault Detection for RRAM-Based Neural Computing Systems
Force-Directed Methods for Generic Placement
Efficient algorithms for exact two-level hazard-free logic minimization
SCERPA: A Self-Consistent Algorithm for the Evaluation of the Information Propagation in Molecular Field-Coupled Nanocomputing
Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs
CRAFT: Criticality-Aware Fault-Tolerance Enhancement Techniques for Emerging Memories-Based Deep Neural Networks
$Q$ -Value Prediction for Reinforcement Learning Assisted Garbage Collection to Reduce Long Tail Latency in SSD
Agglomerative Memory and Thread Scheduling for High-Performance Ray-Tracing on GPUs
Near optimal factorization of Boolean functions
TraNNsformer: Clustered Pruning on Crossbar-Based Architectures for Energy-Efficient Neural Networks
A Matching-Based Escape Routing Algorithm With Variable Design Rules and Multiple Constraints
On Compaction Utilizing Inter and Intra-Correlation of Unknown States
Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs
Application of symbolic computer algebra in high-level data-flow synthesis
Shortest path search using tiles and piecewise linear costpropagation
FastPass: A Fast Pin Access Analysis Framework for Detailed Routability Enhancement
Evaluating the Security of Delay-Locked Circuits
Accelerating Graph Neural Network Training on ReRAM-Based PIM Architectures via Graph and Model Pruning
Thermal and Voltage-Aware Performance Management of 3-D MPSoCs With Flow Cell Arrays and Integrated SC Converters
Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations
A fast signature computation algorithm for LFSR and MISR
On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation
StereoEngine: An FPGA-Based Accelerator for Real-Time High-Quality Stereo Estimation With Binary Neural Network
Exact and efficient crosstalk estimation
Quantitative Evaluation of Self-Checking Circuits
Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography
NN2FPGA: Optimizing CNN Inference on FPGAs With Binary Integer Programming
Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests
Prediction of Multidimensional Spatial Variation Data via Bayesian Tensor Completion
Table Recomputation-Based Higher-Order Masking Against Horizontal Attacks
Symbolic Layout for Bipolar and MOS VLSI
On the Design of Time-Constrained and Buffer-Optimal Self-Timed Pipelines
Improving Multilevel Writes on Vertical 3-D Cross-Point Resistive Memory
DREAMx: A Data-Driven Error Estimation Methodology for Adders Composed of Cascaded Approximate Units
Minimization of Linear Dependencies Through the Use of Phase Shifters
ASSURED: Architecture for Secure Software Update of Realistic Embedded Devices