yusuke1997/dblp-id-title huggingface dataset:
A dataflow Prolog execution model and its architectural support
A 32-bit RISC CPU implemented in GaAs
Hybrid short-term traffic forecasting architecture and mechanisms for reservation-based Cooperative ITS
High-level algorithmic complexity evaluation for system design
A Comprehensive End-to-End Security Framework for Optical On-Chip Networks
Computer systems for real-time process control and supervision A framework for education based on a systems-engineering approach
An example of the efficient message protocol for industrial LAN
Multiprocess architecture for watch applications
Provably secure public key encryption with keyword search for data outsourcing in cloud environments
Energy Optimization of Security-Critical Real-Time Applications with Guaranteed Security Protection
The algorithm of pipelined gossiping
Array processor for LS FIR system identification
A VLSI architecture for video object motion estimation using a novel 2-D hierarchical mesh
An environment to perform functional tests on boards and integrated circuits
A robust multiplexer-based FPGA inspired by biological systems
Run-time support for dynamically reconfigurable computing systems
Development of a technology independent library
The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems
Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures
Resource provisioning in edge/fog computing: A Comprehensive and Systematic Review
Quality-driven model-based architecture synthesis for real-time embedded SoCs
Instruction set architectural guidelines for embedded packet-processing engines
LISAS - Simulation tool for regular networks of finite state machines
A survey on data center cooling systems: Technology, power consumption modeling and control strategy optimization
Reducing cache and TLB power by exploiting memory region and privilege level semantics
An efficient approach for the multiprocessor non-preemptive strictly periodic task scheduling problem
Bradford musical instrument simulator and workstation
Tracing and recording interrupts in embedded software
ASTRA: An associative RISC-Architecture
Chip size estimation for SOC design space exploration
N version programming with majority voting decision: Dependability modeling and evaluation
A real-time hardware implementation of the hough transform
Systematic review on contract-based safety assurance and guidance for future research
Computing exact WCRT for typed DAG tasks on heterogeneous multi-core processors
Modular software architecture for flexible reservation mechanisms on heterogeneous resources
Efficient timing verification via mixed-mode technique
T9000 and T800 transputers: A real-time application
STC: Sub-packetization tunable codes for fast recovery
Design optimization of confidentiality-critical cyber physical systems with fault detection
Evaluation of delay fault testability of LUTs for the enhancement of application-dependent testing of FPGAs
Hardware support for load sharing in parallel systems
Hypervisor for consolidating real-time automotive control units: Its procedure, implications and hidden pitfalls
Fine-grained adaptive parallelism for automotive systems through AMALTHEA and OpenMP
Execution coordination in mobile agent-based distributed job workflow execution
A cloud middleware for assuring performance and high availability of soft real-time applications
CDDT - concurrent system operation display and debugging tool
EUROMICRO 1995 - Short Contributions
The fuzzy set model based on N-ary positively compensatory operators
Efficient communication sets generation for block-cyclic distribution on distributed-memory machines
WEVAN - A mechanism for evidence creation and verification in VANETs
Multiple voltage and frequency scheduling for power minimization
Synthesis of dependency-aware traffic generators from NoC simulation traces
Formal hardware specification and verification using prolog
Three-phase time-aware energy minimization with DVFS and unrolling for Chip Multiprocessors
Multi-Task Learning for Intrusion Detection on web logs
Dependence graph transformations in the design of processor arrays for matrix multiplications
Multistage ring network: An interconnection network for large scale shared memory multiprocessors
A narrow band interval type-2 fuzzy approach for image segmentation
Fully pipelined real time hardware solution for High Efficiency Video Coding (HEVC) intra prediction
Parametric WCET as a function of procedure arguments: Analysis and applications
Structure and application of NNSIM: a general-purpose neural network SIMulator
Multiprocessor based image coding
Image processing on a transputer-based perfect shuffle machine
ANSI: A swarm intelligence-based unicast routing protocol for hybrid ad hoc networks
Orchid: A portable platform for parallel programming
Definitions of predictability for Cyber Physical Systems
Command queue-aware host I/O stack for mobile flash storage
Session A1: Topics on computer architecture
Identity-based proxy matchmaking encryption for cloud-based anonymous messaging systems
Circuit optimization: Gate level modelling and multiobjective programming
Efficient decomposition of strongly connected components on GPUs
A PCI bus simulation framework and some simulation results on PCI standard 2.1 latency limitations
Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization
Backdoor-resistant certificateless-based message-locked integrity auditing for computing power network
Memory efficient and scalable address mapping for flash storage devices
Subtraction of Hyperledger Fabric: A blockchain-based lightweight storage mechanism for digital evidences
Real-time energy-efficient software and hardware implementations of a QCSP communication system
COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications
MultiCS: Circuit switched NoC with multiple sub-networks and sub-channels
LB-CLBS: Lattice-based certificateless blind signature scheme for vehicle sensing within intelligent transportation
Scheduling demand-driven parallel logic programs on transputers
Verifiable fuzzy keyword search supporting sensitive information hiding for data sharing in cloud-assisted e-healthcare systems
Blockchain-driven authorized data access mechanism for digital healthcare
An applicative real-time language for DSP-programming supporting asynchronous data-flow concepts
Reconfigurable embedded systems: Synthesis, design and application
Universal DSP board
Transputer based implementations of the hough transform for computer vision
Minimizing the effects of jitter in distributed hard real-time systems
Energy-efficient scheduling for moldable real-time tasks on heterogeneous computing platforms
An open source framework based on Kafka-ML for Distributed DNN inference over the Cloud-to-Things continuum
Performance evaluation of a bus-based multistage multiprocessor architecture
Teegraph: A Blockchain consensus algorithm based on TEE and DAG for data sharing in IoT
A case study of a distributed high-performance computing system for neurocomputing
Software engineering & environments I
Dynamic forward secure searchable encryption scheme with phrase search for smart healthcare
VPSS: A DAG scheduling heuristic with improved response time bound
Removal of catastrophic noise in hetero-associative training samples
Evaluation of a bit-serial ASIC chip for SAR processing
The Policy Machine: A novel architecture and framework for access control policy specification and enforcement
Design and implementation of the WIPI-to-Android automatic mobile game converter for the contents compatibility in the heterogeneous mobile OS
Massively parallel processing approach to fractal image compression with near-optimal coefficient quantization
A comparison study of minimization methods of unit interconnection in VLIW processors
A composable real-time architecture for replicated railway applications
Update synchronization pursuing site autonomy in heterogeneous distributed databases
Container-based architecture for flexible industrial control applications
Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor
Design of a bus-monitor for real-time applications
Redundancy analysis and removal for VLSI ASIC's
A flexible attribute based data access management scheme for sensor-cloud system
Optimal evaluation of path predicates in object-oriented queries
Parallel character recognition system: Theory, simulation and synthesis
Optimizing allocation of multi-port register file for parallelism in RISC and its implementation
Task scheduling in multiprocessing systems using duplication
A nonlinear 3D MOSFET table for VLSI circuit simulation
Real-time shape description system based on MPEG-7 descriptors
PASS: High level synthesis
A template system for the efficient compilation of domain abstractions onto reconfigurable computers
Generative and incremental implementation for a scripting interface
Towards a framework for cost-based transformation
Privacy attacks against deep learning models and their countermeasures
Assessing the diagnostic power of test pattern sets
Performance evaluation of a distributed system architecture
System diagnosability in some restricted hybrid fault situations. Comparative studies on different system-level fault diagnosis models
An efficient data structure for dynamic two-dimensional reconfiguration
An analytical network performance model for SIMD processor CSX600 interconnects
Infracomposer: Policy-driven adaptive and reflective middleware for the cloudification of simulation & optimization workflows
On the weakest failure detector for hard agreement problems
Session H4: VLSI testing and fault modelling II
Simulation and visualization tools for link-based parallel architectures
A novel method for parallel image processing applications
Occam implementation of path-disjoint routing on the Hathi-2 transputer system
Digital system simulation with VHDL in a high-level synthesis system
Global deadlock detection for concurrency control in multidatabase systems
Dynamic reconfiguration of node location in wormhole networks
A flexible VLSI-based hardware system for medium-large-vocabulary real-time speech recognition
A CMOS implementation of the ESA/390 mainframe architecture
JCOOLS: A toolkit for generating context-aware applications with JCAF and DROOLS
Scheduling optimization with partitioning for mixed-criticality systems
Proving properties of a new high speed data bus with predicate/transition nets
Repair friendly wide-stripe erasure coding for in-memory key-value stores
Recent advances in Hardware/Software co-design
A dataflow model based on a vector queueing scheme
A survey of Flash Translation Layer
Multiprocessor monitoring system
Software architecture for a firm real-time database system
Toy user interfaces: Systematic and industrial mapping
Optimizing encoding and repair for wide-stripe minimum bandwidth regenerating codes in in-memory key-value stores
VLSI architecture for the Winograd Fourier transform algorithm
Alleviating channel bandwidth constraints in multicomputer networks
On hierarchical locking of composite objects
Systolic array description in F 2
SAR: Sharpness-Aware minimization for enhancing DNNs' Robustness against bit-flip errors
End-to-end schedulability tests for multiprocessor embedded systems based on networks-on-chip with priority-preemptive arbitration
Analysis and optimization of communication delay in multi-subscriber environments of ROS 2
Prolog: A new parallel evaluation scheme
Formal analysis of the continuous dynamics of cyber-physical systems using theorem proving
Test data compression scheme based on variable-to-fixed-plus-variable-length coding
On the effectiveness of phase based regression models to trade power and performance using dynamic processor adaptation
The diagnosability of hypercubes with arbitrarily missing links
A trip to object-oriented land
Microprogramming, microprocessing and supercomputing
On-the-fly bisimulation equivalence checking for fresh-register automata
Improving the division instruction of application-specific RISCs
HB-ReTriple: Mobile rendering optimization based on efficient history reusing
Multiprocessor real-time scheduling
Priority-driven concurrency control based on data conflict state in distributed real-time databases
A hierarchical vision processing architecture oriented to 3D integration of smart camera chips
NANI: Energy-efficient Neuron-Aware hardware Noise Injection for adversarial defense using undervolting
APES - Implementation of a CAD tool for array processor design: Textual definition versus graphic description
Architecture for interoperability of network management systems in multi-domain network
Optimal broadcasting in hypercubes with link faults using limited global information
Statecharts based requirements analysis: Deriving user oriented models
Soft error-aware energy-efficient task scheduling for workflow applications in DVFS-enabled cloud
NUMA-aware memory coloring for multicore real-time systems
Vector addressing processor for direct and indirect accesses
Preface to the special issue on worst-case execution-time analysis
Petri Nets applied to the modelling and analysis of computer architecture problems
A portable query language for small scale systems
A Lightweight and Generic Access Rights Update Mechanism for Attribute-Based Encryption in cloud storage
CDPU for SOHO-CEPAC collaboration
The specification and design of hard real-time systems using timed and temporal petri nets
Experiences with VHDL and FPGAs
Using supplier locality in power-aware interconnects and caches in chip multiprocessors
Blocking analysis of real-time tasks with parallel critical sections under federated scheduling
Speedup of NULL convention digital circuits using NULL cycle reduction
Aspects of an expert design system for the wastewater treatment industry
Active object oriented databases in control applications
A Privacy-Preserving Three-Factor Authentication System for IoT-Enabled Wireless Sensor Networks
Ensuring consistent recovery under power failure with minimal NVM write overhead
Corrigendum to 'Fine-Grained Parallelism Framework with Predictable Work-Stealing for Real-Time Multiprocessor Systems' Journal of Systems Architecture Vol. 124, March 2022, Article Number 102393
EdgeMark: An automation and benchmarking system for embedded artificial intelligence tools
A reconfigurable bus structure for multiprocessors with bandwidth reuse
HiEval: A scheduling performance estimation approach for spatial accelerators via hierarchical abstraction
From a high level description of an IC to silicium: Don't loose design intent
Proconsul, a tool for computer-aided protocol engineering
An approach to partitioning programs on the functional basis and applications
Enhancing generalization of computation offloading policies in novel mobile edge computing environments by exploiting experience utility
A communication mechanism and its implementation in the Multi-SIMD massively parallel machine SPHINX
Compiling for power with ScalaPipe
NL1 Machine - A concept of a high performance data type architecture
Radio propagation modeling and real test of ZigBee based indoor wireless sensor networks
Conflict-aware compiler for hierarchical register file on GPUs
State assignment and testability of PLA-based finite state machines
A traceable and revocable decentralized multi-authority privacy protection scheme for social metaverse
Measurements in software requirements specification process
Efficient registration-based signature schemes
Hardware accelerator for an accurate local stereo matching algorithm using binary neural network
Mobile Crowdsensing Model: A survey
Fast revocable attribute-based encryption with data integrity for Internet of Things
Efficient flash-aware page-mapping cache management for on-board remote sensing image processing
Parallel WZ factorization on mesh multiprocessors
A permanent fault tolerant dynamic task allocation approach for Network-on-Chip based multicore systems
A software architecture for sound and music processing
Testing and built-in self-test - A survey
Comparing vertical and horizontal SIMD vector processor architectures for accelerated image feature extraction
Closing the semantic gap
KA: Keyword-based auditing with frequency hiding and retrieval reliability for smart government
An approach to the design of RISC core processors for VLSI embedded systems
ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs
Flash controller-based secure execution environment for protecting code confidentiality
MakeCode and CODAL: Intuitive and efficient embedded systems programming for education
Design of a 1-chip IBM-3270 protocol handler
Reduced instruction buffer for RISC architectures
Testing of serial input convolvers
Special issue on advances in reliable software technologies (AdaEurope20)
Implementation of statecharts with transputers
Enhancing performance in a parallel file system
High-performance computing of I for a vector of inputs x
Multiple interfaces message passing system for transputer network
Dynamic reconfiguration of embedded-DRAM caches employing zero data detection based refresh optimisation
Special issue on: On-chip parallel and network-based systems
Optimal broadcasting on incomplete star graph interconnection networks
A generic adaptive path-based routing method for MPSoCs
Ker-ONE: A new hypervisor managing FPGA reconfigurable accelerators
Qore-DL: A QoS-aware joint optimization framework for distributed deep learning training
Compositional verification of embedded real-time systems
OCCN: a NoC modeling framework for design exploration
NGS: A network GPGPU system for orchestrating remote and virtual accelerators
Coarse-grained reconfigurable architectures for radio baseband processing: A survey
A real-time transputer-based system for a digital recording data channel
Energy-aware page replacement and consistency guarantee for hybrid NVM-DRAM memory systems
Functional test generation based on word-level SAT
Resource-aware Montgomery modular multiplication optimization for digital signal processing
K-means clustering algorithm for multimedia applications with flexible HW/SW co-design
Landscape-aware location-privacy protection in location-based services
The use of Estelle to specify manufacturing systems
High-level co-simulation based on the extension of processor simulators
A new distributed storage scheme for cluster video server
Secure communication protocols with discrete nonlinear chaotic maps
From program to hardware: A parallel architecture compiler
PMSort: An adaptive sorting engine for persistent memory
Real-time continuous feature extraction in large size satellite images
DUDS: Diversity-aware unbiased device selection for federated learning on Non-IID and unbalanced data
Adaptive Steiner tree balancing in distributed algorithm for multicast connection setup
Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives
A portable realtime multitasking kernel for embedded microprocessor systems
Concurrency control in multidatabase systems: A performance study
On the performance analysis of ABR in ATM LANs with Stochastic Petri Nets
A secure index resisting keyword privacy leakage from access and search patterns in searchable encryption
Checkpointing for single core energy-neutral real-time systems
Locking in DAG-structured databases
Session F5: The ESPRIT-PATRICIA project
HCRC-Parallel computer: A massively parallel combined architecture supercomputer
Compilation techniques for a high level language processor
A declarative neural network description language
WITHDRAWN: An improved mechanism for flow rule installation in In-band SDN
Hardware description language for specification of digital systems
Multiple vs. single inheritance in object-oriented programming languages
Session D2: ASIC design
Testability measure with reconvergent fanout analysis and its applications
Efficient analysis of single event transients
Cooker programmers with embedded microcomputers
Using complexity, coupling, and cohesion metrics as early indicators of vulnerabilities
A priority, power and traffic-aware virtual machine placement of IoT applications in cloud data centers
EDXY - A low cost congestion-aware routing algorithm for network-on-chips
Efficient mapping of runnables to tasks for embedded AUTOSAR applications
FDT Tools
PEPA: Paillier cryptosystem-based efficient privacy-preserving authentication scheme for VANETs
A portable parallel environment for complex systems simulation through cellular automata networks
Control of motors by microprocessors for space positioning and localization
Energy analysis and prediction for applications on smartphones
Power- and time-aware buffer cache management for real-time embedded databases
Quantifying behavioral differences between multimedia and general-purpose workloads
On using multivariate polynomial regression model with spectral difference for statistical model-based speech enhancement
Performance evaluation: An analytical model for calculating start misses in caches
VHDL generation from a timed extension of the formal description technique LOTOS within the FORMAT project
RISC-V based virtual prototype: An extensible and configurable platform for the system-level
The design space of shelving
Alchemy model: An operating system model for a microcomputer-based, heterogeneous processing configuration
Mechanizing the verification of real-time discrete systems
A multiple disk failure recovery scheme in RAID systems
A privacy-preserving resource trading scheme for Cloud Manufacturing with edge-PLCs in IIoT
AdapTracer: Adaptive path profiling using arithmetic coding
Rapid design of area-efficient custom instructions for reconfigurable embedded processing
Speedups from extending embedded processors with a high-performance coarse-grained reconfigurable data-path
Designing parallel programs by the graphical language GRAPNEL
Demand-driven logic simulation using a network of loosely coupled processors
Efficient spatio-temporal out-of-distribution detection for learning-enabled autonomous systems
Measurement-based research on cryptographic algorithms for embedded real-time systems
Scheduling computation and communication on a software-defined photonic Network-on-Chip architecture for high-performance real-time systems
Two-level caches tuning technique for energy consumption in reconfigurable embedded MPSoC
Optimizing bus energy consumption of on-chip multiprocessors using frequent values
The online reconfiguration of a distributed on-board computer: The time and network behaviour of a dependable scheduling algorithm
Protocols and performance analysis
Group checkpointing scheme for partition failure recovery in mobile database systems: GCS/MD
A module-based assembly language with parallel processing constructs and its implementation in the ASTOR architecture
Efficient segment-based video transcoding proxy for mobile multimedia services
Towards an optimal combination of error detection mechanisms
Multiparallel systolic arrays for multidimensional FFT-architectures on 3D-VLSI
Special Issue on Emerging Trend and Techniques of Cyber Physical Systems
Failure-tolerant distributed storage with compressed (1 out-of N
Reverse engineering and data flow diagrams in ADA environment
NISHA: A fault-tolerant NoC router enabling deadlock-free Interconnection of Subnets in Hierarchical Architectures
Exploration methodology of dynamic data structures in multimedia and network applications for embedded platforms
The design and simulation of software fault tolerant mechanisms for application in distributed processing systems
A recursive method for synthesizing quantum/reversible quaternary parallel adder/subtractor with look-ahead carry
A product management challenge: Creating software product value through requirements selection
Adaptable system/software architectures
Designing a branch target buffer for executing branches with zero time cost in a RISC processor
Motion-compensated wavelet packet zerotree video coding on multicomputers
Symbolic two-dimensional minimization of strongly unspecified finite state machines