yusuke1997/dblp-id-title huggingface dataset:
Design techniques for high-resolution current-mode sigma-delta modulators
A 1-2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation
A Reconfigurable Phase-Time Array Transmitter Achieving Keyless Secured Transmission and Multi-Receiver Localization for Low-Latency Joint Communication and Sensing
Quick estimation of transient currents in CMOS integrated circuits
A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range
A 1.1-V current-mode and piecewise-linear curvature-corrected bandgap reference
Reversed nested Miller compensation with voltage buffer and nulling resistor
Design of a new squaring function for the Viterbi algorithm
A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC
A Resolution-Reconfigurable 5-to-10-Bit 0.4-to-1 V Power Scalable SAR ADC for Sensor Applications
A PAM-8 Wireline Transceiver With Linearity Improvement Technique and a Time-Domain Receiver Side FFE in 65 nm CMOS
A 5-GHz radio front-end with automatically Q-tuned notch filter and VCO
A 0.79-mm 2 29-mW Real-Time Face Detection Core
A 0.90-Tb/s/in 1.29-pJ/b Wireline Transceiver With Single-Ended Crosstalk Cancellation Coding Scheme for High-Density Interconnects
A 0.6-V 82-dB 28.6- μ W Continuous-Time Audio Delta-Sigma Modulator
A 32 × 32-Pixel CMOS Imager for Quantum Optics With Per-SPAD TDC, 19.48% Fill-Factor in a 44.64-μm Pitch Reaching 1-MHz Observation Rate
An Amplitude-Programmable Energy-Recycling High-Voltage Resonant Pulser for Battery- Powered Ultrasound Devices
256-Channel Neural Recording and Delta Compression Microsystem With 3D Electrodes
Monolithic active-quenching and active-reset circuit for single-photon avalanche detectors
A 10-GB/s SONET-compliant CMOS transceiver with low crosstalk and intrinsic jitter
90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique
A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS
A 10 MS/s 11-bit 0.19 mm 2 Algorithmic ADC With Improved Clocking Scheme
A 100-Gb/s PAM4 Optical Transmitter in a 3-D-Integrated SiPh-CMOS Platform Using Segmented MOSCAP Modulators
A 12-to-1 V Quad-Output Switched-Capacitor Buck Converter With Shared DC Capacitors
Design of Safe Two-Wire Interface-Driven Chip-Scale Neurostimulator for Visual Prosthesis
A 1-Gb/s, four-state, sliding block Viterbi decoder
A Si bipolar monolithic RF bandpass amplifier
A 1/2-in, 1.3 M-pixel progressive-scan CCD image sensor employing 0.25-μm gap single-layer poly-Si electrodes
A micropower CMOS, direct-conversion, VLF receiver chip for magnetic-field wireless applications
A Monolithic, 10.5 W/mm 2 , 600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16 nm Class
A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link
A 100-Mb/s 2.8-V CMOS current-mode analog Viterbi decoder
Multifrequency zero-jitter delay-locked loop
A ReRAM-Based Nonvolatile Flip-Flop With Self-Write-Termination Scheme for Frequent-OFF Fast-Wake-Up Nonvolatile Processors
A Dynamic Voltage-, Frequency-, and Resolution-Scalable (DVFRS) 8-10 b 12.5-to-734 MS/s Non-Interleaved SAR ADC With 0.8-to-5.9 fJ/conv-Step in 22-nm FDSOI
Current-mode subthreshold MOS implementation of the Herault-Jutten autoadaptive network
320 × 240 Back-Illuminated 10-µm CAPD Pixels for High-Speed Modulation Time-of-Flight CMOS Image Sensor
A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in 0.13-$\mu{\hbox{m}}$ CMOS
A 1.9 Gb/s 358 mW 16-256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS
A 25-GHz Compact Low-Power Phased-Array Receiver With Continuous Beam Steering in CMOS Technology
A 5.4 mW/0.07 mm 2 2.4 GHz Front-End Receiver in 90 nm CMOS for IEEE 802.15.4 WPAN Standard
A fully integrated inductor-based 1.8-6-V step-up converter
A CMOS High-Power Broadband 260-GHz Radiator Array for Spectroscopy
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology
A Pulse Shaping Technique for Spur Suppression in Injection-Locked Synthesizers
A 200µs Processing Time Smart Image Sensor for an Eye Tracker Using Pixel-Level Analog Image Processing
A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS
Integrated mixed-mode digital-analog filter converters
A Chopper Class-D Amplifier for PSRR Improvement Over the Entire Audio Band
Compensation Pixel Circuit to Improve Image Quality for Mobile AMOLED Displays
A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μ m CMOS
A 13-b Linear, 40-MS/s Pipelined ADC With Self-Configured Capacitor Matching
Introduction to the Special Section on the 2016 IEEE BCTM and IEEE CSICS
A 20b Clockless DAC With Sub-ppm INL, 7.5 nV/√Hz Noise and 0.05 ppm/°C Stability
Noise in digital dynamic CMOS circuits
A 73.8k-Inference/mJ SVM Learning Accelerator for Brain Pattern Recognition
A low-output-impedance fully differential op amp with large output swing and continuous-time common-mode feedback
A 0.22-mm 2 7.25-mW per-channel audio stereo-DAC with 97-dB DR and 39-dB SNR out
A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache
A Continuous-Time 0-3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS
A high-speed CMOS image sensor with profile data acquiring function
A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing
A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation
Multiple-Loop Design Technique for High-Performance Low-Dropout Regulator
Design and implementation of a switched-current memory cell for low-power and weak-current operations
A Fully Integrated, Domino-Like-Buffered LDO Regulator With High Power-Supply Rejection Across the Full Frequency Spectrum
Design of On-Chip Gate Drivers With Power-Efficient High-Speed Level Shifting and Dynamic Timing Control for High-Voltage Synchronous Switching Power Converters
I.McIC: a single-chip MPEG-2 video encoder for storage
Low-power CMOS/BiCMOS drivers and receivers for on-chip interconnects
Intrinsic 1/f device noise reduction and its effect on phase noise in CMOS ring oscillators
A 2-V 23-μA 5.3-ppm/°C curvature-compensated CMOS bandgap voltage reference
CMOS Smart Sensor for Monitoring the Quality of Perishables
Noise margin enhancement in GaAs ROM's using current mode logic
A 0.18-μm CMOS IA-32 processor with a 4-GHz integer execution unit
Analytical model for switching transitions of submicron CMOS logics
Performance degradation of LC-tank VCOs by impact of digital switching noise in lightly doped substrates
A 94.9% Efficiency Always-Power-Delivered SIDO Buck Converter With Continuous Current Balancing and Complementary Adaptive-Switching Regulation
A closed-form delay expression for digital BiCMOS circuits with high-injection effects
A CMOS 110-dB@40-kS/s programmable-gain chopper-stabilized third-order 2-1 cascade sigma-delta Modulator for low-power high-linearity automotive sensor ASICs
Present and future directions for multichip module technologies
A Multimode 157 μW 4-Channel 80 dBA-SNDR Speech Recognition Frontend With Direction-of-Arrival Correction Adaptive Beamformer
A low-noise fast-lock phase-locked loop with adaptive bandwidth control
A Phase-Domain Readout Circuit for a CMOS-Compatible Hot-Wire CO 2 Sensor
An EEG-NIRS Multimodal SoC for Accurate Anesthesia Depth Monitoring
Low-noise photodiode-amplifier circuit
A single-chip false target radar image generator for countering wideband imaging radars
Fast CMOS ECL receivers with 100-mV worst-case sensitivity
A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation
A 1.1-mW Ground Effect-Resilient Body-Coupled Communication Transceiver With Pseudo OFDM for Head and Body Area Network
A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL
A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS
Indirect current feedback instrumentation amplifier with a common-mode input range that includes the negative roll
A Radio Frequency Analog Computer for Computational Electromagnetics
A 10-Bit LCD Column Driver With Piecewise Linear Digital-to-Analog Converters
An Area-Efficient Smart Temperature Sensor Based on a Fully Current Processing Error-Feedback Noise-Shaping SAR ADC in 180-nm CMOS
A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmission
Design and application of CMOS bulk input scheme
A 12-b 750-ns subranging A/D converter with self-correcting S/H
Limitation of CMOS supply-voltage scaling by MOSFET threshold-voltage variation
A BiCMOS speech circuit with only two external components
Analysis and compact modeling of a vertical grounded-base n-p-n bipolar transistor used as ESD protection in a smart power technology
A $7\times7\times2$ mm 3 8.6- $\mu$ W 500-kb/s Transmitter With Robust Injection-Locking-Based Frequency-to-Amplitude Conversion Receiver Targeting for Implantable Applications
A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, Ultra Low Leakage Power Memory Using Dynamic Cell Stability and a Dual Swing Data Link
A 40-Gbit/s superdynamic decision IC fabricated with 0.12-μm GaAs MESFET's
A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping
CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography
A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS
A high-speed CMOS comparator for use in an ADC
A multirate transceiver IC for four-wire full-duplex data transmission
Low-voltage, high-speed circuit designs for gigabit DRAMs
A 27 mW Reconfigurable Marker-Less Logarithmic Camera Pose Estimation Engine for Mobile Augmented Reality Processor
280-GHz Frequency Multiplier Chains in 250-nm InP HBT Technology
A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit
A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS
A Portable Wideband CMOS NMR Spectrometer for Multinuclear Molecular Fingerprinting
Introduction to the Special Issue on the First IEEE Compound Semiconductor Integrated Circuits Symposium (CSICS)
A Fully Integrated 135-GHz Direct-Digital 16-QAM Wireless and Dielectric Waveguide Link in 28-nm CMOS
An All-Digital 12 pJ/Pulse IR-UWB Transmitter Synthesized From a Standard Cell Library
Multi-Standard Mobile Broadcast Receiver LNA With Integrated Selectivity and Novel Wideband Impedance Matching Technique
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators
SRAM cell stability under the influence of parasitic resistances and data holding voltage as a stability prober
A 10.8 mW Body Channel Communication/MICS Dual-Band Transceiver for a Unified Body Sensor Network Controller
Compact PNP BJT-Based Temperature Sensor and Sub-1-V Bandgap Reference for SoC Applications in 4-nm FinFET
A refreshable analog VLSI neural network chip with 400 neurons and 40 K synapses
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS
A Scalable Multiphase Current-Mode Buck Controller With Sub-Milliohm DCR Current Sensing and Synchronized Overcurrent Protection
A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier
Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and ∓50 ps jitter
An All-Digital Fused PLL-Buck Architecture for 82% Average V dd -Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor
A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power- and Area-Efficient PLL for Impulse Radio UWB Receiver
AC-Coupled Stacked Dual-Active-Bridge DC-DC Converter for Integrated Lithium-Ion Battery Power Delivery
A floating CMOS bandgap voltage reference for differential applications
A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits
A Highly Linear SAW-Less CMOS Receiver Using a Mixer With Embedded Tx Filtering for CDMA
High-performance microprocessor design
A 1.5-V 12-bit power-efficient continuous-time third-order ΣΔ modulator
Bipolar transistor epilayer design using the MAIDS mixed-level simulator
A single-stage variable-gain amplifier with 70-dB dynamic range for CDMA2000 transmit applications
Fault characterization, testing considerations, and design for testability of BiCMOS logic circuits
A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS
A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET
A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems
Switched-current memory circuits for high-precision applications
A High-Resolution Low-Power Incremental Sigma Delta ADC With Extended Range for Biosensor Arrays
A 533-MHz BiCMOS superscalar RISC microprocessor
A 4.13-GHz UHS Pseudo Two-Port SRAM With BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4-nm FinFET Technology
A 13.56 MHz 40 mW CMOS High-Efficiency Inductive Link Power Supply Utilizing On-Chip Delay-Compensated Voltage Doubler Rectifier and Multiple LDOs for Implantable Medical Devices
A high-frequency and high-resolution fourth-order ΣΔ A/D converter in BiCMOS technology
A Dual-Alternating-Slope Digital-to-Time Converter Leveraging Mismatch to Improve Delay Step Size
A multiply-by-3 coupled-ring oscillator for low-power frequency synthesis
A Low-Power 256-Element Ka-Band CMOS Phased-Array Receiver With On-Chip Distributed Radiation Sensors for Small Satellite Constellations
A total solution for a 9600-b/s modem transmitter chip
A Phase Domain Approach for Mitigation of Self-Interference in Wireless Transceivers
A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision Keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM
Integrated pin electronics for VLSI functional testers
VISTA: A Memory-Efficient CNN Processor for Video and Image Spatial/Temporal Interpolation Acceleration
OTA-Free 1-1 MASH ADC Using Fully Passive Noise-Shaping SAR & VCO ADC
A 200 MHz quadrature digital synthesizer/mixer in 0.8 μm CMOS
An Energy-Efficient Unstructured Sparsity-Aware Deep SNN Accelerator With 3-D Computation Array
Novel CMOS image sensor with a 132-dB dynamic range
Xetal-II: A 107 GOPS, 600 mW Massively Parallel Processor for Video Scene Analysis
A Pitch-Matched Front-End ASIC With Integrated Subarray Beamforming ADC for Miniature 3-D Ultrasound Probes
An auto-ranging photodiode preamplifier with 114 dB dynamic range
A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V min Lowering Techniques and Deep Sleep Mode
A Switched-Capacitor RF Front End With Embedded Programmable High-Order Filtering
A 5-V front-end chip for a universal voice-band modem
A 14-b BW /Power Scalable Sensor Interface With a Dynamic Bandgap Reference
Introduction to the Special Issue on the IEEE 2014 Custom Integrated Circuits Conference
A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition
Comments on 'In-place updating of path metrics in Viterbi decoders'
A DLL-Based Programmable Clock Multiplier in 0.18-µm CMOS With -70 dBc Reference Spur
Study of Subharmonically Injection-Locked PLLs
A 200-µV/e - CMOS Image Sensor With 100-ke - Full Well Capacity
MOSFET-C filter, with low excess noise and accurate automatic tuning
Using cache mechanisms to exploit nonrefreshing DRAMs for on-chip memories
A 1.3-ns 32-word×32-bit three-port BiCMOS register file
Improved implementation of the silicon cochlea
Low-power and high-speed ROM modules for ASIC applications
A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC
Multi-Level Amplitude Modulation of a 16.8-GHz Class-E Power Amplifier With Negative Resistance Enhanced Power Gain for 400-Mbps Data Transmission
A single-chip 9-32 mb/s read/write channel for disk-drive applications
A 70-MHz 1.2- mu m CMOS 16-point DFT processor
Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks
Low-Power Organic Light Sensor Array Based on Active-Matrix Common-Gate Transimpedance Amplifier on Foil for Imaging Applications
A 112-Gb/s PAM-4 Voltage-Mode Transmitter With Four-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40-nm CMOS
Low-voltage class AB buffers with quiescent current control
A Large-Swing Transformer-Boosted Serial Link Transmitter With > V DD Swing
High Dynamic Range CMOS Imager Technologies for Biomedical Applications
A 2 W CMOS Hybrid Switching Amplitude Modulator for EDGE Polar Transmitters
A 5.2-GHz CMOS receiver with 62-dB image rejection
Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers
A two-path bandpass sigma-delta modulator with extended noise shaping
A 94 GHz 3D Image Radar Engine With 4TX/4RX Beamforming Scan Technique in 65 nm CMOS Technology
A high-performance, low-power complementary coupled BiCMOS circuit
A 5 V only one-transistor 256 K EEPROM with page-mode erase
A 26-GΩ Input-Impedance 112-dB Dynamic-Range Two-Step Direct-Conversion Front-End With Improved Δ-Modulation for Wearable Biopotential Acquisition
An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers
A single-chip universal cable set-top box/modem transceiver
Divide-by-Three Injection-Locked Frequency Dividers Over 200 GHz in 40-nm CMOS
A Flying-Inductor Hybrid DC-DC Converter for 1-Cell and 2-Cell Smart-Cable Battery Chargers
A 65-nm Sub-10-mW Communication/Ranging Quadrature Uncertain-IF IR-UWB Transceiver With Twin-OOK Modulation
A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN
A 3.1 mW Continuous-Time ΔΣ Modulator With 5-Bit Successive Approximation Quantizer for WCDMA
Complex 3D CMOS circuits based on a triple-decker cell
DIMCA: An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate Arithmetic Hardware in 28 nm
A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS
A 10 Gb/s 45 mW Adaptive 60 GHz Baseband in 65 nm CMOS
A Pulsed UWB Receiver SoC for Insect Motion Control
A mixed-signal RAM decision-feedback equalizer for disk drives
A 0.5° Error 10 mW CMOS Image Sensor-Based Gaze Estimation Processor
A 9.6-Gb/s HEMT ATM switch LSI with event-controlled FIFO
A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell
A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique
An Agile VCO Frequency Calibration Technique for a 10-GHz CMOS PLL
A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3 < -58 dBc in 40 nm CMOS
A 1.25-Gb/s CMOS burst-mode optical transceiver for ethernet PON system
Computational sensor for visual tracking with attention
A ±4-A High-Side Current Sensor With 0.9% Gain Error From -40 °C to 85 °C Using an Analog Temperature Compensation Technique
An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture
Integrated RF components in a SiGe bipolar technology
A PVT-Tolerant >40-dB IRR, 44% Fractional-Bandwidth Ultra-Wideband mm-Wave Quadrature LO Generator for 5G Networks in 55-nm CMOS
A Passive Mixer-First Receiver With Digitally Controlled and Widely Tunable RF Interface
A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer
SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling
An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access
A 1.2-V low-power BiCMOS class AB log-domain filter
Physics-based closed-form inductance expression for compact modeling of integrated spiral inductors
A 65-nm 10-Gb/s 10-mm On-Chip Serial Link Featuring a Digital-Intensive Time-Based Decision Feedback Equalizer
A 640-ps, 0.25-μm CMOS, 16×64-b three-port register file
Design of Single-Topology Continuously Scalable-Conversion-Ratio Switched- Capacitor DC-DC Converters
A direct digital period synthesis circuit
A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique
Comments on "A 4th-Order Active- G m -RC Reconfigurable (UMTS/WLAN) Filter"
A 32 Gb/s Bidirectional 4-channel 4 pJ/b Capacitively Coupled Link in 14 nm CMOS for Proximity Communication
A 7-Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS
A 2-V 7.2° jitter AM-suppression CMOS amplifier using current-mode hybrid magnitude control
A Current-Feedback Instrumentation Amplifier With a Gain Error Reduction Loop and 0.06% Untrimmed Gain Error
A 100- to- 10-kHz 5.4- to- 216- μW Power-Efficient Readout Circuit Employing Closed-Loop Dynamic Amplifier for MEMS Capacitive Accelerometer
A 100-Gb/s PAM-4 Optical Receiver With 2-Tap FFE and 2-Tap Direct-Feedback DFE in 28-nm CMOS
A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance
An External Capacitorless Low-Dropout Regulator With High PSR at All Frequencies From 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique
A 300-MHz 64-b quad-issue CMOS RISC microprocessor
PWM-Based Impedance Boosting Technique With Autonomous Background Calibration for VCO-Based Neural Front Ends
Measurement of digital noise in mixed-signal integrated circuits
A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal
A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS
Half-swing clocking scheme for 75% power saving in clocking circuitry
Bus architecture of a system on a chip with user-configurable system logic
Introduction to the December Special Issue on the 2016 IEEE International Solid-State Circuits Conference
A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications
A transistor-only low-pass filter with adjustable bias and small phase shift at high frequencies
A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-μm CMOS technology
Introduction to the Special Section on the 2022 Asian Solid-State Circuits Conference (A-SSCC)
A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step
A 4.6 μW, 133-V PP Common-Mode Interference-Tolerant Biopotential Amplifier for Two-Electrode Recording System in 110-nm CMOS
DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET
Wideband Dual-Injection Path Self-Interference Cancellation Architecture for Full-Duplex Transceivers
CMOS analog MAP decoder for (8, 4) Hamming code
DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers
A PLL-based frequency synthesizer for 160-MHz double-sampled SC filters
A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS
A Floating-Gate-Based Field-Programmable Analog Array
Clockless, Continuous-Time Analog Correlator Using Time-Encoded Signal Processing Demonstrating Asynchronous CDMA for Wake-Up Receivers
An 18.24-Gb/s, 0.93-pJ/bit Receiver With an Input-Level-Sensing CDR Using Clock-Embedded C-PHY Signaling Over Trio Wires
A 46-ns 1-Mbit CMOS SRAM
A 10 Gb/s AlGaAs/GaAs HBT high power fully differential limiting distributed amplifier for III-V Mach-Zehnder modulator
Highly Integrated ZVS Flyback Converter ICs With Pulse Transformer to Optimize USB Power Delivery for Fast-Charging Mobile Devices
Generating all two-MOS-transistor amplifiers leads to new wide-band LNAs
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control
SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect
A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-µm CMOS for Nonvolatile Processing in Digital Systems
A 320-fs RMS Jitter and - 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC
An Ultra Low Power Bandgap Operational at Supply From 0.75 V