yusuke1997/dblp-id-title huggingface dataset:
An Automated Meta-Level Control Framework for Optimizing the Quality-Time Tradeoff of VLSI Algorithms
On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits
Linear Programming-Based Optimization for Robust Data Modeling in a Distributed Sensing Platform
Floating-point behavioral synthesis
Multiscale Thermal Analysis for Nanometer-Scale Integrated Circuits
Reversible Circuit Optimization Via Leaving the Boolean Domain
Diagnosis of clustered faults for identical degree topologies
An FPGA-Based Hardware Emulator for Neuromorphic Chip With RRAM
A Survey and Evaluation of FPGA High-Level Synthesis Tools
Optimal clock period clustering for sequential circuits with retiming
Increasing encoding efficiency of LFSR reseeding-based test compression
Coupling-aware high-level interconnect synthesis [IC layout]
A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis
Is redundancy necessary to reduce delay?
An analytical model for the aliasing probability in signature analysis testing
Synthesis of Hardware for the Control of Digital Systems
Circuit Theory of Time Domain Adjoint Sensitivity
Computing the initial states of retimed circuits
Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing
A method of fault analysis for test generation and fault diagnosis
PreSIT: Predict Cryptography Computations in SGX-Style Integrity Trees
Process-Based Three-Dimensional Capacitance Simulation -- TRICEPS
FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction
Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation
A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures
Analog Building Blocks Optimization for Low-Pass Filter of IEEE 802.11n Wireless LAN: OTA and CCII
Fast Verification of Guide-Patterns for Directed Self-Assembly Lithography
3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip
SCAR: Security Compliance Analysis and Resynthesis of Reconfigurable Scan Networks
Access Characteristic Guided Partition for Nand Flash-Based High-Density SSDs
Non-tree routing [VLSI layout]
Energy-Efficient Spintronic-Based Neuromorphic Computing System Using Current Mode Track and Termination Circuit
Spatial Timing Analysis With Exact Propagation of Delay and Application to FPGA Performance
On estimation accuracy for guiding low-power resynthesis
Timing optimization of multiphase sequential logic
MPFA: An Efficient Multiple Faults-Based Persistent Fault Analysis Method for Low-Cost FIA
Obfuscated Built-In Self-Authentication With Secure and Efficient Wire-Lifting
A Hierarchy-Driven Amalgamation of Standard and Macro Cells
Quantum KNN Classification With K Value Selection and Neighbor Selection
Generating Routing-Driven Power Distribution Networks With Machine-Learning Technique
Improved algorithmic methods for the prediction of wavefront propagation behavior in multiconductor transmission lines for high frequency digital signal processors
N-channel MOSFET model for the 60-300-K temperature range
DYTEST: a self-learning algorithm using dynamic testability measures to accelerate test generation
MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems
Combining Image Processing and Laser Fault Injections for Characterizing a Hardware AES
Fast and Optimal Redundant Via Insertion
Static Test Compaction Using Independent Suffixes of a Transparent-Scan Sequence
On Device Modeling for Circuit Simulation With Application to Carbon-Nanotube and Graphene Nano-Ribbon Field-Effect Transistors
Multilevel Full-Chip Routing With Testability and Yield Enhancement
Alphabetic trees-theory and applications in layout-driven logicsynthesis
Placement Algorithm in Analog-Layout Designs
Multilayer Global Routing With Via and Wire Capacity Considerations
Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise
On the circuit implementation problem
Slack in static timing analysis
An efficient and regular routing methodology for datapath designsusing net regularity extraction
Semihiding operators and active-edge specification
Robustness Analysis for Droplet-Based Microfluidic Networks
MAID-Q: Minimizing Tail Latency in Embedded Flash With SMR Disk via -Learning Model
Improving the Accuracy of Defect Diagnosis by Considering Fewer Tests
A Machine Learning-Powered Tier Partitioning Methodology for Monolithic 3-D ICs
Long and short covering edges in combination logic circuits
Modeling and synthesis of multiport transmission line for multichannel communication
Dynamic testability measures for ATPG
NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing
A Low Power Reconfigurable Memory Architecture for Complementary Resistive Switches
A CAD methodology for optimizing transistor current and sizing in analog CMOS design
Archer: A History-Based Global Routing Algorithm
General skew constrained clock network sizing based on sequential linear programming
Hitting Time Analysis for Fault-Tolerant Communication at Nanoscale in Future Multiprocessor Platforms
Does Qubit Connectivity Impact Quantum Circuit Complexity?
SALSA: a new approach to scheduling with timing constraints
An O(n log m) algorithm for VLSI design rule checking
Enabling On-Device CNN Training by Self-Supervised Instance Filtering and Error Map Pruning
Pplace-MS: Methodologically Faster Poisson's Equation-Based Mixed-Size Global Placement
Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks
z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs
Scaling Attacks on Large Logic-Locked Designs
Noise-rejection model based on charge-transfer equation for digital CMOS circuits
Layer Sequence Extraction of Optimized DNNs Using Side-Channel Information Leaks
Close-to-Functional Broadside Tests With a Safety Margin
Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods
On the performance bounds for a class of rectilinear Steiner tree heuristics in arbitrary dimension
DEVoT: Dynamic Delay Modeling of Functional Units Under Voltage and Temperature Variations
Thwarting Replication Attack Against Memristor-Based Neuromorphic Computing System
Distributed genetic algorithms for the floorplan design problem
An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints
Simulation of charge transfer in GaAs Cermet-Gate CCDs
Nearly-2-SAT Solutions for Segmented-Channel Routing
Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor
ZoneLife: How to Utilize Data Lifetime Semantics to Make SSDs Smarter
Energy-Aware Real-Time Scheduling of Multiple Periodic DAGs on Heterogeneous Systems
An Automatic Neural Network Architecture-and-Quantization Joint Optimization Framework for Efficient Model Inference
AARF: Any-Angle Routing for Flow-Based Microfluidic Biochips
Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits
Efficient Analog Error Correction for Printed Unary-Encoded Computing
Energy-Aware Heterogeneous Federated Learning via Approximate DNN Accelerators
Floorplan Design for Multimillion Gate FPGAs
Improving DNN Accuracy on MLC PIM via Non-Ideal PIM Device Fine-Tuning
Engineering change protocols for behavioral and system synthesis
BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC
Pad Assignment for Power Nets in VLSI Circuits
A Metric for Identifying Detectable Path Delay Faults
LayoutCopilot: An LLM-Powered Multiagent Collaborative Framework for Interactive Analog Layout Design
Quasi-static scheduling of independent tasks for reactive systems
Temperature Aware Dynamic Workload Scheduling in Multisocket CPU Servers
A weighted Steiner tree-based global router with simultaneous length and density minimization
XMAP: Programming Memristor Crossbars for Analog Matrix-Vector Multiplication: Toward High Precision Using Representable Matrices
PRIDE: an integrated design environment for semiconductor device simulation
Estimation of power dissipation using a novel power macromodelingtechnique
IC thermal simulation and modeling via efficient multigrid-based approaches
A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms
Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs
An efficient CMOS bridging fault simulator: with SPICE accuracy
HyCTor: A Hybrid CNN-Transformer Network Accelerator With Flexible Weight/Output Stationary Dataflow and Multicore Extension
Delay fault coverage, test set size, and performance trade-offs
Hierarchical Steiner tree construction in uniform orientations
Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale
SubIslands: the probabilistic match assignment algorithm for subcircuit recognition
Design error diagnosis and correction via test vector simulation
Resolution, optimization, and encoding of pointer variables for thebehavioral synthesis from C
Multilabel Deep Learning-Based Side-Channel Attack
Pearl: Performance-Aware Wear Leveling for Nonvolatile FPGAs
CNN-Oriented Placement Algorithm for High-Performance Accelerators on Rad-Hard FPGAs
Padding of LFSR Seeds for Reduced Input Test Data Volume
CIM²PQ: An Arraywise and Hardware-Friendly Mixed Precision Quantization Method for Analog Computing-In-Memory
Fast Electromigration Immortality Analysis for Multisegment Copper Interconnect Wires
An automatic biasing scheme for tracing arbitrarily shaped I-V curves
A Highly Compressed Accelerator With Temporal Optical Flow Feature Fusion and Tensorized LSTM for Video Action Recognition on Terminal Device
A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis
Assessing the Potential of Escalating RowHammer Attack Distance to Bypass-Counter-Based Defenses
Harvesting Design Knowledge From the Internet: High-Dimensional Performance Tradeoff Modeling for Large-Scale Analog Circuits
Fault simulation and test algorithm generation for random accessmemories
Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling
Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling
Pseudorandom number generation with self-programmable cellular automata
Efficient Variation-Aware Delay Fault Simulation Methodology for Resistive Open and Bridge Defects
Timing analysis speed-up using a hierarchical and a multimode approach
A parallel fast Fourier transform on multipoles (FFTM) algorithm for electrostatics analysis of three-dimensional structures
Boundary fitted coordinated generation for device analysis on composite and complicated geometries
QuBEC: Boosting Equivalence Checking for Quantum Circuits With QEC Embedding
Application of IP-Based Analog Platforms in the Design of Neuromimetic Integrated Circuits
A traveling-wave-based waveform approximation technique for thetiming verification of single transmission lines
Circuit structure relations to redundancy and delay
MiniControl 2.0: Co-Synthesis of Flow and Control Layers for Microfluidic Biochips With Strictly Constrained Control Ports
An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors
On the Deployment of On-Chip Noise Sensors
A Novel Low-Power Compression Scheme for Systolic Array-Based Deep Learning Accelerators
Software-based self-testing methodology for processor cores
A Global Maximum Error Controller-Based Method for Linearization Point Selection in Trajectory Piecewise-Linear Model Order Reduction
MOS table models for circuit simulation
LILA: layout generation for iterative logic arrays
A transformational approach to synthesizing combinational circuits
Robust and Efficient RTL to C Compiler Optimized for High-Level Synthesis
Testing Chips With Spare Identical Cores
Temperature measurement and equilibrium dynamics of simulated annealing placements
A preprocessor for improving channel routing hierarchical pin permutation
A timing model incorporating the effect of crosstalk on delay andits application to optimal channel routing
A Verification Framework for Time-Triggered Networks Based on Timed Colored Petri Net
YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration
Switch-level simulation of total dose effects on CMOS VLSI circuits
Unified and Scalable Digit-Serial Systolic Array for Multiplication and Division Over GF (2m)
A Combined N/PFET CFET-Based Design and Logic Technology Framework for CMOS Applications
Process variation effects on circuit performance: TCAD simulation of 256-Mbit technology [DRAMs]
High-precision interconnect analysis
On optimal board-level routing for FPGA-based logic emulation
NeuroScrub+: Mitigating Retention Faults Using Flexible Approximate Scrubbing in Neuromorphic Fabric Based on Resistive Memories
POSET timing and its application to the synthesis and verification of gate-level timed circuits
2Deep: Enhancing Side-Channel Attacks on Lattice-Based Key-Exchange via 2-D Deep Learning
EARTH: combined state assignment of PLA-based FSM's targeting area and testability
DRDebug: Automated Design Rule Debugging
Fast on-chip inductance simulation using a precorrected-FFT method
Improved Mapping of Quantum Circuits to IBM QX Architectures
Test synthesis of systems-on-a-chip
Broadcast Electrode-Addressing and Scheduling Methods for Pin-Constrained Digital Microfluidic Biochips
Behavioral optimization using the manipulation of timing constraints
Modeling of the MOS transistor for high frequency analog design
An Efficient Test Scheduling Method Based on Dynamic Pairing
On correction of multiple design errors
Rotation scheduling: a loop pipelining algorithm
PISCES-MC: a multiwindow, multimethod 2-D device simulator
Performance analysis and optimization of mixed asynchronous synchronous systems
Bit-Width Allocation for Hardware Accelerators for Scientific Computing Using SAT-Modulo Theory
LoCoMOBO: A Local Constrained Multiobjective Bayesian Optimization for Analog Circuit Sizing
Utilization of vacant terminals for improved over-the-cell channel routing
Slicing floorplans with boundary constraints
Comments on 'O(n 2 ) algorithms for graph planarization'
RC delay metrics for performance optimization
Fast true delay estimation during high level synthesis
Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits
Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions
Retiming revisited and reversed
Leak Point Locating in Hardware Implementations of Higher-Order Masking Schemes
Volume Reduction and Fast Generation of the Precharacterization Data for Floating Random Walk-Based Capacitance Extraction
Addressing Sparsity in Deep Neural Networks
PhGraph: A High-Performance ReRAM-Based Accelerator for Hypergraph Applications
Flux Controlled Floating Memristor Employing VDTA: Incremental or Decremental Operation
Power-Aware Delay Test Quality Optimization for Multiple Frequency Domains
Statistical interconnect metrics for physical-design optimization
Pulsed-Latch Replacement Using Concurrent Time Borrowing and Clock Gating
On the skew-bounded minimum-buffer routing tree problem
RuleLearner: OPC Rule Extraction From Inverse Lithography Technique Engine
Timing Yield-Aware Color Reassignment and Detailed Placement Perturbation for Bimodal CD Distribution in Double Patterning Lithography
A novel behavioral testability measure
Externally hazard-free implementations of asynchronous control circuits
Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs
A Lightweight Full Entropy TRNG With On-Chip Entropy Assurance
Computation of signal-threshold crossing times directly from higher order moments
A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips
Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing
A mobility model including the screening effect in MOS inversion layer
Fault emulation: A new methodology for fault grading
Inclusion of Chemical-Mechanical Polishing Variation in Statistical Static Timing Analysis
Global flow optimization in automatic logic design
A new method for floor planning using topological constraint reduction
Hardware Trojan Detection Using Backside Optical Imaging
Synthesis of Tile Sets for DNA Self-Assembly
Net Cluster: A Net-Reduction-Based Clustering Preprocessing Algorithm for Partitioning and Placement
Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk
An MIV Test Method Using High-Precision Voltage Dividers
An Explicit Linearized State-Space Technique for Accelerated Simulation of Electromagnetic Vibration Energy Harvesters
Counterexample Ranking Using Mined Invariants
Concurrent Generation of Concurrent Programs for Post-Silicon Validation
Exploring Renewable-Adaptive Computation Offloading for Hierarchical QoS Optimization in Fog Computing
Resource allocation for coarse-grain FPGA development
A Low-Cost Floating-Point Dot-Product-Dual-Accumulate Architecture for HPC-Enabled AI
Concurrent error correction in systolic architectures
A Tile-Expansion Router
Digital ground bounce reduction by supply current shaping and clock frequency Modulation
Stability and Convergency Exploration of Matrix Exponential Integration on Power Delivery Network Transient Simulation
Large-Scale Quantum Approximate Optimization via Divide-and-Conquer
Unified Wear-Leveling Technique for NVM-Based Buffer of SSD
A path-oriented algorithm for the cell selection problem
A Unified Theory of Timing Budget Management
BDD minimization by scatter search
Single-Pass: An Operation Unit-Based In-Memory Computing Architecture for Sparse Neural Networks
Clock-Aware Placement for Large-Scale Heterogeneous FPGAs
Parametric yield formulation of MOS IC's affected by mismatch effect
Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA
Evaluating Pulling Effects in Oscillators Due to Small-Signal Injection
Intractability in linear switch-level simulation
FireFly v2: Advancing Hardware Support for High-Performance Spiking Neural Network With a Spatiotemporal FPGA Accelerator
Efficient Retiming of Multirate DSP Algorithms
A Simple Yet Effective Technique for Global Wiring
A New Design-Centering Methodology for VLSI Device Development
Criticality-Aware EDF Scheduling for Constrained-Deadline Imprecise Mixed-Criticality Systems
An algorithm for identifying unstable operating points using SPICE
Transient sensitivity computation in controlled explicit piecewiselinear simulation
Substrate optimization based on semi-analytical techniques
A technique for micro-rollback self-recovery synthesis
POFGSP: Priority-Based Out-of-Order Scheduling and Fine-Grain Status Polling for SSD Performance Improvement
Delay time sensitivity in nonlinear monotone RC trees
Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures
The SAT Attack on IC Camouflaging: Impact and Potential Countermeasures
On an improved design approach for C-testable orthogonal iterative arrays
Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay Modeling
Broadside Tests for Transition and Stuck-At Faults
Weibull-based analytical waveform model
Defect-Oriented Test: Effectiveness in High Volume Manufacturing
A Methodology for Constraint-Driven Synthesis of On-Chip Communications
Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs
Circuit and Methodology for Testing Small Delay Faults in the Clock Network
Logic BIST With Capture-Per-Clock Hybrid Test Points
Parallel global routing for standard cells
Computation of floating mode delay in combinational circuits: theory and algorithms
Nostradamus: a floorplanner of uncertain designs
A High-Efficiency Design Method of TSV Array for Thermal Management of 3-D Integrated System
Peak-Power-Aware Energy Management for Periodic Real-Time Applications
Fast Statistical Analysis of Rare Failure Events With Truncated Normal Distribution in High-Dimensional Variation Space
An integrated device design environment for semiconductors
Four-Valued Reasoning and Cyclic Circuits
Efficient Op Amp Circuit Analysis with Manufacturer Specified Macromodel Parameters
Accelerating relaxation algorithms for circuit simulation using waveform-Newton and step-size refinement
A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors
Modeling of multiconductor systems for packaging and interconnecting high-speed digital IC's
Test Chips With Scan-Based Logic Arrays
Efficient state classification of finite-state Markov chains
Economic Analysis of Testing Homogeneous Manycore Chips
Applying simulated evolution to high level synthesis
Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains
Table-based modeling of delta-sigma modulators using ZSIM
Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications
Simultaneous Layout Migration and Decomposition for Double Patterning Technology
Quantifying Information Leakage for Security Verification of Compiler Optimizations
Generalization of Yield Optimization Problem: Maximum Income Approach
Event-Driven Time-Domain Simulation of Closed-Loop Switched Circuits
A Novel CNN-Based Redundancy Analysis Using Parallel Solution Decision
A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections
Self-Aligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment
Handling Stuck-at-Fault Defects Using Matrix Transformation for Robust Inference of DNNs
Herringbone-Based TSV Architecture for Clustered Fault Repair and Aging Recovery
Design representation in Movie
Highly accurate and simple models for CML and ECL gates
Image Edge Detection Based on Swarm Intelligence Using Memristive Networks
High-level test compaction techniques
An Integrated High-Level On-Line Test Synthesis Tool
Analytical yield prediction considering leakage/performance correlation
Simulating Resistive-Bridging and Stuck-At Faults
Two-Stage Newton-Raphson Method for Transistor-Level Simulation
Rapid Analysis of Active Cell Balancing Circuits
Heuristic minimization of multiple-valued relations
A new multilevel Green's function interpolation method for large-scale low-frequency EM simulations
Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems
Techniques for minimizing and balancing I/O during functional partitioning
Defect Tolerance Based on Graceful Degradation and Dynamic Reconfiguration for Digital Microfluidics-Based Biochips
GRAND: A Graph Neural Network Framework for Improved Diagnosis
An Automated Quantization Framework for High-Utilization RRAM-Based PIM
Improving Diagnostic Resolution of Failing ICs Through Learning
Optimizing Sequential Cycles Through Shannon Decomposition and Retiming
Algorithms for technology mapping based on binary decision diagrams and on Boolean operations
Reaching the Limit of Nonprofiling DPA
Time-Scalable Mapping for Circuit-Switched GALS Chip Multiprocessor Platforms
SDP: Co-Designing Algorithm, Dataflow, and Architecture for In-SRAM Sparse NN Acceleration
A unified framework for generating all propagation functions for logic errors and events
Current-Aware Flash Scheduling for Current Capping in Solid State Disks
Efficient symbolic simulation-based verification using the parametric form of Boolean expressions
LAYGEN II - Automatic Layout Generation of Analog Integrated Circuits
Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars
Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation
IMGA: Efficient In-Memory Graph Convolution Network Aggregation With Data Flow Optimizations
Multiway partitioning via geometric embeddings, orderings, and dynamic programming
Three-dimensional simulation of HPCVD-linking continuum transport and reaction kinetics with topography simulation
ChainPIM: A ReRAM-Based Processing-in-Memory Accelerator for HGNNs via Chain Structure