yusuke1997/dblp-id-title huggingface dataset:
Two High-Bandwidth Memory Bus Structures
A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec
Guest Editors' Introduction: Opportunities and Challenges of 3D Integration
Can Dark Silicon Be Exploited to Prolong System Lifetime?
Verifying a Multiprocessor Cache Controller Using Random Test Generation
Effective silicon debug is key for time to money
Embedded Systems Week
Design for Testability for Complete Test Coverage
Implications of On-Chip Single-Source Clocking on High-Speed Serial Interfaces in Network SoC
Furthering Moore's Law Integration Benefits in the Chiplet Era
Fundamental Timing Problems in Testing MOS VLSI on Modern ATE
Special Issue on 20 Years of IEEE CEDA
Fault-Tolerant Neural Network Accelerators With Selective TMR
Energy Efficiency in 5G Cellular Network Systems
Natural-Language Interface for CAD: A First Step
Object Programming for CAD
A Metric to Target Small-Delay Defects in Industrial Circuits
Automatic Generation of Digital System Schematic Diagrams
An Automatic Controller Extractor for HDL Descriptions at the RTL
Guest Editors' Introduction: DRAM Architecture and Testing
Spin-Based Reconfigurable Logic for Power- and Area-Efficient Applications
A D&T Roundtable: Test Economics
Accellera's Support for ESL Verification and Stimulus Reuse
Dependable Multicore Architectures at Nanoscale: The View From Europe
Incremental Verification with Error Detection, Diagnosis, and Visualization
Fast-Yet-Accurate Statistical Soft-Error-Rate Analysis Considering Full-Spectrum Charge Collection
Integrating Online and Offline Testing of a Switching Memory
Challenges and Trends in Modern SoC Design Verification
Power-Aware Designers at Odds with Power Grid Designers?
A 3-D Forward into the Past
A Reconfiguration Manager for Dynamically Reconfigurable Hardware
The DFT Psychic Network
Leakage Minimization Technique for Nanoscale CMOS VLSI
In-System Silicon Validation and Debug
A single-row transformation technique
Guest Editors' Introduction: Design for Yield and Reliability
Guest Editors' Introduction: Cloud Computing for Embedded Systems
Speeding Up Analog Integration and Test for Mixed-Signal SoCs
Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems
Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement
Edge Intelligence - On the Challenging Road to a Trillion Smart Connected IoT Devices
Accuracy-Configurable 2-D Gaussian Filter Architecture for Energy-Efficient Image Processing
VHDL as Input for High-Level Synthesis
The First Transaction, but not the Last
Reducing Burn-in Time through High-Voltage Stress Test and Weibull Statistical Analysis
GLU3.0: Fast GPU-based Parallel Sparse LU Factorization for Circuit Simulation
Chips Thinking About Chips
PROD: A VLSI Fault Diagnosis System
TITAC: Design of A Quasi-Delay-Insensitive Microprocessor
Understanding the Accellera SCE-MI Transaction Pipes
CATA: A Computer-Aided Test Analysis System
Metastability and Synchronizers: A Tutorial
The Next 25 Years in EDA: A Cloudy Future?
Overcoming Early-Life Failure and Aging for Robust Systems
Conflicting Criteria in Embedded System Design
Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments
Scan-Based Tests with Low Switching Activity
Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools - Part 2
Chips in 3D
Top Picks in Hardware and Embedded Security
Hybrid Testbench Acceleration for Reducing Communication Overhead
An Isma Lee Router Accelerator
Guest Editors' Introduction: DFM Drives Changes in Design Flow
Ten: A Concurrent Test Engineering Environment
A Fast Partitioning Method for PLA-Based FPGAs
Driving the Internet of Things
Algorithms for automatic test pattern generation
Dependable Computing and Online Testing in Adaptive and Configurable Systems
ARM Twisting with Sir Robin: An Interview with ARM Chairman Sir Robin Saxby
First CADathlon Programming Contest held at 2002 ICCAD
Design for Debug: Catching Design Errors in Digital Chips
ITC 2002 Panels: Part 2
VHDL's Impact on Test
EM Side Channels in Hardware Security: Attacks and Defenses
SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs
AC Scan Path Selection for Physical Debugging
Multipurpose Parallelism for VLSI Cad on the RP3
Aliasing Errors in Signature Analysis Registers
DATE 2022: Aiming for an Online/ Onsite Format and Finally Moving to Online Only
Computing in the Dark Silicon Era: Current Trends and Research Challenges
Report on the 28th Asia and South Pacific Design Automation Conference
Dynamic Power Management in Wireless Sensor Networks
Test Engineering Education is Rational, Feasible, and Relevant
Efficient Spare Allocation for Reconfigurable Arrays
Shared Red Bricks
True Interactive Testing Based on IJTAG
Digital Signal Processing With Molecular Reactions
ITC 2003 panels: Part 2
The Future of Test and DFT
Data-Driven Test Plan Augmentation for Platform Verification
Beyond the CPU: Side-Channel Attacks on GPUs
Conference Reports: Recap of the 24th Asia and South Pacific Design Automation Conference
Tipping the Balance: Imbalanced Classes in Deep-Learning Side-Channel Analysis
Electrical Characterization of Megabit DRAMs, Part 2: Internal Testing
Icon: A Tool for Design at Schematic, Virtual Grid, and Layout Levels
An Integrated CAD Environment for Low-Power Design
VioNet: A Hierarchical Detailed Routing Wire-Short Violation Predictor Based on a Convolutional Neural Network
BHT-NoC: Blaming Hardware Trojans in NoC Routers
The Mutating Metric for Benchmarking Test
Neural Net and Boolean Satisfiability Models of Logic Circuits
A D&T Roundtable: Challenges for Low-Power and High-Performance Chips
OpenAccess: Standard and Practices
Early, Accurate Dependability Analysis of CAN-Based Networked Systems
Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs
Spray-painting on the wall of EDA
Replacing Error Vector Magnitude Test with RF and Analog BISTs
System Partitioning of MCMs for Low Power
Is There an Answer?
Guest Editor's Introduction: Testing and Improving the Testability of Multimegabit Memories
Real-Time Power Sensors for Intelligent Power Management and Beyond
Parallelizing GPGPU-Sim for Faster Simulation with High Fidelity
Open-Source Silicon
Accellera's DVCon Conferences Focus on the Community of Practicing Engineers
Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research
Continuous-Flow Biochips: Technology, Physical-Design Methods, and Testing
On the cusp of a validation wall
A Test-Pattern-Generation Algorithm for Sequential Circuits
Are Primitive Polynomials Always Best in Signature Analysis?
A knowledge-based system for selecting test methodologies
Resizing Rules for MOS Analog-Design Reuse
Pulsed-Latch Circuits: A New Dimension in ASIC Design
BiomedBench: A Benchmark Suite of TinyML Biomedical Applications for Low-Power Wearables
IC SEM Reverse Engineering Tutorial Using Artificial Intelligence
Managing Complex Boundary-Scan Operations
Toward Agile Hardware Designs With Chisel: A Network Use Case
A D&T Roundtable: Power Delivery and Distribution
Engineering a device for electron-beam probing
The Last Byte: System Testing Ourselves
Security Arms Race
Computational Mass Spectrometry in a Reconfigurable Coherent Coprocessing Architecture
Guest Editors' Introduction: Design & Test of a High-Volume 3-D Stacked Graphics Processor With High-Bandwidth Memory
Microprocessor IDDQ Testing: A Case Study
Testing Interconnections to Static RAMs
Using Electrical Bitmap Results from Embedded Memory to Enhance Yield
FASTEN: An FPGA-Based Secure System for Big Data Processing
Test Technology in Europe
Quantum-Safe Internet of Things
A New Testing Acceleration Chip for Low-Cost Memory Tests
Lab on a Chip for Live-Cell Manipulation
The V compiler: automating hardware design
A D&T Roundtable: What's Next for Microelectronics Education?
Is engineering a viable profession in the US?
On the Impact of Uncertainties in Silicon-Photonic Neural Networks
Focus on DRAMs
Wire ordering for detailed routing
A Multicore Processor for Time-Critical Applications
Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687
Guest Editors' Introduction: Critical and Enabling Techniques for Emerging Memories
SPOCK: Reverse Packet Traversal for Deadlock Recovery
Self-Aware Machine Learning for Multimodal Workload Monitoring during Manual Labor on Edge Wearable Sensors
Statistics in Semiconductor Test: Going beyond Yield
3D DRAM Design and Application to 3D Multicore Systems
From the EIC: Special Section on Test
Compact Modeling of Variation in FinFET SRAM Cells
SoC-GPIO-Based Dynamic Power Noise Control for Video Sensor Applications
ITC celebrates 25th meeting
Interoperable Design Constraints for Custom IC Design
Design and Test Economics-An Extra Dimension
Neural Network Inference on Mobile SoCs
Test and Reliability: Partners in IC Manufacturing, Part 2
A Knowledge-Based Logic Design System
Embedded Memories: Progress and a Look into the Future
Voltage-Resistance-Adaptive MPPT Circuit for Energy Harvesting
Placement Optimization of Flexible TFT Digital Circuits
Design of Single-Bit Fault-Tolerant Reversible Circuits
Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics
Hardware-Software Cosynthesis for Digital Systems
A Single-Frame Superresolution Algorithm for Lab-on-a-Chip Lensless Microfluidic Imaging
A CMOS Resizing Methodology for Analog Circuits
Recap of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC)
Cloud-Aided Design for Distributed Embedded Systems
'Tis the gift to be simple
DATE 2024: Consolidating the New Conference Format
System-level design language standard needed
A Self-Correcting Active Pixel Sensor Using Hardware and Software Correction
Test Challenges for 3D Integrated Circuits
Detecting and Preventing Measurement Errors
IEEE Design & Test of Computers 1999 Annual Index, Volume 16
A Mathematical Model for Integrated Diagnostics
Changing Test and Data Modeling Requirements for Screening Latent Defects as Statistical Outliers
A D&T Roundtable: Behavioral Description Languages, Part 1: Are Designers Benefitting?
Remembering Arvind
An Optimization Platform for Digital Predistortion of Power Amplifiers
Designing Safe and Secure Industrial Control Systems: A Tutorial Review
Hybrid Approach to Faster Functional Verification with Full Visibility
Cycle Decomposition in NCL
Recap of the 42nd Edition of the International Conference on Computer- Aided Design (ICCAD 2023)
Losing My Memory
From the EIC: From Smartphones to Wearable Devices
Near Threshold Voltage (NTV) Computing: Computing in the Dark Silicon Era
Process and Reliability Sensors for Nanoscale CMOS
DAC, Moore's Law Still Drive EDA
Tanji: a General-purpose Neural Network Accelerator with Unified Crossbar Architecture
Second Therminic Workshop
40th IEEE VLSI Test Symposium 2022
Success-Driven Learning in ATPG for Preimage Computation
Report on the Design Automation Conference (DAC 2021)
A D&T Roundtable: ASIC Alternatives for System Design
Guest Editor's Introduction: Processor-Based Designs
Chip-level modeling with HDLs
Designing Autonomous Systems
The Changing Computing Paradigm With Internet of Things: A Tutorial Introduction
Milestones of New-Generation ATE
Hybrid, Incremental Assertion-Based Verification for TLM Design Flows
A Quantitative Exploration of Collaborative Pruning and Approximation Computing Towards Energy Efficient Neural Networks
Practical Application of RAM Sequential Test
What's Ahead for 1991?
Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms
Digitally intensive receiver design: opportunities and challenges
Serving a growing community: How D&T began
Guest Editors' Introduction: Speeding Up Analog Integration and Test for Mixed-Signal SoCs
Architecture Exploration for a Reconfigurable Architecture Template
Embedded systems and the kitchen sink
ISLPED 2020: An Experience of Virtual Conference during COVID-19 Time
SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure
The GSRC: Bridging Academia and Industry
A Simple New Method to Calibrate Millimeter-Wave Mixers
An Overview of Nanoscale Devices and Circuits
Guest Editors' Introduction: Clockless VLSI Systems
A D&T Roundtable Deep-Submicron Design
Memory Usage Estimation for Dataflow-Model-Based Software Development Methodology
PiN: Processing in Network-on-Chip
Using Adaptive Circuits to Mitigate Process Variations in a Microprocessor Design
Caring Analytics for Adults With Special Needs
Autonomous Systems, Trust, and Guarantees
Niklaus Wirth (1934-2024) - An Appreciation
Hierarchical Analysis of IC Artwork with User-Defined Rules
A Memory Centric Architecture of the Link Assessment Algorithm in Large Graphs
Code Ocean Is Live: Upload Your Algorithms
Automated Optical Accelerator Search: Expediting Green and Ubiquitous DNN-Powered Intelligence
Online Current Testing
Side Channel and Fault Analyses on Memristor-Based Logic In-Memory
Guest Editor's Introduction: Reengineering Digital Systems
Energy Savings and the "Software-Defined" Building
A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties
Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors
Remote Electrical-level Security Threats to Multi-Tenant FPGAs
Heuristic-Based Algorithms for Low-Complexity AV1 Intraprediction
A Hardware-Software Real-Time Operating System Framework for SoCs
Interdependencies of Degradation Effects and Their Impact on Computing
Dynamic Task Mapping for MPSoCs
Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems
Tracing the Thermal Behavior of ICs
Effectiveness of Microarchitecture Test Program Generation
Adventures in the Mainframe Trade
VHDL Standards
Modeling and Optimizing the Costs of Electronic Systems
EDA meets biology! The bumpy road ahead [Perscetives]
Enabling IP
Testing Defects in Scan Chains
RB-OLITS: A Worst Case Reorder Buffer Size Reduction Approach for 3-D-NoC
A Rapid-Prototyping Environment for Digital-Signal Processors
Pursuing Coordinated Trajectory Progression and Efficient Resource Utilization of GPU-Enabled Molecular Dynamics Simulations
Contactless High-Speed Waveform Measurements on Gallium
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors
Designing an Asynchronous Communications Chip
A 20-Year Retrospective on Power and Thermal Modeling and Management
Compiler Design Issues for Embedded Processors
Transmission Coefficient Correction for DACs
Applied Boolean Equivalence Verification and RTL Static Sign-Off
Technical management: Best shaken, not stirred [The Last Byte]
Verification Approaches for Learning-Enabled Autonomous Cyber-Physical Systems
Error-Free Products
Machine Learning for CAD/EDA: The Road Ahead
Low-Cost Analog/RF IC Testing Through Combined Intra- and Inter-Die Correlation Models
Postsilicon Validation Methodology for Microprocessors
Compact variability modeling to the rescue
On-chip networks
The Problem With EDA is ... DAC 50th Anniversary - Visionary Talk
Reducing Hardware with Fuzzy Multiple Signature Analysis
The 2016 DAC Art Show Winner: Misha Temkin
HAL: A High-Speed Logic Simulation Machine
Guest Editor's Introduction Design Automation
BIST for D/A and A/D Converters
System-in-Package Testing: Problems and Solutions
IBM'S Engineering Design System Support for VLSI Design and Verification
Guest Editors' Introduction: Raising the Abstraction Level of Hardware Design
Self-Aware Network-on-Chip Control in Real-Time Systems
Real Silicon Using Open-Source EDA
Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-Based IoT Applications
High-Level Synthesis: Past, Present, and Future
A DVFS Design and Simulation Framework Using Machine Learning Models
Guest Editors' Introduction: Cyber-Physical Systems for Medical Applications
Test compression saves bits, cycles, and money
Circular Self-Test Path for FSMs
ESWEEK 2019 Conference Report
Fabless or IDM? What the Future Holds for Both: An Interview with Cirrus Logic Chairman, Michael L. Hackworth
A D&T Roundtable: Does VLSI Education Meet Industry's Needs?
Self-Awareness in Systems on Chip - A Survey
Everything but the kitchen sink
FPGA and CPLD Architectures: A Tutorial
A Model-Based Expert System for Digital System Design
Simultaneous Switching Noise: The Relation between Bus Layout and Coding
The CMU-CAM System
Testability Features of the AMD-K6 Microprocessor
Danger! Submicron Defects!
Fault Analysis for Networks with Concurrent Error Detection
A D&T Roundtable: Built-In Self-Test for Designers
An update on IEEE P1647: The e system verification language
Is a Unified Methodology for System-Level Design Possible?
Composable Battery Model Templates Based on Manufacturers' Data
Test and Reliability: Partners in IC Manufacturing, Part 1
A VHDL Standard Package for Logic Modeling
A Mixture of Experts Approach for Low-Cost DNN Customization
Device-Circuit Co-Optimization for Robust Design of FinFET-Based SRAMs
Machine Learning for CAD/EDA
Real-world board test effectiveness
Roadmapping Power
Hunting Security Bugs in SoC Designs: Lessons Learned
Time-Critical Systems Design, Part II
Core-Based Testing of Embedded Mixed-Signal Modules in a SoC
API-Based Hardware Fault Simulation for DNN Accelerators
A D&T Roundtable: Behavioral Description Languages, Part 2: VHDL vs. UDL/I
The 2022 International Conference on Computer-Aided Design (ICCAD)
A Fault Analysis Perspective for Testing of Secured SoC Cores
B#: A Battery Emulator and Power-Profiling Instrument
Self-Test and Self-Aware
MARS: A Multiprocessor-Based Programmable Accelerator
A Reinforcement Learning Framework With Region-Awareness and Shared Path Experience for Efficient Routing in Networks-on-Chip
Wireless NoC Platforms With Dynamic Task Allocation for Maximum Likelihood Phylogeny Reconstruction
Editorial Calendar
Special Issue on Emerging Challenges With 3-D NAND Flash Storage
Variation-Tolerant, Power-Safe Pattern Generation
Self-Adaptive Timing Repair
Benefits of a SoC-Specific Test Methodology
Patents in the IEEE Standards Process
Cyberphysical Systems: Workload Modeling and Design Optimization
About this super issue
ITC 2002 Panels
Testing Embedded Cores
Single-Clock Partial Scan
Improved Test Generation for High-Activity Circuits
Tesla and AND gates
Compact and High-Performing Five-Stage Pipeline RISC-V Microprocessor Designed for IoT Applications
Securing CRYSTALS-Kyber in FPGA Using Duplication and Clock Randomization
Product Futures
AxBench: A Multiplatform Benchmark Suite for Approximate Computing
Fault Sampling Revisited
Research Is Its Own Reward
Functional Verification of a RISC-V Vector Accelerator
Recap of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED'24)
FPGA-enabled computing architectures
Variety at Its Best
A D&T Roundtable- Six Sigma: Moving Towards Perfect Products
Platform-Based Design and Software Design Methodology for Embedded Systems
Report on DATE 2017 in Lausanne
Colif: A Design Representation for Application-Specific Multiprocessor SOCs
Advances in Scalable Implantable Systems for Neurostimulation Using Networked ASICs
SCA Strikes Back: Reverse-Engineering Neural Network Architectures Using Side Channels
Testing and Diagnosing Managed Networks
The ABCs of ITC
Interview With Janet Olson
Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models
Scheduling for Embedded Real-Time Systems
From the Editor in Chief: Predictability in Design and Manufacturing
Linear Algorithmic Checksums for Deep-Neural-Network Error Detection: Fundamentals and Recent Advancements
Design And Test of the 80386
Migortho: A Design Automation Flow for QCA Circuits
Security Assurance Cases for Medical Cyber-Physical Systems
Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs
Learning to assert yourself [review of Creating Assertion-Based IP (H.D. Foster and A.C. Krolnik; 2008)]
Biologically Inspired Robust Tera-Device Processors
Collection and Analysis of Microprocessor Design Errors
Extracting Defect Density and Size Distributions from Product ICs
Cathedral-II: A Silicon Compiler for Digital Signal Processing
FlexWare: A Retargetable Embedded-Software Development Environment
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
The VLSI Design Automation Assistant: An IBM System/370 Design
Infrastructure IP for Configuration and Test of Boards and Systems
Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques
Soft Errors in Advanced Computer Systems
Integrating an Electron-Beam System into VLSI Fault Diagnosis
An Open-Source EDA Flow for Asynchronous Logic
Conference Reports: Report on 2017 IEEE Asian Test Symposium
The Quest for High-Yield IC Manufacturing
Impact of Low-Impedance Substrate on Power Supply Integrity
Real-Time Testing Method for Multilevel Signal Interfaces and Its Impact on Test Cost
IEEE P1149.5 Module Test and Maintenance Bus
1994 Editorial Calendar
Profile-Driven Behavioral Synthesis for Low-Power VLSI Systems
Online BIST for Embedded Systems
High-Throughput Hardware for 3D-HEVC Depth-Map Intra Prediction
Background Receiver IQ Imbalance Correction for In-Field Testing
IDDQ Test and Diagnosis of CMOS Circuits
The network is the chip
Integrated Systems in the More-Than-Moore Era: Designing Low-Cost Energy-Efficient Systems Using Heterogeneous Components
Measurement-Based Ring Oscillator Variation Analysis
SAFER: Safety Assurances for Emergent Behavior
Self-Test and Diagnosis for Self-Aware Systems
ASIC Challenges: Emerging from a Primordial Soup
Scan Design Using Standard Flip-Flops
Analyzing Multichip Module Testing Strategies
A Design Flow and Tool for Avoiding Asymmetric Aging
Similarity-Based Fast Analysis of Data Center Networks
Design Methodology for a Large Communication Chip
Scan-path architecture for pseudorandom testing
Using Partial Isolation Rings to Test Core-Based Designs
Simulation-Based Verification of Cardiac Pacemakers With Guaranteed Coverage
Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell
Built-In EVM Measurement With Negligible Hardware Overhead
Electronic, Wireless, and Photonic Network-on-Chip Security: Challenges and Countermeasures
Verification by the pound
Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method
Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead
Testing the Interconnect of RAM-Based FPGAs
Dynamic Energy and Thermal Management of Multi-core Mobile Platforms: A Survey
OpenHealth: Open-Source Platform for Wearable Health Monitoring
Testing the 500-MHz IBM S/390 Microprocessor
VEGA: A Visual Modeling Language for Digital Systems
Power-Saving 8K Real-Time AV1 Arithmetic Encoder Architecture
From Buildings to Smart Buildings - Sensing and Actuation to Improve Energy Efficiency
On Backside Probing Techniques and Their Emerging Security Threats
From the EIC: Intelligent Resource-Constrained Sensor Nodes
Electrical Characterization of Megabit DRAMs, Part 1: External Testing
Direct Access Network
A Practical Methodology for Verifying Pipelined Microarchitectures
The EDA Business Model Dialogue Part 2
A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines
Ethical Design of Computers: From Semiconductors to IoT and Artificial Intelligence
Fault Models and Test Generation for Hardware-Software Covalidation
Design verification of the WE 32106 math accelerator unit
New Challenges in Delay Testing of Nanometer, Multigigahertz Designs
Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits
Special Issue on the 2021 Workshop on Top Picks in Hardware and Embedded Security
Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing
Identifying and Eliminating Side-Channel Leaks in Programmable Systems
Global On-Chip Coordination at Light Speed
Recap of the 39th Edition of the International Conference on Computer-Aided Design (ICCAD 2020)
Integrating Tester Pin Electronics
Guest Editors' Introduction: Synthetic Biology
Guest Editors' Introduction: On-Chip Power Distribution Networks
Southwest Test Workshop 2004
Using a Programming Language for Digital System Design