yusuke1997/dblp-id-title huggingface dataset:
Test Optimization in Memristor Crossbars Based on Path Selection
An efficient small signal frequency analysis method of nonlinear circuits with two frequency excitations
Subsets of Primary Input Vectors in Sequential Test Generation for Single Stuck-at Faults
Comments on "FPAD: a fuzzy nonlinear programming approach to analog circuit design"
Robust methods for EMC-driven routing
High-Level Design and Validation of the BlueSPARC Multithreaded Processor
Comparing layouts with HDL models: a formal verification technique
Topping Off Test Sets Under Bounded Transparent Scan
Efficient modeling of 1/f alpha / noise using multirate process
Toward a High-Performance and Low-Loss Clos-Benes-Based Optical Network-on-Chip Architecture
Faster Region-Based Hotspot Detection
A Framework for Near Memory Processing With Computation Offloading and Load Balancing
Grid Size Adapted Multistep Methods for High $Q$ Oscillators
An Efficient High-Frequency Linear RF Amplifier Synthesis Method Based on Evolutionary Computation and Machine Learning Techniques
A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems
Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs
Recycled IC Detection Based on Statistical Methods
Flying-Probe Testing: A Trajectory Planner and a Benchmark Suite
Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for Coverage of Information Leakage Faults
A General Time-Domain Method for Harmonic Distortion Estimation in CMOS Circuits
Delay optimization of digital CMOS VLSI circuits by transistor reordering
Fast computation of symmetries in Boolean functions
Iterative placement improvement by network flow methods
Cross-Contamination Avoidance for Droplet Routing in Digital Microfluidic Biochips
IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults
Performance Characterization of a Reconfigurable Planar-Array Digital Microfluidic System
Formal Modeling and Verification of Controllers for a Family of DRAM Caches
Throughput-driven floorplanning with wire pipelining
Timing-Driven and Placement-Aware Multibit Register Composition
Discretization error in MOSFET device simulation
Improved Linear Decomposition of Majority and Threshold Boolean Functions
Accurately Handle Don't-Care Conditions in High-Level Designs and Application for Reducing Initialized Registers
Resampling Plans for Sample Point Selection in Multipoint Model-Order Reduction
Hardware Computation Graph for DNN Accelerator Design Automation Without Inter-PU Templates
SR-BIP: A Soft Error-Resilient Binary Neural Network Inference Processor
Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric
Segment and Conflict Aware Page Allocation and Migration in DRAM-PCM Hybrid Main Memory
Efficient linear circuit analysis by Pade approximation via the Lanczos process
Guest editor's introduction to special section on high-level design validation and test
A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism
Improvements on Efficiency and Efficacy of SPFD-Based Rewiring for LUT-Based Circuits
Performance analysis of latency-insensitive systems
Resolving the Reliability Issues of Open Blocks for 3-D NAND Flash: Observations and Strategies
Fundamental Limits on Energy-Delay-Accuracy of In-Memory Architectures in Inference Applications
Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies
Design of concurrent error-detecting systolic arrays using |g 3N| M codes
CAPMIG: Coherence-Aware Block Placement and Migration in Multiretention STT-RAM Caches
Toward an Efficient Deep Pipelined Template-Based Architecture for Accelerating the Entire 2-D and 3-D CNNs on FPGA
Maximally and arbitrarily fast implementation of linear andfeedback linear computations
New multivalued functional decomposition algorithms based on MDDs
Mining Shape Expressions From Positive Examples
Event suppression by optimizing VHDL programs
DYNAMITE: an efficient automatic test pattern generation system for path delay faults
Error Resilient Online Reinforcement Learning Using Adaptive Statistical Checks
LPCR: Information-Theory-Based Low-Power Code Reordering for Serial Links in Network-on-Chip
A Synthesizable Constant Tuning Gain Technique for Wideband LC -VCO Design
A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults
STYLE: a statistical design approach based on nonparametric performance macromodeling
DAG-Aware Synthesis Orchestration
Amphis: Managing Reconfigurable Processor Architectures With Generative Adversarial Learning
A Methodology for Worst-Case Analysis of Integrated Circuits
On-Chip Diagnosis of Generalized Delay Failures Using Compact Fault Dictionaries
New RTD large-signal DC model suitable for PSPICE
Energy-Efficient Adaptive Pipelined MPSoCs for Multimedia Applications
Guest Editorial Special Section on the 2011 International Symposium on Physical Design
Interconnect estimation for FPGAs
Simultaneous gate sizing and placement
Soft-Core Dataflow Processor Architecture Optimized for Radar Signal Processing
A Methodology for Optimal Test Structure Design for Statistical Process Characterization and Diagnosis
Optimizing Random Forest-Based Inference on RISC-V MCUs at the Extreme Edge
LBIST for Automotive ICs With Enhanced Test Generation
iClaire: A Fast and General Layout Pattern Classification Algorithm With Clip Shifting and Centroid Recreation
Nonsmooth Optimization Method for VLSI Global Placement
CAPCAL-a 3-D capacitance solver for support of CAD systems
Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits
Automatic state space decomposition for approximate FSM traversal based on circuit analysis
Unified Computation of Parameter Sensitivity and Signal-Injection Sensitivity in Nonlinear Oscillators
Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems
Error-Correcting Code Aware Memory Subsystem
System-level design: orthogonalization of concerns andplatform-based design
False Key-Controlled Aggressive Voltage Scaling: A Countermeasure Against LPA Attacks
Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips
A ReRAM-Based Processing-In-Memory Architecture for Hyperdimensional Computing
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures
A new preconditioner for CGS iteration in solving large sparse nonsymmetric linear equations in semiconductor device simulation
PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators
Hyper Parametric Timed CTL
Accurate Modeling of the Delay and Energy Overhead of Dynamic Voltage and Frequency Scaling in Modern Microprocessors
Tight Compression: Compressing CNN Through Fine-Grained Pruning and Weight Permutation for Efficient Implementation
Detection of and Countermeasure Against Thermal Covert Channel in Many-Core Systems
Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis
Moore-Machine Filtering for Timed and Untimed Pattern Matching
Concurrency and Communication in Hardware Simulators
Switched-capacitor simulation models for full-chips verification
A cache-based method for accelerating switch-level simulation
A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy
Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation
Platform-based design from parallel C specifications
Finite-Element Simulation of Local Oxidation of Silicon
Area-optimal technology mapping for field-programmable gate arrays based on lookup tables
Sensitivity computation in piecewise approximate circuit simulation
CKFO: Convolution Kernel First Operated Algorithm With Applications in Memristor-Based Convolutional Neural Network
Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives
MLMSA: Multilabel Multiside-Channel-Information Enabled Deep Learning Attacks on APUF Variants
Scale-Free Sparse Matrix-Vector Multiplication on Many-Core Architectures
Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm
Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing
An effective congestion-driven placement framework
Incremental fault diagnosis
Design space exploration for optimizing on-chip communication architectures
Verifying Asymptotic Temporal Properties of Continuous-State Probabilistic Systems
HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning
GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing
Non-Test Cubes for Test Generation Targeting Hard-to-Detect Faults
SemiMap: A Semi-Folded Convolution Mapping for Speed-Overhead Balance on Crossbars
Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF
A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and Evaluation
High Performance Modular Multiplication for SIDH
Multistage Multirate Transfer Function Automated Synthesis Using Hybrid Sampling Strategy-Based Differential Evolution
Test generation for I DDQ testing of bridging faults in CMOS circuits
SearcHD: A Memory-Centric Hyperdimensional Computing With Stochastic Training
Reinforcement Learning Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips
Optimal shape function for a bidirectional wire under Elmore delay model
A general numerical procedure for multilayer multistep IC process simulation
XID: Don't care identification of test patterns for combinational circuits
Synthesis of symmetric functions for path-delay fault testability
Power supply transient signal analysis for defect-oriented test
Algorithm level recomputing using allocation diversity: a registertransfer level approach to time redundancy-based concurrent errordetection
Partitioning logic on graph structures to minimize routing cost
PartMOR: Partitioning-Based Realizable Model-Order Reduction Method for RLC Circuits
Modeling and Analysis of Optical Modulators Based on Free-Carrier Plasma Dispersion Effect
A Versatile Pulse Control Method to Generate Arbitrary Multidirection Multibutterfly Chaotic Attractors
Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications
A Secure Reconfigurable Crypto IC With Countermeasures Against SPA, DPA, and EMA
Comments on 'Simulation of lossless symmetrical three conductor systems' by W. Guggenbuhl et al
On integrating power and signal routing for shield count minimization in congested regions
Compact Topology-Aware Bus Routing for Design Regularity
MCHEAS: Optimizing Large-Parameter NTT Over Multicluster In-Situ FHE Accelerating System
Xtream-fit: an energy-delay efficient data memory subsystem for embedded media processing
Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data Compression
A predictive distributed congestion metric with application to technology mapping
The implementation of physical boundary conditions in the Monte Carlo simulation of electron devices
A Functional Unit and Register Binding Algorithm for Interconnect Reduction
Specification and analysis of timing constraints for embedded systems
Component synthesis from functional descriptions
Algorithms for approximate FSM traversal based on state space decomposition
On Delay Fault Testing in Logic Circuits
Test compaction for sequential circuits
Simultaneous Optimization of Droplet Routing and Control-Pin Mapping to Electrodes in Digital Microfluidic Biochips
Development of Programmable Logic Array for Multiple-Valued Logic Functions
Design of a High-Efficiency Sequential Load Modulated Balanced Amplifier Based on Multiple Multiobjective Bayesian Optimization
Cardio: CMP Adaptation for Reliability Through Dynamic Introspective Operation
SpikeSpec: An On-Chip Learning Neuromorphic Accelerator for Spectrum Sensing With Triplet-Boosting and Hardware Friendly Loss Function
SASCHA - Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration
3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits
Constraint-based channel routing for analog and mixed analog/digital circuits
Hierarchical Loose Routing for Gate Arrays
Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate
A proposed method for determining a MOSFET gate electrode's bottom dimension and the on-state fringing capacitance
A Distributed and Parallel Accelerator Design for 3-D Acoustic Imaging on FPGA-Based Systems
SparseRC: Sparsity Preserving Model Reduction for RC Circuits With Many Terminals
Repairing a 3-D Die-Stack Using Available Programmable Logic
Hot-Trim: Thermal and Reliability Management for Commercial Multicore Processors Considering Workload Dependent Hot Spots
Electrical model of the floating gate defect in CMOS ICs: implications on I DDQ testing
ML-Accelerated Yield Analysis Framework Using Regularization for Sparsity in High-Sigma and High-Dimensional Scenarios
TSF3D: MSV-Driven Power Optimization for Application-Specific 3D Network-on-Chip
Error Estimation and Error Reduction With Input-Vector Profiling for Timing Speculation in Digital Circuits
Simultaneous EUV Flare Variation Minimization and CMP Control by Coupling-Aware Dummification
Local watermarks: methodology and application to behavioral synthesis
Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations
Revisiting Dynamic Scheduling of Control Tasks: A Performance-Aware Fine-Grained Approach
Circuit Partitioning and Transmission Cost Optimization in Distributed Quantum Circuits
FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient
Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models
Detecting Spoofed Speeches via Segment-Based Word CQCC and Average ZCR for Embedded Systems
A Static Linear Behavior Analog Fault Model for Switched-Capacitor Circuits
PF²A-ViT: Parameter-Free and Feature-Aware Dynamic Token Pruning Accelerator With Complementary Quantization-Encoding for Vision Transformer
Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation
System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm
Compact Test Pattern Selection for Small Delay Defect
Generating Current Budgets to Guarantee Power Grid Safety
Crosstalk noise minimization in domino logic design
Automatic TLM Fault Localization for SystemC
Efficient SRAM Failure Rate Prediction via Gibbs Sampling
Numerical simulator for superconducting integrated circuits
Detection of Voltage Droop-Induced Timing Fault Attacks Due to Hardware Trojans
Line-to-ground capacitance calculation for VLSI: a comparison
Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network
A parity bit signature for exhaustive testing
Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning
MII: A Multifaceted Framework for Intermittence-Aware Inference and Scheduling
Page Type-Aware Full-Sequence Program Scheduling via Reinforcement Learning in High Density SSDs
JiffyTune: circuit optimization using time-domain sensitivities
Microfluidics-Based Biochips: Technology Issues, Implementation Platforms, and Design-Automation Challenges
Pseudopin assignment with crosstalk noise control
An incremental zero/integer delay switch-level simulation environment
Enhancing Temporal Logic Falsification With Specification Transformation and Valued Booleans
A Cooperative Multiagent Reinforcement Learning Framework for Droplet Routing in Digital Microfluidic Biochips
BonnCell: Automatic Cell Layout in the 7-nm Era
Maestro: Autonomous QoS Management for Mobile Applications Under Thermal Constraints
Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints
On the Scheduling of Fault-Tolerant Time-Sensitive Networking With IEEE 802.1CB
Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs
A normalized-area measure for VLSI layouts
Statistical Performance Modeling and Parametric Yield Estimation of MOS VLSI
A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells
Signature analysis for analog and mixed-signal circuit test response compaction
Platune: a tuning framework for system-on-a-chip platforms
LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test
Broadcasting test patterns to multiple circuits
Freezing: Eliminating Unnecessary Drawing Computation for Low Power
SPSA: Exploring Sparse-Packing Computation on Systolic Arrays From Scratch
Correction to "Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications"
Diagnostic Test Generation That Addresses Diagnostic Holes
A Novel Built-In Self-Authentication Technique to Prevent Inserting Hardware Trojans
A multiple layer contour-based gridless channel router
Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus
HCFTL: A Locality-Aware Flash Translation Layer for Efficient Address Translation
Guest Editorial: Special Section on the ACM/IEEE Symposium on Networks-on-Chip 2010
Incorporating performance and testability constraints during binding in high-level synthesis
HERO: Pbit High-Radix Optical Switch Based on Integrated Silicon Photonics for Data Center
Register minimization beyond sharing among variables
Modeling the Dependency of Analog Circuit Performance Parameters on Manufacturing Process Variations With Applications in Sensitivity Analysis and Yield Prediction
Routing With Constraints for Post-Grid Clock Distribution in Microprocessors
A Subthreshold Conduction Model for Circuit Simulation of Submicron MOSFET
A Mixed HVH-VHV Algorithm for Three-Layer Channel Routing
New 3-D CMOS Fabric With Stacked Horizontal Nanowires
Correlation Integral-Based Intrinsic Dimension: A Deep-Learning-Assisted Empirical Metric to Estimate the Robustness of Physically Unclonable Functions to Modeling Attacks
Charge-Controlled Readout and BIST Circuit for MEMS Sensors
Timing-Aware Power-Noise Reduction in Placement
Simulate and Eliminate: A Top-to-Bottom Design Methodology for Automatic Generation of Application Specific Architectures
Demand-Side Management of Domestic Electric Water Heaters Using Approximate Dynamic Programming
Synthesis of single/dual-rail mixed PTL/static logic for low-power applications
Modeling, Analysis, and Hard Real-Time Scheduling of Adaptive Streaming Applications
A high-level simulation and synthesis environment for ΔΣ modulators
Comparison of methods to calculate capacitances and cutoff frequencies from DC and AC simulations on bipolar devices
Design for test using partial parallel scan
A Normalization Method for Arithmetic Data-Path Verification
Hybrid routing
Multi-Accuracy Power and Performance Transaction-Level Modeling
Rewiring for watermarking digital circuit netlists
Automatic Layer-Based Generation of System-On-Chip Bus Communication Models
Design Automation for Interwell Connectivity Estimation in Petroleum Cyber-Physical Systems
Probabilistic Transitive-Closure Ordering and Its Application on Variational Buffer Insertion
Statistical Path Selection for At-Speed Test
CorrectNet+: Dealing With HW Non-Idealities in In-Memory-Computing Platforms by Error Suppression and Compensation
Formal Probabilistic Analysis of Low Latency Approximate Adders
FPGA Trojans Through Detecting and Weakening of Cryptographic Primitives
A Multilevel Solver for Boundary Value Problems
An optimal channel-routing algorithm in the times square model
Two-dimensional semiconductor device analysis based on new finite-element discretization employing the S-G scheme
A Delay-Driven Iterative Technology Mapping Framework
A low overhead design for testability and test generation technique for core-based systems-on-a-chip
A Metal-Only-ECO Solver for Input-Slew and Output-Loading Violations
Architecture and Control Algorithms for Combating Partial Shading in Photovoltaic Systems
Interval methods for modeling uncertainty in RC timing analysis
Efficient Formal Verification of Galois-Field Arithmetic Circuits Using ZDD Representation of Boolean Polynomials
Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling
The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation
SaeCAS: Secure Authenticated Execution Using CAM-Based Vector Storage
Fault Modeling for Digital MOS Integrated Circuits
NR-Router+: Enhanced Non-Regular Electrode Routing With Optimal Pin Selection for Electrowetting-on-Dielectric Chips
Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies
LFSR-Based Test Generation for Reduced Fail Data Volume
Floorplanning for Partially Reconfigurable FPGAs
RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal
Strider: Signal Value Transition-Guided Defect Repair for HDL Programming Assignments
Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams
Automation of IC layout with analog constraints
Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICs
Comparison of iterative methods for AC analysis in PISCES-IIB
iPROBE: Internal Shielding Approach for Protecting Against Front-Side and Back-Side Probing Attacks
A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives
Machine Learning-Based Rowhammer Mitigation
Linear complexity algorithms for hierarchical routing
FFTSVD: A Fast Multiscale Boundary-Element Method Solver Suitable for Bio-MEMS and Biomolecule Simulation
In Memoriam: Margarida F. Jacome
Covering conditions and algorithms for the synthesis of speed-independent circuits
Modeling Power Consumption of NAND Flash Memories Using FlashPower
An Endurance-Aware Metadata Allocation Strategy for MLC NAND Flash Memory Storage Systems
Delay-testable implementations of symmetric functions
A new circuit optimization technique for high performance CMOS circuits
LIAD: A Method for Extending the Effective Time of 3-D TLC NAND Flash Hard Decision
The Meyer model revisited: why is charge not conserved? [MOS transistor]
Low Cost Hypercompression of Test Data
Synthesis of multilevel multiplexer circuits for incompletely specified multioutput Boolean functions with mapping to multiplexer based FPGA's
Power modeling and characteristics of field programmable gate arrays
Hot carrier transport effect in Schottky-barrier diode grown by MBE
Statistical Timing Analysis for Latch-Controlled Circuits With Reduced Iterations and Graph Transformations
An interconnect energy model considering coupling effects
PASS: Pattern-Sequence-Authentication-Based Secure Scan Against Reverse Engineering Attacks
Artificial parameter homotopy methods for the DC operating point problem
Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros
A graph representation for programmable logic arrays to facilitate testing and logic design
Redundancy-Aware Power Grid Electromigration Checking Under Workload Uncertainties
Placement of Thermal Vias in 3-D ICs Using Various Thermal Objectives
Static power modeling of 32-bit microprocessors
Automatic Compilation of Diverse CNNs Onto High-Performance FPGA Accelerators
Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation
Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution
Excellerator: custom CMOS leaf cell layout generator
Testing analog and mixed-signal integrated circuits using oscillation-test method
FeFET-Based In-Memory Hyperdimensional Encoding Design
ISA Extensions of Shuffling Against Side-Channel Attacks
Three-dimensional capacitance computations for VLSI/ULSI interconnections
Quality Optimization of Adaptive Applications via Deep Reinforcement Learning in Energy Harvesting Edge Devices
A Tag Machine Based Performance Evaluation Method for Job-Shop Schedules