yusuke1997/dblp-id-title huggingface dataset:
Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations
A Binary-Feature-Based Object Recognition Accelerator With 22 M-Vector/s Throughput and 0.68 G-Vector/J Energy-Efficiency for Full-HD Resolution
An Effective Solution to Task Scheduling and Memory Partitioning for Multiprocessor System-on-Chip
Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA
Hilbert Transform-Based Workload Prediction and Dynamic Frequency Scaling for Power-Efficient Video Encoding
A Compact RF CMOS Modeling for Accurate High-Frequency Noise Simulation in Sub-100-nm MOSFETs
Runtime Monitoring of ML-Based Scheduling Algorithms Toward Robust Domain-Specific SoCs
Simulation-Assisted Formal Verification of Nonlinear Mixed-Signal Circuits With Bayesian Inference Guidance
Computation of Self-Induced Magnetic Field Effects Including the Lorentz Force for Fast-Transient Phenomena in Integrated-Circuit Devices
QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test
On the simplification of a placement problem
Polyhedral Bubble Insertion: A Method to Improve Nested Loop Pipelining for High-Level Synthesis
Multi-Corner Timing Macro Modeling With Neural Collaborative Filtering From Recommendation Systems Perspective
Fast Random Walk Based Capacitance Extraction for the 3-D IC Structures With Cylindrical Inter-Tier-Vias
A Statistical Model Including Parameter Matching for Analog Integrated Circuits Simulation
Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization
CUTIE: Beyond PetaOp/s/W Ternary DNN Inference Acceleration With Better-Than-Binary Energy Efficiency
High-Performance Remote Data Persisting for Key-Value Stores via Persistent Memory Region
Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling
NEWS: a net-even-wiring system for the routing on a multilayer PGA package
Secured Data Transmission Over Insecure Networks-on-Chip by Modulating Inter-Packet Delays
Design and Implementation of Block-Based Partitioning for Parallel Flip-Chip Power-Grid Analysis
Three-Layer Channel Routing
Fast Algebraic Rewriting Based on And-Inverter Graphs
SPIRIT: a highly robust combinational test generation algorithm
Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits
An Efficient Data Structure for Maxplus Merge in Dynamic Programming
Accelerating Assertion Coverage With Adaptive Testbenches
Adjustable Delay Buffer Allocation under Useful Clock Skew Scheduling
Non-Hanan routing
Analysis and proposal of signature circuits for LSI testing
Erratum to "Model-Driven Design of Network Aspects of Distributed Embedded Systems"
Delay models for CMOS, BiCMOS and BiNMOS circuits and their applications for timing simulations
Energy-Efficient Power Delivery System Paradigms for Many-Core Processors
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization
Timing analysis for full-custom circuits using symbolic DC formulations
3D-TemPo: Optimizing 3-D DRAM Performance Under Temperature and Power Constraints
SATA: Sparsity-Aware Training Accelerator for Spiking Neural Networks
Incremental 3-D Global Routing Considering Cell Movement and Complex Routing Constraints
Performance Improvements and Congestion Reduction for Routing-Based Synthesis for Digital Microfluidic Biochips
An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow
Synthesis of reversible logic circuits
Allocating One Common ACC-Rich Platform for Many Streaming Applications
Silent Data Corruption in Robot Operating System: A Case for End-to-End System-Level Fault Analysis Using Autonomous UAVs
A Practical CAD System Application for Full Custom VLSI Microcomputer Chips
Channel density reduction by routing over the cells
On Multiplexed Signal Tracing for Post-Silicon Validation
Microprocessor Verification via Feedback-Adjusted Markov Models
GTCO: Graph and Tensor Co-Design for Transformer-Based Image Recognition on Tensor Cores
An efficient analytical model for calculating trapped charge in amorphous silicon
A Description of MOS Internodal Capacitances for Transient Simulations
Enhancing the stability of asymptotic waveform evaluation for digital interconnect circuit applications
SIMON-A simulator for single-electron tunnel devices and circuits
Toward Secure and Trustworthy Cyberphysical Microfluidic Biochips
Advances in Concurrent Multilevel Simulation
Two-dimensional power device simulator considering an integral external circuit equation
Fault simulation for multiple faults by Boolean function manipulation
Accuracy-Based Hybrid Parasitic Capacitance Extraction Using Rule-Based, Neural-Networks, and Field-Solver Methods
Congestion-Aware Vertical Link Placement and Application Mapping Onto 3-D Network-on-Chip Architectures
Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment
TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs
A Scalable Formal Verification Methodology for Data-Oblivious Hardware
WATPC: A Computer-Aided Design Package for Digital Bipolar Integrated Circuits
A high-performance architecture and BDD-based synthesis methodology for packet classification
High-Level Synthesis Algorithm for the Design of Reconfigurable Constant Multiplier
Aging Adaption in Integrated Circuits Using a Novel Built-In Sensor
Nonlinear transformer model for circuit simulation
A statistical methodology for wire-length prediction
Dispersion in Placement: Quantification and Insights
Levelized incomplete LU factorization and its application to large-scale circuit simulation
The generation of a mesh for resistance calculation in integrated circuits
TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits
A Two-Dimensional Etching Profile Simulator: ESPRIT
Algorithms for simulation of three-dimensional etching
Test pattern generation for circuits with tri-state modules by Z-algorithm
Three-dimensional effects due to the field oxide in MOS devices analyzed with MINIMOS 5
CompressKey - Near Lossless Layout Compression and Encryption Using Convolutional Auto-Encoder Model and Expansion-Reduction Pattern Techniques
ISPD11: Power-Driven Flip-Flop Merging and Relocation
A Novel Area-Power Efficient Design for Approximated Small-Point FFT Architecture
PAGURUS: Low-Overhead Dynamic Information Flow Tracking on Loosely Coupled Accelerators
Development and Efficiency Analysis of a Switching Scheme for INL Reduction in Unary DACs
Embedded deterministic test
Improving Reliability of Soft Real-Time Embedded Systems on Integrated CPU and GPU Platforms
Probability-based approaches to VLSI circuit partitioning
Mosaic-3C1S: A Low Overhead Crosstalk Suppression Scheme for Rectangular TSV Array
Combined hardware selection and pipelining in high-performance data-path design
Cross-Layer Modeling and Simulation of Circuit Reliability
Burst Automaton: Framework for Speed-Independent Synthesis Using Burst-Mode Specifications
Test vector generation for charge sharing failures in dynamic logic
Testing Transition Delay Faults in Modified Booth Multipliers
On the Scalability and Dynamic Load-Balancing of Optimistic Gate Level Simulation
Parity-scan design to reduce the cost of test application
InTraSim: Incremental Transient Simulation of Power Grids
MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts
TIGER: an efficient timing-driven global router for gate array and standard cell layout design
Table look-up model of thin-film transistors for circuit simulationusing spline interpolation with transformation by y=x+log(x)
On Undetectable Faults and Fault Diagnosis
A Formal Proof of PG Recurrence Equations of Parallel Adders
Leveraging Gate-Level Properties to Identify Hardware Timing Channels
Efficient Hardware Acceleration of Sparsely Active Convolutional Spiking Neural Networks
Design and Evaluation of Fluctuating Power Logic to Mitigate Power Analysis at the Cell Level
Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations
Frequent-Pattern-Guided Multilevel Decomposition of Behavioral Specifications
Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs
Performance Estimation Techniques With MPSoC Transaction-Accurate Models
On the Pitfalls of Using Arbiter-PUFs as Building Blocks
A bounded search algorithm for segmented channel routing for FPGA's and associated channel architecture issues
An Efficient Graph-Based Algorithm for ESD Current Path Analysis
A method for detecting interconnect DSM defects in systems on chip
Signal Delay in General RC Networks
On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
Toward the Design of Fault-Tolerance-Aware and Peak-Power-Aware Multicore Mixed-Criticality Systems
A Compact Memristor-CMOS Hybrid Look-Up-Table Design and Potential Application in FPGA
Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures
Asynchronous circuit synthesis with Boolean satisfiability
Adjusting Learning Rate of Memristor-Based Multilayer Neural Networks via Fuzzy Method
ADIC-2.C a general-purpose optimization program suitable for integrated circuit design applications using the pseudo objective function substitution method (POSM)
Codex-dp: co-design of communicating systems using dynamicprogramming
Training on the Fly: On-Device Self-Supervised Learning Aboard Nano-Drones Within 20 mW
Resource Allocation and Design Techniques of Prebond Testable 3-D Clock Tree
Predicting X-Sensitivity of Circuit-Inputs on Test-Coverage: A Machine-Learning Approach
A parallel standard cell placement algorithm
Transistor Count Optimization in IG FinFET Network Design
WA-OPShare: Workload-Adaptive Over-Provisioning Space Allocation for Multi-Tenant SSDs
Pretraining Graph Neural Networks for Few-Shot Analog Circuit Modeling and Design
Joint Protection Scheme for Deep Neural Network Hardware Accelerators and Models
Automatic Decoder Synthesis: Methods and Case Studies
Formalization of a Parameterized Parallel Adder Within the Coq Theorem Prover
An efficient profile-based algorithm for scratchpad memory partitioning
Reducing Conflict Misses by Application-Specific Reconfigurable Indexing
Understanding Algebraic Rewriting for Arithmetic Circuit Verification: A Bit-Flow Model
An efficient multilayer MCM router based on four-via routing
Equivalence checking of combinational circuits using Boolean expression diagrams
An Unconstrained Topological Via Minimization Problem for Two-Layer Routing
A Latency-Optimized and Energy-Efficient Write Scheme in NVM-Based Main Memory
Guest Editorial: Special Section on the ACM/IEEE Symposium on Networks-on-Chip 2009
Circuit Performance Classification With Active Learning Guided Sampling for Support Vector Machines
Pass/Fail Data for Logic Diagnosis Under Bounded Transparent Scan
A Deflection-Based Deadlock Recovery Framework to Achieve High Throughput for Faulty NoCs
A Novel Layout Decomposition Algorithm for Triple Patterning Lithography
Multiplication Through a Single Look-Up-Table (LUT) in CNN Inference Computation
A Fully Pipelined Reconfigurable Montgomery Modular Multiplier Supporting Variable Bit-Widths
Analytical Side Channel EM Models, Extending Simulation Abilities for ICs, and Linking Physical Models to Cryptographic Metrics
Sequential test generation and synthesis for testability at the register-transfer and logic levels
Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures
Cache-Aware Scratchpad-Allocation Algorithms for Energy-Constrained Embedded Systems
A Novel 3-D Dynamic Cellular Automata Model for Photoresist-Etching Process Simulation
Synthesis of arithmetic hardware using hardware metafunctions
RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency
Effect of the switching order on power dissipation inswitched-capacitor circuits
Energy-conscious, deterministic I/O device scheduling in hard real-time systems
Statistical Compact Model Extraction: A Neural Network Approach
A Monte Carlo approach for maximum power estimation based onextreme value theory
Logic Minimization and Testability of 2-SPP Networks
DARSI: RC data reduction [VLSI simulation]
SeVNoC: Security Validation of System-on-Chip Designs With NoC Fabrics
Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver
Instruction-Level NBTI Stress Estimation and Its Application in Runtime Aging Prediction for Embedded Processors
Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation
Power Grid Analysis and Optimization Using Algebraic Multigrid
A Branch-&-Bound Test-Access-Mechanism Optimization Method for Multi-V dd SoCs
On the verification of sequential machines at differing levels of abstraction
Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations
Cell-level placement for improving substrate thermal distribution
Application-specific worst case corners using response surfaces and statistical models
Hierarchical finite state machines with multiple concurrency models
Guest Editorial Special Section on Automotive Embedded Systems and Software
FPGA Architecture Optimization Using Geometric Programming
AdaMD: Adaptive Mapping and DVFS for Energy-Efficient Heterogeneous Multicores
Quasi-Simultaneous Solution Method: A New Highly Efficient Strategy for Numerical MOST Simulations
Efficient identification of (critical) testable path delay faults using decision diagrams
FPAX: A Fast Prior Knowledge-Based Framework for DSE in Approximate Configurations
Aliasing Reduction in Accumulator-Based Response Verification
ULSeq-TA: Ultra-Long Sequence Attention Fusion Transformer Accelerator Supporting Grouped Sparse Softmax and Dual-Path Sparse LayerNorm
Probabilistic constructive optimization techniques
Flamel: A High-Level Hardware Compiler
Reactant Minimization for Sample Preparation on Microfluidic Biochips With Various Mixing Models
Low-Power Digital Signal Processing Using Approximate Adders
Static electromigration analysis for on-chip signal interconnects
Boosting the Convergence of Reinforcement Learning-Based Auto-Pruning Using Historical Data
Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs
Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design
A new framework of design rules for compaction of VLSI layouts
Optimization by iterative improvement: an experimental evaluation on two-way partitioning
Multidomain Inter/Intrachip Silicon Photonic Networks for Energy-Efficient Rack-Scale Computing Systems
Analysis and generation of control and observation structures foranalog circuits
HotReRAM: A Performance-Power-Thermal Simulation Framework for ReRAM-Based Caches
Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs
Logic Synthesis of Binarized Neural Networks for Efficient Circuit Implementation
BAQE: Backend-Adaptive DNN Deployment via Synchronous Bayesian Quantization and Hardware Configuration Exploration
On the Stability of Analog ReLU Networks
Cellular Structure-Based Fault-Tolerance TSV Configuration in 3D-IC
Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size
The HEROIC Framework: Encrypted Computation Without Shared Keys
NAPA: Intermediate-Level Variational Native-Pulse Ansatz for Variational Quantum Algorithms
Hydrodynamic simulation of semiconductor devices operating at low temperature
A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking
A High-Performance Subcircuit Recognition Method Based on the Nonlinear Graph Optimization
Generation of Functional Broadside Tests for Transition Faults
Divide-and-concatenate: an architecture-level optimization technique for universal hash functions
Flexible Hotspot Detection Based on Fully Convolutional Network With Transfer Learning
Process-Variation Tolerant Channel-Adaptive Virtually Zero-Margin Low-Power Wireless Receiver Systems
An Optimal Pin-Count Design With Logic Optimization for Digital Microfluidic Biochips
A Flexible Parallel Simulator for Networks-on-Chip With Error Control
PSION+: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs
Real-Time Use-Aware Adaptive RF Transceiver Systems for Energy Efficiency Under BER Constraints
Routability-driven repeater block planning for interconnect-centricfloorplanning
Simultaneously Tolerate Thermal and Process Variations Through Indirect Feedback Tuning for Silicon Photonic Networks
Application-Driven Voltage-Island Partitioning for Low-Power System-on-Chip Design
Formal verification of memory circuits by switch-level simulation
Via design rule consideration in multilayer maze routing algorithms
APPLE-DSE: Asynchronous Parallel Pareto Set Learning for Microarchitecture Design Space Exploration
Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs
More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs
A Non-Minimal Routing Algorithm for Aging Mitigation in 2D-Mesh NoCs
Leakage-Aware Predictive Thermal Management for Multicore Systems Using Echo State Network
ProperTEST: a portable parallel test generator for sequential circuits
NEST: a nonenumerative test generation method for path delay faults in combinational circuits
The physical design of on-chip interconnections
Rebel: a clustering algorithm for look-up table FPGA's
Optimizing the Antenna Area and Separators in Layer Assignment of Multilayer Global Routing
Density-Uniformity-Aware Analog Layout Retargeting
A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations
Cost-Effective Error Detection Through Mersenne Modulo Shadow Datapaths
Retention-Aware DRAM Assembly and Repair for Future FGR Memories
An industrial view of electronic design automation
A simulation system for diffusive oxidation of silicon: a two-dimensional finite element approach
Multibank Optimized Redundancy Analysis Using Efficient Fault Collection
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing
Cell-Based Synthesis of Multiple Analog Filter and Oscillator Topologies Employing Graph
Identification of Threshold Functions and Synthesis of Threshold Networks
A New Symbolic Channel Router: YACR2
FlexBCM: Hybrid Block-Circulant Neural Network and Accelerator Co-Search on FPGAs
Efficient sparse matrix factorization for circuit simulation on vector supercomputers
MOOSE: a physically based compact DC model of SOI LD MOSFETs for analogue circuit simulation
Novel Design Strategy Toward A2 Trojan Detection Based on Built-In Acceleration Structure
Easily testable nonrestoring and restoring gate-level cellular array dividers
SPLIM: Bridging the Gap Between Unstructured SpGEMM and Structured In-Situ Computing
Optimizing Graph Algorithms in Asymmetric Multicore Processors
RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars
FPAD: a fuzzy nonlinear programming approach to analog circuit design
Multispeculative Addition Applied to Datapath Synthesis
A state assignment procedure for single-block implementation of state charts
Power-Aware Minimum NBTI Vector Selection Using a Linear Programming Approach
Defocus-Aware Leakage Estimation and Control
Functional Timing Analysis Made Fast and General
Modeling, Simulation, and Optimization of Electrowetting
LUTSim: A Look-Up Table-Based Thermal Simulator for 3-D ICs
An Analog Circuit Design and Optimization System With Rule-Guided Genetic Algorithm
A C infinity -continuous depletion capacitance model
Design and synthesis of self-checking VLSI circuits
CAD Systems for IC Design
A data-centric approach to high-level synthesis
Layout Generator for Transistor-Level High-Density Regular Circuits
A methodology for concurrent process-circuit optimization
Cooperative Buffer Management With Fine-Grained Data Migrations for Hybrid Memory Systems
Computer-Aided Minimization Procedure for Boolean Functions
Capture-Power-Safe Test Pattern Determination for At-Speed Scan-Based Testing
Mixed particle Monte Carlo method for deep submicron semiconductor device simulator
Activity-sensitive architectural power analysis
B-HTRecognizer: Bitwise Hardware Trojan Localization Using Graph Attention Networks
Automatic generation and targeting of application-specificoperating systems and embedded systems software
Network Analysis Approach to Multidimensional Modeling of Transistors Including Thermal Effects
A new built-in TPG method for circuits with random patternresistant faults
VLSI module placement based on rectangle-packing by the sequence-pair
Mitigating the Impact of ReRAM I-V Nonlinearity and IR Drop via Fast Offline Network Training
Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging
System-Level Effects of Soft Errors in Uncore Components
Relaxation-Based Electrical Simulation
On yield consideration for the design of redundant programmable logic arrays
A parallel implementation of an electrothermal simulation for GaAs MESFET devices
Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs
Policy optimization for dynamic power management
LiB: a CMOS cell compiler
CNN-on-AWS: Efficient Allocation of Multikernel Applications on Multi-FPGA Platforms
Redundancy Attack: Breaking Logic Locking Through Oracleless Rationality Analysis
Bulls-Eye: Active Few-Shot Learning Guided Logic Synthesis
A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs
Global Wiring by Simulated Annealing
Planar topological routing
On the assumptions contained in semiconductor yield models
Partitioning Interpolant-Based Verification for Effective Unbounded Model Checking
Incremental Improvement of Voltage Assignment
Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition
Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs
A Study of Variance Reduction Techniques for Estimating Circuit Yields
SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology
PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design Enablement
A Modified General Diode Equation
DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs
Universality of mobility-gate field characteristics of electrons in the inversion charge layer and its application in MOSFET modeling
Physically Secure Logic Locking With Nanomagnet Logic
Logic synthesis of multilevel circuits with concurrent error detection
VALO: A Versatile Anytime Framework for LiDAR-Based Object Detection Deep Neural Networks
Handling soft modules in general nonslicing floorplan usingLagrangian relaxation
Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks
Automatic Generation of Spatial Accelerator for Tensor Algebra
Analysis and future trend of short-circuit power
The intertool profile interchange format: an object-oriented approach [semiconductor technology CAD/CAM]
An efficient multigrid Poisson solver for device simulations
Design-specific path delay testing in lookup-table-based FPGAs
Quantum Circuit Design for Integer Multiplication Based on Schönhage-Strassen Algorithm
A modified Gummel method for the basic semiconductor device equations
PROWAVES: Proactive Runtime Wavelength Selection for Energy-Efficient Photonic NoCs
A g m /I D Methodology Based Data-Driven Search Algorithm for the Design of Multistage Multipath Feed-Forward-Compensated Amplifiers Targeting High Speed Continuous-Time ΣΔ-Modulators
Topological Optimization of Multiple-Level Array Logic
A Transform-Parametric Approach to Boolean Matching
Cost-Effective Power-Aware Core Testing in NoCs Based on a New Unicast-Based Multicast Scheme
Reducing SRAM Reading Power With Column Data Segment and Weights Correlation Enhancement for CNN Processing
Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes
A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits