yusuke1997/dblp-id-title huggingface dataset:
Retargetable compiled simulation of embedded processors using a machine description language
AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models
Reconfigurable Binding against FPGA Replay Attacks
Surrogate Lagrangian Relaxation: A Path to Retrain-Free Deep Neural Network Pruning
Auxiliary variables for BDD-based representation and manipulation of Boolean functions
Cluster-aware iterative improvement techniques for partitioning large VLSI circuits
Behavioral synthesis of field programmable analog array circuits
FOLD: Extreme Static Test Compaction by Folding of Functional Test Sequences
Analog and Mixed-Signal IC Modeling and Optimization: An Artificial Intelligence Perspective
System-level PVT variation-aware power exploration of on-chip communication architectures
A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters
Pareto Optimization of Analog Circuits Using Reinforcement Learning
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture
Stress-Induced Performance Shifts in 3D DRAMs
Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes
Load-balanced clock tree synthesis with adjustable delay buffer insertion for clock skew reduction in multiple dynamic supply voltage designs
A routing algorithm for graphene nanoribbon circuit
An Extended SystemC Framework for Efficient HW/SW Co-Simulation
High-Level Test Synthesis: A Survey from Synthesis Process Flow Perspective
Optimizing instruction TLB energy using software and hardware techniques
Guiding Formal Verification Orchestration Using Machine Learning Methods
Semi-Permanent Stuck-At Fault injection attacks on Elephant and GIFT lightweight ciphers
Deterministic replay for message-passing-based concurrent programs
Synchronizing AMS Assertions with AMS Simulation: From Theory to Practice
Degraded Mode-benefited I/O Scheduling to Ensure I/O Responsiveness in RAID-enabled SSDs
Deep Reinforcement Learning-Based Resource Allocation with Enhanced Perception and Low-Latency for Autonomous Driving in ISAC-aided VEC
Introduction to the Special Issue on Machine Learning for CAD/EDA
A Soft-Error Mitigation Approach Using Pulse Quenching Enhancement at Detailed Placement for Combinational Circuits
A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs
Improving the energy behavior of block buffering using compiler optimizations
Data Pruning-enabled High Performance and Reliable Graph Neural Network Training on ReRAM-based Processing-in-Memory Accelerators
Applying Pay-Burst-Only-Once Principle for Periodic Power Management in Hard Real-Time Pipelined Multiprocessor Systems
Application Mapping and Control-system Design for Microfluidic Biochips with Distributed Channel Storage
A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current
QuanDA: GPU Accelerated Quantitative Deep Neural Network Analysis
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration
Memristive-based Mixed-signal CGRA for Accelerating Deep Neural Network Inference
A codesign back-end approach for embedded system design
Partially Invariant Patterns for LFSR -Based Generation of Close-to-Functional Broadside Tests
Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection
Buffer Optimization and Dispatching Scheme for Embedded Systems with Behavioral Transparency
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration
Exploiting Chip Idleness for Minimizing Garbage Collection - Induced Chip Access Conflict on SSDs
Physics-Informed Learning Based Multiphysics Simulation for Fast Transient TSV Electromigration Analysis
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration
A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs
Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement
Composable thermal modeling and simulation for architecture-level thermal designs of multicore microprocessors
A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits
A Case for Precise, Fine-Grained Pointer Synthesis in High-Level Synthesis
An Efficient FPGA Architecture with Turn-Restricted Switch Boxes
Low-energy Pipelined Hardware Design for Approximate Medium Filter
Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPs
Conditional Diagnosability of k-Ary n-Cubes under the PMC Model
HAPE: Hardware-Aware LLM Pruning For Efficient On-Device Inference Optimization
MFIT : Multi-FIdelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures
Mixed Integer Programming based Placement Refinement by RSMT Model with Movable Pins
Concurrent Prediction of Timing and wire Length Using A Multi-Task Graph Neural Network
Battery voltage modeling for portable systems
SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow
HNM-CIM: An Algorithm-Hardware Co-designed SRAM-based CIM for Transformer Acceleration Exploiting Hybrid N:M Sparsity
High-Level Synthesis of Key-Obfuscated RTL IP with Design Lockout and Camouflaging
Constraints-driven scheduling and resource assignment
A code-motion pruning technique for global scheduling
On the crossing distribution problem
Machine Learning-based Defect Coverage Boosting of Analog Circuits under Measurement Variations
MCEmu: A Framework for Software Development and Performance Analysis of Multicore Systems
Cache optimization for embedded processor cores: An analytical approach
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks
Race analysis for systemc using model checking
A timing-driven design and validation methodology for embedded real-time systems
Cluster-cover a theoretical framework for a class of VLSI-CAD optimization problems
Effective congestion reduction for IC package substrate routing
Dynamic Per-Flow Queues in Shared Buffer TSN Switches
Distributed Machine Learning on Smart-Gateway Network toward Real-Time Smart-Grid Energy Management with Behavior Cognition
E 2 -VOR: An End-to-End En/Decoder Architecture for Efficient Video Object Recognition
A survey of fault tolerant methodologies for FPGAs
An Adaptive Markov Model for the Timing Analysis of Probabilistic Caches
Memory data organization for improved cache performance in embedded processor applications
Minimizing Stack Memory for Hard Real-Time Applications on Multicore Platforms with Partitioned Fixed-Priority or EDF Scheduling
Design Space Optimization of Shared Memory Architecture in Accelerator-rich Systems
Parallel Power Grid Analysis Based on Enlarged Partitions
Combining system scenarios and configurable memories to tolerate unpredictability
Instruction set synthesis with efficient instruction encoding for configurable processors
An energy characterization platform for memory devices and energy-aware data compression for multilevel-cell flash memory
FTT-NAS: Discovering Fault-tolerant Convolutional Neural Architecture
An Efficient Method of DRC Violation Prediction with a Serial Deep Learning Model
Multiway FPGA partitioning by fully exploiting design hierarchy
MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET
Structurally Secure Obfuscation: Assessing and Mitigating Structural Vulnerabilities in Circuits Obfuscation
Rethinking Logic Rewriting: Technology-Aware Subgraph Matching with Exact Synthesis
An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis
Generating Representative Test Sequences from Real Workload for Minimizing DRAM Verification Overhead
Reducing Contention in Shared Last-Level Cache for Throughput Processors
A retargetable parallel-programming framework for MPSoC
A Low-power Programmable Machine Learning Hardware Accelerator Design for Intelligent Edge Devices
Chip placement in a reticle for multiple-project wafer fabrication
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms
DDAM: Data Distribution-Aware Mapping of CNNs on Processing-In-Memory Systems
Verification work reduction methodology in low-power chip implementation
Dynamic security domain scaling on embedded symmetric multiprocessors
Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators
Logic Diagnosis with Hybrid Fail Data
Performance-constrained hierarchical pipelining for behaviors, loops, and operations
Multimode scan: Test per clock BIST for IP cores
Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement
Statistical Rare-Event Analysis and Parameter Guidance by Elite Learning Sample Selection
Sherlock: A Multi-Objective Design Space Exploration Framework
Opposite-phase register switching for peak current minimization
Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules
Overhead-aware energy optimization for real-time streaming applications on multiprocessor System-on-Chip
A Novel Hybrid Cache Coherence with Global Snooping for Many-core Architectures
P3: Privacy Preserving Positioning for Smart Automotive Systems
Simultaneous placement with clustering and duplication
Generating Current Constraints to Guarantee RLC Power Grid Safety
Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies
Hierarchical Statistical Leakage Analysis and Its Application
A framework for heterogeneous specification and design of electronic embedded systems in SystemC
Massively Parallel Logic Simulation with GPUs
Compact Modeling of Interconnect Circuits over Wide Frequency Band by Adaptive Complex-Valued Sampling Method
JAMS-SG: A Framework for Jitter-Aware Message Scheduling for Time-Triggered Automotive Networks
An open-source binary utility generator
Allocation of FIFO structures in RTL data paths
Design Space Exploration for Scalable DNN Accelerators Using a Memory-Centric Analytical Model for HW/SW Co-Design
A Model-Driven Engineering Methodology to Design Parallel and Distributed Embedded Systems
Computer Generation of Hardware for Linear Digital Signal Processing Transforms
D 3 PBO: Dynamic Domain Decomposition-based Parallel Bayesian Optimization for Large-scale Analog Circuit Sizing
Bipartitioning and encoding in low-power pipelined circuits
Hardware Trojans: Lessons Learned after One Decade of Research
Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices
Machine Learning Approaches for Efficient Design Space Exploration of Application-Specific NoCs
GNN-based Multi-bit Flip-flop Clustering and Post-clustering Design Optimization for Energy-efficient 3D ICs
Automatic design of application-specific reconfigurable processor extensions with UPaK synthesis kernel
A Comprehensive Survey of Attacks without Physical Access Targeting Hardware Vulnerabilities in IoT/IIoT Devices, and Their Detection Mechanisms
Guest Editorial: Current Trends in Low-Power Design
A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques
Scalable SMT-Based Equivalence Checking of Nested Loop Pipelining in Behavioral Synthesis
Generating realistic stimuli for accurate power grid analysis
Cluster assignment for high-performance embedded VLIW processors
Microarchitectural synthesis of performance-constrained, low-power VLSI designs
Analog layout retargeting using geometric programming
Security of Microfluidic Biochip: Practical Attacks and Countermeasures
Slicible rectangular graphs and their optimal floorplans
Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators
TEI-power: Temperature Effect Inversion-Aware Dynamic Thermal Management
GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning
Design Automation Techniques for Microfluidic Fully Programmable Valve Array Biochips: A Systematic Survey
An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA
A Special Section on Multicore Parallel CAD: Algorithm Design and Programming
A full lifecycle performance verification methodology for multicore systems-on-chip
An Efficient Area and Reliability Optimization Method for MPRM Circuits Based on High-dimensional Genetic Algorithm
Fault-based Built-in Self-test and Evaluation of Phase Locked Loops
Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware
Access pattern-based code compression for memory-constrained systems
Timing-aware power-optimal ordering of signals
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
A new viewpoint on code generation for directed acyclic graphs
FUBOCO: Structure Synthesis of Basic Op-Amps by FUnctional BlOck COmposition
Energy Efficient Boosting of GEMM Accelerators for DNN via Reuse
Heterogeneous Integration Supply Chain Integrity Through Blockchain and CHSM
Hardware-Enabled Pharmaceutical Supply Chain Security
A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits
GALS-Designer: A design framework for GALS software systems
Reusing an on-chip network for the test of core-based systems
A Mixed-Criticality Traffic Scheduler with Mitigating Congestion for CAN-to-TSN Gateway
A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints
A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability
Automatic Synthesis of FSMs for Enforcing Non-functional Requirements on MPSoCs Using Multi-objective Evolutionary Algorithms
Algorithms to compute bridging fault coverage of I DDQ test sets
Non-Preemptive Scheduling of Periodic Tasks with Data Dependencies in Heterogeneous Multiprocessor Embedded Systems
Runtime Stress Estimation for Three-dimensional IC Reliability Management Using Artificial Neural Network
Test Point Insertion for Multi-Cycle Power-On Self-Test
HeM3D: Heterogeneous Manycore Architecture Based on Monolithic 3D Vertical Integration
Domino Cache: An Energy-Efficient Data Cache for Modern Applications
CuPBoP: Making CUDA a Portable Language
Comparing Platform-aware Control Design Flows for Composable and Predictable TDM-based Execution Platforms
Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision
Thermal analysis of multiprocessor SoC applications by simulation and verification
Hardware/software synthesis of formal specifications in codesign of embedded systems
Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems
Postlayout optimization for synthesis of Domino circuits
SSAGA: SMs Synthesized for Asymmetric GPGPU Applications
Reverse Engineering Digital ICs through Geometric Embedding of Circuit Graphs
Scheduling Globally Asynchronous Locally Synchronous Programs for Guaranteed Response Times
Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware
Power-aware SoC test planning for effective utilization of port-scalable testers
Hierarchical power management for adaptive tightly-coupled processor arrays
Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface
Adaptive virtual channel partitioning for network-on-chip in heterogeneous architectures
High-performance clock mesh optimization
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip
Code placement techniques for cache miss rate reduction
t/t -Diagnosability of regular graphs under the PMC model
Structural diagnosis of interconnects by coloring
GPU-Based Parallelization for Fast Circuit Optimization
A Fast Optimal Double-row Legalization Algorithm
Efficient and Deterministic Parallel Placement for FPGAs
UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine
Approximate Data Reuse-based Accelerator Design for Embedded Processor
Learning From Sleeping Experts: Rewarding Informative, Available, and Accurate Experts
Implicit grading of multiple path delay faults
Multiprocessor Scheduling of a Multi-Mode Dataflow Graph Considering Mode Transition Delay
Performance-driven technology mapping with MSG partition and selective gate duplication
Harvesting Row-Buffer Hits via Orchestrated Last-Level Cache and DRAM Scheduling for Heterogeneous Multicore Systems
MaxSense: Side-channel Sensitivity Maximization for Trojan Detection Using Statistical Test Patterns
On-chip sensor-driven efficient thermal profile estimation algorithms
Implementation and Analysis of History-Based Output Channel Selection Strategies for Adaptive Routers in Mesh NoCs
CAD-Base: An Attack Vector into the Electronics Supply Chain
Analytical Placement with 3D Poisson's Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAs
Flip: Data-centric Edge CGRA Accelerator
On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays
Event propagation conditions in circuit delay computation
A Theoretical Foundation for Timing Synchronous Systems Using Asynchronous Structures
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography
SSA-AC: Static Significance Analysis for Approximate Computing
MESSI: Task Mapping and Scheduling Strategy for FPGA-based Heterogeneous Real-Time Systems
Processor virtualization for secure mobile terminals
ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems
Patchability-Driven Design Exploration for System-on-Chip Patching Architectures
Architectural Design of Flow-Based Microfluidic Biochips for Multi-Target Dilution of Biochemical Fluids
ICP-RL: Identifying Critical Paths for Fault Diagnosis Using Reinforcement Learning
Interval Arithmetic and Self-Similarity Based RTL Input Vector Control for Datapath Leakage Minimization
Processor modeling and code selection for retargetable compilation
Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis
Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Networks: Enhancing Circuit Reliability under Environmental Variation
A survey of Boolean matching techniques for library binding
Synthesis of a novel timing-error detection architecture
Divide and conquer high-level synthesis design space exploration
Improving the performance of port range check for network packet filtering
A Finite-Point Method for Efficient Gate Characterization Under Multiple Input Switching
Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design
A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture
Reducing Writebacks Through In-Cache Displacement
AIMCU-MESO: An In-Memory Computing Unit Constructed by MESO Device
Leakage-Aware Dynamic Thermal Management of 3D Memories
Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS
A Design Methodology for Energy-Aware Processing in Unmanned Aerial Vehicles
Static NBTI Reduction Using Internal Node Control
A recursive technique for computing lower-bound performance of schedules
Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode
Clock Period Minimization with Minimum Leakage Power
Chassis: A Platform for Verifying PMU Integration Using Autogenerated Behavioral Models
Compiler-Assisted and Profiling-Based Analysis for Fast and Efficient STT-MRAM On-Chip Cache Design
DANCE: DAta-Network Co-optimization for Efficient Segmentation Model Training and Inference
Algorithmic Fault Detection for RRAM-based Matrix Operations
Scaling Input Stimulus Generation through Hybrid Static and Dynamic Analysis of RTL
A Bridge-based Algorithm for Simultaneous Primal and Dual Defects Compression on Topologically Quantum-error-corrected Circuits
Optimizing wirelength and routability by searching alternative packings in floorplanning
A Hardware-Assisted Energy-Efficient Processing Model for Activity Recognition Using Wearables
Software/Hardware Co-design of 3D NoC-based GPU Architectures for Accelerated Graph Computations
Improving the Performance of CNN Accelerator Architecture under the Impact of Process Variations
Loop scheduling with timing and switching-activity minimization for VLIW DSP
A Systematic Mapping Study on SystemC/TLM Modeling Capabilities in New Research Domains
Provably efficient algorithms for resolving temporal and spatial difference constraint violations
EPHA: An Energy-efficient Parallel Hybrid Architecture for ANNs and SNNs
Lithography Hotspot Detection with FFT-based Feature Extraction and Imbalanced Learning Rate
A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers
Techniques for the synthesis of reversible Toffoli networks
Synthesis of low-power selectively-clocked systems from high-level specification
Efficient power modeling and software thermal sensing for runtime temperature monitoring
Near-optimal and scalable intrasignal in-place optimization for non-overlapping and irregular access schemes
Adversarial Perturbation Attacks on ML-based CAD: A Case Study on CNN-based Lithographic Hotspot Detection
Annealing placement by thermodynamic combinatorial optimization
Thread-based multi-engine model checking for multicore platforms
Buffer merging - a powerful technique for reducing memory requirements of synchronous dataflow specifications
Sorting it out in Hardware: A State-of-the-Art Survey
A Hierarchical HVAC Control Scheme for Energy-aware Smart Building Automation
Enabling IC Traceability via Blockchain Pegged to Embedded PUF
ATM switch design by high-level modeling, formal verification and high-level synthesis
Content-Aware Bit Shuffling for Maximizing PCM Endurance
Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield Gradient
Transistor placement for noncomplementary digital VLSI cell synthesis
A High-performance Masking Design Approach for Saber against High-order Side-channel Attack
Semantics and verification of action diagrams with linear timing
VFI-Based Power Management to Enhance the Lifetime of High-Performance 3D NoCs
A New Algorithm for VHDL Parallel Simulation
The open family of temporal logics: Annotating temporal operators with input constraints
BIST and production testing of ADCs using imprecise stimulus
A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations
Index-Resilient Zero-Suppressed BDDs: Definition and Operations
STCO: Enhancing Training Efficiency via Structured Sparse Tensor Compilation Optimization
Eliminating false loops caused by sharing in control path
Efficient Security Monitoring with the Core Debug Interface in an Embedded Processor
Performance-driven Wire Sizing for Analog Integrated Circuits
Error Rate Estimation for Defective Circuits via Ones Counting
Scenario-based timing verification of multiprocessor embedded applications
Single-Layer Obstacle-Aware Substrate Routing via Iterative Pin Reassignment and Wire Assignment
Marching-Based Wear-Leveling for PCM-Based Storage Systems
Investigating the Impact of Image Content on the Energy Efficiency of Hardware-accelerated Digital Spatial Filters
A Variation Tolerant Write Assist Read Decoupled 9T SRAM Cell for Low Voltage Application
RGMU: A High-flexibility and Low-cost Reconfigurable Galois Field Multiplication Unit Design Approach for CGRCA
Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics
Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback
Augmenting Operating Systems with OpenCL Accelerators
An Implication-based Test Scheme for Both Diagnosis and Concurrent Error Detection Applications