yusuke1997/dblp-id-title huggingface dataset:
Embedded architecture with hardware accelerator for target recognition in driver assistance system
Memory in processor: a novel design paradigm for supercomputing architectures
Improved parallel I/O via a two-phase run-time access strategy
Chip multi-processor scalability for single-threaded applications
A reply to comments "a comment on 'a hardware unification unit: design and analysis, '"
Review of Advances in computer architecture by Glenford J. Myers. John Wiley & Sons, Inc. 1982
Dynamic memory optimization using pool allocation and prefetching
Runtime multitasking support on polymorphic platforms
A discussion on non-blocking/lockup-free caches
Exploiting parallelism in a network of workstations using COMA-BC
Distributed scheduling algorithms to improve the performance of parallel data transfers
Comparison of hypercube, hypernet, and symmetric hypernet architectures
The first asynchronous microprocessor: the test results
Measured response times for page-sized fetches on a network
A leakage-energy-reduction technique for highly-associative caches in embedded systems
Microcoding an object-oriented instruction set
A temporal coding hardware implementation for spiking neural networks
Review of Advances in computer architecture by Glenford J. Myers. Wiley-Interscience Division of John Wiley and Sons 1978
Implementation of a programming environment with a multithread model for reconfigurable systems
A tagged token dataflow machine for computing small, iterative algorithms
A process-dependent partitioning strategy for cache memories
Publications on storage and systems research
GPU implementation and optimization of electromagnetic simulation using the FDTD method for antenna designing
VISA: A variable instruction set architecture
SPEC CPU2006 memory footprint
Warehouse-Scale Computing: Entering the Teenage Decade
A framework for adaptive routing in multicomputer networks
Parallelizing I/O intensive applications for a workstation cluster: a case study
Multiprocessor enhancements of the SimpleScalar tool set
Computer architecture and the cost of software
On cache memory hierarchy for Chip-Multiprocessor
Conversion of binary to single-term triple base numbers for DSP applications
AADC computer family architecture questions and answers
Storage assignment using expression tree transformations to generate compact and efficient DSP code
VLSI: machine architecture and very high level languages
Cache performance of the integer SPEC benchmarks on a RISC
An overview of techniques to support continuous retrieval of multimedia objects
Peering through the RISC/CISC fog: an outline of research
Domain-specific programmable design of scalable streaming-array for power-efficient stencil computation
A comparison of software code reordering and victim buffers
An FPGA Solver for Partial MaxSAT Problems Based on Stochastic Local Search
Pointer swizzling at page fault time: efficiently supporting huge address spaces on standard hardware
IOBENCH: a system independent IO benchmark
Message-passing algorithms for a SIMD torus with coteries
Performance analysis of a FPGA based novel binary and DBNS multiplier
On hardware enhanced 80386 software emulation, compiled emulation, a program distribution language, and pack computers
A reentrant peripheral interface
Scheduling parallel I/O operations
Using Pin as a memory reference generator for multiprocessor simulation
Register window architecture for multitasking applications
Hiding message delivery and reducing memory access latency by providing direct-to-cache transfer during receive operations in a message passing environment
GRT: A Reconfigurable SDR Platform with High Performance and Usability
Vector prefetching
Reliability and path length analysis of irregular fault tolerant multistage interconnection network
Pascal extensions for describing computer instruction sets
Performance analysis and workload characterization of the 3DMark05 benchmark on modern parallel computer platforms
Instability in parallel I/O systems
Shared cache multiprocessing with pack computers
Fast synchronization for chip multiprocessors
Reply to David R. Cheriton's, Pat Boyle's, and Gert A. Slavenburg's "Comments on 'Coherency for multiprocessor virtual addressed caches' by James R. Goodman"
Benchmark health considered harmful
Hardware support for self-healing software services
Semi-hierarchical approach for reliability, availability, and serviceability of cellular systems
A scalable, clustered SMT processor for digital signal processing
Design aspects of the delft parallel processor DPP84 and its programming system
Current literature: abstracts of articles of interest..
Ocean warning: avoid drowning
The architecture of the Burroughs B5000: 20 years later and still ahead of the times?
Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS
A novel associative memory architecture for quick matching
An introduction to computing with neural nets
Accelerating sequential Monte Carlo method for real-time air traffic management
Wisconsin Architectural Research Tool Set
Characterization of file I/O activity for SPEC CPU2006
SpinWise: A Practical Energy-Efficient Synchronization Technique for CMPs
A technique for passing reference parameters in an information-hiding architecture
Book Review: Practical Parallel Computing by Paul Messina and Almerico Murli, Editors: (John Wiley and Sons, 1992)
A chip prototyping substrate: the flexible architecture for simulation and testing (FAST)
Quick and easy cache performance analysis
Traces for hardware verification
Architecture for a multi-user general-purpose parllel system
Applying predication to efficiently handle runtime class testing
Profiling of parallel processing programs on shared memory multiprocessors using Simics
Notes from HPPAC 2005
HALSIM - a very fast SPARC V9 behavioral model
An analysis of C machine support for other block-structured languages
MediaBreeze: a decoupled architecture for accelerating multimedia applications
FPGA acceleration of CDO pricing based on correlation expansions
Java object look aside buffer for embedded applications
Risks of comparing RISCs
Efficient shared memory with minimal hardware support
Multicore reconfiguration platform an alternative to RAMPSoC
Overview of the Vesta parallel file system
The oxygen H21 handheld
History cache: hardware support for reverse execution
Executable instruction set specification
C++ benchmarks in SPEC CPU2006
A systematic approach to the design and implementation of a computer instruction set
Precise instruction scheduling without a precise machine model
Fault tolerant bus architecture for deep submicron based processors
Wide channel computers
Linear logic and permutation stacks - the Forth shall be first
A compiler optimization to reduce execution time of loop nest
On cacheability of lock-variables in tightly coupled multiprocessor systems
Snoopy cache test-and-test-and-set without execessive bus contention
Designing a high performance parallel logic programming system
Book Review: Logic Design Principles by Edward J. McCluskey: Prentice-Hall Publishers, Englewood Cliffs, New Jersey, 549 pp., $39.95
Future generation supercomputers I: a paradigm for node architecture
ffLink: A Lightweight High-Performance Open-Source PCI Express Gen3 Interface for Reconfigurable Accelerators
Energy-efficient dataflow computations on FPGAs using application-specific coarse-grain architecture synthesis
Improving the accuracy of indirect branch prediction via branch classification
Aliasing and anti-aliasing in branch history table prediction
Workshop on binary translation - 2001
Transparent debugging of dynamically instrumented programs
Graffiti on "the memory wall"
A subclass of Petri Nets as design abstraction for parallel architectures
A MEMS writer system embedded for a programmable optically reconfigurable gate array
The effect of employing advanced branching mechanisms in superscalar processors
Efficient emulations of interconnection networks
Evaluation criteria for abstract machines with unknown applications
Cache memory performance in a unix enviroment
A real innovation in computer architecture
How many operation units are adequate?
Axiom based architecture
CMP cache performance projection: accessibility vs. capacity
PEACH2: An FPGA-based PCIe network device for Tightly Coupled Accelerators
Design and development of framework for diagnosing intermediate nodes
Description and performance of a class of orthogonal multiprocessor networks
Efficient reconfigurable design for pricing asian options
Reply to the case against stack-oriented instruction sets
Some remarks on "Ambiguous Machine Architecture"
A new cache replacement scheme based on backpropagation neural networks
Review of the architecture of concurrent programs by Brinch Hansen. Prentice-Hall 1977
Accelerating finite difference time domain simulations with reconfigurable dataflow computers
TCgen 2.0: a tool to automatically generate lossless trace compressors
Searching for Sinks for the Hénon Map using a Multipleprecision GPU Arithmetic Library
Improving software pipelining with hardware support for self-spatial loads
A trace-level value predictor for Contrail processors
A high-performance object-oriented memory
OPA: a new architecture for Pascal-like languages
More on finding a single number to indicate overall performance of a benchmark suite
A single cached copy data coherence scheme for multiprocessor systems
Workshop report: synthesis of foo bars
A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface
A bibliography for multiprocessor cache memories
Dynamic power reduction of FPGA-based reconfigurable computers using precomputation
Disk arrays with multiple RAID levels
SPEC CPU2006 benchmark descriptions
Starvation-free commit arbitration policies for transactional memory systems
Book Review: SNMP, SNMPv2, and CMIP: The Practical Guide to Network Management Standards by William Stallings: (Addison-Wesley Publishing Company Inc. 1993)
A brief survey of benchmark usage in the architecture community
Power Performance Profiling of 3-D Stencil Computation on an FPGA Accelerator for Efficient Pipeline Optimization
Multiprocessor/distributed processing bibliography (in machine-readable form)
Extending the power of short-wordlength processors by means of context-dependent machine instructions
Performance Evaluations of Graph Database using CUDA and OpenMP Compatible Libraries
VariaSim: simulating circuits and systems in the presence of process variability
A workload characterization of elliptic curve cryptography methods in embedded environments
A microbenchmark suite for OpenMP 2.0
Design space exploration of adaptive beamforming acceleration for bedside and portable medical ultrasound imaging
Use of instruction set simulators to evaluate the LOW RISC
The chaos router: a practical application of randomization in network routing
Optimizing cache miss equations polyhedra
Binary acceleration using coarse-grained reconfigurable architecture
A report on the proposed IEEE Floating Point Standard (IEEE task p754)
IBM's Watson/DeepQA
Implementing the NHT-1 application I/O benchmark
The WM computer architecture
Adapting Tomasulo's algorithm for bytecode folding based Java processors
A comparison of microcode, assembly code, and high-level languages on the VAX-11 and RISC I
My next compiler
A High-speed Verilog HDL Simulation Method using a Lightweight Translator
Special Issue on Input/Output in Parallel Computer Systems: Introduction
An efficient implementation of Boolean functions nd finite state machine as self-timed circuit
Not multi-, but many-core: designing integral parallel architectures for embedded computation
The virtual machine
An architecture a day keeps the hacker away
DSNS (dynamically-hazard-resolved statically-code-scheduled, nonuniform superscalar): yet another superscalar processor architecture
VLSI and rule-based systems
Memory predecryption: hiding the latency overhead of memory encryption
Reducing cache conflicts in data cache prefetching
Task allocation in data flow multiprocessors: an annotated bibliography
Review of "The Computers that Saved Metropolis, by DC Comics and Radio Shack", July 1980
A project on high performance I/0 subsystems
A novel architecture for conversion of binary to single digit double base numbers
A novel approach to character interfaces
A Case Study in Reverse Engineering GPGPUs: Outstanding Memory Handling Resources
B-HIVE: a heterogeneous, interconnected, versatile and expandable multicomputer system
The architecture of a memory management unit for object-oriented systems
Multi-processor system description and simulation using structured multi-programming languages
WBT-2000: workshop on binary translation - 2000
Distributing and load-balancing for loops in scientific applications
Another general purpose computer architecture
How to simulate 1000 cores
A Study of Heterogeneous Computing Design Method based on Virtualization Technology
Wool-A work stealing library
A low overhead abstract architecture for FPGA resource management
NOBLE: non-blocking programming support via lock-free shared abstract data types
OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems
A new architecture for FPGA based implementation of conversion of binary to double base number system (DBNS) using parallel search technique
A study parallel disk organizations
Dataflow architecture for EEG patient monitor
ASM: application security monitor
Controlling program execution through binary instrumentation
Real time power estimation and thread scheduling via performance counters
Survey of commercial parallel machines
Design of high performance RAID in real-time system
Clock architecture and management
Selective-set-invalidation (SSI) for soft-error-resilient cache architecture
Reconfigurable Multiprocessor Systems: Handling Hydras Heads - A Survey
Modelling reconfigurable systems in event driven simulation
Object-based computer architecture
A Transfer-Aware Runtime System for Heterogeneous Asynchronous Parallel Execution
FPGA-based Connect6 solver with hardware-accelerated move refinement
Automatic memory layout transformations to optimize spatial locality in parameterized loop nests
Blueshell: a platform for rapid prototyping of multiprocessor NoCs and accelerators
An optimal floating point format
Book Review: Internetworking with TCP/IP vol. III: Client-Server programming and applications (BSD Sockets version) by Douglas E. Comer and David L. Stevens (Prentice-Hall, 1993)
Book review: The 68000 and 68020 Microprocessors: Hardware, Software and Interfacing Techniques by W. Triebel and A. Singh (Prentice Hall, 1991)
PDOC - a database on paralel processing literature
Introducing the notion of processes to hardware
Eliminating operand read latency
An electro-optic data communication system for the Delft parallel processor
Secondary cache performance in RISC architecture
Efficient custom computing of fully-streamed lattice boltzmann method on tightly-coupled FPGA cluster
BASS: a benchmark suite for evaluating architectural security systems
RISC watch
Performance evaluation of 3-D stacked 32-bit parallel multipliers
Memory performance: dealing with applications, systems and architecture
Telecommunicators and telecommuters: making multiple-site documentation projects work
Improving applications performance: a memory model and cache architecture
RISCY patents
Servo: a programming model for many-core computing
Realizing high IPC through a scalable memory-latency tolerant multipath microarchitecture
DMA considerations on RISC workstations
Bi-directional networks for large parallel processors
Some results concerning clock-regulated queues
Programming, compilation, and resource management issues for multithreading (panel session II)
MCF: a military computer family for computer-based systems
Instruction execution sequence confirmation
The significance of microprogramming
More data on the O/W ratios: a note on a paper by Flynn
Stream Computation of Shallow Water Equation Solver for FPGA-based 1D Tsunami Simulation
Semantics of an algorithm
Should SCC set condition codes?
Effort, resources, and abstraction vs performance in high-level synthesis: finding new answers to an old question
Combinatorial power in multimedia processors
A question of style
BadgerTrap: a tool to instrument x86-64 TLB misses
Comments on "'Coherency for multiprocessor virtual addresses caches' by James R. Goodman"
Direct-execution computer architecture
lnternet Nuggets
The UT1000 microprogramming simulator: an educational tool
A performance evaluation of the Intel 80286
Structuring an instruction cache
Book Review: Computer Architecture by Mario De Blasi: (Addison-Wesley Publishing Company, 1990)
The SimpleScalar tool set, version 2.0
The potential of thread-level speculation based on value profiling
CoreSymphony: an efficient reconfigurable multi-core architecture
Run-time reconfigurability in embedded multiprocessors
Modelling and performance evaluation of multiprocessors, organizations with multi-memory units
Accelerating Breadth First Search on GPU-BOX
An FPGA-based fast classifier with high generalization property
Flow-control machines: the structured execution architecture (SXA)
On the use of stacks in the evaluation of expressions
A domain-specific approach for software development on Manycore platforms
A non-volatile reconfigurable offloader for wireless sensor nodes
Fresh Breeze: a multiprocessor chip architecture guided by modular programming principles
Mapping streaming architectures on reconfigurable platforms
A simultaneous multithreading simulator
Limits of task-based parallelism in irregular applications
Review of Computer design by Glen G. Langdon. Computeach Press
8th annual symposium on computer architecture: heterogeneous computer architecture
LIDE: a simulation environment for shared virtual memory systems
HTGL: a program modelling language
Distributed shared memory multiprocessor architecture MEMSY for high performance paralel computations
Low power techniques for an android based phone
Book review of The structure of computers and computations: volume one by David J. Kuck. John Wiley & Sons 1978
Adapting the DySER Architecture with DSP Blocks as an Overlay for the Xilinx Zynq
Dynamic refresh method for dynamic RAMs
Session types: towards safe and fast reconfigurable programming
Multitasking as a program structuring primitive
A high speed mechanism for short branches
Dusty caches for reference counting garbage collection
Queuing theoretic model for a multiprocessor with private caches and shared memory
On "hot spot" contention
A modular network for dense optical interconnection of processing elements
The design of an asynchronous microprocessor
A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns
Characterizing antivirus workload execution
Model checking race-freeness
Techniques for fast simulation of associative cache directories
Review of The structure of computers and computation Vol. I by David J. Kuck. John Wiley & and Sons 1978
SPEC CPU suite growth: an historical perspective
Probabilistic Directed Writebacks for Exclusive Caches
The collapsed LAN: a solution to a bandwidth problem?
A multi-level parallelism architecture
Book review of "High-performance computer architecture by Harold S. Stone. Addison-Wesley 1987
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
What should graduate students know before joining a large computer architecture project?
Fast and Accurate Optical Flow Estimation using FPGA
A centrally controlled shuffle network for reconfigurable and fault-tolerant architecture
Why not innovations in computer architecture?
Beyond striping: the bridge multiprocessor file system
Asynchronous shared memory parallel computation (preliminary version)
Introduction to the special issue on the 2006 reconfigurable and adaptive architecture workshop
Performance implications of single thread migration on a chip multi-core
Instruction translation for an experimental S/390 processor
Performance evaluation for various configuration of superscalar processors
Parallelism Level Impact on Energy Consumption in Reconfigurable Devices
Addressable WSI: a non-redundant approach
Performance of the KORA-2 cache replacement scheme
A proposed high-speed computer design
Opinion: stay on course with an evolution or choose a revolution in computing
More on microprocessors of the future
Improving instruction level parallelism through reconfigurable units in superscalar processors
A comparison of three current superscalar designs
A hardware mechanism for priority queue
High performance phylogenetic analysis on CUDA-compatible GPUs
The case for crypto protocol awareness inside the OS kernel
Towards the issues in architectural support for protection of software execution
Hardware detection of undefined references
International workshop performance evaluation - origins and directions
Multimedia: towards an electronic performance support system
The case for the sustained performance computer architecture
In the current literature
Two economical directory schemes for large-scale cache coherent multiprocessors
The cognitive architecture project
Cache and Memory Hierarchy Design: A Performance-Directed Approach by Steven A.Przybylski
Report of the 1993 workshop on rapid prototyping of microelectronic systems for universities
Book Review: High-Speed Digital Design: A Handbook of Black Magic by Howard W. Johnson and Martin Graham: (Prentice-Hall, 1993)
Augmenting DR-ASIP flexibility through multi-mode custom instructions
An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division
Cache coherence for large scale shared memory multiprocessors
In memoriam - SIGARCH founder: Caxton C. Foster
Design for fast DSP machine
NICE: an elegant and powerful 32-bit architecture
Parallelization, performance analysis, and algorithm consideration of Hough transform on chip multiprocessors
Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction
GPU and FPGA Acceleration of Level Set Method
Review of High-level language computer architecture by Yaohan Chu. Academic Press, New York, 1975
Book review: Multiprocessors by Daniel Tabak (Prentice Hall, Englewood Cliffs, NJ)
TESLA: an extended study of an energy-saving agent that leverages schedule flexibility
Big Brother Logic: visual-epistemic reasoning in stationary multi-agent systems
Constructing a unifying theory of dynamic programming DCOP algorithms via the generalized distributive law
Allocating training instances to learning agents for team formation
Hypertension and total-order forward decomposition optimizations
Negotiation in exploration-based environment
Artifacts in the A&A meta-model for multi-agent systems
Learning and Exploiting Relative Weaknesses of Opponent Agents
Team-wise effective communication in multi-agent reinforcement learning
Mechanisms for environments in multi-agent systems: Survey and opportunities
Verification of multi-layered assignment problems
Automated Test Case Generation for BDI Agents
Tropos: An Agent-Oriented Software Development Methodology
Coordination in a Content-Addressable Web
Animate Characters
A context-aware convention formation framework for large-scale networks
Petri Net Plans - A framework for collaboration and coordination in multi-robot systems
Disagree and commit: degrees of argumentation-based agreements
Manipulation-resistant false-name-proof facility location mechanisms for complex graphs
Continual planning and acting in dynamic multiagent environments
Comparing variants of strategic ability: how uncertainty and memory influence general properties of games
Protocol Moderators as Active Middle-Agents in Multi-Agent Systems
Field D* path-finding on weighted triangulated and tetrahedral meshes
Personalised electric vehicle charging stop planning through online estimators
BDD-versus SAT-based bounded model checking for the existential fragment of linear temporal logic with knowledge: algorithms and their performance
Diagnosis of coordination failures: a matrix-based approach
Simulating protection rackets: a case study of the Sicilian Mafia
How to trust a few among many
Modelling the Sensory Abilities of Intelligent Virtual Agents
Distributed Belief Revision
An inquiry dialogue system