yusuke1997/dblp-id-title huggingface dataset:
The Feedforward Short-Time Fourier Transform
Reconfigurable biologically inspired visual motion systems using modular neuromorphic VLSI chips
A 12b 50 MS/s 21.6 mW 0.18 mum CMOS ADC Maximally Sharing Capacitors and Op-Amps
A Fully Flexible Circuit Implementation of Clique-Based Neural Networks in 65-nm CMOS
Optimal and self-tuning State estimation for singular stochastic systems: a polynomial equation approach
A Note on Observers for Discrete-Time Lipschitz Nonlinear Systems
Self-Calibration-Based Robust Near-Field Adaptive Beamforming for Microphone Arrays
A Quasi-V 2 Hysteretic Buck Converter With Adaptive COT Control for Fast DVS and Load-Transient Response in RF Applications
On Pulse Position Modulation and Its Application to PLLs for Spur Reduction
Condensed recursive structures for computing multidimensional DCT/IDCT with arbitrary length
A Supply-Noise-Insensitive Digitally-Controlled Oscillator
Stability and Sensitivity Analysis of Uniformly Sampled DC-DC Converter With Circuit Parasitics
Stability of impulsive linear differential equations with time delay
Continuous-Time Analog Two-Dimensional IIR Beam Filters
Random Walk Guided Decap Embedding for Power/Ground Network Optimization
A Parameter-Selection-Based Chaotic System
Applications of Body Biasing in Multistage CMOS Low-Noise Amplifiers
A 0.5-V Supply, 36 nW Bandgap Reference With 42 ppm/°C Average Temperature Coefficient Within -40 °C to 120 °C
Digital Blind Background Calibration of Imperfections in Time-Interleaved ADCs
An 86% Efficiency, Wide-V in SIMO DC-DC Converter Embedded in a Car-Radio IC
Implementation of Locally-Clocked XBM State Machines on FPGAs Using Synchronous CAD Tools
New High-Speed Multioutput Carry Look-Ahead Adders
A Nanopower Biopotential Lowpass Filter Using Subthreshold Current-Reuse Biquads With Bulk Effect Self-Neutralization
RF/DSP Codesign Methodology of Enhanced Doherty Amplifiers
Determining the Range of the Power Consumption in Linear DC Interval Parameter Circuits
Global Finite-Time Stabilization of Planar Linear Systems With Actuator Saturation
Analysis of hbox IM 3 Asymmetry in MOSFET Small-Signal Amplifiers
Gated-diode amplifiers
Corrections to "A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing"
Dual-Tree Error Compensation for High Performance Fixed-Width Multipliers
Dynamic Slew Enhancement Technique for Improving Transient Response in an Adaptively Biased Low-Dropout Regulator
A Systematic Design Methodology for Optimization of Sigma-Delta Modulators Based on an Evolutionary Algorithm
DC-Balance Low-Jitter Transmission Code for 4-PAM Signaling
Low-Cost Fast VLSI Algorithm for Discrete Fourier Transform
Characterization of B-spline digital filters
On the Security of Chaotic Convolutional Coder
A Multilevel Code-Shifted Differential Chaos Shift Keying System With Reference Diversity
A Galvanically Isolated DC-DC Converter Based on Current-Reuse Hybrid-Coupled Oscillators
Variable Step-Size Affine Projection Sign Algorithm
A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration
Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology
76-dB DR, 48 fJ/Step Second-Order VCO-Based Current-to-Digital Converter
A Low-Power 12-Bit Extended Counting ADC Without Calibration for CMOS Image Sensors
Transmit Designs for Spectral Coexistence of MIMO Radar and MIMO Communication Systems
Stability Analysis of Nonlinear System Identification via Delayed Neural Networks
Self-Dithering Technique for High-Resolution SAR ADC Design
Corrections to "Expandable Networks for Neuromorphic Chips"
Novel Block-Formulation and Area-Delay-Efficient Reconfigurable Interpolation Filter Architecture for Multi-Standard SDR Applications
A 5-mW 750-kb/s Noninvasive Transceiver for Around-the-Head Audio Applications
Adaptive Background Estimation for Static Nonlinearity Mismatches in Two-Channel TIADCs
Preferred Transmission Frequency for Size-Constrained Ultralow-Power Short-Range CMOS Oscillator Transmitters
Optimizing Performance of Communication Networks: An Application of Network Science
Correction of Mismatches in a Time-Interleaved Analog-to-Digital Converter in an Adaptively Equalized Digital Communication Receiver
Highly Parallel Vector Radix FFT for High Throughput Video Applications
WLAN security processor
Effects of UHF stimulus and negative feedback on nonlinear circuits
Data-Based H ∞ Control for the Constrained-Input Nonlinear Systems and its Applications in Chaotic Circuit Systems
FPGA Vernier Digital-to-Time Converter With 1.58 ps Resolution and 59.3 Minutes Operation Range
A Histogram-Based Background Interstage Error Estimation and Implementation Method in Pipelined ADCs
A Wavelet-Collocation-Based Trajectory Piecewise-Linear Algorithm for Time-Domain Model-Order Reduction of Nonlinear Circuits
An 11-bit 100-MS/s Pipelined-SAR ADC Reusing PVT-Stabilized Dynamic Comparator in 65-nm CMOS
An ON-OFF log domain circuit that recreates adaptive filtering in the retina
A 2.0 Gb/s Throughput Decoder for QC-LDPC Convolutional Codes
Consideration of Volterra Series With Excitation and/or Impulse Responses in the Form of Dirac Impulses
Double-Input Converters Based on H-Bridge Cells: Derivation, Small-Signal Modeling, and Power Sharing Analysis
Conjugate Symmetric Discrete Orthogonal Transform
A Fully-Printed Self-Biased Polymeric Audio Amplifier for Driving Fully-Printed Piezoelectric Loudspeakers
A Novel Hybrid Active Inductor
Circuit Synthesis for Guaranteed Positive Sparse Realization of Passive State-Space Models
A 37.5 µW Body Channel Communication Wake-Up Receiver With Injection-Locking Ring Oscillator for Wireless Body Area Network
Systematic Methods for the Implementation of Nonlinear Wave-Digital Structures
Mean Stability of Positive Markov Jump Linear Systems With Homogeneous and Switching Transition Probabilities
Anomaly Detection in Moving-Camera Video Sequences Using Principal Subspace Analysis
An Extended Kalman Filtering Approach to Nonlinear Time-Delay Systems: Application to Chaotic Secure Communications
EMI-Resistant CMOS Differential Input Stages
A 51.3-MHz 21.8-ppm/°C CMOS Relaxation Oscillator With Temperature Compensation
Single-Bin DFT-Based Digital Calibration Technique for CDAC in SAR ADCs
Symmetry Study for Delta- Operator-Based 2-D Digital Filters
Calculation of the Performance of Communication Systems From Measured Oscillator Phase Noise
Low-Power G m -C Filter Employing Current-Reuse Differential Difference Amplifiers
Set-Membership Filtering for State-Saturated Systems With Mixed Time-Delays Under Weighted Try-Once-Discard Protocol
A Pseudorandom Number Generator Based on Time-Variant Recursion of Accumulators
A Transconductor and Tunable G m -C High-Pass Filter Linearization Technique Using Feedforward G m3 Canceling
Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability
Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design
Arbitrary waveform DDFS utilizing Chebyshev polynomials interpolation
IMD of Closed-Loop Filterless Class D Amplifiers
High-Resolution Time-Interleaved Eight-Channel ADC for Li-Ion Battery Stacks
Three-stage burst-mode transimpedance amplifier in deep-sub-μm CMOS technology
Fast Start-Up RF Energy Harvester Design for GSM-900 Uplink Band
A time-interleaved recursive loop band-pass delta-sigma modulator for a digital IF CDMA receiver
Physically Unclonable Functions Derived From Cellular Neural Networks
Asynchronous Measurement of Transient Phase-Shift Resulting From RF Receiver State-Change
Auto-Erasable RRAM Architecture Secured Against Physical and Firmware Attacks
Optimized Interpolation and Cached Data Access in LUT-Based RGB-to-RGBW Conversion
Efficient Halfband FIR Filter Structures for RF and IF Data Converters
A 12-bit Multi-Channel R-R DAC Using a Shared Resistor String Scheme for Area-Efficient Display Source Driver
A 140-Mb/s to 1.82-Gb/s Continuous-Rate Embedded Clock Receiver for Flat-Panel Displays
A Wide-Band CMOS LC VCO With Linearized Coarse Tuning Characteristics
Wideband, Bandpass, and Versatile Hybrid Filter Bank A/D Conversion for Software Radio
A Thermal/RF Hybrid Energy Harvesting System With Rectifying-Combination and Improved Fractional-OCV MPPT Method
Closed-Form Design of Digital IIR Integrators Using Numerical Integration Rules and Fractional Sample Delays
Fourier Analysis of Signal Waveforms in An Ideal Concurrent Dual-Band Class-D Power Amplifier
A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL
Degree-Matched Check Node Decoding for Regular and Irregular LDPCs
A new diagnosis approach for handling tolerance in analog and mixed-signal circuits by using fuzzy math
Small Perturbation Harmonic Coupling in Nonlinear Periodicity Preservation Circuits
Design of Monolithic Low Dropout Regulator for Wireless Powered Brain Cortical Implants Using a Line Ripple Rejection Technique
Digital Cancellation of Harmonic and Intermodulation Distortion in Wideband SAW-Less Receivers
A 60-GHz CMOS Dual-Mode Power Amplifier With Efficiency Enhancement at Low Output Power
Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing - Part II: Multiplication and Algebraic Functions
H ∞ Pinning Synchronization of Directed Networks With Aperiodic Sampled-Data Communications
Effects of Measurement Noise on Flocking Dynamics of Cucker-Smale Systems
The Universal Circuit Simulator: A Mixed-Signal Approach to n-Port Network and Impedance Synthesis
A 130 nm 165 nJ/frame Compressed-Domain Smashed-Filter-Based Mixed-Signal Classifier for "In-Sensor" Analytics in Smart Cameras
A Reconfigurable Direct RF Receiver With Jitter Analysis and Applications
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs
Simple, Fast, and Exact RNS Scaler for the Three-Moduli Set 2 n - 1, 2 n , 2 n + 1
Transmission-Line Class-E Power Amplifier With Extended Maximum Operating Frequency
On the Synchronization Condition for Superharmonic Coupled QVCOs
A CMOS Colpitts VCO Using Negative-Conductance Boosted Technology
Connecting border collision with saddle-node bifurcation in switched dynamical systems
Compact Code-Based Signature for Reconfigurable Devices With Side Channel Resilience
Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration
Sampled-Data Modeling of Switched- Capacitor Voltage Regulator With Frequency-Modulation Control
A 12-bit 20 MS/s 56.3 mW Pipelined ADC With Interpolation-Based Nonlinear Calibration
Fast State-Space Harmonic-Distortion Estimation in Weakly Nonlinear G m -C Filters
Discrete Implementation and Linearization of a New Polar Modulator-Based Mixerless Wireless Transmitter Suitable for High Reconfigurability
Reinforcement Learning-Based Control of Nonlinear Systems Using Lyapunov Stability Concept and Fuzzy Reward Scheme
A Multicast Tree Router for Multichip Neuromorphic Systems
A Dynamic Circuit-Based Ferromagnetic Model
An Effective Selective Detection Scheme Based on Pulse Repetition for Noncoherent UWB Systems
Generation of a Clocking Signal in Synchronized All-Digital PLL Networks
An FPGA Implementation of the Resolve Time-Based True Random Number Generator With Quality Control
VWA: Hardware Efficient Vectorwise Accelerator for Convolutional Neural Network
Design of Class-E M Oscillator With Second Harmonic Injection
A 55-GHz-Bandwidth Track-and-Hold Amplifier in 28-nm Low-Power CMOS
The Design of an Operational Amplifier Using Silicon Carbide JFETs
Predistortion of Radio Over Fiber Links: Algorithms, Implementation, and Measurements
Finding the Tuning Curve of a CMOS - LC VCO
CMOS High-Efficiency Wireless Battery Charging System With Global Power Control Through Backward Data Telemetry for Implantable Medical Devices
Robust Switching Control of the Direct-Drive Servo Control Systems Based on Disturbance Observer for Switching Gain Reduction
A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation
Improved Sorting Architecture for K-Best MIMO Detection
I/Q Imbalance Compensation in Wideband Millimeter-Wave Transmitters Using a Single Undersampling ADC
Global Asymptotic Stability of 2-D Digital Filters With a Saturation Operator on the State-Space
A CMOS Injection-Locked Frequency Divider Optimized for Divide-by-Two and Divide-by-Three Operation
Correcting the Effects of Mismatches in Time-Interleaved Analog Adaptive FIR Equalizers
A Normalized Figure of Merit for Capacitive Accelerometer Interface Circuits
A Time-Domain High-Order MASH ΔΣ ADC Using Voltage-Controlled Gated-Ring Oscillator
Time-Domain Modeling of an RF All-Digital PLL
Dual-/Tri-Band Branch Line Couplers With High Power Division Isolation Using Coupled Lines
System Design for Direct RF-to-Digital ΔΣ Receiver
Low-Power Time Deinterleaver for ISDB-T Receiver
A Resistive Degeneration Technique for Linearizing Open-Loop Amplifiers
An ISM Band High-Linear Current-Reuse Up-Conversion Mixer With Built-in-Self-Calibration for LOFT and I/Q Imbalance
A Multilevel Code Shifted Differential Chaos Shift Keying Scheme With Code Index Modulation
Computation of Steady-State Oscillations in Power Converters Through Complementarity
A Fully Synthesizable Ultra- ${N}$ Audio Frequency Multiplier for HDMI Applications
Simple instability criterion for a class of uncertain discrete systems
Parallel scrambler for high-speed applications
A Novel Approach to Overcome the Limitations of Reliability Centered Maintenance Implementation on the Smart Grid Distance Protection System
Time-Delayed Chaotic Circuit Design Using All-Pass Filter
State Metric Compression Techniques for Turbo Decoder Architectures
New current-mode wave-pipelined architectures for high-speed analog-to-digital converters
A GaAs Colpitts VCO Using g m -Boosting and Collector-Emitter Cross-Coupling Techniques
A 12.8-Gb/s Quarter-Rate Transmitter Using a 4: 1 Overlapped Multiplexing Driver Combined With an Adaptive Clock Phase Aligner
A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM
High-Performance Implementation of Point Multiplication on Koblitz Curves
A 0.9-µ A Quiescent Current Output-Capacitorless LDO Regulator With Adaptive Power Transistors in 65-nm CMOS
Nonlinear Phase-Domain Macromodeling of Injection-Locked Frequency Dividers
A 4th Order 3.6 GS/s RF ΣΔ ADC With a FoM of 1 pJ/bit
Fault Localization Strategy for Modular Multilevel Converters in Rectifier Mode Under Submodule Switch Open-Circuit Failure
The Design and Analysis of Dual-Delay-Path Ring Oscillators
A Rigorous Approach to the Robust Design of Continuous-Time Sigma-Delta Modulators
Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination
Further Desensitized FIR Halfband Filters
A 5.8 GHz Digitally Controlled CMOS Receiver With a Wide Dynamic Range for Chinese ETC System
A Volterra-Based Procedure for Multi-Port and Multi-Zone GaN FET Amplifier CAD Simulation
Periodic Pattern Formation and Its Applications in Cellular Neural Networks
A low-power silicon on sapphire CMOS optoelectronic receiver using low- and high-threshold devices
A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques
Synchronization in Networks of Diffusively Time-Delay Coupled (Semi-)Passive Systems
A 200-MS/s Phase-Detector-Based Comparator With 400-μV rms Noise
Controllability of Switching Signed Networks
Super-Resolution Time Delay Estimation in Multipath Environments
A 5-Gbit/s CMOS Optical Receiver With Integrated Spatially Modulated Light Detector and Equalization
A new radix-2/8 FFT algorithm for length-q×2 m DFTs
A Phase-Interpolation and Quadrature-Generation Method Using Parametric Energy Transfer in CMOS
A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI
A High-Performance Charge Pump Topology for Very-Low-Voltage Applications
Power-efficient FIR filter architecture design for wireless embedded system
Fast Sign Detection for RNS (2 n -1, 2 n , 2 n +1)
A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier
On Schur stable multivariate polynomials
A Novel Asynchronous Cellular Automaton Multicompartment Neuron Model
Improving the Performance of Chaos-Based Modulations Via Serial Concatenation
Precision Improvement of Power-Efficient Capacitive Senor Readout Circuit Using Multi-Nested Clocks
Second-Order Equivalent Circuits for the Design of Doubly-Tuned Transformer Matching Networks
Guest Editorial Special Issue on ISCAS 2011
A 6 $\mu$ W 95 dB SNDR Inverter Based $\Sigma\Delta$ Modulator With Subtractive Dithering and SAR Quantizer
Stability of Shift-Varying 2-D State-Space Digital Filters
Two-Parameter Discontinuity-Induced Bifurcation Curves in a ZAD-Strategy-Controlled DC-DC Buck Converter
Neural Synaptic Weighting With a Pulse-Based Memristor Circuit
Synchronizability of Duplex Networks
Finite-time tracking controller design for nonholonomic systems with extended chained form
High-Order Moment Filtering for Markov Jump Systems in Finite Frequency Domain
Stability of Synchronous Solutions in a Directed Kuramoto-Oscillator Network With a Pacemaker
Exploration of Second-Order Effects in High-Performance Continuous-Time ΣΔ Modulators Using Discrete-Time Models
An Improved Switch Compensation Technique for Inverted R-2R Ladder DACs
Stochastic Flash Analog-to-Digital Conversion
Area-Efficient On-Chip DC-DC Converter With Multiple-Output for Bio-Medical Applications
Generalization of the Normal Tree Method for Networks Without Graphic Structures
System-Efficiency Analysis of Power Amplifier Supply-Tracking Regimes in Mobile Transmitters
A 28-GHz 16-Gb/s High Efficiency 16-QAM Transmitter in 65-nm CMOS
Phase Noise Effect on Sine-Shaped Feedback DACs Used in Continuous-Time ΣΔ ADCs
Photonic RF and Microwave Integrator Based on a Transversal Filter With Soliton Crystal Microcombs
Efficient WLS Design of IIR Digital Filters Using Partial Second-Order Factorization
Analysis and Design of Transformer-Based Dual-Band VCO for Software-Defined Radios
Lightweight Hardware Architectures for the Present Cipher in FPGA
A High-Swing, High-Speed CMOS WTA Using Differential Flipped Voltage Followers
Error-Aware Design Procedure to Implement Hardware-Efficient Logarithmic Circuits
A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs
Sandberg's Representation Theorem and Classification of Linear Systems
Fuzzy Modelling and Consensus of Nonlinear Multiagent Systems With Variable Structure
Area-Time Efficient Streaming Architecture for FAST and BRIEF Detector
Offset-Free Nonlinear MPC for Mismatched Disturbance Attenuation With Application to a Static Var Compensator
A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response
Finite-Time Time-Variant Feedback Stabilization of Logical Control Networks With Markov Jump Disturbances
Observers-Based Synchronization and Input Recovery for a Class of Nonlinear Chaotic Models
FET-R-C Circuits: A Unified Treatment - Part II: Extension to Multi-Paths, Noise Figure, and Driving-Point Impedance
Initial and boundary conditions in multidimensional wave digital filter algorithms for plate vibration
In-Field Performance Optimization for mm-Wave Mixed-Signal Doherty Power Amplifiers: A Bandit Approach
Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices
Guaranteed cost control of uncertain differential linear repetitive processes
From Battery Enabled to Natural Harvesting: Enzymatic BioFuel Cell Assisted Integrated Analog Front-End in 130nm CMOS for Long-Term Monitoring
A 0.45-V 300-MHz 10T Flowthrough SRAM With Expanded write/ read Stability and Speed-Area-Wise Array for Sub-0.5-V Chips
Optimization and Implementation of a Viterbi Decoder Under Flexibility Constraints
Push-Pull Forward Three-Level Converter With Reduced Rectifier Voltage Stress
A Two-Step ADC With Statistical Calibration
A 20-Gb/s Transformer-Based Current-Mode Optical Receiver in 0.13-μm CMOS
Towards Accurate PWL Approximations of Parameter-Dependent Nonlinear Dynamical Systems With Equilibria and Limit Cycles
Improved memoryless RNS forward converter based on the periodicity of residues
Nonlinear Cognitive Signal Processing in Ultralow-Power Programmable Analog Hardware
A Robust Decentralized PID Controller Based on Complementary Sensitivity Function for a Multivariable System
Adaptive Beamforming for Vector-Sensor Arrays Based on a Reweighted Zero-Attracting Quaternion-Valued LMS Algorithm
Voltage and Current Selector-Based Biasing Topology for Multiple Supply Voltage Circuits
An Area-Efficient Fully R-DAC-Based TFT-LCD Column Driver
A DLL-Based Variable-Phase Clock Buffer
FPAP: A Folded Architecture for Energy-Quality Scalable Convolutional Neural Networks
All-Digital Adaptive Clocking to Tolerate Transient Supply Noise in a Low-Voltage Operation
Robust Structure Transformation for Causal Lagrange-Type Variable Fractional-Delay Filters
Injection-Locking-Based Power and Speed Optimization of CML Dividers
A Cognitive Radio System Using Discrete Wavelet Multitone Modulation
Design of a K-Band Chip Filter With Three Tunable Transmission Zeros Using a Standard 0.13-muhboxm CMOS Technology
Moving Horizon Estimation for Networked Systems With Quantized Measurements and Packet Dropouts
LDO-Free Power Management System: A 10-bit Pipelined ADC Directly Powered by Inductor-Based Boost Converter With Ripple Calibration
A 1-V 50-MHz Pseudodifferential OTA With Compensation of the Mobility Reduction
A 0.7-V 28-nW CMOS Subthreshold Voltage and Current Reference in One Simple Circuit
Black-Box Calibration for ADCs With Hard Nonlinear Errors Using a Novel INL-Based Additive Code: A Pipeline ADC Case Study
A 32-dB SNR Readout IC With 20-Vpp Tx Using On-Chip DM-TISM in HV BCD Process for Mutual-Capacitive Fingerprint Sensor
Cyber-Medical Systems: Requirements, Components and Design Examples
CMOS LC-oscillator phase-noise analysis using nonlinear models
A 220-mV Power-on-Reset Based Self-Starter With 2-nW Quiescent Power for Thermoelectric Energy Harvesting Systems
A Sensitive Method to Measure the Integral Nonlinearity of a Digital-to-Time Converter Based on Phase Modulation
On the Reachability Index of Positive 2-D Systems
A 0.45-V, 14.6-nW CMOS Subthreshold Voltage Reference With No Resistors and No BJTs
An Efficient Implementation of the Delay Compensation for Sub-Band Filtered-x Least-Mean-Square Algorithm
FSRFT - Fast Simplified Real Frequency Technique via Selective Target Data Approach for Broadband Double Matching
High-Efficiency PFM Boost Converter With an Accurate Zero Current Detector
An Algorithm to Compensate the Effects of Spurious PLL Tones in Spectrum Sensing Architectures
Hybrid Architecture Design for Calculating Variable-Length Fourier Transform
An All-Digital Scalable and Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells
Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS Circuits
Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits
A Low-Noise, Positive-Input, Negative-Output Voltage Generator for Low-to-Moderate Driving Capacity Applications
A 76-84 GHz CMOS 4× Subharmonic Mixer With Internal Phase Correction
A New Robust Kalman Filter-Based Subspace Tracking Algorithm in an Impulsive Noise Environment
Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation
A Dual-Band 2.45/6 GHz CMOS LNA Utilizing a Dual-Resonant Transformer-Based Matching Network
Characteristics of Dual Composite Right/Left-Handed Unit Cell and Its Applications to Bandpass Filter Design
Magnetics-Based Efficiency Optimization for Low Power Cascaded-Buck-Boost Converter
LMS adaptive filters using distributed arithmetic for high throughput
High-level synthesis of switched-capacitor, switched-current and continuous-time ΣΔ modulators using SIMULINK-based time-domain behavioral models
An Ultimate-Shannon-Limit-Approaching Gbps Throughput Encoder/Decoder System