yusuke1997/dblp-id-title huggingface dataset:
Self-Repairing Digital System With Unified Recovery Process Inspired by Endocrine Cellular Communication
Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code
High-Reliability and High-Throughput CIM 10T-SRAM for Multiplication and Accumulation Operations With 274.3 GOPS and 200-237.5 TOPS/W
High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors
KINA: Karatsuba Initiated Novel Accelerator for Ring-Binary-LWE (RBLWE)-Based Post-Quantum Cryptography
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V DDmin -Aware Dual Supply Voltage Technique
An Efficient 4-D 8PSK TCM Decoder Architecture
Principle Hessian Direction-Based Parameter Reduction for Interconnect Networks With Process Variation
VCNPU: An Algorithm-Hardware Co-Optimized Framework for Accelerating Neural Video Compression
High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture
Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding
Scalable Signal Selection for Post-Silicon Debug
FABSYN: floorplan-aware bus architecture synthesis
An Implementation Method for 100% ASK Modulation Applied to NFC Tags
A Robust Integrated Power Delivery Methodology for 3-D ICs
VLSI architectures for discrete wavelet transforms
HYFII: HYbrid Fault Injection Infrastructure for Accurate Runtime System Failure Analysis
A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs
Scalable Network-on-Chip Architectures for Brain-Machine Interface Applications
Low-Energy Two-Stage Algorithm for High Efficacy Epileptic Seizure Detection
Robust Hybrid Memristor-CMOS Memory: Modeling and Design
Embedded power supply for low-power DSP
A Fast Application-Based Supply Voltage Optimization Method for Dual Voltage FPGA
A 150 mW 8: 1 MUX and a 170 mW 1: 8 DEMUX for 2.4 gb/s optical-fiber communication systems using n-AlGaAs/i-InGaAs HJFET's
PEVA: A Page Endurance Variance Aware Strategy for the Lifetime Extension of NAND Flash
Delay Analysis for Current Mode Threshold Logic Gate Designs
A Histogram-Based Calibration Algorithm of Capacitor Mismatch for SAR ADCs
An Ultracompact Butterworth Low-Pass Filter Based on Coaxial Through-Silicon Vias
A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM
Bias-Dependent Variation in FinFET SRAM
A design space exploration scheme for data-path synthesis
Analysis of Resistive-Open Defects in SRAM Sense Amplifiers
Reliable Antifuse One-Time-Programmable Scheme With Charge Pump for Postpackage Repair of DRAM
A New CDMA Encoding/Decoding Method for on-Chip Communication Network
ASTRA: Reconfigurable Training Architecture Design for Nonlinear Softmax and Activation Functions in Transformers
Scenario-Aware Dynamic Power Reduction Using Bias Addition
Low-Power FPGA Design Using Memoization-Based Approximate Computing
Multi-objective optimization of interconnect geometry
Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism
A new algorithm for implementation of design functions by available devices
Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects
Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2023
Dynamic Choke Sensing for Timing Error Resilience in NTC Systems
Hybrid-Scheduling for Reduced Energy Consumption in High-Performance Processors
Fast and Scalable Multicore YOLOv3-Tiny Accelerator Using Input Stationary Systolic Architecture
Fault Emulation for Dependability Evaluation of VLSI Systems
Architectural Analysis for Wirelessly Powered Computing Platforms
Variable-Latency Floating-Point Multipliers for Low-Power Applications
The design of DNA self-assembled computing circuitry
A Configurable Monitoring Infrastructure for NoC-Based Architectures
A 3 GHz Wideband Σ Δ Fractional-N Synthesizer With Switched-RC Sample-and-Hold PFD
Self-Timed Design in GaAs - Case Study of a High-Speed, Parallel Multiplier
Litho-Friendly Decomposition Method for Self-Aligned Double Patterning
Toward architecture-based test-vector generation for timing verification of fast parallel multipliers
Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive
Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors
Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs
All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme
A New Architecture of a Two-Stage Lossless Data Compression and Decompression Algorithm
Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits
Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew
Fast Elliptic Curve Cryptography on FPGA
TDM Virtual-Circuit Configuration for Network-on-Chip
A Reliability-Oriented Startup Analysis of Injection-Locked Frequency Divider Based on Broken Symmetry Theory
Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range
Two-dimensional position detection system with MEMS accelerometers, readout circuitry, and microprocessor for padless mouse applications
High-level synthesis for low power based on network flow method
Comments on "Low-energy CSMT carry generators and binary adders"
A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS
Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators
A Novel x -ploiting Strategy for Improving Performance of Test Data Compression
ATEP: An Asynchronous Timing Error Prediction Circuit With Adaptive Voltage and Frequency Scaling
Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs
An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture
Flux-Controlled Memristor Emulator and Its Experimental Results
Bimodal Oscillation as a Mechanism for Autonomous Majority Voting in PUFs
High Signal-to-Noise Ratio and High-Sensitivity 4-D LiDAR Imaging Receiver
Protocol selection and interface generation for HW-SW codesign
Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors
Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via (TSV) Constraints
High-level address optimization and synthesis techniques for data-transfer-intensive applications
HW-FUTEX: Hardware-Assisted Futex Syscall
Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM
Microarchitecture Design Space Exploration via Pareto-Driven Active Learning
A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture
A Boosting Pass Gate With Improved Switching Characteristics and No Overdriving for Programmable Routing Switch Based on Crystalline In-Ga-Zn-O Technology
Electrical and Thermal Characteristics Optimization in Interposer-Based 2.5-D Integrated Circuits
Decoupling Capacitor Topologies for TSV-Based 3-D ICs With Power Gating
Two-Stage, Pipelined Register Renaming
A rated-clock test method for path delay faults
Designing Precharge-Free Energy-Efficient Content-Addressable Memories
A CMOS Image Sensor With On-Chip Image Compression Based on Predictive Boundary Adaptation and Memoryless QTD Algorithm
Defect Diagnosis via Segment Delay Learning
Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs
Hardware Efficient Mixed Radix-25/16/9 FFT for LTE Systems
High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators
Training Accelerator for Two Means Decision Tree
Electro-thermal and logi-thermal simulation of VLSI designs
Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks
High-Speed Algorithms and Architectures for Range Reduction Computation
A methodology for system-level synthesis of mixed-signal applications
A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells
A Repair-for-Diagnosis Methodology for Logic Circuits
Half-Precision Logarithmic Arithmetic Unit Based on the Fused Logarithmic and Antilogarithmic Converter
Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2 m ) Using Multiple Parity Prediction Schemes
Design and Implementation of a 6.5-Gb/s Multiradix Simplified Viterbi-Sphere Decoder for Trellis-Coded Generalized Spatial Modulation With Spatial Multiplexing
A Timing Mismatch Background Calibration Algorithm With Improved Accuracy
Reasoning and Learning-Based Dynamic Codec Reconfiguration for Varying Processing Requirements in Network-on-Chip
Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors
A design of a fast and area efficient multi-input Muller C-element
A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability
Flexible, Efficient Multimode MIMO Detection by Using Reconfigurable ASIP
A layout-based schematic method for very high-speed CMOS cell design
Area-Efficient Asynchronous Multilevel Single-Track Pipeline Template
Analysis and Calibration of Bit Weights in SAR and Pipelined SAR ADCs Based on Code Distribution
Monolithic Low-EMI CMOS DC-DC Boost Converter for Portable Applications
SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems
THETA: A High-Efficiency Training Accelerator for DNNs With Triple-Side Sparsity Exploration
Tight integration of timing-driven synthesis and placement of parallel multiplier circuits
Stability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression
DRAM-Based Intrinsic Physically Unclonable Functions for System-Level Security and Authentication
A clock power model to evaluate impact of architectural and technology optimizations
Design and Implementation of High-Speed All-Pass Transformation-Based Variable Digital Filters by Breaking the Dependence of Operating Frequency on Filter Order
A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-µm CMOS Technology
A Digital Low Dropout (LDO) Voltage Regulator Using Pseudoflash Transistors
Guest editorial: system level design
A simple yet effective technique for partitioning
Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs
Energy- and Area-Efficient Spin-Orbit Torque Nonvolatile Flip-Flop for Power Gating Architecture
A 2-D Calibration Scheme for Resistive Nonvolatile Memories
Human-Centric Computing
Efficient Pipelined Hardware Architecture for Depth-Map-Based Image Dehazing System
A Scalable and Efficient NTT/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering
Ultra-Low Power SAR ADC Using Statistical Characteristics of Low-Activity Signals
A jitter characterization system using a component-invariant Vernier delay line
A Pipelined Parallel Hardware Architecture for 2-D Real-Time Electrical Capacitance Tomography Imaging Using Interframe Correlation
Utilizing Reverse Short-Channel Effect for Optimal Subthreshold Circuit Design
Energy-Efficient Write Scheme for Nonvolatile Resistive Crossbar Arrays With Selectors
Temperature-Dependent Comparison Between Delay of CNT and Copper Interconnects
FPGA-Based Configurable and Highly Flexible PAM4 SerDes Simulation System
Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing
Reduced-Complexity LCC Reed-Solomon Decoder Based on Unified Syndrome Computation
Memory Optimized Hardware Implementation of Open FEC Encoder
Pulse-Based Prebond TSV Testing
Guest Editorial Special Section on Low-Power Electronics and Design
A Reliable Strong PUF Based on Switched-Capacitor Circuit
A Comparative Study of 20-Gb/s NRZ and Duobinary Signaling Using Statistical Analysis
Area-efficient high-throughput MAP decoder architectures
Automating Design of Voltage Interpolation to Address Process Variations
A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing
Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping
An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth
A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology
Correlation-Based Rectangular Encoding
Low-Power, Low-Noise Edge-Race Comparator for SAR ADCs
Modeling and Crosstalk Evaluation of 3-D TSV-Based Inductor With Ground TSV Shielding
Recursive Pseudo-Exhaustive Two-Pattern Generation
Hardware-Software Co-Design of Statistical and Deep-Learning Frameworks for Wideband Sensing on Zynq System on Chip
On Functional Broadside Tests With Functional Propagation Conditions
An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS
Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits
An Efficient Adaptive High Speed Manipulation Architecture for Fast Variable Padding Frequency Domain Motion Estimation
Improving Line-Based QCA Memory Cell Design Through Dual Phase Clocking
Mitigating Stuck Cell Failures in MLC NAND Flash Memory via Inferred Erasure Decoding
Circuits and architectures for field programmable gate array with configurable supply voltage
A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM
High-Performance Instruction-Set Hardware Accelerator for Ring-Binary-LWE-Based Lightweight PQC
Stochastic Power/Ground Supply Voltage Prediction and Optimization Via Analytical Placement
A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment
AC Computing Methodology for RF-Powered IoT Devices
Cogeneration of Fast Motion Estimation Processors and Algorithms for Advanced Video Coding
High-Performance and Small-Form Factor Near-Field Inductive Coupling for 3-D NoC
Parallel Thermal Analysis of 3-D Integrated Circuits With Liquid Cooling on CPU-GPU Platforms
An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification
Communication-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors
Clock-delayed domino for dynamic circuit design
A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors
Design and implementation of low-energy turbo decoders
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS
Power Management for Multicore Processors via Heterogeneous Voltage Regulation and Machine Learning Enabled Adaptation
Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems
Don't-Care Gating (DCG) TCAM Design Used in Network Routing Table
Flexible Hardware Processor for Elliptic Curve Cryptography Over NIST Prime Fields
A 45-nW 10-b 20-kS/s SAR ADC Based on Single-Capacitor Switching Scheme in 180-nm CMOS
Manipulated Lookup Table Method for Efficient High-Performance Modular Multiplier
Trojan Resilient Computing in COTS Processors Under Zero Trust
An area-efficient universal cryptography processor for smart cards
A Low-Cost TSV Test and Diagnosis Scheme Based on Binary Search Method
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC
Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors
Multiprocessor implementation of real-time DSP algorithms
Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks
Estimating Redundancy-Reliability of CNNs Based on Strip-Median Attributes
An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code
A hardware Gaussian noise generator using the Wallace method
Computing Two-Pattern Test Cubes for Transition Path Delay Faults
Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology
All-Digital Cost-Efficient CMOS Digital-to-Time Converter Using Binary-Weighted Pulse Expansion
Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master-Slave Flip-Flops
Asymmetric Aging: Introduction and Solution for Power-Managed Mixed-Signal SoCs
Low Complexity Out-of-Order Issue Logic Using Static Circuits
Hybrid Timestamping Using Crystal and RC Oscillators for Shock-Resistant Precision
Observation Points on State Variables for the Compaction of Multicycle Tests
Low-Complexity Hardware Design for Fast Solving LSPs With Coordinated Polynomial Solution
Supply Noise and Impedance of On-Chip Power Distribution Networks in ICs With Nonuniform Power Consumption and Interblock Decoupling Capacitors
MASTER: A Multicore Cache Energy-Saving Technique Using Dynamic Cache Reconfiguration
A new 2-D systolic digital filter architecture without global broadcast
Online Alignment and Addition in Multiterm Floating-Point Adders
Duet: an accurate leakage estimation and optimization tool for dual-V t circuits
Robust Fault Models Where Undetectable Faults Imply Logic Redundancy
A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS
Harvesting-Aware Power Management for Real-Time Systems With Renewable Energy
Variational Capacitance Extraction and Modeling Based on Orthogonal Polynomial Method
Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits
Efficient retiming of large circuits
FTC: A Universal Framework for Fault-Injection Attack Detection and Prevention
Improving Radiation Reliability of SRAM-Based Physical Unclonable Function With Self-Healing and Pre-Irradiation Masking Techniques
MAEPER: Matching Access and Error Patterns With Error-Free Resource for Low Vcc L1 Cache
Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition
Multistate Register Based on Resistive RAM
A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits
Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters
Stream Processing Architectures for Continuous ECG Monitoring Using Subsampling- Based Classifiers
SecNVM: Power Side-Channel Elimination Using On-Chip Capacitors for Highly Secure Emerging NVM
Optimal Accelerated Test Framework for Time-Dependent Dielectric Breakdown Lifetime Parameter Estimation
Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance
Editorial New Beginnings for IEEE TVLSI
First Silicon Functional Validation and Debug of Multicore Microprocessors
Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller
FPGA-Oriented Design and Efficient Implementation of a Geometrically Tunable Multiscroll Conservative Chaotic System Without Equilibrium Points
Code Decompression Unit Design for VLIW Embedded Processors
Soft-Core Embedded-FPGA Based on Multistage Switching Networks: A Quantitative Analysis
Resource-Efficient and High-Throughput VLSI Design of Global Optical Flow Method for Mobile Systems
Exploiting Early Tag Access for Reducing L1 Data Cache Energy in Embedded Processors
A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs
Analysis of Clock Scheduling in Frequency Domain for Digital Switching Noise Suppressions
A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design
Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies
A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline Transceivers
Guest Editorial Special Section on Security Challenges and Solutions With Emerging Computing Technologies
Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits
Reconfigurable SRAM Architecture With Spatial Voltage Scaling for Low Power Mobile Multimedia Applications
Energy Management on Battery-Powered Coarse-Grained Reconfigurable Platforms
WCET-Aware Energy-Efficient Data Allocation on Scratchpad Memory for Real-Time Embedded Systems
Test Sequences for Faults in the Scan Logic
Full Fault Resilience and Relaxed Synchronization Requirements at the Cache-Memory Interface
A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme
Multi-Mechanism Reliability Modeling and Management in Dynamic Systems
VLSI architectures for SISO-APP decoders
FIRE: a fault-independent combinational redundancy identification algorithm
Editorial on the Conclusion of the 2020 Editorial Year - The Climactic Finale of a Peculiar Year
Optimization of Overdrive Signoff in High-Performance and Low-Power ICs
Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates
Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms
Comments on "Improved Accuracy Pseudo-Exponential Function Generator With Applications in Analog Signal Processing"
A Memory-Based FFT Processor Design With Generalized Efficient Conflict-Free Address Schemes
Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment
An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications
Rate-0.96 LDPC Decoding VLSI for Soft-Decision Error Correction of NAND Flash Memory
ReHIT: Reconfigurable High-Radix Iterative-Taylor Architecture for Ultraprecise Logarithm/Exponential Functions in FPGA-Based Softmax Accelerators
A Two-Step Analog Accumulator for CMOS TDI Image Sensor With Temporal Undersampling Exposure Method
A High-Performance Unified-Field Reconfigurable Cryptographic Processor
DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect
Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs
Analysis and Design of Magnetically Tuned W -Band Oscillators
Simultaneous switching noise analysis using application specific device modeling
Efficient Broadband Current-Mode Adder- Quantizer Design for Continuous-Time Sigma-Delta Modulators
Special Section on International Symposium on Networks-on-Chip (NOCS)
Deep Neural Network Augmented Wireless Channel Estimation for Preamble-Based OFDM PHY on Zynq System on Chip
Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs
A Sub-1 V, 26 muW, Low-Output-Impedance CMOS Bandgap Reference With a Low Dropout or Source Follower Mode
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
Fast Search and Efficient Placement Algorithm for Reconfigurable Tasks on Modern Heterogeneous FPGAs
Transient IR-Drop Analysis for At-Speed Testing Using Representative Random Walk
Analysis and Reduction of Nonidealities in Stacked-Transistor Current Sources
Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving
Scheduling with bus access optimization for distributed embedded systems
Gate oxide leakage and delay tradeoffs for dual-T ox circuits
Low-Power Rotary Clock Array Design
Improving the Energy Efficiency of Pipelined Delay Lines Through Adaptive Granularity
VLSI Design of Saturation-Based Image Dehazing Algorithm
A multiparameter implantable microstimulator SOC
Short Pulse Generation With On-Chip Pulse-Forming Lines
SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multiprecision DNN Inference
A minimum total power methodology for projecting limits on CMOS GSI
An 11.2-Gb/s LVDS Receiver With a Wide Input Range Comparator
Spin-Transfer-Torque Magnetic-Tunnel-Junction-Based Low-Power Nonvolatile Flip-Flop Designs in the Subthreshold Voltage Region
Achieving Programming Model Abstractions for Reconfigurable Computing
A fuzzy model for path delay fault detection
Cactus: A Multicore Spiking Neural Network Accelerator With Fine-Grained Structured Weight Sparsity
Cost-Efficient Frequency-Domain MIMO-OFDM Modem With an SIMD ALU-Based Architecture
A Flying-Capacitor-Assisted Single-Mode Buck-Boost Converter for Battery-Powered Applications
Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures