yusuke1997/dblp-id-title huggingface dataset:
Network-on-Chip for Turbo Decoders
A High-Performance LDO Regulator Enabling Low-Power SoC With Voltage Scaling Approaches
Power efficient data path synthesis of sum-of-products computations
A synthesis-for-transparency approach for hierarchical and system-on-a-chip test
Analysis of Passive Charge Sharing-Based Segmented SAR ADCs
Analyzing the Efficiency of L1 Caches for Reliable Hybrid-Voltage Operation Using EDC Codes
A Hybrid Design Automation Tool for SAR ADCs in IoT
A Fault-Tolerant Interconnect Mechanism for NMR Nanoarchitectures
Efficient Parallel Testing and Implicit Cost-Driven Tuning of RF-MIMO Systems
ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators
Reliable CRC-Based Error Detection Constructions for Finite Field Multipliers With Applications in Cryptography
Energy and peak-current per-cycle estimation at RTL
A 0.25-3.25-GHz Wideband CMOS-RF Spectrum Sensor for Narrowband Energy Detection
An architecture for a DSP field-programmable gate array
A Framework for Power-Gating Functional Units in Embedded Microprocessors
A New ACD-OMP Accelerator With Clustered Computing Look-Ahead
Comma: A Communication-Minimized Model-Architecture Framework for Efficient Convolution Acceleration
Data Reuse Buffer Synthesis Using the Polyhedral Model
Design of a cycle-efficient 64-b/32-b integer divisor using a table-sharing algorithm
PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low-Power Microprocessors
A recursive MISD architecture for pattern matching
Design-for-testability and fault-tolerant techniques for FFT processors
Multilevel Fixed-Outline Component Placement and Graph-Based Ball Assignment for System in Package
A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits
Automated pin grid array package routing on multilayer ceramic substrates
Power-delay product minimization in high-performance 64-bit carry-select adders
A 1.15-mW Low-Power Low-Complexity Reconfigurable FM-UWB Transmitter
CMOS sensors for on-line thermal monitoring of VLSI circuits
X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing
A 5T0C eDRAM-Based Content Addressable Memory for High-Density Searching and Logic-in-Memory
On Fast and Exact Computation of Error Metrics in Approximate LSB Adders
A Design Methodology for Power Efficiency Optimization of High-Speed Equalized-Electrical I/O Architectures
A Flexible DA-Based Architecture for Computation of Inner Product of Variable Vectors
Adaptive Cooling of Integrated Circuits Using Digital Microfluidics
Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames
Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories
Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation
2.5-dimensional VLSI system integration
Quadrant-Based Online Spatial and Temporal Compressive Acquisition for CMOS Image Sensor
Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery
Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip
Design of DNN-Based Low-Power VLSI Architecture to Classify Atrial Fibrillation for Wearable Devices
Circuit-Level Timing Error Tolerance for Low-Power DSP Filters and Transforms
LoCCo-Based Scan Chain Stitching for Low-Power DFT
A Wideband Input Buffer Based on Cascade Complementary Source Follower
Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code
An Efficient Digital VLSI Implementation of Gaussian Mixture Models-Based Classifier
A Fully Integrated Discrete-Time Superheterodyne Receiver
Overloaded CDMA Crossbar for Network-On-Chip
Automatic synthesis of dynamically configured pipelines supporting variable data initiation intervals
A Concurrent Dual-Band and Dual-Mode Frequency Synthesizer for Radar Systems
Interleaving Test Algorithm for Subthreshold Leakage-Current Defects in DRAM Considering the Equal Bit Line Stress
ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design
NBTI and Leakage Reduction Using ILP-Based Approach
Ultra-High Throughput Low-Power Packet Classification
M×N Booth encoded multiplier generator using optimized Wallace trees
Improving path delay testability of sequential circuits
An Efficient Sparse CNN Inference Accelerator With Balanced Intra- and Inter-PE Workload
A 0.13-µm CMOS Dynamically Reconfigurable Charge Pump for Electrostatic MEMS Actuation
Dual-edge triggered storage elements and clocking strategy for low-power systems
An Energy-Efficient Reconfigurable Baseband Processor for Wireless Communications
A Variation-Aware Adaptive Fuzzy Control System for Thermal Management of Microprocessors
A System-On-Chip Bus Architecture for Thwarting Integrated Circuit Trojan Horses
A Robust Random Number Generator Based on a Differential Current-Mode Chaos
Litho-Friendly Decomposition Method for Self-Aligned Triple Patterning
Digital Watermarking for Detecting Malicious Intellectual Property Cores in NoC Architectures
A 15-Channel 30-V Neural Stimulator for Spinal Cord Repair
Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks
CS-CMOS: A Low-Noise Logic Family for Mixed Signal SoCs
A 1036-F 2 /Bit High Reliability Temperature Compensated Cross-Coupled Comparator-Based PUF
Self-timed divider based on RSD number system
A Closed-Form Expression for Minimum Operating Voltage of CMOS D Flip-Flop
Efficient semisystolic architectures for finite-field arithmetic
Optimization Techniques for the Synchronization of Concurrent Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips
Deep Reinforcement Learning-Based Power Management for Chiplet-Based Multicore Systems
Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations
Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes
A New Cellular-Based Redundant TSV Structure for Clustered Faults
Design Space Exploration for Chiplet-Assembly-Based Processors
Instruction code mapping for performance increase and energy reduction in embedded computer systems
Multilevel Power Optimization of Pipelined A/D Converters
A 2-MHz BW 82-dB DR Continuous-Time Delta-Sigma Modulator With a Capacitor-Based Voltage DAC for ELD Compensation
Opening of the 2023 Editorial Year - This Coda as Prelude of Next TVLSI Cycle With Sustained Growth
Fast Estimation of a Statistical Eye Diagram for Nonlinear High-Speed Links Based on the Minimum Required Order of the Multiple Edge Response Method
A novel design of a two operand normalization circuit
High Performance Phylogenetic Analysis With Maximum Parsimony on Reconfigurable Hardware
Novel techniques for bus power consumption reduction in realizations of sum-of-product computation
Dynamically De-Skewable Clock Distribution Methodology
An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks
Radiation-Hardened, Read-Disturbance-Free New-Quatro-10T Memory Cell for Aerospace Applications
A New ASIC Structure With Self-Repair Capability Using Field-Programmable Nanowire Interconnect Architecture
Evolutionary algorithms for the synthesis of embedded software
Robust Two-Phase RZ Asynchronous SoC Interconnects
Information-theoretic bounds on average signal transition activity [VLSI systems]
A Fully Digital ASK Demodulator With Digital Calibration for Bioimplantable Devices
Compressed On-Chip Framebuffer Cache for Low-Power Display Systems
Power Reduction of Asynchronous Logic Circuits Using Activity Detection
Nanoscale system dynamical behaviors: from quantum-dot-based cell to 1-D arrays
Low-power CMOS with subvolt supply voltages
Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design
Performance and Energy-Efficient Design of STT-RAM Last-Level Cache
A 215-F² Bistable Physically Unclonable Function With an ACF of <0.005 and a Native Bit Instability of 2.05% in 65-nm CMOS Process
Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure
RESAA: A Removal and Structural Analysis Attack Against Compound Logic Locking
POCA: First Power-on Chip Authentication and Key Exchange for Secure Provisioning in System-on-Chip
A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations
A Compact Low-Voltage True Random Number Generator Based on Inkjet Printing Technology
Optimal Positions of Twists in Global On-Chip Differential Interconnects
Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory
Low Overhead Software Wear Leveling for Hybrid PCM + DRAM Main Memory on Embedded Systems
SRAM Stability Analysis and Performance-Reliability Tradeoff for Different Cache Configurations
FastRead: Improving Read Performance for Multilevel-Cell Flash Memory
Designing fast on-chip interconnects for deep submicrometer technologies
A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array
Designing Energy-Efficient Intermittently Powered Systems Using Spin-Hall-Effect-Based Nonvolatile SRAM
A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling
Hardware Accelerator for Probabilistic Inference in 65-nm CMOS
A 24-GHz DCO With High-Amplitude Stabilization and Enhanced Startup Time for Automotive Radar
Time multiplexed color image processing based on a CNN with cell-state outputs
WiT: Optimal Wiring Topology for Electromigration Avoidance
A 4.2-to-0.5-V, 0.8-μA-0.8-mA, Power-Efficient Three-Level SIMO Buck Converter for a Quad-Voltage RISC-V Microprocessor
A Neural Rendering Coprocessor With Optimized Ray Representation and Marching
A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment
Implicit deductive fault simulation for complex delay fault models
A Generalized Power Supply Induced Jitter Model Based on Power Supply Rejection Ratio Response
Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking
High-Speed Low-Power Viterbi Decoder Design for TCM Decoders
3DNN-Xplorer: A Machine Learning Framework for Design Space Exploration of Heterogeneous 3-D DNN Accelerators
Secure Systolic Montgomery Modular Multiplier Over Prime Fields Resilient to Fault-Injection Attacks
An ECC-Assisted Postpackage Repair Methodology in Main Memory Systems
TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier
A Low-Power and Highly Linear 14-bit Parallel Sampling TDC With Power Gating and DEM in 65-nm CMOS
Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture
Design Techniques to Facilitate Processor Power Delivery in 3-D Processor-DRAM Integrated Systems
Arbitrated Time-to-First Spike CMOS Image Sensor With On-Chip Histogram Equalization
Virtual_N2_PDK: A Predictive Process Design Kit for 2-nm Nanosheet FET Technology
Error-Resilient Integrated Clock Gate for Clock-Tree Power Optimization on a Wide Voltage IOT Processor
An Efficient NVM-Based Architecture for Intermittent Computing Under Energy Constraints
Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements
Integrated Solar Energy Harvesting and Storage
Multi-Objective Module Placement For 3-D System-On-Package
A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors
Test Pattern Modification for Average IR-Drop Reduction
Silicon-Validated Power Delivery Modeling and Analysis on a 32-nm DDR I/O Interface
On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions
Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture
CusNoC: Fast Full-Chip Custom NoC Generation
Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge
Clamping Virtual Supply Voltage of Power-Gated Circuits for Active Leakage Reduction and Gate-Oxide Reliability
Energy efficient watermarking on mobile devices using proxy-based partitioning
Glitch power minimization by selective gate freezing
A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication
Design and Analysis of an Ultralow-Voltage Complementary Fold-Interleaved Multiple-Tail Current Mode Logic
Powerline Communication for Enhanced Connectivity in Neuromorphic Systems
A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation
Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching
Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications
Multi-Threshold Voltage FinFET Sequential Circuits
692-nW Advanced Encryption Standard (AES) on a 0.13-mum CMOS
A Novel Test Flow for One-Time-Programming Applications of NROM Technology
Analyzing Potential Throughput Improvement of Power- and Thermal-Constrained Multicore Processors by Exploiting DVFS and PCPG
Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes
Input-Latency Free Versatile Bit-Serial GF(2 m ) Polynomial Basis Multiplication
Test Compaction by Sharing of Transparent-Scan Sequences Among Logic Blocks
Dynamic Voltage and Frequency Scheduling for Embedded Processors Considering Power/Performance Tradeoffs
A novel and efficient routing architecture for multi-FPGA systems
Noise-aware interconnect power optimization in domino logic synthesis
Thermal-Constrained Task Allocation for Interconnect Energy Reduction in 3-D Homogeneous MPSoCs
Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications
Optimizing FPGA Logic Block Architectures for Arithmetic
PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability
A General and Automatic Cell Layout Generation Framework With Implicit Learning on Design Rules
Flexible Hardware Architecture of Hierarchical K-Means Clustering for Large Cluster Number
Multicore Signal Processing Platform With Heterogeneous Configurable Hardware Accelerators
Accurate Estimation of SRAM Dynamic Stability
Scalable Multi-Input-Multi-Output Queues With Application to Variation-Tolerant Architectures
An Efficient O(N) Comparison-Free Sorting Algorithm
A Sub-kT/q Voltage Reference Operating at 150 mV
TABS: Temperature-Aware Layout-Driven Behavioral Synthesis
Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension
ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware
1.2-mW Online Learning Mixed-Mode Intelligent Inference Engine for Low-Power Real-Time Object Recognition Processor
Design Space Exploration of Distributed On-Chip Voltage Regulation Under Stability Constraint
High Resolution Application Specific Fault Diagnosis of FPGAs
A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes
Constant Delay Logic Style
On gate level power optimization using dual-supply voltages
Sparse Regression Driven Mixture Importance Sampling for Memory Design
A 4.4-mA ESD-Safe 900-MHz LNA With 0.9-dB Noise Figure
Gate Leakage Impact on Full Open Defects in Interconnect Lines
Systematic IEEE rounding method for high-speed floating-point multipliers
A Fast and Retargetable Framework for Logic-IP-Internal Electromigration Assessment Comprehending Advanced Waveform Effects
A computationally efficient engine for flexible intrusion detection
System design for pixel-parallel image processing
Editorial Announcing a New Editor-in-Chief
Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks
Buffer block planning for interconnect planning and prediction
Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures
Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis
A DLL Design for Testing I/O Setup and Hold Times
Scheduling and Resource Binding Algorithm Considering Timing Variation
Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base
A behavioral synthesis system for asynchronous circuits
Unveiling the True Power of the Latched Ring Oscillator for a Unified PUF and TRNG Architecture
A 0.0043-mm 2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network
Memristive Computational Memory Using Memristor Overwrite Logic (MOL)
A Dead-Beat-Controlled Fast-Transient-Response Buck Converter With Active Pseudo-Current-Sensing Techniques
A Balunless Frequency Multiplier With Differential Output by Current Flow Manipulation
Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation
Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OFDM Systems
A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications
A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist
Built-In Self-Test and Digital Calibration of Zero-IF RF Transceivers
Power-Aware High-Level Synthesis With Clock Skew Management
All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters
An Ultralow Power Multirate FSK Demodulator With Digital-Assisted Calibrated Delay-Line Based Phase Shifter for High-Speed Biomedical Zero-IF Receivers
Source Coding and Preemphasis for Double-Edged Pulsewidth Modulation Serial Communication
Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time
An Efficient Hardware Implementation of Multialphabet Adaptive Arithmetic Encoder Based on Generalized Virtual Sliding Window
Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis
Architectural optimization for low-power nonpipelined asynchronous systems
Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs
Two-Phase Read Strategy for Low Energy Variation-Tolerant STT-RAM
Z-TCAM: An SRAM-based Architecture for TCAM
Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents
Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level Parallelism
Reliability and Availability in Reconfigurable Computing: A Basis for a Common Solution
Randomized Multitopology Logic Against Differential Power Analysis
Accurate Loop Self Inductance Bound for Efficient Inductance Screening
Architecture for Real-Time Nonparametric Probability Density Function Estimation
Configurable Independent Component Analysis Preprocessing Accelerator
Redundant Via Insertion Based on SCA
Power management in high-level synthesis
Correction to "ATPG for combinational circuits on configurable hardware"
Design and Implementation of a Real-Time Imaging Processor for Spaceborne Synthetic Aperture Radar With Configurability
Design and Implementation of a Field Programmable CRC Circuit Architecture
A High-Density Energy-Efficient CNM Macro Using Hybrid RRAM and SRAM for Memory-Bound Applications
Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 Cache
Variation Resilient Power Sensor With an 80-ns Response Time for Fine-Grained Power Management
An Energy Efficient Layered Decoding Architecture for LDPC Decoder
Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs
Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed
Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices
Design and Analysis of the Leapfrog Control-Bounded A/D Converter
Phase Noise Analysis of Bipolar Class-C VCOs With Delay in Oscillator Loop
Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits
Introduction to the Special Section on Nanocircuits and Systems
Joint Work and Voltage/Frequency Scaling for Quality-Optimized Dynamic Thermal Management
Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes
An efficient logic emulation system
DTMOS Technique for Low-Voltage Analog Circuits
A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator
Power Management of Voltage/Frequency Island-Based Systems Using Hardware-Based Methods
ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints
A Multi-Gb/s Frame-Interleaved LDPC Decoder With Path-Unrolled Message Passing in 28-nm CMOS
Secure Edge-Coded Signaling IoT Transceiver With Reduced Encryption Overhead
RATS: Restoration-Aware Trace Signal Selection for Post-Silicon Validation
Signal processing at 250 MHz using high-performance FPGA's
Passive and Active Reduction Techniques for On-Chip High-Frequency Digital Power Supply Noise
Design of n-Tier Multilevel Interconnect Architectures by Using Carbon Nanotube Interconnects
Power-Aware Neuromorphic Architecture With Partial Voltage Scaling 3-D Stacking Synaptic Memory
Power estimation techniques for FPGAs
Register File Partitioning and Compiler Support for Reducing Embedded Processor Power Consumption
A 57.2 nW, 1.3-5 V V IN , -85 dB PSRR, 50 μs Start-Up Time, Bandgap Reference Circuit
Full-Chip Thermal Analysis for the Early Design Stage via Generalized Integral Transforms
AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture
Functional vector generation for sequential HDL models under an observability-based code coverage metric
Input space adaptive design: a high-level methodology for optimizing energy and performance
Design-for-Debug Architecture for Distributed Embedded Logic Analysis
On-chip decoupling capacitor optimization using architectural level prediction
A Combined Optimization-Theoretic and Side- Channel Approach for Attacking Strong Physical Unclonable Functions
A Test Selection Procedure for Improving the Accuracy of Defect Diagnosis
Pel reconstruction on FPGA-augmented TriMedia
A Ku-Band Eight-Element Phased-Array Transmitter With Built-in Self-Test Capability in 180-nm CMOS Technology
Low power design using double edge triggered flip-flops
CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache
Analysis and Design of a DC-12-GHz Distribution Power Amplifier for Quantum Key Distribution Application
Partial Access Mode: New Method for Reducing Power Consumption of Dynamic Random Access Memory
A Real-Time 1280 × 720 Object Detection Chip With 585 MB/s Memory Traffic
Analytical test buffer design for differential signaling I/O buffers by error syndrome analysis
Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis
Overview of complementary GaAs technology for high-speed VLSI circuits
ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling
Efficiency Optimization of a Step-Down Switched Capacitor Converter for Subthreshold
A 4×5-Gb/s 1.12-µs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels
Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures
Probabilistic delay budget assignment for synthesis of soft real-time applications
Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices
Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces
Fast and Disturb-Free Nonvolatile Flip-Flop Using Complementary Polarizer MTJ
Design of a Tri-Modal Multi-Threshold CMOS Switch With Application to Data Retentive Power Gating
Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization
Simultaneous switching noise in on-chip CMOS power distribution networks
An Inductive 2-D Position Detection IC With 99.8% Accuracy for Automotive EMR Gear Control System
Low Propagation Delay Load-Balanced 4 × 4 Switch Fabric IC in 0.13-µm CMOS Technology
TUTPFL: Triple Node Upset-Tolerant and Single-Event Transient-Filtered Low-Power Latch With HSPICE and FPGA-Based Verifications