yusuke1997/dblp-id-title huggingface dataset:
A 28 nm 0.6 V Low Power DSP for Mobile Applications
A 10/30 MHz Fast Reference-Tracking Buck Converter With DDA-Based Type-III Compensator
A three-data differential signaling over four conductors with pre-emphasis and equalization: a CMOS current mode implementation
1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications
A Multimode Multi-Efficiency-Peak Digital Power Amplifier
A 3-V 0.5-μm CMOS A/D audio processor for a microphone array
Development and Evaluation of a Highly Linear CMOS Image Sensor With a Digitally Assisted Linearity Calibration
Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor
Static CMOS Physically Unclonable Function Based on 4T Voltage Divider With 0.6%-1.5% Bit Instability at 0.4-1.8 V Operation in 180 nm
An analog record, playback, and processing system on a chip for mobile communications devices
A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC
Integrated Fluxgate Magnetometer for Use in Isolated Current Sensing
DSC-TRCP: Dynamically Self-Calibrating Tunable Replica Critical Paths Based Timing Monitoring for Variation Resilient Circuits
Guest Editorial Special Section on the 45th IEEE European Solid-State Circuits Conference (ESSCIRC)
Transimpedance Amplifier for High Sensitivity Current Measurements on Nanodevices
Balanced Colpitt oscillator MMICs designed for ultra-low phase noise
A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation
Low-Power Quadrature Receivers for ZigBee (IEEE 802.15.4) Applications
An 11-bit high-resolution and adjustable-range CMOS time-to-digital converter for space science instruments
A 2.4-GHz MEMS-Based PLL-Free Multi-Channel Receiver With Channel Filtering at RF
A 10-Gb/s OEIC with Meshed Spatially-Modulated Photo Detector in 0.18-μm CMOS Technology
A Low-Power Floating-Gate-MOS-Based CDMA Matched Filter Featuring Coupling Capacitor Disconnection
A Digital-Intensive 1TX/2RX IEEE 802.15.4/4z-Compliant Joint-Radar-Communication-Location Transceiver SoC
A 16-ns 1-Mb CMOS EPROM
A 14-bit high-temperature ΣΔ modulator in standard CMOS
A High-Accuracy and Ultra-Energy-Efficient Cardiac Arrhythmia Classification Processor for Wearable Intelligent ECG Monitoring
A 7F 2 cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4-Gb DRAMs
A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration
A CMOS 13-b cyclic RSD A/D converter
Low power GaAs current-mode 1.2 Gb/s interchip interconnections
A 2.46-mm 2 Miniaturized Brain-Machine Interface (MiBMI) Enabling 31-Class Brain-to-Text Decoding
CMOS active pixel image sensors for highly integrated imaging systems
Novel W-band monolithic push-pull power amplifiers
Simulation and analysis of transient faults in digital circuits
A Compact Broadband Mixed-Signal Power Amplifier in Bulk CMOS With Hybrid Class-G and Dynamic Load Trajectory Manipulation
A CMOS self-calibrating frequency synthesizer
A monolithic gallium arsenide interval timer IC with integrated PLL clock synthesis having 500-ps single shot resolution
VLSI chip set for 2D HDTV subband filtering with on-chip line memories
XiSystem: a XiRisc-based SoC with reconfigurable IO module
A 1920(H)*1035(V) pixel high-definition CCD image sensor
Design of a low-power 32 K CMOS programmable delay-line memory
Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS
A 211-to-263-GHz Dual-LC-Tank-Based Broadband Power Amplifier With 14.7-dBm P SAT and 16.4-dB Peak Gain in 130-nm SiGe BiCMOS
Introduction to the 33rd Annual IEEE Compound Semiconductor Integrated Circuit Symposium
A Proactive System for Voltage-Droop Mitigation in a 7-nm Hexagon™ Processor
A digitally controlled PLL for SoC applications
A multibit ΣΔ modulator in floating-body SOS/SOI CMOS for extreme radiation environments
A monolithic Ka-band 0.25 mu m GaAs MESFET transmitter for high volume production
Forming damped LRC parasitic circuits in simultaneously switched CMOS output buffers
A 1.25-V micropower Gm-C filter based on FGMOS transistors operating in weak inversion
An FDD Wireless Diversity Receiver With Transmitter Leakage Cancellation in Transmit and Receive Bands
Low Distortion 50 GSamples/s Track-Hold and Sample-Hold Amplifiers
Offset word-line architecture for scaling DRAMs to the gigabit level
IBM Telum II Microprocessor: 5.5 GHz With On-Die AI and Data Processing, and Design-Technology Co-Optimizations for Power, Area, and Reliability
Operational transconductance amplifier-based nonlinear function syntheses
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator
A 5.28-Gb/s LDPC Decoder With Time-Domain Signal Processing for IEEE 802.15.3c Applications
A high-voltage output driver in a 2.5-V 0.25-μm CMOS technology
Si bipolar chip set for 10-Gb/s optical receiver
An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators
A 32 K ASIC synchronous RAM using a two-transistor basic cell
Sub-Microwatt Analog VLSI Trainable Pattern Classifier
An ATM routing and concentration chip for a scalable multicast ATM switch
Bandwidth Extension Techniques for CMOS Amplifiers
A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling
A 126.6-mm 2 AND-type 512-Mb flash memory with 1.8-V power supply
A low-power digital matched filter for direct-sequence spread-spectrum signal acquisition
DC-to-20-GHz MMIC multibit digital attenuators with on-chip TTL control
A Fully Bit-Flexible Computation in Memory Macro Using Multi-Functional Computing Bit Cell and Embedded Input Sparsity Sensing
A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling
Low-noise, high-speed data transmission using a ringing-canceling output buffer
Superconducting bandpass ΔΣ modulator with 2.23-GHz center frequency and 42.6-GHz sampling rate
Design of a 60-V 10-A intelligent power switch using standard cells
An Energy-Efficient Processor for Real-Time Semantic LiDAR SLAM in Mobile Robots
A Charging Acceleration Technique for Highly Efficient Cascode Class-E CMOS Power Amplifiers
A Low-Loss Passive D-Band Phase Shifter for Calibration-Free, Precise Phase Control
A transmitter IC for TETRA systems based on a Cartesian feedback loop linearization technique
A 6.25 Gb/s Voltage-Time Conversion Based Fractionally Spaced Linear Receive Equalizer for Mesochronous High-Speed Links
A Fast-Response Hybrid SIMO Power Converter with Adaptive Current Compensation and Minimized Cross-Regulation
A Channel-Select Filter With Agile Blocker Detection and Adaptive Power Dissipation
An Octave-Range, Watt-Level, Fully-Integrated CMOS Switching Power Mixer Array for Linearization and Back-Off-Efficiency Improvement
A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX
A 0.032-mm 2 43.3-fJ/Step 100-200-MHz IF 2-MHz Bandwidth Bandpass DSM Based on Passive N-Path Filters
A 17.8-MS/s Compressed Sensing Radar Accelerator Using a Spiking Neural Network
A 100 MHz A/D interface for PRML magnetic disk read channels
A 4-GS/s 4-bit Flash ADC in 0.18-µm CMOS
A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps
A 4-GHz 8-b ADC system
Introduction to the Special Issue on the 39th European Solid-State Circuits Conference (ESSCIRC)
A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs
Calibration techniques of active BiCMOS mixers
A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET
A CMOS 1.0-μm two-dimensional analog multirate system for real-time image processing
A Chip-PCB Hybrid SC PUF Used for Anti-Desoldering and Depackaging-Attack Protection
Energy-Efficient GHz-Class Charge-Recovery Logic
Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs
A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer
A Highly Efficient Reconfigurable Charge Pump Energy Harvester With Wide Harvesting Range and Two-Dimensional MPPT for Internet of Things
An Area-Efficient Low-Jitter Fractional Output Divider With Replica-DTC-Free Background Calibration
A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM
A 46 µW 13 b 6.4 MS/s SAR ADC With Background Mismatch and Offset Calibration
A W-Band Single-Antenna FMCW Radar Transceiver With Adaptive Leakage Cancellation
A 52 GHz Phased-Array Receiver Front-End in 90 nm Digital CMOS
A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file
Low-Noise Active Cancellation of Transmitter Leakage and Transmitter Noise in Broadband Wireless Receivers for FDD/Co-Existence
A 4.9 mΩ-Sensitivity Mobile Electrical Impedance Tomography IC for Early Breast-Cancer Detection System
A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC for digital wireless communication
A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network
A Low-Noise Wide-BW 3.6-GHz Digital ΔΣ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation
A 1024 × 8, 700-ps Time-Gated SPAD Line Sensor for Planetary Surface Exploration With Laser Raman Spectroscopy and LIBS
A 2.8-3.2-GHz Fractional- N Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO
Fast Charging and High Efficiency Switching-Based Charger With Continuous Built-In Resistance Detection and Automatic Energy Deliver Control for Portable Electronics
Globally updated mesochronous design style
A 2.4-GHz ISM-Band Sliding-IF Receiver With a 0.5-V Supply
A 141-µW High-Voltage MEMS Gyroscope Drive Interface Circuit Based on Flying Capacitors
Microwave CMOS-device physics and design
A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation
Load-Independent Control of Switching DC-DC Converters With Freewheeling Current Feedback
High-speed low-power Darlington ECL circuit
A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control
A capacitive fingerprint sensor chip using low-temperature poly-Si TFTs on a glass substrate and a novel and unique sensing method
An 8-b 100-MSample/s CMOS pipelined folding ADC
A Fractional-N Cascaded PLL With MMD-Based Quantization-Error Cancellation
100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology
Dual-Terahertz-Comb Spectrometer on CMOS for Rapid, Wide-Range Gas Detection With Absolute Specificity
A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 µm CMOS
A 7-20 GHz Ultra-High-Linearity Passive Mixer in 45 nm CMOS SOI
Multi-Feed Antenna and Electronics Co-Design: An E-Band Antenna-LNA Front End With On-Antenna Noise-Canceling and Gₘ-Boosting
Methods for true energy-performance optimization
A switched-capacitor realization of multiple FIR filters on a single chip
A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS
Insights Into Phase-Noise Scaling in Switch-Coupled Multi-Core LC VCOs for E-Band Adaptive Modulation Links
A picosecond-accuracy, 700-MHz range, Si bipolar time interval counter LSI
A digitally temperature-compensated crystal oscillator
A Self-Calibrated Hybrid Thermal-Diffusivity/Resistor-Based Temperature Sensor
A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC
A 0.029-mm 2 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer
A 5-GHz Wireless LAN Transmitter with Integrated Tunable High-Q RF Filter
Design of a 55-nm SiGe BiCMOS 5-bit Time-Interleaved Flash ADC for 64-Gbd 16-QAM Fiberoptics Applications
A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS
A 6.78-MHz Single-Stage Wireless Charger With Constant-Current Constant-Voltage Charging Technique
A 14-to-32-Gb/s Deadzone-Free Referenceless CDR With Autocovariance-Based Seamless Frequency Detector in 40-nm CMOS Technology
A 16-MHz Crystal Oscillator With 17.5- μ s Start-Up Time Under 10 4 -ppm- Δ F Injection Using Automatic Phase-Error Correction
A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver
A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique
A 33 µW 64×64 Pixel Vision Sensor Embedding Robust Dynamic Background Subtraction for Event Detection and Scene Interpretation
A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique
The latch bus driver system
A 30-MHz trellis codec chip for partial-response channels
A Scalable N-Step Equally Split SSHI Rectifier for Piezoelectric Energy Harvesting With Low-Q Inductor
A 0.18-µm CMOS Image Sensor With Phase-Delay-Counting and Oversampling Dual-Slope Integrating Column ADCs Achieving 1e - rms Noise at 3.8-µs Conversion Time
A 5-V-only 16-Mb flash memory with sector erase mode
Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories
A Wide Dynamic Range Buck Converter With Sub-nW Quiescent Power
A multigigabit backplane transceiver core in 0.13-μm CMOS with a power-efficient equalization architecture
A 4-bit RFDAC-Based FMCW Modulator for Automotive Radar
A low noise readout detector circuit for nanoampere sensor applications
A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS
A Battery-Powered Activity-Dependent Intracortical Microstimulation IC for Brain-Machine-Brain Interface
A Two-Step ADC With a Continuous-Time SAR-Based First Stage
A fully compensated active pull-down ECL circuit with self-adjusting driving capability
A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction-multiple-data (SIMD) feature
A 256 Pixel Magnetoresistive Biosensor Microarray in 0.18 µm CMOS
A 390-mm 2 , 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture
An Activity-Triggered 95.3 dB DR -75.6 dB THD CMOS Imaging Sensor With Digital Calibration
A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors
A high-speed low-power rail-to-rail column driver for AMLCD application
A Low Power V-Band CMOS Frequency Divider With Wide Locking Range and Accurate Quadrature Output Phases
Dynamic Vpass Controlled Program Scheme and Optimized Erase Vth Control for High Program Inhibition in MLC NAND Flash Memories
A fully integrated 43.2-Gb/s clock and data recovery and 1: 4 demux IC in InP HBT technology
A Pulse-Based Ultra-Wideband Transmitter in 90-nm CMOS for WPANs
Characterization, design, modeling, and model validation of silicon-wafer M: N balun components under matched and unmatched conditions
The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier
An 8-b 800-MHz DAC
A 5-V p-p 100-ps GaAs pulse amplifier IC with improved pulse fidelity
A 30-frames/s megapixel real-time CMOS image processor
A 2.2 mA 4.3 mm 2 ASIC for a 1000°/s 2-Axis Capacitive Micro-Gyroscope
A Fully-Integrated High-Power Linear CMOS Power Amplifier With a Parallel-Series Combining Transformer
A self-tuning digital telemetry IC for use in a microprocessor-based implantable instrument
A 0.18-μm CMOS bioluminescence detection lab-on-chip
A Biomimetic, 4.5µW, 120+ dB, Log-Domain Cochlea Channel With AGC
Hierarchical symbolic design methodology for large-scale data paths
A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging
Simultaneous Reverse Body and Negative Word-Line Biasing Control Scheme for Leakage Reduction of DRAM
A 0.24-nJ/bit Super-Regenerative Pulsed UWB Receiver in 0.18- μ m CMOS
A 3.68 aF rms Resolution Continuous-Time Bandpass Δ Σ Capacitance-to-Digital Converter for Full-CMOS Sensors in 0.18 μm CMOS
Tunable BiCMOS continuous-time filter for high-frequency applications
A Continuous-Time Ripple Reduction Technique for Spinning-Current Hall Sensors
A 10-Gb/s 180-GHz Phase-Locked-Loop Minimum Shift Keying Receiver
A 5-6 GHz 1-V CMOS Direct-Conversion Receiver With an Integrated Quadrature Coupler
A Self-Powered System for Large-Scale Strain Sensing by Combining CMOS ICs With Large-Area Electronics
PVT-aware leakage reduction for on-die caches with improved read stability
A Monolithic GaN Power IC With On-Chip Gate Driving, Level Shifting, and Temperature Sensing, Achieving Direct 48-V/1-V DC-DC Conversion
10 Gb/s silicon bipolar 8:1 multiplexer and 1:8 demultiplexer
A NEMS-Array Control IC for Subattogram Mass Sensing Applications in 28 nm CMOS Technology
A multi-purpose CMOS sensor interface for low-power applications
A 34-ns 16-Mb DRAM with controllable voltage down-converter
Positive-Feedback Level Shifter Logic for Large-Area Electronics
Omnidirectional Wireless Power Transfer for Millimetric Magnetoelectric Biomedical Implants
EQZ-LDO: A Secure Digital Low Dropout Regulator Armed With Detection-Driven Protection Against Correlation Power Analysis
A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme
Compensator-Free Mixed-Ripple Adaptive On-Time Controlled Boost Converter
Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI
RF-to-Millimeter-Wave Receivers Employing Frequency-Translated Feedback
Analysis of oscillatory metastable operation of an RS flip-flop
A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization
A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS
A content addressable memory management unit with on-chip data cache
12.5 Gb/s Optical Driver and Receiver ICs With Double-Threshold AGC for SATA Out-of-Band Transmission
A Neural Stimulator Frontend With High-Voltage Compliance and Programmable Pulse Shape for Epiretinal Implants
Enhanced Interference Rejection Bluetooth Low-Energy Back-Channel Receiver With LO Frequency Hopping
New monolithic switched-capacitor differentiators with good noise rejection
A low-power stereo 16-bit CMOS D/A converter for digital audio
Design Techniques for Wideband Single-Bit Continuous-Time Delta Sigma Modulators With FIR Feedback DACs
DC-coupled IF stage design for a 900-MHz ISM receiver
A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-μm CMOS
A Spur-Frequency-Boosting PLL With a -74 dBc Reference-Spur Suppression in 90 nm Digital CMOS
An eighth-order CMOS low-pass filter with 30-120 MHz tuning range and programmable boost
A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification
Multiple-level partitioning: an application to the very large-scale hardware simulator
The fundamental limit on binary switching energy for terascale integration (TSI)
Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory
A fully integrated 24-GHz eight-element phased-array receiver in silicon
A Low-Power DCVSL-Like GIDL-Free Voltage Driver for Low-Cost RFID Nonvolatile Memory
A 15-22 Gbps Serial Link in 28 nm CMOS With Direct DFE
Sub-0.2 dB Noise Figure Wideband Room-Temperature CMOS LNA With Non-50 Ω Signal-Source Impedance
Compact low-voltage power-efficient operational amplifier cells for VLSI
STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse
An On-Chip Test Structure and Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process
A four-channel ADSL2+ analog front-end for CO applications with 75 mW per channel, built in 0.13-μm CMOS
NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors
A 130.3 mW 16-Core Mobile GPU With Power-Aware Pixel Approximation Techniques
A PRML read/write channel IC using analog signal processing for 200 Mb/s HDD
A 400-MHz, 12-bit, 18-mW, IF digitizer with mixer inside a sigma-delta modulator loop
A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process
Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability
An analog PLL-based clock and data recovery circuit with high input jitter tolerance
A 65 nm CMOS Multistandard, Multiband TV Tuner for Mobile and Multimedia Applications
Compact Cascadable g m -C All-Pass True Time Delay Cell With Reduced Delay Variation Over Frequency
A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS
A g m /I D based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA
A dynamic line-termination circuit for multireceiver nets
SNPU: An Energy-Efficient Spike Domain Deep-Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit
A Through-Power-Link Hysteretic-Controlled Capacitive Isolated DC-DC Converter With Enhanced Efficiency and Common-Mode Transient Immunity
A Time-Modulated Concurrent Steerable Multibeam MIMO Receiver Array With Spectral-Spatial Mapping Using One Beamformer and Single-Wire Interface
QSERL: quasi-static energy recovery logic
A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration
A low-voltage, low-power CMOS delay element
Low-power 200-Msps, area-efficient, five-tap programmable FIR filter [in BiCMOS]
A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques
A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and pp Supply Ripple
A cost-efficient high-speed 12-bit pipeline ADC in 0.18-μm digital CMOS
A BiCMOS PLL-based data separator circuit with high stability and accuracy
A Four-Channel Beamforming Down-Converter in 90-nm CMOS Utilizing Phase-Oversampling
High-resolution low-power CMOS D/A converter
A deterministic algorithm for automatic CMOS transistor sizing
Design of C-testable DCVS binary array dividers
A $+$31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications
A 0.4-V 0.0294-mm 2 Resistor-Based Temperature Sensor Achieving ±0.24 °C p2p Inaccuracy From40 °C to 125 °C and 385 fJ · K 2 Resolution FoM in 65-nm CMOS
Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node
An Energy-Efficient Neural Network Accelerator With Improved Resilience Against Fault Attacks
An E-Band FMCW Radar Receiver With Arbitrary-Path Spillover Cancellation
A 1-V 17-GHz 5-mW CMOS Quadrature VCO Based on Transformer Coupling
A memory-controlled crosspoint switch using E-beam restructuring
A Flexible, Ultra-Low-Energy 35 pJ/Pulse Digital Back-End for a QAC IR-UWB Receiver
A 10-Gb/s (1.25 Gb/s×8)4×2 0.25-μm CMOS/SIMOX ATM switch based on scalable distributed arbitration
A universal 0.03-mm 2 one-pin crystal oscillator in CMOS
An 85 mW, 10 b, 40 Msample/s CMOS parallel-pipelined ADC
A versatile micropower high-voltage flat-panel display driver in a 100-V 0.7-μm CMOS intelligent interface technology
A 3-V 5.4-mW BiCMOS track & hold circuit with sampling frequency up to 150 MHz
A 12-b, 60-MSample/s cascaded folding and interpolating ADC
A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology
A CMOS-integrated microinstrument for trace detection of heavy metals
A Wireless Stress Mapping System for Orthodontic Brackets Using CMOS Integrated Sensors
Liquid-Metal Vertical Interconnects for Flip Chip Assembly of GaAs C-Band Power Amplifiers Onto Micro-Rectangular Coaxial Transmission Lines
A Multiphase Class-D Automotive Audio Amplifier With Integrated Low-Latency ADCs for Digitized Feedback After the Output Filter
A 5 Gbps 0.13 μ m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links