yusuke1997/dblp-id-title huggingface dataset:
A Piecewise-Linear Moment-Matching Approach to Parameterized Model-Order Reduction for Highly Nonlinear Systems
Design of Application-Specific Architectures for Networked Labs-on-Chips
Stochastic Circuit Synthesis by Cube Assignment
A New Verilog-A SPAD Circuit Model Integrating Crosstalk for Large-Scale Array
Defect Clustering-Aware Spare-TSV Allocation in 3-D ICs for Yield Enhancement
Automated Design and Optimization of Low-Noise Oscillators
Steady-state and transient analysis of submicron devices using energy balance and simplified hydrodynamic models
FedStar: Efficient Federated Learning on Heterogeneous Communication Networks
CHEF: A Framework for Deploying Heterogeneous Models on Clusters With Heterogeneous FPGAs
Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization
Secured Flipped Scan-Chain Model for Crypto-Architecture
Isometric Test Data Compression
Analog functional simulator for multilevel systems
Modeling digital substrate noise injection in mixed-signal IC's
Thermal Balancing Policy for Multiprocessor Stream Computing Platforms
Accurate and Analytical Statistical Spatial Correlation Modeling Based on Singular Value Decomposition for VLSI DFM Applications
MCM-GPU Voltage Noise Characterization and Architecture-Level Mitigation
AccuReD: High Accuracy Training of CNNs on ReRAM/GPU Heterogeneous 3-D Architecture
SMART-II: a three-dimensional CAD model for submicrometer MOSFET's
Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures
Microarchitectural synthesis for rapid BIST testing
Profit: Priority and Power/Performance Optimization for Many-Core Systems
System-Level Simulation of Flow-Induced Dispersion in Lab-on-a-Chip Systems
Power distribution analysis of VLSI interconnects using model orderreduction
Topological channel routing [VLSI]
Analytical model for crosstalk and intersymbol interference in point-to-point buses
A Formal Method for the Specification, Analysis, and Design of Register-Transfer Level Digital Logic
Integrated circuit substrate coupling models based on Voronoi tessellation
Ultrahigh Density Logic Designs Using Monolithic 3-D Integration
Synthesis and Optimization of Pipelined Packet Processors
Force-directed scheduling for the behavioral synthesis of ASICs
Chaotic Weights: A Novel Approach to Protect Intellectual Property of Deep Neural Networks
Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings
Resource- and Workload-Aware Model Parallelism-Inspired Novel Malware Detection for IoT Devices
Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths
An integrated CAD system for algorithm-specific IC design
A new discretization strategy of the semiconductor equations comprising momentum and energy balance
Automatic Application-Specific Calibration to Enable Dynamic Voltage Scaling in FPGAs
Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks
Diagnosis of CMOS op-amps with gate oxide short faults using multilayer perceptrons
Utilizing ATE Vector Repeat With Linear Decompressor for Test Vector Compression
Integrated optimization capabilities in the VISTA technology CAD framework
General Purpose Deep Learning Accelerator Based on Bit Interleaving
SPIDER -- A CAD System for Modeling VLSI Metallization Patterns
Latency-Guided On-Chip Bus-Network Design
LiTformer: Efficient Signal Integrity Analysis for High-Speed Link Transmitters Using Non-Autoregressive Transformer
Segmented channel routing
Modular Design and Optimization of Biomedical Applications for Ultralow Power Heterogeneous Platforms
MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks
Test-Suite-Based Analog/RF Test Time Reduction Using Canonical Correlation
PoBO: A Polynomial Bounding Method for Chance-Constrained Yield-Aware Optimization of Photonic ICs
An exact zero-skew clock routing algorithm
Detection of catastrophic faults in analog integrated circuits
Partition-Based Algorithm for Power Grid Design Using Locality
Old School, New Primitive: Toward Scalable PUF-Based Authenticated Encryption Scheme in IoT
TinyML Design Contest for Life-Threatening Ventricular Arrhythmia Detection
SparseACC: A Generalized Linear Model Accelerator for Sparse Datasets
Standard Description Form for Device Characteristics in VLSI's
An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping
Efficient Complete Verification of Neural Networks via Layerwised Splitting and Refinement
Multiple fault testing using minimal single fault test set for fanout-free circuits
Diversified Butterfly Attractors of Memristive HNN With Two Memristive Systems and Application in IoMT for Privacy Protection
Threshold network synthesis and optimization and its application to nanotechnologies
Fast Vectorless RLC Grid Verification
Combinational ATPG theorems for identifying untestable faults in sequential circuits
Analysis of convergence properties of a stochastic evolution algorithm
A method of reducing aliasing in a built-in self-test environment
Architecting Effectual Computation for Machine Learning Accelerators
Analyzing Deep Learning for Time-Series Data Through Adversarial Lens in Mobile and IoT Applications
Hierarchical current-density verification in arbitrarily shaped metallization patterns of analog circuits
Probabilistic Analysis of Electronic Systems via Adaptive Hierarchical Interpolation
PACT: An Extensible Parallel Thermal Simulator for Emerging Integration and Cooling Technologies
Ace-Sniper: Cloud-Edge Collaborative Scheduling Framework With DNN Inference Latency Modeling on Heterogeneous Devices
A Novel Heuristic Search Method for Two-Level Approximate Logic Synthesis
An I/O Virtualization Framework With I/O-Related Memory Contention Control for Real-Time Systems
Carry-Out Interference Optimization in WCRT Analysis for Global Fixed-Priority Multiprocessor Scheduling
ReSQM: Accelerating Database Operations Using ReRAM-Based Content Addressable Memory
Repeater scaling and its impact on CAD
Restoration-Based Merging of Functional Test Sequences
DiReCtX: Dynamic Resource-Aware CNN Reconfiguration Framework for Real-Time Mobile Applications
Automatic checking of aggregation abstractions through stateenumeration
DUNE-a multilayer gridless routing system
Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization
MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs
Testing Random Defect and Process Variation Induced Comparison Faults of TCAMs With Asymmetric Cells
Equipotential shells for efficient inductance extraction
A strongly code disjoint built-in current sensor for strongly fault-secure static CMOS realizations
An efficient heuristic procedure for solving the state assignment problem for event-based specifications
Robust Processing-In-Memory With Multibit ReRAM Using Hessian-Driven Mixed-Precision Computation
Planning Massive Interconnects in 3-D Chips
Wire width planning for interconnect performance optimization
An integrated logical and physical design flow for deep submicron circuits
Logic of constraints: a quantitative performance and functional constraint formalism
A three-parameters-only MOSFET subthreshold current CAD model considering back-gate bias and process variation
Enabling Latency-Aware Data Initialization for Integrated CPU/GPU Heterogeneous Platform
Minimization of exclusive sum-of-products expressions for multiple-valued input, incompletely specified functions
Efficient Layout Generation and Design Evaluation of Vertical Channel Devices
Deep Reinforcement Learning-Based Approach for Efficient and Reliable Droplet Routing on MEDA Biochips
An efficient algorithm for bipartite PLA folding
Compositional Reachability Analysis for Efficient Modular Verification of Asynchronous Designs
A Correlated Diffusion Noise Model for the Field-Effect Transistor
Interpolation of MOSFET table data in width, length, and temperature
Hardware-Software Co-Design Enabling Static and Dynamic Sparse Attention Mechanisms
Analysis of on-chip inductance effects for distributed RLC interconnects
An analytical integration method for the simulation of continuous-time ΔΣ modulators
ROI-HIT: Region of Interest-Driven High-Dimensional Microarchitecture Design Space Exploration
Scan-Based Testing of Post-Bond Silicon Interposer Interconnects in 2.5-D ICs
NTHU-Route 2.0: A Robust Global Router for Modern Designs
Synthesis of hazard-free asynchronous circuits with bounded wire delays
ParRA: A Shared Memory Parallel FPGA Router Using Hybrid Partitioning Approach
Equiprobability-Based Local Response Surface Method for High-Sigma Yield Estimation With Both High Accuracy and Efficiency
An observability enhancement approach for improved testability and at-speed test
Power Delivery Exploration Methodology Based on Constrained Optimization
Hierarchical Model Checking of SystemVerilog-Specified Asynchronous Circuits for Deadlock Detection
On ATPG for Multiple Aggressor Crosstalk Faults
Phase noise on a 2-GHz CMOS LC oscillator
INDM: Chiplet-Based Interconnect Network and Dataflow Mapping for DNN Accelerators
Multi-level simulation of large analog systems containing behavioral models
BlockHammer: Improving Flash Reliability by Exploiting Process Variation Aware Proactive Failure Prediction
Analytical and simulation studies of failure modes in SRAMs using high electron mobility transistors
On Improving Hotspot Detection Through Synthetic Pattern-Based Database Enhancement
Context Aware Deep Learning-Based Fault Localization for Hardware Design Code
Concurrent detection of erroneous responses in linear analog circuits
FPGA-Based Acceleration for Bayesian Convolutional Neural Networks
Decision problems for interacting finite state machines
ForASec: Formal Analysis of Hardware Trojan-Based Security Vulnerabilities in Sequential Circuits
Path sensitization in critical path problem [logic circuit design]
Mapping and Scheduling of Tasks and Communications on Many-Core SoC Under Local Memory Constraint
Experimental Validation of a Novel Methodology for Electromigration Assessment in On-Chip Power Grids
Synthesis of a Cyberphysical Hybrid Microfluidic Platform for Single-Cell Analysis
Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator
Charge-sharing alleviation and detection for CMOS domino circuits
The First Implementation of a Memtranstor Emulator and its Artificial Synaptic Plasticity Analysis
3-D Parallel Fault Simulation With GPGPU
Device and Architecture Cooptimization for FPGA Power Reduction
Combining technology mapping and placement for delay-minimization in FPGA designs
Intelligent Inverse Designs of Impedance Matching Circuits With Generative Adversarial Network
Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units
Transient simulation of high-speed interconnects based on thesemidiscretization of Telegrapher's equations
An Integrated and Efficient Approach for MOS VLSI Statistical Circuit Design
Optimized Modular Adder Architecture for Cryptographic Applications on FPGAs
SOCRATES: a highly efficient automatic test pattern generation system
Field Programmability of Supply Voltages for FPGA Power Reduction
A theory and implementation of sequential hardware equivalence
Storage-Less and Converter-Less Photovoltaic Energy Harvesting With Maximum Power Point Tracking for Internet of Things
Multi-level logic minimization using implicit don't cares
D-Linker: Debloating Shared Libraries by Relinking From Object Files
Multilevel Dataflow-Driven Macro Placement Guided by RTL Structure and Analytical Methods
Chaining and Biasing: Test Generation Techniques for Shared-Memory Verification
Identifying the Source of BW Failures in High-Frequency Linear Analog Circuits Based on S-Parameter Measurements
GREEN: An Approximate SIMD/MIMD CGRA for Energy-Efficient Processing at the Edge
FRL: Fast and Reconfigurable Accelerator for Distributed Sound Source Localization
On Signal Selection for Visibility Enhancement in Trace-Based Post-Silicon Validation
CIMQ: A Hardware-Efficient Quantization Framework for Computing-In-Memory-Based Neural Network Accelerators
Clock period minimization with wave pipelining
Automated Optical Accelerator Search Toward Superior Acceleration Efficiency, Inference Robustness, and Development Speed
Design and Optimization of a Cyberphysical Digital-Microfluidic Biochip for the Polymerase Chain Reaction
FRESH: A New Test Result Extraction Scheme for Fast TSV Tests
Diagnosis of resistive-open and stuck-open defects in digital CMOS ICs
Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories
A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs
RRAM-Based Analog Approximate Computing
ApproxFTL: On the Performance and Lifetime Improvement of 3-D NAND Flash-Based SSDs
A new discretization scheme for the semiconductor current continuity equations
On computing the minimum feedback vertex set of a directed graph bycontraction operations
Logic Locking With Provable Security Against Power Analysis Attacks
GARUDA: Designing Energy-Efficient Hardware Monitors From High-Level Policies for Secure Information Flow
Direct circuit simulation algorithms for parallel processing [VLSI]
Variation-Aware Modeling of Integrated Capacitors Based on Floating Random Walk Extraction
Beyond Write-Reduction Consideration: A Wear-Leveling-Enabled B⁺-Tree Indexing Scheme Over an NVRAM-Based Architecture
TOV: Sequential Test Generation by Ordering of Test Vectors
Homotopy Method for Finding the Steady States of Oscillators
A Computationally Efficient Reconfigurable FIR Filter Architecture Based on Coefficient Occurrence Probability
Partitioning of polynomial tasks: test generation, an example
Optimal register sharing for high-level synthesis of SSA form programs
Synthesis of robust delay-fault-testable circuits: theory
System-Oriented Harmonic-Balance Algorithms for Circuit-Level Simulation
NICE: A Nonintrusive In-Storage-Computing Framework for Embedded Applications
A Hash-Based Clustering System Software for Intermittent Computing Devices With NAND Flash Memory
IJTAG-Based Fault Recovery and Robust Microelectrode-Cell Design for MEDA Biochips
Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D Architecture and Its Application to Large-Scale Circuits
ESSENCE: Exploiting Structured Stochastic Gradient Pruning for Endurance-Aware ReRAM-Based In-Memory Training Systems
Unknown Output Values of Faulty Circuits and Output Response Compaction
Dynamic DAG Scheduling on Multiprocessor Systems: Reliability, Energy, and Makespan
Theorems and extensions of single wire replacement
An Automatic Circuit Design Framework for Level Shifter Circuits
Optimization of the maximum delay of global interconnects duringlayer assignment
Synchronous approach to the functional equivalence of embeddedsystem implementations
Triple-Phase Watermarking for Reusable IP Core Protection During Architecture Synthesis
A transformation-based method for loop folding
Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability
Path-based scheduling for synthesis
Low Bit-Width Convolutional Neural Network on RRAM
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems
A Unified Framework for Layout Pattern Analysis With Deep Causal Estimation
Path delay fault diagnosis in combinational circuits with implicitfault enumeration
Automated Synthesis of Data Paths in Digital Systems
Reconfigurable Radiation-Hardened SRAM Cell Design for Different Radiation Environments
Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips
Routing for array-type FPGA's
Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs
Elimination of redundant memory traffic in high-level synthesis
Statistical Analysis and Design of HARP FPGAs
ChordMap: Automated Mapping of Streaming Applications Onto CGRA
synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs
Optimizing dominant time constant in RC circuits
An Ultrasynchronization Checking Method With Trace-Driven Simulation for Fast and Accurate MPSoC Virtual Platform Simulation
Numerical modeling of glass flow and spin-on planarization
NOVELLA: Nonvolatile Last-Level Cache Bypass for Optimizing Off-Chip Memory Energy
Finite element analysis of SiGe heterojunction devices
Compute-in-Memory-Based Neural Network Accelerators for Safety-Critical Systems: Worst-Case Scenarios and Protections
TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking
A New ATPG Technique (ExpoTan) for Testing Analog Circuits
A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits
Bounds and analysis of aliasing errors in linear feedback shift registers
Three-level logic minimization based on function regularities
Detailed Routing Algorithms for Advanced Technology Nodes
Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem
An Improved Soft-Error Rate Measurement Technique
A new approach for modeling the MOSFET using a simple, continuous analytical expression for drain conductance which includes velocity-saturation in a fundamental way
Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits
Longer Is Shorter: Making Long Paths to Improve the Worst-Case Response Time of DAG Tasks
Sampling-Biorthogonal Time-Domain Technique for Temperature-Dependent Transient Analysis of Coaxial-TGVs in 3-D Integration
Algorithmically Enhanced Design of Spintronic-Based Tunable True Random Number Generator for Dependable Stochastic Computing
BLAST: Belling the Black-Hat High-Level Synthesis Tool
Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor
InP DHBT Analytical Modeling: Toward THz Transistors
Noninvasive Methodology for the Age Estimation of ICs Using Gaussian Process Regression
Verification of Tempura specification of sequential circuits
QoS-Adaptive Approximate Real-Time Computation for Mobility-Aware IoT Lifetime Optimization
Testability measures in pseudorandom testing
Effective Stack Wear Leveling for NVM
Efficient FinFET Device Model Implementation for SPICE Simulation
STOMA: Simultaneous Template Optimization and Mask Assignment for Directed Self-Assembly Lithography With Multiple Patterning
An Efficient Approach to Gate Matrix Layout
Machine learning-based VLSI cells shape function estimation
Rebirth-FTL: Lifetime Optimization via Approximate Storage for NAND Flash Memory
Defect level estimation of circuit testing using sequential statistical analysis
Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based Nanofabrics
Crossing-Aware Channel Routing for Integrated Optics
Symbolic Matching and Constraint Generation for Systematic Comparison of Analog Circuits
Table Look-Up MOSFET Modeling System Using a 2-D Device Simulator and Monotonic Piecewise Cubic Interpolation
An Efficient Directory Entry Lookup Cache With Prefix-Awareness for Mobile Devices
System and Design Technology Co-Optimization of SOT-MRAM for High-Performance AI Accelerator Memory System
A Statistical Analysis of PLA Folding
SAT-Based On-Track Bus Routing
Consistency checking and optimization of macromodels
An efficient methodology for building macromodels of IC fabrication processes
Strategy for electromagnetic interconnect modeling
WATSON: design space boundary exploration and model generation for analog and RFIC design
Architectural partitioning for system level synthesis of integrated circuits
RL-OPC: Mask Optimization With Deep Reinforcement Learning
Generic ILP-based approaches for time-multiplexed FPGA partitioning
Efficient Boolean division and substitution using redundancy addition and removing
Enhancing Network-on-Chip Performance by Reusing Trace Buffers
DeepPrefetcher: A Deep Learning Framework for Data Prefetching in Flash Storage Devices
A Simple and Accurate Modeling Method of Channel Thermal Noise Using BSIM4 Noise Models
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment
DyBit: Dynamic Bit-Precision Numbers for Efficient Quantized Neural Network Inference
Mining Requirements From Closed-Loop Control Models
Test and Measurement of Analog and RF Cores in Mixed-Signal SoC Environment
Collaborative Power Management Through Knowledge Sharing Among Multiple Devices
Piece-wise Quasi-linear Approximation for Nonlinear Model Reduction
Profile-guided microarchitectural floor planning for deep submicron processor design
System-Level Power Management Using Online Learning
Sparse transformations and preconditioners for 3-D capacitance extraction
FinSAL: FinFET-Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices
Hierarchical whitespace allocation in top-down placement
CARH: service-oriented architecture for validating system-level designs
Fast Attack-Resilient Distributed State Estimator for Cyber-Physical Systems
Transforming Probabilities With Combinational Logic
A Probabilistic Machine Learning Approach for the Uncertainty Quantification of Electronic Circuits Based on Gaussian Process Regression
On-Chip Optical Routing With Provably Good Algorithms for Path Clustering and Assignment
A comment on "Improving a nonenumerative method to estimate path delay fault coverage"
Post-Layout Simulation Time Reduction for Phase-Locked Loop Frequency Synthesizer Using System Identification Techniques
Make It Easy! Timing Leakage Analysis on Cryptographic Chips Based on Horizontal Leakage
LiveSSD: A Low-Interference RAID Scheme for Hardware Virtualized SSDs
Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan
A charge-based capacitance model of short-channel MOSFETs
Stepwise equivalent conductance circuit simulation technique
Verification at RTL Using Separation of Design Concerns
A multilevel engine for fast power simulation of realistic inputstreams
Modular Datapath Optimization and Verification Based on Modular-HED
ENZYME: An Energy-Efficient Transient Computing Paradigm for Ultralow Self-Powered IoT Edge Devices
Testing 3D-SoCs Using 2-D Time-Division Multiplexing
Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure
SNAS: Fast Hardware-Aware Neural Architecture Search Methodology
Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing
MLogNet: A Logarithmic Quantization-Based Accelerator for Depthwise Separable Convolution
Dynamic voltage scaling of mixed task sets in priority-driven systems
Experimental Characterization of CMOS Interconnect Open Defects
Emphasizing Functional Relevance Over State Restoration in Post-Silicon Signal Tracing
A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring
A Generic Table Recomputation-Based Higher-Order Masking
Sensitivity guided net weighting for placement-driven synthesis
Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography
Fast and Accurate Statistical Criticality Computation Under Process Variations
Maximizing Yield per Area of Highly Parallel CMPs Using Hardware Redundancy
LIDS: A Lightweight Intrusion Detection System for Controller Area Network
Full-chip routing optimization with RLC crosstalk budgeting
Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060]
Hybrid Simulation for Energy Estimation of Embedded Software
On determining sensitization criterion in an iterative gate sizing process
Data Encoding Schemes in Networks on Chip
Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools
MCSSA: A Stream-Based Multiconcurrency Systolic Sorting Array Combining Merge Tree
Retiming for Delay Recovery After DfT Insertion on Interdie Paths in 3-D ICs
Self-exercising checkers for unified built-in self-test (UBIST)