yusuke1997/dblp-id-title huggingface dataset:
An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing
Low Cost Concurrent Error Masking Using Approximate Logic Circuits
Elastic Circuits
E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters
Aging-Aware Design of Microprocessor Instruction Pipelines
A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor
Process Modeling for Photoresist Development and Design of DLR/sd (Double-Layer Resist by a Single Development) Process
Fast Algorithms for Slew-Constrained Minimum Cost Buffering
Resolving unknown inputs in mixed-level simulation with sequential elements
Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays
3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator
HIVE: Scalable Hardware-Firmware Co-Verification Using Scenario-Based Decomposition and Automated Hint Extraction
A Simulation-Based Approach for Automated Feature Localization
Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning
A Novel Method for Reducing Metal Variation With Statistical Static Timing Analysis
Simulated Annealing Without Rejected Moves
Pre-Bond Probing of Through-Silicon Vias in 3-D Stacked ICs
A new method for nonlinear circuit simulation in time domain: NOWE
Logic verification algorithms and their parallel implementation
Efficient Federated Learning for Cloud-Based AIoT Applications
Testability-Driven Random Test-Pattern Generation
An instruction-level energy model for embedded VLIW architectures
Corner Stitching: A Data-Structuring Technique for VLSI Layout Tools
Full-wave PEEC time-domain method for the modeling of on-chipinterconnects
PARS: A Pattern-Aware Spatial Data Prefetcher Supporting Multiple Region Sizes
TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis
Static leakage reduction through simultaneous V t /T ox and state assignment
Cell-Aware Test
CNoC: High-Radix Clos Network-on-Chip
AccelTran: A Sparsity-Aware Accelerator for Dynamic Inference With Transformers
Multigranular parallel algorithms for solving linear equations in VLSI circuit simulation
Relaxation-based transient sensitivity computations for MOSFET circuits
Linear dependencies in extended LFSMs
FS-TRA: Evaluating Sequential Circuit Reliability via a Fanout-Source Tracking and Reduction Approach
LithoHoD: A Litho Simulator-Powered Framework for IC Layout Hotspot Detection
DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool
System modeling and transformational design refinement in ForSyDe [formal system design]
Safe Overclocking for CNN Accelerators Through Algorithm-Level Error Detection
DAWN: Efficient Trojan Detection in Analog Circuits Using Circuit Watermarking and Neural Twins
Skewed-Load Tests for Transition and Stuck-at Faults
A Data-Driven Stochastic Memristor Model for Integrated Circuit Simulation
Negative thinking in branch-and-bound: the case of unate covering
On the C-Testability of Generalized Counters
GRIPT: Graph Attention-Assisted Inductive Methodology for Fast and Accurate Average Power Estimation From RTL Simulation Skipping Gate-Level Simulation
MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method
GNA: Reconfigurable and Efficient Architecture for Generative Network Acceleration
Schedule-Extended Synchronous Dataflow Graphs
Optimization of Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders
An algorithm for L-shaped channel routing in a diagonal model
Adaptively controlled explicit simulation
Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits
Composable Worst-Case Delay Bound Analysis Using Network Calculus
A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters
Test application time reduction for sequential circuits with scan
Pipeline optimization for asynchronous circuits: complexity analysis and an efficient optimal algorithm
Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits
Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog
Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices
Technology mapping onto very-high-speed standard CMOS hardware
Exact Timing Analysis for Asynchronous Systems
STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization
Three-dimensional resist process simulator PEACE (photo and electron beam lithography analyzing computer engineering system)
Generating Passive Compact Models for Piezoelectric Devices
Dynamic Planning of Local Congestion From Varying-Size Vias for Global Routing Layer Assignment
Taming the Stability-Constrained Performance Optimization Challenge of Distributed On-Chip Voltage Regulation
A Randomized Greedy Method for Rectangular-Pattern Fill Problems
A methodology for the simultaneous design of supply and signal networks
Flexibility and Optimization of QBF Skolem-Herbrand Certificates
Thermal-Aware Modeling and Analysis for a Power Distribution Network Including Through-Silicon-Vias in 3-D ICs
RTL-Aware Cycle-Accurate Functional Power Estimation
Curvilinear detailed routing with simultaneous wire-spreading and wire-fattening
Photonic Reconfigurable Accelerators for Efficient Inference of CNNs With Mixed-Sized Tensors
Computing Mutation Coverage in Interpolation-Based Model Checking
Input Vector Reordering for Leakage Power Reduction in FPGAs
Parasitics extraction with multipole refinement
Analysis of high-speed VLSI interconnects using the asymptotic waveform evaluation technique
Hierarchical placement and floorplanning in BEAR
Hardware-Based Load Balancing for Massive Multicore Architectures Implementing Power Gating
Generation of correlated parameters for statistical circuit simulation
A Universal Placement Technique of Compressed Instructions for Efficient Parallel Decompression
Efficient Power Network Analysis Considering Multidomain Clock Gating
A neural network approach to PLA folding problems
An ILP-Based Routing Algorithm for Pin-Constrained EWOD Chips With Obstacle Avoidance
A Dynamic Look-Ahead Heuristic for the Qubit Mapping Problem of NISQ Computers
Guest Editorial Special Section on the IEEE Symposium on Application Specific Processors 2008
Crossbar NoCs Are Scalable Beyond 100 Nodes
An Algebraic Framework for Runtime Verification
Pseudofunctional testing
Mason: A Global Floorplanning Approach for VLSI Design
Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip
An improved FET model for computer simulators
ILRM: Imitation Learning-Based Resource Management for Integrated CPU-GPU Edge Systems With Renewable Energy Sources
A new approach to topological via minimization
Security Oriented Design Framework for EM Side-Channel Protection in RTL Implementations
Interpretable CNN-Based Lithographic Hotspot Detection Through Error Marker Learning
Leveraging Probabilistic Switching in Superparamagnets for Temporal Information Encoding in Neuromorphic Systems
Event-driven power management
MUSTANG: state assignment of finite state machines targeting multilevel logic implementations
Adapting an Implicit Path Delay Grading Method for Parallel Architectures
Model selection for SOI MOSFET circuit simulation
Exact path delay fault coverage with fundamental ZBDD operations
Applicability of a Subset of Ada as an Algorithmic Hardware Description Language for Graph-Based Hardware Compilation
Efficient Wire Routing and Wire Sizing for Weight Minimization of Automotive Systems
Macromodeling CMOS circuits for timing simulation
Lithography-Aware Analog Layout Retargeting
How Secure Are Checkpoint-Based Defenses in Digital Microfluidic Biochips?
Temperature-Constrained Feasibility Analysis for Multicore Scheduling
Assessing Benefits of a Buried Interconnect Layer in Digital Designs
ReSP: A Nonintrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration
A functional fault model for sequential machines
Automatic Design for W-Band Front-End System via Bottom-Up Sizing and Layout Generation
Placement for Binary-Weighted Capacitive Array in SAR ADC Using Multiple Weighting Methods
Multiobjective Optimization for Common-Centroid Placement of Analog Transistors
Test Insertion for Dynamic Test Compaction
Efficient Memory Partitioning for Parallel Data Access in FPGA via Data Reuse
Incremental Solving Techniques for SAT-based ATPG
Channel Parameter and Read Reference Voltages Estimation in 3-D NAND Flash Memory Using Unsupervised Learning Algorithms
Cross-Contamination Aware Design Methodology for Pin-Constrained Digital Microfluidic Biochips
Analysis and Design of Tamper-Mitigating Microfluidic Routing Fabrics
SubMap: A Partial Mapping Strategy for CGRA Based on sub-CGRA Exploration
Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip
Power Grid Electromigration Checking Using Physics-Based Models
Capacitance calculation of IC packages using the finite element method and planes of symmetry
Comments on 'Simulation of nonlinear circuits in the frequency domain' [with reply]
Multilevel symmetry-constraint generation for retargeting large analog layouts
Joint Charge and Thermal Management for Batteries in Portable Systems With Hybrid Power Sources
Min-cost flow-based algorithm for simultaneous pin assignment and routing
Generalized Affine Equivalence Checking of Boolean Functions via Reachability Analysis
PolyPUF: Physically Secure Self-Divergence
Operation-centric hardware description and synthesis
Optimized synthesis techniques for testable sequential circuits
Mix & Latch: Comparison With State-of-the-Art Retiming on a RISC-V Benchmark
Alternative Encoding: A Two-Step Transition Reduction Scheme for MLC STT-RAM Cache
An industrially effective environment for formal hardware verification
Personalized Meta-Federated Learning for IoT-Enabled Health Monitoring
A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator
Practical solutions for counting scalars and dependences in ATOMIUM-a memory management system for multidimensional signal processing
Realizable reduction of interconnect circuits including self and mutual inductances
VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool
A charge sheet capacitance model of short channel MOSFETs for SPICE
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits
Design-Specific Optimization Considering Supply and Threshold Voltage Variations
Routing and Wavelength Assignment for Multiple Multicasts in Optical Network-on-Chip (ONoC)
SAT-Based Fault Equivalence Checking in Functional Safety Verification
Modeling of magnetic field sensitivity of bipolar magnetotransistors using HSPICE
Optimality of a feedthrough assignment algorithm in a CMOS logic cell layout
Divide and Slide: Layer-Wise Refinement for Output Range Analysis of Deep Neural Networks
Learning-Based Power Management for Multicore Processors via Idle Period Manipulation
An Implicit Approach to Minimizing Range-Equivalent Circuits
A 3D thermal simulation tool for integrated devices-Atar
Analyzing continuous-time Delta-Sigma-Modulators with generic behavioral models
QT-Adaptation Engine: Adaptive QoS-Aware Scheduling and Governing in Thermally Constrained Mobile Devices
A Novel gamma d/n, RLCG Transmission Line Model Considering Complex RC(L) Loads
3-valued trace-based fault simulation of synchronous sequential circuits
Temperature Tracking: Toward Robust Run-Time Detection of Hardware Trojans
CoMN: Algorithm-Hardware Co-Design Platform for Nonvolatile Memory-Based Convolutional Neural Network Accelerators
Partitioning and Placement Technique for CMOS Gate Arrays
Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method
Information-Theoretic Syndrome Evaluation, Statistical Root-Cause Analysis, and Correlation-Based Feature Selection for Guiding Board-Level Fault Diagnosis
Generation of test patterns without prohibited pattern set
Memristor-Based Brain Emotional Learning Neural Network With Attention Mechanism and Its Application
Extending the FSMD Framework for Validating Code Motions of Array-Handling Programs
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism
A New Automatic Logic Interconnection Verification System for VLSI Design
DynMap: A Heuristic Dynamic Mapper for CGRA Multitask Dynamic Resource Allocation
Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions
A Class of Cellular Architectures to Support Physical Design Automation
Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits
Estimation of power dissipation in switched-capacitor circuits
Synthesis of Timed Circuits Based on Decomposition
Simultaneous routing and buffer insertion with restrictions onbuffer locations
Switch-level simulation using dynamic graph algorithms
Graph-Pair Decision Diagram Construction for Topological Symbolic Circuit Analysis
Enhanced Precision Analysis for Accuracy-Aware Bit-Width Optimization Using Affine Arithmetic
Application and Verification of Local Nonsemantic-Preserving Transformations in System Design
Algorithmic study of single-layer bus routing for high-speed boards
Robust Quantum Feature Selection With Sparse Optimization Circuit
Synthesizable Higher-Order Functions for C++
The Software/Hardware Co-Design and Implementation of SM2/3/4 Encryption/Decryption and Digital Signature System
Toward Efficient Execution of Mainstream Deep Learning Frameworks on Mobile Devices: Architectural Implications
A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based Analysis of Large-Scale Integrated Circuits
Problems of Yield Gradient Estimation for Truncated Probability Density Functions
Accurate Transmission and Crosstalk Estimation Methodology for Silicon Photonic WDM Filters
Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression
Single-Row Routing with Crossover Bound
Instruction Cache Locking Using Temporal Reuse Profile
Entropy Reduction Model for Pinpointing Differential Fault Analysis on SIMON and SIMECK Ciphers
An efficient 3-D spectral-element method for Schrödinger equation in nanodevice simulation
A Novel Attack Mode on Advanced Technology Nodes Exploiting Transistor Self-Heating
Design of CMOS MEMS based on mechanical resonators using a RF simulation approach
Floorplanning using a tree representation
Shuttling for Scalable Trapped-Ion Quantum Computers
Transforming Cyclic Circuits Into Acyclic Equivalents
Neural Evolutionary Architecture Search for Compact Printed Analog Neuromorphic Circuits
Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits
Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis
Cross-Layer Co-Optimization of Network Design and Chiplet Placement in 2.5-D Systems
A robust channel router
Time-domain simulation of multiconductor transmission lines with frequency-dependent losses
Multicycle Broadside and Skewed-Load Tests for Test Compaction
DynLiB: Maximizing Energy Availability of Hybrid Li-Ion Battery Systems
A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning
Mobile Transformer Accelerator Exploiting Various Line Sparsity and Tile-Based Dynamic Quantization
A technique for pull-up transistor folding
On Synthesis of Boolean Expressions for Memristive Devices Using Sequential Implication Logic
Slicing floorplan with clustering constraint
System-Level Online Power Estimation Using an On-Chip Bus Performance Monitoring Unit
Inverse-Geometry Dependence of MOS Transistor Electrical Parameters
DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement
A Reagent-Saving Mixing Algorithm for Preparing Multiple-Target Biochemical Samples Using Digital Microfluidics
Space-Time-Efficient Modeling of Large-Scale 3-D Cross-Point Memory Arrays by Operation Adaption and Network Compaction
Fast Test Integration: Toward Plug-and-Play At-Speed Testing of Multiple Clock Domains Based on IEEE Standard 1500
Boundary single-layer routing with movable terminals
High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models
PRO-TIME: Prerouting Optimization-Aware Timing Prediction via Multimodal Learning
Security-Aware Resource Binding to Enhance Logic Obfuscation
Guest Editorial Special Section on Hardware Security and Trust
Differentiable Inference of Temporal Logic Formulas
Some heuristics for generating tree-like FBDD types
Stochastic Models for Wireability Analysis of Gate Arrays
TEA-Z: A Tiny and Efficient Architecture Based on Z Channel for Image Watermarking and Its Versatile Hardware Implementation
FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large Applications
Improved Simulation of p- and n-channel MOSFET's Using an Enhanced SPICE MOS3 Model
A probably approximately correct framework to estimate performancedegradation in embedded systems
Placement Density Aware Power Switch Planning Methodology for Power Gating Designs
Optimal cell generation for dual independent layout styles
Flicker Noise Formulations in Compact Models
A two-stage solution approach to multidimensional periodicscheduling
Majority-Inverter Graph: A New Paradigm for Logic Optimization
Dynamic Streamization Model Execution for SIMD Engines on Multicore Architectures
An Efficient Low-Power Repeater-Insertion Scheme
Storage-Based Logic Built-In Self-Test With Cyclic Tests
OPDB: A Scalable and Modular Design Benchmark
A compact IGFET model-ASIM
Efficient Job Offloading in Heterogeneous Systems Through Hardware-Assisted Packet-Based Dispatching and User-Level Runtime Infrastructure
Table-Based Model of a Dual-Gate Transistor for Statistical Circuit Simulation
An Adaptive Flash Translation Layer for High-Performance Storage Systems
DC-DC Converter-Aware Power Management for Low-Power Embedded Systems
Throughput-Conscious Energy Allocation and Reliability-Aware Task Assignment for Renewable Powered In-Situ Server Systems
Modeling and Analysis of Leakage Currents in Double-Gate Technologies
Tensor Computation: A New Framework for High-Dimensional Problems in EDA
Integrating communication protocol selection with hardware/software codesign
Efficient approximation of symbolic network functions using matroid intersection algorithms
Using Transfer-Resource Graph for Software-Based Verification of System-on-Chip
Symbolic optimization of interacting controllers based onredundancy identification and removal
SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing
TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits
Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization
Guest Editorial [intro. to the special issue on the 2006 IEEE/ACM Design, Automation and Test in Europe Conference]
Accurate Direct and Indirect On-Chip Temperature Sensing for Efficient Dynamic Thermal Management
Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations
Approximation Attacks on Strong PUFs
LightFS: A Lightweight Host-CSD Coordinated File System Optimizing for Heavy Small File Accesses
A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling
Simulation of Mutually Coupled Oscillators Using Nonlinear Phase Macromodels
Reducing the CNOT Count for Clifford+T Circuits on NISQ Architectures
TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing
Reducing LUT Count for Mealy FSMs With Transformation of States
A fanout optimization algorithm based on the effort delay model
'Zone-refining' techniques for IC layout compaction
SP&R: SMT-Based Simultaneous Place-and-Route for Standard Cell Synthesis of Advanced Nodes
Scan-BIST based on transition probabilities for circuits with single and multiple scan chains
SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes
Multipattern Scan-Based Test Sets With Small Numbers of Primary Input Sequences
Advanced Variance Reduction and Sampling Techniques for Efficient Statistical Timing Analysis
Efficient Variability-Aware NBTI and Hot Carrier Circuit Reliability Analysis
Latch-Based Performance Optimization for Field-Programmable Gate Arrays
Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking
Serial-Equivalent Static and Dynamic Parallel Routing for FPGAs
A New Global Router for Gate Array LSIsi
Generalized optimum path search
DECISIVE: Designing Critical Systems With Iterative Automated Safety Analysis
Transient Analysis of CMOS-Gate-Driven RLGC Interconnects Based on FDTD
WAVING Goodbye to Manual Waveform Analysis in HDL Design With WAL
DLV: Exploiting Device Level Latency Variations for Performance Improvement on Flash Memory Storage Systems
Modeling of avalanche generation current of bipolar junction transistors for computer circuit simulation
Analysis of energy reduction on dynamic voltage scaling-enabled systems
Selection of lumped element models for coupled lossy transmission lines
Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking
Energy-Efficient CNN Personalized Training by Adaptive Data Reformation
Variable-length input Huffman coding for system-on-a-chip test
Track Routing and Optimization for Yield
Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices
Rigorous integration of semiconductor process and device simulators
Bridge fault diagnosis using stuck-at fault simulation
Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment
Comparing two-level and ordered binary decision diagram representations of logic functions
Guest Editorial Special Section on Optical Interconnects
A Memristor Crossbar-Based Lyapunov Equation Solver
A Reliability-Oriented Placement Algorithm for Reconfigurable Digital Microfluidic Biochips Using 3-D Deferred Decision Making Technique
Fast and Efficient High-Sigma Yield Analysis and Optimization Using Kernel Density Estimation on a Bayesian Optimized Failure Rate Model
Enhancing Test Compression With Dependency Analysis for Multiple Expansion Ratios
Statistical Modeling of Soft Error Influence on Neural Networks
SEGRA: a very fast general area router for multichip modules
Techniques to Improve Write and Retention Reliability of STT-MRAM Memory Subsystem
Exploiting Uncorrectable Data Reuse for Performance Improvement of Flash Memory
TIME: A Training-in-Memory Architecture for RRAM-Based Deep Neural Networks
A practical methodology for early buffer and wire resource allocation
Predictability and Performance Aware Replacement Policy PVISAM for Unified Shared Caches in Real-time Multicores
Reliability Analysis of Mixture Preparation Using Digital Microfluidic Biochips
The Tire as an Intelligent Sensor
Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation
Optimized synthesis of asynchronous control circuits from graph-theoretic specifications
A Hardware-Friendly Real-Time Implementation of the Auditory Attention Based on a Novel Spiking Winner-Take-All Network
Increased Output Corruption and Structural Attack Resilience for SAT Attack Secure Logic Locking
Sequential circuit fault simulation using logic emulation
CMCache: An Adaptive Cross-Level Data Placement Method for Multilevel Cache
The analysis of one-dimensional linear cellular automata and their aliasing properties
Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration
Storage-Aware Algorithms for Dilution and Mixture Preparation With Flow-Based Lab-on-Chip
Numerical device modeling for electronic circuit simulation
Module Placement Based on Resistive Network Optimization
Methodology Verification of Hierarchically Described VLSI Circuits
PEDSA: High-Throughput Pipeline-Based FPGA Accelerator for Convolutional Encoder-Decoder Segmentation Networks
Robust Compact Model of High-Voltage MOSFET's Drift Region