yusuke1997/dblp-id-title huggingface dataset:
Discrete H 2 /H ∞ Nonlinear Controller Design Based on Fuzzy Region Concept and Takagi-Sugeno Fuzzy Framework
A Novel Dual-Band Branch Line Coupler for Dual-Band Butler Matrix
Multi-Stub-Loaded Differential-Mode Planar Multiband Bandpass Filters
A 28-nm CMOS 12-Bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC
Stable Patterns Realized by a Class of One-Dimensional Two-Layer CNNs
A Noise Filtering Technique for Fractional-N Frequency Synthesizers
Low-Cost 14-Bit Current-Steering DAC With a Randomized Thermometer-Coding Method
Low-Area and High-Throughput Architecture for an Adaptive Filter Using Distributed Arithmetic
Complex-Network-Inspired Design of Traffic Generation Patterns in Communication Networks
A Spread Spectrum Clock Generator for DisplayPort Main Link
A 2.4-GHz All-Digital PLL With a 1-ps Resolution 0.9-mW Edge-Interchanging-Based Stochastic TDC
Correction Structures for Linear Weakly Time-Varying Systems
Tiny Piezoelectric Harvesters: Principles, Constraints, and Power Conversion
UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications
Selective metal parallel shunting inductor and its VCO application
Maximum Energy Efficiency Tracking Circuits for Converter-Less Energy Harvesting Sensor Nodes
A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer
Analog Iterative LDPC Decoder Based on Margin Propagation
Convergence of a Class of Cooperative Standard Cellular Neural Network Arrays
A Gb/s+ Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time
Low 1/f 3 Phase Noise Quadrature LC VCOs
Fault Estimation Observer Design for Descriptor Switched Systems With Actuator and Sensor Failures
An Output Buffer for 3.3-V Applications in a 0.13- μħbox m 1/2.5-V CMOS Process
An Agile LUT-Based All-Digital Transmitter
A Novel Concept of Virtual Impedance for High Frequency Tri-Band Impedance Matching Networks
A 4 × 64 MIMO Detector for Generalized Spatial Modulation Systems
Miniaturized Single-Ended-to-Balanced Arbitrary Four-Section Coupled-Line Coupler With Inherent Impedance Matching
High-Throughput FPGA Implementation of QR Decomposition
Wideband Varactorless LC VCO Using a Tunable Negative-Inductance Cell
A CMOS burst-mode optical transmitter for 1.25-Gb/s ethernet PON applications
Design-Oriented Analysis of Quantization-Induced Limit Cycles in a Multiple-Sampled Digitally Controlled Buck Converter
Output-Capacitor-Free Adaptively Biased Low-Dropout Regulator for System-on-Chips
A 0.25-V Rail-to-Rail Three-Stage OTA With an Enhanced DC Gain
A 3-MHz 17.3- $\mu$ W 0.015% Period Jitter Relaxation Oscillator With Energy Efficient Swing Boosting
WRA: A 2.2-to-6.3 TOPS Highly Unified Dynamically Reconfigurable Accelerator Using a Novel Winograd Decomposition Algorithm for Convolutional Neural Networks
Piecewise Quadratic Slope Compensation Technique for DC-DC Switching Converters
Statistical Strategies to Reproduce the Propagation Delay Time Variability Using Compact Models
Optically Powered Optical Transmitter Using a Single Light-Emitting Diode
A Low Power Self-healing Resilient Microarchitecture for PVT Variability Mitigation
LDO With Improved Common Gate Class-AB OTA Handles any Load Capacitors and Provides Fast Response to Load Transients
Reduction of Aliasing Effects of RF PWM Modulated Signals by Cross Point Estimation
Influence of Noise on the Phase and Amplitude of Second-Order Oscillators
FPGA Implementations of Piecewise Affine Functions Based on Multi-Resolution Hyperrectangular Partitions
Open-Loop Fractional Division Using a Voltage-Comparator-Based Digital-to-Time Converter
A Two-Stage Approach to Harmonic Rejection Mixing Using Blind Interference Cancellation
Design of KY Converter With Constant On-Time Control Under DCM Operation
Synchronization of Stochastic Lévy Noise Systems on a Multi-Weights Network and Its Applications of Chua's Circuits
Dynamic Power Management for Neuromorphic Many-Core Systems
A High-Performance Stochastic LDPC Decoder Architecture Designed via Correlation Analysis
PID-Based Bit Allocation Strategy for H.264/AVC Rate Control
Effects of Current Time-Delayed Feedback on the Dynamics of a Permanent-Magnet Synchronous Motor
Compressive Self-Powering of Piezo-Floating-Gate Mechanical Impact Detectors
A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector
An Analytical Time-Domain Expression for the Net Ripple Produced by Parallel Interleaved Converters
Bayesian Inference With Muller C-Elements
A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator
Sliding-mode control design of a boost-buck switching converter for AC signal generation
M-Matrix-Based State Observer Design for Genetic Regulatory Networks With Mixed Delays
A Quadrature Modulation Transmitter Using Two Frequency Synthesizers
Single Plastic Optical Fiber, Multiple Channel Data Link for Sensing Applications With PCB Implemented Transmitter and Receiver
Spectral Redundancy Compensation in Multi-Static Millimeter-Wave Imaging
A Wideband Tunable Reflection-Type Phase Shifter With Wide Relative Phase Shift
Nonidealities of Tow-Thomas biquads Using VOA- and CFOA-based Miller integrators
Reconstruction of piecewise chaotic dynamic using a genetic algorithm multiple model approach
A 10-b 200-kS/s 250-nA Self-Clocked Coarse-Fine SAR ADC
A 75 dB SNDR 10-MHz Signal Bandwidth Gm-C-Based Sigma-Delta Modulator With a Nonlinear Feedback Compensation Technique
Enhanced Scaling-Free CORDIC
Memory-efficient architecture for JPEG 2000 coprocessor with large tile image
Fully Distributed Containment Control for Multiple Euler-Lagrange Systems Over Directed Graphs: An Event-Triggered Approach
Advanced Control Strategies for DC-DC Buck Converters With Parametric Uncertainties via Experimental Evaluation
Microwave Voltage-Controlled Oscillator With Harmonic-Suppressed Stepped-Impedance-Resonator Filter
ADC-Based Serial I/O Receivers
Continuous LTI Systems Defined on L p Functions and D L p prime Distributions: Analysis by Impulse Response and Convolution
Adaptive Double Event-Triggered Control for Linear Multi-Agent Systems With Actuator Faults
A Low Phase Noise Open Loop Fractional-N Frequency Synthesizer With Injection Locking Digital Phase Modulator
Tunable Duplexer With Passive Feed-Forward Cancellation to Improve the RX-TX Isolation
A 128-Stage Analog Accumulator for CMOS TDI Image Sensor
Multi-Slot Main Memory System for Post DDR3
A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems
A CMOS Follower-Type Voltage Regulator With a Distributed-Element Fractional-Order Control
Analytical Expression of Quantization Noise in Time-to-Digital Converter Based on the Fourier Series Analysis
On-Chip Support for NoC-Based SoC Debugging
An Analog Approach to Suppressing In-Band Narrow-Band Interference in UWB Receivers
Tunable Neuron With PWL Approximation Based on the Minimum Operator
Multirate Charge-Domain Filter Design for RF-Sampling Multi-Standard Receiver
Realizing Unequal Error Correction for nand Flash Memory at Minimal Read Latency Overhead
Embedding Compression in Chaos-Based Cryptography
Modified Dual-CLCG Method and its VLSI Architecture for Pseudorandom Bit Generation
Online calibration of a Nyquist-rate analog-to-digital converter using output code-density histograms
An Integrated Step-Up/Step-Down DC-DC Converter Implemented With Switched-Capacitor Circuits
A SAW-Less Receiver Front-End Employing Body-Effect Control IIP2 Calibration
Consensus in Networked Multiagent Systems With Stochastic Sampling
Clifford Theory: A Geometrical Interpretation of Multivectorial Apparent Power
Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors
A 2.3-mW 11-cm Range Bootstrapped and Correlated-Double-Sampling Three-Dimensional Touch Sensing Circuit for Mobile Devices
CorrectionS to "Blind Adaptive DS/CDMA Receivers for Multipath and Multiuser Environments"
Optimization of EVM Through Diode Bias Control Using a Blind Algorithm Applied to Multiport Receivers
CMOS Power Amplifier Integrated Circuit With Dual-Mode Supply Modulator for Mobile Terminals
Layered Decoding Algorithm and Two-Level Quasi-Cyclic Matrix Construction for Rate Compatible Modulation
A Capacitive-Based Accelerometer IC Using Injection-Nulling Switch Technique
New Approach to the Reduction of Sign-Extension Overhead for Efficient Implementation of Multiple Constant Multiplications
Switch-Controllable OTRA-Based Square/Triangular Waveform Generator
Design of Constrained Causal Stable IIR Filters Using a New Second- Order-Cone-Programming-Based Model-Reduction Technique
A Quantum-Behaved Particle Swarm Optimization With Diversity-Guided Mutation for the Design of Two-Dimensional IIR Digital Filters
High-Throughput and Area-Efficient MIMO Symbol Detection Based on Modified Dijkstra's Search
Analysis and Optimum Design of a Class E RF Power Amplifier
Statistical Analysis of Self-Oscillating Power Amplifiers
Exploiting a Micro Pirani Gauge for Beyond Atmospheric Pressure Measurement
Reduction in Sampling-Point Numbers for 2-D Discrete Fourier Transform Used in Harmonic Balance Method
Lie algebraic stability analysis for switched systems with continuous-time and discrete-time subsystems
Wideband Signal Synthesis Using Interleaved Partial-Order Hold Current-Mode Digital-to-Analog Converters
12-b Enhanced Input Range On-Chip Quasi-Digital Converter With Temperature Compensation
Real-Time Dynamic Voltage Loop Scheduling for Multi-Core Embedded Systems
The bond between causal complex cepstra and Sheffer polynomials
Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits
Modeling and Evaluating the Gate Length Dependence of BTI
Histogram of Oriented Gradients Feature Extraction From Raw Bayer Pattern Images
SOI CMOS Implementation of a Multirate PSK Demodulator for Space Communications
Low-Area and Low-Power Latch-Based Thermometer-Code Shift-Register
A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators
Novel current-mode background suppression for 2-D LWIR applications
Fully Distributed Consensus Tracking of Multiagent Systems With a High-Dimensional Leader and Directed Communication Topology
Two-port ideal power transferitors: a unified introduction to ideal transformer and gyrator
An Energy Efficient Charging Technique for Switched Capacitor Voltage Converters With Low-Duty Ratio
Compensation of Frequency-Dependent Gain/Phase Imbalance in Predistortion Linearization Systems
Differential Capacitive Readout Circuit Using Oversampling Successive Approximation Technique
Spectral Analysis of Phase Noise in Bipolar LC-Oscillators - Theory, Verification, and Design
Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional- N PLLs
A Self-Calibrated Bang-Bang Phase Detector for Low-Offset Time Signal Processing
Direct Adaptive Optimal Control for Uncertain Continuous-Time LTI Systems Without Persistence of Excitation
TD-SCDMA/HSDPA Transceiver and Analog Baseband Chipset in 0.18-μm CMOS Process
A Frequency-Based Model for Limit Cycle and Spur Predictions in Bang-Bang All Digital PLL
Process Scalability of Pulse-Based Circuits for Analog Image Convolution
A Circuit Model of Human Whole Blood in a Microfluidic Dielectric Sensor
Register-Less NULL Convention Logic
Energy and Delay Tradeoffs of Soft-Error Masking for 16-nm FinFET Logic Paths: Survey and Impact of Process Variation in the Near-Threshold Region
Soft Error Detection and Correction Technique for Radiation Hardening Based on C-element and BICS
A CMOS Ultra Low-Power and Highly Efficient UWB-IR Transmitter for WPAN Applications
Sliding Window Based Nonlinear H ∞ Filtering: Design and Experimental Results
Design of signed powers-of-two coefficient perfect reconstruction QMF Bank using CORDIC algorithms
Impedance Matching and Reradiation in LPTV Receiver Front-Ends: An Analysis Using Conversion Matrices
A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion
Reshuffled Diagonal Rotated Walk Switching Scheme for DAC INL Reduction
Optimal Ladder Filters
Multimode Reconfigurable Digital SigmaDelta Modulator Architecture for Fractional-N PLLs
Processing Near Sensor Architecture in Mixed-Signal Domain With CMOS Image Sensor of Convolutional-Kernel-Readout Method
Design and Implementation of Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids
An Energy-Efficient Partial FFT Processor for the OFDMA Communication System
3-D FIR Cone-Shaped Filter Design by a Nest of McClellan Transformations and Its Variable Design
Fixed-Time Consensus for a Class of Heterogeneous Nonlinear Multiagent Systems
An IEEE Single Precision Floating Point Arithmetic-Based Apodization Architecture for Portable Ultrasound Imaging System
Clock-Voltage Co-Regulator With Adaptive Power Budget Tracking for Robust Near-Threshold-Voltage Sequential Logic Circuits
Adaptive Control for Nonlinear Systems With Uncertain Output Function and Unknown Homogenous Growth Rate
A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process
CMOS Image Sensor Based Physical Unclonable Function for Coherent Sensor-Level Authentication
Generalized Analysis of Symmetric and Asymmetric Memristive Two-Gate Relaxation Oscillators
The universal opamp and applications in continuous-time resistorless and capacitorless linear weighted voltage addition
A Memristive Pascaline
A µ W Complementary Bridge Rectifier With Near Zero Turn-on Voltage in SOS CMOS for Wireless Power Supplies
A 61-nW Level-Crossing ADC With Adaptive Sampling for Biomedical Applications
A 4×4 IR UWB Timed-Array Radar Based on 16-Channel Transmitter and Sampling Capacitor Reused Receiver
Why Analog-to-Information Converters Suffer in High-Bandwidth Sparse Signal Applications
Intrinsic Distortion of a Fully Differential BD-Modulated Class-D Amplifier With Analog Feedback
Predicting the Evolution Process of Infrastructure Networks With an NSIPA Link Prediction Method
A cost-effective approach to the design and layout of a 14-b current-steering DAC macrocell
A 5-bit 300-900-MS/s 0.8-1.2-V Supply Voltage ADC With Background Self-Calibration
A Continuous-Flow Memory-Based Architecture for Real-Valued FFT
Hardware/Software Approach to Designing Low-Power RNS-Enhanced Arithmetic Units
A Lattice Reduction-Aided MIMO Channel Equalizer in 90 nm CMOS Achieving 720 Mb/s
A Novel and High-Performance Modular Square Scheme for Elliptic Curve Cryptography Over GF( ${p}$ )
Toward Understanding the Return Path Capacitance in Capacitive Human Body Communication
Systematic design exploration of delta-sigma ADCs
Low-Power and Area-Efficient Shift Register Using Pulsed Latches
High Sensitivity and Dynamic-Range 25 Gbaud Silicon Receiver Chipset With Current-Controlled DC Adjustment Path and Cube-Shape Ge-on-Si PD
An Energy-Efficient Mobile Memory I/O Interface Using Simultaneous Bidirectional Multilevel Dual-Band Signaling
Frequency-Domain Optimization of Digital Switching Noise Based on Clock Scheduling
A 0.035-pJ/bit/dB 20-Gb/s Adaptive Linear Equalizer With an Adaptation Time of 2.68 µs
Memory-free low-cost designs of advanced encryption standard using common subexpression elimination for subfunctions in transformations
Generation of n˟ m -Wing Lorenz-Like Attractors From a Modified Shimizu-Morioka Model
Approximated Core Transform Architectures for HEVC Using WHT-Based Decomposition Method
A Technique for Enhancing Varactor's Quality Factor in Millimeter-Wave Frequencies
PPV Modeling of Memristor-Based Oscillators and Application to ONN Pattern Recognition
Two Reciprocal Power Theorems for Passive Linear Time-Invariant Multiports
A 5-V 290-µW Low-Noise Chopper-Stabilized Capacitive-Sensor Readout Circuit in 0.8-µm CMOS Using a Correlated-Level-Shifting Technique
Compact Analog Temporal Edge Detector Circuit With Programmable Adaptive Threshold for Neuromorphic Vision Sensors
Low-power GS/s track-and-hold with 10-b resolution at Nyquist in SiGe BiCMOS
Learning in Silicon Beyond STDP: A Neuromorphic Implementation of Multi-Factor Synaptic Plasticity With Calcium-Based Dynamics
Design of Pipelined IIR Filters Using Two-Stage Frequency-Response Masking Technique
Robust Adaptive Algorithm for Smart Antenna System With α-Stable Noise
An analog floating-gate node for Supervised learning
An Approximate Closed-Form Channel Model for Diverse Interconnect Applications
A 12-bit SAR ADC With a DAC-Configurable Window Switching Scheme
A 1 pF-to-10 nF Generic Capacitance-to-Digital Converter Using Zero-Crossing ΔΣ Modulation
A capacitor cross-coupled common-gate low-noise amplifier
LMS-based calibration of an RF digitally controlled oscillator for mobile phones
A Reconfigurable and Extendable Digital Architecture for Mixed Signal Power Electronics Controller
A Review on Compact Modeling of Multiple-Gate MOSFETs
Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance
Sparse Artificial Neural Networks Using a Novel Smoothed LASSO Penalization
Iterative Approach With Optimization-Based Execution Scheme for Parameter Identification of Distributed Parameter Systems and its Application in Secure Communication
A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS
Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints
Applications and improvement of H.264 in medical video compression
Nonlinearity Modeling of a Chireix Outphasing Power Amplifier
Codesign of a PA-Antenna Block in Silicon Technology for 80-GHz Radar Application
Input and output coupled nonlinear systems
A 1.3 mW low-IF, current-reuse, and current-bleeding RF front-end for the MICS band with sensitivity of -97 dbm
A Reconfigurable Dual-Mode CMOS Power Amplifier With Integrated T/R Switch for 0.1-1.5-GHz Multistandard Applications
Wireless Dosimeter: System-on-Chip Versus System-in-Package for Biomedical and Space Applications
Adjoint of a Linear Multiport Element Based on Generalized Duality
Hardware-Algorithm Co-Design of a Compressed Fuzzy Active Learning Method
A 5 pJ/pulse at 1-Gpps Pulsed Transmitter Based on Asynchronous Logic Master-Slave PLL Synthesis
A new modeling and optimization of gain-boosted cascode amplifier for high-speed and low-voltage applications
Reusable silicon IP cores for discrete wavelet transform applications
Turing Meets Circuit Theory: Not Every Continuous-Time LTI System Can be Simulated on a Digital Computer
Boolean Logic Operations and Computing Circuits Based on Memristors
Electromagnetic Energy Harvester Interface Design for Wearable Applications
An Energy Autonomous 400 MHz Active Wireless SAW Temperature Sensor Powered by Vibration Energy Harvesting
Synchronization of Nonlinear Circuits in Dynamic Electrical Networks With General Topologies
A 0.3-V 0.705-fJ/Conversion-Step 10-bit SAR ADC With a Shifted Monotonic Switching Procedure in 90-nm CMOS
Gyrator Realization Based on a Capacitive Switched Cell
An automatic coefficient design methodology for high-order bandpass sigma-delta modulator with single-stage structure
Characterization of Analog Circuits Using Transfer Function Trajectories
IRD Digital Background Calibration of SAR ADC With Coarse Reference ADC Acceleration
Efficient Fuzzy Extractors Based on Ternary Debiasing Method for Biased Physically Unclonable Functions
Adaptive Spur Cancellation Technique in All-Digital Phase-Locked Loops
Adaptive subsample delay estimation using windowed correlation
A DROIC Based on PFM ADCs Employing Over-Integration for Error Shaping
Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation
Ambient Light Organic Sensor in a Printed Complementary Organic TFT Technology on Flexible Plastic Foil
A High-Throughput LDPC Decoder Architecture With Rate Compatibility
Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division
Conditions for the Stability of Switched Systems Containing Unstable Subsystems
A Low-Power Fast Start-Up Crystal Oscillator With an Autonomous Dynamically Adjusted Load
High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards
General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space
CMOS-Based Monolithic Controllers for Smart Sensors Comprising Micromembranes and Microcantilevers
Current-Mode Analog Adaptive Mechanism for Ultra-Low-Power Neural Networks
A Delay-Locked Loop With Statistical Background Calibration
A new SNR's estimator for QPSK Modulations in an AWGN channel
Dual Pulse Shaping Transmission and Equalization for High-Speed Wideband Wireless Communication Systems
Nonlinear Analysis of BBCDR Jitter Generation Using VOLTERRA Series
Techniques for Random Masking in Hardware
On the generalized DFIIt structure and its state-space realization in digital filter implementation
A Study of Phase Noise and Frequency Error of a Fractional-N PLL in the Course of FMCW Chirp Generation
A Background Sample-Time Error Calibration Technique Using Random Data for Wide-Band High-Resolution Time-Interleaved ADCs
Guest Editorial Special Issue on the 2020 IEEE International Symposium on Circuits and Systems
Cooperative Formation of Self-Propelled Vehicles With Directed Communications
Quasi-Reflectionless Microstrip Bandpass Filters Using Bandstop Filter for Out-of-Band Improvement
A 280-KBytes Twin-Bit-Cell Embedded NOR Flash Memory With a Novel Sensing Current Protection Enhanced Technique and High-Voltage Generating Systems
A realization of a below-1-V operational and 30-MS/s sample-and-hold IC with a 56-dB signal-to-noise ratio by applying the current-based circuit approach
A 45-dB, 150-Hz, and 18-mW Touch Controller for On-Cell Capacitive TSP Systems
A High Current Accuracy Boost White LED Driver Based on Offset Calibration Technique
A Novel Asynchronous CA Neuron Model: Design of Neuron-Like Nonlinear Responses Based on Novel Bifurcation Theory of Asynchronous Sequential Logic Circuit
Hardware-Efficient Systolic-Like Modular Design for Two-Dimensional Discrete Wavelet Transform
A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link
A +9-dBm Output P 1dB Active Feedback CMOS Wideband LNA for SAW-Less Receivers
Event-Based Consensus Control for a Linear Directed Multiagent System With Time Delay
A Compact Fully-Integrated Extremum-Selector-Based Soft-Start Circuit for Voltage Regulators in Bulk CMOS Technologies
A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC
A Discrete Model for Correlation Between Quantization Noises
Digital Noise Coupled MASH Delta-Sigma Modulator
Low-Noise Parametric Resonant Amplifier
All-Digital Simple Clock Synthesis Through a Glitch-Free Variable-Length Ring Oscillator
An MTL-Based Configurable Block for Current-Mode Nonlinear Analog Computation
An RF Carrier Bursting System Using Partial Quantization Noise Cancellation
Efficient CMOS Invertible Logic Using Stochastic Computing
Design of Fractional Order Digital Differentiator Using Radial Basis Function
Forward Computations for Context-Adaptive Variable-Length Coding Design
Design of 370-ps Delay Floating-Voltage Level Shifters With 30-V/ns Power Supply Slew Tolerance
Design of Sparse FIR Filters With Joint Optimization of Sparsity and Filter Order
Fully Integrated Digital GaN-Based LSK Demodulator for High-Temperature Applications
High-Efficiency Low Voltage Inverse Class-F Power Amplifier Design Based on Harmonic Control Network Analysis
Dynamic Performance Characterization of Embedded Single-Ended Mixed-Signal Circuits
A 14-Bit 30-MS/s 38-mW SAR ADC Using Noise Filter Gear Shifting
Single-Phase SP-Domino: A Limited-Switching Dynamic Circuit Technique for Low-Power Wide Fan-in Logic Gates
VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter
Breaking two secure communication systems based on chaotic masking
Optimal Coupling Patterns in Interconnected Communication Networks
Series-Parallel Charge Pump Conditioning Circuits for Electrostatic Kinetic Energy Harvesting
A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing
Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC