yusuke1997/dblp-id-title huggingface dataset:
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis
Why Are Memristor and Memistor Different Devices?
A 220-MS/s 9-Bit 2X Time-Interleaved SAR ADC With a 133-fF Input Capacitance and a FOM of 37 fJ/conv in 65-nm CMOS
Designs for Ultra-Tiny, Special-Purpose Nanoelectronic Circuits
Estimation of Magnitude of Self-Induced Oscillations via Piecewise Quadratic Lyapunov Functions
Inductance Model of Interdigitated Power and Ground Distribution Networks
A 2G/3G Cellular Analog Baseband Based on a Filtering ADC
Definition of Simplified Frequency-Domain Volterra Models With Quasi-Sinusoidal Input
Delay-Line-Based Analog-to-Digital Converters
A theory for deriving exactly solvable nonuniform transmission lines systematically
Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits
Improving the Back-Propagation Algorithm Using Evolutionary Strategy
A Scalable, Multimode SVD Precoding ASIC Based on the Cyclic Jacobi Method
A practical Δ-Σ modulator design method based on periodical behavior analysis
Pinning Controllability Analysis of Complex Networks With a Distributed Event-Triggered Mechanism
Efficient Successive Over Relaxation Detectors for Massive MIMO
Highly Digital Second-Order $\Delta\Sigma$ VCO ADC
Noise Estimation Using Mean Square Cross Prediction Error for Speech Enhancement
Minimization of Weighted Pole and Zero Sensitivity for State-Space Digital Filters
Tree-Permutation-Matrix Based LDPC Codes
A biomimetic VLSI sensor for visual tracking of small moving targets
A Semi-Supervised Learning Approach for Identification of Piecewise Affine Systems
Design of voltage-mode and current-mode computational circuits using floating-gate MOS transistors
Adaptive Regularization Matrix for Affine Projection Algorithm
Uniform approximation of periodically-varying systems
A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization
Auto-Scaling Overdrive Method Using Adaptive Charge Amplification for PRAM Write Performance Enhancement
A Family of Single-Switch PWM Converters With High Step-Up Conversion Ratio
Energy-Efficient Distributed Estimation by Utilizing a Nonlinear Amplifier
A Scalable Wavelet Transform VLSI Architecture for Real-Time Signal Processing in High-Density Intra-Cortical Implants
A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-μm CMOS Technology
A free but efficient low-voltage class-AB two-stage operational amplifier
Frequency-Domain Analysis of Effects of the Location of a Feedback Resistor in a Current Feedback Amplifier
Time-interleaved sigma-delta modulator using output prediction scheme
Externally Linear Discrete-Time Systems With Application to Instantaneously Companding Digital Signal Processors
Performing Stateful Logic on Memristor Memory
A high-speed low-complexity Reed-Solomon decoder for optical communications
A Jitter and Power Analysis on DCO
A Wideband dB-Linear VGA With Temperature Compensation and Active Load
Design and Analysis of Energy-Efficient Single-Pulse Piezoelectric Energy Harvester and Power Management IC for Battery-Free Wireless Remote Switch Applications
Analysis and Design of Loosely Inductive Coupled Wireless Power Transfer System Based on Class-E 2 DC-DC Converter for Efficiency Enhancement
A low-voltage, highly linear voltage-controlled transconductor
A New Class of Reconfigurable Microwave Bandpass Filters
A Third-Order Integrated Passive Switched-Capacitor Filter Obtained With a Continuous-Time Design Approach
Fractional-Order Sinusoidal Oscillators: Design Procedure and Practical Examples
A 30-MHz Fifth-Order Elliptic Low-Pass CMOS Filter With 65-dB Spurious-Free Dynamic Range
A Reduced Store/Restore Energy MRAM-Based SRAM Cell for a Non-Volatile Dynamically Reconfigurable FPGA
A Parallel Kernelized Data-Reusing Maximum Correntropy Algorithm
A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces
A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems
Design and Analysis of an Ultrahigh-Speed Glitch-Free Fully Differential Charge Pump With Minimum Output Current Variation and Accurate Matching
Distortion Analysis of RC Integrators With Wideband Input Signals
Radar and Communication Co-Existence Design Based on Mutual Information Optimization
An Ultra Low Power Integrated Radio TX Link Supplied From a Switched Capacitor DC-DC Converter in 65-nm CMOS Achieving 2 Mbps
A Sufficient Condition for Multiple Load Flow Solutions Existence in Three Phase Unbalanced Active Distribution Networks
Passive Loop Filter Assistance for CTSDMs
On the Minimum Supply Voltage for MOSFET Oscillators
A noise-shaped switching power supply using a delta-sigma modulator
Reflectionless Filters for Generalized Elliptic Transmission Functions
A 151-nW Adaptive Delta-Sampling ADC for Ultra-Low Power Sensing Applications
A Power Management System for Microbial Fuel Cells With 53.02% Peak End-to-End Efficiency
Integrated Low-Loss CMOS Active Rectifier for Wirelessly Powered Devices
ACRO-PUF: A Low-power, Reliable and Aging-Resilient Current Starved Inverter-Based Ring Oscillator Physical Unclonable Function
An Adaptive SOSM Controller Design by Using a Sliding-Mode-Based Filter and its Application to Buck Converter
Automated Segmentation of Drosophila RNAi Fluorescence Cellular Images Using Deformable Models
Novel Time-Domain Schottky Diode Modeling for Microwave Rectifier Designs
Exact Discrete-Time Implementation of the Mackey-Glass Delayed Model
Digital Noninverting-Buck-Boost Converter With Enhanced Duty-Cycle-Overlap Control
Bang-Bang Control Class D Amplifiers: Total Harmonic Distortion and Supply Noise
Wireless Voltage Regulation for Passive Transponders Using an IF to Communicate
A Feasibility Study on the Adoption of Human Body Communication for Medical Service
A Low-Noise CMOS Image Sensor With Digital Correlated Multiple Sampling
A CMOS Pixel With Embedded ADC, Digital CDS and Gain Correction Capability for Massively Parallel Imaging Array
Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems
Dynamic NBTI Management Using a 45 nm Multi-Degradation Sensor
A Simple Area-Efficient Ripple-Rejection Technique for Chopped Biosignal Amplifiers
Multi-Carrier Differential Chaos Shift Keying System With Subcarriers Allocation for Noise Reduction
Algorithmic Construction of Lyapunov Functions for Power System Stability Analysis
ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium
Low-Power State-Parallel Relaxed Adaptive Viterbi Decoder
CREMON: Cryptography Embedded on the Convolutional Neural Network Accelerator
Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters
Real-Time Digital Hardware Simulation of the Rodless Pneumatic System
Analysis and Design of Power Supply Circuits for RF Oscillators
Universal Principles for Ultra Low Power and Energy Efficient Design
Design of 2 × V DD -Tolerant I/O Buffer With PVT Compensation Realized by Only 1 × V DD Thin-Oxide Devices
Cauer Ladder Inspired Kron-Branin Modeling of Thermal 1-D Diffusion
A Bio-Inspired Analog Gas Sensing Front End
High-Efficiency Charge Pumps for Low-Power On-Chip Applications
Synchronization and Consensus in State-Dependent Networks
Linearizing CMOS Switching Power Amplifiers Using Supply Regulators
Modular log-domain filters realized using wave port terminators
A Hardware Approach to Real-Time Program Trace Compression for Embedded Processors
Energy Efficient Flash ADC With PVT Variability Compensation Through Advanced Body Biasing
Theoretical Upperbound of the Spurious-Free Dynamic Range in Direct Digital Frequency Synthesizers Realized by Polynomial Interpolation Methods
A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications
Efficient Arithmetic-Residue-Based SEU-Tolerant FIR Filter Design
New Asymptotic Stability Criteria for a Two-Neuron Network With Different Time Delays
Ultra-Low Voltage Split-Data-Aware Embedded SRAM for Mobile Video Applications
Optimizing Address Assignment and Scheduling for DSPs With Multiple Functional Units
Design and Implementation of a Wideband, Highly-Efficient, High-Power Amplifier Using Load-Pull and X-Parameters Models
Maximally flat delay Nyquist pulse design
High-Bandwidth Spatial Equalization for mmWave Massive MU-MIMO With Processing-in-Memory
Performance of differential chaos-shift-keying digital communication systems over a multipath fading channel with delay spread
A Frequency-Reconfigurable CMOS Active Phase Shifter for 5G mm-Wave Applications
A Wide Range, 4.2 ps(rms) Precision CMOS TDC With Cyclic Interpolators Based on Switched-Frequency Ring Oscillators
A Comprehensive Analysis of Quadrature Signal Synthesis in Cross-Coupled RF VCOs
Pi Coil: A New Element for Bandwidth Extension
Efficient Circuit for Parallel Bit Reversal
Low Leakage TCAM for IP Lookup Using Two-Side Self-Gating
Using Floating Gate and Quasi-Floating Gate Techniques for Rail-to-Rail Tunable CMOS Transconductor Design
A Family of Stateful Memristor Gates for Complete Cascading Logic
Performance Analysis and Optimization of Multi-User Differential Chaos-Shift Keying Communication Systems
Symmetric Structures for Odd-Order Maximally Flat and Weighted-Least-Squares Variable Fractional-Delay Filters
A general method to predict the amplitude of oscillation in nearly sinusoidal oscillators
Guest Editorial for Special Issue on High-Performance Multichip Interconnections
Logic-DRAM Co-Design to Exploit the Efficient Repair Technique for Stacked DRAM
50 Years of CORDIC: Algorithms, Architectures, and Applications
Design of Tunable Multi-Pole Multi-Zero Bandpass Filters and Diplexer With High Selectivity and Isolation
Asymptotic Disturbance Rejection of the Duffing's System by Adaptive Output Feedback Control
Global Synchronization of Discrete-Time Dynamical Network With a Directed Graph
UWB Echo Signal Detection With Ultra-Low Rate Sampling Based on Compressed Sensing
Efficient Successive-Cancellation Polar Decoder Based on Redundant LLR Representation
High-Efficiency Microwave Rectifier With Extended Operating Bandwidth
A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances
Chopper-Stabilized Low-Noise Multipath Operational Amplifier With Dual Ripple Rejection Loops
Gaming Temporal Networks
Subsampling Models of Bandwidth Mismatch for Time-Interleaved Converter Calibration
Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder
Six-Port Receiver Analog Front-End: Multilayer Design and System Simulation
Optimal Resource Allocation in Complex Communication Networks
A 0.35 V 376 Mb/s Configurable Long Integer Multiplier for Subthreshold Encryption
Continuous-Time Delta-Sigma Modulator Design Using the Method of Moments
Sparse Distributed Estimation via Heterogeneous Diffusion Adaptive Networks
Novel Dual-Band Matching Network for Effective Design of Concurrent Dual-Band Power Amplifiers
A Low Conduction Loss Modular Multilevel Converter Topology With DC Fault Blocking Capability and Reduced Capacitance
Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes
Implementation of Linear-Phase FIR Nearly Perfect Reconstruction Cosine-Modulated Filterbanks Utilizing the Coefficient Symmetry
Complementarity Model of a Photovoltaic Power Electronic System With Model Predictive Control
Automatic Charge Balancing Content Addressable Memory With Self-control Mechanism
On the Polyphase Decomposition for Design of Generalized Comb Decimation Filters
Higher Dimensional Baker Map and its Digital Implementation With LSB-Extension Method
A 4-GS/s Single Channel Reconfigurable Folding Flash ADC for Wireline Applications in 16-nm FinFET
High-DR CMOS Fluorescence Biosensor With Extended Counting ADC and Noise Cancellation
A 42-dB Ω 25-Gb/s CMOS Transimpedance Amplifier With Multiple-Peaking Scheme for Optical Communications
Digital RFI suppression in DMT-based VDSL systems
Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference
On Modeling of Parallel Repeater-Insertion Methodologies for SoC Interconnects
A Slide Window Variational Adaptive Kalman Filter
SC amplifier and SC integrator with an accurate gain of 2
Parallel Continuous-Time DeltaSigma ADC for OFDM UWB Receivers
A Highly Digital ADC With Enhanced Accuracy Using a Simple Ripple-Transferring Replica Pseudo PLL Technique
A Wide Tuning Range G m - C Continuous-Time Analog Filter
Adaptive Stabilization and Synchronization for Chaotic Lur'e Systems With Time-Varying Delay
Advances in Reversed Nested Miller Compensation
Improved Robust Stability Criteria for Delayed Cellular Neural Networks via the LMI Approach
Vulnerability Assessment of Power Grids Against Link-Based Attacks
A 13.56 MHz Current-Mode Wireless Power Receiver With Energy-Investment Capability
An Improved Mode Transition Technique for a Non-Isolated Bidirectional DC-DC Converter
A Compact Architecture for Simulation of Spatio-Temporally Correlated MIMO Fading Channels
Scalable Digital Power Controller With Phase Alignment and Frequency Synchronization
A 10 Bit 5 MS/s Column SAR ADC With Digital Error Correction for CMOS Image Sensors
Global Frequency Synchronization of Complex Power Networks Via Coordinating Switching Control
(1/3) times hboxVDD-to- (3/2) times hboxVDD Wide-Range I/O Buffer Using 0.35- muhboxm 3.3-V CMOS Technology
A 3.0 Gb/s Throughput Hardware-Efficient Decoder for Cyclically-Coupled QC-LDPC Codes
Settling Time and Noise Optimization of a Three-Stage Operational Transconductance Amplifier
Recursive Binary Neural Network Training Model for Efficient Usage of On-Chip Memory
Feedforward-Regulated Cascode OTA for Gigahertz Applications
A Low-Power High-Precision Comparator With Time-Domain Bulk-Tuned Offset Cancellation
Power-Gating Noise Minimization by Three-Step Wake-Up Partitioning
Impulse response of sinc N FIR filters
A 0.18-µm CMOS 10-Gb/s Dual-Mode 10-PAM Serial Link Transceiver
Radar Emitter Recognition Based on SIFT Position and Scale Features
Reliability and Energy Efficiency of the Tunneling Transistor-Based 6T SRAM Cell in Sub-10 nm Domain
Interleaved Converters Based on Sliding-Mode Control in a Ring Configuration
Dynamical Properties and Design Analysis for Nonvolatile Memristor Memories
Skew symmetry and orthogonality in the equivalent representation problem of a time-varying multiport inductor
10-Gb/s Inductorless CDRs With Digital Frequency Calibration
Robust Exponential Stability of Recurrent Neural Networks With Multiple Time-Varying Delays
An Analog Gabor Transform Using Sub-Threshold 180-nm CMOS Devices
Fixed-Width Multipliers and Multipliers-Accumulators With Min-Max Approximation Error
Asymmetric cross-coupled differential pair configuration to realize neuron activation function and its derivative
UWB in Millimeter Wave Band With Pulsed ILO
Synchronization in Several Types of Coupled Polygonal Oscillatory Networks
Variable Latency Speculative Parallel Prefix Adders for Unsigned and Signed Operands
Chaos Suppression in Forced Chaotic Systems by Innovative Sliding Mode Control
Quantization Noise Power Estimation for Floating-Point DSP Circuits
Design of a Low Voltage-Low Power 3.1-10.6 GHz UWB RF Front-End in a CMOS 65 nm Technology
ASNI: Attenuated Signature Noise Injection for Low-Overhead Power Side-Channel Attack Immunity
Reaction-diffusion navigation robot control: from chemical to VLSI analogic processors
Impact of random channel mismatch on the SNR and SFDR of time-interleaved ADCs
Highly Efficient RF Transmitter Over Broad Average Power Range Using Multilevel Envelope-Tracking Power Amplifier
Wide-Bandwidth, High-Linearity, 2.8-GS/s, 10-bit Accurate Sample and Hold Amplifier in 130-nm SiGe BiCMOS
Unipolar Differential Logic for Large-Scale Integration of Flexible aIGZO Circuits
A Sub-Microwatt Class-AB Super Buffer: Frequency Compensation for Settling-Time Improvement
A High-Voltage UWB Pulse Generator Using Passive Amplification in 65-nm CMOS
Alternative Time-Invariant Multi-Frequency Modeling of PWM DC-DC Converters
A Low-Cost Low-Power Ring Oscillator-Based Truly Random Number Generator for Encryption on Smart Cards
A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS
A Residue-to-Binary Converter for a New Five-Moduli Set
Passive and Active Electrical Balance Duplexers
A near-infrared heart rate measurement IC with very low cutoff frequency using current steering technique
A Differential Two-Pin Crystal Oscillator - Concept, Analysis, and Implementation
Reconfigurable FPGA-Based K-Means/K-Modes Architecture for Network Intrusion Detection
A 1-V-0.6-V 9-b 1.5-MS/s Reference-Free Charge-Sharing SAR ADC for Wireless-Powered Implantable Telemetry
Masked Dithering of MASH Digital Delta-Sigma Modulators with Constant Inputs Using Linear Feedback Shift Registers
Fractional-N Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial
Four-Wire Interface ASIC for a Multi-Implant Link
Integrated ExG, Vibration and Temperature Measurement Front-End for Wearable Sensing
A Low-Cost, Low-Complexity, and Memory-Free Architecture of Novel Recursive DFT and IDFT Algorithms for DTMF Application
New Strategies in Removing Noncoherency From Signals With Large Distortion-to-Noise Ratios
A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture
A 14 b 23 MS/s 48 mW Resetting Sigma Delta ADC
Time-Based Sensing for Reference-Less and Robust Read in STT-MRAM Memories
A New Power Gating Circuit Design Approach Using Double-Gate FDSOI
Optimization Techniques for the Efficient Implementation of High-Rate Layered QC-LDPC Decoders
System-level test and yield improvement for optoelectronic-VLSI chips
A Resistorless Low-Power Voltage Reference
A 5.4 µW Soft-Decision BCH Decoder for Wireless Body Area Networks
Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory
Low-Voltage Bulk-Driven Operational Amplifier With Improved Transconductance
A Note on PIN Polynomials and PRIN Rational Functions
Bias-Compensated Sparsity-Aware NLMM Algorithms for Robust Adaptive Echo Cancellation
A simplified normal optical flow measurement CMOS camera
Maximum Power Point Tracking Employing Sliding Mode Control
A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth
A Tree-Topology Multiplexer for Multiphase Clock System
A Wideband Flat Gain Low Noise Amplifier Using Active Inductor for Input Matching
Implant Position Estimation Via Wireless Power Link
A Spectral Model for RF Oscillators With Power-Law Phase Noise
Guest Editorial Selected Papers From Regional Flagship Conferences of the IEEE Circuits and Systems Society (ICECS 2017, LASCAS 2018, and NEWCAS 2018)
Periodic Oscillations in Weakly Connected Cellular Nonlinear Networks
On Aging-Aware Signoff for Circuits With Adaptive Voltage Scaling
Time-Interleaved ΣΔ Modulators for FPGAs
All-Digital Time-Mode Direct-Form All-Pole Biquadratic Filter Realization
Generalized Method for Extraction of Offset, Gain, and Timing Skew Errors in Time-Interleaved ADCs
Temperature Compensation of Crystal References in NB-IoT Modems
A Reconfigurable Mixed-Signal VLSI Implementation of Distributed Arithmetic Used for Finite-Impulse Response Filtering
Corrections to "A Design of Input-Decimation Technique for Recursive DFT/IDFT Algorithm"
A Novel MTJ-Based Non-Volatile Ternary Content-Addressable Memory for High-Speed, Low-Power, and High-Reliable Search Operation
A 58-ppm/°C 40-nW BGR at Supply From 0.5 V for Energy Harvesting IoT Devices
An Efficient Scheme for Nonlinear Modeling and Predistortion in Mixed-Signal Systems
Statistical analysis of second-order intermodulation distortion in WCDMA direct conversion receivers
A Single-Stage Dual-Output Tri-Mode AC-DC Regulator for Inductively Powered Application
A Picosecond-Resolution Digitally-Controlled Timing Generator With One-Clock-Latency at Arbitrary Instantaneous Input
Achieving Ultralow Standby Power With an Efficient SCCMOS Bias Generator
A Complete Analytical Solution for the On and Off Dynamic Equations of a TaO Memristor
Capacitive Touch Panel With Low Sensitivity to Water Drop Employing Mutual-Coupling Electrical Field Shaping Technique
An Optimal Filter for Singular Systems With Stochastic Multiplicative Disturbance
Fault Estimation for Discrete-Time Systems With Lipschitz Perturbation and Time-Variant Coefficients
Frequency-Adaptive Network Modeling for Integrative Simulation of Natural and Envelope Waveforms in Power Systems and Circuits
Driven interval shift dynamics in sigma-delta modulators and phase-locked loops
A Low-Complexity Three-Error-Correcting BCH Decoder for Optical Transport Network
A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry
A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains
Design and Characterization of a 43.2-ps and PVT-Resilient TDC for Single-Photon Imaging Arrays
A Simple Third-Order Memristive Band Pass Filter Chaotic Circuit
Imbalance-Based Self-Test for High-Speed Mixed-Signal Embedded Systems
Analysis and Design of an Efficient Irreversible Energy Recovery Logic in 0.18-mum CMOS
A Method for the Schmitt-Trigger Propagation-Delay Compensation in Asynchronous Sigma-Delta Modulator
Identifying and Characterizing Non-Convexities in Feasible Spaces of Optimal Power Flow Problems
A 2.4-GHz Ternary Sequence Spread Spectrum OOK Transceiver for Reliable and Ultra-Low Power Sensor Network Applications
An Adaptive QR Decomposition Processor for Carrier-Aggregated LTE-A in 28-nm FD-SOI
Distributed Observer-Based Cyber-Security Control of Complex Dynamical Networks
A Reconfigurable Transient Optimizer Applied to a Four-Phase Buck Converter for Optimizing Both DVS and Load Transient Responses
An Efficient Folded Architecture for Lifting-Based Discrete Wavelet Transform
Generalized High Step-Up DC-DC Boost-Based Converter With Gain Cell
Synthesis of programmable multi-input current-mode linear analog circuits
Design and Performance Analysis of a Unified, Reconfigurable HMAC-Hash Unit
Area- and Power-Efficient Design of Daubechies Wavelet Transforms Using Folded AIQ Mapping
Recursive Filters for Time-Interleaved ADC Mismatch Compensation
A Wideband Frequency Divider With Programmable Odd/Even Division Factors and Quadrature/Symmetrical Outputs
On the design of high-performance wide-band continuous-time sigma-delta converters using numerical optimization
Time-Controlled and FinFET Compatible Sub-Bandgap References Using Bulk-Diodes
SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis
Cluster Tracking Performance Analysis of Linear Heterogeneous Multi-Agent Networks: A Complex Frequency Domain Approach
An Algorithm for Determining the Output Frequency Range of Volterra Models With Multiple Inputs
Temporal G-Neighbor Filtering for Analog Domain Noise Reduction in Astronomical Videos
K-Band SiGe System-on-Chip Radiometric Receiver for Remote Sensing of the Atmosphere
A 19-nW 0.7-V CMOS Voltage Reference With No Amplifiers and No Clock Circuits
A Deep Learning Method for Improving the Classification Accuracy of SSMVEP-Based BCI
A Fast Response PWM Buck Converter With Active Ramp Tracking Control in a Load Transient Period
Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication
High-Speed and Hardware-Efficient Successive Cancellation Polar-Decoder
Editorial A Time for Balance
Comments on "Improved Sufficient Conditions for Global Asymptotic Stability of Delayed Neural Networks"
Input Referred Comparator Noise in SAR ADCs
Design of a Tunable Differential Ring Oscillator With Short Start-Up and Switching Transients
A Dynamic Timing Error Prevention Technique in Pipelines With Time Borrowing and Clock Stretching
A Monolithic High-Voltage Li-Ion Battery Charger With Sharp Mode Transition and Partial Current Control Technique
Unified Systolic-Like Architecture for DCT and DST Using Distributed Arithmetic
Synchronization of Partial Differential Systems via Diffusion Coupling