yusuke1997/dblp-id-title huggingface dataset:
M2A2: Microscale Modular Assembled ASICs for High-Mix, Low-Volume, Heterogeneously Integrated Designs
EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition
An ILD Void Detection Method for Monolithic 3-D ICs Based on Switched Capacitors
Accurate Substrate Analysis Based on a Novel Finite Difference Method via Synchronization Method on Layered and Adaptive Meshing
Algorithms for the transient simulation of lossy interconnect
Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out
Accelerated Harmonic-Balance Analysis Using a Graphical Processing Unit Platform
ML-Based Thermal and Cache Contention Alleviation on Clustered Manycores With 3-D HBM
RESI: Register-Embedded Self-Immunity for Reliability Enhancement
Multiobjective Optimization for PSIJ Mitigation and Impedance Improvement Based on PCPS/DR-NSDE in Chiplet-Based 2.5-D Systems
A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture
Hardware-Level Thread Migration to Reduce On-Chip Data Movement Via Reinforcement Learning
NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs
A QEMU and SystemC-Based Cycle-Accurate ISS for Performance Estimation on SoC Development
Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method
Defect level evaluation in an IC design environment
Algorithm selection: a quantitative optimization-intensive approach
Counter-Based Output Selection for Test Response Compaction
PVSensing: A Process-Variation-Aware Space Allocation Strategy for 3D NAND Flash Memory
Symbolic model checking for sequential circuit verification
SiSMA-a tool for efficient analysis of analog CMOS integrated circuits affected by device mismatch
Optimal diagnostic methods for wiring interconnects
Oct-tree-based multilevel low-rank decomposition algorithm for rapid 3-D parasitic extraction
Optimal Chaining of CMOS Transistors in a Functional Cell
Formal Verification of Arithmetic Circuits by Function Extraction
Improving I/O Performance and Fairness in NVMe SSDs With Pooling Portions of Cache Partitions
Litho-Aware Machine Learning for Hotspot Detection
A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits
Ratio cut partitioning for hierarchical designs
Logic simulation with current-limited switches
Numerical integration using Bezier splines
3-D Thermal-ADI: a linear-time chip level transient thermal simulator
Multiple fault detection using single fault test sets
Highly Parallel CNN Accelerator for RepVGG-Like Network Training on FPGAs
Analysis and compact behavioral modeling of nonlinear distortion in analog communication circuits
A fast, general three-dimensional device simulator and its application in a submicron EPROM design study
Behavior and testability preservation under the retiming transformation
Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence
A Logic Circuit Design for Perfecting Memristor-Based Material Implication
A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs
The complexity of segmented channel routing
A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization
Testability analysis and test-point insertion in RTL VHDL specifications for scan-based BIST
A-Cache: Asymmetric Buffer Cache for RAID-10 Systems Under a Single-Disk Failure to Significantly Boost Availability
An Efficient Transient Electro-Thermal Simulation Framework for Power Integrated Circuits
On O(p 2 ) algorithms for planarization
Optimal aspect ratios of building blocks in VLSI
Exact Synthesis of Majority-Inverter Graphs and Its Applications
PMTP: A MAX-SAT-Based Approach to Detect Hardware Trojan Using Propagation of Maximum Transition Probability
Autonomous Application of Netlist Transformations Inside Lagrangian Relaxation-Based Optimization
Analysis of Breakdown Phenomena in MOSFET's
A Novel Fully Synthesizable All-Digital RF Transmitter for IoT Applications
Resource Optimization for Real-Time Streaming Applications Using Task Replication
Managing Fleets of LEO Satellites: Nonlinear, Optimal, Efficient, Scalable, Usable, and Robust
Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis
Frequency Scaling As a Security Threat on Multicore Systems
Ferroelectric Ternary Content Addressable Memories for Energy-Efficient Associative Search
Statistical threshold formulation for dynamic I dd test
A density-based greedy router
Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search
Test-Delivery Optimization in Manycore SOCs
GPU-Accelerated Adaptive PCBSO Mode-Based Hybrid RLA for Sparse LU Factorization in Circuit Simulation
Parallel Combinational Equivalence Checking
Topology Synthesis of Cascaded Crossbar Switches
Improved Tangent Space-Based Distance Metric for Lithographic Hotspot Classification
Multivariate Modeling of Variability Supporting Non-Gaussian and Correlated Parameters
Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations
CoFS: A Collaboration-Aware Fairness Scheme for NVMe SSD in Cloud Storage System
Levelized High-Level Current Model of Logic Blocks for Dynamic Supply Noise Analysis
Digital-Based Solution for the Generation of FM/PM Test Stimuli
Asymptotic Probability Extraction for Nonnormal Performance Distributions
Charge-based fault simulation for CMOS network breaks
Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering
Approximate Computing for Long Short Term Memory (LSTM) Neural Networks
An algorithmic technique for diagnosis of faulty scan chains
New spectral methods for ratio cut partitioning and clustering
Thermoelectric Cooler Modeling and Optimization via Surrogate Modeling Using Implicit Physics-Constrained Neural Networks
Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model
Partitioned Scheduling With Shared Resources on Imprecise Mixed-Criticality Multiprocessor Systems
System-Level Design Space Exploration Methodology for Energy-Efficient Sensor Node Configurations: An Experimental Validation
DR-Scan: Dual-Rail Asynchronous Scan DfT and ATPG
Fuzzing+Hardware Performance Counters-Based Detection of Algorithm Subversion Attacks on Postquantum Signature Schemes
Delaying Crash Consistency for Building A High-Performance Persistent Memory File System
SaPOSM: an optimization method applied to parameter extraction of MOSFET models
Improved Perturbation Vector Generation Method for Accurate SRAM Yield Estimation
High-Quality Statistical Test Compression With Narrow ATE Interface
Pipette: Efficient Fine-Grained Reads for SSDs
Speeding Up Functional Timing Analysis by Concise Formulation of Timed Characteristic Functions
A Novel Moment Based Framework for Accurate and Efficient Static Timing Analysis
LLSM: A Lifetime-Aware Wear-Leveling for LSM-Tree on NAND Flash Memory
Formal verification of digital systems by automatic reduction of data paths
LOOPLock: Logic Optimization-Based Cyclic Logic Locking
A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC
Highly Efficient Test Response Compaction Using a Hierarchical X-Masking Technique
Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods
The Robust QCA Adder Designs Using Composable QCA Building Blocks
EASE - An Application-Based CAD System for Process Design
Efficient Identification of Critical Faults in Memristor-Based Inferencing Accelerators
A Metric for Test Set Characterization and Customization Toward Fault Diagnosis
Tinker: A Middleware for Deploying Multiple NN-Based Applications on a Single Machine
Finite State Machines With Input Multiplexing: A Performance Study
Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms
On the nonenumerative path delay fault simulation problem
Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption
Co-Scheduling on Fused CPU-GPU Architectures With Shared Last Level Caches
A Directed Test Generator for Shared-Memory Verification of Multicore Chip Designs
HSS--A High-Speed Simulator
Vesper: A Versatile Sparse Linear Algebra Accelerator With Configurable Compute Patterns
Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques
Phantom redundancy: a register transfer level technique for gracefully degradable data path synthesis
Estimation of signal transition activity in FIR filters implementedby a MAC architecture
Safety Verification for Random Ordinary Differential Equations
Statistical Timing Analysis With Coupling
INTEGRA: Fast Multibit Flip-Flop Clustering for Clock Power Saving
Performance analysis of embedded software using implicit path enumeration
An efficient coefficient-partitioning algorithm for realizing low-complexity digital filters
SCANN: Synthesis of Compact and Accurate Neural Networks
BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP
Statistical degradation analysis of digital CMOS IC's
Reduction of Variation-Induced Energy Overhead in Multi-Core Processors
Hierarchical Relational Graph Learning for Autonomous Multirobot Cooperative Navigation in Dynamic Environments
A Coordinated Model Pruning and Mapping Framework for RRAM-Based DNN Accelerators
A Multistep Tag Comparison Method for a Low-Power L2 Cache
Non-Gaussian Statistical Timing Analysis Using Second-Order Polynomial Fitting
An Expert CAD Flow for Incremental Functional Diagnosis of Complex Electronic Boards
HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery
Full-wave analysis of high-speed interconnects using complex frequency hopping
Efficient Timing Analysis With Known False Paths Using Biclique Covering
Single-fault fault-collapsing analysis in sequential logic circuits
Non-Stationary Traffic Analysis and Its Implications on Multicore Platform Design
Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test
Optimizing power using transformations
Charge Allocation in Hybrid Electrical Energy Storage Systems
A Taxonomy of Modern GPGPU Programming Methods: On the Benefits of a Unified Specification
Warp-Aware Adaptive Energy Efficiency Calibration for Multi-GPU Systems
Defect Modeling Using Fault Tuples
Wolfgang Rosenstiel
Static Test Compaction for Functional Test Sequences With Restoration of Functional Switching Activity
CacheEM: For Reliability Analysis on Cache Memory Aging Due to Electromigration
Asynchronous Reinforcement Learning Framework and Knowledge Transfer for Net-Order Exploration in Detailed Routing
Worst case tolerance analysis and CLP-based multifrequency test generation for analog circuits
On the ZBDD-based nonenumerative path delay fault coverage calculation
Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid and Its Applications to VLSI Design
2-D simulation of degenerate hot electron transport in MODFETs including DX center trapping
Optimal Test Margin Computation for At-Speed Structural Test
Secure Power Grid Simulation on Cloud
A First Study of Compressive Sensing for Side-Channel Leakage Sampling
Strong fault-secure and strongly self-checking domino-CMOS implementations of totally self-checking circuits
Practical Attacks on Deep Neural Networks by Memory Trojaning
On improving test quality of scan-based BIST
RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm
A Heuristic Algorithm for Gate Assignment in One-Dimensional Array Approach
A Parallel Solution Method for Large Sparse Systems of Equations
Delay-Time Modeling for ED MOS Logic LSI
A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures
Minimizing total power by simultaneous V dd /V th assignment
AIL-DNN: Modeling of IC Interconnect Parasitic Capacitances Based on Adaptive Incremental Learning
Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill
Efficient physical timing models for CMOS AND-OR-inverter and OR-AND-inverter gates and their applications
An algorithm for identifying and selecting the primed implicants of a multiple-output Boolean function
Transient Simulation of Silicon Devices and Circuits
Detecting Spoofed Noisy Speeches via Activation-Based Residual Blocks for Embedded Systems
CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation
Hinted quad trees for VLSI geometry DRC based on efficient searching for neighbors
Automatic synthesis of low-power gated-clock finite-state machines
iCache: An Intelligent Cache Allocation Strategy for Multitenant in High-Performance Solid-State Disks
Integrated circuit quality optimization using surface integrals
Simple model of metal oxide varistor for Pspice Simulation
Architectural level test generation for microprocessors
VHDL semantics and validating transformations
A hardware logic simulation system
Microprocessor Optimizations for the Internet of Things: A Survey
Analytical Modeling and Characterization of Electromigration Effects for Multibranch Interconnect Trees
Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors
A Technique for Test Coverage Closure Using GoldMine
An SDRAM-Aware Router for Networks-on-Chip
Deep Reinforcement-Learning-Guided Backup for Energy Harvesting Powered Systems
Additive Statistical Leakage Analysis Using Exponential Mixture Model
DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test
On Probability of Detection Lossless Concurrent Error Detection Based on Implications
Translation Validation of Code Motion Transformations Involving Loops
FLAM-PUF: A Response-Feedback-Based Lightweight Anti-Machine-Learning-Attack PUF
Methods to improve digital MOS macromodel accuracy
Accurate Recycled FPGA Detection Using an Exhaustive-Fingerprinting Technique Assisted by WID Process Variation Modeling
Keynote Paper: From EDA to IoT eHealth: Promises, Challenges, and Solutions
A Metric for Automatic Word-Length Determination of Hardware Datapaths
Isolation Techniques for Soft Cores
GPU Performance Optimization via Intergroup Cache Cooperation
Timing analysis for piecewise linear Rsim
Eliminating redundant DC equations for asymptotic waveform evaluation
Energy and Peak Power Efficiency Analysis for the Single Voltage Approximation (SVA) Scheme
On exponential fitting for circuit simulation
On routing two-terminal nets in the presence of obstacles
Equivalence checking of arithmetic circuits on the arithmetic bit level
Post-layout timing simulation of CMOS circuits
ARTEMIS: A Mixed Analog-Stochastic In-DRAM Accelerator for Transformer Neural Networks
3-D numerical modeling of thermal flow for insulating thin film using surface diffusion
Exact Interference of Tasks With Variable Rate-Dependent Behavior
Joint Modulo Scheduling and V dd Assignment for Loop Mapping on Dual- V dd CGRAs
Pad Assignment for Die-Stacking System-in-Package Design
SimPL: An Effective Placement Algorithm
Parmesan: Efficient Partitioning and Mapping Flow for DNN Training on General Device Topology
OBDD-based function decomposition: algorithms and implementation
A fault model for PLAs
Generic linear RC delay modeling for digital CMOS circuits
Topological Heuristics for Scan Test Overhead Reduction
Location-and-Preference Joint Prediction for Task Assignment in Spatial Crowdsourcing
Block placement with a Boltzmann Machine
Analyzing Data Cache Related Preemption Delay With Multiple Preemptions
Computer Generation of Digital Filter Banks
Layout Decomposition for Triple Patterning Lithography
SCALP: an iterative-improvement-based low-power data path synthesis system
DIALOG: An Expert Debugging System for MOSVLSI Design
On the reconfiguration of degradable VLSI/WSI arrays
MVP: Minimum-Violations Partitioning for Reducing Capture Power in At-Speed Delay-Fault Testing
Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers
A Statistical Design Rule Developer
Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis
A Hardware Maze Router with Application to Interactive Rip-Up and Reroute
Modular testprocessor for VLSI chips and high-density PC boards
PowerHerd: a distributed scheme for dynamically satisfying peak-power constraints in interconnection networks
Topology Synthesis for Low Power Cascaded Crossbar Switches
Channel Length Dependence of the Body-Factor Effect in NMOS Devices
A Deep Investigation on Stealthy DVFS Fault Injection Attacks at DNN Hardware Accelerators
Deterministic Stellar BIST for Automotive ICs
Exploiting Parallelism for Access Conflict Minimization in Flash-Based Solid State Drives
Comparing Different Variants of the ic3 Algorithm for Hardware Model Checking
COCO: Configuration-Based Compaction of a Compressed Topped-Off Test Set
Synthesis of TSV Fault-Tolerant 3-D Clock Trees
Modeling and Analysis of Magnetic Field Induced Coupling on Embedded STT-MRAM Arrays
Lithography Hotspot Detection Based on Heterogeneous Federated Learning With Local Adaptation and Feature Selection
Knowledge Transfer in Board-Level Functional Fault Diagnosis Enabled by Domain Adaptation
E-Beam Lithography Character and Stencil Co-Optimization
A space-efficient short-finding algorithm [VLSI layouts]
An Adaptive Graph Sparsification Approach to Scalable Harmonic Balance Analysis of Strongly Nonlinear Post-Layout RF Circuits
The spectral grid method: a novel fast Schrodinger-equation solver for semiconductor nanodevice simulation
Floorplanning With I/O Assignment via Feasibility-Seeking and Superiorization Methods
Formal verification of sequential hardware: a tutorial
A universal test set for CMOS circuits
ESTA: an expert system for DFT rule verification
Anisotropic Mesh Refinement for the Simulation of Three-Dimensional Semiconductor Manufacturing Processes
HyPE: hybrid power estimation for IP-based systems-on-chip
Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy
Test generation and optimization for DRAM cell defects using electrical simulation
${\rm SPICE}^2$: Spatial Processors Interconnected for Concurrent Execution for Accelerating the SPICE Circuit Simulator Using an FPGA
Highly Efficient Gradient Computation for Density-Constrained Analytical Placement
Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs
Koios 2.0: Open-Source Deep Learning Benchmarks for FPGA Architecture and CAD Research
An efficient and optimal algorithm for simultaneous buffer and wire sizing
A state-space behavioral model for CMOS class E power amplifiers
DDtM: Increasing Latent Defect Detection in Analog/Mixed-Signal ICs Using the Difference in Distance to Mean Value
Post global routing crosstalk synthesis
Automated Range and Precision Bit-Width Allocation for Iterative Computations
SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks
Transport effects and characteristic modes in the modeling and simulation of submicron devices
Automatic Design Space Exploration of Register Bypasses in Embedded Processors
Designing electronic engines with electronic engines: 40 years ofbootstrapping of a technology upon itself
On diagnosis and diagnostic test generation for pattern-dependenttransition faults
UI-Timer 1.0: An Ultrafast Path-Based Timing Analysis Algorithm for CPPR
Automatic synthesis of extended burst-mode circuits. II. (Automaticsynthesis)
Timing and Resource-Aware Mapping of Quantum Circuits to Superconducting Processors
Gateways: a technique for adding event-driven behavior to compiled simulations
TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders
Formal Analysis of Galois Field Arithmetic Circuits-Parallel Verification and Reverse Engineering
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop
Buffer insertion for noise and delay optimization
Adaptive Switch on Wear Leveling for Enhancing I/O Latency and Lifetime of High-Density SSDs
Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree
Conflict-free channel definition in building-block layout
Boolean division and factorization using binary decision diagrams
sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing
Affinity-Driven Modeling and Scheduling for Makespan Optimization in Heterogeneous Multiprocessor Systems
Simultaneous signature and syndrome compression
An analytical delay model for RLC interconnects
Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis
On the Saturation of n-Detection Test Generation by Different Definitions With Increased n
The CDB/HCDB semiconductor wafer representation server
FIRM-Tree: A Multidimensional Index Structure for Reprogrammable Flash Memory
Optimal realizations of floorplans [VLSI layout]
A Layered Methodology for the Simulation of Extra-Functional Properties in Smart Systems
Evaluating Neural Network-Inspired Analog-to-Digital Conversion With Low-Precision RRAM
Priority Neuron: A Resource-Aware Neural Network for Cyber-Physical Systems
SANA-FE: Simulating Advanced Neuromorphic Architectures for Fast Exploration
Dynamic-range estimation
Reliable PUF-Based Local Authentication With Self-Correction
Efficient Identification of Undetectable Two-Cycle Gate-Exhaustive Faults
Sequential circuit ATPG using combinational algorithms
ICMarks: A Robust Watermarking Framework for Integrated Circuit Physical Design IP Protection
An Efficient BCNN Deployment Method Using Quality-Aware Approximate Computing
LSTM-Characterized Approach for Chip Floorplanning: Leveraging HyperGCN and DRQN
New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement
Modeling the "Effective capacitance" for the RC interconnect of CMOS gates
Designing Efficient DNNs via Hardware-Aware Neural Architecture Search and Beyond
EigenCircuit: Divergent Synthetic Benchmark Generation for Hardware Security Using PCA and Linear Programming
Considering Crosstalk Effects in Statistical Timing Analysis
Energy-Efficient Application Mapping and Scheduling for Lifetime Guaranteed MPSoCs
Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology
High Frequency Meminductor Emulator Employing VDTA and its Application
Implementing Neural Networks on Nonvolatile FPGAs With Reprogramming
UTACO: a unified timing and congestion optimization algorithm for standard cell global routing
Silicon compilation of very high level language
Improved gate matrix layout
Optimizing Polynomial Expressions by Algebraic Factorization and Common Subexpression Elimination
Switching network logic approach to sequential MOS circuit design
Improving 3-D NAND SSD Read Performance by Parallelizing Read-Retry
Low-Power Scan Operation in Test Compression Environment
GAMER: GPU-Accelerated Maze Routing
Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing
Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits
Predicated switching - optimizing speculation on EPIC machines
Broad-side delay test
PRESERVE: Static Test Compaction that Preserves Individual Numbers of Tests
Improving the Forward Progress of Transient Systems
March DSS: A New Diagnostic March Test for All Memory Simple Static Faults
Enhanced Design Debugging With Assistance From Guidance-Based Model Checking
Board-Level Functional Fault Diagnosis Using Multikernel Support Vector Machines and Incremental Learning
Estimation of peak power dissipation in VLSI circuits using thelimiting distributions of extreme order statistics
PHAX: Physical Characteristics Aware Ex-Situ Training Framework for Inverter-Based Memristive Neuromorphic Circuits
Scalable Detection of Hardware Trojans Using ATPG-Based Activation of Rare Events
Improving the observability and controllability of datapaths foremulation-based debugging
Routability-driven white space allocation for fixed-die standard-cell placement