yusuke1997/dblp-id-title huggingface dataset:
Simulation-based development of Peer-to-Peer systems with the RealPeer methodology and framework
Parallel programmable architectures and compilation for multi-dimensional processing
LINDA: An allocator for embedded multiprocessor systems
Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures
Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems
A survey of optimization techniques for thermal-aware 3D processors
An environment for concurrent programming in Pascal
CEIU: Consistent and Efficient Incremental Update mechanism for mobile systems on flash storage
SHREG: Mitigating register redundancy in GPUs
Synthesis for testability by synthesis controlling
Component-based architectural regression test selection for modularized software systems
On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation
Optimizing both performance and tail latency for B+tree on persistent memory
Computing the generalized eigenvalues of symmetric positive definite pencils on networks of transputers
Randomized execution algorithms for smart cards to resist power analysis attacks
Special Issue on High Performance Computing, Communication and Embedded Software/Systems
Impact of high speed network on performance of real-time concurrency control protocol
A microprocessor based parallel search system for fast data retrieval
An improved signature analysis based CPU self test
An efficient heuristic algorithm for mapping parallel programs onto multicomputers
Multi-protocol communications controller
IP Routing table compaction and sampling schemes to enhance TCAM cache performance
Emulation of a parallel codeblock dataflow processor
SPECS: Formal methods and techniques for telecommunications software development
Architectures and optimization methods of flash memory based storage systems
A comprehensive survey of digital twins: Applications, technologies and security challenges
Session F2: Interconnection networks for multiprocessors
Efficient multicast schemes for 3-D Networks-on-Chip
The multi-associative branch target buffer: a cost effective BTB mechanism
CPU frequency scheduling of real-time applications on embedded devices with temporal encoding-based deep reinforcement learning
Expansion of LOTOS behaviour expressions as an exercise in transformational design
Fault tolerant wormhole routing in hypercube multicomputers
Machine learning-based computation offloading in multi-access edge computing: A survey
Towards an energy-efficient quarter-clairvoyant mixed-criticality system
Memory access schedule minimization for embedded systems
Palisade: A framework for anomaly detection in embedded systems
Resource management for multimedia applications, distributed in open and heterogeneous home networks
A VLSI 'rest' processing element with improved bus connections (an evaluation)
A comparison of two policies for issuing instructions speculatively
Conversations with fixed and potential participants
A flexible architecture for image processing
Prospects of distributed shared memory for reducing global traffic in shared-bus multiprocessors
A thermal-aware scheduling for multicore architectures
Encapsulation constructs in prolog
Mitigating write amplification issue of SMR drives via the design of sequential-write-constrained cache
Image coding using vector quantization of wavelet coefficients
Realization of wireless multimedia communication systems on reconfigurable platforms
A microcomputer database design
Throttle and preempt: A flow control policy for real-time traffic in wormhole networks
An abstract prolog machine based on parallel resolution principle
An energy-efficient cache replacement policy for ultra-dense racetrack memory
Evaluation of the dependability of an artificial DNA in a dynamic automotive environment
Short notes II
Session H1: Fault tolerance
HOSVD prototype based on modular SW libraries running on a high-performance CPU+GPU platform
Speech synthesis system with unlimited vocabulary for the Dutch language
The video-ram multiprocessor architecture
An optimized architecture for a rapid-prototype-emulator
Resource conflict detection in simulation of function unit pipelines
Evaluating the Cost of conditional branches on the performance of superscalar machines
An efficient string solver for string constraints with regex-counting and string-length
A review of 6G autonomous intelligent transportation systems: Mechanisms, applications and challenges
A resource-efficient network interface supporting low latency reconfiguration of virtual circuits in time-division multiplexing networks-on-chip
Realization of multilayer Boolean neural networks with logic gate array
A MAC protocol for reliable communication in low power body area networks
Micro-instruction placement by simulated annealing
Scheduling analysis of tasks constrained by TDMA: Application to software radio protocols
SPL - A different high level language for systolic processors
Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions
An integrated hardware/software design methodology for signal processing systems
Massively parallel systems
Component-oriented verification of noninterference
A knowledge-based framework for VLSI design
GNN-based deep reinforcement learning for computation task scheduling in autonomous multi-robot systems
An efficient attribute-based online/offline searchable encryption and its application in cloud-based reliable smart grid
A cost-effective methodology for the evaluation of interconnection networks
Information-driven circuit synthesis with the pre-characterized gate libraries
Fault tolerant permutation mapping in multistage interconnection network
Experimental evaluation of a set of simple error detection mechanisms
Optimized co-scheduling of mixed-precision neural network accelerator for real-time multitasking applications
Evaluation of the optimal strategy for managing the register file
A model of massively parallel call and service processing in telecommunications
MobileRE: A replicas prioritized hybrid fault tolerance strategy for mobile distributed system
Requirements for coupling small scale DBMSs in a distributed office environment
Issues and approaches to supporting timeliness and security in real-time database systems
ARGUS - a PC based image processing workstation its software and some application examples
Application and implementation of window-based image processing algorithms
A core generator for arithmetic cores and testing structures with a network interface
High-speed hardware implementations of Elliptic Curve Cryptography: A survey
DiVIT: Algorithm and architecture co-design of differential attention in vision transformer
A prototype of a VHDL-based fault injection tool: description and application
Task allocation algorithm and optimization model on edge collaboration
Multiprocessor modelling: An example of object-oriented development
A certificateless multi-dimensional data aggregation scheme for smart grid
Mapping of interconnection networks for parallel processing onto the advanced sea-of-gates VLSI
Implementing associations between objects
Hardware acceleration of the Tate pairing on a genus 2 hyperelliptic curve
What is a software process?
Shift-and-Safe: Addressing permanent faults in aggressively undervolted CNN accelerators
Concurrent architectures for real-time signal processing
Offline/Online lattice-based ciphertext policy attribute-based encryption
A genetic simulation strategy: Application to single-fault analysis of TTEthernet synchronization protocol
Results of the esprit basic research action 3148 demon (design methods based on nets)
Towards dynamic safety assurance for Industry 4.0
Multiprogrammed non-blocking checkpoints in support of optimistic simulation on myrinet clusters
An abstraction model for a Grid execution framework
Vectorization and parallelization of the conjugate gradient algorithm on hypercube-connected vector processors
Global checkpointing scheme for heterogeneous distributed database systems
Design of hardware and software systems
Exploring heterogeneous scheduling for edge computing with CPU and FPGA MPSoCs
Area compaction in silicon structures for neural net implementation
Specification of schedulability assumptions to leverage multiprocessor Analysis
Supporting testing of specifications and implementations
An embedded system for handwritten digit recognition
Multiserver configuration for cloud service profit maximization in the presence of soft errors based on grouped grey wolf optimizer
A computer architecture for real time image processing using VLSI
Breathing new life into compression: Resolving the dilemma of LFS with compression on flash storage
Embedding of complete binary tree with 2-expansion in a faulty Flexible Hypercube
Evaluating IA-32 web servers through simics: a practical experience
A two rounds dynamic authenticated group key agreement protocol based on LWE
A section cache system designed for VLIW architectures
Fast modeling L2 cache reuse distance histograms using combined locality information from software traces
Decentralized and expressive data publish-subscribe scheme in cloud based on attribute-based keyword search
Knowledge-based segmentation using morphological filters
Global hardware synthesis guided by realistic probability computation
Non-invasive testing of real-time avionic μ-processor systems
Performance models for scalable cluster computing
The need for a core method DIALOG - Linking formal proof to the design environment
Transaction multicasting scheme for resilient routing control in parallel cluster database systems
CRISC Configurable Reduced Instruction Set Computer or Complex Reconfigurable Instruction Set Computer
Thermal-aware adaptive VM allocation considering server locations in heterogeneous data centers
A deadlock detection algorithm for nested transaction model
A control-based methodology for power-performance optimization in NoCs exploiting DVFS
Efficient automatic gain control algorithm and architecture for wireless LAN receivers
Real time scheduling algorithms and their performances
Use of local-area networks as alternating sequential-parallel systems
Achieving atomicity in occam
A microcomputer LAN for process control and its VLSI access unit
A survey of techniques for intermittent computing
A high level FPGA-based abstract machine for image processing
Run-time timing prediction for system reconfiguration on many-core embedded systems
Secure fuzzy identity-based public verification for cloud storage
Using Chaos Theory based workload analysis to perform Dynamic Frequency Scaling on MPSoCs
Pairing-free certificateless authenticated encryption with keyword search
Computation and communication schedule optimization for data-sharing tasks on uniprocessor
A provably-secure authenticated key agreement protocol for remote patient monitoring IoMT
Design and implementation of a portable communication transport system for unix network applications in C++
An evaluation of XENIX system V as a real-time operating system
Rule-based synthesis using ADTs and term rewriting
SLOPE: Secure and load optimized packet scheduling model in a grid environment
Introducing structure into behavioural descriptions obtained from timing diagram specifications
Tokenisation and compression of Java class files
Using age registers for a simple load-store queue filtering
A new machine architecture for distributed operating systems
Automating application-driven customization of ASIPs: A survey
DiaSys: Improving SoC insight through on-chip diagnosis
Fuzzing proprietary protocols of programmable controllers to find vulnerabilities that affect physical control
Neural network implementations and speed-up on Massively Parallel machines
MPR-QUIC: Multi-path partially reliable transmission for priority and deadline-aware video streaming
Transient computing for energy harvesting systems: A survey
A new solution of coherence protocol for tightly coupled multiprocessor systems
Virus protection using dynamic linking
The logic of engineering design
A predecoding technique for ILP exploitation in Java processors
Analysis tools applied to VHDL
ParaStation: Efficient parallel computing by clustering workstations: Design and evaluation
A systematic reordering mechanism for on-chip networks using efficient congestion-aware method
Architectures for high performance image processing: The future
Inter-domain movement of functionality as a repartitioning strategy for hardware/software co-design
Implementing ESPITI on a European scale
SimEdgeIntel: A open-source simulation platform for resource management in edge intelligence
Design and evaluation of multikey access methods using signature files
A survey of memory management
Early-phase performance exploration of embedded systems with ABSOLUT framework
An expert system for chip-architecture planning
Performance evaluation of computer architectures with main memory data compression
An intelligent microprocessor interface for a low-cost digital magnetic tape recorder
Evolving classifiers on field programmable gate arrays: Migrating XCS to FPGAs
A survey of branch techniques in pipelined processors
Genetic algorithm based estimation of non-functional properties for GPGPU programs
An efficient for the sequential general decomposition of sequential machines
XFC: Enabling automatic and fast operator synthesis for mobile deep learning compilation
Software process assessment concepts
Interfaces for mixed-level simulation with sequential elements
FASA: A software architecture and runtime framework for flexible distributed automation systems
Subscription-free Pay-TV over IPTV
Dual-tree-based multicasting on wormhole-routed irregular switch-based networks
Packet-in request redirection: A load-balancing mechanism for minimizing control plane response time in SDNs
An efficient variable partitioning approach for functional decomposition of circuits
A new fixed-point simulation methodology for on-device AI based on large language models
A two-tier design space exploration algorithm to construct GPU performance model
Response time analysis of memory-bandwidth-regulated multiframe mixed-criticality systems
Practical multiprocessor and realtime programming in the fifth programming environment
Improving the performance of high-level synthesis
Folded-crossed hypercube: a complete interconnection network
MELOADES: Methodology for long-term online adaptation of embedded software for heterogeneous devices
Session E3: Prolog
Microelectronics: VLSI design tools I
A comparison of programming paradigms for the parallel computation of racah coefficients: An application of transputers to computational atomic physics
UDPF: A unified data provision framework for developing dynamic resource-oriented embedded applications
A suggested protocol for internet access on PSDNs
A robust and real-time DNN-based multi-baseline stereo accelerator in FPGAs
Evolutions in parallel distributed and network-based processing
Computer music I
Network topology A critical factor in the implementation of algorithms intended for efficient execution on a transputer network
TwoPhases: A transmission scheme to reduce the link width at deflection routing based Network-on-Chips
Global query management in heterogeneous distributed database systems
PREDULA a multi-paradigm parallel programming and debugging environment
Scope: An extensible interactive environment for the performance evaluation of parallel systems
Letter from the short-note editor, euromicro 90
Performance evaluation of transputer systems with linear algebra problems
Optimizing cache parameters using CAE workstations
The evolution of IoT Malwares, from 2008 to 2019: Survey, taxonomy, process simulator and perspectives
A Software System evolutionary and adaptive framework: application to Agent-based systems
Recovery meta program in Unix based environment
A high performance hardware accelerator for dynamic texture segmentation
P2PVR: A playback offset aware multicast tree for on-demand video streaming with VCR functions
Energy reduction for scheduling a set of multiple feasible interval jobs
A systematic approach and tool support for GSN-based safety case assessment
A pearl-based multi-loop and multi-sequence controller
Fast path-disjoint routing in transputer networks
Image component labeling on reconfigurable processor array
Parallel control of a waste-water treatment plant using a real-time multi-tasking operating system
An image analysis system for automatic measurements in solid state nuclear track detectors
Massive parallelism for artificial intelligence (extended abstract)
Motion interpretation by analyzing difference images
Evaluating a multicore Mixed-Criticality System implementation against a temporal isolation kernel
An efficient log-based crash recovery scheme for nested transactions
Efficient parallel timing simulation of synchronous models on networks of workstations
Hardware-aware neural architecture search for stochastic computing-based neural networks on tiny devices
Design of clocking schemes in high-level synthesis
SAMFL: Secure Aggregation Mechanism for Federated Learning with Byzantine-robustness by functional encryption
DMSE: Dynamic Multi-keyword Search Encryption based on inverted index
Towards the verification of optimizing transformations for imperative programs
Derivation of protocols implementing services with event priorities
BIDS: An efficient Intrusion Detection System for in-vehicle networks using a two-stage Binarised Neural Network on low-cost FPGA
Formal specification and object-oriented design
Indexed files in the parallel file environment
A flexible indexing structure supporting multi-attribute database applications: MAIN
Use of embedded DRAMs in video and image computing
Adaptive data interleaving using a microprocessor controlled reconfigurable gate array
SLIMBRAIN: Augmented reality real-time acquisition and processing system for hyperspectral classification mapping with depth information for in-vivo surgical procedures
A new approach towards an object-oriented database system
A quick distributed consensus protocol
A survey of techniques for optimizing deep learning on GPUs
Session D3: Program development environments
Assuring the safety of rechargeable energy storage systems in electric vehicles
Detection of multiple stuck-on/stuck-open faults by single faults test sets in MOS transistor networks
RAFL: Reputation-Aware Federated Learning with hierarchical aggregation in LEO satellite networks
Fast profiling framework and race detection for heterogeneous system
Architectural tradeoffs in the design of VLSI-based associative memories
PTD: Architectural system description support based on visual specification languages
Pipelining a memory based CISC processor
Preference-oriented fixed-priority scheduling for periodic real-time tasks
Software productivity in built-in microprocessors
Quality of Service improvement for critical flows via dual-queue transmission in fault-tolerant Time-Sensitive Networking
Enabling blockchain-assisted certificateless public integrity checking for industrial cloud storage systems
Parallel administration of events in real-time systems
OCCAM - The language for educating future parallel programmers?
Constructing communication protocols on reliable bounded FIFO channels without overspecification
Design-space evaluation for non-blocking synchronization in Ada: lock elision of protected objects, concurrent objects, and low-level atomics
A review of Urban Air Mobility-enabled Intelligent Transportation Systems: Mechanisms, applications and challenges
Network-on-Chip interconnect for pairing-based cryptographic IP cores
Introduction to the special issue on architecture of computing systems
Neural networks approach to early breast cancer detection
Run-time adaptive data page mapping: A Comparison with 3D-stacked DRAM cache
A delay insensitive approach to the VLSI design of a DRAM controller
Opening address: Hardware and software in system engineering
Heterogeneous and plaintext checkable signcryption for integrating IoT in healthcare system
POW! - The Programmers Open Workbench
Modeling distributed real-time systems with MAST 2
Architecture optimization for multimedia application exploiting data and thread-level parallelism
An efficient secure data transmission and node authentication scheme for wireless sensing networks
Towards efficient and robust intelligent mobile vision system via small object aware parallel offloading
Development of object-oriented database management system: OOIM
A parallel SVD algorithm and its application to financial ratio analysis
GSPN models of bridged LAN configurations
Some proposals for VLSI implementation of digital PID controllers with some fault-tolerance capabilities
A high speed prolog implementation on a VLIW processor
FC: Built-in flash cache with fast cleaning for SMR storage systems
Blockchain-assisted searchable attribute-based encryption for e-health systems
A model based recognition system for tactile data
A DSP-based VME system for event selection
Self-repairable GALs
Guest editorial: Special issue on edge computing and machine learning-based sensor-cloud systems
Intelligent memory manager: Reducing cache pollution due to memory management functions
Software techniques for integrating text and graphics in VLSI CAD tools
QNoC: QoS architecture and design process for network on chip
The MATERIAL framework: Modeling and AuTomatic code Generation of Edge Real-TIme AppLications under the QNX RTOS
Exploiting program phase behavior for energy reduction on multi-configuration processors
Basic issues in microprocessor architecture
A BCD-based architecture for fast coordinate rotation
Applications: Education I
Message passing via singly-buffered channels: an efficient & flexible communications control mechanism
Efficient FPGA-based architecture of an automatic wheeze detector using a combination of MFCC and SVM algorithms
A platform-based design framework for joint SW/HW multiprocessor systems design
A personal multicomputer for parallel processing of long-running programs
Hardware transactional memory: A high performance parallel programming model
Architecting resilient computing systems: A component-based approach for adaptive fault tolerance
Investigation of transient fault effects in synchronous and asynchronous Network on Chip router
A hardware allocator guided by cost functions
Parallelism measures of task graphs for multiprocessors
An optimal message routing algorithm for circulant networks
Event-based application modeling for analysis of asymmetric multicore-based mobile systems
A generic framework to integrate data caches in the WCET analysis of real-time systems
Broadcast filtering: Snoop energy reduction in shared bus-based low-power MPSoCs
Properties and performance of folded cube-connected cycles
Experiences and results in designing VLSI-chips using standard-cell techniques
Novel source-independent characterization methodology for embedded software energy estimation and optimization
Edge based authentication protocol for vehicular communications without trusted party communication
PVM-based parallel computing: a case study on power plant simulation
A survey of languages integrating functional, object-oriented and logic programming
LicenseNet: Proactively safeguarding intellectual property of AI models through model license
Using transputers to increase speed and flexibility of genetics-based machine learning systems
VCSA: Verifiable and collusion-resistant secure aggregation for federated learning using symmetric homomorphic encryption
Concurrent ring: Design and evaluation of a new Token Ring LAN
Towards holistic secure networking in connected vehicles through securing CAN-bus communication and firmware-over-the-air updating
Implementing the new Ada 2005 timing event and execution time control features on the AVR32 architecture
Lyapunov-guided deep reinforcement learning for delay-aware online task offloading in MEC systems
FedDQ: A communication-efficient federated learning approach for Internet of Vehicles
Development of a fuzzy logic controller on a digital signal processor
Automata decomposition and synthesis with PLAM
An identity-based proxy re-encryption for data deduplication in cloud