yusuke1997/dblp-id-title huggingface dataset:
An HBT MMIC power amplifier with an integrated diode linearizer for low-voltage portable phone applications
Implementation of a third-generation 1.1-GHz 64-bit microprocessor
A built-in Hamming code ECC circuit for DRAMs
A Low Power Inductorless LNA With Double G m Enhancement in 130 nm CMOS
A 2.7-mW 2-MHz Continuous-Time ΣΔ Modulator With a Hybrid Active-Passive Loop Filter
A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC
An integrated 4-20 mA two-wire transmitter with intrinsic temperature sensing capability
EMI-Regulated GaN-Based Switching Power Converter With Markov Continuous Random Spread-Spectrum Modulation and One-Cycle on-Time Rebalancing
An intelligent BiCMOS/DMOS quad 1-A high-side switch
A 400-MHz input flash converter with error correction
40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW
An hierarchical VLSI neural network architecture
A 190-µW zero-IF GFSK Demodulator With a 4-b Phase-Domain ADC
A Millimeter-Wave (40-45 GHz) 16-Element Phased-Array Transmitter in 0.18-µm SiGe BiCMOS Technology
A 12-Bit, 10-MHz Bandwidth, Continuous-Time ΣΔ ADC With a 5-Bit, 950-MS/s VCO-Based Quantizer
An alternative approach to the ROM-less direct digital synthesis
A 28-/37-/39-GHz Linear Doherty Power Amplifier in Silicon for 5G Applications
Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications
A 2-V, 2-GHz low-power direct digital frequency synthesizer chip-set for wireless communication
Variation-Tolerant, Ultra-Low-Voltage Microprocessor With a Low-Overhead, Within-a-Cycle In-Situ Timing-Error Detection and Correction Technique
Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference
A Fully-Reflective Wi-Fi-Compatible Backscatter Communication System With Retro-Reflective MIMO Gain for Improved Range
Testing of multiple-output domino logic (MODL) CMOS circuits
A 1.6-GS/s 12-bit return-to-zero GaAs RF DAC for multiple Nyquist operation
A Compact Transformer-Combined Polar/Quadrature Reconfigurable Digital Power Amplifier in 28-nm Logic LP CMOS
A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS
A 10-b, 100-MS/s CMOS A/D converter
32.9 nV/rt Hz - 60.6 dB THD Dual-Band Micro-Electrode Array Signal Acquisition IC
A 60-GHz superheterodyne downconversion mixer in silicon-germanium bipolar technology
Overview for the Special Section on the 2011 Radio Frequency Integrated Circuits (RFIC) Symposium
A nonlinear CMOS analog cell for VLSI signal and information processing
A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance
A 5-18-GHz Reconfigurable Quadrature Receiver With Enhanced I-Q Isolation and 100-500-MHz Baseband Bandwidth
Edge and Data Adaptive Equalization of Serial-Link Transceivers
A Single-Chip UHF RFID Reader in 0.18 µm CMOS Process
A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability
A Super-Pipelined Energy Efficient Subthreshold 240 MS/s FFT Core in 65 nm CMOS
A 0.02-4.5-GHz LN(T)A in 28-nm CMOS for 5G Exploiting Noise Reduction and Current Reuse
A 30-GHz CMOS SOI Outphasing Power Amplifier With Current Mode Combining for High Backoff Efficiency and Constant Envelope Operation
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology
A -80 dB THD, 4 V pp switched capacitor filter for 1.5 V battery-operated systems
A 1.5-V 45-mW direct-conversion WCDMA receiver IC in 0.13-μm CMOS
Voltage-comparator-based measurement of equivalently sampled substrate noise waveforms in mixed-signal integrated circuits
A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology
An algorithmic 15-bit CMOS digital-to-analog converter
A versatile data string-search VLSI
PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference
A 300-MHz 25-μA/Mb-leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processor
Design of High Efficiency Monolithic Power Amplifier With Envelope-Tracking and Transistor Resizing for Broadband Wireless Applications
A 0.6-V, 0.015-mm 2 , Time-Based ECG Readout for Ambulatory Applications in 40-nm CMOS
A 12-GHz silicon bipolar dual-conversion receiver for digital satellite applications
A 60-GHz Dual-Vector Doherty Beamformer
A 28-nm 36 Kb SRAM CIM Engine With 0.173 μm 2 4T1T Cell and Self-Load-0 Weight Update for AI Inference and Training Applications
TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge
Layout reconstruction of complex silicon chips
50-250 MHz ΔΣ DLL for Clock Synchronization
A fast resolving BiNMOS synchronizer for parallel processor interconnect
A low-noise, low-power VCO with automatic amplitude control for wireless applications
A band-pass delta-sigma modulator for ultrasound imaging at 160 MHz clock rate
A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing
A 1000 frames/s Vision Chip Using Scalable Pixel-Neighborhood-Level Parallel Processing
A 5-Gb/s 0.25-μm CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit
A -123-dBm Sensitivity Split-Channel BFSK Reconfigurable Data/Wake-Up Receiver for Low-Power Wide-Area Networks
A 80-gbit/s D-type flip-flop circuit using InP HEMT technology
A 90 nm-CMOS, 500 Mbps, 3-5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization
A +78 dBm IIP2 CMOS direct downconversion mixer for fully integrated UMTS receivers
A Complex Image Rejection Circuit With Sign Detection Only
20 µ A to 100 mA DC-DC Converter With 2.8-4.2 V Battery Supply for Portable Applications in 45 nm CMOS
A CMOS logarithmic IF amplifier with unbalanced source-coupled pairs
On-wafer BIST of a 200-Gb/s failed-bit search for 1-Gb DRAM
A 26-Gb/s Framed-Pulsewidth Modulation Transceiver for Extended Reach Optical Links
Novel automatic tuning method of RC filters using a digital-DLL technique
Key Aspects in Modeling of Thin Epi SOS Technology With Application of BSIMSOI
Considerations for improving the accuracy of large-signal GaAs MESFET models to predict power amplifier circuit performance
A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications
A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications
A quad-band GSM-GPRS transmitter with digital auto-calibration
Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes
A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration
An approach for fabricating high-performance inductors on low-resistivity substrates
A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths
A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array
A 64-min single-chip voice recorder/player using embedded 4-b/cell flash memory
A 2-V, 1-10 GHz BiCMOS transceiver chip for multimode wireless communications networks
A 915 MHz IoT Transmitter Employing Frequency Tripler and Digitally Controlled Duty-Cycle/Phase Calibration
A -90-dB THD rail-to-rail input opamp using a new local charge pump in CMOS
Programmable, four-channel, 128-sample, 40-Ms/s analog-ternary correlator
A Multi-Aperture Image Sensor With 0.7 µm Pixels in 0.11 µm CMOS Technology
A fast VLSI adder architecture
A 2 × 24 Gb/s Single-Ended Transceiver With Channel-Independent Encoder-Based Crosstalk Cancellation in 28-nm CMOS
Low-Power Highly Selective Channel Filtering Using a Transconductor-Capacitor Analog FIR
Comments on "A robust single phase clocking for low power, high-speed VLSI applications" [and reply]
A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth
A Transformer-Combined 31.5 dBm Outphasing Power Amplifier in 45 nm LP CMOS With Dynamic Power Control for Back-Off Power Efficiency Enhancement
A very high-frequency CMOS complementary folded cascode amplifier
An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at VDD = 0 V Achieving Zero Leakage With < 400-ns Wakeup Time for ULP Applications
A 13 pJ/bit 900 MHz QPSK/16-QAM Band Shaped Transmitter Based on Injection Locking and Digital PA for Biomedical Applications
Digital Fractional-N PLLs Based on a Continuous-Time Third-Order Noise-Shaping Time-to-Digital Converter for a 240-GHz FMCW Radar System
Terahertz CMOS Frequency Generator Using Linear Superposition Technique
A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth
Digitally Controlled Leakage-Based Oscillator and Fast Relocking MDLL for Ultra Low Power Sensor Platform
Silicon Resonator Based 3.2 muW Real Time Clock With pm10 ppm Frequency Accuracy
A 6-Gb/s MIMO Crosstalk Cancellation Scheme for High-Speed I/Os
A 2-V 2-GHz BJT variable frequency oscillator
100+dB A-Weighted SNR Microphone Preamplifier With On-Chip Decoupling Capacitors
Correction to "A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 µm CMOS" [Mar 09 891-900]
A low-jitter wide-range skew-calibrated dual-loop DLL using antifuse circuitry for high-speed DRAM
Introduction to the Special Section on the 2015 Compound Semiconductor Integrated Circuit Symposium
An integrated CMOS micromechanical resonator high-Q oscillator
A 40-67 GHz Power Amplifier With 13 dBm ℙ SAT and 16% PAE in 28 nm CMOS LP
A Sub-100-μW 0.1-to-27-Mb/s Pulse-Based Digital Transmitter for the Human Intranet in 28-nm FD-SOI CMOS
A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction
Event-Driven GHz-Range Continuous-Time Digital Signal Processor With Activity-Dependent Power Dissipation
Noise in RF-CMOS mixers: a simple physical model
Single-chip 4×500-MBd CMOS transceiver
Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference
A 1.5-V-100-μW ΔΣ modulator with 12-b dynamic range using the switched-opamp technique
A 28 nm DSP Powered by an On-Chip LDO for High-Performance and Energy-Efficient Mobile Applications
An efficient MOSFET current model for analog circuit simulation-subthreshold to strong inversion
A 1/3-in interline transfer CCD image sensor with a negative-feedback-type charge detector
A 160-MHz bipolar wide-band IF amplifier
A 25 dBm Digitally Modulated CMOS Power Amplifier for WCDMA/EDGE/OFDM With Adaptive Digital Predistortion and Efficient Power Control
Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator
A low power video-rate pyramid VQ decoder
1-Gb/s 80-dBΩ fully differential CMOS transimpedance amplifier in multichip on oxide technology for optical interconnects
A 1-μW/MHz RC Oscillator With Three-Point Trimmed 2.1-ppm/°C and Single-Point Trimmed 8.7-ppm/°C Stability From40 °C to 95 °C
A 0.5-V power-supply scheme for low-power system LSIs using multi-V th SOI CMOS technology
A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS
A Fully-Implantable Cochlear Implant SoC With Piezoelectric Middle-Ear Sensor and Arbitrary Waveform Neural Stimulation
A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order ΔΣ Linearization
Multipurpose Deep-Learning Accelerator for Arbitrary Quantization With Reduction of Storage, Logic, and Latency Waste
A 400-MHz random-cycle dual-port interleaved DRAM (D 2 RAM) with standard CMOS Process
Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI
A 10 fJ·K 2 Wheatstone Bridge Temperature Sensor With a Tail-Resistor-Linearized OTA
Near- and Sub-V t Pipelines Based on Wide-Pulsed-Latch Design Techniques
A Fractional-N Digital MDLL With Background Two-Point DTC Calibration
A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process
A 5.6 MIPS call-handling processor for switching systems
A Low-Phase-Noise VCO With Common-Mode Resonance Expansion and Intrinsic Differential 2nd-Harmonic Output Based on a Single Three-Coil Transformer
A 125 µW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications
A 12-mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver
Design and Analysis of a Sample-and-Hold CMOS Electrochemical Sensor for Aptamer-Based Therapeutic Drug Monitoring
Simulation of mixed switched-capacitor/digital networks with signal-driven switches
Wordline voltage generating system for low-power low-voltage flash memories
A 13-b 40-MSamples/s CMOS pipelined folding ADC with background offset trimming
High-Voltage Tolerant Digitally Aided DCM/PWM Multiphase DC-DC Boost Converter With Integrated Schottky Diodes in 0.13 µm 1.2 V Digital CMOS Process
nMOS reversible energy recovery logic for ultra-low-energy applications
A Highly Integrated 60 GHz 6-Channel Transceiver With Antenna in Package for Smart Sensing and Short-Range Communications
A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-μm CMOS
A 144-Mb, eight-level NAND flash memory with optimized pulsewidth programming
Quadrature Switched/Floated Capacitor Power Amplifier With Reconfigurable Self-Coupling Canceling Transformer for Deep Back-Off Efficiency Enhancement
A novel high-speed sense amplifier for Bi-NOR flash memories
A 576 K 3.5-ns access BiCMOS ECL static RAM with array built-in self-test
A behavioral model of A/D converters using a mixed-mode simulator
Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS
A monolithic video frequency filter using NIC-based gyrators
Guest Editorial Introduction to the Special Section on the 2024 Asian Solid-State Circuits Conference (A-SSCC)
Non-quasi-static effects in advanced high-speed bipolar circuits
A 63-dB DR 22.5-MHz 21.5-dBm IIP3 Fourth-Order FLFB Analog Filter
A -90 dBm Sensitivity Wireless Transceiver Using VCO-PA-LNA-Switch-Modulator Co-Design for Low Power Insect-Based Wireless Sensor Networks
A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine
A digital signal processor for an ANSI standard ISDN transceiver
MetaVRain: A Mobile Neural 3-D Rendering Processor With Bundle-Frame-Familiarity-Based NeRF Acceleration and Hybrid DNN Computing
A Fully Integrated 0.13-µm CMOS 40-Gb/s Serial Link Transceiver
An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time
A DLL-biased, 14-bit DS analog-to-digital converter for GSM/GPRS/EDGE handsets
A self-testing reconfigurable CAM
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining
A 12-Bit 260-MS/s Pipelined-SAR ADC With Ring-TDC-Based Fine Quantizer for Automatic Cross-Domain Scale Alignment
A CMOS current-mode operational amplifier
A 30-gb/s 70-mW one-stage 4: 1 multiplexer in 0.13-μm CMOS
A Transceiver ASIC for a Single-Cable 64-Element Intra-Vascular Ultrasound Probe
A 27-GHz Quad-Core CMOS Oscillator With No Mode Ambiguity
A Multiband RF Antenna Duplexer on CMOS: Design and Performance
A 2000-MOPS embedded RISC processor with a Rambus DRAM controller
An EPR4 read/write channel with digital timing recovery
A Ka-Band Multi-Beam Phased-Array Transmitter With Time-Modulation for PAPR Reduction and Physical Layer Security
A 10-Bit 800-MHz 19-mW CMOS ADC
A High Resolution Interface for Kelvin Impedance Sensing
A 1.8-65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators
A 136-μW/channel autonomous strain-gauge datalogger
A high-performance multibit ΔΣ CMOS ADC
An offset reduction technique for use with CMOS integrated comparators and amplifiers
Design techniques for tunable transresistance-C VHF bandpass filters
High reliability electron-ejection method for high density flash memories
A CMOS delta-sigma true RMS converter
A 60-GHz HEMT-MMIC analog frequency divider by two
A Silicon-Based 0.3 THz Frequency Synthesizer With Wide Locking Range
A 0.4-4 THz p-i-n Diode Frequency Multiplier in 90-nm SiGe BiCMOS
A fast-settling CMOS op amp for SC circuits with 90-dB DC gain
A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers
An 8.2- $\mu$ W 0.14-mm 2 16-Channel CDMA-Like Capacitance-to-Digital Converter
A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping
A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates
A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination
FLIP-Q: A QCIF Resolution Focal-Plane Array for Low-Power Image Processing
A 64-bit microprocessor in 130-nm and 90-nm technologies with power management features
Monolithic GaAs transimpedance amplifiers for fiber-optic receivers
A software programmable CMOS telephone circuit
High-speed 8:1 multiplexer and 1:8 demultiplexer implemented with AlGaAs/GaAs HBTs
A 0.004-mm 2 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp
A low-noise, GaAs/AlGaAs, microwave frequency-synthesizer IC
Ferroelectric (Fe)-NAND Flash Memory With Batch Write Algorithm and Smart Data Store to the Nonvolatile Page Buffer for Data Center Application High-Speed and Highly Reliable Enterprise Solid-State Drives
A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme
NeuroSLAM: A 65-nm 7.25-to-8.79-TOPS/W Mixed-Signal Oscillator-Based SLAM Accelerator for Edge Robotics
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link
A Low-Power Fullband 802.11a/b/g WLAN Transceiver With On-Chip PA
GANPU: An Energy-Efficient Multi-DNN Training Processor for GANs With Speculative Dual-Sparsity Exploitation
A 30-fps 192 × 192 CMOS Image Sensor With Per-Frame Spatial-Temporal Coded Exposure for Compressive Focal-Stack Depth Sensing
A process-parameter-based circuit simulation model for ion-implanted MOSFETs and MESFETs
A self-off-time detector for reducing standby current of DRAM
A 21-48 GHz Subharmonic Injection-Locked Fractional-N Frequency Synthesizer for Multiband Point-to-Point Backhaul Communications
A CMOS Dual-RC Frequency Reference With ±200-ppm Inaccuracy From -45 °C to 85 °C
A Rail-To-Rail Class-AB Amplifier With an Offset Cancellation for LCD Drivers
A direct digital frequency synthesizer with fourth-order phase domain ΔΣ noise shaper and 12-bit current-steering DAC
A CCD frequency prescaler for broadband applications
High performance asynchronous design using single-track full-buffer standard cells
Dual-Input Stacked Inverter-Based Single-Ended DRAM Sense Amplifier Using BL Switches for Low-Power High-Speed Sensing
A 10 Watt S-Band MMIC Power Amplifier With Integrated 100 MHz Switch-Mode Power Supply and Control Circuitry for Active Electronically Scanned Arrays
Analysis and design of injection-locked LC dividers for quadrature generation
A 0.9-V DAC-Calibration-Free Continuous-Time Incremental Delta-Sigma Modulator Achieving 97-dB SFDR at 2 MS/s in 28-nm CMOS
A 40 mV Transformer-Reuse Self-Startup Boost Converter With MPPT Control for Thermoelectric Energy Harvesting
Optimization of CMOS arbiter and synchronizer circuits with submicrometer MOSFETs
A compact low noise operational amplifier for a 1.2 μm digital CMOS technology
Bristol Ridge: A 28-nm × 86 Performance-Enhanced Microprocessor Through System Power Management
A 10-b 40-MHz 0.8- mu m CMOS current-output D/A converter
A Low-EMI 3-W Audio Class-D Amplifier Compatible With AM/FM Radio
Simple noise model and low-noise data-output buffer for ultrahigh-speed memories
A ±5A Integrated Current-Sensing System With ±0.3% Gain Error and 16μA Offset From -55°C +85°C
A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration
High-Throughput Signal Component Separator for Asymmetric Multi-Level Outphasing Power Amplifiers
Widely programmable high-frequency continuous-time filters in digital CMOS technology
A 5-GHz CMOS transceiver for IEEE 802.11a wireless LAN systems
A differential 160-MHz self-terminating adaptive CMOS line driver
A 12-Bit 200-MHz CMOS ADC
Modular 128-Channel Δ-ΔΣ Analog Front-End Architecture Using Spectrum Equalization Scheme for 1024-Channel 3-D Neural Recording Microsystems
High-performance CMOS/SOS circuits in SPEAR material
Harmonic-Resilient Fully Passive Mixer-First Receiver for Software-Defined Radios
A 1-GHz CMOS up-conversion mixer
Circuits and techniques for high-resolution measurement of on-chip power supply noise
A 0.1 mm 2 , Wide Bandwidth Continuous-Time ΔΣ ADC Based on a Time Encoding Quantizer in 0.13 µm CMOS
A 76 dB Ω 1.7 GHz 0.18 μ m CMOS Tunable TIA Using Broadband Current Pre-Amplifier for High Frequency Lateral MEMS Oscillators
Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler"
Short channel models and scaling limits of SOI and bulk MOSFETs
A 125 μ m-Pitch-Matched Transceiver ASIC With Micro-Beamforming ADC and Multi-Level Signaling for 3-D Transfontanelle Ultrasonography
A single-chip adaptive DPCM video codec
A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8× oversampling ratio
A voltage down converter with submicroampere standby current for low-power static RAMs
A 19 nm 112.8 mm 2 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface
A 77-GHz Mixed-Mode FMCW Signal Generator Based on Bang-Bang Phase Detector
A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECC
48-to-1 V Direct Conversion Using High-Voltage Storage and Low-Voltage Boost Bootstrap Technique and Early Comparison On-Time Generator for Precise Nanosecond Pulses and 90.3% Efficiency in Automotive Applications
A Single-Photon Avalanche Diode Array for Fluorescence Lifetime Imaging Microscopy
Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs
Interconnection and packaging of solid-state circuits
An analog neural network processor with programmable topology
A 4.6-400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration
Reconfigurable Clock Networks for Wide Voltage Scaling
A 1.8-V 256-Mb Multilevel Cell NOR Flash Memory With BGO Function
A Monolithically Integrated Large-Scale Optical Phased Array in Silicon-on-Insulator CMOS
An 8-ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D 2 /RAM)
A 64-b quad-issue CMOS RISC microprocessor
Race logic architecture (RALA): a novel logic concept using the race scheme of input variables
A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips
A Wideband Millimeter-Wave Power Amplifier With 20 dB Linear Power Gain and +8 dBm Maximum Saturated Output Power
Associative IC memories with relational search and nearest-match capabilities
An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling
Low-voltage 1.9-GHz front-end receiver in 0.5-μm CMOS technology
A Single Analog-to-Digital Converter That Converts Two Separate Channels (I and Q) in a Broadband Radio Receiver
Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting
10-GSymbols/s Supply-Modulated APSK C SiGe HBT Transmitter RF Front End for Operation at 250 GHz With 6.8-dBm Peak Modulated Power
Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators With Inductor
A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator With Digital Noise Coupling
CMOS subnanosecond true-ECL output buffer
A 1.25-inch 60-frames/s 8.3-M-pixel digital-output CMOS image sensor
An 8-bit-resolution, 360-μs write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS)
A 50-Gbit/s 450-mW Full-Rate 4: 1 Multiplexer With Multiphase Clock Architecture in 0.13-µm InP HEMT Technology
Metal-mask configurable RF front-end circuits
Ultrasonic Imaging Transceiver Design for CMUT: A Three-Level 30-Vpp Pulse-Shaping Pulser With Improved Efficiency and a Noise-Optimized Receiver