yusuke1997/dblp-id-title huggingface dataset:
A 4-bit Josephson data processor chip
Power-Efficient W-Band (92-98 GHz) Phased-Array Transmit and Receive Elements With Quadrature-Hybrid-Based Passive Phase Interpolator
A Wideband Millimeter-Wave Frequency Synthesis Architecture Using Multi-Order Harmonic-Synthesis and Variable N -Push Frequency Multiplication
A robust 43-GHz VCO in CMOS for OC-768 SONET applications
A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC
Analysis and Design of High-Harmonic-Rejection Multi-Ratio mm-Wave Frequency Multipliers
A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC
A 20-Gb/s Adaptive Equalizer in 0.13-$muhbox m$CMOS Technology
Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops
A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter
Algebraic Series-Parallel-Based Switched-Capacitor DC-DC Boost Converter With Wide Input Voltage Range and Enhanced Power Density
Clock and data recovery IC for 40-Gb/s fiber-optic receiver
A 44-μW 4.3-GHz injection-locked frequency divider with 2.3-GHz locking range
A serial bus transceiver for the automotive environment
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS
Simplified linear representation of logic gate terminal impedances for use in interconnect crosstalk calculations
BiCMOS circuit technology for high-speed DRAMs
The MICROMIXER: a highly linear variant of the Gilbert mixer using a bisymmetric Class-AB input stage
A Fully Integrated 14 Band, 3.1 to 10.6 GHz 0.13 μm SiGe BiCMOS UWB RF Transceiver
A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme
A 40-Gb/s CDR Circuit With Adaptive Decision-Point Control Based on Eye-Opening Monitor Feedback
Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing
Wide-band transimpedance amplifiers using AlGaAs/In x Ga 1-x As pseudomorphic 2-DEG FET's
A Capacitively Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver
A Programmable Vision Chip Based on Multiple Levels of Parallel Processors
A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS
A Wideband IQ-Mapping Direct-Digital RF Modulator for 5G Transmitters
1-cc Computer: Cross-Layer Integration With UWB-IR Communication and Locationing
A 10-GHz SiGe BiCMOS phase-locked-loop frequency synthesizer
Multichannel 65 zF rms Resolution CMOS Monolithic Capacitive Sensor for Counting Single Micrometer-Sized Airborne Particles on Chip
Circuit partitioning for logic synthesis
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology
A reconfigurable system featuring dynamically extensible embedded microprocessor, FPGA, and customizable I/O
A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF
Analog layout using ALAS!
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth
A 1.5 V class AB CMOS buffer amplifier for driving low-resistance loads
A 15-b, 5-Msample/s low-spurious CMOS ADC
Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digital Converter Without Noise Sensors
Energy-Efficient Design Methodologies: High-Performance VLSI Adders
A comprehensive analysis of IMD behavior in RF CMOS power amplifiers
A 12.8-15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation
A ΔΣ Interface for MEMS Accelerometers Using Electrostatic Spring Constant Modulation for Cancellation of Bondwire Capacitance Drift
Multi-Phase Injection Widens Lock Range of Ring-Oscillator-Based Frequency Dividers
A 5.3-GHz programmable divider for HiPerLAN in 0.25-μm CMOS
An Orthogonal Current-Reuse Amplifier for Multi-Channel Sensing
Pulsewidth control loop in high-speed CMOS clock buffers
Asynchronous Approximation of a Center of Gravity for Pixel Detectors' Readout Circuits
A 118 dB PSRR, 0.00067% (-103.5 dB) THD+N and 3.1 W Fully Differential Class-D Audio Amplifier With PWM Common Mode Control
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique
A 200 MHz steered current operational amplifier in 1.2-μm CMOS technology
Reducing Power Side-Channel Information Leakage of AES Engines Using Fully Integrated Inductive Voltage Regulator
A 30% Efficient High-Output Voltage Fully Integrated Self-Biased Gate RF Rectifier Topology for Neural Implants
A simple precharged CMOS phase frequency detector
Guest Editorial Introduction to the Special Section on the 2021 Asian Solid-State Circuits Conference (A-SSCC)
A Delta-Sigma Modulator With a Widely Programmable Center Frequency and 82-dB Peak SNDR
A 200 MHz CMOS broad-band switching chip
A Physically Unclonable Function Using Soft Oxide Breakdown Featuring 0% Native BER and 51.8 fJ/bit in 40-nm CMOS
A 20-Gb/s flip-flop circuit using direct-coupled FET logic
A mm-Wave Switched-Capacitor RFDAC
High-Value Tunable Pseudo-Resistors Design
A new CR-delay circuit technology for high-density and high-speed DRAMs
The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs
A Self-Powered CMOS Reconfigurable Multi-Sensor SoC for Biomedical Applications
A 2.7-V 300-MS/s track-and-hold amplifier
Design of A Transformer-Based Reconfigurable Digital Polar Doherty Power Amplifier Fully Integrated in Bulk CMOS
A DC-100 GHz Active Frequency Doubler With a Low-Voltage Multiplier Core
A Sub-7-GHz Linear Receiver for 5G Local Area Base Station Applications
Fully bipolar, 120-Msample/s 10-b track-and-hold circuit
A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters
A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers
A CMOS Broadband Power Amplifier With a Transformer-Based High-Order Output Matching Network
High Linearity Transmit Power Mixers Using Baseband Current Feedback
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply
A 550-μW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction
A Full-Duplex Rake Receiver Using RF Code-Domain Signal Processing for Multipath Environments
Design techniques for a compatible single and dual supply analog cell library
Low-power CMOS digital design
A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate
A multifunctional high-speed switch element for ATM applications
FreFlex: A High-Performance Processor for Convolution and Attention Computations via Sparsity-Adaptive Dynamic Frequency Boosting
Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry
A Bypass-Switching SAR ADC With a Dynamic Proximity Comparator for Biomedical Applications
A dual-channel voice-band PCM codec using Sigma Delta modulation technique
Comments, with reply, on 'Characterization and modeling of mismatch in MOS transistors for precision analog design'
A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination
A compact high-speed (31, 5) parallel counter circuit based on capacitive threshold-logic gates
A single-chip CIF 30-Hz, H261, H263, and H263+ video encoder/decoder with embedded display controller
Corrections to "A Synchronized Switch Harvesting Rectifier With Reusable Storage Capacitors for Piezoelectric Energy Harvesting"
Enhanced-Selectivity High-Linearity Low-Noise Mixer-First Receiver With Complex Pole Pair Due to Capacitive Positive Feedback
A 20 GHz 8 bit multiplexer IC implemented with 0.5 μm WN x /W-gate GaAs MESFET's
A 12.1 TOPS/W Quantized Network Acceleration Processor With Effective-Weight-Based Convolution and Error-Compensation-Based Prediction
A 13.56 MHz, 94.1% Peak Efficiency CMOS Active Rectifier With Adaptive Delay Time Control for Wireless Power Transmission Systems
A CMOS four-quadrant analog multiplier with single-ended voltage output and improved temperature performance
A 0.65-V 2.5-GHz Fractional-N Synthesizer With Two-Point 2-Mb/s GFSK Data Modulation
A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors
Comments on the optimum CMOS tapered buffer problem
Integrated selectivity for narrow-band FM IF systems
A 1-Gb/s bidirectional I/O buffer using the current-mode scheme
Highly parallel residue arithmetic chip based on multiple-valued bidirectional current-mode logic
A 108 Gb/s PAM-4 VCSEL-Based Direct-Drive Optical Engine for Co-Packaged Optics Applications
A 26/28/39-GHz Reconfigurable Phased-Array Receiver Front-End With Built-In Calibration Technique for 5G New Radio
A 1-V 86-mW-RX 53-mW-TX Single-Chip CMOS Transceiver for WLAN IEEE 802.11a
A Front-End ASIC With High-Voltage Transmit Switching and Receive Digitization for 3-D Forward-Looking Intravascular Ultrasound Imaging
A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O
Integration of a short-loop SLIC in a low-voltage submicron BiCMOS technology
Digital characteristics of CMOS devices at cryogenic temperatures
A 0.5 nJ/Pixel 4 K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications
Consideration of poly-Si loaded cell capacity limits for low-power and high-speed SRAMs
An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW
A Full-Duplex Line Driver for Gigabit Ethernet With Rail-to-Rail Class-AB Output Stage in 28 nm CMOS
Low switching noise and load-adaptive output buffer design techniques
Low voltage, high efficiency GaAs Class E power amplifiers for wireless transmitters
A 373-F 2 0.21%-Native-BER EE SRAM Physically Unclonable Function With 2-D Power-Gated Bit Cells and ${V}_{\text{SS}}$ Bias-Based Dark-Bit Detection
Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous conduction mode
Limitations and challenges of multigigabit DRAM chip design
An efficient digital sliding controller for adaptive power-supply regulation
A 4 GHz Continuous-Time ΔΣ ADC With 70 dB DR and -74 dBFS THD in 125 MHz BW
A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver
A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM
A 115-mW, 0.5-μm CMOS GPS receiver with wide dynamic-range active filters
A 2.267-Gb/s, 93.7-pJ/bit Non-Binary LDPC Decoder With Logarithmic Quantization and Dual-Decoding Algorithm Scheme for Storage Applications
A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse
The waveform degradation in VLSI interconnections
A programmable piecewise linear large-signal CMOS amplifier
A Sub-100 μ W MICS/ISM Band Transmitter Based on Injection-Locking and Frequency Multiplication
A fuzzy logic inference processor
A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop
132-Gb/s 4: 1 multiplexer in 0.13-μm SiGe-bipolar technology
MOSFET thermal noise modeling for analog integrated circuits
A single-path pulsewidth control loop with a built-in delay-locked loop
Structured design of a 288-tap FIR filter by optimized partial product tree compression
A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications
A Resonant One-Step 325 V to 3.3-10 V DC-DC Converter With Integrated Power Stage Benefiting From High-Voltage Loss-Reduction Techniques
A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture
A dual-phase-controlled dynamic latched amplifier for high-speed and low-power DRAMs
A 410-mW 1.22-GHz downconverter in a dual-conversion tuner IC for OpenCable applications
A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization
A Transformer-Based Series-Resonance CMOS VCO
A broadband 10-GHz track-and-hold in Si/SiGe HBT technology
A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture
A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 μ m CMOS
A 24-29.5-GHz Highly Linear Phased-Array Transceiver Front-End in 65-nm CMOS Supporting 800-MHz 64-QAM and 400-MHz 256-QAM for 5G New Radio
A 147-dB dynamic range electronic attenuator for audiometric applications with on-chip 1-W power amplifier
A Single-Inductor Triple-Source Quad-Mode Energy-Harvesting Interface With Automatic Source Selection and Reversely Polarized Energy Recycling
Design-Agnostic Distributed Timing Fault Injection Monitor With End-to-End Design Automation
Class AB CMOS amplifiers with high efficiency
A 24-Gb/s Double-Sampling Receiver for Ultra-Low-Power Optical Communication
A 1 Gbit synchronous dynamic random access memory with an independent subarray-controlled scheme and a hierarchical decoding scheme
Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks
An automatic offset compensation scheme with ping-pong control for CMOS operational amplifiers
Analysis and Design of D-Band Injection-Locked Frequency Dividers
A 64-Channel Inverter-Based Neural Signal Recording Amplifier With a Novel Differential-Like OTA Achieving an NEF of 0.84
An 80 × 60 Flash LiDAR Sensor With In-Pixel Delta-Intensity Quaternary Search Histogramming TDC
A 1-Tap 40-Gb/s Look-Ahead Decision Feedback Equalizer in 0.18-$muhbox m$SiGe BiCMOS Technology
Design concept for radiation hardening of low power and low voltage dynamic memories
Introduction to the Special Section on the 2008 Compound Semiconductor Integrated Circuit Symposium (CSICS'08)
A 28 GHz Single-Input Linear Chireix (SILC) Power Amplifier in 130 nm SiGe Technology
A 0.8-1.2 V 10-50 MS/s 13-bit Subranging Pipelined-SAR ADC Using a Temperature-Insensitive Time-Based Amplifier
A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS
Optimum buffer circuits for driving long uniform lines
Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing
Addition to "An analysis of flicker noise rejection in low-power and low-voltage CMOS mixers"
Optimization of word-line booster circuits for low-voltage flash memories
Low-power pipeline ADC for wireless LANs
Comments on "A sinh Resistor and Its Application to tanh Linearization"
2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors
Design of High Dynamic Range HBT N-Path Receivers With Dual-Resonant-Mode LO Drive
SRAM bitline circuits on PD SOI: advantages and concerns
Switch-Matrix-Based High-Density Microelectrode Array in CMOS Technology
A 0.15 V Input Energy Harvesting Charge Pump With Dynamic Body Biasing and Adaptive Dead-Time for Efficiency Improvement
Phase Noise and Jitter in CMOS Ring Oscillators
A 512-mb DDR3 SDRAM prototype with C IO minimization and self-calibration techniques
ΣHigh-frequency LC VCO design using capacitive degeneration
A 10-b 1-GHz 33-mW CMOS ADC
Array Architecture for a Nonvolatile 3-Dimensional Cross-Point Resistance-Change Memory
A 2.5-V 12-b 54-Msample/s 0.25-μm CMOS ADC in 1-mm 2 with mixed-signal chopping and calibration
A 60-Gb/s PAM4 Wireline Receiver With 2-Tap Direct Decision Feedback Equalization Employing Track-and-Regenerate Slicers in 28-nm CMOS
A no-trimming SLIC two-chip set with coin telephone signaling facilities
Compensation in variable ratio current mirrors
A Compact and Low Power 5-10 GHz Quadrature Local Oscillator for Cognitive Radio Applications
A 143 × 81 Mutual-Capacitance Touch-Sensing Analog Front-End With Parallel Drive and Differential Sensing Architecture
Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports
A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface
A 28-nm 1.3-mW Speech-to-Text Accelerator for Edge AI Devices
Design considerations for CMOS digital circuits with improved hot-carrier reliability
Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings
A 1.8-V operation RF CMOS transceiver for 2.4-GHz-band GFSK applications
A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop
A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers
A Fully Integrated 2×2 Power Amplifier for Dual Band MIMO 802.11n WLAN Application Using SiGe HBT Technology
An 80-Gb/s/pin Single-Ended Voltage-Mode PAM-4 Transmitter With a Pulsewidth Pre-Emphasis and a 4-Tap FFE in 28-nm CMOS
Introducing Short Regular Papers
Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology
A β-Compensated NPN-Based Temperature Sensor With ±0.1 °C (3σ) Inaccuracy From -55 °C to 125 °C and 200fJ · K² Resolution FoM
Substrate-triggered ESD protection circuit without extra process modification
A 130-dB CMRR Instrumentation Amplifier With Common-Mode Replication
Fault-tolerant designs for 256 Mb DRAM
A 0.44-μJ/dec, 39.9-μs/dec, Recurrent Attention In-Memory Processor for Keyword Spotting
A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver
A 79 GHz Phase-Modulated 4 GHz-BW CW Radar Transmitter in 28 nm CMOS
A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder
A 288-GHz Lens-Integrated Balanced Triple-Push Source in a 65-nm CMOS Technology
A 20 MHz Bandwidth 79 dB SNDR SAR-Assisted Noise-Shaping Pipeline ADC With Gain and Offset Calibrations
A 2-11 GHz 7-Bit High-Linearity Phase Rotator Based on Wideband Injection-Locking Multi-Phase Generation for High-Speed Serial Links in 28-nm CMOS FDSOI
Realization of In-Band Full-Duplex Operation at 300 and 4.2 K Using Bilateral Single-Sideband Frequency Conversion
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References
0.77 fJ/bit/search Content Addressable Memory Using Small Match Line Swing and Automated Background Checking Scheme for Variation Tolerance
A resonant switching write driver for magnetic recording
Single-X-Ray Sensitive Energy-Binning Dosimeter for Closed-Loop Cancer External-Beam Radiotherapy
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling
A 10-V-Tolerant Dual-Mode Neural Stimulation System With Self-Sustaining Dynamic Supply and Error-Resilient Digital Stimulus Odometer
A complete single-chip GPS receiver with 1.6-V 24-mW radio in 0.18-μm CMOS
Fully balanced CMOS current-mode circuits
A Continuous-Time Digital IIR Filter With Signal-Derived Timing and Fully Agile Power Consumption
Haswell: A Family of IA 22 nm Processors
A 100-MHz pipelined CMOS comparator
A Digitally Intensive Transmitter/PA Using RF-PWM With Carrier Switching in 130 nm CMOS
A 10-b, 75-MHz two-stage pipelined bipolar A/D converter
Configurable Hybrid Energy Synchronous Extraction Interface With Serial Stack Resonance for Multi-Source Energy Harvesting
Level-shifted 0.5- mu m BiCMOS circuits
3-V MSM-TIA for Gigabit Ethernet
A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC
Guest Editorial Introduction to the Special Issue on the 2021 Symposium on VLSI Circuits
Write pulse Generator for 16x DVD recording with symmetric CMOS inverter ring oscillator
ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier
A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering
Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing
A Crystal-Less BLE Transmitter With Clock Recovery From GFSK-Modulated BLE Packets
CAMELEON: a process-tolerant symbolic layout system
A Variable-Phase Ring Oscillator and PLL Architecture for Integrated Phased Array Transceivers
A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology
Integrated AlGaAs/GaAs HBT high slew-rate and wide band operational amplifier
Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs
High-speed driving scheme and compact high-speed low-power rail-to-rail class-B buffer amplifier for LCD applications
A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR-ΔΣ ADC With On-Chip Buffer in 28 nm CMOS
A CMOS RF power amplifier with parallel amplification for efficient power control
A 2.5 Gb/s ATM add-drop unit for B-ISDN based on a GaAs LSI
A 15-mW, 155-Mb/s CMOS burst-mode laser driver with automatic power control and end-of-life detection
A new MOS imager using photodiode as current source
A 23-GHz TX/LNA Front-End Module for Inter-Satellite Links With 27.8% Peak Efficiency in the TX Path and 3.1-dB NF in the RX Path
Monolithic AGC loop for a 160 Mb/s transimpedance amplifier
The design and analysis of a DLL-based frequency synthesizer for UWB application
A 0.8- mu m CMOS technology for high-performance ASIC memory and channelless gate array
Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's
A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers
A 4-Mb pseudo SRAM operating at 2.6+or-1 V with 3- mu A data retention current
A 5.35-mW 10-MHz Single-Opamp Third-Order CT ΔΣ Modulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS
A Low-Power Convolutional Neural Network Face Recognition Processor and a CIS Integrated With Always-on Face Detector
A 3-Tap FIR Filter With Cascaded Distributed Tap Amplifiers for Equalization Up to 40 Gb/s in 0.18-$mu$m CMOS
A Multiphase Switched-Capacitor DC-DC Converter Ring With Fast Transient Response and Small Ripple
A 4-Mbit DRAM with 16-bit concurrent ECC
A 500-dpi AC capacitive hybrid flip-chip CMOS ASIC/sensor module for fingerprint, navigation, and pointer detection with on-chip data processing
Design and characterization of a CMOS off-chip driver/receiver with reduced power-supply disturbance
A High Dynamic Range CMOS Variable Gain Amplifier for Mobile DTV Tuner
Introduction to the Special Issue on the 2011 Symposium on VLSI Circuits
A 1-V, 8-bit successive approximation ADC in standard CMOS process
A 2-V 300-MHz 1-Mb current-sensed double-density SRAM for low-power 0.3-μm CMOS/SIMOX ASICs
A 0.25-μm 3.0-V 1T1C 32-Mb nonvolatile ferroelectric RAM with address transition detector and current forcing latch sense amplifier scheme
An 87-mA · min Iontophoresis Controller IC With Dual-Mode Impedance Sensor for Patch-Type Transdermal Drug Delivery System
Correction to "high-Q Hf microelectromechanical filters"
Design of a low-noise preamplifier for nerve cuff electrode recording
A -90-dBFS-IM 3 , -164-dBFS/Hz-NSD, 700-MHz-Bandwidth Continuous-Time Pipelined ADC With Digital Cancellation of DAC Errors
A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes
A 1-V 3.5-mW CMOS switched-opamp quadrature IF circuitry for Bluetooth receivers
CMOS analog front end of a transceiver with digital echo cancellation for ISDN
A Harmonic-Mixer-Based Fractional-N PLL Employing Voltage-Domain Feed-Forward Noise Cancellation
Clock generation and distribution for the 130-nm Itanium ® 2 processor with 6-MB on-die L3 cache
A 16-bit 250-kHz delta-sigma modulator and decimation filter
In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations
Introduction to the Special Issue on the 2012 Symposium on VLSI Circuits
A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer
Offset-trimming bit-line sensing scheme for gigabit-scale DRAM's
A 250-622 MHz deskew and jitter-suppressed clock buffer using two-loop architecture
A 128×128-pixel standard-CMOS image sensor with electronic shutter