yusuke1997/dblp-id-title huggingface dataset:
Redundancy removal and test generation for circuits with non-Boolean primitives
TSAR-ILP: Tile-Based, Synchronization-AwaRe ILP Allocating Heterogeneous Platforms for Streaming Applications
Linear Decomposition of Approximate Multicontrolled Single Qubit Gates
Automatic interconnection rectification for SoC design verification based on the port order fault model
Critical path selection for performance optimization
A Software-Only Solution to Use Scratch Pads for Stack Data
Notes on "Complexity of the lookup-table minimization problem for FPGA technology mapping"
Register transfer level power optimization with emphasis on glitch analysis and reduction
Pulsed-Latch Aware Placement for Timing-Integrity Optimization
A synthesis for testability scheme for finite state machines using clock control
Reconfiguration techniques for a single scan chain
Testing and testable designs for one-time programmable FPGAs
A Monte Carlo Particle Study of the Intrinsic Noise Figure in GaAs MESFET's
The Variable Geometry Automated Universal Array Layout System (VGAUA)
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems
Fast Methodology for Time-Domain Analysis of Nonlinear-Loaded Transmission Line Excited by an Arbitrary Modulated Signal
Adaptive grid generation for VSLI device simulation
On optimal hyperuniversal and rearrangeable switch box designs
An Approach to Topological Pin Assignment
An efficient delay test generation system for combinational logic circuits
Design of Pin-Constrained General-Purpose Digital Microfluidic Biochips
Evaluating the reliability of NAND multiplexing with PRISM
PeF: Poisson's Equation-Based Large-Scale Fixed-Outline Floorplanning
Hotspot Detection via Attention-Based Deep Layout Metric Learning
Layout-Aware Multiple Scan Tree Synthesis for 3-D SoCs
Verified functions for generating signed-binary arithmetic hardware
NeuADC: Neural Network-Inspired Synthesizable Analog-to-Digital Conversion
Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models
Security in MPSoCs: A NoC Firewall and an Evaluation Framework
A Compiler-Microarchitecture Hybrid Approach to Soft Error Reduction for Register Files
Constant-time algorithms for the channel assignment problem on processor arrays with reconfigurable bus systems
EQ-ViT: Algorithm-Hardware Co-Design for End-to-End Acceleration of Real-Time Vision Transformer Inference on Versal ACAP Architecture
FDAM: Filter-Dedicated Approximate Multiplier Design for Real-Time CNN Acceleration
Analysis of mixed-signal systems with affine arithmetic
Massively parallel algorithms for scattering in optical lithography
Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis
TaintLock: Hardware IP Protection Against Oracle-Guided and Oracle-Reconstruction Attacks
Memory Carousel: LLVM-Based Bitwise Wear Leveling for Nonvolatile Main Memory
Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms
Design of multioutput CMOS combinational logic circuits for robust testability
Modeling and Optimization for Soft-Error Reliability of Sequential Circuits
The transition matrix for linear circuits
APmap: An Open-Source Compiler for Automata Processors
Online Rerouting and Rescheduling of Time-Triggered Flows for Fault Tolerance in Time-Sensitive Networking
Domain-Adaptive Online Active Learning for Real-Time Intelligent Video Analytics on Edge Devices
A Synthesis Approach for Coarse-Grained Antifuse-Based FPGAs
An accurate analytical delay model for BiCMOS driver circuits
Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops
From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration
A Compact Gated-Synapse Model for Neuromorphic Circuits
Reduced Worst-Case Communication Latency Using Single-Cycle Multihop Traversal Network-on-Chip
Datapath synthesis using a problem-space genetic algorithm
Monte Carlo Calculation of One- and Two-Dimensional Particle and Damage Distributions for Ion-Implanted Dopants in Silicon
Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL
A Class of Array Architectures for Hardware Grid Routers
Comments on "A small-signal MOSFET model for radio frequency IC applications"
Interconnect Bundle Sizing Under Discrete Design Rules
An Optimal Solution for the Heterogeneous Multiprocessor Single-Level Voltage-Setup Problem
GEM-Water: Generation of EM-Based Watermark With Hidden FSM for SoC IPs to Combat Piracy
Stochastic modeling of a power-managed system-construction andoptimization
A Dynamically Adjusting Gracefully Degrading Link-Level Fault-Tolerant Mechanism for NoCs
Semi-Individual Wire-Length Prediction With Application to Logic Synthesis
An Efficient Fault-Tolerant Valve-Based Microfluidic Routing Fabric for Droplet Barcoding in Single-Cell Analysis
HMC-FHE: A Heterogeneous Near Data Processing Framework for Homomorphic Encryption
Analog Models Manipulation for Effective Integration in Smart System Virtual Platforms
A Time, Energy, and Area Efficient Domain Wall Memory-Based SPM for Embedded Systems
PervasiveFL: Pervasive Federated Learning for Heterogeneous IoT Systems
Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution
DeepThings: Distributed Adaptive Deep Learning Inference on Resource-Constrained IoT Edge Clusters
Systolic temporal arithmetic: a new formalism for specification and verification of systolic arrays
A synthesis and optimization procedure for fully and easily testable sequential machines
Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits
RTL to Transistor Level Power Modeling and Estimation Techniques for FPGA and ASIC: A Survey
System-on-a-Chip (SoC)-Based Hardware Acceleration for an Online Sequential Extreme Learning Machine (OS-ELM)
Legalizing a placement with minimum total movement
A Statistical Model-Based Cell-to-Cell Variability Management of Li-ion Battery Pack
Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes
A BIST Scheme With the Ability of Diagnostic Data Compression for RAMs
An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles
Generating synthetic benchmark circuits for evaluating CAD tools
GPCB Routing: Generative Pretrained Transformers-Based Printed Circuit Board Routing Method
Constructing a Memristive Chaotic Oscillator With 2-D Offset Boosting
Runtime Efficiency-Accuracy Tradeoff Using Configurable Floating Point Multiplier
Using configurable computing to accelerate Boolean satisfiability
A parallel block iterative method for the hydrodynamic device model
Analog Integrated Circuit Topology Synthesis With Deep Reinforcement Learning
Ellipsoidal method for design centering and yield estimation
Improving the SSD Performance by Exploiting Request Characteristics and Internal Parallelism
A parallel multipole accelerated 3-D capacitance simulator based on an improved model
Selecting Representative Critical Paths for Sensor Placement Provides Early FPGA Aging Information
Compact modeling of BJT self-heating in SPICE
Parallelization of a Monte Carlo ion implantation simulator
The Road Not Taken: eFPGA Accelerators Utilized for SoC Security Auditing
Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking
Bridging fault modeling and simulation for deep submicron CMOS ICs
Recursive learning: a new implication technique for efficient solutions to CAD problems-test, verification, and optimization
Efficient and Robust RRAM-Based Convolutional Weight Mapping With Shifted and Duplicated Kernel
A partition and resynthesis approach to testable design of large circuits
A Tree Based Novel Representation for 3D-Block Packing
Floorplet: Performance-Aware Floorplan Framework for Chiplet Integration
Evaluating the Security of Logic-Locked Probabilistic Circuits
Minimizing total wire length by flipping modules
Analog Placement Based on Symmetry-Island Formulation
Efficient Hardware Design of Iterative Stencil Loops
Limitations of switch level analysis for bridging faults
Global rebuilding of OBDD's avoiding memory requirement maxima
Modeling and Simulation of Low-Frequency Noise in Nano Devices: Stochastically Correct and Carefully Crafted Numerical Techniques
A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators
A methodology for optimal repeater insertion in pipelined interconnects
Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Networks-on-Chip
Keeping Deep Lithography Simulators Updated: Global-Local Shape-Based Novelty Detection and Active Learning
Efficient Single-Layer Routing Along a Line of Points
Circular self-test path: a low-cost BIST technique for VLSI circuits
Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA
A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage
A Highly Routable ULM Gate Array and Its Automated Customizaton
PUF-Kyber: Design of a PUF-Based Kyber Architecture Benchmarked on Diverse ARM Processors
Test data compression and decompression based on internal scanchains and Golomb coding
Reconfigurable Physical Resource Block Using Novel - Beamforming Filter Circuit for LTE-Based Cell-Edge Terminals
Efficient design exploration based on module utility selection
Hot-Spot Suppression for Resource-Constrained Image Recognition Devices With Nonvolatile Memory
Context sensitive symbolic pointer analysis
A smoothed boundary condition for reducing nonphysical field effects
From IC Layout to Die Photograph: A CNN-Based Data-Driven Approach
An Optimal and Practical Approach to Single Constant Multiplication
Threshold Optimized DVR Model for RF Power Amplifier Using Particle Swarm Algorithm for 5G Application
A Pattern-Mining Method for High-Throughput Lab-on-a-Chip Data Analysis
An Efficient MOS Transistor Model for Computer-Aided Design
Two-stage channel routing for CMOS gate arrays
Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems
RefSCAT-2.0: Formal Verification of Large-Scale Optimized Multipliers via Quantum-Inspired Ant Colony Optimization-Based Reference Generation
A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing Mismatch
An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs
A Novel HDL Code Generator for Effectively Testing FPGA Logic Synthesis Compilers
Product Transformation and Heuristic EXOR-AND-OR Logic Synthesis of Incompletely Specified Functions
Specification, Synthesis, and Simulation of Transactor Processes
Numerical treatment of nonrectangular field-oxide for 3-D MOSFET simulation
Optimal intratask dynamic voltage-scaling technique and its practical extensions
Phoenix: A Dynamically Reconfigurable Hybrid Memory System Combining Caching and Migration
Safety Verification of Nonlinear Hybrid Systems Based on Bilinear Programming
Nonlinear driver models for timing and noise analysis
Optimizing large multiphase level-clocked circuits
Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging
Exact and Heuristic Approaches to Input Vector Control for Leakage Power Reduction
An algorithm for functional verification of digital ECL circuits
A Triple-Memristor Hopfield Neural Network With Space Multistructure Attractors and Space Initial-Offset Behaviors
Hybrid Evolutionary Design Space Exploration Algorithm With Defence Against Third Party IP Vulnerabilities
Algorithms for transient three-dimensional mixed-level circuit and device simulation
A Scalable 2T-1FeFET-Based Content Addressable Memory Design for Energy Efficient Data Search
Fast algorithm for polygon decomposition
An Approach to Solving Multiparticle Diffusion Exhibiting Nonlinear Stiff Coupling
GNN-Based Hierarchical Annotation for Analog Circuits
A generalized Scharfetter-Gummel method to eliminate crosswind effects [semiconduction device modeling]
Delivering global DC convergence for large mixed-signal circuits via homotopy/continuation methods
Accuracy of magnitude-class calculations in switch-level modeling
Trading-Off Accuracy and Energy of Deep Inference on Embedded Systems: A Co-Design Approach
Correctly Model the Diagonal Capacity in Escape Routing
Buffer Optimization in Network-on-Chip Through Flow Regulation
Search-in-Memory: Reliable, Versatile, and Efficient Data Matching in SSD's NAND Flash Memory Chip for Data Indexing Acceleration
MARS-a multilevel full-chip gridless routing system
Everything Leaves Footprints: Hardware Accelerated Intermittent Deep Inference
Sehwa: a software package for synthesis of pipelines from behavioral specifications
Simulating and testing oversampled analog-to-digital converters
MEEC Models for RFIC Design Based on Coupled Electric and Magnetic Circuits
ILPGRC: ILP-Based Global Routing Optimization With Cell Movements
Transition time modeling in deep submicron CMOS
Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations
System Level Performance Analysis for Real-Time Automotive Multicore and Network Architectures
Classified Round Robin: A Simple Prioritized Arbitration to Equip Best Effort NoCs With Effective Hard QoS
Architecture and synthesis for on-chip multicycle communication
EDA in IBM: past, present, and future
QLMOR: A Projection-Based Nonlinear Model Order Reduction Approach Using Quadratic-Linear Representation of Nonlinear Systems
LOCSTEP: a logic-simulation-based test generation procedure
Robust Deep Learning for IC Test Problems
Hiding Hardware Trojan Communication Channels in Partially Specified SoC Bus Functionality
High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures
Neural Rendering Acceleration With Deferred Neural Decoding and Voxel-Centric Data Flow
Two-dimensional impurity profiling with emission computed tomography techniques
Multiconstraint Static Scheduling of Synchronous Dataflow Graphs Via Retiming and Unfolding
Process-Variation-Aware Rule-Based Optical Proximity Correction for Analog Layout Migration
MDD: A Unified Model-Driven Design Framework for Embedded Control Software
FastGR: Global Routing on CPU-GPU With Heterogeneous Task Graph Scheduler
Aging-Aware Energy-Efficient Task Deployment of Heterogeneous Multicore Systems
Time-Domain Numerical Simulation of Electronic Circuits and Surface Acoustic Wave Devices Using Their Admittance Parameters
Exploiting communication complexity for Boolean matching
Optimal algorithms for recovery point insertion in recoverable microarchitectures
Region-Based and Panel-Based Algorithms for Unroutable Placement Recognition
A parasitics extraction and network reduction algorithm for analog VLSI
Network Pruning for Bit-Serial Accelerators
Symmetric Displacement Algorithms for the Timing Analysis of Large Scale Circuits
Clock Gating Synthesis of Pulsed-Latch Circuits
Statistical Simulation of the IC Manufacturing Process
CPU Address-Leakage Transient Execution Attack Detection and Its Countermeasures
Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate
Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks
On the Scaling of Temperature-Dependent Effects
New algorithms for circuit simulation of device breakdown
Algorithms for minimizing standby power in deep submicrometer, dual-V t CMOS circuits
Polynomial Neural Barrier Certificate Synthesis of Hybrid Systems via Counterexample Guidance
Ultralow Power Nonvolatile Logic Based on Spin-Orbit and Exchange Coupled Nanowires
New algorithms for the rectilinear Steiner tree problem
A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits
A provably good multilayer topological planar routing algorithm in IC layout designs
Computation of Seeds for LFSR-Based Diagnostic Test Generation
Direct mapping of RTL structures onto LUT-based FPGA's
QuickFPS: Architecture and Algorithm Co-Design for Farthest Point Sampling in Large-Scale Point Clouds
Architecting Decentralization and Customizability in DNN Accelerators for Hardware Defect Adaptation
On comparing functional fault coverage and defect coverage for memory testing
A New Paradigm of Common Subexpression Elimination by Unification of Addition and Subtraction
REIN the RobuTS: Robust DNN-Based Image Recognition in Autonomous Driving Systems
Measuring the Gap Between FPGAs and ASICs
Power grid analysis using random walks
Light-CIM: A Lightweight ADC/DAC-Fewer RRAM CIM DNN Accelerator With Fully Analog Tiles and Nonideality-Aware Algorithm for Consumer Electronics
Machine Learning for Power, Energy, and Thermal Management on Multicore Processors: A Survey
TRIM: testability range by ignoring the memory
Efficient Static-Driven Integration for Step-Function Transient Simulation
Modeling Approaches for Functional Verification of RF-SoCs: Limits and Future Requirements
CoaCAD: Correlation-Assisted Computer-Aided Design for Nonvolatile FPGAs
Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization
Circuit width, register allocation, and ordered binary decision diagrams
Structural Variance-Based Error-Tolerability Test Method for Image Processing Applications
A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits
Theory of latency-insensitive design
Computing observability don't cares efficiently through polarization
A realistic fault model and test algorithms for static random access memories
COCKTAIL: Multicore Co-Optimization Framework With Proactive Reliability Management
A gridless multilayer router for standard cell circuits using CTMcells
Fast and Correct Load-Link/Store-Conditional Instruction Handling in DBT Systems
Comprehensive Physical Design Flow Incorporating 3-D Connections for Monolithic 3-D ICs
Runtime Power Management of 3-D Multi-Core Architectures Under Peak Power and Temperature Constraints
TRASIM: compact and efficient two-dimensional transient simulator for arbitrary planar semiconductor devices
Correction to "Optimal State Assignment for Finite State Machines"
Logic Synthesis of Approximate Circuits
Run-Time Scheduling Framework for Event-Driven Applications on a GPU-Based Embedded System
Efficient Overdetection Elimination of Acceptable Faults for Yield Improvement
An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power
On Test Generation With Test Vector Improvement
Statistical Analysis of MUX-Based Physical Unclonable Functions
Timing verification using statically sensitizable paths
Synergistic HW/SW Approximation Techniques for Ultralow-Power Parallel Computing
Schematic generation with an expert system
Functionally Possible Scan-Based Test Set as a Dual of a Compressed Multicycle Test Set
Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
Symbolic generation of constrained random logic cells
VirtualSync+: Timing Optimization With Virtual Synchronization
Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches
Throughput Maximization in Wireless Communication Systems Powered by Hybrid Energy Harvesting
Channel ordering for VLSI layout with rectilinear modules
Addressing useless test data in core-based system-on-a-chip test
Minimum rectangular partition problem for simple rectilinear polygons
Closed-Form Delay and Crosstalk Models for RLC On-Chip Interconnects Using a Matrix Rational Approximation
ProperCAD: A portable object-oriented parallel environment for VLSI CAD
ELIXIR: An Expedient Connection Paradigm for Self-Powered IoT Devices
Through Silicon Via Aware Design Planning for Thermally Efficient 3-D Integrated Circuits
Enabling ILP-Based DSE for Multigranularity, Unified Domain Platforms With DmTSAR-ILP
An Algorithmic Study of Exact Route Matching for Integrated Circuits
Accelerating the compaction of test sequences in sequential circuits through problem size reduction
Implementation of a UMTS turbo decoder on a dynamically reconfigurable platform
A new approach to the pin assignment problem
Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration
Retiming Pulsed-Latch Circuits With Regulating Pulse Width
PROMETHEUS: A Proactive Method for Thermal Management of Heterogeneous MPSoCs
Hierarchical Multialgorithm Parallel Circuit Simulation
On the Impact of Within-Die Process Variation in GALS-Based NoC Performance
New Reconfigurable Architectures for Implementing FIR Filters With Low Complexity
Wiring space and length estimation in two-dimensional arrays
A Multichiplet Computing-in-Memory Architecture Exploration Framework Based on Various CIM Devices
Approximate Conformance Checking for Closed-Loop Systems With Neural Network Controllers
A Message-Passing Microcoded Synchronization for Distributed Shared Memory Architectures
Microword length minimization in microprogrammed controller synthesis
Algorithm/Hardware Co-Optimization for Sparsity-Aware SpMM Acceleration of GNNs
A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor
Robust and accurate hierarchical floorplanning with integrated global wiring
Layerwise Buffer Voltage Scaling for Energy-Efficient Convolutional Neural Network
Channel/switchbox definition for VLSI building-block layout
Optimizing AES Threshold Implementation Under the Glitch-Extended Probing Model
Simulation of microcrack effects in dissolution of positive resist exposed by X-ray lithography
Micromachined polysilicon power dissipation: simulation and experiment
A Modeling Method of Reverse Biased Electric Field for JBS Diodes Based on Schwarz-Christoffel Transformation
Optimal design of a CMOS op-amp via geometric programming
Geometric compaction on channel routing
Vision Transformer Acceleration via a Versatile Attention Optimization Framework
Harmony: static noise analysis of deep submicron digital integrated circuits
An efficient microcode compiler for application specific DSP processors
Data structuring for process and device simulations
Exposing Hardware Trojans in Embedded Platforms via Short-Term Aging
Efficient Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Geometric Reduction
VISTA-the data level
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis
Improving FPGA Placement With Dynamically Adaptive Stochastic Tunneling
Practical Integration of Process, Device, and Circuit Simulation
RAGS-real-analysis ALAP-guided synthesis
Novel Techniques for High-Sensitivity Hardware Trojan Detection Using Thermal and Power Maps
Automated Model-Based Assurance Case Management Using Constrained Natural Language
Corrections to "mogac: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems"
Transparent-Test Methodologies for Random Access Memories Without/With ECC
Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding
Reliability Analysis of Multiple-Outputs Logic Circuits Based on Structure Function Approach
Invariant States and Redundant Logic in Synchronous Sequential Circuits
Finite memory test response compactors for embedded test applications
Generalized Memristive Device SPICE Model and its Application in Circuit Design
Physically-Aware N-Detect Test
Performance optimization by gate sizing and path sensitization
Agile Simulation of Stochastic Computing Image Processing With Contingency Tables
Simulation of Nonlinear Circuits in the Frequency Domain
A simplified model for the effect of interfinger metal on maximum temperature rise in a multifinger bipolar transistor
Gemini+: Enhancing Real-Time Video Analytics With Dual-Image FPGAs
LDPC Level Prediction Toward Read Performance of High-Density Flash Memories
Detailed-Placement-Enabled Dynamic Power Optimization of Multitier Gate-Level Monolithic 3-D ICs