yusuke1997/dblp-id-title huggingface dataset:
High-Throughput Hardware Design for 3D-HEVC Disparity Estimation
Exploiting Execution Dynamics in Timing Analysis Using Job Sequences
The Road to Open-Source EDA
Guest Editor's Introduction: Design, Design Automation, and Test in Europe
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis
Parallel Discrete-Event Simulation
Software Quality Assurance And CAD User Interfaces
Security-Performance Trade-offs in Embedded Systems Using Flexible ECC Hardware
Time-to-Digital Converter Compiler for On-Chip Instrumentation
An EMG Denoising Method Based on Flexible Wearable Sensors
ViT-Reg: Regression-Focused Hardware-Aware Fine-Tuning for ViT on TinyML Platforms
Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation
Testing for Electromigration in Sub-5-nm FinFET Memories
Guest Editors' Introduction Challenges and Opportunities in Analog/Mixed-Signal CAD
Self-Aware On-Chip Systems
RT-Level ITC'99 Benchmarks and First ATPG Results
A Survey of Silicon Photonics for Energy-Efficient Manycore Computing
Exact Stochastic Computing Multiplication in Memristive Memory
Hardware/Algorithm Codesign for Adversarially Robust Deep Learning
The 1989 Annual Index
Saving Power by Synthesizing Gated Clocks for Sequential Circuits
A 100-GOPS Programmable Processor for Vehicle Vision Systems
Book Reviews: A Comprehensive EDA Handbook
Error Tolerance
IC Outlier Identification Using Multiple Test Metrics
Noise-Optimized Neuromorphic Spiking Radio in Context-Aware IoT
Virtual Simulation of Distributed IP-Based Designs
Reconfiguring the Bioinformatics Computational Spectrum: Challenges and Opportunities of FPGA-Based Bioinformatics Acceleration Platforms
Full Key Extraction of SNOW-V Using ML-Assisted Power SCA
On the Relation Between Reliability and Entropy in Physical Unclonable Functions
Energy-Efficient Computing in Nanoscale CMOS
A second course on testing [review of System on Chip Test Architectures (Wang, L.-T et al., Eds.; 2007)]
Clarifying the record on testability cost functions
An EDA compendium
An Interview With Semiconductor Pioneer and EDA Visionary Leader Wally Rhines
Product Health Insights Using Telemetry
Probing Attacks on Integrated Circuits: Challenges and Research Opportunities
Robust Circuit Design for Flexible Electronics
Guest Editor's Introduction: Examples of Management Decision Criteria
N.mPc: A Study in University-Industry Technology Transfer
Fault: Open-Source EDA's Missing DFT Toolchain
1997 Asian Test Symposium
Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System
Fred Terman, the Father of Silicon Valley
Major Milestones for Two IEEE Standards Groups in 2011
A Case Study of Signal-to-Noise Ratio in Ring-Based Optical Networks-on-Chip
Designing a Cyber-Physical System for Fall Prevention by Cortico-Muscular Coupling Detection
Understanding Error Propagation in Deep-Learning Neural Networks' Accelerators and Applications
What Makes a Good Standard?
Guest Editor's Introduction: VHDL and Next-Generation Design Automation
Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis
Dynamic Statistical Control of Manufacturing Test
The Last Byte: Are You Sure You Love That Store?
The 55th Design Automation Conference
Algorithms for high-level synthesis
Guest Editors' Introduction: Configurable Computing
The Redesign System: A Knowledge-Based Approach to VLSI CAD
Efficient Parametric Fault Detection in Switched-Capacitor Filters
Bringing up a chip on the cheap
Analysis and Implementation of Practical, Cost-Effective Networks on Chips
Not just research as usual
Concurrent Checking of Clock Signal Correctness
Heterogeneous MPSoCs for Mixed-Criticality Systems: Challenges and Opportunities
Concurrent Device/Specification Cause-Effect Monitoring for Yield Diagnosis Using Alternate Diagnostic Signatures
Guest Editors' Introduction: Special Issue on Time-Critical Systems Design
Automating PBX System Testing
Localizing Multiple Faults in a Protocol Implementation
The Design Automation Conference and the Early Days of EDA
Test Length in a Self-Testing Environment
3D Test
An Energy-Aware Nanoscale Design of Reversible Atomic Silicon Based on Miller Algorithm
Cell Phone Integration: SiP, SoC, and PoP
Leakage Power Contributor Modeling
Economics of Built-in Self-Test
Chip-Package Codesign Flow for Mixed-Signal SiP Designs
Losing control
Too Many Cooks Make the Product
Guest Editors' Introduction: Application-Specific Microprocessors
A Survey of Hardware Accelerators Used in Computer-Aided Design
Guest Editors' Introduction: Competing to Secure SoCs
Creating Structural Patterns for At-Speed Testing: A Case Study
Synthesizing Multiple Scan Trees to Optimize Test Application Time
PortLoc: A Portable Data-Driven Indoor Localization Framework for Smartphones
Déjà vu, all over again
On-Chip Digital Jitter Measurement, from Megahertz to Gigahertz
1985 to 1987: My years with D&T
Metastable Behavior in Digital Systems
Test Solution Selection Using Multiple-Objective Decision Models and Analyses
Test for Automotive
Wider Coverage
Internet of Things - The Quest for Trust
Guest Editors' Introduction: Special Issue on Top Picks in Hardware and Embedded Security
Fast Analysis Using Finite Queuing Model for Multilayer NoCs
VLSI design
Self-Sustainable Wearable and Internet of Things (IoT) Devices for Health Monitoring: Opportunities and Challenges
Paperless Design and Test
Fault Models and Tests for a 2-Bit-per-Cell MLDRAM
Low-Power Electronics
Holding Conferences Online due to COVID-19: The DATE Experience
Measuring System Design and Experimental Research on Electrostatic Attractive Force
Guest Editor's Introduction: Formal Verification of Commercial Integrated Circuits
Modeling, Architecture, and Applications for Emerging Memory Technologies
SAT-Based Analysis of Sensitizable Paths
Conference Reports: Recap of the 37th Edition of the International Conference on Computer-Aided Design (ICCAD 2018)
The Hybrid Field-Programmable Architecture
The Emerging Majority: Technology and Design for Superconducting Electronics
Three Decades of HDLs: Part II, Conlan Through Verilog
Total and Peak Energy Consumption Minimization of Building HVAC Systems Using Model Predictive Control
Automatic Test Program Generation: A Case Study
Book Reviews: Test Tutorials in Book Form
Evolution of the electronic design automation industry
Analyzing the Impact of Intermittent Faults on Microprocessors Applying Fault Injection
Verification synergies
Designing and Debugging Custom Computing Applications
Cybersecurity for Control Systems: A Process-Aware Perspective
Hybrid-SBST Methodology for Efficient Testing of Processor Cores
Path to Eco-Driving: Electric Vehicle HVAC and Route Joint Optimization
Flexible and Portable Management of Secure Scan Implementations Exploiting P1687.1 Extensions
Empirical Validation of Yield Recovery Using Idle-Cycle Insertion
A Comparative Study of State-of-the-Art High-Performance Spectral Test Methods
Test Trade-Offs Take Center Stage at ITC
Reliability of Deep Neural Networks: Impact and Open Issues
Architecture and Design of Multichannel Millimeter-Wave Wireless NoC
Our Gated Community
Guest Editor's Introduction: What is Infrastructure IP?
Hardware Accelerator for Runtime Temperature Estimation in Many-Cores
The Five Stages of Project Grief
Deep-Submicron Challenges
Diagnosing IC Failures in a Fast Environment
An Energy-Efficient Silicon Microring Resonator-Based Photonic Transmitter
Two Approaches to Handling Late Essential/Necessary Patent Claims Against Standards
Fault-Tolerant Neuromorphic Computing With Memristors Using Functional ATPG for Efficient Recalibration
Selective Hardening: Toward Cost-Effective Error Tolerance
Intelligent Chargers Will Make Mobile Devices Live Longer
Guest Editor's Introduction: Multimedia Drives Changes
Designing in the multimedia era
On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs
EM-Based On-Chip Aging Sensor for Detection of Recycled ICs
A data structure for fast region searches
Identifying Untestable Faults in Sequential Circuits
Implementing Macro Test in Silicon Compiler Design
Survey of Automotive Controller Area Network Intrusion Detection Systems
Poirot: Applications of a Logic Fault Diagnosis Tool
Précis: A Usercentric Word-Length Optimization Tool
From the EIC: Secure Automotive Systems
Using a Test-Specification Format in Automatic Test-Program Generation
Self-Aware Thermal Management for High-Performance Computing Processors
Towards more digital content in wireless systems [From the EiC]
Guest Editors' Introduction: Secure Automotive Systems
Web-Based Energy Exploration Tool for Embedded Systems
A Method for Consistent Fault Coverage Reporting
Functional Testing and Repair for ReRAM-Based Deep-Learning Accelerators
Designing Fault-Tolerant Photovoltaic Systems
Inserting Scan at the Behavioral Level
The Greatest "Tech-Onomic Push-Pull" in Human History
Codesign of Embedded Systems: Status and Trends
A Design-for-Verification Technique for Functional Pattern Reduction
A GALS Infrastructure for a Massively Parallel Multiprocessor
SuBhI: Securing Embedded System's Runtime Integrity via Behavioral Information
Managing Power
Robustness for 3-D Circuits - Industrial Perspectives
Low-Cost Testing of High-Density Logic Components
Ultralow Power and the New Era of Not-So-VLSI
Three Generations of Asynchronous Microprocessors
Microprocessor Software-Based Self-Testing
Protected Shared Variables in VHDL: IEEE Standard 1076a
Special Issue on Benchmarking Machine Learning Systems and Applications
Guest Editors' Introduction: Intelligent Resource-Constrained Sensor Nodes
Special Issue on Near-Memory and In-Memory Processing
An ATE System for Testing RF Digital Communication Devices With QAM Signal Interfaces
Testing of Stuck-Open Faults in Nanometer Technologies
An Automatic DFT System for the Silc Silicon Compiler
Panel Summaries: Real-Time Volume Diagnostics--Requirements and Challenges
Using a Soft Core in a SoC Design: Experiences with picoJava
IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions
Verification evolution or industrial revolution?
Date 98
Data-Driven Formal Reasoning and Their Applications in Safety Analysis of Vehicle Autonomy Features
Special Issue on Silicon Lifecycle Management
Hitest: A Knowledge-Based Test Generation System
Applying an XC6200 to Real-Time Image Processing
ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon
Revisiting DAC's 50th Anniversary
DAC Turns 40!
ITC and the Future of Test - We've Won
Looking back, looking around
Scaling: More than Moore's law
Combining synchronous and asynchronous timing schemes for high-performance systems
A Built-in Method to Repair SoC RAMs in Parallel
A Complete Strategy for Testing an On-Chip Multiprocessor Architecture
VHDL Motivation
Who Reads This Stuff Anyway?
Analog Signature- Driven Postmanufacture Multidimensional Tuning of RF Systems
Standards: Technical activities in Accellera
Design Challenges for New Application-Specific Processors
Prototyping the M68060 for Concurrent Verification
Optimizing VHDL Compilation for Parallel Simulation
Fault Isolation in an Integrated Diagnostic Environment
Guest Editors' Introduction: Yield Learning Processes and Methods
Fast-Write Resistive RAM (RRAM) for Embedded Applications
Current-Based Testing for Deep-Submicron VLSIs
Embedded DRAM in 45-nm Technology and Beyond
Crosstalk- and SEU-Aware Networks on Chips
Development of Building Automation and Control Systems
Three Misconceptions Regarding Standards
High-Performance Deterministic Stochastic Computing Using Residue Number System
Improving SoC Design Quality through a Reproducible Design Flow
High-Level Synthesis: Status, Trends, and Future Directions
Design for Test and Time to Market: A Personal Perspective
Technological Benchmark of Analog Synaptic Devices for Neuroinspired Architectures
Guest Editor's Introduction: Roadmaps and Visions for Design and Test
Exploring NoC-Based MPSoC Design Space with Power Estimation Models
A Case Study in Embedded-System Design: The VuMan 2 Wearable Computer
Safety Ethics for Design and Test of Automated Driving Features
Rapid Prototyping of High-Speed Communications Chips
Data Attack Detection and Command Authentication via Cyber-Physical Comodeling
A Strategy for Mixed-Signal Yield Improvement
On-Chip RF Phased Array Characterization with DC-Only Measurements for In-Field Calibration
Design and Test of Large Embedded Memories: An Overview
GPU-Accelerated Soft Error Rate Analysis of Large-Scale Integrated Circuits
Best in Test
Economic Effects in Design and Test
Expanding Column Line Code Adaptive (CLC-A) for Protecting 32-and 64-Bit Data
CFI leads development of design data standard
2018 Embedded Systems Week (ESWEEK) in Torino
2D Test Sequence Generators
Design and Test of Innovative Three-Couplers-Based Bandpass Negative Group Delay Active Circuit
Computers with Tailfins?
Innovative Failure Analysis Techniques for 3-D Packaging Developments
How to make your own processor architecture
Toward a Standard Hardware Description Language
Security and Privacy in Cyber-Physical Systems: A Survey of Surveys
Robust On-Chip Signaling by Staggered and Twisted Bundle
Survey of Test Vector Compression Techniques
The importance of innovation in the economy of advanced countries
Guest Editors' Introduction: Green Buildings
A New Economical Implementation for Scannable Flip-Flops in MOS
Alpha 21164 Manufacturing Test Development and Coverage Analysis
Thinking About Adopting IEEE P1687?
Power Supply Noise: A Survey on Effects and Research
A D&T Roundtable: System Test-What, Why, and How?
A testability strategy for multiprocessor architecture
Silicon-Proven Timing Signoff Methodology Using Hazard-Free Robust Path Delay Tests
Fast Power Estimation of Large Circuits
Implementing and Managing a CAD System Based on Vendor-Supplied Tools
Scan Integrity Tests for EDT Compression
Cyber-Physical System Design With Sensor Networking Technologies
Transitioning Desktops to Set Tops
Training Large-scale Artificial Neural Networks on Simulated Resistive Crossbar Arrays
Linking the Verification and Validation of Complex Integrated Circuits Through Shared Coverage Metrics
Report of the 2016 Embedded Systems Week (ESWEEK)
Affordable and Comprehensive Testing of 3-D Stacked Die Devices
1993 Annual Index: Complete author and subject listing
Automating IEEE 1500 Core Test—An EDA Perspective
Designing in Power-Down Test Circuits
Power Analysis Attacks and Countermeasures
Crypto-DSEDA: A Domain-Specific EDA Flow for CiM-Based Cryptographic Accelerators
From Less Batteries to Battery-Less Alert Systems with Wide Power Adaptation down to nWs - Toward a Smarter, Greener World
Impact of Orientation on the Bias of SRAM-Based PUFs
Implementing Embedded Security on Dual-Virtual-CPU Systems
High Defect Coverage with Low-Power Test Sequences in a BIST Environment
Automotive Cyber-Physical Systems: A Tutorial Introduction
Modeling Process Variability in Scaled CMOS Technology
A Production IR-Drop Screen on a Chip
Book Reviews: A guide for the wrapper perplexed
Asynchronous Circuits for Low Power: A DCC Error Corrector
A Common Language Framework for Next-Generation Embedded Testing
Adapt&Cap: Coordinating System- and Application-Level Adaptation for Power-Constrained Systems
Report on First and Second ACM/IEEE Workshop on Machine Learning for CAD (MLCAD)
KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications
Guest Editors' Introduction: More Practical Asynchronous Design
The continuing evolution of EDA standards
The Future Depends on Innovation: An Interview with Irwin M. Jacobs, cofounder, chairman, and CEO of Qualcomm
Tracking Uncertainty with Probabilistic Logic Circuit Testing
Know Your Channel First, then Calibrate Your mmWave Phased Array
Prototype Debug using ATE
Chips That Do Things
The Joys of Open-Source Hardware
Practices in Mixed-Signal and RF IC Testing
Linking Simulation with Formal Verification at a Higher Level
Fast Template Placement for Reconfigurable Computing Systems
An Automatic Test-Generation System for Large Digital Circuits
Interview With Vishwani Agrawal
The VIVID Symbolic Design System: Current Overview And Future Directions
A D&T Roundtable: Deep-Submicron Test in cooperation with the Test Technology Technical Committee
A Survey of Digital Design Reuse
A D&T Roundtable: The Practical Application of Formal Verification
EdgeAl: A Vision for Deep Learning in the IoT Era
The GSRC's Role in Meeting Tomorrow's Design Challenges
High-Performance HBM Known-Good-Stack Testing
Processor Stew (review of Processor Description Languages by P. Mishra and N. Dutt, Eds.; 2008) [Book reviews]
Guest editors' introduction: Nanoscale Memories Pose Unique Challenges
PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning
Sharing standards work with Japan
Hardware/Software Codesign and Rapid Prototyping of Embedded Systems
Fast Prototyping of Datapath-Intensive Architectures
Wafer Test Methods to Improve Semiconductor Die Reliability
Hard-Sign: A Hardware Watermarking Scheme Using Dated Handwritten Signature
To Verification Infinity and Beyond
Asymmetric Aging and Workload Sensitive Bias Temperature Instability Sensors
NSF Workshop on EDA: Past, Present, and Future (Part 1)
Recap of the ITC15 Test Conference
Technology Mapping in Circuit Design Aids
The 41st IEEE VLSI Test Symposium
A Top-Down Methodology for Microprocessor Validation
Characterizing Substrate Coupling in Deep-Submicron Designs
A Fault-Driven, Comprehensive Redundancy Algorithm
Storage and Caching: Synthesis of Flow-Based Microfluidic Biochips
Characterization and Testing of Physical Failures in MOS Logic Circuits
A Metamodel for Studying Concepts in Electronic System Design
Security in SRAM FPGAs
Understanding Yield Losses in Logic Circuits
Concurrent Error Detection Using Monitoring Machines
Seven Strategies for Tolerating Highly Defective Fabrication
Aging-Aware Power or Frequency Tuning With Predictive Fault Detection
A VHDL Fault Diagnosis Tool Using Functional Fault Models
Guest Editors' Introduction: Special Issue on EDA Industry Standards
Guest Editors' Introduction: Robust 3-D Stacked ICs
IC Phone Home!
A D&T Special Report: P1149.4 Mixed-Signal Test Bus
Goalie: A Space Efficient System for VLSI Artwork Analysis
Net Scheduling in High-Level Synthesis
Formal Models for Embedded System Design
Opportunities and Challenges for Smarter Mobile Devices
Design and Test of Core-Based Systems on Chips
Intelligent IoT Motes: Preventing Their Abuse at the Weakest Entry Point
An Automated Low-Cost Analog and Mixed-Signal DfT Method Using Testing Diodes
In Vitro Long-Term Performance Evaluation and Improvement in the Response Time of CMOS-Based Implantable Glucose Sensors
Testing for Multiple Faults in Deep Neural Networks
Reengineering Legacy Embedded Systems
Designing and Verifying Embedded Microprocessors
Online Self-Repair of FIR Filters
Design and Test Education in Latin America
Using Ada as an HDL
Functional Fault Models for Analog Circuits
Advances in Forensic Data Acquisition
RF Front-End Test Using Built-in Sensors
FSA SiP Market and Patent Analysis Report
A Large-Area Integrated Multiprocessor System for Video Applications
The Last Byte: Big Data, Big Faults
International Mixed-Signal Testing Workshop 1999
DAC: Serving the EDA Community for 40 Years
Engineering Secure Internet of Things Systems
How Useful are the ITC 02 SoC Test Benchmarks?
A World Without Standards
MOSFET Mismatch Modeling: A New Approach
Automated Source-Level Error Localization in Hardware Designs
Reducing Power Dissipation, Delay, and Area in Logic Circuits by Narrowing Transistors
Faults, Injection Methods, and Fault Attacks
ITC 2003: Breaking Test Interface Bottlenecks
Model-Based Optimization of Individualized Deep Brain Stimulation Therapy
Testing and Characterization of SDRAMs
Validating the Itanium 2 Exception Control Unit: A Unit-Level Approach
Computing-In-Memory Using Ferroelectrics: From Single- to Multi-Input Logic
Guest Editors' Introduction: Compact Variability Modeling in Scaled CMOS Design
Energy Optimization for Latency- and Quality-Constrained Video Applications
A Unified Design Methodology for Offline and Online Testing
Pass and Run: A Privacy Preserving Delay Tolerant Network Communication Protocol for CyberVehicles
Hardware IP Protection During Evaluation Using Embedded Sequential Trojan
EDA: Synergy or sum of the parts? [review of "Electronic Design Automation: Synthesis, Verification and Test (Systems on Silicon" (Wang, L.-T., Eds., et al; 2009)]
Enabling Rapid Construction of Arrival Curves From Execution Traces
Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits
Disaster Recovery Centers
Employing the STDF V4-2007 Standard for Scan Test Data Logging
Nano-Tera.ch: Information Technology for Health, Environment, and Energy
Self-Tested Data Flow Logic: A New Approach
Conference Reports: Recap of DATE 2019 in Florence, Italy
Energy Efficiency Like Your Momma Used to Make
New beginnings, continued success
Computing with High-Dimensional Vectors
A Study on Confidence: An Unsupervised Multiagent Machine Learning Experiment
Challenges and Directions for Low-Voltage SRAM
Special Issue on the 2023 Symposium on Integrated Circuits and Systems Design
A Survey on Machine Learning Accelerators and Evolutionary Hardware Platforms
Report on the 2023 Embedded Systems Week (ESWEEK)
A Survey on Energy Management for Mobile and IoT Devices
High-Performance Asynchronous Pipelines: An Overview
The Scientific Method and Design and Test
Low-Power Design Solutions forWireless Multimedia SoCs
Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings
Characterization of Equalized and Repeated Interconnects for NoC Applications
Highlights of ICCAD 2016
Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits
Combining Theorem Proving with Model Checking through Predicate Abstraction
Recap of the 53rd Design Automation Conference (DAC)
Comprehensive Approach to High-Performance Server Chipset Debug
An Illustrated Methodology for Analysis of Error Tolerance
Silicon Nanophotonics for Future Multicore Architectures: Opportunities and Challenges
Minutes Found on a Cave Wall
Correlated Effects on Forming and Retention of Al Doping in HfO 2 -Based RRAM
Silicon for embedded multimedia processing
2006 Latin American Test Workshop
UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting
RF Leakage in Embedded Devices: Security and Reliability Risks
Design Synthesis and Silicon Compilation
Boundary-Scan Update: IEEE P1149.2 Description and Status Report
Scalable One-Pass Synthesis for Digital Microfluidic Biochips
Recap of the 22nd Asia and South- Pacific Design Automation Conference
Handling variations and uncertainties
Computer-Aided Design and Test for Digital Microfluidics
Testing in 2100
Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors
A Rule-Based System for Optimizing Combinational Logic
Split-Chip Design to Prevent IP Reverse Engineering
Efficient System-Level Functional Verification Methodology for Multimedia Applications
An Automatic Technique for Optimizing Reed-Solomon Codes to Improve Fault Tolerance in Memories
Automatic Generation of Parallel CRC Circuits
Guest Editors' Introduction: Cyber-Physical Systems Security and Privacy
The Magic VLSI Layout System
SeMAP - A Method to Secure the Communication in NoC-Based Many-Cores
Observable Time Windows: Verifying High-Level Synthesis Results
Metamodels in Europe: Languages, Tools, and Applications
Security of Emergent Automotive Systems: A Tutorial Introduction and Perspectives on Practice
A Programmable BIST Core for Embedded DRAM
Analyzing Manufacturing Test Costs
ISCA: Intelligent Sense-Compute Adaptive Co-Optimization of Multimodal Machine Learning Kernels for Resilient mHealth Services on Wearables
A Comprehensive Design-for-Test Infrastructure in the Context of Security-Critical Applications
Leveraging RISC-V for HW/SW Codesign of Flexible and Efficient TinyML SoCs
Hardware Virtualization and Task Allocation for Plug-and-Play Automotive Systems
Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects
Interview With Janusz Rajski