yusuke1997/dblp-id-title huggingface dataset:
Two-dimensional process simulation using verified phenomenological models
PartGen: a generator of very large circuits to benchmark thepartitioning of FPGAs
Effective Corner-Based Techniques for Variation-Aware IC Timing Verification
Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking
Computationally efficient and accurate capacitance model for the GaAs MESFET for microwave nonlinear circuit design
Time-domain macromodels for VLSI interconnect analysis
A simple, continuous, analytical charge/capacitance model for the short-channel MOSFET
Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator
A Novel Fast Layout Encoding Method for Exact Multilayer Pattern Matching With Prüfer Encoding
An Efficient Placement Speedup Technique Based on Graph Signal Processing
Computation of floating mode delay in combinational circuits: practice and implementation
MOSFET global modeling for deep submicron devices with a modified BSIM1 SPICE model
A New Compact Model for Third-Order Memristive Neuron With Box-Shaped Hysteresis and Dynamics Analysis
CARTAD: Compiler-Assisted Reinforcement Learning for Thermal-Aware Task Scheduling and DVFS on Multicores
ReLAccS: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems
Verification algorithms for VLSI synthesis
An Algorithm for Synthesis of Reversible Logic Circuits
Fast factorization method for implicit cube set representation
An Adaptive Memory-Side Encryption Method for Improving Security and Lifetime of PCM-Based Main Memory
Test planning for modular testing of hierarchical SOCs
Parallel Static Learning Toward Heterogeneous Computing Architectures
RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors
SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives
Equivalent waveform propagation for static timing analysis
Advancing Neuromorphic Architecture Toward Emerging Spiking Neural Network on FPGA
A reliable and efficient procedure for oscillator PPV computation, with phase noise macromodeling applications
SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings
System-Level Modeling and Analysis of Thermal Effects in WDM-Based Optical Networks-on-Chip
An Efficient Method of Sampling for Statistical Circuit Design
Stress Aware Layout Optimization Leveraging Active Area Dependent Mobility Enhancement
On-chip embedding mechanisms for large sets of vectors for delay test
Fault-Tolerant Topology Generation Method for Application-Specific Network-on-Chips
Wire sizing as a convex optimization problem: exploring the area-delay tradeoff
Data-Flow Graph Mapping Optimization for CGRA With Deep Reinforcement Learning
Algorithms and Software Tools for IC Yield Optimization Based on Fundamental Fabrication Parameters
BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs
Analysis and verification of power grids considering process-induced leakage-current variations
Extraction of two-node bridges from large industrial circuits
Energy- and performance-aware mapping for regular NoC architectures
The excess capacitance of a microstrip via in a dielectric substrate
SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement
A controller redesign technique to enhance testability of controller-data path circuits
Allocation of Multibit Retention Flip-Flops for Power Gated Circuits: Algorithm-Design Unified Approach
FDPUF: Frequency-Domain PUF for Robust Authentication of Edge Devices
Block-Level Hardware Logic Simulation Machine
Controller-based power management for control-flow intensive designs
Hierarchical Analog/Mixed-Signal Circuit Optimization Under Process Variations and Tuning
CU.POKer: Placing DNNs on WSE With Optimal Kernel Sizing and Efficient Protocol Optimization
Addressing design for testability at the architectural level
Simulation of multiconductor transmission lines using Krylov subspace order-reduction techniques
A temperature-aware simulation environment for reliable ULSI chipdesign
Energy-Aware Mixed-criticality Sporadic Task Scheduling Algorithm
On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures
Efficient Symbolic Computation for Word-Level Abstraction From Combinational Circuits for Verification Over Finite Fields
A Noise-Driven Heterogeneous Stochastic Computing Multiplier for Heuristic Precision Improvement in Energy-Efficient DNNs
Sampled data simulation of linear and nonlinear circuits
Verifying Coalitions in 3-Party Systems
Single-layer global routing
A High-Efficiency Power Obfuscation Switched-Capacitor DC-DC Converter Architecture
Exact algorithms for multilayer topological via minimization
BSG-Route: A Length-Constrained Routing Scheme for General Planar Topology
A Sub- 10 μs In-Memory-Search Collision Detection Accelerator Based on RRAM-TCAMs
High-level current macro model for logic blocks
A neural network approach to topological via-minimization problems
Echelon: a multilayer detailed area router
Small Sampling Overhead Error Mitigation for Quantum Circuits
Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs
A beta model for estimating the testability and coverage distributions of a VLSI circuit
Three-dimensional capacitance evaluation on a Connection Machine
Voltage- and current-based fault simulation for interconnect open defects
Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure
Incremental SAT-Based Accurate Auto-Correction of Sequential Circuits Through Automatic Test Pattern Generation
A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache System
A CAD procedure for optimizing bipolar devices relative to BiCMOS circuit delays
Control unit synthesis from a high-level language
Multilayer Perceptron-Based Stress Evolution Analysis Under DC Current Stressing for Multisegment Wires
Extraction of MOSFET Parameters Using the Simplex Direct Search Optimization Method
Architectural synthesis for DSP silicon compilers
Interface finite-state machines: definition, minimization, and decomposition
iFKVS: Lightweight Key-Value Store for Flash-Based Intermittently Computing Devices
The CoveRT Approach for Coverage Management in Analog and Mixed-Signal Integrated Circuits
Accurate and efficient modeling of SOI MOSFET with technology independent neural networks
Multiple Subpage Writing FTL in MLC by Exploiting Dual Mode Operations
Data dependency size estimation for use in memory optimization
Efficient formulation and model-order reduction for the transient simulation of three-dimensional VLSI interconnect
Design of hierarchical cellular automata for on-chip test pattern generator
Ion Implantation Calculations in Two Dimensions Using the Boltzmann Transport Equation
Selective Flip-Flop Optimization for Reliable Digital Circuit Design
NetVGE: Netwise Hardware Trojan Detection at RTL Using Variable Dependency and Knowledge Graph Embedding
Pin Accessibility Prediction and Optimization With Deep-Learning-Based Pin Pattern Recognition
Efficient Quantum Circuit Synthesis for SAT-Oracle With Limited Ancillary Qubit
Mixing Models as Integer Factorization: A Key to Sample Preparation With Microfluidic Biochips
Conditionally robust two-pattern tests and CMOS design for testability
Analytical Post-Voiding Modeling and Efficient Characterization of EM Failure Effects Under Time-Dependent Current Stressing
Watermarking graph partitioning solutions
A Framework for Energy-Consumption-Based Design Space Exploration for Wireless Sensor Nodes
GPOS: A General and Precise Offloading Strategy for High Generality of DNN Acceleration by OCP and NDP Co-Optimizing
Schedulability Analysis of Engine Control Systems With Dynamic Switching Speeds
BDD minimization using symmetries
Detectability of CMOS stuck-open faults using random and pseudorandom test sequences
Reconditioning: A Framework for Automatic Power Optimization of QDI Circuits
Accelerating Static Timing Analysis Using CPU-GPU Heterogeneous Parallelism
FreePrune: An Automatic Pruning Framework Across Various Granularities Based on Training-Free Evaluation
Enabling Weakly Supervised Temporal Action Localization From On-Device Learning of the Video Stream
Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method
SAT-based counterexample-guided abstraction refinement
Workload-Aware Elastic Striping With Hot Data Identification for SSD RAID Arrays
Automatic verification of implementations of large circuits against HDL specifications
Soft-Error-Rate-Analysis (SERA) Methodology
Cascade: An Application Pipelining Toolkit for Coarse-Grained Reconfigurable Arrays
A macromodeling algorithm for analog circuits
Mating Sensitivity Analysis and Statistical Verification for Efficient Yield Estimation
GAN-OPC: Mask Optimization With Lithography-Guided Generative Adversarial Nets
Emerging simulation approaches for micromachined devices
Congestion-aware topology optimization of structured power/ground networks
TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis
Time-Triggered Switch-Memory-Switch Architecture for Time-Sensitive Networking Switches
ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits
MacLeR: Machine Learning-Based Runtime Hardware Trojan Detection in Resource-Constrained IoT Edge Devices
Fault diagnosis and logic debugging using Boolean satisfiability
Timing-Aware Fill Insertions With Design-Rule and Density Constraints
Single-Row Routing in Narrow Streets
A Divide-And-Conquer Pebbling Strategy for Oracle Synthesis in Quantum Computing
An efficient test relaxation technique for synchronous sequential circuits
A new method for hierarchical compaction [VLSI]
Self-Test Library Generation for In-Field Test of Path Delay Faults
Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structures
Noise Sensitivity-Based Energy Efficient and Robust Adversary Detection in Neural Networks
Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line system
Multivoltage Floorplan Design
Standing on the Shoulders of Giants: Hardware and Neural Architecture Co-Search With Hot Start
Symbolic debugging of embedded hardware and software
Mixed-Cell-Height Placement With Complex Minimum-Implant-Area Constraints
Module relocation to obtain feasible constrained floorplans
SPICE Compact BJT, MOSFET, and JFET Models for ICs Simulation in the Wide Temperature Range (From -200 °C to +300 °C)
A knowledge-based system for the evaluation and redesign of digital circuit networks
Enabling High-Level Synthesis Resource Sharing Design Space Exploration in FPGAs Through Automatic Internal Bitwidth Adjustments
An MOS transistor charge model for VLSI design
A Distributed Heuristic Algorithm for the Rectilinear Steiner Minimal Tree Problem
On symbolic model order reduction
Path delay fault diagnosis and coverage-a metric and an estimationtechnique
Reliable Radix-4 Complex Division for Fault-Sensitive Applications
Gibbon: An Efficient Co-Exploration Framework of NN Model and Processing-In-Memory Architecture
Hierarchical algorithm partitioning at system level for an improved utilization of memory structures
NEMO: A New Implicit-Connection-Graph-Based Gridless Router With Multilayer Planes and Pseudo Tile Propagation
Magnifier: A Chiplet Feature-Aware Test Case Generation Method for Deep Learning Accelerators
iSAFE: Enabling Evenness of Data Freshness in Multipriority Networked Intermittent Systems
The invention of CMOS amplifiers using genetic programming and current-flow analysis
GALLO: a genetic algorithm for floorplan area optimization
Sequential Test Generation Based on Preferred Primary Input Cubes
Analytical charge-control and I-V model for submicrometer anddeep-submicrometer MOSFETs fully comprising quantum mechanical effects
Reactant and Waste Minimization in Multitarget Sample Preparation on Digital Microfluidic Biochips
Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation
SENTunnel: Fast Path for Sensor Data Access on Automotive Embedded Systems
A Reactive and Cycle-True IP Emulator for MPSoC Exploration
NOBtree: A NUMA-Optimized Tree Index for Nonvolatile Memory
Improving Computing Systems Automatic Multiobjective Optimization Through Meta-Optimization
A Progressive-ILP-Based Routing Algorithm for the Synthesis of Cross-Referencing Biochips
Runtime Task Scheduling Using Imitation Learning for Heterogeneous Many-Core Systems
A Macromodeling Approach for Analog Behavior of Digital Integrated Circuits
Resistance Estimation for Lateral Power Arrays Through Accurate Netlist Generation
Exploration and Optimization of 3-D Integrated DRAM Subsystems
Graceful Space Degradation: An Uneven Space Management for Flash Storage Devices
A faster compaction algorithm with automatic jog insertion
Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy
Revive Bad Flash-Memory Pages by HLC Scheme
When Storage Response Time Catches Up With Overall Context Switch Overhead, What Is Next?
Two-Dimensional Schemes for Clocking/Timing of QCA Circuits
Formal Verification of Virtualization-Based Trusted Execution Environments
Energy-Efficient Real-Time UAV Object Detection on Embedded Platforms
Symmetry-Eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures
Layer assignment for VLSI interconnect delay minimization
Design of Optimal Multiplierless FIR Filters With Minimal Number of Adders
A circuit-compatible model of ballistic carbon nanotube field-effect transistors
Two novel multiway circuit partitioning algorithms using relaxed locking
Virtual Point-to-Point Connections for NoCs
On Complete Functional Broadside Tests for Transition Faults
A Novel Algorithm for Hardware Trojan Detection Through Reverse Engineering
FADESIM: Enable Fast and Accurate Design Exploration for Memristive Accelerators Considering Nonidealities
Efficient Identification of Unstable Loops in Large Linear Analog Integrated Circuits
Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations
Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array
On optimizing VLSI testing for product quality using die-yield prediction
r-map: Relating Implementation and Specification in Hardware Refinement Checking
Interleaved LDPC Decoding Scheme Improves 3-D TLC NAND Flash Memory System Performance
Optimal state chains and state codes in finite state machines
Minimum Implant Area-Aware Placement and Threshold Voltage Refinement
Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography
An Efficient Procedure to Generate Highly Compact Diagnosis Patterns for Transition Faults
CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement
A Dynamic and Proactive GPU Preemption Mechanism Using Checkpointing
A New Approach to Clock Skewing for Area and Power Optimization of ASICs Using Differential Flipflops and Local Clocking
Benchmarking of Mask Fracturing Heuristics
Presynthesis Area Estimation of Reconfigurable Streaming Accelerators
A Semantic-Integrated LSM-Tree-Based Key-Value Storage Engine for Blockchain Systems
Multi-Dimensional Automatic Sampling Schemes for Multi-Point Modeling Methodologies
A User-Centric CPU-GPU Governing Framework for 3-D Mobile Games
Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design
An Efficient Power Optimization Approach for Fixed Polarity Reed-Muller Logic Circuits Based on Metaheuristic Optimization Algorithm
An adaptive grid refinement strategy for the drift-diffusion equations
MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules
Robust Optimization of Multiple Timing Constraints
Preserving the film coefficient as a parameter in the compact thermal model for fast electrothermal simulation
Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving
A delay budgeting algorithm ensuring maximum flexibility in placement
Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP
CSA-CiM: Enhancing Multifunctional Computing-in-Memory With Configurable Sense Amplifiers
Novel Proximal Group ADMM for Placement Considering Fogging and Proximity Effects
An efficient filter-based approach for combinational verification
Efficient Algorithms for Layer Assignment Problem
On the generation of area-time optimal testable adders
SqueezeLight: A Multi-Operand Ring-Based Optical Neural Network With Cross-Layer Scalability
The Monte Carlo method for semiconductor device and process modeling
Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits
Exploring Synchronous Page Fault Handling
CaptorX: A Class-Adaptive Convolutional Neural Network Reconfiguration Framework
Bit-parallel multidelay simulation
On the problem of gate assignment under different rise and fall delays
SpMMPlu-Pro: An Enhanced Compiler Plug-In for Efficient SpMM and Sparsity Propagation Algorithm
Derivation of Signal Flow Direction in MOS VLSI
Modeling Latch-Up in CMOS Integrated Circuits
Randomized Cholesky Factorization With Threshold-Based Multisampling for Power Grid Simulation
Hardware Trojan Design With Low Overhead and High Destructiveness for STT-MRAM-Based CIMs
From Layout to System: Early Stage Power Delivery and Architecture Co-Exploration
An Efficient Unknown BlockingScheme for Low Control Data Volume and High Observability
Fast functional simulation: an incremental approach
On the numerical stability of Green's function for substrate coupling in integrated circuits
A theory of nondeterministic networks
Linked faults in random access memories: concept, fault models, test algorithms, and industrial results
LAMP: Load-Balanced Multipath Parallel Transmission in Point-to-Point NoCs
Fast Energy-Optimal Multikernel DNN-Like Application Allocation on Multi-FPGA Platforms
A Silicon Compiler System Based on Asynchronous Architecture
A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance
A compiled-code hardware accelerator for circuit simulation
Causal Path Identification for Timed and Sequential Circuits
Solar Power Prediction Assisted Intra-task Scheduling for Nonvolatile Sensor Nodes
A performance and routability-driven router for FPGAs considering path delays
Analysis and synthesis of concurrent digital circuits using control-flow expressions
Sign-Off Timing Considerations via Concurrent Routing Topology Optimization
Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA
Inter-Task Energy-Hotspot Elimination in Fixed-Priority Real-Time Embedded Systems
Timing-Aware Qubit Mapping and Gate Scheduling Adapted to Neutral Atom Quantum Computing
A multigrid-like technique for power grid analysis
Fast Node Merging With Don't Cares Using Logic Implications
Analytical models for RTL power estimation of combinational andsequential circuits
Fault secure property versus strongly code disjoint checkers
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures
Synthesis of asynchronous controllers using integer linear programming
Virtual Channels and Multiple Physical Networks: Two Alternatives to Improve NoC Performance
Simulation and Experimental Demonstration of the Importance of IR-Drops During Laser Fault Injection
Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies
Data-Driven Mapping Using Local Patterns
Transient Sensitivity Computation for MOSFET Circuits
Decomposition-Based Real-Time Scheduling of Parallel Tasks on Multicores Platforms
LoCoExNet: Low-Cost Early Exit Network for Energy Efficient CNN Accelerator Design
A Temperature-Aware Reliability Enhancement Strategy for 3-D Charge-Trap Flash Memory
Impact of Interconnect on Ferroelectric FinFET-Based Logic-in-Memory Circuits at 3-nm Technology Node
VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits
Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs
Valid clock frequencies and their computation in wavepipelined circuits
Threshold voltage for GaAs MESFET with a recoil-implanted channel profile
A new transition count method for testing of logic circuits
Real-Time Lossless Compression for Silicon Debug
Test pattern generation using Boolean satisfiability
Dynamic Indexing: Leakage-Aging Co-Optimization for Caches
Security Analysis of Industrial Test Compression Schemes
Fasolt: a program for feedback-driven data-path optimization
Diagnostic fault simulation for synchronous sequential circuits
Low-power weighted random pattern testing
KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer
BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms
Aging Effects on Template Attacks Launched on Dual-Rail Protected Chips
A New Algorithm to Derive High Performance and Low Hardware Cost DCT for HEVC
A Fast Precision Tuning Solution for Always-On DNN Accelerators
Fault Diagnosis With Convolutional Compactors
Generation of distributed logic-memory architectures through high-level synthesis
An Incremental Placement Flow for Advanced FPGAs With Timing Awareness
Quasi-Static Compact Model for Coupling Between Aligned Contacts on Finite Substrates With Insulating or Conducting Backplanes
Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs
Optimized Micro-Channel Design for Stacked 3-D-ICs
Efficiently Mapping VLSI Circuits With Simple Cells
TheSPoT: Thermal Stress-Aware Power and Temperature Management for Multiprocessor Systems-on-Chip
PACA: A Pattern Pruning Algorithm and Channel-Fused High PE Utilization Accelerator for CNNs
Attacks on Recent DNN IP Protection Techniques and Their Mitigation
Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips
Design Guidelines and Feedback Structure of Ring Oscillator PUF for Performance Improvement
Analysis and synthesis of weighted-sum functions
Model-Based Initial Bias (MIB): Toward a Single-Iteration Optical Proximity Correction
Computer-aided modeling and evaluation of reconfigurable VLSI processor arrays with VHDL
Synthesis of high-performance analog circuits in ASTRX/OBLX
A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform
Symbolic layout compaction under conditional design rules
An Abstract Simulator for Species Concentrations in Channel-Based Microfluidic Devices
Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors
Asymptotic waveform evaluation for timing analysis
A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits With Strong Parasitic Couplings
The role of long and short paths in circuit performance optimization
Improved physical modeling of submicron MOSFETs based on parameter extraction using 2-D simulation
Modeling and Simulation of Electrified Droplets and Its Application to Computer-Aided Design of Digital Microfluidics
Structure-Aware Placement Techniques for Designs With Datapaths
Coverage Driven High-Level Test Generation Using a Polynomial Model of Sequential Circuits
Accelerating Markovian analysis of asynchronous systems using state compression
PFD - A Flexible Higher-Order Masking Scheme
Optimization of Droplet Routing in Microfluidic Biochips Using Calibrated Droplet-Shape Morphing
InnovA: A Cognitive Architecture for Computational Innovation Through Robust Divergence and Its Application for Analog Circuit Design
Adjustable RF Mixers' Alternate Test Efficiency Optimization by the Reduction of Test Observables
Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications
Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction