yusuke1997/dblp-id-title huggingface dataset:
A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V
A novel image rejection architecture for quadrature radio receivers
Design and Analysis of a 12-b Current-Steering DAC in a 14-nm FinFET Technology for 2G/3G/4G Cellular Applications
Extending Blackman's Formula to Feedback Networks With Multiple Dependent Sources
Conflict-Free Parallel Memory Accessing Techniques for FFT Architectures
A 5.4-Gb/s Clock and Data Recovery Circuit Using Seamless Loop Transition Scheme With Minimal Phase Noise Degradation
A 16-28-W 92.8%-Efficiency Monolithic Quasi-Resonant LED Driver With Constant-Duty-Ratio Frequency Regulator
Pentavariate V min Analysis of a Subthreshold 10T SRAM Bit Cell With Variation Tolerant Write and Divided Bit-Line Read
A Study on Multi-Level PWM and Asynchronous ΣΔ Modulations for Enhanced Bandlimited Signal Tracking in Switching Power Amplifiers
Guest Editorial Special Issue on the IEEE International Symposium on Circuits and Systems 2018
A circuit to model the electrical behavior of an ionic polymer-metal composite
A Floating-Gate-Based Programmable CMOS Reference
A Fully Differential Rail-to-Rail CMOS Capacitance Sensor With Floating-Gate Trimming for Mismatch Compensation
Evolution of Function-Call Network Reliability in Android Operating System
Energy Efficient MIMO Relay Transmissions via Joint Power Allocations
Integrated Phase-Locking Scheme for SDFT-Based Harmonic Analysis of Periodic Signals
Micropower gradient flow acoustic localizer
High Accuracy Adaptive Microwave Ranging Using SNR-Based Perception for Coherent Distributed Antenna Arrays
Optimum masking levels and coefficient sparseness for Hilbert transformers and half-band filters designed using the frequency-response masking technique
Multiple-output low-power linear feedback shift register design
Matrix decomposition and butterfly diagrams for mutual relations between Hadamard-Haar and arithmetic spectra
Variable Digital Filter With Group Delay Flatness Specification or Phase Constraints
Printed Electronics: Effects of Bending and a Self-Compensation Means
A Phase-Locked Loop With Background Leakage Current Compensation
Energy-Efficient Adaptive Match-Line Controller for Large-Scale Associative Storage
Design of a 77-GHz LC-VCO With a Slow-Wave Coplanar Stripline-Based Inductor
Digitally Assisted 28 GHz Active Phase Shifter With 0.1 dB/0.5° RMS Magnitude/Phase Errors and Enhanced Linearity
A Wideband Low Power Low-Noise Amplifier in CMOS Technology
A Frequency-Folded ADC Channelizer With Digital Equalization and Relaxed Anti-Alias Filtering
Design of CMOS Ternary Latches
A Compact Tunable Power Divider With Wide Tuning Frequency Range and Good Reconfigurable Responses
Phase control for resonant DC-DC converter with class-DE inverter and class-E rectifier
Strategy Competition Dynamics of Multi-Agent Systems in the Framework of Evolutionary Game Theory
Accurate Spectral Testing With Non-Coherent Sampling for Multi-Tone Test
A Lower Error and ROM-Free Logarithmic Converter for Digital Signal Processing Applications
A New Current-Mode Incremental Signaling Scheme With Applications to Gb/s Parallel Links
Design of Adaptive Exponential Functional Link Network-Based Nonlinear Filters
Oversampling A/D Converters With Reduced Sensitivity to DAC Nonlinearities
Efficient Modeling of Crosstalk Noise on Power Distribution Networks for Contactless 3-D ICs
Improved Coding-Efficiency Two-Level Source Encoder for RF Switch-Mode Power Amplifiers
High Input Impedance Low-Noise CMOS Analog Frontend IC for Wearable Electrocardiogram Monitoring
A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme
Wide-band CMOS cascode low-noise amplifier design based on source degeneration topology
Analysis and Design of Nonlinear Circuits With a Self-Consistent Carleman Linearization
Partial-Information-Based Distributed Filtering in Two-Targets Tracking Sensor Networks
Exact analytical bit error rates for multiple access chaos-based communication systems
System-Level Analysis of Phase Noise in Full-Duplex Wireless Transceivers
On Stability of Neural Networks by a Lyapunov Functional-Based Approach
An 80.2 dB DR 23.25 mW/Channel 8-Channel Ultrasound Receiver With a Beamforming Embedded SAR ADC
An On-Chip Tunable Frequency Generator for Crystal-Less Low-Power WBAN Radio
A Coin-Battery-Powered LDO-Free 2.4-GHz Bluetooth Low-Energy Transmitter With 34.7% Peak System Efficiency
A Flexible UMTS-WiMax Turbo Decoder Architecture
Post-Quantum Cryptography on FPGA Based on Isogenies on Elliptic Curves
Two-Dimensional Multi-Parameter Adaptation of Noise, Linearity, and Power Consumption in Wireless Receivers
Full On-Chip CMOS Low-Dropout Voltage Regulator
A Mismatch Calibration Technique for SAR ADCs Based on Deterministic Self-Calibration and Stochastic Quantization
Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator
Thermal Noise Analysis of a Programmable-Gain Switched-Capacitor Amplifier With Input Offset Cancellation
Multilayer Packaging SIW Three-Way Filtering Power Divider With Adjustable Power Division
Continuous-Time Algorithms for Solving Maxwell's Equations Using Analog Circuits
Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters
Analysis of a Frequency Acquisition Technique With a Stochastic Reference Clock Generator
Memory Reduction Methodology for Distributed-Arithmetic-Based DWT/IDWT Exploiting Data Symmetry
High-Gain Operational Transconductance Amplifiers in a Printed Complementary Organic TFT Technology on Flexible Foil
A Mixed Signal (Analog-Digital) Integrator Design
A 50- to 300-MHz CMOS Gm-C Tracking Filter Based on Parallel Operation of Saturation and Triode Transconductors for Digital TV Tuner ICs
An Analysis of DCM-Based True Random Number Generator
A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler
Distributed Filtering for Switched Linear Systems With Sensor Networks in Presence of Packet Dropouts and Quantization
A Simple Programmable Autowave Generator Network for Wave Computing Applications
Hold-In, Pull-In, and Lock-In Ranges of PLL Circuits: Rigorous Mathematical Definitions and Limitations of Classical Theory
Output-Jitter Performance of Second-Order Digital Bang-Bang Phase-Locked Loops With Nonaccumulative Reference Clock Jitter
Precise, wide-range approximations to arc sine function suitable for analog implementation in sensors and instrumentation applications
FPGA Implementation of the Fractional Order Integrator/Differentiator: Two Approaches and Applications
Modeling and Design of Spintronic Integrated Circuits
Algorithms and Architectures of Energy-Efficient Error-Resilient MIMO Detectors for Memory-Dominated Wireless Communication Systems
Design and Complexity Optimization of a New Digital IF for Software Radio Receivers With Prescribed Output Accuracy
Ultralow-Power Processing Array for Image Enhancement and Edge Detection
A Tunable Concurrent Dual-Band Phase Shifter MMIC for Beam Steering Applications
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist
Influence of LFSR Dither on the Periods of a MASH Digital Delta-Sigma Modulator
A Transceiver Front End for Electronic Control Units in FlexRay-Based Automotive Communication Systems
Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs
An Energy-Efficient Low Frequency-Dependence Switching Technique for SAR ADCs
Digital Background Calibration of Capacitor-Mismatch Errors in Pipelined ADCs
Simulation and Design of Nanocircuits With Resonant Tunneling Devices
Transformer-Feedback Dual-Band Neutralization Technique
A High-Efficiency Ultra-Broadband Mixed-Mode GaN HEMT Power Amplifier
A 256-Mcell Phase-Change Memory Chip Operating at 2+ Bit/Cell
Construction of Two-Dimensional Paraunitary Filter Banks Over Fields of Characteristic Two and Their Connections to Error-Control Coding
Affine-Projection-Like Adaptive-Filtering Algorithms Using Gradient-Based Step Size
A 0.4 V 298 nJ/op Neural Signal Spectral Feature Extraction Module With Novel Approximate MACs and Custom Compressors
A New Quadrature PWM Modulator With Tunable Center Frequency for Digital RF Transmitters
Complex Interaction Between Tori and Onset of Three-Frequency Quasi-Periodicity in a Current Mode Controlled Boost Converter
Low-Power Current-Mode Interval Type-2 Fuzzy Inference Engine Circuit
A Locally Active Memristor and Its Application in a Chaotic Circuit
Robust Pinning Constrained Control and Adaptive Regulation of Coupled Chua's Circuit Networks
Concurrent Multi-Channel Crosstalk Jitter Characterization Using Coprime Period Channel Stimulus
Adaptive Piecewise Linear Predistorters for Nonlinear Power Amplifiers With Memory
A 1-V 560-nW SAR ADC With 90-dB SNDR for IoT Sensing Applications
Toward CNN chip-specific robustness
Switching Time in Relaxation Oscillations of Emitter-Coupled Multivibrators
Performance Analysis of Distributed Short-Path Set Based Routing in Complex Networks
A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS
A Millimeter-Wave Fully Integrated Passive Reflection-Type Phase Shifter With Transformer-Based Multi-Resonance Loads for 360° Phase Shifting
Design of Noise Transfer Functions for Delta-Sigma Modulators Using the Least-pth Norm
Elimination of overflow oscillations in fixed-point state-space digital filters with saturation arithmetic: an LMI approach
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule
Event-Based Control for Network Systems via Integral Quadratic Constraints
A New Class of Continuous-Time Delay-Compensated Parameter-Varying Low-Pass Elliptic Filters With Improved Dynamic Behavior
New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy
A Power-Efficient Highly Linear Reconfigurable Biopotential Sensing Amplifier Using Gate-Balanced Pseudoresistors
Averaging and Cancellation Effect of High-Order Nonlinearity of a Power Amplifier
Compensation of Loudspeaker Nonlinearity in Acoustic Echo Cancellation Using Raised-Cosine Function
Multiband 0.25-muhbox m CMOS Base Station Chips for Indirect and Direct Conversion Receivers
An Indoor Photovoltaic Energy Harvester Using Time-Based MPPT and On-Chip Photovoltaic Cell
Gain-Boosting Charge Pump for Current Matching in Phase-Locked Loop
Low-Latency Lattice Reduction Based on Dual-Basis Updates for High-Dimensional MIMO Streams
Stochastic Stability of Genetic Networks With Disturbance Attenuation
Frequency-Domain Analysis of Digital PWM-Based RF Modulators for Flexible Wireless Transmitters
Analog Circuit Implementation of Fractional-Order Memristor: Arbitrary-Order Lattice Scaling Fracmemristor
A Continuous-Time Delta-Sigma Modulator for Biomedical Ultrasound Beamformer Using Digital ELD Compensation and FIR Feedback
A Novel Convolution Computing Paradigm Based on NOR Flash Array With High Computing Speed and Energy Efficiency
Fast-Transient Integrated Digital DC-DC Converter With Predictive and Feedforward Control
Phase-Aware Multitone Digital Signal Based Test for RF Receivers
Digital differentiator design using fractional delay filter and limit computation
Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters
A Capacitor-Less Ripple-Less Hybrid LDO With Exponential Ratio Array and 4000x Load Current Range
Low Latency and Low Error Floating-Point Sine/Cosine Function Based TCORDIC Algorithm
Wide V DD Embedded Asynchronous SRAM With Dual-Mode Self-Timed Technique for Dynamic Voltage Systems
Optimal Tuning of Inductive Wireless Power Links: Limits of Performance
Fast-Transient PCCM Switching Converter With Freewheel Switching Control
Nonseparable Three-Dimensional IIR Notch Filter Design Using Outer Product Expansion
A 0.5-V Wideband Amplifier for a 1-MHz CT Complex Delta-Sigma Modulator
A 6-GHz All-Digital Fractional-N Frequency Synthesizer Using FIR-Embedded Noise Filtering Technique
Design Constraints for Image-Reject Frequency-Translating Delta Sigma Modulators
A Speed-Optimized Systolic Array Processor Architecture for Spatio-Temporal 2-D IIR Broadband Beam Filters
Ultra-Low Complex Blind I/Q-Imbalance Compensation
A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS
Stability Analysis of Single-Phase Low-Voltage AC Microgrids With Constant Power Terminals
A Precision-Scalable Energy-Efficient Convolutional Neural Network Accelerator
Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist
On the Spectral Tones in a Digital-Analog Converter Due to Mismatch and Flicker Noise
Adaptive methods to preserve power amplifier linearity under antenna mismatch conditions
Compensating for Quantizer Delay in Excess of One Clock Cycle in Continuous-Time DeltaSigma Modulators
A CMOS Low-Dropout Regulator With a Momentarily Current-Boosting Voltage Buffer
Spur Mitigation in High-Sensitivity GNSS Receivers
Design of practically perfect-reconstruction cosine-modulated filter banks: a second-order cone programming approach
Closed-Form Design of Maximally Flat IIR Hilbert Transformer With Integer Delay
Dynamic Reference Voltage Sensing Scheme for Read Margin Improvement in STT-MRAMs
Novel Low-Power and Highly Reliable Radiation Hardened Memory Cell for 65 nm CMOS Technology
A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes
Power Regeneration From DC Motor With Bidirectional Router in Power Packet Dispatching System
Continuous Class-E Power Amplifier Modes
A Package Aware QLMVF Receiver Front End
A New Approach to the Design of Efficient Residue Generators for Arbitrary Moduli
Congestion estimation for 3-D circuit architectures
A Low-Power Analog Adder and Driver Using a-IGZO TFTs
A 2.12-V V pp 11.67-pJ/pulse Fully Integrated UWB Pulse Generator in 65-nm CMOS Technology
Dark Count Rate Modeling in Single-Photon Avalanche Diodes
Some Necessary and Sufficient Conditions on the Controllability of Star Networks
Insight into PIN diode behaviour leads to improved control circuit
Modeling and Simulation of Vanadium Dioxide Relaxation Oscillators
Minimum Phase Wide Output Range Digitally Controlled SIDO Boost Converter
Smooth perturbation on a classical energy function for lossy power system stability analysis
Convergence Analysis of Teleoperation Systems With Unsymmetric Time-Varying Delays
Analog Assisted Multichannel Digital Postcorrection for Time-Interleaved ADCs
A New Blind-Equalization Algorithm for an FIR SIMO System Driven by MPSK Signal
Embedded Low-Power Processor for Personalized Stress Detection
High-Pass Negative Group Delay RC-Network Impedance
Digital Multiplierless Implementation of Biological Adaptive-Exponential Neuron Model
An Ultra Low-Power CMOS Transceiver Using Various Low-Power Techniques for LR-WPAN Applications
Fast Fixed-Time Nonsingular Terminal Sliding Mode Control and Its Application to Chaos Suppression in Power System
Energy-Efficient Hardware Architectures for Fast Polar Decoders
A 10/24-GHz CMOS/IPD Monopulse Receiver for Angle-Discrimination Radars
Some Simple Synchronization Criteria for Complex Dynamical Networks
Reduced-Communication Diffusion RLS for Distributed Estimation Over Multi-Agent Networks
Design of Least-Squares and Minimax Composite Filters
Optimal Filter Networks
Piecewise-linear approximation of nonlinear dynamical systems
Computation of singular and singularity induced bifurcation points of differential-algebraic power system model
On Semiglobal Stabilization of Discrete-Time Periodic Systems With Bounded Controls
Necessary and Sufficient Stability Criteria for a Class of Fractional-Order Delayed Systems
A 1.8-GHz injection-locked quadrature CMOS VCO with low phase noise and high phase accuracy
Wideband Receiver for a Three-Dimensional Ranging LADAR System
Design and analysis of power-CMOS-gate-based switched-capacitor boost DC-AC inverter
A Method for Reduced Finite Precision Effects in Parallel Filtering Echo Cancellation
Distributed Fault-Tolerant Time-Varying Formation Control for Second-Order Multi-Agent Systems With Actuator Failures and Directed Topologies
NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization
Incremental Data Converters at Low Oversampling Ratios
Robust Voltage Regulation of a DC-AC Inverter With Load Variations via a HDOBC Approach
Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm for the Design of Area-Power Efficient FIR Filters
Dual-Phase-Shift Control Scheme With Current-Stress and Efficiency Optimization for Wireless Power Transfer Systems
Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications
Nano-Ampere Low-Dropout Regulator Designs for IoT Devices
Guest Editorial Special Section on 2009 IEEE Custom Integrated Circuits Conference
Wideband Inductorless Low-Power LNAs with G m Enhancement and Noise-Cancellation
Half-Delay B-Spline Filter for Construction of Shift-Invariant Wavelet Transform
A Biomedical Implantable FES Battery-Powered Micro-Stimulator
Single Bit Filtering Circuit Implemented in a System for the Generation of Colored Noise
A 170.7-dB FoM-DR 0.45/0.6-V Inverter-Based Continuous-Time Sigma-Delta Modulator
Multichannel Clock and Data Recovery: A Synchronous Approach
Digital Synthesizer/Mixer With Hybrid CORDIC-Multiplier Architecture: Error Analysis and Optimization
A Fully Differential Comparator-Based Switched-Capacitor DeltaSigma Modulator
1.5-V square-root domain second-order filter with on-chip tuning
A Cryogenic 1 GSa/s, Soft-Core FPGA ADC for Quantum Computing Applications
Complex Independent Component Analysis by Entropy Bound Minimization
The Design of an Energy-Efficient IR-UWB Transmitter With Wide-Output Swing and Sub-Microwatt Leakage Current
A Simple and Reliable System to Detect and Correct Setup/Hold Time Violations in Digital Circuits
A Switchless Multiband Impedance Matching Technique Based on Multiresonant Circuits
An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Sigma Delta Modulator and a Flash Converter
Design of Stage-Selective Negative Voltage Generator to Improve On-Chip Power Conversion Efficiency for Neuron Stimulation
RF Circuit Linearity Optimization Using a General Weak Nonlinearity Model
Image descreening by GA-CNN-based texture classification
A Low Energy and High Performance ${\rm DM}^{2}$ Adder
CIPRNG: A VLSI Family of Chaotic Iterations Post-Processings for $\mathbb {F}_{2}$ -Linear Pseudorandom Number Generation Based on Zynq MPSoC
A High-Throughput Hardware Architecture for AV1 Non-Directional Intra Modes
Generalized Output Synchronization of Dynamical Networks Using Output Quasi-Passivity
Stabilizing periodic solutions of nonlinear systems and applications in chaos control
A Low-Voltage Sense Amplifier for Embedded Flash Memories
Phase Predistortion of a Class-D Outphasing RF Amplifier in 90 nm CMOS
Self-Reconfigurable Channel Data Buffering Scheme and Circuit Design for Adaptive Flow Control in Power-Efficient Network-on-Chips
Design of Millimeter-Wave CMOS Radios: A Tutorial
Multiple Line-Outage Detection in Power System With Load Stochastic Perturbations
Digital implementation of a wavelet-based event detector for cardiac pacemakers
Factoring Integers With a Brain-Inspired Computer
Necessary and Sufficient Condition for a Class of Planar Dynamical Systems Related to CNNs to be Completely Stable
Anti-Windup Design for Saturated Semi-Markovian Switching Systems With Stochastic Disturbance
Lyapunov Stability and Strong Passivity Analysis for Nonlinear Descriptor Systems
Set-Membership NLMS Algorithm With Robust Error Bound
A 53-67 GHz Low-Noise Mixer-First Receiver Front-End in 65-nm CMOS
Low-Latency Low-Complexity Architectures for Viterbi Decoders
Efficient time-recursive implementation of matched filterbank spectral estimators
Compact High-Efficiency Broadband Rectifier With Multi-Stage-Transmission-Line Matching
Design of Reverse Converters for the New RNS Moduli Set {2 n +1, 2 n -1, 2 n , 2 n-1 +1} ( n odd)
A Feedforward 10times CMOS Current-Ripple Suppressor for Switching Power Supplies
A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector
A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization
SCDVP: A Simplicial CNN Digital Visual Processor
Dynamic Element Matching With Signal-Independent Element Transition Rates for Multibit ΔΣ Modulators
Design and Analysis of a CMOS Ratio-Memory Cellular Nonlinear Network (RMCNN) Requiring No Elapsed Time
An LLC-Type Resonant Forward Converter With Adjustable Turning-Off Time Control
Optimized Fundamental Signal Processing Operations For Energy Minimization on Heterogeneous Mobile Devices
Multibit Delta-Sigma Modulator With Two-Step Quantization and Segmented DAC
Fast Reciprocal Jacket Transform With Many Parameters
A Novel Compact Isolation Circuit Suitable for Ultracompact and Wideband Marchand Baluns
A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video
Joint Detection and Decoding of Polar-Coded OFDM-IDMA Systems
Trigger-Wave Asynchronous Cellular Logic Array for Fast Binary Image Processing
A 10-Bit 5 MS/s VCO-SAR ADC in 0.18-µm CMOS
Note on the Design of an Equiripple DC-Notch FIR Filter
Wide-Range 5.0/3.3/1.8-V I/O Buffer Using 0.35-m 3.3-V CMOS Technology
Timing Recovery in Conjunction With Maximum Likelihood Sequence Detection in the Presence of Intersymbol Interference
A low-cost unrestricted fast playback scheme for video streaming
A Wide-Swing Low-Noise Transconductance Amplifier and the Enabling of Large-Signal Handling Direct-Conversion Receivers
An In-Place FFT Architecture for Real-Valued Signals
A Fast and Power-Efficient Hardware Architecture for Non-Maximum Suppression
Systematically Re-encoded Algebraic Soft-Decision Reed-Solomon Decoder
VLSI Implementation of a High-Throughput Iterative Fixed-Complexity Sphere Decoder
A prewhitening-induced bound on the identification error in independent component analysis
Three hardware architectures for the binary modular exponentiation: sequential, parallel, and systolic
A 10-MHz Hysteretic-Controlled Buck Converter With Single On/Off Reference Tracking Using Turning-Point Prediction for DVFS Application
Cooperative Output Regulation of Singular Multi-Agent Systems Under Switching Network by Standard Reduction
Least mean square adaptive digital background calibration of pipelined analog-to-digital converters
A Σ Δ-FIR-DAC for Multi-Bit Σ Δ Modulators
Design and Iso-Area V min Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS
Design of Linear Phase FIR Filters With High Probability of Achieving Minimum Number of Adders
Blind-Source Separation Based on Decorrelation and Nonstationarity
Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders
Fast analytical design algorithms for FIR notch filters
A Reconfigurable Random Number Generator Based on the Transient Effects of Ring Oscillators
FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder
Area-Efficient Approach for Generating Quantized Gaussian Noise
An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS
Exponential Stability Analysis and Stabilization for Continuous Time-Delay Systems With Controller Failure
Residual Syntax Elements Analysis and Design Targeting High-Throughput HEVC CABAC
A 0.4-V Wide Temperature Range All-MOSFET Subthreshold Voltage Reference With 0.027%/V Line Sensitivity
Efficient Calculation of the Impulse Sensitivity Function in Oscillators
A 2-MS/s, 11.22 ENOB, Extended Input Range SAR ADC With Improved DNL and Offset Calculation
An analytical formulation of phase noise of signals with Gaussian-distributed jitter
A 0.8-4-GHz Software-Defined Radio Receiver With Improved Harmonic Rejection Through Non-Overlapped Clocking
TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65nm CMOS and Experimental Results
Rotary Traveling-Wave Oscillators, Analysis and Simulation
A Clock-Less Jitter Spectral Analysis Technique
A Fractional- N Frequency Synthesizer With No Fractional Spurs