yusuke1997/dblp-id-title huggingface dataset:
A Quantized Analog RF Front End
A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router
A Readout IC for Capacitive Touch Screen Panels With 33.9 dB Charge-Overflow Reduction Using Amplitude-Modulated Multi-Frequency Excitation
Class-G Impedance-Modulation Multi-Core Power Oscillator for High P out and Power Back-Off Efficiency Enhancement
A 29-ns 64-Mb DRAM with hierarchical array architecture
Si IC-compatible inductors and LC passive filters
An SNR-Enhanced 8-Ary (SNRE-8) Modulation Technique for Wireline Transceivers Using Pulse Width, Position, and Amplitude Modulation
Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation Effect Under Resonant Supply Noise
CORDIC-Less Digital Polar Transmitter Architecture Based on Delta-Sigma Modulator
GaAs MESFET differential pass-transistor logic
3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition
A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme
Comments on "A one volt four-quadrant analog current mode multiplier cell" [with reply]
A 0.02-mm 2 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology
Second-order intermodulation mechanisms in CMOS downconverters
Multi-gigabit-per-second silicon bipolar ICs for future optical-fiber transmission systems
Simultaneous Transmission of Up To 94-mW Self-Regulated Wireless Power and Up To 5-Mb/s Reverse Data Over a Single Pair of Coils
A 48-80-V Input 2-MHz Adaptive ZVT-Assisted Bus Converter With Light-Load Efficiency Improvement
A Class-G Headphone Amplifier in 65 nm CMOS Technology
All Rivers Flow to the Sea: A High-Density Wireless Power Receiver With Split-Dual-Path and Hybrid-Quad-Path Step-Down Rectifying Conversion
20-nm In 0.8 Ga 0.2 As MOSHEMT MMIC Technology on Silicon
A new wide-band Darlington amplifier
Automatic Compensation of the Voltage Attenuation in 3-D Interconnection Based on Capacitive Coupling
A 16-Gb/s -11.6-dBm OMA Sensitivity 0.7-pJ/bit Optical Receiver in 65-nm CMOS Enabled by Duobinary Sampling
Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers
A Compact 180-GHz Stacked-FET Oscillator With 11-dBm Output Power and 13.9% DC-to-RF Efficiency in a 45-nm CMOS SOI Process
Low-power high-performance arithmetic circuits and architectures
A Sub-400-nW Real-Time Event-Driven Spectrogram Extraction Unit in 28-nm FD-SOI CMOS for Keyword Spotting Application
A Single-Stage Bias-Flip Regulating Rectifier With Fully Digital Duty-Cycle-Based MPPT for Piezoelectric Energy Harvesting
Cores, Cache, Content, and Characterization: IBM's Second Generation 14-nm Product, z15
A Quadrature Digital Power Amplifier With Wide Efficiency Enhancement Coverage and High Dynamic Power Range
An Ultra-High 6318-PPI Pixel Circuit for Micro-OLED Displays With V th Compensated up to 10-bit Gray Levels
A 43.3-μW Biopotential Amplifier With Tolerance to Common-Mode Interference of 18 V pp and T-CMRR of 105 dB in 180-nm CMOS
A single-chip text-to-speech synthesis device utilizing analog nonvolatile multilevel flash storage
A 23-mW 24-GS/s 6-bit Voltage-Time Hybrid Time-Interleaved ADC in 28-nm CMOS
A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems
All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform
Wide-band symmetrical analog multiplier IC for coherent optical-fiber receivers operating up to 10 Gb/s
A 0.4-6 GHz Receiver for Cellular and WiFi Applications
A GaAs upconverter MMIC with an automatic gain control amplifier for 1.9 GHz PHS
Optimization of chopper amplifiers for speed and gain
Studies in VLSI technology economics. IV. Models for gate array design productivity
A monolithic CMOS 20-b analog-to-digital converter
A Near-Threshold 480 MHz 78 µW All-Digital PLL With a Bootstrapped DCO
An All-Passive Negative Feedback Network for Broadband and Wide Field-of-View Self-Steering Beam-Forming With Zero DC Power Consumption
Low-power monolithic signal-conditioning system
Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications
A Successive Approximation Recursive Digital Low-Dropout Voltage Regulator With PD Compensation and Sub-LSB Duty Control
A 5.2-Mpixel 88.4-dB DR 12-in CMOS X-Ray Detector With 16-bit Column-Parallel Continuous-Time Incremental ΔΣ ADCs
A Batteryless 19 µW MICS/ISM-Band Energy Harvesting Body Sensor Node SoC for ExG Applications
CMOS oversampling ΔΣ magnetic-to-digital converters
A wide dynamic range receiver channel for a pulsed time-of-flight laser radar
A biomorphic digital image sensor
A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-µm CMOS
Compact BJT-Based Thermal Sensor for Processor Applications in a 14 nm tri-Gate CMOS Process
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications
A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems
A Threshold-Based Bioluminescence Detector With a CMOS-Integrated Photodiode Array in 65 nm for a Multi-Diagnostic Ingestible Capsule
AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks
Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System
A 10-Gb/s CDR/DEMUX with LC delay line VCO in 0.18-μm CMOS
A 77 GHz 90 nm CMOS Transceiver for FMCW Radar Applications
Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)
A 40-170 MHz PLL-Based PWM Driver Using 2-/3-/5-Level Class-D PA in 130 nm CMOS
GaAs Schmitt trigger memory cell design
A Centimeter Resolution, 10 m Range CMOS Impulse Radio Radar for Human Motion Monitoring
Neuro-CIM: ADC-Less Neuromorphic Computing-in-Memory Processor With Operation Gating/Stopping and Digital-Analog Networks
230-GHz self-aligned SiGeC HBT for optical and millimeter-wave applications
A 136-GΩ Input-Impedance Active Electrode for Non-Contact Biopotential Signals Monitoring
Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip
Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring
Design and applications of tunable analog BiCMOS circuits
Monolithic GaN-Based Driver and GaN Switch With Diode-Emulated GaN Technique for 50-MHz Operation and Sub-0.2-ns Deadtime Control
Analog circuits in ultra-deep-submicron CMOS
A 128×128 1.5% Contrast Sensitivity 0.9% FPN 3 µs Latency 4 mW Asynchronous Frame-Free Dynamic Vision Sensor Using Transimpedance Preamplifiers
Hotspot-Limited Microprocessors: Direct Temperature and Power Distribution Measurements
Accurate in situ measurement of peak noise and delay change induced by interconnect coupling
A 763 pW 230 pJ/Conversion Fully Integrated CMOS Temperature-to-Digital Converter With +0.81 °C/-0.75 °C Inaccuracy
A 16-channel CMOS neural stimulating array
A 34 Gb/s Distributed 2: 1 MUX and CMU Using 0.18$muhbox m$CMOS
A 4-W X-band compact coplanar high-power amplifier MMIC with 18-dB gain and 25% PAE
Analysis and design of a new race-free four-phase CMOS logic
Design analysis and circuit enhancements for high-speed bipolar flip-flops
Photoreceiver module using an InP HEMT transimpedance amplifier for over 40 gb/s
A Supply-Noise-Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM
Pipelined architecture for fast CMOS buffer RAMs
The design of a 3-V 900-MHz CMOS bandpass amplifier
A 128-Gb/s PAM-4 Transmitter With Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28-nm CMOS
1-V operational amplifier with rail-to-rail input and output ranges
Multi-Watt, 1-GHz CMOS Circulator Based on Switched-Capacitor Clock Boosting
Guest Editorial IEEE 2024 European Solid-State Electronics Research Conference
A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing
A 6.5-12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS
eCIMC: A603.1-TOPS/W eDRAM-Based Cryogenic In-Memory Computing Accelerator Supporting Boolean/Convolutional Operations
Correlated Dual-Loop Sturdy MASH Continuous-Time Delta-Sigma Modulators
A QVGA 143 dB Dynamic Range Frame-Free PWM Image Sensor With Lossless Pixel-Level Video Compression and Time-Domain CDS
A 6.78-MHz Multiple-Transmitter Wireless Power Transfer System With Efficiency Maximization by Adaptive Magnetic Field Adder IC
A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS
40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0.18-µm CMOS
Corrections to "A 10/20/30/40 MHz Feed-Forward FIR DAC Continuous-Time ΔΣ ADC With Robust Blocker Performance for Radio Receivers"
A 50-450 MHz Tunable RF Biquad Filter Based on a Wideband Source Follower With > 26 dBm IIP 3 , +12 dBm P 1 dB , and 15 dB Noise Figure
An interactive layout design system with real-time logical verification and extraction of layout parasitics
An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection
D-Band Frequency Quadruplers in BiCMOS Technology
A 256-Kb Dual-V CC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor
A Multi-Event, 7.9-ps Resolution Time Amplification-Based TDC With an Ultra-Low Static Phase Error DLL Using Interpolator Recycling Technique for dToF Applications
Notice of Violation of IEEE Publication Principles: A 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation
A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme
A 7 mW 20 MHz BW Time-Encoding Oversampling Converter Implemented in a 0.08 mm 2 65 nm CMOS Circuit
A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage
True Filterless Class-D Audio Amplifier
A 250-MHz BiCMOS receiver channel with leading edge timing discriminator for a pulsed time-of-flight laser rangefinder
A 10-50-GHz CMOS Distributed Step Attenuator With Low Loss and Low Phase Imbalance
A 56-nm CMOS 99-mm 2 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput
A Wideband Sub-6-GHz Transceiver Front End for 5G Base Stations in 22-nm FD-SOI CMOS
Improved address buffers, TTL input current reduction, and hidden refresh test mode in a 4-Mb DRAM
Hysteresis effect in pass-transistor-based, partially depleted SOI CMOS circuits
A 200 MHz CMOS pipelined multiplier-accumulator using a quasi-domino dynamic full-adder cell design
A 28-nm 18.7 TOPS/mm² 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh
A 128-Gb/s D-Band Receiver With Integrated PLL and ADC Achieving 1.95-pJ/b Efficiency in 22-nm FinFET
Design and Analysis of a DCO-Based Phase-Tracking RF Receiver for IoT Applications
A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channel applications
A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC
A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp With Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS
A Cryo-CMOS DAC-Based 40-Gb/s PAM4 Wireline Transmitter for Quantum Computing
A 100-800 MHz 8-Path Polyphase Transmitter With Mixer Duty-Cycle Control Achieving <-40 dBc for ALL Harmonics
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS
A BiCMOS low-power current mode gate
A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture
Design of High-Gain Sub-THz Regenerative Amplifiers Based on Double-G max Gain Boosting Technique
RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator
Application of enhancement mode FET technology for wireless subscriber transmit/receive circuits
Schottky-barrier infrared focal plane arrays with novel readout structures
Analytical and numerical analyses of the delay time of BiCMOS structures
A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing
Analysis and experimental verification of digital substrate noise generation for epi-type substrates
A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip
Process and temperature compensation in a 7-MHz CMOS clock oscillator
Highly Linear High-Power 802.11ac/ax WLAN SiGe HBT Power Amplifiers With a Compact 2nd-Harmonic-Shorted Four-Way Transformer and a Thermally Compensating Dynamic Bias Circuit
A CCD programmable signal processor
A Wide-Range Mixed-Mode DLL for a Combination 512 Mb 2.0 Gb/s/pin GDDR3 and 2.5 Gb/s/pin GDDR4 SDRAM
A 2.2-ps Time-of-Flight Resolution Frequency-Domain fNIRS Readout IC With a Dynamic Architecture and Cross-Coupling-Free Intensity and Phase-to-Digital Converter
Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates
A class-AB high-speed low-power operational amplifier in BiCMOS technology
Hybrid SRAM/ROM Compute-in-Memory Architecture for High Task-Level Energy Efficiency in Transformer Models With 8928-kb/mm² Density in 28nm CMOS
Rail-to-Rail-Input Dual-Radio 64-Channel Closed-Loop Neurostimulator
A low power-noise output driver with an adaptive characteristic applicable to a wide range of loading conditions
A 1.3 GHz low-phase noise fully tunable CMOS LC VCO
Fully Integrating a 400 V-to-12 V DC-DC Converter in High-Voltage CMOS
A class A/B floating buffer BiCMOS power op-amp
A Current Reuse Quadrature GPS Receiver in 0.13 μ m CMOS
A 394-TOPS/W Matched Filter With Charge-Domain Computing for GPS Signal Acquisition
A CMOS Timer-Injector Integrated Circuit for Self-Powered Sensing of Time-of-Occurrence
A 3.5-mW, 2.5-GHz diversity receiver and a 1.2-mW, 3.6-GHz VCO in silicon on anything
A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM
A 13.5-b 1.2-V micropower extended counting A/D converter
Large-Area Microphone Array for Audio Source Separation Based on a Hybrid Architecture Exploiting Thin-Film Electronics and CMOS
A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR
Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM
A Fully Differential Charge-Balanced Accelerometer for Electronic Stability Control
A third-generation SPARC V9 64-b microprocessor
Low-Area TCAM Using A Don't Care Reduction Scheme
Heterogeneous multiprocessor for the management of real-time video and graphics streams
A Low-Power Magnitude Detector for Analysis of Transient-Rich Signals
A Wireless Power and Data Transfer System for Medical Implants Using a Miniaturized Inductive Link With Frequency-Splitting Enhancement
A CMOS 49-63-GHz Phase-Locked Stepped-Chirp FMCW Radar Transceiver
A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip
Prospects of CMOS technology for high-speed optical communication circuits
An 8-b 650-MHz folding ADC
A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips
A 71-MHz CMOS IF-baseband strip for GSM
A Bi-Directional Dual-Path Boost-Buck Hybrid Converter for High-Voltage Power Transmission Delivery Cable in Humanoid Robots
A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications
A 3.7-mW 2.4-GHz Phase-Tracking GFSK Receiver With BBPLL-Based Demodulation
A 52-Gb/s Low-Power PAM-4 Baud-Rate CDR Using Pattern-Based Phase Detector for Short-Reach Applications
Design and Analysis of 55-63-GHz Fundamental Quad-Core VCO With NMOS-Only Stacked Oscillator in 28-nm CMOS
A 50 MHz eight-tap adaptive equalizer for partial-response channels
A stereo audio chip using approximate processing for decimation and interpolation filters
A source-line programming scheme for low-voltage operation NAND flash memories
A 0.54 THz Signal Generator in 40 nm Bulk CMOS With 22 GHz Tuning Range and Integrated Planar Antenna
Mismatch sensitivity of a simultaneously latched CMOS sense amplifier
A CMOS Chopper Offset-Stabilized Opamp
A 0.1% THD, 1-MΩ to 1-GΩ Tunable, Temperature-Compensated Transimpedance Amplifier Using a Multi-Element Pseudo-Resistor
Cellular handset integration - SIP versus SOC
A Wearable 8-Channel Active-Electrode EEG/ETI Acquisition System for Body Area Networks
A Low-Voltage Broadband Feedforward-Linearized BJT Mixer
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm
Insights Into Silicon Photonics Mach-Zehnder-Based Optical Transmitter Architectures
A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacitance multiplier
An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter
Optimization-based placement algorithm for BiCMOS leaf cell generation
A Wideband Supply Modulator for 20 MHz RF Bandwidth Polar PAs in 65 nm CMOS
Multiple twisted dataline techniques for multigigabit DRAMs
Modeling and simulation of hot-carrier-induced device degradation in MOS circuits
Optical Pixel Sensor of Hydrogenated Amorphous Silicon Thin-Film Transistor Free of Variations in Ambient Illumination
Super Class-AB Recycling Folded Cascode OTA
Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs
A 2.5-GHz low-power, high dynamic range, self-tuned Q-enhanced LC filter in SOI
20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems
A 42 mW 200 fs-Jitter 60 GHz Sub-Sampling PLL in 40 nm CMOS
Notice of Violation of IEEE Publication Principles: A low reference spurs 1-5 GHz 0.13 μm CMOS frequency synthesizer using a fully-sampled feed-forward loop filter architecture
A Quad-Band GSM/EDGE-Compliant SiGe-Bipolar Power Amplifier
A 50 Gb/s 190 mW Asymmetric 3-Tap FFE VCSEL Driver
Ultra-Low Phase Noise X-Band BiCMOS VCOs Leveraging the Series Resonance
A 14-b 2.5 MSPS pipelined ADC with on-chip EPROM
A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration
A MOSFET-C variable equalizer circuit with simple on-chip automatic tuning
A 2 V, 10 b, 20 Msample/s, mixed-mode subranging CMOS A/D converter
Channel-Adaptive ADC and TDC for 28 Gb/s PAM-4 Digital Receiver
A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference
39-44 GHz Phased-Array Transmitter Circuits in RFSOI CMOS Technology
A Wideband Class-AB Power Amplifier With 29-57-GHz AM-PM Compensation in 0.9-V 28-nm Bulk CMOS
A 684-mW adaptive supply full-rate ADSL CO driver
Double-Quadrature UWB Receiver for Wide-Range Localization Applications With Sub-cm Ranging Precision
14-bit 2.2-MS/s sigma-delta ADC's
A 5-GHz-band multifunctional BiCMOS transceiver chip for GMSK modulation wireless systems
A baseband processor for IS-54 cellular telephony
Gain/bandwidth programmable PA control loop for GSM/GPRS quad-band cellular handsets
1.3- mu m CMOS/bipolar standard cell library for VLSI computers
A highly integrated dual-band triple-mode transmit IC for cellular CDMA2000 applications
A video signal processor for motion-compensated field-rate upconversion in consumer television
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture
A VCF-Step-Reconfigurable Continuously Scalable-Conversion-Ratio Switched- Capacitor Converter
Dynamic Power Reduction in Scalable Neural Recording Interface Using Spatiotemporal Correlation and Temporal Sparsity of Neural Signals
A direct digital synthesizer with interpolation circuits
Flexibility of interconnection structures for field-programmable gate arrays
W-Band CMOS Amplifiers Achieving +10 dBm Saturated Output Power and 7.5 dB NF
A High-Efficiency 40.68-MHz Single-Stage Dual-Output Regulating Rectifier With ZVS and Synchronous PFM Control for Wireless Powering
Introduction to the Special Section on the 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Design and Analysis of Low-Power High-Frequency Robust Sub-Harmonic Injection-Locked Clock Multipliers
Realization of a 1-V active filter using a linearization technique employing plurality of emitter-coupled pairs
A GaAs HEMT MMIC chip set for automotive radar systems fabricated by optical stepper lithography
Self-checking self-repairing computer nodes using the Mirror Processor
A 2.8-W Q-Band High-Efficiency Power Amplifier
A 2-GHz carrier leakage calibrated direct-conversion WCDMA transmitter in 0.13-μm CMOS
A 1.2 mW RDS receiver for portable applications
Acceptance sampling: an efficient, accurate method for estimating and optimizing parametric yield
Dithering Skip Modulation, Width and Dead Time Controllers in Highly Efficient DC-DC Converters for System-On-Chip Applications
A Coupling-Adaptive Wireless Power Transfer System With Voltage-/Current-Mode Receiver and Global Digital-PWM Regulation
Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution
A Scalable Massively Parallel Processor for Real-Time Image Processing
A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC
A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression
A 5.2-GHz BFSK Transceiver Using Injection-Locking and an On-Chip Antenna
Analysis and optimization of BiCMOS gate circuits
Processor-based built-in self-test for embedded DRAM
A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture
A Bidirectional Neural Interface SoC With Adaptive IIR Stimulation Artifact Cancelers
A CMOS line driver with 80-dB linearity for ISDN applications
A 30-μW 94.7-dB SNDR Noise-Shaping Current-Mode Direct-to-Digital Converter Using Triple-Slope Quantizer for PPG/NIRS Readout
A 0.4 ps-RMS-Jitter 1-3 GHz Ring-Oscillator PLL Using Phase-Noise Preamplification
Introduction to the 20th annual IEEE GaAs IC Symposium
A Widely-Tunable, Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio
A compact on-chip ECC for low cost flash memories
A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture
Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX
Multistage amplifier topologies with nested G m -C compensation
A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V
Guest Editorial 2022 Radio Frequency Integrated Circuits Symposium
A Bio-Impedance Readout IC With Digital-Assisted Baseline Cancellation for Two-Electrode Measurement
Design and Analysis of Broadband Dual-Gate Balanced Low-Noise Amplifiers
A Supply-Rail-Coupled eTextiles Transceiver for Body-Area Networks
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition
A silicon model of an auditory neural representation of spectral shape
A 1.8-V ΔΣ modulator interface for an electret microphone with on-chip reference
A 0.2 mm 2 , 27 Mbps 3 mW ADC/FFT-Less FDM BAN Receiver With Energy Exploitation Capability
A fast-settling op amp with low supply current
Advanced modeling of distortion effects in bipolar transistors using the Mextram model
ANP-G: A 28-nm 1.04-pJ/SOP Sub-mm² Asynchronous Hybrid Neural Network Olfactory Processor Enabling Few-Shot Class-Incremental On-Chip Learning
A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR
A pulsed sensing scheme with a limited bit-line swing
Verification of Digital RF Processors: RF, Analog, Baseband, and Software
A fully integrated self-calibrating transmitter/receive IC for an ultrasound presence detector microsystem
AC boosting compensation scheme for low-power multistage amplifiers