yusuke1997/dblp-id-title huggingface dataset:
Sub-1-V Fast-Response Hysteresis-Controlled CMOS Buck Converter Using Adaptive Ramp Techniques
Multi-Symbol-Sliced Dynamically Reconfigurable Reed-Solomon Decoder Design Based on Unified Finite-Field Processing Element
A Cryo-Tolerant >40-dB IRR, 4.7-7.9-GHz Double Quadrature Cryo-CMOS Receiver With a Broadband LNA for Scalable Quantum Applications
An Ultra Low Power Baseband Transceiver IC for Wireless Body Area Network in 0.18-mu m CMOS Technology
Hardware Implementation of Rayleigh and Ricean Variate Generators
A 17.5-fJ/bit Energy-Efficient Analog SRAM for Mixed-Signal Processing
Area-Time-Efficient Code-Based Postquantum Key Encapsulation Mechanism on FPGA
Multiphase Digital Low-Dropout Regulators
PCBRouteNet: Dynamic Quadrilateral-Flow Dataset and Benchmarks for Machine-Learning PCB Routing
Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications
Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic
Dual-Thread Deflate/Inflate Accelerator With Multicheckpoint Control With High Throughput and Compression Ratio for Bandwidth-Efficient Systems
Dynamic Thermal Management Under Soft Thermal Constraints
Optimizing Floating Point Units in Hybrid FPGAs
Distributed control schemes for fast arbitration in large crossbar networks
Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method
High-Performance Error and Erasure Decoding With Low Complexities Using SPC-RS Concatenated Codes
System design methodologies: aiming at the 100 h design cycle
Design and Analysis of Saturated Ring Oscillators Based on the Random Mid-Point Voltage Concept
A Highly Scalable Optical Network-on-Chip With Small Network Diameter and Deadlock Freedom
Rowhammer Vulnerability of DRAMs in 3-D Integration
Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm
Vector generation for power supply noise estimation and verification of deep submicron designs
Bias-Induced Healing of $V_{\text {min}}$ Failures in Advanced SRAM Arrays
Security-Adaptive Voltage Conversion as a Lightweight Countermeasure Against LPA Attacks
A low latency asynchronous arbitration circuit
Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits
Piecewise Linear Modulation Technique for Spread Spectrum Clock Generation
High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives
Asymmetrical Dead-Time Control Driver for Buck Regulator
Decoding-Aware Compression of FPGA Bitstreams
Analysis of Bitwise and Samplewise Switched Passive Charge Sharing SAR ADCs
A High Performance Switched Capacitor-Based DC-DC Buck Converter Suitable for Embedded Power Management Applications
Diagnosis and Layout Aware (DLA) Scan Chain Stitching
A Low Power 4T2C nvSRAM With Dynamic Current Compensation Operation Scheme
A Mismatch-Insensitive Skew Compensation Architecture for Clock Synchronization in 3-D ICs
28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique
Compressive Acquisition CMOS Image Sensor: From the Algorithm to Hardware Implementation
Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs
On Parallelization of High-Speed Processors for Elliptic Curve Cryptography
Compiler-Assisted STT-RAM-Based Hybrid Cache for Energy Efficient Embedded Systems
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages
Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems
Energy-Efficient Joint Scheduling and Application-Specific Interconnection Design
Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations
Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system
SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design
Built-in Loopback Test for IC RF Transceivers
A Multibank Memory-Based VLSI Architecture of DVB Symbol Deinterleaver
Broadside and Skewed-Load Tests Under Primary Input Constraints
HS3-DPG: Hierarchical Simulation for 3-D P/G Network
Energy-Efficient Hardware Data Prefetching
GPU NTC Process Variation Compensation With Voltage Stacking
A 4×10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS
A Nonbinary LDPC Decoder Architecture With Adaptive Message Control
A 3-bit/Unit Time-Domain Compute-In-Memory Macro With Adjustable Unit Delay
Low-Complexity Methodology for Complex Square-Root Computation
Low-energy CSMT carry generators and binary adders
A Low-Cost Quadruple-Node-Upsets Resilient Latch Design
Signature Driven Hierarchical Post-Manufacture Tuning of RF Systems for Performance and Power
Joint Profit and Process Variation Aware High Level Synthesis With Speed Binning
Thwarting Security Threats From Malicious FPGA Tools With Novel FPGA-Oriented Moving Target Defense
Guest Editorial Foreword to the Special Section on WSI'95
A Low-Power Pipelined-SAR ADC Using Boosted Bucket-Brigade Device for Residue Charge Processing
A Low-Cost and High-Throughput FPGA Implementation of the Retinex Algorithm for Real-Time Video Enhancement
An 8.55-17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fs rms Jitter and Fast Frequency Hopping
ALT-Lock: Logic and Timing Ambiguity-Based IP Obfuscation Against Reverse Engineering
VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache
Efficient Architectures for Multigigabit CCSDS LDPC Encoders
An Efficient Fully Parallel Decoder Architecture for Nonbinary LDPC Codes
Utilizing Redundancy for Timing Critical Interconnect
Range Unlimited Delay-Interleaving and -Recycling Clock Skew Compensation and Duty-Cycle Correction Circuit
CVNS-Based Storage and Refreshing Scheme for a Multi-Valued Dynamic Memory
A MITE-Based Translinear FPAA
FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects
A 50-mA 99.2% Peak Current Efficiency, 250-ns Settling Time Digital Low-Dropout Regulator With Transient Enhanced PI Controller
A 33-41-GHz SiGe-BiCMOS Digital Step Attenuator With Minimized Unit Impedance Variation
Physical models and algorithms for optoelectronic MCM layout
Design and Analysis of a Delay Sensor Applicable to Process/Environmental Variations and Aging Measurements
Creating a Backscattering Side Channel to Enable Detection of Dormant Hardware Trojans
Asynchronous Current Mode Serial Communication
Fast Decimal Floating-Point Division
A Goldschmidt Division Method With Faster Than Quadratic Convergence
High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic
A process-tolerant cache architecture for improved yield in nanoscale technologies
Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion
FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing
Novel VLSI Architecture for Fractional-Order Correntropy Adaptive Filtering Algorithm
An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation
Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations
Performance Optimization Using Variable-Latency Design Style
A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones
Fast Electromigration Stress Evolution Analysis for Interconnect Trees Using Krylov Subspace Method
VLSI Design of Light-Field Factorization for Dual-Layer Factored Display
Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing
PSM: an object-oriented synthesis approach to multiprocessor system design
84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor
Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design
Wireless NoC and Dynamic VFI Codesign: Energy Efficiency Without Performance Penalty
A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy
BiCMOS logic testing
Design of self-checking fully differential circuits and boards
Trifecta: A Nonspeculative Scheme to Exploit Common, Data-Dependent Subcritical Paths
A microcoded elliptic curve processor using FPGA technology
Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting
Efficient time-space mappings of nested loops onto multidimensional systolic arrays with a flexible buffer scheme
Preprocessing and Partial Rerouting Techniques for Accelerating Reconfiguration of Degradable VLSI Arrays
Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays
MASL-AFU: A High Memory Access Efficiency 2-D Scalable LUT-Based Activation Function Unit for On-Device DNN Training
Sub µW Noise Reduction for CIC Hearing Aids
Leakage control with efficient use of transistor stacks in single threshold CMOS
ZigBee 868/915-MHz Modulator/Demodulator for Wireless Personal Area Network
Investigation on the Worst Read Scenario of a ReRAM Crossbar Array
Unified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect
Path clustering in software timing analysis
Low-Jitter Frequency Doubling Circuit Supporting Higher-Speed BISG and Aging Sensing in a Chiplet-Based Design Environment
A Sub-1 V Transient-Enhanced Output-Capacitorless LDO Regulator With Push-Pull Composite Power Transistor
Editorial Rolling Out the IEEE TVLSI EDICS
Array Termination Impacts in Advanced SRAM
Editorial: New Associate Editor Appointments
HML, a novel hardware description language and its translation to VHDL
A Reference Voltage Interpolation-Based Calibration Method for Flash ADCs
An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs
1.2-V Analog Interface for a 300-MSps HD Video Digitizer in Core 65-nm CMOS
Runtime Self-Calibrated Temperature-Stress Cosensor for 3-D Integrated Circuits
Two systolic architectures for modular multiplication
Security-Enabled Near-Field Communication Tag With Flexible Architecture Supporting Asymmetric Cryptography
Low Power Chien Search for BCH Decoder Using RT-Level Power Management
Low-power memory mapping through reducing address bus activity
Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs
Energy-Efficient Object Detection Using Semantic Decomposition
Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse
PERA: Power-Efficient Routing Architecture for SRAM-Based FPGAs in Dark Silicon Era
Ultralow-power adiabatic circuit semi-custom design
A Domain-Specific Processor Microarchitecture for Energy-Efficient, Dynamic IoT Communication
Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage
An Asynchronous and Low-Power True Random Number Generator Using STT-MTJ
A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug
Test Compaction by Test Removal Under Transparent Scan
SimRPU: A Simulation Environment for Reconfigurable Architecture Exploration
Guest editorial: low-power electronics and design
ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture
SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m ) based multiplication and division algorithm
Temperature-Aware Idle Time Distribution for Leakage Energy Optimization
Low-Complexity Reconfigurable Fast Filter Bank for Multi-Standard Wireless Receivers
A dynamically reconfigurable interconnect for array processors
Combined circuit and architectural level variable supply-voltage scaling for low power
Modeling multidimensional data and control flow
AdNoC: Runtime Adaptive Network-on-Chip Architecture
A 4-Transistors/1-Resistor Hybrid Synapse Based on Resistive Switching Memory (RRAM) Capable of Spike-Rate-Dependent Plasticity (SRDP)
Routing-Based Traffic Migration and Buffer Allocation Schemes for 3-D Network-on-Chip Systems With Thermal Limit
An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording
A Two-Channel Interleaved ADC With Fast-Converging Foreground Time Calibration and Comparison-Based Control Logic
Protecting Analog Circuits Using Switch Mode Time Domain Locking
Managing on-chip inductive effects
Efficient Design Space Exploration for the BOOM Using SAC-Based Reinforcement Learning
Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia
Fast Waveform Estimation (FWE) for Timing Analysis
VLSI implementation of a focal plane image processor-a realization of the near-sensor image processing concept
Sequential Element Timing Parameter Definition Considering Clock Uncertainty
Placement for large-scale floating-gate field-programable analog arrays
Energy Efficiency Optimization Through Codesign of the Transmitter and Receiver in High-Speed On-Chip Interconnects
An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM
Defect Detection in Transparent Printed Electronics Using Learning-Based Optical Inspection
FinCANON: A PVT-Aware Integrated Delay and Power Modeling Framework for FinFET-Based Caches and On-Chip Networks
Efficient Vector Graphics Rasterization Accelerator Using Optimized Scan-Line Buffer
Component selection for high-performance pipelines
Hardware-software partitioning and pipelined scheduling of transformative applications
An Energy-Efficient GeMM-Based Convolution Accelerator With On-the-Fly im2col
Estimating probabilistic timing performance for real-time embedded systems
An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS
CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects
A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
FPGA prototyping of a RISC processor core for embedded applications
A Compact 0.3-V Class AB Bulk-Driven OTA
Multikernel Data Partitioning With Channel on OpenCL-Based FPGAs
Scaling trends of on-chip power distribution noise
Edge Word-Line Reliability Problem in 3-D NAND Flash Memory: Observations, Analysis, and Solutions
Hotspots Elimination and Temperature Flattening in VLSI Circuits
Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies
A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic
A Highly Efficient Ultralow Photovoltaic Power Harvesting System With MPPT for Internet of Things Smart Nodes
Algorithm and Architecture Design of Adaptive Filters With Error Nonlinearities
Aging Management Using a Reconfigurable Switch Network for Arrays of Nonideal Power Cells
Design and analysis of a dynamically reconfigurable three-dimensional FPGA
A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm
2.31-Gb/s/ch Area-Efficient Crosstalk Canceled Hybrid Capacitive Coupling Interconnect for 3-D Integration
Self-Timed Adaptive Digit-Serial Addition
Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing
A practical current sensing technique for I DDQ testing
VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm
LECTOR: a technique for leakage reduction in CMOS circuits
Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances
A Low-Power High-Speed Comparator for Precise Applications
Highly-Parallel Decoding Architectures for Convolutional Turbo Codes
A Multiscale Anisotropic Thermal Model of Chiplet Heterogeneous Integration System
An Efficient Accelerator for Dehazing Neural Network Based on Physical Perception Model and Cross-Scale Pixel Attention
A model for battery lifetime analysis for organizing applications on a pocket computer
Machine-Learning-Based Ranking of Cell Layout Delay Considering Layout-Dependent Effects
Computing support-minimal subfunctions during functional decomposition
Circuit-Level Design Approaches for Radiation-Hard Digital Electronics
All-Digital Duty-Cycle Corrector With a Wide Duty Correction Range for DRAM Applications
On-chip induction modeling: basics and advanced methods
Clock Distribution Networks in 3-D Integrated Systems
Throughput optimized architectural synthesis
Enhancing Model Order Reduction for Nonlinear Analog Circuit Simulation
An 8-Bit in Resistive Memory Computing Core With Regulated Passive Neuron and Bitline Weight Mapping
A Flexible and Energy-Efficient Convolutional Neural Network Acceleration With Dedicated ISA and Accelerator
ALT: Area-Efficient and Low-Latency FPGA Design for Torus Fully Homomorphic Encryption
Synthesis Algorithm for Application-Specific Homogeneous Processor Networks
Improving Linear Test Data Compression
A 0.9-5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration
Trident: Comprehensive Choke Error Mitigation in NTC Systems
FPGA-Based Bit Error Rate Performance Measurement of Wireless Systems
A 10-bit 200-MS/s Zero-Crossing-Based Pipeline ADC in 0.13-µm CMOS Technology
A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM)
DiffAccel: Accelerating Diffusion Models Through Adaptive Feature Optimization and Dynamic Hardware Adaptation
Reliable Hardware Watermarks for Deep Learning Systems
A Fast Leakage-Aware Green's-Function-Based Thermal Simulator for 3-D Chips
Lowering power consumption in concurrent checkers via input ordering
Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs
An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set 2n+1, 2n, 2n-1
A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies
On-chip traffic modeling and synthesis for MPEG-2 video applications
Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation
An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs
Assessment of on-chip wire-length distribution models
RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors
Efficient Analog Circuits for Boolean Satisfiability
Per-Device Adaptive Test for Analog/RF Circuits Using Entropy-Based Process Monitoring
A VLSI Majority-Logic Device Based on Spin Transfer Torque Mechanism for Brain-Inspired Computing Architecture
Implicit FSM decomposition applied to low-power design
VLSI compressor design with applications to digital neural networks
Efficient Error Detection Cryptographic Architectures Benchmarked on FPGAs for Montgomery Ladder
A Simple Miller Compensation With Essential Bandwidth Improvement
WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks
Minimizing memory access energy in embedded systems by selective instruction compression
An On-Chip Relaxation Oscillator With Comparator Delay Compensation
Sequence-Aware Watermark Design for Soft IP Embedded Processors
A VLSI priority packet queue with inheritance and overwrite
CC-SPRA: Correlation Coefficients Approach for Signal Probability-Based Reliability Analysis
BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture
Higher Radix and Redundancy Factor for Floating Point SRT Division
Nanomagnetic Logic Microprocessor: Hierarchical Power Model
Dual-Quality 4: 2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers
Low-Power, Highly Reliable Dynamic Thermal Management by Exploiting Approximate Computing
Compute-in-Memory Technologies and Architectures for Deep Learning Workloads
Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino Logic
A New Static Compaction of Deterministic Test Sets
A 60-GHz Transmission Line Phase Shifter Using Varactors and Tunable Inductors in 65-nm CMOS Technology
Four-phase micropipeline latch control circuits
Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling
Architectural design and analysis of learnable self-feedback ratio-memory cellular nonlinear network (SRMCNN) for nanoelectronic systems
Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network
Cell-based layout techniques supporting gate-level voltage scaling for low power
Clock Delayed Domino Logic With Efficient Variable Threshold Voltage Keeper
Variable Conversion Approach for Design Optimization of Low-Voltage Low-Pass Filters
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers
Signal Assignment to Hierarchical Memory Organizations for Embedded Multidimensional Signal Processing Systems
Multi-Gb/s LDPC Code Design and Implementation
De-Embedding Methodology to Characterize Linearity of Active Filters Under Process Variations
Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage
An Error Compensation Technique for Low-Voltage DNN Accelerators
Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits
Formal-Analysis-Based Trace Computation for Post-Silicon Debug
A Self-Calibrated DLL-Based Clock Generator for an Energy-Aware EISC Processor
Dynamic Partial Reconfiguration of Customized Single-Row Accelerators
A Highly Efficient Conditional Feedthrough Pulsed Flip-Flop for High-Speed Applications
ACBN: Approximate Calculated Batch Normalization for Efficient DNN On-Device Training Processor
Introduction to generalized symbolic trajectory evaluation
Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures
A cost-effective VLSI architecture for anisotropic texture filtering in limited memory bandwidth
An All-Digital Time-Domain Smart Temperature Sensor With a Cost-Efficient Curvature Correction
An Ultralow Power Subthreshold CMOS Voltage Reference Without Requiring Resistors or BJTs
Energy/Lifetime Cooptimization by Cache Partitioning With Graceful Performance Degradation
10-bit 30-MS/s SAR ADC Using a Switchback Switching Method
Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks
Electro-Thermal Analysis of Multi-Fin Devices
Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation
BTI Aging Analysis and Mitigation for Differential Input In-Memory Computing SRAMs
Field programmable gate arrays and floating point arithmetic
A Predictive Model for Fluid-Control Codesign of Paper-Based Digital Biochips Following a Machine Learning Approach
SC-IMC: Algorithm-Architecture Co-Optimized SRAM-Based In-Memory Computing for Sine/Cosine and Convolutional Acceleration
Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography
VLSI Implementation of BCH Error Correction for Multilevel Cell NAND Flash Memory
A Saliency-Driven LCD Power Management System
Temporal Partitioning Data Flow Graphs for Dynamically Reconfigurable Computing
Application-Specific MPSoC Reliability Optimization
Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2022
Design of a low power wide-band high resolution programmable frequency divider
Oscillation and Transition Tests for Synchronous Sequential Circuits
Adaptive On-Chip Power Supply With Robust One-Cycle Control Technique
A High-Throughput Hardware Design for the AV1 Decoder Intraprediction
A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell
Edge PoolFormer: Modeling and Training of PoolFormer Network on RRAM Crossbar for Edge-AI Applications
Design and Analysis of Sub-Sampling Phase-Locked Loop for Quantum Computing
SiPGuard: Run-Time System-in-Package Security Monitoring via Power Noise Variation
New 2-D Eye-Opening Monitor for Gb/s Serial Links
0.4-1 GHz Subsampling Mixer-First RF Front-End With 50-dB HRR, +10-dBm IB-IIP3 in 65-nm CMOS
Circuit activity based logic synthesis for low power reliable operations
A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications