yusuke1997/dblp-id-title huggingface dataset:
A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration
CMOS Optical PUFs Using Noise-Immune Process-Sensitive Photonic Crystals Incorporating Passive Variations for Robustness
A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array
A Modular, Direct Time-of-Flight Depth Sensor in 45/65-nm 3-D-Stacked CMOS Technology
A Wideband Receiver With Resonant Multi-Phase LO and Current Reuse Harmonic Rejection Baseband
A gallium-arsenide digital phase shifter for clock and control signal distribution in high-speed digital systems
A 2.1-Mpixel Organic Film-Stacked RGB-IR Image Sensor With Electrically Controllable IR Sensitivity
A Frequency-Agile RF Frontend Architecture for Multi-Band TDD Applications
High-performance BiCMOS 100 K-gate array
Digital Adaptive IIP2 Calibration Scheme for CMOS Downconversion Mixers
Compressed Sensing Analog Front-End for Bio-Sensor Applications
A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection
A 81-dB Dynamic Range 16-MHz Bandwidth ΔΣ Modulator Using Background Calibration
A CMOS transceiver for 10-Mb/s and 100-Mb/s Ethernet
A 60-GHz Dual-Mode Class AB Power Amplifier in 40-nm CMOS
A 40*40 CCD/CMOS absolute-value-of-difference processor for use in a stereo vision system
A CMOS 210-GHz Fundamental Transceiver With OOK Modulation
Design of a Low-Power, High-Data-Rate, and Crystal-Less All-Digital IR-UWB Transmitter for High-Density Neural Implants
A BiCMOS W-Band 2×2 Focal-Plane Array With On-Chip Antenna
A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver
A 64-Channel Transmit Beamformer With ±30-V Bipolar High-Voltage Pulsers for Catheter-Based Ultrasound Probes
Bufferless broadcasting: a low power distributed circuit technique for broadcasting 10-Gb/s chip input signals
A 0.8-V Resistor-Based Temperature Sensor in 65-nm CMOS With Supply Sensitivity of 0.28 °C/V
A 1-V CMOS D/A converter with multi-input floating-gate MOSFET
Picowatt-Power Super-Cutoff Analog Building Blocks and 78-pW Battery-Less Wake-Up Receiver for Light-Harvested Near-Always-On Operation
Electronic-Photonic Integrated Circuit for 3D Microimaging
A fast pump-down V BB generator for sub-1.5-V DRAMs
A 0.033-mm 2 21.5-aF to 114.9-aF Resolution Continuous-Time Δ Σ Capacitance-to-Digital Converter Achieving Parasitic Capacitance Immunity Up to 480 pF
Physical random number generator based on MOS structure after soft breakdown
A 0.038-mm 2 SAW-Less Multiband Transceiver Using an N-Path SC Gain Loop
A 2.30 NEF Split-Steering Amplifier for Switched-Capacitor Circuits With -14.2-dB CM-CM Gain and 100-V/μs Slew Rate
A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth
A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise
High-speed low-power ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage
Single-chip surface micromachined integrated gyroscope with 50°/h Allan deviation
The role of VLSI in multimedia
A CMOS Wideband Watt-Level 4096-QAM Digital Power Amplifier Using Reconfigurable Power-Combining Transformer
Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM
A 10-b 185-MS/s track-and-hold in 0.35-μm CMOS
A 0.022 mm 2 98.5 dB SNDR Hybrid Audio ΔΣ Modulator With Digital ELD Compensation in 28 nm CMOS
A Low-Noise Digital PLL With an Adaptive Common-Mode Resonance Tuning Technique for Voltage-Biased Oscillators
A Subthreshold Voltage Reference With Scalable Output Voltage for Low-Power IoT Systems
A Precision Low-TC Wide-Range CMOS Current Reference
A 3-D Camera With Adaptable Background Light Suppression Using Pixel-Binning and Super-Resolution
A distributed selector IC using GaAs MESFET's with multilayer-interconnection structure
A 10.7-MHz switched-capacitor bandpass filter
A Reconfigurable Single-Photon-Counting Integrating Receiver for Optical Communications
A wafer-scale 170000-gate FFT processor with built-in test circuits
Fast-switching frequency synthesizer with a discriminator-aided phase detector
In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations
A programmable analog cellular neural network CMOS chip for high speed image processing
A wideband CMOS sigma-delta modulator with incremental data weighted averaging
The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server
A Battery-Less Thermoelectric Energy Harvesting Interface Circuit With 35 mV Startup Voltage
3.5-Gb/s⨉4-ch Si bipolar LSI's for optical interconnections
A 4th-order active-G m -RC reconfigurable (UMTS/WLAN) filter
A 21-dm-OP 1 dB 20.3%-Efficiency -131.8-dBm/Hz-Noise $X$ -Band Cartesian Error Feedback Transmitter With Fully Integrated Power Amplifier in 65-nm CMOS
Parallel implementation of a 4*4-bit multiplier using a modified Booth's algorithm
Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs
Monolithic optical position encoder with on-chip photodiodes
Mixed-mode correlator for micropower acoustic transient classification
High-speed DRAM architecture development
Nanowatt, Sub-nS OTAs, With Sub-10-mV Input Offset, Using Series-Parallel Current Mirrors
A small-signal model for the frequency-dependent drain admittance in floating-substrate MOSFET's
A 1.3 GHz SOI CMOS test chip for low-power high-speed pulse processing
A 2 MHz Bandwidth TMR-Based Contactless Current Sensor With Ping-Pong Auto-Zeroing and SAR-Assisted Offset Calibration
A 31.3-dBm Bulk CMOS T/R Switch Using Stacked Transistors With Sub-Design-Rule Channel Length in Floated p-Wells
A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement
Reply to Comments on "A Digitally Modulated Polar CMOS Power Amplifier With a 20-MHz Channel Bandwidth"
Design of a Compact, Highly Efficient, and High-Power Q-/V-Band SiGe HBT Cascode Power Amplifier With a Four-Way Wilkinson Power Combiner Balun
Supply-Scaling for Efficiency Enhancement in Distributed Power Amplifiers
A new high-dynamic range dual-loop power-to-current amplifier
A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement
A Single-Inductor Step-Up DC-DC Switching Converter With Bipolar Outputs for Active Matrix OLED Mobile Display Panels
2 GHz$rm Q$-Enhanced Active Filter With Low Passband Distortion and High Dynamic Range
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
A Single-Trim Frequency Reference Achieving ±120 ppm Accuracy From -50 °C to 170 °C
Power and temperature control on a 90-nm Itanium family processor
A 0.5-mΩ/√Hz Dry-Electrode Bioimpedance Interface With Current Mismatch Cancellation and Input Impedance of 100 MΩ at 50 kHz
Estimation methods for quality factors of inductors fabricated in silicon integrated circuit process technologies
A bootstrapped bipolar CMOS (B 2 CMOS) Gate for low-voltage applications
A 23-μW Keyword Spotting IC With Ring-Oscillator-Based Time-Domain Feature Extraction
A single-chip GaAs RF transceiver for 1.9-GHz digital mobile communication systems
A 92-mW Real-Time Traffic Sign Recognition System With Robust Illumination Adaptation and Support Vector Machine
A 2-ns detecting time, 2- mu m CMOS built-in current sensing circuit
A 12 bit 100 MS/s SAR-Assisted Digital-Slope ADC
Standby/active mode logic for sub-1-V operating ULSI memory
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking
A 28-GHz Beam-Space MIMO RX With Spatial Filtering and Frequency-Division Multiplexing-Based Single-Wire IF Interface
A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology
A voltage reduction technique for battery-operated systems
A Monolithically Integrated Pressure/Oxygen/Temperature Sensing SoC for Multimodality Intracranial Neuromonitoring
A 13.56-MHz Wireless Power Transfer System With Enhanced Load-Transient Response and Efficiency by Fully Integrated Wireless Constant-Idle-Time Control for Biomedical Implants
Area-efficient linear regulator with ultra-fast load regulation
A 13-b 10-Msample/s ADC digitally calibrated with oversampling delta-sigma converter
A Thin-Film, a-IGZO, 128b SRAM and LPROM Matrix With Integrated Periphery on Flexible Foil
BiCMOS circuit technology for a 704 MHz ATM switch LSI
A 2.5- to 3.5-Gb/s Adaptive FIR Equalizer With Continuous-Time Wide-Bandwidth Delay Line in 0.25-$muhbox m$CMOS
Multiphase sine-shaper circuit
An Asynchronous Sampling-Based 128x128 Direct Photon-Counting X-Ray Image Detector with Multi-Energy Discrimination and High Spatial Resolution
SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors
A 1 MHz Bandwidth, 6 GHz 0.18 µm CMOS Type-I ΔΣ Fractional-NSynthesizer for WiMAX Applications
Low-Power, Low-Cost CMOS Direct-Conversion Receiver Front-End for Multistandard Applications
A transistor-only switched current sigma-delta A/D converter for a CMOS speech CODEC
A 125-mm 2 1-Gb NAND flash memory with 10-MByte/s program speed
A Highly Integrated 1.8 GHz Frequency Synthesizer Based on a MEMS Resonator
A low-power SRAM using hierarchical bit line and local sense amplifiers
A 1-V 10-MHz clock-rate 13-bit CMOS ΔΣ modulator using unity-gain-reset op amps
A CMOS Time-of-Flight Depth Image Sensor With In-Pixel Background Light Cancellation and Phase Shifting Readout Technique
A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture
A 700-MHz 1-W fully differential CMOS class-E power amplifier
A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET
Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits
A 1 V Wireless Transceiver for an Ultra-Low-Power SoC for Biotelemetry Applications
A 28-GHz SiGe BiCMOS PA With 32% Efficiency and 23-dBm Output Power
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing
An 80 GHz Low-Noise Amplifier Resilient to the TX Spillover in Phase-Modulated Continuous-Wave Radars
An Embedded DRAM Technology for High-Performance NAND Flash Memories
Jitter and phase noise in ring oscillators
A CMOS time to digital converter IC with 2 level analog CAM
On the design and implementation of a lossless data compression and decompression chip
A 9-Mb HZO-Based Embedded FeRAM With 10-Cycle Endurance and 5/7-ns Read/Write Using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier
First Demonstration of Distributed Amplifier MMICs With More Than 300-GHz Bandwidth
Analysis and Design of mm-Wave Frequency Dividers Based on Dynamic Latches With Load Modulation
Errata for "A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO"
A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration
A low glitch 14-b 100-MHz D/A converter
Introduction to the Special Issue on the 2020 Symposium on VLSI Circuits
A 0.2-2 Gb/s 6x OSR Receiver Using a Digitally Self-Adaptive Equalizer
Design and Analysis of Low-Voltage Low-Parasitic ESD Protection for RF ICs in CMOS
A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay
A 40-nm Cryo-CMOS Quantum Controller IC for Superconducting Qubit
Corrections to "A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier"
A 400 nW Single-Inductor Dual-Input-Tri-Output DC-DC Buck-Boost Converter With Maximum Power Point Tracking for Indoor Photovoltaic Energy Harvesting
94/47-GHz regenerative frequency divider MMIC with low conversion loss
A 25 dBm Outphasing Power Amplifier With Cross-Bridge Combiners
A 32 kbyte integrated cache memory
A fully integrated 40-Gb/s clock and data recovery IC with 1: 4 DEMUX in SiGe technology
Optically Synchronized Phased Arrays in CMOS
A 0.5-V 35-µW 85-dB DR Double-Sampled ΔΣ Modulator for Audio Applications
A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chip automatic tuning
A 10-b 50 MS/s 500-mW A/D converter using a differential-voltage subconverter
A CMOS-Microfluidic Chemiluminescence Contact Imaging Microsystem
Design of a Sub-mW 960-MHz UWB CMOS LNA
A Compact 0.2-0.3-V Inverse-Class-F 23 Oscillator for Low 1/f 3 Noise Over Wide Tuning Range
BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel
A 9.8-11.5-GHz quadrature ring oscillator for optical receivers
An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design
A 700-V interface IC for power bridge circuits
A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme
Regulated Switched-Capacitor Doubler With Interleaving Control for Continuous Output Regulation
An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance
Multihit multichannel time-to-digital converter with ±1% differential nonlinearity and near optimal time resolution
A 4.69-TOPS/W Training, 2.34-μJ/Image Inference On-Chip Training Accelerator With Inference-Compatible Backpropagation and Design Space Exploration in 28-nm CMOS
A CMOS high-speed data recovery circuit using the matched delay sampling technique
An analog trimming circuit based on a floating-gate device
A 0.2-mW CMOS ΣΔ modulator for speech coding with 80 dB dynamic range
A Sub-10-pJ/bit 5-Mb/s Magnetic Human Body Communication Transceiver
A 200-MSample/s trellis-coded PRML read/write channel with analog adaptive equalizer and digital servo
A Reconfigurable Sliding-IF Transceiver for 400 MHz/2.4 GHz IEEE 802.15.6/ZigBee WBAN Hubs With Only 21% Tuning Range VCO
A 28-GHz Flip-Chip Packaged Chireix Transmitter With On-Antenna Outphasing Active Load Modulation
High-frequency phase-locked loops in monolithic bipolar technology
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 × 128 I/Os Using TSV Based Stacking
Erratum to "High-Power Radiation at 1 THz in Silicon: A Fully Scalable Array Using a Multi-Functional Radiating Mesh Structure"
A reconfigurable VLSI neural network
A 14-bit digitally self-calibrated pipelined ADC with adaptive bias optimization for arbitrary speeds up to 40 MS/s
Guest Editorial Introduction to the Special Section on the 2025 IEEE International Solid-State Circuits Conference (ISSCC)
Power dissipation analysis and optimization of deep submicron CMOS digital circuits
A 28-nm Automotive Flash Microcontroller With Virtualization-Assisted Processor Supporting ISO26262 ASIL D
A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting
A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control
A High-Voltage Class-D Power Amplifier With Switching Frequency Regulation for Improved High-Efficiency Output Power Range
Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter
A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors
Digitally programmable switched-current FIR filter for low-voltage applications
On the use of MOS varactors in RF VCOs
Word-line architecture for highly reliable 64-Mb DRAM
Quadrature bandpass ΔΣ modulation for digital radio
A 0.013 mm 2 , 5 µW , DC-Coupled Neural Signal Acquisition IC With 0.5 V Supply
A 66-MHz DSP-augmented RAMDAC for smooth-shaded graphic applications
A 120 GHz Fully Integrated 10 Gb/s Short-Range Star-QAM Wireless Transmitter With On-Chip Bondwire Antenna in 45 nm Low Power CMOS
A 3-D-Integrated Silicon Photonic Microring-Based 112-Gb/s PAM-4 Transmitter With Nonlinear Equalization and Thermal Control
A 123-mW W-CDMA uplink baseband receiver IC with beamforming capability
Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers
An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display
A 2.5-5-V Input 100-V Output 86.2% Peak Efficiency Fibonacci-Dickson Hybrid Converter for Acoustic Surface Audio Driver
A 16-18.8-GHz Sub-Integer-N Frequency Synthesizer for 60-GHz Transceivers
Design of a 0.6-V, 429-MHz FSK Transceiver Using Q-Enhanced and Direct Power Transfer Techniques in 90-nm CMOS
An Eight-Lane 800-Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5-nm FinFET Process
18-GHz 1/8 dynamic frequency divider using Si bipolar technologies
A Spike-Latency Transceiver With Tunable Pulse Control for Low-Energy Wireless 3-D Integration
A Blocker-Tolerant Receiver With VCO-Based Non-Uniform Multi-Level Time-Approximation Filter
A 240-frames/s 2.1-Mpixel CMOS Image Sensor With Column-Shared Cyclic ADCs
A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC's Second-/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM
A Sub- μ W Embedded CMOS Temperature Sensor for RFID Food Monitoring Application
The on-chip 3-MB subarray-based third-level cache on an Itanium microprocessor
A Multi-Loop-Controlled AC-Coupling Supply Modulator With a Mode-Switching CMOS PA in an EER System With Envelope Shaping
Measurement and Analysis of Variability in 45 nm Strained-Si CMOS Technology
3.3-V, 200-Ms/s BiCMOS comparator for current-mode interpolation using a transconductance stage
Accurate SI filters using RGC integrators
A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, -98 dB THD, and 79 dB SNDR
A 10-bit video BiCMOS track-and-hold amplifier
A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference
PRESTO: A Processing-in-Memory-Based k-SAT Solver Using Recurrent Stochastic Neural Network With Unsupervised Learning
Introduction to the Special Section on the 2008 Bipolar/BiCMOS Circuits and Technology Meeting
Asynchronous VLSI neural networks using pulse-stream arithmetic
A 22-nm Delta-Sigma Computing-In-Memory SRAM Macro With Near-Zero-Mean Outputs and LSB-First ADCs for Edge AI Processing
A 175-MV multiply-accumulate unit using an adaptive supply voltage and body bias architecture
Design Considerations for a 6 Bit 20 GS/s SiGe BiCMOS Flash ADC Without Track-and-Hold
A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator
Si bipolar 2-GHz 6-bit flash A/D conversion LSI
A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS
A wide-bandwidth Si/SiGe HBT direct conversion sub-harmonic mixer/downconverter
A 19.4-nJ/Decision, 364-K Decisions/s, In-Memory Random Forest Multi-Class Inference Accelerator
Improved compact modeling of output conductance and cutoff frequency of bipolar transistors
A 950 nW Analog-Based Data Reduction Chip for Wearable EEG Systems in Epilepsy
Statistical modeling of device mismatch for analog MOS integrated circuits
8 Gb/s 8:1 multiplexer and 1:8 demultiplexer IC's using GaAs DCFL circuit
An architecture for high-performance/small-area multipliers for use in digital filtering applications
Delay propagation effect in transistor gates
Hotplate-based monolithic CMOS microsystems for gas detection and material characterization for operating temperatures up to 500 °C
A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD
A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM
A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface
Scalable and Programmable Neural Network Inference Accelerator Based on In-Memory Computing
A delay model and optimization method of a low-power BiCMOS logic circuit
A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation
A 119-dBA Dynamic Range, 3.3-mW Audio CTDSM With a Class-B Resistor DAC and Continuous-Time Quantizer
A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter
A Pulsed-Coherent Lidar With Sub-10 μm Precision
Introduction to the Special Section on the 25th Bipolar/BiCMOS Circuits and Technology Meeting
Optimized sensing scheme of DRAMs
Dynamic sleep transistor and body bias for active leakage power control of microprocessors
A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS
An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels
A Fractional-N Reference Sampling PLL With Linear Sampler and CDAC Based Fractional Spur Cancellation
Three-Dimensional 128 Gb MLC Vertical nand Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming
A 3-to-8-GHz fast-hopping frequency synthesizer in 0.18-μm CMOS technology
A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET
Sequence-invariant state machines
GaAs pseudodynamic latched logic for high performance processor cores
A 90-nm Wideband Merged CMOS LNA and Mixer Exploiting Noise Cancellation
A High-Power Broadband Multi-Primary DAT-Based Doherty Power Amplifier for mm-Wave 5G Applications
A SiGe Terahertz Heterodyne Imaging Transmitter With 3.3 mW Radiated Power and Fully-Integrated Phase-Locked Loop
A 14-b, 100-MS/s CMOS DAC designed for spectral performance
A low-power 12-b analog-to-digital converter with on-chip precision trimming
A Novel Variable Inductor Using a Bridge Circuit and Its Application to a 5-20 GHz Tunable LC-VCO
A 250-Mb/s 32*32 CMOS crosspoint LSI for ATM switching systems
A 99-mm 2 0.7-W single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mb embedded DRAM for portable 422P@HL encoder system
Phase noise in digital frequency dividers
An 18 nA, 87% Efficient Solar, Vibration and RF Energy-Harvesting Power Management System With a Single Shared Inductor
A Monolithic Buck Converter With Near-Optimum Reference Tracking Response Using Adaptive-Output-Feedback
A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS
MRTP: Mobile Ray Tracing Processor With Reconfigurable Stream Multi-Processors for High Datapath Utilization
A 5-GHz frequency-doubling quadrature modulator with a ring-type local oscillator
An 852×600 pixel OLED-on-silicon color microdisplay using CMOS subthreshold-voltage-scaling current drivers
A 15-nW per Sensor Interference-Immune Readout IC for Capacitive Touch Sensors
A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS
A High-Speed Efficient 220-GHz Spatial-Orthogonal ASK Transmitter in 130-nm SiGe BiCMOS
A 0.18-μm CMOS 3.5-gb/s continuous-time adaptive cable equalizer using enhanced low-frequency gain control method
A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs
A 2.7-V 11.8-mW baseband ADC with 72-dB dynamic range for GSM applications
A 128 × 128 Single-Photon Image Sensor With Column-Level 10-Bit Time-to-Digital Converter Array
Reduction of UHF power transistor distortion with a nonuniform collector doping profile
A 28 nm FDSOI Integrated Reconfigurable Switched-Capacitor Based Step-Up DC-DC Converter With 88% Peak Efficiency
A 433-MHz 64-b quad-issue RISC microprocessor
High speed, high linearity CMOS buffer amplifier
An Error-Based Controlled Single-Inductor 10-Output DC-DC Buck Converter With High Efficiency Under Light Load Using Adaptive Pulse Modulation
A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk
Correction to "A Third-Order$Sigma Delta $Modulator in 0.18-$muhboxm$CMOS With Calibrated Mixed-Mode Integrators"
A 5-MS/s 16-bit Low-Noise and Low-Power Split Sampling SAR ADC With Eased Driving Burden
Securing Encryption Systems With a Switched Capacitor Current Equalizer
A Low-Voltage Processor for Sensing Applications With Picowatt Standby Mode
A low voltage-power 13-bit 16 MSPS CMOS pipelined ADC
A Wideband Power Amplifier MMIC Utilizing GaN on SiC HEMT Technology