yusuke1997/dblp-id-title huggingface dataset:
A Comparison of Dual Modular Redundancy and Concurrent Error Detection in Finite Impulse Response Filters Implemented in SRAM-Based FPGAs Through Fault Injection
The Study of a Dual-Mode Ring Oscillator
Adaptive order reduction scheme for high-order single-bit ΔΣ Modulators
A 0.7-MHz-10-MHz CT+DT Hybrid Baseband Chain With Improved Passband Flatness for LTE Application
Parasitic-aware RF circuit design and optimization
Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools
W-Band CMOS 4-Bit Phase Shifter for High Power and Phase Compression Points
A Converter Combination Scheme for Efficiency Improvement of PV Systems
Stochastic Analysis and Optimal Design of Majority Systems
A Compact Single-FPGA Fading-Channel Simulator
The Spectrum of a Noisy Free-Running Oscillator Explained by Random Frequency Pulling
A Low-Offset Low-Noise Sigma-Delta Modulator With Pseudorandom Chopper-Stabilization Technique
Multiple Error Detection in DNA Self-Assembly Using Coded Tiles
An Energy-Efficient Error Correction Scheme for IEEE 802.15.4 Wireless Sensor Networks
A Low-Leakage Body-Guarded Analog Switch in 0.35-μm BiCMOS and Its Applications in Low-Speed Switched-Capacitor Circuits
Prediction of Phase Noise and Spurs in a Nonlinear Fractional-N Frequency Synthesizer
A -20 dBm Passive UHF RFID Tag IC With MTP NVM in 0.13-μm Standard CMOS Process
Robust Shrinkage Normalized Sign Algorithm in an Impulsive Noise Environment
IIP3 Enhancement of Subthreshold Active Mixers
Design and Implementation of Low-Power Hardware Architecture With Single-Cycle Divider for On-Line Clustering Algorithm
Optimizing the Stage Resolution in Pipelined SAR ADCs for High-Speed High-Resolution Applications
What are Memristor, Memcapacitor, and Meminductor?
Optimization-Oriented Design of RF/Microwave Circuits Using Inverse-Linear-Input Neuro-Fuzzy-Output Space Mapping With Two Different Dimensionality Simulators
Statistics-Based Digital Background Calibration of Residue Amplifier Nonlinearity in Pipelined ADCs
Design of Multiplierless Decimation Filters Using an Extended Search of Cyclotomic Polynomials
High-Performance Four-Stage CMOS OTA Suitable for Large Capacitive Loads
Base Transformation With Injective Residue Mapping for Dynamic Range Reduction in RNS
Hardware-Efficient QR-Decomposition Using Bivariate Numeric Function Approximation
Disturbance Rejection Adaptive Fault-Tolerant Constrained Consensus for Multi-Agent Systems With Failures
Line Coding Techniques for Channel Equalization: Integrated Pulse-Width Modulation and Consecutive Digit Chopping
Compact Variable Gain Amplifier for a Multistandard WLAN/WiMAX/LTE Receiver
Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Packet Transform
Interconnect-Aware Design of Fast Large Fan-In CMOS Multiplexers
A Circuit to Eliminate Serial Skew in High-Speed Serial Communication Channels
A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS
A MURS Band Digital Quadrature Transmitter With Class-B I/Q Cell Sharing for Long Range IoT Applications
An Optically Programmable SoC for an Autonomous Mobile mm 3 -Sized Microrobot
Comparative Study of Riemann-Liouville and Caputo Derivative Definitions in Time-Domain Analysis of Fractional-Order Capacitor
A Fully Differential Band-Selective Low-Noise Amplifier for MB-OFDM UWB Receivers
A novel approach to the design of the class of triplet halfband filterbanks
A 60 nV/ √Hz <0.01%-THD ±200 mV-DC-Rejection Bio-Sensing Chopper Amplifier With Noise-Nonlinearity-Cancelling Loop
Efficient Compensation of the Nonlinearity of Solid-State Power Amplifiers Using Adaptive Sequential Monte Carlo Methods
Pseudonoise Optical Modulation for Real-Time 3-D Imaging With Minimum Interference
Always-On 674μ W@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node
An Analog CMOS Silicon Photomultiplier Using Perimeter-Gated Single-Photon Avalanche Diodes
Digital Background Correction of Harmonic Distortion in Pipelined ADCs
Analysis of emitter (source)-coupled multivibrators
RFI-induced distortion in switched-capacitor circuits
A New Population-Based Optimization Method for Online Minimization of Voltage Harmonics in Islanded Microgrids
Implications of I/Q Imbalance, Phase Noise and Noise Figure for SNR and BER of FSK Receivers
Resonant DC-DC Converter With Class-E Oscillator
Equiripple Approximation of Low-Pass FIR Filters
An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications
Fractional Order Modeling of Large Three-Dimensional RC Networks
Network-Based Quantized Control for Fuzzy Singularly Perturbed Semi-Markov Jump Systems and its Application
A 44-93-µs 250-400-mV 0.18-µm CMOS Starter for DC-Sourced Switched-Inductor Energy Harvesters
A Direct Digital Frequency Synthesizer Based on the Quasi-Linear Interpolation Method
Two-Stage-Based Polyphase Structures for Arbitrary-Integer Sampling Rate Conversion
Analysis and Modeling of Capacitive Power Transfer in Microsystems
Front and Back Illuminated Dynamic and Active Pixel Vision Sensors Comparison
GSR: A New Genetic Algorithm for Improving Source and Channel Estimates
Synchronization of Passifiable Lurie Systems Via Limited-Capacity Communication Channel
Modeling of a constant Voltage transformer
A Fractionally Delaying Complex Hilbert Transform Filter
Nighttime Vehicle Distance Measuring Systems
Hardware Implementation of a Backtracking-Based Reconfigurable Decoder for Lowering the Error Floor of Quasi-Cyclic LDPC Codes
A 0.13-µm CMOS Interface Circuit for a MEMS Resonator-Based Vacuum Measurement System
Robust Learning Over Multitask Adaptive Networks With Wireless Communication Links
Nonclassical Channel Design in MOSFETs for Improving OTA Gain-Bandwidth Trade-Off
A mux -based High-Performance Single-Cycle CMOS Comparator
Four-Way Microstrip-Based Power Combining for Microwave Outphasing Power Amplifiers
A 25mW Highly Linear Continuous-Time FIR Equalizer for 25Gb/s Serial Links in 28-nm CMOS
Wideband SAW-Less Receiver Front-End With Harmonic Rejection Mixer in 65-nm CMOS
Self-Optimizing IoT Wireless Video Sensor Node With In-Situ Data Analytics and Context-Driven Energy-Aware Real-Time Adaptation
Positive Linear Systems Consisting of n Subsystems With Different Fractional Orders
Extensible supply voltage control mechanism for low power array structure design
Dynamical Systems Guided Design and Analysis of Silicon Oscillators for Central Pattern Generators
New Delay-Dependent Global Exponential Stability Criterion for Cellular-Type Neural Networks With Time-Varying Delays
A 26-28-Gb/s Full-Rate Clock and Data Recovery Circuit With Embedded Equalizer in 65-nm CMOS
A Memory-Based Logic Block With Optimized-for-Read SRAM for Energy-Efficient Reconfigurable Computing Fabric
A Highly Linear Dual-Gain CMOS Low-Noise Amplifier for X-Band
A K-band CMOS Differential Vackar VCO With the Gate Inductive Feedback
A Differential Push-Pull Voltage Mode VCSEL Driver in 65-nm CMOS
Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy
Energy-Efficiency Analysis of Analog and Digital Compressive Sensing in Wireless Sensors
Block-level parallel processing for scaling evenly divisible images
A 6.1-nA Fully Integrated CMOS Supply Modulated OOK Transmitter in 55-nm DDC CMOS for Glasses-Free, Self-Powered, and Fuel-Cell-Embedded Continuous Glucose Monitoring Contact Lens
A Self-Calibration Technique for On-Chip Precise Clock Generator
Observability of Boolean Networks With Redundant Channels
Synchronization of coupled connected neural networks with delays
Design of Efficient Class-E Power Amplifiers for Short-Distance Communications
Area-Efficient VLSI Design of Reed-Solomon Decoder for 10GBase-LX4 Optical Communication Systems
Hopfield Neural Network Based on Estimation of Distribution for Two-Page Crossing Number Problem
A Framework of L-HC and AM-MKF for Accurate Harmonic Supportive Control Schemes
Compressed Principal Component Regression (C-PCR) Algorithm and FPGA Validation
New LMI Approach to Fuzzy H infty Filter Designs
Finding the Initial Estimate for the Diode Bias Point in Multiport Receivers
A Hybrid 3D Interconnect With 2x Bandwidth Density Employing Orthogonal Simultaneous Bidirectional Signaling for 3D NoC
A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things
High-performance Viterbi decoder with circularly connected 2-D CNN unilateral cell array
Design of Energy-Efficient High-Speed Links via Forward Error Correction
An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits
Design of a High-Data-Rate Differential Chaos-Shift Keying System
A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform
Modeling of DC-DC Buck Converters for Large-Signal Frequency Response and Limit Cycles
A Digital Implementation of Extreme Learning Machines for Resource-Constrained Devices
Hybrid 7-Level Boost Active-Neutral-Point- Clamped (H-7L-BANPC) Inverter
Small-Area and Low-Energy K -Best MIMO Detector Using Relaxed Tree Expansion and Early Forwarding
A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror
On-Chip T/R Switchable Balun for 5- to 6-GHz WLAN Applications
A multiple access scheme for chaos-based digital communication systems utilizing transmitted reference
Identification of Hammerstein systems with time-varying piecewise-linear characteristics
Robust Maximum Mixture Correntropy Criterion-Based Semi-Supervised ELM With Variable Center
Memristor Circuits: Flux - Charge Analysis Method
State Estimation for Systems With Packet Dropping and State Equality Constraints
Area-Efficient Multimode Encoding Architecture for Long BCH Codes
Delay-Dependent Robust H ∞ Filtering for Uncertain Discrete-Time Systems With Time-Varying Delay Based on a Finite Sum Inequality
The design and multiplier-less realization of software radio receivers with reduced system delay
A Submicrowatt 1.1-MHz CMOS Relaxation Oscillator With Temperature Compensation
An LDPC-Coded SCMA Receiver With Multi-User Iterative Detection and Decoding
A Class of Maximum-Period Nonlinear Congruential Generators Derived From the Rényi Chaotic Map
Nanocell Devices and Architecture for Configurable Computing With Molecular Electronics
Insight Into a Generic Interconnect Resource Model for Xilinx Virtex and Spartan Series FPGAs
Liquid Crystal Display (LCD) Supplied by Highly Integrated Dual-Side Dual-Output Switched-Capacitor DC-DC Converter With Only Two Flying Capacitors
Event-Based Adaptive Power Control in Vehicular Networked Systems With State-Dependent Bursty Fading Channels
A Novel Minimum-Size Activation Function and Its Derivative
Computation of Running Averages
Mitigation of Sampling Errors in VCO-Based ADCs
Low-Power Cache Design Using 7T SRAM Cell
Time Interleaved RF Carrier Modulations and Demodulations
Robust Set-Membership Normalized Subband Adaptive Filtering Algorithms and Their Application to Acoustic Echo Cancellation
A Ferroelectric Nonvolatile Processor with 46 $\mu $ s System-Level Wake-up Time and 14 $\mu $ s Sleep Time for Energy Harvesting Applications
A 5.2-Gb/s Low-Swing Voltage-Mode Transmitter With an AC-/DC-Coupled Equalizer and a Voltage Offset Generator
Analysis of Encoding Degradation in Spiking Sensors Due to Spike Delay Variation
A CORDIC Based Digital Hardware For Adaptive Exponential Integrate and Fire Neuron
Design and analysis of switched-capacitor-based step-up resonant converters
Nonisolation Soft-Switching Buck Converter With Tapped-Inductor for Wide-Input Extreme Step-Down Applications
An Integrated High-Voltage Low-Distortion Current-Feedback Linear Power Amplifier for Ultrasound Transmitters Using Digital Predistortion and Dynamic Current Biasing Techniques
Stability Analysis of a Charge Pump Phase-Locked Loop Using Autonomous Difference Equations
A Low-Power and High-Precision Programmable Analog Filter Bank
Continuous-Time Opinion Dynamics With Stochastic Multiplicative Noises
Dithered Sliding-Mode Control for Switched Systems
A 60-GHz 360° 5-Bit Phase Shifter With Constant IL Compensation Followed by a Normal Amplifier With ±1 dB Gain Variation and 0.6-dBm OP -1dB
Low-noise amplifier design for ultrawideband radio
An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example
Systematic Synthesis of Step-Down Switched-Capacitor Power Converter Topologies
Comments on "Estimation of Carrier Frequency Offset With I/Q Mismatch Using Pseudo-Offset Injection in OFDM Systems"
Synchronization in a Multilevel CMOS Time-to-Digital Converter
A Bio-Inspired Cochlear Heterodyning Architecture for an RF Fovea
Design of an All-Digital LVDS Driver
A Dual-Stage Boost Converter Using Two- Dimensional Adaptive Input-Sampling MPPT for Thermoelectric Energy Harvesting
A CMOS Current-Steering D/A Converter With Full-Swing Output Voltage and a Quaternary Driver
On Factor Prime Factorizations for n-D Polynomial Matrices
A CMOS RF Programmable-Gain Amplifier for Digital TV With a +9-dBm IIP3 Cross-Coupled Common-Gate LNA
On the Absence of Limit Cycles in State-Space Digital Filters With Minimum L 2 -Sensitivity
Linear Kalman Filtering Algorithm With Noisy Control Input Variable
Ultra-Dense Ring-Shaped Racetrack Memory Cache Design
Recovering Structures of Complex Dynamical Networks Based on Generalized Outer Synchronization
Planar Balanced-to-Unbalanced In-Phase Power Divider With Wideband Filtering Response and Ultra-Wideband Common-Mode Rejection
Low Complexity Fan Filters Using Multiobjective Artificial Bee Colony Optimization Aided McClellan Transformation for Directional Filtering
Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions
Optimizing Synchronizability of Multilayer Networks Based on the Graph Comparison Method
IMAGING: In-Memory AlGorithms for Image processiNG
On Chebyshev design of linear-phase FIR filters with frequency inequality constraints
An Energy-Efficient Multiplier With Fully Overlapped Partial Products Reduction and Final Addition
Analysis of Ranging Precision in an FMCW Radar Measurement Using a Phase-Locked Loop
A Disruptive Receiver Architecture Dedicated to Software-Defined Radio
A Digitally Assisted Nonlinearity Mitigation System for Tunable Channel Select Filters
An Inductive Voltage Regulator With Overdrive Tracking Across Input Voltage in Cascoded Power Stage
Universal delay-insensitive systems with buffering lines
A digital blind background capacitor mismatch calibration technique for pipelined ADC
A 2.9 GHz Variable Inductor-Based DCO With 1.3 kHz Frequency Resolution for FMCW Radar Applications
Degree of Equiripple Narrow Bandpass FIR Filter
Flicker Noise Up-Conversion due to Harmonic Distortion in Van der Pol CMOS Oscillators
A Dividerless Ring Oscillator PLL With 250fs Integrated Jitter Using Sampled Lowpass Filter
A mixed-mode polynomial cellular array processor hardware realization
Low-Complexity Symbol Detector for MIMO-OFDM-Based Wireless LANs
A Floating Buck Controlled Multi-Mode Dimmable LED Driver Using a Stacked NMOS Switch
A New Method for Designing Causal Stable IIR Variable Fractional Delay Digital Filters
A Case Study on a 2-1-1 Cascaded Continuous-Time Sigma-Delta Modulator
Hierarchical Average-Tracking Algorithm for Multiagent Systems With Unmatched Constant References Signals
Stochastic Sliding Mode Control for Parametric Uncertain Systems Using Functional Observer
Reconfigurable BPF With Constant Center Frequency and Wide Tuning Range of Bandwidth
Analysis of Oscillator Injection Locking Through Phase-Domain Impulse-Response
Closed-Form Design of Variable Fractional-Delay FIR Filters With Low or Middle Cutoff Frequencies
An Integrated Low-Noise Sensing Circuit With Efficient Bias Stabilization for CMOS MEMS Capacitive Accelerometers
A 0.5-V Capless LDO With 30-dB PSRR at 10-kHz Using a Lightweight Local Generated Supply
Multirate Simulations With Simultaneous-Solution Using Direct Integration Methods in a Partitioned Network Environment
Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm
A Lightweight Masked AES Implementation for Securing IoT Against CPA Attacks
Robustness Enhancement of a Class-C Quadrature Oscillator Using Capacitive Source Degeneration Coupling
Application-Specific Processor for Piecewise Linear Functions Computation
Robust H infty Synchronization Design of Nonlinear Coupled Network via Fuzzy Interpolation Method
A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS
A Generalized Study of Multiphase Parallel Resonant Inverters for High-Power Applications
A Low-Power Low-Cost GFSK Demodulator With a Robust Frequency Offset Tolerance
Fast-Settling Feedforward Automatic Gain Control Based on a New Gain Control Approach
Performance of MIMO Relay DCSK-CD Systems Over Nakagami Fading Channels
High Speed Speculative Multipliers Based on Speculative Carry-Save Tree
Robust Passive Control for Uncertain Time-Delay Singular Systems
A Power-Delay and Area Efficient Voltage Level Shifter Based on a Reflected-Output Wilson Current Mirror Level Shifter
Capacitive Inter-Chip Data and Power Transfer for 3-D VLSI
Novel Field-Support Vector Regression-Based Soft Sensor for Accurate Estimation of Solar Irradiance
A Wideband Subharmonic Mixer With Low Conversion Loss and High Port-to-Port Isolations
Network Essentiality
Improving Digital-to-Analog Converter Linearity by Large High-Frequency Dithering
Corrections to "MRC-Based RNS Reverse Converters for the Four-Moduli Sets 2 n +1, 2 n -1, 2 n , 2 2n+1 -1 and 2 n +1, 2 n -1, 2 2n , 2 2n+1 -1"
A Subharmonically Injection-Locked All-Digital PLL Without Main Divider
Temperature control by chip-implemented adaptive recurrent fuzzy controller designed by evolutionary algorithm
Improved Delay-Dependent Globally Asymptotic Stability Criteria for Neural Networks With a Constant Delay
Adaptive Algorithm for Sparse System Identification Based on Hard-Thresholding Techniques
Application-Specific Instruction-Set Processor for Control of Multi-Rail DC-DC Converter Systems
Analysis and design of class E amplifier with shunt capacitance composed of nonlinear and linear capacitances
A Basis-Function Canonical Piecewise-Linear Approximation
Switched-Capacitor/Switched-Inductor Structures for Getting Transformerless Hybrid DC-DC PWM Converters
A 5-GHz Subharmonic Injection-Locked Oscillator and Self-Oscillating Mixer
A Low-Power Compression-Based CMOS Image Sensor With Microshift-Guided SAR ADC
Regulated Charge Pump With New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process
A High-Linearity Wideband Common-Gate LNA With a Differential Active Inductor
Dual AC Boosting Compensation Scheme for Multistage Amplifiers
Ultra-Low-Voltage CMOS Crystal Oscillators
A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS
CMOS High-CMRR Current Output Stages
Schottky Diode Large-Signal Equivalent-Circuit Parameters Extraction for High-Efficiency Microwave Rectifying Circuit Design
Space-Frequency Parallel Transmitter Diversity Techniques for Three Pre-Coded OFDM Systems
Nondegeneracy Conditions for Active Memristive Circuits
Load-Independent Current Control Technique of a Single-Inductor Multiple-Output Switching DC-DC converter
Using the Dynamic Power Source Technique to Reduce TCAM Leakage Power
Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps
Robustness of Link Prediction Under Network Attacks
Design of arbitrary-phase variable digital filters using SVD-based vector-array decomposition
Fully Automated RF/Microwave Filter Tuning by Extracting Human Experience Using Fuzzy Controllers
A New Algorithm for High-Speed Modular Multiplication Design
A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching
Impedance-Based Local Stability Criterion for DC Distributed Power Systems
A 330-µW 400-MHz BPSK Transmitter in 0.18- µm CMOS for Biomedical Applications
On the design and multiplierless realization of perfect reconstruction triplet-based FIR filter banks and wavelet bases
High-Speed ECC Processor Over NIST Prime Fields Applied With Toom-Cook Multiplication
RLWE-Oriented High-Speed Polynomial Multiplier Utilizing Multi-Lane Stockham NTT Algorithm
An H infty Approach for Robust Calibration of Cascaded Sigma-Delta Modulators
Complex Oscillation-Based Test and Its Application to Analog Filters
A Speed-Enhancing Dual-Trial Instantaneous Switching Architecture for SAR ADCs
Analysis of the Flash ADC Bandwidth-Accuracy Tradeoff in Deep-Submicron CMOS Technologies
A 7-bit, 1.4 GS/s ADC With Offset Drift Suppression Techniques for One-Time Calibration
BER-Aware ADC-Based 2×1 MIMO Blind Receiver for High Speed Broadband Communication Links
A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems
High-Selectivity Single-Ended/Balanced DC-Block Filtering Impedance Transformer and Its Application on Power Amplifier
Discrete-Time Modeling and Stability Analysis of Periodic Orbits With Sliding for Switched Linear Systems
Impedance-Sensing CMOS Chip for Noninvasive Light Detection in Integrated Photonics
A Reconfigurable Rectifier With Optimal Loading Point Determination for RF Energy Harvesting From -22 dBm to -2 dBm
Inverse Class-E Amplifier With Transmission-Line Harmonic Suppression
260-µW DCO With Constant Current Over PVT Variations Using FLL and Adjustable LDO
Digital Peak Current Control for Switching DC-DC Converters With Asymmetrical Dual-Edge Modulation
Design of D-Band Transformer-Based Gain-Boosting Class-AB Power Amplifiers in Silicon Technologies
Analog PLL Design With Ring Oscillators at Low-Gigahertz Frequencies in Nanometer CMOS: Challenges and Solutions
Improved Results on Statistic Information Control With a Dynamic Neural Network Identifier
Stochastic Wave-Pipelined On-Chip Interconnect
Signal and Noise Analysis of an MIMO-SSFA
Semi-Blind Most Significant Tap Detection for Sparse Channel Estimation of OFDM Systems
A QRD-RLS-Based Predistortion Scheme for High-Power Amplifier Linearization
Design and Implementation of High-Speed and Energy-Efficient Variable-Latency Speculating Booth Multiplier (VLSBM)
Fast HUB Floating-Point Adder for FPGA
A Flexible Multichannel EEG Feature Extractor and Classifier for Seizure Detection
Constrained Sampled-Data Reachability and Stabilization of Logical Control Networks
Joint Symbol and Chip Synchronization for a Burst-Mode-Communication Superregenerative MSK Receiver
On the Design of Optimal Noise Transfer Functions for Delta-Sigma Modulators
Frequency-Domain Study of Lock Range of Non-Harmonic Oscillators With Multiple Multi-Tone Injections
Distortion Contribution Analysis for Identifying EM Immunity Failures
A Power-Efficient CNN Accelerator With Similar Feature Skipping for Face Recognition in Mobile Devices
Low-Power Channel Select Filters for DVB-H Receivers
Efficiency-Improved High-Voltage Analog Power Amplifier for Driving Piezoelectric Actuators
Jitter Minimization in Digital PLLs with Mid-Rise TDCs
Sign-Extension Avoidance and Word-Length Optimization by Positive-Offset Representation for FIR Filter Design
A 9.6 nW, 8-Bit, 100 S/s Envelope-to-Digital Converter for Respiratory Monitoring
A Full Ka-Band Power Amplifier With 32.9% PAE and 15.3-dBm Power in 65-nm CMOS
A 6-bit 1.3-GS/s Ping-Pong Domino-SAR ADC in 55-nm CMOS
Guest Editorial: Special Section on the 2012 IEEE Custom Integrated Circuits Conference (CICC 2012)
Combined Parametric and Worst Case Circuit Analysis via Taylor Models
A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits
Calibration of Time-Interleaved ADCs via Hermitianity-Preserving Taylor Approximations
Finite-Time Consensus for Leader-Following Second-Order Multi-Agent Networks
Charge pump circuits with only capacitive loads: optimized design
Bit-Level Multiplierless FIR Filter Optimization Incorporating Sparse Filter Technique
Hardware Design of an Energy-Efficient High-Throughput Median Filter
Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs
Complex Dynamics in Arrays of Memristor Oscillators via the Flux-Charge Method