yusuke1997/dblp-id-title huggingface dataset:
Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters
Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint
Multiplierless Design of Folded DSP Blocks
CASCA: A Design Automation Approach for Designing Hardware Countermeasures Against Side-Channel Attacks
Application-aware snoop filtering for low-power cache coherence in embedded multiprocessors
A tool for automatic detection of deadlock in wormhole networks on chip
Configurable range memory for effective data reuse on programmable accelerators
High-level design verification of microprocessors via error modeling
Design of Hardened Embedded Systems on Multi-FPGA Platforms
Automatic Mapping of the Best-Suited DNN Pruning Schemes for Real-Time Mobile Acceleration
Sequential optimization in the absence of global reset
Holistic Optimization Framework for FPGA Accelerators
Multiterminal Pathfinding in Practical VLSI Systems with Deep Neural Networks
Low-overhead F max calibration at multiple operating points using delay-sensitivity-based path selection
Graph-based code selection techniques for embedded processors
AGENTS a distributed client-server system for leaf cell generation
Implementation, Characterization and Application of Path Changing Switch based Arbiter PUF on FPGA as a lightweight Security Primitive for IoT
Minimizing leakage power of sequential circuits through mixed- V t flip-flops and multi- V t combinational gates
Accurate Modeling of Nonideal Low-Power PWM DC-DC Converters Operating in CCM and DCM using Enhanced Circuit-Averaging Techniques
SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling
PriorMSM: An Efficient Acceleration Architecture for Multi-Scalar Multiplication
ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories
A Survey of Techniques for Cache Locking
An ILP solution to address code generation for embedded applications on digital signal processors
Power-delay optimization in VLSI microprocessors by wire spacing
A critical-path-aware partial gating approach for test power reduction
Formal hardware specification languages for protocol compliance verification
Mitigating Negative Impacts of Read Disturb in SSDs
Storage requirement estimation for optimized design of data intensive applications
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching
Demand-Driven Single- and Multitarget Mixture Preparation Using Digital Microfluidic Biochips
Deadline and Period Assignment for Guaranteeing Timely Response of the Cyber-Physical System
Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching
A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing
Distance-aware Approximate Nanophotonic Interconnect
Rectilinear Steiner trees on a checkerboard
Fast memory bank assignment for fixed-point digital signal processors
NPU-Accelerated Imitation Learning for Thermal Optimization of QoS-Constrained Heterogeneous Multi-Cores
Verifying sequential equivalence using ATPG techniques
Soft-HaT: Software-Based Silicon Reprogramming for Hardware Trojan Implementation
Universal switch modules for FPGA design
Enhancing Speculative Execution With Selective Approximate Computing
Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-Interconnect
FPGAPRO: A Defense Framework Against Crosstalk-Induced Secret Leakage in FPGA
Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits
An efficient algorithm for finding the minimal-area FPGA technology mapping
Postplacement Voltage Island Generation
PARR: Pin-Access Planning and Regular Routing for Self-Aligned Double Patterning
Modeling layout tools to derive forward estimates of area and delay at the RTL level
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
Performance-driven placement for dynamically reconfigurable FPGAs
Layout Congestion Prediction Based on Regression-ViT
Approximate Learning and Fault-Tolerant Mapping for Energy-Efficient Neuromorphic Systems
An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis
DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing
Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network
Resister: A Resilient Interposer Architecture for Chiplet to Mitigate Timing Side-Channel Attacks
Guest Editor's Introduction: Machine Learning for VLSI Physical Design
Spatio-Temporal Scheduling of Preemptive Real-Time Tasks on Partially Reconfigurable Systems
CRM_BF: A Low-Overhead, High-Efficient and Reconfigurable Operation Unit Design Approach Using the Customized Reed-Muller Unit For Boolean Functions of Sequence Cipher Algorithms
Core Placement Optimization for Multi-chip Many-core Neural Network Systems with Reinforcement Learning
PACE: A Piece-Wise Approximate Floating-Point Divider with Runtime Configurability and High Energy Efficiency
A Methodology to Recover RTL IP Functionality for Automatic Generation of SW Applications
Introduction to special section on verification challenges in the concurrent world
Genetic-Algorithm-Based FPGA Architectural Exploration Using Analytical Models
Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators
A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons
Smart-Hop Arbitration Request Propagation: Avoiding Quadratic Arbitration Complexity and False Negatives in SMART NoCs
TSocket: Thermal Sustainable Power Budgeting
Energy-Efficient LSTM Inference Accelerator for Real-Time Causal Prediction
A fast heuristic approach for parametric yield enhancement of analog designs
C-Mine: Data Mining of Logic Common Cases for Improved Timing Error Resilience with Energy Efficiency
A Canonical Test Representation for Verification of Shared-Memory Behavior in Multiprocessor Systems
Graph-Grammar-Based IP-Integration (GRIP) - An EDA Tool for Software-Defined SoCs
An Adaptive Demand-Based Caching Mechanism for NAND Flash Memory Storage Systems
An Adaptive Application Framework with Customizable Quality Metrics
Realizing In-Memory Computing using Reliable Differential 8T SRAM for Improved Latency
Wire Load Oriented Analog Routing with Matching Constraints
Multi-objective Optimization of Mapping Dataflow Applications to MPSoCs Using a Hybrid Evaluation Combining Analytic Models and Measurements
False-noise analysis using logic implications
Exact Logic and Fault Simulation in Presence of Unknowns
Detection Mechanisms for Unauthorized Wireless Transmissions
Energy-Constrained Scheduling for Weakly Hard Real-Time Systems Using Standby-Sparing
Skew-aware polarity assignment in clock tree
Simulation-based verification using Temporally Attributed Boolean Logic
How Secure Is Split Manufacturing in Preventing Hardware Trojan?
Low-power gated and buffered clock network construction
Playing the trade-off game: Architecture exploration using Coffeee
BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults
CNN-Cap: Effective Convolutional Neural Network-based Capacitance Models for Interconnect Capacitance Extraction
Optimization Algorithms for the Multiplierless Realization of Linear Transforms
CoMPSoC: A template for composable and predictable multi-processor system on chips
A high-level clustering algorithm targeting dual V dd FPGAs
Explaining Software Failures by Cascade Fault Localization
Lazy-RTGC: A Real-Time Lazy Garbage Collection Mechanism with Jointly Optimizing Average and Worst Performance for NAND Flash Memory Storage Systems
A CPU+FPGA OpenCL Heterogeneous Computing Platform for Multi-Kernel Pipeline
Energy and switch area optimizations for FPGA global routing architectures
Accelerated Soft-Error-Rate (SER) Estimation for Combinational and Sequential Circuits
Multiple wire reconnections based on implication flow graph
Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip
A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization
Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAs
Analysis of Dissipative Losses in Modular Reconfigurable Energy Storage Systems Using SystemC TLM and SystemC-AMS
Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs
Formal Modeling and Verification of a Victim DRAM Cache
Power Modeling for GPU Architectures Using McPAT
A cosimulation methodology for HW/SW validation and performance estimation
A mapping algorithm for computer-assisted exploration in the design of embedded systems
Estimation of lower bounds in scheduling algorithms for high-level synthesis
Mitigating Mode-switch through Run-time Computation of Response Time
Designing Hybrid DRAM/PCM Main Memory Systems Utilizing Dual-Phase Compression
Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs
Optimizing designs containing black boxes
Performance Evaluation of NoC-Based Multicore Systems: From Traffic Analysis to NoC Latency Modeling
System-level performance/power analysis for platform-based design of multimedia applications
Machine Learning for Electronic Design Automation: A Survey
A 36μW heartbeat-detection processor for a wireless sensor node
Hardware-Software Codesign of an Embedded Multiple-Supply Power Management Unit for Multicore SoCs Using an Adaptive Global/Local Power Allocation and Processing Scheme
ILP-Based energy minimization techniques for banked memories
VeriGen: A Large Language Model for Verilog Code Generation
Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip Multiprocessors
iTimerM: A Compact and Accurate Timing Macro Model for Efficient Hierarchical Timing Analysis
Compilation framework for code size reduction using reduced bit-width ISAs (rISAs)
A Brain-Inspired Hardware Architecture for Evolutionary Algorithms Based on Memristive Arrays
Trading Off Power Consumption and Prediction Performance in Wearable Motion Sensors: An Optimal and Real-Time Approach
A Heterogeneous Chiplet Architecture for Accelerating End-to-End Transformer Models
Incomplete Tests for Undetectable Faults to Improve Test Set Quality
SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard Scan
Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs
A 4-geometry maze router and its application on multiterminal nets
Demand-Driven Multi-Target Sample Preparation on Resource-Constrained Digital Microfluidic Biochips
Obfuscation-Based Protection Framework against Printed Circuit Boards Unauthorized Operation and Reverse Engineering
A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs
A Single-Tier Virtual Queuing Memory Controller Architecture for Heterogeneous MPSoCs
Built-in generation of multicycle functional broadside tests with observation points
An Integration Flow for Mixed-Critical Embedded Systems on a Flexible Time-Triggered Platform
Gate-Level Simulation with GPU Computing
Impact of Electrostatic Coupling on Monolithic 3D-enabled Network on Chip
Data memory design and exploration for low-power embedded systems
Component-Based Synthesis of Embedded Systems Using Satisfiability Modulo Theories
RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks
Enabling energy efficient reliability in embedded systems through smart cache cleaning
Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and Prospect
Synthesis of networks of custom processing elements for real-time physical system emulation
Satisfiability models and algorithms for circuit delay computation
A gateway node with duty-cycled radio and processing subsystems for wireless sensor networks
An Energy-aware Online Learning Framework for Resource Management in Heterogeneous Platforms
Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness
A new efficient retiming algorithm derived by formal manipulation
PSCMark: Power Side Channel-based Watermarking for SoC IPs Using Clock Gates
Array Interleaving - An Energy-Efficient Data Layout Transformation
Co-synthesis of pipelined structures and instruction reordering constraints for instruction set processors
Postscheduling buffer management trade-offs in streaming software synthesis
Achieving high encoding efficiency with partial dynamic LFSR reseeding
Incremental Concolic Testing of Register-Transfer Level Designs
An Efficient Hardware-Based Higher Radix Floating Point MAC Design
Reliability-Aware Resource Allocation and Binding in High-Level Synthesis
Incremental Analysis of Power Grids Using Backward Random Walks
A Comprehensive Survey on Electronic Design Automation and Graph Neural Networks: Theory and Applications
Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Compression
Destination-based congestion awareness for adaptive routing in 2D mesh networks
Performance-Driven Post-Processing of Control Loop Execution Schedules
Security-aware Routing and Scheduling for Control Applications on Ethernet TSN Networks
Enhanced Test Compaction for Multicycle Broadside Tests by Using State Complementation
BoA-PTA: A Bayesian Optimization Accelerated PTA Solver for SPICE Simulation
Modified Decoupled Sense Amplifier with Improved Sensing Speed for Low-Voltage Differential SRAM
Monotone bipartitioning problem in a planar point set with applications to VLSI
Handling inverted temperature dependence in static timing analysis
UCR: An Unclonable Environmentally Sensitive Chipless RFID Tag For Protecting Supply Chain
ModelGen: Automating Semiconductor Parameter Extraction with Large Language Model Agents
GraphPlanner: Floorplanning with Graph Neural Network
Manhattan-diagonal routing in channels and switchboxes
Enhancing the Reliability of MLC NAND Flash Memory Systems by Read Channel Optimization
SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation
An Optimized Cost Flow Algorithm to Spread Cells in Detailed Placement
Introducing redundant computations in RTL data paths for reducing BIST resources
A detailed power model for field-programmable gate arrays
Huffman-based code compression techniques for embedded processors
Speedups in embedded systems with a high-performance coprocessor datapath
Exploiting Instruction Set Encoding for Aging-Aware Microprocessor Design
gem5-NVDLA: A Simulation Framework for Compiling, Scheduling, and Architecture Evaluation on AI System-on-Chips
Stochastic sequential machine synthesis with application to constrained sequence generation
A3MAP: Architecture-aware analytic mapping for networks-on-chip
H -Matrix-Based Finite-Element-Based Thermal Analysis for 3D ICs
Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement
Probabilistic Model Checking for Uncertain Scenario-Aware Data Flow
System level design paradigms: Platform-based design and communication synthesis
Hierarchical Integration of Reinforcement Learning and Optimization Algorithms for Time-Efficient Design Automation of Complex Analog Circuit
Integrated Approach of Airgap Insertion for Circuit Timing Optimization
Use It or Lose It: Proactive, Deterministic Longevity in Future Chip Multiprocessors
ISOAcc: In-situ Shift Operation-based Accelerator For Efficient in-SRAM Multiplication
High-performance obstacle-avoiding rectilinear steiner tree construction
On Battery Recovery Effect in Wireless Sensor Nodes
A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations
Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture
Introduction to Special Issue on Large Language Models for Electronic System Design Automation
H3D-Transformer: A Heterogeneous 3D (H3D) Computing Platform for Transformer Model Acceleration on Edge Devices
NeuPow: A CAD Methodology for High-level Power Estimation Based on Machine Learning
Model-driven automation for simulation-based functional verification
Boosting interpolation with dynamic localized abstraction and redundancy removal
VSSD: Performance Isolation in a Solid-State Drive
IDeSyDe: Systematic Design Space Exploration via Design Space Identification
Reconfigurable content-based router using hardware-accelerated language parser
DeepOTF: Learning Equations-constrained Prediction for Electromagnetic Behavior
A New Uncertainty Budgeting-Based Method for Robust Analog/Mixed-Signal Design
Exploring Energy-Efficient Cache Design in Emerging Mobile Platforms
Share-n-Learn: A Framework for Sharing Activity Recognition Models in Wearable Systems With Context-Varying Sensors
A Metric for Quantifying Similarity between Timing Constraint Sets in Real-Time Systems
FV-LIDAC: Formally Verified Library of Input Data Aware Approximate Arithmetic Circuits
Early Stage DRC Hotspot Prediction for Mixed-Size Designs Through an Efficient Graph-Based Deep Learning
FLAG: Finding Line Anomalies (in RTL code) with Generative AI
Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources
Uncertainty Theory Based Partitioning for Cyber-Physical Systems with Uncertain Reliability Analysis
A Fast Hierarchical Adaptive Analog Routing Algorithm Based on Integer Linear Programming
Test Modification for Reduced Volumes of Fail Data
Hierarchical Scheduling of an SDF/L Graph onto Multiple Processors
Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection
A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM Cell
Energy-Efficient Progressive Remote Update for Flash-Based Firmware of Networked Embedded Systems
FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements
Automatic Correction of Arithmetic Circuits in the Presence of Multiple Bugs by Groebner Basis Modification
A data-centric chip design agent framework for Verilog code generation
Efficient memory management for hardware accelerated Java Virtual Machines
LOGIC: Logic Synthesis for Digital In-Memory Computing
Optimal Model Partitioning with Low-Overhead Profiling on the PIM-based Platform for Deep Learning Inference
Secure & Reliable 10T SRAM Cell during Read, Write and Hold Operations against Power Analysis Attack
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme
Providing SLO Compliance on NVMe SSDs Through Parallelism Reservation
ReSC: An RFID-Enabled Solution for Defending IoT Supply Chain
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog
High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications
PROTECTS: Progressive Rtl Obfuscation with ThrEshold Control Technique during architectural Synthesis
Introduction to the Special Section on Advances in Physical Design Automation
Partitioning techniques for partially protected caches in resource-constrained embedded systems
Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats
AMSnet-KG: A Netlist Dataset for LLM-based AMS Circuit Auto-design Using Knowledge Graph RAG
Optimal folding of standard and custom cells
Agglomerative-based flip-flop merging and relocation for signal wirelength and clock tree optimization
Efficient routability check algorithms for segmented channel routing
Three-layer bubble-sorting-based nonManhattan channel routing
Topological Approach to Automatic Symbolic Macromodel Generation for Analog Integrated Circuits
Automatic verification of safety and liveness for pipelined machines using WEB refinement
Hidden in Plaintext: An Obfuscation-based Countermeasure against FPGA Bitstream Tampering Attacks
ARM-CO-UP: ARM COoperative Utilization of Processors
A fast approach to computing exact solutions to the resource-constrained scheduling problem
C-testable bit parallel multipliers over GF (2 m )
Optimization of Fault-Tolerant Mixed-Criticality Multi-Core Systems with Enhanced WCRT Analysis
Compilation for compact power-gating controls
A text-compression-based method for code size minimization in embedded systems
Data-Driven Optimization of Order Admission Policies in a Digital Print Factory
Direction-Constrained Rectangle Escape Routing
Achieving autonomous power management using reinforcement learning
Two-sided Net Untangling with Internal Detours for Single-layer Bus Routing
Energy-Efficient GPU L2 Cache Design Using Instruction-Level Data Locality Similarity
On the properties of the input pattern fault model
Poor Man's Training on MCUs: A Memory-Efficient Quantized Back-Propagation-Free Approach
Programmable In-memory Computing Circuit of Fast Hartley Transform
Global array reference allocation
From VHDL to efficient and first-time-right designs: a formal approach
A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration
Adaptive Generation of Unique IDs for Digital Chips through Analog Excitation
LVS verification across multiple power domains for a quad-core microprocessor
Non-Intrusive In-Situ Requirements Monitoring of Embedded System
Decoupling Capacitance Design Strategies for Power Delivery Networks with Power Gating
Machine-learning-driven Architectural Selection of Adders and Multipliers in Logic Synthesis
An energy-efficient I/O request mechanism for multi-bank flash-memory storage systems
Auto-tuning Fixed-point Precision with TVM on RISC-V Packed SIMD Extension
Timing-driven routing for symmetrical array-based FPGAs
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design
Power-delay optimizations in gate sizing
HyperPlace: Harnessing a Large Language Model for Efficient Hyperparameter Optimization in GPU-Accelerated VLSI Placement
The Synthesis of Cyclic Dependencies with Boolean Satisfiability
Routability optimization for crossbar-switch structured ASIC design
A Yield and Reliability Improvement Methodology Based on Logic Redundant Repair with a Repairable Scan Flip-Flop Designed by Push Rule
InterAxNN: Reconfigurable and Approximate in-Memory Processing Accelerator for Ultra-Low-Power Binary Neural Network Inference in Intermittently Powered Systems
Large-scale circuit placement
Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance
Editorial to special section on networks on chip: Architecture, tools, and methodologies
Polling-Based Memory Interface
Analysis and optimization of prediction-based flow control in networks-on-chip
SwitchX : Gmin-Gmax Switching for Energy-efficient and Robust Implementation of Binarized Neural Networks on ReRAM Xbars
Lightweight Authenticated Integration and In-Field Secure Operation of System-in-Package
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation
Measurement-Based Worst-Case Execution Time Estimation Using the Coefficient of Variation
Multi-Row Guiding Template Design for Lamellar Directed Self-Assembly with Self-Aligned Via Process
Reliability analysis of memories protected with BICS and a per-word parity bit
Power Converter Circuit Design Automation Using Parallel Monte Carlo Tree Search
CBDC-PUF: A Novel Physical Unclonable Function Design Framework Utilizing Configurable Butterfly Delay Chain Against Modeling Attack
Instrumenting AMS assertion verification on commercial platforms
Test data compression using dictionaries with selective entries and fixed-length indices
Enhancements to SAT Attack: Speedup and Breaking Cyclic Logic Encryption
A Symbolic Approach to Detecting Hardware Trojans Triggered by Don't Care Transitions