yusuke1997/dblp-id-title huggingface dataset:
Reliable Concurrent Error Detection Architectures for Extended Euclidean-Based Division Over GF(2 m )
A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO
Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding
Distance-based recent use (DRU): an enhancement to instruction cache replacement policies for transition energy reduction
ANT-on-YARDS: FPGA/MPU hybrid architecture for telecommunication data processing
Traffic-Based Virtual Channel Activation for Low-Power NoC
A hardware cost minimized fast Phong shader
Multiprocessor system for high-resolution image correlation in real time
Multiterminal net routing for partial crossbar-based multi-FPGA systems
Multiplierless Unity-Gain SDF FFTs
TCPM: A Reconfigurable and Efficient Toom-Cook-Based Polynomial Multiplier Over Rings Using a Novel Compressed Postprocessing Algorithm
Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing
Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array
A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements
On the Latency and Energy of Checkpointed Superscalar Register Alias Tables
A Low-Noise Digital-to-Frequency Converter Based on Injection-Locked Ring Oscillator and Rotated Phase Selection for Fractional- $N$ Frequency Synthesis
Probabilistic Error Modeling for Nano-Domain Logic Circuits
Linear-programming-based techniques for synthesis of network-on-chip architectures
Interspike-Interval-Based Analog Spike-Time-Dependent Encoder for Neuromorphic Processors
A New Compact SD2 Positive Integer Triangular Array Division Circuit
FlooNoC: A 645-Gb/s/link 0.15-pJ/B/hop Open-Source NoC With Wide Physical Links and End-to-End AXI4 Parallel Multistream Support
Dynamic Self-Regulated Charge Pump With Improved Immunity to PVT Variations
Highly parallel and energy-efficient exhaustive minimum distance search engine using hybrid digital/analog circuit techniques
A Hardware Architecture for Columnar-Organized Memory Based on CMOS Neuron and Memristor Crossbar Arrays
McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations
Fast Transient Low-Dropout Voltage Regulator With Hybrid Dynamic Biasing Technique for SoC Application
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
Design considerations for databus charge recovery
RASHT: A Partially Reconfigurable Architecture for Efficient Implementation of CNNs
Design and Evaluation of a Printed Analog-Based Differential Physical Unclonable Function
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I - Methodology and Design Strategies
Signal and Power Integrity IO Buffer Modeling Under Separate Power and Ground Supply Voltage Variation of the Input and Output Stages
Statistical skew modeling for general clock distribution networks in presence of process variations
Fast and Low-Power Quantized Fixed Posit High-Accuracy DNN Implementation
An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop
An Information Theory Perspective for the Binary STT-MRAM Cell Operation Channel
28-nm Latch-Type Sense Amplifier Modification for Coupling Suppression
A novel high-speed sense-amplifier-based flip-flop
Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems
Design of a CMOS Chlorophyll Concentration Detector Based on Organic Chlorophyll Battery for Measuring Vegetable Chlorophyll Concentration
Pulsed wave interconnect
A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits
RPE-TCAM: Reconfigurable Power-Efficient Ternary Content-Addressable Memory on FPGAs
Selection of Primary Output Vectors to Observe Under Multicycle Tests
Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion
Simultaneous Scheduling, Allocation, Binding, Re-Ordering, and Encoding for Crosstalk Pattern Minimization During High-Level Synthesis
Design and synthesis of dynamic circuits
Energy-Efficient Encoding for High-Speed Serial Interfaces
Efficient and Correct by Construction Assertion-Based Synthesis
Multiradix Trivium Implementations for Low-Power IoT Hardware
Lithography Defect Probability and Its Application to Physical Design Optimization
Application-directed voltage scaling
Estimation for maximum instantaneous current through supply lines for CMOS circuits
Planar clock routing for high performance chip and package co-design
A Mixed-Decimation MDF Architecture for Radix-2 k Parallel FFT
Distributed Spintronic/CMOS Sensor Network for Thermal-Aware Systems
A Multimode Area-Efficient SCL Polar Decoder
Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads
HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures
A Reinforcement Learning-Based Framework for Solving the IP Mapping Problem
Differential current-sensing for on-chip interconnects
Improved Pervasive Sensing With RFID: An Ultra-Low Power Baseband Processor for UHF Tags
A VLSI architecture for a real-time code book generator and encoder of a vector quantizer
A 28-GHz 2-by-2 MIMO Transceiver Deploying Transformer Gain Equalization Technique for 5G New Radio
Autotuning of Integrated Inductive Voltage Regulator Using On-Chip Delay Sensor to Tolerate Process and Passive Variations
Techniques to Prioritize Paths for Diagnosis
Application-Aware Topology Reconfiguration for On-Chip Networks
A Single-TSV and Single-DCDL Approach for Skew Compensation of Multi-Dies Clock Synchronization in 3-D-ICs
Temperature Characteristics and Analysis of Monolithic Microwave CMOS Distributed Oscillators With ${G}_{m}$-Varied Gain Cells and Folded Coplanar Interconnects
Test Data Compression for Transparent-Scan Sequences
A High-Performance Double-Layer Counting Bloom Filter for Multicore Systems
High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree
A Highly Reliable RRAM-Based 12T2R NVSRAM Architecture With Dual-Layer ECC
A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures
Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications
Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability
Modeling of mixed control and dataflow systems in MASCOT
Unified Analog PUF and TRNG Based on Current-Steering DAC and VCO
Spread Spectrum-Based Countermeasures for Cryptographic RISC-V SoC
A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression
An On-Chip Network Fabric Supporting Coarse-Grained Processor Array
A 64-Mb Chain FeRAM With Quad BL Architecture and 200 MB/s Burst Mode
A Low-Power High-Speed Hybrid ADC With Merged Sample-and-Hold and DAC Functions for Efficient Subranging Time-Interleaved Operation
Highly Stable Reconfigurable TERO PUF Architecture for Hardware Security Applications
Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD
High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications
Gradual Diagnostic Test Generation and Observation Point Insertion Based on the Structural Distance Between Indistinguished Fault Pairs
On the Implementation of Computation-in-Memory Parallel Adder
Low-Power Digital Temperature Compensation Technique for XO Wake-Up Timers
An Analytic RLC Model for Coupled Interconnects Which Uses a Numerical Inverse Laplace Transform
Design of an Area-Effcient Million-Bit Integer Multiplier Using Double Modulus NTT
A Highly Efficient Composite Class-AB-AB Miller Op-Amp With High Gain and Stable From 15 pF Up To Very Large Capacitive Loads
A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines
Postvoiding FEM Analysis for Electromigration Failure Characterization
An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration
Fast Thermal Analysis on GPU for 3D ICs With Integrated Microchannel Cooling
An efficient merging scheme for prescribed skew clock routing
Functionally Possible Path Delay Faults With High Functional Switching Activity
Crosstalk-Induced Delay, Noise, and Interconnect Planarization Implications of Fill Metal in Nanoscale Process Technology
An 197-μJ/Frame Single-Frame Bundle Adjustment Hardware Accelerator for Mobile Visual Odometry
A Hybrid Reconfigurable Architecture and Design Methods Aiming at Control-Intensive Kernels
Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits
A Low-Power Field-Programmable Gate Array Routing Fabric
From Design to Test: A High-Speed PRBS
A Single-Chip Solution for Diagnosing Peripheral Arterial Disease
Synthesis of area-efficient and high-throughput rate data format converters
Pipelined Radix-2 k Feedforward FFT Architectures
Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks
FPGA-Based Low-Bit and Lightweight Fast Light Field Depth Estimation
5-bit 5-GS/s Noninterleaved Time-Based ADC in 65-nm CMOS for Radio-Astronomy Applications
Reducing Data Migration Overheads of Flash Wear Leveling in a Progressive Way
An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs
Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models
QDI Constant-Time Counters
Practical Approaches Toward Deep-Learning-Based Cross-Device Power Side-Channel Attack
OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application
A High-Performance Dual-Context MQ Encoder Architecture Based on Extended Lookup Table
Verification of the Power and Ground Grids Under General and Hierarchical Constraints
Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed
Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects
Coding schemes for chip-to-chip interconnect applications
A stochastic model for the interconnection topology of digital circuits
Body Bias Voltage Computations for Process and Temperature Compensation
A digitally programmable delay element: design and analysis
A Real-Time Rotation Calibration for Interchannel Offset Mismatch in Time-Interleaved SAR ADCs
PhLock: A Cache Energy Saving Technique Using Phase-Based Cache Locking
DScanPUF: A Delay-Based Physical Unclonable Function Built Into Scan Chain
Co-RAM: combinational logic synthesis applied to software partitions for mapping to a novel memory device
Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors
Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles
Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) From Circuit/Architecture Perspective
A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicers and PRTS Checker
Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs
SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability
An 8-bit 0.35-V 5.04-fJ/Conversion-Step SAR ADC With Background Self-Calibration of Comparator Offset
Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication
A Flexible-Weighted Nonbinary Searching Technique for High-Speed SAR-ADCs
A 20-nW 0.25-V Inverter-Based Asynchronous Delta-Sigma Modulator in 130-nm Digital CMOS Process
A Highly Parameterized and Efficient FPGA-Based Skeleton for Pairwise Biological Sequence Alignment
A Study on Nonlinearity in Mixers Using a Time-Varying Volterra-Based Distortion Contribution Analysis Tool
Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns
Fault Tolerant Parallel Filters Based on Error Correction Codes
A High-Precision and High-Dynamic-Range Current-Mode WTA Circuit for Low-Supply-Voltage Applications
Fault isolation for nonisolated blocks
Reconfigurable parallel inner product processor architectures
Noise Modeling and Analysis of SAR ADCs
Time-Interleaved and Circuit-Shared Dual-Channel 10 b 200 MS/s 0.18 µm CMOS Analog-to-Digital Convertor
A Hardware Acceleration of Maximum Likelihood Estimation Algorithm With Alternating Projection on FPGA
Low-Complexity Architecture of Orthogonal Matching Pursuit Based on QR Decomposition
Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation
A Source and Channel Coding Approach for Improving Flash Memory Endurance
A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique
An SAR-Assisted Noise-Shaping Pipeline ADC With Gain-Boosted Cascoded Floating Inverter Amplifier
Maximizing the Functional Yield of Wafer-to-Wafer 3-D Integration
SPI - a system model for heterogeneously specified embedded systems
Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability
EM-Aware and Lifetime-Constrained Optimization for Multisegment Power Grid Networks
The Error Analysis of Bit Weight Self-Calibration Methods for High-Resolution SAR ADCs
SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking
Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance
Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs
A Hierarchical K-Means-Assisted Scenario-Aware Reconfigurable Convolutional Neural Network
Hardware Acceleration for Media/Transaction Applications in Network Processors
Maximum power estimation for CMOS circuits using deterministic and statistical approaches
POMR: a power-aware interconnect optimization methodology
Realizing a Sub-Linear Time String-Matching Algorithm With a Hardware Accelerator Using Bloom Filters
A Skew-Normal Canonical Model for Statistical Static Timing Analysis
Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures
Synthesis for Width Minimization in the Single-Electron Transistor Array
A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2 m )
A Generic Power Management Circuit for Energy Harvesters With Shared Components Between the MPPT and Regulator
System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems
Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error
Cumulative balance testing of logic circuits
PVT Variation Tolerant Current Source With On-Chip Digital Self-Calibration
Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application
Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation
Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits
A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting
A High-Throughput Constructive Interference Precoder for 16 × MU-MIMO Systems
Improvement in Resilience of AES Design With Reconfigured CFB Mode Against Power Attacks
Enhanced-Linearity Wideband Full-Duplex Receiver With Shared Self-Interference Canceller
Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator
Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture
On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems
A Two-Channel Asynchronous SAR ADC With Metastable-Then-Set Algorithm
ArXrCiM: Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory
PDP and TPD Flexible MCML and MTCML Ultralow-Power and High-Speed Structures for Wireless and Wireline Applications
Stability-based algorithms for high-level synthesis of digital ASICs
High Speed Architectures for Finding the First two Maximum/Minimum Values
Individual wire-length prediction with application to timing-driven placement
VLSI architectures for polygon recognition
Pattern Sensitive Placement Perturbation for Manufacturability
Overview of a compiler for synthesizing MATLAB programs onto FPGAs
Secure Public Verification of IP Marks in FPGA Design Through a Zero-Knowledge Protocol
Gate-level power and current simulation of CMOS integrated circuits
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration
A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise Cancellation
Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator
CMOS Bandgap References With Self-Biased Symmetrically Matched Current-Voltage Mirror and Extension of Sub-1-V Design
Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures
Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs)
Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors
Optimized Quantum Gate Library for Various Physical Machine Descriptions
On Concurrent Detection of Errors in Polynomial Basis Multiplication
VLSI implementation of new arithmetic residue to binary decoders
Scalable Elliptic Curve Cryptosystem FPGA Processor for NIST Prime Curves
Efficient RNS Implementation of Elliptic Curve Point Multiplication Over ${\rm GF}(p)$
A New Binary-Halved Clustering Method and ERT Processor for ASSR System
An M-Cache-Based Security Monitoring and Fault Recovery Architecture for Embedded Processor
Design of synchronous and asynchronous variable-latency pipelined multipliers
An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation
Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG
A Framework for Reliability Analysis of Combinational Circuits Using Approximate Bayesian Inference
Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection
Adaptive In-Cache Streaming for Efficient Data Management
Novel MIMO Detection Algorithm for High-Order Constellations in the Complex Domain
Robust Hardware Trojan Detection Method by Unsupervised Learning of Electromagnetic Signals
High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications
Another Look at Side-Channel-Resistant Encoding Schemes
Selecting Replacements for Undetectable Path Delay Faults
Statistical Run-Time Verification of Analog Circuits in Presence of Noise and Process Variation
A low-power ROM using single charge-sharing capacitor and hierarchical bit line
Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow
SALE: Smartly Allocating Low-Cost Many-Bit ECC for Mitigating Read and Write Errors in STT-RAM Caches
A low-power high-speed class-AB buffer amplifier for flat-panel-display application
Nonvolatile Latch Designs With Node-Upset Tolerance and Recovery Using Magnetic Tunnel Junctions and CMOS
PFMAP: Exploitation of Particle Filters for Network-on-Chip Mapping
A Modular Shared L2 Memory Design for 3-D Integration
Skew Compensation Technique for Source-Synchronous Parallel DRAM Interface
An RRAM Digital Computing-in-Memory Macro With Dual-Mode Multiplication and Maximum Value Rounding Adder Tree
A Test Generation Framework for Quantum Cellular Automata Circuits
Protein Alignment Systolic Array Throughput Optimization
PAQCS: Physical Design-Aware Fault-Tolerant Quantum Circuit Synthesis
A 66-Gb/s/5.5-W RISC-V Many-Core Cluster for 5G+ Software-Defined Radio Uplinks
Testable Path Selection and Grouping for Faster Than At-Speed Testing
Dynamic Rate Neural Acceleration Using Multiprocessing Mode Support
Design of Reliable SoCs With BIST Hardware and Machine Learning
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks
Selective Writeback: Reducing Register File Pressure and Energy Consumption
Design of a configurable accelerator for moment computation
MICRO: a new hybrid test data compression/decompression scheme
HW/SW codesign techniques for dynamically reconfigurable architectures
Trimodal Scan-Based Test Paradigm
A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy
A 137-μW 1.78-mm 2 30-Frames/s Real-Time Gesture Recognition SoC for Smart Devices
A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI
Power-driven simultaneous resource binding and floorplanning: a probabilistic approach
Corrections to "An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FPGA Implementation"
PROTEUS-Lite project: dedicated to developing a telecommunication-oriented FPGA and its applications
A memory-based architecture for MPEG2 system protocol LSIs
Low Leakage Clock Tree With Dual-Threshold- Voltage Split Input-Output Repeaters
DSM interconnects: importance of inductance effects and corresponding range of length
Coprocessor design for multilayer surface-mounted PCB routing
Low-Power Multimedia System Design by Aggressive Voltage Scaling
FAMS: A FrAmework of Memory-Centric Mapping for DNNs on Systolic Array Accelerators
Memory sub-banking scheme for high throughput MAP-based SISO decoders
A High-SFDR 14-bit 500 MS/s Current-Steering D/A Converter in 0.18~µm CMOS
A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications
Spatial Distribution Measurement of Dynamic Voltage Drop Caused by Pulse and Periodic Injection of Spot Noise
Built-In Self-Repair of Small Delay Faults Occurring to TSVs in a 3D-DRAM Using an Enhanced Pulse-Vanishing Test
HIPU: A Hybrid Intelligent Processing Unit With Fine-Grained ISA for Real-Time Deep Neural Network Inference Applications
Fitted Elmore delay: a simple and accurate interconnect delay model
Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling
Locally clocked pipelines and dynamic logic
Design and analysis of low-power cache using two-level filter scheme
Design of a parameterizable silicon intellectual property core for QR-based RLS filtering
A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus
Sequoia: A High-Endurance NVM-Based Cache Architecture
Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era
Electro-thermal circuit simulation using simulator coupling
An automated design tool for analog layouts
Maximizing Common Idle Time on Multicore Processors With Shared Memory
Area Efficient ROM-Embedded SRAM Cache
RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures
A Flexible Framework for the Automatic Generation of SBST Programs
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative
Modeling and Detectability of Full Open Gate Defects in FinFET Technology
Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders
A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks
Synthesis of Analog and Mixed-Signal Circuits on a Programmable Array
Combined Architecture/Algorithm Approach to Fast FPGA Routing
The use of nanoelectronic devices in highly parallel computing systems
Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
Power modeling for high-level power estimation
Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells
Design and Optimization of Power-Gated Circuits With Autonomous Data Retention
A Low-Cost Secure Branch Predictor to Mitigate the Speculative Attacks by Disrupting Setup Phase
Scheduling and mapping in an incremental design methodology for distributed real-time embedded systems
A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation
A Case Study for NoC-Based Homogeneous MPSoC Architectures
A high-speed energy-efficient 64-bit reconfigurable binary adder