yusuke1997/dblp-id-title huggingface dataset:
Predicting Failures in Embedded Systems Using Long Short-Term Inference
An Abstract Fault Model for NAND Flash Memory
Energy-Efficient Personalized Federated Continual Learning on Edge
A Security Layer for Smartphone-to-Vehicle Communication Over Bluetooth
Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture
Verifying Cross-Layer Interactions Through Formal Model-Based Assertion Generation
Toward RISC-V CSR Compliance Testing
A Comparative Evaluation of High-Level Hardware Synthesis Using Reed-Solomon Decoder
TAFT: Thermal-Aware Hybrid Fault-Tolerant Technique for Multicore Embedded Systems
VANet: A Solution for Ventricular Arrhythmias Detection of IEGM on Embedded Devices
Reconfigurable Field Effect Transistors Design Solutions for Delay-Invariant Logic Gates
Characterizing Vulnerability of Network Interfaces in Embedded Chip Multiprocessors
Designing Neural Networks for Real-Time Systems
DATA: Throughput and Deadline-Aware Genetic Approach for Task Scheduling in Fog Networks
Automated Power Control for Mobile Laser Speckle Imaging System
Marine Monitoring System Powered by Flexible Solar Panel
Accelerated Updating Mechanisms for FPGA-Based Ternary Content-Addressable Memory
High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications
HLC-PCP: A Resource Synchronization Protocol for Certifiable Mixed Criticality Scheduling
A Novel Insight Into the Vulnerability of DDR4 DRAM Cells Across Multiple Hammering Settings
System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform
OpenNoC: An Open-Source NoC Infrastructure for FPGA-Based Hardware Acceleration
Design and Implementation of Digital Down Converter for WiFi Network
TENDRA: Targeted Endurance Attack on STT-RAM LLC
Efficient Programmable Random Variate Generation Accelerator From Sensor Noise
QLlama: An FPGA-Based Microscaling Quantization Accelerator for Energy-Efficient Llama2 Inference
A Hardware Compensation Mechanism for Embedded Energy Harvesting Emulation
Adaptive Extended Kalman Filtering for Battery State of Charge Estimation on STM32
LoFFT: Low-Voltage FFT Using Lightweight Fault Detection for Energy Efficiency
Gbit/s Throughput Under 6.3-W Lossless Hyperspectral Image Compression on Parallel Embedded Devices
Area-Optimized Constant-Time Hardware Implementation for Polynomial Multiplication
Crypto-Coding Scheme via Dynamic Interleaver for New Communication Standards
Fast and High-Accuracy Approximate MAC Unit Design for CNN Computing
Design of Fault-Tolerant Distributed Cyber-Physical Systems for Smart Environments
A Taxonomy of General Purpose Approximate Computing Techniques
RoadNet: An 80-mW Hardware Accelerator for Road Detection
CAAM: Compressor-Based Adaptive Approximate Multiplier for Neural Network Applications
Challenges and Limitations of IEEE 802.1CB-2017
A High Throughput Efficient Approach for Decoding LDPC Codes onto GPU Devices
Design and Implementation of a Universal Shift Convolutional Neural Network Accelerator
Fictitious Play Game Theory for Server Deployment Optimization in Edge-Fog Environments
An Explainable and Formal Framework for Hypertension Monitoring Using ECG and PPG
FPonAP: Implementation of Floating Point Operations on Associative Processors
An Efficient VCD Parser for Dynamic Power Estimation of Digital Integrated Circuits
Wireless Sensor Networks for Pilgrims Tracking
FPGA Implementation of an Image Classifier Using Pipelined FFT Architecture
Evaluating NTT/INTT Implementation Styles for Post-Quantum Cryptography
Trivial Bypassing in GPGPUs
A Control System for Real-Time Driving of LCoS SLM Based on FPGA
All-Digital Energy-Constrained Controller for General-Purpose Accelerators and CPUs
SMT-Based Verification of Safety-Critical Embedded Control Software
Software-Defined Watchdog Timers for Cyber-Physical Systems
Improving the Trustworthiness of Medical Device Software with Formal Verification Methods
Embedded System for Controlling Temperature, Relative Humidity, and Lighting for a Test Chamber
Efficient Exact Response Time Analysis for Fixed Priority Scheduling in Lowest Priority First-Based Feasibility Tests
A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors
Virtually Contiguous Memory Allocation in Embedded Systems: A Performance Analysis
Accelerating LSM-Tree KV Stores via Caching Hot Keys on Hybrid Zoned Storage
SAM: Software-Assisted Memory Hierarchy for Scalable Manycore Embedded Systems
FPGA Implementation of Modified SNOW 3G Stream Ciphers Using Fast and Resource Efficient Substitution Box
Infeasibility Test for Fixed-Priority Scheduling on Multiprocessor Platforms
PRIOT: Pruning-Based Integer-Only Transfer Learning for Embedded Systems
Managing Battery and Supercapacitor Resources for Real-Time Sporadic Workloads
Implementation of a Convolutional Neural Network Into an Embedded Device for Polyps Detection
Payload-XL: A Platform for the In-Orbit Validation of the BRAVE FPGA
An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA
Parallelism, Performance, and Energy-Efficiency Tradeoffs for In Situ Sensor Data Processing
Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators
Optimizing Learned Bloom Filters: How Much Should Be Learned?
Data Communication for Low Resources IoT Devices: RS485 Over Electrical Wires
Efficient Embedded System for Small Object Detection: A Case Study on Floating Debris in Environmental Monitoring
Verifying IEC 61499 Function Blocks Using Esterel
Building Relationships: Using Embedded Plug Load Sensors for Occupant Network Inference
Minimum-Energy Operation Via Error Resiliency
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs
High Speed Partial Pattern Classification System Using a CAM-Based LBP Histogram on FPGA
Embedded System for the Simultaneous Study of SAHS and Cardiac Arrhythmia
A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters
Low-Power Synchronization for Multi-IMU WSNs
FPGA-Based Accelerator for AI-Toolbox Reinforcement Learning Library
TVI PUF: A Temperature- and Voltage-Independent PUF With High Resistance to Modeling Attacks
ANT3D: Simultaneous Partitioning and Placement for 3-D FPGAs based on Ant Colony Optimization
Securing Hardware Accelerators: A New Challenge for High-Level Synthesis
Design and Implementation of a Virtual Platform of Solid-State Disks
Bringing Hardware Multithreading to the Real-Time Domain
Minimizing Capacity Degradation of Heterogeneous Batteries in a Mobile Embedded System
Using Approximate Computing for the Calculation of Inverse Matrix p th Roots
Exploiting Partially-Forgetful Memories for Approximate Computing
Automatic Generation of Heterogeneous SoC Architectures With Secure Communications
Brain-Inspired Hyperdimensional Computing: How Thermal-Friendly for Edge Computing?
High-Performance 1-Bit Full Adder With Excellent Driving Capability for Multistage Structures
GANDALF: A Fine-Grained Hardware-Software Co-Design for Preventing Memory Attacks
Optimizated Allocation of Data Variables to PCM/DRAM-based Hybrid Main Memory for Real-Time Embedded Systems
Kol-4-Gen: Stacked Kolmogorov-Arnold and Generative Adversarial Networks for Malware Binary Classification Through Visual Analysis
Lossless Hyperspectral Image Compression System-Based on HW/SW Codesign
Implications of Various Preemption Configurations in TSN Networks
Towards FHE in Embedded Systems: A Preliminary Codesign Space Exploration of a HW/SW Very Large Multiplier
Guest Editorial: Special Issue on System Level Design of Automotive Electronics/Software
Self-Adaptive Network-on-Chip Interface
Genelle et al. Revisited: Masking an AES Round With Only Four Secure ANDs
Enhanced Multicore Performance Using Novel Thread-Aware Cache Coherence and Prefetch-Control Mechanism
Enhancing Matrix Multiplication With a Monolithic 3-D-Based Scratchpad Memory
RISC-V Integrated Nested Loop Analyzer for Runtime DRAM Test Pattern Generation
Regularized Differentiable Architecture Search
Energy Efficient Outdoor Light Monitoring and Control Architecture Using Embedded System
Bactran: A Hardware Batch Normalization Implementation for CNN Training Engine
A General Embedded Underwater Acoustic Communication System Based on Advance STM32
Scheduling Dynamic Hard Real-Time Task Sets on Fully and Partially Reconfigurable Platforms
Revisiting Black-Hat HLS: A Lightweight Countermeasure to HLS-Aided Trojan Attack
Reconfigurable Computing in Next-Generation Automotive Networks
Guest Editorial Special Section on Memory Architectures and Organization
Hardware-Level Secure Coding
Reduce Refresh Operations on 3-D TLC nand Flash System via Wordline (WL) Interference
FEARLESS: A Federated Reinforcement Learning Orchestrator for Serverless Edge Swarms
Fast Filter-Based Boolean Matchers
Respiratory Rate Estimation on Embedded System
FPGA-Based RF Signal Generator for Radar Applications
Cometes: Cross-Device Mapping for Energy and Time-Aware Deployment on Edge Infrastructures
External Timed I/O Semantics Preserving Utilization Optimization for LET-Based Effect Chain
Schedulability of Blocking Threads
Parallel and Pipelined 2-D Median Filter Architecture
Reducing ADC Front-End Costs During Training of On-Sensor Printed Multilayer Perceptrons
Hardware Resource Virtualization for Dynamically Partially Reconfigurable Systems
An Analyzable Memory Controller for Hard Real-Time CMPs
Lightweight Surveillance Image Classification Through Hardware-Software Co-Design
A Hybrid Prototyping Framework in a Virtual Platform Centered Design and Verification Flow
Model-Based Test Case Generation by Reusing Models From Runtime Monitoring of Deeply Embedded Systems
Decoupled Branch Predictor for Embedded DSP
Real-Time Optical Localization and Tracking of UAV Using Ellipse Detection
Wireless Tag Sensor Network for Apnea Detection and Posture Recognition Using LSTM
MUSIC-Lite: Efficient MUSIC Using Approximate Computing: An OFDM Radar Case Study
EcoSpire: An Application Development Kit for an Ultra-Compact Wireless Sensing System
In-Situ Requirements Monitoring of Embedded Systems
LabOSat-02: Hardware and Firmware Development of an On-Board Computer for Small Satellites
Function-Level Processor (FLP): A High Performance, Minimal Bandwidth, Low Power Architecture for Market-Oriented MPSoCs
Process Algebra as a Common Framework for Hardware/Software Coverification
SCoPE: Towards a Systolic Array for SVM Object Detection
Condition Codes Evaluation on Dynamic Binary Translation for Embedded Platforms
An Energy-Efficient Heterogeneous System for Embedded Learning and Classification
Dynamic Partial Reconfiguration Profitability for Real-Time Systems
Mapping of Embedded Applications on Hybrid Networks-on-Chip with Multiple Switching Mechanisms
HypAp: A Hypervolume-Based Approach for Refining the Design of Embedded Systems
Corrections to "FDPFS: Leveraging File System Abstraction for FDP SSD Data Placement"
Using Static Analysis for Enhancing HLS Security
Optimizing Bandwidth of Call Traces for Wireless Embedded Systems
Estimation of Maximum Speed-Up in Multicore-Based Mobile Devices
Approximate Row-Merging-Based Multipliers for Neural Network Acceleration on FPGAs
Device-Free Human Motion Detection Using Single Link WiFi Channel Measurements for Building Energy Management
Design of an Embedded System for Integrated Underwater Communication and Detection
Introducing New Localization and Positioning System for Aerial Vehicles
A Novel Micro-Architecture Using a Simplified Logistic Map for Embedded Security
Iterative Histogram-Based Performance Analysis of Embedded Systems
A Graph Attention Network Approach to Partitioned Scheduling in Real-Time Systems
Power Simulation of a CubeSat: Influence of Orbit, Attitude, and Thermal Control
An Efficient Self-Healing Architecture for Improving the RAS Characteristics of RISC-V Server and Its Quantitative Evaluation Method
The Upcoming Era of Specialized Models
FedTinyWolf - A Memory Efficient Federated Embedded Learning Mechanism
PEG-C: Performance Enhancement Guaranteed Cache for Hard Real-Time Systems
Key-Recovery Attack on Enhanced PSLL Techniques
HotSniper: Sniper-Based Toolchain for Many-Core Thermal Simulations in Open Systems
Toward Efficient FPGA Accelerator DSE via Hierarchical and RM-Guided Methods
An Embedded Module of Enhanced Turbo Product Code Algorithm
Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays
Digital Circuit Design for the Square Root Computation by Means of Unfolding Techniques
A Video Elaboration System for Image Deinterlacing and Processing in Race Cars
Hierarchical Additive Hough Transform for Lane Detection
New Compact Finite-Field Arithmetic Circuits Over GF(p) Based on Spiking Neural P Systems With Communication on Request Implemented in a Low-Cost FPGA
Meeting Thermal Safe Power in Fault-Tolerant Heterogeneous Embedded Systems
A Quantitative Analysis and Optimization on the Cache Behavior Influenced by Literal Pools
Cooperative On-Chip Temperature EstimationUsing Multiple Virtual Sensors
SCALLER: Standard Cell Assembled and Local Layout Effect-Based Ring Oscillators
A Kleene Algebra of Tagged System Actors
Hardware Trojan Detection Method Against Balanced Controllability Trigger Design
Self-Tuning Model for Energy-Context Optimization in Perpetual Sensor Nodes Within IoT-Integrated Hydroponic Systems
Speed Record of AES-CTR and AES-ECB Bit-Sliced Implementation on GPUs
Design of Tri-Band Bandpass Filter Using Modified X-Shaped Structure for IoT-Based Wireless Applications
Efficient Transform Algorithms for Parallel Ultra-Low-Power IoT End Nodes
Embedded Identification of Surface Based on Multirate Sensor Fusion With Deep Neural Network
Bandwidth-Sensitivity-Aware Arbitration for FPGAs
Point Multiplication Accelerator for Arbitrary Montgomery Curves
The IoT Energy Challenge: A Software Perspective
TAFFO: Tuning Assistant for Floating to Fixed Point Optimization
Verification of Synchronous Elastic Processors
Vector-Based Dedicated Processor Architecture for Efficient Tracking in VSLAM Systems
Hardware-Assisted Detection of Malicious Software in Embedded Systems
A Flexible Architecture for Managing Vehicle Sharing Systems
A New Fast Convergence Speed q-APL Algorithm for Active Noise Control Applied to Airplane Seats
An Efficient FPGA IP Core for Automatic Modulation Classification
Employing Symmetric Dual-Rail Logic to Thwart LPA Attack
ORION3.0: A Comprehensive NoC Router Estimation Tool
An Ultra-Lightweight Transmitter for Contactless Rapid Identification of Embedded IP in FPGA
ARTS: A Framework for AI-Rooted IoT System Design Automation
Novel Substitution Box Architectural Synthesis for Lightweight Block Ciphers
Adaptive Kernel Merge and Fusion for Multi-Tenant Inference in Embedded GPUs
Hardware Acceleration of SIKE on Low-End FPGAs
Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic Injection
An Optimized Structure for Data Alignment Logic in Parallel CRC Computing Circuits
Accurate Measurement of Small Execution Times - Getting Around Measurement Errors
Combining Automated Measurement-Based Cost Modeling With Static Worst-Case Execution-Time and Energy-Consumption Analyses
Implementation in FPGA of Alternative Modulation Strategy for Energy Balancing Purposes
Fault-Tolerant Architecture for an MPEG-4 Based Video Decoder Driver
High-Efficient Approximate Subtractors for Change Detection Applications
Investigation of Security Vulnerabilities in NVM-Based Persistent TinyML Hardware
Lazy Versus Eager Conflict Detection in Software Transactional Memory: A Real-Time Schedulability Perspective
An Energy Consumption Benchmark for a Low-Power RISC-V Core Aimed at Implantable Medical Devices
Automatic Generation of Reconfiguration Blueprints for IMA Systems Using Reinforcement Learning
Configurable Multiport Memory Architecture for High-Speed Data Communication
SuperVAULT: Superparamagnetic Volatile Auxiliary Tamper-Proof Storage
Hardware and Firmware Design and Implementation of Twin 8-Bit and 32-Bit Microcontroller Boards for Research and Educational Applications
Rapid Integration of CPS Security and Safety
Compilation of Parallel Data Access for Vector Processor in Radio Base Stations
LOTUS: A Scalable Framework to Lock Multimodule Designs With One-Time Self-Destructing Key
Design of a Hardware-Efficient Approximate 4-2 Compressor for Multiplications in Image Processing
Location Monitoring System for Sailboats by GPS Using GSM/GPRS Technology
DynHD: Hyperdimensional Computing Approach for Efficient Radar Spectrum Classification
Slack-Time Computation for Temporal Robustness in Embedded Systems
Implicit Programming: A Fast Programming Strategy for nand Flash Memory Storage Systems Adopting Redundancy Methods
A Compact Portable Microwave Life-Detection Device for Finding Survivors
Revisiting Simple and Energy Efficient Embedded Processor Designs Toward the Edge Computing
Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing
Smartphone-Based Vehicle-to-Driver/Environment Interaction System for Motorcycles
Co-Synthesis of Loop Execution Patterns for Multihop Control Networks
Configurable Logic Blocks and Memory Blocks for Beyond-CMOS FPGA-Based Embedded Systems
ASIP-Based Universal Demapper for Multiwireless Standards
Time-Delayed Converter-Reshuffling: An Efficient and Secure Power Delivery Architecture
Acceleration of an Optimized Kvazaar All Intra Prediction on Embedded Systems Based on the Directional Texture Complexity
Driver Generation for IoT Nodes With Optimization of the Hardware/Software Interface
Secure Protocol for Remote Testing Critical Systems Over Public Networks Using Zero-Knowledge Proofs
Guest Editor Introduction: Embedded Security Challenge
Methodology for CNN Implementation in FPGA-Based Embedded Systems
Anatomy of Memory Corruption Attacks and Mitigations in Embedded Systems
Hechi: A Hybrid Approach for Efficient Memory Reclamation Techniques in Mobile Systems
A Dynamic Resource Management and Scheduling Environment for Embedded Multimedia and Communications Platforms
Triple-A: Early Operand Collector Allocation for Maximizing GPU Register Bank Utilization
Comments on "A Square-Root-Free Matrix Decomposition Method for Energy-Efficient Least Square Computation on Embedded Systems"
CADEN: Compression-Assisted Adaptive Encoding to Improve Lifetime of Encrypted Nonvolatile Main Memories
A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems
Implementation of ACO-Based Selection with Backward-Ant Mechanism for Adaptive Routing in Network-on-Chip Systems
Combining Thermal Maps With Inception Neural Networks for Hardware Trojan Detection
Layered Scheduling: Toward Better Real-Time Lingua Franca
Meeting Power Constraints While Mitigating Contention on Clustered Multiprocessor System
High-Speed Architecture for Successive Cancellation Decoder With Split-g Node Block
Automatic Fecal Eggs Counting in Ruminants Using Xilinx DPU
On the Retiming for Register Minimization by Means of Breadth Coefficients Matrix
Accurate Machine-Learning-Based On-Chip Router Modeling
Convolutional Neural Network-Based Signal Classification in Real Time
Embedded Software Design of Scalable Low-Area Elliptic-Curve Cryptography
RSSI-Aware Energy Saving For Large File Downloading on Smartphones
Dynamic Alternation of Huffman Codebooks for Sensor Data Compression
Virtio Front-End Network Driver for RTEMS Operating System
Parallel Enumeration of Custom Instructions Based on Multidepth Graph Partitioning
Design Space Exploration of FPGA-Based System With Multiple DNN Accelerators
Controlling a House's Air-Conditioning Using Nonlinear Model Predictive Control
Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs
Secure Register Allocation for Trusted Code Generation
Call String Sensitivity for Hardware-Based Hybrid WCET Analysis
High-Speed Serial-Parallel Multiplier in Quantum-Dot Cellular Automata
Guaranteeing That Multilevel Prioritized DNN Models on an Embedded GPU Have Inference Performance Proportional to Respective Priorities
An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures
CASH-RF: A Compiler-Assisted Hierarchical Register File in GPUs
Making Sensor Node Virtual Machines Work for Real-World Applications
A Framework of Reconfigurable Transducer Nodes for Smart Home Environments
Pythia: An Edge-First Agent for State Prediction in High-Dimensional Environments
An Instruction-Level Quality-Aware Method for Exploiting STT-RAM Read Approximation Techniques
A New Switching MVC Algorithm for Active Impulsive Noise Control
QRTT: Stateful Round Trip Time Estimation for Wireless Embedded Systems Using Q-Learning
Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators
Virtualizing Programmable Logic Controllers: Toward a Convergent Approach
CasCon: Cascaded Thermal and Electrical Current Throttling for Mobile Devices
Cross Hardware-Software Boundary Exploration for Scalable and Optimized Deep Learning Platform Design
Motion Noise Cancelation in Heartbeat Sensing using Accelerometer and Adaptive Filter
Guest Editorial: Special Issue on Rigorous Modeling and Analysis of Cyber-Physical Systems
Analysis of S-Box Hardware Resources to Improve AES Intrinsic Security Against Power Attacks
MQTT-Based Adaptive Estimation Over Distributed Network Using Raspberry Pi Pico W
Indoor Collaborative Robot Exploration: A Distributed Market-Based Approach
Design and Development of Deep Learning-Aided Vision Guidance System for AUV Homing Applications
HTree: Hardware Trojan Attack on Cache Resizing Policies
Portability Versus Efficiency Tradeoffs in MAC Implementations for Microsensor Platforms
Machine Learning for Sensor Transducer Conversion Routines
Developing Compact Models Using Regression Confidence Forge Knowledge Distillation for IMU-Based Indoor Positioning System
Are You Sitting With Good Posture? Tracking the Position of the Legs via 2-D LiDAR
A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code
i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-Signal Processing
A Uniquified Virtualization Approach to Hardware Security
High-Level Synthesis of Number-Theoretic Transform: A Case Study for Future Cryptosystems
High-Speed AES Encryptor With Efficient Merging Techniques
ViTSen: Bridging Vision Transformers and Edge Computing With Advanced In/Near-Sensor Processing
Arc Model and DDG: Deadlock Avoidance and Detection in Torus NoC
Navigating Time and Energy Tradeoffs in Reactive Heterogeneous Systems
FPGA Design of Elliptic Curve Cryptosystem (ECC) for Isomorphic Transformation and EC ElGamal Encryption
Quant-PIM: An Energy-Efficient Processing-in-Memory Accelerator for Layerwise Quantized Neural Networks
Deep Learning Inference Parallelization on Heterogeneous Processors With TensorRT
Beyond BNNs: Design and Acceleration of Sub-Bit Neural Networks Using RISC-V Custom Functional Units
Analysis of Outdoor Air Quality Using Low-Cost MEMS-Based Electronic Nose and Gas Analyzer With Multivariate Statistical Approach
FPGA Implementation of the Proposed DCNN Model for Detection of Tuberculosis and Pneumonia Using CXR Images
Scenario-Based Specification of Automotive Requirements With Quantitative Constraints and Synthesis of SL/SF Monitors
Codesign for Generation of Large Random Sequences on Zynq FPGA
Monitoring Software Execution Flow Through Power Consumption and Dynamic Time Warping
Design and Implementation of an Embedded Cardiorespiratory Monitoring System for Wheelchair Users
DeBAM: Decoder-Based Approximate Multiplier for Low Power Applications
Thermal-Aware Compilation for Register Window-Based Embedded Processors
Design of AI-Powered Hybrid Control Algorithm of Robot Vehicle for Enhanced Driving Performance
Specifying Dynamic Adaptations for Embedded Applications Using a DSL
MetaTinyML: End-to-End Metareasoning Framework for TinyML Platforms
A New XOR-Free Approach for Implementation of Convolutional Encoder
A Fully Configurable SoC-Based IR-UWB Platform for Data Acquisition and Algorithm Testing
EMGAxO: Extending Machine Learning Hardware Generators With Approximate Operators