yusuke1997/dblp-id-title huggingface dataset:
A 140 dB-DR Light-to-Digital Converter Using Current-Domain Hybrid Zoom for Baseline Cancellation and Interference Compensation
Gaussian Monocycle Pulse Transmitter Using 0.18 µm CMOS Technology With On-Chip Integrated Antennas for Inter-Chip UWB Communication
A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications
A four-level storage 4-Gb DRAM
A 100-mega-access per second matching memory for a data-driven microprocessor
A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical Servers
A 2.4-GHz CMOS receiver for IEEE 802.11 wireless LANs
Error suppressing encode logic of FCDL in a 6-b flash A/D converter
Low phase noise millimeter-wave frequency sources using InP-based HBT MMIC technology
A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS
A 300-MPOS video signal processor with a parallel architecture
An Energy-Efficient Transformer Processor Exploiting Dynamic Weak Relevances in Global Attention
A high slew-rate unity-gain low-voltage buffer with large active/quiescent current ratio
Low-power BiCMOS circuits for high-speed interchip communication
A 20-Msample/s switched-capacitor finite-impulse-response filter using a transposed structure
Introduction to the Special Issue on the 38th European Solid-State Circuits Conference (ESSCIRC)
A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping
3-D Ultrasonic Fingerprint Sensor-on-a-Chip
300-GHz Double-Balanced Up-Converter Using Asymmetric MOS Varactors in 65-nm CMOS
A 110 nA Voltage Regulator System With Dynamic Bandwidth Boosting for RFID Systems
A 5-ns GaAs 16-kb SRAM
An 80-Gb/s 300-GHz-Band Single-Chip CMOS Transceiver
A MOSFET-only continuous-time bandpass filter
An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with <10-Hz RF carrier resolution
Managing subthreshold leakage in charge-based analog circuits with low-V TH transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS)
A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate
An Always-On 3.8 $\mu$ J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS
A Low-Dropout Regulator for SoC With Q-Reduction
A power-efficient wide-range phase-locked loop
Cramming More Weight Data Onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM With 3984-kb/mm 2 Density in 65-nm CMOS
A 10 K-gate 950 MHz CML demonstrator circuit made with a 1- mu m trench-isolated bipolar silicon technology
A Thin Elastic NFC Forum Type 1 Compatible RFID Tag
A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS
A LiDAR-PNN Pipelined Processor With Cylindrical Bin Partitioning and Halo Indexing for 3-D Perception in Outdoor Autonomous Driving Applications
A 0.18-μm Monolithic Li-Ion Battery Charger for Wireless Devices Based on Partial Current Sensing and Adaptive Reference Voltage
A monolithic 2-b delta-sigma A/D converter
Low-Power 16 x 10 Gb/s Bi-Directional Single Chip CMOS Optical Transceivers Operating at ≪ 5 mW/Gb/s/link
Analysis of Metastability in Pipelined ADCs
A quadrature digital synthesizer/mixer architecture using fine/coarse coordinate rotation to achieve 14-b input, 15-b output, and 100-dBc SFDR
A 6-bit 0.81-mW 700-MS/s SAR ADC With Sparkle-Code Correction, Resolution Enhancement, and Background Window Width Calibration
A 10-b 15-MHz CMOS recycling two-step A/D converter
A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology
Cryo-CMOS Circuits and Systems for Quantum Computing Applications
Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine
A Cryo-CMOS PLL for Quantum Computing Applications
A 20-bit 25-kHz delta-sigma A/D converter utilizing a frequency-shaped chopper stabilization scheme
A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM
A Compact, Supply-Voltage Scalable 45-66 GHz Baseband-Combining CMOS Phased-Array Receiver
A Multi-Loop Slew-Rate-Enhanced NMOS LDO Handling 1-A-Load-Current Step With Fast Transient for 5G Applications
Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL
A 70 pJ/Pulse Analog Front-End in 130 nm CMOS for UWB Impulse Radio Receivers
A 1.8 μ W 60 nV √ Hz Capacitively-Coupled Chopper Instrumentation Amplifier in 65 nm CMOS for Wireless Sensor Nodes
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI
Concurrent error detection and fault location in an FFT architecture
A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance
An Integrated DC-DC Converter With Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery
Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier
A noise-shaping coder topology for 15+ bit converters
Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits
A 0.9-V, 150-MHz, 10-mW, 4 mm 2 , 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme
A 4 Mb NAND EEPROM with tight programmed V t distribution
A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With -101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction
A Residue-Current-Locked Hybrid Low-Dropout Regulator Supporting Ultralow Dropout of Sub-50 mV With Fast Settling Time Below 10 ns
A 3-10 fJ/conv-step Error-Shaping Alias-Free Continuous-Time ADC
OC-192 transmitter and receiver in standard 0.18-μm CMOS
Energy-Efficient Flexible RNS-CKKS Processor for FHE-Based Privacy-Preserving Computing
3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules
An In-Band Full-Duplex Radio Receiver With a Passive Vector Modulator Downmixer for Self-Interference Cancellation
Neural networks for high-storage content-addressable memory: VLSI circuit and learning algorithm
A Baseband-Matching-Resistor Noise-Canceling Receiver With a Three-Stage Inverter-Only OpAmp for High In-Band IIP3 and Wide IF Applications
A 12 Gb/s Si bipolar 4:1-multiplexer IC for SDH systems
A reduced clock-swing flip-flop (RCSFF) for 63% power reduction
A low-distortion output stage with improved stability for monolithic power amplifiers
A single-chip tuner for DVB-T
A 3-D IC for Mitigating Energy of Memory Accessing and Data Movement in Accelerator- Based Streaming Architectures
A 370-pJ/b Multichannel BFSK/QPSK Transmitter Using Injection-Locked Fractional-N Synthesizer for Wireless Biotelemetry Devices
A wide dynamic range CMOS image sensor with multiple exposure-time signal outputs and 12-bit column-parallel cyclic A/D converters
An Active Feedback Interference Cancellation Technique for Blocker Filtering in RF Receiver Front-Ends
A 1.5-V 14-bit 100-MS/s self-calibrated DAC
Correction to "A 40 GS/s Time Interleaved ADC Using SiGe BiCMOS Technology"
A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation
A Flicker Noise/IM3 Cancellation Technique for Active Mixer Using Negative Impedance
A 150-V subscriber line interface circuit (SLIC) in a new BiCMOS/DMOS-technology
An experimental 256-Mb DRAM with boosted sense-ground scheme
A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness
Weak inversion charge injection in analog MOS switches
Design of a 128-mb SOI DRAM using the floating body cell (FBC)
A 345 µW Multi-Sensor Biomedical SoC With Bio-Impedance, 3-Channel ECG, Motion Artifact Reduction, and Integrated DSP
Compact multiple-valued multiplexers using negative differential resistance devices
Sub-1-V CMOS proportional-to-absolute temperature references
A Multi-Phase Sub-Harmonic Injection Locking Technique for Bandwidth Extension in Silicon-Based THz Signal Generation
A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS
An 80-MFLOPS (peak) 64-b microprocessor for parallel computer
40-Gb/s 2: 1 multiplexer and 1: 2 demultiplexer in 120-nm standard CMOS
A Time-Domain Wavefront Computing Accelerator With a 32 × 32 Reconfigurable PE Array
"Zeppelin": An SoC for Multichip Architectures
An Event-driven Clockless Level-Crossing ADC With Signal-Dependent Adaptive Resolution
A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP Control
A Compact First-Order ΣΔ Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process
CMOS open-fault detection in the presence of glitches and timing skews
A Multi-Granularity FPGA With Hierarchical Interconnects for Efficient and Flexible Mobile Computing
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion
Capacity limits and matching properties of integrated capacitors
W-Band Direct-Modulation >20-Gb/s Transmit and Receive Building Blocks in 32-nm SOI CMOS
Structure-Reconfigurable Power Amplifier (SR-PA) and 0X/1X Regulating Rectifier for Adaptive Power Control in Wireless Power Transfer System
A CMOS finite impulse response filter with a crossover traveling wave topology for equalization up to 30 Gb/s
New associate editor [Editor]
A 13.8-ENOB Fully Dynamic Third-Order Noise-Shaping SAR ADC in a Single-Amplifier EF-CIFF Structure With Hardware-Reusing kT/C Noise Cancellation
A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS
Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding
An 88.9-dB SNR Fully-Dynamic Noise-Shaping SAR Capacitance-to-Digital Converter
A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator
A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm 2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture
Silicon Photonic Switches Hybrid-Integrated With CMOS Drivers
8-ns CMOS 64 K*4 and 256 K*1 SRAMs
A direct-conversion CMOS transceiver for the 802.11a/b/g WLAN standard utilizing a Cartesian feedback transmitter
A CMOS channel-select filter for a direct-conversion wireless receiver
A 1-GS/s FFT/IFFT processor for UWB applications
A CMOS Ku-Band 4x Subharmonic Mixer
Optical Wireless APD Receiver With High Background-Light Immunity for Increased Communication Distances
A Display Source-Driver IC Featuring Multistage-Cascaded 10-Bit DAC and True-DC-Interpolative Super-OTA Buffer
A Type-II Phase-Tracking Receiver
Introduction to the Special Issue on the 25th Annual IEEE GaAs Integrated Circuits Conference
A CMOS bandgap reference for differential signal processing
1-V 9-bit pipelined switched-opamp ADC
Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM
A 65 nm CMOS 4-Element Sub-34 mW/Element 60 GHz Phased-Array Transceiver
A fourth-order bandpass sigma-delta modulator
An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 µm CMOS
A novel memory cell for multiport RAM on 0.5 μm CMOS Sea-of-Gates
A single-chip image rejecting receiver for the 2.44 GHz band using commercial GaAs-MESFET-technology
A 10-bit 5-Msample/s CMOS two-step flash ADC
Introduction to the Special Section on the 2018 RFIC Symposium
Design for reducing alpha-particle-induced soft errors in ECL logic circuitry
A 3.3-V 21-Gb/s PRBS generator in AlGaAs/GaAs HBT technology
A low-noise amplifier with automatic gain control and anticlipping control in CMOS technology
Frequency mixer with a frequency doubler for integrated circuits
Chopper Stabilization of Analog Multipliers, Variable Gain Amplifiers, and Mixers
Design of wide-band CMOS VCO for multiband wireless LAN applications
A 10-Gb/s CMOS clock and data recovery circuit with a half-rate binary phase/frequency detector
A 24.5-43.5-GHz Ultra-Compact CMOS Receiver Front End With Calibration-Free Instantaneous Full-Band Image Rejection for Multiband 5G Massive MIMO
A Fill-In Technique for Robust IMD Suppression in Chopper Amplifiers
An Eight-Element 136-147 GHz Wafer-Scale Phased-Array Transmitter With 32 dBm Peak EIRP and >16 Gbps 16QAM and 64QAM Operation
A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture
A study of pipeline architectures for high-speed synchronous DRAMs
A 35-mW 3.6-mm2 fully integrated 0.18-μm CMOS GPS radio
Highly Linear RF CMOS Variable Attenuators With Adaptive Body Biasing
Evaluation of delay-time degradation of low-voltage BiCMOS based on a novel analytical delay-time modeling
A pipelined 13-bit 250-ks/s 5-V analog-to-digital converter
Resonant-tunneling diode and HEMT logic circuits with multiple thresholds and multilevel output
An Automatic Loop Gain Enhancement Technique in Magnetoimpedance-Based Magnetometer
Novel design for testability schemes for CMOS ICs
A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm
A Sub-µg Bias-Instability MEMS Oscillating Accelerometer With an Ultra-Low-Noise Read-Out Circuit in CMOS
A Double Pulse Overlapping Laser Diode Driver With Minimum 100-ps Pulse for LiDAR System
Dual Polarization Dynamic Alignment of Integrated Phased Arrays
Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance
SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation
A Single-Chip 125-MHz to 32-GHz Signal Source in 0.18- μ m SiGe BiCMOS
A technology-independent approach to custom analog cell generation
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power
A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses
A 1-GHz charge-packet replicator/subtractor circuit for GaAs CCD signal processing
A bit-stream digital-to-analog converter with 18-b resolution
Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications
A new nonlinear time-domain op-amp macromodel using threshold functions and digitally controlled network elements
CMOS image sensors comprised of floating diffusion driving pixels with buried photodiode
A 2.5-5.75-GHz Ring-Based Injection-Locked Clock Multiplier With Background-Calibrated Reference Frequency Doubler
40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170°C
A comprehensive delay macro modeling for submicrometer CMOS logics
Guest Editorial 2024 Custom Integrated Circuits Conference
50nW Opamp-Less ΔΣ-Modulated Bioimpedance Spectrum Analyzer for Electrochemical Brain Interfacing
A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration
Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging Architecture
A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring
A frequency agile monolithic QPSK modulator with spectral filtering and 75 Ω differential line driver
A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS
An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes
A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner
A Highly Linear Dual-Band Mixed-Mode Polar Power Amplifier in CMOS with An Ultra-Compact Output Network
High-speed, high-reliability circuit design for megabit DRAM
Magnetoelectric Bio-Implants Powered and Programmed by a Single Transmitter for Coordinated Multisite Stimulation
Second-generation RISC floating point with multiply-add fused
A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS
Chip-Scale Molecular Clock
Noise analysis and characterization of a sigma-delta capacitive microaccelerometer
SPICE modeling and quick estimation of MOSFET mismatch based on BSIM3 model and parametric tests
Analysis and Design of Broadband Terahertz Push-Push Frequency Doublers With Second Harmonic Source Tuning
0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking
A Fully Integrated Split-Electrode SSHC Rectifier for Piezoelectric Energy Harvesting
A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition
A monolithic analog video comb filter in 1.2- mu m CMOS
A multiple sampling, single A/D conversion technique for I/Q demodulation in CMOS
Ultra-Sensitive Capacitive Detection Based on SGMOSFET Compatible With Front-End CMOS Process
A Fully Integrated Dual-Mode Highly Linear 2.4 GHz CMOS Power Amplifier for 4G WiMax Applications
A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC
A 16-Element 4-Beam 1 GHz IF 100 MHz Bandwidth Interleaved Bit Stream Digital Beamformer in 40 nm CMOS
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode
A Wideband Receiver for Multi-Gbit/s Communications in 65 nm CMOS
High performance analog VLSI computational circuits
A Wideband Four-Way Doherty Bits-In RF-Out CMOS Transmitter
A High-Gain mm-Wave Amplifier Design: An Analytical Approach to Power Gain Boosting
Broadband Oscillator-Free THz Pulse Generation and Radiation Based on Direct Digital-to-Impulse Architecture
A 10 V Fully-Integrated Switched-Mode Step-up Piezo Drive Stage in 0.13µm CMOS Using Nested-Bootstrapped Switch Cells
An 11-Band 3-10 GHz Receiver in SiGe BiCMOS for Multiband OFDM UWB Communication
3.2-mW Ultra-Low-Power 173-207-GHz Amplifier With 130-nm SiGe HBTs Operating in Saturation
Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces
Monolithic Electronic-Biophotonic System-on-Chip for Label-Free Real-Time Molecular Sensing
A DC-to-1 GHz Tunable RF Delta Sigma ADC Achieving DR = 74 dB and BW = 150 MHz at f 0 = 450 MHz Using 550 mW
A variable precharge voltage sensing
Architecture, design, and test of continuous-time tunable intermediate-frequency bandpass delta-sigma modulators
A Spatial-Temporal Multiresolution CMOS Image Sensor With Adaptive Frame Rates for Tracking the Moving Objects in Region-of-Interest and Suppressing Motion Blur
An NMOS LDO With TM-MOS and Dynamic Clamp Technique Handling Up To Sub-10-μs Short-Period Load Transient
A 4-μW Bandwidth/Power Scalable Delta-Sigma Modulator Based on Swing-Enhanced Floating Inverter Amplifiers
A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS
An interpolating clock synthesizer
A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging
PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits
A 67-mW D-Band FMCW I/Q Radar Receiver With an N-Path Spillover Notch Filter in 28-nm CMOS
A Stackable, 6-Cell, Li-Ion, Battery Management IC for Electric Vehicles With 13, 12-bit ΣΔ ADCs, Cell Balancing, and Direct-Connect Current-Mode Communications
A High-Speed Low-Power Multi-VDD CMOS/SIMOX SRAM With LV-TTL Level Input/Output Pins - Write/Read Assist Techniques for 1-V Operated Memory Cells
Dual-Band, Two-Layer Millimeter-Wave Transceiver for Hybrid MIMO Systems
A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS
A Fully Integrated Ultra-Low Insertion Loss T/R Switch for 802.11b/g/n Application in 90 nm CMOS Process
A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO
Automated bias control (ABC) circuit for high-performance VLSIs
Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines
A 51.2-GOPS scalable video recognition processor for intelligent cruise control based on a linear array of 128 four-way VLIW processing elements
A 900-MHz transceiver chipset for two-way paging applications
A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection
A 200-MHz IF 11-bit fourth-order bandpass ΔΣ ADC in SiGe
Very low-voltage analog signal processing based on quasi-floating gate transistors
An Impedance-Boosted Transformer-First Discrete-Time Analog Front-End Achieving 0.34 NEF and 389-MΩ Input Impedance
A high-performance GaAs pin electronics circuit for automatic test equipment
A 16 MHz CMOS RC Frequency Reference With ±90 ppm Inaccuracy From -45 °C to 85 °C
A Cryo-CMOS Controller With Class-DE Driver and DC Magnetic-Field Tuning for Quantum Computers Based on Color Centers in Diamond
A 100-dB SFDR 80-MSPS 14-Bit 0.35-$ muhbox m$BiCMOS Pipeline ADC
A dual-loop delay-locked loop using multiple voltage-controlled delay lines
A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm
A Logic-Compatible Embedded Flash Memory for Zero-Standby Power System-on-Chips Featuring a Multi-Story High Voltage Switch and a Selective Refresh Scheme
An IR-UWB CMOS Transceiver With Extended Pulse Position Modulation
Low leakage techniques for FPGAs
Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS
A 50-W low distortion GaAs MESFET for digital cellular base stations
A Millimeter-Wave Direct Digital Transmitter Using Multiphase Subharmonic Switching PA
A Miniaturized 3-D-MRI Scanner Featuring an HV-SOI ASIC and Achieving a 10 × 8 × 8 mm 3 Field of View
2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor
Implementation of a fourth-generation 1.8-GHz dual-core SPARC V9 microprocessor
Design Techniques for Fully Integrated Switched-Capacitor DC-DC Converters
Analysis and Design of a 10.4-ENOB 0.92-5.38-μW Event-Driven Level-Crossing ADC With Adaptive Clocking for Time-Sparse Edge Applications
A Linearization Technique for RF Receiver Front-End Using Second-Order-Intermodulation Injection
A Programmable Frequency Multiplier-by-29 Architecture for Millimeter Wave Applications
Guest Editorial Introduction to the Special Section on the 2021 RFIC Symposium
A 6- μ W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology
Reduced complexity two-phase micropipeline latch controller
A GaAs 4-bit adder-accumulator circuit for direct digital synthesis
Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays
Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors
A 1.1 G MAC/s sub-word-parallel digital signal processor for wireless communication applications
TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-Voltage Bitcoin Mining Core
An Efficient Buck/Buck-Boost Reconfigurable LED Driver Employing SIN 2 Reference
A 28-GHz Hybrid Beamforming Transmitter With Spatial Notch Steering Enabling Concurrent Dual Data Streams for 5G MIMO Applications
A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance
A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier
A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency
A 22 nm 15-Core Enterprise Xeon® Processor Family
A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET
A mixed frequency-time approach for distortion analysis of switching filter circuits
A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques
A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL
Integrated FSK demodulator with very high sensitivity
A 1.8-GΩ Input-Impedance 0.15-μV Input-Referred-Ripple Chopper Amplifier With Local Positive Feedback and SAR-Assisted Ripple Reduction
A 32 b 90 nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation From Sub-Threshold to High Performance