yusuke1997/dblp-id-title huggingface dataset:
A Simple Method for Generating Electromagnetic Oscillations
A Novel CMOS Frequency-Mixing Transimpedance Amplifier for Frequency Domain Near Infrared Spectroscopy
An Improved Stability Theorem for Nonlinear Systems on Time Scales With Application to Multi-Agent Systems
A Clockless Temperature-Compensated Nanowatt Analog Front-End for Wake-Up Radios Based on a Band-Pass Envelope Detector
Low-Voltage Low-Power 1.6 GHz Quadrature Signal Generation Through Stacking a Transformer-Based VCO and a Divide-by-Two
RF Front-End Concept and Implementation for Direct Sampling of Multiband Signals
Analysis, Simulation, and Implementation of Dual-Band Filtering Power Divider Based on Terminated Coupled Lines
Zero-Crossing-Time-Difference Model for Stability Analysis of VCO-Based OTAs
Guest Editorial Special Issue on Circuits and Systems for the Internet of Things - From Sensing to Sensemaking
A -8 mV/+15 mV Double Polarity Piezoelectric Transformer-Based Step-Up Oscillator for Energy Harvesting Applications
Digital Background-Calibration Algorithm for "Split ADC" Architecture
A burst-mode word-serial address-event link-III: analysis and test results
Analysis and Design of an Ultrabroadband Stacked Power Amplifier in CMOS Technology
10-ms 18-Band Quasi-ANSI S1.11 1/3-Octave Filter Bank for Digital Hearing Aids
Efficient hardware architectures for eigenvector and signal subspace estimation
All-Digital PLL With Ultra Fast Settling
Envelope Tracked Pulse Gate Modulated GaN HEMT Power Amplifier for Wireless Transmitters
A Pseudo Single-Stage Amplifier With an Adaptively Varied Medium Impedance Node for Ultra-High Slew Rate and Wide-Range Capacitive-Load Drivability
A Simple Subthreshold CMOS Voltage Reference Circuit With Channel- Length Modulation Compensation
A High-Gain Power-Matching Technique for Efficient Radio-Frequency Power Harvest of Passive Wireless Microsystems
Square-Root Generalized Eigenvalue Decomposition Processor for Leakage-Based Multi-User MIMO Precoding With Multi-Antenna Users
Efficient Soft Error-Tolerant Adaptive Equalizers
Adaptive Consensus for Multiple Nonidentical Matching Nonlinear Systems: An Edge-Based Framework
Projectional Observers of Nonlinear Systems With Full-State Constraints
Design and Multiplierless Realization of Digital Synthesis Filters for Hybrid-Filter-Bank A/D Converters
Unified Frequency-Domain Analysis of Switched-Series- RC Passive Mixers and Samplers
A rail-to-rail amplifier input stage with ±0.35%g m fluctuation
Almost Output Regulation for Switched Positive Systems With Different Coordinates Transformations and its Application to a Positive Circuit Model
Design of an Area-Efficient One-Dimensional Median Filter
A Reconfigurable SIMT Processor for Mobile Ray Tracing With Contention Reduction in Shared Memory
Synthesis of Low-Pass Real-to-Real Impedance Transformer With Coupled-Inductors
Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals
Efficient Generation of 1/f beta Noise Using Signal Modeling Techniques
Design and Analysis of a Class-D Stage With Harmonic Suppression
Robust Global Exponential Stability for Interval Reaction-Diffusion Hopfield Neural Networks With Distributed Delays
A Heterogeneous 16-Bit DAC Using a Replica Compensation
Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters
Efficient Low-Latency Implementation of CORDIC-Based Sorted QR Decomposition for Multi-Gbps MIMO Systems
Wandering Spurs in MASH 1-1 Delta-Sigma Modulators
Bit-Stream Adders and Multipliers for Tri-Level Sigma-Delta Modulators
Tile Adaptation for Workload Balancing of 3D-HEVC Encoder in Homogeneous Multicore Systems
Novel Process and Temperature-Stable, IDD Sensor for the BIST Design of Embedded Digital, Analog, and Mixed-Signal Circuits
An analytical charge-based compact delay model for submicrometer CMOS inverters
A Harmonic Rejection Strategy for 25% Duty-Cycle IQ-Mixers Using Digital-to-Time Converters
A Compact Adder and Reprogrammable Logic Gate Using Micro-Electromechanical Resonators With Partial Electrodes
Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures
Maximization of Crossbar Array Memory Using Fundamental Memristor Theory
Digital-to-Frequency Converters With a DTC: Theoretical Analysis of the Output SFDR
Multiplierless, Folded 9/7- 5/3 Wavelet VLSI Architecture
A Propagation Analysis of Residual Distributions in Pipeline ADCs
Sparsity Constrained Recursive Generalized Maximum Correntropy Criterion With Variable Center Algorithm
An HV-CMOS Integrated Circuit for Neural Stimulation in Prosthetic Applications
Switched-Capacitor Track-and-Hold Amplifiers With Low Sensitivity to Op-Amp Imperfections
Heterogeneous Strategy Particle Swarm Optimization
Data-Driven Enhanced Nonlinear Gaussian Filter
Performance of Coupled-Oscillator Arrays With Angle-Modulated Injection Signals
Passivity-Based Integral Sliding Mode Control and $\varepsilon$ - Bound Estimation for Uncertain Singularly Perturbed Systems With Disturbances
Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs
Passive Rational Interpolation-Based Reduction via Carathéodory Extension for General Systems
An On-Chip CMOS Temperature Sensor Using Self-Discharging P-N Diode in a Δ-Σ Loop
Design of 2-D Wideband Circularly Symmetric FIR Filters by Multiplierless High-Order Transformation
Linearity Enhanced Harmonic-Modulated Impedance Inverter Doherty-Like Power Amplifier
Collision-Free Formation Control for Multi-Agent Systems With Dynamic Mapping
On Existence and Stability of Equilibria of Linear Time-Invariant Systems With Constant Power Loads
A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC With Dual Rising-Edge Fractional-Phase Detector
Synchronizer-Free Digital Link Controller
Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation
Fast Time-Recursive Block Correlators for Pseudorandom Sequences
An Ultra-Low-Power Low-Voltage WuTx With Built-In Analog Sensing for Self-Powered WSN
A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting
Communication Channel Analysis and Real Time Compressed Sensing for High Density Neural Recording Devices
Prefilter-Based Reconfigurable Reconstructor for Time-Interleaved ADCs With Missing Samples
Structural Controllability of Temporally Switching Networks
Steady State Computation and Noise Analysis of Analog Mixed Signal Circuits
New results for exponential stability of delayed cellular neural networks
Feedback Loop Analysis and Optimized Compensation Slope of the Current-Mode Buck DC-DC Converter in DCM
Steady-State Performance Analysis of Nonlinear Spline Adaptive Filter Under Maximum Correntropy Criterion
Revealing Impacts of Cyber Attacks on Power Grids Vulnerability to Cascading Failures
Editorial TCAS-I State and Plans for the Future
Hybrid CMOS Rectifier Based on Synergistic RF-Piezoelectric Energy Scavenging
All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition
Analysis and Design of a 0.6- to 10.5-GHz LNTA for Wideband Receivers
Low-Voltage Linearly Tunable CMOS Transconductor With Common-Mode Feedforward
True Random Number Generation Via Sampling From Flat Band-Limited Gaussian Processes
An Improved Broadband High Linearity SiGe HBT Differential Amplifier
Hybrid Filterbank ADCs With Blind Filterbank Estimation
A Multibit Delta-Sigma Modulator With Double Noise-Shaped Segmentation
The wavelet transform-domain LMS adaptive filter with partial subband-coefficient updating
A Fully Integrated Galvanically Isolated DC-DC Converter With Data Communication
Reconfigurable Digital Spiking Neuron and Its Pulse-Coupled Network: Basic Characteristics and Potential Applications
The Low-Frequency Distortion in D-Class Amplifiers
Logarithmic AD Converter With Selectable Transfer Characteristic
A recurrent neural network for nonlinear convex optimization subject to nonlinear inequality constraints
The Unpredictability Analysis of Boolean Chaos
Rigorous Analysis of Chua's Circuit With a Smooth Nonlinearity
Dynamic Output-Feedback Control for Nonlinear Time-Delay Systems and Applications to Chemical Reactor Systems
Passivity Analysis of Neural Networks With Time Delay
Vector Autoregressive Model-Order Selection From Finite Samples Using Kullback's Symmetric Divergence
A Design Methodology for MOS Current-Mode Logic Frequency Dividers
Equivalent Complex Baseband Model for Digital Transmitters Based on 1-bit Quadrature Pulse Encoding
Nonlinear H∞ Filtering Based on Tensor Product Model Transformation
A Study of Operating Condition and Design Methods to Achieve the Upper Limit of Power Gain in Amplifiers at Near-f max Frequencies
Discrete-Time Positive Edge-Consensus for Undirected and Directed Nodal Networks
A 100 MHz-to-1 GHz Fast-Lock Synchronous Clock Generator With DCC for Mobile Applications
A Wideband Beamforming Lowpass Filter for 60 GHz Phased-Array Receivers
Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder
Improvement of Stability and Power Factor in PCM Controlled Boost PFC Converter With Hybrid Dynamic Compensation
An Incremental Variable Step-Size LMS Algorithm for Adaptive Networks
Optimization of Power Conversion Efficiency in Threshold Self-Compensated UHF Rectifiers With Charge Conservation Principle
A Scalable Bandwidth Mismatch Calibration Technique for Time-Interleaved ADCs
A 7-GHz CMOS Bidirectional Variable Gain Amplifier With Low Gain and Phase Imbalances
Steady-State Simulation Methods of Closed-Loop Power Converter Systems - A Systematic Solution Procedure
On Analog Networks and Mixed-Domain Spatio-Temporal Frequency Response
A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS
Optimal Use of Some Classical Approximations in Filter Design
Power Packet Router With Power and Signal Switches for a Single Power Packet
A Nearly All-Digital Frequency Mixer Based on Nonlinear Digital-to-Analog Conversion and Intermodulation Cancellation
Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation
Theoretical Analysis of Novel Multi-Order LC Oscillators
Improved Bounds on the L(2, 1)-Number of Direct and Strong Products of Graphs
Designing Hyperchaotic Systems With Any Desired Number of Positive Lyapunov Exponents via A Simple Model
A Novel Application of FM-ADC Toward the Self-Calibration of Phase-Locked Loops
A MOS Parametric Integrator With Improved Linearity for SC ΣΔ Modulators
Efficient analysis of slow-varying oscillator dynamics
Well-behaved global on-chip interconnect
Blind channel estimation via combining autocorrelation and blind phase estimation
A Data-Pattern-Tolerant Adaptive Equalizer Using the Spectrum Balancing Method
Noise-Shaped Residue-Discharging Delta-Sigma ADCs With Time-Modulated Pulse Feedback
High-Throughput VLSI Architecture for FFT Computation
Quantization Noise Suppression in Digitally Segmented Amplifiers
WLS Design of Variable Fractional-Delay FIR Filters Using Coefficient Relationship
Analog VLSI focal-plane array with dynamic connections for the estimation of piecewise-smooth optical flow
Complex Network Analysis of Wire-Mesh Sensor Measurements for Characterizing Vertical Gas-Liquid Two-Phase Flows
High Frame-Rate VGA CMOS Image Sensor Using Non-Memory Capacitor Two-Step Single-Slope ADCs
High-Gain Wide-Bandwidth Capacitor-Less Low-Dropout Regulator (LDO) for Mobile Applications Utilizing Frequency Response of Multiple Feedback Loops
An L-Band Low Phase Noise Evanescent-Mode Cavity-Based Frequency Synthesizer
Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory Architectures
A Unified Approach to the Design of Interpolated and Frequency-Response-Masking FIR Filters
Adaptive Robust Stabilization of Output Feedback Systems With Application to Chua's Circuit
Generating Multi-Scroll Chua's Attractors via Simplified Piecewise-Linear Chua's Diode
Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs
A Novel Low Gate-Count Pipeline Topology With Multiplexer-Flip-Flops for Serial Link
Robust Stabilization in LMI Regions for Constrained Input Systems
A Radius Adaptive K-Best Decoder With Early Termination: Algorithm and VLSI Architecture
An Energy Efficient Level Shifter Capable of Logic Conversion From Sub-15 mV to 1.2 V
Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation
A General Theory of Phase Noise in Transconductor-Based Harmonic Oscillators
A Time-Domain Perspective of the Signal Transfer Function of a Continuous-Time ΔΣ Modulator
Design of a Ku-band Low-Phase-Noise VCO Using the Dual LC Tanks
An Implementation of the L-Estimate Distributions for Analysis of Signals in Heavy-Tailed Noise
Simple approach to approximation and dynamical realization of pseudodifferential time operators such as fractional ones
A Low-Cost Resonance Mitigation Technique for Multidrop Memory Interfaces
Prediction of Subharmonic Oscillation in Switching Converters Under Different Control Strategies
Distortion Contribution Analysis With the Best Linear Approximation
Guest Editorial Special Section on the 2013 IEEE International Symposium on Circuits and Systems (ISCAS 2013)
Design procedure of class-E amplifier for off-nominal operation at 50% duty ratio
Design and Qualitative Robustness Analysis of an DOBC Approach for DC-DC Buck Converters With Unmatched Circuit Parameter Perturbations
A Few-Step and Low-Cost Memristor Logic Based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications
Design of a Practical Memcapacitor Emulator Without Grounded Restriction
Global Asymptotic Stability and Robust Stability of a Class of Cohen-Grossberg Neural Networks With Mixed Delays
A Discrete-Time Technique for the Steady-State Analysis of Nonlinear Class-E Amplifiers
Stability Analysis and Hardware Resource Optimization in Channel Emulator Design
A 2nd-Order Noise-Shaping SAR ADC With Lossless Dynamic Amplifier Assisted Integrator
Determination of Wavelet Ridges of Nonstationary Signals by Singular Value Decomposition
Half-Matrix Normal Basis Multiplier Over GF(p m )
Stochastic Analysis of Deep-Submicrometer CMOS Process for Reliable Circuits Designs
Reconfigurable Nonuniform Transmultiplexers Using Uniform Modulated Filter Banks
Computational Complexity Analysis of Determinant Decision Diagram
Security of Public-Key Cryptosystems Based on Chebyshev Polynomials Over $\mathbb Z/p^{k}\mathbb Z$
Consensus Analysis Based on Impulsive Systems in Multiagent Networks
FET-R-C Circuits: A Unified Treatment - Part I: Signal Transfer Characteristics of a Single-Path
New positive realness conditions for uncertain discrete descriptor systems: analysis and synthesis
A Fully Integrated High-Power-Supply-Rejection Linear Regulator With an Output-Supplied Voltage Reference
A 35-dBm OIP3 CMOS Constant Bandwidth PGA With Extended Input Range and Improved Common-Mode Rejection
Implementing Wavelets in Continuous-Time Analog Circuits With Dynamic Range Optimization
Adaptive Modified Versoria Zero Attraction Least Mean Square Algorithms
A Boost Type Resonant Forward Converter With Topology Combination
A 5.4/2.7/1.62-Gb/s Receiver for DisplayPort Version 1.2 With Multi-Rate Operation Scheme
A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS
Design of Near-Allpass Strictly Stable Minimal-Phase Real-Valued Rational IIR Filters
A Split-Path Sensing Circuit for Spin Torque Transfer MRAM
Parallel Plate Cavity Mode Suppression by Miniaturized 2.5-D Electromagnetic Bandgap Structure for Low Frequency Microwave Circuit
On Some Input-Output Dynamic Properties of Complex Networks
Noise Performance of a Regulated Cascode Transimpedance Amplifier for Radiation Detectors
Pseudobasin of attraction for combinatorial dynamical systems: theory and its application to combinatorial optimization
Steady-State Mean-Square Performance Analysis of the Affine Projection Sign Algorithm
Consensus of Multi-Agents With Event-Based Nonlinear Coupling Over Time-Varying Digraphs
Locking Range Maximization in Injection-Locked Class-E Oscillator - A Case Study for Optimizing Synchronizability
Aliasing-Compensated Polar PWM Transmitter
A (21150, 19050) GC-LDPC Decoder for NAND Flash Applications
A -24 dB in-Band Noise-Immunity Mutual Capacitance Readout System for Variable Refresh Rate of Active-Matrix OLED Display
A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme
Analysis of Power Consumption and Linearity in Capacitive Digital-to-Analog Converters Used in Successive Approximation ADCs
A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for ΔΣ PLLs
Energy-Efficient Processor for Blind Signal Classification in Cognitive Radio Networks
New Globally Asymptotic Stability Criteria for Delayed Cellular Neural Networks
Adaptive nonlinear PCA algorithms for blind source separation without prewhitening
A Robust ICA-Based Adaptive Filter Algorithm for System Identification
A Pulse-Modulated Polar Transmitter Using Direct Digital Synthesis for 5G NR Mobile Applications
A Low Power High Precision Trim-Less Envelope Detector for Fail-Safe Circuit in LVDS Receiver
The IEEE Standard 1459, the CPC Power Theory, and Geometric Algebra in Circuits With Nonsinusoidal Sources and Linear Loads
One-ports composed of power-law resistors
Farrow-Structure-Based Reconfigurable Bandpass Linear-Phase FIR Filters for Integer Sampling Rate Conversion
Performance Enhancement of Switched-Current Technique Using Subthreshold MOS Operation
Efficient Systolic Implementation of DFT Using a Low-Complexity Convolution-Like Formulation
A Wide Operating Range LC Quadrature Phase VCO With Seamless Tunability
An Efficient Method of Power Spectral Density Estimation for On-Chip IR-UWB Transmitter Self-Calibration
A low-Voltage 10-bit CMOS DAC in 0.01-mm 2 die area
System-On-Mud: Ultra-Low Power Oceanic Sensing Platform Powered by Small-Scale Benthic Microbial Fuel Cells
Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability
Correction to "Noise Figure Optimization of Inductively-Degenerated CMOS LNA's With Integrated Gate Inductors"
New Majority Gate-Based Parallel BCD Adder Designs for Quantum-Dot Cellular Automata
Throughput/Area-efficient ECC Processor Using Montgomery Point Multiplication on FPGA
A High Performance InGaZnO Thin-Film Transistors Integrated Amplifier Circuit for Capacitance Sensing
An Efficient Radix-4 Scalable Architecture for Montgomery Modular Multiplication
A Novel Architecture to Eliminate Bottlenecks in a Parallel Tiled QRD Algorithm for Future MIMO Systems
A Slew Rate Enhanced 2 x VDD I/O Buffer With Precharge Timing Technique
Realization of Extremely High and Low Impedance Transforming Ratios Using Cross-Shaped Impedance Transformer
Effect of loop delay on phase margin of first-order and second-order control loops
A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT
A CMOS Hard-Decision Analog Convolutional Decoder Employing the MFDA for Low-Power Applications
Resistive Computing: Memristors-Enabled Signal Multiplication
Improving Robustness of Interdependent Networks by Reducing Key Unbalanced Dependency Links
Projected Kernel Recursive Maximum Correntropy
Multiplexer and Memory-Efficient Circuits for Parallel Bit Reversal
Hardware Reduction of MASH Delta-Sigma Modulator Based on Partially Folded Architecture
Design of a 5.2-GHz CMOS Power Amplifier Using TF-Based 2-Stage Dual-Radial Power Splitting/Combining Architecture
A Robust Multiplicative Watermark Detector for Color Images in Sparse Domain
Development of Integrated Broad-Band CMOS Low-Noise Amplifiers
Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations
Roundoff Noise Minimization in State-Space Discrete-Time Systems Using Joint Optimization of High-Order Error Feedback and Realization
A 200-Mbps 0.02-nJ/b Dual-Mode Inductive Coupling Transceiver for cm-Range Multimedia Application
A sparse Bayesian method for determination of flexible design matrix for fMRI data analysis
Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing
An Improved Gradient Descent Bit-Flipping Decoder for LDPC Codes
Equi-Noise: A Statistical Model That Combines Embedded Memory Failures and Channel Noise
Nash games for multiparameter singularly perturbed systems with uncertain small singular perturbation parameters
Locking Range of Frequency Dividers With Dual-Resonance Tank
On exact Kalman filtering of polynomial systems
Rapid Balise Telegram Decoder With Modified LFSR Architecture for Train Protection Systems
Analysis of the QAC IR-UWB Receiver for Low Energy, Low Data-Rate Communication
Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM
A High-Voltage Generation Charge-Pump IC Using Input Voltage Modulated Regulation for Neural Implant Devices
Fractional-Order Memristor-Based Chua's Circuit
Discrete Chaos-I: Theory
A 12-GHz Calibration-Free All-Digital PLL for FMCW Signal Generation With 78 MHz/μs Chirp Slope and High Chirp Linearity
A 65-nm CMOS DAC Based on a Differentiating Arbitrary Waveform Generator Architecture for 5G Handset Transmitter
Hybrid Description and the Spectrum of Linear Multiports
Global asymptotic and robust stability of recurrent neural networks with time delays
A 14-Bit 500-MS/s Time-Interleaved ADC With Autocorrelation-Based Time Skew Calibration
Piecewise-exponential approximation for fast time-domain simulation of 2-D cellular neural networks
Flip-Flops for Accurate Multiphase Clocking: Transmission Gate Versus Current Mode Logic
Generalized Analysis of Random Common-Mode Rejection Performance of CMOS Current Feedback Instrumentation Amplifiers
Efficient Multibit Quantization in Continuous-Time Sigma Delta Modulators
Reset-Free Memoryless Delta-Sigma Analog-to-Digital Conversion
A 17 mW 3-to-5 GHz Duty-Cycled Vital Sign Detection Radar Transceiver With Frequency Hopping and Time-Domain Oversampling
A Systematic Design Flow for Optimal Capacitance Assignment in Switched-Capacitor Biquads
An Ultra Low-Power Dual-Band IR-UWB Transmitter in 130-nm CMOS
A 115× Conversion-Ratio Thermoelectric Energy-Harvesting Battery Charger for the Internet of Things
A Simple Model of Double-Loop Hysteresis Behavior in Memristive Elements
Transformer-Based Input Integrated Matching in Cascode Amplifiers: Analytical Proofs
3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model
Clock Synchronization Errors in Circuits: Models, Stability and Fault Detection
Digital Calibration of Amplifier Finite DC Gain and Gain Bandwidth in MASH ΣΔ Modulators
Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells
Faster, Stabler, and Simpler - A Recursive-Least-Squares Algorithm Exploiting the Frisch-Waugh-Lovell Theorem
The Doubler of Electricity Used as Battery Charger
On Turing Instability in Nonhomogeneous Reaction-Diffusion CNN's
A Low-Voltage SRAM Sense Amplifier With Offset Cancelling Using Digitized Multiple Body Biasing
Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths
Log-domain filtering by simulating the topology of passive prototypes
Low-Energy and Fast Spiking Neural Network For Context-Dependent Learning on FPGA
Cascading Failure Tolerance of Modular Small-World Networks
Design of a High Temperature 2.37 GHz Voltage-Controlled Oscillator With GaN-on-SiC HEMTs
Hardware-Compliant Compressive Image Sensor Architecture Based on Random Modulations and Permutations for Embedded Inference
Behavioral Analysis and Optimization of CMOS CML Dividers for Millimeter-Wave Applications
Clock- and Data-Recovery Circuit With Independently Controlled Eye-Tracking Loop for High-Speed Graphic DRAMs
A Highly Power-Efficient Single-Inductor Bipolar-Output DC-DC Converter Using Hysteretic Skipping Control for OLED-on-Silicon Microdisplays
Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation
A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS