yusuke1997/dblp-id-title huggingface dataset:
Key lengths revisited: GPU-based brute force cryptanalysis of DES, 3DES, and PRESENT
Enhanced fault tolerant routing algorithms using a concept of "balanced ring"
An operating system extension for a multiprocessor
Neural network simulation of a dielectric ring resonator antenna
SSD internal cache management policies: A survey
Timimg model for SDCFL digital circuits
Deep neural networks compiler for a trace-based accelerator
FPGA/DSP-based implementation of a high-performance multi-channel counter
A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs
The communication processor of TUMULT-64
A hybrid controller for safe and efficient longitudinal collision avoidance control
Bit-accurate energy estimation for Networks-on-Chip
An interactive environment for the model-based design of analog circuits
Real-Time scheduling and analysis of parallel tasks on heterogeneous multi-cores
Automatic verification of distributed logic specifications
Préforme/aGAPE: a synergy between symbolic cell design and assembly
CoMIC: Complementary Memristor based in-memory computing in 3D architecture
An energy-efficient encryption mechanism for NVM-based main memory in mobile systems
Modelling the hardware cost of full register bypassing in a multiple instruction issue processor
The software development environment at Rijkswaterstaat
Avoidance of deadlock in loop structures - a two process solution
Minimizing energy by thermal-aware task assignment and speed scaling in heterogeneous MPSoC systems
Hamun: An approximate computing method to prolong the lifespan of ReRAM-based accelerators
Deriving structured parallel implementations for numerical methods
Designing computer architectures with SADAN
BEPHAP: A Blockchain-based Efficient Privacy-Preserving Handover Authentication Protocol with key agreement for Internet of Vehicles
On the derivation of a correct deadlock free communication kernel for loop connected message passing architecture from its user's specification
A microprogram meta-disassembler
Verifying cooperative software: A SMT-based bounded model checking approach for deterministic scheduler
JORA: Blockchain-based efficient joint computing offloading and resource allocation for edge video streaming systems
ComboFTL: Improving performance and lifespan of MLC flash memory using SLC flash buffer
System performance modeling with functional schemes and VHDL
Migration-aware slot-based memory request scheduler to guarantee QoS in DRAM-PCM hybrid memories
Processor control part synthesis using effective partitioning algorithms
An interworking mechanism between LAN & WAN and implementation method
A frame-based approach to conformance testing
Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement
Fine-grained parallelism framework with predictable work-stealing for real-time multiprocessor systems
In-vehicle monitoring and management for military vehicles' integrated vetronics architectures
Compiling a vector and array processing language for an associative processor
Modeling and simulation of open source development using an agile practice
Performance of tightly-coupled systems with shared cache
Multi-teacher knowledge distillation for compressed video action recognition based on deep learning
Cold start latency mitigation mechanisms in serverless computing: Taxonomy, review, and future directions
Documenting the process of conformance testing
Run-time generation of partial FPGA configurations
Register bypassing in an asynchronous superscalar processor
Stabilizing ring clustering
A low-delay AVB flow scheduling method occupying the guard band in Time-Sensitive Networking
Exploring the Processing-in-Memory design space
Mutation testing of unsupervised learning systems
S-CNN-ESystem: An end-to-end embedded CNN inference system with low hardware cost and hardware-software time-balancing
VenusAI: An artificial intelligence platform for scientific discovery on supercomputers
Analyzing the memory ordering models of the Apple M1
Special issue on network-based many-core embedded systems
FPGA-assisted Design Space Exploration of Parameterized AI Accelerators: A Quickloop Approach
Fuzzy pattern tree for edge malware detection and categorization in IoT
Multiple fault diagnosis for interconnection networks for distributed systems
Specification of a communication virtual processor for parallel processing systems
Design of a custom dram storage unit coupled to i486(tm)
Interprocess communication with multicast support in DMINIX operating system
An effective and verifiable secure aggregation scheme with privacy-preserving for federated learning
Task level specification and communication
Design flows and system architectures for adaptive computing on reconfigurable platforms
CLFLDP: Communication-efficient layer clipping federated learning with local differential privacy
Designing secure blockchain-based authentication and key management mechanism for Internet of Drones applications
A real-time embedded architecture for SIFT
Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network
Reactive programming in Ada 2012 with RxAda
Run-time analysis of time-critical systems
A behavioral approach to testability analysis for neural networks
Scheduling imprecise computations to minimize total error
Comments on an identity-based signature scheme for VANETs
Accelerating tensor multiplication by exploring hybrid product with hardware and software co-design
DPCM studies using edge prediction and adaptive quantisation laws for the transmission of still pictures over the ISDN
FreqCounter: Efficient Cacheability of Encryption and Integrity Tree Counters in Secure Processors
High-level synthesis
Evaluating the impact of microservice-centric computations in internet of vehicles
Specification and design of concurrent control units
Comparing timed-division multiplexing and best-effort networks-on-chip
ThreadAbs: A template to build verified thread-local interfaces with software scheduler abstractions
Design principles of the ATHENA software maintainability toll
ICAS: Two-factor identity-concealed authentication scheme for remote-servers
A conflict-free CAN-to-TSN scheduler for CAN-TSN gateway
Embedding a complete binary tree into the supercube
Embedded software verification in hardware-software codesign
IMISSED: Interactive microprocessor instruction set simulation environment with graphical display
Increasing the efficiency and feasibility of configurable computing units
Navigational assistance for disabled wheelchair-users
Parallel parsing in a multiprocessor environment
Simultaneous decompositions of sequential machines
PRO: A periodical reset optimized page migration scheme for hybrid memory system
Online energy-efficient scheduling of DAG tasks on heterogeneous embedded platforms
Access region cache with register guided memory reference partitioning
Fast modular exponentiation of large numbers with large exponents
An Efficient Certificateless Ring Signcryption Scheme With Conditional Privacy-Preserving in VANETs
A genetic algorithm based energy efficient group paging approach for IoT over 5G
An authentication and signature scheme for UAV-assisted vehicular ad hoc network providing anonymity
MVM: A GaAs microprocessor for critical real-time applications
High-frequency pulse width modulation implementation using FPGA and CPLD ICs
A robust stack folding approach for Java processors: an operand extraction-based algorithm
Extending semantics of relational operators for vague queries
Exploring the performance impact of stripe size on network attached storage systems
Achieving multipoint-to-multipoint fairness with RCNWA
Integrated design tools for very large scale cellular architectures
A technique to transform programs into circuits
Battery-aging-aware run-time slack management for power-consuming real-time systems
A survey On hardware accelerators and optimization techniques for RNNs
Analysis of network protocol performance in the context of multi-workstation parallel distributed applications
Design space exploration of thermal-aware many-core systems
HP-FLEXAR: A reconfigurable multi-unit heterogeneous topology architecture for time critical applications
Implementation issues of image texture analysis and segmentation
Partitioning real-time workloads on multi-core virtual machines
TSV: A novel energy efficient Memory Integrity Verification scheme for embedded systems
TP2SF: A Trustworthy Privacy-Preserving Secured Framework for sustainable smart cities by leveraging blockchain and machine learning
Performance of OPS5 matching on CUPID
The transition from network operating systems to distributed global operating systems: Do we stretch too much the real-time requirements?
A multiprocessor bus system with cyclic data exchange for the field of control and signal processing
An object oriented approach to data persistence
Hardlock: Real-time multicore locking
An environment for developing concurrent software for transputer-based image processing
A software generator for multi-transputer-based real-time applications
Impact of priority assignment on schedule-based attacks in real-time embedded systems
A university framework for correct by construction IC design
CUTE: A scalable CPU-centric and Ultra-utilized Tensor Engine for convolutions
SOFIA: An automated framework for early soft error assessment, identification, and mitigation
The implementation of a software engineering database using desk-size computing resources
A secure and efficient authentication and data sharing scheme for Internet of Things based on blockchain
Database support for the PROTOS-L system
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators
Contrasting instruction-fetch time and instruction-decode time branch prediction mechanisms: Achieving synergy through their cooperative operation
Architecture and C++-programming environment of a highly parallel image signal processor
Formal approach to agent-based dynamic reconfiguration in Networks-On-Chip
An O-O logical machine monitor supporting disk block migration
A library for developing real-time and embedded applications in C
Language and runtime support for distributed object groups
A comprehensive systematic review of integration of time sensitive networking and 5G communication
DELTA-T: A user-transparent software-monitoring tool for multi-transputer systems
Hybrid evolutionary motion planning using follow boundary repair for mobile robots
A mechanism for reducing the cost of branches in RISC architectures
Flexibly expressive and revocable multi-authority KP-ABE scheme from RLWE for Internet of Medical Things
A pairing-free certificateless searchable public key encryption scheme for IoMT
Pessimism in multicore global schedulability analysis
CoDBT: A multi-source dynamic binary translator using hardware-software collaborative techniques
Optical transpose k-ary n-cube networks
Dynamic feature selection for hardware prediction
Parallel K-set mutual range-join in hypercubes
Qualitative trust modeling in SOA
On-line energy-efficient real-time task scheduling for a heterogeneous dual-core system-on-a-chip
DETON: DEfeating hardware Trojan horses in microprocessors through software ObfuscatioN
The design and implementation of VOOM: a parallel virtual Object Oriented machine
k-Nearest neighbor query processing algorithm for cloaking regions towards user privacy protection in location-based services
Animation prototyping of formal specifications of real-time systems
Bandwidth of a reconfigurable multiple-group multiprocessor system
Faces detection method based on skin color modeling
Clustering and reassignment-based mapping strategy for message-passing architectures
Exploitation of parallelism to nested loops with dependence cycles
Structure and performances of a campus-wide IBM token ring multi-network
A comprehensive study of energy efficiency and performance of flash-based SSD
A fault-tolerant systolic data flow machine
DVFS-based energy-aware scheduling of imprecise mixed-criticality real-time tasks
Efficient and self-recoverable privacy-preserving k-NN classification system with robustness to network delay
A scalable design for VLSI dictionary machines
Introducing the new paradigm of Social Dispersed Computing: Applications, Technologies and Challenges
Cooperative task assignment in spatial crowdsourcing via multi-agent deep reinforcement learning
Dependable design technique for system-on-chip
MADDPG-based task offloading and resource pricing in edge collaboration environment
Fast and compact sequential circuits for the FPGA-based reconfigurable systems
An efficient on-chip deterministic test pattern generation scheme
HLL enhancement for stack based processors
Multi-factor single-registration authentication and key exchange protocol for IIoT
Scheduling of precedence-constrained parallel program tasks on multiprocessors
Multiple stuck-at faults detection in CMOS combinational gates
Implementation details of ALBA in a transputer machine
Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques
A tool for syntax directed software design
A Petri Net based compiler for the prototyping language RELOS
Declarative programming of the embedded control systems based on OR-ed dataflow operational principle
Self test for the Intel 8085
Experimental evaluation of Mad Postman bidimensional routing networks
Development of an autonomous heterogeneous distributed database system: DHIM
PSpSys: A time-predictable mixed-criticality system architecture based on ARM TrustZone
Realization of a fuzzy Boolean neural network classifier
Measures for mobile users: an architecture
Advances in object-oriented design
A fault-tolerant server on MACH
Adaptive window working set replacement policies
Storage as a service in Fog computing : A systematic review
Application specific conversation schemes for ADA programs
Memory management in LOGFLOW
An efficient model-based methodology for developing device-independent mobile applications
Self-secured devices: High performance and secure I/O access in TrustZone-based systems
An efficient diversity-driven selective forwarding approach for replicated data queries in wireless sensor networks
Integrated write buffer management for solid state drives
Optimum: Runtime optimization for multiple mixed model deployment deep learning inference
Parallel algorithm for table division in relational databases
TC-SEPM: Characterizing soft error resilience of CNNs on Tensor Cores from program and microarchitecture perspectives
A Scalable Virtual memory system based on decentralization for many-cores
A comprehensive survey of hardware-based security techniques from an architectural perspective
Combining admission tests for heuristic partitioning of real-time tasks on ARM big.LITTLE multi-processor architectures
Logic synthesis in the design of the VLSI-/370 microprocessor
Letter from the short notes editors, Euromicro '92
CLBM: Controlled load-balancing mechanism for congestion management in silicon interposer NoC architecture
Online scheduling algorithms for unbiased distributed learning over wireless edge networks
A gene-inspired metaheuristic for scheduling workflow tasks in mobile edge computing-supported cyber-physical systems
Performance analysis of multistage interconnection networks with a new high-level net model
Locality-aware cache random replacement policies
Quantitative logic-based framework for agile methodologies
Data streaming and traffic gathering in mesh-based NoC for deep neural network acceleration
Integrating an on-chip MMU into a highly pipelined architecture
Dispatching simultaneous instructions
ENOrMOUS: ENergy Optimization for MObile plateform using User needS
Implementing Prolog on a DAP/Multi-transputer computer
An efficient conditional privacy-preserving authentication scheme with scalable revocation for VANETs
Graphics fundamentals for a PCB - CAD PC system
Distributed memory management
FPGA Implementation Issues of a Flexible Synchronizer Suitable for NC-OFDM-Based Cognitive Radios
Special issue on design of algorithms and architectures for signal and image processing
Fast reconfigurable systolic hardware for modular multiplication and exponentiation
Simulation of hardware and multitasking for the parallel programming language ParMod
Federated scheduling for Typed DAG tasks scheduling analysis on heterogeneous multi-cores
Dynamic and adaptive SPM management for a multi-task environment
Efficient parity placement schemes for tolerating up to two disk failures in disk arrays
Verifying parallel dataflow transformations with model checking and its application to FPGAs
Parallel neural network simulation using sparse matrix techniques
Supporting user mobility in the Distributed Logical Machine System
Execution cost interval refinement in static software analysis
A storage computing architecture with multiple NDP devices for accelerating compaction performance in LSM-tree based KV stores
A flexible architecture for H.263 video coding
A Text-to-Multivoice converter for Spanish: Real time operation analysis
High-level synthesis using hierarchical conditional dependency graphs in the CODESIS system
A case study in improving programming productivity on transputer networks
Realization of multiprocessing on a RISC-like architecture
A five step method for metric-based software evaluation - effective software metrication with respect to quality standards
A local external coupling matrix solution and dynamic processing in medical cyber-physical cloud systems
Real-time UNIX operating system: RX-UX 832
Enhancing intermodel transformations in a distributed object-oriented database system
Are task mappings with the highest frequency of servers so good? A case study on Heterogeneous Earliest Finish Time (HEFT) algorithm
An experimental multiprocessor system for distributed parallel computations
Modeling and evaluation of ring-based interconnects for Network-on-Chip
Optimized partitioning and priority assignment of real-time applications on heterogeneous platforms with hardware acceleration
2F-MASK-VSS: Two-factor mutual authentication and session key agreement scheme for video surveillance system
Processor architecture I
Session C3: AI architecture and applications I
Design optimization for AUTOSAR models with preemption thresholds and mixed-criticality scheduling
Verifiable privacy-preserving semantic retrieval scheme in the edge computing
A unified architecture for a public key cryptographic coprocessor
A behavioral level tool for design and verification of parallel architectures: PADS
SecurityCloak: Protection against cache timing and speculative memory access attacks
Fundamental principles of modeling timing in hardware description languages
Rapid prototyping of an ATM programmable associative operator
Hybrid structure: data structuring for data flow
CPP: A lightweight memory page management extension to prevent code pointer leakage
Session K1: Opening and keynote session
Scheduling multiple agile earth observation satellites with an edge computing framework and a constructive heuristic algorithm
Efficient hardware implementation of Ray Tracing based on an embedded software for intersection computation
Issues in distributed systems
Multi-processor scheduling of elastic applications in compositional real-time systems
A hierarchical program structure for concurrent fault tolerant software
A rule based programming language for real-time applications
Sim2PIM: A complete simulation framework for Processing-in-Memory
A high performance embedded machine tool controller
CUPID: A labeled dataset with Pentesting for evaluation of network intrusion detection
Implementation of algorithms for graphic surface modeling using transputers
On the fundamentals of leakage aware real-time DVS scheduling for peak temperature minimization
Lightweight ID-based broadcast signcryption for cloud-fog-assisted IoT
Data flow processors for automated visual inspection
Constraints-driven design space exploration for distributed embedded systems
Leveraging real-time and multitasking Ada capabilities to small microcontrollers
Optimal placement for hierarchical VLSI layout design
A multilevel partitioning approach for efficient tasks allocation in heterogeneous distributed systems
Synchronous sessions and fixed priority scheduling
An Occam-based evaluation of a parallel version of simulated annealing
An effective cache scheduling scheme for improving the performance in multi-threaded processors
Transputer based digital signal processing unit for A 3-D vision system
A model-based approach for self-adaptive security in CPS: Application to smart grids
Formal Analysis of 5G Authentication and Key Management for Applications (AKMA)
Feasibility interval and sustainable scheduling simulation with CRPD on uniprocessor platform
Effectiveness of smart toy applications in teaching children with intellectual disability
High speed data searching with a processor array
SPICE: Overview for software process improvement
Systolic MIMD architectures for 4-level spherical subspace tracking
MoNoC: A monitored network on chip with path adaptation mechanism
PADP-FedMeta: A personalized and adaptive differentially private federated meta learning mechanism for AIoT
Smart devices and spaces for pervasive computing
Joint optimization of layering and power allocation for scalable VR video in 6G networks based on Deep Reinforcement Learning
Conflict-free access to streams in multiprocessor systems
Identity authentication based on trajectory characteristics of mobile devices
Quail: Using NVM write monitor to enable transparent wear-leveling
Exploring ICMetrics to detect abnormal program behaviour on embedded devices
A two-layer optimal scheduling framework for energy savings in a data center for Cyber-Physical-Social Systems
Efficient fault tolerant cache memory design
A novel min-process checkpointing scheme for mobile computing systems
Optimal all-ports collective communication algorithms for the k-ary n-cube interconnection networks
Wagyromag: Wireless sensor network for monitoring and processing human body movement in healthcare applications
Real-time probabilistic programming
Concurrent checking of program flow using single-chip microcomputers
Incremental resources estimation with real-time feedback from measurement
Distributed system diagnosability based in self-testing system nodes
Session H3: Parallel processing: Concurrent program design
An architecture of a high-speed digital hologram generator based on FPGA
Enabling PIM-based AES encryption for online video streaming
Analyzing concurrency in streaming applications
Optimization techniques for parallel irregular reductions
Enhanced Gaussian mixture model of RSSI purification for indoor positioning
Corrigendum to 'Blockchain-based decentralized data dissemination scheme in smart transportation' Journal of Systems Architecture 134 (2023) 102800
A Java processor architecture for embedded real-time systems
Model-typed component interfaces
FMESP: Framework for the modeling and evaluation of software processes
LEFT - A learning tool for early floorplanning
An image distance measure insensitive to amplitude and mean value variations: Application to data reduction through SVD
Optimal scheduling of independent jobs in multiprocessor systems
Enforcing role based access control model with multimedia signatures
MeT: The expert methodology tutor of GENITOR
Gray code clustering of wireless data for partial match queries
On-line evolvable fuzzy system for ATM cell-scheduling
TL: A system specification system
Provenance security guarantee from origin up to now in the e-Science environment
Secure checkpointing
ATTEST: Automating the review and update of assurance case arguments
Developments in parallel discrete event simulation at the centre for parallel computing
Interpretation of null values in database machine architecture
Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics
Keynote address K4: The state of global printing in the '90s
A Multi-hashing Index for hybrid DRAM-NVM memory systems
A genetic algorithm-based circuit partitioner for MCMs