yusuke1997/dblp-id-title huggingface dataset:
A Study of Signed-Digit Hybrid Stochastic Number for Arithmetic Computing
A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor
A DC-to-1-GHz Continuously Tunable Bandpass ADC
Neuromorphic Vision Hybrid RRAM-CMOS Architecture
Selection of a Fault Model for Fault Diagnosis Based on Unique Responses
Analysis of Defect Tolerance in Molecular Crossbar Electronics
Fast Writeable Block-Aware Cache Update Policy for Spin-Transfer-Torque RAM
Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core
Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise
Variability Driven Gate Sizing for Binning Yield Optimization
Resistive Open Faults Detectability Analysis and Implications for Testing Low Power Nanometric ICs
Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform
An Efficient Approach to On-Chip Logic Minimization
Baud-rate channel equalization in nanometer technologies
Solving satisfiability problems using reconfigurable computing
Multiple-Bit Upset Protection in Microprocessor Memory Arrays Using Vulnerability-Based Parity Optimization and Interleaving
Memristor-Based Neuromorphic Hardware Improvement for Privacy-Preserving ANN
Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips
Exposing Approximate Computing Optimizations at Different Levels: From Behavioral to Gate-Level
High-Performance Gemmini-Based Matrix Multiplication Accelerator for Deep Learning Workloads
Near-Field Communication Transceiver System Modeling and Analysis Using SystemC/SystemC-AMS With the Consideration of Noise Issues
Instruction level and operating system profiling for energy exposed software
Four-Level Forms for Memristive Material Implication Logic
An Algorithm-Hardware Co-Optimized Framework for Accelerating N: M Sparse Transformers
Low-Supply Sensitivity LC VCOs With Complementary Varactors
Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction
A High-Level Simulink-Based Tool for FPAA Configuration
Providing Integrity in Real-Time Networks-on-Chip
Crosstalk modeling for coupled RLC interconnects with application to shield insertion
Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores
Clock Buffer Polarity Assignment for Power Noise Reduction
Transimpedance Limit Exploration and Inductor-Less Bandwidth Extension for Designing Wideband Amplifiers
Machine Learning Attack Resistant Area-Efficient Reconfigurable Ising-PUF
Efficient test-point selection for scan-based BIST
Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC
Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs
A Novel Thermal-Aware Floorplanning and TSV Assignment With Game Theory for Fixed-Outline 3-D ICs
A 0.0067-mm 2 12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS
Incremental Trace-Buffer Insertion for FPGA Debug
On-chip inductance cons and pros
Timing modeling and optimization under the transmission line model
Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors
HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design
Analog Matrix Inversion Circuit Design for Solving Tridiagonal Linear Systems: A Compact and Decoupled Approach
Analysis and Design of Ripple-Free Bandgap Reference Circuit With p-n-p Bipolars
A Top-Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs
AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications
PIPECIM: Energy-Efficient Pipelined Computing-in-Memory Computation Engine With Sparsity-Aware Technique
Efficient Error Detection Architectures for Postquantum Signature Falcon's Sampler and KEM SABER
A Novel Low Area Overhead Direct Adaptive Body Bias (D-ABB) Circuit for Die-to-Die and Within-Die Variations Compensation
Configurable Logic Operations Using Hybrid CRS-CMOS Cells
A differential equation for placement analysis
Efficient semicustom micropipeline design
Performance-Oriented Parameter Dimension Reduction of VLSI Circuits
Effective Radii of On-Chip Decoupling Capacitors
An Ultralow-Power 65-nm Standard Cell Library for Near/Subthreshold Digital Circuits
Hardware Constructions for Error Detection of Number-Theoretic Transform Utilized in Secure Cryptographic Architectures
Gain and Power Enhancement With Coupled Technique for a Distributed Power Amplifier in 0.25- μm GaN HEMT Technology
Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems"
A 2.4-3.6-GHz Wideband Subharmonically Injection-Locked PLL With Adaptive Injection Timing Alignment Technique
A Single-Ended High-Voltage-Compliant 11-bit Current-Steering Digital-to-Analog Converter for Adaptive Noise Cancellation in Power Over Data Line Networks
A Code-Recombination Algorithm-Based ADC With Feature Extraction for WBSN Applications
Efficient logic-level timing analysis using constraint-guided critical path search
Low-Latency Nested Decoding for Short Generalized Integrated Interleaved BCH Codes
A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber
Finite-Point-Based Transistor Model: A New Approach to Fast Circuit Simulation
Efficient FFT network testing and diagnosis schemes
Diagnostic Fail Data Minimization Using an N-Cover Algorithm
A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC
Improve Chip Pin Performance Using Optical Interconnects
Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification
Theoretical analysis of bus-invert coding
Analysis and Design of On-Chip Decoupling Capacitors
An Energy-Efficient FPGA Accelerator for Swin Transformer
High-Dimensional Many-Objective Bayesian Optimization for LDE-Aware Analog IC Sizing
Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs
Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs Achieving ±1 LSB INL
A 3.5 in 230 Mbytes read-channel chip set for magneto-optical disk drives
Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint
A 15 MHz to 600 MHz, 20 mW, 0.38 mm 2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS
Background memory area estimation for multidimensional signal processing systems
A Statistical Design Approach Using Fixed and Variable Width Transconductors for Positive-Feedback Gain-Enhancement OTAs
The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis
Comparison of high-performance VLSI adders in the energy-delay space
An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform
Background Digital Calibration of Comparator Offsets in Pipeline ADCs
An ROBDD-Based Combinatorial Method for the Evaluation of Yield of Defect-Tolerant Systems-on-Chip
GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths
Diagnosing scan chain faults
A Simplified Vector-Sum Phase Shifter Topology With Low Noise Figure and High Voltage Gain
Online Fault Detection in ReRAM-Based Computing Systems for Inferencing
PFHA: A Novel Page Migration Algorithm for Hybrid Memory Embedded Systems
RISC-V-Based GPGPU With Vector Capabilities for High-Performance Computing
Test-Point Insertion Efficiency Analysis for LBIST in High-Assurance Applications
A 5.4-Gb/s, 0.57-pJ/bit, Single-Loop Referenceless CDR With an Unlimited Bilateral Frequency Detection Scheme
Low-Complexity All-Digital Sample Clock Dither for OFDM Timing Recovery
Power analysis and minimization techniques for embedded DSP software
Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies
An Experimental Evaluation and Analysis of Transient Voltage Fluctuations in FPGAs
A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source
Design and Application of Adaptive Delay Sequential Elements
A Systematic Design Methodology for Low-Power NoCs
A Combined SDC-SDF Architecture for Normal I/O Pipelined Radix-2 FFT
Split-SAR ADCs: Improved Linearity With Power and Speed Optimization
COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems
Revisiting Multiple ECC on High-Density NAND Flash memory
Pop-Crypt: Identification and Management of Popular Words for Enhancing Lifetime of EnCrypted Nonvolatile Main Memories
Nano Magnetic STT-Logic Partitioning for Optimum Performance
A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS
A Lightweight High-Performance Fault Detection Scheme for the Advanced Encryption Standard Using Composite Fields
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme
A Voltage-Time Model for Memristive Devices
Conflux - An Asynchronous Two-to-One Multiplexor for Time-Division Multiplexing and Clockless, Tokenless Readout
Fast comparisons of circuit implementations
Energy-Efficient Multiple Network-on-Chip Architecture With Bandwidth Expansion
A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops
Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA
VLSI Design for SVM-Based Speaker Verification System
Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits
Analysis and Comparison of Low-Power 6-GHz N-Path-Filter-Based Harmonic Selection RF Receiver Front-End Architectures
Dynamic Built-In Redundancy Analysis for Memory Repair
Reverse-body bias and supply collapse for low effective standby power
Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation
QEC: A Quantum Entropy Chip and Its Applications
The Optimal Fan-Out of Clock Network for Power Minimization by Adaptive Gating
A clock interconnect extractor for multigigahertz frequencies incorporating inductance effect
Improving DRAM Performance in 3-D ICs via Temperature Aware Refresh
An On-Chip-Training Keyword-Spotting Chip Using Interleaved Pipeline and Computation-in-Memory Cluster in 28-nm CMOS
Contactless Testing for Prebond Interposers
EMBIRA: An Accelerator for Model-Based Iterative Reconstruction
On Incremental Component Implementation Selection in System Synthesis
Efficient FPGA Mapping of Pipeline SDF FFT Cores
A Low-Power Timing-Error-Tolerant Circuit by Controlling a Clock
IR-Drop in On-Chip Power Distribution Networks of ICs With Nonuniform Power Consumption
Unified functional decomposition via encoding for FPGA technology mapping
Dynamic Wear Leveling for Phase-Change Memories With Endurance Variations
A 10-Gb/s/lane, Energy-Efficient Transceiver With Reference-Less Hybrid CDR for Mobile Display Link Interfaces
Dynamic Bit-Width Adaptation in DCT: An Approach to Trade Off Image Quality and Computation Energy
A Statistical Design Approach for a Digitally Programmable Mismatch-Tolerant High-Speed Nauta Structure Differential OTA in 65-nm CMOS
Fault Tolerance of Switch Blocks and Switch Block Arrays in FPGA
Analysis of power dissipation in double edge-triggered flip-flops
Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning
Effects of Using Advanced Cooling Systems on the Overall Power Consumption of Processors
Stochastic Belief Propagation-Based Iterative Detection and Decoding for MIMO Systems
Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement
An Auto-Reconfigurable 2×4× AC-DC Regulator for Wirelessly Powered Biomedical Implants With 28% Link Efficiency Enhancement
System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs
Fast Neural Network Training on FPGA Using Quasi-Newton Optimization Method
A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification
Effective Radii of On-Chip Decoupling Capacitors Under Noise Constraint
Analysis and Optimization of Switched-Capacitor Piezoelectric Energy Harvesting Interface Circuits
A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems
Efficient Selection of Trace and Scan Signals for Post-Silicon Debug
Synthesis of folded pipelined architectures for multirate DSP algorithms
A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes
Energy-Efficient and Calibration-Aware Fourier-Domain OCT Imaging Processor
Frequency-Limited Reduction of Regular and Singular Circuit Models Via Extended Krylov Subspace Method
On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time
Multicore SIMD ASIP for Next-Generation Sequencing and Alignment Biochip Platforms
Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks
Functional Test-Sequence Grading at Register-Transfer Level
Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops
Efficient Implementation of Dilithium Signature Scheme on FPGA SoC Platform
Characterizing Multistage Nonlinear Drivers and Variability for Accurate Timing and Noise Analysis
On the Use of Simple Electrical Circuit Techniques for Performance Modeling and Optimization in VLSI Systems
A 5-V Switch for Analog Multiplexers With 2.5-V Transistors in 28-nm CMOS Technology
Computation on Stochastic Bit Streams Digital Image Processing Case Studies
Design and FPGA Implementation of a Reconfigurable Digital Down Converter for Wideband Applications
Energy and Performance Models for Synchronous and Asynchronous Communication
A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance
Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator"
Design and Evaluation of a Hybrid Chaotic-Bistable Ring PUF
IPDR: An Inter-Chiplet Priority-Driven Deadlock Resolution for 2-D/2.5-D Multichiplet Systems
An Efficient Component for Designing Signed Reverse Converters for a Class of RNS Moduli Sets of Composite Form {2 k , 2 P -1}
Nanowire Crossbar Logic and Standard Cell-Based Integration
Calibration of Rent's rule models for three-dimensional integrated circuits
Low-Phase-Noise 20-GHz Phase-Locked Loop Using Harmonic-Tuned VCO Assisting With g m -Boosting Technique
PhaseCamouflage: Leveraging Adiabatic Operation to Thwart Reverse Engineering
Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch
A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme
Dynamic Characteristics of Power Gating During Mode Transition
Self-reset logic for fast arithmetic applications
Impact of three-dimensional architectures on interconnects in gigascale integration
Pulsed-Latch Utilization for Clock-Tree Power Optimization
Stopping-Time Management of Smart Sensing Nodes Based on Tradeoffs Between Accuracy and Power Consumption
Diagnosis of single stuck-at faults and multiple timing faults in scan chains
A 0.116 pJ/bit Latch-Based True Random Number Generator Featuring Static Inverter Selection and Noise Enhancement
A Low-Power Single-Phase Clock Multiband Flexible Divider
Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part II - Results and Figures of Merit
Soft errors issues in low-power caches
On Temperature Dependency of Delay for Local, Intermediate, and Repeater Inserted Global Copper Interconnects
Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model
A 6.13 µW and 96 dB CMOS Exponential Generator
A bitstream reconfigurable FPGA implementation of the WSAT algorithm
Reliable Power Gating With NBTI Aging Benefits
Design and Analysis of a Highly Efficient Linearized CMOS Subharmonic Mixer for Zero and Low-IF Applications
Flex-PE: Flexible and SIMD Multiprecision Processing Element for AI Workloads
Improved model-order reduction by using spacial information in moments
Visual register-transfer description of VLSI microarchitectures
NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices
ECP- and CMP-Aware Detailed Routing Algorithm for DFM
Unifiable scheduling and allocation for minimizing system cycle time
Design of a 3-D fully depleted SOI computational RAM
A Charge Domain SRAM Computing-in-Memory Macro With Quantized Interval-Optimized ADC and Input Bit-Level Sparsity-Optimized P2O-DAC for 8-b MAC Operation
An Effective Faults Detection Method for RRAM Application
A Scalable In-Memory Logic Synthesis Approach Using Memristor Crossbar
Two-dimensional retiming [VLSI design]
In~Situ and In-Field Technique for Monitoring and Decelerating NBTI in 6T-SRAM Register Files
Locking by Untuning: A Lock-Less Approach for Analog and Mixed-Signal IC Security
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption
An orthogonal simulated annealing algorithm for large floorplanning problems
MCM-SR: Multiple Constant Multiplication-Based CNN Streaming Hardware Architecture for Super-Resolution
A 9T SRAM Computation-in-Memory Architecture With High-Precision MAC, Enhanced Bitline Voltage Margin, and Improved Frequency Performance Over Conventional Architectures
Efficient Shuffled Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes
Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs
A Reconfigurable CMOS Rectifier With 14-dB Power Dynamic Range Achieving >36-dB/mm 2 FoM for RF-Based Hybrid Energy Harvesting
Automatic Processor Customization for Zero-Overhead Online Software Verification
Nonvolatile Nanopipelining Logic Using Multiferroic Single-Domain Nanomagnets
Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction
A 10-bit 50-MS/s Radiation Tolerant Split Coarse/Fine SAR ADC in 65-nm CMOS
An Efficient and Precision-Reconfigurable Digital CIM Macro for DNN Accelerators
An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock
A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging
All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator
Automatic ReRAM SPICE Model Generation From Empirical Data for Fast ReRAM-Circuit Coevaluation
Editorial Opening of the 2022 TVLSI Editorial Year - Connecting Trends From Society to VLSI Systems
A GPU-Accelerated Parallel Shooting Algorithm for Analysis of Radio Frequency and Microwave Integrated Circuits
Competitive Neural Network Circuit Based on Winner-Take-All Mechanism and Online Hebbian Learning Rule
IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures
Aurora: A Cross-Layer Solution for Thermally Resilient Photonic Network-on-Chip
Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew
RingNet: A Memory-Oriented Network-On-Chip Designed for FPGA
Architecturally Homogeneous Power-Performance Heterogeneous Multicore Systems
Clairvoyant: a synthesis system for production-based specification
A Fully Integrated Architecture for Fast and Accurate Programming of Floating Gates Over Six Decades of Current
A High-Efficiency 6.78-MHz Full Active Rectifier With Adaptive Time Delay Control for Wireless Power Transmission
High-Level Energy Estimation for Submicrometric TSV Arrays
A Wide-Range All-Digital Delay-Locked Loop for DDR1-DDR5 Applications
False path exclusion in delay analysis of RTL structures
Improving multiplier design by using improved column compression tree and optimized final adder in CMOS technology
Sampling phase detector using a resonant tunneling high electron mobility transistor for microwave phase-locked oscillators
Using Scan Side Channel to Detect IP Theft
Practical Implementation of Robust State-Space Obfuscation for Hardware IP Protection
A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS
Computation of Storage Requirements for Multi-Dimensional Signal Processing Applications
GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis
Identifying Optimal Workload Offloading Partitions for CPU-PIM Graph Processing Accelerators
ZeROA: Zero Clock Skew Rotary Oscillatory Array
A Switched-Capacitor-Controlled Digital-Current Modulated Class-E Transmitter
Design of Octave Tuning Range LC VCO With Ultralow K VCO Using Frequency-Dependent Implicit Capacitance Neutralization Technique
Cache sampling by sets
Cost-Optimized Double-Node-Upset-Recovery Latch Designs With Aging Mitigation and Algorithm-Based Verification for Long-Term Robustness Enhancement
Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors
Experimental 5-GHz RF Frontends for Ultra-Low-Voltage and Ultra-Low-Power Operations
Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown
High-Density NVMe SSD With DRAM-Less eRAID Architecture
An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs
Memristor-Based Hardware Accelerator for Image Compression
A Dual-Data Line Read Scheme for High-Speed Low-Energy Resistive Nonvolatile Memories
Symmetric 2-D-Memory Access to Multidimensional Data
Architectural techniques for accelerating subword permutations with repetitions
Editorial: Renewed Excellence for 2025-2026
Some experiments about wave pipelining on FPGA's
Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V DD LSIs
Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits
Efficient Partial Recomputation-Based Fault Detection Approaches for Z-transform
Evaluation of Tradeoffs in the Design of FPGA Fabrics Using Electrostrictive 2-D FETs
Optimization of Pattern Matching Circuits for Regular Expression on FPGA
Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division
Floating Gate Nonvolatile Memory Using Individually Cladded Monodispersed Quantum Dots
Greedy hardware optimization for linear digital circuits using number splitting and refactorization
A 13.4-MHz Relaxation Oscillator With Temperature Compensation
A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range
Verification of Scheduling of Conditional Behaviors in High-Level Synthesis
FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction
High Bandwidth Thermal Covert Channel in 3-D-Integrated Multicore Processors
Drafting in Self-Timed Circuits
Channel width tapering of serially connected MOSFET's with emphasis on power dissipation
Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign
Embedded I/O PAD Circuit Design for OTP Memory Power-Switch Functionality
A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning
Layer-Sensitive Neural Processing Architecture for Error-Tolerant Applications
Path Delay Test Generation Toward Activation of Worst Case Coupling Effects
FPGA Implementation of Staged Projection Refining Multiple Orthogonal Matching Pursuit Algorithm for Compressed Sensing
Optimized Built-In Self-Repair for Multiple Memories
A High-Throughput and Area-Efficient Video Transform Core With a Time Division Strategy
An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS
Mixed-Signal Overclocked I/O Buffers Model Abstraction for Signal Integrity Assessment
Weighted pseudorandom hybrid BIST
DRC Violation Prediction After Global Route Through Convolutional Neural Network
Boolean Functions Over Nano-Fabrics: Improving Resilience Through Coding
On area/depth trade-off in LUT-based FPGA technology mapping
A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction
Backside Active Power Delivery With Hybrid DC-DC Converter Enabled by Amorphous Oxide Semiconductor Transistors