yusuke1997/dblp-id-title huggingface dataset:
In-Memory Computation With Improved Linearity Using Adaptive Sparsity-Based Compact Thermometric Code
High-level library mapping for arithmetic components
VSAGE: An End-to-End Automated VCO-Based ΔΣ ADC Generator
A 28-nm 9T1C SRAM-Based CIM Macro With Hierarchical Capacitance Weighting and Two-Step Capacitive Comparison ADCs for CNNs
Corrections to "Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction"
MOS current mode circuits: analysis, design, and variability
Validating Power Architecture TM Technology-Based MPSoCs Through Executable Specifications
A 2-D Interpolation-Based QRD Processor With Partial Layer Mapping for MIMO-OFDM Systems
Low Voltage and Low Power Divide-By-2/3 Counter Design Using Pass Transistor Logic Circuit Technique
Power Estimation of Embedded Multiplier Blocks in FPGAs
Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect
Statistical estimation of delay-dependent switching activities in embedded CMOS combinational circuits
Delay-Lock-Loop-Based Inductorless and Electrolytic Capacitorless Pseudo-Sine-Current Controller in LED Lighting Systems
DLB-CNet: Difference Learning-Based Convolution Network for Building Change Detection
A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions
Polynomial circuit models for component matching in high-level synthesis
A real-time clustering microchip neural engine
A priori wire length distribution models with multiterminal nets
An Energy-Efficient Binary-Interfaced Stochastic Multiplier Using Parallel Datapaths
Low-Power High-Density STT MRAMs on a 3-D Vertical Silicon Nanowire Platform
An 112-Ch Neural Signal Acquisition SoC With Full-Channel Read-Out and Processing Accelerators
Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses
Hybrid-Type CAM Design for Both Power and Performance Efficiency
An FPGA-Based 1-GHz, 128 × 128 Cross-Correlator for Aperture Synthesis Imaging
Enhanced Secure Architecture for Joint Action Test Group Systems
An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks
Modeling and Synthesis of Asynchronous Pipelines
Accelerating k-Medians Clustering Using a Novel 4T-4R RRAM Cell
A 3-10 GHz, 14 Bands CMOS Frequency Synthesizer With Spurs Reduction for MB-OFDM UWB System
Opening of the 2021 Editorial Year - Overture for a New Year of Change
IoT-Edge Splitting With Pruned Early-Exit CNNs for Adaptive Inference
Analytical models and algorithms for the efficient signal integrity verification of inductance-effect-prominent multicoupled VLSI circuit interconnects
A Distributed Filter Within a Switching Converter for Application to 3-D Integrated Circuits
Delay-Based Dual-Rail Precharge Logic
Complexity of Computing Convex Subgraphs in Custom Instruction Synthesis
A SET/MOS Hybrid Multiplier Using Frequency Synthesis
Mixed FBB/RBB: A Novel Low-Leakage Technique for FinFET Forced Stacks
Reducing Energy at the Minimum Energy Operating Point Via Statistical Error Compensation
Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers
Low-power network-on-chip for high-performance SoC design
Test Cycle Reduction for TSV Test Using Streaming Scan Network on 3-D IC
Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction
An improved Montgomery's algorithm for high-speed RSA public-key cryptosystem
Architectural Impacts of RFiop: RF to Address I/O Pad and Memory Controller Scalability
Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique
Decentralized Thermal-Aware Task Scheduling for Large-Scale Many-Core Systems
Flip-Chip Routing With I/O Planning Considering Practical Pad Assignment Constraints
Efficient Spectrum Sensing for Aeronautical LDACS Using Low-Power Correlators
ContextPreRF: Enhancing the Performance and Energy of GPUs With Nonuniform Register Access
Accurate power estimation of CMOS sequential circuits
SenHDC: A 3-D NAND Flash-Based Processing-in-Sensor Hyperdimensional Computing Architecture
Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM
A Fast Convergence Second-Order Compensation for Timing Skew in Time-Interleaved ADCs
A 0.875-0.95-pJ/b 40-Gb/s PAM-3 Baud-Rate Receiver With One-Tap DFE
Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores
High-Accuracy and Low-Multiplication Recursive Discrete Cosine Transform Algorithm Design and Its Realization in Mel-Scale Frequency Cepstral Coefficients
The design of the MGAP-2: a micro-grained massively parallel array
Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping
Design of a pipelined datapath synthesis system for digital signal processing
Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI [microprocessors]
Low-Cost and Energy-Efficient Distributed Synchronization for Embedded Multiprocessors
A High-Performance Three-Engine Architecture for H.264/AVC Fractional Motion Estimation
Quasi-Resonant Interconnects: A Low Power, Low Latency Design Methodology
Layout-driven architecture synthesis for high-speed digital filters
Configurable Multimode Embedded Floating-Point Units for FPGAs
SoPC Self-Integration Mechanism for Seamless Architecture Adaptation to Stream Workload Variations
Integrated Placement and Skew Optimization for Rotary Clocking
A Physical-Location-Aware X-Bit Redistribution for Maximum IR-Drop Reduction
Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting
Design Space Exploration for 3-D Cache
Closed-Form Expressions for I/O Simultaneous Switching Noise Revisited
A Self-Biased Current Reference Source-Based Pre-Bond TSV Test Solution
Real-Time ORB Accelerator for Embedded FPGA-Based SoCs With ROS Integration
Comprehensive Analysis and Control of Design Parameters for Power Gated Circuits
Floating-Point Divider Design for FPGAs
The design and verification of a high-performance low-control-overhead asynchronous differential equation solver
Design and Analysis of Dual-Mode Digital-Control Step-Up Switched-Capacitor Power Converter With Pulse-Skipping and Numerically Controlled Oscillator-Based Frequency Modulation
MetaCore: an application-specific programmable DSP development system
Design of FSM-Based Function With Reduced Number of States in Integral Stochastic Computing
On the Exploitation of Narrow-Width Values for Improving Register File Reliability
Clocked Hysteresis Control Scheme With Power-Law Frequency Scaling in Buck Converter to Improve Light-Load Efficiency for IoT Sensor Nodes
Single-Chip Design for Intelligent Surveillance System
Defragmentation for Efficient Runtime Resource Management in NoC-Based Many-Core Systems
Configuration Locking and Schedulability Estimation for Reduced Reconfiguration Overheads of Reconfigurable Systems
True Random Number Generation Using Latency Variations of FRAM
A 0.31-1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications
Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults
A New Fast-Response Current-Mode Buck Converter With Improved I 2 -Controlled Techniques
A simulation tool for dynamically reconfigurable field programmable gate arrays
Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework
Dynamic Statistical-Timing-Analysis-Based VLSI Path Delay Test Pattern Generation
P 2 -ViT: Power-of-Two Post-Training Quantization and Acceleration for Fully Quantized Vision Transformer
Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube
A Method for Improving Power Grid Resilience to Electromigration-Caused via Failures
A 0.3 nW, 0.093%/V Line Sensitivity, Temperature Compensated Bulk-Programmable Voltage Reference for Wireless Sensor Nodes
Corrections to "Efficient Fault-Detection Architectures for Barrett Reduction and Multiplication in Classical and Post-Quantum Cryptographic Systems"
Design and Analysis of $D$ -Band On-Chip Modulator and Signal Source Based on Split-Ring Resonator
Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key
Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors
A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures
Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing
Accurate On-Chip Temperature Sensing for Multicore Processors Using Embedded Thermal Sensors
SysCIM: A Heterogeneous Chip Architecture for High-Efficiency CNN Training at Edge
A Novel Thyristor-Based Silicon Physical Unclonable Function
Thermal Exploration of RSFQ Integrated Circuits
Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores
Design of a 5.3-GHz 31.3-dBm Fully Integrated CMOS Power Amplifier Using Folded Splitting and Combining Architecture
An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling
A MIMO Decoder Accelerator for Next Generation Wireless Communications
Guest editorial 11th international symposium on system-level synthesis and design (ISSS'98)
Placement-Based Nonlinearity Reduction Technique for Differential Current-Steering DAC
SRAM Leakage Reduction by Row/Column Redundancy Under Random Within-Die Delay Variation
Design and Analysis of a New Three-Stage Feedback Amplifier Utilizing Signal Flow Graph Domain Inspection Approach
EMPIRE: An Efficient and Compact Multiple-Parameterized Model-Order Reduction Method for Physical Optimization
Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors
Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology
A -20-dBm Sensitivity RF Energy-Harvesting Rectifier Front End Using a Transformer IMN
Graded-channel MOSFET (GCMOSFET) for high performance, low voltage DSP applications
Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk
A Compact Power-on-Reset Circuit With Configurable Brown-Out Detection
A Highly-Digital VCO-Based Analog-to-Digital Converter Using Phase Interpolator and Digital Calibration
Stack Sizing for Optimal Current Drivability in Subthreshold Circuits
A 1.2-V 450-μW G m -C Bluetooth Channel Filter Using a Novel Gain-Boosted Tunable Transconductor
Hardware Implementation for Real-Time Haze Removal
X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan
On the Restore Operation in MTJ-Based Nonvolatile SRAM Cells
1.9-ps Jitter, 10.0-dBm-EMI Reduction Spread-Spectrum Clock Generator With Autocalibration VCO Technique for Serial-ATA Application
A Design Methodology for Thermal Monitoring of Reusable Passive Interposers With RTDs
LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor
A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains
Integer Codes Correcting Double Errors and Triple-Adjacent Errors Within a Byte
SRAM Read/Write Margin Enhancements Using FinFETs
A Chip-Area Efficient Voltage Regulator for VLSI Systems
Orchestrating Cache Management and Memory Scheduling for GPGPU Applications
A 300-mV Auto Shutdown Comparator-Based Continuous Time Δ∑ Modulator
Algorithm-based low-power transform coding architectures: the multirate approach
A Fast Floating-Point Multiply-Accumulator Optimized for Sparse Linear Algebra on FPGAs
Decentralized and Passive Model Order Reduction of Linear Networks With Massive Ports
PCBChain: Lightweight Reconfigurable Blockchain Primitives for Secure IoT Applications
Runtime Adaptive Circuit Switching and Flow Priority in NoC-Based MPSoCs
Efficient Error Estimation for High-Level Design Space Exploration of Approximate Computing Systems
FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators
Parametric Yield Analysis and Optimization in Leakage Dominated Technologies
Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems
Memory-Efficient Multiplier-Less 2-D DWT Design Using Combined Convolution and Lifting Schemes for Wireless Visual Sensors
Partial bus-invert coding for power optimization of application-specific systems
Accurate and efficient simulation of synchronous digital switching noise in systems on a chip
Power minimization in QoS sensitive systems
A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less
Many-Core Processors Granularity Evaluation by Considering Performance, Yield, and Lifetime Reliability
Reconfigurable Filter Bank With Complete Control Over Subband Bandwidths for Multistandard Wireless Communication Receivers
Extracting secret keys from integrated circuits
A Wide Voltage Range Digital I/O Design Using Novel Floating N-Well Circuit
Information Theoretic Modeling and Analysis for Global Interconnects With Process Variations
True single-phase adiabatic circuitry
SA-FEMIP: A Self-Adaptive Features Extractor and Matcher IP-Core Based on Partially Reconfigurable FPGAs for Space Applications
A 5.8 nW 9.1-ENOB 1-kS/s Local Asynchronous Successive Approximation Register ADC for Implantable Medical Device
RCU- 2 m : A VLSI Radix- 2 m Cubic Unit
Graceful Degradation of Reconfigurable Scan Networks
Designing via-configurable logic blocks for regular fabric
Low Complexity Design of Logistic Distance Metric Adaptive Filter for Impulsive Noise Environments
Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling
An Equalizer With Controllable Transfer Function for 6-Gb/s HDMI and 5.4-Gb/s DisplayPort Receivers in 28-nm UTBB-FDSOI
A Reliability Enhanced Address Mapping Strategy for Three-Dimensional (3-D) NAND Flash Memory
Fine-Grained Energy-Constrained Microprocessor Pipeline Design
A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL
Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration
Guest Editorial System-Level Interconnect Prediction
A 65-nm 55.8-TOPS/W Compact 2T eDRAM-Based Compute-in-Memory Macro With Linear Calibration
Run-Time Integration of Reconfigurable Video Processing Systems
Time-Domain Multiply-Accumulate Unit
Design of Modified Second-Order Frequency Transformations Based Variable Digital Filters With Large Cutoff Frequency Range and Improved Transition Band Characteristics
DVFT: A Lightweight Solution for Power-Supply Noise-Based TRNG Using Dynamic Voltage Feedback Tuning System
A Methodology for Datapath Energy Prediction and Optimization in Near Threshold Voltage Regime
A 0.4-1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End
Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system
Memory Optimization for Energy-Efficient Differentially Private Deep Learning
All-Rounder: A Flexible AI Accelerator With Diverse Data Format Support and Morphable Structure for Multi-DNN Processing
Lifetime Enhancement Techniques for PCM-Based Image Buffer in Multimedia Applications
Intrinsic leakage in deep submicron CMOS ICs-measurement-based test solutions
Soft-Error-Aware SRAM With Multinode Upset Tolerance for Aerospace Applications
FX: a fast approximate fault simulator for the switch-level using VHDL
Viewer-Aware Intelligent Efficient Mobile Video Embedded Memory
Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs
Area-Efficient Iterative Logarithmic Approximate Multipliers for IEEE 754 and Posit Numbers
A Design of Fast-Settling, Low-Power 4.19-MHz Real-Time Clock Generator With Temperature Compensation and 15-dB Noise Reduction
Simplifying Clock Gating Logic by Matching Factored Forms
Accurate Temperature Estimation Using Noisy Thermal Sensors for Gaussian and Non-Gaussian Cases
A 170-dB Ω CMOS TIA With 52-pA Input-Referred Noise and 1-MHz Bandwidth for Very Low Current Sensing
Symmetric and Multiphase-Interleaved Ladder Bucks for DC Capacitors Elimination
Multivoltage Multifrequency Low-Energy Synthesis for Functionally Pipelined Datapath
DFSB-Based Thermal Management Scheme for 3-D NoC-Bus Architectures
EMFORCED: EM-Based Fingerprinting Framework for Remarked and Cloned Counterfeit IC Detection Using Machine Learning Classification
Integrated Hardware Architecture for Efficient Computation of the $n$-Best Bio-Sequence Local Alignments in Embedded Platforms
A 12-bit, 1.1-GS/s, Low-Power Flash ADC
All-Digital Fast-Locking Pulsewidth-Control Circuit With Programmable Duty Cycle
Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications
Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating
On Efficiency Enhancement of SHA-3 for FPGA-Based Multimodal Biometric Authentication
SAT-Hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain
An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM
Run-Time Management of a MPSoC Containing FPGA Fabric Tiles
Adaptive Proactive Reconfiguration: A Technique for Process-Variability- and Aging-Aware SRAM Cache Design
Architectural Frameworks for Security and Reliability of MPSoCs
A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time
Automatic Correction of Dynamic Power Management Architecture in Modern Processors
An RRAM-Based Computing-in-Memory Macro With Low-Power Readout/Hold Circuits and Activation Differential Strategy for AdderNet
A 40-nm 1.89-pJ/SOP Scalable Convolutional Spiking Neural Network Learning Core With On-Chip Spatiotemporal Back-Propagation
Memory binding for performance optimization of control-flow intensive behavioral descriptions
Global Passivity Enforcement Algorithm for Macromodels of Interconnect Subnetworks Characterized by Tabulated Data
Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection
Reconfigurable Stateful Logic Circuit With Cu/CuI/Pt Memristors for In-Memory Computing
Fixed-outline floorplanning: enabling hierarchical design
CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers
Test Scores for Improving the Accuracy of Logic Diagnosis for Multiple Defects
A Hierarchical Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs
Memory-Based Architecture for Multicharacter Aho-Corasick String Matching
Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM
LAMANet: A Real-Time, Machine Learning-Enhanced Approximate Message Passing Detector for Massive MIMO
DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates
A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits
Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars
A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration
Power Analysis of Embedded NoCs on FPGAs and Comparison With Custom Buses
Power-optimal encoding for a DRAM address bus
A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply
Enhancing Wireless PHY With Adaptive OFDM and Multiarmed Bandit Learning on Zynq System-on-Chip
A Triple Burst Error Correction Based on Region Selection Code
Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs
An Accumulator - Based Test-Per-Clock Scheme
Object-oriented domain specific compilers for programming FPGAs
Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design
Virtual-Tile-Based Flip-Flop Alignment Methodology for Clock Network Power Optimization
Bounds on pseudoexhaustive test lengths
Exploring the design space of mixed swing quadrail for low-power digital circuits
Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC
A Comparator-Based Rail Clamp
A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications
Time-Domain Arithmetic Logic Unit With Built-In Interconnect
Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs
Optimum Circuits for Bit-Dimension Permutations
FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs
Design of a Real-Time Movement Decomposition-Based Rodent Tracker and Behavioral Analyzer Based on FPGA
Scan Chain Hold-Time Violations: Can They be Tolerated?
FPGA Implementations of 256-Bit SNOW Stream Ciphers for Postquantum Mobile Security
CORDIC-Based High-Speed VLSI Architecture of Transform Model Estimation for Real-Time Imaging
Addressing Resiliency of In-Memory Floating Point Computation
Toward the accurate prediction of placement wire length distributions in VLSI circuits
Power and Reliability Management of SoCs
A Flexible Continuous-Time Δ Σ ADC With Programmable Bandwidth Supporting Low-Pass and Complex Bandpass Architectures
Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs
Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3-D Multicore Processors
A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder
Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops
A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration
Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities
A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories
Design of wireless on-wafer submicron characterization system
Write Disturbance Modeling and Testing for MRAM
A Scalable Hardware Accelerator for Mobile DNA Sequencing
Variable Resistance Spectrum Assignment in Phase Change Memory Systems
Fast and Accurate Emissivity and Absolute Temperature Maps Measurement for Integrated Circuits
FPGA-Based Real-Time ECG Classification System Using Quantized Inception-ResNeXt Neural Network and CWT Approximation
Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM)
An evaluation of asynchronous addition
Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs
Critical evaluation of SOI design guidelines
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
Corrections to "GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features"
Design Methodology for Distributed Large-Scale ERSFQ Bias Networks
Imitation Learning for Dynamic VFI Control in Large-Scale Manycore Systems
The Conjugated Current Mirrors: A General Enhancement in Transconductance Amplifiers
Improving Error Tolerance for Multithreaded Register Files
Bit-Complemented Test Data to Replace the Tail of a Fault Coverage Curve
Non-Uniform Coverage by n -Detection Test Sets
A Novel Hybrid Delay Unit Based on Dummy TSVs for 3-D On-Chip Memory
Partial address directory for cache access
Efficient Modulo 2 n +1 Multipliers
A Low-Power Reconfigurable Narrowband/Wideband LNA for Cognitive Radio-Wireless Sensor Network
Efficient Pattern Matching Algorithm for Memory Architecture
GPU-Based Redundancy Analysis Using Concurrent Evaluation
Detection of Recycled ICs Using Backscattering Side-Channel Analysis
Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers
A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling
Built-In Functional Tests for Silicon Validation and System Integration of Telecom SoC Designs
Hardware Implementation of Nakagami and Weibull Variate Generators
Polaris: A System-Level Roadmapping Toolchain for On-Chip Interconnection Networks
Watermarking in Hard Intellectual Property for Pre-Fab and Post-Fab Verification