yusuke1997/dblp-id-title huggingface dataset:
Nonvolatile Memory With Extremely Low-Leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistor
An Ultra-Low-Power 9.8 GHz Crystal-Less UWB Transceiver With Digital Baseband Integrated in 0.18 µm BiCMOS
A 1.8-V MOSFET-only ΣΔ modulator using substrate biased depletion-mode MOS capacitors in series compensation
A high resolution frequency multiplier for clock signal generation
An RC Delay-Based Pressure-Sensing System With Energy-Efficient Bit-Level Oversampling Techniques for Implantable IOP Monitoring Systems
Introduction to the Special Issue on ESSCIRC'2004
A 2-GHz Bandwidth, 0.25-1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13µm CMOS
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity
Precise final state determination of mismatched CMOS latches
A high performance 0.35-μm 3.3-V BiCMOS technology optimized for product porting from a 0.6-μm 3.3-V BiCMOS technology
A low-power 3D rendering engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals
A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling
Curvature-compensated BiCMOS bandgap with 1-V supply voltage
A SAR-Assisted Two-Stage Pipeline ADC
A 0.5 V Operation V TH Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems
A 240 GHz Fully Integrated Wideband QPSK Transmitter in 65 nm CMOS
A 174.3-dB FoM VCO-Based CT ΔΣ Modulator With a Fully-Digital Phase Extended Quantizer and Tri-Level Resistor DAC in 130-nm CMOS
An enhanced slew rate source follower
An 8 ns 256 K BiCMOS RAM
Introduction to the Special Issue on the IEEE 2011 Custom Integrated Circuits Conference
A 9.5-Gb/s Si-bipolar ECL array
Common-Gate Load-Pull With Q-Band Application
A Reconfigurable Cross-Connected Wireless-Power Transceiver for Bidirectional Device-to-Device Wireless Charging
A 320-MHz NS TD-ADC-Assisted C/DT Hybrid Pipelined ADC With Single OTA Second-Order RAF
A 64-bit carry look ahead adder using pass transistor BiCMOS gates
A high-speed current-multiplexed sample-and-hold amplifier with low hold step
A family of high-swing CMOS operational amplifiers
A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells
A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter
Design of Sub-Gigahertz Reconfigurable RF Energy Harvester From -22 to 4 dBm With 99.8% Peak MPPT Power Efficiency
An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS
Macromodels in the frequency domain analysis of microwave resonators
A High-Efficiency Dual-Polarity Thermoelectric Energy-Harvesting Interface Circuit With Cold Startup and Fast-Searching ZCD
An Efficiency-Enhanced Auto-Reconfigurable 2 ˟ /3 ˟ SC Charge Pump for Transcutaneous Power Transmission
Code-Domain Multiplexing for Shared IF/LO Interfaces in Millimeter-Wave MIMO Arrays
A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation
Offset cancelling circuit
Practical Considerations for a Digital Inductive-Switching DC/DC Converter With Direct Battery Connect in Deep Sub-Micron CMOS
A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS
A DTC-Free Fractional-N BBPLL With FIR-Embedded Injection-Locked-Oscillator-Based Phase-Domain Lowpass Filter
A 3-Axis Gyroscope for Electronic Stability Control With Continuous Self-Test
A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM
A High-Efficiency Low-Cost Multi-Antenna Energy Harvesting System With Leakage Suppression
High-sensitivity BiCMOS OEIC for optical storage systems
Skew-tolerant domino circuits
A low-power wide-band amplifier using a new parasitic capacitance compensation technique
On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM
Smart Write Algorithm to Enhance Performances and Reliability of an RRAM Macro
Thermal design and simulation of bipolar integrated circuits
A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding
RF circuit design aspects of spiral inductors on silicon
A scannable pulse-to-static conversion register array for self-timed circuits
A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories
A 1.2- mu m BiCMOS sample-and-hold circuit with a constant-impedance, slew-enhanced sampling gate
A 64-point Fourier transform chip for video motion compensation using phase correlation
Low-noise, high-gain Si-bipolar preamplifiers for 10 Gb/s optical-fiber links-design and realization
A 400-μW IoT Low-IF Voltage-Mode Receiver Front-End With Charge-Sharing Complex Filter
A 900-MHz/1.8-GHz CMOS receiver for dual-band applications
A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning
Analysis and Design of Wideband Filtering ADCs Using Continuous-Time Pipelining
VIPER: a VLIW integer microprocessor
A register-controlled symmetrical DLL for double-data-rate DRAM
A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver
Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra
Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC
An analog background calibration technique for time-interleaved analog-to-digital converters
A 232-1996-kS/s Robust Compressive Sensing Reconstruction Engine for Real-Time Physiological Signals Monitoring
A 77-GHz SiGe Integrated Six-Port Receiver Front-End for Angle-of-Arrival Detection
Dynamic computational blocks for bit-level systolic arrays
Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration
A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor
A neuron-MOS neural network using self-learning-compatible synapse circuits
A Single-Chip Dual-Band 22-29-GHz/77-81-GHz BiCMOS Transceiver for Automotive Radars
A 1.1 nW Energy-Harvesting System with 544 pW Quiescent Power for Next-Generation Implants
Wrapper-based bus implementation techniques for performance improvement and cost reduction
A 12 bit 2.9 GS/s DAC With IM3 ≪ -60 dBc Beyond 1 GHz in 65 nm CMOS
CMOS OTA-C high-frequency sinusoidal oscillators
A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS
A cellular-band CDMA 0.25-μm CMOS LNA linearized using active post-distortion
A Hybrid Structure Dual-Path Step-Down Converter With 96.2% Peak Efficiency Using 250-m $\Omega$ Large-DCR Inductor
A fully differential sample-and-hold circuit for high-speed applications
A 60 mW per Lane, 4$, times, $23-Gb/s 2$ ^7 -$1 PRBS Generator
A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver
A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI
A Calibration-Free 14-b 0.7-mW 100-MS/s Pipelined-SAR ADC Using a Weighted- Averaging Correlated Level Shifting Technique
A 40-43-Gb/s clock and data recovery IC with integrated SFI-5 1: 16 demultiplexer in SiGe technology
Large-swing CMOS buffer amplifier
A Multi-Phase Coupled Oscillator Using Inductive Resonant Coupling and Modified Dual-Tank Techniques
A 0.18-μm 3.0-V 64-Mb nonvolatile phase-transition random access memory (PRAM)
A 1-V TFT-load SRAM using a two-step word-voltage method
A multigigahertz clocking scheme for the Pentium(R) 4 microprocessor
A scalable substrate noise coupling model for design of mixed-signal IC's
A Highly Efficient 165-GHz 4FSK 17-Gb/s Transceiver System With Frequency Overlapping Architecture in 65-nm CMOS
A 1.5-μJ/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of Microrobots
Design and Analysis of a Microwave-Optical Dual Modality Biomolecular Sensing Platform
A 10-Gb/s laser/modulator driver IC with a dual-mode actively matched output buffer
Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory
A bit-serial VLSI array processing chip for image processing
A Synchronized Switch Harvesting Rectifier With Reusable Storage Capacitors for Piezoelectric Energy Harvesting
A Fully Parallel Nonbinary LDPC Decoder With Fine-Grained Dynamic Clock Gating
A 40-GHz frequency divider in 0.18-μm CMOS technology
A ferroelectric memory-based secure dynamically programmable gate array
A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS
The design of a charge-integrating modified floating-point ADC chip
Comprehensive study of multiband unconditional stabilization of common-source and common-gate MESFET transistors using feedback
A four-quadrant CMOS analog multiplier for analog neural networks
Design techniques for automatically tuned integrated gigahertz-range active LC filters
A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU
A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor
A packaged broad-band monolithic variable gain amplifier implemented in AlGaAs/GaAs HBT technology
A high-speed CMOS dual-phase dynamic-pseudo NMOS ((DP) 2 ) latch and its application in a dual-modulus prescaler
A 30-frames/s, $252\times144$ SPAD Flash LiDAR With 1728 Dual-Clock 48.8-ps TDCs, and Pixel-Wise Integrated Histogramming
Capacitorless 1T DRAM sensing scheme with automatic reference generation
A 1920 × 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles
Analytical modeling of the CMOS-like a-Si:H TFT inverter circuit
A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution
An Energy-Efficient Equalized Transceiver for RC-Dominant Channels
A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter
A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques
A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, -0.12% for Battery-Monitoring Applications
Minimizing the Supply Sensitivity of a CMOS Ring Oscillator Through Jointly Biasing the Supply and Control Voltages
A 5-V CMOS programmable acoustic front-end for ISDN terminals and digital telephone sets
Comments on "A General Theory of Phase Noise in Electrical Oscillators"
Watt-Level mm-Wave Power Amplification With Dynamic Load Modulation in a SiGe HBT Digital Power Amplifier
74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain
A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 μm CMOS Technology
A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories
A Σ-Δ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications
Comments on "A carry-free 54 b×54 b multiplier using equivalent bit conversion algorithm"
A portable clock multiplier generator using digital CMOS standard cells
A VLSI array processor for 16-point FFT
A Fast Back-to-Lock DPLL-Based 192-210-GHz Chirp Generator With +5.9-dBm Peak Output Power for Sub-THz Imaging and Sensing
An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips
Efficient RF-PA Two-Chip Supply Modulator Architecture for 4G LTE and 5G NR Dual-Connectivity RF Front End
Physical design guides for substrate noise reduction in CMOS digital circuits
A new low-noise 100-MHz balanced relaxation oscillator
A low noise, high resolution silicon temperature sensor
A MOS switched-capacitor ladder filter in SIMOX technology for high temperature applications up to 300°C
A Wearable Real-Time CMOS Dosimeter With Integrated Zero-Bias Floating Gate Sensor and an 861-nW 18-Bit Energy-Resolution Scalable Time-Based Radiation to Digital Converter
Direct-conversion radio transceivers for digital communications
An optimized 1.0- mu m CMOS technology for next-generation channelless gate arrays
A 0.5-V 1-μW successive approximation ADC
Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers
A 1.8-GHz monolithic LC voltage-controlled oscillator
A 1.9-3.8 GHz ΔΣ Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency
A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
A CCD video delay line with charge-integrating amplifier
A low-power CMOS analog vector quantizer
46 Gb/s DEMUX, 50 Gb/s MUX, and 30 GHz static frequency divider in silicon bipolar technology
DC to 40-GHz broad-band amplifiers using AlGaAs/GaAs HBT's
A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications
Circuit techniques for 1.5-V power supply flash memory
A robust, load-insensitive pad driver
High-Throughput Non-Binary LDPC Decoder Architecture Using Parallel EMS Algorithm
SLAM-CIM: A Visual SLAM Backend Processor With Dynamic-Range-Driven-Skipping Linear-Solving FP-CIM Macros
A 0.5-1-V Time-Voltage Hybrid Domain Dual- Loop Analog LDO With Wide-Bandwidth High PSR in 28 nm
A 1 A, Dual-Inductor 4-Output Buck Converter With 20 MHz/100 MHz Dual-Frequency Switching and Integrated Output Filters in 65 nm CMOS
A video codec LSI for high-definition TV systems with one-transistor DRAM line memories
A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET
An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs
Integration of algorithmic VLSI synthesis with testability incorporation
Double Pile-Up Resonance Energy Harvesting Circuit for Piezoelectric and Thermoelectric Materials
CMOS tapered buffer
Chip-to-Chip Interfaces for Large-Scale Highly Configurable mmWave Phased Arrays
A nonvolatile analog programmable voltage source using the VIPMOS EEPROM structure
A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation
12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s
Compact CMOS constant-g m rail-to-rail input stage with g m -control by an electronic zener diode
Effect of gate resistance on high-frequency power switching efficiencies of advanced power MOSFETs
A 0.24-nJ/b Wireless Body-Area-Network Transceiver With Scalable Double-FSK Modulation
Analysis and Design of Ultra-Wideband mm-Wave Injection-Locked Frequency Dividers Using Transformer-Based High-Order Resonators
A 16-b 320-kHz CMOS A/D converter using two-stage third-order Sigma Delta noise shaping
A 1.24 $\mu$ A Quiescent Current NMOS Low Dropout Regulator With Integrated Low-Power Oscillator-Driven Charge-Pump and Switched-Capacitor Pole Tracking Compensation
A Wideband Digital RF Receiver Front-End Employing a New Discrete-Time Filter for m-WiMAX
A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump
Rapid yield estimation as a computer aid for analog circuit design
A wide-band NMOS balanced modulator/amplifier which uses 1- mu m transistors for linearity
A Differential-Ramp Based 65 dB-Linear VGA Technique in 65 nm CMOS
A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC
Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies
All-digital PLL and transmitter for mobile phones
Introduction to the Special Section on the 2007 Asian Solid-State Circuits Conference (A-SSCC'07)
The CMOS gate forest: an efficient and flexible high-performance ASIC design environment
A 45-Mbit/s CMOS VLSI digital phase aligner
A 0.5-V MTCMOS/SIMOX logic gate
A 915-1220 TOPS/W, 976-1301 GOPS Hybrid In-Memory Computing Based Always-On Image Processing for Neuromorphic Vision Sensors
An 8 GHz silicon bipolar clock-recovery and data-regenerator IC
A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel
A 112-dB SFDR 89-dB SNDR VCO-Based Sensor Front-End Enabled by Background-Calibrated Differential Pulse Code Modulation
A 25 Gb/s 1.13 pJ/b -10.8 dBm Input Sensitivity Optical Receiver in 40 nm CMOS
An Ultra-Low Voltage, Low-Noise, High Linearity 900-MHz Receiver With Digitally Calibrated In-Band Feed-Forward Interferer Cancellation in 65-nm CMOS
A Subharmonic Receiver in SiGe Technology for 122 ~ GHz Sensor Applications
A Si BiCMOS transimpedance amplifier for 10-Gb/s SONET receiver
Advanced integrated-circuit reliability simulation including dynamic stress effects
A 270-kb/s 35-mW modulator IC for GSM cellular radio hand-held terminals
250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture
A Clock-Less 10-bit Pipeline-Like A/D Converter for Self-Triggered Sensors
A 40 nm Fully Integrated 82 mW Stereo Headphone Module for Mobile Applications
A Ten-Level Series-Capacitor 24-to-1-V DC-DC Converter With Fast In Situ Efficiency Tracking, Power-FET Code Roaming, and Switch Node Power Rail
A wide-bandwidth low-voltage PLL for PowerPC microprocessors
A 256×256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output
34-GBd Linear Transimpedance Amplifier for 200-Gb/s DP-16-QAM Optical Coherent Receivers
A Millimeter-Wave CMOS Heterodyne Receiver With On-Chip LO and Divider
A 450-Mb/s analog front end for PRML read channels
A 900-MHz 1-V CMOS frequency synthesizer
Phase noise degradation at high oscillation amplitudes in LC-tuned VCO's
A Low-Power, High-Fidelity Stereo Audio Codec in 0.13 µm CMOS
Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process
A 69 dB SNDR, 25 MHz BW, 800 MS/s Continuous-Time Bandpass ΔΣ Modulator Using a Duty-Cycle-Controlled DAC for Low Power and Reconfigurability
Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes
On-Chip I DDQ testability schemes for detecting multiple faults in CMOS ICs
A 32-mW 320-MHz continuous-time complex delta-sigma ADC for multi-mode wireless-LAN receivers
A 1-10-MHz Frequency-Aware CMOS Active Rectifier With Dual-Loop Adaptive Delay Compensation and >230-mW Output Power for Capacitively Powered Biomedical Implants
Highly linear 0.18-μm CMOS power amplifier with deep n-Well structure
An integrated one-cycle control buck converter with adaptive output and dual loops for output error correction
Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time
CMOS wireless phase-shifted transmitter
A digital readout technique for capacitive sensor applications
A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration
A Monolithic 25-Gb/s Transceiver With Photonic Ring Modulators and Ge Detectors in a 130-nm CMOS SOI Process
A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS
Fully parallel integrated CAM/RAM using preclassification to enable large capacities
A 286 F 2 /Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access
A Three-Stage 18.5-24-GHz GaN-on-SiC 4 W 40% Efficient MMIC PA
Analog ALC crystal oscillators for high-temperature applications
A design and implementation of fully programmable switched-current IIR filters
An Embedded 65 nm CMOS Baseband IQ 48 MHz-1 GHz Dual Tuner for DOCSIS 3.0
A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit
A Large-Area Image Sensing and Detection System Based on Embedded Thin-Film Classifiers
Design of high-power, high-efficiency 60-GHz MMICs using an improved nonlinear PHEMT model
Polysilicon TFT circuit design and performance
A 5 mm 2 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform
A self-latching A/D converter using resonant tunneling diodes
A 0.18-μm CMOS offset-PLL upconversion modulation loop IC for DCS1800 transmitter
A 250-Mb/s, 700-mW, 32-highway*8-b S/P converter LSI with cross-access memory
A 0.7-V 870-µW Digital-Audio CMOS Sigma-Delta Modulator
Evaluation of three 32-bit CMOS adders in DCVS logic for self-timed circuits
A Power-Efficient Switched-Capacitor Stimulating System for Electrical/Optical Deep Brain Stimulation
A 7 GHz ERBW 1.1 GS/s 6-bit PVT Tolerant Asynchronous Charge-Injection SAR With Only 8.5 fF Input Capacitance in 28 nm CMOS
The process engineer's workbench
A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation
A 58.9-dB ACR, 85.5-dB SBA, 5-26-MHz Configurable-Bandwidth, Charge-Domain Filter in 65-nm CMOS
A 660-μW 50-Mops 1-V DSP for a hearing aid chip set
A 1.5-ns 32-b CMOS ALU in double pass-transistor logic
Quad-band GSM/GPRS/EDGE polar loop transmitter
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration
A 17.1-17.3-GHz image-reject downconverter with phase-tunable LO using 3× subharmonic injection locking
A 1-GHz/0.9-mW CMOS/SIMOX divide-by-128/129 dual-modulus prescaler using a divide-by-2/3 synchronous counter
Computer-aided design considerations for mixed-signal coupling in RF integrated circuits
SOI-DRAM circuit technologies for low power high speed multigiga scale memories
A novel CMOS digital clock and data decoder
Scalable Spatial Notch Suppression in Spatio-Spectral-Filtering MIMO Receiver Arrays for Digital Beamforming
1.6 GHz Low-Power Cross-Correlator System Enabling Geostationary Earth Orbit Aperture Synthesis
Energy-Efficient Motion-Triggered IoT CMOS Image Sensor With Capacitor Array-Assisted Charge-Injection SAR ADC
A PAL/NTSC digital video encoder on 0.6-μm CMOS with 66 dB typical SNR, 0.4% differential gain, and 0.2° differential phase
A 1.2-V 10-μ W NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2°C (3 Sigma ) From - 70°C to 125°C
A 100-MHz macropipelined VAX microprocessor
A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip
Auto Correction Feedback for Ripple Suppression in a Chopper Amplifier
A multiplier-accumulator macro for a 45 MIPS embedded RISC processor
An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS
An Automotive-Grade Monolithic Masterless Fault-Tolerant Hybrid Dickson DC-DC Converter for 48-V Multi-Phase Applications
An 80×25 Pixel CMOS Single-Photon Sensor With Flexible On-Chip Time Gating of 40 Subarrays for Solid-State 3-D Range Imaging
A 63 mA 112/94 dB DR IF Bandpass ΔΣ Modulator With Direct Feed-Forward Compensation and Double Sampling
A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain
Supply and threshold voltage scaling for low power CMOS
A front-end processor for modems
A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter
A Pipelined ADC With Metastability Error Rate <10 -15 Errors/Sample
A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC
Energy control and accurate delay estimation in the design of CMOS buffers
Quad Full-HD Transform Engine for Dual-Standard Low-Power Video Coding
A 1.9-GHz Single-Chip CMOS PHS Cellphone
An Integrated Power Supply System for Low Power 3.3 V Electronics Using On-Chip Polymer Electrolyte Membrane (PEM) Fuel Cells
Security and performance optimization of a new DES data encryption chip
A 44-64-GHz mmWave Broadband Linear Doherty PA in Silicon With Quadrature Hybrid Combiner and Non-Foster Impedance Tuner
Design techniques for low-voltage high-speed digital bipolar circuits
A 0.7-V 0.6-µW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction
Single-Ended and Differential Ka-Band BiCMOS Phased Array Front-Ends
Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs
Error correction techniques for high-performance differential A/D converters
Fully Digital Transmit Equalizer With Dynamic Impedance Modulation