yusuke1997/dblp-id-title huggingface dataset:
Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications
Efficient Trace Signal Selection for Silicon Debug by Error Transmission Analysis
Generation of Functional Broadside Tests for Logic Blocks With Constrained Primary Input Sequences
Irredundant sequential machines via optimal logic synthesis
Highly Reliable Memory Architecture Using Adaptive Combination of Proactive Aging-Aware In-Field Self-Repair and ECC
Formal Modeling and Verification of Security Properties of a Ransomware-Resistant SSD
A modeling technique for CMOS gates
Exploiting In-Memory Data Patterns for Performance Improvement on Crossbar Resistive Memory
DTC: A Drift-Tolerant Coding to Improve the Performance and Energy Efficiency of -Level-Cell Phase-Change Memory
PROBE: A Placement, Routing, Back-End-of-Line Measurement Utility
The S-Algorithm: A Promising Solution for Systematic Functional Test Generation
Monitoring Aging Defects in STT-MRAMs
Optimizing Secure Deletion in Interlaced Magnetic Recording With Move-on-Cover Approach
GridNetOpt: Fast Full-Chip EM-Aware Power Grid Optimization Accelerated by Deep Neural Networks
Vector replacement to improve static-test compaction forsynchronous sequential circuits
Efficient Modeling Attack on Multiplexer PUFs via Kronecker Matrix Multiplication
Forward-Looking Reverse Order Fault Simulation for n -Detection Test Sets
Methodology for submicron device model development
Enhancing SRAM-Based PUF Reliability Through Machine Learning-Aided Calibration Techniques
Automatic Mapping of Heterogeneous DNN Models on Adaptive Multiaccelerator Systems
Closing the gap between analog and digital testing
Memristor-Based Edge Computing of ShuffleNetV2 for Image Classification
Minimal energy fixed-priority scheduling for variable voltage processors
Timing-Driven Placement Optimization Facilitated by Timing-Compatibility Flip-Flop Clustering
Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty
An efficient technique for exploring register file size in ASIP design
Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs
Fast evaluation of sequence pair in block placement by longestcommon subsequence computation
Hardware-Assisted Cross-Generation Prediction of GPUs Under Design
Near-Free Lifetime Extension for 3-D nand Flash via Opportunistic Self-Healing
Retiming edge-triggered circuits under general delay models
ESp: Placement by simulated evolution
On the multiple-fault testability of generalized counters
A parallel-in-time method for the transient simulation of SOI devices with drain current overshoots
Exponentially fitted discretization schemes for diffusion process simulation on coarse grids
Simulation of dry etch processes by COMPOSITE
A Scalable Test Structure for Multicore Chip
Design Framework to Overcome Aging Degradation of the 16 nm VLSI Technology Circuits
A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations
Silicon Modeling of Spiking Neurons With Diverse Dynamic Behaviors
Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies
Temperature-Aware DRAM Cache Management - Relaxing Thermal Constraints in 3-D Systems
Out-of-Order Parallel Discrete Event Simulation for Transaction Level Models
A new matrix solution technique for general circuit simulation
A Design Space Exploration Framework for Convolutional Neural Networks Implemented on Edge Devices
A test evaluation technique for VLSI circuits using register-transfer level fault modeling
A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations
Comment on "Event suppression by optimizing VHDL programs"
Escher-a geometrical layout system for recursively defined circuits
Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis
Task-Based Parallel Programming for Gate Sizing
High-level power modeling, estimation, and optimization
Toward Hardware-Based IP Vulnerability Detection and Post-Deployment Patching in Systems-on-Chip
Dynamic Power and Energy Management for NCFET-Based Processors
A behavioral model of a 1.8-V flash A/D converter based on deviceparameters
Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States
AccSiM: State-Aware Simulation Acceleration for Simulink Models
Optimal integer delay-budget assignment on directed acyclic graphs
Simulation of a MOS transistor with spatially nonuniform channel parameters
An integrated DFT solution for mixed-signal SOCs
ACHILLES: Accuracy-Aware High-Level Synthesis Considering Online Quality Management
Transistor sizing for low power CMOS circuits
An Ising Model-Based Parallel Tempering Processing Architecture for Combinatorial Optimization
Benchmarking of Machine Learning Methods for Multiscale Thermal Simulation of Integrated Circuits
Min-cut floorplacement
Downsizing Without Downgrading: Approximated Dynamic Time Warping on Nonvolatile Memories
Guest Editorial Circuit and System Design Automation for Internet of Things
An RLC interconnect model based on fourier analysis
Intelligent Voltage Ramp-Up Time Adaptation for Temperature Noise Reduction on Memory-Based PUF Systems
Exploiting Shared-Memory to Steer Scalability of Fault Simulation Using Multicore Systems
A performance-driven global router for custom VLSI chip design
Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents
A Compilation Framework for SRAM Computing-in-Memory Systems With Optimized Weight Mapping and Error Correction
SLOPES: Hardware-Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs
DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips
Switching well noise modeling and minimization strategy for digitalcircuits with a controllable threshold voltage scheme
Robust Wafer Classification With Imperfectly Labeled Data Based on Self-Boosting Co-Teaching
Versatile Task Assignment for Heterogeneous Soft Dual-Processor Platforms
PLA-based regular structures and their synthesis
Built-In Self-Repair Scheme for the TSVs in 3-D ICs
Subresolution Assist Feature Generation With Supervised Data Learning
Mitigating Slow-to-Write Errors in Memristor-Mapped Graph Neural Networks Induced by Adversarial Attacks
Optimizing pipelined networks of associative and commutative operators
SKOL: a system for logic synthesis and technology mapping
ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference
Parametric Fault Testing and Performance Characterization of Post-Bond Interposer Wires in 2.5-D ICs
Atleus: Accelerating Transformers on the Edge Enabled by 3D Heterogeneous Manycore Architectures
Enhanced Optimal Multi-Row Detailed Placement for Neighbor Diffusion Effect Mitigation in Sub-10 nm VLSI
Compact Modified Nodal Approach for Switched-Capacitor Network Analysis
Secure Run-Time Hardware Trojan Detection Using Lightweight Analytical Models
GCN-ABFT: Low-Cost Online Error Checking for Graph Convolutional Networks
Exploring Edge Computing for Multitier Industrial Control
A method of fault simulation based on stem regions
A High-Flexibility CAN-TSN Gateway With a Low-Congestion TSN-to-CAN Scheduler
On Coloring Rectangular and Diagonal Grid Graphs for Multipatterning and DSA Lithography
Circuit clustering using a stochastic flow injection method
Efficient Resubstitution-Based Approximate Logic Synthesis
Modeling and Simulating Electromagnetic Fault Injection
Primitive delay faults: identification, testing, and design for testability
Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill
An Approach to Placement-Coupled Logic Replication
An algorithm for determining repetitive patterns in very large IC layouts
Dynamically partitioned test scheduling with adaptive TAM configuration for power-constrained SoC testing
Simultaneous Technology Mapping and Placement for Delay Minimization
VLSI Yield Prediction and Estimation: A Unified Framework
Verifying RLC Power Grids With Transient Current Constraints
Analytical Placement Considering the Electron-Beam Fogging Effect
Harmonic-Balance Algorithms for the Circuit-Level Nonlinear Analysis of UWB Receivers in the Presence of Interfering Signals
A High-Level Approach for Energy Efficiency Improvement of FPGAs by Voltage Trimming
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level
SSD-Tailor: Automated Customization System for Solid-State Drives
Switch-level timing simulation of bipolar ECL circuits
Optimizing Sensor Deployment and Maintenance Costs for Large-Scale Environmental Monitoring
Verification of analytic point defect models using SUPREM-IV [dopant diffusion]
A Fast Semi-Analytic Approach for Combined Electromigration and Thermomigration Analysis for General Multisegment Interconnects
Segment-based etch algorithm and modeling
Analog Layout Generator for CMOS Circuits
Energy-Efficient Image Recognition System for Marine Life
PLS: a scheduler for pipeline synthesis
Transient analysis of dispersive VLSI interconnects terminated in nonlinear loads
An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits
eWASM: Practical Software Fault Isolation for Reliable Embedded Devices
Two new and 'more difficult' channel routing problems
A Parallel Simulation Technique for Multicore Embedded Systems and Its Performance Analysis
Two-Dimensional Simulation of Photolithography on Reflective Stepped Substrate
Provably Secure Camouflaging Strategy for IC Protection
ATOM: An Automatic Topology Synthesis Framework for Operational Amplifiers
An Efficient and Accurate Time Step Control Method for Power Device Transient Simulation Utilizing Dominant Time Constant Approximation
Computer-aided selection of components for technology-independent specifications
Efficient Cartesian Genetic Programming-Based Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits
High-Level Synthesis With Behavioral-Level Multicycle Path Analysis
FALPEM: Framework for Architectural-Level Power Estimation and Optimization for Large Memory Sub-Systems
Multimode Security-Aware Real-Time Scheduling on Multiprocessors
iNVMFS: An Efficient File System for NVRAM-Based Intermittent Computing Devices
CMOS circuit verification with symbolic switch-level timingsimulation
MTFS: Mixed Time-Frequency Method for the Steady-State Analysis of Almost-Periodic Nonlinear Circuits
Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure
Hierarchical topological sorting of apparent loops via partitioning
Making Deduction More Effective in SAT Solvers
Logic design verification via test generation
On-Chip Sample Preparation for Multiple Targets Using Digital Microfluidics
Time-Multiplexed Multiple-Constant Multiplication
Improving the computational efficiency of the tree relaxation method for an iterative solution of linear circuit equations
Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization
Stable Reduced Models for Nonlinear Descriptor Systems Through Piecewise-Linear Approximation and Projection
A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise
DSP-Efficient Hardware Acceleration of Convolutional Neural Network Inference on FPGAs
Domino logic synthesis based on implication graph
AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing
Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration
Multicore Parallelization of Min-Cost Flow for CAD Applications
An Analytical Dynamic Scaling of Supply Voltage and Body Bias Based on Parallelism-Aware Workload and Runtime Distribution
AutoFix: a hybrid tool for automatic logic rectification
Enhanced multipole acceleration technique for the solution of large Poisson computations
A Space-Time Neural Network for Analysis of Stress Evolution Under DC Current Stressing
An Edge 3D CNN Accelerator for Low-Power Activity Recognition
A Platform of Resynthesizing a Clock Architecture Into Power-and-Area Effective Clock Trees
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams
LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments
Combined word-length optimization and high-level synthesis ofdigital signal processing systems
RHPM: Using Relative Hotness to Guide Page Migration for Hybrid Memory Systems
Design of Sequential Load Modulation Balance Amplifier Using Multiobjective Particle Swarm Algorithm
Optimization of combinational logic circuits based on compatible gates
Automatic generation of parasitic constraints for performance-constrained physical design of analog circuits
Joint Optimization of Dimension Reduction and Mixed-Precision Quantization for Activation Compression of Neural Networks
Multi-Pair Active Shielding for Security IC Protection
The benefits of flexibility in lookup table-based FPGAs
Early evaluation for performance enhancement in phased logic
Cross-Domain Optimization of Low-Power Mixed-Signal Sensor Systems Under Classification Accuracy Constraints
Computational forensic techniques for intellectual property protection
ATPG for Delay Defects in Current Mode Threshold Logic Circuits
Multiple storage adaptive multi-trees
Thermal Aware Test Scheduling for NTV Circuit
A new approach to wiring layouts
'Defensive programming' in the rapid development of a parallel scientific program
On determining symmetries in inputs of logic circuits
On the over-specification problem in sequential ATPG algorithms
A row-based cell placement method that utilizes circuit structural properties
Symbolic two-level minimization
iTEM: a temperature-dependent electromigration reliability diagnosis tool
A module generator based on the PQ-tree algorithm
Reversible cascades with minimal garbage
Cyber-Physical Verification of Intermittently Powered Embedded Systems
Advanced Simulation of Quantum Computations
Circuit analysis and optimization driven by worst-case distances
Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings
High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints
Reliability-Driven Chip-Level Design for High-Frequency Digital Microfluidic Biochips
Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations
Erratum to "Time-Multiplexed-Network for Test Cost Reduction"
Dynamic Voltage Scaling for Multitasking Real-Time Systems With Uncertain Execution Time
UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-Placed Modules
MFS: A Brain-Inspired Memory Formation System for GAN
Effect of Gate Structure on the Performances of Lateral AlGaN/GaN High-Electron-Mobility Avalanche-Transit-Time Transistor
Fine-grained transaction-level verification: using a variable transactor for improved coverage at the signal level
A Multi-Site Test Solution for Quadrature Modulation RF Transceivers
Diagnosis-Assisted Adaptive Test
A CAD-Oriented Analytical MOSFET Model for High-Accuracy Applications
Stateful Neural Networks for Intermittent Systems
A priori wirelength and interconnect estimation based on circuit characteristic
Generating minimal covers of symmetric functions
Accurate X-Propagation for Test Applications by SAT-Based Reasoning
Graph-based output phase assignment for PLA minimization
Cocktail: Mixing Data With Different Characteristics to Reduce Read Reclaims for nand Flash Memory
mpsym: Improving Design-Space Exploration of Clustered Manycores With Arbitrary Topologies
Routing Region Definition and Ordering Scheme for Building-Block Layout
Efficient Comparison and Addition for FHE With Weighted Computational Complexity Model
Simulation of high-speed distributed interconnects using Krylov-space techniques
Metal--Metal Matrix (M 3 ) for High-Speed MOS VLSI Layout
Test Time Reduction in EDT Bandwidth Management for SoC Designs
Technology CAD for competitive products
Identifying invalid states for sequential circuit test generation
Finding a Maximum Planar Subset of a Set of Nets in a Channel
A Method to Detect Bit Flips in a Soft-Error Resilient TCAM
Slope propagation in static timing analysis
Efficient Model Switching in RRAM-Based DNN Accelerators
Efficient canonical form for Boolean matching of complex functions in large libraries
Dilution and Mixing Algorithms for Flow-Based Microfluidic Biochips
Circuit Topology-Aware Vaccination-Based Hardware Trojan Detection
FINDER: A CAD System-Based Electron Beam Tester for Fault Diagnosis of VLSI Circuits
Two-Layered Falsification of Hybrid Systems Guided by Monte Carlo Tree Search
Analysis of nonuniform, frequency-dependent high-speed interconnects using numerical inversion of Laplace transform
Integrated Test Module Design for Microfluidic Large-Scale Integration
CyberRL: Brain-Inspired Reinforcement Learning for Efficient Network Intrusion Detection
Efficient Interconnect Test Patterns for Crosstalk and Static Faults
On-Chip Droop-Induced Circuit Delay Prediction Based on Support-Vector Machines
Algorithms for Automatic Model Topology Formulation
MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD Tool
VLSI Layout Compaction with Grid and Mixed Constraints
Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm
Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences
ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification
Optimizing the Power-Delay Product of a Linear Pipeline by Opportunistic Time Borrowing
SpecCharts: a VHDL front-end for embedded systems
Application-independent testing of FPGA interconnects
MCXplore: Automating the Validation Process of DRAM Memory Controller Designs
An efficient solution scheme for the spherical-harmonics expansion of the Boltzmann transport equation [MOS transistors]
New approximations for the rectilinear Steiner arborescence problem [VLSI layout]
One-Pass Design of Reversible Circuits: Combining Embedding and Synthesis for Reversible Logic
Optimum clustering for delay minimization
High-level DSP synthesis using concurrent transformations, scheduling, and allocation
Offline Training-Based Mitigation of IR Drop for ReRAM-Based Deep Neural Network Accelerators
Echo State Networks for Black-Box Modeling of Integrated Circuits
EWA: efficient wiring-sizing algorithm for signal nets and clock nets
A Distributed Approach to Timing Verification of Synchronous and Asynchronous Digital Designs
Bug Prediction of SystemC Models Using Machine Learning
Optimizing Lifetime Capacity and Read Performance of Bit-Alterable 3-D NAND Flash
Path-Congestion-Aware Adaptive Routing With a Contention Prediction Scheme for Network-on-Chip Systems
Exploration and Customization of FPGA-Based Soft Processors
On Error Injection for NoC Platforms: A UVM-Based Generic Verification Environment
Glitter: A Gridless Variable-Width Channel Router
Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks
Finding Maximum Disjoint Set of Boundary Rectangles With Application to PCB Routing
Creating and exploiting flexibility in rectilinear Steiner trees
Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation
A 90-nm Low-Power FPGA for Battery-Powered Applications
Timing-Error-Tolerant Network-on-Chip Design Methodology
DefScan: Provably Defeating Scan Attack on AES-Like Ciphers
Improved universal MOSFET electron mobility degradation models for circuit simulation
A formal model of computer architectures for digital system design environments
Optimized Extraction of MOS Model Parameters
On the Security of Sequential Logic Locking Against Oracle-Guided Attacks
The Elmore delay as a bound for RC trees with generalized input signals
Average-case technology mapping of asynchronous burst-mode circuits
Search-Free Inference Acceleration for Sparse Convolutional Neural Networks
Recursive convolution and discrete time domain simulation of lossy coupled transmission lines
An Efficient Projector-Based Passivity Test for Descriptor Systems
A Novel Faster-Than-at-Speed Transition-Delay Test Method Considering IR-Drop Effects
A Persistent Fault-Based Collision Analysis Against the Advanced Encryption Standard
Matching-based methods for high-performance clock routing
Modeling and Experimental Measurement of Active Substrate-Noise Suppression in Mixed-Signal 0.18µm BiCMOS Technology
FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design
Timing analysis with crosstalk is a fixpoint on a complete lattice
An object-oriented approach to device simulation-FLOODS
Testing ASICs with multiple identical cores
Energy-Aware Design of Stochastic Applications With Statistical Deadline and Reliability Guarantees
High-Throughput CNN Inference on Embedded ARM Big.LITTLE Multicore Processors
A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates]
Myosotis: An Efficiently Pipelined and Parameterized Multiscalar Multiplication Architecture via Data Sharing
TD-Zero: Automatic Golden-Free Hardware Trojan Detection Using Zero-Shot Learning
Reduce Loss and Crosstalk in Integrated Silicon-Photonic Multistage Switching Fabrics Through Multichip Partition
SPADIX: A Highly Efficient Accelerator for Solving 3-D Partial Differential Equations
C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations
Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach
A Millimeter Wave Loss-Aware Methodology for Switchless PALNA Integrated Circuit Design
Synthesis of SPP three-level logic networks using affine spaces
Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design
Fast Communication Architecture Exploration of Processor Pool-Based MPSoC via Static Performance Analysis
Quadratic Approximations for the Isochrons of Oscillators: A General Theory, Advanced Numerical Methods, and Accurate Phase Computations
Energy Efficiency Enhancement of SCM-Based Systems: Write-Friendly Coding
Simulation of semiconductor devices using a Galerkin/spherical harmonic expansion approach to solving the coupled Poisson-Boltzmann system
Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits
High-Level Test Synthesis With Hierarchical Test Generation for Delay-Fault Testability
Nested Speculative Execution Attacks via Runahead
Numerically stable Green function for modeling and analysis of substrate coupling in integrated circuits
An Efficient and Accurate Variation-Aware Design Methodology for Near-Threshold MOS-Varactor-Based VCO Architectures
Temperature Gradient Exploration Method for Determining the Appropriate Number of Cells in Mesh-Based Thermal Analysis
Graph-theory-based simplex algorithm for VLSI layout spacingproblems with multiple variable constraints
An efficient volume-removal algorithm for practical three-dimensional lithography simulation with experimental verification
Multiple-Valued Minimization for PLA Optimization
Application of Load-Pull X-Parameters for GaN Device-Based Load Modulated Balanced Power Amplifier Design
Automated parameter extraction and modeling of the MOSFET below threshold
Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication
An Integrated Approach for Managing Read Disturbs in High-Density NAND Flash Memory
A Scanline Data Structure Processor for VLSI Geometry Checking
An improved optimal algorithm for bubble-sorting-basednon-Manhattan channel routing
An efficient algorithm for parametric fault simulation of monolithic IC's
Silicon Debug for Timing Errors
Synthesis of a CNTFET-Based Ternary Full Adder Using a Carry-Less Ternary Half Adder
Group LARS-Based Iterative Reweighted Least Squares Methodology for Efficient Statistical Modeling of Memory Designs
An Efficient GCNs Accelerator Using 3D-Stacked Processing-in-Memory Architectures
An exact algorithm for single-layer wire length minimization