yusuke1997/dblp-id-title huggingface dataset:
Calibration of phase and gain mismatches in Weaver image-reject receiver
A High Bandwidth Power Scalable Sub-Sampling 10-Bit Pipelined ADC With Embedded Sample and Hold
A 108-GHz InP-HBT monolithic push-push VCO with low phase noise and wide tuning bandwidth
A high-resolution multibit Sigma Delta ADC with digital correction and relaxed amplifier requirements
A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard
A 1-V 10.7-MHz switched-opamp bandpass ΣΔ modulator using double-sampling finite-gain-compensation technique
A study of digital and analog automatic-amplitude control circuitry for voltage-controlled oscillators
A 1024-Channel CMOS Microelectrode Array With 26, 400 Electrodes for Recording and Stimulation of Electrogenic Cells In Vitro
A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier
A 40 Mb/s soft-output Viterbi decoder
802.11g/n Compliant Fully Integrated Wake-Up Receiver With -72-dBm Sensitivity in 14-nm FinFET CMOS
An engineering model for short-channel MOS devices
25.2-Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter With Embedded Partial DBI: Improving I/O Bandwidth/pin and DBI Efficiencies
HNPU: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-Point and Active Bit-Precision Searching
An integrated pre-access architecture for CMOS SRAM
Space-variant nonorthogonal structure CMOS image sensor design
Introduction to the Special Section on the 2016 Radio Frequency Integrated Circuits (RFIC) Symposium
The implementation of digital echo cancellation in codecs
CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops
Large-Area, Fast-Gated Digital SiPM With Integrated TDC for Portable and Wearable Time-Domain NIRS
A 0.9-V 28-MHz Highly Digital CMOS Dual-RC Frequency Reference With ±200 ppm Inaccuracy From -40 °C to 85 °C
A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS
ISAAC: a symbolic simulator for analog integrated circuits
Correction to "A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication"
Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time
A 25-kft, 768-kb/s CMOS analog front end for multiple-bit-rate DSL transceiver
Design and Optimization of an HSDPA Turbo Decoder ASIC
Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise
A 150 K channelless gate array design in 0.5- mu m CMOS technology
Integrated All Electrical Pulse Wave Velocity and Respiration Sensors Using Bio-Impedance
0.3-4.3 GHz Frequency-Accurate Fractional-N Frequency Synthesizer With Integrated VCO and Nested Mixed-Radix Digital Δ-Σ Modulator-Based Divider Controller
A Sub-nW Multi-stage Temperature Compensated Timer for Ultra-Low-Power Sensor Nodes
Addition to "A Wideband 2.4-GHz Delta-Sigma Fractional-$N$PLL With 1-Mb/s In-Loop Modulation"
A noise-shifting differential Colpitts VCO
A low-power and high-performance CMOS fingerprint sensing and encoding architecture
A 1.8-V operation 5-GHz-band CMOS frequency doubler using current-reuse circuit design technique
A 670-GHz 4 × 2 Oscillator-Radiator Array Achieving 7.4-dBm EIRP in 40-nm CMOS
A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process
The Design of a CMOS Nanoelectrode Array With 4096 Current-Clamp/Voltage-Clamp Amplifiers for Intracellular Recording/Stimulation of Mammalian Neurons
A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800
RF CMOS comes of age
A 25 Ms/s 8-b-10 Ms/s 10-b CMOS data acquisition IC for digital storage oscilloscopes
A CMOS ultrasound range-finder microsystem
A CDMA InGaP/GaAs-HBT MMIC Power Amplifier Module Operating With a Low Reference Voltage of 2.4 V
A self-calibration method for fast high-resolution A/D and D/A converters
A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop
A 1.8 pJ/bit 16×16Gb/s Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration
A Sub-0.1°/h Bias-Instability Split-Mode MEMS Gyroscope With CMOS Readout Circuit
Guest Editorial 2017 IEEE Custom Integrated Circuits Conference
A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter With ±1.5% Frequency and ±3.6% Current-Sharing Error
Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss
A low-power 200-MHz receiver for wireless hearing aid devices
A Micropower Chopper-Stabilized Operational Amplifier Using a SC Notch Filter With Synchronous Integration Inside the Continuous-Time Signal Path
A 90-240 MHz Hysteretic Controlled DC-DC Buck Converter With Digital Phase Locked Loop Synchronization
A 28-nm RRAM/SRAM Collaborative CIM Accelerator Supporting RRAM-Endurance-Latency Awareness for Edge Fine-Tuning
Highly Efficient Terahertz Beam-Steerable Integrated Radiator Based on Tunable Boundary Conditions
Broadband Harmonic-Assisted Power and Efficiency Enhancement in a 174-232-GHz SiGe Voltage-Controlled Oscillator
A Wideband 400 MHz-to-4 GHz Direct RF-to-Digital Multimode ΔΣ Receiver
Improved sense-amplifier-based flip-flop: design and measurements
A filtering technique to lower LC oscillator phase noise
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling
A 36 V Programmable Instrumentation Amplifier With Sub-20µV Offset and a CMRR in Excess of 120 dB at All Gain Settings
A Self-Powered 50-Mb/s OOK Transmitter for Optoisolator LED Emulation
A 100-MHz 8-mW ROM-less quadrature direct digital frequency synthesizer
A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS
A 15-MHz Bandwidth 1-0 MASH Σ Δ ADC With Nonlinear Memory Error Calibration Achieving 85-dBc SFDR
A 1-V 175- $\mu$ W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques
Josephson pseudorandom bit-sequence generator
Evaluation of two-summand adders implemented in ECDL CMOS differential logic
A 6 Gb/s Transceiver With a Nonlinear Electronic Dispersion Compensator for Directly Modulated Distributed-Feedback Lasers
A 41.3/26.7 pJ per Neuron Weight RBM Processor Supporting On-Chip Learning/Inference for IoT Applications
A Fractional-N Sampling PLL With a Merged Constant-Slope DTC and Sampling PD
An integrated LMS adaptive filter of TX leakage for CDMA receiver front ends
A 9-31-GHz Subharmonic Passive Mixer in 90-nm CMOS Technology
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS
A ±36-A Integrated Current-Sensing System With a 0.3% Gain Error and a 400-µA Offset From -55 °C to +85 °C
A 5-GHz 20-dBm Power Amplifier With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process
40-43-Gb/s OC-768 16: 1 MUX/CMU chipset with SFI-5 compliance
A simple nonsaturated CMOS multivibrator
A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory
A 5-MHz 11-Bit Self-Oscillating Sigma Delta Modulator With a Delay-Based Phase Shifter in 0.025 mm 2
A mixed-signal 0.18-μm CMOS SoC for DVD systems with 432-MSample/s PRML read channel and 16-Mb embedded DRAM
A 65-nm CMOS Temperature-Compensated Mobility-Based Frequency Reference for Wireless Sensor Networks
A capacitive threshold-logic gate
Scalable Inter-Core-Shaping Multi-Core Oscillator With Canceled Common-Mode Destructive Coupling and Robust Common-Mode Resonance
A 1024-Channel 268-nW/Pixel 36×36 μm 2 /Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces
A Wideband Digital-Intensive Current-Mode Transmitter Line-Up
A 7.3-μ W 13-ENOB 98-dB SFDR Noise-Shaping SAR ADC With Duty-Cycled Amplifier and Mismatch Error Shaping
Highly Efficient Differential Frequency Doubler With Output Resistance Boosting Feedback
A 1.95-V, 0.34-mW, 12-b sigma-delta modulator stabilized by local feedback loops
Baseband and audio mixed-signal front-end IC for GSM/EDGE applications
A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS
Design considerations for soft embedded programmable logic cores
A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory
A Low-Jitter Fractional- N Digital PLL With Spur Cancellation Based on a Multi-DTC Topology
Boolean decomposition in multilevel logic optimization
Design, Modeling, and Test of a Programmable Adaptive Phase-Shifting PLL for Enhancing Clock Data Compensation
A 54*54-b regularly structured tree multiplier
A high-efficiency CMOS +22-dBm linear power amplifier
An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects
A Fully Integrated 7.3 kV HBM ESD-Protected Transformer-Based 4.5-6 GHz CMOS LNA
A 116-Gb/s PAM4 0.9-pJ/b Transmitter With Eight-Tap FFE in 5-nm FinFET
A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS
0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation
An SRAM design using dual threshold voltage transistors and low-power quenchers
A Fractional- PLL for Multiband (0.8-6 GHz) Communications Using Binary-Weighted D/A Differentiator and Offset-Frequency Δ-Σ Modulator
A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension
SiGe W-CDMA transmitter for mobile terminal application
A Compact 10-MHz RC Frequency Reference With a Versatile Temperature Compensation Scheme
A theoretical design basis for minimizing CMOS fixed taper buffer area
A 62 mV 0.13 µ m CMOS Standard-Cell-Based Design Technique Using Schmitt-Trigger Logic
A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization
A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC
A 16 nm 128 Mb SRAM in High-κ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications
A Dual-Mode Continuously Scalable-Conversion-Ratio SC Energy Harvesting Interface With SC-Based PFM MPPT and Flying Capacitor Sharing Scheme
High-speed CMOS wavefront sensor with resistive-ring networks of winner-take-all circuits
MIMO Switched-Capacitor DC-DC Converters Using Only Parasitic Capacitances Through Scalable Parasitic Charge Redistribution
A 2-mW 70.7-dB SNDR 200-MS/s Pipelined-SAR ADC Using Continuous-Time SAR-Assisted Detect-and-Skip and Open-Then-Close Correlated Level Shifting
A 4-Phase 30-70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator
A 9-b charge-to-digital converter for integrated image sensors
A 113.3-dB Dynamic Range 600 Frames/s SPAD X-Ray Detector With Seamless Global Shutter and Time-Encoded Extrapolation Counter
High-frequency analysis of linearity improvement technique of common-emitter transconductance stage using a low-frequency-trap network
A 2✖ Time-Interleaved 28-GS/s 8-Bit 0.03-mm 2 Switched-Capacitor DAC in 16-nm FinFET CMOS
Efficient Power Management Circuit: From Thermal Energy Harvesting to Above-IC Microbattery Energy Storage
A low-jitter mutual-correlated pulsewidth control loop circuit
A 3.3-V/5-V low power TTL-to-CMOS input buffer
A rail-to-rail constant-g m low-voltage CMOS operational transconductance amplifier
A 0.4-V 0.93-nW/kHz Relaxation Oscillator Exploiting Comparator Temperature-Dependent Delay to Achieve 94-ppm/°C Stability
A 100 MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline (CCB) Cell
Enhanced peaking current reference
A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers
AAD-KWS: A Sub-μ W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS
A 100-MHz, 50-Ω, -45-dB distortion, 3.3-V CMOS line driver for Ethernet and fast Ethernet networking applications
A Bits-to-Antenna F-Band 120-Gb/s CMOS RF-64QAM Transmitter for FutureG Wireless Links
A testable CMOS asynchronous counter
Introduction to the Special Issue on the IEEE 2004 Custom Integrated Circuits Conference
Analog AGC Circuitry for a CMOS WLAN Receiver
H-Band Power Amplifiers in 65-nm CMOS by Adopting Output Power Maximized G max -Core and Transmission Line-Based Zero-Degree Power Combining Networks
Voltage-controlled oscillators up to 98 GHz in SiGe bipolar technology
A 0.5-8.5 GHz fully differential CMOS distributed amplifier
A 70 dB MTPR Integrated Programmable Gain/Bandwidth Fourth-Order Chebyshev High-Pass Filter for ADSL/VDSL Receivers in 65 nm CMOS
A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects
A 1 V 1.07 μW 15-Bit Pseudo-Pseudo-Differential Incremental Zoom ADC
Resonant Regulating Rectifiers (3R) Operating for 6.78 MHz Resonant Wireless Power Transfer (RWPT)
Design of a scalable pipelined RAM system
An RF-Ultrasound Relay for Adaptive Wireless Powering Across Tissue Interfaces
Efficient Digital Quadrature Transmitter Based on IQ Cell Sharing
A 50.1-Mpixel 14-Bit 250-frames/s Back-Illuminated Stacked CMOS Image Sensor With Column-Parallel kT/C-Canceling S&H and ΔΣADC
Compact Low-Power Impedance-to-Digital Converter for Sensor Array Microsystems
A resistance-variation-tolerant constant-power heating circuit for integrated sensor applications
Coplanar millimeter-wave ICs for W-band applications using 0.15 μm pseudomorphic MODFETs
Over-30-GHz limiting amplifier ICs with small phase deviation for optical communication systems
Correction to "An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation"
A Packaged 54-to-69-GHz Wideband 2T2R FMCW Radar Transceiver Employing Cascaded-PLL Topology and PTAT-Enhanced Temperature Compensation in 40-nm CMOS
On the phase-noise and phase-error performances of multiphase LC CMOS VCOs
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration
Design Considerations for 60 GHz Transformer-Coupled CMOS Power Amplifiers
Memory design using a one-transistor gain cell on SOI
A low-phase-noise reference oscillator with integrated pMOS varactors for digital satellite receivers
A 120.9-dB DR Digital-Input Capacitively Coupled Chopper Class-D Audio Amplifier
A 0.3-1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller
Linearized Darlington Cascode Amplifier Employing GaAs PHEMT and GaN HEMT Technologies
A 24 GHz Self-Calibrated All-Digital FMCW Synthesizer With 0.01% RMS Frequency Error Under 3.2 GHz Chirp Bandwidth and 320 MHz/µs Chirp Slope
A 950-MHz IF second-order integrated LC bandpass delta-sigma modulator
A 0.8-V 230-µW 98-dB DR Inverter-Based ΣΔ Modulator for Audio Applications
A scalable pipelined architecture for fast buffer SRAMs
A 1.22 TOPS and 1.52 mW/MHz Augmented Reality Multicore Processor With Neural Network NoC for HMD Applications
A 12-/13.56-MHz Crystal Oscillator With Binary-Search-Assisted Two-Step Injection Achieving 5.0-nJ Startup Energy and 45.8-μs Startup Time
A 2.7-V 1.8-GHz fourth-order tunable LC bandpass filter based on emulation of magnetically coupled resonators
A Single-Stage Dual-Output Regulating Voltage Doubler for Wireless Power Transfer
A nonredundant-radix-4 serial multiplier
Single-pole double-throw CMOS switches for 900-MHz and 2.4-GHz applications on p - silicon substrates
Cell-based fully integrated CMOS frequency synthesizers
An Ultra-Low-Voltage Bias-Current-Free Fractional-N Hybrid PLL With Voltage-Mode Phase Detection and Interpolation
A 16 MHz BW 75 dB DR CT ΔΣ ADC Compensated for More Than One Cycle Excess Loop Delay
The effect of dielectric relaxation on charge-redistribution A/D converters
Match Sensing Using Match-Line Stability in Content-Addressable Memories (CAM)
A 50-MHz 8-Mbit video RAM with a column direction drive sense amplifier
A Low Voltage SRAM Using Resonant Supply Boosting
A single-chip 12.7 Mchips/s digital IF BPSK direct sequence spread-spectrum transceiver in 1.2 μm CMOS
Comments on "On unilateral dual feedback low-noise amplifier with simultaneous noise, impedance, and IIP3 Match"
Design for testability of embedded integrated operational amplifiers
A current memory cell with switch feedthrough reduction by error feedback
A mixed-signal decision-feedback equalizer that uses a look-ahead architecture
A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- G m Bias
A 0.4-V G m -C Proportional-Integrator-Based Continuous-Time ΔΣ Modulator With 50-kHz BW and 74.4-dB SNDR
Analysis and Design of Continuous-Time Delta-Sigma Converters Incorporating Chopping
An 802.11g WLAN SoC
A Wireless Somatosensory Feedback System Using Human Body Communication
An adaptive line equalizer VLSI using digital signal processing
A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's
A 130 nm CMOS 6-bit Full Nyquist 3 GS/s DAC
A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber
Cosmic ray soft error rates of 16-Mb DRAM memory chips
Arbitrary Analog/RF Spatial Filtering for Digital MIMO Receiver Arrays
Advanced controlling scheme for a DRAM voltage generator system
A 106 dB A-Weighted DR Low-Power Continuous-Time ΣΔ Modulator for MEMS Microphones
A 15-b pipelined CMOS floating-point A/D converter
A low-power reconfigurable analog-to-digital converter
An Energy-Efficient ECG Processor in 45-nm CMOS Using Statistical Error Compensation
A 26.9 K 314.5 Mb/s Soft (32400, 32208) BCH Decoder Chip for DVB-S2 System
A single-chip 802.11a MAC/PHY with a 32-b RISC processor
A Robust BBPLL-Based 0.18- $\mu$ m CMOS Resistive Sensor Interface With High Drift Resilience Over a -40 °C-175 °C Temperature Range
An 8-bit 20-MS/s CMOS A/D converter with 50-mW power consumption
Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver
Characterization and improvement of GaAs HEMT analog switches for sampled-data applications
Performance predictions of scaled BiCMOS gates using physical simulation
A 141-dB Dynamic Range CMOS Gas-Sensor Interface Circuit Without Calibration With 16-Bit Digital Output Word
Monolithic Capacitive DC-DC Converter With Single Boundary-Multiphase Control and Voltage Domain Stacking in 90 nm CMOS
ASCH-PUF: A "Zero" Bit Error Rate CMOS Physically Unclonable Function With Dual-Mode Low-Cost Stabilization
Low Power Design Techniques for Single-Bit Audio Continuous-Time Delta Sigma ADCs Using FIR Feedback
A CMOS Readout Circuit for SOI Resonant Accelerometer With 4-µg Bias Stability and 20-µg/√Hz Resolution
3-5 GHz 4-Channel UWB Beamforming Transmitter With 1° Scanning Resolution Through Calibrated Vernier Delay Line in 0.13-µm CMOS
A source sensing technique applied to SRAM cells
Precise delay generation using coupled oscillators
A Bluetooth radio in 0.18-μm CMOS
A High Dynamic-Range Neural Recording Chopper Amplifier for Simultaneous Neural Recording and Stimulation
A 0.6-V High-Efficiency BLE Transmitter Using a Hybrid PLL With RDAC-Based Common-Mode Ripple Cancellation in 65-nm CMOS
A pipelined temporal difference imager
Broadband Millimeter-Wave LNAs (47-77 GHz and 70-140 GHz) Using a T-Type Matching Topology
Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System
Active Feedback Technique for RF Channel Selection in Front-End Receivers
Simulation and measurement of supply and substrate noise in mixed-signal ICs
A Monolithically Integrated DWDM Si-Photonics Transceiver for Chiplet Optical I/O
Analysis of reliability and power efficiency in cascode class-E PAs
A 13-b 1.1-MHz oversampled DAC with semidigital reconstruction filtering
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
An EEPROM Programming Controller for Passive UHF RFID Transponders With Gated Clock Regulation Loop and Current Surge Control
Wideband Rapid Interferer Detector Exploiting Compressed Sampling With a Quadrature Analog-to-Information Converter
A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters
Generalized Linear Periodic Time-Varying Analysis for Noise Reduction in an Active Mixer
Circuit implementations of the differential capacitance read scheme (DCRS) for ferroelectric random-access memories (FeRAM)
A Monolithically Integrated Single-Input Load-Modulated Balanced Amplifier With Enhanced Efficiency at Power Back-Off
A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration
A Time-Interleaved Digital-to-Analog Converter up to 118 GS/s With Integrated Analog Multiplexer in 28-nm FD-SOI CMOS Technology
Energy Recycling Telemetry IC With Simultaneous 11.5 mW Power and 6.78 Mb/s Backward Data Delivery Over a Single 13.56 MHz Inductive Link
Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp
A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques
Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips
A low-power precomputation-based fully parallel content-addressable memory
A 10-b 20-Msample/s analog-to-digital converter
A 3.1-μW Analog-Assisted Zoom Histogramming TDC in 35-μm Pixel Pitch for Flash LiDAR Sensor
An efficient redundant-binary number to binary number converter
A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS
Opamp-Less Sub-μW/Channel Δ-Modulated Neural-ADC With Super-GΩ Input Impedance
A 40-nm 131-mW 6.4-Gb/s 256 × 32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems
A 2.2-mW CMOS bandpass continuous-time multibit Δ-Σ ADC with 68 dB of dynamic range and 1-MHz bandwidth for wireless applications
A CMOS Two-Element 170-GHz Fundamental-Frequency Transmitter With Direct RF-8PSK Modulation
Power-Combining Transformer Techniques for Fully-Integrated CMOS Power Amplifiers
A 334 μW 0.158 mm 2 ASIC for Post-Quantum Key-Encapsulation Mechanism Saber With Low-Latency Striding Toom-Cook Multiplication
480-GMACS/mW Resonant Adiabatic Mixed-Signal Processor Array for Charge-Based Pattern Recognition
An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's
A Fully Passive Compressive Sensing SAR ADC for Low-Power Wireless Sensors
An Energy-Efficient Precision-Scalable ConvNet Processor in 40-nm CMOS
A Wide-Range Variation-Resilient Physically Unclonable Function in 28 nm
High-Efficiency SiGe-BiCMOS $E$ -Band Power Amplifiers Exploiting Current Clamping in the Common-Base Stage
A 1500 fps Highly Sensitive 256 , ˟, 256 CMOS Imaging Sensor With In-Pixel Calibration
Monolithic magnetic Hall sensor using dynamic quadrature offset cancellation
A low-power low-noise accurate linear-in-dB variable-gain amplifier with 500-MHz bandwidth
A Wideband Injection Locked Quadrature Clock Generation and Distribution Technique for an Energy-Proportional 16-32 Gb/s Optical Receiver in 28 nm FDSOI CMOS
A 79-GHz 2 × 2 MIMO PMCW Radar SoC in 28-nm CMOS
A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-μm digital CMOS process
A merged CMOS LNA and mixer for a WCDMA receiver
A Highly Linear and Efficient 28-GHz PA With a P sat of 23.2 dBm, P 1 dB of 22.7 dBm, and PAE of 35.5% in 65-nm Bulk CMOS
A CMOS TV tuner/demodulator IC with digital image rejection
Design techniques for a low-power low-cost CMOS A/D converter
A low-power 5-70-MHz seventh-order log-domain filter with programmable boost, group delay, and gain for hard disk drive applications
A 1-pJ/bit 80-Gb/s $2^{15}-1$ PRBS Generator With a Modified Cherry-Hooper Output Driver
Design and characterization of a CMOS 3-D image sensor based on single photon avalanche diodes
An adaptive biasing one-stage CMOS operational amplifier for driving high capacitive loads
A 700+-mW class D design with direct battery hookup in a 90-nm process
A Millimeter-Wave CMOS Series-Doherty Power Amplifier With Post-Silicon Inter-Stage Passive Validation