yusuke1997/dblp-id-title huggingface dataset:
Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays
Self-Controlled High-Performance Precharge-Free Content-Addressable Memory
Configuration relocation and defragmentation for run-time reconfigurable computing
A Power-Proportional, Dual-Bandwidth, and Constant-Delay Receiver Front-End for Energy-Efficient Dual-Rate Optical Links
Low-Power Test Generation by Merging of Functional Broadside Test Cubes
A Quad-Core VCO Incorporating Area-Saving Folded S-Shaped Tail Filtering in 28-nm CMOS
Layout of Decoupling Capacitors in IP Blocks for 90-nm CMOS
Exploiting Memristors for Compressive Sampling of Sensory Signals
A Unified Write Buffer Cache Management Scheme for Flash Memory
Throughput Optimization for Area-Constrained Links With Crosstalk Avoidance Methods
EddySuperblock: Improving NAND Flash Efficiency and Lifetime by Endurance-Driven Dynamic Superblock Management
A Switched-Based Slew Rate and Gain Boosting Parallel-Path Amplifier for Switched-Capacitor Applications
Testability analysis and behavioral testing of the Hopfield neural paradigm
Low-Noise Distributed RC Oscillator
DSP-Driven Self-Tuning of RF Circuits for Process-Induced Performance Variability
Improved Accuracy Pseudo-Exponential Function Generator With Applications in Analog Signal Processing
A Residue-to-Binary Converter for the Extended Four-Moduli Set {2 n -1, 2 n +1, 2 2n +1, 2 2n+p }
A Low-Power Multiplier With the Spurious Power Suppression Technique
Second Quarter of the 2021 Editorial Year - A Year in Crescendo
Satisfiability Models for Maximum Transition Power
A Receiver Front-End for VCSEL-Based Optical Links With 49 UI Turn-On Time
Partitioning sequential circuits for pseudoexhaustive testing
Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations
GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic Locking
A Laddered-Inverter Nonoverlapping Clock Generator
DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays
Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits
Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET
Architecture and design of NX-2700: a programmable single-chip HDTV all-format-decode-and-display processor
A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy
A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique
A practical approach to model long MIS interconnects in VLSI circuits
Wire Topology Optimization for Low Power CMOS
High-performance energy-efficient D-flip-flop circuits
A 14-bit 6.7 MS/s 0.018 mm 2 98 μW SAR A/D Converter With On-the-Fly Autocalibration for Array Applications
Exploiting the on-chip inductance in high-speed clock distribution networks
A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz
Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders
Hidden Costs of Analog Deobfuscation Attacks
FANNS: An FPGA-Based Approximate Nearest-Neighbor Search Accelerator
Editorial on the Opening of the New Editorial Year - The State of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asynchronous Data-Driven Circuit Synthesis
Temperature-Aware Dynamic Voltage Scaling to Improve Energy Efficiency of Near-Threshold Computing
High-Level Modeling of Analog Computational Elements for Signal Processing Applications
A Parallel Pruned Bit-Reversal Interleaver
An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling
L1-L2 Interconnect Design Methodology and Arbitration in 3-D IC Multicore Compute Clusters
A 4-kB 500-MHz 4-T CMOS SRAM using low-V THN bitline drivers and high-V THP latches
Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation
TAONoC: A Regular Passive Optical Network-on-Chip Architecture Based on Comb Switches
BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning
A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling
Improved Accuracy Current-Mode Multiplier Circuits With Applications in Analog Signal Processing
Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback
RISC-V CPU Design Using RRAM-CMOS Standard Cells
A Routing-Aware ILS Design Technique
Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor
Design-for-testability for embedded delay-locked loops
VLSI Design of a High-Performance Multicontext MQ Arithmetic Coder
Narrow bus encoding for low-power DSP systems
Information Leakage Through Physical Layer Supply Voltage Coupling Vulnerability
Novel Feature Selection Algorithm for Thermal Prediction Model
A High-Performance Low-Power Double-Node Upset Resilient Latch for Harsh Radiation Environments
A Study on Bandgap Reference Circuit With Leakage-Based PTAT Generation
CPA Secured Data-Dependent Delay-Assignment Methodology
Robust Bioinspired Architecture for Optical-Flow Computation
Low-Complexity Compressed-Sensing-Based Watermark Cryptosystem and Circuits Implementation for Wireless Sensor Networks
Power-Efficient Workload Balancing for Video Applications
Technique for Efficient Evaluation of SRAM Timing Failure
Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics
Current-Comparison-Based Domino: New Low-Leakage High-Speed Domino Circuit for Wide Fan-In Gates
A High-Density eDRAM Macro With Programmable Sense Amplifier and TG-Shifter for Logical-Instruction-Based In-Memory Computing
Knowledge-Based Neural Network Model for FPGA Logical Architecture Development
A 0.1-2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS
RA-Aware Fail Data Collection Architecture for Cost Reduction
On the effect of floorplanning on the yield of large area integrated circuits
In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays
Analytical Soft Error Models Accounting for Die-to-Die and Within-Die Variations in Sub-Threshold SRAM Cells
Circuit and microarchitectural techniques for reducing cache leakage power
A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC
General Parameterized Thermal Modeling for High-Performance Microprocessor Design
An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing
System-on-chip test scheduling with reconfigurable core wrappers
Analysis and Modeling of Energy Consumption in RLC Tree Circuits
0.6-2.7-Gb/s Referenceless Parallel CDR With a Stochastic Dispersion-Tolerant Frequency Acquisition Technique
Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design
RC4-AccSuite: A Hardware Acceleration Suite for RC4-Like Stream Ciphers
A low-power high-performance current-mode multiport SRAM
Design of Approximate Booth Squarer for Error-Tolerant Computing
Reducing Measurement Uncertainty in a DSP-Based Mixed-Signal Test Environment Without Increasing Test Time
Hybrid LUT/Multiplexer FPGA Logic Architectures
REC-STA: Reconfigurable and Efficient Chip Design With SMO-Based Training Accelerator
EmGen-a module generator for logic emulation applications
Using Lifetime-Aware Progressive Programming to Improve SLC NAND Flash Memory Write Endurance
A multicarrier QAM modulator for WCDMA base-station with on-chip D/A converter
A Fully Passive Noise-Shaping SAR ADC Utilizing Last-Bit Majority Voting and Cyclic Dynamic Element Matching Techniques
A Processor and Cache Online Self-Testing Methodology for OS-Managed Platform
Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets
High-Resolution All-Digital Transmit Beamformer for High-Frequency and Wearable Ultrasound Imaging Systems
A Thermal Energy Harvesting Power Supply With an Internal Startup Circuit for Pacemakers
Performance analysis of low-power 1-bit CMOS full adder cells
Self-Optimizing and Self-Programming Computing Systems: A Combined Compiler, Complex Networks, and Machine Learning Approach
Novel sorting network-based architectures for rank order filters
Placement and routing tools for the Triptych FPGA
Recursive Synaptic Bit Reuse: An Efficient Way to Increase Memory Capacity in Associative Memory
Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues and Eigenvectors Using CORDIC-Based Parallel Jacobi Method
HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization
Architectural strategies for low-power VLSI turbo decoders
Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform
Task Allocation on Nonvolatile-Memory-Based Hybrid Main Memory
Efficient realizations of encoders and decoders based on the 2-D discrete wavelet transform
Certified timing verification and the transition delay of a logic circuit
On the measurement of crosstalk in integrated circuits
In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations
A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta-Sigma Modulator in 0.18-µm CMOS
A Bit-Serial Pipelined Architecture for High-Performance DHT Computation in Quantum-Dot Cellular Automata
Timing Jitter and Power Spectral Density of Random Walk Noise in VCO
The simulation automation system (SAS); concepts, implementation, and results
A coding framework for low-power address and data busses
Re-Pen: Reinforcement Learning-Enforced Penetration Testing for SoC Security Verification
A Study of Tapered 3-D TSVs for Power and Thermal Integrity
An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection
Performance and Accuracy Tradeoffs for Training Graph Neural Networks on ReRAM-Based Architectures
Dynamic and Leakage Energy Minimization With Soft Real-Time Loop Scheduling and Voltage Assignment
X-Rel: Energy-Efficient and Low-Overhead Approximate Reliability Framework for Error-Tolerant Applications Deployed in Critical Systems
A Fast and Low-Complexity Operator for the Computation of the Arctangent of a Complex Number
Further Exploring the Strength of Prediction in the Factorization of Soft-Decision Reed-Solomon Decoding
A Dynamic Longest Prefix Matching Content Addressable Memory for IP Routing
A 1-Gb/s 6-10-GHz, Filterless, Pulsed UWB Transmitter With Symmetrical Waveform Analysis and Generation
A 57-to-64-GHz 0.094-mm 2 5-bit Passive Phase Shifter in 65-nm CMOS
Synthesis of custom interleaved memory systems
Nine-coded compression technique for testing embedded cores in SoCs
Timing constraints for high-speed counterflow-clocked pipelining
A Hardware and Software Co-Design for Energy-Efficient Neural Network Accelerator With Multiplication-Less Folded-Accumulative PE for Radar-Based Hand Gesture Recognition
A Novel Printed-Lookup-Table-Based Programmable Printed Digital Circuit
FPGA Implementation of Sparsity Adaptive Atomic Correlation Difference Pursuit Algorithm for Compressed Sensing
Independently Reconfigurable Multiband All-Digital Transmitter Using SMASH Delta-Sigma Modulation
SAADI-EC: A Quality-Configurable Approximate Divider for Energy Efficiency
ReLOPE: Resistive RAM-Based Linear First-Order Partial Differential Equation Solver
A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages
A 0.4-V Startup, Dead-Zone-Free, Monolithic Four-Mode Synchronous Buck-Boost Converter
Static energy reduction techniques for microprocessor caches
Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits
Board-level multiterminal net assignment for the partial cross-bar architecture
A Half-Select Disturb-Free 11T SRAM Cell With Built-In Write/Read-Assist Scheme for Ultralow-Voltage Operations
An Unconditional Evenly Spaced STRO With a New Mitigated Drafting Effect Muller C-Element
Efficient Data Placement for Improving Data Access Performance on Domain-Wall Memory
Autogeneration of Pipelined Belief Propagation Polar Decoders
Wrapper design for multifrequency IP cores
On circuit techniques to improve noise immunity of CMOS dynamic logic
Examining Timing Path Robustness Under Wide-Bandwidth Power Supply Noise Through Multi-Functional-Cycle Delay Test
Low Power Design of Precomputation-Based Content-Addressable Memory
An FPGA-Based Hardware Accelerator for Traffic Sign Detection
Approximate Error Detection With Stochastic Checkers
Fast Interconnect and Gate Timing Analysis for Performance Optimization
Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns
Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection
Embryonics: a new methodology for designing field-programmable gate arrays with self-repair and self-replicating properties
A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps
A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS
A 3.2-GHz 178-fs rms Jitter Subsampling PLL/DLL-Based Injection-Locked Clock Multiplier
Test-Quality Optimization for Variable $n$ -Detections of Transition Faults
Intrinsic MOSFET parameter fluctuations due to random dopant placement
Analysis and comparison on full adder block in submicron technology
Boosting NVDIMM Performance With a Lightweight Caching Algorithm
An IP Core Mapping Algorithm Based on Neural Networks
Variable voltage task scheduling algorithms for minimizing energy/power
Efficient Fault-Detection Architectures for Barrett Reduction and Multiplication in Classical and Post-Quantum Cryptographic Systems
Practical Asynchronous Interconnect Network Design
An FIR processor with programmable dynamic data ranges
Efficient Memory Repair Using Cache-Based Redundancy
Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application
A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing
An 8-bit 1.5-GS/s Two-Step SAR ADC With Embedded Interstage Gain
R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction
A Novel TriNet Architecture for Enhanced Analog IC Design Automation
Partitioning and pipelining for performance-constrained hardware/software systems
STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique
Multiplierless MP-Kernel Machine for Energy-Efficient Edge Devices
A 1-16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator
Analysis of Security of Split Manufacturing Using Machine Learning
A Multi-Agent Framework for Thermal Aware Task Migration in Many-Core Systems
Test Generation in Systolic Architecture for Multiplication Over GF(2 m )
Efficient Critical Path Identification Based on Viability Analysis Method Considering Process Variations
Switching activity estimation of VLSI circuits using Bayesian networks
Variability in Multistage Synchronizers
A Current-Recycling Technique for Shadow-Match-Line Sensing in Content-Addressable Memories
Electrical Model of Microcontrollers for the Prediction of Electromagnetic Emissions
An STM-16 Frame Termination VLSI With 2.5-Gb/s/Pin Input/Output Buffers: High-Speed and Low-Power Multi-𝕍 DD CMOS/SIMOX Techniques
Uni-OPU: An FPGA-Based Uniform Accelerator for Convolutional and Transposed Convolutional Networks
A High-Accuracy Programmable Pulse Generator With a 10-ps Timing Resolution
Partitioning Methods for Interface Circuit of Heterogeneous 3-D-ICs Under Process Variation
Securing a Wireless Network-on-Chip Against Jamming-Based Denial-of-Service and Eavesdropping Attacks
A 3D Unified Analysis Method (3D-UAM) for Wafer-on-Wafer Stacked Near-Memory Structure
Vertically integrated SOI circuits for low-power and high-performance applications
Design and Analysis of Two Low-Power SRAM Cell Structures
Reliability Modeling and Management of Nanophotonic On-Chip Networks
Architectural Exploration for Waferscale Switching System
2.4-GHz High-Efficiency Adaptive Power
Symbolic NFA scheduling of a RISC microprocessor
Analysis and Reduction of Supply Noise Fluctuations Induced by Embedded Via-Programming ROM
Generation of Customized Accelerators for Loop Pipelining of Binary Instruction Traces
High-performance and low-power conditional discharge flip-flop
The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage
Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs
A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability
PUF-Based Secure Chaotic Random Number Generator Design Methodology
Highly Defect Detectable and SEU-Resilient Robust Scan-Test-Aware Latch Design
Decoding the Golden Code: A VLSI Design
Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs
Energy-Efficient Wide-Range Level Shifter With a Logic Error Detection Circuit
Make Shuffling Great Again: A Side-Channel-Resistant Fisher-Yates Algorithm for Protecting Neural Networks
Layout-driven memory synthesis for embedded systems-on-chip
RandShift: An Energy-Efficient Fault-Tolerant Method in Secure Nonvolatile Main Memory
Delay Test for Diagnosis of Power Switches
Cascaded Bayesian inferencing for switching activity estimation with correlated inputs
Single-Port SRAM-Based Transpose Memory With Diagonal Data Mapping for Large Size 2-D DCT/IDCT
A Low-Power High-Performance H.264/AVC Intra-Frame Encoder for 1080pHD Video
Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid
Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits
Efficient algorithms for multilevel power estimation of VLSI circuits
Error-Resilient Motion Estimation Architecture
Golden-Free Hardware Trojan Detection Using Self-Referencing
An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers
A 230-MHz half-bit level pipelined multiplier using true single-phase clocking
RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device
Evaluating layout area tradeoffs for high level applications
Using the Minimum Set of Input Combinations to Minimize the Area of Local Routing Networks in Logic Clusters Containing Logically Equivalent I/Os in FPGAs
A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture
Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier
Functional Test Sequences as a Source for Partially Functional Launch-on-Shift Tests
Noise Analysis and Design Methodology of Chopper Amplifiers With Analog DC-Servo Loop for Biopotential Acquisition Applications
A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application
A Bit-Time-Dependent Model of I/O Drivers for Overclocking Analysis
Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors
Modular Active Charge Balancing for Scalable Battery Packs
Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution
A buffer distribution algorithm for high-performance clock net optimization
Synchronous and asynchronous A-D conversion
A 0.1-9-GHz Frequency Synthesizer for Avionic SDR Applications in 0.13-μm CMOS Technology
Full-Spectrum Spatial-Temporal Dynamic Thermal Analysis for Nanometer-Scale Integrated Circuits
Statistical Timing Yield Optimization by Gate Sizing
Low-Power and High-Accurate Synchronization for IEEE 802.16d Systems
Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed-Solomon Decoding
New power-of-2 RNS scaling scheme for cell-based IC design
High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array
Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits
Floating Gate-Based Field Programmable Mixed-Signal Array
Current Optimized Coset Coding for Efficient RRAM Programming
Impact of Radix-10 Redundant Digit Set [-6, 9] on Basic Decimal Arithmetic Operations
Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System
Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements
High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR-XNOR Cell
An Improved MOS Self-Biased Ring Amplifier and Modified Auto-Zeroing Scheme
An On-Demand Queue Management Architecture for a Programmable Traffic Manager
Circuit Level Defences Against Fault Attacks in Pipelined NCL Circuits
Analog-to-digital converter based on single-electron tunneling transistors
A Design of 12.8-Gpixels/s Hardware-Efficient Lossless Embedded Compression Engine for Video Coding Applications
A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology
Fast Transient (FT) Technique With Adaptive Phase Margin (APM) for Current Mode DC-DC Buck Converters
Accelerated Accurate Timing Yield Estimation Based on Control Variates and Importance Sampling
Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies
Real-Time Driver Monitoring: Implementing FPGA-Accelerated CNNs for Pose Detection
High-Throughput 0.13-µm CMOS Lattice Reduction Core Supporting 880 Mb/s Detection
Cooperating Virtual Memory and Write Buffer Management for Flash-Based Storage Systems
A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation
Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM
Applying CDMA Technique to Network-on-Chip
GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features
Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes
A 12.5-Gb/s On-Chip Oscilloscope to Measure Eye Diagrams and Jitter Histograms of High-Speed Signals
Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology
An optimization approach to the synthesis of multichip architectures
Architecture of Cobweb-Based Redundant TSV for Clustered Faults
A 470-µW 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider With an In-Phase Dual-Input Injection Scheme
Hierarchical Segmentation for Hardware Function Evaluation
All-Digital Wide Range Precharge Logic 50% Duty Cycle Corrector
Scheduling of uniform multidimensional systems under resource constraints
Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In
Temperature-Gradient-Based Burn-In and Test Scheduling for 3-D Stacked ICs
Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width Values
Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers
On chip testing data converters using static parameters
Voltage Driven Nondestructive Self-Reference Sensing Scheme of Spin-Transfer Torque Memory
Incoherent Undersampling-Based Waveform Reconstruction Using a Time-Domain Zero-Crossing Metric
Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks
Jitter of Delay-Locked Loops Due to PFD
Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks
Fault-tolerant self-organizing map implemented by wafer-scale integration
Autonomous, Multilevel Ring Tuning Scheme for Post-Silicon Active Clock Deskewing Over Intra-Die Variations
Dual-Channel Multiplier for Piecewise-Polynomial Function Evaluation for Low-Power 3-D Graphics
LEAP: Lightweight and Efficient Accelerator for Sparse Polynomial Multiplication of HQC
Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis
Fast Stochastic Analysis of Electromigration in Power Distribution Networks
SPOT: Fast and Optimal Built-In Redundancy Analysis Using Smart Potential Case Collection
Scalable Methods for Analyzing the Circuit Failure Probability Due to Gate Oxide Breakdown
On the Power Management of Simultaneous Multithreading Processors
Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches