yusuke1997/dblp-id-title huggingface dataset:
Advances in Parallel Discrete Event Simulation for Electronic System-Level Design
Hacking in the Dark
Test Considerations for Gate Oxide Shorts in CMOS ICs
An Overview of Open SystemC Initiative Standards Development
Power Supply Noise in SoCs: Metrics, Management, and Measurement
Metamodeling for model-based system design
Testing Core-Based Systems: A Symbolic Methodology
The Last Byte: 3-D TV? We Got 6-D TV!
The DAD Reamework Interactive
How ATE Planning Affects LSI Manufacturing Cost
What Is the Next Implementation Fabric?
Incremental switch-level analysis
Adaptive Alternate Analog Test
Framework for Load Power Consumption in HANs Using Machine Learning and IoT Assistance
How Do I Boot Thee? Let Me Check Page 3
Who knew this "experiment" would be so successful?
A D&T Roundtable: Low-Power Design
Report on the 2022 Embedded Systems Week (ESWEEK)
Debug Automation for Logic Circuits Under Timing Variations
Design and test for reliability and efficiency
Ethics in Sustainability
Minimizing Pattern Count for Interconnect Test under a Ground Bounce Constraint
Guest Editors' Introduction: Early Modeling and Analysis of Packaged Systems
Rothko: A Three-Dimensional FPGA
Concurrent Engineering in Product Development
1991 Annual Index
Analyzing Packaging Trade-Offs During System Design
Design Techniques for EEPROMs Embedded in Portable Systems on Chips
Electronic Design Methods and Technologies for Green Buildings
Hierarchical Test Compression for SoC Designs
Behavioral model synthesis with Cones
The Need for a SiP Design and Test Infrastructure
Machine Learning in Advanced IC Design: A Methodological Survey
Special Report: Shared-I/O Scan Test
Moving the Market to Embedded Memory
A Survey of Switch-Level Algorithms
From measurements to sustainable choices [Persepectives]
Remote Power Side- Channel Attacks on FPGAs
Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package
A Fault Injection Technique for VHDL Behavioral-Level Models
Submicron design tools: problems and suppliers
Embedded DRAM Development: Technology, Physical Design, and Application Issues
A Reliability Testing Environment for Off-the-Shelf Memory Subsystems
250-MHz advanced test systems
Report on the 2025 Embedded Systems Week (ESWEEK)
Case Study on Speed Failure Causes in a Microprocessor
Dealing with early life failures
Failure diagnosis of structured VLSI
20 Years of IEEE CEDA and More of EDA
TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification
Report on MECO'2015
Empowering the designer
A Brief 20-Year History and Future Perspectives on Sizing and Layout Synthesis of Analog/RF ICs
How much variability can designers tolerate?
Statistical High-Level Synthesis under Process Variability
An expert system to automate timing design
Guest Editors' Introduction: The Status of IEEE Std 1500 - Part 2
Top-Down Layout for Hierarchical Custom Design
Call For Articles
Design Aids for VLSI: A Perspective Revisited
FPGA-Based Particle Recognition in the HADES Experiment
Packaging a 40-Gbps Serial Link Using a Wire-Bonded Plastic Ball Grid Array
Guest Editors' Introduction: New Dimensions in 3D Integration
Proteus: An ASIC Flow for GHz Asynchronous Designs
What Is Real Time Computing? A Personal View
Turbo-FHE: Accelerating Fully Homomorphic Encryption With FPGA and HBM Integration
Built-In Self-Test Trends in Motorola Microprocessors
Guest Editor's Introduction: Design Tools for Embedded Systems
Using Atomic Force Microscopy for Deep-Submicron Failure Analysis
Jitter Measurements of High-Speed Serial Links
On the Mitigation of Read Disturbances in Neuromorphic Inference Hardware
Autoprobing on the L200 Functional Tester
Hierarchical Electric Vehicle Charging Aggregator Strategy Using Dantzig-Wolfe Decomposition
Sustaining an Industry Obsession
Vulnerability of Hardware Neural Networks to Dynamic Operation Point Variations
Logic Design for Printability Using OPC Methods
Managing your EDA investments
Unleashing Fury: A New Paradigm for 3-D Design and Test
An Efficient Hardware Design for the VVC Prediction Refinement With Optical Flow
Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations
IDDQ Design and Test Advantages Propel Industry
SBCCI 2022
Lifelong Exploratory Navigation: An Architecture for Safer Mobile Robots
A Component-Based Design Environment for ESL Design
Moore's law meets the life sciences
Discontinuities Driven by a Billion Connected Machines
Knowledge-Based Code Selection Methods in Retargetable Microcode Synthesis
Long-Wire Leakage: The Threat of Crosstalk
Testing for what?
VTS 1994 Panel Report on BIST for Consumer Products
A D&T Roundtable: Design Automation in Europe
Embedded Software-Based Self-Test for Programmable Core-Based Designs
Using VHDL for High-Level, Mixed-Mode System Simulation
T-Topology Coupler-Based Bandpass Negative Group Delay Active Circuit Design and Test
Cypress: Compression and Encryption of Data and Code for Embedded Multimedia Systems
Bringing Robustness and Power Efficiency to Autonomous Energy-Harvesting Microsystems
Asynchronous Design - Part 2: Systems and Methodologies
About the power problem [review of "Power-Aware Testing and Test Strategies for Low Power Devices" (Girard, P., Eds., et.; 2010)]
Adaptive Integer Linear Programming Model for Optimal Qubit Permutation
Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs
Materials, Processing, and Testing of Flexible Image Sensor Arrays
Low-Impact Processor for Dynamic Runtime Power Management
Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories
Building your yield of dreams
Boundary-scan architecture, neutral testing models
Speed Binning with Path Delay Test in 150-nm Technology
Report on the 2018 IEEE/ACM International Symposium on Low Power Electronics and Design
D&T and the Future
Texas A&M Hackin' Aggies' Security Verification Strategies for the 2019 Hack@DAC Competition
Recap of the 2017 International Symposium on Low Power Electronics and Design (ISLPED)
Optical Interconnect for High-End Computer Systems
Designing and Testing Implantable Medical Devices
Power Estimation of Digital Data Paths Using HEAT
Guest Editors' Introduction: Mixed Analog and Digital Systems
On the Implementation of Fixed-Point Exponential Function for Machine Learning and Signal- Processing Accelerators
Integrating Interobject Scenarios with Intraobject Statecharts for Developing Reactive Systems
A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers
From Protocol Models to Their Implementation: A Versatile Testing Methodology
CTL and Its Usage in the EDA Industry
Reorganizing Circuits to Aid Testability
An ultra high speed test system
Current testing for nanotechnologies: Myths, facts, and figures
Intellectual Property Protection of Deep-Learning Systems via Hardware/Software Co-Design
From the EIC: The changing face of IC design and its industry
Book Review: An Assay of Biochips
Unveiling the ISCAS-85 Benchmarks: A Case Study in Reverse Engineering
Interconnection Problems in Modern Computers
Applications of a Laser-Induced Plasma Pathway to Testing of Electronic Modules
Standing on the Shoulders of ..
Recap of the 2016 DATE Conference & Exhibition
The commonality of vector generation techniques
Assessment of Circuit Optimization Techniques Under NBTI
Mixed-Signal Production Test: A Measurement Principle Perspective
Formal-Based Design and Verification of SoC Arbitration Protocols: A Comparative Analysis of TDMA and Round-Robin
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield
Electronic Detection of DNA Hybridization: Toward CMOS Microarrays
Practices and Challenges for Achieving Functional Safety of Modern Automotive SoCs
DDATC Newsletter
Practical Oscillation-Based Test of Integrated Filters
At-Speed Testing: A Shared Red Brick between Design and Test
Automatic Calibration of Streaming Applications for Software Mapping Exploration
Management Perspectives in EDA
Merged Logic and Memory Fabrics for Accelerating Machine Learning Workloads
Advances in 3-D Integrated Circuits, Systems, and CAD Tools
Top Picks in Hardware and Embedded Security 2022
Light-Enhanced FET Switch Improves ATE RF Power Settling
Using VHDL for Board Level Simulation
Performing Effective Fault Isolation in Integrated Diagnostics
Bandpass NGD Time- Domain Experimental Test of Double-Li Microstrip Circuit
Your Core-My Problem? Integration and Verification of IP
FPGA Architectural Research: A Survey
Traversal Packets: Opportunistic Bypass Packets for Deadlock Recovery
IEEE Design & Test of Computers, 1998 Annual Index, Volume 15
Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design
Linking Design&Test
Autonomous Systems and the Challenges in Verification, Validation, and Test
Lab on a Chip Based on CMOS Technology: System Architectures, Microfluidic Packaging, and Challenges
Open-Source Multilevel Converter Power IC Design and Test
IEEE Design & Test of Computers 2000 Annual Index, Volume 17
Strange Loops in Design and Technology: 59th DAC Keynote Speech
Reconfigurable Pipelined Control Systems
Hardware Obfuscation and Logic Locking: A Tutorial Introduction
Design and Testing of Millimeter-Wave/Subterahertz Circuits and Systems
The other face of design for manufacturability
Design Closure with Cell-Based Synthesis
Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits
Fuzzing for Automated SoC Security Verification: Challenges and Solution
Holding Conferences Online in Pandemic Times: The DATE Experience
The Psychology of Electronic Test
Matisse: An Architectural Design Tool for Commodity ICs
Eavesdropping Attack Detection Using Machine Learning in Network-on-Chip Architectures
NVIDIA MATHS: Mechanism to Access Test-Data Over High-Speed Links
On the Origin of AI Species
Stored Programs Restored
Systematic Design of Medical Capsule Robots
OCP-IP NoC Benchmarking WG activities
Guest Editors' Introduction: Cross-Layer Design of Cyber-Physical Systems
Computer-Aided Design of Fault-Tolerant VLSI Systems
The Design of Dedicated 32-Bit Processors
IEEE Design & Test of Computers
Getting More out of ITC
The Role of the Good-Die Project in Miniaturized-System Design
Conference Reports: 2005 International Test Conference
Computer-Vision-Based Decision Support in Surgical Robotics
Testing Mixed-Signal Devices
Automated Probe-Mark Analysis for Advanced Probe Technology Characterization
Application Scenarios in Streaming-Oriented Embedded-System Design
Guest Editors' Introduction: Special Issue on Design and Test of Multidie Packages
Determining a Failure Root Cause Distribution From a Population of Layout-Aware Scan Diagnosis Results
Deep Submicron CMOS Current IC Testing: Is There a Future?
Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs
A Hardware Accelerator for Language-Guided Reinforcement Learning
Guest Editors' Introduction: RTL to GDSII - From Foilware to Standard Practice
Workload-Aware Periodic Interconnect BIST
Design of Asynchronous Circuits Using Synchronous CAD Tools
Identifying Systematic Failures on Semiconductor Wafers Using ADCAS
A Growing and Thriving Electronic Design, Automation, and Test Community: A DATE 2025 Perspective
Thermoelectric Codesign of 3-D CPUs and Embedded Microfluidic Pin-Fin Heatsinks
Global competitiveness, outsourcing, and education in the semiconductor industry
Configurations for IDDQ-Testable PLAs
Defeating Cache Timing Channels with Hardware Prefetchers
Improving color CAD Systems for Users: Some Suggestions from Human Factors Studies
A Multichannel Power-Supply-Modulated Microstimulator With Energy Recycling
RASSP: Changing the Paradigm of Electronic-System Design
Powering the Future: Organic Solar Cells with Polymer Energy Storage
Practical, Lightweight Secure Inclusion of Third-Party Intellectual Property
Preventing IC Piracy Using Reconfigurable Logic Barriers
Orthogonality of Verilog Data Types and Object Kinds
Cross-Layer Design of Automotive Systems
The State of ESL Design [Roundtable]
Design Considerations for Modeling Modes in Cyber-Physical Systems
Guest Editors' Introduction: Special Issue on Benchmarking Machine Learning Systems and Applications
Compact Modeling of Thin-Film Transistors for Flexible Hybrid IoT Design
Design and Development Paradigm for Industrial Formal Verification CAD Tools
Semicustom Design of an IEEE 1394-Compliant Reusable IC Core
SystemVerilog Assertions: Past, Present, and Future SVA Standardization Experience
Exploring Resilience of LPDRAM Against RowHammer
The ARM Cortex-A8 Microprocessor IEEE Std 1500 Wrapper
Guest Editors' Introduction: Special Issue on Energy and Power Management for Electric Vehicles
High-Frequency, At-Speed Scan Testing
The Swarm at the Edge of the Cloud
A Flexible DSP Core for Embedded Systems
Guest Editors' Introduction: Managing Uncertainty through Postfabrication Calibration and Repair
Digitally intensive wireless transceivers
Design and Test of Genetic Circuits Using ${\tt iBioSim}$iBioSim
Virtual Roundtable: User Perspectives
Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators
IEEE Std 1149.1: Where Are We? Where From Here?
Getting to Know All About Us
Security Vulnerabilities and Countermeasures in MPSoCs
BIST the hard way
From the EIC: Architecture Advances Enabled by Emerging Technologies
Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity
Integration Continues
Three Decades of HDLs: Part I, CDL Through TI-HDL
A Mixed-Signal Design Roadmap
Adaptive Neural Network Architectures for Power Aware Inference
Test Synthesis with Alternative Graphs
Approximate Computing: Solving Computing's Inefficiency Problem?
Randomized Testing of RISC-V CPUs Using Direct Instruction Injection
LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing
Computational RAM: Implementing Processors in Memory
Special Issue on Top Picks in Test and Reliability
StepNP: A System-Level Exploration Platform for Network Processors
On-Chip IDDQ Testing in the AE11 Fail-Stop Controller
High-Performance MCM Routing
Compilation Approach for Coarse-Grained Reconfigurable Architectures
CaSA: End-to-End Quantitative Security Analysis of Randomly Mapped Caches
VHDL - Feature Description and Analysis
Generating Functional Design Verification Tests
Cyber-Physical Systems Security Education Through Hands-on Lab Exercises
Flute an Expert Floor Planner for Full-Custom VLSI Design
Aegis: A Single-Chip Secure Processor
From the EIC: Past successes, future challenges
ISLPED 2022: An Experience of a Hybrid Conference in the Time of COVID-19
Is it time to reexamine patent policy for standards?
Yield-Driven, False-Path-Aware Clock Skew Scheduling
Analysis and Mitigation of DRAM Faults in Sparse-DNN Accelerators
Conference Report From The 57th Design Automation Conference
A Basis for Setting Burn-in Yield Criteria
A Fault-Tolerant Digital Artificial Neuron
The EDA Business Model Dialogue Part 1
Pseudorandom Testing for Boundary-Scan Design with Built-In Self-Test
Reconfigurable Photovoltaic Systems for Electric Vehicles
Are CNNs Reliable Enough for Critical Applications? An Exploratory Study
Serial Interfacing for Embedded-Memory Testing
DC Built-In Self-Test for Linear Analog Circuits
Asynchrony in Quantum-Dot Cellular Automata Nanocomputation: Elixir or Poison?
Quantum Computing Circuits and Devices
Computing and Minimizing Cache Vulnerability to Transient Errors
25th IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2017)
Hardware Trojans Inspired IP Watermarks
Creating a Successful Partnership Between Industry, Academia, and Government
Nanotechnology: Where science of the small meets math of the large
Making a List...Checking it Twice
Approximate Computing: A Survey
Secure and Robust Error Correction for Physical Unclonable Functions
Test's Evolving Mission
Power-/Energy Efficient BIST Schemes for Processor Data Paths
Detecting and Scoring Equipment Faults in Real Time During Semiconductor Test Processes
Overview of Debug Standardization Activities
Small Smarts
Integrating Machine-Learning Probes in FPGA CAD: Why and How?
Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale
Improvement of Functional Safety of the Level-Crossing Barrier Machine by a Noninvasive Angle-Detection Method
BIST to Detect and Characterize Transient and Parametric Failures
Guest Editor's Introduction: Field-Programmable Gate Arrays
Asynchronous FUD
A D&T Roundtable: Online Test
Guest Editors' Introduction: Security and Trust in Embedded-Systems Design
Advanced Fault Collapsing (Logic Circuits Testing)
Robust and Secure Systems
Low-Power High-Throughput Architecture for AV1 Arithmetic Decoder
Functional Equivalence Verification Tools in High-Level Synthesis Flows
Progress in Design for Test: A Personal View
Embedded System Design: Milestones, Momentum, and the Frontier
Designing a Real-Time Coprocessor for Ada Tasking
A Coding Efficiency-Aware Hardware Design for VVC Affine Motion Estimation Reconstructor
Bringing down NRE
The New World of ESL Design
Automatic Detection of Respiratory Symptoms Using a Low-Power Multi-Input CNN Processor
Guest Editorial: High-Level Synthesis of Digital Circuits
Guest Editors' Introduction: GALS Design and Validation
Designing "Vary" Good Circuitry
The Story behind the Intel Atom Processor Success
Can Product-Specific Assurance Case Templates Be Used as Medical Device Standards?
Making Java Work for Microcontroller Applications
Efficient Associative Search in Brain-Inspired Hyperdimensional Computing
Verification and Test
Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques
Design & Test in the new decade: Continuity and new directions
A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs
Guest Editors' Introduction: SBCCI 2020
A Knowledge-Based System for Designing Testable VLSI Chips
EM/Power Side-Channel Attack: White-Box Modeling and Signature Attenuation Countermeasures
Random-Access Data Storage Components in Customized Architectures
Specification and Design of Embedded Hardware-Software Systems
Software Energy Reduction Techniques for Variable-Voltage Processors
Using a Periodic Square Wave Test Signal to Detect Crosstalk Faults
Noise Problems in Testing VLSI Hardware
Compilation for FPGA-Based Reconfigurable Hardware
Embedded Deterministic Test for Low-Cost Manufacturing
The Changing Design Landscape
IC Failure Analysis: Magic, Mystery, and Science
IP-based business conflicts
A Methodology for Architectural Design of Multimedia Multiprocessor SoCs
Time to retire our benchmarks
OpenDFM Bridging the Gap Between DRC and DFM
Status Report on Standards Affecting Design and Test
A DFT Approach for Testing Embedded Systems Using DC Sensors
Welcome to 2001
Using Laser Defect Avoidance to Build Large-Area FPGAs
Edge AI - An Industry View
Making more out of open-source tools
Scalable Processor Instruction Set Extension
Developing Micropipeline Wavefront Arbiters
Low-Cost Structural Monitoring of Analog Circuits for Secure and Reliable Operation
CAFEEN: A Cooperative Approach for Energy-Efficient NoCs With Multiagent Reinforcement Learning
Impact of Design-Manufacturing Interface on SoC Design Methodologies
Guest Editors' Introduction: Special Issue on Machine Learning for CAD/EDA
Automated Design Error Localization in RTL Designs
DAC2013 Visionary Talk
Reliable Nonvolatile Memories: Techniques and Measures
Synthesizing Fast, Online-Testable Control Units
Fault-Tolerant Systolic Array Based Accelerators for Deep Neural Network Execution
Standards update from IP 07
The reliability of approximate testability measures
OEM Component Authentication
Open Defects in CMOS RAM Address Decoders
Extensions to Backward Propagation of Variance for Statistical Modeling
Built-In Self-Diagnosis for Repairable Embedded RAMs
Transition Fault Simulation
1990 Annual Index
Assertion-based verification turns the corner
Yield Recovery of RF Transceiver Systems Using Iterative Tuning-Driven Power-Conscious Performance Optimization
Designing UltraSparc for Testability
Analytical Model for Performance Evaluation of Token-Passing-Based WiNoCs
The Effects of Modeling on Simulator Performance
VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG
Needed: Third-generation ATPG Benchmarks
Lazy Discharge: A High- Speed Energy-Efficient Read Technique for NAND Flash Memory
A Fully-Automated Electron Beam Test System for VLSI Circuits
Hardware Coprocessor Synthesis from an ANSI C Specification
Project-Based CPS Education: A Case Study of an Autonomous Driving Student Project
And He Built a Crooked Chip
High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulations
Expedited-compact architecture for average scan power reduction
Self-Healing Phase-Locked Loops in Deep-Scaled CMOS Technologies
Information-Theoretic Framework for Evaluating and Guiding Board-Level Functional-Fault Diagnosis
The Internet of Tiny Things: Recent Advances of Millimeter-Scale Computing
Guest Editors' Introduction: The State of the Art in Nanoscale CAD
Variability and New Design Paradigms
Behavioral-level fault simulation
Power Management in the Amulet Microprocessors
Machine Intelligence at the Edge
A clockless future for systems on chip
A Truly Wireless Future?
The Future of Signoff
Data Center Energy Efficiency: Improving Energy Efficiency in Data Centers Beyond Technology Scaling
Runtime Thermal Management Using Software Agents for Multi- and Many-Core Architectures
Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices
Efficient Multiplexer Synthesis Techniques
Designing Self-Timed Devices Using the Finite Automaton Model
Emerging Accelerator Platforms for Data Centers
A D&T Roundtable: RF Integration into CMOS and Deep-Submicron Challenges
ELEMENT: Energy-Efficient Multi-NoP Architecture for IMC-Based 2.5-D Accelerator for DNN Training
Microarchitectural dI/dt Control
Rapid Prototyping for DSP Systems with Multiprocessors
Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology
Automated Synthesis of Digital systems
Design Verification of FPGA Implementations
Book Review: A book on system test, and testing systems also
Interactive Debug of SoCs with Multiple Clocks
Design and test on chip for EMC
Design for manufacturability comes of age
An Overview of Challenges and Requirements for Real-Time Spectrum Sensing in Modern RF Autonomy Systems
UVM-SystemC-AMS Framework for System-Level Verification and Validation of Automotive Use Cases
Testing Methodology for FireWire
Author Guidelines IEEE Design & Test of Computers
Multiplexing ATE Channels for Production Testing at 2.5 Gbps
A Platform-Based Taxonomy for ESL Design
A Highly Scalable GALS Crossbar Using Token Ring Arbitration
Mixed-Criticality Scheduling Theory: Scope, Promise, and Limitations
Sensor-Driven Reliability and Wearout Management
Guest Editors' Introduction: Advances in VLSI Testing at MultiGbps Rates
Self-Healing of Redundant FLASH ADCs
ALIGN: A System for Automating Analog Layout
Historical Perspective on Scan Compression
Still in the Stone Age?
Reliability Challenges Related to TSV Integration and 3-D Stacking
FlooNoC: A Multi-Tb/s Wide NoC for Heterogeneous AXI4 Traffic
Recap of the 29th Edition of the Asia and South Pacific Design Automation Conference (ASPDAC 2024)
Guest Editors' Introduction: Emerging Challenges and Solutions in SoC Verification
STLs for GPUs: Using High-Level Language Approaches
An Open-Source 12-bit 10-kS/s Incremental ADC in 130-nm CMOS
Raisin: Redundancy Analysis Algorithm Simulation
From the EIC: The next EDA challenge - Design for manufacturability
Novel Technique for Manufacturing, System-Level, and In-System Testing of Large SoC Using Functional Protocol-Based High-Speed I/O
Multichannel Wireless Neural Recording AFE Architectures: Analysis, Modeling, and Tradeoffs
Economic Aspects of Memory Built-in Self-Repair
A Promising Alternative to Conventional Silicon
Creating a Foundation for Next-Generation Autonomous Systems
A workstation approach to IC process and device design
Handling Nondeterminism in Logic Simulation so That Your Waveform Can Be Trusted Again
Test Economics in the 21st Century