yusuke1997/dblp-id-title huggingface dataset:
Reconfigurable computer systems: from the first FPGAs towards liquid cooling systems
Toward Exascale Resilience: 2014 update
Porting and Optimizing Molecular Docking onto the SX-Aurora TSUBASA Vector Computer
Communication Complexity of the Fast Multipole Method and its Algebraic Variants
Supercomputer Modeling of Dual-Site Acetylcholinesterase (AChE) Inhibition
Data merging for the cultural heritage imaging based on Chebfun approach
Parallel Numerical Algorithm for Solving Advection Equation for Coagulating Particles
Hybrid CPU + Xeon Phi implementation of the Particle-in-Cell method for plasma simulation
State of the Art and Future Trends in Data Reduction for High-Performance Computing
Scalability prediction for fundamental performance factors
Live Programming in Scientific Simulation
HPC Processors Benchmarking Assessment for Global System Science Applications
Record-and-Replay Techniques for HPC Systems: A Survey
Extreme Big Data (EBD): Next Generation Big Data Infrastructure Technologies Towards Yottabyte/Year
Workflows for Science: a Challenge when Facing the Convergence of HPC and Big Data
A Dynamic Congestion Management System for InfiniBand Networks
High Performance Computing of Magnetized Galactic Disks
Towards a performance portable, architecture agnostic implementation strategy for weather and climate models
Online MPI Process Mapping for Coordinating Locality and Memory Congestion on NUMA Systems
Enhancing the in Situ Visualization of Performance Data in Parallel CFD Applications
Supercomputer technologies in tomographic imaging applications
Performance Analysis of Different Computational Architectures: Molecular Dynamics in Application to Protein Assemblies, Illustrated by Microtubule and Electron Transfer Proteins
Continuum Computing - on a New Performance Trajectory beyond Exascale
Computer Design of Structure of Molecules of High-Energy Tetrazines. Calculation of Thermochemical Properties
On the Inversion of Multiple Matrices on GPU in Batched Mode
Additivity: A Selection Criterion for Performance Events for Reliable Energy Predictive Modeling
Size & Shape Matters: The Need of HPC Benchmarks of High Resolution Image Training for Deep Learning
Towards A Data Centric System Architecture: SHARP
Computational Resource Consumption in Convolutional Neural Network Training - A Focus on Memory
Parallel algorithm for 3D modeling of monochromatic acoustic field by the method of integral equations
Recent Progress on Supercomputer Modelling of High-Speed Rarefied Gas Flows Using Kinetic Equations
Supercomputer Lomonosov-2: Large Scale, Deep Monitoring and Fine Analytics for the User Community
Parallel software platform INMOST: a framework for numerical modeling
Resilience Design Patterns: A Structured Approach to Resilience at Extreme Scale
Exploiting the Performance Benefits of Storage Class Memory for HPC and HPDA Workflows
Perspectives on Supercomputing and Artificial Intelligence Applications in Drug Discovery
Survey on Software Tools that Implement Deep Learning Algorithms on Intel/x86 and IBM/Power8/Power9 Platforms
Multicore Platform Efficiency Across Remote Sensing Applications
In Situ Exploration of Particle Simulations with CPU Ray Tracing
Comparative Analysis of Virtualization Methods in Big Data Processing
Runtime-Aware Architectures: A First Approach
Optimizing Deep Learning RNN Topologies on Intel Architecture
Creating interconnect topologies by algorithmic edge removal: MOD and SMOD graphs
The L-CSC cluster: Optimizing power efficiency to become the greenest supercomputer in the world in the Green500 list of November 2014
Forecastability Measures that Describe the Complexity of a Site for Deep Learning Wind Predictions
Server Level Liquid Cooling: Do Higher System Temperatures Improve Energy Efficiency?
Fully Implicit Time Stepping Can Be Efficient on Parallel Computers
A Flux Splitting Method for the SHTC Model for High-performance Simulations of Two-phase Flows
From Processing-in-Memory to Processing-in-Storage
An Application of GPU Acceleration in CFD Simulation for Insect Flight
Potential of I/O Aware Workflows in Climate and Weather
Supercomputer Simulations of Fluid-Structure Interaction Problems Using an Immersed Boundary Method
High-performance Full-atomistic Simulation of Optical Thin Films
Many-Core Approaches to Combinatorial Problems: case of the Langford Problem
Update on Performance Analysis of Different Computational Architectures: Molecular Dynamics in Application to Protein-Protein Interactions
Three-dimensional Inversion of Electromagnetic Geophysical Data with Parallel Computational Code on Supercomputer Complex "Lomonosov"
Efficient Implementation of Liquid Crystal Simulation Software on Modern HPC Platforms
3D Problems of Rotating Detonation Wave in a Ramjet Engine Modeled on a Supercomputer
Supercomputer Modeling of Parachute Flight Dynamics
xSDK Foundations: Toward an Extreme-scale Scientific Software Development Kit
The Coordination Language Facility: Coordination of Distributed Objects
Tool Construction for the British Airways SEE with the O 2 ODBMS
Understanding and Using Patterns in Software Development
Managing Historical Semistructured Data
Facilitating Object-Based Navigation Through Multimedia Web Databases
Dynamic versus Static Optimization Techniques for Object-Oriented Languages
T_Chimera: A Temporal Object-Oriented Data Model
Class Composition for Specifying Framework Design
Roles: Conceptual Abstraction Theory and Practical Language Issues
Foundations of Object-Oriented Languages - Introduction
Editorial - Third Workshop on Foundations of Object-Oriented Languages
Building CORBA Applications with an Object Database System
Enhancing Object-Oriented Methods with Formal Notations
Modular Atomic Objects
Research Directions: The Future of CORBA - Editorial
Evaluating the Performance of Object-Oriented Database Systems by means of a Concrete Application
A Structured Text ADT for Object-Relational Databases
On Binary Methods
Data-intensive Intra- and Internet Applications based on Java, CORBA, and the World Wide Web
Design of Class Hierarchies Based on Concept (Galois) Lattices
Automatic Generation of User-Defined Virtual Documents Using Query and Layout Templates
An Object Oriented Approach to Web-Based Applications Design
Inheritance Anomaly in CORBA Multithreaded Environments
Maintainance of Object-Oriented Systems During Structural Schema Evolution
A Perspective on Object-Oriented Research
Combining Reflection and Finite State Diagrams for Design Enforcement
Object Oriented Protocol Hierarchies for Distributed Workflow Systems
Performance Evaluation of Object-Oriented Active Database Systems Using the BEAST Benchmark
An Imperative Object Calculus (Invited Paper)
An Experience Using Design Patterns: Lessons Learned and Tool Support
O2 and The ODMG Standard: Do They Match?
The Electronic Library Project: SGML Document Management System Based on ODBMS
Trader Down Under: Upside Down and Inside Out
Mandatory Security and Object-Oriented Systems: A Multilevel Entity Model and its Mapping onto a Single-Level Object Model
Specifying Subject-Oriented Composition
Object-Oriented Databases and Applications - Selected Papers from ICDE'98
PSiGene: A Pattern-Based Component Generator for Building Simulation
A Formal View of Object-Oriented Database Systems
Experiences in the Implementation of a Process-centered Software Engineering Environment Using Object-Oriented Technology
The Development of Type Systems for Object-Oriented Languages
On the Relationship Between Classes, Objects, and Data Abstraction
Object Management for a Visual Data Analysis Tool
Towards Deductice Object Databases
Using Dynamic Classes and Role Classes to Model Object Migration
Building Reliable Distributed Systems with CORBA
Multiple-Dispatching Based on Automata
Type Inference with Constrained Types
The Event Notification Pattern - Integrating Implicit Invocation with Object-Orientation
Object Identifiers, Keys, and Surrogates: Object Identifiers Revisited
The MultiView OODB View System: Design and Implementation
The Maestro Approach to Building Reliable Interoperable Distributed Applications with Multiple Execution Styles
Object Acquaintance Selection and Binding
Using Design Patterns to Restructure the User Interface Part of an Application Framework
SEMCOG: A Hybrid Object-based Image and Video Database System and Its Modeling, Language, and Query Processing
Processes, Functions, and Datatypes
Integrating Security in the CORBA Architecture
A Performance Study of Object Database Management Systems
A Refactoring Tool for Smalltalk
Space and Time-Efficient Hashing of Garbage-Collected Objects
Typed pi-calculus at Work: A Correctness Proof of Jones's Parallelisation Transformation on Concurrent Objects
Law-Governed Regularities in Object Systems, Part 2: A Concrete Implementation
A Processing Model for Two-Dimensional Images Based on the Object-Oriented Paradigm
Breaking Through the n 3 Barrier: Faster Object Type Inference
Object-Oriented Software Evolution and Reengineering - Editorial
Towards Foundations of Concurrent Object-Oriented Programming-Types and Language Design
Class-Graph Inference for Adaptive Programs
Design and Implementation of Pep, A Java Just-in-Time Translator
Editorial - Objects, Databases, and the WWW
An Experiment in Framework Development
The Implementation of a CORBA Object Group Service
Law-Governed Regularities in Object Systems. Part 1: An Abstract Model
Implementing Object Access Control a posteriori
A Simple and Unifying Approach to Subjective Objects
A Family of Design Patterns for Applications-Level Gateways
Consistent Object Replication in the external System
Editorial - High Availability in CORBA
Architectural Support for Quality of Service for CORBA Objects
Inheritance of Proofs
Behaviorally Adaptive Objects
In the Trenches with ObjectStore
Experience with Distributed Replicated Objects: The Nile Project
Is the Java Type System Sound?
THE GPR System: An Architecture for Integrating Active and Deductive Rules on Complex Database Objects
Supporting Interoperation of Continuous Media Objects
An Entropy-Based Complexity Measure for Object-Oriented Designs
Objective ML: An Effective Object-Oriented Extension to ML
Maximizing Object Reuse with a Biological Metaphor
Dotplot Patterns: A Literal Look at Pattern Languages
MaRs: a parallel graph reduction multiprocessor
Disk array performance in a random IO environment
The memory gap and the future of high performance memories
Internet nuggets
Optimized communication in an extended remote procedure call model
Practical analysis of stripped binary code
Thread standardization and relative cost
Three-dimensional computers and measuring their performance
Efficient Mapping and Allocation of Execution Units to Task Graphs using an Evolutionary Framework
"Floating point RNS": a new concept for designing the MAC unit of digital signal processor
Representation of logic functions by if-then clauses
A transparent Linux super page kernel for Alpha, Sparc64 and IA32: reducing TLB misses of applications
An integrated system for neural network simulations
From chaos to QoS: case studies in CMP resource management
Efficient architecture and scheduling technique for pairwise sequence alignment
Using DISE to protect return addresses from attack
DRAMsim: a memory system simulator
Performance/Watt: the new server focus
High Throughput Sketch Based Online Heavy Hitter Detection on FPGA
The peripheral bus
Ariel: a scalable multiprocessor for the simulation of neural networks
GPU Accelerated Hybrid Tree Algorithm for Collision Less N-body Simulations
Towards modeling & analysis of consolidated CMP servers
State-space exploration for concurrent algorithms under weak memory orderings: (preliminary version)
An example RISC vector machine architecture
Distributed directory tags
Rebuild processing in RAID5 with emphasis on the supplementary parity augmentation method[37]
A novel single instruction computer architecture
Review of "Microcomputer architecture and programming by John F. Wakerly." John Wiley & Sons, Inc., 1981
A parallel pipelined processor with conditional instruction execution
A common machine language for grid-based architectures
Internet Nuggets
Embedding computers in a cellular array
Protection at the micromachine level
A comment on "a fetch - and - op implementation for parallel computers"
A novel trace sampling technique
Future multicomputers: beyond minimalist multiprocessors?
Airdisks and airRAID (expanded extract): modeling and scheduling periodic wireless data broadcast
Architectural support for the cache based vector computation
Optimal VLSI architectures for multidimensional DFT (preliminary version)
Book review: The Definition of Standard ML by R. Milner, M. Torte, R. Harper
Optimising hot paths in a dynamic binary translator
A case for user-level interrupts
Book review: Systems Programming in Parallel Logic Languages by lan Foster (Prentice Hall, 1990)
A hybrid CPU-FPGA system for high throughput (10Gb/s) streaming document classification
Survey and analysis of disk scheduling methods
An EGA approach to the compile-time assignment of data to multiple memories in digital-signal processors
The limits of instruction level parallelism in SPEC95 applications
The Mill: split-stream encoding
Surviving the end of frequency scaling with reconfigurable dataflow computing
Beyond the Baskett benchmark
Data cache management on EPIC architecture: optimizing memory access for image processing
An approach to fault tolerance and error recovery in a parallel graph reduction machine: MaRS - a case study
Benefits of implementing on-line methods and procedures
Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05)
Prototype implementation of array-processor extensible over multiple FPGAs for scalable stencil computation
Customisable architectures for the set covering problem
Errata on "Measuring Experimental Error in Microprocessor Simulation"
From defects to failures: a view of dependable computing
The nature of "computer architecture"
The RISC processor DMN-6: a unified data-control flow architecture
Performance comparison of GPU programming frameworks with the striped Smith-Waterman algorithm
The compiler controlled pack cache and messaging
The unconventional replacement algorithms
An innovative implementation for directory-based cache coherence in shared memory multiprocessors
Keeping jump instructions out of the pipeline of a RISC-like computer
Network load and traffic pattern on the capacity of wireless ad hoc networks
Book review: Technology Projection Modeling of Future Computer Systems by Al Cutaia (Prentice-Hall, 1990)
A stack addressing scheme based on windowing
Energy efficient Reconfigurable Computing with Adaptive Voltage and Logic scaling
Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms
A virtual memory system for the Hewlett Packard 2100A
The International Computers Ltd. ICL2900 computer architecture
Exploring the Efficiency of the OpenCL Pipe Semantic on an FPGA
A model for recentralization of computing: (distributed processing comes home)
HIBRID-SOC: a multi-core architecture for image and video applications
FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT
An augmented reality system with a coarse-grained reconfigurable device
RSIM: Rice simulator for ILP multiprocessors
Architectural potholes
Scalability of relaxed consistency models in NoC based multicore architectures
Coordinating parallel processors: a partial unification
Representation of arrays in computers
Performance modeling using the Motorola PowerPC timing simulator
Streaming vs.latency in information mass-transit
Roberts: reconfigurable platform for benchmarking real-time systems
Subroutine profiling results for the CPU2006 benchmarks
A SIMD computer for multigrid methods
Truth in SPEC benchmarks
Performance of the HARRIS RTX 2000 Stack Architecture versus the Sun 4 SPARC and the Sun 3 M68020 Architectures
MonteSim: a Monte Carlo performance model for in-order microachitectures
Inthreads: a low granularity parallelization model
An argument against scalable cache coherency
Review of Content addressable parallel processors by Caxton C. Foster. Van Nostrand Reinhold Co. 1976
RISC vector CPU's and crossbars in desktops
The twisted double helix: a minimum distance architecture for 5th generation computing
Book review: Neural Net Applications and Products by Richard K. Miller, Terri C. Walker, and Anne M. Ryan (SEAl Technical Publications, 1990)
On the attributes of the SCISM organization
Exploiting the replication cache to improve cache read bandwidth cost effectively
FPGA implementation of a novel DCT architecture reducing constant cosine terms
Floating point significance interrupt proposal
A multiprocessor configuration in accordance with the aspects of physical and systems design
A computer console design to help the operator
An in-depth look at computer performance growth
Computer architecture at Johns Hopkins
Running algorithms efficiently on faulty hypercubes (extended abstract)
A study of an FPGA based flexible SIMD processor
Improving power efficiency of D-NUCA caches
Power and area optimisation in heterogeneous 3D networks-on-chip architectures
SAMP: a general purpose processor based on a self-timed VLIW structure
A new algorithm for computing triple-base number system
Input/Output considerations in look-ahead processing
Systolic implementations of a move-to-front text compressor
A bidirectional data driven Lisp engine for the direct execution of Lisp in parallel
Automatic parallelization of simulation code for equation-based models with software pipelining and measurements on three platforms
Reconfigurable and hardwired ORB engine on FPGA by Java-to-HDL synthesizer for realtime application
High speed CRC with 64-bit generator polynomial on an FPGA
A comparison of the effect of branch prediction on multithreaded and scalar architectures
Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system
10x10: A Case Study in Highly-Programmable and Energy-Efficient Heterogeneous Federated Architecture
Protected procedure call on the PRIME(TM) machines
Automatic fusions of CUDA-GPU kernels for parallel map
Storage research in industry and universities
Design and evaluation of a distributed asynchronous VLSI crossbar switch controller for a packet switched supercomputer network
Making a case for split data caches for embedded applications
KPN2GPU: an approach for discovery and exploitation of fine-grain data parallelism in process networks
Book review: Computing with Parallel Architectures: T.Node edited by D. Gassilloud and J. C. Grossetie (Kluwer Academic Publishers 1991)
Design team composition for high level language computer architectures
From the other side of the Alantic: how to improve upon the MU5 design
Architectural contesting : exposing and exploiting temperamental behavior
Review of Large-scale computer architecture: parallel and associative processors by Kenneth J. Thurber. Hayden Book Company, Rochelle Park, New Jersey 1976
Parallelization of the channel width search for FPGA routing
A proposal for input-sensitivity analysis of profile-driven optimizations on embedded applications
Coming to grips with a RISC: a report of the progress of the LOW RISC design group
Usenet Nuggets
A hardware implementation of capability-based addressing
Review of Digital system implementation by Gerrit A. Blaauw. Prentice Hall, Series in Automatic Computatin 1976
The challenges of writing portable, correct and high performance libraries for GPUs
Performance counters and development of SPEC CPU2006
Pipelining through Dynamic Control ROM
Data trace cache: an application specific cache architecture
μ-EP-1: a simple 32-bit architecture
ParcBench: a benchmark for shared-memory architectures
Constraint centric scheduling guide
Introduction to the special issue on the 2007 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'07)
Tracing multimedia benchmarks with five degrees of validation
Fixed-point trigonometric functions on FPGAs
A RISCy approach to VLSI
A stream chip-multiprocessor for bioinformatics
An algebraic memory model
The effect of VLSI on computer architecture
HDTrans: a low-overhead dynamic translator
Comparing production system architectures
Puzzling with microcode
Some thoughts on data flow architectures
Future generation supercomputers II: a paradigm for cluster architecture
Some applications of the implicit register reference
Book review: Neural Networks and Fuzzy Systems: A Dynamical Systems Approach to Machine Intelligence by Bart Kosko (Prentice Hall 1992)
An intelligent memory system
Monitoring and diagnosing computer systems by radio communication
Hybrid multi-core architecture for boosting single-threaded performance
A high level simulator integrated with the Mirv compiler
A dynamic binary translation approach to architectural simulation
Energy characterization of embedded real-time operating systems
Combining both microcode and hardwired control in RISC
Dynamic binary control-flow errors detection
A security assessment of the minos architecture
SPIRE: streaming processing with instructions release element
Indirect VLIW memory allocation for the ManArray multiprocessor DSP
A variation on the PDP 11
An analysis of server-based locking
The gem5 simulator
Measurement of I/O bus contention and correlation among heterogeneous device types in a single-bus multiprocessor system
Book review of Logic and logic design by B. Girling and H. G. Morning. International Textbook Company Limited 1973
Providing architectural support for expert systems
The evaluation of expressions in a storage-to-storage architecture
Architectural tradeoff in implementing RSA processors
Performance evaluation of multimedia systems with MPEG-2 bitstreams
Timing on computers
On processes and interrupts
The design and programming of a powerful short wordlength processor using context-dependent machine instructions
A new architecture for FPGA implementation of a MAC unit for digital signal processors using mixed number system
An Efficient GPUAccelerated Implementation of Genomic Short Read Mapping with BWAMEM
Quantification of architectures using software science
The memory wall and the CMOS end-point
A cost-effective reliable multipath interconnection network
Memory bandwidth optimization through stream descriptors
The way forward in computer architecture research
The ultimate ultimate RISC
Compile time instruction cache optimizations
A generalized queue scheme for process synchronization and communication
A performance evaluation of the Intel iAPX 432
Application of the military computer family architecture selection criteria to the PR1ME P400
Performance evaluation of a massively parallel I/O subsystem
Gleipnir: a memory profiling and tracing tool
Speculations on the evolution of an architecture
Leading the design team - the evolution of the technical writer from a support role to a design role
FPGA-based Multicore Architecture for Integrating Multiple DDoS Defense Mechanisms
Persistence in dynamic code transformation systems
An evaluation methodology for microprocessor and system architecture
Talk on interpreters
Using the abstract interpretation technique for static pointer analysis
A minimal CISC
Disjoint Eager Execution: what it is / what it is not
The ultimate RISC
Areatime Efficient Implementation of Local Adaptive Image Thresholding in Reconfigurable Hardware
Panel on future directions in parallel computer architecture
Effects of Stacking Granularity on 3-D Stacked Floating-point Fused Multiply Add Units
A generalized mapping device to help memory latency
Summary of the workshop on frontiers in functional programming and dataflow architecture
On navel contemplation and the art of computer maintenance
Book review: Computer Architecture and Organization, 2nd ed. by John P. Hayes (McGraw Hill, 1988)
A bibliography of local computer network architectures
Configurable string matching hardware for speeding up intrusion detection
Analysis of embedded video coder systems: a system-level approach
Codes to reduce switching transients across VLSI I/O pins
Towards hybrid last level caches for chip-multiprocessors
Fault tolerance in hypercube-derivative networks (preliminary version)