yusuke1997/dblp-id-title huggingface dataset:
Introduction to the Special Issue on BioFoundries and Cloud Laboratories
PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer
Testable cross-power domain interface (CPDI) circuit design in monolithic 3D technology
Energy-Neutral Design Framework for Supercapacitor-Based Autonomous Wireless Sensor Networks
Application-independent defect tolerance of reconfigurable nanoarchitectures
Carbon nanotube transistor compact model for circuit design and performance optimization
Redesign the Memory Allocator for Non-Volatile Main Memory
Resilient and Secure Hardware Devices Using ASL
Placement and Routing for Tile-based Field-coupled Nanocomputing Circuits Is NP -complete (Research Note)
PicoServer: Using 3D stacking technology to build energy efficient servers
Robust In-Field Testing of Digital Microfluidic Biochips
Early Design Space Exploration Framework for Memristive Crossbar Arrays
Hardware Trojan Detection Using Unsupervised Deep Learning on Quantum Diamond Microscope Magnetic Field Images
ULS: A dual- V th /high-kappa nano-CMOS universal level shifter for system-level power management
Design and Multi-Abstraction-Level Evaluation of a NoC Router for Mixed-Criticality Real-Time Systems
An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs
A Noninvasive Technique to Detect Authentic/Counterfeit SRAM Chips
Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM
Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing
Electro-Photonic NoC Designs for Kilocore Systems
MNEMOSENE: Tile Architecture and Simulator for Memristor-based Computation-in-memory
Stochastic Model Checking of Genetic Circuits
SPARCNet: A Hardware Accelerator for Efficient Deployment of Sparse Convolutional Networks
A study of asynchronous design methodology for robust CMOS-nano hybrid system design
Energy-Efficient and Improved Image Recognition with Conditional Deep Learning
Dynamic Cache Pooling in 3D Multicore Processors
NANA: A nano-scale active network architecture
Ultra-low-leakage chip multiprocessor design with hybrid FinFET logic styles
Hardware IP Assurance against Trojan Attacks with Machine Learning and Post-processing
Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things
NBTI tolerance and leakage reduction using gate sizing
SILVerIn: Systematic Integrity Verification of Printed Circuit Board Using JTAG Infrastructure
Reversible logic synthesis with Fredkin and Peres gates
Introduction to Special Issue on Implantable Electronics
Improving AES Core Performance via an Advanced ASBUS Protocol
A Hardware Viewpoint on Biosequence Analysis: What's Next?
Quantifying Irreversible Information Loss in Digital Circuits
Introduction to Special Issue: Asynchrony in System Design
An Algorithm for Quantum Template Matching
A Survey of Architectural Techniques for Near-Threshold Computing
Heterogeneous Scheduling of Deep Neural Networks for Low-power Real-time Designs
Demonstration of a Scalable DNA Computing Platform: Writing and Selection
Evolving dependability
Automated design of pin-constrained digital microfluidic biochips under droplet-interference constraints
Introduction to Special Issue on Bioinformatics
IMFlexCom: Energy Efficient In-Memory Flexible Computing Using Dual-Mode SOT-MRAM
Improving Performance under Process and Voltage Variations in Near-Threshold Computing Using 3D ICs
Neural Network Classifiers Using a Hardware-Based Approximate Activation Function with a Hybrid Stochastic Multiplier
Multilayer stacking technology using wafer-to-wafer stacked method
Power-based Attacks on Spatial DNN Accelerators
Energy-Efficient Neural Computing with Approximate Multipliers
GARDENIA: A Graph Processing Benchmark Suite for Next-Generation Accelerators
CMOS LC voltage controlled oscillator design using multiwalled and single-walled carbon nanotube wire inductors
A physical design tool for carbon nanotube field-effect transistor circuits
Hardware Trojan Horse Detection through Improved Switching of Dormant Nets
Fault-Tolerant Operations for Universal Blind Quantum Computation
An Electro-Photonic System for Accelerating Deep Neural Networks
Scan-chain design and optimization for three-dimensional integrated circuits
Guest Editorial: Trustworthy AI
SkyBridge 2.0: A Fine-grained Vertical 3D-IC Technology for Future ICs
Introduction to nanophotonic communication technology integration
Real-Time and Low-Power Streaming Source Separation Using Markov Random Field
Attack Mitigation of Hardware Trojans for Thermal Sensing via Micro-ring Resonator in Optical NoCs
Identification of Synthesis Approaches for IP/IC Piracy of Reversible Circuits
Design for dependability in emerging technologies
A Rule-Based Design Specification Language for Synthetic Biology
An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer Interconnects
Countering Modeling Attacks in PUF-based IoT Security Solutions
Application and Thermal-reliability-aware Reinforcement Learning Based Multi-core Power Management
On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations
Gated-diode FinFET DRAMs: Device and circuit design-considerations
Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs
Challenges and design choices in nanoscale CMOS
Design Automation and Test Solutions for Monolithic 3D ICs
Language Support for Navigating Architecture Design in Closed Form
Design of Approximate Compressors for Multiplication
A Lightweight Architecture for Hardware-Based Security in the Emerging Era of Systems of Systems
Depth-bounded Graph Partitioning Algorithm and Dual Clocking Method for Realization of Superconducting SFQ Circuits
Integrated Power Signature Generation Circuit for IoT Abnormality Detection
A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing
A Survey on Silicon Photonics for Deep Learning
Designing a Million-Qubit Quantum Computer Using a Resource Performance Simulator
RNNFast: An Accelerator for Recurrent Neural Networks Using Domain-Wall Memory
Nanoscale electronic synapses using phase change devices
Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks
Self-replicating hardware for reliability: The embryonics project
SCALPEL: Exploring the Limits of Tag-enforced Compartmentalization
Characterization of Timing-based Software Side-channel Attacks and Mitigations on Network-on-Chip Hardware
A Modular End-to-End Framework for Secure Firmware Updates on Embedded Systems
A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory
Nanowire-based programmable architectures
FinFET-Based Low-Swing Clocking
A hybrid nano/CMOS dynamically reconfigurable system - Part I: Architecture
MFNW: An MLC/TLC Flip-N-Write Architecture
Design space exploration for 3D architectures
LiwePMS: A Lightweight Persistent Memory with Wear-aware Memory Management
FinFET-Based Power Management for Improved DPA Resistance with Low Overhead
Design Considerations for Memristive Crossbar Physical Unclonable Functions
Computational Capacity of Complex Memcapacitive Networks
Victims Can Be Saviors: A Machine Learning-based Detection for Micro-Architectural Side-Channel Attacks
Permutation Network De-obfuscation: A Delay-based Attack and Countermeasure Investigation
ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors
Defects, Fault Modeling, and Test Development Framework for RRAMs
Organizing wires for reliability in magnetic QCA
A Θ( √ n)-depth quantum adder on the 2D NTC quantum computer architecture
Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture
Spin-transfer torque magnetic random access memory (STT-MRAM)
A Fast Extraction Algorithm for Defect-Free Subcrossbar in Nanoelectronic Crossbar
Energy- and performance-aware scheduling of tasks on parallel and distributed systems
DAHM: A green and dynamic web application hosting manager across geographically distributed data centers
A Synthesis Algorithm for 4-Bit Reversible Logic Circuits with Minimum Quantum Cost
A Deep Neural Network Accelerator using Residue Arithmetic in a Hybrid Optoelectronic System
Cryptography with Analog Scheme Using Memristors
Relativistic Causality and Clockless Circuits
Design and Analysis of a Robust Carbon Nanotube-Based Asynchronous Primitive Circuit
Hardware Trojan Detection Using the Order of Path Delay
Reducing Power Consumption of Lasers in Photonic NoCs through Application-Specific Mapping
Quit When You Can: Efficient Evaluation of Ensembles by Optimized Ordering
DeepPeep: Exploiting Design Ramifications to Decipher the Architecture of Compact DNNs
Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design
Design of Adiabatic Logic-Based Energy-Efficient and Reliable PUF for IoT Devices
Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits
Hypercolumn Sparsification for Low-Power Convolutional Neural Networks
Guest Editors Introduction: Special Issue on Network-on-Chip Architectures of the Future (NoCArc)
SCT: A novel approach for testing and configuring nanoscale devices
Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization
Accurate Leakage/Delay Estimation for FinFET Standard Cells under PVT Variations using the Response Surface Methodology
Iris: A hybrid nanophotonic network design for high-performance and low-power on-chip communication
Efficient Hardware Implementation of Cellular Neural Networks with Incremental Quantization and Early Exit
Rethinking Computer Architectures and Software Systems for Phase-Change Memory
Performance and Energy Impact of Locally Controlled NML Circuits
Fusing In-storage and Near-storage Acceleration of Convolutional Neural Networks
Dynamic Reliability Management in Neuromorphic Computing
Computing Polynomials Using Unipolar Stochastic Logic
Reliability Hardening Mechanisms in Cyber-Physical Digital-Microfluidic Biochips
Clock-Tree Synthesis with Methodology of Reuse in 3D-IC
Process Variability and Electrostatic Analysis of Molecular QCA
Integrated droplet routing and defect tolerance in the synthesis of digital microfluidic biochips
Introduction to the special issue on sustainable and green computing systems
Online Adaptation and Energy Minimization for Hardware Recurrent Spiking Neural Networks
Statistical Optimization of FinFET Processor Architectures under PVT Variations Using Dual Device-Type Assignment
Formalizing Modularization and Data Hiding in Synthetic Biology
An Integrated Nanophotonic Parallel Adder
Designing Garbage-Free Reversible Implementations of the Integer Cosine Transform
Simulation of random cell displacements in QCA
Integrated High-Speed Optical SerDes over 100GBd Based on Optical Time Division Multiplexing
Hardware Optimizations of Dense Binary Hyperdimensional Computing: Rematerialization of Hypervectors, Binarized Bundling, and Combinational Associative Memory
A Survey on Memory-centric Computer Architectures
A Cost-Efficient Digital ESN Architecture on FPGA for OFDM Symbol Detection
Guest Editorial: Special Issue on Advances in Design of Ultra-Low Power Circuits and Systems in Emerging Technologies
PUF-based Digital Money with Propagation-of-Provenance and Offline Transfers between Two Parties
Fluigi: Microfluidic Device Synthesis for Synthetic Biology
QuTiBench: Benchmarking Neural Networks on Heterogeneous Hardware
Parametric yield management for 3D ICs: Models and strategies for improvement
Exploring Dynamic Redundancy to Resuscitate Faulty PCM Blocks
Survey of STT-MRAM Cell Design Strategies: Taxonomy and Sense Amplifier Tradeoffs for Resiliency
A Cross-Layer Approach to Measure the Robustness of Integrated Circuits
Digital Fault-based Built-in Self-test and Evaluation of Low Dropout Voltage Regulators
A Practical Shared Optical Cache With Hybrid MWSR/R-SWMR NoC for Multicore Processors
SHARP: Shared Heterogeneous Architecture with Reconfigurable Photonic Network-on-Chip
Toward the Generation of Test Vectors for the Detection of Hardware Trojan Targeting Effective Switching Activity
STIFT: A Spatio-Temporal Integrated Folding Tree for Efficient Reductions in Flexible DNN Accelerators
Large-Scale Spiking Neural Networks using Neuromorphic Hardware Compatible Models
Semi-Trained Memristive Crossbar Computing Engine with In Situ Learning Accelerator
Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory
Interpreting Assays with Control Flow on Digital Microfluidic Biochips
Formal methods for the analysis and synthesis of nanometer-scale cellular arrays
Polyhedral-Based Compilation Framework for In-Memory Neural Network Accelerators
Job completion time on a virtualized server with software rejuvenation
SaARSP: An Architecture for Systolic-Array Acceleration of Recurrent Spiking Neural Networks
GPUOPT: Power-efficient Photonic Network-on-Chip for a Scalable GPU
High parallelism, portability, and broad accessibility: Technologies for genomics
STT-MRAM-Based PUF Architecture Exploiting Magnetic Tunnel Junction Fabrication-Induced Variability
Towards Compact Modeling of Noisy Quantum Computers: A Molecular-Spin-Qubit Case of Study
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip
A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits
Trading Accuracy for Energy in Stochastic Circuit Design
Composable Probabilistic Inference Networks Using MRAM-based Stochastic Neurons
Delay-based processing-in-wire for design of QCA serial decimal arithmetic units
AroMa: Evaluating Deep Learning Systems for Stealthy Integrity Attacks on Multi-tenant Accelerators
Fully Exploiting PCM Write Capacity Within Near Zero Cost Through Segment-Based Page Allocation
Complex network-enabled robust wireless network-on-chip architectures
MiC: Multi-level Characterization and Optimization of GPGPU Kernels
Energy-efficient FPGA Spiking Neural Accelerators with Supervised and Unsupervised Spike-timing-dependent-Plasticity
Network-on-Chip Intellectual Property Protection Using Circular Path-based Fingerprinting
A Scalable Cluster-based Hierarchical Hardware Accelerator for a Cortically Inspired Algorithm
Towards Energy-Efficient Spiking Neural Networks: A Robust Hybrid CMOS-Memristive Accelerator
Error-Aware Training for In-RRAM Computing Design Considering Non-Ideal Effects in RRAM Crossbar Array and Peripheral Circuits
A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits
Hardware and Software Co-optimization for the Initialization Failure of the ReRAM-based Cross-bar Array
Design of efficient reversible logic-based binary and BCD adder circuits
SPLIT PUF: Efficient PUF Implementation Using Underutilized FPGA Resource
FPIC: A Novel Semantic Dataset for Optical PCB Assurance
Predictive technology model for nano-CMOS design exploration
LosPem: A Novel Log-Structured Framework for Persistent Memory
QCOR: A Language Extension Specification for the Heterogeneous Quantum-Classical Model of Computation
Hardware Trojan Attack in Embedded Memory
Thread Batching for High-performance Energy-efficient GPU Memory Design
Sketching Computation with Stochastic Processing Engines
High-level Modeling and Verification Platform for Elastic Circuits with Process Variation Considerations
Probabilistic modeling and analysis of molecular memory
Real-Time Anomaly Detection Framework for Many-Core Router through Machine-Learning Techniques
Taming Molecular Field-Coupling for Nanocomputing Design
PPU: A Control Error-Tolerant Processor for Streaming Applications with Formal Guarantees
Sorting in Memristive Memory
Theory and analysis of generalized mixing and dilution of biochemical fluids using digital microfluidic biochips
Temporal State Machines: Using Temporal Memory to Stitch Time-based Graph Computations
Implantable Closed-Loop Epilepsy Prosthesis: Modeling, Implementation and Validation
Emerging Technology-Based Design of Primitives for Hardware Security
Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes
An efficient heuristic to identify threshold logic functions
A Process-Variation-Tolerant Method for Nanophotonic On-Chip Network
SWIFTNoC: A Reconfigurable Silicon-Photonic Network with Multicast-Enabled Channel Sharing for Multicore Architectures
Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories
A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays
Hardware Trojan Detection Potential and Limits with the Quantum Diamond Microscope
Improved Threshold Logic Synthesis Using Implicant-Implicit Algorithms
Graphene-Based Artificial Synapses with Tunable Plasticity
An energy management framework for energy harvesting embedded systems
Sparse Hardware Embedding of Spiking Neuron Systems for Community Detection
Higher Dimension Quantum Entanglement Generators
Spatial and temporal thermal characterization of stacked multicore architectures
Dynamically Adapting Page Migration Policies Based on Applications' Memory Access Behaviors
A thermal-driven test application scheme for pre-bond and post-bond scan testing of three-dimensional ICs
Special Issue on Emerging Many-Core Systems for Exascale Computing
Optimized Standard Cells for All-Spin Logic
Design-time Reference Current Generation for Robust Spintronic-based Neuromorphic Architecture
Garbage-Free Reversible Multipliers for Arbitrary Constants
A Multi-Level-Optimization Framework for FPGA-Based Cellular Neural Network Implementation
Molecular QCA design with chemically reasonable constraints
An Implantable Release-on-Demand CMOS Drug Delivery SoC Using Electrothermal Activation Technique
CONCEALING-Gate: Optical Contactless Probing Resilient Design
Color image processing with multi-peak resonant tunneling diodes
A Review and Comparison of AI-enhanced Side Channel Analysis
Design of False Data Injection Attacks in a Cyber-Physical System Using Gaussian Distribution
A ReRAM Memory Compiler for Monolithic 3D Integrated Circuits in a Carbon Nanotube Process
PEAL: Probabilistic Error Analysis Methodology for Low-power Approximate Adders
An FPGA Implementation of a Time Delay Reservoir Using Stochastic Logic
A Holistic Solution for Reliability of 3D Parallel Systems
A Quantum Computing Performance Simulator Based on Circuit Failure Probability and Fault Path Counting
High-level synthesis of digital microfluidic biochips
Diverse, Neural Trojan Resilient Ecosystem of Neural Network IP
DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices
Resilient and adaptive performance logic
Mitigate Parasitic Resistance in Resistive Crossbar-based Convolutional Neural Networks
Effect of the Active Layer on Carbon Nanotube-Based Cells for Yield Analysis
Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators
CosMoS: Architectural Support for Cost-Effective Data Movement in a Disaggregated Memory Systems
Silicon Photonics for Computing Systems
A Sub-μ A Stand-By Current Synchronous Electric Charge Extractor for Piezoelectric Energy Harvesting
Analytical Reliability Analysis of 3D NoC under TSV Failure
Multiple fault diagnosis in digital microfluidic biochips
Timing-Optimized Hardware Implementation to Accelerate Polynomial Multiplication in the NTRU Algorithm
Direction-aggregated Attack for Transferable Adversarial Examples
Spike-Time-Dependent Encoding for Neuromorphic Processors
Energy-Efficiency Comparison of Multi-Layer Deposited Nanophotonic Crossbar Interconnects
Guest Editorial: ACM JETC Special Issue on Hardware-Aware Learning for Medical Applications
Brownian Circuits: Fundamentals
Frontside Versus Backside Laser Injection: A Comparative Study
Design and Evaluation of Technology-Agnostic Heterogeneous Networks-on-Chip
All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin Circuits
Towards Synaptic Behavior of Nanoscale ReRAM Devices for Neuromorphic Computing Applications
Introduction to: Special Issue on Cross-Layer System Design
A Memristor-Based Compressive Sampling Encoder with Dynamic Rate Control for Low-Power Video Streaming
Hardware Trust and Assurance through Reverse Engineering: A Tutorial and Outlook from Image Analysis and Machine Learning Perspectives
Editorial to special issue DAC 2006
SCKVdd: A Scalable Clock-Controlled Self-Stabilized Voltage Technique for Low Power CMOS Digital Circuits
Guest Editors' Introduction to the Special Section on Hardware and Algorithms for Energy-Constrained On-chip Machine Learning
Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations: Observing the Trends between the 22nm and 14nm Technology Nodes
Resource-Constrained Scheduling for Digital Microfluidic Biochips
Design considerations of sub-mW indoor light energy harvesting for wireless sensor systems
Large-scale integrated photonics for high-performance interconnects
Introduction to the Special Issue on Reversible Computation
Reliability improvement of logic and clock paths in power-efficient designs
Deep Neural Network Optimized to Resistive Memory with Nonlinear Current-Voltage Characteristics
Towards achieving reliable and high-performance nanocomputing via dynamic redundancy allocation
Early History and Challenges of Implantable Electronics
Breaking On-Chip Communication Anonymity Using Flow Correlation Attacks
Design Considerations for Multilevel CMOS/Nano Memristive Memory
Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs
Special section on new circuit and architecture-level solutions for multidiscipline systems
ChaoticImmuneNet: A Chaos-driven Immunity Inspired Neural Network Paradigm for Embodied Intelligence in Resource-Constrained Devices
SSS: Self-aware System-on-chip Using a Static-dynamic Hybrid Method
Eternal-thing 2.0: Analog-Trojan-resilient Ripple-less Solar Harvesting System for Sustainable IoT
Low-Power Heterogeneous Graphene Nanoribbon-CMOS Multistate Volatile Memory Circuit
Introduction to special issue on WoSAR 2011
Integration of Literature with Heterogeneous Information for Genes Correlation Scoring
On-the-fly Page Migration and Address Reconciliation for Heterogeneous Memory Systems
Yield enhancement of reconfigurable microfluidics-based biochips using interstitial redundancy
Lotus: A New Topology for Large-scale Distributed Machine Learning
Integrated control-path design and error recovery in the synthesis of digital microfluidic lab-on-chip
Data structures and algorithms for simplifying reversible circuits
A Learning-Based Thermal-Sensitive Power Optimization Approach for Optical NoCs
A Comparative Cross-layer Study on Racetrack Memories: Domain Wall vs Skyrmion
Automated design flow for diode-based nanofabrics
Design and Analysis of FPGA-based PUFs with Enhanced Performance for Hardware-oriented Security
A Novel Algorithm for Fast Synthesis of DNA Probes on Microarrays
Fortifying Vehicular Security through Low Overhead Physically Unclonable Functions
Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model
Low-overhead defect tolerance in crossbar nanoarchitectures
A Chip-Level Anti-Reverse Engineering Technique
Microarchitectural Transformations Using Elasticity
Introduction to Special Issue: Highlights of NANOARCH'09
A Reconfigurable Multiplier for Signed Multiplications with Asymmetric Bit-Widths
Coupled Spin-Torque Nano-Oscillator-Based Computation: A Simulation Study
Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method
Guest Editors' Introduction: Hardware and Algorithms for Energy-Constrained On-Chip Machine Learning (Part 2)
Guest Editorial: Secure Radio-Frequency (RF)-Analog Electronics and Electromagnetics
QLib: Quantum module library
Repercussions of Using DNN Compilers on Edge GPUs for Real Time and Safety Critical Systems: A Quantitative Audit
Making a Case for Partially Connected 3D NoC: NFIC versus TSV
A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs
Secure and Lightweight Authentication Protocol Using PUF for the IoT-based Wireless Sensor Network