yusuke1997/dblp-id-title huggingface dataset:
Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence
Multi-Layer Interdigitated Power Distribution Networks
A High-Level Design Framework for the Automatic Generation of High-Throughput Systolic Binomial-Tree Solvers
DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis
The yield enhancement of field-programmable gate arrays
A New Single-Ended SRAM Cell With Write-Assist
Exact Distribution of the Max/Min of Two Gaussian Random Variables
Speed and area tradeoffs in cluster-based FPGA architectures
Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology
A Reconfigurable 2×2.5×3×4× SC DC-DC Regulator With Fixed On-Time Control for Transcutaneous Power Transmission
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces
System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip
A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18-µm CMOS
Cell-Based Process Resilient Multiphase Clock Generation
Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs
RPkNN: An OpenCL-Based FPGA Implementation of the Dimensionality-Reduced kNN Algorithm Using Random Projection
Sequential circuit testability enhancement using a nonscan approach
Direct Period Synthesis for Achieving Sub-PPM Frequency Resolution Through Time Average Frequency: The Principle, The Experimental Demonstration, and Its Application in Digital Communication
Diagnosis of MRAM Write Disturbance Fault
Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping
DCG: deterministic clock-gating for low-power microprocessor design
Efficient Decompression of Binary Encoded Balanced Ternary Sequences
Solving covering problems using LPR-based lower bounds
An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering
Low-Power, Minimally Invasive Process Compensation Technique for Sub-Micron CMOS Amplifiers
Single Cycle Access Structure for Logic Test
Variation-Aware Aging Analysis in Digital ICs
PSR Enhancement Through Super Gain Boosting and Differential Feed-Forward Noise Cancellation in a 65-nm CMOS LDO Regulator
A Novel Design Approach and VLSI Architecture of Rationalized Bi-Orthogonal Wavelet Filter Banks
Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis
Figures-of-Merit to Evaluate the Significance of Switching Noise in Analog Circuits
Corrections to "Crosstalk-Canceling Multimode Interconnect Using Transmitter Encoding"
C-Based Complex Event Processing on Reconfigurable Hardware
Power-Planning-Aware Soft Error Hardening via Selective Voltage Assignment
architect: Arbitrary-Precision Hardware With Digit Elision for Efficient Iterative Compute
High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-1
Power and Bandwidth Scalable 10-b 30-MS/s SAR ADC
Design for Test and Hardware Security Utilizing Retention Loss of Memristors
Architectural and compiler techniques for energy reduction in high-performance microprocessors
A new architecture for the automatic design of custom digital neural network
A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array
A Trifilar Transformer-Based Class-F 23 VCO With Noise-Circulating Technology
Model-Based Study on the Limit of the Dynamic Load Regulation Performance of a Digital Low Dropout Regulator
Editorial First TVLSI Best AE and Reviewer Awards
A Parasitic and Mismatch Tolerant Fully Common-Centroided and Shielded Split-CDAC With Identical Unit Capacitors for SAR-ADC
"It's a small world after all": NoC performance optimization via long-range link insertion
Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing
Power estimation of embedded systems: a hardware/software codesign approach
Registers for Phase Difference Based Logic
Fault Bounding On-Die BCH Codes for Improving Reliability of System ECC
Small area parallel Chien search architectures for long BCH codes
Concurrent fault simulation on message passing multicomputers
Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs
An Area-Efficient, Conflict-Free, and Configurable Architecture for Accelerating NTT/INTT
Zero-aware asymmetric SRAM cell for reducing cache power in writing zero
All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation
Time-Domain CMOS Temperature Sensors With Dual Delay-Locked Loops for Microprocessor Thermal Monitoring
Low Power and High Speed Multi Threshold Voltage Interface Circuits
EBSCam: Background Subtraction for Ubiquitous Computing
Go/No-Go Testing of VCO Modulation RF Transceivers Through the Delayed-RF Setup
C-testable design techniques for iterative logic arrays
A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator
Effective Parallel Redundancy Analysis Using GPU for Memory Repair
Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis
Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic
ADC-Less Reprogrammable RRAM Array Architecture for In-Memory Computing
VLSI Design of a Large-Number Multiplier for Fully Homomorphic Encryption
Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors
A High Throughput List Decoder Architecture for Polar Codes
Multi-Pattern $n$-Detection Stuck-At Test Sets for Delay Defect Coverage
The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies
On-line fault detection for bus-based field programmable gate arrays
Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput
Efficiency Optimization of Voltage-Mode CMOS Digital Doherty Power Amplifiers
A Novel Matchline Scheduling Method for Low-Power and Reliable Search Operation in Cross-Point-Array Nonvolatile Ternary CAM
Application Space Exploration of a Heterogeneous Run-Time Configurable Digital Signal Processor
Logic Design Partitioning for Stacked Power Domains
UNISM: Unified Scheduling and Mapping for General Networks on Chip
FPGA routing and routability estimation via Boolean satisfiability
Adaptive Precision Cellular Nonlinear Network
A Multiband VCO Using a Switched Series Resonance for Fine Frequency Tuning Sensitivity and Phase Noise Improvement
Fault-Aware Dependability Enhancement Techniques for Flash Memories
Relative timing [asynchronous design]
Reconfigurable VLSI architectures for evolvable hardware: from experimental field programmable transistor arrays to evolution-oriented chips
In-DRAM Data Initialization
Efficient Mixed-Signal Neurocomputing Via Successive Integration and Rescaling
A multiple clocking scheme for low-power RTL design
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation
ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration
1.2 V 10-bit 75 MS/s Pipelined ADC With Phase-Dependent Gain-Transition CDS
FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks With Efficient DSP and Memory Optimization
Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors
Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems
Architecture-Level Thermal Characterization for Multicore Microprocessors
Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process
Modeling skin and proximity effects with reduced realizable RL circuits
Statistical analysis of subthreshold leakage current for VLSI circuits
Embedding Repeaters in Silicon IPs for Cross-IP Interconnections
Synthesis of Approximate Parallel-Prefix Adders
High-Volume Testing and DC Offset Trimming Technique of On-Die Bandgap Voltage Reference for SOCs and Microprocessors
A Blockchain-Based Privacy-Preserving Authentication Scheme for VANETs
Performance improvement technique for synchronous circuits realized as LUT-based FPGAs
ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling
Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm
Linear and Switch-Mode Conversion in 3-D Circuits
DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits
An Energy-Efficient Pipelined-Multiprocessor Architecture for Biological Sequence Alignment
Distributed Pass Gates in Power Delivery Systems With Digital Low-Dropout Regulators
PVHArray: An Energy-Efficient Reconfigurable Cryptographic Logic Array With Intelligent Mapping
Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction
Design of Self-Timed Reconfigurable Controllers for Parallel Synchronization via Wagging
TAO: regular expression-based register-transfer level testability analysis and optimization
HVS-Aware Dynamic Backlight Scaling in TFT-LCDs
High-efficiency multiple-output DC-DC conversion for low-voltage systems
VLSI Implementation of an Edge-Oriented Image Scaling Processor
A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security
Scaling Energy Per Operation via an Asynchronous Pipeline
Dummy Faulty Units for Reduced Fail Data Volume From Logic Faults
High-Throughput Ring-LWE Cryptoprocessors
A high-performance VLSI architecture for the histogram peak-climbing data clustering algorithm
A Design Framework for Generating Energy-Efficient Accelerator on FPGA Toward Low-Level Vision
A Process-Adaptive Cell-Based Cyclic Time-to-Digital Converter Using One-Way Varactor Cells
Test Compaction by Sharing of Functional Test Sequences Among Logic Blocks
Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator
Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority
A Dual-Mode Buck Converter with Light-Load Efficiency Improvement and Seamless Mode Transition Technique
Segmented Virtual Ground Architecture for Low-Power Embedded SRAM
FELIX: FPGA-Based Scalable and Lightweight Accelerator for Large Integer Extended GCD
SFANC: Scalable and Flexible Architecture for Neuromorphic Computing
Optimal and Efficient Algorithms for Multidomain Clock Skew Scheduling
Racetrack Queues for Extremely Low-Energy FIFOs
Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains
Heterogeneous architecture models for interconnect-motivated system design
General gate array routing using a k-terminal net routing algorithm with failure prediction
A Fast Fault-Tolerant Architecture for Sauvola Local Image Thresholding Algorithm Using Stochastic Computing
Golden Reference-Free Hardware Trojan Localization Using Graph Convolutional Network
Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing
Built-In Self-Test of SFQ Circuits Using Side-Channel Leakage Information
A 22-nm 264-GOPS/mm 2 6T SRAM and Proportional Current Compute Cell-Based Computing-in-Memory Macro for CNNs
Scalable Hierarchical Instruction Cache for Ultralow-Power Processors Clusters
A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory
Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations
Impact of Selector Devices in Analog RRAM-Based Crossbar Arrays for Inference and Training of Neuromorphic System
Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS
CMOS Transimpedance Amplifier for Visible Light Communications
Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design
Prediction and Comparison of High-Performance On-Chip Global Interconnection
A Robust 4-PAM Signaling Scheme for Inter-Chip Links Using Coding in Space
On Reducing Hidden Redundant Memory Accesses for DSP Applications
Fixation Ratio of Error Location-Aware Strategy for Increased Reliable Retention Time of Flash Memory
Dynamic Challenge Cross-Selection Physical Unclonable Function Based on MRAM
High Fill Factor Low-Voltage CMOS Image Sensor Based on Time-to-Threshold PWM VLSI Architecture
Fixed-State Tests for Delay Faults in Scan Designs
Multiple-symbol parallel decoding for variable length codes
Test Primitives: The Unified Notation for Characterizing March Test Sequences
A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits
Rapid estimation for parameterized components in high-level synthesis
CMOS current steering logic for low-voltage mixed-signal integrated circuits
Delta-Sigma Modulation for Direct Digital Frequency Synthesis
A TSV Misalignment-Based Repair Architecture in 3-D Chips
All-Digital CMOS Time-to-Digital Converter With Temperature-Measuring Capability
Bitstream Database-Driven FPGA Programming Flow Based on Standard OpenCL
Hierarchical design space exploration for a class of digital systems
Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM
A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store
CLAP: Clustered Look-Ahead Prefetching for Energy-Efficient DRAM System
CMCS: Current-Mode Clock Synthesis
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS
Inkjet-Printed EGFET-Based Physical Unclonable Function - Design, Evaluation, and Fabrication
Assessing Trends in Performance per Watt for Signal Processing Applications
Zero-Power Feed-Forward Spur Cancelation for Supply-Regulated CMOS Ring PLLs
Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC
MOL-Based In-Memory Computing of Binary Neural Networks
Low Cost Hardware Implementation of Logarithm Approximation
A 0.5-V Multiple-Input Bulk-Driven OTA in 0.18-μm CMOS
Low Cost MIMO Testing for RF Integrated Circuits
Defect-oriented test scheduling
Dual Use of Power Lines for Design-for-Testability - A CMOS Receiver Design
Global Analysis of C Concurrency in High-Level Synthesis
Contiguity Representation in Page Table for Memory Management Units
Reconfigurable 10T SRAM for Energy-Efficient CAM Operation and In-Memory Computing
Approximate Sum-of-Products Designs Based on Distributed Arithmetic
Loop Acceleration Exploration for ASIP Architecture
Ultra-low-power DLMS adaptive filter for hearing aid applications
BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing Under High Temperature
A Low-Power DSP for Wireless Communications
An XGBoost-Based Method for Predicting the Location of MIV Open Fault
Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture
Applying Effective Dynamic Frequency Scaling Method in Contactless Smart Card
Performance improvement of geographically distributed cosimulation by hierarchically grouped messages
Exploiting statistical information for implementation of instruction scratchpad memory in embedded system
On the Functional Test of Branch Prediction Units
Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies
Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators
Fighting Dark Silicon: Toward Realizing Efficient Thermal-Aware 3-D Stacked Multiprocessors
Design of a static MIMD data flow processor using micropipelines
High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers
High-Efficiency Soft-Error-Tolerant Digital Signal Processing Using Fine-Grain Subword-Detection Processing
System-Level Specification Testing Of Wireless Transceivers
A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA
Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits
A new approach to built-in self-testable datapath synthesis based on integer linear programming
A nMOS-R Cross-Coupled Level Shifter With High dV/dt Noise Immunity for 600-V High-Voltage Gate Driver IC
Low-Complexity Implementation of Real-Time Reconfigurable Low-Pass Equalizers
A nonredundant ternary CAM circuit for network search engines
An Operation and Interconnection Sharing Algorithm for Reconfiguration Overhead Reduction Using Static Partial Reconfiguration
Novel Offset Techniques for Improving Bitstring Quality of a Hardware-Embedded Delay PUF
Practical Implementation of Multichannel Filtered-x Least Mean Square Algorithm Based on the Multiple-Parallel-Branch With Folding Architecture for Large-Scale Active Noise Control
FLAT: Layout-Aware and Security Property-Assisted Timing Fault-Injection Attack Assessment
Pipelined Parallel FFT Architectures via Folding Transformation
Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor
Chip-Specific Power Delivery and Consumption Co-Management for Process-Variation-Aware Manycore Systems Using Reinforcement Learning
Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models
Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs
Hybrid Accumulator Factored Systolic Array for Machine Learning Acceleration
Single-Ended/Differential Wideband Track-and-Hold Amplifier in 22-nm FD-SOI CMOS Process
Cross-Layer Approximate Design of Low-Power Fractional Motion Estimation Accelerators for VVC
A Discrete-Time MOS Parametric Amplifier-Based Chopped Signal Demodulator
Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications
Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits
Dynamic fault dictionaries and two-stage fault isolation
A Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs
High-Speed Dynamic Asynchronous Pipeline: Self-Precharging Style
Interconnect-Based PUF With Signature Uniqueness Enhancement
A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits
An Energy-Efficient Block-Based Nonmaximum Suppression Engine for High-Parallel Postprocessing of Visual Object Detection
Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors
Resource requirements and layouts for field programmable interconnection chips
Transformations and resynthesis for testability of RT-level control-data path specifications
Ekho: A 30.3W, 10k-Channel Fully Digital Integrated 3-D Beamformer for Medical Ultrasound Imaging Achieving 298M Focal Points per Second
Timestamp-Based Secure Shield Architecture for Detecting Invasive Attacks
Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays
A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex Caches
MSDF-Based MAC for Energy-Efficient Neural Networks
FSpGEMM: A Framework for Accelerating Sparse General Matrix-Matrix Multiplication Using Gustavson's Algorithm on FPGAs
Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory
Line coverage of path delay faults
A Sparse CNN Accelerator for Eliminating Redundant Computations in Intra- and Inter-Convolutional/Pooling Layers
Algorithms and bounds for layer assignment of MCM routing
Power optimization of core-based systems by address bus encoding
A unified design methodology for CMOS tapered buffers
Thermal Management of Batteries Using Supercapacitor Hybrid Architecture With Idle Period Insertion Strategy
Customizable elliptic curve cryptosystems
TVF: A Metric for Quantifying Vulnerability Against Hardware Trojan Attacks
Architecture of Ring-Based Redundant TSV for Clustered Faults
QPA: A Quantization-Aware Piecewise Polynomial Approximation Methodology for Hardware-Efficient Implementations
Low-Leakage Storage Cells for Ternary Content Addressable Memories
Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA
Efficient Warranty-Aware Wear Leveling for Embedded Systems With PCM Main Memory
Variation-Aware Delay Fault Testing for Carbon-Nanotube FET Circuits
A Security-Enhanced, Charge-Pump-Free, ISO14443-A-/ISO10373-6-Compliant RFID Tag With 16.2-μW Embedded RRAM and Reconfigurable Strong PUF
A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications
Experiments with low-level speculative computation based on multiple branch prediction
Fuer Chris H. Kim 2 Eintraege in Db, Chris H. Kim und Chris Kim. Identisch. Siehe EE-Links: Univ. of Minnesota. Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply Integrity
Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects
A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer With Integrated Transformer-Based Gate Inductor and IM2 Injection Technique
Analysis Towards Minimization of Total SRAM Energy Over Active and Idle Operating Modes
A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K
A Multiring Julia Fractal Chaotic System With Separated-Scroll Attractors
Customization of Arbitration Policies and Buffer Space Distribution Using Continuous-Time Markov Decision Processes
A 285-nA Quiescent Current, 94.7% Peak Efficiency Buck Converter With AOT Control for IoT Application
High-Throughput Trellis Processor for Multistandard FEC Decoding
A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS
A 22-nm All-Digital Time-Domain Neural Network Accelerator for Precision In-Sensor Processing
A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications
Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications
Modeling and Experimental Verification of Misalignment Tolerance in Inductive-Coupling Inter-Chip Link for Low-Power 3-D System Integration
Realistic and efficient simulation of electro-thermal effects in VLSI circuits
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect
Analog Layout Retargeting With Process-Variation-Aware Hybrid OPC
A new, cellular automaton-based, nearest neighbor pattern classifier and its VLSI implementation
A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip-Flops With Embedded Logic
A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches
ADIC: Anomaly Detection Integrated Circuit in 65-nm CMOS Utilizing Approximate Computing
FPUx: High-Performance Floating-Point Support for Cost-Constrained RISC-V Cores
Floating-Point FPGA: Architecture and Modeling
A 14 μJ/Decision Keyword-Spotting Accelerator With In-SRAMComputing and On-Chip Learning for Customization
Extraction of VLSI Multiconductor Transmission Line Parameters by Complementarity
A CMOS PWM Transceiver Using Self-Referenced Edge Detection
A Generic Scalable Architecture for Min-Sum/Offset-Min-Sum Unit for Irregular/Regular LDPC Decoder
A Design-for-Digital-Testability Circuit Structure for Sigma-Delta Modulators
Low-power high-performance nand match line content addressable memories
Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory
Grammar-based hardware synthesis from port-size independent specifications
A Review of IC Drivers for VCSELs in Datacom Applications
Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization and Voltage Scaling
Low-power design of decimation filters for a digital IF receiver
Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors
Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip
A Hybrid Stochastic-Binary Computing Batch Normalization Engine for Low-Power On-Chip Learning Spiking Neural Networks
Wave steering to integrate logic and physical syntheses
Design techniques and test methodology for low-power TCAMs
An Implementation of Reconfigurable Match Table for FPGA-Based Programmable Switches
46-nA High-PSR CMOS Buffered Voltage Reference With 1.2-5 V and -40 ◦ C to 125 ◦ C Operating Range
Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing
Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures
Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units
Design of a Low-Voltage Low-Dropout Regulator