yusuke1997/dblp-id-title huggingface dataset:
A Detailed Router Based on Incremental Routing Modifications: Mighty
Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation
A framework for comparing models of computation
Gate-length biasing for runtime-leakage control
Application-driven synthesis of memory-intensive systems-on-chip
On Reducing LDE Variations in Modern Analog Placement
ApproxDup: Developing an Approximate Instruction Duplication Mechanism for Efficient SDC Detection in GPGPUs
Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements
AROMA: An Area Optimized CAD Program for Cascade SC Filter Design
Replacement Policy Adaptable Miss Curve Estimation for Efficient Cache Partitioning
Leveraging Datapath Propagation in IC3 for Hardware Model Checking
MUSE: a multilevel symbolic encoding algorithm for state assignment
Optimization of Dilution and Mixing of Biochemical Samples Using Digital Microfluidic Biochips
VTSMOC: An Efficient Voronoi Tree Search Boosted Multiobjective Bayesian Optimization With Constraints for High-Dimensional Analog Circuit Synthesis
An analysis of fault partitioned parallel test generation
Modeling delay and noise in arbitrarily coupled RC trees
Synthesis of mm-Wave Wideband Receivers in 28-nm CMOS Technology for Automotive Radar Applications
Test-Cost Modeling and Optimal Test-Flow Selection of 3-D-Stacked ICs
Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization
Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug
A rapid, stable decoupled algorithm for solving semiconductor hydrodynamic equations
NeRF-PIM: PIM Hardware-Software Co-Design of Neural Rendering Networks
Automatic Generation of Differential-Input Differential-Output Second-Order Filters Based on a Differential Pair
Design of built-in test generator circuits using width compression
A Novel Approach for Using TSVs As Membrane Capacitance in Neuromorphic 3-D IC
Timed Boolean calculus and its applications in timing analysis
Microprocessors functional testing techniques
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications
Identification of primitive faults in combinational and sequentialcircuits
A Pattern Recognition Based Method for IC Failure Analysis
The ellipsoidal technique for design centering and region approximation
REDUSA: module generation by automatic elimination of superfluous blocks in regular structures
BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips
A new aggregation technique for the solution of large systems of algebraic equations [IC simulation]
Integration of Traveling Wave Optical Device Models Into an MNA-Based Circuit Simulator
Publicly detectable watermarking for intellectual property authentication in VLSI design
Diagnosing arbitrary defects in logic designs using single location at a time (SLAT)
FTCD: Fault-Tolerant Co-Design of Flow and Control Layers for Fully Programmable Valve Array Biochips
Generation of Compact Stuck-At Test Sets Targeting Unmodeled Defects
Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization
RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy
A Cost Effective Approach for Online Error Detection Using Invariant Relationships
IVQ: In-Memory Acceleration of DNN Inference Exploiting Varied Quantization
Pad minimization for planar routing of multiple power nets
Generalized Manhattan path algorithm with applications
Nonisothermal device simulation using the 2D numerical process/device simulator TRENDY and application to SOI-devices
TSV-Based 3-D ICs: Design Methods and Tools
Power-Aware Runtime Scheduler for Mixed-Criticality Systems on Multicore Platform
GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists
NGLIC: A Nonaligned-Row Legalization Approach for 3-D Interdie Connection
COP: a Crosstalk OPtimizer for gridded channel routing
Zone scheduling
OS-Level PMC-Based Runtime Thermal Control for ARM Mobile CPUs
An Effective Algorithm for Buffer Insertion in General Circuits Based on Network Flow
Constraint Solving for Synthesis and Verification of Threshold Logic Circuits
HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS
Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy
Buffer planning as an Integral part of floorplanning with consideration of routing congestion
Formal Hardware/Software Co-Verification of Embedded Power Controllers
A heuristic standard cell placement algorithm using constrained multistage graph model
Optimizing a Reconfigurable Power Distribution Network in a Multicore Platform
Clock selection for performance optimization of control-flowintensive behaviors
A Data-Driven Asynchronous Neural Network Accelerator
An Efficient Compiler Framework for Cache Bypassing on GPUs
A Parallel Harmonic-Balance Approach to Steady-State and Envelope-Following Simulation of Driven and Autonomous Circuits
Error Resilience in Deep Neural Networks Using Neuron Gradient Statistics
Reducing memory energy consumption of embedded applications that process dynamically allocated data
Optimizing the Performance of Consistency-Aware Deduplication Using Persistent Memory
Algorithms in FastStokes and Its Application to Micromachined Device Simulation
RESCUE: Resilient, Scalable, High-Corruption, Compact-Key-Set Locking Framework
Extracting transistor changes from device simulations by gradient fitting
An Ultraspeed Middle Voltage and Timing Analyzer With Near-SPICE Accuracy for Charge-Recycling Buses
On variable clock methods for path delay testing of sequential circuits
Generation of Unstructured Meshes for Process and Device Simulation by Means of Partial Differential Equations
Analytical estimation of signal transition activity from word-level statistics
Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation
Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs
Optimizing DNN Inference on Multi-accelerator SoCs at Training-Time
Rapid method to account for process variation in full-chip capacitance extraction
Quantized Neural Network Synthesis for Direct Logic Circuit Implementation
pFed-Litho: Lithography Modeling With a Personalized Federated Learning-Based Framework
A first-order charge conserving MOS capacitance model
Adaptive Management With Request Granularity for DRAM Cache Inside nand-Based SSDs
Voltage-Driven Hysteresis Model for Resistive Switching: SPICE Modeling and Circuit Applications
Mixed-element decomposition method for three-dimensional grid adaptation
A Simulation Method to Completely Model the Various Transistor I-V Operational Modes of Long Channel Depletion MOSFET's
Variable ordering algorithms for ordered binary decision diagrams and their evaluation
Comments on "Sympathy: fast exact minimization of fixedpolarity Reed-Muller expansion for symmetric functions"
Trace Logic Locking: Improving the Parametric Space of Logic Locking
Improving F2FS Performance in Mobile Devices With Adaptive Reserved Space Based on Traceback
Toward Speculative Loop Pipelining for High-Level Synthesis
A method for increasing the I DDQ testability
Exploiting multicycle false paths in the performance optimization of sequential logic circuits
Graph based analysis of 2-D FPGA routing
Compact Functional Testing for Neuromorphic Computing Circuits
Variation-Aware False Path Analysis Based on Statistical Dynamic Timing Analysis
STPAcc: Structural TI-Based Pruning for Accelerating Distance-Related Algorithms on CPU-FPGA Platforms
Testability of SPP Three-Level Logic Networks in Static Fault Models
TSV Repair Architecture for Clustered Faults
Gate Sizing by Lagrangian Relaxation Revisited
Theory of safe replacements for sequential circuits
ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochips
A time dependent hydrodynamic device simulator SNU-2D with new discretization scheme and algorithm
Parametric yield optimization for MOS circuit blocks
A unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 µm NMOS devices
Mask Assignment and DSA Grouping for DSA-MP Hybrid Lithography for Sub-7 nm Contact/Via Holes
GCIM: Toward Efficient Processing of Graph Convolutional Networks in 3D-Stacked Memory
Parallel standard cell placement algorithms with quality equivalent to simulated annealing
Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions
Computer-aided design and scaling of deep submicron CMOS
Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs
Design of robustly testable combinational logic circuits
Learning Malicious Circuits in FPGA Bitstreams
Modeling and Controlling Parallel Tasks in Droplet-Based Microfluidic Systems
Chebyshev Affine-Arithmetic-Based Parametric Yield Prediction Under Limited Descriptions of Uncertainty
PMEH: A Parallel and Write-Optimized Extendible Hashing for Persistent Memory
Reliable Hybrid Small-Signal Modeling of GaN HEMTs Based on Particle-Swarm-Optimization
Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review
GRAP: Efficient GPU-Based Redundancy Analysis Using Parallel Evaluation for Cross Faults
Design Methodology for Low Power and Parametric Robustness Through Output-Quality Modulation: Application to Color-Interpolation Filtering
Two-Dimensional Routing for the Silc Silicon Compiler
Optimal Program-Read Schemes Toward Highly Reliable Open Block Operations in 3-D Charge-Trap NAND Flash Memory
Exploiting Process Variations to Secure Photonic NoC Architectures From Snooping Attacks
A Physical Design Flow Against Front-Side Probing Attacks by Internal Shielding
Directed Test Generation for Validation of Cache Coherence Protocols
Scan Architecture With Align-Encode
Model-Driven Design of Network Aspects of Distributed Embedded Systems
A hybrid energy-estimation technique for extensible processors
Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching
Scan Chain Architecture With Data Duplication for Multiple Scan Cell Fault Diagnosis
On partitioning and symbolic model checking
Completely automatic completion of VLSI designs
Combination of interpolation and self-organizing approximation techniques-a new approach to circuit performance modeling
Device Design Guidelines to Boost Up AC Performance of CFET (Complementary Field-Effect-Transistor)-Based Inverter
Analysis of digital circuits through symbolic reduction
A decoupling technique for efficient timing analysis of VLSI interconnects with dynamic circuit switching
A massively parallel algorithm for three-dimensional device simulation
A novel framework for logic verification in a synthesis environment
Multilevel logic synthesis with extended arrays
On Reverse Engineering-Based Hardware Trojan Detection
Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays
Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug
Finding obstacle-avoiding shortest paths using implicit connection graphs
Miss Penalty Aware Cache Replacement for Hybrid Memory Systems
Dynamic Allocation Mechanism to Reduce Read Latency in Collaboration With a Device Queue in Multichannel Solid-State Devices
MOSTSM: a physically based charge conservative MOSFET model
Comparisons of quad trees and 4-D trees: new results [VLSI layout]
New fault models and efficient BIST algorithms for dual-port memories
Explainable Machine Learning for Intrusion Detection via Hardware Performance Counters
Common-case computation: a high-level energy and performance optimization technique
Reliable Physical Unclonable Functions Using Data Retention Voltage of SRAM Cells
Hierarchical Partitioning-Based Interchip Redistribution Layer Routing for Fan-Out Wafer-Level Packaging
Generalized Asynchronous Time-Triggered Scheduling for FlexRay
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
Simultaneous power supply planning and noise avoidance in floorplan design
Optimal path routing in single- and multiple-clock domain systems
Inductance Extraction for Interconnects in the Presence of Nonlinear Magnetic Materials
A Predictive Readout Fidelity Model Considering Nonidealities for Readout Circuit Design in Superconducting Quantum Computers
Priority Assignment for Global Fixed Priority Scheduling on Multiprocessors
Clock skew reduction in ASIC logic design: a methodology for clock tree management
reTSN: Resilient and Efficient Time-Sensitive Network for Automotive In-Vehicle Communication
A high-speed 2-D topography simulator based on a pixel model
High-voltage device modeling for SPICE simulation of HVIC's
PARALLEX: a parallel approach to switchbox routing
Skew measurements in clock distribution circuits using an analytic signal method
Multidimensional interleaving for synchronous circuit design optimization
Guest Editorial Special Section on Contemporary and Emerging Issues in Physical Design
Analysis of communication circuits based on multidimensional Fourier transformation
Scalable Construction of Clock Trees With Useful Skew and High Timing Quality
Low Energy yet Reliable Data Communication Scheme for Network-on-Chip
Three-dimensional numerical semiconductor device simulation: algorithms, architectures, results
Approximate DCT and Quantization Techniques for Energy-Constrained Image Sensors
A prescriptive formal model for data-path hardware
Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs
Leveraging Modern C++ in High-Level Synthesis
Precedence-Aware Automated Competitive Analysis of Real-Time Scheduling
xMAS-Based QoS Analysis Methodology
On the complexity of gate duplication
feGRASS: Fast and Effective Graph Spectral Sparsification for Scalable Power Grid Analysis
General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs
A fast hierarchical algorithm for three-dimensional capacitanceextraction
Critical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimization
Efficient Feasibility Analysis for Graph-Based Real-Time Task Systems
A Novel Test Application Scheme for High Transition Fault Coverage and Low Test Cost
Real-Time Detection and Localization of Distributed DoS Attacks in NoC-Based SoCs
Constraint-Aware E-Graph Rewriting for Hardware Performance Optimization
Accelerated Fault Simulation and Fault Grading in Combinational Circuits
QIG: Quantifying the Importance and Interaction of GPGPU Architecture Parameters
Fault coverage estimation by test vector sampling
NExG: Provable and Guided State-Space Exploration of Neural Network Control Systems Using Sensitivity Approximation
Improved n-Detection Test Sequences Under Transparent Scan
High-level energy macromodeling of embedded software
A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash
Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity
HEIF: Highly Efficient Stochastic Computing-Based Inference Framework for Deep Neural Networks
Functional synthesis of digital systems with TASS
KPAC: Efficient Emulation of the ARM Pointer Authentication Instructions
Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design
Optimal wiresizing under Elmore delay model
High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints
CMOS Circuit Speed and Buffer Optimization
A general purpose, multiple-way partitioning algorithm
A Granular Resampling Method and Adaptive Speculative Mechanism-Based Energy-Efficient Architecture for Multiclass Heartbeat Classification
ARBSA: Adaptive Range-Based Simulated Annealing for FPGA Placement
A scalable algorithm for RTL insertion of gated clocks based on ODCs computation
OpeNPDN: A Neural-Network-Based Framework for Power Delivery Network Synthesis
Unified Incremental Physical-Level and High-Level Synthesis
hPRESS: A Hardware-Enhanced Proxy Re-Encryption Scheme Using Secure Enclave
The Detection of Open and Leakage Faults for Prebond TSV Test Based on Weak Current Source
Characterization and parameterized generation of synthetic combinational benchmark circuits
SeqL+: Secure Scan-Obfuscation With Theoretical and Empirical Validation
Interval Image Abstraction for Verification of Camera-Based Autonomous Systems
How to build a hardware description and measurement system on an object-oriented programming language
Programmable Crossbar Quantum-Dot Cellular Automata Circuits
Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSAT
Toward Register Spilling Security Using LLVM and ARM Pointer Authentication
Systematic Methodology for Designing Reconfigurable DeltaSigma Modulator Topologies for Multimode Communication Systems
Intrabus crosstalk estimation using word-level statistics
Resynthesis and retiming for optimum partial scan
Minimizing the number of delay buffers in the synchronization of pipelined systems
Chip Temperature Optimization for Dark Silicon Many-Core Systems
Relaxing Bounds for Linear RC Mesh Circuits
A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC
Yield enhancement of field programmable logic arrays by inherent component redundancy
OPT-GCN: A Unified and Scalable Chiplet-Based Accelerator for High-Performance and Energy-Efficient GCN Computation
Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration
Symmetry Detection and Boolean Matching Utilizing a Signature-Based Canonical Form of Boolean Functions
Optimization of advanced MOS technologies for narrow distribution of circuit performance
Ballistic deposition simulation of via metallization using a quasi-three-dimensional model
Postroute gate sizing for crosstalk noise reduction
System-on-Chip Information Flow Validation Under Asynchronous Resets
Numerical integral method for diffusion modeling
PowerField: A Probabilistic Approach for Temperature-to-Power Conversion Based on Markov Random Field Theory
A Faithful Binary Circuit Model
X-compact: an efficient response compaction technique
Numerical simulation of the gas immersion laser doping (GILD) process in silicon
Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers
Linear sifting of decision diagrams and its application insynthesis
Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework
Reverse-Engineering Optimization Techniques of High-Level Synthesis: Practical Insights Into Accelerating Applications With AMD-Xilinx Vitis
Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization
Hierarchical Verification of Galois Field Circuits
Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation
Using Data Compression for Increasing Memory System Utilization
Towards a high-level power estimation capability [digital ICs]
Pattern routing: use and theory for increasing predictability andavoiding coupling
On-Chip Analog Trojan Detection Framework for Microprocessor Trustworthiness
A Method of Improving the Terminal Assignment in the Channel Routing for Gate Arrays
DEPS: Exploiting a Dynamic Error Prechecking Scheme to Improve the Read Performance of SSD
Power optimization of variable-voltage core-based systems
Implementation of a comprehensive and robust MOSFET model in cadence SPICE for ESD applications
Analysis and design of latch-controlled synchronous digital circuits
A Parallel Direct Solver for the Simulation of Large-Scale Power/Ground Networks
Numerical Analysis of Multidomain Systems: Coupled Nonlinear PDEs and DAEs With Noise
Timing constraints for wave-pipelined systems
Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips
Toward Robust Vehicle Platooning With Bounded Spacing Error
On Computing Criticality in Refactored Timing Graphs
Threshold-Defined Logic and Interconnect for Protection Against Reverse Engineering
Models and algorithms for bounds on leakage in CMOS circuits
Compact, netlist-based representation of thermal transient coupling using controlled sources
Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers
Fast and simple method for calculating the minority-carrier current in arbitrarily doped semiconductors
Substrate Topological Routing for High-Density Packages
Optimal Double Via Insertion With On-Track Preference
ADAPT: A Write Disturbance-Aware Programming Technique for Scaled Phase Change Memory
SIERRA: a 3-D device simulator for reliability modeling
A Fast Analog Circuit Analysis Algorithm for Design Modification and Verification
DtCraft: A High-Performance Distributed Execution Engine at Scale
Extending Flash Lifetime in Embedded Processors by Expanding Analog Choice
Bridge-NDP: Efficient Communication-Computation Overlap in Near Data Processing System
Yield prediction by sampling IC layout
Methods for generating and editing merged isotropic/anisotropic triangular-element meshes
A Study of the Electroforming Process in 1T1R Memory Arrays
Optimization-intensive watermarking techniques for decision problems
Statistical Modeling With the PSP MOSFET Model
Area fill synthesis for uniform layout density
Statistical Reachability Analysis of Stochastic Cyber-Physical Systems Under Distribution Shift
Airgap Insertion and Layer Reassignment Under Setup and Hold Timing Constraints
Partitioning and analysis of static digital CMOS circuits
Autonomous Volterra Algorithm for Steady-State Analysis of Nonlinear Circuits
Bit-Swapping LFSR and Scan-Chain Ordering: A Novel Technique for Peak- and Average-Power Reduction in Scan-Based BIST
Formulations and a Computer-Aided Test Method for the Estimation of IMD Levels in an Envelope Feedback RFIC Power Amplifier
Yield Prediction With a New Generalized Process Capability Index Applicable to Non-Normal Data
RICE: rapid interconnect circuit evaluation using AWE
Hybrid dynamic/quadratic programming algorithm for interconnecttree optimization
Performance-driven technology mapping for heterogeneous FPGAs
Boosting Bit-Error Resilience of DNN Accelerators Through Median Feature Selection
Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime
Understanding and closed-form-formula determination of frequency-dependent bonding-pad characterization
A Flexible Yet Efficient DNN Pruning Approach for Crossbar-Based Processing-in-Memory Architectures
Predictive Compositional Method to Design and Reoptimize Complex Behavioral Dataflows
Online Signal Monitoring With Bounded Lag
SPICE Simulation of SOI MOSFET Integrated Circuits
Parameter extraction for statistical IC modeling based on recursive inverse approximation
Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits
Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning
Congestion-Constrained Layer Assignment for Via Minimization in Global Routing
Efficient FPGA-Based Sparse Matrix-Vector Multiplication With Data Reuse-Aware Compression
Reducing correlation to improve coverage of delay faults in scan-path design
A discrete syntax for level-sensitive latched circuits having n clocks and m phases
TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations
Timing and area optimization for standard-cell VLSI circuit design
Design and analysis of segmented routing channels for row-based FPGA's
Area-Optimal Transistor Folding for 1-D Gridded Cell Design
Voltage-Based Concatenatable Full Adder Using Spin Hall Effect Switching
TritonRoute-WXL: The Open-Source Router With Integrated DRC Engine
Domino-Pro-Max: Toward Efficient Network Simplification and Reparameterization for Embedded Hardware Systems
A simple metric for slew rate of RC circuits based on two circuit moments
Timing-Driven Technology Mapping Approximation Based on Reinforcement Learning
Mesh of Trees FPGA Architecture: Exploration and Optimization