yusuke1997/dblp-id-title huggingface dataset:
DFT and BIST of a Multichip Module for High-Energy Physics Experiments
Event-Triggered Sensing for High-Quality and Low-Power Cardiovascular Monitoring Systems
Burton Smith's Multithreaded Success Strategy
Multicore Parallelism Exploration Targeting 3D-HEVC Intra-Frame Prediction
Computer-Aided Prototyping for ASIC-Based Systems
Guest Editors' Introduction: IR Drop in Very Deep-Submicron Designs
Metamodeling: What is it good for?
Testability: Barriers to Acceptance
Enabling Timing Error Resilience for Low-Power Systolic-Array Based Deep Learning Accelerators
Dispelling the Myths of Parallel Computing
Testing of Prebond Through Silicon Vias
Sailing on a Sea of Processors
Analog Testing with Time Response Parameters
Indirect Test Pattern Generation for Mixed-Signal Circuits Using Machine Learning
Conflicting International Standards Pressure Chip Designers
Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling
A Heterogeneous Multiprocessor Architecture for Flexible Media Processing
The Last Byte: Real Time, Real People
Strategies for Low-Cost Test
On the Integration of Design and Test for Chips Embedding MEMS
ITC Highlights
Variability: For headache and profit
Guest Editor's Introduction: Getting More Out of Test
Recap of the 62nd ACM/IEEE Design Automation Conference (DAC62): The "Chips to Systems Conference"
Remote Fault Attacks in Multitenant Cloud FPGAs
From the EIC: Manufacturing test woes
FPGA Adders: Performance Evaluation and Optimal Design
Testing On-Die Process Variation in Nanometer VLSI
Survey of Low-Power Electric Vehicles: A Design Automation Perspective
Interface Design for Core-Based Systems
Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST
A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits
Managing Electric Vehicles
Recap of the European Test Symposium 2017 (ETS'17)
IP for Embedded Diagnosis
Achieving Accurate Timing Measurements on TTL/CMOS Devices
Scan design at NEC
IEEE 1149.6: A Boundary-Scan Standard for Advanced Digital Networks
Tangram: Virtual Integration of IP Components in a Distributed Cosimulation
VLSI Test and Trust Roundtable
Test Generation for Current Testing (CMOS ICs)
WRAPLE: The Weighted Repair Assistance Program Learning Extension
GlucoseHD: Predicting Glucose Levels Using Hyperdimensional Computing
Vision from the Top
Design Issues in Parallel Simulation Languages
The Tides of EDA
FPGA-Based Embedded Tester with a P1687 Command, Control, and Observe-System
Integrated Task Scheduling and Data Assignment for SDRAMs in Dynamic Applications
IDDQ Test: Will It Survive the DSM Challenge?
Specification, Planning, and Synthesis in a VHDL Design Environment
Testability Implications of Performance-Driven Logic Synthesis
Microfluidics: Design and Test Solutions for Enabling Biochemistry on a Chip
Guest Editors' Introduction: Special Issue on Architecture Advances Enabled by Emerging Technologies
Rapid Hardware Prototyping on RPM-2
Ladder Scaling Fracmemristor: A Second Emerging Circuit Structure of Fractional-Order Memristor
The 10th China Test Conference
Exploring Exploration: A Tutorial Introduction to Embedded Systems Design Space Exploration
A Digital Polarity Correlator with Built-in Self Test and Self Repair
Case Study of a 65-nm SoC Design
Solving Satisfiability in Combinational Circuits
TTTC Newsletter Jan Feb 2021
ITC is Cool
From Behavior to Structure: High-Level Synthesis
Rethinking SoC Verification for Secure Cross-Layer Interactions
Datapath Extension of NPUs to Support Nonconvolutional Layers Efficiently
IC Diagnosis Using Multiple Supply Pad IDDQs
Core Design and System-on-a-Chip Integration
A D&T Special Report on ACM/SIGDA Design Automation Benchmarks: Catalyst or Anathema?
Modeling and Testing for Timing Faults in Synchronous Sequential Circuits
ETM10 Incorporates Hardware Segment of IEEE P1500
Design automation systems in Japan
Designing Secure Electronics: Challenges From a Hardware Perspective
Logic simulation engines in Japan
VHDL - The Designer Environment
Self-Test in a Standard Cell Environment
Guest Editor's Introduction: Mixing Analog and Digital Systems
CLEAR Cross-Layer Resilience: A Retrospective
VHDL Critique
Flow-Layer Physical Design for Microchips Based on Monolithic Membrane Valves
Design Considerations for Cooling High Heat Flux IC Chips With Microchannels
Reliable Systems on Unreliable Fabrics
Boundary Scan: The Internet of Test
A BIST Approach to Approximate Co-Testing of Embedded Data Converters
Measuring Jitter and Phase Error in Microprocessor Phase-Locked Loops
Author Guidelines: IEEE Design & Test of Computers
A Novel Method for Scalable VLSI Implementation of Hyperbolic Tangent Function
Reconciling Time Predictability and Performance in Future Computing Systems
Reliability Analysis of Small-Delay Defects Due to Via Narrowing in Signal Paths
An Area- and Power-Efficient Stochastic Number Generator for Bayesian Sensor Fusion Circuits
COSI: A Framework for the Design of Interconnection Networks
Physically-Aware Analysis of Systematic Defects in Integrated Circuits
Adaptive ECC for Tailored Protection of Nanoscale Memory
Protecting Critical Data
NSF Workshop on EDA: Past, Present, and Future (Part 2)
Hardware Trojans in Wireless Cryptographic ICs
Design automation Technical Committee Newsletter
Real-Time Current Testing for A/D Converters
Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools
ITC 99 Panels
A Survey of Hardware Trojan Taxonomy and Detection
Formal Interpretation of Assertion-Based Features on AMS Designs
A career in system-level design research
Cyber-Physical Systems Security and Privacy
Deep Reinforcement Learning for Optimization at Early Design Stages
Ultralow-Power LED-Enabled On-Chip Optical Communication Designed in the III-Nitride and Silicon CMOS Process Integrated Platform
IEEE Standards Coordinating Committee 20
Large-Scale Pairwise Sequence Alignments on a Large-Scale GPU Cluster
Hierarchical ATPG for Analog Circuits and Systems
Bridging the Processor-Memory Performance Gapwith 3D IC Technology
Design and CAD for Nanotechnologies
A Tutorial on Built-In Self-Test, Part 2: Applications
Embedded Systems Secure Path Verification at the Hardware/Software Interface
Verilog and Other Standards
Compacting Test Responses for Deeply Embedded SoC Cores
An Efficient, Low-Cost I/O Subsystem for Network Processors
The Last Byte: Too many reboots
Guest Editors' Introduction: Tackling Key Problems in NoCs
Fault-Secure Parity Prediction Arithmetic Operators
2016 ASP-DAC
Enabling Safe Interoperation by Medical Device Virtual Integration
The Last Byte: Baseball and Testing
System on Chip or System on Package?
Test Data Compression
Embedded Boundary Scan
Design Automation TC Newsletter
To Thread or Not to Thread
Shape Engineering for Custom Nanomagnetic Logic Circuits in NMLSim 2.0
Test Generation Methods for Utilization Improvement of Hardware-Accelerated Simulation Platforms
Designing CMOS Circuits for Switch-Level Testability
Keeping in touch: Reader survey results; planned e-mail survey
XML-Based Hierarchical Description of 3D Systems and SIP
Efficient and Economical Test Equipment Setup Using Procorrelation
RosettaStone: Connecting the Past, Present, and Future of Physical Design Research
Report of the Fourth International Workshop on Design Automation for Cyber-Physical Systems (DACPS) 2019
Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs
Demystifying 3D ICs: The Pros and Cons of Going Vertical
Design Challenges of Intrachiplet and Interchiplet Interconnection
Reliability, Security, and Sustainability Challenges in 3-D NAND Flash SSDs
Implementation-Independent Model of an Instruction Set Architecture in VHDL
From the EIC: Education for Cyber-Physical Systems
A Survey of Lightweight-Cryptography Implementations
Multicore Algorithms for Transient-Noise Simulation
Design for Testability and Self-Testing Approaches for Bit-Serial signal Processors
Randomized Checkpoints: A Practical Defense for Cyber-Physical Microfluidic Systems
RISE++: A Symbolic Environment for Scan-Based Testing
Guest Editors' Intoduction: The New World of Large Embedded Memories
Topology-Aided Multicorner Timing Predictor for Wide Voltage Design
Automating the Design of SOCs Using Cores
A D&T Roundtable: Telecommunications System Design
Site-to-Site Variation in Analog Multisite Testing: A Survey on Its Detection and Correction
Signal Integrity Enhancement in Digital Circuits
High-Bandwidth Memory (HBM) Test Challenges and Solutions
Symbolic Quick Error Detection for Pre-Silicon and Post-Silicon Validation: Frequently Asked Questions
Smart-Substrate Multichip-Module Systems
Thermal Testing on Reconfigurable Computers
A Wirelist Compare Program for Verifying VLSI Layouts
A Systematic Design Methodology of Formally Proven Side-Channel-Resistant Cryptographic Hardware
Variability Expeditions: A Retrospective
Automatic TLM Generation for Early Validation of Multicore Systems
Low-Power Sparse Hyperdimensional Encoder for Language Recognition
How to achieve 95% fault coverage without really trying
Stochastic Computing for Neuromorphic Applications
Postquantum Cryptography for Internet of Things
NREC: Risk Assessment and Planning of Complex Designs
From the Heart of Silicon Valley to the Hill Country - Highlights of ICCAD 2015
Multiple Fault Diagnosis by Sensitizing Input Pairs
Five Years Teaching Ethics and Computing
An Interview With Professor Chenming Hu, Father of 3D Transistors
A Tutorial on Built-in Self-Test. I. Principles
PyH2: Using PyMTL3 to Create Productive and Open-Source Hardware Testing Methodologies
Hardware-Based Real-Time Workload Forensics
An MPGA-Like FPGA
Multilevel Testing for Design Verification of Embedded Systems
Statistical Test Compaction Using Binary Decision Trees
Parallel distributed-time logic simulation
Eliminating Timing Information Flows in a Mix-Trusted System-on-Chip
Guest Editors' Introduction: Asynchronous Design Is Here to Stay (and Is More Mainstream Than You Thought)
DSS: A Distributed High-Level Synthesis System
Deriving Feature Fail Rate from Silicon Volume Diagnostics Data
Special Issue on NOCS 2022
Interview With Prof. Sung-Mo (Steve) Kang
A. Richard Newton: Technologist with a Mission
A Case for PIM Support in General-Purpose Compilers
VLSI design and CAD technology in Korea
Hey, you, get onna my cloud [The Last Byte]
Shortening the Design Cycle for Programmable Logic
Improving Transition Delay Test Using a Hybrid Method
The VLSI Design Automation Assistant: From Algorithms to Silicon
Magic's Circuit Extractor
Reliability for the Masses
The Future of Design for Test and Silicon Lifecycle Management
Fair and Comprehensive Benchmarking of Machine Learning Processing Chips
SUAVE: Extending VHDL to Improve Data Modeling Support
Pioneering in Asia With the US Venture Capital Model
Guest Editors' Introduction: Selected Papers from IEEE VLSI Test Symposium
Mapping and Repairing Embedded-Memory Defects
Adaptive Testing: Dealing with Process Variability
Hardware-Software Codesign
xMAS: Quick Formal Modeling of Communication Fabrics to Enable Verification
Open-Source Electronic Design Automation (EDA) Tools
Yet Another Thiotimoline Application
IEEE Council for Electronic Design Automation: A new beginning
Dedicated Shapelet Distance Engine for Time-Series Classification
Determining Mechanical Stress Testing Parameters for FHE Designs with Low Computational Overhead
ED&TC 1995: Simulation versus formal verification
Improving IC Security Against Trojan Attacks Through Integration of Security Monitors
Celebrating 20 Years of EDA: Milestones, Challenges, and Future Directions
CS On-Line Service
LOCST: A Built-In Self-Test Technique
Hardware-Software Cosynthesis for Microcontrollers
A SystemC Refinement Methodology for Embedded Software
Guest Editorial: Robust Resource-Constrained Systems for Machine Learning
Multiprocessor SoC Platforms: A Component-Based Design Approach
System Specification with the SpecCharts Language
Customizable Domain-Specific Computing
Test Resource Partitioning for SOCs
Test Program Generation for Communication Peripherals in Processor-Based SoC Devices
Optimization of a Dual-Band Wireless Power and Data Telemetry System Using Genetic Algorithm
Middleware for IoT-Cloud Integration Across Application Domains
Design and Characterization of Null Convention Self-Timed Multipliers
OpenTimer v2: A Parallel Incremental Timing Analysis Engine
Tttc Newsletter
A practical look at ATPG
Guest Editor's Introduction: ITC Helps Get More Out of Test
Q-Learning-Based Voltage-Swing Tuning and Compensation for 2.5-D Memory-Logic Integration
CAD Tools for Bridging Microsystems and Foundries
A Deep Transfer Learning Design Rule Checker With Synthetic Training
All I Know I Learned at ITC
Control-Quality-Driven Design of Embedded Control Systems with Stability Guarantees
Report of the 2015 Embedded Systems Week (ESWEEK)
Virtualizing USB Kernel Mode Debug (KMD) Class to Guest OS for Native OS-Like Debug Experience
First Results of ITC'99 Benchmark Circuits
Design for manufacturability: Then and now
A Programmable Open Architecture Testbed for CPS Education
3-D WiRED: A Novel WIDE I/O DRAM With Energy-Efficient 3-D Bank Organization
Addressing the Cross-Temperature Issue in 3-D NAND Flash Memories: Characterization and Mitigation for Solid-State Drives
A Graduate Curriculum in Cyber-Physical Systems
Testing Microelectronic Biofluidic Systems
An Optimizer for Hardware Synthesis
Towards Occupancy-Driven Heating and Cooling
Testing Gbps Interfaces without a Gigahertz Tester
The 2017 Embedded Systems Week (ESWEEK)
Wireless, ESL, DFM, and Power on Stage at 42nd DAC
From the Editor in Chief: Addressing Problems of the Large
BEE2: A High-End Reconfigurable Computing System
Dynamic Backlight Adaptation for Low-Power Handheld Devices
Two Enduring Questions for Computer Design
Device Model for Ballistic CNFETs Using the First Conducting Band
Special Issue on the First IEEE Top Picks in VLSI Test and Reliability Workshop
Embedded Timing Analysis: A SoC Infrastructure
Advances in ESL Design
Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort
Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders
The Compiled Logic Simulator
Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices
Cloud-Ready Acceleration of Formal Method Techniques for Cyber-Physical Systems
25 Years (and a Bit More) of The Last Byte
The impact of boundary scan on board test
A D&T Roundtable: Industrial and University Test Research Collaboration
End-to-End Automated Exploit Generation for Processor Security Validation
Incorporating Cost Modeling in Embedded-System Design
Shmoo Plotting: The Black Art of IC Testing
HELP: A Hardware-Embedded Delay PUF
The Counterflow Pipeline Processor Architecture
Exploratory Data Analysis for Semiconductor Manufacturing
Enhancing Yield at the End of the Technology Roadmap
High-Level Modeling and Design of Asynchronous Interface Logic
A Brief History of Multiprocessors and EDA
Detecting FET Stuck-Open Faults in CMOS Latches and Flip-Flops
Dado Banatao: Profile of a Silicon Valley Entrepreneur
Twenty Years Ago Today
Power Grid Physics and Implications for CAD
Cell-Aware Test on Various Circuits in an Advanced 3-nm Technology
From Specification to High-Volume Production
Exploring the Precision Limitation for RRAM-Based Analog Approximate Computing
Guest Editors' Introduction: SBCCI 2023
When tools cry wolf: Testability pitfalls of synthesized designs
Pentium Pro Processor Design for Test and Debug
Defect-Oriented Testing and Defective-Part-Level Prediction
ASPLOS Report
System-on-Chip Testability Using LSSD Scan Structures
Toward Energy-Quality Scaling in Deep Neural Networks
Clock system design
Placement and Routing in 3D Integrated Circuits
Active and Passive Physical Attacks on Neural Network Accelerators
A Hierarchical Infrastructure for SoC Test Management
Challenges in Assessing and Improving Deep Neural Networks' Reliability
Tree-Based Unidirectional Neural Networks for Low-Power Computer Vision
Defect Tolerance for Nanoscale Crossbar-Based Devices
Special Issue on 2021 Top Picks in Hardware and Embedded Security
Book Review: A physical-design picture book
The K*BMD: A Verification Data Structure
Verification of Pin-Accurate Port Connections
Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs
Was it worth the wait? Yes!
Application-Specific System-on-a-Chip Multiprocessors
Impact of FinFET on Near-Threshold Voltage Scalability
Guest Editors' Introduction: Special Issue on Autonomous Systems Design
Evaluating Theoretical Baselines for ML Benchmarking Across Different Accelerators
Estimating Circuit Activity in Combinational CMOS Digital Circuits
Searching for clues: Diagnosing IC failures
A Different View: Hardware Synthesis from SystemC is a Maturing Technology
Special Issue on Ethics in Computing
Postsilicon Adaptation for Low-Power SRAM under Process Variation
The case for power with test
Postpandemic Conferences: The DATE 2023 Experience
A silicon El Niño?
Real-Time Fault Detection and Diagnosis System for Analog and Mixed-Signal Circuits of Acousto-Magnetic EAS Devices
Challenges of Rapidly Emerging Consumer Space Multiprocessors
Teradyne's J967 VLSI Test System: Getting VLSI to the Market on Time
Guest Editorial: The Many Faces of Test
Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers
Multisource Indoor Energy Harvesting for Nonvolatile Processors
Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits
Small Is Good
Electromagnetic Signatures as a Tool for Connectionless Test
Critical Path Tracing: An Alternative to Fault Simulation
Intra-Task Voltage Scheduling for Low-Energy, Hard Real-Time Applications
Wireless System for Microwave Test Signal Generation
A NoC-Based Spatial DNN Inference Accelerator With Memory-Friendly Dataflow
Master numerical tasks with ease
Robust Machine Learning Systems: Challenges, Current Trends, Perspectives, and the Road Ahead
From the EIC: Embedded Intelligence in the Internet-of-Things
Challenges and Options
Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements
Multicore Simulation of Transaction-Level Models Using the SoC Environment
Tackling Test Challenges for Interposer-Based 2.5-D Integrated Circuits
Analysis of Power Supply Noise in the Presence of Process Variations
Validating PowerPC Microprocessor Custom Memories
Guest Editor's Introduction: Dynamic Power Management of Electronic Systems
FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology
Open-Source Silicon - Unleashing Innovation and Collaboration
Practical Formal Verification in Microprocessor Design
Safe and Efficient Deployment of Data-Parallelizable Applications on Many-Core Platforms: Theory and Practice
An insider's look at microprocessor design
Built-In Self-Test Structures
Will hardware and software be codesigned? [review of "A Practical Introduction to Hardware/Software Codesign" (Schaumont, P.R.; 2010)]
Cross-Layer Design of Cyber-Physical Systems
From-the-EiC_38_1
Analog, digital, and mixed-signal people
Safety Property Verification Using Sequential SAT and Bounded Model Checking
HPC-Based Malware Detectors Actually Work: Transition to Practice After a Decade of Research
In the Licensing Dungeon: CAD by the Minute
Guest Editors' Introduction: Special Issue on 2021 Top Picks in Hardware and Embedded Security
Cocktail approach to functional verification
Logic Modeling in WAVES
Getting Your Bits in Order
A Survey on Security Threats and Countermeasures in IEEE Test Standards
Graph-Based Circuit Simulator for Switched Capacitor Circuits
Exploiting ECC Redundancy to Minimize Crosstalk Impact
DRAM PUFs in Commodity Devices
An Industrial Study of System-Level Test
Embedded Intelligence in the Internet-of-Things
Opportunities and Challenges for 3D Systems and Their Design
SIT: Stochastic Input Transformation to Defend Against Adversarial Attacks on Deep Neural Networks
A D&T Special Report-Boundary Scan: An End-of-Term Report-IEEE Std 1149.1 Survey Results
Noise Generation and Coupling Mechanisms in Deep-Submicron ICs
Fault Diagnosis in Analog Circuits Using Element Modulation
DVFS Pruning for Wireless NoC Architectures
Analysis of Error Recovery Schemes for Networks on Chips
Estimating the Economic Benefits of DFT
Verifying Inevitability of Oscillation in Ring Oscillators Using the Deductive SOS-QE Approach
Test Development for a Third-Version ColdFire Microprocessor
Impact of System Partitioning on Test Cost
Energy-Aware Distributed Speech Recognition for Wireless Mobile Devices
D&T Expands
Verifying Timing Consistency in Formal Specifications
Predictability Analysis of Interruptible Systems by Statistical Model Checking
Automatic Test Wrapper Synthesis for a Wireless ATE Platform
An Attachable Battery-Supercapacitor Hybrid for Large Pulsed Load
The Last Byte: IoT and That Nagging Feeling
Online and Offline BIST in IP-Core Design
Deadlock-Freedom in Computational Neuroscience Simulators
Gordon E. Moore: A Pioneer Looks Back at Semiconductors
IEEE Rebooting Computing Week
Communication-Based Power Management
Delay Characterization and Testing of Arbitrary Multiple-Pin Interconnects
Noncontact Testing of Circuits Via a Laser-Induced Plasma Electrical Pathway
Digital-Compatible BIST for Analog Circuits Using Transient Response Sampling
Titan II: An IPcomp Processor for 10-Gbps Networks
Guest Editors' Introduction: The Resurgence of Open- Source EDA Technology
The Challenges of Synthesizing Hardware from C-Like Languages
Calling Yourself Back
Survey of Low-Power Testing of VLSI Circuits
The truth about outsourcing
Crosstalk Mitigation for High-Radix and Low-Diameter Photonic NoC Architectures
DAC at 50: The Second 25 Years
ITC 2004 panels: Part 1
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization
Multifrequency Analysis of Faults in Analog Circuits
Simulation-Based Verification for High-Level Synthesis
Analog DFT Using an Undersampling Technique
Sociology of Design and EDA
Designing for FPGAs in the Cloud
An Asynchronous, High-Speed Packet Switching Component
Guest Editors' Introduction: Hot Topics at This Year's Design Automation Conference
Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses
Designing Micro- and Nanosystems for a Safer and Healthier Tomorrow
Testing and Applications of Inverter-Free PLAs
Physical Design for 3D System on Package
Guest Editors' Introduction: Test and the Product Life Cycle
Introduction to the Scheduling Problem
Embedded in this issue
Steven P. Levitan (1950-2016)
Wafer-level testing with a membrane probe
Rapid Digital System Prototyping: Current Practice, Future Challenges
Overview of Popular Benchmark Sets
The Last Byte
ITC 2008 Highlights
Reduced-Code Linearity Testing of Pipeline ADCs
Post-Silicon Validation in the SoC Era: A Tutorial Introduction
Backdoor Suppression in Neural Networks using Input Fuzzing and Majority Voting
Adaptive Approximate Computing With CGRAgen
Majority-Logic-Based Self-Checking Adder in Quantum-Dot Cellular Automata
Automated BIST for sequential logic synthesis
Power Density
Fault Detection and Location Using IDD Waveform Analysis
Electrical Modeling of Integrated-Package Power and Ground Distributions
Guest Editors' Introduction: Highlights of the 50th DAC
ITC exhibits for fun and profit
Teaching someone to fish
Some Thoughts on the IC Design-Manufacture Interface
Guest Editors' Introduction: Advances in Configurable Computing
Designing Secure TLBs
SerDes Interoperability and Optimization
Built-in test for RAMs
Low-Power Design Using the Si2 Common Power Format
Effective Built-In Self-Test for Booth Multipliers
ITC 2005 panels
Using STLs for Effective In-Field Test of GPUs
Edward J. McCluskey 1929-2016
JARVA: Joint Application-Aware Oblivious Routing and Static Virtual Channel Allocation
Achieving At-Speed Structural Test
The Role of Competence Networks in the Era of Cyber-Physical Systems - Promoting Knowledge Sharing and Knowledge Exchange
Collateral ASIC Test
Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic
Guest Editors' Introduction: Approximate Computing
Guest Editor's Introduction: Practical Asynchronous Design