yusuke1997/dblp-id-title huggingface dataset:
A 0.3 lx-1.4 Mlx Monolithic Silicon Nanowire Light-to-Digital Converter With Temperature-Independent Offset Cancellation
Sub-1-V swing internal bus architecture for future low-power ULSIs
Harmonic Rejection Mixing Techniques Using Clock-Gating
A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC
A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme
Cache-processor coupling: a fast and wide on-chip data cache design
Fully Integrated Fluorescence Biosensors On-Chip Employing Multi-Functional Nanoplasmonic Optical Structures in CMOS
A 10-b 300-MHz interpolated-parallel A/D converter
An auto-I/Q calibrated CMOS transceiver for 802.11g
A 0.5-mW passive telemetry IC for biomedical applications
Multilevel voltage wave-shaping display driver for AC plasma display panel application
A Fully Adaptive 19-58-Gb/s PAM-4 and 9.5-29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET
A wireless implantable multichannel digital neural recording system for a micromachined sieve electrode
A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications
A Wide DR and Linear Response CMOS Image Sensor With Three Photocurrent Integrations in Photodiodes, Lateral Overflow Capacitors, and Column Capacitors
A High-Fractional-Bandwidth, Millimeter-Wave Bidirectional Image-Selection Architecture With Narrowband LO Tuning Requirements
A VLSI chip set for a large-scale parallel inference machine: PIM/m
Recursive Receiver Down-Converters With Multiband Feedback and Gain-Reuse
A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators
A 10.7-MHz IF-to-baseband ΣΔ A/D conversion system for AM/FM radio receivers
A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs
A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme
A Digitally Controlled Variable-Gain Low-Noise Amplifier With Strong Immunity to Interferers
A low-power 72.8-GHz static frequency divider in AlInAs/InGaAs HBT technology
Dynamic current mode logic (DyCML): a new low-power high-performance logic style
A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse-Fine Time-to-Digital Converter With Subpicosecond Resolution
A time digitizer CMOS gate-array with a 250 ps time resolution
An Energy-Efficient Double Ratchet Cryptographic Processor With Backward Secrecy for IoT Devices
A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current
A new successive approximation architecture for low-power low-cost CMOS A/D converter
DSPU: An Efficient Deep Learning-Based Dense RGB-D Data Acquisition With Sensor Fusion and 3-D Perception SoC
A low-power low-noise CMOS amplifier for neural recording applications
Multi-Watt-Level 4.9-GHz Silicon Power Amplifier for Portable Thermoacoustic Imaging
Fully Immersible Subcortical Neural Probes With Modular Architecture and a Delta-Sigma ADC Integrated Under Each Electrode for Parallel Readout of 144 Recording Sites
A Reference-Free Phase Noise Measurement Circuit Achieving 24.2-fs Periodic Jitter Sensitivity and 275-fsrms Resolution With Background Self-Calibration
Oscillator-Based Reactance Sensors With Injection Locking for High-Throughput Flow Cytometry Using Microwave Dielectric Spectroscopy
A Quick Startup Technique for High-Q Oscillators Using Precisely Timed Energy Injection
20-Mb/s erase/record flash memory by asymmetrical operation
A Dual-Input Bidirectional Three-Level Battery Charger Using Coarse-Fine V CF Balancing and Frequency Foldback Control for Foldable Mobile Applications
An ultralow power CMOS/SIMOX programmable counter LSI
A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP) ULSI
Millimeter-wave VCOs with wide tuning range and low phase noise, fully integrated in a SiGe bipolar production technology
The design of a fully integrated graphics system
Testing of zipper CMOS logic circuits
Oversampling Successive Approximation Technique for MEMS Differential Capacitive Sensor
13 Gb/s Si-bipolar AGC amplifier IC with high gain and wide dynamic range for optical-fiber receivers
A 1-GHz single-chip quadrature modulator
Addition to "Evaluation of three 32-bit CMOS" adders in DCVS logic for self-timed circuits"
A dynamic programming processor for speech recognition
Second-Harmonic Power Generation Limits in Harmonic Oscillators
A Neurochemical Pattern Generator SoC With Switched-Electrode Management for Single-Chip Electrical Stimulation and 9.3 µW, 78 pA rms , 400 V/s FSCV Sensing
Correction to "Voltage-Comparator-Based Measurement of Equivalentiy Samlpled Substrate Noise Wavefor
A 27-MHz digital-to-analog video processor
Reduction of Inductive Crosstalk Using Quadrupole Inductors
2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8: 1 multiplexers with a 0.15-μm CMOS technology
A SONET/SDH overhead terminator for STS-3, STS-3C, and STM-1
A 21.5/43-GHz dual-frequency balanced Colpitts VCO in SiGe technology
A 610-mW zero-overhead class-G full-rate ADSL CO line driver
A 5.2-GHz LNA in 0.35-μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance
An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects
Analysis and Design of a 195.6 dBc/Hz Peak FoM P-N Class-B Oscillator With Transformer-Based Tail Filtering
Introduction to the Special Issue on the 2019 Symposium on VLSI Circuits
A 5-V single-chip delta-sigma audio A/D converter with 111 dB dynamic range
A circuit design of intelligent cache DRAM with automatic write-back capability
A Li-Ion Battery Input Highly Integrated LED Driver With 96.8% Peak Efficiency and Dual-Color Mixing Capability
A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator
A 40-Gb/s integrated clock and data recovery circuit in a 50-GHz f T silicon bipolar technology
Addition to "Digitally programmable switched-current FIR filter for low-voltage applications"
Antenna Preprocessing and Element-Pattern Shaping for Multi-Band mmWave Arrays: Multi-Port Transmitters and Antennas
A negative V th cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories
A 1.4 V Supply CMOS Fractional Bandgap Reference
Polar Antenna Impedance Detection and Tuning for Efficiency Improvement in a 3G/4G CMOS Power Amplifier
A Low-Jitter Injection-Locked Multi-Frequency Generator Using Digitally Controlled Oscillators and Time-Interleaved Calibration
A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking
A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration
Staggered Gain for 100+ GHz Broadband Amplifiers
A CMOS clock recovery circuit for 2.5-Gb/s NRZ data
Retinal Stimulator ASIC Architecture Based on a Joint Power and Data Optical Link
A fully integrated zero-IF transceiver for GSM-GPRS quad-band application
A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-linearity Predistortion
An access-sequence control scheme to enhance random-access performance of embedded DRAM's
A 2.1-Gb/s 12-Channel Transmitter With Phase Emphasis Embedded Serializer for 55-in UHD Intra-Panel Interface
A 57.9-to-68.3 GHz 24.6 mW Frequency Synthesizer With In-Phase Injection-Coupled QVCO in 65 nm CMOS Technology
Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies
Highly Interleaved 5-bit, 250-MSample/s, 1.2-mW ADC With Redundant Channels in 65-nm CMOS
Fully Integrated Startup at 70 mV of Boost Converters for Thermoelectric Energy Harvesting
A 1.4-V 10-bit 25-MS/s pipelined ADC using opamp-reset switching technique
A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With < ±0.5-ppm Frequency Stability and < 1-ps Integrated Jitter
Design and fabrication of a wideband 56- to 63-GHz monolithic power amplifier with very high power-added efficiency
A 256-Mb SDRAM using a register-controlled digital DLL
Charge recycling differential logic (CRDL) for low power application
A 12.3-μW 0.72-mm² Fully Integrated Front-End IC for Arterial Pulse Waveform and ExG Recording
A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS
A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters
7.5 Gb/s monolithically integrated clock recovery circuit using PLL and 0.3-μm gate length quantum well HEMT's
A wide tuning range gated varactor
Mixed body bias techniques with fixed V t and I ds generation circuits
Adaptive On/Off Delay-Compensated Active Rectifiers for Wireless Power Transfer Systems
A Low Phase-Noise Multi-Phase LO Generator for Wideband Demodulators Based on Reconfigurable Sub-Harmonic Mixers
Low supply voltage operation of over-40-Gb/s digital ICs based on parallel-current-switching latch circuitry
Introduction to the Special Issue on the 2006 IEEE International Solid-State Circuits Conference
An Injectable 64 nW ECG Mixed-Signal SoC in 65 nm for Arrhythmia Monitoring
A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications
PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor
A comparison of linear handset power amplifiers in different bipolar technologies
A 0.7-2-GHz self-calibrated multiphase delay-locked loop
A Fully Integrated Li-Ion-Compatible Hybrid Four-Level DC-DC Converter in 28-nm FDSOI
A Novel 61.25 GHz Monostatic CMOS Interrogator for Batteryless Backscattering RFID Solutions
A fourth-order ΣΔ interface for micromachined inertial sensors
Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages
An Embedded All-Digital Circuit to Measure PLL Response
A Multi-Branch Receiver With Modulated Mixer Clocks for Concurrent Dual-Carrier Reception and Rapid Compressive-Sampling Spectrum Scanning
An Energy-Efficient Hybrid SAR-VCO ΔΣ Capacitance-to-Digital Converter in 40-nm CMOS
An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line
An integrated-circuit reliability simulator-RELY
A 1-V multigigahertz RF mixer core in 0.5-μm CMOS
Mutual Pulling Between Two Oscillators
Thin-Film Transistor-Based Sensor Interface Circuits Enabling Distributed Local In-Module Solar Cell Temperature Monitoring
Merged Two-Stage Power Converter With Soft Charging Switched-Capacitor Stage in 180 nm CMOS
DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks
A Wide-Dynamic-Range Neural-Recording IC With Automatic-Gain-Controlled AFE and CT Dynamic-Zoom ΔΣ ADC for Saturation-Free Closed-Loop Neural Interfaces
Fully integrated analog telephone
An Efficiency-Enhanced CMOS Rectifier With Unbalanced-Biased Comparators for Transcutaneous-Powered High-Current Implants
A Calibrated Pulse Generator for Impulse-Radio UWB Applications
A quasi-passive CMOS pipeline D/A converter
A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC
Triple-push oscillator approach: theory and experiments
A Hybrid Loop Two-Point Modulator Without DCO Nonlinearity Calibration by Utilizing 1 Bit High-Pass Modulation
A high-sensitivity CMOS image sensor with gain-adaptive column amplifiers
RePQC: A 3.4-uJ/Op 48-kOPS Post-Quantum Crypto-Processor for Multiple-Mathematical Problems
Refinements to the regenerative carry scheme
A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration
A 1.1-V 270-μA mixed-signal hearing aid chip
A BiCMOS active substrate probe-card technology for digital testing
A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems
Internal node probing of a DRAM with a low-temperature e-beam tester
Characterization of Dynamic SRAM Stability in 45 nm CMOS
Design and implementation of an untrimmed MOSFET-only 10-bit A/D converter with -79-dB THD
New nibbled-page architecture for high-density DRAMs
A very low-power quadrature VCO with back-gate coupling
A 20 kbit associative memory LSI for artificial intelligence machines
A CMOS 76-81-GHz 2-TX 3-RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator
Clock/data recovery PLL using half-frequency clock
Design Techniques for a 66 Gb/s 46 mW 3-Tap Decision Feedback Equalizer in 65 nm CMOS
Direct extraction of an empirical temperature-dependent InGaP/GaAs HBT large-signal model
A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter
An on-chip ECC circuit for correcting soft errors in DRAMs with trench capacitors
SiGe bipolar transceiver circuits operating at 60 GHz
A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS
A Universal UHF RFID Reader IC in 0.18-µm CMOS Technology
A 220-to-320-GHz FMCW Radar in 65-nm CMOS Using a Frequency-Comb Architecture
Minimized Transient and Steady-State Cross Regulation in 55-nm CMOS Single-Inductor Dual-Output (SIDO) Step-Down DC-DC Converter
340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS
Design Considerations for a 100 Gbit/s SiGe-BiCMOS Power Multiplexer With 2 V pp Differential Voltage Swing
An 800-MHz 8.17-TOPS/W 0.63-TOPS/mm 2 Memory-Utilization-Aware CNN Accelerator Featuring a Memory Stationary Dataflow
A 10-b 20-Msample/s low-power CMOS ADC
2.4-GHz Highly Selective IoT Receiver Front End With Power Optimized LNTA, Frequency Divider, and Baseband Analog FIR Filter
A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET
An all-band TV tuner IC with 10-GHz 100-V mixed analog/digital Si bipolar technology
A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation
Highly sensitive Hall magnetic sensor microsystem in CMOS technology
A 12 b 5-to-50 MS/s 0.5-to-1 V Voltage Scalable Zero-Crossing Based Pipelined ADC
A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing
High-level Video Analytics PC Subsystem Using SoC With Heterogeneous Multicore Architecture
A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver
120-GHz Wideband I/Q Receiver Based on Baseband Equalizing Technique
A 32-KB ePCM for Real-Time Data Processing in Automotive and Smart Power Applications
A monolithic double-balanced direct conversion mixer with an integrated wideband passive balun
A low-power 170-MHz discrete-time analog FIR filter
Reference-Less Time-Division Duplex Transceiver IC for a Renal Denervation System
A 14-bit intrinsic accuracy Q 2 random walk CMOS DAC
A 4-GS/s 80-dB DR Current-Domain Analog Frontend for Phase-Coded Pulse-Compression Direct Time-of-Flight Automotive Lidar
iRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor
A 10-bit DC-20-GHz Multiple-Return-to-Zero DAC With >48-dB SFDR
A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a - 62.1-dBc Fractional Spur
The implementation of a 2-core, multi-threaded itanium family processor
A High-Resolution Accelerometer With Electrostatic Damping and Improved Supply Sensitivity
A 40-Gb/s 14-mW CMOS Wireline Receiver
Wireless Body-Area-Network Transceiver and Low-Power Receiver With High Application Expandability
A 63-μW standby power microcontroller with on-chip hybrid regulator scheme
SHINSAI: A 586 mm 2 Reusable Active TSV Interposer With Programmable Interconnect Fabric and 512 Mb Underdeck Memory
Clocking design and analysis for a 600-MHz Alpha microprocessor
1-GHz GaAs ADC building blocks
Wideband Balun-LNA With Simultaneous Output Balancing, Noise-Canceling and Distortion-Canceling
Analysis and Design of Tuning-Less mm-Wave Injection-Locked Frequency Dividers With Wide Locking Range Using 8th-Order Transformer-Based Resonator in 40 nm CMOS
A Low-Power Processor With Configurable Embedded Machine-Learning Accelerators for High-Order and Adaptive Analysis of Medical-Sensor Signals
A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm
A 2.4-GHz silicon bipolar oscillator with integrated resonator
A 3-V GSM baseband transmitter
A CMOS Chip With Active Pixel Array and Specific Test Features for Subretinal Implantation
6-kΩ 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range
A 0.55 THz Near-Field Sensor With a µm-Range Lateral Resolution Fully Integrated in 130 nm SiGe BiCMOS
A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration
A wide-tunable translinear second-order oscillator
Design and Analysis of a W-band 9-Element Imaging Array Receiver Using Spatial-Overlapping Super-Pixels in Silicon
A 20-32-GHz Quadrature Digital Transmitter Using Synthesized Impedance Variation Compensation
A 2000-volumes/s 3-D Ultrasound Probe With Monolithically-Integrated 23 × 23-mm² 4096 -Element CMUT Array
An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive V DD System for Wireless Sensor Networks
A 77 GHz SiGe sub-harmonic balanced mixer
40-Gbit/s TDM transmission technologies based on ultra-high-speed ICs
A 4×9 Gb/s 1pJ/b Hybrid NRZ/Multi-Tone I/O With Crosstalk and ISI Reduction for Dense Interconnects
3.3-V BiCMOS current-mode logic circuits for high-speed adders
A Coupler-Based Differential mm-Wave Doherty Power Amplifier With Impedance Inverting and Scaling Baluns
Compressive Sensing Photoacoustic Imaging Receiver With Matrix-Vector-Multiplication SAR ADC
Comments on 'Split ADC' architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC"
An asynchronous instruction length decoder
Analysis of temporal noise in CMOS photodiode active pixel sensor
A Fractional-N Digital LC-PLL Using Coupled Frequency Doubler With Frequency-Tracking Loop for Wireline Applications
A Millimeter-Wave Intra-Connect Solution
Design considerations for high-frequency continuous-time filters and implementation of an antialiasing filter for digital video
High Frequency Buck Converter Design Using Time-Based Control Techniques
A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores
A High-Speed Inductive-Coupling Link With Burst Transmission
Broadband ESD protection circuits in CMOS technology
An 8-Gb 12-Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications
A CMOS-based analog standard cell product family
A CMOS IF transceiver with reduced analog complexity
A 200-GHz Power Amplifier With a Wideband Balanced Slot Power Combiner and 9.4-dBm P sat in 65-nm CMOS: Embedded Power Amplification
A CMOS Temperature-to-Frequency Converter With an Inaccuracy of Less Than$\pm \hbox{0.5}\, ^{\circ}{\hbox{C}}$(3$\sigma$) From$-\hbox{40}\, ^{\circ}\hbox{C}$to 105$\, ^{\circ}\hbox{C}$
Fully ECL-compatible GaAs standard-cell library
Substrate current reduction techniques for BiCMOS DRAM
A speed, power, and supply noise evaluation of ECL driver circuits
A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems
A 28-GHz Phased-Array Receiver Front End With Dual-Vector Distributed Beamforming
A 2.5 Gb/s Run-Length-Tolerant Burst-Mode CDR Based on a 1/8th-Rate Dual Pulse Ring Oscillator
A CMOS modem analog processor for V.22 bis modems
A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems
A 104-dB Dynamic Range Transimpedance-Based CMOS ASIC for Tuning Fork Microgyroscopes
A 0.35-V 5, 200-μm 2 2.1-MHz Temperature-Resilient Relaxation Oscillator With 667 fJ/Cycle Energy Efficiency Using an Asymmetric Swing-Boosted RC Network and a Dual-Path Comparator
A Sub-1 V Capacitively Biased BJT-Based Temperature Sensor With an Inaccuracy of ±0.15 °C (3σ) From - 55 °C to 125 °C
Comments, with reply, on 'Metastability of CMOS latch/flip-flop'
A fully integrated 5.3-GHz 2.4-V 0.3-W SiGe bipolar power amplifier with 50-Ω output
A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration
A DC-4-GHz true logarithmic amplifier: theory and implementation
A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique
A 10 Gb/s ATM data synchronizer
A monolithic 6 GHz quadrature frequency doubler with adjustable phase offset
A MM-Wave Current-Mode Inverse Outphasing Transmitter Front-End: A Circuit Duality of Conventional Voltage-Mode Outphasing
A Slew Controlled LVDS Output Driver Circuit in 0.18 µm CMOS Technology
A custom digital intermediate frequency filter for the American mobile telephone system
Design of Direct 48-V/1-V Three-Path Four-State Switching Power Converter With Adaptive V CF Rebalancing and Dual-Edge t dead Modulation
A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces
The 68040 32-b monolithic processor
100-V high-performance amplifiers in BCD technology for SLIC applications
A cell transistor scalable DRAM array architecture
Integrated stereo ΔΣ class D amplifier
A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic
A Low-Power, Differential Relaxation Oscillator With the Self-Threshold-Tracking and Swing-Boosting Techniques in 0.18-µm CMOS
2.5-V bipolar/CMOS circuits for 0.25- mu m BiCMOS technology
A 1.8 V 1.0 GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9.1 ENOB at Nyquist Frequency
A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68
A spread-spectrum clock generator with triangular modulation
A Transformer-Based Broadband Front-End Combo in Standard CMOS
An Octave Tuning-Range Frequency Generator Integrating a Quad-Core VCO Using Quad-Mode Coupled Dual-Path Inductor With a Wideband ILFD
Novel VCO Architecture Using Series Above-IC FBAR and Parallel LC Resonance
A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications
A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios
Guest Editorial IEEE 2022 European Solid-State Circuits Conference
An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET
A High-Swing 45 Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS FDSOI
A low-jitter 1.9-V CMOS PLL for UltraSPARC microprocessor applications
Automated Design of a 13.56 MHz 19µW Passive Rectifier With 72% Efficiency Under 10µA load
Floating-body effects in partially depleted SOI CMOS circuits
Design Considerations for a Direct Digitally Modulated WLAN Transmitter With Integrated Phase Path and Dynamic Impedance Modulation
A 70 mΩ intelligent high side switch with full diagnostics
A dual-band CMOS front-end with two gain modes for wireless LAN applications
A Second-Order ΔΣ ADC Using Noise-Shaped Two-Step Integrating Quantizer
Optimum tapered buffer
Ultra-Compact and Robust Physically Unclonable Function Based on Voltage-Compensated Proportional-to-Absolute-Temperature Voltage Generators
A 0.5 V < 4 µW CMOS Light-to-Digital Converter Based on a Nonuniform Quantizer for a Photoplethysmographic Heart-Rate Sensor
An SRAM cell with nonvolatile memory for programmable logic applications
Design and Analysis of a High-Efficiency High-Voltage Class-D Power Output Stage
A 100-MHz CMOS wide-band IF amplifier
Early effect modeling in SPICE
Introduction to the Special Section on the 2012 Asian Solid-State Circuits Conference (A-SSCC)
A wide dynamic range continuously adjustable CMOS current mirror
Active capacitor multiplier in Miller-compensated circuits
A Multiband FDD SAW-Less Transmitter for 5G-NR Featuring a BW-Extended N-Path Filter-Modulator, a Switched-BB Input, and a Wideband TIA-Based PA Driver
Full-swing BiCMOS logic circuits with complementary emitter-follower driver configuration
A - 137 dBm/Hz Noise, 82% Efficiency AC-Coupled Hybrid Supply Modulator With Integrated Buck-Boost Converter