yusuke1997/dblp-id-title huggingface dataset:
Processing Distributed Mobile Queries with Interleaved Remote Mobile Joins
Hypercube-Based Multipath Social Feature Routing in Human Contact Networks
Causality-Based Predicate Detection across Space and Time
Ternary Rate-Multipliers
Fast and Flexible Elliptic Curve Point Arithmetic over Prime Fields
Hybrid Binary-Unary Hardware Accelerator
Analysis of Signal Transmission in Ultra High Speed Transistorized Digital Computers
Bounding Pipeline and Instruction Cache Performance
Incentive Assignment in Hybrid Consensus Blockchain Systems in Pervasive Edge Environments
On Analysis of Lightweight Stream Ciphers with Keyed Update
BE-NPU: A Bandwidth-Efficient Neural Processing Unit With Adaptive Processing Schemes for Reduced Off-Chip Bandwidth Demand
Design of a Self-Checking Microprogram Control
Ultimate-Speed Adders
DepAsync: An Asynchronous SNN Accelerator Based on Core-Dependency
Aliasing Probability Calculations for Arbitrary Compaction under Independently Selected Random Test Vectors
An Operational Hybrid Computing System Provides Analog-Type Computation with Digital Elements
On Reliability Modeling and Analysis of Ultrareliable Fault-Tolerant Digital Systems
Efficient Out-of-Core and Out-of-Place Rectangular Matrix Transposition and Rotation
On the Diagnosis of System Faults with Propagation
Associative Processing of Network Flow Problems
An Effective DRAM Address Remapping for Mitigating Rowhammer Errors
Evaluating Associativity in CPU Caches
Guest Editors' Introduction: Special Issue on Cloud of Clouds
Design of Testable Multipliers for Fixed-Width Data Paths
Improving the Lifetime of Non-Volatile Cache by Write Restriction
An Efficient Algorithm for Out-of-Core Matrix Transposition
AILC: Accelerate On-Chip Incremental Learning With Compute-in-Memory Technology
System Utilization of Large-Scale Integration
Learning Algorithms for Nonparametric Solution to the Minimum Error Classification Problem
FeFET Multi-Bit Content-Addressable Memories for In-Memory Nearest Neighbor Search
FOCUS: An Experimental Environment for Fault Sensitivity Analysis
Analysis of Checkpointing Schemes with Task Duplication
Efficiently Securing Systems from Code Reuse Attacks
Unate Cascade Realization of Synchronous Sequential Machines
An Efficient Algorithm-Based Fault Tolerance Design Using the Weighted Data-Check Relationship
A Systematic (16, 8) Code for Correcting Double Errors and Detecting Triple-Adjacent Errors
Struktur und Arbeitsweise der Telefunken-Digitalrechenanlage TR 4
Being Patient and Persistent: Optimizing An Early Stopping Strategy for Deep Learning in Profiled Attacks
Asynchronous State Assignments with Unateness Properties and Fault-Secure Design
Construction of Check Sets for Algorithm-Based Fault Tolerance
Genetic Programming for Energy-Efficient and Energy-Scalable Approximate Feature Computation in Embedded Inference Systems
An Adaptive Endurance-Aware B + -Tree for Flash Memory Storage Systems
Using Equilibrium Policy Gradients for Spatiotemporal Planning in Forest Ecosystem Management
Dynamic Balanced Key Tree Management for Secure Multicast Communications
An Improved Hardware Implementation of the Fault-Tolerant Clock Synchronization Algorithm for Large Multiprocessor Systems
Reconstruction of a Linear Scrambler
An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design
Wrong-Path-Aware Entangling Instruction Prefetcher
(SM)²-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations
Clause-Column Table Approach for Generating All the Prime Implicants of Switching Functions
Quatrain: Accelerating Data Aggregation between Multiple Layers
Trends in Graphic Display Design
Cache-Memory Interfaces in Compressed Memory Systems
Lightweight Authentication Scheme for Data Dissemination in Cloud-Assisted Healthcare IoT
Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters
A LOTOS Specification of the PROWAY Highway Service
Bypassing Multicore Memory Bugs With Coarse-Grained Reconfigurable Logic
A Squaring Analog-Digital Converter
Physical Uncertainty and Information
A General Junction-Transistor Equivalent Circuit for Use in Large-Signal Switching Analysis
An Efficient Deep Reinforcement Learning-Based Automatic Cache Replacement Policy in Cloud Block Storage Systems
On the Computational Complexity of System Diagnosis
Dynamic Reconfiguration in Computer Clusters with Irregular Topologies in the Presence of Multiple Node and Link Failures
Speedup Versus Efficiency in Parallel Systems
An Optimized Cell BE Special Function Library Generated by Coconut
A DAG-Based Algorithm for Prevention of Store-and-Forward Deadlock in Packet Networks
$\mathsf{MC{-}FLEX}$MC-FLEX: Flexible Mixed-Criticality Real-Time Scheduling by Task-Level Mode Switch
A Graphical Method for Checking Complete Monotonicity
Utilization-Tensity Bound for Real-Time DAG Tasks under Global EDF Scheduling
Iterative Solution of Linear Equations on a Parallel Processor System
A Symbolic Simulator for Microprogram Development
Guest Editors' Introduction: Special Section on Chips and Architectures for Emerging Technologies and Applications
Counting Two-State Transition-Tour Sequences
Wavefront Array Processor: Language, Architecture, and Applications
A Fast Recognition-Complete Processor Allocation Strategy for Hypercube Computers
Multi-Resource VNF Deployment in a Heterogeneous Cloud
Integer Multiplication with Overflow Detection or Saturation
System-Wide Cooperative Optimization for NAND Flash-Based Mobile Systems
Checking Experiments ror Sequential Machines
Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques
Delay-Insensitive Pipelined Communicatioon on Parallel Buses
A Complex Integer Multiplier Using the Quadratic-Polynomial Residue Number System with Numbers of Form 2 2n + 1
Asymptotic Analysis of a Nonparametric Clustering Technique
A Deep Learning-Assisted Template Attack Against Dynamic Frequency Scaling Countermeasures
Performance Analysis of Virtual Cut-Through Switching in HARTS: A Hexagonal Mesh Multicomputer
Nonparametric Learning Without a Teacher Based on Mode Estimation
Comments on "Leading-One Prediction with Concurrent Position Correction"
Processor Architectures for Two-Dimensional Convolvers Using a Single Multiplexed Computational Element with Finite Field Arithmetic
Performance Evaluation of Host Aware Shingled Magnetic Recording (HA-SMR) Drives
Analog-to-Digital Conversion with Threshold Detectors
On the Constant Diagnosability of Baseline Interconnection Networks
Efficient Design of Totally Self-Checking Checkers for all Low-Cost Arithmetic Codes
Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions
Bit-Sparsity Aware Acceleration With Compact CSD Code on Generic Matrix Multiplication
Adaptively Reduced DRAM Caching for Energy-Efficient High Bandwidth Memory
B74-13 Operating Systems - Infotech State of the Art Report # 14
Improved Error Bounds for Floating-Point Quotients
Systolic Evaluation of Polynomial Expressions
Linear Branch Entropy: Characterizing and Optimizing Branch Behavior in a Micro-Architecture Independent Way
An Autoscale Residue Multiplier
On Detecting Total or Partial Symmetry of Switching Functions
The Architectural Elements of a Symmetric Fault-Tolerant Multiprocessor
Stretching a Knock-Knee Layout for Multilayer Wiring
Tunnel-Diode Amplitude Comparator
The D21 Data Processing System by Svenska Aeroplan Aktiebolaget, Sweden
Some Codes for Correcting and Detecting Unidirectional Byte Errors
Correlation Matrix Memories
Off-Line Correlation Analysis of Nonstationary Signals
Efficient Function Implementation for Bit-Serial Parallel
A Note on the Basic Block Diagrams of Finite Automata from the Engineering Point of View
Enhancing Proportional IO Sharing on Containerized Big Data File Systems
Processor Architecture and Data Buffering
Accelerating Federated Learning With a Global Biased Optimiser
Fast Nondestructive Read, Slow Write Memory Device Using Thick Magnetic Films
Modular Networks and Nondeterministic Sequential Machines
Buffer Sizing for Rate-Optimal Single-Rate Data-Flow Scheduling Revisited
A Magnetostrictive Delay-Line Shift Register
Magnetic Fields of Square-Loop Thin Films of Oblate Spheroidal Geometry
Concurrent Multiresource Arbiter: Design and Applications
A Decimal Code for Analog-to-Digital Conversion
Efficient Byzantine Fault-Tolerance
Self-Synchronized Asynchronous Sequential Machines
Digit-Recurrence Dividers with Reduced Logical Depth
PPMB: A Partial-Multiple-Bus Multiprocessor Architecture with Improved Cost-Effectiveness
Horizons in Guidance Computer Component Technology
Alternative Algorithm for Hilbert's Space-Filling Curve
BCD and Radi x-2 Conversions
A Transition Sequence Generator for RAM Fault Detection
Programmable BIST Space Compactors
Distance on Hesagonal Grid
Closed sets of boolean functions and the reliability problem for polyfunctional nets
Property Encoding: Application in Binary Picture Encoding and Boundary Following
SqueezeFlow: A Sparse CNN Accelerator Exploiting Concise Convolution Rules
Comments on "On the Nondomination of Cohorts Coteries"
Multi-User Computation Partitioning for Latency Sensitive Mobile Cloud Applications
CAPE: Criticality-Aware Performance and Energy Optimization Policy for NCFET-Based Caches
A Fault Attack on Pairing-Based Cryptography
Compression of Three-State Data Serial Streams by Means of a Parallel LFSR Signature Analyzer
GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks
A Clocked Multivalued Flip-Flop
Rounding and Truncation in Radix (-2) Systems
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers
On Improving the Write Responsiveness for Host-Aware SMR Drives
A Preprocessing High-Speed Memory System
Load Sharing in Distributed Systems
A Quantitative Comparison of the Performance of Three Discrete Distributed Associative Memory Models
Partial Scan with Preselected Scan Signals
A SISO Register Circuit Tailored for Input Data with Low Transition Probability
B74-18 Computer System Organization
R68-25 An On-Line Editor
(lambda, T ) Complexity Measures for VLSI Computations in Constant Chip Area
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
A Spectral Stability Analysis of Finite Difference Operators
Effects of Cache Coherency in Multiprocessors
Approximation Algorithms for Capacitated Minimum Forest Problems in Wireless Sensor Networks with a Mobile Sink
LFSR-Based Generation of Partially-Functional Broadside Tests
Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach
An Algorithm for the Solution of the Two-Dimensional "Hidden-Line" Problem
The Containment Set Approach to Upsets in Digital Systems
The Automatic Speech Recognition System for Conversational Sound
Time and Space-Efficient Write Parallelism in PCM by Exploiting Data Patterns
Symmetric Ternary Switching Functions: Their Detection and Realization with Threshold Logic
On the Determination of the ps Maximal Implicants of a Switching Function
Circuit-Based Quantum Random Access Memory for Classical Data With Continuous Amplitudes
On Fault-Tolerant Structure, Distributed Fault-Diagnosis, Reconfiguration, and Recovery of the Array Processors
Design of Totally Fault Locatable Combinational Networks
Logarithm Function Generated by Parallel Resistors
A Synthesis Approach to Design Optimally Fault Tolerant Network Architecture
Asynchronous Comparison-Based Decoders for Delay-Insensitive Codes
A Graph Model for Fault-Tolerant Computing Systems
A Logic System for Fault Test Generation
Recoverable Robust Timetables: An Algorithmic Approach on Trees
Restructuring for Fault-Tolerant Systolic Arrays
STES: A Stream Cipher Based Low Cost Scheme for Securing Stored Data
Fan-In Constrained Tree Networks of Flexibe Cells
Parallel Algorithms for Geometric Connected Component Labeling on a Hypercube Multiprocessor
Secure Remote Attestation With Strong Key Insulation Guarantees
Reliability Enhancement of Flash-Memory Storage Systems: An Efficient Version-Based Design
Squashing Alternatives for Software-Based Speculative Parallelization
A New Class of Optimal Bounded-Degree VLSI Sorting Networks
Experiments with Highleyman's Data
Modular Construction of Low Complexity Parallel Multipliers for a Class of Finite Fields GF(2^m)
Application of Multithreshold Elements in the Realization of Many-Valued Logic Networks
Maryanski's Grammatical Inferencer
A Thin Magnetic Film Shift Register
Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms
High-Speed Adders and Comparators Using Transistors and Tunnel Dioes
Addressing Irregularity in Sparse Neural Networks Through a Cooperative Software/Hardware Approach
Algorithm-Based Error Detection Schemes for Iterative Solution of Partial Differential Equations
Mastrovito Multiplier for All Trinomials
DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture
Synthesis and Comparison of Two's Complement Parallel Multipliers
Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling
An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors
Modified Berger Codes for Detection of Unidirectional Errors
Run-Time Disambiguation: Coping with Statically Unpredictable Dependencies
CoSpMV: Towards Agile Software and Hardware Co-Design for SpMV Computation
Queuing-Based eDRAM Refreshing for Ultra-Low Power Processors
Synthesis of Minimal Binary Decision Trees
Hamiltonian Path Embedding and Pancyclicity on the Möbius Cube with Faulty Nodes and Faulty Edges
Optimization of Latency Insensitive Systems Through Back Pressure Minimization
Nonideal Battery Properties and Their Impact on Software Design for Wearable Computers
Table-Lookup Methods for Generating Arbityrary Random Numbers
Significant Digit Computer Arithmetic
Author's Reply 2
CaCo: An Efficient Cauchy Coding Approach for Cloud Storage Systems
Calibration of an Integrated Land-Use and Transportation Model Using Maximum-Likelihood Estimation
A Cooperative Game Framework for QoS Guided Job Allocation Schemes in Grids
Segmented Selcuk Communication Networks and Response Routing
Storage Reduction Through Minimal Spanning Trees and Spanning Forests
Reducing Memory Latency via Read-after-Read Memory Dependence Prediction
The Arithmetic Cube
Architecture Optimization of Aerospace Computing Systems
3D-ICE: A Compact Thermal Model for Early-Stage Design of Liquid-Cooled ICs
Trends in Microprogramming: A Second Reading
An Experimental Procedure for Handwritten Character Recognition
Some Further Experiments in the Parallel Processing of Pictures
Clock Skew Optimization
Federated Learning Based DDoS Attacks Detection in Large Scale Software-Defined Network
Fault Tolerance Properties of Pyramid Networks
Reducing the MISR Size
PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM
Exponential Sums and Correctly-Rounded Functions
The Parallel Evaluation of Arithmetic Expressions Without Division
Sequential Machines Realizable with Delay Elements Only
A Geometric Theorem for Network Design
Copper-Mandrel Potentiometer Dynamic Error and Compensation
Some Notes on Logical Binary Counters
Direct Transition Memory and its Application in Computer Design
Time Average Thermal Properties of a Computer Utilizing Thin-Film Superconducting Elements
Automated Synthesis of Combinational Logic Using Theorem-Proving Techniques
Integrated Design-Stage Failure Analysis of Software-Driven Hardware Systems
R68-46 Use of Transition Matrices in Compiling
Enabling Printed Multilayer Perceptrons Realization via Area-Aware Neural Minimization
Preemptable Malleable Task Scheduling Problem
A Microeconomic Model for Hierarchical Bandwidth Sharing in Dynamic Spectrum Access Networks
Look-Up Table-Based Large Finite Field Multiplication in Memory Constrained Cryptosystems
Comments on "The Application of the Rademacher-Walsh Transform to Boolean Function Classification and Threshold Logic Synthesis"
A Nonlinear Transformation for Digital Picture Processing
A New Approach to Realizing Partially Symmetric Functions
Cluster Mapping with Experimental Computer Graphics
Multivalued Integrated Injection Logic
Privacy-Preserving Bloom Filter-Based Keyword Search Over Large Encrypted Cloud Data
Fast Multipliers for Number Theoretic Transforms
Classification of Incomplete Pattern Vectors Using Modified Discriminant Functions
Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip
About Signal Flow Graph Techniques for Sequential Circuits
AxMAP: Making Approximate Adders Aware of Input Patterns
A Performance Model for Wormhole-Switched Interconnection Networks under Self-Similar Traffic
VCAlign: An Effective Method for the Removal of Random Delays by Vertical Clustering
ZigZag: Enlarging Joint Architecture-Mapping Design Space Exploration for DNN Accelerators
Toward an SGX-Friendly Java Runtime
Test Generation for Path Delay Faults Using Binary Decision Diagrams
Exploiting Program Branch Probabilities in Hardware Compilation
Scan and Display Considerations in Processing Images by Digital Computer
Joint Optimization of Rule Placement and Traffic Engineering for QoS Provisioning in Software Defined Network
On the Prediction of Java Object Lifetimes
Tology-Aware Optimal Data Placement Algorithm for Network Traffic Optimization
Comments on Pulsed-Data Hybrid Computers
New Formats for Computing with Real-Numbers under Round-to-Nearest
Multiprocessor Fault Diagnosis Under Local Constraints
A Clustering Heuristic for Line-Drawing Analysis
The Generation of a Class of Multipliers: Synthesizing Highly Parallel Algorithms in VLSI
Energy-Resilient Real-Time Scheduling
Evaluating Elementary Functions in a Numerical Coprocessor Based on Rational Approximations
Modeling of Concurrent Task Execution in a Distributed System for Real-Time Control
Fault Detection Architectures for Field Multiplication Using Polynomial Bases
An Analytical Model for a Class of Processor-Memory Interconnection Networks
Efficient Exact Schedulability Tests for Fixed Priority Real-Time Systems
Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes
A Probabilistic Pipeline Algorithm for K Selection on the Tree Machine
Fed-OGD: Mitigating Straggler Effects in Federated Learning via Orthogonal Gradient Descent
Comments on "Delayed Universal Logic Modules and Sequential Machine Synthesis"
Lattice-Based Cryptosystems on FPGA: Parallelization and Comparison Using HLS
A Stabilized Parallel Algorithm for Direct-Form Recursive Filters
An Optimal Algorithm for Detecting Weak Visibility of a Polygon
Irrelevant Features in Pattern Recognition
A New Type Double-Rank Sequential Machine
PERFECTORY: A Fault-Tolerant Directory Memory Architecture
Fast and Efficient Totally Self-Checking Checkers for m -out-of-(2 m ±1) Codes
Bibliography of Digital Magnetic Circuits and Materials
Utilization-Based Scheduling of Flexible Mixed-Criticality Real-Time Tasks
Machine Characterization Based on an Abstract High-Level Language Machine
A Continued-Fraction Analysis of Trigonometric Argument Reduction
UniSched: A Unified Scheduler for Deep Learning Training Jobs With Different User Demands
A Computer-Oriented Factoring Algorithm for NOR Logic Design
Data Broadcasting in SIMD Computers
Fault Tolerance of a General Purpose Computer Implemented by Very Large Scale Integration
X-Block: An Efficient LFSR Reseeding-Based Method to Block Unknowns for Temporal Compactors
Revealing DRAM Operating GuardBands Through Workload-Aware Error Predictive Modeling
Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs
Synthesis of Nonlinear Decision Boundaries by Cascaded Threshold Gates
Comparing Communication Paradigms in Cause-Effect Chains
On-Line Task Migration in Hypercubes Through Double Disjoint Pats
Disaggregated Cloud Memory with Elastic Block Management
Conditional Partial Order Graphs: Model, Synthesis, and Application
Trade-Offs in Test Data Compression and Deterministic X-Masking of Responses
Fault-Tolerant Routing in Distributed Loop Networks
Unified Mitchell-Based Approximation for Efficient Logarithmic Conversion Circuit
Using Quasi-EZ-NAND Flash Memory to Build Large-Capacity Solid-State Drives in Computing Systems
Comments on Duprat and Muller's Branching CORDIC Paper
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
A Figure of Merit for Single-Pass Data Recording Systems
Delay-Optimized Implementation of IEEE Floating-Point Addition
Consistent Global checkpoints that Contain a Given Set of Local Chekpoints
The Minimal Test Set for Multioutput Threshold Circuits Implemented as Sorting Networks
A Fast Leakage-Aware Full-Chip Transient Thermal Estimation Method
Sparse-Iteration 4D CORDIC Algorithms for Multiplying Quaternions
Comments on "Tolerance of Double-Loop Computer Networks to Multinode Failures". IEEE Trans. Comput., vol. 38, no. 5, pp. 738-741, May 1989
Resolving Multiple Responses in an Associative Memory
Framework for Supporting Genomic Operations
Evaluating Robustness of Subnetworks for the Split-Star Network
Minimum Spanning Trees of Moving Points in the Plane
Task Synchronization in Reservation-Based Real-Time Systems
Recognition of Handwritten Characters by Topological Feature Extraction and Multilevel Categorization
On the Generation of Permutations in Magnetic Bubble Memories
Unidirectional Bit/Byte Error Control
Efficient Sketching for Heavy Item-Oriented Data Stream Mining With Memory Constraints
On Digital Differential Analyzer (DDA) Circle Generation for Computer Graphics
R68-42 On Designing Generalized File Records for Management Information Systems
Comments on "Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean Differences"
A Neural Network Implementation of the Moment-Preserving Technique and Its Application to Thresholding
Square Roots and Functional Decompositions of Boolean Functions
On Symmetry Detection
Statistical Approach to Networks-on-Chip
A Class of Algorithms for Ln x, Exp x, Sin x, Cos x, Tan -1 x, and Cot -1 x
Design and Application of Self-Testing Comparators Implemented with MOS PLA's
Balancing Reuse Opportunities and Performance Gains with Subblock Value Reuse
The Memory System of a High-Performance Personal Computer
ADC-Free ReRAM-Based In-Situ Accelerator for Energy-Efficient Binary Neural Networks
Switching Functions of Three Variables
DwarfCode: A Performance Prediction Tool for Parallel Applications
Detection of Multiple Faults in Combinational Logic Networks
Comment on "A pattern recognition experiment with near-optimum results"
Combinatorial Merging and Huffman's Algorithm
Impact of Peripheral-Processor Interference on WCET Analysis of Real-Time Embedded Systems
Low Latency Hybrid CORDIC Algorithm
Anonymous Wireless Authentication on a Portable Cellular Mobile System
An Analysis of Computational Cost in Image Processing: A Case Study
Real-Time Detection of Hogweed: UAV Platform Empowered by Deep Learning
An Analysis on the Performance of Silicon Implementations of Backpropagation Algorithms for Artificial Neural Networks
Reconfigurable Multipipelines for Vector Supercomputers
Synthesis of Application Specific Instructions for Embedded DSP Software
Hybrid Redundancy for Reliable Task Offloading in Collaborative Edge Computing
Cost-Effective Authentic and Anonymous Data Sharing with Forward Security
An Efficient Denoising Architecture for Removal of Impulse Noise in Images
Hybrid-SIMD: A Modular and Reconfigurable Approach to Beyond von Neumann Computing
Comments on "Line Digraph Iterations and Connectivity Analysis of de Bruijn and Kautz Graphs"
RO(SE)${}^{2}$ 2: Search-Efficient Robust Searchable Encryption With Forward and Backward Security
Gate-Interconnection Minimization of Switching Networks Using Negative Gates
UNIYAC-LARC High-Speed Circuitry: Case History in Circuit Optimization
A Hybrid Approach to Refine WCRT Bounds for DAG Scheduling Using Anomaly Classification
Comment on "High Speed Parallel Decimal Multiplication With Redundant Internal Encodings"
A Fully Distributed Method to Detect and Reduce Cut Vertices in Large-Scale Overlay Networks