yusuke1997/dblp-id-title huggingface dataset:
Same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution
FPGA implementation of hardware efficient adaptive filter robust to impulsive noise
LFSR generation for high test coverage and low hardware overhead
High speed hardware architecture to compute galois fields GF(p) montgomery inversion with scalability features
Probabilistic model for nanocell reliability evaluation in presence of transient errors
Locality-protected cache allocation scheme with low overhead on GPUs
Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis
Low-overhead single-event upset hardened latch using programmable resistance cells
Fast sign-detection algorithm for residue number system moduli set {2 n - 1, 2 n , 2 n +1 - 1}
Exploiting parallelism in configurable architectures through custom array mapping
Algorithmic-level exploration of discrete signal transforms for partitioning to distributed hardware architectures
Generic approach for hardening state machines against strong adversaries
Unified multi-objective mapping and architecture customisation of networks-on-chip
Test scheduling for built-in self-tested embedded SRAMs with data retention faults
Network-on-chip heuristic mapping algorithm based on isomorphism elimination for NoC optimisation
Static test compaction for diagnostic test sets of full-scan circuits
An integer linear programming model for mapping applications on hybrid systems
Exploiting memory allocations in clusterised many-core architectures
Hardware Trojans: current challenges and approaches
Charge-based testing BIST for embedded memories
Exploring architectural solutions for energy optimisations in bus-based system-on-chip
Embedding torus in hexagonal honeycomb torus
An optimized knight traversal technique to detect multiple faults and Module Sequence Graph based reconfiguration of microfluidic biochip
Unified multi-objective mapping for network-on-chip using genetic-based hyper-heuristic algorithms
Energy efficient i-cache using multiple line buffers with prediction
On-chip generation of primary input sequences for multicycle functional broadside tests
Partial coding algorithm for area and energy efficient crosstalk avoidance codes implementation
Hetro8T: power and area efficient approximate heterogeneous 8T SRAM for H.264 video decoder
Modelling and simulation of wireless sensor system for health monitoring using HDL and Simulinkw mixed environment
A Systematic Literature Review on the Applications, Models, Limitations, and Future Directions of Generative Adversarial Networks
Behavioural synthesis utilising recursive definitions
Efficient VLSI architectures of lifting based 3D discrete wavelet transform
Binary decision diagram-based synthesis technique for improved mapping of Boolean functions inside memristive crossbar-slices
Reconfigurable broadcast scan compression using relaxation-based test vector decomposition
Simultaneous capture and shift power reduction test pattern generator for scan testing
IRES: An integrated software and hardware interface framework for reconfigurable embedded system
Guest Editorial: Special issue on battery-free computing
Efficient residue number system iterative modular multiplication algorithm for fast modular exponentiation
Light-weight configurable architecture for QRS detection
Homeland security video surveillance system utilising the internet of video things for smart cities
Single event transient tolerant frequency divider
Research on mapping recognition of arc welding molten pool characterisation and penetration state based on embedded system
Energy reduction of the fetch mechanism through dynamic adaptation
HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors
A fault-tolerant core mapping technique in networks-on-chip
ECAP: energy-efficient caching for prefetch blocks in tiled chip multiprocessors
Versatile processor for GF(p m ) arithmetic for use in cryptographic applications
Evaluating fault tolerance on asymmetric multicore systems-on-chip using iso-metrics
ASIC implementation of a hardware-embedded physical unclonable function
Watermarking of Transient Fault-Detectable IP Designs Using Multivariate HLS Scheduling Based Multimodal Security
Fast approximation of the top-k items in data streams using FPGAs
Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems
Design and simulation of reusable IP CORDIC core for special-purpose processors
V th and dual- T ox assignment in 16 nm CMOS technology Design topologies with dual- V th and dual- T ox assignment in 16 nm CMOS technology
Cluster-based approach for improving graphics processing unit performance by inter streaming multiprocessors locality
Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation
Efficient digital implementation of a multi-precision square-root algorithm
Test pattern generation for droop faults
Kernel and layer vulnerability factor to evaluate object detection reliability in GPUs
Built-in time measurement circuits - a comparative design study
Heterogeneity aware power abstractions for dynamic power dominated FinFET-based microprocessors
Corrigendum: Throughput/area optimised pipelined architecture for elliptic curve crypto processor
A radix-8 modulo 2n multiplier using area and power-optimized hard multiple generator
Energy estimation models for video decoders: reconfigurable video coding-CAL case-study
Multi-objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow
Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols
Time-space test response compaction and diagnosis based on BCH codes
High-throughput multi-key elliptic curve cryptosystem based on residue number system
Leveraging design diversity to counteract process variation: theory, method, and FPGA toolchain to increase yield and resilience in-situ
Efficient implementation of low cost and secure framework with firmware updates
Statistical placement for FPGAs considering
Hybrid wire-surface wave interconnects for next-generation networks-on-chip
Improving high-level and gate-level testing with FATE: A functional automatic test pattern generator traversing unstabilised extended FSM
Energy efficiency via thread fusion and value reuse
Mapping application-specific topology to mesh topology with reconfigurable switches
Single-configuration fault detection in applicationdependent testing of field programmable gate array interconnects
Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application
Synchronization in graph analysis algorithms on the Partially Ordered Event-Triggered Systems many-core architecture
Decision heuristic for Davis Putnam, Loveland and Logemann algorithm satisfiability solving based on cube subtraction
Scheme for periodical concurrent fault detection in parallel CRC circuits
Reliable computation with unreliable computers
Low-cost parametric test and diagnosis of RF systems using multi-tone response envelope detection
ActiveGuard: An active intellectual property protection technique for deep neural networks by leveraging adversarial examples as users' fingerprints
Massively parallel modular exponentiation method and its implementation in software and hardware for high-performance cryptographic systems
Processing while routing: a network-on-chipbased parallel system
Scheduling of dual supercapacitor for longer battery lifetime in safety-critical embedded systems with power gating
Analysis and design of moderate inversion based low power low-noise amplifier
Very large scale integration architecture for integer wavelet transform
Fluid-level synthesis unifying reliability, contamination avoidance, and capacity-wastage-aware washing for droplet-based microfluidic biochips
Low-power dual-edge triggered state-retention scan flip-flop
Advanced architecture optimisation and performance analysis of a reconfigurable grid ALU processor
LTL transformation modulo positive transitions
Design and evaluation of a high throughput robust router for network-on-chip
Self-routing, reconfigurable and fault-tolerant cell array
Control-theoretic dynamic voltage scaling for embedded controllers
Simplified bit parallel systolic multipliers for special class of galois field (2 m ) with testability
Reliability-aware simultaneous multithreaded architecture using online architectural vulnerability factor estimation
Probabilistic timing analysis of time-randomised caches with fault detection mechanisms
Simulation-based method for optimum microfluidic sample dilution using weighted mix-split of droplets
Ultra-low power digital front-end for single lead ECG acquisition integrated with a time-to-digital converter
Deterministic logic BIST for transition fault testing
SD-SHO: Security-dominated finite state machine state assignment technique with a satisfactory level of hardware optimization
Comparison of the cost metrics through investigation of the relation between optimal NCV and optimal NCT three-qubit reversible circuits
A Temperature Noise Correction Method for CMOS Spatial Camera Using LSTM With Attention Mechanism
Enhancing delay fault coverage through low-power segmented scan
Dynamic scheduling of tasks for multi-core real-time systems based on optimum energy and throughput
Built-in-self-test technique for diagnosis of delay faults in cluster-based field programmable gate arrays
Accelerated LiDAR data processing algorithm for self-driving cars on the heterogeneous computing platform
March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs
Fragmented software-based self-test technique for online intermittent fault detection in processors
Low overhead DFT using CDFG by modifying controller
Temperature control in three-network on chips using task migration
Tree-based scheme for reducing shared cache miss rate leveraging regional, statistical and temporal similarities
Design of reliable storage and compute systems with lightweight group testing based non-binary error correction codes
Efficient parallelisation of the packet classification algorithms on multi-core central processing units using multi-threading application program interfaces
Field programmable gate arrays-based differential evolution coprocessor: a case study of spectrum allocation in cognitive radio network
Dynamic fault-tolerant routing algorithm for networks-on-chip based on localised detouring paths
High-performance low-power sensing scheme for nanoscale SRAMs
Enhanced power management scheme for embedded road side units
Design and evaluation of fine-grain-mode transition method based on dynamic memory access analysing for variable stages pipeline processor
State retained dual- V th feedback sleeper-stack for leakage reduction
BIST-based diagnosis scheme for field programmable gate array interconnect delay faults
Improved circuit synthesis approach for exclusive-sum-of-product-based reversible circuits
Throughput enhancement for repetitive internal cores in latency-insensitive systems
Machine learning predictive modelling high-level synthesis design space exploration
Performance/energy trade-off in scientific computing: the case of ARM big.LITTLE and Intel Sandy Bridge
Comparative analysis of GALS clocking schemes
Radix-4 3 based two-dimensional FFT architecture with efficient data reordering scheme
Moving towards grey-box predictive models at micro-architecture level by investigating inherent program characteristics
ROM to DSP block transfer for resource constrained synthesis
Asymmetric large size multipliers with optimised FPGA resource utilisation
MPGA: an evolutionary state assignment for dynamic and leakage power reduction in FSM synthesis
Towards a configurable SoC MPEG-4 advanced simple profile decoder
Comparative study of centralised and distributed compatibility-based test data compression
Morphable hundred-core heterogeneous architecture for energy-aware computation
Hybrid cache architecture for high-speed packet processing
Evolvable multi-processor: A novel MPSoC architecture with evolvable task decomposition and scheduling
Skew compensation in energy recovery clock distribution networks
Intellectual property core implementation of decision trees
Implementation of MIMO data reordering and scheduling methodologies for eight-parallel variable length multi-path delay commutator FFT/IFFT
Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment
Design and implementation challenges for adoption of the IEEE 1500 standard
Circuit enclaves susceptible to hardware Trojans insertion at gate-level designs
Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection
eXtended Torus routing algorithm for networks-on-chip: a routing algorithm for dynamically reconfigurable networks-on-chip
Register array-based sum of absolute difference processor with parallel memory system for fast motion estimation
Multiprocessor platform-based design for multimedia
An Efficient RTL Design for a Wearable Brain-Computer Interface
Effectiveness of scan-based delay fault tests in diagnosis of transition faults
Image and video processing platform for field programmable gate arrays using a high-level synthesis
A digital system to emulate wireless networks
Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies
Fast and accurate circuit delay model for FPGA architectural exploration
Prevention slot flow-control mechanism for low latency torus network-on-chip
Diagnostic test-pattern generation targeting open-segment defects and its diagnosis flow
System-on-chip communication architecture: dynamic parallel fraction control bus design and test methodologies
Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug
Four-level realisation of 3-qubit reversible functions
Yield modelling and analysis of bundled data and ring-oscillator based designs
Design and security evaluation of balanced 1-of-n circuits
Multi-layer floorplanning for reconfigurable designs
Extending gate-level diagnosis tools to CMOS intra-gate faults
AMBA bus hardware accelerator IP for Viola-Jones face detection
Guest Editorial: Defect and Fault Tolerance in VLSI and Nanotechnology Systems
Implementation of elementary functions for logarithmic number systems
Modelling and simulation techniques for highly integrated, low-power wireless sensor networks
RTL development of a parameterizable Reed-Solomon Codec
Collaborative fuzzy-based partially-throttling dynamic thermal management scheme for three-dimensional networks-on-chip
Interconnection system for the spiNNaker biologically inspired multi-computer
Improving the speed of decimal division
Methodology to derive context adaptable architectures for FPGAs
E-Commerce Logistics Software Package Tracking and Route Planning and Optimization System of Embedded Technology Based on the Intelligent Era
Rectilinear routing algorithm for crosstalk minimisation in 2D and 3D IC
Scalable GF( p ) Montgomery multiplier based on a digit-digit computation approach
Design of flip-flops with clock-gating and pull-up control scheme for power-constrained and speed-insensitive applications
Hybrid approach based on partial tag comparison technique and search methods to improve cache performance
The analogy of matchline sensing techniques for content addressable memory (CAM)
Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse
Efficient composition of scenario-based hardware specifications
Reducing power of functional units in high-performance processors by checking instruction codes and resizing adders
Variable length mixed radix MDC FFT/IFFT processor for MIMO-OFDM application
KBMA: A knowledge-based multi-objective application mapping approach for 3D NoC
Two-dimensional partially functional broadside tests
Non-uniform random number generation through piecewise linear approximations
FPGA acceleration of rigid-molecule docking codes
Sign detector for the extended four-moduli set { 2 n - 1 , 2 n + 1 , 2 2n + 1 , 2 n + k }
Integration schemes and enabling technologies for three-dimensional integrated circuits
FPGA accelerator for floating-point matrix multiplication
Optimal subgraph covering for customisable VLIW processors
Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality
High-performance elliptic curve cryptography processor over NIST prime fields
Efficient implementation of distributed routing algorithms for NoCs
Sample preparation with multiple dilutions on digital microfluidic biochips
Image feature extraction algorithm based on CUDA architecture: case study GFD and GCFD
Energy-aware instruction cache design using small trace cache
Linking run-time resource management of embedded multi-core platforms with automated design-time exploration
Functional-oriented mask-based built-in self-test
Lower complexity error location detection block of adjacent error correcting decoder for SRAMs
Guest Editorial: Hardware-Assisted Techniques for Security and Protection of Consumer Electronics
ASATM: Automated security assistant of threat models in intelligent transportation systems
Design of a novel energy efficient topology for maximum magnitude generator
Application-specific topology generation algorithms for network-on-chip design
Co-scheduling tasks on multi-core heterogeneous systems: An energy-aware perspective
High performance physical random number generator
New scan compression approach to reduce the test data volume
Verification by parts: reusing component invariant checking results
Guest Editorial: Energy-efficient Computing for Embedded and IoT Devices
Accuracy enhancement of equal segment based approximate adders
EmRep: Energy management relying on state-of-charge extrema prediction
Fast inversion algorithm in GF(2 m ) suitable for implementation with a polynomial multiply instruction on GF(2)
Impact of on-chip network parameters on nuca cache performances
Application modelling and hardware description for network-on-chip benchmarking
Long-run order-independence of vector-based transition systems
Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation
Automated planning for finding alternative bug traces
FPGA-based implementation of floating point processing element for the design of efficient FIR filters
Sparse convolutional neural network acceleration with lossless input feature map compression for resource-constrained systems
Static test compaction for mixed broadside and skewed-load transition fault test sets
Test vector chains for increasing the fault coverage and numbers of detections
Performance and energy aware robust specification of control execution patterns under dropped samples
Power bumps and through-silicon-vias placement with optimised power mesh structure for power delivery network in three-dimensional-integrated circuits
Low-power hybrid complementary metaloxide- semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping
Transparent code authentication at the processor level
Hardware platform for software-defined WCDMA/OFDM baseband receiver implementation
Three-factor control protocol based on elliptic curve cryptosystem for universal serial bus mass storage devices
Optimising power efficiency in trace cache fetch unit
Reconfiguration time overhead on field programmable gate arrays: reduction and cost model
Application of Lightweight Target Detection Algorithm Based on YOLOv8 for Police Intelligent Moving Targets
Multi-mode-segmented scan architecture with layout-aware scan chain routing for test data and test time reduction
Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits
Multi-modal response compaction adaptive to x-density variation
Hardware architectures for eigenvalue computation of real symmetric matrices
P-EdgeCoolingMode: an agent-based performance aware thermal management unit for DVFS enabled heterogeneous MPSoCs
Flexible and high-throughput structures of Camellia block cipher for security of the Internet of Things
Online learning based on a novel cost function for system power management
Efficient test compaction for combinational circuits based on Fault detection count-directed clustering
Fault tolerance for nanotechnology devices at the bit and module levels with history index of correct computation
PSN-aware circuit test timing prediction using machine learning
Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processor
Dynamically reconfigurable systolic array accelerators: A case study with extended Kalman filter and discrete wavelet transform algorithms
Inexact-aware architecture design for ultra-low power bio-signal analysis
Efficient ASIC and FPGA implementation of cube architecture
Design and synthesis of improved reversible circuits using AIG- and MIG-based graph data structures
Networks on chips [editorial]
Binary-coded decimal digit multipliers
Modelling and verification of parameterized architectures: A functional approach
VLSI design of low-cost and high-precision fixed-point reconfigurable FFT processors
Secure distribution infrastructure for hardware digital contents
Accuracy-aware processor customisation for fixed-point arithmetic
Multiplier-less pipeline architecture for lifting-based two-dimensional discrete wavelet transform
Towards power-elastic systems through concurrency management
LUT-based high-speed point multiplier for Goldilocks-Curve448
Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation
VLSI architecture and chip for combined invisible robust and fragile watermarking
Design and evaluation of variable stages pipeline processor with low-energy techniques
Simulation and development environment for mobile 3D graphics architectures
Connecting fabrication defects to fault models and SPICE simulations for DNA self-assembled nanoelectronics
Synthesis and exploration of clock spines
Test compaction methods for transition faults under transparent-scan
Heuristic algorithm for the resource constrained scheduling problem during high-level synthesis
Comments on 'improving the speed of decimal division'
Model order reduction by Miller's theorem and root localisation
FPGA-based implementation of cuckoo search
Embedding of signatures in reconfigurable scan architecture for authentication of intellectual properties in system-on-chip
Integer linear programming model for allocation and migration of data blocks in the STT-RAM-based hybrid caches
Bandwidth-aware routing algorithms for networks-on-chip platforms
Algebraic approach to time borrowing
Is triple modular redundancy suitable for yield improvement?
Critical race-free low-power nand match line content addressable memory tagged cache memory
Evaluation of testability enhancement using software prototype
Two-dimensional, two-channel signal-adapted filter banks
Truncated ternary multipliers
An embedded intelligence engine for driver drowsiness detection
Distributed bus arbitration algorithm comparison on FPGA-based MPEG-4 multiprocessor system on chip
Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles
Temperature gradient-aware thermal simulator for three-dimensional integrated circuits
Memory hierarchy for high-performance and energyaware reconfigurable systems
On-chip evaluation, compensation and storage of scan diagnosis data
Editorial - Selected papers from the 16th IEEE International Symposium on Asynchronous Circuits and Systems
Efficient two phase heuristic routing technique for digital microfluidic biochip
High throughput and secure advanced encryption standard on field programmable gate array with fine pipelining and enhanced key expansion
Energy-efficient LDPC codec design using cost-effective early termination scheme
Advanced calibration techniques for high-speed source-synchronous interfaces