yusuke1997/dblp-id-title huggingface dataset:
Worst-case and average-case analysis of n-detection test sets and test generation strategies
Test-wrapper optimisation for embedded cores in through-silicon via-based three-dimensional system on chips
Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios
SkipCache: application aware cache management for chip multi-processors
Editorial Silicon Debug and Diagnosis
Towards virtual memory support in real-time and memory-constrained embedded applications: the interval page table
Design of experiments and integer linear programming-assisted conjugate-gradient optimisation of high-κ/metal-gate nano-complementary metal-oxide semiconductor static random access memory
High-order Taylor series approximation for efficient computation of elementary functions
High performance and energy efficient single-precision and double-precision merged floating-point adder on FPGA
Exploration and implementation of a highly efficient processor element for multimedia and signal processing domains
High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4
SUBHDIP: process variations tolerant subthreshold Darlington pair-based NBTI sensor circuit
Mastering CMOS variability is the key to success
Efficient hardware structure for extended Euclidean-based inversion over F 2 m
Towards IP integration on SoC: a case study of high-throughput and low-cost wrapper design on a novel IBUS architecture
Soft error rate estimation of combinational circuits based on vulnerability analysis
Architecture for integrated test data compression and abort-on-fail testing in a multi-site environment
Residual vulnerabilities to power side channel attacks of lightweight ciphers cryptography competition finalists
Majority-based evolution state assignment algorithm for area and power optimisation of sequential circuits
Low-power fast Fourier transform hardware architecture combining a split-radix butterfly and efficient adder compressors
Variability compensation for full-swing against low-swing on-chip communication
DICA: destination intensity and congestion-aware output selection strategy for network-on-chip systems
A Galois field-based logic synthesis with testability
Finite state machine-based DRAM power management with early resynchronisation
Thermal-electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints
Hybrid multi-level hardware Trojan detection platform for gate-level netlists based on XGBoost
σ n LBDR: generic congestion handling routing implementation for two-dimensional mesh network-on-chip
Fabrication and characterisation of Al gate n -metal-oxide-semiconductor field-effect transistor, on-chip fabricated with silicon nitride ion-sensitive field-effect transistor
High-throughput dilution engine for sample preparation on digital microfluidic biochips
Efficient design of 15: 4 counter using a novel 5: 3 counter for high-speed multiplication
Power minimisation during field programmable gate array placement
Scheme to minimise short effects of single-event upsets in triple-modular redundancy
Building an accurate hardware Trojan detection technique from inaccurate simulation models and unlabelled ICs
SC Build: a computer-aided design tool for design space exploration of embedded central processing unit cores for field-programmable gate arrays
Routing of asynchronous Clos networks
Evaluation of the soft error assessment consistency of a JIT-based virtual platform simulator
Updating the sets of target faults during test generation for multiple fault models
Refinement-based verification of elastic pipelined systems
Energy-efficient and reliable in-memory classifier for machine-learning applications
Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware
The DFA/DFT-based hacking techniques and countermeasures: Case study of the 32-bit AES encryption crypto-core
Cone-based placement for field programmable gate arrays
Low-power and error protection coding for network-on-chip traffic
Noise-based logic locking scheme against signal probability skew analysis
Simultaneous scheduling and binding for low gate leakage nano-complementary metaloxide-semiconductor data path circuit behavioural synthesis
History-aware, resource-based dynamic scheduling for heterogeneous multi-core processors
HEALERS: a heterogeneous energy-aware low-overhead real-time scheduler
Sensitivity analysis of testability parameters for secure IC design
Predicting mixed-signal dynamic performance using optimised signature-based alternate test
Low power design of phase-change memory based on a comprehensive model
Dynamic global security-aware synthesis using SystemC
Optimised HEVC encoder intra-only configuration
Design of an extended 2D mesh network-on-chip and development of A fault-tolerant routing method
Adaptive error control for nanometer scale network-on-chip links
Low-cost digital signature architecture suitable for radio frequency identification tags
Dependability analysis of cyber physical systems
Efficient post-configuration testing of an asynchronous nanowire crossbar system for reliability
VHDL architecture for IEC 61499 function blocks
Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits
Efficient model checking of PSL safety properties
Editorial - Field-programmable logic and applications
Very-large-scale integration implementation of a 16-bit clocked adiabatic logic logarithmic signal processor
Skewing-based method for reduction of functional crosstalk and power supply noise caused by on-chip buses
Multiple parallel assay operations with cross contamination avoidance in a given biochip
Novel low-overhead roll-forward recovery scheme for distributed systems
Debug enhancements in assertion-checker generation
Introducing KeyRing self-timed microarchitecture and timing-driven design flow
Droop sensitivity of stuck-at fault tests
Signal word-level statistical properties-based activation approach for hardware Trojan detection in DSP circuits
Sizes of test sets for path delay faults using strong and weak non-robust tests
A ROM-less reverse RNS converter for moduli set {2 q ±1, 2 q ±3}
Recycled integrated circuit detection using reliability analysis and machine learning algorithms
Variable ordering for shared binary decision diagrams targeting node count and path length optimisation using particle swarm technique
Memory-efficient buffering method and enhanced reference template for embedded automatic speech recognition system
On multi-cycle test cubes
Static test compaction procedure for large pools of multicycle functional broadside tests
A Configurable Accelerator for CNN-Based Remote Sensing Object Detection on FPGAs
Coarse-grained reconfiguration: dataflow-based power management
Approach to design a compact reversible low power binary comparator
Autonomous temperature control technique in VLSI circuits through logic replication
A FPGA Accelerator of Distributed A3C Algorithm with Optimal Resource Deployment
Utilisation of inverse compatibility for test cost reductions
Functional broadside tests for embedded logic blocks
Fault model and test procedure for phase change memory
Toolchain-based approach to handling variability in embedded multiprocessor system on chips
Fast INC-XOR codec for low-power address buses
Two-stage logarithmic converter with reduced memory requirements
Reducing bypass-based network-on-chip latency using priority mechanism
Statistical analysis of crosstalk-induced errors for on-chip interconnects
Throughput/area optimised pipelined architecture for elliptic curve crypto processor
High-throughput Dickson basis multiplier with a trinomial for lightweight cryptosystems
Accelerating the SM3 hash algorithm with CPU-FPGA Co-Designed architecture
Investigating the role of interconnect surface roughness towards the design of power-aware network on chip
High throughput and area-efficient FPGA implementation of AES for high-traffic applications
High-performance scalable bidirectional mixed radix-2 n serial-serial multipliers
High-performance FPGA implementations of the cryptographic hash function JH
An algorithm for obstacle-avoiding clock routing tree construction with multiple TSVs on a 3D IC
Definition and generation of partially-functional broadside tests
Two-phase colour-aware multicore real-time scheduler
Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array
Enhanced overloaded code division multiple access for network on chip
Compressing fully connected layers of deep neural networks using permuted features
Indicating combinational logic decomposition
GRSNet: An Ultra-Lightweight Neural Network for 3D Point Cloud Classification and Segmentation
Q-scheduler: A temperature and energy-aware deep Q-learning technique to schedule tasks in real-time multiprocessor embedded systems
Soft-error reliable architecture for future microprocessors
Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding
Physical-aware systematic multiple defect diagnosis
A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects
Application-oriented cache memory configuration for energy efficiency in multi-cores
Voltage over-scaling CNT-based 8-bit multiplier by high-efficient GDI-based counters
Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array
Monitoring field-programmable gate array-based processing engines of dependable computer systems
Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks
Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP
On-chip bus thermal analysis and optimisation
Column selection solutions for L1 data caches implemented using eight-transistor cells
Diagnosis of path delay faults based on low-coverage tests
Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches
Reducing the input test data volume under transparent scan
Hardware variant NSP with security-aware automated preferential algorithm
Scheduling configuration memory error checks to improve the reliability of FPGA-based systems
Secure control protocol for universal serial bus mass storage devices
Reset and partial-reset-based functional broadside tests
Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips
Testing ternary content addressable memories with active neighbourhood pattern-sensitive faults
Supporting non-contiguous processor allocation in mesh-based chip multiprocessors using virtual point-to-point links
Write-variation aware alternatives to replace SRAM buffers with non-volatile buffers in on-chip interconnects
An integrated taxonomy of standard indicators for ranking and selecting supercomputers
Robust paradigm for diagnosing hold-time faults in scan chains
Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks
Reducing the system standby power of a personal computer
Simple true random number generator for any semi-conductor technology
Precision tunable RTL macro-modelling cycle-accurate power estimation
Low error fixed-width two's complement squarer design using Booth-folding technique
Adaptive and dynamic reconfigurable multiprocessor system to improve software productivity
Enhanced prefix inclusion coding filter-encoding algorithm for packet classification with ternary content addressable memory
Multi-objective constraint and hybrid optimisation-based VM migration in a community cloud
A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits
Study of the monte-carlo fault injection simulator to measure a fault derating
BFT: a placement algorithm for non-rectangle task model in reconfigurable computing system
Reordering the assembly instructions in basic blocks to reduce switching activities on the instruction bus
Adaptively weighted round-robin arbitration for equality of service in a many-core network-on-chip
P2M-based security model: security enhancement using combined PUF and PRNG models for authenticating consumer electronic devices
Survey of hardware protection of design data for integrated circuits and intellectual properties
Electronic characterisation of atomistic modelling based electrically doped nano bio p-i-n FET
VLSI implementation of anti-notch lattice structure for identification of exon regions in Eukaryotic genes
Novel hazard-free majority voter for n-modular redundancy-based fault tolerance in asynchronous circuits
Area and power-efficient variable-length fast Fourier transform for MR-OFDM physical layer of IEEE 802.15.4-g
Static power model for CMOS and FPGA circuits
Technique for two-dimensional nearest neighbour realisation of quantum circuits using weighted look-ahead
Binary LNS-based naive Bayes inference engine for spam control: noise analysis and FPGA implementation
Built-in fast gather control network for efficient support of coherence protocols
Low-power enhanced system-on-chip design for sequential minimal optimisation learning core with tri-layer bus and butterfly-path accelerator
Ten years of hardware Trojans: a survey from the attacker's perspective
Server-based execution of periodic tasks on dynamically reconfigurable hardware
Block-based two-dimensional wavelet transform running on graphics processing unit
Model validation for embedded systems using formal method-aided simulation
Online task scheduler in 3D-MCPs with TADVA
Decimal floating-point fused multiply-add with redundant internal encodings
Micro-architectural approach to the efficient employment of STTRAM cells in a microprocessor register file
Efficient test compression technique based on block merging
Design-time application mapping and platform exploration for MP-SoC customised run-time management
System-level power management for system-on-a-chip -based mobile devices
Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router
Construction of an adaptive scan network for test time and data volume reduction
Admitting and ejecting flits in wormhole-switched networks on chip
Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation
Research on Adding Global Registration Model in Video Coding With Local Affine Motion Model
Yield-driven design-time task scheduling techniques for multi-processor system on chips under process variation: a comparative study
Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism
HW/SW co-design of dedicated heterogeneous parallel systems: an extended design space exploration approach
Arithmetic module-based built-in self test architecture for two-pattern testing
Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems
Bit-serial and digit-serial GF(2 m )Montgomery multipliers using linear feedback shift registers
Resilient training of neural network classifiers with approximate computing techniques for hardware-optimised implementations
Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips
Coupled variable-input LCG and clock divider-based large period pseudo-random bit generator on FPGA
System-level assertions: approach for electronic system-level verification
Efficient testing and diagnosis of faulty power switches in SOCs
Formal verification methodology for real-time Field Programmable Gate Array
A four-stage yield optimization technique for analog integrated circuits using optimal computing budget allocation and evolutionary algorithms
CUDA memory optimisation strategies for motion estimation
Comparative analysis of network-on-chip simulation tools
Low-cost security aware HLS methodology
Test data compression for system-on-a-chip using extended frequency-directed run-length code
Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures
Manipulation and optimisation techniques for Boolean logic
Hardware architecture for high-speed real-time dynamic programming applications
Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration
Fast and low-power leading-one detectors for energy-efficient logarithmic computing
Comparison of network-on-chip mapping algorithms targeting low energy consumption
Efficient spiking neural network training and inference with reduced precision memory and computing
Performance evaluation of many-core systems: case study with TILEPro64
Hardware accelerated constrained random test generation
A Reconfigurable Coarse-to-Fine Approach for the Execution of CNN Inference Models in Low-Power Edge Devices
Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips
Temperature-aware core management in MPSoCs: modelling and evaluation using MRMs
Strengthened 32-bit AES implementation: Architectural error correction configuration with a new voting scheme
Customised soft processor design: a compromise between architecture description languages and parameterisable processors
Contention-aware selection strategy for application-specific network-on-chip
LFSR-based generation of boundary-functional broadside tests
Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source
Energy-aware online non-clairvoyant multiprocessor scheduling: multiprocessor priority round robin
Quadruple throughput fixed point quarter precision multiply accumulate circuit design
Low-level implementation and side-channel detection of stealthy hardware trojans on field programmable gate arrays
Test vector chains for increased resolution and reduced storage of diagnostic tests
Constant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arrays
Practical realisation of a return map immune Lorenz-based chaotic stream cipher in circuitry
Error analysis of LNS addition/subtraction with direct-computation implementation
Optimising pseudo-random built-in self-testing of fully synchronous as well as multisynchronous networks-on-chip
Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction
RASSS: a hijack-resistant confidential information management scheme for distributed systems
Hybrid timing-address oriented load-store queue filtering for an x86 architecture
Hybrid NEMS-CMOS integrated circuits: A novel strategy for energy-efficient designs
High throughput fault-resilient AES architecture
Optimising the SHA-512 cryptographic hash function on FPGAs
Improving security in cache memory by power efficient scrambling technique
Self-heating burn-in pattern generation based on the genetic algorithm incorporated with a BACK-like procedure
Time-domain interconnect characterisation flow for appropriate model segmentation
Highly adaptive and deadlock-free routing for three-dimensional networks-on-chip
Efficient advanced encryption standard implementation using lookup and normal basis
Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2 n - 1, 2 n , 2 n + 1}
Guest Editorial: Bio-inspired Hardware and Evolvable Systems
Deterministic built-in self-test using split linear feedback shift register reseeding for low-power testing
Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher
Removing constant-induced errors in stochastic circuits
Scan chain configuration based X-filling for low power and high quality testing
In memory computation using quantum-dot cellular automata
Path delay test generation at functional level
Power-aware floorplanning-based power throughsilicon- via technology and bump minimisation for three-dimensional power delivery network
Hardware implementation of a stereo co-processor in a medium-scale field programmable gate array
Reconstruction of a functional test sequence for increased fault coverage
Field programmable gate array prototyping of end-around carry parallel prefix tree architectures
A New Squarer design with reduced area and delay
Extending standard cell library for aging mitigation
Heuristic algorithm for periodic clock optimisation in scheduling-based latency-insensitive design
Approach of genetic algorithm for power-aware testing of 3D IC
Robustness of predictive energy harvesting systems: Analysis and adaptive prediction scaling
High-performance embedded branch predictor by combining branch direction history and global branch history
Globally asynchronous systems of interactive Moore state machines
On the trade-off of mixing scientific applications on capacity high-performance computing systems
RNS multiplication/sum-of-squares units
Design networks-on-chip with latency/ bandwidth guarantees
Low-complexity and differential power analysis (DPA)-resistant two-folded power-aware Rivest-Shamir-Adleman (RSA) security schema implementation for IoT-connected devices
Impact of spintronic memory on multicore cache hierarchy design
Methodology to derive resource aware context adaptable architectures for FPGAs
ON-OFF: a reactive routing algorithm for dynamic thermal management in 3D NoCs
Design space extension for secure implementation of block ciphers
Run-time power and performance scaling in 28 nm FPGAs
Decimal floating-point antilogarithmic converter based on selection by rounding: algorithm and architecture
Field programmable gate array-based acceleration of shortest-path computation
Use of input necessary assignments for test generation based on merging of test cubes
Low-distance path-based multicast routing algorithm for network-on-chips
Energy-delay efficient test
65-nm CMOS low-energy RNS modular multiplier for elliptic-curve cryptography
Fault tolerance and reliability in field-programmable gate arrays
Vertex decomposition method for wirelength problem and its applications to enhanced hypercube networks
Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnects
Advanced verification by automatic property generation
Output remapping technique for critical paths soft-error rate reduction
Reconfigurable baseband processing architecture for communication
Singular perturbation theory
Szemerédi's Theorem
Lattice quantum field theory
Chaotic spiking oscillators
Transistor-based chaotic oscillator
Intracellular recording
Whisking pattern generation
Multiple scale analysis
NETMORPH
Bogoliubov-Parasiuk-Hepp-Zimmermann renormalization scheme
Linear multistep method
Matiyasevich theorem
Cancelable biometrics
Models of deep brain stimulation
Tactile Sensors
Magneto-convection
Planetary formation and migration
Post-decision wagering
Topological dynamics
Matrix and Operator Trace Inequalities
Sustainable Operations
Linear algebra - software issues
Delay partial differential equations
Time's arrow and Boltzmann's entropy
Relativistic Celestial Mechanics
Topological transitivity
Attractor dimensions
FitzHugh-Nagumo model
Aplysia operant conditioning
S1 microcircuits
Renormalization group for non-relativistic fermions
Special relativity: kinematics
Electrical properties of cell membranes
G protein-coupled receptor
The R-matrix theory in nuclear and atomic physics
Hamiltonian normal forms
Neutrino astronomy
Neuronal noise
Computational astrophysics
Fano inequality
Bradykinesia models of Parkinson's disease
Fuzzy control
Coherent state (Quantum mechanics)
Lymnaea learning and memory
Method of lines
Modulation of memory
S1 laminar specialization
Cataplexy
Control of mechanical systems
XPPAUT
Lymnaea
Painful touch
Pleurobranchaea
Bethe-Salpeter equation (origins)
Rotation theory
Cellular mechanisms of morphogenesis
Voltage-sensitive dye
Archontis dynamo
Pearce-Hall error learning theory
Synchronization of extended chaotic systems
Jakobson theorem
Haptic saliency
Interoception
Computational Aspects of Mobile Membranes, Brane Calculi and Mobile Ambients
Corollary discharge in primate vision
Lattice gauge theories
Fuzzy C-means cluster analysis
Vibrissal thalamic modes