yusuke1997/dblp-id-title huggingface dataset:
Extracting Motor Unit Firing Information by Independent Component Analysis of Surface Electromyogram: A Preliminary Study Using a Simulation Approach
A randomized model of the hypercolumn neural network for gesture recognition
An Adaptive Impedance Control Scheme for Constrained Robots
Reverse Logistics in the Computer Industry
Temporal knowledge discovery with self-organizing neural networks
Genetic algorithms and extraction of rules for detection of short DNA motifs
Content-based Profiling of Image Collections: a SOM-based Approach
Evolving Optimal Multi-Objective Hardware Using Strength Pareto Evolutionary Algorithms
Unmanned aircraft control on the trajectory
Directed Multi-Objective Optimization
An adaptive sumarizing control chart
An Algorithm for Accurate Measurement of Corneal Thickness Using Ultrasound RF Signal
Understanding the Dynamics of IS Value Creation in an Inter-organizational Context
Control Of Flow Cycles In An Ion Exchange Desalination Pilot Plant Using Labviewtm
Synthesis of Read-Once Digital Hardware with Reduced Energy Delay Product
Application of a Systems Methodology in the Diagnosis of the Organizational Culture in a Telecommunications Company
Systems Thinking - a Studie of Alternatives of R. Flood, M. Jackson, W. Ulrich, and G. Midgley
Editorial - Special Issue: Soft Systems Approaches to Information and Communication Technology problems
Special Issue On Multi-Objective Evolution: Editorial
A framework for extracting information with semantics from the Web - An application to knowledge discovery for Web agents
Applications of quadratic forms to modeling and simulations of dynamical systems
Recursive Filter Design for Estimating Time Varying Multijoint Human Arm Viscoelasticity
A general neural framework for classification rule mining
Nonlinear self-turning controller for Hammerstein plants with application to a pressure tank
Application of EFUNN for the Classification of Handwritten Digits
Segregative Genetic Algorithms (SEGA): A hybrid superstructure upwards compatible to genetic algorithms for retarding premature convergence
Business Engineering with Mobile Workforce Solutions
Editorial message from the Editor-in-Chief
Recurrent neural network-based quadratic optimisation training algorithm for feedforward neural networks
The generative topographic mapping as a principal model for data visualization and market segmentation: an electronic commerce case
Towards a Critical Systems Approach to Policy Formulation in Organizations
Ethics of Business Continuity and Disaster RecoveryTechnologies: a Conceptual Orientation
Minimum Jerk Reaching Movements of Human Arm with Mechanical Constraints at Endpoint
Editorial: Broadening the Scope of IJCSS
Structure of multi-agent tutoring system and its application in aeronautical training
A Satisfying Game Theoretic Framework for Retrieving Relevant Objects from a Database
Fuzzy gait control of an hexapod walking machine
Some Implementation Issues of Heuristic Methods for Motif Extraction from DNA Sequences
The prediction of financial distress using structured financial data from the internet
Evolving Computation Offers Potential for Estimation of Pest Establishment
Towards a Better Understanding of Stakeholders' Roles in Software Customization
Direct adaptive neural control for turning complex rotating profiles
The Impact of Computer Systems such as Interanet on Human Behaviour
A Methodology and a System for Adaptive, Integrated Speech and Image Learning and Recognition
Information from the Internet and Health
AI-based discrete sliding-mode control for real-time implementation
A clustering algorithm for extracting rules from supervised neural network models in data mining tasks
Application Of Evolutionary Algorithm In Supply Chain Management
A Field Experiment on the Effect of Task Decomposition on the Quality of Decisions in a Group Support Environment
A double-loop self-tuning PID controller with application to nonlinear systems
Creating rules from trained networks using genetic algorithms
Self-Optimization Combined with Fuzzy Logic Control for Ball Mill
AST Pre-Processing For The Sliding Window Method Using Genetic Algorithms
Message from the Guest Editor
Automated design approaches for multi-domain dynamic systems using bond graphs and genetic programming
Analysis based on sub-samples: An application to survival analysis
Insights on the relationship between probability of misclassification and information transfer through classifiers
Simulations of tree destruction by elephant using Monte Carlo methods
A discrete-time recurrent neural network for image restoration from its Fourier spectrum magnitudes
Semantic Web And Peer-To-Peer: Integration And Interoperability In Industry
Complexity results on open shop scheduling to minimize total cost of operations
A Multi-Objective Evolutionary Algorithm Using Neural Networks to Approximate Fitness Evaluations
Combining Soft Systems Methodology (SSM) Techniques and Data Envelopment Analysis in an Exploratory Analysis of the Use of Technology Consultants for IS Implementation
A Dynamic and Adaptive Bargaining Algorithm for Intelligent Selling Agents in Electronic Commerce
Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs
A Fast Architecture-Level Thermal Analysis Method for Runtime Thermal Regulation
Compact and Low Power 11T-2MTJ Non-Volatile Ternary Content Addressable Memory Cell with High Sense Margin
Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection
Forecasting-Based Dynamic Virtual Channel Management for Power Reduction in Network-on-Chips
Power and Design for Test: A Design Automation Perspective
Low-Power CMOS Ramp Generator Circuit for DC-DC Converters
Exploiting Temporal Discharge Current Information to Improve the Efficiency of Clustered Power-Gating
Robust FinFET Memory Circuits with P-Type Data Access Transistors for Higher Integration Density and Reduced Leakage Power
A Programmable Oversampling CMOS Delta-Sigma Analog-to-Digital Converter for Low-Power Interface Electronics
Improving Energy Efficiency of Virtual Machines with Timer Tick Variations
Variable Gain Potentiostat Architecture for Glucose Sensing from Blood and Tear Fluid
A Low Power Built-in Self-Test Scheme Based on Overlapping Bit Swapping Linear Feedback Shift Register
CMOS Proportional-to-Absolute Temperature Current Reference for Low Voltage Operation
A Low Power Wearable Device for Real-Time Electrocardiogram Monitoring and Cardiovascular Arrhythmia Detection for Resource Constrained Regions
Heuristic on a Novel Power Management System Cooperating with Compiler
A 3-Bit Pseudo Flash ADC Based Low-Power CMOS Interface Circuit Design for Optical Sensor
Smart Control of Internal Supply Voltage Spikes in a Low Voltage DC-DC Buck Converter
SmartDPM: Machine Learning-Based Dynamic Power Management for Multi-Core Microprocessors
Dynamic Energy Optimization in Network-on-Chip-Based System-on-Chips
Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan
A Special Section On Machine Learning and Artificial Intelligence In Low Power Electronics
Programmable Current Source Design Dedicated to an Advanced Cochlear Implant Micro-Stimulator
Versatile CMOS Current Conveyor for Digital VLSI Systems with Low-Voltage Power Supply
Static Random Access Memory Cells with Intrinsically High Read Stability and Low Standby Power
Energy Efficient Lifetime Reliability-Aware Checkpointing for Real-Time System
Selected Peer-Reviewed Articles from the PATMOS 2008 Workshop
A Multiple Input Floating Gate Based Arithmetic Logic Unit with a Feedback Loop for Digital Calibration
Design and Analysis of Sub-DT Sub-Domino Logic Circuits for Ultra Low Power Applications
A 6-Wire Plug and Play Clockless Distributed On-Chip-Sensor Network in 28 nm UTBB FD-SOI
Energy Efficient Network-on-Chip Architectures for Many-Core Near-Threshold Computing System
Design and Power Analysis of New Coplanar One-Bit Full-Adder Cell in Quantum-Dot Cellular Automata
Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing
2.4-/5.2-GHz Concurrent Dual-Band Wireless Local Area Network Transmitter
A Special Issue on Low Power Design and Verification Techniques
Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level
Survey of Hardware Systems for Wireless Sensor Networks
A Novel Low Power Three-Input OR/XNOR Gate Design
An Evolutionary Algorithm Approach to Stress Program Generation During Burn-In
A Power-Driven Stochastic-Deterministic Hierarchical High-Level Synthesis Framework for Module Selection, Scheduling and Binding
Design and Analysis of Robust Spin Transfer Torque Magnetic Random Access Memory Bitcell Using FinFET
Microstrip Filter Against the Crosstalk Effect in Planar Power Devices
Low Power and Energy Efficient Asynchronous Design
Digitally Assisted Analog: An Anti-Clipping Function for Class-D Audio Amplifier
Selected Articles from the VARI 2011 Workshop
Low Power Test Generation for Path Delay Faults
A 1.9 µ W Transient-Enhanced Low-Dropout Regulator with Voltage-Spike Suppression
Power Optimization Techniques for High-Level Designs Using Multiple Voltage Components for Low Power Consumption
Automotive Reliable Memories Integrated into an Ultra-Low Power 40 nm CMOS Logic Process
Radio-Frequency Performance Degradation in CMOS Divide-by-3 Injection-Locked Frequency Divider Due to Hot Carrier Effects
A Special Section on Industrial Experiences in Low Power Electronics
Exploring a Low-Cost and Power-Efficient Hybridization Technique for 3D NoC-Bus Hybrid Architecture Using LastZ-Based Routing Algorithms
CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff
Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays
Resistive Random Access Memory Variability and Its Mitigation Schemes
A Power Efficient Regulated Charge Pump Based on Charge Sharing for Contactless Devices: An Alternative to Four-Phase Charge Pumps
Design of Hybrid Low Voltage DC/DC Converters Based on Power Efficiency
Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications
Circuit Sensing Techniques in Magnetoresistive Random-Access Memory
Ultra-Thin Body and Buried Oxide (UTBB) FDSOI Technology with Low Variability and Power Management Capability for 22 nm Node and Below
A 45 nm 10T Dual-Port SRAM with Shared Bit-Line Scheme for Low Power Operation
4-Switch Buck-Boost DC-DC Converter: A Case Study
X-DNNs: Systematic Cross-Layer Approximations for Energy-Efficient Deep Neural Networks
Impact of Power Supply Voltage Variations on FPGA-Based Digital Systems Performance
An Optimized Super-Junction VDMOS with Breakdown Voltage Over 600 V
Ultra Low Voltage and Low Power Biopotential Amplifier with High Electromagnetic Interference Immunity
Energy-Efficient Dual-Voltage Design Using Topological Constraints
Power Modeling and Exploration of Dynamic and Partially Reconfigurable Systems
Post Optimization of a Clock Tree for Dynamic Clock Tree Power Reduction in 45 nm and Below Technology Nodes
Performance Improvement of Soft Switching DC-DC Boost Converter for Photovoltaic (PV) Applications
Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays
New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET
Defect Tolerant Voter Designs Based on Transistor Redundancy
Design of Peripheral Circuits for the Implementation of Memory Array Using Data-Aware (DA) SRAM Cell in 65 nm CMOS Technology for Low Power Consumption
Design and Implementation of Low-Power Bloom Filters for Deep Packet Inspection
Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization
Selected Peer Reviewed Articles from the 17th "IEEE Latin-American Test Symposium, " Foz do Iguaçu, Brazil, April 6-8, 2016
Power-Efficient Application of Sleep Transistors to Enhance the Reliability of Integrated Circuits
Robust Low Power Embedded SRAM: From System Considerations to Cell Design
Enhanced Statistical Blockade Approaches for Fast Robustness Estimation and Compensation of Nano-CMOS Circuits
Low-Power, Battery-Operated, Large-Bandwidth Analog Integrated DC/DC Step-Down Converters
Design and Verification of Analog CMOS Circuits Using the g m / I D -Method with Age-Dependent Degradation Effects
Triple Reduced Surface Field Drain Extended MOS Device Design and Its RF Performance Evaluation for Sub-Micron RF SoC Platform
Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits
Chip Multiprocessor Performance Modeling for Contention Aware Task Migration and Frequency Scaling
High Resolution Temperature Dependent Timing Model in Digital Standard Cell Designs
Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability
Accurate Logic-Level Current Estimation for Digital CMOS Circuits
Ternary Flip-Flops Based on Emerging Sub-32 nm Technology Nodes
Energy-Efficient and High-Speed Robust System Design for Remote Cardiac Health Monitoring
Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style
Near-Threshold Computing of Clocked Adiabatic Logic with Complementary Pass-Transistor Logic Circuits
Complementary Metal Oxide Semiconductor Amplifier Behaviour Considering Different Points of Electromagnetic Interference Injection
A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes
Robust Self-Collapsing Level-Shifter for Wide Voltage Operation
A Low-Power Parallel Architecture for Finite Galois Field GF(2 m ) Arithmetic Operations for Elliptic Curve Cryptography
Low Noise and Fast Locking Phase Locked Loop Using a Variable Delay Element in the Phase Frequency Detector
Time Management for Low-Power Design of Digital Systems
A 1.3- μ W, 0.6- μ m CMOS Current-Frequency Analog-Digital Converter for Implantable Blood-Glucose Monitors
Energy Consumption Optimized Scheduling Algorithm for Clustered VLIW Architectures
A Fixed Frequency Duty-Ratio Based Digital Sliding-Mode Controller for DC-DC Buck Converter
Automatic Design of Low-Power Low-Voltage Analog Circuits Using Particle Swarm Optimization with Re-Initialization
A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters
An Ultra-Low Power Charge Redistribution Successive Approximation Register A/D Converter for Biomedical Applications
A Bus Switch Coding System with Minimal Hardware Demand
Hybrid Fuel Cell Power System for Electric Vehicles Application
Accurate Energy-Aware Workload Distribution for Wireless Sensor Networks Using a Detailed Communication Energy Cost Model
Low Power 28 nm Fully Depleted Silicon on Insulator 2.45 GHz Phase Locked Loop
A Flexible Architecture for Finite Field Galois Fields(2 m ) Arithmetic Processor
A Low Power Novel Encoding Technique for RC Modelled VLSI Interconnects
MLTimer: Leakage Power Minimization in Digital Circuits Using Machine Learning and Adaptive Lazy Timing Analysis
An Ultra-Low Power and High Performance Single Ended Sense Amplifier for Low Voltage Flash Memories
A Robust Reliable and Low Complexity on Chip f-QRS Detection and Identification Architecture for Remote Personalized Health Care Applications
Replica Tracked Post Silicon Trimming Enabled Negative Bit Line Voltage Based Write Assist Scheme in SRAM Design
Intelligate: An Algorithm for Learning Boolean Functions for Dynamic Power Reduction
Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test
Design, Test and Optimization of Inductive Coupled Coils for Implantable Biomedical Devices
Junctionless Silicon-Nanowire Gate-All-Around Tunnel Field Effect Transistor
Ultra Low Power Asynchronous Charge Sharing Logic
Design and Implementation of Extended 16 Bit Co-Operative Arithmetic and Logic Unit (CALU) for 16 Bit Instructions
An Approach for Low Power Design of Power Gated Finite State Machines Considering Partitioning and State Encoding Together
Spin Transport in Single Layer Germanene: The Role of Electron Electron Scattering
CMOS Phase-Locked Loop Circuits and Hot Carrier Effects
Performance Tradeoffs in the Design of Low-Power SRAM Arrays for Implantable Devices
Statistical Power Analysis for High-Performance Processors
An Optimal Leakage-Aware Approach for Nano-CMOS Post-Physical-Optimization
Design and Implementation of Field Programmable Gate Array based Digital Pulse Width Modulator for Synchronous Buck Converter
Vector Cross Product and Coordinate Rotation Based n D Hybrid FastICA
On the Suitability of Single-Walled Carbon Nanotube Bundle Interconnects for High-Speed and Power-Efficient Applications
An Optimum Inexact Design for an Energy Efficient Hearing Aid
A 65 nm CMOS Ultra-Low-Power Impulse Radio-Ultra-Wideband Emitter for Short-Range Indoor Localization
Optimization of Softmax Layer in Deep Neural Network Using Integral Stochastic Computation
Serial Data Driven Cyclic Redundancy Check Generator for Low Power RFID Applications
Enhancing the Static Noise Margins by Upsizing Length for Ultra-Low Voltage/Power/Energy Gates
A Semi-Analytical Approach to Study the Energy Consumption of On-Chip Networks Testing
Reducing Power of Memory Hierarchy in General Purpose Graphics Processing Units
PoETE: A Method to Design Temperature-Aware Integrated Systems
A 65 nm Design of 0.6 V/8.98 μ W Process-Voltage-Aware Dynamic Analog Comparator for High Speed Data Reconstruction Applications
A Special Section on Low Power Electronics: A Compilation of Emerging Ideas and Efficient Solutions
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption
Optimization of FinFET-Based Gain Cells for Low Power Sub- V T Embedded DRAMs
A Hardware Description Language-Based Serial Link for Multicores SoC/NoC Interconnect
A Formally Verified Peak-Power Reduction Technique for Hardware Synthesis from Concurrent Action-Oriented Specifications
TILTS: A Fast Architectural-Level Transient Thermal Simulation Method
Power Modeling and Runtime Performance Optimization of Power Limited Many-Core Systems Based on a Dynamic Adaptive Approach
Power and Energy Issues on Lightweight Cryptography
High-Level Power Analysis for Intellectual Property-Based Digital Systems
Selected Articles from the NGCAS 2017 Conference
Low-Power Perceptron Branch Predictor
Energy Estimation of the Memory Subsystem in Multiprocessor Systems
A Low Cost Design of Time Division Multiplexing Based 3rd Order Continuous-Time Incremental ΣΔ Modulator with Excess Loop Delay
Design of a Low Cost RGB Color Sensor for Rural Health Care Applications
A Configurable Architecture to Limit Inrush Current in Power-Gated Reconfigurable Devices
Low Power SR-Latch Based Flip-Flop Design Using 21 Transistors
High-Level Synthesis for Low Power Hardware Implementation of Unscheduled Data-Dominated Circuits
Analysis and Optimization of MPSoC Reliability
Adiabatic Logic Based Low-Power Precomputation-Based Content Addressable Memory Parameter Extractor Design
Optimisation of Gate-Drain/Source Overlap in 90 nm NMOSFETs for Low Noise Amplifier Performance
Low-Power Circuit Techniques for Epileptic Seizures Detection and Subsequent Neurostimulation
Effect of Channel Thickness and Doping Concentration on Sub-Threshold Performance of Graded Channel and Gate Stack DG MOSFETs
Power-Accuracy Trade-Offs for Heartbeat Classification on Neural Networks Hardware
Lower V DD Operation of FPGA-Based Digital Circuits Through Delay Modeling and Time Borrowing
Exploiting Speculation Cost Prediction in Power-Aware Applications
A Passive Radio Frequency Amplifier for Radio Frequency Identification Tags
Gate Sizing and Vt Assignment for Active-Mode Leakage Power Reduction
A Modular Design to Synthesize Symmetric Functions Using Quantum Quaternary Logic
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization
An Energy Efficient E-Skin Embedded System for Real-Time Tactile Data Decoding
Analytical Model for Key Electrical Parameter of Superjunction VDMOS
Characterization of GaN/(4H)SiC Heterostructure Vertical pn Power Diode
Modeling of Inherent Losses of Fully Integrated Switched Capacitor DC-DC Converters
A Multiple Input Variable Output Switched Capacitor DC-DC Converter for Harnessing Renewable Energy and Powering LEDs
Low Power Main Memory Configuration and Tasks Allocation
Selected Articles from the PATMOS 2009 Workshop
A Binary Decision Diagram Structure for Probabilistic Switching Activity Estimation
Ultrathin Compound Semiconductor in Bulk Planar Junctionless Transistor for High-Performance Nanoscale Transistors
A Novel High Frequency Low Voltage Low Power Current Mode Analog to Digital Converter Pipeline
Improving the Performance of Static CMOS Gates by Using Independent Bodies
Radiation Effects in Low Power and Ultra-Low Power Voltage References
Runtime Leakage Power Reduction Using Loop Unrolling and Fine Grained Power Gating
Ultra-Low Voltage Realization of the Tau-Cell and Its Application for Filtering Electrocardiogram Signals
Ab-Initio Modeling of Effect of Boron and Phosphorus Doping in CoFe/MgO Magnetic Tunnel Junctions
Power Distribution Techniques for Dual VDD Circuits
Selective Forward Body Bias for High Speed and Low Power SRAMs
Static Power Analysis and Estimation in Ternary Content Addressable Memory Cells
Implementation of Virtual Instruments as a Power Quality Analysis Tool
An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs
Efficient Test Set Modification for Capture Power Reduction
Power-Gated Arithmetic Circuits for Energy-Precision Tradeoffs in Mobile Graphics Processing Units
Cross-Layer Error Resilience and Its Application to Wireless Communication Systems
A Simplified Mathematical Toolbox for Thermal Runaway Analysis
Towards the Simulation Based Design and Validation of Mobile Robotic Cyber-Physical Systems
Optimizing Memory Efficiency for Deep Convolutional Neural Network Accelerators
An Alternative Hybrid Power-Aware Adder for High-Performance Processors
Soft-Switched High Step-Up Converter for Low Voltage Sustainable Energy Systems
A 0.4 V 520 nW 990 μ m 2 Fully Integrated Frequency-Domain Smart Temperature Sensor in 65 nm CMOS
Approximate Computing Techniques for Low Power Implementation of Reconfigurable Coordinate Rotation Digital Computer Circuits
A Low Power, Scalable and Runtime Customizable Microprocessor Architecture for Image Processing
Ultra-Low Voltage Analog Pre-Processing Stage for Realizing the Pan-Tompkins Algorithm
Inter-Plane Communication Methods for 3-D ICs
Towards Approximate Computing with Quantum-Dot Cellular Automata
Low Voltage, Low Power G m -C Filter for Low Frequency Applications
A Novel IR-Drop Tolerant Transition Delay Fault Test Pattern Generation Procedure
Particle Swarm Optimization Based Reversible Circuit Synthesis Using Mixed Control Toffoli Gates
A 52.6 mW 10-bit, 100 MS/s Pipelined CMOS Analog-To-Digital Converter
Performance Analysis and Comparison of Surface and Interior Bearingless Permanent Magnet Synchronous Motors
Sleep Mode and Wakeup Method for OpenFlow Switches
Analysis and Improvement of Delay-Insensitive Asynchronous Circuits Operating in Subthreshold Regime
Non-Hysteretic Behavior of Super Steep Ferroelectric Negative Capacitance Tunnel Field Effect Transistor Based on Body Profile Engineering
EX-DRIVE: An Execution Driven Functional Verification Flow
A Specialized Static Content Addressable Memory for Longest Prefix Matching in Internet Protocol Routing
Arithmetic-Level Instruction Based Energy Estimation for FPGA based Soft Processors
Low Energy and Area Efficient Nonbinary Capacitor Array Based Successive Approximation Register Analog-to-Digital Converter
Exploring Circuit Adaptation for Yield Optimization of Low-Power All-Digital Phase-Locked Loops
Full System Emulation of Approximate Memory Platforms with AppropinQuo
Power Aware High Level Synthesis of Hardware Coprocessors