yusuke1997/dblp-id-title huggingface dataset:
Microwave Logic Circuits Using Diodes
Diagnosabilities of Hypercubes Under the Pessimistic One-Step Diagnosis Strategy
Dapper: An Adaptive Manager for Large-Capacity Persistent Memory
Functional Fault Simulation as a Guide for Biased-Random Test Pattern Generation
Logic Hazards in Threshold Networks
STEM: A Thermal-Constrained Real-Time Scheduling for 3D Heterogeneous-ISA Multicore Processors
Autocorrelations for Boolean Functions of Noiselike Periodic Sequences
PRESTO: A Penalty-Aware Real-Time Scheduler for Task Graphs on Heterogeneous Platforms
Logic Equations for a Built-In Square Root Method
Initializability Consideration in Sequential Machine Synthesis
Counter-Based Cache Replacement and Bypassing Algorithms
Low Overhead Multiprocessor Allocation Strategies Exploiting System Space Capacity for Fault Detection and Location
Homomorphic Property-Based Concurrent Error Detection of RSA: A Countermeasure to Fault Attack
On the Efficiency of Universal Machines
A Path-Based Topology-Agnostic Fault Diagnosis Strategy for Multiprocessor Systems
The Simplification of Sequential Machines with Input Restrictions
Tree Realizations of Iterative Circuits
Ternary Scan Design for VLSI Testability
SCAUL: Power Side-Channel Analysis With Unsupervised Learning
A Method of Theoretical Analysis of High-Speed Junction Diode Logic Circuits
Debugging Parallel Programs with Instant Replay
Parallel Decodable Two-Level Unequal Burst Error Correcting Codes
An Approximation Algorithm for Scheduling Tasks on Varying Partition Sizes in Partitionable Multiprocessor Systems
Least-Square Dead-Time Approximations
VLSI Architectures for Computing Multiplications and Inverses in GF (2 m )
The Simplification of Multiple-Output Switching Networks Composed of Unilateral Devices
Cache Replacement Algorithms with Nonuniform Miss Costs
A Highly OR-Parallel Inference Machine (Multi-ASCA) and Its Performance Evaluation: An Architecture and Its Load Balancing Algorithms
Finite Buffer Analysis of Multistage Interconnection Networks
Multiple-Fault Detection and Location in Fan-Out Free Combinational Circuits
A Computer Simulation of Electrical Loss and Loading Effect in Magnetic Recording
A Caching Scheme for Routing in Mobile Ad Hoc Networks and Its Application to ZRP
Least-Latency Routing over Time-Dependent Wireless Sensor Networks
Feature Evalution with Measures of Probabilistic Dependence
Refinable Bounds for Large Markov Chains
Realizations of Sequential Machines Using Random Access Memory
Measured Flip-Flop Responses to Marginal Triggering
Axiomatic Majority-Decision Logic
WhistleBlower: A System-Level Empirical Study on RowHammer
A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays
Multidomain Fault Models Covering the Analog Side of a Smart or Cyber-Physical System
On Statistical Analysis of a DTL Gate
Parallel Generation of Binary Search Trees
Time-Division Optical Communications in Multiprocessor Arrays
A Performance Model of Pipelined K-ary n-cubes
Retrieval-Guaranteed Location-Aware Information Brokerage Scheme in 3D Wireless Ad Hoc Networks
Optimal Checkpoint Selection with Dual-Modular Redundancy Hardening
Localized Broadcasting with Guaranteed Delivery and Bounded Transmission Redundancy
Simulation of a Biological System on an Analog Computer
Self-Routing Quantum Sparse Crossbar Packet Concentrators
On the Microprocessor Solution of Ordinary Differential Equations Using Integer Arithmetic
Efficient Multiplier Architectures for Galois Fields GF(2 4n )
Trajectory Optimization and Power Allocation for Multi-UAV Wireless Networks: A Communication-Based Multi-Agent Deep Reinforcement Learning Approach
Regular Expressions and State Graphs for Automata
Telepathy: A Lightweight Silent Data Access Protocol for NVRAM+RDMA Enabled Distributed Storage
WHISTLE: CPU Abstractions for Hardware and Software Memory Safety Invariants
An Efficient Non-Linear Cost Compression Algorithm for Multi Level Cell Memory
A GaAs-Based Microprocessor Architecture for Real-Time Applications
Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions
HPDK: A Hybrid PM-DRAM Key-Value Store for High I/O Throughput
Efficient On-Line Proofs of Equalities and Inequalities of Formulas
Unit-Distance Error-Checking Codes
A Note on Optimum Pattern Recognition Systems
Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs
A New Construction of Massey-Omura Parallel Multiplier over GF (2 m )
Synthesis of Vector Networks
Unifying Maximum Cut and Minimum Cut of a Planar Graph
Operational Analog Simulation of the Vibration of a Beam and a Rectangular Multicellular Structure
VLSI Implementation for One-Dimensional Multilevel Lifting-Based Wavelet Transform
Hiding Relaxed Memory Consistency with a Compiler
Boundary Points of Threshold Functions
Boolean Features of Sign-Flipping and Signed-Carry Logic in Base -2
Compiler-Assisted Synthesis of Algorithm-Based Checking in Multiprocessors
Reconfigurability and Reliability of Systolic/Wavefront Arrays
An Integrated Planning and Adaptive Resource Management Architecture for Distributed Real-Time Embedded Systems
Design of a Dynamically Programmable Logic Gate
Rate Monotonic Analysis: The Hyperbolic Bound
ILLIAC II-A Short Description and Annotated Bibliography
Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience
A Signed-Digit Architecture for Residue to Binary Transformation
Some Properties of Ternary Threshold Logic
On the Conversion of Hensel Codes to Farey Rationals
On Magnetic Bubble Logic Circuits
A Least Mean Squares CUBIC Algorithm for On-Line Differential of Sampled Analog Signals
Dense Trivalent Graphs for Processor Interconnection
DART: A Programmable Architecture for NoC Simulation on FPGAs
Code Manipulation for Virtual Platform Integration
An Algorithm for Testing 2-Asummability of Boolean Functions
An Analog-to-Digital Converter
A New Representation for Faults in Combinational Digital Circuits
Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM in Embedded Systems
A Neural Network Approach to the Labeling of Line Drawings
Parameter-Aware I/O Management for Solid State Disks (SSDs)
Adaptive Page Migration Policy With Huge Pages in Tiered Memory Systems
A Minimum Area VLSI Network for O (log n ) Time Sorting
Optimal Piecewise Polynomial L 2 Approximation of Functions of One and Two Variables
On Determination of Optimal Distributions of Carry Skips in Adders
Deriving Logic Systems for Path Delay Test Generation
Detecting I/O and Internal Feedback Bridging Faults
A Sequential Magnetic-Core Storage System
Table-Lookup/Interpolation Function Generation for Fixed-Point Digital Computations
Stateful Serverless Application Placement in MEC With Function and State Dependencies
Visual Learning from Multiple Views
Reconfigurable Intelligent Surface Assisted UAV-MCS Based on Transformer Enhanced Deep Reinforcement Learning
Real-Time Analog-Digital Computation
Incorporation of Optimal Timeouts into Distributed Real-Time Load Sharing
Closure Partition Method for Minimizing Incomplete Sequential Machines
The Reliability of Linear Feature Extractors
The Montgomery Inverse and Its Applications
Structural and Tree Embedding Aspects of Incomplete Hypercubes
Analysis and Methods for Detection of Some DC Amplifier Errors
MUCH: Multithreaded Content-Based File Chunking
Two-Dimensional Microprocessor Pipelines for Image Processing
A Simple Approximation Algorithm for Two Problems in Circuit Design
A Cost-Effective Distribution-Aware Data Replication Scheme for Parallel I/O Systems
Exploiting Application/System-Dependent Ambient Temperature for Accurate Microarchitectural Simulation
Improved Yield Models for Fault-Tolerant Memory Chips
Reduction of Output Dependency in Sequential Machines
A Heuristic Algorithm for the Testing of Asynchronous Circuits
CurIAs: Current-Based IC Authentication by Exploiting Supply Current Variations
Scheduling Analysis of Imprecise Mixed-Criticality Real-Time Tasks
Optimizing Multi-AAV Cooperative Tracking for Real-Time Applications in Network-Challenged Environments
Division Algorithms and Implementations
Compact Dictionaries for Fault Diagnosis in Scan-BIST
Comments on "Error-Correcting Codes for Byte-Organized Arithmetic Processors"
Reduction of Sizes of Decision Diagrams by Autocorrelation Functions
Granular Evaluation of Anomalies in Wireless Sensor Networks Using Dynamic Data Partitioning with an Entropy Criteria
Modeling a Slotted Ring Local Area Network
Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs
Some Results on Distribution-Free Analysis of Paging Algorithms
Improved Procedures for Determining Diagnostic Resolution
A Novel Photonic Container Switched Architecture and Scheduler to Design the Core Transport Network
An Improved Approximation Ratio to the Partial-Terminal Steiner Tree Problem
B74-4 Minicomputers in Data Processing and Simulation
Automatic Code Mapping on an Intelligent Memory Architecture
Efficient Deduplication Techniques for Modern Backup Operation
Efficient Multiple-Precision Floating-Point Fused Multiply-Add with Mixed-Precision Support
Short-Packet Transfer Performance in Local Area Ring Networks
Coincident-Current Superconductive Memory
Fast Parallel Algorithm for Ternary Multiplication Using Multivalued I²L Technology
Correction to "Enumeration of seven-argument threshold functions" [and AFCRL Rept, 64-925]
Slack Time Management for Imprecise Mixed-Criticality Systems With Reliability Constraints
Synthesizing a Protocol Converter from Executable Protocol Traces
Threshold implementation of ternary systems
Comment on "Computation of the Fast Walsh-Fourier Transform"
Allocation of Periodic Task Modules with Precedence and Deadline Constraints
Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors
EQAR: Effective QoS-Aware Relay Node Placement Algorithm for Connecting Disjoint Wireless Sensor Subnetworks
On the Optimal Design of Multiple-Valued PLA's
Division-and-Accumulation over GF(2''')
Program Counter-Based Prediction Techniques for Dynamic Power Management
Obtaining the Internal Junction Characteristics of a Transistor for Use in Analog Simulation
Bit-Parallel Arithmetic in a Massively-Parallel Associative Processor
Distributed Multihop Task Offloading in Massive Heterogeneous IoT Systems
Replacing Associative Load Queues: A Timing-Centric Approach
A General Stochastic Model for Dynamic Locking in Database Systems
A Multiplexer-Based Arbiter PUF Composition with Enhanced Reliability and Security
Almost Uniform Distributions for Computer Image Enhancement
Measurement and Generation of Error Correcting Codes for Package Failures
On the Structure of the Homogeneous Multiprocessor
High-Bandwidth Interleaved Memories for Vector Processors-A Simulation Study
Hypercube Communication Delay with Wormhole Routing
Model Checking Prioritized Timed Systems
An O(t 3 + |E|) Fault Identification Algorithm for Diagnosable Systems
A Totally Self-Chicking Error Indicator
Berkeley Array Processor
Fault-Tolerant Matrix Triangularizations on Systolic Arrays
Un-IOV: Achieving Bare-Metal Level I/O Virtualization Performance for Cloud Usage With Migratability, Scalability and Transparency
Partial Precedence Constrained Scheduling
Some Properties of Image-Processing Operations on Projection Sets Obtained from Digital Pictures
Regular Sparse Crossbar Concentrators
Runtime Performance Optimization of 3-D Microprocessors in Dark Silicon
Carry-Select Adder
Constructing Connected-Dominating-Set with Maximum Lifetime in Cognitive Radio Networks
A High-Speed Microprogrammable Digital Signal Processor Employing Distributed Arithmetic
End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators
Letter Recognition Using a Captive Scan
Towards Thermal-Aware Workload Distribution in Cloud Data Centers Based on Failure Models
A Parallel Algorithm for Reconfiguring a Multibutterfly Network with Faulty Switches
Localization for Wireless Sensor and Actor Networks with Meandering Mobility
AdaptDQC: Adaptive Distributed Quantum Computing With Quantitative Performance Analysis
Arithmetic Unit Design for Neural Accelerators: Cost Performance Issues
Hardware-Friendly Actor-Critic Reinforcement Learning Through Modulation of Spike-Timing-Dependent Plasticity
Analog Representation of Poisson's Equation in Two Dimensions
STfusion: Fast and Flexible Multi-NN Execution Using Spatio-Temporal Block Fusion and Memory Management
On the Genus of Star Graphs
A Function Generator Using Cold-Cathode Selector Tubes
Efficient Implementations of Reduced Precision Redundancy (RPR) Multiply and Accumulate (MAC)
Pattern Recognition and Image Processing
Energy Proportional Neural Network Inference with Adaptive Voltage and Frequency Scaling
Synthesis of Discrete Functions Using I 2 L Technology
Comments on "Heuristic Synthesis of Microprogrammed Computer Architecture"
Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis
An Application of the Analog Computer to Electronic Circuit Simulation
On the Paging Performance of Array Algorithms
Comments on "An O(n^2.5) Fault Identification Algorithm for Diagnosable Systems"
Synthesis of Logical Systems of Given Activity
Localizing Multiple Bugs in RTL Designs by Classifying Hit-Statements Using Neural Networks
Guest Editors' Introduction: Special Section on Dependable Computer Architecture
Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems
DDA Scaling Graph
Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations
Rigorous Development of an Embedded Fault-Tolerant System Based on Coordinated Atomic Actions
Building 3D Torus Using Low-Profile Expansion Cards
Wavelength Division Multiple Access Channel Hypercube Processor Interconnection
Representation Error for Real Numbers in Binary Computer Arithmetic
A Simple Postcorrection for Nonrestoring Division
Error-Correcting Codes with Byte Error-Detection Capability
On Computing Connected Components of Line Segments
An Upper Bound for the Bisection Width of a Diagonal Mesh
An Interconnection Network for Distributed Recursive Computations
Reduced Solutions of Boolean Equations
A Unified Approach to Feature Selection and Learning in Unsupervised Environments
The Suboptimal Routing Algorithm for 2D Mesh Network
$\mathtt{PARLE}$PARLE-$\mathtt{G}$G: Provable Automated Representation and Analysis Framework for Learnability Evaluation of Generic PUF Compositions
Worst Case Bounds for Maximal Compatible Subsets
Dynamic Programming for the Partitioning of Numerical Simulations with Hybrid Computer Applications
Computer Detection of Freehand Forgeries
The Use of Analog Techniques in Binary Arithmetic Units
A Family of Permutations for Concurrent Factorization of Block Tridiagonal Matrices
Conservative Logic Elements and Their Universality
On-Line Simulation of Block-Diagram Systems
On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays
A Very Fast Parallel Processor
QoS-Based Composition of Service Specific Overlay Networks
Accurate Cost Estimation of Memory Systems Utilizing Machine Learning and Solutions from Computer Vision for Design Automation
NV-eCryptfs: Accelerating Enterprise-Level Cryptographic File System with Non-Volatile Memory
A New Representation of Elements of Finite Fields GF(2 m ) Yielding Small Complexity Arithmetic Circuits
A Mathematical Model for Diagnosing System Failures
A Parallel Algorithm for the Knapsack Problem
A VLIW Architecure for a Trace Scheduling Compiler
On Performance Optimization and Quality Control for Approximate-Communication-Enabled Networks-on-Chip
Comments on "Synthesis of Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops"
Bulk Data Dissemination in Wireless Sensor Networks: Analysis, Implications and Improvement
NV-Dedup: High-Performance Inline Deduplication for Non-Volatile Memory
The Characteristic Polynomials for a Class of Eigenvalue Problems
Digital Twin-Assisted Federated Learning Service Provisioning Over Mobile Edge Networks
Error Correction in Adders using Systematic Subcodes
Design to Minimize Diameter on Building-Block Network
Communication performance in multiple-bus systems
A Versatile Multiplying Digital-to-Analog Converter
A Programmed Variable-Rate Counter for Generating the Sine Function
The Simulation of Cognitive Processes: An Annotated Bibliography
Optimal Utilization Bounds for the Fixed-Priority Scheduling of Periodic Task Systems on Identical Multiprocessors
Linear Feedback Shift Register Design Using Cyclic Codes
Depth-Size Tradeoffs for Neural Computation
Analysis of Multiprocessors with Private Cache Memories
Time-delay networks for an analog computer
An Algorithm for Transformation of an Arbitrary Switching Function to a Completely Symmetric Function
B72-3 Computer Structures, Readings and Examples
Theory and Design of t -Error Correcting and d(d > t) -Unidirectional Error Detecting ( t -EC d -UED) Codes
The Synthesis and Analysis of Digital Systems by Boolean Matrices
On the Effective Bandwidth of Parallel Memories
An O(n 2.5 ) Fault Identification Algorithm for Diagnosable Systems
An Additional Algorithm for a System of Coupled Algebraic Matrix Riccati Equations
A Framework for the Quantitative Evaluation of Distributed Computer Systems
FACCT: FAst, Compact, and Constant-Time Discrete Gaussian Sampler over Integers
Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements
A Hybrid Approach to NAND-Flash-Based Solid-State Disks
Exploring the Potential of Threshold Logic for Cryptography-Related Operations
Syntactic Recognition of Imperfectly Specified Patterns
Sequential and Parallel Neural Network Vector Quantizers
Hardware Implementation of Montgomery's Modular Multiplication Algorithm
CDT-Based Gaussian Sampling: From Multi to Double Precision
Speculative Barriers With Transactional Memory
Specification and Management of QoS in Real-Time Databases Supporting Imprecise Computations
DSTC: Dual-Side Sparse Tensor Core for DNNs Acceleration on Modern GPU Architectures
Cascaded Multithreshold Networks
On the Tradeoff Between Logic Performance and Circuit-to-Pin Ratio for LSI
VSPN: VANET-Based Secure and Privacy-Preserving Navigation
Lower Bounds of the Number of Threshold Functions and a Maximum Weight
On subsequences of arithmetic sequences
Node-Wise Hardware Trojan Detection Based on Graph Learning
Architecture, User Interface, and Enabling Technology in Windows Vista's Speech Systems
An Effective Multilevel Algorithm for Bisecting Graphs and Hypergraphs
An Algorithm for the Computation of Binary Logarithms
A Restructurable Computer System
A Distributed System-Level Diagnosis Algorithm for Arbitrary Network Topologies
Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems
Performance Optimization Based on Analytical Modeling in a Real-Time System with Constrained Time/Utility Functions
On Program Placement in a Directly Executable Hierarchy of Memories
Word-Level Recognition of Cursive Script
Correction to "Discrete Convolutions via Mersenne Transforms"
Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices
Optimizing Communication Overhead while Reducing Path Length in Beaconless Georouting with Guaranteed Delivery for Wireless Sensor Networks
Nanosecond Logic by Amplitude Modulation at X Band
$\pi$π-BA: Bundle Adjustment Hardware Accelerator Based on Distribution of 3D-Point Observations
A High-Level Synthesis Methodology for Energy and Reliability-Oriented Designs
Synchronous and Asynchronous Procedures for the Synthesis of Master-Slave Circuits
A VLSI Algorithm for Computing the Euclidean Norm of a 3D Vector
Approximation Algorithms for Multiconstrained Quality-of-Service Routing
Signal-Transition Patterns of Functional Broadside Tests
Independent Partitioning of Algorithms with Uniform Dependencies
History and Introductionߝ Microwave Techniques for Computers
Survivable Data Aggregation in Multiagent Network Systems with Hybrid Faults
Parallel Algorithms for Image Processing on OMC
Tolerance of Siamese Networks (SNs) to Memory Errors: Analysis and Design
A Sequential Decision Model for Selecting Feature Subsets in Pattern Recognition
A Case for Acoustic Wave Detectors for Soft-Errors
Synthesis of Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops
Computer Experience on Partitioned List Algorithms
Generation of All Closed Partitions on the State Set of a Sequential Machine
Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip
Discharge Current Steering for Battery Lifetime Optimization
About Some Properties of Definite, Reverse-Definite and Related Automata
New Classes of Synchronous Codes
A Graphic Method for the Synthesis of Threshold Ternary Functions
A 100 Megapulse per Second Binary Counter with Impedance Steering
Enclavisor: A Hardware-Software Co-Design for Enclaves on Untrusted Cloud
The Optimal Node Placement for Long Belt Coverage in Wireless Networks
On Self-Routing in Benes and Shuffle-Exchange Networks
A Microprocessor-Based Office Image Processing System
Analog and Digital Computation of Fourier Series and Integrals
ToEx: Accelerating Generation Stage of Transformer-Based Language Models via Token-Adaptive Early Exit
Novel $GF\left(2^{m}\right)$GF2m Digit-Serial PISO Multipliers for the Self-Dual Gaussian Normal Bases
Implementing Sequential Machines as Self-Timed Circuits
OverCome: Coarse-Grained Instruction Commit with Handover Register Renaming
Fault Attacks on Pairing-Based Protocols Revisited
A High-Resilience Imprecise Computing Architecture for Mixed-Criticality Systems
A Class of Autonomous One-Dimensional Iterative Arrays of Linear Machines
Realization of Fail-Safe Sequential Machines by Using a k-out-of-n Code
Modular Design of Asynchronous Circuits Defined by Graphs
Properties of Faults and Criticalities of Values under Tests for Combinational Networks
Some Notes on Speeding Up Certain Loops by Software, Firmware, and Hardware Means
Dynamic Bit Encoding for Privacy Protection against Correlation Attacks in RFID Backward Channel
Systolic Arrays for Matrix Transpose and Other Reorderings
Workload-Cognizant Concurrent Error Detection in the Scheduler of a Modern Microprocessor
FISHNET: A Distributed Architecture for High-Performance Local Computer Networks
Maxterm Covering for Satisfiability
Microsecond Word-Recognition System
Necessary and Sufficient Conditions on Block Codes Correcting/Detecting Errors of Various Types
On Easily Diagnosable Sequential Machines
Logic Design Automation of Fan-In Limited NAND Networks
StaleLearn: Learning Acceleration with Asynchronous Synchronization Between Model Replicas on PIM
On the Design of Pseudoexhaustive Testable PLA's
Workload Execution Strategies and Parallel Speedup on Clustered Computers
The Syntax of Programming Languages-A Survey
R70-28 A Note on Definite Stochastic Sequential Machines
A Method for Redundancy Scheme Performance Assessment
Buffer Length for Erlang Input and Constant Removal Rate
The Design of a Microprogrammed Self-Checking Processor of an Electronic Switching System
Time/Utility Function Decomposition Techniques for Utility Accrual Scheduling Algorithms in Real-Time Distributed Systems
A Hybrid Optical Computer Processing Technique for Fingerprint Identification
Storage Placement in Path Networks
Embedding of Rings and Meshes onto Faulty Hypercubes Using Free Dimensions
NPC: A Non-Conflicting Processing-in-Memory Controller in DDR Memory Systems
On the Execution of Fuzzy Programs Using Finite-State Machines
The Modular Arithmetic of Arbitrarily Long Sequences of Digits
The Minimization of Inverters in Analog Computer Programming
The Fast Hartley Transform Algorithm
Optimal Rack-Coordinated Updates in Erasure-Coded Data Centers: Design and Analysis
Elastic Buffer Flow Control for On-Chip Networks
Towards the Design of Efficient and Consistent Index Structure with Minimal Write Activities for Non-Volatile Memory
Tunnel Diode-Charge Storage Diode Shift Register
A Verifiable Language for Programming Real-Time Communication Schedules
Generation of Design Equations in Asynchronous Sequential Circuits
Incremental Curve Generation