yusuke1997/dblp-id-title huggingface dataset:
Process, Voltage and Temperature Variations Aware Low Leakage Approach for Nanoscale CMOS Circuits
Efficient and Low Overhead Memristive Activation Circuit for Deep Learning Neural Networks
0.5 V RMS-to-DC Converter Topologies Suitable for Implantable Biomedical Devices
Self-Power Saving Technique in State Machine Circuit of Automatic Teller Machine Application
A Novel Coordinate Rotation Digital Computer Method for Energy and Latency Saving by Trigonometric Operations Spatial Locality Principle
Hybrid Subthreshold and Nearthreshold Design Methodology for Energy Minimization
Tinnitus Detector Realization Using Sinh-Domain Circuits
Cellular Automata Approach for a Low Power Fusion Center to Evaluate Spectrum Status and Coverage Area in Cognitive Radios
System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation
An Optimal Two-Mixer Dilution Engine with Digital Microfluidics for Low-Power Applications
An Automated Power Emulation Framework for Embedded Software - Detecting Power-Critical Code Regions and Optimizing Software-Induced Power Consumption Peaks
Pseudo Dual Supply Voltage Domino Logic Design
Fault-Tolerance in Field Programmable Gate Array with Dynamic Voltage and Frequency Scaling
State Space Reconfigurability: A Low Energy Implementation Architecture for Self Modifying Finite Automata
Portable Lock-In Amplifier-Based Optoelectronic Readout Circuit for High-Sensitivity Differential Measurements of Laser Pulse Energy Variations
A New Simple P -MOS Charge Pump for Low Voltage Operations
Lithography Aware Regular Cell Design Based on a Predictive Technology Model
Clocking Scheme Implementation for Multi-Layered Quantum Dot Cellular Automata Design
Selected Articles from the VARI 2012 Workshop
Selected Peer-Reviewed Articles from the VARI 2010 Workshop
Power Optimized Design of CMOS Programmable Gain Amplifiers
CMOS Power Management Unit Along with Load Regulation Using Switched Capacitor Converters
A Low Power Design for Sbox Cryptographic Primitive of Advanced Encryption Standard for Mobile End-Users
Design of 8T Volatile and Non-Volatile RAM Cells with Improved Holding Phase Performance
Efficient-Block-Processing Parallel Architecture for Multilevel Lifting 2-D DWT
A Technology Based Complexity Model for Reversible Cuccaro Ripple-Carry Adder
Energy Aware Spectrum Decision Framework for Cognitive Radio Network: A Spectrum Decision Framework for Cognitive Radio Network with Energy Awareness
Techniques for Power-Aware Hardware Synthesis from Concurrent Action Oriented Specifications
Trading Accuracy for Power in a Multiplier Architecture
Digital Adaptive Calibration of Multi-Step Analog to Digital Converters
Selected Articles from the NGCAS 2018 Conference
24th "IEEE International Conference on VLSI Design" Chennai, India, 2-7 January 2011
Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture
Asynchronous Parallel Platforms with Balanced Performance and Energy
Minimum Operating Voltage Due to Intrinsic Noise in Subthreshold Digital Logic in Nanoscale CMOS
Effect of Self Heating on Selective Buried Oxide and Silicon on Insulator Based Junctionless Transistors
Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters
Statistical Moment Estimation of Delay and Power in Circuit Simulation
SCoPE : Statistical Regression Based Power Models for Co-Processors Power Estimation
Novel NBTI Aware Approach for Low Power FinFET Based Wide Fan-In Domino Logic
Design of Reconfigurable Filter Bank Architecture Using Improved Coefficient Decimation-Interpolation-Masking Technique for Multi-Standard Wireless Communication Receivers
A Review of DC/DC Converters for Ultra Low Voltage Energy Harvesting
Epsilon-Optimal Minimal-Skew Battery Lifetime Routing in Distributed Embedded Systems
Architectural Power Analysis for Intellectual Property-Based Digital System
Interconnect Aware Test Power Reduction
SiGe Source Dual Metal Double Gate Tunnel Field Effect Transistor
Energy Study for 28 nm Fully Depleted Silicon-On-Insulator Devices
A Fully Differential Operational Amplifier with Slew Rate Enhancer and Adaptive Bias for Ultra Low Power
A Multi-Processing Systems-on-Chip Native Simulation Framework for Power and Thermal-Aware Design
A Compact CMOS Electrochemical Sensor Readout Circuit for a Conductometric Sensor Array
High Speed Low Power Ping Pong Buffering Based Network Interface for Network on Chip
Estimation of Power Dissipation in Ternary Quantum Dot Cellular Automata Cell
Selective Algorithms for Built-In Self-Test and Self-Diagnosis in Embedded SRAMS
Customized Power Management System Using a Capacitor Array and DC/DC Booster for Flat-Plate Microbial Fuel Cells
Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology
A 0.35 um CMOS Operational Amplifier Using Multi-Path Frequency Compensation
Back to the Future: Digital Circuit Design in the FinFET Era
Test Power Analysis at Register Transfer Level
Junctionless Tunnel Field Effect Transistor with Enhanced Performance Using III-V Semiconductor
Performance Improvement in Nanoscale Ge-GaAs Heterojunction Junctionless Tunnel FET Using a Dual Material Gate
Targeting System-Level and Kernel-Level Optimizations of Computer Vision Applications on Embedded Systems
Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks
On-Chip Single-Inductor Multiple-Output Power Converter Design with Adaptive Cross Regulation and Supply Variation Control for Power-Efficient VLSI Systems
Recent Advances in Low Power Asynchronous Circuit Design
Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory
Leakage/Temperature-Aware Dynamic Voltage Scaling and Dynamic Cache Reconfiguration to Reduce Power Consumption
An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects
An Ultra-Low Power Data Aggregation System for Wireless Micro Sensor Networks
Transistor Sizing of Logic Gates to Maximize Input Delay Variability
Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems
Interconnect-Aware Technology and Design Co-Optimization for the 5-nm Technology and Beyond
Li-Ion Battery Charging with a Buck-Boost DC-DC Converter for a Portable Device Power Management
Interconnect Delay Model for Wide Supply Voltage Range Repeater Insertion in Sub-22 nm FinFET Technologies
Wideband CMOS Receiver with Integrated Filtering and a Current-Mode Sigma-Delta Analog-to-Digital Converter
A Power-Aware Fault Detection Scheme for 2D Mesh-Based Network-on-Chip Interconnects
An Adaptive Frames Per Second-Based CPU-GPU Cooperative Dynamic Voltage and Frequency Scaling Governing Technique for Mobile Games
Design Space Exploration of Split-Path Data Driven Dynamic Full Adder
Selected Articles from the IEEE LPonTR 2012 Workshop
Low-Leakage and Compact Registers with Easy-Sleep Mode
A Low Power L1 Cache Design Based on Data and Tag Re-Mapping
Secured Hardware Design with Locker-Box Against a Key-Guessing Attacks
A CMOS Switched Capacitor Based Low Power Amperometric Readout Circuit for Microneedle Glucose Sensor
Device Physics of Germanium-Junctionless Tunnel Field Effect Transistor and an Approach to Optimize I on / I off by Drain Engineering and Work Function Engineering
Leakage-Aware Speculative Branch Target Buffer
Simple Single Time Constant Circuits Using Low Voltage Operational Floating Conveyor
Ultra Low-Voltage Low-Power Realization of Non-Linear Energy Operator for Spike Detection
A Way Cache Locking Scheme Supported by Knowledge Based Smart Preload Effective for Low-Power Multicore Electronics
A Refinement Methodology for Clock Gating Optimization at Layout Level in Digital Circuits
Effect of Nanoribbon Width and Strain on the Electronic Properties of the WS2 Nanoribbon
Selected Articles from the 5th European Workshop on CMOS Variability, Palma (Mallorca), Spain, September 29-October 1, 2014
On the Use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits
Thermal Modeling of an Integrated Inductor in a Micro-Converter
A Special Issue on Power, Parasitics, and Process-Variation (P3) Awareness in Mixed-Signal Design
Efficiency Issues for a Wind-Driven Energy Harvesting Device
Microarchitecture Level Interconnect Modeling Considering Layout Optimization
A Low-Power Clock-Less Pulse Width Modulator Architecture for Smart Imaging
A General Approach to High-Level Energy and Performance Estimation in System-on-Chip Architectures
Evaluation of Parasitic Components in LC Oscillators by Time-Varying Root-Locus
Reducing Power Dissipation in SRAM during Test
Selected Articles from the IEEE ISED 2013 Conference
Test Power Reduction via Deterministic Alignment of Stimulus and Response Bits
Functional Broadside Tests with Minimum and Maximum Switching Activity
An EDA Framework for Reliability Estimation and Optimization of Combinational Circuits
Capacitor Less Voltage Regulator with Split Drive Error Amplifier for Segmented Pass Transistors
A Measurement-Based Automatic Energy Optimization Technique for Embedded Applications
A Bidirectional Differential Cascode Voltage Switch DC-DC Buck-Boost Converter for Low Voltage Application
Low-Power Data Driven Symbol Decoder for a UHF Passive RFID Tag
Frame-Based Dynamic Voltage and Frequency Scaling for an MPEG Player
Distributed Runtime Energy Management for Many-Core Systems Running Real-Time Applications
Performance Analysis of Microkernel Based Virtualization Techniques on Embedded Systems
Low-Complexity and Reconfigurable Discrete Hilbert Transform Architecture Design Methodology
A High Speed and Low Power 8 Bit × 8 Bit Multiplier Design Using Novel Two Transistor (2T) XOR Gates
Thermal Analysis of a Segmented Rotor Switched Reluctance Motor Used as the Belt-Driven Starter/Generator for Hybrid Electric Vehicles
Selected Peer-Reviewed Articles from the LPonTR 2009 Workshop
Dynamic Mathematical Model for Low Power Electrical Discharge Machining Applications
Energy-aware Dynamic Task Scheduling Applied to a Real-time Multimedia Application on an Xscale Board
A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder
Performance Evaluation of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems
Negative Bias Temperature Instability-Aware Instruction Scheduling: A Cross-Layer Approach
Signal Activity Analysis for High-Level Power Estimation in Time-Shared Linear Systems
A Leakage-aware Low Power Technology Mapping Algorithm Considering the Hot-Carrier Effect
Test Sequences with Reduced and Increased Switching Activity
A Low-Power Baseband Filter Based on a 1.2-V 65-nm CMOS Bulk-Driven Linear Tunable Transconductor
A Low-Power Instrumentation System for Nano-Electro-Mechanical-Sensors for Environmental and Healthcare Applications
Selected Articles from the IEEE ISED 2012 Conference
Using Adaptive Body Biasing for Robust Process Variation Aware DRAM Design
Modeling and Optimization of Nano-Scale Sensing Shorted Gate FinFET D Flip-Flop Using AVL
Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits
Wireless Power Transfer Systems Based on LCC-Compensated Topology for Left Ventricular Assist Device (LVAD) Battery Charging Application
Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures
Communication Power Optimization for Network-on-Chip Architectures
Gate Driver Voltage Optimization for Multi-Mode Low Power DC-DC Conversion
Power Management Methods: From Specification and Modeling, to Techniques and Verification
Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power
Scheduling Instructions for Enhanced Performance and Energy Efficiency on a Clustered Architecture with Applications in Big-Data Sensor Networks
Microprocessor Power Supply Noise Aware Floorplanning Using a Circuit-Architectural Framework
A Power Efficient Low Noise Preamplifier for Biomedical Applications
Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits
A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality
A Thermal-Aware Scheduling Algorithm for Core Migration in Multicore Processors
Simulated Annealing Based Temperature Aware Floorplanning
Design of Low Power Parallel Multiplier
Optimization of On-Chip Interconnect Signaling for Low Energy and High Performance
Power Estimation at Different Abstraction Levels for Wireless Baseband Processors
System Wide Dynamic Power Management for Weakly Hard Real-Time Systems
Energy Savings in Networks-on-Chip with Smart Temporal Shielding
Design of a Gate Driver for a Class-D Audio Output Stage with Break-Before-Make in 130 nm SOI-BCD Technology
Timing-Aware Power Minimization via Extended Timing Graph Methods
Look-Up Table Based Low Power Rotary Traveling Wave Oscillator Design Considering the Skin Effect
A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction
Test Pattern Generation Based on Multi-TRC Scan Architecture for Reducing Test Cost
Welcome to the Journal of Low Power Electronics
High-Level Interconnect Delay and Power Estimation
Low-Power Coding for Networks-on-Chip with Virtual Channels
A Design Approach for Efficient Multipliers for Wearable Technology
Low Power SER Tolerant Design to Mitigate Single Event Transients in Nanoscale Circuits
Real-Time Scheduling on Dynamic Resources in a Fog Computing Environment
A New Automated Power-Estimation Method for SystemC Hardware Design
A Robust and Energy Efficient Pulse-Triggered Flip-Flop Design for Ultra Low Voltage Operations
Minimum Energy Point Tracking with All-Digital On-Chip Sensors
An Ultra-High Speed and Low Complexity Quantum-Dot Cellular Automata Full Adder
DFT MAX and Power
A 30 mV-2.5 V DC/DC Converter for Energy Harvesting
A Novel Threshold Voltage Assignment for 3D Multicore Designs
A Hierarchical Reliability Simulation Methodology for AMS Integrated Circuits and Systems
Learning-Based Run-Time Power and Energy Management of Multi/Many-Core Systems: Current and Future Trends
A Dynamic Power Estimation Method for System on Chip Designs
Power Gating Clustered Many-Core Architectures
A Reliable Routing Protocol Based on Mesh Under for G3-PLC
Differential Voltage Mode On-Chip Serial Transceiver for Global Interconnects
Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays
Selected Articles from the CDNLive! EMEA 2012 Conference
Adaptive Global Elimination Algorithm for Low Power Motion Estimation (J. Low Power Electronics 5: 1-16 (2009))
Low-Power Heterogeneous Systems-on-Chips
Physical Power Evaluation of Low Power Logic-BIST Scheme Using Test Element Group Chip
Implementation of Smart Battery Charger with Low Power Photo-Voltaic Energy System Using Synchronous Buck Converter
A Two-Write and Two-Read Multi-Port SRAM with Shared Write Bit-Line Scheme and Selective Read Path for Low Power Operation
Power Aware Architecture Exploration for Field Programmable Gate Arrays
Improving Electro-Magnetic Interference of Embedded Systems Through Jittered-Delay Desynchronization
Reducing Power and Cycle Requirement for Fast Fourier Transform of Electrocardiogram Signals Through Low Level Arithmetic Optimizations for Cardiac Implantable Devices
Adaptive Global Elimination Algorithm for Low Power Motion Estimation
Ultra Low-Voltage Ultra Low-Power Sinh-Domain Wavelet Filer for Electrocardiogram Signal Analysis
AdaFlow: Aggressive Convolutional Neural Networks Approximation by Leveraging the Input Variability
A Fast, Dynamic, Fine-Detail, Source Level Technique to Estimate the Energy Consumed by Embedded Software on Single-Issue Processor Cores
A Special Issue on 23rd IEEE International Conference on VLSI Design, Bangalore, India, 3-7 January 2010
Implementation of an Asynchronous Low-Power Small-Area Passive Radio Frequency Identification Design Using Synchronous Tools for Automation Applications
Timing-Driven Power Optimisation and Power-Driven Timing Optimisation of Combinational Circuits
Distributed Task Migration in a Homogeneous Many-Core System for Leakage and Fan Power Reduction
On the Effect of Approximate-Computing in Motion Estimation
Low Power-Variable Resolution Analog-to-Digital Converter
An Architecture Design Methodology for Minimal Total Power Consumption at Fixed Vdd and Vth
Design and Analysis of a Low Power Multi-Threshold CMOS Based ARM926 System
Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation
A Novel Low Energy Scheduling Algorithm for Clustered Very Long Instruction Word Architectures
Design and Chip Implementation of the Segment Weighted Random BIST for Low Power Testing
An Effective Combinatorial Algorithm for Gate-Level Threshold Voltage Assignment
Charge Recycling in Voltage-Dithered Circuits
Design of High Sensitivity Radiofrequency Energy Harvesters Dedicated to Low-Power Applications
Effect of Aging on Power Integrity and Conducted Emission of Digital Integrated Circuits
Thermo-Magnetic Control System for Nano-Ferromagnetic Particle Doped Shape Memory Alloy for Orthopedic Devices and Rehabilitation Techniques
Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers
Dynamic Feedback Controlled Static Random Access Memory for Low Power Applications
Delay-Assignment-Variation Based Optimization of Digital CMOS Circuits for Low Power Consumption
Delay Modeling for Power Noise and Temperature-Aware Design and Test of Digital Systems
Spatial Switching Data Coding Technique Analysis and Improvements for Interconnect Power Consumption Optimization
Energy Efficient Adiabatic Logic Styles in Sub-Threshold Region for Ultra Low Power Application
Low Power Digital Alternative to Analog Control of Step-Down Converter
Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses
Implementation of Low Power Digital Multipliers using 10 -Transistor Adder Blocks
A New Technique for Runtime Leakage Reduction and Its Sensitivity and Parametric Yield Analysis Under Effective Channel-Length Variation
Low-Energy Heterogeneous Non-Volatile Memory Systems for Mobile Systems
Dynamic Reconfiguration of Two-Level Cache Hierarchy in Real-Time Embedded Systems
Leakage and Leakage Sensitivity Computation for Combinational Circuits
Design Analysis and Implementation of a Dynamic Voltage Restorer
Software Level Power Consumption Models and Power Saving Techniques for Embedded DSP Processors
Low Swing Charge Recycling Driver for On-Chip Interconnect
A High Linear and Temperature Compensation Ring Voltage-Controlled Oscillator for Random Number Generator
Quantum-Dot Cellular Automata-Implementing Reversible Benchmarks
RFID Systems: Passive versus Active and a Novel Low-Power RF Transceiver for IEEE 802.15.4 (ZigBee) Standard Based Applications
Design and Analysis of a Modified Low Power CMOS Full Adder Using Gate-Diffusion Input Technique
Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process
Characterization Methodology for MOSFET Local Systematic Variability in Presence of Statistical Variability
Back-Annotation in High-Speed Asynchronous Design
SRAM Cell Optimization for Ultra-Low Power Standby
Energy Efficiency Comparison of Asynchronous and Synchronous Circuits Operating in the Sub-Threshold Regime
Message Passing-Aware Power Management on Many-Core Systems
Adaptive Thermal Monitoring of Deep-Submicron CMOS VLSI Circuits
A High Power Switch-Mode LED Driver with an Efficient Current Sensing Scheme
Implementation Strategy and Results of an Energy-Aware System-on-Chip for 5 GHz WLAN Applications
A Four-Transistor Level Converter for Dual-Voltage Low-Power Design
Temperature-Aware Floorplanning of 3-D ICs Considering Thermally Dependent Leakage Power
An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process
Task Assignment Algorithms for Multicore Platforms with Process Variations
A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs
Addressing Productivity Challenges in Domain-Specific Reconfigurable Platforms: A Case Study on Extended Kalman Filter-Based Motor Control
A Novel Synthetic Traffic Pattern for Power/Performance Analysis of Network-on-Chips Using Negative Exponential Distribution
Design and Analysis of Improved Soft Switching DC-DC Boost Converter for Low Power Photovoltaic Applications
In 0 25 Ga 0 75 As Channel Double Gate Junctionless Transistor
Domain Wall Dynamics Due to Voltage Controlled Magnetic Anisotropy
A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics
Low Power Radio Frequency Identification Design Using Custom Asynchronous Passive Computer
Cut-less Technology Mapping Using Shannon Factor Graph with on-the-fly Size Reduction
A 20 ppm/°C Temperature Coefficient and High Power Supply Rejection Ratio Bandgap Reference Implemented in 90 nm CMOS Technology for Low Drop-Out Voltage Regulator Applications
Minimising Impact of Wire Resistance in Low-Power Crossbar Array Write Scheme
Adaptive Input-Output Selection Based On-Chip Router Architecture
Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits
Spatially Distributed Dual-Spacer Null Convention Logic Design
Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits
A Special Section on New and Future Trends in Low Power Electronics
Amplitude and Quadrature Errors of Two-Integrator Oscillator
Super Class AB OTAs Based on Low-Power Adaptive Techniques at the Input Stage and the Active Load
An Improved Reconfigurable Finite Impulse Response Filter Using Common Subexpression Elimination Algorithm for Cognitive Radio
Robust SRAM Design via Joint Sizing and Voltage Optimization Under Dynamic Stability Constraints
An Asynchronous Advanced Encryption Standard Core Design for Energy Efficiency
Ultra-Low Power, Low Voltage, Self-Powered Resonant DC-DC Converter for Energy Harvesting
A New Cell Design Methodology for Balanced XOR-XNOR Circuits for Hybrid-CMOS Logic
Impact of Collector Length on the Performance of NPN SiGe HBT on Thin Film SOI
The Effect of Dynamic Power Management on Mid-Frequency and Low-Frequency Power Supply Noise
Low Power Correlating Caches for Network Processors
An Integer Linear Programming Framework for Energy Optimization of Non-Preemptive Real Time Tasks on Multiprocessors
ActivIC: Design-Based Automatic Characterization of Mixed-Signal Integrated Circuits
Power Supply Noise: Causes, Effects, and Testing
Energy-Aware MPEG-4 FGS Streaming
Electrical Braking in Matrix Converter for More Electric Aircraft: Bi-Directional Switch and Input Power Clamp Methods
A Scan Controller Concept for Low Power Scan Tests
Branch grafting method for R-tree implementation
Assuring software quality through measurements: A buyer's perspective
From AADL to Timed Abstract State Machines: A verified model transformation
Quality assurance in software ecosystems: A systematic literature mapping and research agenda
Incremental-concurrent fusion checking for efficient context consistency
Measuring design complexity of semantic web ontologies
A theory of FLOSS projects and Open Source business models dynamics
Characterizing and detecting Python version incompatibilities caused by inconsistent version specifications
Automating resource allocation for multiprocessors
An empirical investigation of architectural prototyping
In search of the customer's quality view
Understanding the relevance of micro-structures for design patterns detection
Software test process improvement approaches: A systematic literature review and an industrial case study
A Locally Adaptive Data Compression Strategy for Chinese-English Characters
From IT application to organizational transformation
Identification and classification of free, open source software licenses: A systematic literature review
Software engineering education: Results from a training intervention based on SonarCloud when developing web apps
Modeling change requests due to faults in a large-scale telecommunication system