yusuke1997/dblp-id-title huggingface dataset:
A resource-constrained CNN accelerator for real-time license plate character recognition on FPGA platforms
VLSI supply chain security risks and mitigation techniques: A survey
Intra-class CutMix data augmentation based deep learning side channel attacks
Dynamic detection of wireless interface faults and fault-tolerant routing algorithm in WiNoC
Systematic serialisation of array-based architectures
A novel net-degree distribution model and its application to floorplanning benchmark generation
Analysis of SRAM metrics for data dependent BTI degradation and process variability
Partial product reduction by using look-up tables for M×N multiplier
On the bit complexity of parallel computations
Pattern-based verification of connections to intellectual property cores
A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process
On a new class of C-testable systolic arrays
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
An accurate classifier based on adaptive neuro-fuzzy and features selection techniques for fault classification in analog circuits
Failure probability analysis and critical node determination for approximate circuits
Floorplan-aware analog IC sizing and optimization based on topological constraints
Multi-source data fusion technique for parametric fault diagnosis in analog circuits
Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style
The Retiming Lemma: A simple proof and applications
Regular layouts of butterfly networks
SubMac: Exploiting the subword-based computation in RRAM-based CNN accelerator for energy saving and speedup
Critical path-aware voltage island partitioning and floorplanning for hard real-time embedded systems
Design and hardware implementation of 4D memristive hyperchaotic map with rich initial-relied and parameter-relied dynamics
A 32 GBit/s communication SoC for a waferscale neuromorphic system
Reinforcement learning-driven net order selection for efficient analog IC routing
Analysis of memristive maps with asymmetry
Constructing keyed strong S-Box with higher nonlinearity based on 2D hyper chaotic map and algebraic operation
Testing asynchronous circuits: A survey
Frequency-dependent mutual resistance and inductance formulas for coupled IC interconnects on an Si-SiO2 substrate
Dual-rail asynchronous logic multi-level implementation
Design of a memristor-based look-up table (LUT) for low-energy operation of FPGAs
Battery lifetime prediction considering domain-variate error
Improving the energy efficiency of reversible logic circuits by the combined use of adiabatic styles
A fast hypergraph min-cut algorithm for circuit partitioning
FLORA: A data path allocator based on branch-and-bound search
A 28-GHz highly efficient Class-J SiGe power amplifier with pi-type load network
B2N2: Resource efficient Bayesian neural network accelerator using Bernoulli sampler on FPGA
Meminductor emulators using off-the-shelf active blocks with application in chaotic oscillator
Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay1
System-level design consideration and optimization of through-silicon-via inductor
FRDS: An efficient unique on-Chip interconnection network architecture
Neuromorphic computing's yesterday, today, and tomorrow - an evolutional view
A low-cost platform for the prototyping and characterization of digital circuit IPs
Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome
A novel spatially configurable differential interface for an electronic system prototyping platform
The systolic control ring instruction processor (SCRIP)
Path planning algorithm for data acquisition system based on 3D network-on-chip
Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs
Homogeneous droplet routing in DMFB: An enhanced technique for high performance bioassay implementation
A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee receiver consuming 2 mA
Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training
Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective
Low power, high speed approximate multiplier for error resilient applications
Design of a soft error resilient 13T SRAM architecture for radiation-prone environments in FinFET 18 nm technology
Bitmask aware compression of NISC control words
Logical effort based dynamic power estimation and optimization of static CMOS circuits
FPGA and GPU-based acceleration of ML workloads on Amazon cloud - A case study using gradient boosted decision tree library
System-level evaluation of dynamic effects in a GaN-based class-E power amplifier
A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition
Performance evaluation metrics for ring-oscillator-based temperature sensors on FPGAs: A quality factor
BEAD: Bounded error approximate adder with carry and sum speculations
Model and system robustness in distributed CNN inference at the edge
Vulnerable objects detection for autonomous driving: A review
SPLASH: A framework for chip design and layout
An efficient XOR-free implementation of polar encoder for reconfigurable hardware
Complex exponential functions: A high-precision hardware realization
Selecting test methodologies for PLAs and random logic modules in VLSI circuits - an expert systems approach
Linear Clock Tree Topology for Dynamic Source Synchronous and Fully Synchronous 3-D Interfaces
Block flipping and white space distribution for wirelength minimization
A high performance MQ encoder architecture in JPEG2000
Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding
K Band SiGe HBT single ended active inductors
FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures
Hardware implementation of a robust image cryptosystem using reversible cellular-automata rules and 3-D chaotic systems
An efficient NBTI -aware wake-up strategy: Concept, design, and manipulation
Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints
A Low cost area-efficient modified Russian peasant multiplier(MRPM) for biomedical applications
A non-iterative gate resizing algorithm for high reduction in power consumption
Self-triggering hardware trojan: Due to NBTI related aging in 3-D ICs
Real-time neural identification using a recurrent wavelet first-order neural network of a chaotic system implemented in an FPAA
Bit-level two's complement matrix multiplication
Threshold adjustment of receiver chip to achieve a data rate >66 Gbit/sec in point to point interconnect
VLSI parallel shift sort algorithm and design
Hardness of crosstalk minimization in two-layer channel routing
A new scheme of test data compression based on equal-run-length coding (ERLC)
Simulation of fractional order chaotic oscillators applying the Grünwald-Letnikov definition and the Adams-Bashforth-Moulton method
VLSI architectures to compute the Wigner Distribution
A high speed 2-D discrete cosine transform chip
Exploiting bit sparsity in both activation and weight in neural networks accelerators
A low-voltage low-power capacitive-feedback voltage controlled oscillator
Weak signal detection and circuit implementation based on a novel 3D chaotic synchronization system
Rasterization theory, architectures, and implementations for a class of two-dimensional problems
Linear test sequences for detecting functionally faulty RAM's
A high-speed 13-bit two-step single-slope ADC for large array CMOS image sensors
A programmable delay chain for the source-synchronous interface
Partitioning-based decoupling capacitor budgeting via sequence of linear programming
On a case of symbiosis between systolic arrays
A thermal-aware layer-wise quantization framework for ReRAM-Based DNN CIM systems
Test generation by activation and defect-drive (TEGAD)
Architectures for large-capacity CAMs
SEAM: A synergetic energy-efficient approximate multiplier for application demanding substantial computational resources
Integration of loop gain measurement circuit for stability evaluation in DC/DC converters with time-based control
Simple memristive chaotic systems with complex dynamics
Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing
Implementation of imprecise multipliers using 2-bit adder for image processing
Multiple block structure-preserving reduced order modeling of interconnect circuits
Editorial: Special Issue on The 14th International Conference on Computer-Aided Design and Computer Graphics (CAD/Graphics 2015)
Power routing in channelless floorplan layouts
Machine learning application for cell delay accuracy improvement at post-placement stage: A case study for combinational cells
Nature inspired algorithm based design of near ideal fractional order low pass Chebyshev filters and their realization using OTAs and CCII
VLSI design in the 3rd dimension
An efficient multiplier-less architecture for 2-D convolution with quadrant symmetric kernels
Top-down design of a VLSI digital filter bank
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors
A mixed-signal demodulator for a low-complexity IR-UWB receiver: Methodology, simulation and design
Analysis and implementation of a novel parametrically controllable spherical multi-scroll memristive conservative hyperchaotic system
Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning
An algorithm for optimal two-dimensional compaction of VLSI layouts
Fast algorithm for optimal layer assignment
On the optimal four-way switch box routing structures of FPGA greedy routing architectures1
Introduction to the special issue on PRIME 2016 and SMACD 2016
Selective congestion control for mixed-critical networks-on-chip
Approximate Error Detection-Correction for efficient Adaptive Voltage Over-Scaling
Color image encryption based on discrete memristor logistic map and DNA encoding
A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications
GreyHound: A methodology for utilizing datapath regularity in standard design flows
A real-time systolic integer multiplier
Picowatt 0.3-V MOS-only voltage reference based on a picoamp cascode current generator
ALSO: A system for chip floorplan design
The Involution Tool for Accurate Digital Timing and Power Analysis
A 25-Gb/s inductorless SiGe BiCMOS receiver for 100-Gb/s optical links
Handling routability in floorplan design with twin binary trees
High-level hardware design of digital comparator with multiple inputs
2.0 V Bipolar/CMOS differential logic methodology for iterative network implementation
Low-complexity multi-mode multi-way split-row layered LDPC decoder for gigabit wireless communications
High-throughput and area-efficient architectures for image encryption using PRINCE cipher
ATSS-PUF with hardware sharing for secure in-situ memory circuit
On the complexity of allocation problems in high-level synthesis
A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications
A digital array based bit serial processor for arbitrary window size kernel convolution in vision sensors
An analytic algorithm for global circuit placement
ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS
Editorial: 5th meeting for the dissemination and research in the study of complex systems and their applications
Switch-level testability of the dynamic CMOS PLA
FsmTest: Functional test generation for sequential circuits
A high throughput pass parallel block decoder architecture for JPEG 2000 that prevents stalling in the decoding process
FPGA-enhanced system-on-chip for finger vein-based biometric system using novel DL model
Hw/Sw Co-Design technique for 2D fast fourier transform algorithm on Zynq SoC
CDA-GC: An effective cache data allocation for garbage collection in flash-based solid-state drives
Optimal asymmetrical back plane biasing for energy efficient digital circuits in 28 nm UTBB FD-SOI
A logic minimization algorithm of functions with large DC-set
An Adaptive Congestion-aware Approximate Communication (ACAC) scheme and implementation for Network-on-Chip systems
Robust battery lifetime prediction with noisy measurements via total-least-squares regression
A combined sensor placement and convex optimization approach for thermal management in 3D-MPSoC with liquid cooling
Dynamic precision configurable multiply and accumulate architecture for hardware accelerators
A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs
Enhanced fault detection in digital VLSI circuits using convolutional autoencoders
Flexible VLSI architectures for Galois field multipliers
Novel designs of fault-tolerant nano-scale circuits for digital signal processing using quantum dot technology
BΔ-NIS: Performance analysis of an efficient data compression technique for on-chip communication network
A note on hierarchical layer-assignment
A High Performance Early Acknowledged Asynchronous Pipeline using Hybrid-logic Encoding
Calibration of optimized minimum inductor bandpass filter with controllable bandwidth and stopband rejection
Design of low-power wideband frequency quadruplers based on transformer-coupled resonators for E-Band backhaul applications
Constrained algorithmic IP design for system-on-chip
Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems
Transaction-level power analysis of VLSI digital systems
MAGIC-DHT: Fast in-memory computing for Discrete Hadamard Transform
A new approach to power estimation and reduction in CMOS digital circuits
DIF: A framework for VLSI multi-level representation
Low-power content addressable memory design using two-layer P-N match-line control and sensing
Energy efficient implementation of multi-phase quasi-adiabatic Cyclic Redundancy Check in near field communication
A passive and low-complexity Compressed Sensing architecture based on a charge-redistribution SAR ADC
VLSI physics
Design of joint reconfigurable hybrid adder and subtractor using FinFET and GnrFET technologies
Versatile hardware architectures for GF(p m ) arithmetic in public key cryptography
Length-constrained escape routing of differential pairs
Synthesis of systems specified as interacting VHDL processes
A comprehensive analysis of the impact of sub 10-nm CNFET technology on 64-bit parallel prefix adders and 32-bit matrix multiply units
Design of self-recovering low-cost multiple-node-upset-tolerant latch
An inductor modeling and optimization toolbox for RF circuit design
Stochastic testing of processing cores in a many-core architecture
Language semantics to support secure computation and communication in embedded systems via hardware monitors
FPGA implementation of EEG based hardware optimized data encryption technique for IoT applications
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
Time redundancy and gate sizing soft error-tolerant based adder design
Retiming control logic
Log-hybrid architecture for tonal correction combined with modified un-sharp masking filter algorithm for colour image enhancement
On characterization of catastrophic faults in two-dimensional VLSI arrays
CAPUF: Design of a configurable circular arbiter PUF with enhanced security and hardware efficiency
A fast hardware accelerator for nighttime fog removal based on image fusion
SVM algorithm oriented for implementation in a low-cost Xilinx FPGA
A fast algorithm for rectilinear block packing based on selected sequence-pair
Power and electromagnetic analysis: Improved model, consequences and comparisons
Discharge-path-based antenna effect detection and fixing for X-architecture clock tree
Performance evaluation of the low-voltage CML D-latch topology
Statistical lifetime reliability optimization considering joint effect of process variation and aging
Pareto optimization technique in actuation control for error minimization and reliability analysis in an operational pin-constrained digital microfluidic biochip
Ultra-low-power signaling challenges for subthreshold global interconnects
An optimum channel routing algorithm in the restricted wire overlap model
Assessing merged DRAM/Logic technology
Realizations of simple fractional-order capacitor emulators with electronically-tunable capacitance
A study about the efficiency of formal high-level synthesis applied to verification
Integrating error correction and detection techniques in RISC-V processor microarchitecture for enhanced reliability
A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies
An efficient SRAM yield analysis method based on scaled-sigma adaptive importance sampling with meta-model accelerated
Delay fault models for VLSI circuits1
Energy aware synthesis of application kernels through composition of data-paths on a CGRA
Cascode subthreshold PTAT source bandgap voltage reference circuit
Flipped voltage follower based fourth order filter and its application to portable ECG acquisition system
High-speed systolic architectures for finite field inversion
Channel routing for strictly multiterminal nets
A survey on fault injection methods of digital integrated circuits
Timing modeling of latch-controlled sub-systems
Design methodologies and CAD tools
Automatic design rule adaptation of leaf cell layouts
Compiling concurrent programs for embedded sequential execution
A high current efficiency multipath nested feedforward compensation technique for two-stage amplifier
Approximate Toom-Cook FFT with sparsity aware error tuning in a shared memory architecture
A low power passive-active ΔΣ modulator with high-resolution employing an integrator with open-loop unity-gain buffer
High-robustness CMOS voltage reference for automotive applications with PVT variation tolerance
Pipelined recursive filter architectures for subband image coding
A low-power 2GHz data conversion using delta modulation for portable application
Integrated FIR median hybrid filter
Low power chaotic oscillator employing CMOS
Reducing signal timing variations in inter-core busses
A novel single-ended 9T FinFET sub-threshold SRAM cell with high operating margins and low write power for low voltage operations
Self-timed communication platform for implementing high-performance systems-on-chip
A split-based fully digital feedforward background calibration technique for timing mismatch in TIADC
Low power finite state machine synthesis using power-gating
Clock buffer polarity assignment under useful skew constraints
Side-channel attack resilient implementation of homomorphic encryption using elliptic curve cryptography for secure cloud computing
Synthesis-based design and implementation methodology of high-speed, high-performing unit: L2 cache unit design
Sensitivity aware NSGA-II based Pareto front generation for the optimal sizing of analog circuits
An autolayout system for a hierarchical i.c. design environment
A column parity based fault detection mechanism for FIFO buffers
A new wiring architectUre for parallel processing applications
An architecture for a VLSI FFT processor
Compact model to efficiently characterize TSV-to-transistor noise coupling in 3D ICs
ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing
Guest editorial - Special issue on hardware assisted techniques for IoT and bigdata applications
New efficient totally self-checking Berger code checkers
Hardware efficient approximate activation functions for a Long-Short-Term Memory cell
Compiled code simulation of analog and mixed-signal systems using piecewise linear modeling of nonlinear parameters: A case study for DeltaSigma modulator simulation
Fredkin Gate-based Arbiter PUF design through challenge obfuscation using garbage outputs
BiLink: A high performance NoC router architecture using bi-directional link with double data rate
A proof rule for restoring logic circuits
Fast thermal analysis for fixed-outline 3D floorplanning
Methods increasing inherent resistance of ECC designs against horizontal attacks
Low-power VLSI synthesis of DSP systems
Avoidance vs. repair: New approaches to increasing electromigration robustness in VLSI routing
Delay fault diagnosis in sequential circuits based on path tracing
Generalized high speed Itoh-Tsujii multiplicative inversion architecture for FPGAs
A practical IC design system for VLSI technology
An area-efficient path memory structure for VLSI implementation of high speed Viterbi decoders
Hardware acceleration of Tiny YOLO deep neural networks for sign language recognition: A comprehensive performance analysis
An overclocking clock software PUF circuit with no additional hardware resource overhead based on video coding circuit
Strategy of logic synthesis using MTBDD dedicated to FPGA
Improved diagnosis using enhanced fault dominance
Design of a high-speed, low-noise CMOS data output buffer
BIST for systems-on-a-chip
Operators allocation in the silicon compiler SCOOP
Hybrid asynchronous circuit generation amenable to conventional EDA flow
Gated logic controlled 10T-SRAM for low-power bidirectional ring oscillators
Formal verification of high-level data-flow synthesis designs using relational modeling and symbolic computation
Minimization of Word-Level Decision Diagrams
Fault-tolerant analysis of TMR design with noise-aware logic
Component placement in VLSI circuits using a constant pressure Monte Carlo method
Orthogonal obfuscation based key management for multiple IP protection
On retiming for FPGA logic module minimization
Hardware architectures for algebra, cryptology, and number theory
A bulk-driven quasi-floating gate FVF current mirror for low voltage, low power applications
A compact structure for triple-memristor maps with a hyperplane of fixed points
DSA guiding template assignment with multiple redundant via and dummy via insertion
Novel hybrid TFET-FinFET 12T SRAM cells with enhanced write margin and read performance
Semi-empirical RF MOST model for CMOS 65 nm technologies: Theory, extraction method and validation
Performance analysis of radix-4 adders
Trade-offs among power consumption and other design parameters of two-stage recycling folded cascode OTA that using embedded cascode current buffer compensation technology
An FPGA systolic array using pseudo-random bit generators for computing Goldbach partitions
SMS-CAM: Shared matchline scheme for content addressable memory
VYUHA: A detailed router for multiple routing models
Quasi-exact logic functions through classification trees
Circal: A calculus for circuit description
The design of a high-performance cache controller: a case study in asynchronous synthesis
PDQRRFF: Poisson-distributed quantum random reversible flip flop generator for BIST
Communication code generation in systems of affine recurrence equations
A foreground-liked continuous-time offset cancellation strategy for open-loop inter-stage amplifiers in high-resolution ADCs
Systolic algorithms for solving a sparse system of linear equations in circuit simulation
Low-memory and high-performance architectures for the CCSDS 122.0-B-1 compression standard
An innovative two-stage data compression scheme using adaptive block merging technique
Hierarchical sizing and biasing of analog firm intellectual properties
Compact agile Tchebycheff transform variant for temporal compression of neural signals on brain-implantable microsystems
Heterogeneous neural network based on locally active memristor with multiple firing patterns
Balanced multi-level multi-way partitioning of analog integrated circuits for hierarchical symbolic analysis
Dynamics analysis of 3D hyperchaotic map based on discrete Hopfield neural network coupled discrete cosine memristor
FSPICE: a tool for fault modelling in MOS circuits
Observability in systems with extreme multistability
Customization of an embedded RISC CPU with SIMD extensions for video encoding: A case study
Contemporary CMOS aging mitigation techniques: Survey, taxonomy, and methods