yusuke1997/dblp-id-title huggingface dataset:
Stochastic Error-Correcting Syntax Analysis for Recognition of Noisy Patterns
High-Speed Analog-to-Digital Converters Utilizing Tunnel Diodes
Solution to Boolean Equations
Construction of Rotation Symmetric S-Boxes with High Nonlinearity and Improved DPA Resistivity
A Nonlinear-Summation Threshold Device
Finding Rectangle Intersections by Divide-and Conquer
Impact of Large Scale Integration on Aerospace Computers
B74-16 Design of On-Line Computer Systems
Processor Allocation for Horizontal and Vertical Parallelism and Related Speedup Bounds
Determination of the Irredundant Normal Forms of a Truth Function by Iterated Consensus of the Prime Implicants
ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling
Enabling Context-Awareness by Predicate Detection in Asynchronous Environments
An Automatic Test Generation System for Illiac IV Logic Boards
A Quantitative Characterization of Cross Coverage
JCSRC: Joint Client Selection and Resource Configuration for Energy-Efficient Multi-Task Federated Learning
An Algorithm for Redundant Binary Bit-Pipelined Rational Arithmetic
Zweilous: A Decoupled and Flexible Memory Management Framework
XMeter: Finding Approximable Functions and Predicting Their Accuracy
On Monte Carlo Testing of Logic Tree Networks
Reliability Measure of Hardware Redundancy Fault-Tolerant Digital Systems with Intermittent Faults
A Straightforward Way of Generating All Boolean Functions of N Variables Using a Single Magnetic Circuit
Systolic Array Implementation o Euclid's Algorithm for Inversion and Division in GF (2 m )
An Efficient TCAM-Based Implementation of Multipattern Matching Using Covered State Encoding
A Modification to a Decomposition Algorithm of Gordon and Srikanthan
Application of Uniform Loading Theory to Circuit Packaging and Memory Arrays in High-Speed Computers
Blockchain-Based Privacy-Preserving Deduplication and Integrity Auditing in Cloud Storage
B73-6 Computing Terminals: International Computer State of the Art Report
A Simple Technique for the Determination of Delayed Maximal Length Linear Binary Sequences
Comments on "The Prime Memory Systems for Array Access"
Learning the Error Features of Approximate Multipliers for Neural Network Applications
Analysis of a Magneto-Optic Readout System
On the Solution of Boolean and Pseudo-Boolean Relations
Dynamic Erase Voltage and Time Scaling for Extending Lifetime of NAND Flash-Based SSDs
Partitioning Problems in Parallel, Pipelined, and Distributed Computing
B 74-33 Peripheral Devices
Some Fundamental Properties of Multiple-Valued Kleenean Functions and Determination of Their Logic Formulas
Tree Structured Sequential Multiple-Valued Logic Design from Universal Modules
Efficient complex matrix multiplication
Contention Minimization in Emerging SMART NoC via Direct and Indirect Routes
A Unified Framework for Line-Like Skeleton Extraction in 2D/3D Sensor Networks
A Performance Modeling and Evaluation of the Cambridge Fast Ring
R68-48 A Multiprogramming Monitor for Small Machines
Reducing Area Overhead for Error-Protecting Large L2/L3 Caches
Test Generation from LOTOS Specifications
Improved Miller's Algorithm for Computing Pairings on Edwards Curves
Dynamic Multiple Parity (DMP) Disk Array for Serial Transaction Processing
On Arithmetical Shift for Walsh Functions
Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis
Your Favorite Parallel Algorithms Might Not Be as Fast as You Think
The Solenoid Array-A New Computer Element
An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor
Price Competition in an Oligopoly Market with Multiple IaaS Cloud Providers
Synthesis of Optimal Amiguity Resolver Functions
( N, K ) Concept Fault Tolerance
A Unified Numeric Representation Arithmetic Unit and Its Language Support
Hierarchical Diagnosis of Identical Units in a System
An Abstract Model for Digital System Fault Diagnosis
Comment on "An Efficient Homomorphic MAC with Small Key Size for Authentication in Network Coding"
A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults
Dynamic Memories with Enhanced Data Access
Design of Strongly Secure Communication and Computation Channels by Nonlinear Error Detecting Codes
FERRARI: A Flexible Software-Based Fault and Error Injection System
On the Design of the Arithmetic Unit of a Fixed-Word-Length Computer from the Standpoint of Computational Accuracy
Deadlock-Free Fault-Tolerant Routing in Injured Hypercubes
Proactive Power-Aware Cache Management for Mobile Computing Systems
AXI-IC$^{\mathrm{ RT}}$ RT : Towards a Real-Time AXI-Interconnect for Highly Integrated SoCs
MINIME: Pattern-Aware Multicore Benchmark Synthesizer
SPONGENT: The Design Space of Lightweight Cryptographic Hashing
An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time
Classification of the Keyhole Shaped Tombs by Template Matching Method
Efficient Replicated Remote File Comparison
Prediction-Based Micro-Scheduler: Toward Responsive Scheduling of General-Purpose Operating Systems
Practical Parameters for Somewhat Homomorphic Encryption Schemes on Binary Circuits
Homing Sequence Derivation With Quantified Boolean Satisfiability
An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System
A Comparative Analysis of Cache Designs for Vector Processing
Address Generation in an Array Processor
High-Performance Designs for Linear Algebra Operations on Reconfigurable Hardware
Deterministic Scheduling with Pipelined Processors
On (d, k, μ) Graphs
Compound Sequential Probability Ratio Test for the Classification of Statistically Dependent Patterns
EPRICE: An Efficient and Privacy-Preserving Real-Time Incentive System for Crowdsensing in Industrial Internet of Things
A New Self-Routing Permutation Network
Paired Many-to-Many Disjoint Path Covers in Recursive Circulants $(G(2^m, 4))$
Complexity and Fast Algorithms for Multiexponentiations
Dynamic Characteristics of Loops
Multiaccess Memory System for Attached SIMD Computer
Zero and Narrow-Width Value-Aware Compression for Quantized Convolutional Neural Networks
Comments on "On a New Class of Bounds on Bayes' Risk in Multihypothesis Pattern Recognition"
Practical Temporal Prefetching With Compressed On-Chip Metadata
Floating Point Fault Tolerance with Backward Error Assertions
The Philips Computer PASCAL
Average Values of Quantities Appearing in Multiple Output Boolean Minimization
Computation of an Equilibrium in Spectrum Markets for Cognitive Radio Networks
On the Complexity of Boolean Functions Computed by Lazy Oracles
The Cascade Decomposition of Sequential Machines
Automatic Generation and Optimization Framework of NoC-Based Neural Network Accelerator Through Reinforcement Learning
Synchronous Counters Constructed Entirely of J-K Flip-Flops
Spare Capacity as a Means of Fault Detection and Diagnosis in Multiprocessor Systems
Diode-Steered Magnetic-Core Memory
Minimum Broadcast Trees
On Distributed Computing Systems Reliability Analysis Under Program Execution Constraints
Counting with Feedback Shift Registers by Means of a Jump Technique
Data Allocation on Wireless Broadcast Channels for Efficient Query Processing
Digital Straight Line Segments
Analytic Modeling of Clustered RAID with Mapping Based on Nearly Random Permutation
A Sound and Complete Axiomatization of Majority-n Logic
A New Technique for Optimization Problems in Graph Theory
A Unified and Division-Free CORDIC Argument Reduction Method with Unlimited Convergence Domain Including Inverse Hyperbolic Functions
Comments on "Matrix Processors Using p -Adic Arithmetic for Exact Linear Computations"
Families of Fixed Degree Graphs for Processor Interconnection
Ensuring Cloud Data Reliability with Minimum Replication by Proactive Replica Checking
Side-Channel Analysis and Countermeasure Design on ARM-Based Quantum-Resistant SIKE
Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs
A Comparison of Linear Sequential Circuits and Arithmetic Sequences
Meta-Block: Exploiting Cross-Layer and Direct Storage Access for Decentralized Blockchain Storage Systems
Fast Complex BIFORE Transform by Matrix Partitioning
Tissue P Systems With States in Cells
A Method for Minimizing the Number of Internal States in Incompletely Specified Sequential Networks
SciNet: Codesign of Resource Management in Cloud Computing Environments
Matching Language and Hardware for Parallel Computation in the Linda Machine
Tolerating Sensor Timing Faults in Highly Responsive Hard Real-Time Systems
A Method for Reducing the Number of Input Variables to Synchronous Sequential Circuits
Algorithms for a Set Partitioning Problem Arising in the Design of Multipurpose Units
Stochastic Bounds for Parallel Program Execution Times with Processor Constraints
Cache Friendliness-Aware Managementof Shared Last-Level Caches for HighPerformance Multi-Core Systems
Real-Time Scheduling and Analysis of Fixed-Priority Tasks on a Basic Heterogeneous Architecture With Multiple CPUs and Many PEs
Dynamic Load Balancing of Dispatch Scheduling for Solid State Disks
Towards an Oscillator Based TRNG with a Certified Entropy Rate
NoC-Based FPGA Acceleration for Monte Carlo Simulations with Applications to SPECT Imaging
Breaking the Interaction Wall: A DLPU-Centric Deep Learning Computing System
Synergistic Fault-Tolerance for Memory Chips
A Quantification of Aborting Effect for Real-Time Data Accesses
The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits
Data Replication Approach with Consistency Guarantee for Data Grid
ReDas: A Lightweight Architecture for Supporting Fine-Grained Reshaping and Multiple Dataflows on Systolic Array
A Combination Hardware-Software Debugging System
Minimizing Eavesdropping Risk by Transmission Power Control in Multihop Wireless Networks
Node-Covering, Error-Correcting Codes and Multiprocessors with Very High Average Fault Tolerance
A Simple Approach to the Error Analysis of Division-Free Numerical Algorithms
Quantum Dimension Reduction for Pattern Recognition in High-Resolution Spatio-Spectral Data
Robust Soft Error Tolerant CMOS Latch Configurations
A Matrix Formalism for Asynchronous Implementation of Algorithms
Interprocessor Traffic Scheduling Algorithm for Multiple-Processor Networks
Algebraic Properties of Symmetric and Partially Symmetric Boolean Functions
Two-Level Replacement Decisions in Paging Stores
An Energy-Efficient Memristive Threshold Logic Circuit
Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults
B74-15 Iterative Methods for Nonlinear Optimization Problems
Database Applications ot the FETCH-AND-ADD Instruction
Finding Lowest Common Ancestors in Parallel
Synergy of Lip-Motion and Acoustic Features in Biometric Speech and Speaker Recognition
Distributed Training of Support Vector Machine on a Multiple-FPGA System
The Tree Set of a Linear Machine
A New Data Base for Syntax-Directed Pattern Analysis and Recognition
The Computational Complexity of a Class of Minimization Algorithms for Switching Functions
Irredundant Normal Forms and Minimal Dependece Sets of a Boolean Function
Comments on "A Readily Implemented Single-Error-Correcting Unit-Distance Counting Code"
Graph-Based Algorithms for Boolean Function Manipulation
Universal Logic Modules and Their Applications
Low Complexity Bit Parallel Architectures for Polynomial Basis Multiplication over GF(2^{m})
Serial Matrix Storage Systems
An Examination of the Cost Function for Programmable Logic Arrays
RepuCoin: Your Reputation Is Your Power
Performance-Energy Optimizations for Shared Vector Accelerators in Multicores
Dual-Polarity Logic as a Design Tool
A Scalable Peer-to-Peer Architecture for Distributed Information Monitoring Applications
On the Memory Access Patterns of Supercomputer Applications: Benchmark Selection and Its Implications
Geometrical Learning Algorithm for Multilayer Neural Networks in a Binary Field
Improving the Accuracy of History Based Branch Prediction
Fully Digit On-Line Networks
On the Construction of Data Aggregation Tree with Minimum Energy Cost in Wireless Sensor Networks: NP-Completeness and Approximation Algorithms
Digital techniques in analog systems
Ara2: Exploring Single- and Multi-Core Vector Processing With an Efficient RVV 1.0 Compliant Open-Source Processor
Constructing Optimal Search Trees in Optimal Time
Virtual Tree Machines
Easily Testable Iterative Systems
LS-Sig: Locality-Sensitive Signatures for Transactional Memory
On Instantiating Pairing-Based Protocols with Elliptic Curves of Embedding Degree One
Bounds on the Number of Processors and Time for Multiprocessor Optimal Schedules
Stability and Admissibility of Adaptive Threshold Logic Convergence
Compact Hash Tables Using Bidirectional Linear Probing
A Parallel Computational Model for Integrated Speech and Natural Language Understanding
On the Improvement of a Linear Separation by Extending the Adaptive Process with a Stricter Criterion
Economical Circuits for the Analog Solution of Algebraic Equations
A/D Conversion for Radix (-2)
Dynamic Remapping of Parallel Computations with Varying Resource Demands
Optimal Fault Diagnosis in Comparison Models
Automated Design of Multiple-Valued Logic Circuits by Automatic Theorem Proving Techniques
Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors
Type-Aware Federated Scheduling for Typed DAG Tasks on Heterogeneous Multicore Platforms
A New Double-Rank Realization of Sequential Machines
Pulse Input Asynchronous Sequential Circuits
Hierarchical Multipartite Function Evaluation
On the State Assignment Problem for Sequential Machines. I
Free Dimensions-An Effective Approach to Achieving Fault Tolerance in Hypercubes
Design Issues in Division and Other Floating-Point Operations
Focus and Shoot: Exploring Auto-Focus in RFID Tag Identification Towards a Specified Area
Some Performance Issues in Multiprocessor System Design
Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing
Generation and Asymmetry of Self-Dual Threshold Functions
On the Equivalence of Finite-State Sequential Machine Models
Heuristic Algorithms for Single Row Routing
RSQC: Recursive Sparse QUBO Construction for Quantum Annealing Machines
Tamper Proofing by Design Using Generalized Involution-Based Concurrent Error Detection for Involutional Substitution Permutation and Feistel Networks
False Sharing ans Spatial Locality in Multiprocessor Caches
A General Model for Memory Interference in Multiprocessors
A Transistor Pulse Generator for Digital Systems
Comments on "Sign/Logarithm Arithmetic for FFT Implementation''
On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences
Intelligent Magnetic Bubble Memories and Their Applications in Data Base Management Systems
A Metaobject Architecture for Fault-Tolerant Distributed Systems: The FRIENDS Approach
Link-Layer Multicast in Large-Scale 802.11n Wireless LANs with Smart Antennas
Closed Partition Lattice and Machine Decomposition
Optimal Free-Space Management and Routing-Conscious Dynamic Placement for Reconfigurable Devices
Hardware Trojan Detection Methods for Gate-Level Netlists Based on Graph Neural Networks
A General Fault-Tolerant Minimal Routing for Mesh Architectures
Low-Overhead Network-on-Chip Support for Location-Oblivious Task Placement
Design of a Graphic Generator for Remote Terminal Application
Comment on "A New Routing Algorithm for a Class of Rearrangeable Networks"
Theory and Applications of the Double-Base Number System
Revision of the Buffer Length Derivation for a Modified E k /D/ 1 Systems by Maritsas and Hartley
Area Minimization in a Three-Sided Switchbox by Sliding the Modules
Decoupled Sectored Caches
The Time Dilation Technique for Timing Error Tolerance
A Family of New Efficient Arrays for Matrix Multiplication
Synthesizing Linear Array Algorithms from Nested For Loop Algorithms
On the Calculation of the Piecewise Linear Approximation to a Discrete Function
Some Aids to the Detection of Hazards in Combinational Switching Circuits
Low-Complexity Bit-Parallel Systolic Montgomery Multipliers for Special Classes of GF(2 m )
An Electronic Analog Cross Correlator for Dip Logs
A Dead-End Free Topology Maintenance Protocol for Geographic Forwarding in Wireless Sensor Networks
Scheduling Divisible Loads in Gaussian, Mesh and Torus Network of Processors
The Hall-Effect Analog Multiplier
A Fully Pipelined Systolic Array for Sinusoidal Sequence Generation
Neighborhood Information Dissemination in the Star Graph
Division Using a Logarithmic-Exponential Transform to Form a Short Reciprocal
On Concatenative Decompositions of Regular Events
A Time-Sequential Tabular Analysis of Flip-Flop Logical Operation
On Distributed Computations with Limited Resources
Computational Work of Combinational Machines
Bit-Level Systolic Array for Fast Exponentiation in GF(2^m)
Performance of Processor-Memory Interconnections for Multiprocessors
A Note on the Accuracy of Differential Analyzers
Algorithm-Based Fault Tolerant Synthesis for Linear Operations
A Note on the Accuracy of Digital Differential Analyzers
Pancyclicity of Matching Composition Networks under the Conditional Fault Model
Digital Letdown Computer for Vertical Guidance
Bounds on the Period of Oscillatory Activity in Randomly Interconnected Networks of Neuron-Like Elements
Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process
Short Code: An Efficient RAID-6 MDS Code for Optimizing Degraded Reads and Partial Stripe Writes
Testing from a Nondeterministic Finite State Machine Using Adaptive State Counting
Workload-Based Software Rejuvenation in Cloud Systems
On the Use of Continued Fractions for Digital Computer Arithmetic
Enabling Homomorphically Encrypted Inference for Large DNN Models
Concurrency Control for Mixed Transactions in Real-Time Databases
A Time Fairness-Based MAC Algorithm for Throughput Maximization in 802.11 Networks
Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip
Anomaly Detection in Embedded Systems
Block-Precise Processors: Low-Power Processors with Reduced Operand Store Accesses and Result Broadcasts
A Logarithmic Voltage Quantizer
Model-Free Reinforcement Learning and Bayesian Classification in System-Level Power Management
Characterization of Unate Cascade Realizability Using Parameters
Composable Proxy Services to Support Collaboration on the Mobile Internet
Detection of Storage Errors in Mass Memories Using Low-Cost Arithmetic Error Codes
Parallel Digital Differential Analyzer with Arbitrary Stored Interconnections
Asignment of Job Modules onto Array Processors
A sub-audio time delay circuit
A Realizable Model for Stochastic Sequential Machines
Complex Function Approximation Using Two-Dimensional Interpolation
Multithreading with Distributed Functional Units
B74-44 The Elements of Programming Style
An Automaton Model for Scheduling Constraints in Synchronous Machines
On the Number of Fanout-Free Functions and Unate Cascade Functions
The Concept of Unschedulability Core for Optimizing Real-Time Systems with Fixed-Priority Scheduling
Cache Design with Domain Wall Memory
An Efficient Deadlock Avoidance Rechnique
A Memory-Efficient Tables-and-Additions Method for Accurate Computation of Elementary Functions
FVM: Practical Feather-Weight Virtualization on Commodity Microcontrollers
A Study of Feedback and Errors in Sequential Machines
Propagation of Sense Signals in Large-Scale Magnetic Thin Film Memories
Comments on "The Reliability of Periodically Repaired n - 1/ n Parallel Redundant Systems"
The Extra Stage Cube: A Fault-Tolerant Interconnection Network for Supersystems
General and Fast Inter-Process Communication via Bypassing Privileged Software
Localized Minimum-Energy Broadcasting for Wireless Multihop Networks with Directional Antennas
Efficient Prefix Updates for IP Router Using Lexicographic Ordering and Updatable Address Set
Modeling Bus Contention and Memory Interference in a Multiprocessor System
Completeness of Sets of Delayed-Logic Devices
A Class of M-Ary Asymmetric Symbol Error Correcting Codes for Data Entry Devices
Canonical Tributary Networks
Design of a Repairable Redundant Computer
Synthesis of Feed-Forward MOS Networks with Cells of Similar-Complexities
Transposition Networks as a Class of Fault-Tolerant Robust Networks
Diagnosis in the Presence of Known Faults
A Generalized Orthogonal Transformation Matriz
Optimal Placements of Flexible Objects: Part I: Analytical Results for the Unbounded Case
Proximity-Aware Local-Recoding Anonymization with MapReduce for Scalable Big Data Privacy Preservation in Cloud
Analysis of Multiprocessor Control Organizations with Partial Program Memory Replication
Queueing Analysis of Global Locking Synchronization Schemes for Multicopy Databases
Bitstream Fault Injections (BiFI)-Automated Fault Attacks Against SRAM-Based FPGAs
RAP.2 - An Associative Processor for Databases and Its Applications
On Binary Multiplication Using the Quarter Square Algorithm
Rotated Logging Storage Architectures for Data Centers: Models and Optimizations
Comments on "The Relationship Between Multivalued Switching Algebra and Boolean Algebra under Different Definitions of Complement"
Runtime Application Behavior Prediction Using a Statistical Metric Model
B72-4 Expanding Use of Computers in the 70' Technology-Markets • Needs • Technology
PCB Hardware Trojan Run-Time Detection Through Machine Learning
Remote Password Extraction from RFID Tags
Accelerating Correctly Rounded Floating-Point Division when the Divisor Is Known in Advance
SEER, A SEquence Extrapolating Robot
A New Second-Order Side Channel Attack Based on Linear Regression
Prediction-Based Asynchronous CPU-Budget Allocation for Soft-Real-Time Applications
Spatial-Keyword Skyline Publish/Subscribe Query Processing Over Distributed Sliding Window Streaming Data
Neuromorphic System for Spatial and Temporal Information Processing
A Threshold Logic Network for Shape Invariance
Redundant Floating-Point Decimal CORDIC Algorithm
The PM22I Interconnection Network
Efficient Multidimensional Packet Classification with Fast Updates
Generalized RTL Circuitsߝ Supplementary
Efficient Software Partial Packet Recovery in 802.11 Wireless LANs
Advanced Analysis Techniques for Cross-Product Coverage
An Optimal Frame Synchronization Technique Using an Associative Processor
High density digital recording system
Boolean and Pseudo-Boolean Test Generation for Feedback Bridging Faults
Distributed and Fault-Tolerant Computation for Retrieval Tasks Using Distributed Associative Memories
A Multifont Word Recognition System for Postal Address Reading
Hybrid Annealing Method Based on subQUBO Model Extraction With Multiple Solution Instances
Formal Verification of Fault Tolerance Using Theorem-Proving Techniques
Random Pattern Testability
Systematic Design of Pipelined Recursive Filters
Examples of Abstract Machines
A Scheme to Design Concurrent Error Detection Techniques for the Fast Fourier Transform Implemented in SRAM-Based FPGAs
Unleashing the Power of Differential Fault Attacks on QARMAv2
Dependability Analysis of a High-Speed Network Using Software-Implemented Fault Injection and Simulated Fault Injection
A Design of Reed-Solomon Decoder with Systolic Array Structure
Corrections and Comments on "On Models for Diagnosable Systems and Probabilistic Fault Diagnosis"
A Cache Tuning Heuristic for Multicore Architectures
Clockless Spintronic Logic: A Robust and Ultra-Low Power Computing Paradigm
Trigonometric Resolution in Analog Computers by Means of Multiplier Elements
An Improved Algorithm for Fault-Tolerant Routing in Hypercubes
Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures
Energy-Delay-Aware Joint Microservice Deployment and Request Routing With DVFS in Edge: A Reinforcement Learning Approach
An Architecture for Computing Zech's Logarithms in GF(2 m )
Interconnection Networks from Three-State Cells
A Systolic Accelerator for the Iterative Solution of Sparse Linear Systems
A Study of Software Failures and Recovery in the MVS Operating System
An Analysis of Edge Fault Tolerance in Recursively Decomposable Regular Networks
A Preemtive Scheduling Mechanism for Accurate Behavioral Simulation of Digital Designs