yusuke1997/dblp-id-title huggingface dataset:
Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP
Design Space Exploration of 1-D FFT Processor
Real-time Hand Gesture Recognition from Depth Images Using Convex Shape Decomposition Method
A New Moving Horizon Estimation Based Real-Time Motion Artifact Removal from Wavelet Subbands of ECG Signal Using Particle Filter
Omni-Directional Stereoscopic Images from One Omni-Directional Camera
Supervised Single Channel Speech Enhancement Based on Stationary Wavelet Transforms and Non-negative Matrix Factorization with Concatenated Framing Process and Subband Smooth Ratio Mask
Blind Source Separation for Non-Stationary Mixing
Peak Temperature Minimization via Task Allocation and Splitting for Heterogeneous MPSoC Real-Time Systems
Mesoscopic-level Simulation of Dynamics and Interactions of Biological Molecules Using Monte Carlo Simulation
A Hybrid Bags-of-Feature model for Sports Scene Classification
IterML: Iterative Machine Learning for Intelligent Parameter Pruning and Tuning in Graphics Processing Units
A Noise-Robust Convex-Optimized Positioning System Based on Code-Aided RSS Estimation and Virtual Base Station Transform
Audio-Video based People Counting and Security Framework for Traffic Crossings
An Efficient Architecture for the In-Place Fast Cosine Transform
A Link Layer Design for DisplayPort Interface with State Machine Based Packet Processing
Joint Algorithm-Architecture Optimization of CABAC
Statistical Performance Analysis and Estimation for Parallel Multimedia Processing
A Flexible LDPC/Turbo Decoder Architecture
Image processing on a memory array architecture
Resource Sharing Combined with Layout Effects in High-Level Synthesis
An Efficient Scalable RNS Architecture for Large Dynamic Ranges
Simple, Robust, and Memory-Efficient FastICA Algorithms Using the Huber M-Estimator Cost Function
He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores
Multipath Delay Estimation for Frequency Hopping Systems
GLRT Based Adaptive-Thresholding for CFAR-Detection of Pareto-Target in Pareto-Distributed Clutter
Probabilistic complexity analysis for a class of approximate DFT algorithms
Face Hallucination via Trend-Constrained Regularization
Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems
Joint Big Data Extraction Method for Coal Mine Safety with Characters and Words Fusion
Low-Complexity MIMO Detection in 5G IoT: The Box Decoding Approach
Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design
A Survey on Application Specific Processor Architectures for Digital Hearing Aids
Investigating the Effects of Transfer Learning on ROI-based Classification of Chest CT Images: A Case Study on Diffuse Lung Diseases
Single-chip image sensors with a digital processor array
On enhancing SIMD-controlled DSPs for performing recursive filtering
Practical Bounded-Skew Clock Routing
Parameterized High Throughput Function Evaluation for FPGAs
Deep Learning for Automated Occlusion Edge Detection in RGB-D Frames
Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits
A Stage-Combined Belief Propagation Decoder for Polar Codes
Improved Direction-of-Arrival Estimation Using Wavelet Based Denoising Techniques
Dynamically Adaptive Fast Motion Estimation Algorithm for HD Video
Compiling for Reduced Bit-Width Queue Processors
Acceleration of Zelinski Post-Filtering Calculation
Sequential Large Multipliers on FPGAs
DFC++ Processing Framework Concept - A Novel Framework Approach for Flexible Signal Processing on Embedded Systems
Throughput and Energy Efficiency of Wireless Powered Multi-tier MIMO HetNets
A High-Throughput VLSI Architecture Design of Arithmetic Encoder in JPEG2000
Inference from Low Precision Transcriptome Data Representation
Signal Adaptive Pipelined Hardware Design of Time-Varying Optimal Filter for Highly Nonstationary FM Signal Estimation
Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis
A Robust Video-Based Algorithm for Detecting Snow Movement in Traffic Scenes
On the Performance Analysis of a Class of Transform-domain NLMS Algorithms with Gaussian Inputs and Mixture Gaussian Additive Noise Environment
Special Issue on the Internet of Things (ISCC 2020)
PDA-SVM Hybrid: A Unified Model for Kernel-Based Supervised Classification
A Programmable Imager for Very High Speed Cellular Signal Processing
Cost-efficient high-radix division
Top-Down Saliency Detection via Contextual Pooling
Co-Synthesis to a Hybrid RISC/FPGA Architecture
A Low Cost Architecture for Variable Block Size Motion Estimation
Mapping Large LSTMs to FPGAs with Weight Reuse
Bioinspired Parallel Algorithms for Maximum Clique Problem on FPGA Architectures
Automatic Text-Independent Syllable Segmentation Using Singularity Exponents And Rényi Entropy
Designing Run-Time Reconfigurable Systems with JHDL
High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse
A chip set for pipeline and parallel pipeline FFT architectures
Algorithm and Software Optimization of Variable Block Size Motion Estimation for H.264/AVC on a VLIW-SIMD DSP
Low-energy Formulations of Support Vector Machine Kernel Functions for Biomedical Sensor Applications
Dictionary Learning for Bioacoustics Monitoring with Applications to Species Classification
Recognition of Pulse Wave Feature Points and Non-invasive Blood Pressure Measurement
Multicore and Manycore Implementations of ADMM-based Decoders for LDPC Decoding
Architecture of an Image Rendering Co-Processor for MPEG-4 Visual Compositing
Blind Model Selection for Automatic Speech Recognition in Reverberant Environments
Degradation Pattern of High Speed Roller Bearings Using a Data-Driven Deep Learning Approach
A UMTS-FDD Cell Search Engine
Optimizing throughput and resource utilization using pipelining: Transformation based approach
Pitch-Scaled Spectrum Based Excitation Model for HMM-based Speech Synthesis
Compact Code Generation for Tightly-Coupled Processor Arrays
A Low-power Dry Electrode-based ECG Signal Acquisition with De-noising and Feature Extraction
Polyphase Filter Approach for High Performance, FPGA-Based Quadrature Demodulation
Device-Free Target Following with Deep Spatial and Temporal Structures of CSI
Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies
A Data-Driven Based Security Situational Awareness Framework for Power Systems
Hazard-Free Self-Timed Design: Methodology and Application to Asynchronous Routing in an Heterogeneous Parallel Machine
A Temperature Compensated CMOS Ring Oscillator for Wireless Sensing Applications
Adaptive Score Functions for Maximum Likelihood ICA
Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse
Efficient System-Level Hardware Synthesis of Dataflow Programs Using Shared Memory Based FIFO - HEVC Decoder Case Study
An Adrenal Segmentation Model Based on Shape Associating Level Set in Sequence of CT Images
Adaptive Reliability Measure and Optimum Integration Weight for Decision Fusion Audio-visual Speech Recognition
A Wavelet Optimized Video Copy Detection Using Content Fingerprinting
Resource constrained scheduling of uniform algorithms
Prototype Filter Design Approaches for Near Perfect Reconstruction Cosine Modulated Filter Banks - A Review
Improvement of Honey Bee Tracking on 2D Video with Hough Transform and Kalman Filter
Correction to: Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System
Energy-Efficient Double-Edge Triggered Flip-Flop
Enhancing Hardware Assisted Test Insertion Capabilities on Embedded Processors using an FPGA-based Agile Test Support Co-processor
Design and Factorization of Two-Channel Perfect Reconstruction Filter Banks with Causal-Stable IIR Filters
A Reconfigurable Posit Tensor Unit with Variable-Precision Arithmetic and Automatic Data Streaming
Network-Adaptive Rate Control and Unequal Loss Protection with TCP-Friendly Protocol for Scalable Video Over Internet
Pipelined VLSI Architecture using CORDIC for Transform Domain Equalizer
Dedicated Circuits for the Generation of Windows in Image Processing Architectures
An Improved SLM Algorithm for OFDMA System with Implicit Side Information
High-level algorithm and architecture transformations for DSP synthesis
Signal processing using cellular neural networks
An Efficient Pipeline Architecture and Memory Bit-Width Analysis for Discrete Wavelet Transform of the 9/7 Filter for JPEG 2000
Low Power Synthesis Methodology with Data Format Optimization Applied on a DWT
Code Density and Energy Efficiency of Exposed Datapath Architectures
Fast Inter Mode Decision Algorithm Based on Mode Mapping and Decision Tree for P Frames in MPEG-2 to H.264/AVC Transcoding
SIS-CAM: An Interpretability Analysis Method for the Security of Convolutional Neural Network Models Based on Image Big Data
Efficient Parallel Computing-Based Implementation Methods of DCT-Kernel-Based Real-Valued Discrete Gabor Transform and Expansion
Supernode Fusion Model Based on Bimodal Action Recognition
The sarnoff engine: A massively parallel computer for high definition system simulation
A Review of Audio Fingerprinting
Fast Integer Word-length Optimization for Fixed-point Systems - Integer Word-length Optimization
Combination of Multi Level Forecasts
Correction to: Anomaly Detection Techniques in the Gaia Space Mission Data
A Technical Review of SCA Based Software Defined Radios: Vision, Reality and Current Status
GC-Net: An Unsupervised Network for Gaussian Curvature Optimization on Images
Area-Efficient Parallel Syndrome Generators for Linear Block Codes
Multicore Performance Prediction with MPET
MPEG-2 AAC 5.1-Channel Decoder Software for a Low-Power Embedded RISC Microprocessor
Design and Implementation of a Multi-Beam Passive Sonar System on Multi-Core Processors
A Distortion-Sensitive Seam Carving Algorithm for Content-Aware Image Resizing
Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs - In-Depth Study of a Computer Vision Application
A Novel Recyclable Garbage Detection System for Waste-to-energy Based On Optimized CenterNet With Feature Fusion
Hazy Removal via Graph Convolutional with Attention Network
TAFFNet: Two-Stage Attention-Based Feature Fusion Network for Surface Defect Detection
Fully Systolic FFT Architecture for Giga-sample Applications
Linear QR Architecture for a Single Chip Adaptive Beamformer
A Scalable System Architecture for High-Throughput Turbo-Decoders
Frame Rate and Viseme Analysis for Multimedia Applications to Assist Speechreading
Consistent Estimation of Erased Data in a DPCM Based Multiple Description Coding System
A Co-Design Methodology for Telecommunication Systems: A Case Study of an Acoustic Echo Canceller
Improved Particle Filter Resampling Architectures
An Ultrasonic Positioning System for an Assembly-Work Guide
Efficient Weighted Histogram Features for Single-Shot Person Re-Identification
On-line Convolutive Blind Source Separation of Non-Stationary Signals
Move Based Algorithm for Runtime Mapping of Dataflow Actors on Heterogeneous MPSoCs
3D-Object Space Reconstruction from Planar Recorded Data of 3D-Integral Images
Memory Controller for Vector Processor
Spectrum Analysis-Based Traffic Video Synopsis
Structure and Sequencing Preserving Representations for Skeleton-based Action Recognition Relying on Attention Mechanisms
System Level Design as Applied to CMU Wearable Computers
Multi Feature Extraction and Trend Prediction for Weibo Topic Dissemination Network
Feature Selection for Genomic Signal Processing: Unsupervised, Supervised, and Self-Supervised Scenarios
Design of RNS Reverse Converters with Constant Shifting to Residue Datapath Channels
Multiplierless Realization of Linear DSP Transforms by Using Common Two-Term Expressions
Performance and ASIC Designs of the K-best LSD and LMMSE Detectors for LTE Downlink
Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture
Self-tuned continuous-time notch filters
Scanning Modulation Transfer Function Model of TDI CMOS Image Sensor
Automatic Target Segmentation based on Texture for Microscopic Images of Natural Medical Herbal Powders
A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration
How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System
Concurrent Error Detection in Multiplexer-Based Multipliers for Normal Basis of GF(2 m ) Using Double Parity Prediction Scheme
Correction: A Model to Detect the Fraud of Electronic Payment Card Transactions Based on Stream Processing in Big Data
Legitimate Skew Clock Routing with Buffer Insertion
Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Codec
Binomial filters
Real-Time Software Video Codec with a Fast Adaptive Motion Vector Search
VASS - A VLSI array system synthesizer
Deep Multimodal Habit Tracking System: A User-adaptive Approach for Low-power Embedded Systems
A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification
A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling
Analysis of Forwarding Mechanisms on Fine-Grain Gradient Sinking Model in WSN
A Finite Volume Framework for Geometric Surface Processing
Fisher Discriminative Dictionary Learning for Vehicle Classification in Acoustic Sensor Networks
Design and FPGA Implementation of Pre-computation Based Radix-4 Hyperbolic CORDIC for Direct Digital Synthesis
Pedestrian Detection by Using Weighted Channel Features with Hierarchical Region Reduction
Block-Layered Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes
Optimization of Energy and Security in Mobile Sensor Network Using Classification Based Signal Processing in Heterogeneous Network
Efficient Recursive Digital Filters using Combined Look-Ahead Denominator Distribution and Numerator Decomposition
Design and Implementation of a Flexible Multi-Mode DVB-T/H Receiver and Extension to DVBT-2
Dynamic Texture Classification Based on 3D ICA-Learned Filters and Fisher Vector Encoding in Big Data Environment
Implementation of a Virtual Assistant System Based on Deep Multi-modal Data Integration
An Architecture for Programmable Multi-core IP Accelerated Platform with an Advanced Application of H.264 Codec Implementation
Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits
Optimized Implementation of RNS FIR Filters Based on FPGAs
A Multiplierless 2-D Convolver Chip for Real-Time Image Processing
An Improved Single and Double-Adjacent Error Correcting Codec with Lower Decoding Overheads
Beamforming and Scalable Image Processing in Vehicle-to-Vehicle Networks
Web Load Balancing Based on DNS Coordination and Reducing Energy Consumption Strategy
Electromagnetics-Related Aspects of Signaling and Signal Processing for UWB Short Range Radios
Design and Implementation of Portable Device Based Mobile Medical Service System
Block-Matching Correlation Motion Estimation for Frame-Rate up-Conversion
Erratum: Non-negative Matrix Factorization with Orthogonality Constraints and its Application to Raman Spectroscopy
An Orthogonal Time-Frequency Extraction Approach to 2D Systolic Architecture for 1D DFT Computation
An efficient tree architecture for modulo 2 n +1 multiplication
Editor's Note: Special Issue on Big Data Analysis and Privacy
DSP system integration and prototyping with FPGAS
C++ Support and Applications for Embedded Multicore DSP Systems
Correction to: Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop
Fast Reconfigurable Elliptic Curve Cryptography Acceleration for GF (2 m ) on 32 bit Processors
Two-channel-based Noise Reduction in a Complex Spectrum Plane for Hands-free Communication System
A bit-level systolic architecture for implementing a VQ tree search
DTW Based Classification of Diverse Pre-Processed Time Series Obtained from Handwritten PIN Words and Signatures
Loop Distribution and Fusion with Timing and Code Size Optimization
Retinal Vessel Radius Estimation and a Vessel Center Line Segmentation Method Based on Ridge Descriptors
An Equivalent Exchange Based Data Forwarding Incentive Scheme for Socially Aware Networks
Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications
Using FPGAs to implement self-timed systems
Social Similarity Routing Algorithm based on Socially Aware Networks in the Big Data Environment
An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture
Parallelization of Connected-Component Labeling on TILE64 Many-Core Platform
Pathological Gait Detection Based on Multiple Regression Models Using Unobtrusive Sensing Technology
A Cyber-Physical System for Integrated Remote Control and Protection of Smart grid Critical Infrastructures
Editor's Note: Special Issue on Big Data Analytics and Privacy
System Comparison of Electronic and Optical Correlator
Hardware Architecture for Guessing Random Additive Noise Decoding Markov Order (GRAND-MO)
Resolution Improvement of Scanning Acoustic Microscopy Using Sparse Signal Representation
Exploring Hypermedia Processor Design Space
Energy Efficient Real-Time Task Scheduling for Embedded Systems with Hybrid Main Memory
An Ultra-Highly Parallel Polynomial Multiplier for the Bootstrapping Algorithm in a Fully Homomorphic Encryption Scheme
Optimization-Based Embedding for Wavelet-Domain Audio Watermarking
Adaptive CFAR PI Processor for Radar Target Detection in Pulse Jamming
Increasing SDR Receiver Dynamic Range by ADC Diversity
Implementation of a Multi-band Pulsed-OFDM Transceiver
Maximize Parallelism Minimize Overhead for Nested Loops via Loop Striping
A Halide-based Synergistic Computing Framework for Heterogeneous Systems
Times Square - Marriage of Real-Time and Logical-Time in GALS and Synchronous Languages
Knowledge Based Image Annotation Refinement
Parallel Compensation of Scale Factor for the CORDIC Algorithm
A study of VLSI symmetric FIR filter structures
Correction to: Efficient Hardware Architectures for 1D- and MD-LSTM Networks
FFT computation with linear processor arrays using a data-driven control scheme
On the Mapping of Incremental Redundancy into a Physical Layer ASIC
Preface to the Special Issue on Methods, Tools, and Architectures for Signal and Image Processing
Grid-Enabled BLASTZ: Application to Comparative Genomics
Smart Camera for Traffic Applications
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications
CSD-RNS-based Single Constant Multipliers
RImCom: Raster-order Image Compressor for Embedded Video Applications
A Novel Deblocking Filter Architecture for H.264/AVC
Memory Power Reduction for High-Speed Implementation of Turbo Codes
A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications
Sensitivity Analysis of Calibration Methods and Factors Effecting the Statistical Nature of Radiation Measurement
HIBI Communication Network for System-on-Chip
Energy-Efficient Object Detection: Impact of Weight Clustering for Different Arithmetic Representations
MAHASIM: Machine-Learning Hardware Acceleration Using a Software-Defined Intelligent Memory System
Fast Multi-reference Motion Estimation via Enhanced Downhill Simplex Search
Quantitative Analysis of MR Brain Image Sequences by Adaptive Self-Organizing Finite Mixtures
Decimal Division Algorithms: The Issue of Partial Remainders
Medical Image Compression Approach Based on Image Resizing, Digital Watermarking and Lossless Compression
Data Center Switch for Load Balanced Fat-Trees
A New Intelligent Approach for Recognition of Digital Satellite Signals
Correction to: the Video Spatial Error Concealment Algorithm Using Separately-Directional Interpolation Technique
A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform
Integrating Energy-Optimizing Scheduling of Moldable Streaming Tasks with Design Space Exploration for Multiple Core Types on Configurable Platforms
GPUBlocks: GUI Programming Tool for CUDA and OpenCL
Tree-based special-purpose Array architectures for neural computing
Adversarial Attacks on Voice Recognition Based on Hyper Dimensional Computing
A Reconfigurable Channel Filter for Software Defined Radio Using RNS
Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme
A Framework for Mimic Defense System in Cyberspace
A floating-point systolic array processing element with serial communication and built-in self-test
High Frame Rate 3-D Ultrasound Imaging Using Separable Beamforming
Hardware Resource Optimized Detection of LFM Signals with Unknown Start Frequency and Frequency Rate
Reconfigurable Interpolation Architecture for Multistandard Video Decoding
Sign Language Phoneme Transcription with Rule-based Hand Trajectory Segmentation
Exploiting Compress Sensing in Training of Deep Neural Network for Self-Noise Cancellation in Underwater Acoustics
Energy-adaptive Pulse Amplitude Modulation for IR-UWB Communications Under Renewable Energy
A polyphase architecture for serial-input convolvers
A Low Cost Multi-Tiered Approach to Improving the Reliability of Multi-Level Cell Pram
Adaptive Particle Filter for Data Fusion of Multiple Cameras
Multi-Level Cell Progressive Differentiable Architecture Search to Improve Image Classification Accuracy
An Efficient Architecture for Sequential Monte Carlo Receivers in Wireless Flat-Fading Channels
High Order Multi-User MIMO Subspace Detection
A New Fast Discrete Fourier Transform
Rapid Prototyping of Application-Specific Signal Processors (RASSP) In-Progress Report
An Adaptive Multicast Tree with QoS Support for Heterogeneous Recipients
A High Speed VLSI Architecture for Handwriting Recognition
Real-Time FPGA Implementation of Parallel Connected Component Labelling for a 4K Video Stream
Comments on "Minimizing Buffer Requirements Under Rate-Optimal Schedule in Regular Dataflow Networks" - Comments on Paper from R. Govindarajan, Guang R. Gao and Palash Desai Published in Journal of VLSI Signal Processing, Volume n.31, pp 207-229, 2002
Closely-Coupled Lifting Hardware for Efficient DWT Computation in an SoC
Improved Class Prediction in DNA Microarray Gene Expression Data by Unsupervised Reduction of the Dimensionality followed by Supervised Learning with a Perceptron
Modulation and Coding for Noncoherent Communications
Algorithmic and implementation issues in analog low power learning neural network chips
Using Planar Embedded DRAM in Memory Intensive Signal Processing Circuits: Case Studies on LDPC Decoding and Motion Estimation
A Novel Object-Oriented Software Cache for Scratchpad-Based Multi-Core Clusters
An Adaptive Feature-fusion Method for Object Matching over Non-overlapped Scenes
Application Level Resource Scheduling for Deep Learning Acceleration on MPSoC
A computational approach to VLSI analog design
System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach
Image Compression Using KLT, Wavelets and an Adaptive Mixture of Principal Components Model
Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System
Energy-Efficient Considerations on a Variable-Bitrate PCI-Express Device
6G-AUTOR: Autonomic Transceiver via Realtime On-Device Signal Analytics
Numerical integration of partial differential equations using principles of multidimensional wave digital filters
Learning from Examples with Information Theoretic Criteria
Energy-Efficient Allocation of Real-Time Applications onto Single-ISA Heterogeneous Multi-Core Processors
A million transistor systolic array graphics engine
Deep Learning-based Privacy-preserving Publishing Method for Location Big Data in Vehicular Networks
Min-max Extrapolation Scheme for Fast Estimation of 3D Potts Field Partition Functions. Application to the Joint Detection-Estimation of Brain Activity in fMRI
Towards Dictionaries of Optimal Size: A Bayesian Non Parametric Approach
ALMARVI System Solution for Image and Video Processing in Healthcare, Surveillance and Mobile Applications
Floating Point CGRA based Ultra-Low Power DSP Accelerator