yusuke1997/dblp-id-title huggingface dataset:
Design of NBTI-resilient extensible processors
An arithmetic residue to binary conversion technique
A low voltage input boost converter with novel switch driver enhancement technology for indoor solar energy harvesting
Design and implementation of low power Advanced Encryption Standard cryptocore utilizing dynamic pipelined asynchronous model
Full-Swing Gate Diffusion Input logic - Case-study of low-power CLA adder design
Aging signature properties and an efficient signature determination tool for online monitoring
Full custom MEMS design: A new method for the analysis of motion-dependent parasitics
Innovative feedback approach for high-performance low-voltage current mirror
Design of Narrow Transition Band Digital Filter: An Analytical Approach
On the quadrature accuracy of in-phase coupled quadrature LC oscillator
Novel low leakage and energy efficient dual-pullup/dual-pulldown repeater
Test and diagnosis pattern generation for distinguishing stuck-at faults and bridging faults
Learning placement order for constructive floorplanning
Fast start crystal oscillator design with negative resistance control
Design methodology for full custom CMOS microcomputers
A novel design methodology for the mixed-domain optimization of a MEMS accelerometer
Substrate noise isolation improvement in a single-well standard CMOS process
Performance analysis of 4:1 MUX APUF Architecture Implemented on Zynq 7000 SoC FPGA
Analysis of missing and additional cell defects in sequential quantum-dot cellular automata
The design of parallel square-root covariance Kalman filters using algorithm engineering
RECO-ASCON: Reconfigurable ASCON hash functions for IoT applications
On the superiority of modularity-based clustering for determining placement-relevant clusters
Scalable lumped models of integrated transformers for galvanically isolated power transfer systems
Routability-constrained multi-bit flip-flop construction for clock power reduction
Efficient false path elimination algorithms for timing verification by event graph preprocessing
An electronically controllable floating capacitor multiplier for low frequency applications
A digitally controlled adaptive LDO for power management unit in sensor node
Joint channel estimation and data detection under fading on reconfigurable fabric
Management of charge pump circuits
ADPLL design parameters determinations through noise modeling
Noise canceling LNA with gain enhancement by using double feedback
Dynamical analysis and secure communication application of parameter-controlled multiscroll attractors in memristive chaotic system
A transparent virtual channel power gating method for on-chip network routers
A current monitoring technique for I DDQ testing in digital integrated circuits
COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing
Logic gate characterization through ringoscillators
Introduction to special issue of 2019 China Semiconductor Technology International Conference (CSTIC) Symposium on Design and Automation of Circuits and Systems
A static verification approach for architectural integration of mixed-signal integrated circuits
Fine-grained data integration for high throughput and bandwidth-efficient computation on FPGAs
Electronically tunable floating DXCCDITA-based universal memelement emulator and its applications
Design and optimization of on-chip thick-plated copper-transformers for galvanic isolated DC-DC converter achieving up to 38.9% peak efficiency
An integrated DFT solution for power reduction in scan test applications by low power gating scan cell
An efficient method for gradient-aware dummy fill synthesis
Multi-agent based minimal-layer via routing algorithm for PCB design
Fault tolerant arithmetic unit using duplication and residue codes
A high-precision current-mode multifunction analog cell suitable for computational signal processing
Layout-aware design methodology for a 75 GHz power amplifier in a 55 nm SiGe technology
Multithreshold voltage low-swing/low-voltage techniques in logic gates
Optimal gate-matrix layout of CMOS functional cells
A bottom-up layout technique based on two-rectangle routing
StarPlace: A new analytic method for FPGA placement
An efficient multiple shortest augmenting paths algorithm for constructing high performance VLSI subarray
A processor framework customized for navigation computations
New memristor-less, resistor-less, two-OTA based grounded and floating meminductor emulators and their applications in chaotic oscillators
Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications
Image encryption algorithm based on the dynamic RNA computing and a new chaotic map
A broadband MVDR beamforming core for ultrasound imaging
IPRM: IP core resource multiplexing of core wrapper design for reducing test application time in DVFS-based multicore SoCs
VLSI implementation of the capacitance matrix method
Efficient construction of catastrophic patterns for VLSI reconfigurable arrays
A new current-mode computational analog block free from the body-effect
Compact and efficient structure of 8-bit S-box for lightweight cryptography
Custom NoC topology generation using Discrete Antlion Trapping Mechanism
A new low-power Dynamic-GDI full adder in CNFET technology
Synchronous control of memristive hindmarsh-rose neuron models with extreme multistability
Erratum to: "High-speed systolic architectures for finite field inversion" [Integration 38(3) (2005) 383-398]
Design, analysis and application of Non-Hamiltonian conservative chaotic system based on memristor
Reference-free power supply monitor with enhanced robustness against process and temperature variations
Grammar-based fuzz testing for microprocessor RTL design
A 2.4 mW 2.5 GHz multi-phase clock generator with duty cycle imbalance correction in 0.13 µm CMOS
Multi-schedule design space exploration: an alternative synthesis framework
Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications
High-performance and energy-efficient 64-bit incrementer/decrementer using Multiple-Output Monotonic CMOS
Direct connect device core: design and applications
Efficient and secure cryptographic systems based on addition chains: Hardware design vs. software/hardware co-design
A frequency boosting technique for cold-start charge pump units
Experimental study of terrain coverage of an autonomous chaotic mobile robot
Energy efficient adaptive clustering of on-chip power delivery systems
Improved designs of digit-by-digit decimal multiplier
Litho-NeuralODE 2.0: Improving hotspot detection accuracy with advanced data augmentation, DCT-based features, and neural ordinary differential equations
Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons
Highly robust power efficient Full Adder and Full Subtractor CiM architecture using 10T SRAM cell
FPGA-based hardware acceleration for local complexity analysis of massive genomic data
Third-order resonance networks and their application to chaos generation
Wiring in uniform grids and two-colorable maps
An integrated fault tolerance technique for combinational circuits based on implications and transistor sizing
Design of new single-bit multilayer ALU in QCA technology
Reduction of variation and leakage in wide fan-in OR Logic domino gate
Area, energy, and time assessment for a distributed TPM for distributed trust in IoT clusters
On minimum delay clustering without replication
An effective watermarking technique using BTC and SVD for image authentication and quality recovery
Graph-based STA for asynchronous controllers
The multiple-processor PPS chip of the NON-VON 3 supercomputer
Combinational static CMOS networks
A new addition scheme and fast scaling factor compensation methods for CORDIC algorithms
A novel tunable gain CMOS buffer amplifier for large resistive loads
The instruction systolic array - a parallel architecture for VLSI
The determination of the cycle length in high level synthesis
Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing
Package routability- and IR-drop-aware finger/pad planning for single chip and stacking IC designs
Transmission synchronization of multiple memristor chaotic circuits via single input controller and its application in secure communication
Low power hardware implementations for network packet processing elements
Differential receiver with 2 × VDD input signals using 1 × VDD devices
A CMOS transimpedance amplifier with broad-band and high gain based on negative Miller capacitance
Double laser-faults based PFA on cryptographic circuits with algebraic analysis
A fast symbolic SNR computation method and its Verilog-A implementation for Sigma-Delta modulator design optimization
VLSI mask optimization: From shallow to deep learning
Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator
Example of combined algorithm development and architecture design
Verifying integrity of decision diagrams
Design of quadruple precision multiplier architectures with SIMD single and double precision support
Performance optimization of VLSI interconnect layout
Time-based calibration-less read-out circuit for interfacing wide range MOX gas sensors
A reliable PUF in a dual function SRAM
Intelligent IP retrieval driven by application requirements
An embedded CDMA-receiver A design example
Enhanced FPGA implementation of Echo State Networks for chaotic time series prediction
Low power & mobile hardware accelerators for deep convolutional neural networks
Simultaneous switching noise reduction by resonant clock distribution networks
50-830 MHz noise and distortion canceling CMOS low noise amplifier
A circuit level analysis of power distribution network on a PCB layout exposed to intentional/unintentional electromagnetic threats
On-chip parallel and network-based systems
A new array architecture for signed multiplication using Gray encoded radix-2 m operands
An enhanced bottom-up algorithm for floorplan design
APoX-M: Accelerate deep point cloud analysis via adaptive graph construction
Hybrid GACO approach for optimized floorplanning in partially reconfigurable FPGAs
Testing aware dynamic mapping for path-centric network-on-chip test
Circuit power optimization using pipelining and dual-supply voltage assignment
The SPIRIT of ESPRIT
A low power Schmitt-trigger driven 10T SRAM Cell for high speed applications
Glitch-less hardware implementation of block ciphers based on an efficient glitch filter
Retiming: Theory and practice
High-throughput architecture for post-quantum DME cryptosystem
A formal framework for interfacing mixed-timing systems
Characterizing the Effectiveness of Hot Sparing on Cost and Performance-per-Watt in Application Specific SIMT
A fast VLSI solution for approximate string matching
Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling
Exact analyses for locking range in injection-locked frequency dividers
A fast pipelined multi-mode DES architecture operating in IP representation
Reducing leakage power with BTB access prediction
A PN-based approach to the high-level synthesis of digital systems
Variability in nanometer CMOS: Impact, analysis, and minimization
Dynamics analysis, FPGA realization and image encryption application of a 5D memristive exponential hyperchaotic system
A new strategy to design low power translinear based CMOS analog multiplier
High bandwidth transimpedance amplifier using FGMOS for low voltage operation
A wide-input-range boost converter with three-phase self-start and adaptive zero current detector for photovoltaic energy harvesting
An efficient construction of S-box based on the fractional-order Rabinovich-Fabrikant chaotic system
Re-configurable parallel Feed-Forward Neural Network implementation using FPGA
A transformer with high coupling coefficient and small area based on TSV
A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power
Low voltage fully differential OTA using DTMOS based self cascode transistor with slew-rate enhancement and its filter application
A methodology for low power scheduling with resources operating at multiple voltages
High-performance ternary operators for scrambling
Accelerating large-scale multi-scalar multiplication in Zk-SNARK through exploiting its multilevel parallelism
Timing-driven via placement heuristics for three-dimensional ICs
Shifts in INTEGRATION: 20 years of VLSI design
Design automation for application-specific on-chip interconnects: A survey
On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy
Allocation algorithms based on path analysis
A 1.5 ∼ 5 GHz CMOS broadband low-power high-efficiency power amplifier for wireless communications
Resource allocation applied to flexible printed circuit routing based on constrained Delaunay triangulation
A low noise instrument amplifier in 40 nm CMOS with positive feedback loop and DC servo loop for neural signal acquisition
Integration mixer: An efficient mixed neural network for memory dynamic stability analysis in high dimensional variation space
A bit-interleaved systolic architecture for a high-speed RSA system
A lifetime-aware analog circuit sizing tool
A modified Tow-Thomas G-C filter with enhanced linearity
Formal semantics for a symbolic IC design technique: Examples and applications
Concurrent error detection architectures for Gaussian normal basis multiplication over GF(2 m )
Algorithms and parallel VLSI architectures
Dynamics analysis and DSP implementation of a new four-dimensional discrete memristor hyperchaotic map
Allocation heuristics and defragmentation measures for reconfigurable systems management
Thermal modeling and analysis of 3D multi-processor chips
Design of approximate Booth multipliers based on error compensation
"X/OPEN Portability Guide" by the X/OPEN Group, from: Elsevier SciencePublishers B.V., Book Order Department, P.O. Box 211, 1000 AE Amsterdam, The Netherlands
A wideband RF receiver with extended statistical element selection based harmonic rejection calibration
Modeling computational networks by time-varying systems
Safe and efficient power management of hard real-time networks-on-chip
Full-V DD and near-threshold performance of 8T FinFET SRAM cells
A survey of DA techniques for PLD and FPGA based systems
A DRV-based bit selection method for SRAM PUF key generation and its impact on ECCs
Coprocessor design to support MPI primitives in configurable multiprocessors
Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems
Eh-DRVP: Combining placement and global routing data in a hyper-image-based DRV predictor
A stepwise-overlapped parallel simulated annealing algorithm
An approximation algorithm for the register allocation problem
An area and power efficient VLSI architecture for epileptic seizure detection using Transpose Form Retimed Delayed LMS filter and spiking neural networks
An improved common subexpression elimination method for reducing logic operators in FIR filter implementations without increasing logic depth
Testing CMOS combinational iterative logic arrays for realistic faults
New approach for digital calibration of pipelined analog to digital converters based on secant method
Statistical estimation and evaluation for communication mapping in Network-on-Chip
Design of 2.54 GHz active inductor-based LC-voltage controlled oscillator for bluetooth/WLAN applications
Design of CMOS fully differential multipath two-stage OTA with boosted slew rate and power efficiency
An NTF-enhanced incremental ΣΔ modulator using a SAR quantizer
Interval-graph-based PLA folding
Regular partitioning for synthesizing fixed-size systolic arrays
A 2.69-ppm/°C curvature-compensated BJT-based bandgap voltage reference
A novel tunable capacitively-copuled instrumentation amplifier with 14.4 nV/ √(H z) noise and 190.47 nW micro-power for ECG applications
A hierarchy preserving hierarchical bottom-up 2-layer wiring algorithm with respect to via minimization
Post-silicon power mapping techniques for integrated circuits
Power-aware hold optimization for ASIC physical synthesis
Architectural design and realization of a single-chip Viterbi decoder
An analytical investigation on the propagation delay in ring oscillators
Reliable and low power Negative Capacitance Junctionless FinFET based 6T SRAM cell
Multi-bend bus-driven floorplanning considering fixed-outline constraints
A physics-aware methodology for equivalent circuit model extraction of TSV-inductors
A chaotic PRNG tested with the heuristic Differential Evolution
A low-power half-select free 8T SRAM cell with process-induced variation resistance for voltage scaling at 32 nm technology node
Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling
High two-signal dynamic range and accurate frequency measurement for close frequency separation wideband digital receiver using adaptive gain control and adaptive thresholding
Statistical timing and power analysis of VLSI considering non-linear dependence
A comparative study on formal verification techniques to verify large integer multiplier circuits
QNoC asynchronous router
AI-enabled image processing approach for efficient clustering and identification of hardware Trojans
Comments on "New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application"
Run-time support for heterogeneous multitasking on reconfigurable SoCs
A microprogrammable processor using single poly EPROM
Partitioning and ordering of CMOS circuits for switch level analysis
Region definition and ordering for macrocells with unconstrained placement
Arduino-controlled HP memristor emulator for memristor circuit applications
PLA implementation of a differential predictive coder for digital television signals
An ultra-wideband 6-14 GHz frequency modulated continuous wave primary radar with 3 cm range resolution
Systematic synthesis of approximate adders and multipliers with accurate error calculations
Novel fault tolerance topology using corvus seek algorithm for application specific NoC
A study of analog decision feedback equalization for ADC-Based serial link receivers
High-level synthesis techniques for functional test pattern execution1
Nadam optimized deep self-guided clustering dual-domain attention network security framework for reliable detection of malicious modules in VLSI circuits
An energy-efficient analog circuit for detecting QRS complexes from ECG signal
An evolutionary constraint satisfaction solution for over the cell channel routing
CL-CPA: A hybrid carry-lookahead/carry-propagate adder for low-power or high-performance operation mode
Using virtual prototypes and metamorphic testing to verify the hardware/software-stack of embedded graphics libraries
Low delay non-binary error correction codes based on Orthogonal Latin Squares
A new approach to analysis of residue probability density function in pipelined ADCs
An optimal channel coding scheme for high-speed data communication
High level synthesis strategies for ultra fast and low latency matrix inversion implementation for massive MIMO processing
Machine learning classification algorithm for VLSI test cost reduction
HERMES: an infrastructure for low area overhead packet-switching networks on chip
Multiplierless implementation of 2-D FIR filters
Dynamical analysis, hardware implementation, and image encryption application of new 4D discrete hyperchaotic maps based on parallel and cascade memristors
Functional validation of highly synthesizable voltage comparator on FPGA
Loop aware CFG matching strategy for accurate performance estimation in IR-level native simulation
Electronically tunable single FTFNTA-based universal memelement emulator using only grounded passive elements
Graph neural network based cell library characterization method for fast design technology co-optimization
Optimization of fourth order noise transfer function using PSO algorithm for delta sigma modulator
Detection probabilities of interconnect breaks: an analysis
Contention free delayed keeper for high density large signal sensing memory compiler
Optimized matrix ordering of sparse linear solver using a few-shot model for circuit simulation
A MMIC power amplifier in GaN on Si technology for next generation Q band high throughput satellite systems
Dual split-three segment capacitor array Design Based Successive approximation ADC for Io-T ecosystem
Soft fault diagnosis in analog electronic circuits using supervised machine learning
A neuromorphic hardware architecture based on TTFS coding with temporal quantization for spiking neural networks
Semi-modularity and testability of speed-independent circuits
Compiler compatible 5.66 Mb/mm 2 8T 1R1W register file in 14 nm FinFET technology
A novel on-chip linear and switching mixed regulation against power analysis attacks
An O(n) algorithm for width determination of power/ground routes for VLSI circuits
Discrete relaxation method for contact layer decomposition of DSA with triple patterning
A fully integrated VLSI architecture using chaotic PWM for RF transmitter design with electromagnetic interference reduction
Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergence
A heuristic for constructing a rectilinear Steiner tree by reusing routing resources over obstacles
A high reliability under-voltage lock out circuit for power driver IC
Implications of accelerated self-healing as a key design knob for cross-layer resilience
Maximizing pin alignment by pin permutations
A Pulse Compression procedure for power inductors modeling up to moderate non-linearity
SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage
Optimizing detailed-routability for 3D global routing through dynamic resource model and routability-aware cost scheme
Digital implementation of a virtual insect trained by spike-timing dependent plasticity
Scheduling algorithms for reservoir- and mixer-aware sample preparation with microfluidic biochips
DULBC: A dynamic ultra-lightweight block cipher with high-throughput
A quantum-based building block for designing a nanoscale full adder circuit with power analysis
Scheduling with multiple voltages
High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes
VLSI architecture design and implementation of 5/3 and 9/7 lifting Discrete Wavelet Transform
Predictive test strategy for CMOS RF mixers
Design of highly reliable radiation hardened 10T SRAM cell for low voltage applications
Improving power analysis attack resistance using intrinsic noise in 3D ICs
Defense-in-depth: A recipe for logic locking to prevail
Agile-AES: Implementation of configurable AES primitive with agile design approach
Statistical static timing analysis: A survey
Test-set partitioning for multi-weighted random LFSRs
A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime
Design of hyperchaotic system based on multi-scroll and its encryption algorithm in color image
On optimal ordering of signals in parallel wire bundles
Scheduling under resource constraints and module assignment
Ultrafast single phase dynamic CMOS PLA
Architectures for language recognition
An energy efficient synthesis flow for application specific SoC design
Efficient architecture and hardware implementation of hybrid fuzzy-Kalman filter for workload prediction
New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application
Solution of PDEs-electrically coupled systems with electrical analogy
DCDRO:A true random number generator based on dynamically configurable dual-output ring oscillator
An algorithm for polygon conversion to boxes for VLSI layouts
Stitch aware detailed placement for multiple E-beam lithography
Fast clock scheduling and an application to clock tree synthesis
Design and implementation of SVM OTPC searching based on Shared Dot Product Matrix
An energy-efficient, high-precision SFP LPFIR filter engine for digital hearing aids
AutoNFT: Architecture synthesis for hardware DFT of length-of-coprime-number products