yusuke1997/dblp-id-title huggingface dataset:
Statistical analysis of large on-chip power grid networks by variational reduction scheme
A memristive neural network with features of asymmetric coexisting attractors and large-scale amplitude control
Dynamical analysis and FPGA implementation of a memristive non-Hamiltonian conservative hyperchaotic system with extreme multistability
Accuracy and fidelity of fast net length estimates
Full-chip wire-oriented back-end-of-line TDDB hotspot detection and lifetime analysis
Minimization of free BDDs
Resource-constrained link insertion for delay reduction
Corrigendum to "Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm" [Integr. VLSI J. 58. (2017) 74-81]
High-performance unified modular multiplication algorithm and hardware architecture over G(2m)
An adaptive digital predistortion for compensating nonlinear distortions in RF power amplifier with memory effects
Floorplanning with abutment constraints based on corner block list
Modeling of CMOS transistors from 0.18 μm process by artificial neural network
Energy efficient hybrid adder architecture
Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs
Reducing test application time, test data volume and test power through Virtual Chain Partition
A novel architecture of high performance fully differential two stage RFC OTA designed using DFVF and hybrid cascode compensation techniques
An improved heuristic technique for nearest neighbor realization of quantum circuits in 2D architecture
A low power high area-efficiency NMOS LDO with fast adaptive bias
High-performance hardware architecture of a robust block-cipher algorithm based on different chaotic maps and DNA sequence encoding
Analysis and architecture design of scalable fractional motion estimation for H.264 encoding
Robust low leakage controlled keeper by current-comparison domino for wide fan-in gates
FPGA routing congestion prediction combining DAGNN and GCN
Low-power and high-speed SRAM cells for double-node-upset recovery
Localisation of malicious nets in integrated circuits using unsupervised methodologies
An area and power efficient VLSI architecture for ECG feature extraction for wearable IoT healthcare applications
A robust radiation resistant SRAM cell for space and military applications
Trading off circuit lines and gate costs in the synthesis of reversible logic
A PVT tolerant low power wide tuning range differential voltage controlled oscillator design in 90 nm CMOS technology
A Fast FIR filtering technique for multirate filters
River routing and density minimization for channels with interchangeable terminals
An efficient XOR-free architecture for successive cancellation polar decoding
Design of a high precision digital interface circuit for capacitive MEMS accelerometers with floating point ADC
Beware the isochronic fork
Bounds, designs and layouts for multi-terminal FPIC architectures
Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits
On the models for designing VLSI asynchronous digital systems
ESegNet-ILT: An end-to-end mask optimization method in VLSI design flow based on enhanced SegNet
Efficient and low-cost approximate multipliers for image processing applications
Efficient design of magnitude and 2's complement comparators
Neuro-inspired hardware solutions for high-performance computing: A TiO2-based nano-synaptic device approach with backpropagation
Multi-objective design space exploration for system partitioning of FPGA-based Dynamic Partially Reconfigurable Systems
RESET: A real-time scheduler for energy and temperature aware heterogeneous multi-core systems
Tripartite modular multiplication
Permutation and phase independent Boolean comparison
MEDA based Biochips: Technology, application and design automation issues - A brief review
Low power post quantum cryptography on reconfigurable devices for cyber physical system in IoT
There is a limit to everything: Automating AMS operating condition check generation on system-level
A PVT aware differential delay circuit and its performance variation due to power supply noise
Co-design based FPGA implementation of an efficient new speech hyperchaotic cryptosystem in the transform domain
Identifying malicious modules using deformable graph convolutional network-based security framework for reliable VLSI circuit protection
A novel equivalent circuit model for split ring resonator with an application of low phase noise reference oscillator
Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption
On-line testing for VLSI: state of the art and trends
A SPAD-based random number generator pixel based on the arrival time of photons
A modem in CMOS technology for data communication on the low-voltage power line
Reliability-aware application mapping onto mesh based Network-on-Chip
Micro-display backplane power reduction techniques: Column segmentation and row charge sharing
Run-time demand estimation and modulation of on-chip decaps at system level for leakage power reduction in multicore chips
A novel filter-bank architecture of 2D-FIR symmetry filters using LUT based multipliers
An on-chip frequency programmable test clock generation and application method for small delay defect detection
Coexistence of infinite attractors in a fractional-order chaotic system with two nonlinear functions and its DSP implementation
The synthesis method of logic circuits based on the iMemComp gates
PCoSA: A product error correction code for use in memory devices targeting space applications
Design of mixed-signal systems for testability
A three-stage single-miller CMOS OTA with no lower load capacitor limit
Routing in and around a rectangle using the overlap model
Bit-serial architecture for rank order and stack filters
Synthesis of ASIPs for DSP algorithms
Systolic-based parallel architecture for the longest common subsequences problem
OKFDD minimization by genetic algorithms with application to circuit design
Experimental characterization of dedicated front-end electronics for piezoelectric tactile sensing arrays
Low-power current-reused RF front-end based on optimized transformers topology
An ant colony based mapping of quantum circuits to nearest neighbor architectures
High-performance multiply-accumulate unit by integrating binary carry select adder and counter-based modular wallace tree multiplier for embedding system
High throughput true random number generator based on dynamically superimposed hybrid entropy sources
OTA-C signal delay compensation circuit for transimpedance-mode audio signal processing systems
Design of an ultra-wideband LNA using transformer matching method
Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections
A security oriented transient-noise simulation methodology: Evaluation of intrinsic physical noise of cryptographic designs
Hyperchaotic fractional Grassi-Miller map and its hardware implementation
A hardware accelerator for two-dimensional image analysis
A 158 nw, 2.877 ppm/°C resistorless bandgap reference circuit
Hardware SLE solvers: Efficient building blocks for cryptographic and cryptanalyticapplications
Misalignment-aware energy modeling of narrow buses for data encoding schemes
An accelerated modulus-based matrix splitting iteration method for mixed-size cell circuits legalization
Fast search algorithms for layout permutation problems
An assertion graph based abstraction algorithm in GSTE and Its application
Modeling memory effects in RF power amplifiers applied to a digital pre-distortion algorithm and emulated on a DSP-FPGA board
An efficient hardware architecture for detection of vowel-like regions in speech signal
LFSR multipliers over GF(2 m ) defined by all-one polynomial
A 5.8 GHz digitally configurable DSRC RF-SoC transmitter for China ETC systems
Reliability based hardware Trojan design using physics-based electromigration models
Corrigendum to"Approximate error detection-correction for efficient adaptive voltage Over-Scaling"[Integration 63 (2018) 220-231]
Electromigration assessment for power grid networks considering temperature and thermal stress effects
Corrigendum to "WDP-BNN: Efficient wafer defect pattern classification via binarized neural network" [Integration 85 (2022) 76-86]
A language for designer controlled behavioral synthesis
Research on digital predistortion technique of harmonic cancellation based on volterra series
ASLIC: A low power CMOS analog circuit design automation
A fast and high-performance global router with enhanced congestion control
A gate-delay model focusing on current fluctuation over wide range of process-voltage-temperature variations
New theoretical results on quadratic placement
Synchronization of mutual coupled fractional order one-sided lipschitz systems
A new realization scheme for dynamic PFSCL style
High-speed redundant reciprocal approximation
A Fully RNS based ECC Processor
A low offset low power CMOS dynamic comparator for analog to digital converters
Protection against soft errors in the space environment: A finite impulse response (FIR) filter case study
An ultra-wideband low noise amplifier with cascaded flipped-active inductor for cognitive radio applications
Convex optimization of random dynamic voltage and frequency scaling against power attacks
Introduction to the special issue on SMACD 2015
A novel area efficient on-chip RO-Sensor for recycled IC detection
Synthesis and self-test of random logic control units
Multi-harvesting smart solution for self-powered wearable objects: System-level model and transistor-level design
Experimental verification of the multi-scroll chaotic attractors synchronization in PWL arbitrary-order systems using direct coupling and passivity-based control
On the convex formulation of area for slicing floorplans
A robust 12T SRAM cell with improved write margin for ultra-low power applications in 40 nm CMOS
A high performance hardware architecture for portable, low-power retinal vessel segmentation
A graph theoretic approach to feed-through pin assignment
FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping
Adaptive prairie dog optimization based variable length conditional counter for designing multiplier
CMOS single-ended-to-differential low-noise amplifier
Test data compression using alternating variable run-length code
Design of electronic system for linearization of sinusoidal characteristics of cascaded tunneling magneto-resistance sensor
Test patterns reordering method based on Gamma distribution
Edge effects on the TSV array capacitances and their performance influence
An 8T SRAM cell for high-speed sub-threshold operation with dynamic body biasing
A new model for computation of probabilistic testability in combinational circuits
A pseudo resistor with temperature self-adaptive scheme
Challenges and directions for testing IC
FTPUF:Feedback structure of TERO PUF for high reliability
Hot-spot aware thermoelectric array based cooling for multicore processors
Fast electromigration stress analysis using Low-Rank Balanced Truncation for general interconnect and power grid structures
Power-gating-aware scheduling with effective hardware resources optimization
Electronically tunable MOSFET-C only meminductor emulator and its application
Synthesis of P-circuits for logic restructuring
Minimum fault covering in reconfigurable arrays
A VLSI architecture for RNS with MI adders
Comparative study of planar stacked integrated transformers for MMICs
A programmable inductive position sensor interface circuit
Low power dynamic logic circuit design using a pseudo dynamic buffer
Contactless Heterogeneous 3-D ICs for Smart Sensing Systems
An area-time efficient NMOS adder
An Enhanced Memetic Algorithm using SKB tree representation for fixed-outline and temperature driven non-slicing floorplanning
An area efficient LDPC decoder using a reduced complexity min-sum algorithm
A new approach in feature interaction testing
Clock domain crossing (CDC) in 3D-SICs: Semi QDI asynchronous vs loosely synchronous
ObfusX: Routing obfuscation with explanatory analysis of a machine learning attack
A dynamic specification to automatically debug and correct various divider circuits
Simulink ® -based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation
Application of the object-oriented principles for hardware and embedded system design
Review: Application and development of machine learning in semiconductor manufacturing for automated wafer map pattern recognition and classification
Study of the dynamical behavior of an Ikeda-based map with a discrete memristor
Crosstalk-aware multi-bit flip-flop generation for power optimization
A new approach for the design of linear systolic arrays for computing third-order cumulants
Solving modern mixed-size placement instances
Weighted median filters: An analog implementation
CMOS event-driven tactile sensor circuit
Peel-the-box: a concept of switch-box routing and tractable problems
Effects of aging and compensation mechanisms in ordering based RO-PUFs
On VLSI layouts of the star graph and related networks
A very stable diode-based physically unclonable constant
Technology mapping for low power in logic synthesis
Applications of computational geometry to VLSI layout pattern design
Low-power and high-speed design of a versatile bit-serial multiplier in finite fields GF(2 m )
Highly stable, low power FinFET SRAM cells with exploiting dynamic back-gate biasing
Fluid-control codesign for paper-based digital biochips using volumetric memory networks: A predictive modelling approach
Analog and mixed-signal IC design and design methodologies
A CMOS temperature-independent current reference optimized for mixed-signal applications
Test generation and fault detection for VLSI PPL circuits
FSM decomposition for pipelined data
Design of a low power LNA circuit with noise canceling approach in 90 nm CMOS process
A novel current-mode low-power adjustable wide input range four-quadrant analog multiplier
Placement legalization for heterogeneous cells of non-integer multiple-heights
Dynamics analysis and application of multi-stable Hopfield neural networks under pulsed current stimulation
Theoretical properties of LFSRs for built-in self test
An 8 bits, RF UHF-Band DAC based on interleaved bandpass delta sigma modulator assisted by background digital calibration
Exploring the dynamics of a multistable general model of discrete memristor-based map featuring an exponentially varying memristance
An algorithm for finding a non-trivial lower bound for channel routing1
On minimizing memory in systolic arrays for the dynamic time warping algorithm
A novel low-resource consumption and high-speed hardware implementation of HOG feature extraction on FPGA for human detection
Analysis and comparison of Direct Digital Frequency Synthesizers implemented on FPGA
A high-accuracy approximate adder with correct sign calculation
A novel design method for discrete time chaos based true random number generators
A simulated approach to evaluate side-channel attack countermeasures for the Advanced Encryption Standard
Implementation of a fully integrated memristive Chua's chaotic circuit with a voltage-controlled oscillator
Super class AB-AB bulk-driven folded cascode OTA
Look-ahead mapping of Boolean functions in memristive crossbar array
A 1-V RF-CMOS LNA design utilizing the technique of capacitive feedback matching network
An energy-efficient image filtering interpolation algorithm using domain-specific dynamic reconfigurable array processor
A fast transient response current-feedback low-dropout regulator with dynamic current-enhancement technique
Design of efficient architectures for 1-D and 2-D DLMS adaptive filters
Gate all around carbon nanotube field effect transistor espoused discrepancy cascode pass transistor adiabatic logic for ultra-low power application
High gain amplifier with feedforward compensation based on quasi-floating gate transistors
Phase noise analysis of proposed PFD and CP switching circuit and its advantages over various PFD/CP switching circuits in phase-locked loops
SET-detection low complexity burst error correction codes for SRAM protection
On-board processing for autonomous drone racing: An overview
A Survey of FIR Filter Design Techniques: Low-complexity, Narrow Transition-band and Variable Bandwidth
Stumped nature hyperjerk system with fractional order and exponential nonlinearity: Analog simulation, bifurcation analysis and cryptographic applications
A standard cell phase locked loop design, analysis and high-level synthesis tool (CellPLL)
A novel one-equilibrium memristive chaotic system with multi-parameter amplitude modulation and large-scale offset boosting
A 0.6V 44.6 ppm/ºC subthreshold CMOS voltage reference with wide temperature range and inherent leakage compensation
Timing analysis with compact variation-aware standard cell models
Frame buffer-less stream processor for accurate real-time interest point detection
A single-chip adaptive delta modulator with optimum performance
Towards generic charge-pump phase-locked loop, jitter estimation techniques using indirect on chip methods
To Booth or not to Booth
Chaos-based approaches to data security: Analysis of incommensurate fractional-order Arneodo chaotic system and engineering application on a microcomputer
VLSI design of an FFT processor network
An area efficient 64 point Radix-42 MDC FFT architecture for OFDM applications
Automatic determination of signal flow through MOS transistor networks
FPGA enabled ECG signal reconstruction based on an enhanced orthogonal matching pursuit algorithm
A Sigma-Delta ADC design automation tool with embedded performance estimator
Hardware efficient approximate sigmoid activation function for classifying features around zero
Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder
A non-degenerate n-dimensional integer domain chaotic map model with application to PRNG
Research on modeling and prediction method of conducted electromagnetic interference for electric vehicle on-board charging system
SERA: statistical error rate analysis for profit-oriented performance binning of resilient circuits
Analysis of the impact of interferers on VCO-based continuous time delta-sigma modulators
Low space complexity CRT-based bit-parallel GF (2 n ) polynomial basis multipliers for irreducible trinomials
Design and implementation of multi-mode routers for large-scale inter-core networks
FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems
Efficient fracturing of all angle shaped VLSI mask pattern data
A VLSI model for residue number system architectures
Analog circuit optimization system based on hybrid evolutionary algorithms
Cryptanalysis of nonlinear confusion component based encryption algorithm
MASH ΣΔ modulators with a noise-shaped two-step ADC in the second stage
Synthesis of optical circuits using binary decision diagrams
Fast transient current-steering CMOS LDO regulator based on current feedback amplifier
A low power noise tolerant wide fan-in OR logic domino gate
A stochastic evolution algorithm based 2D VLSI global router
High-performance power spectral/bispectral estimator for biomedical signal processing applications using novel memory-based FFT processor
Leveraging asynchronous quantum secretary bird Generative propagation adversarial attention networks for FIR filter design in ECG applications
An energy and area efficient 4: 2 compressor based on FinFETs
Building discrete maps with memristor and multiple nonlinear terms
Chosen ciphertext correlation power analysis on Kyber
A thermal-sensitive design of a 3D torus-based optical NoC architecture
Efficient lattice-based Mordell elliptic curve S-box for secure lightweight cryptography
OP-Fibo: An efficient Forbidden Pattern Free CAC design
Hardware Trojan detection based on graph neural networks
A new hardware Trojan detection technique using deep convolutional neural network
Verification of physical designs using an integrated reverse engineering flow for nanoscale technologies
A tool for the automatic generation and analysis of regular analog layout modules
A comprehensive analysis on the resilience of adiabatic logic families against transient faults
DCNN search and accelerator co-design: Improve the adaptability between NAS frameworks and embedded platforms
A highly-linear, sub-mW LNA at 2.4 GHz in 40 nm CMOS process
An algorithmic approach to construct the library of universal logic gates beyond NAND and NOR
P2R2: Parallel Pseudo-Round-Robin arbiter for high performance NoCs
A complete dynamic power estimation model for data-paths in FPGA DSP designs
Hierarchical constraint transformation based on genetic optimization for analog system synthesis
A Novel four - Wing chaotic system with multiple attractors based on hyperbolic sine: Application to image encryption*
Analog circuit design space description based on ordered clustering of feature uniqueness and similarity
A PUS based nets weighting mechanism for power, hold, and setup timing optimization
Optimization of quantum circuit mapping using gate transformation and commutation
Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping
Systolic product-sum circuit for GF ((2 2 ) m ) using neuron MOSFETs
Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures
Testing and fault tolerance techniques for carbon nanotube-based FPGAs
Design of a new compact multiplier-less memtranstor emulator and its application in neuromorphic and chaos generation
Double-precision Dual Mode Logic carry-save multiplier
Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits
Single phase three-layer channel routing algorithms
Debugging reversible circuits
A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load
Low-cost compression architecture based on extended DCT algorithm
Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources
RF calibration of on-chip DfT chain by DC stimuli and statistical multivariate regression technique
An enhanced key expansion module based on 2D hyper chaotic map and Galois field
Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs
SPYDER: a serial/parallel goal-directed router
Hardware implementation of a spatio-temporal average filter for real-time denoising of fluoroscopic images
Optimal design of mixed dielectric coaxial-annular TSV using GWO algorithm based on artificial neural network
A K-band low-noise bipolar class-C VCO for 5G backhaul systems in 55 nm BiCMOS technology
Shaping data for application performance and energy optimization in dynamic data view framework
An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2 m )
A well conditioned checksum scheme for algorithmic fault tolerance
Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers
LQNTL: Low-overhead quadruple-node-upset self-recovery latch based on triple-mode redundancy
rel-SLIFMEM: Design and analysis of a reliability-aware neuromorphic system
A metal - metal matrix cell generator for multi-level metal MOS technology
Domino logic designs for high-performance and leakage-tolerant applications
Complete automatic Q tuning system on a chip
An approach to test synthesis from higher level
A scalable LDPC decoder ASIC architecture with bit-serial message exchange
VLSI computations: from physics to algorithms
A 20-Gb/s wideband AGC amplifier with 26-dB dynamic range in 0.18-μm SiGe BiCMOS
"Introduction to nMOS and cMOS VLSI Systems Design" by Amar Mukherjee, from: Prentice-Hall, Englewood Cliffs, NJ 07632, U.S.A.
AutoTEA: An Automated Transistor-level Efficient and Accurate design tool for FPGA design
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement
A function-independent self-test for large programmable logic arrays
Design of Flash analog-to-digital converter based on MoS2 FET