yusuke1997/dblp-id-title huggingface dataset:
Register Expansion, SemaCall, and SideData: Three Low-Overhead Dynamic Watermarks Suitable for Automation in LLVM
Intrusion Survivability for Commodity Operating Systems
The Economics of Ransomware Attacks on Integrated Supply Chain Networks
Lessons Learned from Automated Sharing of Intrusion Detection Alerts: The Case of the SABU Platform
Threat-Based Simulation of Data Exfiltration Toward Mitigating Multiple Ransomware Extortions
Methods for Host-based Intrusion Detection with Deep Learning
Exposing Vulnerabilities of Deepfake Detection Systems with Robust Attacks
ADAPT: Adaptive Camouflage Based Deception Orchestration For Trapping Advanced Persistent Threats
Blockchain Vulnerabilities in Practice
Vulnerability Forecasting: Theory and Practice
Fuzzing and Symbolic Execution for Multipath Malware Tracing: Bridging Theory and Practice via Survey and Experiments
GALU: A Genetic Algorithm Framework for Logic Unlocking
InviSeal: A Stealthy Dynamic Analysis Framework for Android Systems
A Self-adaptive and Secure Approach to Share Network Trace Data
Breaking Captcha System with Minimal Exertion through Deep Learning: Real-time Risk Assessment on Indian Government Websites
Building Machine Learning-based Threat Hunting System from Scratch
IronNetInjector: Weaponizing .NET Dynamic Language Runtime Engines
Game Theory based Cyber-Insurance to Cover Potential Loss from Mobile Malware Exploitation
Building a Better SOC: Towards the Ontology for Security Operations Center Assistance and Replication (OSCAR)
Unsupervised Learning Techniques for Malware Characterization: Understanding Certain DNS-based DDoS Attacks
Assessing a Decision Support Tool for SOC Analysts
Improving Automated Labeling for ATT&CK Tactics in Malware Threat Reports
Desire: Leveraging the Best of Centralized and Decentralized Contact Tracing Systems
Introduction to the ACSAC'22 Special Issue
Machine Learning (In) Security: A Stream of Problems
SCA-Pitaya: A Practical and Affordable Side-Channel Attack Setup for Power Leakage-Based Evaluations
Automated ATT&CK Technique Chaining
Automated Model Learning for Accurate Detection of Malicious Digital Documents
Handling Internet Activism During the Russian Invasion of Ukraine: A Campus Network Perspective
Understanding How National CSIRTs Evaluate Cyber Incident Response Tools and Data: Findings from Focus Group Discussions
Metrics Matter - Source Camera Forensics for Large-Scale Investigations
Will You Trust This TLS Certificate?: Perceptions of People Working in IT (Extended Version)
ATFuzzer: Dynamic Analysis Framework of AT Interface for Android Smartphones
CuMONITOR: Continuous Monitoring of Microarchitecture for Software Task Identification and Classification
Sensor Identification via Acoustic Physically Unclonable Function
Advanced Persistent Threat Attack Detection Systems: A Review of Approaches, Challenges, and Trends
Introduction to the IMF 2024 Special Issue
COVID-19 Contact Tracing and Privacy: A Longitudinal Study of Public Opinion
Classifying Co-resident Computer Programs Using Information Revealed by Resource Contention
The County Fair Cyber Loss Distribution: Drawing Inferences from Insurance Prices
Introduction to the Special Issue on the Digital Threats of Hardware Security
Evasion and Countermeasures Techniques to Detect Dynamic Binary Instrumentation Frameworks
Large-scale Debloating of Binary Shared Libraries
The Ecosystem of Detection and Blocklisting of Domain Generation
Enhancements to Threat, Vulnerability, and Mitigation Knowledge for Cyber Analytics, Hunting, and Simulations
Evaluating Tamper Resistance of Digital Forensic Artifacts during Event Reconstruction
ANDROIDGYNY: Reviewing Clustering Techniques for Android Malware Family Classification
Threat Intelligence Quality Dimensions for Research and Practice
The Intelligent Process Lifecycle of Active Cyber Defenders
Introduction to the ACSAC'20 Special Issue
Insiders Dissected: New Foundations and a Systematisation of the Research on Insiders
The Evolving Menace of Ransomware: A Comparative Analysis of Pre-pandemic and Mid-pandemic Attacks
Introduction to the ACSAC'19 Special Issue - Part 1
Validating a Set of Candidate Criteria for Evaluating Software Tools and Data Sources for National CSIRTs' Cyber Incident Responses
General-purpose Unsupervised Cyber Anomaly Detection via Non-negative Tensor Factorization
Introduction to the Special Issue on Ransomware
APTHunter: Detecting Advanced Persistent Threats in Early Stages
VERICONDOR: End-to-End Verifiable Condorcet Voting with support for Strict Preference and Indifference
Digital Threats: Research and Practice Inaugural Issue Editorial
Analyzing the Direct and Transitive Impact of Vulnerabilities onto Different Artifact Repositories
Old Wine in New Wineskins: How Remnant Data Challenges Forensics and the Law
SwissCovid in the Perspective of Its Goals
Dead Man's PLC: Towards Viable Cyber Extortion for Operational Technology
Toward Automated Factchecking: Developing an Annotation Schema and Benchmark for Consistent Automated Claim Detection
Cut-and-Mouse and Ghost Control: Exploiting Antivirus Software with Synthesized Inputs
LGuard: Securing Enterprise-IoT Systems against Serial-Based Attacks via Proprietary Communication Buses
Analysis and Correlation of Visual Evidence in Campaigns of Malicious Office Documents
Securely Sharing Randomized Code That Flies
Fight Hardware with Hardware: Systemwide Detection and Mitigation of Side-channel Attacks Using Performance Counters
security.txt Revisited: Analysis of Prevalence and Conformity in 2022
Demonstrating Spoofability of an Originating Number when Sending an SMS using SMPP
Ransomware as a Predator: Modelling the Systemic Risk to Prey
Special Issue on Offensive and Defensive Techniques in the Context of Man-At-The-End (MATE) Attacks
Trace of the Times: Rootkit Detection through Temporal Anomalies in Kernel Activity
From ML to LLM: Evaluating the Robustness of Phishing Web Page Detection Models against Adversarial Attacks
CDNs' Dark Side: Security Problems in CDN-to-Origin Connections
Fingerpointing False Positives: How to Better Integrate Continuous Improvement into Security Monitoring
Introduction to the Special Issue on Challenges and Trends in Malware Analysis
Zero Trust Architecture: Risk Discussion
CVSS: Ubiquitous and Broken
Scrybe: A Secure Audit Trail for Clinical Trial Data Fusion
A Novel Hybrid Algorithm for Fake News Detection
Anonymization of Network Traces Data through Condensation-based Differential Privacy
Cookies from the Past: Timing Server-side Request Processing Code for History Sniffing
Evaluating Dynamic Binary Instrumentation Systems for Conspicuous Features and Artifacts
Introduction to the FIRST Special Issue
Thinking Unveiled: An Inference and Correlation Model to Attack EEG Biometrics
Premadoma: An Operational Solution to Prevent Malicious Domain Name Registrations in the .eu TLD
Introduction to the Special Issue on Insider Threats
Requirements for Playbook-Assisted Cyber Incident Response, Reporting and Automation
On Secure E-Voting over Blockchain
A Survey on Network Attack Surface Mapping
PDoT: Private DNS-over-TLS with TEE Support
TTPXHunter: Actionable Threat Intelligence Extraction as TTPs from Finished Cyber Threat Reports
HiPeR - Early Detection of a Ransomware Attack using Hardware Performance Counters
FedNIDS: A Federated Learning Framework for Packet-Based Network Intrusion Detection System
Industrial Experience of Finding Cryptographic Vulnerabilities in Large-scale Codebases
Unveiling Cyber Threat Actors: A Hybrid Deep Learning Approach for Behavior-Based Attribution
Investigating Sharing of Cyber Threat Intelligence and Proposing A New Data Model for Enabling Automation in Knowledge Representation and Exchange
Vulnerability Exposure Driven Intelligence in Smart, Circular Cities
rpkiller: Threat Analysis of the BGP Resource Public Key Infrastructure
Introduction to the Special Issue on Information Sharing
OATs'inside : Retrieving Object Behaviors From Native-based Obfuscated Android Applications
Introduction to the IMF 2025 Special Issue
Limits to the Forensic Analysis of Container Applications in Cloud Environments
Field Note on CVE-2019-11510: Pulse Connect Secure SSL-VPN in the Netherlands
Goosewolf: An Embedded Intrusion Detection System for Advanced Programmable Logic Controllers
Introduction to the Special Issue on the 2020 FIRST Conference
Web Application Security: A Pragmatic Exposé
From IaC to IoC - Using Infrastructure as Code (IaC) to Generate Synthetic Datasets of Compromised (IoC) Linux Systems for Use in Digital Forensics
On Collaboration and Automation in the Context of Threat Detection and Response with Privacy-Preserving Features
Results From Invoking Artificial Neural Networks to Measure Insider Threat Detection & Mitigation
Emerging Cybersecurity Capability Gaps in the Industrial Internet of Things: Overview and Research Agenda
Active and Passive Collection of SSH Key Material for Cyber Threat Intelligence
Exploit Prediction Scoring System (EPSS)
The Gamification of Online Romance Fraud through Offenders' Cards
ARIMA Supplemented Security Metrics for Quality Assurance and Situational Awareness
Introduction to the Special Issue on Vulnerabilities
Beyond the Hype: An Evaluation of Commercially Available Machine Learning-based Malware Detectors
The Role of Machine Learning in Cybersecurity
A Machine Learning and Optimization Framework for Efficient Alert Management in a Cybersecurity Operations Center
User Perceptions of Security and Privacy for Group Chat
Back and Forth - On Automatic Exposure of Origin and Dissemination of Files on Windows
Dark Web Marketplaces: Data for Collaborative Threat Intelligence
Field Note on IoT Security: Novel JIT Security for Large-Scale Heterogeneous IoT Deployments
DiskForge: Timestomping on Disk Images for Educational Benefit
Single and Hybrid-Ensemble Learning-Based Phishing Website Detection: Examining Impacts of Varied Nature Datasets and Informative Feature Selection Technique
Perceptions of Human and Machine-Generated Articles
Risk-aware Fine-grained Access Control in Cyber-physical Contexts
Advanced Persistent Threats (APT) Attribution Using Deep Reinforcement Learning
Review of Human Decision-making during Computer Security Incident Analysis
Aegis+: A Context-aware Platform-independent Security Framework for Smart Home Systems
Human Factors in Information Security: A Quantitative Study with Technical Solutions to Prevent Social Engineering Attacks
Causal Inconsistencies Are Normal in Windows Memory Dumps (Too)
Know Thy Ransomware Response: A Detailed Framework for Devising Effective Ransomware Response Strategies
Toward a Better Understanding of "Cybersecurity"
Privacy-aware Character Pattern Matching over Outsourced Encrypted Data
Introduction: On the Nature of Situational Awareness
Introduction to the Special Issue on Incident Response
Strategies for Practical Hybrid Attack Graph Generation and Analysis
Detection of Advanced Web Bots by Combining Web Logs with Mouse Behavioural Biometrics
Introduction to the Special Issue on Memory-Based Malware and Other Unconventional Threats
"Unless One Does the Research, It May Seem as Just a Useless Battery-consuming App" - Field Notes on COVID-19 Contact Tracing Applications
Evading Anti-Phishing Models: A Field Note Documenting an Experience in the Machine Learning Security Evasion Competition 2022
Asm2Seq: Explainable Assembly Code Functional Summary Generation for Reverse Engineering and Vulnerability Analysis
Modeling Realistic Adversarial Attacks against Network Intrusion Detection Systems
Database Traffic Interception for Graybox Detection of Stored and Context-sensitive XSS
How Good is Good Enough? Quantifying the Impact of Benefits, Accuracy, and Privacy on Willingness to Adopt COVID-19 Decision Aids
Deception in Network Defences Using Unpredictability
Dynamic Detection of Mobile Malware Using Smartphone Data and Machine Learning
Unveiling the Threat: Investigating Distributed and Centralized Backdoor Attacks in Federated Graph Neural Networks
Towards Attack Detection in Multimodal Cyber-Physical Systems with Sticky HDP-HMM based Time Series Analysis
Identifying Real-world Credible Experts in the Financial Domain
Code Polymorphism Meets Code Encryption: Confidentiality and Side-channel Protection of Software Components
COVID-19 Vaccination Certificates in the Darkweb
Towards a Greater Understanding of Coordinated Vulnerability Disclosure Policy Documents
BUDS+: Better Privacy with Converger and Noisy Shuffling
Field Note on Doing Digital Rights: Central and Southeast Europe Monitoring Project
"Off-Label" Use of DNS
Using Dirichlet Marked Hawkes Processes for Insider Threat Detection
Built-in self test design of power switch with clock-gated charge/discharge transistor
Survey on memory management techniques in heterogeneous computing systems
Design feasibility study for a 500 Gbits/s advanced encryption standard cipher/decipher engine
Finite state machine-based fault tolerance technique with enhanced area and power of synthesised sequential circuits
Interconnect and communication synthesis for distributed register-file microarchitecture
Energy efficient VLSI architecture of real-valued serial pipelined FFT
Debug architecture for the En-II system chip
Hybrid spin-CMOS stochastic spiking neuron for high-speed emulation of In vivo neuron dynamics
Single error correctable bit parallel multipliers over GF(2 m )
Extending multi-level STT-MRAM cell lifetime by minimising two-step and hard state transitions in hot bits
Hybrid shared-memory and message-passing multiprocessor system-on-chip for UWB MAC layer
Undetectable transition faults under broadside tests with constant primary input vectors
Editorial Advances in Electronics Systems Simulation
Machine learning guided thermal management of Open Computing Language applications on CPU-GPU based embedded platforms
Half-buffer retiming and token cages for synchronous elastic circuits
Embedded high-resolution delay measurement system using time amplification
Area- and power-efficient iterative single/double-precision merged floating-point multiplier on FPGA
Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems
Scan cell design for launch-on-shift delay tests with slow scan enable
Design of efficient modulo 2 n +1 multipliers
Reconstructing a lightweight security protocol in the radio-frequency identification systems
Low-precision DSP-based floating-point multiply-add fused for field programmable gate arrays
Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction
Primary input cones based on test sequences in synchronous sequential circuits
Bridging fault diagnostic tool based on DIDDQ probabilistic signatures, circuit layout parasitics and logic errors
Effect of scaling on the area and performance of the H.264/AVC full-search fractional motion estimation algorithm on field-programmable gate arrays
Fully digital test solution for a set of ADCs and DACs embedded in a SIP or SOC
Analysis of power-accuracy trade-off in digital signal processing applications using low-power approximate adders
Methodology for adapting on-chip interconnect architectures
High performance and predictable memory controller for multicore mixed-criticality real-time systems
Enhancing the security of memory in cloud infrastructure through in-phase change memory data randomisation
Modelling tools built upon the hardware description language foundation
Test data truncation for test quality maximisation under ATE memory depth constraint
A novel self-timing CMOS first-edge take-all circuit for on-chip communication systems
Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor
Challenges and advances in Toffoli network optimisation
Inversion schemes for sublithographic programmable logic arrays
Low-power and real-time address translation through arithmetic operations for virtual memory support in embedded systems
Optimised realisations of large integer multipliers and squarers using embedded blocks
Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits
H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture
Online multi-object tracking based on time and frequency domain features
Evaluation of simulator tools and power-aware scheduling model for wireless sensor networks
Implementation of nMPRA CPU architecture based on preemptive hardware scheduler engine and different scheduling algorithms
Phone-nomenon 2.0: A compact thermal model for smartphones
Switchable cache: utilising dark silicon for application specific cache optimisations
Signal transition graph decomposition: internal communication for speed independent circuit implementation
Delay performance due to thermal variation on field-programmable gate array via the adoption of a stable ring oscillator
Multi-cycle broadside tests with runs of constant primary input vectors
Evaluation of low-energy and high-performance processor using variable stages pipeline technique
HW-SW optimisation of JPEG2000 wavelet transform for dedicated multimedia processor architectures
Energy-Efficient Branch Predictor via Instruction Block Type Prediction in Decoupled Frontend
High-level estimation methodology for designing the instruction cache memory of programmable embedded platforms
TLP: Towards three-level loop parallelisation
Flexible and scalable methodology for testing high-speed source synchronous interfaces on automated test equipment (ATE) with multiple fixed phase capture and compare
Reliable SRAM using NAND-NOR Gate in beyond-CMOS QCA technology
Design and analysis of a novel fast adder using logical effort method
Advances in nanoelectronics circuits and systems [Editorial]
Accelerating Deep Neural Networks implementation: A survey
Power-efficient real-time solution for adaptive vision algorithms
Computer-aided crosstalk minimisation design for system-on-chip
Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform
High-throughput one-dimensional median and weighted median filters on FPGA
Improving the accuracy of defect diagnosis by adding and removing tests
Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips
Automatic diagnosis of single fault in interconnect testing of SRAM-based FPGA
Fast and memory-efficient invariant computation of ordinary Petri nets
Fully adaptive routing algorithms and region-based approaches for two-dimensional and three-dimensional networks-on-chip
Exploring branch target buffer access filtering for low-energy and high-performance microarchitectures
Selected papers from the 18 th International Conference on Field Programmable Logic and Applications (FPL 2008) [Editorial]
State assignment for sequential circuits using multi-objective genetic algorithm
A novel task scheduling approach for dependent non-preemptive tasks using fuzzy logic
Power efficient error correction coding for on-chip interconnection links
Fault-tolerance techniques for hybrid CMOS/nanoarchitecture
Intensive computing on a large data volume with a short-vector single instruction multiple data processor
Defect avoidance in programmable devices
Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories
Combined input test data volume reduction for mixed broadside and skewed-load test sets
MetaWire: Using FPGA configuration circuitry to emulate a network-on-chip
Role of circuit representation in evolutionary design of energy-efficient approximate circuits
Single bit-line 11T SRAM cell for low power and improved stability
Low energy multi-stage level converter for sub-threshold logic
FPGA-based fault emulation of synchronous sequential circuits
Near-optimal Y-routed delay trees in nanometric interconnect design
Efficient implementation of bit-parallel fault tolerant polynomial basis multiplication and squaring over GF(2 m )
Who is wearing me? TinyDL-based user recognition in constrained personal devices
Real-time speech enhancement using optimised empirical mode decomposition and non-local means estimation
Efficient and scalable cross-by-pass-mesh topology for networks-on-chip
Multi-objective optimisations for a superscalar architecture with selective value prediction
Static test compaction for circuits with multiple independent scan chains
Analysis of the error susceptibility of a field programmable gate array-based image compressor through random event injection simulation
Mitigating information leakage during critical communication using S*FSM
Analysis of shared-link AXI
Partitioned security processor architecture on FPGA platform
Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures
Metric for the ability of functional capture cycles to ensure functional operation conditions
Case studies in determining the optimal field programmable gate array design for computing highly parallelisable problems
Design of power-efficient pipelined truncated multipliers with various output precision
Defect-tolerant n 2 -transistor structure for reliable nanoelectronic designs
Editorial- three-dimensional integrated circuits design
Mechanically coupled ring-resonator filter and array (analytical and finite element model)
Automatic management of Software Programmable Memories in Many-core Architectures
Event-based high throughput computing: A series of case studies on a massively parallel softcore machine
Three-dimensional integrated circuits implementation of multiple applications emphasising manufacture reuse
Power-efficient reliable register file for aggressive-environment applications
State encoding algorithm for peak current minimisation
A novel FPGA-Based Bi input-reduced order extended Kalman filter for speed-sensorless direct torque control of induction motor with constant switching frequency controller
Customisation of on-chip network interconnects and experiments in field-programmable gate arrays
Multi-core hardware realisation of the quasi maximum likelihood PPS estimator
Evaluation of the Soft Error Assessment Consistency of a JIT-based Virtual Platform Simulator
Algebra of switching networks
Verification of serialising instructions for security against transient execution attacks
Joint multicast routing and network design optimisation for networks-on-chip
Power domain management interface: flexible protocol interface for transaction-level power domain management
Adaptive Shrink and Shard Architecture Design for Blockchain Storage Efficiency
HASTI: hardware-assisted functional testing of embedded processors in idle times
Self-reconfigurable secure file system for embedded Linux
Performance analysis of dynamic CMOS circuit based on node-discharger and twist-connected transistors
Instruction cache tuning for embedded multitasking applications
Energy-efficient fault tolerant technique for deflection routers in two-dimensional mesh Network-on-Chips
Contention resolution on a broadcast-based distributed shared memory multiprocessor
Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays
Low-space bit-serial systolic array architecture for interleaved multiplication over GF(2m)
Low-power algorithm for automatic topology generation for application-specific networks on chips
Robust intellectual property protection of VLSI physical design
Multi-objective optimisation algorithm for routability and timing driven circuit clustering on FPGAs
On-chip communication for neuro-glia networks
Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration
Encoding of processor instruction sets with explicit concurrency control
Performance/energy aware task migration algorithm for many-core chips
FPGA accelerated multipliers over binary composite fields constructed via low hamming weight irreducible polynomials
On-chip memory space partitioning for chip multiprocessors using polyhedral algebra
Multi-standard reconfigurable motion estimation processor for hybrid video codecs
Amdahl's law in the context of heterogeneous many-core systems - a survey
Test data compression using hierarchical block merging technique