yusuke1997/dblp-id-title huggingface dataset:
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns
Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement
Efficient Built-In Test and Calibration of High Speed Serial I/O Systems Using Monobit Signal Acquisition
Comments on "optimizing error masking in BIST by output data modification"
Fault Diagnosis of Analog Circuits Using Bayesian Neural Networks with Wavelet Transform as Preprocessor
Quiescent current analysis and experimentation of defective CMOS circuits
Design of Memories with Concurrent Error Detection and Correction by Nonlinear SEC-DED Codes
A realistic defect oriented testability methodology for analog circuits
A Survey of Test Techniques for MCM Substrates
2022 Reviewers
Modeling Remapping Based Fault Tolerance Techniques for Chip Multiprocessor Cache with Design Space Exploration
Using Evolutionary Algorithms for Signal Integrity Assessment of High-Speed Data Buses
A New Method for Testing Re-Programmable PLAs
Test Strategies for Electrode Degradation in Bio-Fluidic Microsystems
A Polynomial Transform Method for Hardware Systematic Error Identification and Correction in Semiconductor Multi-Site Testing
Using Stochastic Differential Equation for Verification of Noise in Analog/RF Circuits
Neuro-Fuzzy Evaluation of the Software Reliability Models by Adaptive Neuro Fuzzy Inference System
Design and Optimization Methodology of Coplanar Waveguide Test Structures for Dielectric Characterization of Thin Films
A New Approach to Model the Effect of Topology on Testing Using Boundary Scan
Modular Test Kit - A Modular Approach for Efficient and Function-Oriented Testing
RSBST: an Accelerated Automated Software-Based Self-Test Synthesis for Processor Testing
HVoC: a Hybrid Model Checking - Interactive Theorem Proving Approach for Functional Verification of Digital Circuits
YOLOv8-TDD: An Optimized YOLOv8 Algorithm for Targeted Defect Detection in Printed Circuit Boards
MoDiVHA: A Hierarchical Strategy for Distributed Test Assignment
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits
Constrained state assignment of easily testable FSMs
On-line Condition Monitoring and Maintenance of Power Electronic Converters
Ring-like testing of digital circuits
General Design for Test Guidelines for RF IC
Survey of Verification of RISC-V Processors
2024 Reviewers
Fault Models and Test Generation for OpAmp Circuits - The FFM
Experimental Results for Self-Dual Multi-Output Combinational Circuits
An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration
Partial Symmetry in Cellular Automata Rule Vectors
Fault simulation for general FCMOS ICs
Testing of static random access memories by monitoring dynamic power supply current
Simulation-based Analysis of RPL Routing Attacks and Their Impact on IoT Network Performance
A Built-in Self-Test Scheme for Memory Interfaces Timing Test and Measurement
A Novel Compact Model for On-Chip Vertically-Coiled Spiral Inductors
Experience in Validation of PowerPCTM Microprocessor Embedded Arrays
Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta I DDQ Testing
One More Class of Sequential Circuits having Combinational Test Generation Complexity
A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs
Model Transferability from ImageNet to Lithography Hotspot Detection
A 10-Transistor 65 nm SRAM Cell Tolerant to Single-Event Upsets
Design Error Diagnosis with Re-Synthesis in Combinational Circuits
A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks
A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters
NBTI and Power Reduction Using a Workload-Aware Supply Voltage Assignment Approach
New Editors, 2013
Tutorial on semiconductor memory testing
Scan Test Strategy for Asynchronous-Synchronous Interfaces
Study of Low-Cost Electrical Test Strategies for Post-Silicon Yield Improvement of MEMS Convective Accelerometers
A Functional Approach for Testing the Reorder Buffer Memory
Hardware Trojan Detection Using an Advised Genetic Algorithm Based Logic Testing
Reliability benefits of IDDQ
A data optimization test technique for characterizing embedded ADCs
Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach
High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors
On Built-In Self-Test for Adders
Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks
An Oscillation-Based Technique for Degradation Monitoring of Sensing and Actuation Electrodes Within Microfluidic Systems
Impact of Negative Bias Temperature Instability on Gate-All-Around Flip-Flops
Technology and layout-related testing of static random-access memories
Low Cost Built-in Sensor Testing of Phase-Locked Loop Dynamic Parameters
Random Pattern Testability of Control and Address Circuitry of an Embedded Memory with Feed-Forward Data-Path Connections
Smart Substrate MCMs
Fault simulation on massively parallel SIMD machines algorithms, implementations and results
On the Reuse of Heterogeneous IPs into SysML Models for Integration Validation
Fault Coverage Analysis of Peak-Detector Based BIST for RF LNAs
Comparison of the Output Parameters of the Memristor-based Op-amp Model and the Traditional Op-amp Model
Constant testability of combinational cellular tree structures
Incomplete Testing of SOC
Test Data Compression Using Selective Sparse Storage
Detection of Defects Using Fault Model Oriented Test Sequences
Error Correction Schemes with Erasure Information for Fast Memories
Reducing Average and Peak Test Power Through Scan Chain Modification
A Jitter Injection Signal Generation and Extraction System for Embedded Test of High-Speed Data I/O
An Efficient Framework for Scalable Defect Isolation in Large Scale Networks of DNA Self-Assembly
A Novel Metaheuristic Based Method for Software Mutation Test Using the Discretized and Modified Forrest Optimization Algorithm
Testability and test generation for majority voting fault-tolerant circuits
Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study
Easily Testable Cellular Carry Lookahead Adders
Defect-Oriented Sampling of Non-Equally Probable Faults in VLSI Systems
Current testing in dynamic CMOS circuits
Reliability Analysis for a GaAs LNA with Temperature Stress
A Test Platform for Dependability Analysis of SoCs Exposed to EMI and Radiation
A Formal Analysis of Fault Diagnosis with D -matrices
New Editors - 2022
Test Points Selection for Analog Fault Dictionary Techniques
Towards Nanoelectronics Processor Architectures
Parity bit calculation and test signal compaction for BIST applications
Functional Verification of DMA Controllers
Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits
Detailed Analysis of Compilation Options for Robust Software-based Embedded Systems
On the Use of Static Temperature Measurements as Process Variation Observable
Efficient Test Compression Technique for SoC Based on Block Merging and Eight Coding
Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality
Transient power supply current monitoring - A new test method for CMOS VLSI circuits
A Complete Design-for-Test Scheme for Reconfigurable Scan Networks
Isolation of Failing Scan Cells through Convolutional Test Response Compaction
Analysis of Security Vulnerability Levels of In-Vehicle Network Topologies Applying Graph Representations
Design of Approximate Subtractors and Dividers for Error Tolerant Image Processing Applications
Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis
A New Analytical Model of SET Latching Probability for Circuits Experiencing Single- or Multiple-Cycle Single-Event Transients
A New On-chip Signal Generator for Charge-Based Capacitance Measurement Circuit
Soft Computing Techniques Based CAD Approach for Power Supply Noise Reduction in System-on-Chip
Adaptive Bayesian Diagnosis of Intermittent Faults
Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies
Linearity Testing of A/D Converters Using Selective Code Measurement
A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores
Variability and Analog Parameter Characterization in Enclosed Layout Transistors
Test Generation Algorithm for Linear Systems Based on Genetic Algorithm
Formal Verification of a Dependable State Machine-Based Hardware Architecture for Safety-Critical Cyber-Physical Systems: Analysis, Design, and Implementation
MCM Test Strategy Synthesis from Chip Test and Board Test Approaches
Assessment of Microfluidic System Testability using Fault Simulation and Test Metrics
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems
Methodical Approach for Immunity Assessment of Electronic Devices Excited by High Power EMP
Fault Tolerant Lanczos Eigensolver via an Invariant Checking Method
Logical redundancies in irredundant combinational circuits
Time-Based Embedded Test Instrument with Concurrent Voltage Measurement Capability
Test Technology Newsletter February 2020
Measurement of Nonlinear Dielectric Behaviour of Semiconductor Material Under Microwave Field in Dual-Mode Rectangular Cavity
Scan Latch Design for Test Applications
Analysis and Detection of Open-gate Defects in Redundant Structures of a FinFET SRAM Cell
Predicting Energy Dissipation in QCA-Based Layered-T Gates Under Cell Defects and Polarisation: A Study with Machine-Learning Models
Electromagnetic Parameters Measurement of Sheet Using Separate Microstrip Line
Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing
Exploration of Noise Impact on Integrated Bulk Current Sensors
Economics of "design for test" to remain competitive in the 90s
Experience with Widening Based Equivalence Checking in Realistic Multimedia Systems
Debug Facilities in the TriMedia CPU64 Architecture
Research on the Efficiency Improvement of Design for Testability Using Test Point Allocation
Hardware Trojan Detection Leveraging a Novel Golden Layout Model Towards Practical Applications
Searching for Global Test Costs Optimization in Core-Based Systems
Substrate Testing on a Multi-Site/Multi-Probe ATE
Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits
Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits
Automatic Feature Selection of Hardware Layout: A Step toward Robust Hardware Trojan Detection
On-Line Fault Monitoring
Too Few or Too Many Properties? Measure it by ATPG!
A Quadruple-Node Upsets Hardened Latch Design Based on Cross-Coupled Elements
ATPG and diagnostics for boards implementing boundary scan
HT-Pred: An Extensive Methodology for Dataset Preparation and Hardware Trojan Prediction using Gate-Level Netlist
Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics
A Test Generation Method of R-2R Digital-to-Analog Converters Based on Genetic Algorithm
On the Consolidation of Mixed Criticalities Applications on Multicore Architectures
A synthesis-based test generation and compaction algorithm for multifaults
Grouped Genetic Algorithm Based Optimal Tests Selection for System with Multiple Operation Modes
On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits
Calibration Enabled Scalable Current Sensor Module for Quiescent Current Testing
A Framework for Configurable Joint-Scan Design-for-Test Architecture
Fault Detection in Switched Current Circuits Using Built-in Transient Current Sensors
Small Delay Fault Testing with Multiple Voltages under Variations: Defect vs. Fault Coverage
Fault Diagnosis of Linear Analog Electronic Circuit Based on Natural Response Specification using K-NN Algorithm
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Automatic Test Pattern Generation for Resistive Bridging Faults
Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique
A Mixed Mode BIST Scheme Based on Reseeding of Folding Counters
Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures
Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems
Short test procedures for R-2R D/A converters by electrical modeling and application of the ambiguity algorithm
Self-Calibration of Output Match and Reverse Isolation in LNAs Based Switchable Resistor
Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations
A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation
Fast PWM-Based Test for High Resolution SigmaDelta ADCs
Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets
An algebra of multiple faults in RAMs
Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion
Activity Factor Based Hardware Trojan Detection and Localization
Fast Anti-Random (FAR) Test Generation to Improve the Quality of Behavioral Model Verification
QCA Circuits for Robust Coplanar Crossing
ICCQ: A Test Method for Analogue VLSI Using Local Current Sensors
Measurement and Simulation of the Near Magnetic Field Radiated by Integrated Magnetic Inductors
Low Cost Signal Reconstruction Based Testing of RF Components using Incoherent Undersampling
Chebyshev-based Algorithm: Achieving Fast ADC Static Parameter Testing Using a Low-precision Signal Source
A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips
Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures
Partial scan design and test sequence generation based on reduced scan shift method
Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis
Hardware Trojan Free Netlist Identification: A Clustering Approach
Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults
Distributed Scan Like Fault Detection and Test Optimization for Digital Microfluidic Biochips
Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs
A tale of two designs: the cheapest and the most economic
Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic System Assembly
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
Dynamic Analog/RF Alternate Test Strategies Based on On-chip Learning
Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications
Traxtor: An Automatic Software Test Suit Generation Method Inspired by Imperialist Competitive Optimization Algorithms
Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST
Detecting Multiple Faults in One-Dimensional Arrays of Reversible QCA Gates
Analog Fault Diagnosis Using Conic Optimization and Ellipsoidal Classifiers
Abort-on-Fail Based Test Scheduling
A Program-Output Estimator for Software Testing Using Program Analysis and Deep Learning Algorithms
Guest Editorial: Special Issue on Testing of 3D Stacked Integrated Circuits
A model for sequential machine testing and diagnosis
A New Approach for Modeling Inconsistencies in Digital-Assisted Analog Design
A Novel TOPSIS-Based Test Vector Compaction Technique for Analog Fault Detection
Design and Evaluation of XOR Arbiter Physical Unclonable Function and its Implementation on FPGA in Hardware Security Applications
Behavioral Level Noise Modeling and Jitter Simulation of Phase-Locked Loops with Faults Using VHDL-AMS
A Diagnostics Method for Analog Circuits Based on Improved Kernel Entropy Component Analysis
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger
Defect-tolerant Logic with Nanoscale Crossbar Circuits
Test and diagnosis of analog circuits: When fuzziness can lead to accuracy
A Novel Approach of Data Content Zeroization Under Memory Attacks
An Extensible Code for Correcting Multiple Cell Upset in Memory Arrays
Self-Testing Embedded Two-Rail Checkers
The Fundamental Primitives with Fault-Tolerance in Quantum-Dot Cellular Automata
Thermal Monitoring of Self-Checking Systems
SIVA: A System for Coverage-Directed State Space Search
Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits
An Approximate Calculation of Ratio of Normal Variables and Its Application in Analog Circuit Fault Diagnosis
Alternate Test of LNAs Through Ensemble Learning of On-Chip Digital Envelope Signatures
Compressive Sampling Coupled OFDM Technique for Testing Continuous Wave Radar
A Bist Scheme for Non-Volatile Memories
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits
Code Generation for Functional Validation of Pipelined Microprocessors
Trade-off analysis on cost and manufacturing technology of an electronic product: Case study
Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems
Detection of coupling faults in RAMs
Novel Fault-Tolerant Processing in Memory Cell in Ternary Quantum-Dot Cellular Automata
A quasi-optimal scheduling of intermediate signatures for multiple signature analysis compaction testing schemes
On Maximizing the Coverage of Catastrophic and Parametric Faults
Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System
Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests
Sequential circuit test generation using dynamic justification equivalence
Modeling Soft Error Propagation in Near-Threshold Combinational Circuits Using Neural Networks
Online Diagnosis and Self-Recovery of Faulty Cells in Daisy-Chained MEDA Biochips Using Functional Actuation Patterns
Measuring Group Delay of Frequency Downconverter Devices Using a Chirped RF Modulated Signal
Feature Vector Selection Method Using Mahalanobis Distance for Diagnostics of Analog Circuits Based on LS-SVM
Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories
Susceptible Workload Evaluation and Protection using Selective Fault Tolerance
Improve the Quality of Per-Test Fault Diagnosis Using Output Information
An Efficient Compatibility-Based Test Data Compression and Its Decoder Architecture
Design and Simulation of a Dependable Architecture Using Triple Modular Redundancy for Embedded Cyber-Physical Systems
A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices
Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation
Bridging Faults in Pipelined Circuits
Testability of 2-Level AND/EXOR Circuits
A Discussion on Test Pattern Generation for FPGA - Implemented Circuits
Comprehensive Analysis and Optimization of Reliable Viterbi Decoder Circuits Implemented in Modular VLSI Design Logic Styles
Balanced Secure Scan: Partial Scan Approach for Secret Information Protection
Redundancy Removal during High-Level Synthesis Using Scheduling Don't-Cares
The Design and Implementation of an On-Line Testable UART
Self-checking combinational circuit design for single and unidirectional multibit error
Minimized Power Consumption for Scan-Based BIST
New Methodology for Complete Properties Extraction from Simulation Traces Guided with Static Analysis
Testing for Bounded Faults in RAMs
Applications for Low Frequency Impedance Analysis Systems
Design for Testability Using State Distances
Low-Cost Concurrent Error Detection for GCM and CCM
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits
Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness
Multiple Soft Fault Diagnosis of Nonlinear Circuits Using the Continuation Method
Library Characterization of Arithmetic Circuits for Reliability-Aware Designs in SRAM-Based FPGAs
Efficient Test and Characterization of Space Transmit-Receive Modules Using Scalable and Multipurpose Automated Test System
A Distributed Error and Anomaly Communication Architecture for Analog and Mixed-Signal Systems
Multiple-Constraint Driven System-on-Chip Test Time Optimization
Measurement selection for parametric IC fault diagnosis
Universal test set generation for CMOS circuits
Sushil Doranga Joins JETTA Editorial Board
A Built-in Single Event Upsets Detector for Sequential Cells
A Fault Detection Scheme for the FPGA Implementation of SHA-1 and SHA-512 Round Computations
Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST
Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion
New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency
Novel Method for Nondestructive Body Effect Measurement in Dynamic Random Access Memory
Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients
Security Analysis of the Efficient Chaos Pseudo-random Number Generator Applied to Video Encryption
An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology
Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments
A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator
Diagnosis and Compensation of Control Program, Sensor and Actuator Failures in Nonlinear Systems Using Hierarchical State Space Checks
A parametric yield model
A Defect Detection Method of Mixed Wafer Map Using Neighborhood Path Filtering Clustering Algorithm
Fault Diagnosis of Analog Circuits Using an Improved BiTCN Combined with BiLSTM
Reliability Properties Assessment at System Level: A Co-Design Framework
Current Testing Procedure for Deep Submicron Devices
Selecting measurements to test the functional behavior of analog circuits
SEU Fault Injection Strategy for SRAM-based FPGA User Memory Based on Dual-Circuit Model
Intra-Cell Defects Diagnosis
Built-in Self Test of RF Subsystems with Integrated Detectors
Inherent Hardware Identifiers: Advancing IC Traceability and Provenance in the Multi-Die Era
A Graph-Based Approach to Power-Constrained SOC Test Scheduling
Upgrading In-Circuit Test of High Density PCBAs Using Electromagnetic Measurement and Principal Component Analysis
LFSR-Based Deterministic TPG for Two-Pattern Testing
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits
A New Neural Network Based on CNN for EMIS Identification
Single-Event Effects Analysis of a Pulse Width Modulator IC in a DC/DC Converter
Test Generation and Fault Simulation for Cell Fault Model using Stuck-at Fault Model based Test Tools
Self-checking CMOS circuits using pass-transistor logic
Correction: PCB Defects: a Unified Survey of Trends, Detection Techniques, and Limitations Through Systematic Literature Review
Study of an Electrical Setup for Capacitive MEMS Accelerometers Test and Calibration
An Isochronous Testing Strategy for Hierarchical Adaptive Distributed System-Level Diagnosis
Adaptive Management Techniques for Optimized Burn-in of Safety-Critical SoC
A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm
Layout Driven Selection and Chaining of Partial Scan Flip-Flops
Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor
Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time
A Source-code Aware Method for Software Mutation Testing Using Artificial Bee Colony Algorithm
Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction
On-Chip Test for Mixed-Signal ASICs using Two-Mode Comparators with Bias-Programmable Reference Voltages
An Implementation Approach of the IEEE 1149.1 for the Routing Test of a VLSI Massively Parallel Architecture
Extreme Learning Machine Model For Multi-Fault Diagnosis of Analog Circuits
Self-Adaptive Fault Tolerance in Multi-/Many-Core Systems
Fault Detection of Analog Circuits Using Network Parameters
Testing and Diagnosis of Digital Microfluidic Biochips using Multiple Droplets
Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs
2020 JETTA-TTTC Best Paper Award
Symmetry Measure for Memory Test and Its Application in BIST Optimization