yusuke1997/dblp-id-title huggingface dataset:
High-Performance Fault-Tolerant VLSI Systems Using Micro Rollback
Design and Evaluation of a Proxy Cache for Peer-to-Peer Traffic
R70-26 Probabilistic Aspects of Machine Decomposition Theory
On Single-Fault Set Diagnosability in the PMC Model
Fault Tolerant Algorithms for Broadcasting on the Star Graph Network
Capacity-Independent Address Mapping for Flash Storage Devices with Explosively Growing Capacity
A Provably Secure Strong PUF Based on LWE: Construction and Implementation
An Algorithm for Optimal NAND Cascade Logic Synthesis
Token Relabeling in a Tagged Token Data-Flow Architecure
Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs
Stare 2-A Graphical Hard-Copy System
On the Cost of Base N Adders
Structural and Dynamic Changes in Concurrent Systems: Reconfigurable Petri Nets
Vector Register Allocation
Comments on "A TCAM-Based Parallel Architecture for High-Speed Packet Forwarding"
The Use of the Simplex Algorithm in the Mechanization of Boolean Switching Functions by Means of Magnetic Cores
A Generalization of Eklundh's Algorithm for Transposing Large Matrices
Qu-Trefoil: Large-Scale Quantum Circuit Simulator Working on FPGA With SATA Storages
I/O Causality Based In-Line Data Deduplication for Non-Volatile Memory Enabled Storage Systems
Diagnosis of Faults in Linear Tree Networks
Radix-4 Reciprocal Square-Root and Its Combination with Division and Square Root
Analytic Queueing Models for Programs with Internal Concurrency
Orchid: An Online Learning Based Resource Partitioning Framework for Job Colocation With Multiple Objectives
Global and Modular Two's Complement Cellular Array Multipliers
Minimization of the Partially-Developed Transfer Tree
Relating the Cyclic Behavior of Linear and Intrainverted Feedback Shift Registers
The Total Delay Fault Model and Statistical Delay Fault Coverage
An Efficient Solution to the Cache Thrashing Problem Caused by True Data Sharing
ARETE: Accurate Error Assessment via Machine Learning-Guided Dynamic-Timing Analysis
Scalable Concolic Testing of RTL Models
A Class of Simple Decoding Networks for Marcus Matrix Switches
Comparing Neural Network Based Decoders for the Surface Code
Data Transfers in Broadcast Networks
A FORTRAN Extension to Facilitate Proposal Preparation
On Estimating the Large Entries of a Convolution
Abstractions of Finite-State Machines and Immediately-Detectable Output Faults
Automatic Data-Accumulation System for Wind Tunnels
Enabling Pulse-Level Programming, Compilation, and Execution in XACC
A Modified Working Set Paging Algorithm
General Theory of Metastable Operation
Using Lossless Data Compression in Data Storage Systems: Not for Saving Space
A Statistical Study of the Performance of a Task Scheduling Algorithm
PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era
A Low-Cost Real-Time Embedded Stereo Vision System for Accurate Disparity Estimation Based on Guided Image Filtering
The Prospects for Multivalued Logic: A Technology and Applications View
The Solution of Lagrange's Equations by Analog Computation
Energy Efficient On-Demand Dynamic Branch Prediction Models
EPIC: Profiling the Propagation and Effect of Data Errors in Software
On the Number of Acceptable Task Assignments in Distributed Computing Systems
Comments on "Algorithmic State Machine Design and Automatic Theorem Proving: Dual Approaches to the Same Activity"
Testable Realizations for FET Stuck-Open Faults CMOS Combinational Logic Circuits
A High Data-Rate Digital Output Correlator Design
Microdiagnostics for the Standard Computer MLP-900 Processor
Multiresolution Spatial and Temporal Coding in a Wireless Sensor Network for Long-Term Monitoring Applications
Signature Analysis for Multiple-Output Circuits
ISSA: Architecting CNN Accelerators Using Input-Skippable, Set-Associative Computing-in-Memory
A Note on Easily Testable Realizations for Logic Functions
A Simplified Procedure for the Realization of Linearly-Separable Switching Functions
A Note on the Walsh Functions
High Performance Graph Processing with Locality Oriented Design
Internode Distance and Optimal Routing in a Class of Alternating Group Networks
Two Tests for the Linearity of Sequential Machines
Synthesis of Electronic Circuits for Symmetric Functions
Probabilistic Loop Scheduling for Applications with Uncertain Execution Time
Comments on "Analysis of Self-Stabilizing Clock Synchronization by Means of Stochastic Petri Nets"
Branch Predictor Design for Energy Harvesting Powered Nonvolatile Processors
Symbolic Analysis of Bounded Petri Nets
QoS-Aware Fault-Tolerant Scheduling for Real-Time Tasks on Heterogeneous Clusters
Square Rooting Algorithms for Integer and Floatingg-Point Numbers
A Methodical Approach to Analyzing and Synthesizing a Self-Repairing Computer
Theory of Unidirectional Error Correcting/Detecting Codes
Sparse Gaussian Elimination with Controlled Fill-in on a Shared Memory Multiprocessor
Practical Multituple Packet Classification Using Dynamic Discrete Bit Selection
Toward Fuzzy Traffic Adaptation Solution in Wireless Mesh Networks
An Algorithm for Determining the Topological Dimensionality of Point Clusters
Harvest Rate of Reconfigurable Pipelines
A Generalization of the Fast Fourier Transform
Digital System Design Automation - A Method for Designing a Digital System as a Sequential Network System
Coping with Anomalies in Parallel Branch-and-Bound Algorithms
Network Synthesis for Distributed Embedded Systems
R70-40 Module Clustering to Minimize Delay in Digital Networks
A Fast Computer Method for Matrix Transposing
On Computer Self-Diagnosis Part II-Generalizations and Design Principles
A Decision Support System for the Design and Evaluation of Sustainable Wastewater Solutions
A Computer Algorithm for Calculating the Product A B Modulo M
Approximation Algorithms for Min-Max Cycle Cover Problems
Computationally Efficient PKI-Based Single Sign-On Protocol, PKASSO for Mobile Devices
Exploitation of Initial Conditions to Achieve Flux Gain and Nondestructive Readout in Balanced Magnetic Circuits
Aspects of Language Design for Combinatorial Computing
Virtual NVMe-Based Storage Function Framework With Fast I/O Request State Management
Improving Latency Tolerance of Multithreading through Decoupling
High-Speed Plated-Wire Memory System
Parallel Processor Configuration Design with Processing/Transmission Costs
Optimizing Hardware Function Evaluation
A Characterization of Ternary Simulation of Gate Networks
Myopic Policies in Sequential Classification
Double-Edge-Triggered Flip-Flops
Some Combinatorial Aspects of Parallel Algorithm Design for Matrix Multiplication
Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming
Radix-16 Evaluation of Certain Elementary Functions
Resource Selection for Tasks with Time Requirements Using Spectral Clustering
Constant Time Inner Product and Matrix Computations on Permutation Network Processors
Hardware Task/Processor Scheduling in a Polyprocessor Environment
A New Addition Formula for Elliptic Curves over GF(2 n )
A Parallel Structure for Signed-Number Multiplication and Addition
Functional Notation for NOR and NAND Networks
Generation of Self-Dual and Self-Complementary Dual Functions
A Realization Procedure for Multithreshold Threshold Elements
Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis
On the Series-to-Parallel Transformation of Linear Sequential Circuits
Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition
Guest Editors' Introduction: Special Section on Energy Efficient Computing
Detection of Ellipses by a Modified Hough Transformation
XHive: Efficient Cooperative Caching for Virtual Machines
Cost Reduction in the CCD Realization of MVMT Function
Condensed Linear Feedback Shift Register (LFSR) Testing - A Pseudoexhaustive Test Technique
Fast Base Extension Using a Redundant Modulus in RNS
Exploiting the Common Case When Accelerating Input-Dependent Stream Processing by FPGA
Comparative Fault Tolerance of Parallel Distributed Processing Networks
AINNS: All-Inclusive Neural Network Scheduling Via Accelerator Formalization
Comments on "Low-Latency Digit-Serial Systolic Double Basis Multiplier over GF(2 m ) Using Subquadratic Toeplitz Matrix-Vector Product Approach"
Reciprocal Walsh Series
Performance-Driven Load Balancing with a Primary-Backup Approach for Computational Grids with Low Communication Cost and Replication Cost
Shell: A Spatial Decomposition Data Structure for Ray Traversal on GPU
Design of Optimal Systolic Algorithms for the Transitive Closure Problem
CDS: Coupled Data Storage to Enhance Read Performance of 3D TLC NAND Flash Memory
Consistent Updates for Packet Classifiers
Self-Routing Technique in Perfect-Shuffle Networks Using Control Tags
Short-Cut Method of Deriving Nearly Optimal Arrays of NAND Trees
Concurrent Error Detection in Wavelet Lifting Transforms
Breaking the DECT Standard Cipher With Lower Time Cost
Identifying the Worst Reliability Input Vectors and the Associated Critical Logic Gates
R68-38 Accurate Analog Computer Generation of Bessel Functions for Large Ranges
Instruction Issue Logic in Pipelined Supercomputers
FedGKD: Toward Heterogeneous Federated Learning via Global Knowledge Distillation
Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors
Failure-Erasure Circuitry: A Duplicative Technique of Failure-Masking Systems
A Residue Arithmetic Extension for Reliable Scientific Computation
Graphs of Linear Forms on Modules over Boolean Rings
Comments on "Redundancy Testing in Combinational Networks"
Improving Unstructured Peer-to-Peer Systems by Adaptive Connection Establishment
Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity
Arithmetic Unit of a Computing Element in a Global, Highly Parallel Computer
The Solution of Differential Equations on Short-Word-Length Computing Devices
Arithmetic Algorithms for Error-Coded Operands
Timed Atomic Commitment
Idler : I/O Workload Controlling for Better Responsiveness on Host-Aware Shingled Magnetic Recording Drives
Distributed Program Deployment for Resource-Aware Programmable Switches
Lossless Trace Compression
User-Level QoS-Adaptive Resource Management in Server End-Systems
A Semantic Approach to Host-Based Intrusion Detection Systems Using Contiguousand Discontiguous System Call Patterns
Simulation of Steam Generation in a Heat Exchanger
Guest Editors Introduction: Special Section on Computer Arithmetic
A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs
Design of Self-Diagnosable Multiprocessor Systems with Concurrent Computation and Diagnosis
System Modeling and Performance Evaluation of Rate Allocation Schemes for Packet Data Services in Wideband CDMA Systems
A Regular Network for Multicomputer Systems
A Statistical Approach to the Computation of Delays in Logic Circuits
Soft N-Modular Redundancy
Synthesis of Symmetric Switching Functions Using Threshold Logic Elements
The Security of ARM TrustZone in a FPGA-Based SoC
A Hybrid Neural Network Model for Solving Optimization Problems
SAFA: A Semi-Asynchronous Protocol for Fast Federated Learning With Low Overhead
Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks
Decimal Adder with Signed Digit Arithmetic
Computer Methods for Creating Photomosaics
Analysis of Binary Time Series in Periodic Functions
Deadlock-Free Systems for a Bounded Number of Processes
The Parallel Enumeration Sorting Scheme for VLSI
Variable-Threshold Threshold Elements
Probability of State Transition Errors in a Finite State Machine Containing Soft Failures
On the Properties and Applications of Fuzzy-Valued Switching Functions
Comments on "Very Fast Fourier Transform Algorithms Hardware for Implementation"
A Systematic View of Model Leakage Risks in Deep Neural Network Systems
An Effective Area-Based Localization Algorithm for Wireless Networks
Synchronizing Transactions on Objects
Multithreaded Reactive Programming - the Kiel Esterel Processor
Lower Bound of the Number of Threshold Functions
Statistical Higher-Order Correlation Attacks Against Code-Based Masking
Conditional-Sum Early Completion Adder Logic
Recursive Pseudoexhaustive Test Pattern Generation
Balanced Codes with Parallel Encoding and Decoding
Hybrid CPU Management for Adapting to the Diversity of Virtual Machines
Rise and Fall Times of Transistors in Switching Operation Regardless of the Driving Source Impedance
Toward QoS-Awareness and Improved Utilization of Spatial Multitasking GPUs
Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials
Delayed-Staging Hierarchy Optimization
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
A Rounding Method to Reduce the Required Multiplier Precision for Goldschmidt Division
A VLSI Residue Arithmetic Multiplier
Network Resilience: A Measure of Network Fault Tolerance
R68-18 Random Pulse Machines
A Non-Iterative Multiple Residue Digit Error Detection and Correction Algorithm in RRNS
A New Double Point Multiplication Algorithm and Its Application to Binary Elliptic Curves with Endomorphisms
Effective and Efficient Memory Protection Using Dynamic Tainting
Low Cost and High Speed Embedded Two-Rail Code Checker
Cache Latency Control for Application Fairness or Differentiation in Power-Constrained Chip Multiprocessors
One-Dimensional Optimization on Multiprocessor Systems
All-Optical Wavelength-Routed Architecture for a Power-Efficient Network on Chip
Probability to Achieve TSC Goal
Rebuttal to the Authors' Reply to our Comments on "The Relationship Between Multivalued Switching Algebra and Boolean Algebra Under Different Definitions of Complement."
Guest Editorial: Special Section on Wireless Internet
Via Assignment in Single-Row Routing
Can I/O Variability Be Reduced on QoS-Less HPC Storage Systems?
A Computer Algorithm for Transposing Nonsquare Matrices
Hydra: A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture
Generation of Right-Linear Grammars from Regular Expressions
On Open Nesting in Distributed Transactional Memory
Maintenance Techniques of a Microprogrammed Self-Checking Control Complex of an Electronic Switching System
An Efficient Basis Conversion Algorithm for Composite Fields with Given Representations
The Reliability Wall for Exascale Supercomputing
Comments on "A Method of Generating Functions of Several Variables
$C\!\!-\!\!Lock$ : Energy Efficient Synchronization for Embedded Multicore Systems
NNPIM: A Processing In-Memory Architecture for Neural Network Acceleration
Practical Cellular Dividers
Exploiting Write Heterogeneity of Morphable MLC/SLC SSDs in Datacenters with Service-Level Objectives
The Multiple Observation Time Test Strategy
A Multi-Attribute Adaptive Fault Diagnosis Framework for Star Networks
Optimal Release Times for Software Systems with Scheduled Delivery Time Based on the HGDM
Improved Algorithms for Partitioning Problems in Parallel, Pipelined, and Distributed Computing
An Embedded Microprocessor Radiation Hardened by Microarchitecture and Circuits
An Efficient Real-Time Disk-Scheduling Framework with Adaptive Quality Guarantee
Digital Multiplexing Analog Signals
Memory MISER: Improving Main Memory Energy Efficiency in Servers
Optimization Strategies for Microprograms
On the Conversion Between Binary Code and Binary-Reflected Gray Code on Binary Cubes
Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands
Semi-Clairvoyant Scheduling in Data Analytics Systems
An Empirical Study of Off-Line Permutation Packet Routing on Two-Dimensional Meshes Based on the Multistage Routing Method
MGen: A Framework for Energy-Efficient In-ReRAM Acceleration of Multi-Task BERT
R68-28 A Microprogrammed Implementation of EULER on IBM System/360 Model 30
R70-11 Representation of Events in the von Neumann Cellular Model
A New Network Topology with Multiple Meshes
Growing and Pruning Neural Tree Networks
A Block-Level Log-Block Management Scheme for MLC NAND Flash Memory Storage Systems
Simplification of Incompletely Specified Flow Tables with the Help of Prime Closed Sets
A Solution to the Hidden-Line Problem for Computer-Drawn Polyhedra
MM-FSM$: $: A High-Efficiency General Nonlinear Function Generator for Stochastic Computation
An Availability-Aware Task Scheduling Strategy for Heterogeneous Systems
A 40-ns 17-Bit by 17-Bit Array Multiplier
SPDL: A Blockchain-Enabled Secure and Privacy-Preserving Decentralized Learning System
An Examination of Algebraic Test Generation Methods for Multiple Faults
Leveraging Access Locality for the Efficient Use of Multibit Error-Correcting Codes in L2 Cache
An experimental study to determine task size for rollback recovery systems
Staged Circuit Switching
Hardware Private Circuits: From Trivial Composition to Full Verification
An New J-K Flip-Flop for Synchronizers
Processor Assignment and Execution Sequence for Multiversion Software
Affinity-Aware VNF Placement in Mobile Edge Clouds via Leveraging GPUs
Access Time Analysis for IEEE P1687
Diagnosis of Parallel Computers with Arbitrary Connectivity
Task Allocation for Maximizing Reliability of Distributed Computer Systems
Logic Networks of Carry-Save Adders
A High-Speed Permanent Storage Device
Voltage Over-Scaling-Based Lightweight Authentication for IoT Security
Implementation and Performance Evaluation of Indirekt TCP
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
Comments on "A Least Mean Squares CUBIC Algorithm for On-Line Differential of Sampled Analog Signals"
On the Realizability of Special Classes of Autonomous Sequential Networks
Comments on "A Two's Complement Parallel Array Multiplication Algorithm"
Application of Information Theory to Sequential Fault Diagnosis
Adaptive Scheduling of Task Graphs with Dynamic Resilience
Decoding of DBEC-TBED Reed-Solomon Codes
Trouble-Shooting at GAN Point: Improving Functional Safety in Deep Learning Accelerators
On Classes of Positive, Negative, and Imaginary Radix Number Systems
Improving MapReduce Performance Using Smart Speculative Execution Strategy
A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation
Russian Visit to U. S. Computers
OFWAR: Reducing SSD Response Time Using On-Demand Fast-Write-and-Rewrite
Real-Time Computation and Recursive Functions Not Real-Time Computable
Incremental Throughput Allocation of Heterogeneous Storage With No Disruptions in Dynamic Setting
An Improved Time Delay Simulation
Design of the ESIACÂ® Algebraic Computer
Bounds for Maxium Parallelism in a Bilogic Graph Model of Computations
Digital Multiplexing of Analog Data in a Microprocessor Controlled Data Acquisition System
A Versatile Comparator for Encoding Devices
Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic
Analysis of Detection Capability of Parallel Signature Analyzers
An Incremental Computer Technique for Solving Coordinate-Rotation Equations
Design and Implementation of Modified Signed-Digit Adder
A Cellular Array for Multivalued Logic Functions
A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier
Analysis and Comparison of Cache Coherence Protocols for a Packet-Switched Multiprocessor
Extending Multiversion Time-Stamping Protocols to Exploit Type Information
When to Use Random Testing
A Method for the Generation and Processing of Dyadic Indexed Data
Sequential Fault Occurrence and Reconfiguration in System Level Diagnosis
Failure dependent bandwidth in shuffle-exchange networks
The Synonym Lookaside Buffer: A Solution to the Synonym Problem in Virtual Caches
Error Complexity Analysis of Algorithms for Matrix Multiplication and Matrix Chain Product
On the Height of Multidimensional Height-Balanced Trees
Decimal Numbers for Checking Summability
On Closedness and Test Complexity of Logic Circuits
A Shuffle-Exchange Network with Simplified Control
A Method to Determine the Expressive Power of a Set of Connectives
Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction
Tackling the Bus Turnaround Overhead in Real-Time SDRAM Controllers
An Algorithm for Solving Linear Recurrence Systems on Parallel and Pipelined Machines
R70-25 Construction of Multistep Integration Formulas for Simulation Purposes
Stability-Optimized Time Adjustment for a Networked Computer Clock
The Exclusive-Writer Approach to Updating Replicated Files in Distributed Processing Systems
Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses
DCT Implementation with Distributed Arithmetic
Matrix Criteria for Arbitrary Reliability in Iterated Neural Nets
Realization of Asynchronous Sequential Circuits Without Inserted Delay Elements
Resource Optimization of a Parallel Computer for Multiple Vector Processing
Falcon: Addressing Stragglers in Heterogeneous Parameter Server Via Multiple Parallelism
Partial Connection-Aware Topology Synthesis for On-Chip Cascaded Crossbar Network
Majority Gates Applied to Simultaneous Comparators
Ecomap: Sustainability-Driven Optimization of Multi-Tenant DNN Execution on Edge Servers
Fast Parallel GF(2^m) Polynomial Multiplication for All Degrees
Sign Detection and Implicit-Explicit Conversion of Numbers in Residue Arithmetic
Resolution, Refinements, and Search Strategies: A Comparative Study
Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach
A Digital Quarter Square Multiplier
ARB: A Hardware Mechanism for Dynamic Reordering of Memory References
Reduction of Depth of Boolean Networks with a Fan-In Constraint
PSBS: Practical Size-Based Scheduling
Multiple Fault Testing of Large Circuits by Single Fault Test Sets
Over Redundant Digit Sets and the Design of Digit-by-Digit Division Units
Tan-Like State Assignments ror Synchronous Sequential Machines
High-Speed DC Coupled Digit Detector
Positive Fail-Safe Realization of Synchronous Sequential Machines
Parallel Sorting in Two-Dimensional VLSI Models of Computation
Detecting Natural "Plateaus" in One-Dimensional Patterns
Thread Voting DVFS for Manycore NoCs
Performance of Fault-Tolerant Diagnostics in the Hypercube Systems
Discrete-Time Systems with the Decomposition Property
An Improvement of Reliability of Memory System with Skewing Reconfiguration
Predicate Detection in Asynchronous Distributed Systems: A Probabilistic Approach
BiRD: Bi-Directional Input Reuse Dataflow for Enhancing Depthwise Convolution Performance on Systolic Arrays
Calculating Cumulative Operational Time Distributions of Rpairable Computer Systems
Fenglin-I: An Open-Source Time-Sensitive Networking Chip Enabling Agile Customization
B74-41 The Metaphorical Brain, an Introduction to Cybernetics as Artificial Intelligence and Brain Theory
An Adaptive Threshold Logic Gate Using Capacitive Analog Weights
Computer Minimization of Multivalued Switching Functions
Resolution-Oriented Fault Interrelationships in Combinational Logic Networks
A New Random-Error-Correction Code
Salphasic Distribution of Clock Signals for Synchronous Systems
Schedulability Analysis of Periodic Fixed Priority Systems
The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis
The Performance and Energy Consumption of Embedded Real-Time Operating Systems
A Digital Correlator Based on the Residue Number System
Hierarchical Interconnection Networks for Multicomputer Systems
Toward a Theory for Scheduling Dags in Internet-Based Computing
Comments on "An Algorithm for Synthesis of Multiple-Output Combinational Logic"
A Polynomial Time Algorithm for Reconfiguring Multiple-Track Models
A New Performance Metric for Construction of Robust and Efficient Wireless Backbone Network
A Note on EDF Schedulingfor Real-Time Energy Harvesting Systems
Self-Synchronizing Communication Protocols
Electronic Data Sorting
The Discrete Fourier Transform Over Finite Rings with Application to Fast Convolution
Privacy-Preserving Selective Aggregation of Online User Behavior Data
Single-Channel and Multichannel Finite-State Machines
An Iterative Array for Multiplication of Signed Binary Numbers