yusuke1997/dblp-id-title huggingface dataset:
High-Order Compensated Capacitive Power Transfer Systems With Misalignment Insensitive Resonance
Polynomial Formal Verification of Multi-Valued Approximate Circuits Within Constant Cutwidth
Smart Frequency Control of Cyber-Physical Power System Under False Data Injection Attacks
Metastability in Superconducting Single Flux Quantum (SFQ) Logic
Online Identification of Piecewise Affine Systems Using Integral Concurrent Learning
Edge of Chaos Theory Sheds Light Into the All-to-None Phenomenon in Neurons - Part I: On the Fundamental Role of the Sodium Ion Channel
A DVS-Enabled Distributed Digital LDO Providing Rapid Uniform Power Grid and Ripple Reduction Achieving 20.1-ps FOM in 28 nm CMOS
Symmetrical Doherty Power Amplifier With Extended Bandwidth and Back-Off Range Based on Nonlinear Current Profile
Secure Adaptive Control of Linear Networked Systems Using Paillier Encryption
Mode Composite Waveguide Based on Hybrid Substrate Integrated Waveguide and Spoof Surface Plasmon Polariton Structure
Synchronization for Directed Multi-Level Complex Networks With Multiple Weights
Noise Model of Large-Format Readout Integrated Circuit for Infrared Focal Plane Array
A Stochastic Algorithm to Design Min-Entropy Tuning Controllers for True Random Number Generators
A Low Noise 8.3-Mpixel CMOS Image Sensor With Selectable Multiple Sampling Technique by 5.36 GHz Global Counter and Dual Latch Skew Canceler
HAS-RL: A Hierarchical Approximate Scheme Optimized With Reinforcement Learning for NoC-Based NN Accelerators
A Reconfigurable 12-to-18-Bit Dynamic Zoom ADC With Pole-Optimized Technique
Knowledge Distillation and Contrastive Learning for Detecting Visible-Infrared Transmission Lines Using Separated Stagger Registration Network
Efficient and Side-Channel Resistant Ed25519 on ARM Cortex-M4
Finite/Fixed-Time Anti-Synchronization of Inconsistent Markovian Quaternion-Valued Memristive Neural Networks With Reaction-Diffusion Terms
A Dual-Precision and Low-Power CNN Inference Engine Using a Heterogeneous Processing-in-Memory Architecture
A Direct Frequency-Interleaving Continuous-Time Bandpass Delta-Sigma ADC
Kolmogorov-Arnold Networks-Based Calibration for Single-Channel ADCs: High-Precision Nonlinear Code Synthesis With Low Power Consumption
Generating Grid Multi-Scroll Attractors in Memristive Neural Networks
Performance Analysis of an MLS-Based Interface for Impulse Response Estimation of Resistive and Capacitive Sensors
Dynamic Event-Triggered Terminal Sliding Mode Control Under Binary Encoding: Analysis and Experimental Validation
A 10.5 W, 93% Efficient Dual-Path Hybrid (DPH)-Based DC-DC Converter Incorporating a Continuous-Current-Input Switched-Capacitor Stage and Enhanced I L Reduction for 12 V/24 V Inputs
Advancing Circuit Transient Response Macromodeling: From Conventional Neural Networks to Siamese-LSTM
A 60-GHz Antenna-Duplexed Modular Front-End for Channel Sounding and Physical Layer Security
Consensus of Nonlinear Multiagent Systems With Uncertainties Using Reinforcement Learning Based Sliding Mode Control
Observer-Based Stabilization of Networked IT2 Fuzzy Semi-Markov Jump Models With Redundant Channels and Applications to Tunnel Circuit Model
A 0.5-2.5 GHz Mixer First Receiver With 200 MHz RF Bandwidth and +18.5 dBm OB-IIP3 in 180 nm CMOS for 5G NR Band
A Block PatchMatch-Based Energy-Resource Efficient Stereo Matching Processor on FPGA
Consensus Tracking of Switched Heterogeneous Nonlinear Systems With Uncertain Target
Continuous-Time, Configurable Analog Linear System Solutions With Transconductance Amplifiers
A Bit-Partitioned Floating-Point 6T SRAM Computing-in-Memory Macro Based on Dual-Edge Time-Domain Structure
Motion Detection and Analysis Using Multimaterial Fiber Sensors
Miniature Dual-Band Absorptive Bandstop Filters With Improved Passband Performance
A Proof-of-Concept of a Multiple-Cell Upsets Detection Method for SRAMs in Space Applications
Computational Vector Stimulation for Spatially Targeted, Low-Latency Adaptive Neuromodulation With Common-Mode Artifact Suppression
FREYA: A 0.023-mm²/Channel, 20.8- μW/Channel, Event-Driven 8-Channel SoC for Spiking End-to-End Sensing of Time-Sparse Biosignals
28 Gbaud PAM-4 Burst-Mode CDR With Reconfigurable Sampling Scheme
Analysis and Design of a 570-Stage CMOS RF-DC Rectifier With Ground Shielded Input Coupling Capacitors
Reduced Complexity Optimal Convolution Based on the Discrete Hirschman Transform
Input-Retention Strategies for Secure Synchronization of Piecewise Markov Neural Networks Under Hybrid Cyber-Attacks
Analytical Modeling of Short-Channel MOSFET Differential Pair Non-Linearity
High-Speed Polynomials Multiplication HW Accelerator for CRYSTALS-Kyber
Hybrid-Diode-Based Shinriki Circuit: Coexisting Oscillations and Bifurcation Trees
A Multi-Form Optimization Framework for Analog Integrated Circuit Sizing
Analysis and Design of VCO-Based Neural Front-End With Mixed Domain Level-Crossing for Fast Artifact Recovery
An Ultra-Low-Power Non-Uniform Derivative-Based Sampling Scheme With Tunable Accuracy
A Power-Efficient Autonomous Current Adaptation ADC Input Driver
CRADLE: Combined RF/Acoustic Detection and Localization of Passive Tags
Command Filtered-Based Adaptive Predefined-Time Control for Uncertain Nonlinear Systems With Applications to RLC Circuit
Design Techniques for a Multi-Phase Injection- Based Eight-Phase 17-GHz Clock Generator for Multi-Phase Wireline Receivers
Design of Enhanced Three-Level Buck Converter With Configurable Power and Control Stages for Fast Load Transient Response
Design and Optimization of a High Linearity On-Chip Sinusoidal Current Generator for Bioimpedance Measurements Using Direct Digital Synthesis
Intermittent Dynamic Event-Triggered Control for Synchronization of Stochastic Complex Networks
Finite-/Fixed-Time Synchronization of Coupled Memristive Neural Networks With Actuator Nonlinearity and Applications in Secure Communication
A Family of ΔΣ Modulators With High Spur Immunity and Low Folded Nonlinearity Noise When Used in Fractional- Frequency Synthesizers
Bursting Oscillations Induced by the Variable Discontinuous Boundary in Chua's Circuit
A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity
Bounded-Input Bounded-Output Stability Tests for Two-Dimensional Continuous-Time Systems
High-Precision Method and Architecture for Base-2 Softmax Function in DNN Training
A Memristor Emulation in 180-nm CMOS Process for Spiking Signal Generation and Chaos Application
Specific ADC of NVM-Based Computation-in-Memory for Deep Neural Networks
A-Connect: An Ex Situ Training Methodology to Mitigate Stochasticity in Neural Network Analog Accelerators
LSMCore: A 69k-Synapse/mm 2 Single-Core Digital Neuromorphic Processor for Liquid State Machine
Fanout-Based Reliability Model for SER Estimation in Combinational Circuits
Uncertain Disturbance Rejection and Attenuation for Semi-Markov Jump Systems With Application to 2-Degree-Freedom Robot Arm
Dynamic Event-Based Non-Fragile Dissipative State Estimation for Quantized Complex Networks With Fading Measurements and Its Application
Two-Dimensional Cyclic Chaotic System for Noise-Reduced OFDM-DCSK Communication
In-Situ Privacy via Mixed-Signal Perturbation and Hardware-Secure Data Reversibility
A Fully-Integrated Flexible Dual-Ring Switched-Capacitor DC-DC Converter With Fractional VCRs and Parasitic Reduction
Mittag-Leffler Stability of Fractional-Order Nonlinear Differential Systems With State-Dependent Delays
Millimeter-Wave Integrated Phased Arrays
Design of a Zero-Voltage-Transition Clamped Very-High-Frequency DC-DC Converter With Low Voltage Stress on Power Semiconductor Devices
A Low-Offset VCO-Based Time-Domain Comparator Using a Phase Frequency Detector With Reduced Dead and Blind Zones
A TM-Based Adaptive Learning Data-Model for Trajectory Tracking and Real-Time Control of a Class of Nonlinear Systems
A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks
Comprehensive Evaluation of Toroid Ring Core Parallel Inductor and Resistor as a Transformer Protection Device
Distributed Dual-Terminal Adaptive Triggered Consensus Tracking of Descriptor Multi-Agent Systems Against Asynchronous DoS Attacks With Markov Switching Topologies
QuantBayes: Weight Optimization for Memristive Neural Networks via Quantization-Aware Bayesian Inference
Bit-Level Optimized Constant Multiplication Using Boolean Satisfiability
Multi-Cell Battery Sensing and Protection IC With Integrated Low-Temperature-Drift Reference for Series Battery Pack Management
Dadu-Eye: A 5.3 TOPS/W, 30 fps/1080p High Accuracy Stereo Vision Accelerator
A 25 MHz-BW 81 dB-DR TDC-Based CTDSM With Background Analog-Integration-Based ISI Error Calibration Achieving >8 dB Even-Order Harmonic Suppression
A Two-Stage Operand Trimming Approximate Logarithmic Multiplier
Robust Fractional-Order-Based Von Mises Subband Adaptive Filtering for Feedback Cancellation in Hearing Aids
Efficient Hardware Arithmetic for Inverted Binary Ring-LWE Based Post-Quantum Cryptography
Maximum Wireless Power Transmission Using Real-Time Single Iteration Adaptive Impedance Matching
A Foreground Wide-Band Receiver I/Q Mismatch Calibration Method in FDD Transceiver
Diagnosis of Open-Switch Faults in Grid-Tied Three-Level NPC Inverters With Parameter Uncertainty Using Variable Forgetting Factor Bias-Compensation Recursive Least Squares
Near Optimal Control for Discrete-Time Switched Nonlinear Systems With Unknown Backlash-Like Hysteresis
Research Progress on Memristor: From Synapses to Computing Systems
A Buck Converter Using Auxiliary-Stage With Multiple-Single-Cycle Non-Linear Control (MSCNLC) for Fast Load Transient Response
APCCAS 2021 Guest Editorial
Frequency Splitting Elimination and Utilization in Magnetic Coupling Wireless Power Transfer Systems
HDSuper: High-Quality and High Computational Utilization Edge Super-Resolution Accelerator With Hardware-Algorithm Co-Design Techniques
Fast Nested Key Equation Solvers for Generalized Integrated Interleaved Decoder
ReMCA: A Reconfigurable Multi-Core Architecture for Full RNS Variant of BFV Homomorphic Evaluation
A 16-to-30-Gb/s 1.03-pJ/b Baud-Rate Receiver With Referenceless CDR Employing Integrated Pattern Decoding Technique in 28-nm CMOS
A Symmetrical Double Step-Down Converter With Extended Voltage Conversion Ratio
Modeling and Predicting Noise-Induced Failure Rates in Ultra-Low-Voltage SRAM Bitcells Affected by Process Variations
Structure-Reconfigurable Wide Gain Series Resonant Converter for On-Board Charger
A Noise-Tolerant Proximal Neurodynamic Algorithm for Solving MVIPs in Fixed-Time With Circuit Implementations and Applications
An Efficient Algorithm-Hardware Co-Design for Radar-Based Fall Detection With Multi-Branch Convolutions
Frequency-Domain Analysis of Reconfigured Incremental ΔΣ ADCs on the Example of the Exponential Phase
ShortcutFusion: From Tensorflow to FPGA-Based Accelerator With a Reuse-Aware Memory Allocation for Shortcut Data
MWSCAS Guest Editorial Special Issue Based on the 67th International Midwest Symposium on Circuits and Systems
Leveraging Negative Capacitance CNTFETs for Image Processing: An Ultra-Efficient Ternary Image Edge Detection Hardware
Hierarchical Prescribed-Time Coordination for Multiple Lagrangian Systems With Input-to-Output Redundancy and Matrix-Weighted Networks
HRFF: Hierarchical and Recursive Floorplanning Framework for NoC-Based Scalable Multidie FPGAs
Time-Domain Computing in Memory Using Spintronics for Energy-Efficient Convolutional Neural Network
Neuromorphic Circuit Implementation of Operant Conditioning Based on Emotion Generation and Modulation
Dynamic Tsetlin Machine Accelerators for On-Chip Training Using FPGAs
PMU-Spill: A New Side Channel for Transient Execution Attacks
Observerless Output Feedback Control of DC-DC Converters Feeding a Class of Unknown Nonlinear Loads via Power Shaping
Global Finite-Time Controller Design for HOSM Dynamics Subject to Upper-Triangular Structure
Efficient Design of Spiking Neural Network With STDP Learning Based on Fast CORDIC
Power and Frequency Intrinsic Channels on gem5
Second-Order VCO-ADC Architecture With Low-Area and High Dynamic Range Using Internal Binary Encoding
Data-Based Output Containment of Completely Heterogeneous Multi-Agent Systems With Unknown Dynamics and Its Application
Analog VLSI Implementation of Subthreshold Spiking Neural Networks and Its Application to Reservoir Computing
A 12 ps Precision Two-Step Time-to-Digital Converter Consuming 434 μW at 1 MS/s in 180 nm CMOS With a Dual-Slope Time Amplifier
Design and Implementation of a Dual-Mode Supercapacitor Fast Charger Employing Continuous and Fine-Tuned Pulse Currents
The Mismatch Performance of Pseudo Digital Ring Oscillators Used in VCO ADCs: PSRR and CMRR
Cloud-Edge Model Predictive Control of Cyber-Physical Systems Under Cyber Attacks
A Compact Wideband SPDT Switch Using Compensating Inductors and Highpass Matching Network
Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS
A Fully Integrated Stimulator With High Stimulation Voltage Compliance Using Dynamic Bulk Biasing Technique in a Bulk CMOS Technology
22 dB Signal-to-Noise Ratio Real-Time Proton Sound Detector for Experimental Beam Range Verification
Noise Measure Revisited for Design of Amplifiers Close to Activity Limits
LiCryptor: High-Speed and Compact Multi-Grained Reconfigurable Accelerator for Lightweight Cryptography
An Improved Common-Mode Transient Immunity Isolated Gate Driver With On-the-Fly Deadtime Control
The Algorithm and VLSI Architecture of High-Throughput and Highly Efficient Tensor Decomposition Engine
Accelerated RISC-V for Post-Quantum SIKE
Mixed-Signal Silicon Photomultiplier With Reconfigurable Pulse Shaper for Background Light Rejection
A GaN Driver for a Bi-Directional Buck/Boost Converter With Three-Level V GS Protection and Optimal-Point Tracking Dead-Time Control
An Analysis and Design Guideline of High-Speed and Low-Distortion Bootstrapped Switches
An Output-Capacitorless Analog LDO Featuring Frequency Compensation of Four-Stage Amplifier
Quaternion-Based Attitude Synchronization With an Event-Based Communication Strategy
Structure-Varying Complex Network Chaotic Model and Its Hardware Implementation
Self-Synchronized DS/SS With High Spread Factors for Robust Millimeter-Wave Datalinks
Hybrid Stochastic LDPC Decoder With Fully Correlated Stochastic Computation
Multiple-Receiver Inductive Power Transfer System Based on Multiple-Coil Power Relay Module
Theoretical Analysis and Hardware Reproduction of Smale Paradox Based on CCM Neurons and Edge of Chaos
Resilient Decentralized Frequency Regulation for Multi-Area Power Systems With Electric Vehicles Under Hybrid Cyber-Attacks
A Highly Linear Ka-Band GaN-on-Si Active Balanced Mixer for Radar Applications
Hybrid Batch-Normalized Deep Feedforward Neural Network Incorporating Polynomial Regression for High-Dimensional Microwave Modeling
A Coupling Matrix Synthesized Three-Dimensional Filtering Power Amplifier
Theory and Design of Pseudo-Doherty Load-Modulated Double Balanced Amplifier With Intrinsic Insensitivity to Antenna VSWR
IIP2-Calibration-Free 5G NR Cellular Receiver Front-End With Mixer-Sharing Global N-Path Notch Filter Feedback Achieving +72 dBm IIP2
Observer-Based Adaptive Optimized Control for Uncertain Cyclic Switched Nonlinear Systems: Reinforcement Learning Algorithm Approach
Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks
A Hybrid-Mode On-Chip Router for the Large-Scale FPGA-Based Neuromorphic Platform
An Inductor-First Single-Inductor Multiple-Output Hybrid DC-DC Converter With Integrated Flying Capacitor for SoC Applications
Constant Voltage Regulation of Delayed Inductive Power Transfer Systems: A Data-Driven Approach
An Energy Efficient All-Digital Time-Domain Compute-in-Memory Macro Optimized for Binary Neural Networks
A 1.8-5.4-GHz GaN MMIC Distributed Efficient Power Amplifier With Reactance Compensation and Adaptive Biasing
Simulation-Based Approaches for Comprehensive Schmitt-Trigger Analyses
Synthesis of an Equivalent Circuit for Spike-Timing-Dependent Axon Growth: What Fires Together Now Really Wires Together
Guest Editorial: Special Issue on Learning, Optimization, and Implementation for Circuits and Systems Driven by Artificial Intelligence
Neural Network-Based Distributed Adaptive Pre-Assigned Finite-Time Consensus of Multiple TCP/AQM Networks
Computer-Aided Systematic Topology Derivation of Single-Inductor Multi-Input Multi-Output Converters From Working Principle
Optimal Subband Adaptive Filter Over Functional Link Neural Network: Algorithms and Applications
Serial Butterflies for Non-Power-of-Two FFT Architectures in 5G and Beyond
A Novel Online Adaptive Dynamic Programming Algorithm With Adjustable Convergence Rate
Robust Model Predictive Control for Linear Systems via Self-Triggered Pseudo Terminal Ingredients
Bifunctional Graphene-Graphite-Based THz Wave Metasurface Absorber for Sensing and Electromagnetic Shielding
Floquet Modulation Optimizing the Tunable Isolators Based on PT-Symmetric LCR Resonators
A Highly Integrated Tri-Path Hybrid Buck Converter With Reduced Inductor Current and Self-Balanced Flying Capacitor Voltage
Distributed Bipartite Containment Control of High-Order Nonlinear Multi-Agent Systems With Time-Varying Powers
Dynamic Event-Triggered Reinforcement Learning-Based Consensus Tracking of Nonlinear Multi-Agent Systems
Multiasynchronous Extended Dissipative Sliding Mode Control of LC Circuits in Grid-Connected System Under Actuator Attacks
Distributed Nash Equilibrium Seeking for Aggregative Games With Quantization Constraints
Extended Application of Improved D-D-Σ Current Control in Synchronous Inverter Cluster Considering N Times Equivalent Impedance
A Fast-Transient Low-Dropout Regulator With Current-Efficient Super Transconductance Cell and Dynamic Reference Control
-11 to 7 dBm Power Range, Triple Band RF Energy Harvesting System With 99.9% Peak Tracking Efficiency and Improved PCE
A 3-D Crossbar Architecture for Both Pipeline and Parallel Computations
Variation-Aware SRAM Cell Optimization Using Deep Neural Network-Based Sensitivity Analysis
A Single-Step Subranging Relaxation Oscillator-Based Open-Loop Sigma-Delta ADC
Joint State and Fault Estimation for Networked Interconnected PDE Systems With Semi-Markov Fault Coefficient via Conjunct Measurement
A Transistor-Based High-Efficiency Rectifier Using Input Second Harmonic Component
A Recycling Krylov Subspace Method With High-Order Time Integration Methods for Fast Periodic AC and Noise Analysis
Secure Synchronization of Lur'e Systems Under DoS Attacks With Application to Chua's Circuit: Aperiodic Sampled-Data Control
A Programmable Adaptive-Q BPF Circuit
Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems
Sensor Fault Tolerant Control for a 3-DOF Helicopter Considering Detectability Loss
Transistor Self-Heating-Aware Synthesis for Reliable Digital Circuit Designs
Single-Ended Receiver-Side Crosstalk Cancellation With Independent Gain and Timing Control for Minimum Residual FEXT
A Novel Approach to Prescribed-Time Cooperative Output Regulation in Linear Heterogeneous Multi-Agent Systems Using Cascade System Criteria
Dual Chua's Circuit
Robust Fuzzy Control of Network-Type Re-Entrant Manufacturing Systems With Communication Delays
Quantification of Cascading Failure Propagation in Power Systems
Nonlinear Analysis of Quadrature Switched-Capacitor Power Amplifier and Digital Predistortion
Multi-Channel Analog-to-Digital Conversion Using a Delta-Sigma Modulator Without Reset and a Modulated-Sinc-Sum Filter
Customized Non-Monotonic Prescribed Performance Control for Stochastic MEMS Gyroscopes With Insufficient Input Capability
An 8-bit 5-GS/s Single-Channel Hybrid ADC With a λ/4 Transmission Line Based Time Quantizer
Event-Triggered Adaptive Fuzzy Fixed-Time Tracking Control for a Class of Nonstrict-Feedback Nonlinear Systems
An Interference-Tolerant Synchronization Scheme for Wireless Communication Systems Based on Direct Sequence Spread Spectrum
Autoencoder-Based Transceivers for Multiple Access Human Body Communication Networks
Output Series-Parallel Connection of Passivity-Based Controlled DC-DC Converters: Generalization of Asymptotic Stability
SYNtzulu: A Tiny RISC-V-Controlled SNN Processor for Real-Time Sensor Data Analysis on Low-Power FPGAs
Extremum-Seeking for PWM-Controlled Double-Integrator System via Nonlinear Small-Gain Approach
Solving Non-Homogeneous Linear Ordinary Differential Equations Using Memristor-Capacitor Circuit
Miniaturized Broadband Doherty Power Amplifier Using Simplified Output Matching Topology
Disturbance Utilization-Based Tracking Control for the Fixed-Wing UAV With Disturbance Estimation
A 20 nW +0.8°C/-0.8°C Inaccuracy (3σ) Leakage-Based CMOS Temperature Sensor With Supply Sensitivity of 0.9°C/V
Fast Strategies for the Implementation of SIKE Round 3 on ARM Cortex-M4
InterGrad: Energy-Efficient Training of Convolutional Neural Networks via Interleaved Gradient Scheduling
Timing Optimization Model and PVT Tracked Scheme for STT-MRAM Voltage-Mode Sense
RoadNet-RT: High Throughput CNN Architecture and SoC Design for Real-Time Road Segmentation
An Efficient and Reconfigurable Post-Quantum Crypto-Processor for SPHINCS+
Design and Application of Brain-Inspired Circuit With Context-Dependent and State-Dependent Memory
A 254-nW 20-kHz On-Chip RC Oscillator With 21-ppm/°C Minimum Temperature Stability and 10-ppm Long Term Stability
Robust Timing Error Detection for Multilevel Baud-Rate CDR
Power-Speed Trade-Offs in Design of Scaled FET Circuits Using C/I DS Methodology
Fault-Resilient RIS Systems: Toward SINR- and Sum-Rate Maximization of IoT Networks Using ML Frameworks
Area and Delay Trade-Offs in Three-Way Toom-Cook Large Integer Multipliers Implemented on FPGAs
A 0.0375-pJ/bit Charge-Steering Based Hybrid for 8-Gb/s/pin Full-Duplex Chip-to-Chip Interconnects in 65-nm CMOS
Adaptive Fuzzy Output-Feedback Control Design for a Class of p-Norm Stochastic Nonlinear Systems With Output Constraints
A 23-41 GHz Broadband Power Amplifier With Common-Mode Stability Enhancement Technique in 65-nm CMOS Process
Advanced Mixed Signal Concepts Exploiting the Strong Body-Bias Effect in CMOS 22FDX ®
A 310 nA DCM Hysteretic Buck Converter With 95.8% Peak Efficiency and Greater Than 90% Efficiency in 10 μA-100 mA Load Range for Battery Powered IoT Sensors
Multi-Time-Scale Voltage Regulation in ADN: A Designable Event-Triggered Method
A Fast, Accurate, and Comprehensive PPA Estimation of Convolutional Hardware Accelerators
Topkima-Former: Low-Energy, Low-Latency Inference for Transformers Using Top-k In-Memory ADC
Vibration Control of Conveying Fluid Pipe Based on Inerter Enhanced Nonlinear Energy Sink
An Improved Dual-Output Five-Level Buck PFC Rectifier With Reduced Switch Count
Hysteresis-Dependent Synchronized Load Shift Keying and Reconfigurable Class-D Power Amplifier-Based Fully Integrated Adaptive Control in Wireless Power Transfer System
Design of a Highly Efficient Class-F GaN MMIC Power Amplifier Using a Multi-Function Bias Network and a Harmonic-Isolation L-C Resonator
A Reinforcement-Learning-Assisted Power Amplifier for RF Fingerprint Generation in 65 nm CMOS
Meta: A Memory-Efficient Tri-Stage Polynomial Multiplication Accelerator Using 2D Coupled-BFUs
Analysis and Design of a 21.2-to-25.5-GHz Triple-Coil Transformer-Coupled QVCO
A Compact DC-DC Converter With Pulse-Counting MPPT and Fast One-Path Self-Startup for Thermal Energy Harvesting
A High-Sensitivity Wide Input-Power-Range Ultra-Low-Power RF Energy Harvester for IoT Applications
RL-Based Adaptive Optimal Bipartite Consensus Control for Nonlinear Heterogeneous MASs via Event-Triggered State Feedback
Comments on "Fixed-Time Backstepping Fractional-Order Sliding Mode Excitation Control for Performance Improvement of Power System"
PL-NPU: An Energy-Efficient Edge-Device DNN Training Processor With Posit-Based Logarithm-Domain Computing
An Energy-and-Area-Efficient CNN Accelerator for Universal Powers-of-Two Quantization
An Energy-Efficient, Unified CNN Accelerator for Real-Time Multi-Object Semantic Segmentation for Autonomous Vehicle
Multi-Receiver Wireless Power Transfer Systems Using Metasurface-Based Resonator