yusuke1997/dblp-id-title huggingface dataset:
Parallel implementation of neural networks
A Novel Cost-Effective and Programmable VLSI Architecture of CAVLC Decoder for H.264/AVC
An integrated multiplier for complex numbers
Savitzky-Golay Filter Based Quantitative Dynamic Contrast-Enhanced Ultrasound on Assessing Therapeutic Response in Mice with Hepatocellular Carcinoma
Robust Design of Basic Low Voltage CMOS Transconductors
Reconfigurable Computing for Digital Signal Processing: A Survey
Guest Editorial: Advances in Deep Learning for Speech Processing
Memory Access Optimized VLSI for 5000-Word Continuous Speech Recognition
Designs of Approximate Floating-Point Multipliers with Variable Accuracy for Error-Tolerant Applications
FFTs with Near-Optimal Memory Access Through Block Data Layouts: Algorithm, Architecture and Design Automation
High-Precision Real-Time Premature Ventricular Contraction (PVC) Detection System Based on Wavelet Transform
Static scheduling for synthesis of DSP algorithms on various models
Reducing the Complexity of a Multiview H.264/AVC and HEVC Hybrid Architecture
Image Segmentation of Rectal Tumor Based on Improved U-Net Model with Deep Learning
A Novel Model Based on Big Data Environment for Text Content Security Recognition
Variable Partitioning and Scheduling for MPSoC with Virtually Shared Scratch Pad Memory
Fast Discrete Cosine Transform via Computation of Moments
Tradeoffs of Source Coding, Channel Coding and Spreading in Frequency Selective Rayleigh Fading Channels
Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms
Multidimensional DSP Core Synthesis for FPGA
Guest Editorial: New Frontiers in Signal Processing Applications and Embedded Processing Technologies
New Procedure for Estimation of Amplitude and Phase of Analog Multiharmonic Signal Based on the Differential Irregular Samples
Model-Year Architectures for Rapid Prototyping
On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes
Monaural Speech Separation Based on Gain Adapted Minimum Mean Square Error Estimation
Video Rate Controller Development Through Neuro-Fuzzy Quantization Parameter Modifiers
System-Level Data-Flow Transformation Exploration and Power-Area Trade-offs Demonstrated on Video Codecs
IEEE 802.11ac MIMO Transceiver Baseband Processing on a VLIW Processor
Low-Power High-Speed Hybrid Wave-Pipeline Architectures for Binary Morphological Dilation
Lattice Based Transcription Loss for End-to-End Speech Recognition
Monotonic Optimization of Dataflow Buffer Sizes
Hardware/Software Co-reconfigurable Instruction Decoder for Adaptive Multi-core DSP Architectures
Body Sensor Network Based Context-Aware QRS Detection
An Improved Logarithmic Multiplier for Media Processing
Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications
A Lightweight Deep Feature Selection Contour for Emotion Recognition from Human Faces
Optimal-Stopping Spectrum Sensing in Energy Harvesting Cognitive Radio Systems
New Recursive Algorithms for the Unified Forward and Inverse MDCT/MDST
Identification of Shared Components and Sparse Networks in Gene Expression Time-Course Data
Design and Tool Flow of Multimedia MPSoC Platforms
On Detecting Spectrum Opportunities for Cognitive Vehicular Networks in the TV White Space
A Clock Methodology for High-Performance Microprocessors
A Model-Free De-Drifting Approach for Detecting BOLD Activities in fMRI Data
A Low-overhead Scheduling Methodology for Fine-grained Acceleration of Signal Processing Systems
Pipelined HAC Estimation Engines for Multivariate Time Series
Topological Patterns for Scalable Representation and Analysis of Dataflow Graphs
Maximally Informative Feature and Sensor Selection in Pattern Recognition Using Local and Global Independent Component Analysis
Data and Decision Intelligence for Human-in-the-Loop Cyber-Physical Systems: Reference Model, Recent Progresses and Challenges
Brain Image Segmentation Based on the Hybrid of Back Propagation Neural Network and AdaBoost System
An Iterative Algorithm and Low Complexity Hardware Architecture for Fast Acquisition of Long PN Codes in UWB Systems
MSSM - A design aid for multi-stage systolic mapping
Adaptive Energy Weight Based Active Contour Model for Robust Medical Image Segmentation
Automotive Perception System Evaluation with Reference Data from a UAV's Camera Using ArUco Markers and DCNN
A VLSI Architecture of the Square Root Algorithm for V-BLAST Detection
Fault tolerance in FFT arrays: Time redundancy approaches
Fast RLS-Like Algorithm for Generalized Eigendecomposition and its Applications
Evaluation of Static Mapping for Dynamic Space-Shared Multi-task Processing on FPGAs
Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization
Video Super-resolution using Edge-based Optical Flow and Intensity Prediction
On the optimality of linear schedules
Technology Road Map to Methodologies for Mixed-Signal System Design and Simulation
Digital Image Fusion Using HVS in Block Based Transforms
Special Issue on Embedded Vision Architectures for Machine Learning
An all adder systolic structure for fast computation of moments
Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing
Jointly Optimal Region-Classified Adaptive Vector Quantization for Very Low Bit Rate Video Coding
Investigating Deep Neural Network Adaptation for Generating Exclamatory and Interrogative Speech in Mandarin
Synthesis and Optimization of Combinational Interface Circuits
Semi-Supervised Few-Shot Learning Via Dependency Maximization and Instance Discriminant Analysis
Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing
Iterative Semi-Supervised Sparse Coding Model for Image Classification
Reliability-Aware Energy Management for Embedded Real-Time Systems with (m, k)-Hard Timing Constraint
Design of Sparse Filters for Channel Shortening
Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems
High Throughput Entropy Coding in the HEVC Standard
Reconfigurable Digital Channelizer Design Using Factored Markov Decision Processes
Efficient Generalized Integer Division and Modular Reduction Architectures for Homomorphic Encryption
Near-optimal Multiplier-Less Broadband Noise Shaping Filters
A Framework for Representation and Processing of Multi-view Video Using the Concept of Layered Depth Image
3.2 Gbps Channel-Adaptive Configurable MIMO Detector for Multi-Mode Wireless Communication
Performance Analysis of HEVC Scalable Extension for Depth Maps
Geometrical Kernel Machine for Prediction and Novelty Detection of Disruptive Events in TOKAMAK Machines
Scheduling a system of nonsingular affine recurrence equations onto a processor array
A New Euclidean Division Algorithm for Residue Number Systems
Discriminative Boosting Algorithm for Diversified Front-End Phonotactic Language Recognition
A Container-Based Elastic Cloud Architecture for Pseudo Real-Time Exploitation of Wide Area Motion Imagery (WAMI) Stream
New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2 m ) Under Polynomial Basis and Normal Basis Representations
Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications
A Linear Systolic Array for Real-Time Morphological Image Processing
Editorial for the Special Issue on Field Programmable Technology
An Affinity-Based Algorithm in Nonsubsampled Contourlet Transform Domain: Application to Synthetic Aperture Radar Image Denoising
Automatic Non-Invasive Cough Detection based on Accelerometer and Audio Signals
Discrete Orthogonal Multi-transform on Chip (DOMoC)
Unit Selection Speech Synthesis Using Frame-Sized Speech Segments and Neural Network Based Acoustic Models
Mapping Cognitive Radio System Scenarios into the TVWS Context
Formalisation of multi-precision arithmetic for high-level synthesis of DSP architectures
Adaptive Image Watermarking Scheme Using Fuzzy Entropy and GA-ELM Hybridization in DCT Domain for Copyright Protection
Binary Adders on Quantum-Dot Cellular Automata
On the Traffic Offloading in Wi-Fi Supported Heterogeneous Wireless Networks
Impulse Noise Correction in OFDM Systems
Super-Resolution via Sparse Representation for Low-dose X-ray Photography
Large-Scale Pairwise Alignments on GPU Clusters: Exploring the Implementation Space
Interleaving on Parallel DSP Architectures
Integration of GPU Computing in a Software Radio Environment
Lung-Nodule Classification Based on Computed Tomography Using Taxonomic Diversity Indexes and an SVM
Design, Debug, Deploy: The Creation of Configurable Computing Applications
Algorithms to Minimize Data Transfer for Code Update on Wireless Sensor Network
Multidimensional fourier transforms by systolic architectures
Hardware Efficient Fast Computation of the Discrete Fourier Transform
A Content Model for the Mobile Adaptation of Multimedia Information
The Architectural Optimizations of a Low-Complexity and Low-Latency FFT Processor for MIMO-OFDM Communication Systems
Towards Secure and Efficient Scientific Research Project Management Using Consortium Blockchain
Signal Background Estimation and Baseline Correction Algorithms for Accurate DNA Sequencing
A VLSI 8 × 8 MIMO Near-ML Detector with Preprocessing
Dirichlet Priors for MAP Inference of Protein Conformation Abundances from SAXS
SoC Memory Hierarchy Derivation from Dataflow Graphs
3D EM/MPM Image Segmentation Using an FPGA Embedded Design Implementation
Performance and Energy Evaluation of Different Multi-Threading Interfaces in Embedded and General Purpose Systems
An Efficient In-Place VLSI Architecture for Viterbi Algorithm
Control and Data Channel Resource Allocation in OFDMA Heterogeneous Networks
VLSI Implementation of An Adaptive Equalizer for ATSC Digital TV Receivers
Non-Uniform Microphone Arrays for Robust Speech Source Localization for Smartphone-Assisted Hearing Aid Devices
Guest Editorial for Special Issue on the 2005 IEEE Workshop on Machine Learning for Signal Processing
The Design and Construction of a Movable Image-Based Rendering System and Its Application to Multiview Conferencing
Using Heterogeneity to Enhance Random Walk-based Queries
Improved Message Forwarding for Multi-Hop HaRTES Real-Time Ethernet Networks
Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS"
Redundant Constant-Factor Implementation of Multi-Dimensional CORDIC and Its Application to Complex SVD
Low-Power Multiplier Design Using a Bypassing Technique
Guest Editorial: Special Issue on Signal Processing Systems: Part II
A Vlsi Architecture for Separable 2-D Discrete Wavelet Transform
Camera Exposure Determination Based on a Psychometric Quality Model
Effective Filtration Techniques for Gallbladder Ultrasound Images with Variable Contrast
A method for implementation of one-dimensional systolic algorithms with data contraflow using pipelined functional units
Real Time Diagnosis & Fault Detection for the Reliability Improvement of the Embedded Systems
Synthesis for real time systems: Solutions and challenges
Selection of a Closed-Form Expression Polynomial Orthogonal Basis for Robust Nonlinear System Identification
Audio Feature Extraction and Analysis for Scene Segmentation and Classification
Extended Tied-Mixture HMMs for Both Labeled and Unlabeled Time Series Data
Low Complexity On-Line Adaptation Techniques in Context of Assamese Spoken Query System
A High Throughput Processor Chip for Transform and Quantization Coding in H.264/AVC
Wavelet-based Interpolation Scheme for Resolution Enhancement of Medical Images
Ensemble Acoustic Modeling for CD-DNN-HMM Using Random Forests of Phonetic Decision Trees
A Hardware/Software Co-design of High Efficiency AAC Audio Decoder
An Energy-Efficient Hardware Implementation of HOG-Based Object Detection at 1080HD 60 fps with Multi-Scale Support
Design Methodology for Offloading Software Executions to FPGA
Pruning 3D Convolutional Neural Networks via Channel Independence
Adaptation of an Iterative PCA to a Manycore Architecture for Hyperspectral Image Processing
On-Chip and Distributed Dynamic Parallelism for Task-based Hardware Accelerators
Ultra large scale static rams
Research on Resampling and Clustering Method of Aircraft Flight Trajectory
Adaptive Beamforming and DOA Estimation Using Uniform Concentric Spherical Arrays with Frequency Invariant Characteristics
10.07uW Multi-Mode Baseband Transceiver for Encrypted Capsule Endoscopy
Efficient Systolic Designs for 1- and 2-Dimensional DFT of General Transform-Lengths for High-Speed Wireless Communication Applications
The Architecture and Development Flow of the S5 Software Configurable Processor
Virtualized Execution and Management of Hardware Tasks on a Hybrid ARM-FPGA Platform
Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools
Utilization of Pipeline Technique in AOP Based Multipliers with Parallel Inputs
Accelerating OpenVX Application Kernels Using Halide Scheduling
Adaptive Directional Lifting Wavelet Transform VLSI Architecture
A Scalable Configurable Architecture for Advanced Wireless Communication Algorithms
System-on-Chip Subband Decomposition Architectures for Ultrasonic Detection Applications
Adaptable Accelerometer Signal Processing Pipelines for Smartphone based Evenness Estimation
Flexible Controller Design and Its Application for Concurrent Execution of Buffer Centric Dataflows
Parallel implementation of synthetic aperture radar algorithms
Real-Time Traffic Scheduling and Routing in Packet-Switched Networks Using a Least-Laxity-First Strategy
Parameterized Scheduling of Topological Patterns in Signal Processing Dataflow Graphs
Fractional Fourier-Radial Transform for Digital Image Recognition
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors
Low-power architectural synthesis and the impact of exploiting locality
Research and Application of U 2 -NetP Network Incorporating Coordinate Attention for Ship Draft Reading in Complex Situations
A Super-Resolution Imaging Method Based on Dense Subpixel-Accurate Motion Fields
LSTM Network Integrated with Particle Filter for Predicting the Bus Passenger Traffic
Exploiting Task Parallelism with OpenCL: A Case Study
Further Reducing the Redundancy of a Notation Over a Minimally Redundant Digit Set
A Novel Redundant Binary Number to Natural Binary Number Converter
A Public Chinese Dataset for Language Model Adaptation
Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles
Multimodal Cardiovascular Information Monitor Using Piezoelectric Transducers for Wearable Healthcare
Properties and Algorithms for Unfolding of Probabilistic Data-Flow Graphs
Performance of the H.263 Video Compression Standard
Correction to: Web Load Balancing Based on DNS Coordination and Reducing Energy Consumption Strategy
High-speed VLSI arithmetic processor architectures using hybrid number representation
Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding
Latest Advances on Design and Implementation of DSP Systems
Biorthogonal Recombination Nonuniform Cosine-Modulated Filter Banks and their Multiplier-Less Realizations
The Conceptual-Level Design Approach to Complex Systems
Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study
Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing Applications
Combining Coarse-Grained Software Pipelining with DVS for Scheduling Real-Time Periodic Dependent Tasks on Multi-Core Embedded Systems
Systolic architectures for adaptive multichannel least squares lattice filters
Vlsi programmable digital filter for video signal processing
Improving the Performance of Hyperspectral Image and Signal Processing Algorithms Using Parallel, Distributed and Specialized Hardware-Based Systems
An Energy-Efficient Reconfigurable ASIP Supporting Multi-mode MIMO Detection
VLSI-Implementation-Based Fast Symbol Detector for PQSM MIMO Systems
Discrete Lagrangian Methods for Designing Multiplierless Two-Channel PR-LP Filter Banks
Design and Experimental Evaluation of a Database-Assisted V2V Communications System Over TV White Space
Secure Routing Strategy Based on Attribute-Based Trust Access Control in Social-Aware Networks
A Low Complexity Reconfigurable Multi-stage Channel Filter Architecture for Resource-Constrained Software Radio Handsets
A Radix-10 BKM Algorithm for Computing Transcendentals on Pocket Computers
A Fixed-Point Neural Network Architecture for Speech Applications on Resource Constrained Hardware
A low-overhead scheme for testing a bit-level finite ring systolic array
Implementations of Sorted-QR Decomposition for MIMO Receivers: Complexity, Reusability and Efficiency Analysis
A Clinical Application of Ensemble ICA to the Quantification of Myocardial Blood Flow in Dynamic H 15 2 O H^{{15}}_{2} O PET
Signal Assignment Model for the Memory Management of Multidimensional Signal Processing Applications
Comparison of Cell Sizes for Cost Efficient Deployment of a Sensor Network Aided Cognitive Radio System
On Blind Timing Acquisition and Channel Estimation for Wideband Multiuser DS-CDMA Systems
On the Implementation of a Hardware Architecture for an Audio Data Hiding System
An Efficient FPGA-based Implementation of Fractional Fourier Transform Algorithm
New Distortion Metric for Efficient JPEG Steganography Using Linear Prediction
Low-Resolution Architectures for Power-Efficient Scaling of mmWave Phased Array Receivers
Run-Time Reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs
Focal Plane Implementation of 2D Steerable and Scalable Gabor-Type Filters
Neural Successive Cancellation Flip Decoding of Polar Codes
Training Classifiers for Tree-structured Categories with Partially Labeled Data
Low Complexity Implementation of OTFS Transmitter using Fully Parallel and Pipelined Hardware Architecture
Multimedia Signal Processors: An Architectural Platform with Algorithmic Compilation
A Memory Reliability Enhancement Technique for Multi Bit Upsets
An Image Mosaic Method Based on Convolutional Neural Network Semantic Features Extraction
Informed Prefetching for Distributed Multi-Level Storage Systems
Guest editor's introduction design environments for DSP
The Advanced Architecture On-board Processor signal processing testbed
An Efficient High-Throughput LZ77-Based Decompressor in Reconfigurable Logic
A Constrained Monitoring Protocol for the Internet of Things
A Single-Pass Connected Component Labeler without Label Merging Period
Hardware Implementation of a Fixed-Point Decoder for Low-Density Lattice Codes
Genetic Algorithm-based Adaptive Optimization for Target Tracking in Wireless Sensor Networks
A 4μW Low-Power Audio Processor System for Real-Time Jaw Movements Recognition in Grazing Cattle
The Impact of Cache and Dynamic Memory Management in Static Dataflow Applications
An Efficient VLSI Architecture for Full-Search Block Matching Algorithms
Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling
On-Device Partial Learning Technique of Convolutional Neural Network for New Classes
DNA Encoded Color Image Encryption Based on Chaotic Sequence from Neural Network
In-place memory management of algebraic algorithms on application specific ICs
Configurable hardware: Two case studies of micro-grain computation
Dynamic Learning with the EM Algorithm for Neural Networks
Dynamic Assignment of Gaussian Components in Modelling Speech Spectra
A VLSI structure for X (mod m ) operation
Foveation-Based Error Resilience and Unequal Error Protection over Mobile Networks
An Auto-tuning Assisted Power-Aware Study of Iris Matching Algorithm on Intel's SCC
A Comparison of Variational and Markov Chain Monte Carlo Methods for Inference in Partially Observed Stochastic Dynamic Systems
Multi-directional Hole Filling Method for Virtual View Synthesis
Low-Power FPGA-Implementation of atan ( Y / X ) Using Look-Up Table Methods for Communication Applications
Instruction Scheduling for Low Power
An Efficient Curve-Scanline Intersection Locator Design for 2D Graphics Rendering
Efficient Loop Scheduling for Chip Multiprocessors with Non-Volatile Main Memory
Rapid Synthesis and Simulation of Computational Circuits in an MPPA
Seamless Dynamic Runtime Reconfiguration in a Software-Defined Radio
A FlexRay Transceiver Design with Bus Guardian for In-car Networking Systems Compliant with FlexRay Standard
Design Strategy for Clocking and Runtime Parametrization in the Channelization Accelerator of Multistandard Radios
Concept and Construction Example of an Interactive Movie System
Application-specific Processor Architecture: Then and Now
High-Speed Reconfigurable Parallel System to Design Good Error Correcting Codes in Communications
HARP2: An X-Scale Reconfigurable Accelerator-Rich Platform for Massively-Parallel Signal Processing Algorithms
Design and Implementation of a Power-aware FFT Core for OFDM-based DSA-enabled Cognitive Radios
Design and Analysis of an Efficient Evolutionary Image Segmentation Algorithm
Low-Complexity High-Throughput Bit-Wise LDPC Decoder
PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision
Kaczmarz Projection Algorithms with Rank Two Gain Update
Finding Space-Time Transformations for Uniform Recurrences via Branching Parametric Linear Programming
Scalable Gaussian Normal Basis Multipliers over GF(2 m ) Using Hankel Matrix-Vector Representation
Blind Stochastic Feature Transformation for Channel Robust Speaker Verification
Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder
Fractional Rate Dataflow Model for Efficient Code Synthesis
Efficient Reconfigurable Mixed Precision ℓ 1 Solver for Compressive Depth Reconstruction
Enabling Dynamic System Integration on Maxeler HLS Platforms
The Implementation of a VHDL-AMS to SPICE Converter
Computer Vision Accelerators for Mobile Systems based on OpenCL GPGPU Co-Processing
A Stage-Wise Soft-Error Detection Scheme for Flip-Flop Based Pipelines in Secure Cloud Servers
Correction to: Non-Uniform Microphone Arrays for Robust Speech Source Localization for Smartphone-Assisted Hearing Aid Devices
Pipeline interleaving design for FIR, IIR, and FFT array processors
Hardware Implementation of FAST Algorithm for Mobile Applications
Design of a Residue Number System Based Linear System Solver in Hardware
An Intelligent Framework for Automatic Breast Cancer Classification Using Novel Feature Extraction and Machine Learning Techniques
Estimating Brain Deformation During Surgery Using Finite Element Method: Optimization and Comparison of Two Linear Models
A Skin Cancer Classification Approach using GAN and RoI-Based Attention Mechanism
Data Masking: A New Approach for Steganography?
Guest Editorial: Signal Processing for Ultra High Performance and High Efficiency in 5G Mobile Networks
High Throughput, Scalable VLSI Architecture for Block Matching Motion Estimation
An Iterative Algorithm for tagSNP Selection Based on Information Entropy Analysis
Negative Save Sign Extension for Multi-term Adders and Multipliers
Efficient VLSI Architectures of Convolution based DWT using Bit Accumulation
Initializing RAM-based logarithmic processors
Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical Imaging
Subsetting Behavioral Intellectual Property for Low Power ASIP Design
PipeBERT: High-throughput BERT Inference for ARM Big.LITTLE Multi-core Processors
Editor's Note: Special Issue on Application-specific Systems, Architectures and Processors
Dynamic Scheduling and Real-Time Rendering for Large-Scale 3D Scenes
Modeling Stream-Based Applications Using the SBF Model of Computation
Efficient Attitude Estimators: A Tutorial and Survey
On the Ergodic Capacity and Energy Efficiency for Fading MIMO NOMA Systems
Predictive Distribution of the Dirichlet Mixture Model by Local Variational Inference
Coarse Grained Reconfigurable Array Based Architecture for Low Power Real-Time Seizure Detection
Guest Editorial: Special Issue on Embedded Multicore Applications and Optimization
On Interactive Object Shape Modeling Using Algebraic Curves