yusuke1997/dblp-id-title huggingface dataset:
Hardware-efficient algorithm and architecture design with memory and complexity reduction for semi-global matching
The effect of ECG data variability on side-channel attack success rate in wearable devices
SystemC-AMS modeling of photodiode based on PWL technique to be used in energy harvesting CMOS image sensor
A 2d channel router for the diagonal model
VLSI computing architectures for Ising model simulation
A new post-processing approach for improvement of nonlinearity property in substitution boxes
A systolic VLSI matrix for a family of fundamental searching problems
ECO routing based on network flow method
Modern development methods and tools for embedded reconfigurable systems: A survey
Optimization of NULL convention self-timed circuits
Low power time-domain rail-to-rail comparator with a new delay element for ADC applications
Optimization of the V T control method for low-power ultra-thin double-gate SOI logic circuits
Compaction of CD(2 k - D) control unit architectures
Direct digital-to-RF converter employing semi-digital FIR voltage-mode RF DAC
Efficient, reliable, and secure PUF architecture with temperature invariance and ML attack resilience
A novel high-throughput method for table look-up based analog design automation
Design and application of multiscroll chaotic attractors based on memristors
A low-power wide tuning-range CMOS current-controlled oscillator
Two efficient synchronous <--> asynchronous converters well-suited for networks-on-chip in GALS architectures
New partitioned domino circuit for power-efficient wide gates
Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architecture
Network-on-Chip design and synthesis outlook
A parametric, scalable and efficient architecture for schoolbook polynomial multiplier for lattice-based cryptography
Generic integration infrastructure for IP-based design processes and tools with a unified XML format
Towards an automated design flow for memristor based VLSI circuits
Optimal gate sizing using a self-tuning multi-objective framework
Novel state minimization and state assignment in finite state machine design for low-power portable devices
First-order universal filters with two CCII+s and a grounded capacitor: Theory and experimental validation
Parallel implementations of the statistical cooling algorithm
Partitioning of processor arrays: a piecewise regular approach
Edge effect aware low-power crosstalk avoidance technique for 3D integration
A versatile Nyquist-rate A/D converter with 16-18 bit performance for sensor readout applications
Alternative method to reveal encoded images via Gaussian distribution functions
AMS/RF-CMOS circuit design for wireless transceivers
An ASIC design and formal analysis of a novel pipelined and parallel sorting accelerator
Fast execution for circuit consistency verification
Fast locking, startup-circuit free, low area, 32-phase analog DLL
Integrating firewire peripheral interface with an ethernet custom network processor
Universal gates as a cornerstone for next-generation configurable ring oscillator PUFs
Rapid design space exploration using legacy design data and technology scaling trend
Row-structure stencil planning approaches for E-beam lithography with overlapped characters
High-resolution calibrated successive-approximation-register analog-to-digital converter
Generating new benchmark designs using a multi-terminal net model
Shaping a VLSI wire to minimize Elmore delay with consideration of coupling capacitance
Reordering method of test set based on vector eigenvalues using critical area estimation
A hybrid memory polynomial digital predistortion model for RF transmitters
Optimal and heuristic algorithms to synthesize lattices of four-terminal switches
Stretching and three-layer wiring planar layouts
Reliable techniques for integrated circuit identification and true random number generation using 1.5-transistor flash memory
CAPE: A cross-layer framework for accurate microprocessor power estimation
Hierarchical Krylov subspace based reduction of large interconnects
Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults
Four-input-C-element-based multiple-node-upset-self-recoverable latch designs
A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process
Speeding-up neuromorphic computation for neural networks: Structure optimization approach
WF-SPR: A weighted single fanout approach for signal probability-based reliability estimation
A 15.13 mW 3.2 GHz 8-bit carry look-ahead adder using single-phase all-N-transistor logic
Accelerating cycle-accurate system-level simulations through behavioral templates
Efficient VLSI architecture of 3D discrete transformation
A mechanism for detecting on-chip radio frequency interference of field-programmable gate array
An integral matrix-based technique for systematic systolic design
Authors' reply to "A note on architectures for large-capacity CAMs"
Low-power compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel XOR Gate
A 85dB-SNDR 50 kHz bootstrapping-free resistor-less SC Delta-Sigma modulator IP block for PVT-robust low-power ADCs
Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits
Testable PLA design with minimal overheads
Multi-dimensional parallel computing structures for regular iterative algorithms
Design and implementation of a second order PLL based frequency synthesizer for implantable medical devices
Low computational complexity digital predistortion for power amplifiers based on A-CNN-GRU
All MOS noise-shaped time-mode temperature sensor
Compact MAX and MIN Stochastic Computing architectures
Real-time medical image encryption for H-IoT applications using improved sequences from chaotic maps
A synchronous latency-insensitive RISC for better than worst-case design
Hashchip: A shared-resource multi-hash function processor architecture on FPGA
Optimized design of parallel carry-select adders
Asynchronous control of modules activity in integrated systems for reducing peak temperatures
Full-chip multilevel routing for power and signal integrity
MOSCAP compensation of three-stage operational amplifiers: Sensitivity and robustness, modeling and analysis
Extended-chip-on-board (e-COB) heterogeneous integration of LEDs with LED drivers
30 GHz SiGe active inductor with voltage controlled Q
Integrated DC - DC converter design methodology for design cycle speed up
iCOACH: A circuit optimization aid for CMOS high-performance circuits
Implementation of real-time image edge detector based on a bump circuit and active pixels in a CMOS image sensor
A modified noising algorithm for the graph partitioning problem
A survey on vertical interconnection and topology of three-dimensional network-on-chip
An efficient macro-cell placement algorithm
A two stage cascode LNA using modified derivative superposition technique in 0.13μm HBT with an IIP3 of 2 dBm and NF of 4.8 dB for IEEE 802.11ad standard
Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI
Guest editors' introduction to the special issue on asynchronous systems
3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing
Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study
Loosely coupled multi-bit flip-flop allocation for power reduction
Formal specification and verification of microprocessor systems
VLSI layout of binary tree structures
Area Constrained Performance Optimized ASNoC Synthesis with Thermal‐aware White Space Allocation and Redistribution
Efficient hardware mapping of Boolean substitution boxes based on functional decomposition for RFID and ISM band IoT applications
Challenges of cell selection algorithms in industrial high performance microprocessor designs
Lightweight encryption mechanism with discrete-time chaotic maps for Internet of Robotic Things
An ultra low-power current-mode clock and data recovery design with input bit-rate adaptability for biomedical applications in CMOS 90 nm
High-Precision Spatial Filtering with AI-driven control and multicolor laser testing for interferometric application
Design and analysis of VDIBA-based chaotic oscillators and their applications in communication system
Design and FPGA implementation of a novel cryptographic secure pseudo random number generator based on artificial neural networks and chaotic systems
Clustered checkpointing: Maximizing the level of confidence for non-equidistant checkpointing
Energy-efficient architecture for high-performance FIR adaptive filter using hybridizing CSDTCSE-CRABRA based distributed arithmetic design: Noise removal application in IoT-based WSN
Crosstalk fault modeling in defective pair of interconnects
HashHeat: A hashing-based spatiotemporal filter for dynamic vision sensor
An efficient open-source design and implementation framework for non-quantized CNNs on FPGAs
Design and implementation of current mode circuit for digital modulation
FPGA implementation of PUF based key generator for secure communication in IoT
A new modeling technique for mixed-mode simulation of CMOS circuits
Application driven routing for mesh based Network-on-Chip architectures
Refinement rules for the automatic TLM-to-RTL conversion of temporal assertions
Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS
Radiation-aware analog circuit design via fully-automated simulation environment
Minimizing detection-to-boosting latency toward low-power error-resilient circuits
On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs
Enhancing logic optimization of Alliance tool based on directed acyclic graphs
Optimal design of a low-power, phase-switching modulator for implantable medical applications
Hardware trojans in 3-D ICs due to NBTI effects and countermeasure
UA 2 TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs
A new approach to the multiport memory allocation problem in data path synthesis
An attractor-controllable memristive Hopfield neural network and its application on voice encryption
ProHys PUF: A Proteresis - Hysteresis switch based Physical Unclonable Function
A Parity-based Multi-bit Fault-Tolerant Instruction Decoder for RISC-V pipelined soft processor
Design of UWB low noise amplifier using noise-canceling and current-reused techniques
Thermal aware placement in 3D ICs using quadratic uniformity modeling approach
Designing efficient FPGA tiles for power-constrained ultra-low-power applications
Edge computing design space exploration for heart rate monitoring
A new parallel hardware architecture for high-performance stereo matching calculation
An heuristic SPICE2-based approach for 2D IIL device simulation
An effective algorithm for optimal PLA column folding
Breaking LPA-resistant cryptographic circuits with principal component analysis
Refinement based techniques for mapping nested loop algorithms onto linear systolic arrays
W-IQ: Wither-logic based issue queue for RISC-V superscalar out-of-order processor
Maximum weighted independent sets on transitive graphs and applications1
Cross-channel image chain scrambling encryption algorithm using two memristor-based twin multi-scroll hyperchaotic systems
High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic
AMOLED pixel driver circuits based on poly-Si TFTs: A comparison
A functional block decomposition method for automatic op-amp design
Computer algebra and logic programming
Electronically tunable positive and negative fractional order inductor circuit using single topology
Quantization aware approximate multiplier and hardware accelerator for edge computing of deep learning applications
Efficient CNFET-based ternary logic design with emphasis on half-adder and multiplier circuits
Sparse matrix superchip: A reconfigurable architecture for VLSI processing arrays
Heterogenous ensemble learning driven multi-parametric assessment model for hardware Trojan detection
Γ (Gamma): A SaaS-enabled fast and accurate analog design System
Energy-efficient canonical Huffman decoders on many-core processor arrays and FPGAs
Hardware for bioinformatics applications
An all-digital frequency tunable IR-UWB transmitter with an approximate 15th derivative Gaussian pulse generator
Multi-cell lightweight high-throughput TRNG based on selector clock driving and XOR feedback
Normalization and dropout for stochastic computing-based deep convolutional neural networks
Inexact radix-4 Booth multipliers based on new partial product generation scheme for image multiplication
Fast low energy RNS comparators for 4-moduli sets {2 n ±1, 2 n , m} with m∈{2 n+1 ±1, 2 n-1 -1}
Post-process die-level electromagnetic field analysis on microwave CMOS low-noise amplifier for first-pass silicon fabrication success
Valid test pattern identification for VLSI adaptive test
High speed VLSI architecture for improved region based active contour segmentation technique
Memory device based on memristor-diode crossbar and control CMOS logic for spiking neural network hardware
Parallel GMRES solver for fast analysis of large linear dynamic systems on GPU platforms
Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design
IPRAIL - intellectual property reuse-based analog IC layout automation
An analytical placement algorithm with looking-ahead routing topology optimization
Optimization and CMOS design of chaotic oscillators robust to PVT variations: INVITED
A highly linear current-starved VCO based on a linearized current control mechanism
JoBiS: Joint capacitance and inductance bit stuffing CAC for interposer based multi-chip Deep Learning Accelerator
Adaptive congestion-aware high performance scalable 2-D and 3-D topologies for network-on-chip based interconnect for quantum computing
A new family of CMOS inverter-based OTAs for biomedical and healthcare applications
A tunable highly linear CMOS transconductor with 80 dB of SFDR
Design and simulation of an ultra-low power high performance CMOS logic: DMTGDI
Energy and power awareness in hardware schedulers for energy harvesting IoT SoCs
3D-multiscroll chaotic attractors design, circuit implementation and application to medical image encryption
Automatic generation of test infrastructures for analog integrated circuits by controllability and observability co-optimization
Corrigendum to "On minimizing charge injection error using multi-dummy switches with enhanced linearity" [Integration volume 97 (2024) 102175]
A global router based on a multicommodity flow model
Kernel-based template attacks of cryptographic circuits using static power
Modelling, analysis and synthesis of asynchronous control circuits using Petri nets
Orbital circuit elements table: A novel approach to elementary circuit elements
Rapid and coding-efficient SPIHT algorithm for wavelet-based ECG data compression
Yield constrained automated design algorithm for power optimized pipeline ADC
An algorithm and architecture based on orthonormal μ-rotations for computing the symmetric EVD
Resource efficient LDPC decoders for multimedia communication
Chaos-based authentication of encrypted images under MQTT for IoT protocol
A new die-level flexible design-for-test architecture for 3D stacked ICs
On optimizing system energy of voltage-frequency island based 3-D multi-core SoCs under thermal constraints
Ringed bit-parallel systolic multipliers over a class of fields GF(2 m )
A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models
Low overhead online periodic testing for GPGPUs
Unified data path allocation and BIST intrusion
On improving the quality of simple graphics
Charge shared based low power and high-speed dynamic comparator for high frequency analog signal processing architecture
An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture
A novel locally active memristive autapse-coupled Hopfield neural network under electromagnetic radiation
Multi-channel lock-in based differential front-end for broadband Raman spectroscopy
A low-power 6-bit MOS CML flash ADC with a novel multi-segment encoder for UWB applications
A low-power common-mode insensitive rail-to-rail dynamic comparator for ADCs
A low power RFID based energy harvesting temperature resilient CMOS-only reference voltage
Heuristic approaches to energy optimization in deep submicron bus design through QAP formulation
Exact ESOP expressions for incompletely specified functions
CTSNet: Collaborative temporal-spatial net with dual-branch cross-attention for dynamic IR drop prediction
Verification of a high precision CMOS sensor for angle-of-arrival (AOA) measurement of LED light in ultra-miniaturized applications
Recent advances in EM and BTI induced reliability modeling, analysis and optimization (invited)
A four-dimensional chaotic system with coexisting attractors and its backstepping control and synchronization
Fast, compact and symmetric modular exponentiation architecture by common-multiplicand Montgomery modular multiplications
Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction
Versatile multiplier architectures in GF(2 k ) fields using the Montgomery multiplication algorithm
CMOS analogue current-mode multiplier/divider circuit operating in triode-saturation with bulk-driven techniques
An efficient estimation of the ROBDD's complexity
Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design
Hardware footprints of S-box in lightweight symmetric block ciphers for IoT and CPS information security systems
Reducing process variation impact on replica-timed static random access memory sense timing
High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications
Survey on recent counterfeit IC detection techniques and future research directions
Stochastic logical effort as a variation aware delay model to estimate timing yield
Plug N' PIM: An integration strategy for Processing-in-Memory accelerators
Secure access microcontroller system based on fingerprint template with hyperchaotic encryption
Grid stretching algorithms for routing multiterminal nets through a rectangle
Monolithic 3D neuromorphic computing system with hybrid CMOS and memristor-based synapses and neurons
A robust Euclidean metric based ID extraction method using RO-PUFs in FPGA
Delay-insensitive gate-level pipelining
AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL
Input match and load tank digital calibration of an inductively degenerated CMOS LNA
Intelligent and kernelized placement: A survey
Nested chopper instrument amplifier with noise modulation for physiological signal sensing
Feed-through river routing
Designs for efficient low power cardinality and similarity sketches by Two-Step Hashing (TSH)
Self calibrated cooler-less microbolometer readout architecture
Multi-bit error detection and correction technique using HVDK (Horizontal-Vertical-Diagonal-Knight) parity
Development of a large word-width high-speed asynchronous multiply and accumulate unit
A mixed-signal pulse width modulator for portable SMPS applications
SDCLR: Scalable Dual Control-Layer Routing for continuous-flow microfluidic biochips with minimized control ports
A low-area, 43.5% PAE, 0.9 W, Class-E differential power amplifier in 2.4 GHz for IoT applications
Extrinsic calibration of complex machine vision system for mobile robot
Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB
VLSI architecture for device simulation
CLASS: a CAD system for automatic synthesis and verification of asynchronous finite state machines
EOHEAA: Error-Optimized Hardware-Efficient Approximate Adder for energy-aware error-resilient applications
Highly-parallel hardware implementation of optimal ate pairing over Barreto-Naehrig curves
Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications
Cluster-based delta-QMC technique for fast yield analysis
Real-time automated register abstraction active power-aware electronic system level verification framework
Simple method of asynchronous circuits implementation in commercial FPGAs
X-RAM: a novel and efficient multi-ported memory for AI accelerator
Design of A prototype 128 × 128 ROIC array for 2.6 μm-wavelength SWIR image sensor applications
An efficient quadratic placement based on search space traversing technology
VLSI implementation of a digital image threshold selection architecture
SAND-2: An optimized implementation of lightweight block cipher
An efficient technique for obtaining unate implementation of functions through input encoding
Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment
Design and process variation analysis of CNTFET-based ternary memory cells
Inductorless dynamic logic based on 2 ϕ -Josephson junctions
A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs
Concurrent built-in self-testing under the constraint of shared test resources and its test time reduction
Impact of losses and mismatches on power and efficiency of Wireless Power Transfer Systems with controlled secondary-side rectifier
FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits
Resonant amplifier-based sub-harmonic mixer for zero-IF transceiver applications
3-Path SiGe BiCMOS power amplifier on thinned substrate for IoT applications
In -memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC)
Scaling trends of power noise in 3-D ICs
Design of an SRAM-bitcell with enhanced self-recoverability from soft errors for space and critical terrestrial applications
A local positive feedback loop-reused technique for enhancing performance of folded cascode amplifier
A machine learning-based design automation framework for differential mmWave LNAs
Revisiting 3DIC benefit with multiple tiers
A pre-silicon logic level security verification flow for higher-order masking schemes against glitches on FPGAs
Testing of non-feedback bridging faults
A CMOS circuit for ultra high frequency chaos generation utilizing a Clapp oscillator with dual memristors
Circuit design of a dual-versioning L1 data cache
Co-AGSA: An efficient self-adaptive approach for constrained optimization of analog IC based on the shrinking circles technique
Customizable embedded processor array for multimedia applications
A full-scale solution to the rectilinear obstacle-avoiding Steiner problem
MASHER: An automatic VLSI layout system
Yield optimization in wafer scale circuits with hierarchical redundancies
NBTI-aware adaptive minimum leakage vector selection using a linear programming approach
A simulated annealing multi-layer router
Explicit formulae for Mastrovito matrix and its corresponding Toeplitz matrix for all irreducible pentanomials using shifted polynomial basis
Design and analysis of a flat gain and linear low noise amplifier using modified current reused structure with feedforward structure
A novel memristive chaotic system without any equilibrium point
An exact algorithm for wirelength optimal placements in VLSI design
Harvester-aware transient computing: Utilizing the mechanical inertia of kinetic energy harvesters for a proactive frequency-based power loss detection
A highly robust RF 65 nm CMOS power amplifier design using Quasi-Newton control algorithm for wireless system
Erratum to "VLSI based fuzzy logic controller enabled adaptive interactive multiple model for target tracking" [Integration 35 (2003) 1-10]
2-Dimensional minimum cost path planning using a cellular automaton architecture
A low-jitter and low-phase noise switched-loop filter PLL using fast phase-error correction and dual-edge phase comparison technique
A new 3-layer rectilinear area router with obstacle avoidance