yusuke1997/dblp-id-title huggingface dataset:
Authenticated Group Key Transfer Protocol Based on Secret Sharing
The Effects of Races, Delays, and Delay Faults on Test Generation
Combining Crypto with Biometrics Effectively
A Parallel Hardware Architecture for Real-Time Object Detection with Support Vector Machines
A Note on Open Shop Preemptive Schedules
On the Precision Attainable with Various Floating-Point Number Systems
Implementation of a Constrained Regularization Program (CONTIN) on a Desktop Computer
Modeling and Measurement of Error Propagation in a Multimodule Computing System
Software Support and Evaluation of Hardware Transactional Memory on Blue Gene/Q
Efficient and Consistent NVMM Cache for SSD-Based File System
Time-Multiplexed Online Checking
An Optimal Wide-Sense Nonblocking Distributor
Scalable Montgomery Modular Multiplication Architecture with Low-Latency and Low-Memory Bandwidth Requirement
Implementing Synchronous Models on Loosely Time Triggered Architectures
Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller
Computer Performance Evaluation Methodology
Synchronization of Fault-Tolerant Clocks in the Presence of Malicious Failures
Uniqueness of Weighted Code Representations, III
Software-Based Cache Coherence with Hardware-Assisted Selective Self-Invalidations Using Bloom Filters
Language Correction Using Probabilistic Grammars
Syndrome-Testing of "Syndrome-Untestable" Combinational Circuits
Evaluations on Deep Neural Networks Training Using Posit Number System
Error-Checking Logic for Arithmetic-Type Operations of a Processor
Application-Support Particle Filter for Dynamic Voltage Scaling of Multimedia Applications
High-Speed Multiprocessors and Compilation Techniques
A Distributed Coverage- and Connectivity-Centric Technique for Selecting Active Nodes in Wireless Sensor Networks
Woven Wire Memory for NDRO System
Diagnosis and Fault Equivalence in Combinational Circuits
A Decentralized Damage Detection System for Wireless Sensor and Actuator Networks
Stackless Multi-Threading for Embedded Systems
Implementation of Ternary Circuits with Binary Integrated Circuits
MPS: Miss-Path Scheduling for Multiple-Issue Processors
Reed-Solomon Coding Algorithms Based on Reed-Muller Transform for Any Number of Parities
Software Defined Monitoring of Application Protocols
File Allocation in a Distributed Computer Communication Network
Strongly Diagnosable Systems under the Comparison Diagnosis Model
Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking
Branch Prediction, Instruction-Window Size, and Cache Size: Performance Trade-Offs and Simulation Techniques
One-Level Storage System
Failure Dependent Performance Analysis of a Fault-Tolerant Multistage Interconnection Network
Experiments with "Characteristic Loci" for Recognition of Handprinted Characters
A Performance Study of Instruction Cache Prefetching Methods
A B-Tree Dynamic Router-Table Design
Diagnosis of Scan Cells in BIST Environment
Serving Multi-DNN Workloads on FPGAs: A Coordinated Architecture, Scheduling, and Mapping Perspective
B74-20 Systematic Programming: An Introduction
Serial-to-Parallel Transformation of Linear-Feedback Shift-Register Circuits
Design and Properties of a New Pseudorandom Generator Based on a Filtered FCSR Automaton
Evaluation of a Flexible Task Scheduling Algorithm for Distributed Hard Real-Time Systems
Estimating the Reliability of Regeneration-Based Replica Control Protocols
The UNIVAC Tube Program
An Algorithm for Automatic Design of Logical Cryogenic Circuits
Bibliography on magnetostrictive delay lines
Self-Diagnosis in Distributed Systems
Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance
Error Analysis of Approximate Chinese-Reminder-Theorem Decoding
A Universal Cellular Array
Nicaea: A Byzantine Fault Tolerant Consensus Under Unpredictable Message Delivery Failures for Parallel and Distributed Computing
A Simple Algorithm for Evaluating Positive Values of the Function x y
Design of Parity Testable Combinational Circuits
Serial Binary Division by Ten
The Universality of a Class of Modified Single-Stage Shuffle/Exchange Networks
A Tree Storage Scheme for Magnetic Bubble Memories
Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization
Collaborative Accelerators for Streamlining MapReduce on Scale-up Machines With Incremental Data Aggregation
Better Adaptive Diagnosis of Hypercubes
Comments on "Multiprocessor Scheduling with Memory Allocation - A Deterministic Approach"
A Class of Rate-Based Real-Time Scheduling Algorithms
Performance Analysis Using Stochastic Petri Nets
Comments on "A Measure of Computational Work"
An Improvement of the Elliptic Net Algorithm
Constant-Weight Counters and Decoding Trees
Self-Synchronized Encryption for Physical Layer in 10Gbps Optical Links
Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem
Rank-Level Parallelism in DRAM
DAHE: Parameter-Adaptive and Memory Efficient FPGA Acceleration of Homomorphic Encryption
Automatic Digital Programming of Analog Computers
Efficient Distributed Algorithms for Self Testing of Multiple Processor Systems
Efficient, Flexible, and Constant-Time Gaussian Sampling Hardware for Lattice Cryptography
Adaptive Load Distribution Strategies for Divisible Load Processing on Resource Unaware Multilevel Tree Networks
Detailed Modeling and Reliability Analysis of Fault-Tolerant Processor Arrays
An automatic cruise control computer for long range aircraft
Estimates for Best Placement of Voters in a Triplicated Logic Network
Custom CMOS Ising Machine Based on Relaxed Burer-Monteiro-Zhang Heuristic
Fault Detection in Multiprocessor Systems and Array Processors
Counting Responders in an Associative Memory
ELmD: A Pipelineable Authenticated Encryption and Its Hardware Implementation
A Triple Modular Redundancy Technique Providing Multiple-Bit Error Protection Without Using Extra Redundancy
Deriving Unbounded Reachability Proof of Linear Hybrid Automata during Bounded Checking Procedure
A stabilized driftless analog integrator
The Diagnosis of Asynchronous Sequential Switching Systems
Anomalous Behavior of Synchronizer and Arbiter Circuits
Fault Tolerance on Large Scale Systems using Adaptive Process Replication
Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns
Comments on "Signature Analysis for Multiple Output Circuits"
Design and Use of Fault Simulation for Saturn Computer Design
A 2.18-Microsecond Megabit Core Storage Unit
Extending Magny-Cours Cache Coherence
Bilateral Switching Using Nonsymmetric Elements
HashScape: Leveraging Virtual Address Dynamics for Efficient Hashed Page Tables
A Simple Technique for Determination of Essential Multiple Output Prime Implicants
Binary Search Revisited: Another Advantage of Fibonacci Search
Markov Regenerative Stochastic Petri Nets to Model and Evaluate Phased Mission Systems Dependability
Elliptic Curve Cryptography Point Multiplication Core for Hardware Security Module
Asynchronous Sequential Circuits with Feedback
Locatability of Faults in Combinational Networks
Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums
New CRT-Based RNS Converter Using Restricted Moduli Set
The Polish Assembler
On Winograd's Algorithm for Inner Products
Concurrent Error Detection in Montgomery Multiplication over Binary Extension Fields
Linear Dependencies in Linear Feedback Shift Registers
High-Speed Booth Encoded Parallel Multiplier Design
Computation of the Base Two Logarithm of Binary Numbers
Broadcast Normalization in Systolic Design
Enabling High-Efficient ReRAM-Based CNN Training Via Exploiting Crossbar-Level Insignificant Writing Elimination
Leveraging Register Windows to Reduce Physical Registers to the Bare Minimum
Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions
Controllable Testing from Nondeterministic Finite State Machines with Multiple Ports
Estimating Metrical Change in Fully Connected Mobile Networks - A Least Upper Bound on the Worst Case
Computer-Aided Preliminary Layout Design of Customized MOS Arrays
Bit-Sequential Arithmetic for Parallel Processors
Analysis of Checksums, Extended-Precision Checksums, and Cyclic Redundancy Checks
Coverage Modeling for Dependability Analysis of Fault-Tolerant Systems
Design Method of a Class of Embedded Combinational Self-Testing Checkers for Two-Rail Codes
Single-Domain Generalized Predictor for Neural Architecture Search System
Trading Aggregate Statistics Over Private Internet of Things Data
Realization Methods for Asynchronous Sequential Circuits
An Approach to Implementing Multiplication with Small Tables
Mission Reliability, Cost and Time for Cold Standby Computing Systems with Periodic Backup
R68-37 Intercommunication of Processors and Memory
The Constrained-Input Problem
Notes on Shuffle/Exchange Type Permutation Sets
Clock Synchronization of a Large Multiprocessor System in the Presence of Malicious Faults
An Algebraic Model for Asynchronous Circuits Verification
The Conservativeness of Reliability Estimates Based on Instantaneous Coverage
Accelerating Sparse DNNs Based on Tiled GEMM
9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits
A Prefetch Taxonomy
On Embedding Rectangular Grids in Square Grids
ASSER: An Efficient, Reliable, and Cost-Effective Storage Scheme for Object-Based Cloud Storage Systems
Software-Based Self-Testing of Embedded Processors
Security Relevant Methods of Android's API Classification: A Machine Learning Empirical Evaluation
Performance Evaluation of Hierarchical Ring-Based Shared Memory Multiprocessors
Evaluation of Fault Tolerance Latency from Real-Time Application's Perspectives
Energy-Efficient Multihop Polling in Clusters of Two-Layered Heterogeneous Sensor Networks
Enabling High Performance and Resource Utilization in Clustered Cache via Hotness Identification, Data Copying, and Instance Merging
Scenario-Based AI Benchmark Evaluation of Distributed Cloud/Edge Computing Systems
Star: A Local Network System for Real-Time Management of Imagery Data
Some Inequalities Between Distance Measures for Feature Evaluation
On Reliability Modeling of Closed Fault-Tolerant Computer Systems
Memory Systems for Image Processing
Restricted Cellular Networks
ApproxSSD: Data Layout Aware Sampling on an Array of SSDs
On the Connectivity of Some Telecommunications Networks
Robust Mixed-Criticality Systems
Scaling and Better Approximating Quantum Fourier Transform by Higher Radices
Sonnet: A Workflow-Aware Serverless Platform for Time-Sensitive Edge Computing With WebAssembly
Magnetic Recording Storage
New Methods for Digital Generation and Postprocessing of Random Data
Symbolic programming
SinkTrail: A Proactive Data Reporting Protocol for Wireless Sensor Networks
Comments on "Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach"
Sign Detection in Nonredundant Residue Systems
Picture Reconstruction from Projections
On Systolic Contractions of Program Graphs
Isomorph-Redundancy in Sequential Circuits
Delayed Universal Logic Modules and Sequential Machine Synthesis
Always-On Speech Recognition Using TrueNorth, a Reconfigurable, Neurosynaptic Processor
An Approach to Source-Code Plagiarism Detection and Investigation Using Latent Semantic Analysis
Fault Detection in Redundant Circuits
Interactive Pattern Analysis and Classification
Significance Arithmetic: Application to a Partial Differential
Stochastic Syntactic Decoding for Pattern Classification
Fast Modular Arithmetic on the Kalray MPPA-256 Processor for an Energy-Efficient Implementation of ECM
Note on Self-Checking Checkers
Testbench Qualification of SystemC TLM Protocols through Mutation Analysis
Comments on "The Error Latency of a Fault in a Sequential Digital Circuit"
A Study of Two Approaches for Reconfiguring Fault-Tolerant Systolic Arrays
The Synthesis of Binary Sequence Detectors
Region-Based Collaborative Caching With Joint Latency and Lifetime Optimization for Hybrid SMR-Flash Storage
On Codes Identifying Vertices in the Two-Dimensional Square Lattice with Diagonals
Non-Real-Time Content Scheduling Algorithms for Wireless Data Networks
Area-Time Optimal Fast Implementation of Several Functions in a VLSI Model
Analytical Design of Resistor-Coupled Transistor Logical Circuits
The Theory Underlying the Partitioning of Permutation Networks
Asymmetric/Unidirectional Error Correcting and Detecting Codes
Elastic Power-Aware Resource Provisioning of Heterogeneous Workloads in Self-Sustainable Datacenters
Optimal Rotation Problems in Channel Routing
CABA: Continuous Authentication Based on BioAura
Random Multiple Access Algorithms Using a Control Mini-Slot
Concurrent Error Detection in Multiply and Divide Arrays
Equipment Configuration in Balanced Computer Systems
Eliminating Periodic Flush Overhead of File I/O with Non-Volatile Buffer Cache
A Neural Network Based Fault Management Scheme for Reliable Image Processing
Automated Custom Instruction Generation for Domain-Specific Processor Acceleration
Monarch: A Durable Polymorphic Memory for Data Intensive Applications
A Robust Sorting Network
Test Length for Pseudorandom Testing
The Synthesis of Multivalued Cellular Cascades
The Simulation of a Multicomputer System
Laser-Induced Fault Injection on Smartphone Bypassing the Secure Boot-Extended Version
Guest Editors' Introduction to the Special Issue on Cryptographic Engineering in a Post-Quantum World: State of the Art Advances
On a Simple Postcorrection for Nonrestoring Division
Generation of Pseudorandom Noise Having a Gaussian Spectral Density
Optimal Matrix Multiplication on Fault-Tolerant VLSI Arrays
Quantum Circuit Design of a T-count Optimized Integer Multiplier
A Comparative Study of Unification Algorithms for OR-Parallel Execution of Logic Languages
Fast Fourier Transforms on Finite Non-Abelian Groups
OPTIMUS: A Security-Centric Dynamic Hardware Partitioning Scheme for Processors that Prevent Microarchitecture State Attacks
A GPU-Enabled Real-Time Framework for Compressing and Rendering Volumetric Videos
Dynamic Fault Reconfiguration in a Mesh-Connected MIMD Environment
Fault-Tolerance of the Iterative Cell Array Switch for Hybrid Redundancy
Hardware Designs for Decimal Floating-Point Addition and Related Operations
Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?
Two Modulator-Switches for Computer Applications
Authenticating Multicast Internet Electronic Mail Messages Using a Bidirectional MAC is Insecure
A Reduced Complexity Wallace Multiplier Reduction
CHAOS-Kernel Support for Objects in the Real-Time Domain
SCARF: Securing Chips With a Robust Framework Against Fabrication-Time Hardware Trojans
Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders
Optimal Parallel Scheduling of Gaussian Elimination DAG's
VLSI Sorting with Reduced Hardware
Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache
An Iterative Technique for Determining the Minimal Number of Variables for a Totally Symmetric Function with Repeated Variables
A Pattern Adaptive NAND Flash Memory Storage Structure
Remote Control: A Simple Deadlock Avoidance Scheme for Modular Systems-on-Chip
Online Energy Estimation of Relational Operations in Database Systems
Nets of Variable-Threshold Threshold Elements
Parallel Processing in Boolean Algebra
Coding for Multiple Asymmetric Errors in One Channel of a Multichannel System
An Efficient Control-Driven Period Optimization Algorithm for Distributed Real-Time Systems
Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission
Trident: The Acceleration Architecture for High-Performance Private Set Intersection
A Low Hardware Overhead Self-Diagnosis Technique Using Reed-Solomon Codes for Self-Repairing Chips
Structure Automata
Integer Division in Linear Time with Bounded Fan-In
Guest Editors' Introduction: Special Section on Computer Arithmetic
The Optimal Interconnection of Circuit Modules in Microprocessor and Digital System Design
Compiler Support for Scalable and Efficient Memory Systems
Graph-Theoretical Methods for Detecting and Describing Gestalt Clusters
An Analytic and Experimental Study of Multiple Channel Controllers
On Fine-Grained Runtime Power Budgeting for Networks-on-Chip Systems
FSA-Hash: Flow-Size-Aware Sketch Hashing for Software Switches
Deductive Fault Simulation for Sequential Module Circuits
Knowledge Sharing in the Online Social Network of Yahoo! Answers and Its Implications
A Parallel Efficient Architecture for Large Cryptographically Robust n × k (k>n/2) Mappings
On Uniquely Decipherable Codes with Two Codewords
Performance of Hierarchical Processor Scheduling in Shared-Memory Multiprocessor Systems
An Improved Authenticated Group Key Transfer Protocol Based on Secret Sharing
Flexible and Adaptable Buffer Management Techniques for Database Management Systems
Collaborative Location-Based Sleep Scheduling for Wireless Sensor Networks Integratedwith Mobile Cloud Computing
B72-22 FORTRAN IV: A Modem Approach
Finding Prototypes For Nearest Neighbor Classifiers
Optimal Deadline Assignment for Scheduling Soft Aperiodic Tasks in Hard Real-Time Environments
The Effects of Problem Partitioning, Allocation, and Granularity on the Performance of Multiple-Processor Systems
Separating and Completely Separating Systems and Linear Codes
Upper Bounds for Dynamic Memory Allocation
Maximal and Near-Maximal Shift Register Seqyences: Efficient Event Counters and Easy Discrete Logarithms
Memory Efficient Hash-Based Longest Prefix Matching Architecture With Zero False +ve and Nearly Zero False -ve Rate for IP Processing
A Parallel and Uniform k -Partition Method for Montgomery Multiplication
Opens and Delay Faults in CMOS RAM Address Decoders
A Hardware Approach to Self-Testing of Large Programmable Logic Arrays
An Analysis Model for Digital System Diagnosis
Fault Diagnosis and Spare Allocation for Yield Enhancement in Large Reconfigurable PLA's
An Improved Lower Bound for Sorting Networks
Addendum to "Hierarchical Scalable Photonic Architectures for High-Performance Processor Interconnection"
Toward Adaptive Sleep Schedules for Balancing Energy Consumption in Wireless Sensor Networks
In Memoriam: Richard E. Merwin (1922-1981)
Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics
Fault-Tolerant Routing in DeBruijn Communication Networks
The Graph Structure of Baker's Maps Implemented on a Computer
A Novel Approach to Random Pattern Testing of Sequential Circuits
Data Partitioning on Multicore and Multi-GPU Platforms Using Functional Performance Models
A New Scheme for Reducing Link and Signaling Costs in Mobile IP
On the Construction of Composite Finite Fields for Hardware Obfuscation
A Reliability-Critical Path Identifying Method With Local and Global Adjacency Probability Matrix in Combinational Circuits
Searching on a Tape
On a Class of Recursive Algorithms for Continuous Estimation of the Mean
An Algorithm for Finding Intrinsic Dimensionality of Data
Theoretical and Experimental Evaluation of RZ and NRZ Recording Characteristics
Fault Detection in CVS Parity Trees with Application to Strongly Self-Checking Parity and Two-Rail Checkers
Synthetic Traces for Trace-Driven Simulation of Cache Memories
Increasing Reliability by the Use of Redundant Machines
Efficient Implementations of the Chinese Remainder Theorem for Sign Detection and Residue Decoding
R70-39 On the Relational Homomorphisms of Automata
The Parametron Digital Computer MUSASINO-1
Efficient Hardware Hashing Functions for High Performance Computers
Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems
Lightweight Graph Partitioning Enhanced by Implicit Knowledge
Device Applications of Charge Rectifiers
A Novel Two-Round Two-Party Quantum Private Comparison Protocol Based on Quantum Walks
Multicore-Aware Virtual Machine Placement in Cloud Data Centers
Energy Minimization in Multi-Task Software-Defined Sensor Networks
Automatic Generation of Transducer Models for Bus-Based MPSoC Design
On Embedding Between 2D Meshes of the Same Size
Reducing the Memory Bandwidth Overheads of Hardware Security Support for Multi-Core Processors
The Piecewise Data Flow Architecture: Architectural Concepts
Parallel Algorithms and Architectures for Optimal State Estimation
Performance Analysis for Heterogeneous Cloud Servers Using Queueing Theory
Instruction Replication for Reducing Delays Due to Inter-PE Communication Latency
Can Redundancy and Masking Improve the Performance of Synchronizers?
EXTREME: Exploiting Page Table for Reducing Refresh Power of 3D-Stacked DRAM Memory
Exact and Approximate Squarers for Error-Tolerant Applications
A Built-Off Self-Repair Scheme for Channel-Based 3D Memories
ANGEL: Agent-Based Scheduling for Real-Time Tasks in Virtualized Clouds
Incremental Reconfiguration and Load Adjustment in Adaptive Real-Time Systems
An Algorithm for Synthesis of Multiple-Output Combinational Logic
MIPSGPU: Minimizing Pipeline Stalls for GPUs With Non-Blocking Execution
Efficient Pipelined Execution of CNNs Based on In-Memory Computing and Graph Homomorphism Verification
Distributed Virtual Bit-Slice Synchronizer: A Scalable Hardware Barrier Mechanism for n-Dimensional Meshes
Concurrent Event Handling through Multithreading
Analysis of Gate Oxide Shorts in CMOS Circuits
Fourier Analysis by Machine Methods
Deterministic and Stochastic Response of Linear Time Variable Systems
Adaptive Fault-Tolerant Deadlock-Free Routing in Meshes and Hypercubes
Design of Self-Testing Checkers for Borden Codes
Compiler-Assisted Data Streaming for Regular Code Structures
On Shift-Register Realizations of Sequential Machines and Finite-State Universal Sequential Machines
Analog Computer Generation of Bessel Functions of Arbitrary Order
Redundancy Testing in Combinational Networks
The Human Computer in Flight Control
Comprehensive and Efficient Design Parameter Selection for Soft Error Resilient Processors via Universal Rules
A State Assignment Procedure for Asynchronous Sequential Circuits
Interval-Based Timing Constraints Their Satisfactions and Applications
R68-32 The IADIC: A Hybrid Computing Element
Leakage Prototype Learning for Profiled Differential Side-Channel Cryptanalysis
Parallel Compressors
On Negabinary-Binary Arithmetic Relationships an Their Hardware Reciprocity
A Procedure for Selecting Diagnostic Tests
Reliable Communication Scheme Based on Completely Independent Spanning Trees in Data Center Networks
Design of Fast Self-Testing Checkers for a Class of Berger Codes
Lime: Low-Cost and Incremental Learning for Dynamic Heterogeneous Information Networks
Elections in a Distributed Computing System
An Optimal Set of Discriminant Vectors
R68-23 The Greenblatt Chess Program
Guest Editors' Introduction: Special Section on Emergent Systems, Algorithms and Architectures for Speech-Based Human-Machine Interaction
Bounding of Performance Measures for Threshold-Based Queuing Systems: Theory and Application to Dynamic Resource Management in Video-on-Demand Servers
Comparison of Physical and Software-Implemented Fault Injection Techniques
Decrypting a Class of Stream Ciphers Using Ciphertext Only
Integrating Evolutionary Computation with Abstraction Refinement for Model Checking
Testing and Realization of Threshold Functions with Don't Cares
Correction [to "Linearity of sequential machines"]
Interference-Aware Cooperative Communication in Multi-Radio Multi-Channel Wireless Networks
Microcode Bit Optimizations is N P -Complete
Concurrent Error Detectable Carry Select Adder with Easy Testability
Compressed Tree Machines
WLAN Location Service with TXOP
B74-37 Data Base Management - International Computer State of the Art Report 15
Lower Bounds for Sorting with Realistic Instruction Sets
R68-36 Dataless Programming
Solving Large Problem Sizes of Index-Digit Algorithms on GPU: FFT and Tridiagonal System Solvers
Performability of an Algorithm for Connection Admission Control
Test Scheduling and Control for VLSI Built-In Self-Test
Simple Error Detection Methods for Hardware Implementation of Advanced Encryption Standard
R70-23 Multi-Tape and Multi-Head Pushdown Automata