yusuke1997/dblp-id-title huggingface dataset:
Radix-64 Floating-Point Division and Square Root: Iterative and Pipelined Units
FD-Buffer: A Cost-Based Adaptive Buffer Replacement Algorithm for FlashMemory Devices
Junction Transistor Switching Circuits for High-Speed Digital Computer Applications
On the Multihop Performance of Synchronization Mechanisms in High Propagation Delay Networks
Fault-Tolerant Computing - Concepts and Examples
Analysis of Error Masking and Restoring Properties of Sequential Circuits
Vector Boolean Algebra and Calculus
Flexible Job Scheduling With Spatial-Temporal Compatibility for In-Network Aggregation
Connectivity of Imase and Itoh Digraphs
A Configurable Membership Service
On Symmetric Functions with Redundant Variables-Weighted Functions
Optimal 2-Bit Branch Predictors
Routing Algorithms for Cellular Interconnection Arrays
Enhanced Machine Learning Sketches for Network Measurements
A Fast Filtering Mechanism to Improve Efficiency of Large-Scale Video Analytics
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set
On Block-Parallel Methods for Solving Linear Equations
Performance of Cross-Bar Multiprocessor Systems
Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero
Scheduling Inputs in Early Exit Neural Networks
A Note on Three-Valued Logic Simulation
Bias-Controlled Tunnel-Pair Logic Circuits
System Functions for an Optical/Digital Processor
A 2-Level TCAM Architecture for Ranges
Multilevel Optimization of Pipelined Caches
DPU-Direct: Unleashing Remote Accelerators via Enhanced RDMA for Disaggregated Datacenters
Randomized Mixed-Radix Scalar Multiplication
Movement-Based Mobility Management and Trade Off Analysis for Wireless Mobile Networks
Evaluating FTRE's for Dependability Measures in Fault Tolerant Systems
Antecedence Graph Approach to Checkpointing for Fault Tolerance in Mobile Agent Systems
R68-19 Bulk Core in a 360/67 Time Sharing System
A Massive Memory Machine
A New Approach for Side Channel Analysis on Stream Ciphers and Related Constructions
Correction to "Error-Correcting Parsers for Formal Languages"
Reconfiguration Alfoithms for Interconnection Networks
Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit
Pattern Classification Using Stochastic Approximation Techniques
Optimal Layout of CMOS Functional Arrays
Methods Used in an Automatic Logic Design Generator (ALERT)
A Memory Organization for an Elementary List-Processing Computer
Asynchronous and Clocked Control Structures for VSLI Based Interconnection Networks
Random Redundant Storage in Disk Arrays: Complexity of Retrieval Problems
Application-Specific Low-Power Multipliers
Network Applications on Simultaneous Multithreading Processors
Efficiency of Random Compact Testing
A Note on Testing and Realization of Threshold Functions
Product Form Approximations for Queueing Networks with Multiple Servers and Blocking
Transmission Time Analysis for the Parallel Asynchronous Communication Scheme
Algorithmic State Machine Design and Automatic Theorem Proving: Dual Approaches to the Same Activity
k-Times Attribute-Based Anonymous Access Control for Cloud Computing
A Method for Synthesizing the Waveform Generated by a Character, Printed in Magnetic Ink, in Passing Beneath a Magnetic Reading Head
Carry-Free Addition of Recorded Binary Signed-Digit Numbers
Very Fast Fourier Transform Algorithms Hardware for Implementation
A Two-Dimensional, Distributed Logic Architecture
The Model II Unityper
Correction to "Analyzing Errors with the Boolean Difference" 1
Prime Implicants, Minimum Covers, and the Complexity of Logic Simplification
A New Reader Service-Publication of Informational Retrieval Catalog Cards
Nonobservable or Noncontrollable Analog Schemes for the Solution of a Special Class of Differential Equations
Optimal VLSI Dictionary Machines Without Compress Instructions
29-Billion Atoms Molecular Dynamics Simulation With Ab Initio Accuracy on 35 Million Cores of New Sunway Supercomputer
Data Routing Networks for Systolic/Pipeline Realization of Prime Factor Mapping
A Buffer-Based Method for storage Allocation in an Object-Oriented System
A Theory for Protocol Validation
A Simply Solvable Class of Simultaneous Linear Equations
DeepWare: Imaging Performance Counters With Deep Learning to Detect Ransomware
An Algorithm for Optimally Exploiting Spatial and Temporal Locality in Upper Memory Levels
Secure and Efficient Cross-Modal Retrieval Over Encrypted Multimodal Data
AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems
Discrete Relaxation Method for Triple Patterning Lithography Layout Decomposition
On the Hyperplanes of the Taylor-Steinbuch Linear Separator
Programming Languages - The First 25 Years
Easily Testable Realizations ror Logic Functions
Constructing Protocols with Alternative Functions
FedQClip: Accelerating Federated Learning via Quantized Clipped SGD
Theoretical Limitations on the Efficient Use of Parallel Memories
Analysis of the Statistical Cipher Feedback Mode of Block Ciphers
Transients in Markov Chains
Wireless NoC for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Trade-Offs
Calculation of Cross-Coupled Noise in Digital Systems
On the Generation of a Class of Multithreshold Functions
On the Hardness of Approximating the Multicast Delay Variation Problem
On the Design of High-Yield Reconfigurable PLA's
Objective-Optimal Algorithms for Long-Term Web Prefetching
Protected Object References in Heterogeneous Distributed Systems
A Structural Redundancy in d -Sequences
On Supporting Temporal Quality of Service in WDMA-Based Star-Coupled Optical Networks
The Application of Shift Registers to Secondary State Assignment: Part I
A Note on t-EC/d-UED Codes
Triple Speed: Energy-Aware Real-Time Task Synchronization in Homogeneous Multi-Core Systems
Distributed Data Cache Designs for Clustered VLIW Processors
Leveraging Data Deduplication to Improve the Performance of Primary Storage Systems in the Cloud
System Architecture for Partition-Tolerant Distributed Databases
Computing a Most Probable Delay Constrained Path: NP-Hardness and Approximation Schemes
Analyzing Scheduled Maintenance Policies for Repairable Computer Systems
On the Maximum Value of Aliasing Probabilities for Single Input Signature Registers
Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa
A High-Coverage and Efficient Instruction-Level Testing Approach for x86 Processors
Routing and Transmitting Problems in de Bruijn Networks
Some Comments Concerning Design of Pipeline Arithmetic Arrays
A Systolic Array for the Assignment Problem
Generalized Inversion Attack on Nonlinear Filter Generators
Improved Diagnosability Algorithms
Contour: A Process Variation Aware Wear-Leveling Mechanism for Inodes of Persistent Memory File Systems
A New Design Technique for Column Compression Multipliers
Synchronized Disk Interleaving
Fully Learnable Hyperdimensional Computing Framework With Ultratiny Accelerator for Edge-Side Applications
A Note on Testing Logic Circuits by Transition Counting
GliFreD: Glitch-Free Duplication Towards Power-Equalized Circuits on FPGAs
A Note on Magnetic Shift Registers
Logic Networks with a Minimum Number of NOR(NAND) Gates for Parity Functions of n Variables
Some Frills for Modal Tic-Tac-Toe: Semantics of Predicate Complement Constructions
Universal Text Preprocessing for Data Compression
The Smallest Pair of Noncrossing Paths in a Rectilinear Polygon
An Energy-Efficient and Privacy-Aware MEC-Enabled IoMT Health Monitoring System
Optimal Storage Placement for Tree-Structured Networks with Heterogeneous Channel Costs
New Svoboda-Tung Division
Modeling and Digital Simulation for Design Verification and Diagnosis
A Framework for Describing Block Cipher Cryptanalysis
Complete Test Sets for Logic Functions
Diagonal and Toroidal Mesh Networks
Boolean Matrix Transforms for the Minimization of Modulo-2 Canonical Expansions
Honeycomb: Ordered Key-Value Store Acceleration on an FPGA-Based SmartNIC
An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array
Global Flow Analysis in Automatic Logic Design
An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores
The Maximum and Minimum Selector SELRAM and its Application for Developing Fast Sorting Machines
Partitioned List Algorithms for Prime Implicant Determination from Canonical Forms
STAR: Strategy-Proof Double Auctions for Multi-Cloud, Multi-Tenant Bandwidth Reservation
Cache Operations by MRU Change
A Weighted Z Spectrum, Parallel Algorithm, and Processors for Mathematical Model Estimation
The Warp Computer: Architecture, Implementation, and Performance
Fault-Tolerant Design Strategies for High Reliability and Safety
Fast Carry Logic for Digital Computers
A Deep Reinforcement Learning Based Offloading Game in Edge Computing
A New Class of Efficient Algorithms for Reconfiguration of Memory Arrays
Heterogeneity and Interference-Aware Virtual Machine Provisioning for Predictable Performance in the Cloud
EGCN: An Efficient GCN Accelerator for Minimizing Off-Chip Memory Access
Exploiting Spatio-Temporal Tradeoffs for Energy-Aware MapReduce in the Cloud
A Comparison of Universal-Logic-Module Realizations and Their Application in the Synthesis of Combinatorial and Sequential Logic Networks
Efficient Execution of Arbitrarily Complex Cross-Shard Contracts for Blockchain Sharding
The Deferrable Server Algorithm for Enhanced Aperiodic Responsiveness in Hard Real-Time Environments
Review section
A Dynamic Large Signal Model for a Single-Domain Thin Magnetic Film Inductor
Parallel Block Predictor-Corrector Methods for ode's
Algorithms for Computing the WCRT Bound of OpenMP Task Systems With Conditional Branches
Using Physical Context for Just-in-Time Information Retrieval
A Burroughs 220 Emulator for the IBM 360/25
Diagnosability of Nonlinear Circuits and Systems - Part I: The dc Case
Constructing a Wireless Sensor Network to Fully Cover Critical Grids by Deploying Minimum Sensors on Grid Points Is NP-Complete
S${}^{2}$2FL: Toward Efficient and Accurate Heterogeneous Split Federated Learning
Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput
Rewritable Progammable Logic Array of Current Mode Logic
AsyncGBP${}^{+}$+: Bridging SSL/TLS and Heterogeneous Computing Power With GPU-Based Providers
On the Number of Stable States in a NOR Network
Computing Cumulative Measures of Stiff Markov Chains Using Aggregation
Implementing Fail-Silent Nodes for Distributed Systems
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal
Approximate MRAM: High-Performance and Power-Efficient Computing With MRAM Chips for Error-Tolerant Applications
Dynamic Scheduling of Real-Time Mixture-of-Experts Systems on Limited Resources
Object Fingerprint Cache for Heterogeneous Memory System
Differential FEC and ARQ for Radio Link Protocols
Improving Bit Flip Reduction for Biased and Random Data
R70-14 Some Results on Cascade Decomposition of Automata
Minimal Fault Tests for Combinational Networks
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators
R70-41 Diagnosis and Utilization of Faulty Universal Tree Circuits
Nonlinear Transfer Functions with Thyrite
A Fluid Scheduling Algorithm for DAG Tasks With Constrained or Arbitrary Deadlines
Age-Aware Data Selection and Aggregator Placement for Timely Federated Continual Learning in Mobile Edge Computing
Conditional Diagnosability Measures for Large Multiprocessor Systems
A Cyclic Algebra for the Synthesis of Ternary Digital Systems
Some Thoughts on Digital Components and Circuit Techniques
Automatic Recognition of Intermittent Failures: An Experimental Study of Field Data
Enumeration of Threshold Functions of Eight Variables
On the Time Necessary to Compute Switching Functions
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors
Two-Dimensional Binary Arrays
Multi-Bank On-Chip Memory Management Techniques for CNN Accelerators
Mangrove: An Inference-Based Dynamic Invariant Mining for GPU Architectures
Weighted Diagnosis with Asymmetric Invalidation
Strongly Fault Secure Logic Networks
Inconsistent Canonical Forms of Switching Functions
Applying Statistical Sampling for Fast and Efficient Simulation of Commercial Workloads
Polylinear Sequential Circuit Realizations of Finite Automata
Fault-Detection Experiments for Parallel-Decomposable Sequential Machines
On Optimal Replacement of Nonuniform Cache Objects
Dynamic Errors in Electronic Analog Computers
Complexity of Single-Layer Routing
FlashDecoding++Next: High Throughput LLM Inference With Latency and Memory Optimization
A New Approach to the Evaluation of the Reliability of Digital Systems
CAA Decoder for Cellular Automata Based Byte Error Correcting Code
Automatic Verification of Sequential Circuits Using Temporal Logic
An Easily Testable Design of Programmable Logic Arrays for Multiple Faults
Compiler Algorithms for Synchronization
A Realization Procedure for Threshold Gate Networks
Fault-Aware Load-Balancing Routing for 2D-Mesh and Torus On-Chip Network Topologies
Design of Goldschmidt Dividers with Quantum-Dot Cellular Automata
Globally Optimal Diagnosis in Systems with Random Faults
PARMA: Parallelization-Aware Run-Time Management for Energy-Efficient Many-Core Systems
Self-Synchronization of Asynchronous Sequential Circutis Employing a General Clock Function
High-Speed Arithmetic Arrays
Error-Correcting Codes in Binary-Coded-Decimal Arithmetic
ADDSEN: Adaptive Data Processing and Dissemination for Drone Swarms in Urban Sensing
Efficient Reachability Analysis for Time Petri Nets
A Floating-Point Unit for 4D Vector Inner Product with Reduced Latency
Analysis and Implementation of Hybrid Switching
An RSA Implementation Resistant to Fault Attacks and to Simple Power Analysis
Requirement-Aware Scheduling of Bag-of-Tasks Applications on Grids with Dynamic Resilience
Additive Bernoulli Noise Linear Sequential Circuits
Star Local Area Networks: A Performance Study
A Simple Random Test Procedure for Detecion of Single Intermittent Fault in Combinational Circuits
NICO: Reducing Software-Transparent Crash Consistency Cost for Persistent Memory
Design of Self-Checking Circuits Using DCVS Logic: A Case Study
Algorithms for Detection of Faults in Logic Circuits
Cascade Realizations of Magnetic Bubble Logic Using a Small Set of Primitives
Self-Implicating Structures for Diagnosable Systems
SEDUM: Exploiting Social Networks in Utility-Based Distributed Routing for DTNs
Analog-Computer Technique for Simulation of Dynamic Pressure in Re-Entry Studies
Using Traffic Regulation to Meet End-to-End Deadlines in ATM Networks
Torus and Other Networks as Communication Networks With Up to Some Hundred Points
Exploiting Emergence in On-Chip Interconnects
An Analog Comparator as a Pseudo-Light Pen for Computer Displays
Predictive Execution of Parallel Simulations in Hard Real-Time Systems
Doubly Linked Ring Networks
Guest Editor's Introduction: 1997 IEEE Real-Time Technologies and Applications Symposium
A Note on Linear Separation
An Improved Search Method for Accumulator-Based Test Set Embedding
Optimal Camera Placement for Providing Angular Coverage in Wireless Video Sensor Networks
An Improved Method of Prime C-Class Derivation in the State Reduction of Sequential Networks
Modular Architecture for High Performance Implementatin of the FFT Algorithm
Synthesis of Nonconstant Weight Binary Codes for Minimum Diode Counters
Ambiguity in Graphs and Expressions
A Diagrammatic Approach to Multilevel Logic Synthesis
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
Efficient Integrity Auditing Mechanism With Secure Deduplication for Blockchain Storage
Use of the Multipole Expansion to Extract Significant Features of the Surface Electrocardiogram
Response Time Stochastic Analysis for Fixed-Priority Stable Real-Time Systems
Use of Postfix Notation for the Description of Microcellular Arrays
Generating De Bruijn Sequences: An Efficient Implementation
CUSPX: Efficient GPU Implementations of Post-Quantum Signature SPHINCS +
DBC - A Database Computer for Very Large Databases
State-Variable Techniques for Digital Simulation of Bandpass Systems
Arb: Efficient Arbitrary-Precision Midpoint-Radius Interval Arithmetic
Pruning-Based Adaptive Federated Learning at the Edge
An Optimal Strategies for Cycle-Stealing in Networks of Workstations
Analog Computation of Covariance Matrices
On the Communication Complexity of Generalized 2-D Convolution on Array Processors
A General Model for Memory-Based Finite-State Machines
Modeling, Analysis, and Self-Management of Electronic Textiles
On-Bound Selection Cache Replacement Policy for Wireless Data Access
A Novel En-Route Filtering Scheme Against False Data Injection Attacks in Cyber-Physical Networked Systems
Computer Simulation of Waveform Distortions in Digital Magnetic Recordings
Logic Circuits for a Transistor Digital Computer
Minimization of Interprocessor Communication for Parallel Computation
On Modulo 2^n+1 Adder Design
Algorithms for Binary Coded Balanced and Ordinary Ternary Operations
REMOTE: Robust External Malware Detection Framework by Using Electromagnetic Signals
Easily Testable Cellular Realizations for the (Exactly P)-out-of n and (p or More)-out-of n Logic Functions
Initial Conditions in Computer Simulation
Toward Optimal Broadcast in a Star Graph Using Multiple Spanning Trees
Topoglyphs
Code Optimization for Tagged-Token Dataflow Machines
Maintaining Sorted Files in a Magnetic Bubble Memory
An analog multiplier using thyrite
Pako: Multi-Valued Byzantine Agreement Comparable to Partially-Synchronous BFT
Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors
FLALM: A Flexible Low Area-Latency Montgomery Modular Multiplication on FPGA
Stochastic Automata and the Problems of Reliability in Sequential Machines
A Q-Learning Based Self-Adaptive I/O Communication for 2.5D Integrated Many-Core Microprocessor and Memory
Zero Aliasing for Modeled Faults
Guardauto: A Decentralized Runtime Protection System for Autonomous Driving
HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems
Online Bounds on Balancing Two Independent Criteria with Replication and Reallocation
WBSP: A Novel Synchronization Mechanism for Architecture Parallel Simulation
High-Radix Design of a Scalable Montgomery Modular Multiplier With Low Latency
Threshold Gate Building Blocks
Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems
B72-24 Adaptation and Learning in Automatic Systems
Designing High-Performance Processors Using Real Address Prediction
Modulo Scheduling with Reduced Register Pressure
Simple Radix-4 Division with Opterands Scaling
VecQ: Minimal Loss DNN Model Compression With Vectorized Weight Quantization
Comments on "A Note on Synchronizer or Interlock Maloperation"
A Method for Evaluating Amplifier Phase Shift at Low Frequencies
On the Determination of Irredundant Prime Closed Sets
Design of Balanced and Constant Weight Codes for VLSI Systems
R70-13 Multigate Synthesis of General Boolean Functions by Threshold Logic Elements
B74-38 Operating Systems Theory
Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture
A Novel Implementation Method for Addition and Subtraction in Residue Number Systems
Formal Modeling and Verification of Microprocessors
Linear System Identification Using Real-Time Deconvolution
Efficient Checkpointing of Live Virtual Machines
Effective Pipelining of Digital Systems
Five, Six, and Seven-Term Karatsuba-Like Formulae
The Boundary Matrix of Threshold Functions
Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches
Performance Implications of Tolerating Cache Faults
Tapping into NFV Environment for Opportunistic Serverless Edge Function Deployment
Techniques for Change Detection
Design of CAECC-Cellular Automata Based Error Correcting Code
Testing for Faults in Wiring Networks
Limited Magnitude Error Detecting Codes over Z_{q}
Parallel Detection of Concavities in Cellular Blobs
Complex Number Arithmetic with Odd-Valued Logic
Longest "Separated" Paths and Loops in an N Cube
Solution of Nonlinear Equations
A Nonbulk Addition Technique for Associative Processors
Comments on "Asynchronous Sequential Machines Designed for Fault Detection"
Finite Precision Error Analysis of Neural Network Hardware Implementations
Automatic Reconfiguration and Yield of the TESH Multicomputer Network
The Special Issue on High-Speed Memories
Multiplier/Shifter Design Tradeoffs in a 32-bit Microprocessor
Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits
Spanning Multiaccess Channel Hypercube Computer Interconnection
Fast Hadamard Transform Using the H Diagram
Fault Propagation Through Embedded Multiport Memories
Threshold Priority Policy for Channel Assignment in Cellular Networks
Note on Minimal Congruences on Transition Graphs
Plasticity-on-Chip Design: Exploiting Self-Similarity for Data Communications
Energy Efficient and Scalable Search in Dense Wireless Sensor Networks
Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection
Race-Free State Assignment for Synthesizing Large-Scale Asynchronous Sequential Logic Circuits
A Fast and Efficient Processor Allocation Scheme for Mesh-Connected Multicomputers
Is Switching Theory Mathematics or Engineering?
Detection and Parallel Execution of Independent Instructions
Magnifying Side-Channel Leakage of Lattice-Based Cryptosystems With Chosen Ciphertexts: The Case Study of Kyber
Maximizing Active Storage Resources with Deadlock Avoidance in Workflow-Based Computations
Near-Optimal Thermal Monitoring Framework for Many-Core Systems-on-Chip
Measurement and Analysis of HYPERchannel Networks
Multiple-Bit Parity-Based Concurrent Fault Detection Architecture for Parallel CRC Computation
Analysis of Digital Systems Using a New Measure of System Diagnosis
Large-Scale Circuit Interconnection for Boolean Function Implementation
Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors
Translation, Abstraction and Integration for Effective Smart System Design
Multioperand Parallel Decimal Adder: A Mixed Binary and BCD Approach
Multithreaded Maximum Flow Based Optimal Replica Selection Algorithm for Heterogeneous Storage Architectures
Easily Testable Realizations for Generalized Reed-Muller Expressions
Energy-Efficient Operation of Multicore Processors by DVFS, Task Migration, and Active Cooling
On the Buffer Behavior with Poisson Arrivals, Priority Service, and Random Server Interruptions
Unsupervised Speaker Change Detection Using SVM Training Misclassification Rate
Concurrent Support of Multiple Page Sizes on a Skewed Associative TLB
Generating Cyclic-Random Sequences in a Constrained Space for In-System Validation
Algorithms to Process Distributed Queries in Fast Local Networks
The Residue Number System
Using Multilevel Phase Change Memory to Build Data Storage: A Time-Aware System Design Perspective
A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations
DPPC: Dynamic Power Partitioning and Control for Improved Chip Multiprocessor Performance
A Note on Moore's Distinguishability Theorem
Computing Tasks Saving Schemes Through Early Exit in Edge Intelligence-Assisted Systems
Determination of Cache's Capacity and its Matching Storage Hierarchy
A Fast Parallel Algorithm for Routing in Permutation Networks
How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins
On the Size of PLA's Required to Realize Binary and Multiple-Valued Functions
An Approach to Optimum Tolerance Adaptive Threshold Elements
SHIELD: Scalable Homomorphic Implementation of Encrypted Data-Classifiers
Experimental Results on Subgoal Reordering
Empowering Authenticated and Efficient Queries for STK Transaction-Based Blockchains
Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories
S-R-T Flip-Flop
Structural Factors in the Fault Diagnosis of Combinational Networks