yusuke1997/dblp-id-title huggingface dataset:
Minimum Deadline Calculation for Periodic Real-Time Tasks in Dynamic Priority Systems
Digital Computers in Continuous Control Systems
Precise Mixed-Criticality Scheduling on Varying-Speed Multiprocessors
Dynamic Memories with Rapid Random and Sequential Access
Adaptive Federated Learning Through Dynamic Model Splitting and Multi-Objective Clustering
Electrical Assemblies with a Minimum Number of Interconnections
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor
On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines
A High-Performance, Energy-Efficient Modular DMA Engine Architecture
ParaX : Bandwidth-Efficient Instance Assignment for DL on Multi-NUMA Many-Core CPUs
Human-Inspired Computing for Robust and Efficient Audio-Visual Speech Recognition
On the Quantitative Evaluation of Edge Detection Schemes and Their Comparison with Human Performance
Skewed Associativity Improves Program Performance and Enhances Predictability
Computer Description of Bodies Bounded by Quadric Surfaces from a Set of Imperfect Projections
Searching Worst Cases of a One-Variable Function Using Lattice Reduction
On the Computation of Correctly Rounded Sums
Differentiating Services with Noncongestive Queuing (NCQ)
Spin-Variable Reduction Method for Handling Linear Equality Constraints in Ising Machines
An Algorithm for Scaling and Single Residue Error Correction in Residue Number Systems
Ultra-Scalable CPU-MIC Acceleration of Mesoscale Atmospheric Modeling on Tianhe-2
Hybrid Wordlength Optimization Methods of Pipelined FFT Processors
Results Obtained Using a Simple Character Recognition Procedure on Munson's Handprinted Data
Fault Hamiltonicity and Fault Hamiltonian Connectivity of the Arrangement Graphs
Comments on "Magnetic Bubble Memory Architectures for Supporting Associative Searching of Relational Databases"
Increased Thoughput for the Testing and Repair of RAM's with Redundancy
On the Cascade Decomposition of Prefix Automata
Equivalence Between Functionality and Topology of Log N-Stage Banyan Networks
A Performance Model for Duato's Fully Adaptive Routing Algorithm in k-Ary n-Cubes
Analysis and Mitigation of Shared Resource Contention on Heterogeneous Multicore: An Industrial Case Study
On Input and Next-State Equations of the R-S Type M -Stable
Models of DASD Subsystems with Multiple Access Paths: A Throughput-Driven Approach
Topologies of Combined (2logN - 1)-Stage Interconnection Networks
Efficient Unidirectional Error Codes for Block Memories
A Lower Bound on the Complexity of Arbitrary Switching Function Realizers
Optimum State Assignment for Synchronous Sequential Circuits
An Optimal Algorithm for Determining the Visibility of a Polygon from an Edge
Generalized Partially-Mixed-Polarity Reed-Muller Expansionand Its Fast Computation
Distributed Computation Via Active Messages
Concurrent Error Detection in Finite-Field Arithmetic Operations Using Pipelined and Systolic Architectures
Multi-Path Bound for Parallel Tasks With Conditional Branches
A Note on High-Speed Digital Multiplication
An efficient class of unidirectional error detecting/correcting codes
A Parallel Implementation of the Fast Fourier Transform Algorithm
An Area Shading Graphics Display Systems
A Hardware-Based Architecture-Neutral Framework for Real-Time IoT Workload Forensics
Pseudoexhaustive Test Pattern Generator with Enhanced Fault Coverage
Tetris: Using Software/Hardware Co-Design to Enable Handheld, Physics-Limited 3D Plane-Wave Ultrasound Imaging
High Speed Generation of Maximal Length Sequences
A Formal Definition of SOL
Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST
QCA Systolic Array Design
Area-Time Efficient Sign Detection Technique for Binary Signed-Digit Number System
Manetho: Transparent Rollback-Recovery with Low Overhead, Limited Rollback, and Fast Output Commit
Improving the Accuracy of Defect Diagnosis with Multiple Sets of Candidate Faults
Concurrent Error Detection and Correction in Real-Time Systolic Sorting Arrays
An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication
A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture
Efficient Verification and Optimization of Real-Time Logic-Specified Systems
B74-12 Principles of Interactive Computer Graphics
Algorithms for Generating Probabilities with Multivalued Stochastic Relay Circuits
A Deadlock-Free and Connectivity-Guaranteed Methodology for Achieving Fault-Tolerance in On-Chip Networks
High-Speed Hybrid-Double Multiplication Architectures Using New Serial-Out Bit-Level Mastrovito Multipliers
The Design and Verification of the Rio File Cache
On the Complexity of Inversions
A Pipelined Pseudoparallel System Architecture for Real-Time Dynamic Scene Analysis
Latch Susceptibility to Transient Faults and New Hardening Approach
Secure and Efficient Control Data Isolation with Register-Based Data Cloaking
Realization of Fault-Tolerant Machines - Linear Code Application
Reliability Aspects of the Variable Instruction Computer
Optimal Design and Sequential Analysis of VLSI Testing Strategy
Real-Time Processing in Client-Server Databases
Apictorial Jigsaw Puzzles: The Computer Solution of a Problem in Pattern Recognition
Optimal Scheduling Strategies in a Multiprocessor System
Robust Storage Structures for Crash Recovery
Reliable and Efficient Multi-Path Transmission Based on Disjoint Paths in Data Center Networks
Continuous Learning Automata Solutions to the Capacity Assignment Problem
B 74-29 Currents in the Theory of Computing
Parallel Simulation of Pore Networks Using Multicore CPUs
Self-Testing Embedded Parity Checkers
Wafer-Scale Integration of Systolic Arrays
Modular Asynchronous Control Design
A State Assignment Approach to Asynchronous CMOS Circuit Design
On the Complexity of Scheduling Problems for Parallel/Pipelined Machines
ReDO: Cross-Layer Multi-Objective Design-Exploration Framework for Efficient Soft Error Resilient Systems
The Lee Path Connection Algorithm
Multiprocessor Capacity Metric and Analysis
Comments on "A Fast Digital Computer Method for Recursive Estimation of the Mean"
The Simulation of Cognitive Processes, II: An Annotated Bibliography
Computer Representation of Real Numbers
An Expandable Ferroelectric Random Access Memory
Optimal Distance Networks of Low Degree for Parallel Computers
Generation of a Clock Pulse for Asynchronous Sequential Machines to Eliminate Critical Races
The Architectural Features and Implementation Techniques of the Multicell CASSM
Error and Reject Rates in a Hierarchical Pattern Recognizer
The Tree-Match Chip
A Dynamic Adaptive Framework for Practical Byzantine Fault Tolerance Consensus Protocol in the Internet of Things
An Improved Algorithm for the Construction of Decision Diagrams by Rearranging and Partitioning the Input Cube Set
Post-Quantum Key Exchange on ARMv8-A: A New Hope for NEON Made Simple
Time and Parallel Processor Bounds for Fortran-Like Loops
Principal Features of the VOLTAN Family of Reliable Node Architectures for Distributed Systems
Authors Reply
Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits
An Efficient Multipolling Mechanism for IEEE 802.11 Wireless LANs
Load Balancing Scheduling for Batch-Ordered Job-Store: Online vs. Offline
Hybrid Edge-Cloud Collaborator Resource Scheduling Approach Based on Deep Reinforcement Learning and Multiobjective Optimization
Macro E-Nets for Representation of Parallel Systems
Distributed Reset
GCONV Chain: Optimizing the Whole-Life Cost in End-to-end CNN Acceleration
Making LRU Friendly to Weak Locality Workloads: A Novel Replacement Algorithm to Improve Buffer Cache Performance
Built-in Security Computer: Deploying Security-First Architecture Using Active Security Processor
Leading-One Prediction with Concurrent Position Correction
Performance-Related Reliability Measures for Computing Systems
Realization of Fuzzy Forms
The Switching Characteristics of 4-79 Permalloy Cores with Different Anneals
CCLS: An Efficient Local Search Algorithm for Weighted Maximum Satisfiability
A Real-Time Operating System for Manned Spaceflight
The Stack Growth Function: Cache Line Reference Models
An Efficient Methodology for Binary Logarithmic Computations of Floating-Point Numbers With Normalized Output Within One ulp of Accuracy
A Prioritized Petri Net Model and Its Application in Distributed Multimedia Systems
Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems
Sherlock N-overlap: Invasive Normalization and Overlap Coefficient for the Similarity Analysis Between Source Code
Strongly Code Disjoint Checkers
A Remark on the Concepts of Input-Memory and Output-Memory of Sequential Machines
A Diagnosis Algorithm for the BGM System Level Fault Model
Some New Results About the ( d, k ) Graph Problem
Complexities of Graph-Based Representations for Elementary Functions
A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields
Rethinking Memory Management in Modern Operating System: Horizontal, Vertical or Random?
Probabilistically Guaranteeing End-to-End Latencies in Autonomous Vehicle Computing Systems
More Efficient Radix-2 Algorithms for Some Elementary Functions
On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic
Computer Aided Design of Fault-Tolerant Application Specific Programmable Processors
Logical Machine Design: A Selected Bibliography
Guided Probabilistic Checksums for Error Control in Low-Power Digital Filters
A Wire-Routing Scheme Based on Trunk-Division Methods
B70-1 Truth Functions and the Problem of Their Realization by Two-Terminal Graphs
Hypercube Multiprocessors with Bus Connections for Improving Communication Performance
Equivalence and Transformations for Post Multivalued Algebras
On-Line Fault Protection for ReRAM-Based Neural Networks
Computing Techniques for the Sampling Parametric Computer
An On-Board Executable Pareto-Based Iterated Local Search Algorithm for Embedded Multi-Core Processor Task Scheduling
Hitchhiker: Accelerating ORAM With Dynamic Scheduling
FFT-Based McLaughlin's Montgomery Exponentiation without Conditional Selections
Time Redundant Fault-Location in Bit-Sliced ALU's
A Note on SEC/AUED Codes
Low Delay Single Symbol Error Correction Codes Based on Reed Solomon Codes
On Scheduling Tasks with a Quick Recovery from Failure
The Reverse-Exchange Interconnection Network
A Fast Algorithm for Optimum Syndrome Space Compression
A Random and an Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits
A Method for Testing and Realization of Threshold Functions
Resource-Oriented Partitioning for Multiprocessor Systems with Shared Resources
On the Uniqueness of Minimal-State Stochastic Sequential Machines
Drum Organization for Strobe Addressing
Automatic Generation of Symbolic Reliability Functions for Processor-Memory-Switch Structures
Divide-and-Correct Algorithm for Division in a Negative Base
Multigrid Algorithms on the Hypercube Multiprocessor
Fine-Grained Multithreading with Process Calculi
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs
Prefetch-Aware Memory Controllers
Performability Analysis: Measures, an Algorithm, and a Case Study
Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis
Design of Self-Diagnostic Boards by Multiple Signature Analysis
Hard-Wired Multipliers with Encoded Partial Products
Exploring the Feasibility of Fully Homomorphic Encryption
High-Speed Function Approximation Using a Minimax Quadratic Interpolator
A Design Theory of Recognition Functions in Self-Organizing Systems
Independent Spanning Trees on Multidimensional Torus Networks
A Methodology for the Rapid Injection of Transient Hardware Errors
An Attempt to Design an Improved Multiplication System
A Distributed TCAM Coprocessor Architecture for Integrated Longest Prefix Matching, Policy Filtering, and Content Filtering
Efficient Tests for Realistic Faults in Dual-Port SRAMs
Efficient Boolean Manipulation With OBDD's can be Extended to FBDD's
Group Properties of Cellular Automata and VLSI Applications
A Software Cost Model for Quantifying the Gain with Considerations of Random Field Environments
Optimal Scheduling in Buffered WDM Interconnects with Limited Range Wavelength Conversion Capability
Comments on "Decomposition of Complex Multipliers Using Polynomial Encoding"
Minimal Weight Digit Set Conversions
Equivalence of the Arbiter, the Synchronizer, the Latch, and the Inertial Delay
Delay Analysis of Broadcast Routing in Packet-Switching Networks
Reducing Communication Overhead of the Subset Difference Scheme
Correction to "Self-Dual Symmetric Switching Functions with a Certain a-Number Constraint"
Reliability Evaluation of BC Networks in Terms of the Extra Vertex- and Edge-Connectivity
Multiple Addition by Residue Threshold Functions and Their Representation by Array Logic
Commutativity-Based Concurrency Control for Abstract Data Types
Addition and Subtraction in the Residue Number System
An Angle Recoding Method for CORDIC Algorithm Implementation
Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test
A Holistic Approach to Designing Energy-Efficient Cluster Interconnects
Processor Scheduling for Linearly Connected Parallel Processors
Minimizing Latency in CCD Memories
Logic, discovery, and the foundations of computing machinery
Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor
Some Properties of Binary Counters with Feedback
Comments on "Fault Folding for Irredundant and Redundant Combinational Circuits"
An Efficient Algorithm for Generating Complete Test Sets for Combinational Logic Circuits
Path Length Computations on Graph Models of Computations
Window Random Access Protocols for Local Computer Networks
Worst Case Design of Variable-Threshold TRL Circuits
Improved Voltage Selector and Cascade Multiplier Circuits
Analyzed Binary Computing
A State Assignment Technique for Sequential Machines Using J-K Flip-Flops
An Approximation to the Asymmetric Strip-Line Coupling Coefficient
Seniority Logic: A Logic for a Committee Machine
Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy
A Fault-Tolerant Information Processing Concept for Space Vehicles
Optimizing Polynomial Convolution for NTRUEncrypt
Fault-Tolerant Computing: An Introduction
Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System
Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning Techniques
System Diagnosis and Redundant Tests
Improving Performance and Capacity of Flash Storage Devices by Exploiting Heterogeneity of MLC Flash Memory
Practical Resilience Analysis of GPGPU Applications in the Presence of Single- and Multi-Bit Faults
Manipulation of State Transition Matrices of Finite Markov Chains
Analysis of Detection Probability and Some Applications
Comment on "A Magnetostrictive Delay-Line Shift Register
Handling Transients of Dynamic Real-Time Workload Under EDF Scheduling
A Distributed Commit Protocol for a Multicomputer System
Extending the Definition of Prime Compatibility Classes of States in Incomplete Sequential Machine Reduction
B72-19 Future Developments in Telecommunications
Characterizing Experiments for Finite-Memory Binary Automata
Optimizing the Instruction Cache Performance of the Operating System
Invertible Boolean Functions
On the Dual-Monotonicity of Threshold Functions
Virtual Flash Chips: Reinforcing the Hardware Abstraction Layer to Improve Data Recoverability of Flash Devices
B72-2 A Compiler Generator
Modulo 2n±1 Adder Design Using Select-Prefix Blocks
In-Memory Processing on the Spintronic CRAM: From Hardware Design to Application Mapping
WASP: Selective Data Prefetching with Monitoring Runtime Warp Progress on GPUs
Two-Level Emitter-Function Logic Structures for Logic-in-Memory Computers
Bio-Inspired Load-Balancing Framework for Loosely Coupled Heterogeneous Server Systems
On the Number of Functions Realized by Cascades and Disjunctive Networks
Adaptive Federated Learning on Non-IID Data With Resource Constraint
On the Time-Bandwidth Proof in VLSI Complexity
Optimally Routing LC Permutations on k-Extra-Stage Cube-Type Networks
Extreme Area-Time Tradeoffs in VLSI
Properties of Wired Logic
Invariant Properties of the Shuffle-Exchange and a Simplified Cost-Effective Version of the Omega Network
Minimal Characterizing Experiments for Finite Memory Automata
Systolic Algorithms for String Manipulations
Hardware Optimizations and Analysis for the WG-16 Cipher with Tower Field Arithmetic
A Class of Unidirectional Bit Serial Systolic Architectures for Multiplicative Inversion and Division over GF(2 m )
A Fast and Low Cost Self-Routing Permutation Network
A Parallel Algorithm to Compute the Shortest Paths and Diameter of a Graph and Its VLSI Implementation
Double-Basis Multiplicative Inversion Over GF(2 m )
Crash Recovery Scheme for a Memory-Resident Database System
Path Allocation Access Control in Fiber Optic Communication Systems
Design of an Accumulator for a General Purpose Computer
Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays
Fast Simulation of Highly Dependable Systems with General Failure and Repair Processes
Minimizing Incompletely Specified Sequential Switching Functions
R70-10 The Minimalization of Tree Automata
Scanners for Ferroelectric Memory Capacitors
Constructing Composite Field Representations for Efficient Conversion
A High-Speed Analog to Digital Converter
Circuits Employing Toroidal Magnetic Cores as Analogs of Multipath Cores
An Electronic Analog Multiplier Using Carriers
Combinational Relay Switching Fields
Sequential Algorithm for the Determination of Maximum Compatibles
A Machine Learning Pipeline Stage for Adaptive Frequency Adjustment
A Method for Solving Polynomial Equations by Continued Fractions
Some Computer Organizations and Their Effectiveness
Scheme to Measure Packet Processing Time of a Remote Host through Estimation of End-Link Capacity
Innovative Structures for CMOS Combinational Gates Synthesis
A CFD-Based Tool for Studying Temperature in Rack-Mounted Servers
Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification
Hardware Acceleration of Hash Operations in Modern Microprocessors
TRAST: Trust-Based Distributed Topology Management for Wireless Multimedia Sensor Networks
A System-Level Test Methodology for Communication Peripherals in System-on-Chips
On Adaptive System Diagnosis
Properties of the Multidimensional Generalized Discrete Fourier Transform
A Uniform Representation of Single- and Multistage Interconnection Networks Used in SIMD Machines
Synthesis of Gate-Minimum Multi-Output Two-Level Negative Gate Networks
On Polynomial Multiplication in Chebyshev Basis
Single Asymmetric Error-Correcting Cyclic AN Codes
Data Structure Optimization for Power- Efficient IP Lookup Architectures
A Symmetric Tree Structure Interconnection Network and its Message Traffic
Encoding of Asynchronous Sequential Networks
Organization of Semiconductor Memories for Parallel-Pipelined Processors
An O (2 0.304 n ) Algorithm for Solving Maximum Independent Set Problem
Flight Simulation of Orbital and Re-Entry Vehicles
An Algorithm for Determining the Fault Diagnosability of a System
A New Rule for Reducing CC Tables
FITS: An Integrated ILP-Based Test Scheduling Environment
SmartZone: Runtime Support for Secure and Efficient On-Device Inference on ARM TrustZone
Diminished-One Modulo 2 n +1 Adder Design
Fast Constant Division Routines
Accumulator Compression Testing
An Embedded Memory-Centric Reconfigurable Hardware Accelerator for Security Applications
Comments on "A Floating Point Multiplexed DDA System"
Evaluation of Walsh Power Spectrum of Nearly White Signals
Accelerating Graph Convolutional Networks Through a PIM-Accelerated Approach
Statistical Estimation of the Intrinsic Dimensionality of a Noisy Signal Collection
Fault Testing and Diagnosis in Combinational Digital Circuits
Activity in an Interleaved Memory
Eliminate Data Divergence in SpMV via Processor and Memory Co-Computing Framework
Addendum to Voltage-Clock-Scaling Adaptive Scheduling Techniques for Low Power in Hard Real-Time Systems
Fault Diagnosis of MOS Combinational Networks
Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency
Negative-Base Number-Representation Systems
An Extension of the Clause Table Approach to Multi-Output Combinational Switching Networks
Fault Detection Capabilities of Alternating Logic
A Connecting Network with Fault Tolerance Capabilities
TPF: TCP Plugged File System for Efficient Data Delivery over TCP
A New Range-Reduction Algorithm
Exact Performance Estimates for Multiprocessor Memory and Bus Interference
A Novel Technique for Efficient Parallel Implementation of a Classical Logic/Fault Simulation Problem
Stop and Look: A Novel Checkpointing and Debugging Flow for FPGAs
Analytic Models of Cyclic Service Systems and Their Application to Token-Passing Local Networks
Counting and Reporting Intersections of d -Ranges
A Hardware Scheduler Based on Task Queues for FPGA-Based Embedded Real-Time Systems
High-Performance and Compact Architecture for Regular Expression Matching on FPGA
On the Determination of Complete Sets of Logical Functions
Image Processing by Transforms Over a Finite Field
Algorithms for Reporting and Counting Geometric Intersections
Complete Decomposition of Stochastic Petri Nets Representing Generalized Service Networks (Corrected Version)
Dynamic Accuracy and Error in Analog Computations
Database Operations in a Cube-Connected Multicomputer System
R70-22 Subdirect Decompositions of Transformation Graphs
Multidimensional Height-Balanced Trees
Parametric Techniques for Eliminating Division and Treating Singularities in Computer Solutions of Ordinary Differential Equations
Power-Aware Branch Prediction: Characterization and Design
A Digital System Design Language (DDL)
Enhancing High-Level Synthesis Using a Meta-Programming Approach
Stochastic Well-Formed Colored Nets and Symmetric Modeling Applications
Fast Approximation Algorithms on Maxcut, k-Coloring, and k-Color Ordering vor VLSI Applications
Identification of Symmetry, Redundancy and Equivalence of Boolean Functions
An Efficient TSC 1-out-of-3 Code Checker
A Numerical Expansion Technique and Its Application to Minimal Multiplexer Logic Circuits
NPAM: NVM-Aware Page Allocation for Multi-Core Embedded Systems
SYREL: A Symbolic Reliability Algorithm Based on Path and Cutset Methods
MIHST: A Hardware Technique for Embedded Microprocessor Functional On-Line Self-Test
Dependability of the K Minimum Values Sketch: Protection and Comparative Analysis
Deriving Petri Nets for Finite Transition Systems
Subcube Determination in Faulty Hypercubes
Implementation of Permutation Functions in Illiac IV-Type Computers
Algorithm for Generating a Digital Straight Line on a Triangular Grid
High-Speed Flip-Flops for the Millimicrosecond Region
Optimal Design of Distributed Information Systems
An HIPPI Interconnection System
Enabling the Duo-Phase Data Management to Realize Longevity Bit-Alterable Flash Memory
Analysis and Design of Linear Finite State Machines for Signature Analysis Testing
Efficient Fast Fourier Transform Programs for Arbitrary Factors with One Step Loop Unscrambling
$\tt{PoisonedGNN}$: Backdoor Attack on Graph Neural Networks-Based Hardware Security Systems
Tolerating C Integer Error via Precision Elevation
The Use of Higher Order Logic in Program Verification
Determining an Optimal Secondary Storage Service Rate for the PASM Control System
Gimpel's Reduction Technique Extended to the Covering Problem with Costs
Sabrac-A New Generation Serial Computer
JEM: Just in Time/Just Enough Energy Management Methodology for Computing Systems
A Synthesis Technique for Networks Consisting of Logical Functions Feeding a Linear Summation Element
Variable Instruction Set Architecture and Its Compiler Support
Sigmoid Generators for Neural Computing Using Piecewise Approximations
Special Section on Secure Computer Architectures
Comments on "Provably Sublinear Point Multiplication on Koblitz Curves and Its Hardware Implementation"
An Implementation Technique for Walsh Functions
Analysis and Design of Real-Time Servers for Control Applications