yusuke1997/dblp-id-title huggingface dataset:
Odd-Element Half-Wave-Rectification Superposition Technique for High-Multiplication Factor Frequency Multipliers Design
Intelligent Coordination of Traditional Power Plants and Inverters Air Conditioners Controlled With Feedback-Corrected MPC in LFC
Low-Power Decibel-Linear Programmable-Gain Amplifier With Complementary Current-Switching Technique
Hardware Implementation for Belief Propagation Flip Decoding of Polar Codes
A 12-Bit 1 GS/s RF Sampling Pipeline-SAR ADC With Harmonic Injecting Cross-Coupled Pair Achieving 7.5 fj/Conv-Step
DC-Readout of Semiconductor Spin Qubits: Opportunities and Limits
A Computing In-Memory Multibit Multiplication Based on Decoupling and In-Array Storing
A 1.31-ppm/ ° C CMOS Voltage Reference With Second-Order and Sub-Ranging Compensation
A CMOS AFE With 37-nA rms Input-Referred Noise and Marked 96-dB Timing DR for Pulsed LiDAR
A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm
Quantization-Uncertainty-Dependent Analysis and Control of Linear Systems With Multi-Input-Multi-Output Quantization
Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors
A Study of a Millimeter-Wave Transmitter Architecture Realizing QAM Directly in RF Domain
A Novel Memristor Regulation Method for Chaos Enhancement in Unidirectional Ring Neural Networks
Hardware Implementation of Projection-Aggregation Decoders for Reed-Muller Codes
Dynamic Periodic Event-Triggered Adaptive Prescribed Performance Control of Uncertain Semi-Strict Feedback Systems With Application
MMSE Equalizer Design Optimization for Wireline SerDes Applications
Chaos Division Multi-Access Communication System
MS-SCIM: A Mixed-Signal Stochastic Computing-in-Memory Paradigm for Information Security
Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization
An Interstage-Reflectionless V-Band Radiometer With Capacitor-Reused Absorptive Matching in 0.13-μm SiGe BiCMOS
Ultra-Low-Power Low-Input-Voltage Charge Pump for Micro-Energy Harvesting Applications
Adaptive Prescribed-Time Consensus for a Class of Nonlinear Multi-Agent Networks by Bounded Time-Varying Protocols
A Ku-Band CMOS Power Amplifier With Series-Shunt LC Notch Filter for Satellite Communications
A 1-8b Reconfigurable Digital SRAM Compute-in-Memory Macro for Processing Neural Networks
Design of Miniaturized Sub-6 GHz Rectifier With Self-Impedance Matching Technique
Predictor-Based Neural Dynamic Surface Control of a Nontriangular System With Unknown Disturbances
A 0.65-pJ/bit 3.6-TB/s/mm I/O Interface With XTalk Minimizing Affine Signaling for Next-Generation HBM With High Interconnect Density
Adaptive Neural Control of Superheated Steam System in Ultra-Supercritical Units With Output Constraints Based on Disturbance Observer
A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS
Efficient Soft-Output Gauss-Seidel Data Detector for Massive MIMO Systems
Output Feedback-Based Neural Adaptive Finite-Time Containment Control of Non-Strict Feedback Nonlinear Multi-Agent Systems
H∞ Stabilization of Discrete-Time Nonlinear Semi-Markov Jump Singularly Perturbed Systems With Partially Known Semi-Markov Kernel Information
BSTCIM: A Balanced Symmetry Ternary Fully Digital In-MRAM Computing Macro for Energy Efficiency Neural Network
An X-Band CMOS VCO Using Ultra-Wideband Dual Common-Mode Resonance Technique
Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder
LearnAFE: Circuit-Algorithm Co-Design Framework for Learnable Audio Analog Front-End
Analysis and Design of Quasi-Circulating Quadrature Hybrid for Full-Duplex Wireless
Distributed Adaptive Resilient Formation Control of Uncertain Nonholonomic Mobile Robots Under Deception Attacks
Practical Prescribed-Time Consensus of Uncertain Multi-Agent Systems via Intermittent Dynamic Event-Triggered Control
Modeling of Izhikevich Spiking Neurons With High Matching Accuracy Using Comb-Exp Functions and Its Multiplier-Free Realization
Data-Driven Resilient Control for Linear Discrete-Time Multi-Agent Networks Under Unconfined Cyber-Attacks
Analysis and Design of EIT-Like Magnetic Coupling Wireless Power Transfer Systems
Accurate Crosstalk Noise Modeling and Analysis of Non-Identical Lossy Interconnections Using Convex Optimization Method
A Chopper-Stabilized Switched-Capacitor Front-End for Peripheral Nervous System Recording
A Wide-Input-Range Time-Based Buck Converter With Adaptive Gain and Continuous Phase Preset for Seamless PFM/PWM Transitions
Winograd for NTT: A Case Study on Higher-Radix and Low-Latency Implementation of NTT for Post Quantum Cryptography on FPGA
Scalable Double Crosstalk Canceling Digital Predistortion for MIMO Transmitters
LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization
Discovering Important Nodes of Complex Networks Based on Laplacian Spectra
Efficient Hardware Implementations of Legendre Symbol Suitable for MPC Applications
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures
Sub-ppm/°C Bandgap References With Natural Basis Expansion for Curvature Cancellation
Anti-Aliasing and Anti-Color-Artifact Demosaicing for High-Resolution CMOS Image Sensor
Low-Complexity Parallel Min-Sum Medium-Density Parity-Check Decoder for McEliece Cryptosystem
Prescribed-Time Input-to-State Stabilization of Normal Nonlinear Systems by Bounded Time-Varying Feedback
Distributed Secondary Resilient Controller Design for Islanded AC Microgrids Under Stealthy Frequency Sensor Attack
A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs
UniDec: A Unified Factor-Graph-Based Decoder Fully Compatible With 5G NR LDPC/Polar Codes
Distributed Fault-Tolerant Consensus Tracking Control of Multi-Agent Systems Under Fixed and Switching Topologies
PRADO: A Low-Latency and Energy-Efficient 6DoF Pose Refinement Accelerator With Domain-Specific Explorations
Non-Volatile Approximate Arithmetic Circuits Using Scalable Hybrid Spin-CMOS Majority Gates
Flat-Group-Delay RF Planar Filters With Transmission Zeros Using Transversal Circuits
A Universal, Analog, In-Memory Computing Primitive for Linear Algebra Using Memristors
Expectation-Maximization Based Disturbance Identification and Velocity Tracking for Gimbal Servo Systems With Dynamic Imbalance
Channel Estimation Using Deep Learning on an FPGA for 5G Millimeter-Wave Communication Systems
Variation Aware Evaluation Approach and Design Methodology for SOT-MRAM
Firing Patterns and Synchronicity of Locally Active Memristor-Based Neuromorphic Circuits
Parallel Delta-Sigma Modulator-Based Digital Predistortion of Wideband RF Power Amplifiers
A 69MHz-Bandwidth 40V/μ s-Slew-Rate 3n V/√Hz-Noise 4.5 μ V-Offset Chopper Operational Amplifier
A W-Band 2 × 2 Phased-Array Transmitter With Digital Gain-Compensation Technique
Exploiting Wireless Technology for Energy-Efficient Accelerators With Multiple Dataflows and Precision
Investigation to Dual-Frequency Direct Digital Synthesis and Resonance Frequency Tracking in Power Ultrasonic Generator
X-Band Power Divider Design and Its Network for Active Electronically Scanned Array Vertical Integration
An RF Energy Harvesting and Power Management Unit Operating Over -24 to +15 dBm Input Range
A 660 MHz-5 GHz 6-Phase/3-Phase Transmitter With Cancellation of Counter-Intermodulation Distortion and Improved Image Rejection
A 36.8-μW 66 nV/√Hz 85.7 dB-System-SNDR Reconfigurable Single-Channel ExG Acquisition System for Bio-Sensor Modules
Three Time-Scale Singular Perturbation Hybrid Control and Large-Signal Analysis Stability in AC-Microgrids
Analysis of Inductor Current Ripple Minimization in PV-Fed Modular Multilevel DC-DC Converter With Distributed MPPT Control
On the Resilience Analysis of DC Microgrids With Power Buffer Control
Constant Power-Constant Voltage Battery Charging Based on a Loss-Free Resistor Approach
Analysis and Design of High-Efficiency Charge Pumps With Improved Current Driving Capability Using Gate Voltage Boosting Technique
An 11-bit 360-MS/s Pipelined SAR ADC With Feedback Factor Compensation Using a Dynamic Negative-C-Assisted Residue Amplifier
A Cryogenic CMOS Current Integrator and Correlation Double Sampling Circuit for Spin Qubit Readout
Co-Event-Triggered Estimation and Control for DC Microgrids With Distributed Switching Encryption: Privacy Guarantees Under Active Eavesdropper
Memristor-Based Large-Scale High-Radix FFT Circuit Design in NR System
A Metal-Via Resistance Based Physically Unclonable Function With Backend Incremental ADC
Enhanced Dual-Mode Reciprocal Doherty Power Amplifier Using Modified Combining Load and Parameter Sweeping Analysis
Differentially Private Distributed Optimization With an Event-Triggered Mechanism
An Energy-Efficient Domain-Specific Reconfigurable Array Processor With Heterogeneous PEs for Wearable Brain-Computer Interface SoCs
A 4-22 GHz Ultra-Wideband Low-Noise Amplifier With 0.8-1.5 dB NF and 28-31 dB Gain Enhanced by the Negative Load Impedance
A 0.3-mm 2 1.3 μW Wireless Monitoring System IC for Hermeticity Testing of Biomedical Implants
A Self-Decryption Pass Transistor Logic-Based In-MRAM Computing Macro Using Hybrid VGSOT-MTJ/GAA-CNTFET
A Smoothed LASSO-Based DNN Sparsification Technique
Analysis and Design of Class-E M Power Amplifier at Subnominal Operation
Optimized and Automated Secure IC Design Flow: A Defense-in-Depth Approach
Impedance Shaping Control Strategy for Wireless Power Transfer System Based on Dynamic Small-Signal Analysis
A Novel In-Memory Wallace Tree Multiplier Architecture Using Majority Logic
The Hidden Behavior of a D-Latch
Low-Latency Low-Complexity Method and Architecture for Computing Arbitrary Nth Root of Complex Numbers
A 0.0058-mm 2 Inductor-Less CMOS Active Balun With Gain and Phase Errors Within -0.1 ± 0.2 dB and -0.18 ± 1.17 ° From DC to 8 GHz
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique
A Millimeter-Wave CMOS VCO Featuring a Mode-Ambiguity-Aware Multi-Resonant-RLCM Tank
Data-Driven Attack Detection and Identification for Cyber-Physical Systems Under Sparse Sensor Attacks: Iterative Reweighted l 2 /l 1 Recovery Approach
A Novel Topology of Coupled Phase-Locked Loops
Applications of Artificial Intelligence on the Modeling and Optimization for Analog and Mixed-Signal Circuits: A Review
Reciprocity and Inter-Reciprocity: A Tutorial - Part I: Linear Time-Invariant Networks
Double-Conversion, Noise-Cancelling Receivers Using Modulated LNTAs and Double-Layer Passive Mixers for Concurrent Signal Reception With Tuned RF Interface
A G m -Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing
A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS
A Foreground Calibration for M-Channel Time-Interleaved Analog-to-Digital Converters Based on Genetic Algorithm
A 40-GHz Load Modulated Balanced Power Amplifier Using Unequal Power Splitter and Phase Compensation Network in 45-nm SOI CMOS
An Adaptive Fully Integrated Dual-Output Energy Harvesting System With MPPT and Storage Capability
A Digital Signature Architecture Suitable for V2V Applications
Design of Loss-Free Resistors Terminated at a Generic Nonlinear Static Load
MERRC: A Memristor-Enabled Reconfigurable Low-Power Reservoir Computing Architecture at the Edge
Adaptive Event-Triggered SMC for Stochastic Switching Systems With Semi-Markov Process and Application to Boost Converter Circuit Model
A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators
Two- and Three-Way Filtering Power Dividers With Harmonic Suppression Using Triangle Patch Resonator
Adequacy of Reduced-Order DFIG Models for Dynamic Stability Assessment
Broadband Mismatch Calibration for Time-Interleaved ADC Based on Linear Frequency Modulated Signal
Simplified ADP-Based Distributed Event-Triggered Fault-Tolerant Control of Heterogeneous Nonlinear Multiagent Systems With Full-State Constraints
Exponential Synchronization of Complex Networks: An Intermittent Adaptive Event-Triggered Control Strategy
Hardware-Efficient SoftMax Architecture With Bit-Wise Exponentiation and Reciprocal Calculation
A Dynamic Event-Triggered Approach to State Estimation for Switched Memristive Neural Networks With Nonhomogeneous Sojourn Probabilities
A 16-bit 4-MS/s SAR ADC With Dual-Segmental Bit Weight Self-Calibration
Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAM
Modeling of CMOS Integrated Strain Sensors and Sensitivity Enhanced Readout Architecture
Discrete Memristor Hyperchaotic Maps
Process-Variation-Aware In-Memory Computation With Improved Linearity Using On-Chip Configurable Current-Steering Thermometric DAC
Virtual Actuator and Sensor Fault Tolerant Consensus for Homogeneous Linear Multi-Agent Systems
A Radio-Frequency Cross-Connected Rectifier With LC Source Degeneration
Ferroelectric FET-Based Bayesian Inference Engine for Disease Diagnosis
MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM
Distributed Time-Varying Optimization for High-Order Linear Multi-Agent Systems With Applications in Battery Energy Storage Systems
Second-Order Transimpedance Amplifiers in Mixer-First Receivers: Design for Optimum Blocker Tolerance
Distributed Hybrid-Triggered Observer-Based Secondary Control of Multi-Bus DC Microgrids Over Directed Networks
Area, Time and Energy Efficient Multicore Hardware Accelerators for Extended Merkle Signature Scheme
Hardware Topologies for Decentralized Large-Scale MIMO Detection Using Newton Method
Broadband Amplifier Design Technique by Dissipative Matching Networks
Noise-Shaping SAR ADC Using a Two-Capacitor Digitally Calibrated DAC With 82.6-dB SNDR and 90.9-dB SFDR
Design of Digital OTAs With Operation Down to 0.3 V and nW Power for Direct Harvesting
Implementation of an On-Chip Learning Neural Network IC Using Highly Linear Charge Trap Device
Implementation of Linear Differential Equations Using Pulse-Coupled Oscillators With an Ultra-Low Power Neuromorphic Realization
A Compact 1.0-12.5-GHz LNA MMIC With 1.5-dB NF Based on Multiple Resistive Feedback in 0.15-μm GaAs pHEMT Technology
Neural Synaptic Plasticity-Inspired Computing: A High Computing Efficient Deep Convolutional Neural Network Accelerator
Generalization and Differentiation Circuit Design Based on Memristor Under Different Emotional Conditions
Efficient Design and Implementation of Scale-Free CORDIC With Mutually Exclusive Micro-Rotations
Event-Triggered Adaptive Fault-Tolerant Control for a Class of Nonlinear Multiagent Systems With Sensor and Actuator Faults
Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories
Distributed Sparse LQR Control for Power Systems With Markov Jump Interconnection Topologies
Spiking Cochlea With System-Level Local Automatic Gain Control
PipeCIM: A High-Throughput Computing-In-Memory Microprocessor With Nested Pipeline and RISC-V Extended Instructions
3-12-V Wide Input Range Adaptive Delay Compensated Active Rectifier for 6.78-MHz Loosely Coupled Wireless Power Transfer System
A 2 μ A I q Passive-Ramp-Adaptive-Extended-T ON Controlled Buck Converter Leveraging Clamped Adaptive Biased Error Amplifier to Achieve DVS/Load Transient One-Cycle Recovery Time
Gain-Scheduling Fault Estimation for Discrete-Time Takagi-Sugeno Fuzzy Systems: A Depth Partitioning Approach
The Dickson Charge Pump as a Signal Amplifier
Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction
Observer-Based Adaptive Neural Output Feedback Constraint Controller Design for Switched Systems Under Average Dwell Time
Data-Driven Event-Triggered Fixed-Time Load Frequency Control for Multi-Area Power Systems With Input Delays
Low-Complexity Resource-Shareable Parallel Generalized Integrated Interleaved Encoder
Analysis and Design of a 15.2-to-18.2-GHz Inverse-Class-F VCO With a Balanced Dual-Core Topology Suppressing the Flicker Noise Upconversion
Predefined Finite-Time Output Containment of Nonlinear Multi-Agent Systems With Leaders of Unknown Inputs
A Graph Transformer-Driven Approach for Network Robustness Learning
A Weak PUF-Assisted Strong PUF With Inherent Immunity to Modeling Attacks and Ultra-Low BER
A Phase Interpolated Dual-Phase Adaptive On-Time Controlled Buck Converter
KERNTROL: Kernel Shape Control Toward Ultimate Memory Utilization for In-Memory Convolutional Weight Mapping
Reinforcement Learning-Based Power Management Policy for Mobile Device Systems
Reinforcement Learning Solutions to Stochastic Multi-Agent Graphical Games With Multiplicative Noise
Accelerating Deep Convolutional Neural Networks Using Number Theoretic Transform
A Novel CHB-Based Photovoltaic Grid-Tied System Integration of Centralized Energy Storage and Its Power Security Domain
Intrusion-Detector-Dependent Distributed Economic Model Predictive Control for Load Frequency Regulation With PEVs Under Cyber Attacks
Dual-Band Bandpass Filter Based on Suspended Coplanar Waveguide-Microstrip Hybrid
Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme
Adaptive Formation for Multiagent Systems Subject to Denial-of-Service Attacks
Efficient Schemes and Architectures for Check Node Update in Shuffled Min-Sum Decoding of LDPC Codes
RDCIM: RISC-V Supported Full-Digital Computing-in-Memory Processor With High Energy Efficiency and Low Area Overhead
Distributed Estimation and Smoothing for Linear Dynamic Systems Over Sensor Networks
60-dB 70-V/μs Three-Stage Op-Amp With Dual Single-Miller Frequency Compensation in GaN-IC Technology
Dual-Band Multi-Resonant Class-E Inverter With Load-Independent CC/CV Output
A Priori-Knowledge-Free Real-Valued Capon-Like Method and Implementation on FPGA
Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell
An Efficient Unstructured Sparse Convolutional Neural Network Accelerator for Wearable ECG Classification Device
A Sub-1 V 90 dB-SNDR Power/BW Scalable DTDSM Using Low-Voltage Cascoded Floating Inverter Amplifiers in 130 nm CMOS
Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus
CAMiSE: Content Addressable Memory-Integrated Searchable Encryption
High-Throughput LDPC Decoder for Multiple Wireless Standards
A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs
Ferroelectric FET Nonvolatile Sense-Amplifier-Based Flip-Flops for Low Voltage Operation
Accurate Modeling of Transformer-Based Voltage-Multiplier Considering Reverse Recovery Process of the Leakage Inductance in Step-up Converter
A Highly Power- and Area-Efficient PMU for Cell-Size Autonomous Microsystems
A Duty-Cycle-Error-Immune Reference Frequency Doubling Technique for Fractional-N Digital PLLs
Random Telegraph Noise in Analog CMOS Circuits
Iteration and SDA-Driven LDPC Decoding Latency Reduction for 3-D TLC NAND Flash Memory
Satisfiability Attack-Resilient Camouflaged Multiple Multivariable Logic-in-Memory Exploiting 3D NAND Flash Array
False Data Injection Attacks on LFC Systems: An AI-Based Detection and Countermeasure Strategy
A 32-Bit Ripple-Ling Hybrid Carry Adder
A Fully Integrated Low-Power Hall-Based Isolation Amplifier With IMR Greater Than 120 dB
Spur Immunity in MASH-Based Fractional-N CP-PLLs With Polynomial Nonlinearities
Intelligent Control of Performance Constrained Switched Nonlinear Systems With Random Noises and Its Application: An Event-Driven Approach
Reconciliation of Statistical Approaches to Predicting Nonlinearity-Induced Spurs in Fractional-N Frequency Synthesizers
Variability-Aware Approximate Circuit Synthesis via Genetic Optimization
Non-Local Mean Denoising of Multi-Layer With Adaptive Filtering Strength Based on ASIC Implementation
A Low-Latency Feed-Forward Architecture for Image Filtering via Row-by-Row Processing
FPGA Implementation of Non-Commensurate Fractional-Order State-Space Models
Low-Power Subthreshold Voltage References for High-Temperature Applications
Recoding Hybrid Stochastic Numbers for Preventing Bit Width Accumulation and Fault Tolerance
OD-TGCN: An Observer-Driven Temporal Graph Convolutional Network for Early Fault Detection of Control Systems
A Flexible and Efficient FPGA Accelerator for Various Large-Scale and Lightweight CNNs
Statistical Post-FEC BER Estimation of High-Speed Serial Links Subject to DFE Error Propagation
A High-Throughput FPGA Accelerator for Lightweight CNNs With Balanced Dataflow
A Reconfigurable Wireless Power Receiver With Shared-Inductor Buck-Boost Converter for NFC-Powered Battery-Less Electronic Shelf Label
Stability Conditions for Cluster Synchronization in Directed Networks of Diffusively Coupled Nonlinear Systems
On the Fulfilment of the Gain and Matching Specifications in the Design of a Single-Stage High-Frequency Amplifier
Comments on "Adaptive Continuous Barrier Function Terminal Sliding Mode Control Technique for Disturbed Robotic Manipulator"
All-Port-Reflectionless Narrowband Filtering Power Divider Topology With Generic Equations
Influence Analysis of Oscillation Harmonics in LCC-HVDC Delivery System Based on Impedance Modeling
Dynamic Quantization Driven Synchronization of Networked Systems Under Event-Triggered Mechanism
A 2-Channel Time-Interleaved Noise-Shaping SAR ADC Directly Powered by a DC-DC Converter
An AFD-Based ILC Dynamics Adaptive Matching Method in Frequency Domain for Distributed Consensus Control of Unknown Multiagent Systems
On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning
A General Efficiency Enhancement Method for Compact Broadband Rectifiers
A Broadband Fully Integrated Power Amplifier Using Waveform Shaping Multi-Resonance Harmonic Matching Network
Systematic Design of a 3.5 GS/s 11-bit Time-Interleaved SAR ADC in 28 nm CMOS Achieving 54 dB SNDR at Nyquist Frequency
Stereo Matching Accelerator With Re-Computation Scheme and Data-Reused Pipeline for Autonomous Vehicles
A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces
An Ultra-Low-Power Octave-Tuning VCO IC With a Single Analog Voltage-Controlled Novel Varactor
A PAM-4 Crosstalk Compensation Receiver Using an RC Circuit per Pin for 4×24 Gb/s/Pin Single-Ended DRAM Interface
Neural Network Adaptive Control of Magnetic Shape Memory Alloy Actuator With Time Delay Based on Composite NARMAX Model
An Output Voltage Tracking Control Method With Overcurrent Protection Property for Disturbed DC-DC Boost Converters
Gain-Boosted Super Class AB OTAs Based on Nested Local Feedback
Real-Valued Discrete Fractional Hadamard Transform: Fast Algorithms and Implementations
Towards Safe and Robust Closed-Loop Artificial Pancreas Using Improved PID-Based Control Strategies
A 362-TOPS/W Mixed-Signal MAC Macro With Sampling-Weight-Nonlinearity Cancellation and Dynamic-Amplified Accumulation
An Efficient Asymmetric Outphasing Power Amplifier With Extended Back-Off Range for 5G Applications
Outgoing Editorial
Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS
Small Signal Modeling of a Four-Level Flying Capacitor Multilevel Totem-Pole PFC Converter
Digital Approach In Case of FPGA Realization of Quartic Neuron Model (QNM) Using Cost-Effective Mathematical Modifications
Compact Balanced-to-Balanced Filtering Power Divider With Wide Range and High Level of Reflectionless, Isolation, Common-Mode Rejection, and Enhanced Frequency Selectivity
Synthesis of Constant Power Loads Using Switching Converters Under Sliding-Mode Control
A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition
Distributed Adaptive Finite-Time Compensation Control for UAV Swarm With Uncertain Disturbances
Two Efficient Approximate Unsigned Multipliers by Developing New Configuration for Approximate 4:2 Compressors
Trade-Off-Oriented Impedance Optimization of Chiplet-Based 2.5-D Integrated Circuits With a Hybrid MDP Algorithm for Noise Elimination