yusuke1997/dblp-id-title huggingface dataset:
Fault Simulation for Analog Circuits Under Parameter Variations
A Gated Clock Scheme for Low Power Testing of Logic Cores
A CMOS Ripple Detector for Voltage Regulator Testing
Behavioral-Level DFT via Formal Operator Testability Measures
Fault Tolerant Single Error Correction Encoders
Optimizing error masking in BIST by output data modification
Fault Diagnosis in Highly Dependable Medical Wearable Systems
Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors
A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology
Efficient Path Selection for Delay Testing Based on Path Clustering
A Hilbert-Transform-Based Method to Estimate and Correct Timing Error in Time-Interleaved ADCs
Minimal March Tests for Detection of Dynamic Faults in Random Access Memories
Digital Predistortion for Spectrum Compliance in the Internet of Things
ADC Non-Linearity Low-Cost Test Through a Simplified Double-Histogram Method
Design of Nonlinear CA Based TPG Without Prohibited Pattern Set In Linear Time
Application of the Kalman Filter in Linearity Testing of Analog-to-Digital Converters
Extending a DWDM Optical Network Test System to 12 Gbps x4 Channels
Boundary scan test, test methodology, and fault modeling
Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets
Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test
Application of Deterministic Logic BIST on Industrial Circuits
Synthesis of Reversible Circuits with Reduced Nearest-Neighbor Cost Using Kronecker Functional Decision Diagrams
On-Wafer Calibration Technique for High Frequency Measurement with Simultaneous Voltage and Current Tuning
Spectrum Analyzer Based on a Dynamic Filter
Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing
Testability analysis and fault modeling of BiCMOS circuits
Fault Detection and Diagnosis of DMFB Using Concurrent Electrodes Actuation
A Cost-efficient Input Vector Monitoring Concurrent On-line BIST Scheme Based on Multilevel Decoding Logic
Erratum to: A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator
On minimal set of test nodes for fault dictionary of analog circuit fault diagnosis
Automated Design Error Debugging of Digital VLSI Circuits
Fault Modeling and Multi-Tone Dither Scheme for Testing 3D TSV Defects
TIES: A testability increase expert system for VLSI design
A Multi-Objective Test Scenario Prioritization Method Based on UML Activity Diagram
A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST
Extended selection of switching target faults in CONT algorithm for test generation
An On-Chip Spectrum Analyzer for Analog Built-In Testing
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs
Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications
On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines
A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash
Reduced Latch Count Shift Registers
Testing of multi-output circuits by means of signature analyzer
Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism
Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints
A Review of Various Defects in PCB
Delay Fault Coverage Enhancement Using Variable Observation Times
Low-Cost 20 Gbps Digital Test Signal Synthesis Using SiGe and InP Logic
X-tolerant Test Data Compaction with Accelerated Shift Registers
A New Design Method for Self-Checking Unidirectional Combinational Circuits
Monitoring Power Dissipation for Fault Detection
A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs
Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips
New Editors - 2015
A Survey of PCB Defect Detection Algorithms
Optimal Selective Count Compatible Runlength Encoding for SOC Test Data Compression
Analog Circuit Test Point Selection Incorporating Discretization-Based Fuzzification and Extended Fault Dictionary to Handle Component Tolerances
Experimental Results on BIC Sensors for Transient Current Testing
Test Planning in Digital Microfluidic Biochips Using Efficient Eulerization Techniques
Reliability Model and Sensitivity Analysis for General Electronic Systems with Failure Types based on Non-identical Correlated Components
High-Dimensional Feature Fault Diagnosis Method Based on HEFS-LGBM
Count Your Toggles: a New Leakage Model for Pre-Silicon Power Analysis of Crypto Designs
Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes
A Layout-Based Rad-Hard DICE Flip-Flop Design
Time Complexity Comparison of Stopping at First Failure and Completely Running the Test
Modeling the Effect of Process, Power-Supply Voltage and Temperature Variations on the Timing Response of Nanometer Digital Circuits
Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids
Authors' reply to comments on "Aliasing Properties of Circular MISRs"
Multiple Experiment Environments for Testing
Instruction-Vulnerability-Factor-Based Reliability Analysis Model for Program Memory
Minimal cost one-dimensional linear hybrid cellular automata of degree through 500
A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs
Enhanced Low Complex Double Error Correction Coding with Crosstalk Avoidance for Reliable On-Chip Interconnection Link
An Effective and Accurate Methodology for the Cell Internal Defect Diagnosis
A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design
Incorporating I DDQ Testing with BIST for Improved Coverage: An Experimental Study
Functional Test of Mesh-Based NoCs with Deterministic Routing: Integrating the Test of Interconnects and Routers
Model-based reasoning for electron-beam debugging of VLSI circuits
On-Chip Clock Faults' Detector
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs
Dynamic Smartcard Protection and SSELUR-GRU-Based Attack Stage Identification in Industrial IoT
Analysing NBTI Impact on SRAMs with Resistive Defects
Securing Scan Control in Crypto Chips
Failure Analysis and Power-on Sequence Optimization for InP DHBT Stacked Amplifiers
A Low-cost BIST Design Supporting Offline and Online Tests
Clocked Dosimeter Compatible with Digital CMOS Technology
Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications
A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment
LFSR Reseeding-Oriented Low-Power Test-Compression Architecture for Scan Designs
Deterministic Built-in Pattern Generation for Sequential Circuits
Machine Learning for Hardware Security: Opportunities and Risks
Multi-Objective Optimization Based Test Pattern Generation for Hardware Trojan Detection
A Test Generation Methodology for Interconnection Opens Considering Signals at the Coupled Lines
NBTI-Aware Design of Integrated Circuits: A Hardware-Based Approach for Increasing Circuits' Life Time
Journal of Electronic Testing: Theory and Applications New Editors - 2023
A Novel Two-Stage Model Based SCA against secAES
Current-Based Testing, Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT
Application of Machine Learning Techniques in Post-Silicon Debugging and Bug Localization
Hierarchical Verification for Increasing Performance in Reliable Processors
Scan Division Algorithm for Shift and Capture Power Reduction for At-Speed Test Using Skewed-Load Test Application Strategy
Boundary scan in board manufacturing
Near-optimal tests for classes of write-triggered coupling faults in RAMs
On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST
A Study of PN Junction Diffusion Capacitance of MOSFET in Presence of Single Event Transient
Error-Efficient Approximate Multiplier Design using Rounding Based Approach for Image Smoothing Application
On IEEE P1500's Standard for Embedded Core Test
Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects
Adaptive Fault Diagnosis of Analog Circuits by Operation-Region Model and X - Y Zoning Method
Trade-off Mechanism Between Reliability and Performance for Data-flow Soft Error Detection
Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits
SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement
Performance-Optimized Design for Parametric Reliability
Digital Test Method for Embedded Converters with Unknown-Phase Harmonics
A Wideband Digital-to-Frequency Converter with Built-In Mechanism for Self-Interference Mitigation
A New Analog Circuit Fault Diagnosis Method Based on Improved Mahalanobis Distance
One-to-Many: Context-Oriented Code for Concurrent Error Detection
A Novel RF Test Scheme Based on a DFT Method
High Speed Error Tolerant Adder for Multimedia Applications
Fault-tolerance in balanced sorting networks
Optimal Selection of Tests for Fault Diagnosis in Multi-Path System with Time-delay
Fault simulation for mixed-signal systems
Synthesis of Native Mode Self-Test Programs
On Faster I DDQ Measurements
Harzard-Based ATPG for Improving Delay Test Quality
SEU Fault-Injection in VHDL-Based Processors: A Case Study
Improving Reconfigurable Systems Reliability by Combining Periodical Test and Redundancy Techniques: A Case Study
Fault Models for Quantum Mechanical Switching Networks
A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems
Test Set Compaction Using Relaxed Subsequence Removal
A Better Method than Tail-fitting Algorithm for Jitter Separation Based on Gaussian Mixture Model
Efficient Designs of Reversible Majority Voters
Deterministic BIST with Multiple Scan Chains
Reduction of Number of Paths to be Tested in Delay Testing
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper
The Effect of Temperature-Induced Quiescent Operating Point Shift on Single-Event Transient Sensitivity in Analog/Mixed-Signal Circuits
An Analog Circuit Fault Characterization Methodology
Multiple error detection and identification via signature analysis
Single- and Double-Output Embedded Checker Architectures for Systematic Unordered Codes
Detectability Conditions of Full Opens in the Interconnections
Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy
Low-Distortion Sinewave Generation Method Using Arbitrary Waveform Generator
Light Emission Tracking and Measurements for Analog Circuits Fault Diagnosis in Automotive Applications
Electro-thermal Stimuli for MEMS Testing in FSBM Technology
An efficient built-in self test method for robust path delay fault testing
Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach
Low-Power Area-Efficient Fault Tolerant Adder in Current Mode Multi Valued Logic Using Berger Codes
2020 JETTA Reviewers
Testability Properties of Divergent Trees
Secure JTAG Implementation Using Schnorr Protocol
Testing of Oscillators
SFFHO: Development of Statistical Fitness-based Fire Hawk Optimizer for Software Testing and Maintenance Approach using Adaptive Deep Learning Method
Mahalanobis Distance Based Approach for Anomaly Detection of Analog Filters Using Frequency Features and Parzen Window Density Estimation
High Performance Approximate Memories for Image Processing Applications
Guaranteed fault detection sequences for single transition faults in finite state machine models using concurrent fault simulation
Compressed Bit Fail Maps for Memory Fail Pattern Classification
An Efficient Dictionary Organization for Maximum Diagnosis
A method for automatic design error location and correction in combinational logic circuits
Cost based surface mount PCB design evaluation
Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells
A Routability-Aware Algorithm for Both Global and Local Interconnect Resource Test and Diagnosis of Xilinx SRAM-FPGAs
Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs
An Accumulator-Based BIST Approach for Two-Pattern Testing
Hierarchical Delay Test Generation
New Second-order Threshold Implementation of Sm4 Block Cipher
A Flexible Approach for Defining Distributed Dependable Tests in SNMP-Based Network Management Systems
Frequency Response Verification of Analog Circuits Using Global Optimization Techniques
A Fault Tolerant Approach for FPGA Embedded Processors Based on Runtime Partial Reconfiguration
Pebble Traversal-Based Fault Detection and Advanced Reconfiguration Technique for Digital Microfluidic Biochips
Dynamic Threshold Delay Characterization Model for Improved Static Timing Analysis
Synthesis of Scan Chains for Netlist Descriptions at RT-Level
Towards the Detection of Hardware Trojans with Cost Effective Test Vectors using Genetic Algorithm
Reverse Breakdown Voltage Measurement for Power P + NN + Rectifier
Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits
A Totally Self-Checking 1-out-of-3 Code Error Indicator
A Novel EDA Tool for VLSI Test Vectors Management
Algorithms to select I DDQ measurement points to detect bridging faults
High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design
On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits
Exemplar-based Failure Triage for Regression Design Debugging
Low Delay 3-Bit Burst Error Correction Codes
Scalable Test Generators for High-Speed Datapath Circuits
Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability
Concurrent Error Detection in a Polynomial Basis Multiplier over GF(2 m )
Test Data Compression Using Multi-dimensional Pattern Run-length Codes
Energy minimization and design for testability
Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables
Hybrid Ring Generators for In-System Testing
Modular implementation of efficient self-checking checkers for the Berger code
Non-Invasive Hardware Trojans Modeling and Insertion: A Formal Verification Approach
Mutation Analysis and Constraint-Based Criteria: Results from an Empirical Evaluation in the Context of Software Testing
Memory-Aware Design Space Exploration for Reliability Evaluation in Computing Systems
A Time-Domain Digital-Intensive Built-In Tester for Analog Circuits
2021 Reviewers
Built-in Test with Modified-Booth High-Speed Pipelined Multipliers and Dividers
An optimal algorithm for cycle breaking in directed graphs
Partial Virtual Channel Sharing: A Generic Methodology to Enhance Resource Management and Fault Tolerance in Networks-on-Chip
A Novel Test Point Selection Method for Analog Fault Dictionary Techniques
Cohesive Coverage Management: Simulation Meets Formal Methods
The SigmaDelta-BIST Method Applied to Analog Filters
Concurrent Delay Testing in Totally Self-Checking Systems
Generating a family of testable designs using the BILBO methodology
Methods of Testing Discrete Semiconductors in the 1149.4 Environment
On the Reuse of TLM Mutation Analysis at RTL
New Lightweight Architectures for Secure FSM Design to Thwart Fault Injection and Trojan Attacks
A Note on System-on-Chip Test Scheduling Formulation
LEAP: An Accurate Defect-Free I DDQ Estimator
2014 JETTA-TTTC Best Paper Award
Low Power BIST by Filtering Non-Detecting Vectors
Single-Event Transient Measurements on a DC/DC Pulse Width Modulator Using Heavy Ion, Proton, and Pulsed Laser
Combining Functional and Structural Approaches for Switched-Current Circuit Testing
Enhancing design-for-test for active analog filters by using CLP
Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer
Development of a Simplified Programming Kit Based 16LF18856 for Embedded Systems Testing and Education in Developing Countries
Aging-Resilient SRAM-based True Random Number Generator for Lightweight Devices
A Novel Framework For Optimal Test Case Generation and Prioritization Using Ent-LSOA And IMTRNN Techniques
A Fast Statistical Soft Error Rate Estimation Method for Nano-scale Combinational Circuits
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits
Design-For-Test in a Multiple Substrate Multichip Module
A Fault Verification Method Based on the Substitution Theorem and Voltage-Current Phase Relationship
A Combined Clustering and Neural Network Approach for Analog Multiple Hard Fault Classification
Modeling of Physical Defects in PN Junction Based Graphene Devices
Multi-VDD Testing for Analog Circuits
Modeling and Evaluating Errors Due to Random Clock Shifts in Quantum-Dot Cellular Automata Circuits
Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor
A Novel Fault Localization Technique Based on Deconvolution and Calibration of Power Pad Transients Signals
A Method of Formal Verification of Cryptographic Circuits
Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption
A Unity Gain High Speed Buffer to Improve Signal Integrity in High Frequency Test Interface
Yield Improvement for 3D Wafer-to-Wafer Stacked Memories
Delivering Dependable Telecommunication Services Using Off-the-Shelf System Components
Proposal of Fault Diagnosis of Analog Circuits by Combining Operation-Region Model and X - Y Zoning Method: Case Study
Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack
An Algebraic Approach to Formal Verification of Microprocessors
On Concurrent Test of Core-Based SOC Design
Analyzing the Effectiveness of Various NMOS Layouts for Total Ionizing Dose Hardening in 180nm CMOS
Uncertainty-Aware Crosstalk Predictors for Adaptive Reliability in Core Interconnects
An Access Mechanism for Embedded Sensors in Modern SoCs
An Analytic Model for Predicting Single Event (SE) Crosstalk of Nanometer CMOS Circuits
Incremental Testability Analysis for Partial Scan Selection and Design Transformations
Design of High Speed Error Tolerant Adder Using Gate Diffusion Input Technique
Efficient multiple path propagating tests for delay faults
Majority Logic Mapping for Soft Error Dependability
Low Cost Time Efficient Multi-tone Test Signal Generation Using OFDM Technique
A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis
Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability
Modulo p =3 Checking for a Carry Select Adder
Design for Testability Techniques at the Behavioral and Register-Transfer Levels
TRAP-GATE: A Probabilistic Approach to Enhance Hardware Trojan Detection and its Game Theoretic Analysis
Testing of Synchronizers in Asynchronous FIFO
Preserving Hamming Distance in Arithmetic and Logical Operations
Bridging defects resistance in the metal layer of a CMOS process
Real Time Fault Diagnosis with Tests of Uncertain Quality for Multimode Systems and its Application in a Satellite Power System
Three-Stage Optimization of Pre-Bond Diagnosis of TSV Defects
Modeling Fault Coverage of Random Test Patterns
Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints
Low Overhead and High Stability Radiation-Hardened Latch for Double/Triple Node Upsets
On-Chip Weighted Random Patterns
Effective Software Mutation-Test Using Program Instructions Classification
Combinatorial Analysis of Check Set Construction for Algorithm-Based Fault Tolerance Systems
Guest Editorial: Analog, Mixed-Signal and RF Testing
Digital Design-for-Diagnosis Method for Error Identification of Pipelined ADCs
On the generation of test patterns for multiple faults
Symbolic Handling of Bridging Fault Effects
A Novel Approach for Diagnosis of Analog Circuit Fault by Using GMKL-SVM and PSO
Reconstruction method for jitter tolerant data acquisition system
Iterative Antirandom Testing
Classification of Defective Analog Integrated Circuits Using Artificial Neural Networks
2016 JETTA-TTTC Best Paper Award - Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu and Kunihiro Asada, "Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing, " Journal of Electronic Testing: Theory and Applications, Volume 32, Number 3, pp. 247-271. June 2016
A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip
Digital Window Comparator DfT Scheme for Mixed-Signal ICs
Test Scheduling for Network-on-Chip Using XY-Direction Connected Subgraph Partition and Multiple Test Clocks
JTAG Security System Based on Credentials
Comparing Graph-Based Algorithms to Generate Test Cases from Finite State Machines
An Integrated on-Silicon Verification Method for FPGA Overlays
Design Considerations for High Performance RF Cores Based on Process Variation Study
Intelligent Analysis and Off-Line Debugging of VLSI Device Test Programs
On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions
On-Chip Delay Measurement Based Response Analysis for Timing Characterization
IC Immunity Modeling Process Validation Using On-Chip Measurements
Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding
A Heuristic Measure to Maximize Detected Faults per Test
The Effectiveness of Test in Controlling Quality Costs: A Conformability Analysis Based Approach
Differential fault simulation for sequential circuits
Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits
Extending Fault-Based Testing to Microelectromechanical Systems
Multi-Step-Ahead Prediction for a CMOS Low Noise Amplifier Aging Due to NBTI and HCI Using Neural Networks
Improving Semiconductor Reliability with Advanced Engineering Methods in Test Program Development
Multichip Module Diagnosis by Product-Code Signatures
Analog Circuit Fault Diagnosis via Sensitivity Computation
Reliability Analysis of Fault-Tolerant Bus-Based Interconnection Networks
Reliability Testing of 3D-Printed Electromechanical Scanning Devices
Controllability of Static CMOS Circuits for Timing Characterization
Formal Verification of Analog and Mixed Signal Designs Using SPICE Circuit Simulation Traces
Delay fault simulation of sequential circuits
Testing Biquad Filters under Parametric Shifts Using X-Y Zoning
A New Built-in TPG Based on Berlekamp-Massey Algorithm
An exact algorithm for selecting partial scan flip-flops
Wafer-level Adaptive Testing Based on Dual-Predictor Collaborative Decision
A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment
Assessing the Reliability of Successive Approximate Computing Algorithms under Fault Injection
A Method of Redundant Feature Suppression in Circuit Output Positions for Analog Circuit Soft and Hard Fault Diagnosis
Efficient Totally Self-Checking Shifter Design
Detection Method of Hardware Trojan Based on Attention Mechanism and Residual-Dense-Block under the Markov Transition Field
Trojan Detection Test for Clockless Circuits
Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation
BIDES: A BIST design expert system
Refined Self-calibration of an Inductorless Low-noise Amplifier with Non-intrusive Circuit
Test Development Through Defect and Test Escape Level Estimation for Data Converters
Analysis of Scheduled Latency Insensitive Systems with Periodic Clock Calculus
Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures
Comments on "Aliasing Properties of Circular MISRs"
A Single Event Upset Resilient Latch Design with Single Node Upset Immunity
Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs
Analysis and Evaluations of Reliability of Reconfigurable FPGAs
Resistance of the Montgomery Ladder Against Simple SCA: Theory and Practice
Defect Detection from Visual Abnormalities in Manufacturing Process Using IDDQ
Double Node Upsets Hardened Latch Circuits
A New Approach to the Analysis of Single Event Transients in VLSI Circuits
Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories