yusuke1997/dblp-id-title huggingface dataset:
Leaving One Slot Empty: Flit Bubble Flow Control for Torus Cache-Coherent NoCs
Conditional Interpretation of Operation Codes
Submicrosecond Core Memories Using Multiple Coincidence
OsmoticGate: Adaptive Edge-Based Real-Time Video Analytics for the Internet of Things
High-Speed Transistorized Adder for a Digital Computer
An Adaptive Multilevel Indexing Method for Disaster Service Discovery
Computing Irredundant Normal Forms from Abbreviated Presence Functions
Antisequential Suffix Sorting for BWT-Based Data Compression
Toward Personalized Federated Meta-Learning With Constrained Hypernetwork on Non-IID Data
AMULET1: A Asynchronous ARM Microprocessor
A Theory of Completely Monotonic Functions and its Applications to Threshold Logic
Minimization of Modulo-2 Sum of Products
An Efficient Formulation of the Real-Time Feasibility Region for Design Optimization
Basic Properties and a Construction Method for Fail-Safe Logical Systems
Stochastic Models for Performance Analysis of Database Recovery Control
An Algebraic Model of Fault-Masking Logic Circuits
Demonstration of Conditional Stability on an Analog Computer
Mitigating Adversarial Attacks Based on Denoising & Reconstruction With Finance Authentication System Case Study
Multithreading in Java: Performance and Scalability on Multicore Systems
High-Performance Hardware Implementation of Crystals-Dilithium Based on Improved MDC-NTT
Interference Analysis of Shuffle/Exchange Networks
Serial Integer Arithmetic with Magnetic Bubbles
Building a Distance Function for Gestalt Grouping
Corrections to 'Arithmetic on the European Logarithmic Microprocessor'
A More Realistic Thinning Scheme for Call Admission Control in Multimedia Wireless Networks
Nonlinear Code-Based Low-Overhead Fine-Grained Control Flow Checking
On-Line CORDIC Algorithms
Expandable and Cost-Effective Network Structures for Data Centers Using Dual-Port Servers
Asynchronous Arbiter Module
A Decoupled Predictor-Directed Stream Prefetching Architecture
A Sampled-Data Analog of Neuron Properties
A Spectral Lower Bound Techniqye for the Size of Decision Trees and Two Level AND/OR Circuits
Subtraction by Minuend Complementation
DCC Linear Congruential Graphs: A New Class of Interconnection Networks
A Microeconomic Approach to Optimal Resource Allocation in Distributed Computer Systems
Gossigping in a Distributed Network
Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions
Flock: Towards Multitasking Virtual Machines for Function-as-a-Service
Concerning Abstracts
The Susceptibility of Programs to Context Switching
An Analog-Digital Character Recognition System
Multivalued I 2 L Circuits for TSC Checkers
Generation of Nonparametric Curves
Performance Prediction and Calibration for a Class of Multiprocessors
Performance of IP-Based Services over GPRS
A Low-Latency Pipelined 2D and 3D CORDIC Processors
Memory Bandwidth Management for Efficient Performance Isolation in Multi-Core Platforms
Realization of a Class of Switching Functions by Threshold-Logic Networks
Revisiting the Optimization of Cauchy Reed-Solomon Coding Matrix for Fault-Tolerant Data Storage
Virtual Checkpoints: Architecture and Performance
Deterministic Learning Automata Solutions to the Equipartitioning Problem
A Modification to the SHR-Optimal State Assignment Procedure
LNS with Co-Transformation Competes with Floating-Point
Applications of CRC-105 decimal digital differential analyzer
Analytical Model for Memory-Centric High Level Synthesis-Generated Applications
A Promise of Realizable, Ultra-Scalable Communications at Nano-Scale: A Multi-Modal Nano-Machine Architecture
On Autonomous NOR Sequential Machines
Multicasting in Quantum Switching Networks
Byte-Oriented Error-Correcting Codes for Semiconductor Memory Systems
A Binary Multiplication Scheme Based on Squaring
Improved Three-Way Split Formulas for Binary Polynomial and Toeplitz Matrix Vector Products
On the Implementation of Failure-Tolerant Counters
Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures
Exact and Approximated Error of the FMA
Hazard Correction in Asynchronous Sequential Circuits
Fault-Tolerant Computing: An Introduction and an Overview
Analysis of Iterative NOR Autonomous Sequential Machines
A DCFL E/D-MESFET GaAs Experimental RISC Machine
Accelerating Address Translation for Virtualization by Leveraging Hardware Mode
PStream: A Popularity-Aware Differentiated Distributed Stream Processing System
EABE-PUFPH: Efficient Attribute-Based Encryption With Reliable Policy Updating Under Full Policy Hiding
Comments on "Self-Stabilizing Programs: The Fault-Tolerant Capability of Self-Checking Programs"
An Autonomous Reading Machine
Magnetic Core Access Switches
A Theorem on Linearity
A Cellular Permuter Array
Characterizing Computers and Optimizing the FACR( l ) Poisson-Solver on Parallel Unicomputers
Fast and Predictable Non-Volatile Data Memory for Real-Time Embedded Systems
Arithmetic Operations in Finite Fields of Medium Prime Characteristic Using the Lagrange Representation
Optimizing Multi-DNN Parallel Inference Performance in MEC Networks: A Resource-Aware and Dynamic DNN Deployment Scheme
Physarum Optimization: A Biology-Inspired Algorithm for the Steiner Tree Problem in Networks
Deep Learning Acceleration Optimization of Stress Boundary Value Problem Solvers
The MOLEN Polymorphic Processor
Adaptive Optimal Load Balancing in a Nonhomogeneous Multiserver System with a Central Job Scheduler
RST Flip-Flop Input Equations
PDG_GEN: A Methodology for Fast and Accurate Simulation of On-Chip Networks
Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays
The Conjectured Highest Scoring Machines for Rado's Σ(k) for the Value k = 4
An Optimal Shortest-Path Routing Policy for Network Computers with Regular Mesh-Connected Topologies
Two Approaches for Increasing Storage Density in Modern Digital Computing Systems
A Reputation-Based Mechanism for Transaction Processing in Blockchain Systems
Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit
Breaking Fault Attack Countermeasures With Side-Channel Information
A New Algorithm for Generating Prime Implicants
PolyLUT: Ultra-Low Latency Polynomial Inference With Hardware-Aware Structured Pruning
The VPC Trace-Compression Algorithms
Logarithmic and Exponential Function Evaluation in a Variable Structure Digital Computer
High-Speed CAM-Based Architecture for a Prolog Machine (ASCA)
Application of Continued Fractions for Fast Evaluation of Certain Functions on a Digital Computer
A Computer Interface for Efficient Zero-Crossing Interval Measurement
On the 2-Dimensional Channel Assignment Problem
An Array Layout Methodology for VLlSI Circuits
A Fast Translation Method for Paging on top of Segmentation
Pattern Matching in LZW Compressed File
Bounds On the Sequency Content of the Circular Functions
Integration and Boost of a Read-Modify-Write Module in Phase Change Memory System
Verification Testing - A Pseudoexhaustive Test Technique
FFT Implementation with Fused Floating-Point Operations
On Realizations of Synchronous Sequential Machines
On a Novel Approach of Fault Detection in an Easily Testable Sequential Machine with Extra Inputs and Extra Outputs
Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty
Randomized Pattern Search
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays
A Dynamically Tunable Memory Hierarchy
Exploiting Compression-Induced Internal Fragmentation for Power-Off Recovery in SSD
Perf&Fair: A Progress-Aware Scheduler to Enhance Performance and Fairness in SMT Multicores
Sampled Simulation of Task-Based Programs
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits
Compressed Sharer Tracking and Relinquishment Coherence for Superior Directory Efficiency of Chip Multiprocessors
Word-Based Montgomery Modular Multiplication Algorithm for Low-Latency Scalable Architectures
On the Complexity of VLSI Implementations and Graph Representations of Boolean Functions with Application to Integer Multiplication
A Case Study of a Versatile Generator of Repeatable Non-Poisson Sequences of Pseudorandom Pulses
On the Discriminant Vector Method of Feature Selection
A Combinatorial Analysis of Subcube Reliability in Hybercubes
A Brief History of the IEEE Transactions on Computers
On the Network Power Effectiveness of Data Center Architectures
A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing
Low Complexity Bit-Parallel Multiplier for GF(2^m) Defined by All-One Polynomials Using Redundant Representation
An Algebraic Construction for q -ary Shift Register Sequences
A Post-Synthesis Optimization Technique for Reversible Circuits Exploiting Negative Control Lines
An Approach to Unsupervised Learning Classification
Magnetic Fields of Twistors Represented by Confocal Hollow Prolate Spheroids
Derivation and Calibration of a Transient Error Reliability Model
Fast Iterative Division of p -adic Numbers
VSPIM: SRAM Processing-in-Memory DNN Acceleration via Vector-Scalar Operations
Design of AC Computing Amplifiers Using Transistors
On the number of regions in input domain of a free distributive lattice
Embedding Tree Stuctures in VLlSI Hexagonal Arrays
An Unbiased MCMC FPGA-Based Accelerator in the Land of Custom Precision Arithmetic
B74-25 Operating Systems: A Pragmatic Approach
A Row Assignment for Delay-Free Realizations of Flow Tables Without Essential Hazards
A GPU-Enabled Framework for Light Field Efficient Compression and Real-Time Rendering
An Analytic Model of Printed Circuit Wiring Distributions
A Reliability Model for Various Switch Designs in Hybrid Redundancy
Near-Optimal Ordering of Electronic Circuit Equations
A Space-Efficient List Structure Tracing Algorithm
Statistical Carry Lookahead Adders
Fault Injection Experiments Using FIAT
A High-Speed Arithmetic Unit Using Tunnel Diodes
SWEL-COFAE : Wear Leveling and Adaptive Encoding Assisted Compression of Frequent Words in Non-Volatile Main Memories
DeepFire2: A Convolutional Spiking Neural Network Accelerator on FPGAs
Fault-Free: A Framework for Analysis and Mitigation of Stuck-at-Fault on Realistic ReRAM-Based DNN Accelerators
IO Workload Characterization Revisited: A Data-Mining Approach
Efficient Deadlock Avoidance for 2-D Mesh NoCs That Use OQ or VOQ Routers
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors
Power and Performance Trade-Offs in Contemporary DRAM System Designs for Multicore Processors
High-Performance Hardware Architectures for Galois Counter Mode
Hardware-Based Trusted Computing Architectures for Isolation and Attestation
A Low-Power High-Performance Concurrent Fault Detection Approach for the Composite Field S-Box and Inverse S-Box
An Algorithm for Deriving All Pairs of Compatible States by Closure Classes
Predicting the Effect of Memory Contention in Multi-Core Computers Using Analytic Performance Models
A Parallel Computing Scheme Utilizing Memristor Crossbars for Fast Corner Detection and Rotation Invariance in the ORB Algorithm
Dynamic Load Balancing in Very Large Shared-Nothing Hypercube Database Computers
Embedding Meshes and Tori on Double-Loop Networks of the Same Size
Novel Packet Size-Based Covert Channel Attacks against Anonymizer
Handling Execution Overruns in Hard Real-Time Control Systems
SADIMM: Accelerating $\underline{\text{S}}$S - parse $\underline{\text{A}}$A - ttention Using $\underline{\text{DIMM}}$DIMM - -Based Near-Memory Processing
An algebraic theory for use in digital computer design
Finite-Turn Repetitive Checking Automata and Sequential/Parallel Matrix Languages
Pipelined Adders
Enhancing In-Network Computing Deployment via Collaboration Across Planes
Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis
Approximation and Intractability Results for the Maximum Cut Problem and its Variants
Diagnosis of Intermittent Faults in Combinational Networks
Remote Transaction Commit: Centralizing Software Transactional Memory Commits
The Optimal Organization of Serial Memory Transfers
Properties of Threshold Functions
Processing by Data and Program Blocks
Cost-Performance Bounds for Multimicrocomputer Networks
Comparative Performance of Saturating and Current-Clamped High-Frequency Pulse Circuits
Comment on "Performability Analysis: A New Algorithm"
A New Look at Counters: Don't Run Like Marathon in a Hundred Meter Race
Automated Customization of On-Device Inference for Quality-of-Experience Enhancement
A General Framework of Side-Channel Atomicity for Elliptic Curve Scalar Multiplication
Low Complexity Bit-Parallel Multipliers for a Class of Finite Fields
Versatile Direct and Transpose Matrix Multiplication with Chained Operations: An Optimized Architecture Using Circulant Matrices
Remote Device Command and Resource Sharing over the Internet: A New Approach Based on a Distributed Layered Architecture
Design of Self-Checking Iterative Networks
An IEEE Compliant Floating-Point Adder that Conforms with the Pipelined Packet-Forwarding Paradigm
A Hardware Accelerator for the Fast Retrieval of DIALIGN Biological Sequence Alignments in Linear Space
Diversity Combining ARQ over the m(\geq 2)-ary Unidirectional Channel
A Cost-Effective Multistage Interconnection Network with Network Overlapping and Memory Interleaving
A Hierarchical Description Model for Microcode
Quick-and-Dirty: An Architecture for High-Performance Temporary Short Writes in MLC PCM
Fuzzy-Controlled Voltage Scaling Based on Supply Current Tracking
Complexity of Data Collection, Aggregation, and Selection for Wireless Sensor Networks
R70-12 Diagnosis of Single-Gate Failures in Combinational Circuits
The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing
Systolic Super Summation
Shared Cache for Multiple-Stream Computer Systems
Adaptive Cooperation of Prefetching and Warp Scheduling on GPUs
A Mechanized Chart for Simplification of Switching Functions
High Rate Realization of Finite-State Machines
Augmenting Loop Tiling with Data Alignment for Improved Cache Performance
The Anomalous Behavior of Flip-Flops in Synchronizer Circuits
Authors' Reply 2
A Number System with Continuous Valued Digits and Modulo Arithmetic
A High-Speed Threshold Memory Element
Parallel Algorithms to Set Up the Benes Permutation Network
Error Correction in Residue Arithmetic
Microprogrammed Control for Specialized Processors
A Window Protocol for Transmission of Time-Constrained Messages
Mitigating Observability Loss of Toggle-Based X-Masking via Scan Chain Partitioning
Pattern Recognition with Three Added Requirements
Negabinary A/D Conversion
FIFO-Based Multicast Scheduling Algorithm for Virtual Output Queued Packet Switches
Support for Software Interrupts in Log-Based Rollback-Recovery
Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm
On Delivery Guarantees and Worst-Case Forwarding Bounds of Elementary Face Routing Components in Ad Hoc and Sensor Networks
Multistep Gradual Rounding
The Organization and Use of Parallel Memories
Shared Recurrence Floating-Point Divide/Sqrt and Integer Divide/Remainder With Early Termination
Trojan Detection in Embedded Systems With FinFET Technology
Time-Component Complexity of Two Approaches to Multioperand Binary Addition
Design of a Functionally Distributed, Multiprocessor Database Machine Using Data Flow Analysis
Storage Management in Virtual Tree Machines
Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing
A Lightweight and Chip-Level Reconfigurable Architecture for Next-Generation IoT End Devices
Reliable Broadcast in Hypercube Multicomputers
Self-Repairing Computers
First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip
Interconnection Networks of Degree Three Obtained by Pruning Two-Dimensional Tori
log n P and log 3 P: Accurate Analytical Models of Point-to-Point Communication in Distributed Systems
R68-20 Effects of Scheduling on File Memory Applications
An Efficient Implementation of Boolean Functions as Self-Timed Circuits
On Compact Cauchy Matrices for Substitution-Permutation Networks
An Experimental Investigation of a Nonsupervised Adaptive Algorithm
Combinational Circuit Synthesis with Time and Component Bounds
An Energy-Aware High Performance Task Allocation Strategy in Heterogeneous Fog Computing Environments
A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival
Combinatorial Analysis of the Fault-Diameter of the n-cube
Conversion from Positive to Negative and Imaginary Radix
Session-Based Admission Control: A Mechanism for Peak Load Management of Commercial Web Sites
Sequential Permutation Networks
Analysis of Mask-Based Nanowire Decoders
Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs
CBuild: Cluster-Oriented Collaborative Image Building for Containers
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers
Comment on "Computer-Aided Design: Simulation of Digital Design Logic"
Susceptibility of Commodity Systems and Software to Memory Soft Errors
Blockchain-Based Portable Authenticated Data Transmission for Mobile Edge Computing: A Universally Composable Secure Solution
Multi-Target Adaptive Reconfigurable Acceleration for Low-Power IoT Processing
Proactive Demand Participation of Smart Buildings in Smart Grid
Detection of Single, Stuck-Type Faulures in Multivalued Combinational Networks
Avalon: A Scalable and Secure Distributed Transaction Ledger Based on Proof-of-Market
Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables
On Adding Bloom Filters to Longest Prefix Matching Algorithms
The Probability of a Correct Output from a Combinational Circuit
(t, k)-Diagnosable System: A Generalization of the PMC Models
Computer Recognition of Partial Views of Curved Objects
Electron Beam Recording of Digital Information
Schmoo Plot Analysis of Coincident-Current Memory Systems
Generation of Internal State Assignments for Large Asynchronous Sequential Machines
New Matrix Inversion Algorithms Based on Exchange Method
Co-Design of Approximate Multilayer Perceptron for Ultra-Resource Constrained Printed Circuits
Dynamic Cluster Reconfiguration for Energy Conservation in Computation Intensive Service
An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays
An Inherently Stabilizing Algorithm for Node-To-Node Routing over All Shortest Node-Disjoint Paths in Hypercube Networks
Fast Vectorization for Calculating a Moving Sum
Rate-Monotonic Scheduling on Uniform Multiprocessors
Tolerating Faults in Hypercubes Using Subcube Partitioning
Towards Reconstructing Routing Paths in Large Scale Sensor Networks
Computer Optimization of Recognition Networks
Computation Times of Arithmetic and Boolean Functions in (d, r) Circuits
Computer Multiplication and Division Using Binary Logarithms
Improving Disk Cache Hit-Ratios Through Cache Partitioning
ConformalALU: A Conformal Geometric Algebra Coprocessor for Medical Image Processing
Reducing the Diameters of Computer Networks
Computational Complexity Issues in Operative Diagnosis of Graph-Based Systems
R70-45 On Decompositions of Regular Events
Structure Specification with a Procedural Hardware Description Language
Note on a Class of Statistical Recognition Functions
Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache
Pipeline Iterative Arithmetic Arrays
Efficient Resource Constrained Scheduling Using Parallel Structure-Aware Pruning Techniques
A Combinatoric Division Algorithm for Fixed-Integer Divisors
TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches
Mini-Rank: A Power-EfficientDDRx DRAM Memory Architecture
Improving Log-Based Anomaly Detection by Pre-Training Hierarchical Transformers
Design of High-Speed Digital Divider Units
RDIS: Tolerating Many Stuck-At Faults in Resistive Memory
Performance Tradeoffs in Rings of Data-Driven Elements
Process Performance Computer for Adaptive Control Systems
Sparse Learning-to-Rank via an Efficient Primal-Dual Algorithm
Fast Sorting Algorithms on Uniform Ladders (Multiple Shift-Register Loops)
B70-4 Theory of Scheduling
The Relationship Between Multivalued Switching Algebra and Boolean Algebra Under Different Definitions of Complement
High-Speed Microprogrammable Asynchronous Controller Modules
A Data Flow Multiprocessor
Diagnosis of Multiple Hold-Time and Setup-Time Faults in Scan Chains
A New Technique for Analog Integration and Differentiation
An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories
Inverse Queuing Model-Based Feedback Control for Elastic Container Provisioning of Web Systems in Kubernetes
A Proof of the Modified Booth's Algorithm for Multiplication
Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications
On Serial-Input Multipliers for Two's Complement Numbers
The Impulse Memory Controller
The Minimum Distance Diagram of Double-Loop Networks
Logical Design Using Shift Registers
Efficient, Decentralized Computation of the Topology of Spatial Regions
Class Library Support for Workflow Environments and Applications
Test Generation for Microprocessors
ML-PTA: A Two-Stage ML-Enhanced Framework for Accelerating Nonlinear DC Circuit Simulation With Pseudo-Transient Analysis
Minimal Detecting Transition Sequences: Application to Random Testing
A Graph-Theoretic Approach to Nonparametric Cluster Analysis
Unified Matrix Treatment of the Fast Walsh-Hadamard Transform
Exploiting Small World Properties for Message Forwarding in Delay Tolerant Networks
Computer-Aided Design: Simulation of Digital Design Logic
On Performance Analysis of Retrieval Functions
Finite State Model and Compatibility Theory: New Analysis Tools for Permutation Networks
A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits
Exact Fault-Sensitive Feasibility Analysis of Real-Time Tasks
Composite Spectra and the Analysis of Switching Circuits
An Efficient and Secure Data Sharing Scheme for Edge-Enabled IoT
Pattern Recognition by Using an Associative Memory
Statistical Reliability Estimation of Microprocessor-Based Systems
Adaptive Cloud Bundle Provisioning and Multi-Workflow Scheduling via Coalition Reinforcement Learning
Efficient Reclaiming in Reservation-Based Real-Time Systems with Variable Execution Times
An Adaptive Thermal Management Framework for Heterogeneous Multi-Core Processors
Recovering from Multiple Process Failures in the Time Warp Mechanism
Performance of a Simulated Dataflow Computer
R70-35 Classes of Automata and Transitive Closure
On Fourier Transforms Over Extensions of Finite Rings
Relay Node Placement in Wireless Sensor Networks
Automatic Synthesis of Self-Recovering VLSI Systems
LACS: A Locality-Aware Cost-Sensitive Cache Replacement Algorithm
Boolean Differential Calculus and its Application to Switching Theory
Certifying the Floating-Point Implementation of an Elementary Function Using Gappa
Systolic Sorting on a Mesh-Connected Network
Spectral Features of Higher-Order Side-Channel Countermeasures
Comments on 'Novel Totally Self-Checking Berger Checker Designs Based on Generalized Berger Code Partitioning'
Fault Location in a Semiconductor Random-Access Memory Unit
Leveraging Social Networks for Effective Spam Filtering
Applying Delta Compression to Packed Datasets for Efficient Data Reduction
A Thin-Film Rod Memory for the NCR 315 RMC Computer
Synchronization-Aware Energy Management for VFI-Based Multicore Real-Time Systems
Message-Based Response Routing with Selcuk Networks
An Algorithm for the Genaration of Test Sets for Conmbinational Logic Networks
Sequential Circuit Design for Embedded Cryptographic Applications Resilient to Adversarial Faults
AI Trojan Attack for Evading Machine Learning-Based Detection of Hardware Trojans
Systematic Unidirectional Error-Detecting Codes
TeraPool: A Physical Design Aware, 1024 RISC-V Cores Shared-L1-Memory Scaled-Up Cluster Design With High Bandwidth Main Memory Link
A Scheme for Synchronizing High-Speed Logic: Part I
Correlation of Adjacent Pixels for Multiple Image Registration
The Cost of Broadcasting on Star Graphs and k-Ary Hypercubes
Push-Based Information Delivery in Two Stage Satellite-Terrestrial Wireless Systems
R 68-44 Mathematical Logic