yusuke1997/dblp-id-title huggingface dataset:
Fast Combinatorial RNS Processors for DSP Applications
Toward Advocacy-Free Evaluation of Packet Classification Algorithms
CoFormer: Collaborating With Heterogeneous Edge Devices for Scalable Transformer Inference
A Multipurpose Electronic Switch for Analog Computer Simulation and Autocorrelation Applications
Dynamic Boolean Algebras
Architecting against Software Cache-Based Side-Channel Attacks
Cross-Channel: Scalable Off-Chain Channels Supporting Fair and Atomic Cross-Chain Operations
Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support
B74-2 Man and the Computer
Subcube Allocation and Task Migration in Hypercube Multiprocessors
Real-Time Data Semantics and Similarity-Based Concurrency Control
Optimal Parallel and Pipelined Processing Through a New Class of Matrices with Application to Generalized Spectral Analysis
Guest Editors' Introduction to Special Section on Asynchronous Real-Time Distributed Systems
Rare Computing: Removing Redundant Multiplications From Sparse and Repetitive Data in Deep Neural Networks
An Efficient Implementation of Batcher's Odd-Even Merge Algorithm and Its Application in Parallel Sorting Schemes
Task Allocation Algorithms for Maximizing Reliability of Distributed Computing Systems
Fault-Tolerant Array Processors Using Single-Track Switches
A Kleene Algebra of Tagged System Actors for Reasoning about Heterogeneous Embedded Systems
Design of Diagnosable Sequential Machines Utilizing Extra Outputs
Trace Scheduling: A Technique for Global Microcode Compaction
A Performability Solution Method for Degradable Nonrepairable Systems
A Design Procedure for Fault-Locatable Switching Circuits
AT²-Optimal Galois Field Multiplier for VLSI
An Iterative Analog Computer Using Pulse-Ratio Modulation
Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics
HyVE: Hybrid Vertex-Edge Memory Hierarchy for Energy-Efficient Graph Processing
MViD: Sparse Matrix-Vector Multiplication in Mobile DRAM for Accelerating Recurrent Neural Networks
B 74-28 Computer Hardware and Software: An Interdisciplinary Introduction
On the Number of Types of Self-Dual Logical Functions
Comments on "Reliable Loop Topologies for Large Local Computer Networks"
A Destructive-Readout Associative Memory
Design of a Multiple-Valued Systolic System for the Computation of the Chrestenson Spectrum
SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip
Energy Scalable Universal Hashing
TensorMap: A Deep RL-Based Tensor Mapping Framework for Spatial Accelerators
Optimal Tower Fields
Polylinear Decomposition of Synchronous Sequential Machines
On-Line Computer Recognition of Handprinted Characters
A Stabilizing Deactivation/Reactivation Protocol
Complete Binary Spanning Trees of the Eight Nearest Neighbor Array
On Complementation of Boolean Functions
Processing Data in Bits and Pieces
Computer Aided Memory Design Using Transmission Line Models
CINTEL - Computer Interface for Television
Topology Control of Ad Hoc Wireless Networks for Energy Efficiency
Cross-Platform Resource Scheduling for Spark and MapReduce on YARN
Effective Huge Page Strategies for TLB Miss Reduction in Nested Virtualization
Set Membership Classification: A Unified Approach to Geometric Intersection Problems
Translation of the Problem of Complete Test Set Generation to Pseudo-Boolean Programming
B 74-39 A Course in APL/360 with Applications
SafeDRL: Dynamic Microservice Provisioning With Reliability and Latency Guarantees in Edge Environments
SimBU: Self-Similarity-Based Hybrid Binary-Unary Computing for Nonlinear Functions
Code Transformations for Energy-Efficient Device Management
System Design of a FORTRAN Machine
3D Many-Core Microprocessor Power Management by Space-Time Multiplexing Based Demand-Supply Matching
A Search of Minimal Key Functions for Normal Basis Multipliers
A Black-White Representation of a Gray-Scale Picture
Enabling Highly Efficient Capsule Networks Processing Through Software-Hardware Co-Design
Leveraging GPU in Homomorphic Encryption: Framework Design and Analysis of BFV Variants
Simple Relationships Among Moments of Queue Lengths in Product Form Queueing Networks
(Adversarial) Electromagnetic Disturbance in the Industry
Algorithms for Scheduling Imprecise Computations with Timing Constraints to Minimize Maximum Error
An Analytic Response Time Model For Single-and Dual-Density Disk Systems
Codes for Error Correction in High-Speed Memory Systems - Part I: Correction of Cell Defects in Integrated Memories
Near Embeddings of Hypercubes into Cayley Graphs on the Symmetric Group
Disproving the Perfect-Rate Property of Data-Flow Graphs Unfolded by the Least Common Multiple of the Number of Loop Registers
Endurance-Aware Security Enhancement in Non-Volatile Memories Using Compression and Selective Encryption
Preserving Temporal Relationships of Events for Wireless Sensor Actor Networks
Design of Totally Self-Checking Circuits with an Unrestricted Stuck-At Fault-Set Using Redundancy in Space and Time Domains
Distributed Call Admission Control for a Heterogeneous PCS Network
Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support
Generation of Polynomial Discriminant Functions for Pattern Recognition
Efficient Uses of FPGAs for Implementations of DES and Its Experimental Linear Cryptanalysis
Reliable Multicast in Data Center Networks
Code Constructions for Error Control in Byte Organized Memory Systems
An Efficient Method for Calculating the Error Statistics of Block-Based Approximate Adders
Finite Field Multiplier Using Redundant Representation
A Chinese Remainder Theorem Approach to Bit-Parallel GF(2 n ) Polynomial Basis Multipliers for Irreducible Trinomials
A Module-Level Testing Approach for Combinational Networks
A Basis for the Quantitative Comparison of Computer Number Systems
An Interactive Computer Approach to Tolerance Analysis
Scheduling Concurrent Bag-of-Tasks Applications on Heterogeneous Platforms
An Analog Computer Simulation of the Restricted Three-Body Problem by Automatic Scale-Changing Techniques
Analysis of Dual-Link Networks for Real-Time Applications
Optimized Custom Precision Function Evaluation for Embedded Processors
Fault Diagnosis in Combinational Tree Networks
High-Performance Mixed-Precision Linear Solver for FPGAs
Compressed Signal Processing on Nyquist-Sampled Signals
Analysis of the Terminal Behavior of Some Classes of Iterative Arrays of Linear Machines
B70-5 Theories of Abstract Automata
A Fault-Tolerant Modular Architecture for Binary Trees
On the Design of Iterative Approximate Floating-Point Multipliers
A Comment on "An Analytical Model for Designing Memory Hierarchies"
A Symmetric Load Balancing Algorithm with Performance Guarantees for Distributed Hash Tables
A Branch and Bound Algorithm for Feature Subset Selection
ULM Implicants for Minimization of Universal Logic Module Circuits
Hierarchical Orchestration of Disaggregated Memory
High-Speed Parallel-Prefix VLSI Ling Adders
Hierarchical Strategies for Efficient Fault Recovery on the Reconfigurable PAnDA Device
TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAM's
Early Analysis of Fault-based Attack Effects in Secure Circuits
Detection of SLA Violation for Big Data Analytics Applications in Cloud
Boolean Matrices and the Stability of Neural Nets
An Improved Logarithmic Multiplier for Energy-Efficient Neural Computing
A Model-Based Vision System for Industrial Parts
Experiences, Strategies, and Challenges in Building Fault-Tolerant CORBA Systems
Message-Efficient Location Prediction for Mobile Objects in Wireless Sensor Networks Using a Maximum Likelihood Technique
A Cellular Array for Binary to BCD Conversion
Throughput and Time Delay Analysis for a Common Queue Configuration in a Multiprocessor Environment
Multiplying D/A Converter
Design and Analysis of Hybrid Flow Control for Hierarchical Ring Network-on-Chip
A Complexity-Effective Local Delta Prefetcher
Three-Valued Propositional Calculus of Lukasiewicz and Three-Position Double Switches
Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages
Microcontroller TRNGs Using Perturbed States of NOR Flash Memory Cells
A Variable-Lengt Shift-Register
Destage Algorithms for Disk Arrays with Nonvolatile Caches
Comments on "An Optimal Solution for the Channel-Assignment Problem"
Adaptive Power Shifting for Power-Constrained Heterogeneous Systems
A Deterministic Model for Evaluating the Performance of a Multiple Processor with a Shared Bus
A Generalized Theory for System Level Diagnosis
Privacy Preserving Ranked Multi-Keyword Search for Multiple Data Owners in Cloud Computing
On the Design of Minimum Length Fault Tests for Combinational Circuits
A Geometric Approach to Maximum-Speed n-Dimensional Continuous Linear Interpolation in Rectangular Grids
Algorithms for Inversion Mod ps k
Optimum Digit Serial GF(2^m) Multipliers for Curve-Based Cryptography
High-Radix Multiplier-Dividers: Theory, Design, and Hardware
VLSI Algorithms, Architectures, and Implementation of a Versatile GF(2 m ) Processor
Fuzzy Memoization for Floating-Point Multimedia Applications
OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems
Broadcast Ring Sandwich Networks
A Model of SIMD Machines and a Comparison of Various Interconnection Networks
Asynchronous Arbiters
High Density Digital Magnetic Recording Techniques
A Linear Time Pessimistic Diagnosis Algorithm for Hypermesh Multiprocessor Systems under the PMC Model
To SAT or Not to SAT: Scalable Exploration of Functional Dependency
ROC-1: Hardware Support for Recovery-Oriented Computing
Detection of Single Intermittent Faults in Sequential Circuits
Instruction Profiling Based Predictive Throttling for Power and Performance
Reduction of Connections for Multibus Organization
Generating and Counting the Double Adjacencies in a Pure Circulating Shift Register
A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2^m)
DNA: A General Dynamic Neural Network Accelerator
Concurrent VLSI Architectures
Optimal Placements of Flexible Objects: Part II: A Simulated Annealing Approach for the Bounded Case
Closed-Form Solutions of Performability
LFOC+: A Fair OS-Level Cache-Clustering Policy for Commodity Multicore Systems
HPC: A Model of Structure and Change in Distributed Systems
Synthesis of Multiple-Input Change Asynchronous Circuits Using Transition-Sensitive Flip-Flops
The Types and Interactions of Vertical Migrations of Functions in a Multilevel Interpretive System
Universal Data Compression Based on the Burrows-Wheeler Transformation: Theory and Practice
A Method of Using Cluster Analysis to Study Statistical Dependence in Multivariate Data
CPC (Cyclic Pipeline Computer) - An Architecture Suited for Josephson and Pipelined-Memory Machines
An Efficient Preprocessing-Based Approach to Mitigate Advanced Adversarial Attacks
Joint Virtual Network Function Placement and Flow Routing in Edge-Cloud Continuum
Multiplex Logic Circuits
Information Sharing in Multi-Tenant Metaverse via Intent-Driven Multicasting
Verifying and Comparing Finite State Machines for Systems that Have Distributed Interfaces
Procedures for Eliminating Static and Dynamic Hazards in Test Generation
A Mechanism Design Approach to Resource Procurement in Cloud Computing
Power-Efficient Pipelined Reconfigurable Fixed-Width Baugh-Wooley Multipliers
On the Definition and Generation of Walsh Functions
Tangram: Enabling Efficient and Balanced Dynamic Storage Extension on Sharding Blockchain Systems
Energy-Efficient Resource Utilization for Heterogeneous Embedded Computing Systems
On Minimization of Fuzzy Functions
Synthesis of an Optimal Family of Matrix Multiplication Algorithms on Linear Arrays
Toward Correctly Rounded Transcendentals
On the Effects of Transaction Data Access Patterns on Performance in Lock-Based Concurrency Control
An organization for checking experiments on sequential circuits
Synchronizing Hypercube Networks in the Presence of Faults
Vector-Indistinguishability: Location Dependency Based Privacy Protection for Successive Location Data
Malware Analysis by Combining Multiple Detectors and Observation Windows
On Table Bandwidth and Its Update Delay for Value Prediction on Wide-Issue ILP Processors
The Modeling and Design of Multiple Function-Unit Processors
Disk Scheduling onMultimedia Storage Servers
Pattern Classifier Design by Linear Programming
Direct Coherent Optical Fourier Transform of Curves
Adaptive Voltage Scaling with In-Situ Detectors in Commercial FPGAs
A Systematic Methodology for the Design of High Performance Recursive Digital Filters
A Node-Elimination Theorem for Boolean Matrices
A Scheduling-Function-Based Distributed Access Protocol that Uses CDM to Relay Control Information in a Network with Hidden Nodes
Component Dependencies Based Network-on-Chip Test
Embedding Binary Trees into Crossed Cubes
Comments on "Analog Computer Simulation of a Frequency Detector
Experimental Study of a New Method of Time Delay for Analog Computers
Power and Area-Efficient Unified Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems
Cellular Synthesis of Synchronous Sequential Machines
A Two-Rail Cascade Synthesis of Boolean Functions
Implementation and Evaluation of Raptor Codes on Embedded Systems
A Class of (12, 8) Codes for Correcting Single Errors and Detecting Double Errors within a Nibble
Computer Processing of Radiation Sensor PCM Data
Some Aspects of the Zoom Transform
An Augmented Iterative Array for High-Speed Binary Division
Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures
Binary Logic for Residue Arithmetic Using Magnitude Index
A Switch-Level Model and Simulator for MOS Digital Systems
Asynchronous Disk Interleaving: Approximating Access Delays
Optimal Prioritized Conflict Resolution on a Multiple Access Channel
B 74-31 Signals, Systems, and the Computer
CC Meets FIPS: A Hybrid Test Methodology for First Order Side Channel Analysis
Direct Implementation of Asynchronous Control Units
FlinkCL: An OpenCL-Based In-Memory Computing Architecture on Heterogeneous CPU-GPU Clusters for Big Data
Analytic Modeling and Comparisons of Striping Strategies for Replicated Disk Arrays
Pseudo-Random Number Generator Based on Binary and Quinary Maximal-Length Sequences
Improving the Variable Ordering of OBDDs Is NP-Complete
Input Variable Assignment and Output Phase Optimization of PLA's
Curvature and Creases: A Primer on Paper
Analysis of Algorithms for the Evaluation of Monotonic Boolean Functions
An Algorithm for the Disjunctive Decomposition of Switching Functions
Evaluating Elastic Buffer and Wormhole Flow Control
Uniform Parity Group Distribution in Disk Arrays with Multiple Failures
A Nearly Optimal Packet Scheduling Algorithm for Input Queued Switches with Deadline Guarantees
Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache
HDLC Throughput and Response Time for Bidirectional Data Flow with Nonuniform Frame Sizes
Energy Optimal Task Scheduling with Normally-Off Local Memory and Sleep-Aware Shared Memory with Access Conflict
Being Stingy with Multipliers
$\mathcal{O}(n)$O(n) Key-Value Sort With Active Compute Memory
Timing Issues in the Distributed Execution of Ada Programs
A Cost-Effective Pipelined Divider with a Small Lookup Table
E-MACs: Toward More Secure and More Efficient Constructions of Secure Channels
Multiplication Using Logarithms Implemented with Read-Only Memory
On the Number of Distinct State Assignments for Synchronous Sequential Machines
Testing Open Defects in Memristor-Based Memories
Hotness- and Lifetime-Aware Data Placement and Migration for High-Performance Deep Learning on Heterogeneous Memory Systems
Redundancy Mining for Soft Error Detection in Multicore Processors
Two Efficient Algorithms for Linear Time Suffix Array Construction
The Maximum Factor Queue Length Batching Scheme for Video-on-Demand Systems
The Cubical Ring Connected Cycles: A Fault-Tolerant Parallel Computation Network
Multiple-Valued Logic: An Introduction and Overview
NAND-AND Circuits
Minimal Sequential Machines
Software Implementation of an Attribute-Based Encryption Scheme
On the Design of Universal Boolean Functions
Ternary Threshold Logic
GraNDe: Efficient Near-Data Processing Architecture for Graph Neural Networks
Pfair Scheduling of Generalized Pinwheel Task Systems
Feature Extraction in an Optical Character Recognition Machine
Robot Coordination for Energy-Balanced Matching and Sequence Dispatch of Robots to Events
Existence Algorithms for Synchronizing/Distinguishing Sequences
Efficient Parallel Evaluation of Boolean Expression
Availability of CAUTRA, a Subset of the French Air Traffic Control System
A Reconfigurable Tree Architecture with Multistage Interconnection Network
Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array
PASM: A Partitionable SIMD/MIMD System for Image Processing and Pattern Recognition
An Application-Oriented Programming Language for Sequential Machine Studies
Local Concurrent Error Detection and Dorrection in Data Structures Using Virtual Backpointers
Grid Coverage for Surveillance and Target Location in Distributed Sensor Networks
PaRTAA: A Real-Time Multiprocessor for Mixed-Criticality Airborne Systems
Improvement of Electronic-Computer Reliability through the Use of Redundancy
Toward Comprehensive Shifting Fault Tolerance for Domain-Wall Memories With PIETT
Multi-Layer Diagnosis for Fault-Tolerant Networks-on-Chip
CABE: A New Comparable Attribute-Based Encryption Construction with 0-Encoding and 1-Encoding
Fast Static Compaction Algorithms for Sequential Circuit Test Vectors
Interpolator for a Computer Numerical Control System
A Fast Fourier Transform for High-Speed Signal Processing
Single Residue Error Correction Based on K-Term m_j-Projection
Minimization of Memory and Network Contention for Accessing Arbitrary Data Patterns in SIMD Systems
DaDianNao: A Neural Network Supercomputer
On the Bound to the Memory of a Sequential Machine
Comment on "Delay-Free Asynchronous Circuits with Constrained Line Delays"
The Design of Shift Register Generators for Finite Sequences
An Analysis of the Use of Rademacher-Walsh Spectrum in Compact Testing
Fault-Tolerant 256K Memory Designs
Distribution-Free Pattern Verification Using Statistically Equivalent Blocks
Sensitivity-Based Optimization of Disk Architecture
Detection of Multiple Faults in Two-Dimensional ILAs
A Quality Factor for Measuring Program Efficiency
Unbiased Rounding for HUB Floating-Point Addition
On-Set Realization of Fail-Safe Sequential Machines
Architecture of an Array Processor Using a Nonlinear Skewing Scheme
Optimum Choice of Noise Frequency Band and Sampling Rate for Generating Random Binary Digits from Clipped White Noise
Automatic Assignment of Computations in a Variable Structure Computer System
Bulk Processing in Distributed Logic Memory
Parallel GPU Architecture Simulation Framework Exploiting Architectural-Level Parallelism with Timing Error Prediction
BaPa: A Novel Approach of Improving Load Balance in Parallel Matrix Factorization for Recommender Systems
A Note on Tributary Switching Networks
Multivariate Rational Approximants for Multiclass Closed Queuing Networks
Good Controllability and Observability Do Not Guarantee Good Testability
vTrust: Remotely Executing Mobile Apps Transparently With Local Untrusted OS
A Note on "New Strategies for Assigning Real-Time Tasks to Multiprocessor Systems"
A Parallel Mechanism for Describing Silhouettes
Logical Design Using the Stroke Function
Read-Ahead Efficiency on Mobile Devices: Observation, Characterization, and Optimization
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
FITS: A Finite-Time Reputation System for Cooperation in Wireless Ad Hoc Networks
A Tabular Method for Guard Strengthening, Symmetrization, and Operator Reduction for Martin's Asynchronous Design Methodology
On the Periodic Equivalents of Finite Automata
Dynamic Fault-Tolerant Routing Based on FSA for LEO Satellite Networks
Structures of the Affine Families of Switching Functions
Test Generation for Multiple State-Table Faults in Finite-State Machines
Rank-Aware Dynamic Migrations and Adaptive Demotions for DRAM Power Management
MOVE Architecture in Digital Controllers
The Broadcast Comparison Model for On-Line Fault Diagnosis in Multicomputer Systems
Dynamically Selecting Optimal Distribution Strategies for Web Documents
PBC: Prefetched Blocks Compaction
A New Simulation-Based Property Checking Algorithm Based on Partitioned Alternative Search Space Traversal
Automatic Generation of Analog/Mixed Signal Virtual Platforms for Smart Systems
ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation
Resolution of Deadlocks in Object-Oriented Distributed Systems
Unified Matrix Treatment of Discrete Transforms
Tessellation Aspect of Combinational Cellular Array Testing
A Modified Training Procedure for Linear Threshold Devices
MEMORY-Based Hardware Architectures to Detect ClamAV Virus Signatures with Restricted Regular Expression Features
The Metric Relationship Between Extra Connectivity and Extra Diagnosability of Multiprocessor Systems
JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits
Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m)
Serial Hybrid Computation and Errors in Hybrid Loops
High-Speed Architectures for Multiplication Using Reordered Normal Basis
On the Complexity of Estimating the Size of a Test Set
Decision Problems of Phrase-Structure Grammars
Nondeterministic Multithreading
Fault-Tolerant Newton-Raphson and Goldschmidt Dividers Using Time Shared TMR
Diagnosis and Repair in Multiprocessor Systems
Efficient Quantum Secure Vector Dominance and Its Applications in Computational Geometry
Processes for Random and Sequential Accessing in Dynamic Memories
Achieving NTRU with Montgomery Multiplication
Hybrid Computer Methods for Direct Functional Optimization
On the Permutation Capability of Multistage Interconnection Networks
Introducting the New Editor-in-Chief of the IEEE Transactions on Computers
Negation Trees: A Unified Approach to Boolean Function Complementation
Design for a Tunnel Diode-Transistor Store with Nondestructive Read-Out of Information
A Variational Calculus Approach to Optimal Checkpoint Placement
Design of Space-Optimal Regular Arrays for Algorithms with Linear Schedules
An Energy-Efficient Last-Level Cache Architecture for Process Variation-Tolerant 3D Microprocessors
Tunnel Diode Digital Circuitry
Solving Stochastic Nonlinear Resource Allocation Problems Using a Hierarchy of Twofold Resource Allocation Automata
On Iterative Arrays for the Euclidean Algorithm over Finite Fields
A Functional Form Approach to Test Set Coverage in Tree Networks
Revocable Blockchain-Aided Attribute-Based Encryption With Escrow-Free in Cloud Storage
Timing extraction at high bit densities
Testing Memories for Single-Cell Pattern-Sensitive Faults
A Geometric Transversals Approach to Analyzing the Probability of Track Detection for Maneuvering Targets
The Structure of Periodic Storage Schemes for Parallel Memories
Nonprime Memory Systems and Error Correction in Address Translation
Analysis of Temporal-Based Program Behavior for Improved Instruction Cache Performance
Comments on "Direct Coherent Optical Fourier Transforms of Curves"
Charge-Recovery Computing on Silicon
Operation-Saving VLSI Architectures for 3D Geometrical Transformations
An Example Computer Logic Graph and Its Partitions and Mappings
Dynamic Bin Packing With Heterogeneous Dependent Bins for Regionless in Geo-Distributed Clouds
L4L: Experience-Driven Computational Resource Control in Federated Learning
Salvaging Test Windows in BIST Diagnostics
RUPA: A High Performance, Energy Efficient Accelerator for Rule-Based Password Generation in Heterogenous Password Recovery System
BR-Tree: A Scalable Prototype for Supporting Multiple Queries of Multidimensional Data
Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis