yusuke1997/dblp-id-title huggingface dataset:
Response-Hiding and Volume-Hiding Verifiable Searchable Encryption With Conjunctive Keyword Search
Array Organization and Data Management Exploration in Racetrack Memory
Regional ACO-Based Cascaded Adaptive Routing for Traffic Balancing in Mesh-Based Network-on-Chip Systems
An On-Line Algorithm for Checkpoint Placement
High Speed Externally Asynchronous/Internally Clocked Systems
A Direct Approach to the Parallel Evaluation of Rational Expressions with a Small Number of Processors
SPAC: A Synergistic Prefetcher Aggressiveness Controller for Multi-Core Systems
Requester-Based Spin Lock: A Scalable and Energy Efficient Locking Scheme on Multicore Systems
Speaker Verification via High-Level Feature Based Phonetic-Class Pronunciation Modeling
Comments on "Theory and Applications of Cellular Automata in Cryptography"
Comments on "A Computer Algorithm for Transposing Nonsquare Matrices"
A Time-Division Multiplier
Cost-Aware Cooperative Resource Provisioning for Heterogeneous Workloads in Data Centers
Routing Bandwidth-Guaranteed Paths in MPLS Traffic Engineering: A Multiple Race Track Learning Approach
Constructing Completely Independent Spanning Trees in a Family of Line-Graph-Based Data Center Networks
Simple Instructions Which Enhance the Error Control Capabilities of a Programmed Communications Processor
Phase-Shift Analysis of Linear Feedback Shift Register Structures Generating Pseudorandom Sequences
Structured Storage AFA
HAM: Hotspot-Aware Manager for Improving Communications With 3D-Stacked Memory
A VLSI DEsign for Computing Exponentiations in GF(2^m) and Its Application to Generate Pseudorandom Number Sequences
Analog-Computer Technique for Impulsive Atmospheric Radio-Noise Analysis
A Hierarchical Computer Architecture for Distributed Simulation
Optimal Metastability-Containing Sorting via Parallel Prefix Computation
DataFly: A Confidentiality-Preserving Data Migration Across Heterogeneous Blockchains
Lightweight, Effective Detection and Characterization of Mobile Malware Families
An Improved Rate-Monotonic Admission Control and Its Applications
Distributed Sorting on Local Area Networks
Enabling Efficient Fast Convolution Algorithms on GPUs via MegaKernels
Sifter: An Efficient Operator Auto-Tuner With Speculative Design Space Exploration for Deep Learning Compiler
Test Sets for Combinational Logic - The Edge-Tracing Approach
Test Bus Sizing for System-on-a-Chip
Fault Analysis-Based Logic Encryption
Convolutionally Encoded Memory Protection
SAFLA: Scheduling Multiple Real-Time Periodic Task Graphs on Heterogeneous Systems
Comments on "Ternary Scan Design for VLSI Testability"
Limitations on Carry Lookahead Networks
Hardware/Software Co-Design of Memory Page Translation for Mobile Virtualization
Design and Evaluation of a Parallel Invocation Protocol for Transactional Applications over the Web
Overview of the SpiNNaker System Architecture
ID2S Password-Authenticated Key Exchange Protocols
Hierarchical Hashing: A Dynamic Hashing Method With Low Write Amplification and High Performance for Non-Volatile Memory
A Utility Accrual Scheduling Algorithm for Real-Time Activities with Mutual Exclusion Resource Constraints
TetriX: Flexible Architecture and Optimal Mapping for Tensorized Neural Network Processing
Dynamic Establishment and Termination of Real-Time Message Streams in Dual-Bus Networks
Availability Analysis of Repairable Computer Systems and Stationarity Detection
SAFA: Handling Sparse and Scarce Data in Federated Learning With Accumulative Learning
PRECIOUS: Approximate Real-Time Computing in MLC-MRAM Based Heterogeneous CMPs
A New Class of Digital Division Methods
An Improvement on Constructions of t-EC/AUED Codes
Replicated Process Allocation for Load Distribution in Fault-Tolerant Multicomputers
Shuffling with the Illiac and PM21 SIMD Networks
A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes
Autonomous Clocks in Sequential Machines
Online Scheduling of Distributed Machine Learning Jobs for Incentivizing Sharing in Multi-Tenant Systems
A Note on Detecting Sneak Paths in Transistor Networks
Vector Instruction Set Extensions for Efficient Computation of Keccak
DORY: Automatic End-to-End Deployment of Real-World DNNs on Low-Cost IoT MCUs
Minimal Feedback Realizations of Sequential Machines
Bisectionla Fault-Tolerant Communication Archtecture for Supercomputer Systems
Blockchain-Cloud Transparent Data Marketing: Consortium Management and Fairness
On Optimization of E-Textile Systems Using Redundancy and Energy-Aware Routing
The Expected (Not Worst-Case) Throughput of the Ethernet Protocol
Towards the Integration of Reverse Converters into the RNS Channels
An FPGA Based Accelerator for Clustering Algorithms With Custom Instructions
Deterministic BIST for RNS Adders
Building and Checking Suffix Array Simultaneously by Induced Sorting Method
Comments on "A Measure of Computational Work" and "Logical Network Cost and Entropy"
Unit-Distance Binary-Decimal Codes for Two-Track Commutation
Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs
Modeling Cache Contention and Throughput of Multiprogrammed Manycore Processors
A Slimplified Architecture for Modulo (2 n + 1) Multiplication
Computing Affine Equivalence Classes of Boolean Functions by Group Isomorphism
Immunet: Dependable Routing for Interconnection Networks with Arbitrary Topology
PRESENCE: A Human-Inspired Architecture for Speech-Based Human-Machine Interaction
On Task Mapping in Multi-chiplet Based Many-Core Systems to Optimize Inter- and Intra-chiplet Communications
Fast Arithmetical Algorithms in Möbius Number Systems
Solenoid-Coupled READ-ONLY Memory
Secure Tensor Decomposition for Big Data Using Transparent Computing Paradigm
A Counterexample to Tang and Padubidri's Claim about the Bisection Width of a Diagonal Mesh
A New Associative Memory System Utilizing Holography
Pipelining of Arithmetic Functions
Energy Aware Computing through Probabilistic Switching: A Study of Limits
Computer Benchmark Evaluation and Design of Experiments, a Case Study
Distributed Learning for Large-Scale Models at Edge With Privacy Protection
A Digital Computer for Use in an Operational Flight Trainer
Combinational Logic Design with Decoders
Caches and Predictors for Real-Time, Unobtrusive, and Cost-Effective Program Tracing in Embedded Systems
Design Considerations for a Parallel Bit-Organized MOS Memory
A Fast VLSI-Efficient Self-Routing Permutation Network
On the Construction of Projectors Using Products of Elementary Matrices
Eliminating the Normalization Problem in Digit On-Line Arithmetic
Inverter-Minimum Networks
Comment on "Nonobservable or noncontrollable analog schemes for the solution of a special class of differential equations"
On Redundancy and Fault Detection in Sequential Circuits
On a Constant-Time, Low-Complexity Winner-Take-All Neural Network
B70-2 Transmission of Information by Orthogonal Functions
A Combinatorial Limit to the Computing Power of VLSI Circuits
Optimally Removing Intercore Communication Overhead for Streaming Applications on MPSoCs
Booting Time Minimization for Real-Time Embedded Systems with Non-Volatile Memory
Sign/Logarithm Arithmetic for FFT Implementation
ElasticDNN: On-Device Neural Network Remodeling for Adapting Evolving Vision Domains at Edge
An Architecture for Tolerating Processor Failures in Shared Memory Multiprocessors
DCS3: A Dual-Layer Co-Aware Scheduler With Stealing Balance and Synchronized Priority in Virtualization Environments
Preventing Coherence State Side Channel Leaks Using TimeCache
Analysis and Optimal Design of Self-Diagnosable Systems with Repair
New Algorithms for the Approximate Evaluation in Hardware of Binary Logarithms and Elementary Functions
DMRlib: Easy-Coding and Efficient Resource Management for Job Malleability
Coverage Estimation Using Statistics of the Extremes for When Testing Reveals No Failures
A Kernel for High-Performance Multicast Communications
R68-27 Programming Languages for Automata
An Improved Algorithm for Deriving Checking Experiments
REBUS, A Fault-Tolerant Distributed System for Industrial Real-Time Control
Coverage Estimation Methods for Stratified Fault Injection
Optimization of Microprograms
A Character Recognition Application of an Iterative Procedure for Feature Selection
Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration
Fault Injection and Dependability Evaluation of Fault-Tolerant Systems
External Sorting in VLSI
Decomposition of Permutation Networks
Predicate Detection in Asynchronous Pervasive Environments
New Low-Area Designs for the AES Forward, Inverse and Combined S-Boxes
Using Branch Predictors and Variable Encoding for On-the-Fly Program Tracing
An Accurate Analog Multiplier and Divider
Channel-Hopping Scheme and Channel-Diverse Routing in Static Multi-Radio Multi-Hop Wireless Networks
A New Design Method for m -Out-of- n TSC Checkers
MLCD: Machine Learning-Based Code Version and Device Selection for Heterogeneous Systems
Nonblocking Broadcast Switching Networks
Reflections on the Pentium Bug
On Multivalued Multithreshold Networks Composed of Conventional Threshold Elements
On the Performance of Magnetic Bubble Memories in Computer Systems
Numerical Procedures for Boolean Function Minimization
A Systolic Design for Connectivity Problems
Authors' Reply 3
On Selection of Modulus of Quadratic Codes for the Protection of Cryptographic Operations against Fault Attacks
Efficient Techniques for Dynamic Test Sequence Compaction
A Bibliographical Sketch of All-Magnetic Logic Schemes
PAM: A Piecewise-Linearly-Approximated Floating-Point Multiplier With Unbiasedness and Configurability
WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory
Constant Weight Codes for Correcting Symmetric Errors and Detecting Unidirectional Errors
Binary Multiplication with Overlapped Addition Cycles
N-Fail-Safe Sequential Machines
PRECISION: A Reconfigurable SIMD/MIMD Coprocessor for Computer Vision Systems-on-Chip
A Characterization of Some Asynchronous Sequential Networks and State Assignments
Exact Worst Case TCAM Rule Expansion
Adaptive Universal Fault-Tolerant Logic Networks
Simple Equivalent Circuits for a Step Recovery Diode and a Switching Transistor
SenSmart: Adaptive Stack Management for Multitasking Sensor Networks
Adaptive Fault Management of Parallel Applications for High-Performance Computing
Improving Cluster Utilization Through Adaptive Resource Management for Deep Neural Network and CPU Jobs Colocation
A Management Strategy for the Reliability and Performance Improvement of MLC-Based Flash-Memory Storage Systems
Fast Exact NPN Classification by Co-Designing Canonical Form and Its Computation Algorithm
A Search Memory for Many-to-Many Comparisons
Approximate Analysis of Single and Multiple Ring Networks
Efficient Encoding and Decoding Schemes for Balanced Codes
Bounds on the Number of Threshold Functions
Programming-Language-Oriented Instruction Streams
Massively Parallel Circuit Setup in GPU-SPICE
A Mobile Data Gathering Framework for Wireless Rechargeable Sensor Networks with Vehicle Movement Costs and Capacity Constraints
ELOFS: An Extensible Low-Overhead Flash File System for Resource-Scarce Embedded Devices
Notice of Violation of IEEE publication Principles in "Performance Enhancement of Ad Hoc Networks with Localized Route Repair"
An Analysis of Vector Startup Access Delays
Functional Partitioning and Simulation of Digital Circuits
Tours in Machines and Digraphs
Compile-Time Scheduling and Assignment of Data-Flow Program Graphs with Data-Dependent Iteration
Testing Programmable Logic Arrays by Sum of Syndromes
MuR-DPA: Top-Down Levelled Multi-Replica Merkle Hash Tree Based Secure Public Auditing for Dynamic Big Data Storage on Cloud
Edge Generation Scheduling for DAG Tasks Using Deep Reinforcement Learning
Authors' Reply 4
On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication
Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems
Simplification of the Covering Problem for Multiple Output Logical Networks
A New Form of Cryotron Logical Circuitry
Comments on "A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Field"
Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip
Remap-Based Inter-Partition Copy for Arrayed Solid-State Drives
Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders
Cache Memories for Data Flow Machines
Design and Performance Analysis of a Disk Array System
A User Friendly Software Environment for Protocol Synthesis
Bounded Auditable Restoration of Distributed Systems
A Fault-Tolerant Communication Architecture for Distributed Systems
Schnorr-Based Implicit Certification: Improving the Security and Efficiency of Vehicular Communications
On the Number of Transitions Entering the States of a Finite Automaton
Proving Programs to be Correct
Leveraging a Compound Graph-Based DHT for Multi-Attribute Range Queries with Performance Analysis
A Problem in Multiprogrammed Storage Allocation
MUSE: A Multi-Tierd and SLA-Driven Deduplication Framework for Cloud Storage Systems
Performance and Environment-Aware Advanced Driving Assistance Systems
Adaptive Partition Testing
A Class of Error Control Codes for Byte Organized Memory Systems -SbEC-(Sb+S)ED Codes-
Performance Evaluation of a Decoded Instruction Cache for Variable Instruction Length Computers
Chip Multiprocessor Design Space Exploration through Statistical Simulation
Fault Detection and Design Complextity in C-Testable VLSI Arrays
Some Observations on Equivalence Handling Methods
Real-Time Correction of Intensity Nonlinearities in Imaging Systems
MANA: Microarchitecting a Temporal Instruction Prefetcher
Redundancy and Don't Cares in Logic Synthesis
Design and Implementation of an Embedded Coprocessor with Native Support for 5D, Quadruple-Based Clifford Algebra
State Minimization of Incompletely Specified Sequential Machines
Relating Diagnosability, Strong Diagnosability and Conditional Diagnosability of Strong Networks
Totally Self-Checking Checkers with Separate Internal Fault Indication
Fault-Tolerant Carry-Save Adders
A Synthesis Method for Cutpoint Cellular Arrays
Speaker Diarization For Multiple-Distant-Microphone Meetings Using Several Sources of Information
A New Class of Sequential Circuits with Combinational Test Generation Complexity
Autor's Reply
Hidden regenerative loops in electronic analog computers
Near-Optimal One-Sided Scheduling for Coded Segmented Network Coding
Micro Time Cost Analysis of Parallel Computations
Microprogrammed Arrays
Fast Online Diagnosis and Recovery of Reconfigurable Logic Fabrics Using Design Disjunction
Comments on "Dynamic Window-Constrained Scheduling of Real-Time Streams in Media Servers'
Time Multiplexing as Applied to Analog Computation
A Systolic Redundant Residue Arithmetic Error Correction Circuit
The Chaos Router
Comments on "A High-Speed Algorithm for the Computer Generation of Fourier Transforms"
ST-CDP: Snapshots in TRAP for Continuous Data Protection
Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware
A Corner-Finding Algorithm for Chain-Coded Curves
Phased Logic Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry
Improving Goldschmidt Division, Square Root, and Square Root Reciprocal
Reducing Code Length of Second-Order Spectral-Null Code
A Syntactic Description and Recognition of Rotary Machine Elements
A Dictionary Machine (for VLSI)
Recent Developments in Pattern Recognition
Efficient Subquadratic Space Complexity Binary Polynomial Multipliers Based on Block Recombination
Retention-Aware Hybrid Main Memory (RAHMM): Big DRAM and Little SCM
Filter Data Cache: An Energy-Efficient Small L0 Data Cache Architecture Driven byMiss Cost Reduction
The Detection and Identification of Symmetric Switching Functions with the Use of Tables of Combinations
Properties Incompleteness Evaluation by Functional Verification
Acceleration of XML Parsing through Prefetching
Class-Congruence Property and Two-Phase Routing of Borel Cayley Graphs
On the Synthesis of Finite-State Machines from Samples of Their Behavior
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
Generic Fault Characterizations for Table Look-Up Coverage Bounding
Digit-Set Conversions: Generalizations and Application
An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs
A Data Layout With Good Data Locality for Single-Machine Based Graph Engines
Bounds on the Average Number of Products in the Minimum Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions
Optimal Search Policies for Searches with I/O Bound Tasks
The Relationship of Algorithms Used with Adjustable Threshold Elements to Differential Equations
A Model-Driven Development Approach to Mapping UML State Diagrams to Synthesizable VHDL
A Rewarding Framework for Network Resource Sharing in Co-Channel Hybrid Access Femtocell Networks
Time and Parallel Processor Bounds for Linear Recurrence Systems
Scalable Pattern Matching on Multicore Platform via Dynamic Differentiated Distributed Detection (D⁴)
Wave Scheduling - Decentralized Scheduling of Task Forces in Multicomputers
Check Schemes for Integrated Microprogrammed Control and Data Transfer Circuitry
Use of Contextual Constraints in Recognition of Contour-Traced Handprinted Characters
Competitive Learning Algorithms and Neurocomputer Architecture
Three Snakes in One Hole: The First Systematic Hardware Accelerator Design for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes
A Damage- and Fault-Tolerant Input/Output Network
Oscillographic Examination of the Operation of Function Generators
Locality-Preserving Clustering and Discovery of Resources in Wide-Area Distributed Computational Grids
On the Number of Classes of Binary Matrices
Resilient Embedded Systems Designs via on the Fly Generation of Adaptive Degenerate Components Using Machine Learning
Benchmarks on Japanese and American Supercomputers - Preliminary Results
On the Statistical Properties of a Class of Linear Product Feedback Shift-Register Sequences
Some Techniques of State Assignment for Synchronous Sequential Machines
Analytical Modeling of Set-Associative Cache Behavior
Comments on "Universal Logic Modules and Their Applications"
On the Complexity of Two Circle Strongly Connecting Problems
Numerical Function Generators Using LUT Cascades
Measures of Presortedness and Optimal Sorting Algorithms
A High Density Programmable Logic Array Chip
Relations Between Pn Cycles and Stable Feedback Shift Registers
Simple Methods for the Testing of 2-Summability of Boolean Functions and Isobaricity of Threshold Functions
A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs
An Approach for the Realization of Multithreshold Threshold Elements
Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns
Optimizing Inter-Core Communications Under the LET Paradigm using DMA Engines
Conflict-Free Access for Streams in Multimodule Memories
Progress Toward Block Diagram Standards
User-Distribution-Aware Federated Learning for Efficient Communication and Fast Inference
On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests
Taming Hardware Event Samples for Precise and Versatile Feedback Directed Optimizations
Analysis of a Shared Resource MIMD Computer Organization
On Addition and Multiplication with Hensel Codes
Conflict-Free Accesses to Strided Vectors on a Banked Cache
Transmission Capacity of Disk Storage Systems with Concurrent Arm Positioning
Collaborative Neural Architecture Search for Personalized Federated Learning
Error Correction by Alternate-Data Retry
Optimal Bounds for Finding Maximum on Array of Processors with k Global Buses
Increasing Endurance and Security of Phase-Change Memory with Multi-Way Wear-Leveling
Sink-Free Audio-on-Demand over Wireless Sensor Networks
Performance of Synchronous and Asynchronous Schemes for VLSI Systems
Efficient Modular Design of TSC Checkers for M -out-of-2 M Codes
Instruction Window Size Trade-Offs and Characterization of Program Parallelism
High-Speed Double-Precision Computation of Reciprocal, Division, Square Root and Inverse Square Root
A Learning Network Using Adaptive Threshold Elements
An Enhanced Universal N x N Fully Nonblocking Quantum Switch
A Unified Theory of the Algebraic Topological Methods for the Synthesis of Switching Systems
Efficient Privacy-Preserving Ciphertext-Policy Attribute Based-Encryption and Broadcast Encryption
NBBS: A Non-Blocking Buddy System for Multi-Core Machines
Engineering Practical Rank-Code-Based Cryptographic Schemes on Embedded Hardware. A Case Study on ROLLO
Efficient and High-Performance Parallel Hardware Architectures for the AES-GCM
Detecting Exitory Stuck-At Faults in Semimodular Asynchronous Circuits
Divided Difference Methods for Galois Switching Functions
Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders
A Scan-Based Configurable, Programmable and Scalable Architecture for Sliding Window-Based Operations
A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects
High-Throughput CORDIC-Based Geometry Operations for 3D Computer Graphics
Predictive Temperature-Aware DVFS
Cascading Transmission Gates to Enhance Multiplier Performance
A Representation of Hypergraphs in the Euclidean Space
Floating-point to logarithmic encoder error analysis
Comments on "On the Number of Classes of Binary Matrices"
Semi-Fast Fourier Transforms over GF (2 m )
Performability Analysis: A New Algorithm
A Comparison of Register Transfer Languages for Describing Computers and Digital Systems
Timing Error Tolerance in Small Core Designs for SoC Applications
Asynchronous Agreement and Its Relation with Error-Correcting Codes
An Efficient Algorithm for Determining Hadamard Sequency Vectors
Associative-Search Bubble Devices for Content-Addressable Memory and Array Logic
Reconfigurable Multiagent Embedded Control Systems: From Modeling to Implementation
Store Buffer Design for Multibanked Data Caches
Improved Fault Analysis on Subterranean 2.0
Efficient Mitchell's Approximate Log Multipliers for Convolutional Neural Networks
Joint Reliability of Medium Access Control and Radio Link Protocol in 3G CDMA Systems
Correlation Method for Computing Sensitivity Functions on a High-Speed Iterative Analog Computer
Self-Stabilizing Microprocessor: Analyzing and Overcoming Soft Errors
Optimal and Near-Optimal Universal Logic Modules with Interconnected External Terminals
Reducing Cache Pollution via Dynamic Data Prefetch Filtering
On Computer Multiplication and Division Using Binary Logarithms
Exploiting Omissive Faults in Synchronous Approximate Agreement
Experiments with a Density Router for PC Cards
Constructing Multiple CISTs on BCube-Based Data Center Networks in the Occurrence of Switch Failures
A Division Algorithm for Signed-Digit Arithmetic
A Hybrid Computer Technique for Treating Nonlinear Partial Differential Equations
Some Results in Fixed-Point Fast Fourier Transform Error Analysis
Automatic Compiler-Inserted Prefetching for Pointer-Based Applications
An Incentive Compatible Flow Control Algorithm for Rate Allocation in Computer Networks
Optimizing Nonindexed Join Processing in Flash Storage-Based Systems
A CASTLE With TOWERs for Reliable, Secure Phase-Change Memory
Architecture for VLSI Design of Reed-Solomon Decoders
Comment on "Content-addressed memory using magneto-or electro-optical interrogation"
A Video Simulation Facility
A Generalized Resistor-Transistor Logic Circuit and Some Applications
Multipartite Table Methods
Synthesis of Stochastic Flow Networks
Synthesis of Delay-Verifiable Combinational Circuits
Cost Aware Service Placement and Load Dispatching in Mobile Cloud Systems
Discriminative Fine-Grained Mixing for Adaptive Compression of Data Streams
Optimal Scheduling of Disk File Data Transfers
An Efficient and Scalable Approach for Implementing Fault-Tolerant DSM Architectures
Generalized Mixed-Criticality Static Scheduling for Periodic Directed Acyclic Graphs on Multi-Core Processors
Optimized Layout of MOS Cells