yusuke1997/dblp-id-title huggingface dataset:
Embedded cryptographic hardware
Power/ground networks in VLSI: are general graphs better than trees?
Fault-aware routing approach for mesh-based Network-on-Chip architecture
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs
A nonlinearity error calibration technique for pipelined ADCs
Architectural exploration of perpendicular Nano Magnetic Logic based circuits
Simplifying low-power SoC top-down design using the system-level abstraction and the increased automation
Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm
BUSpec: A framework for generation of verification aids for standard bus protocol specifications
Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing
An efficient background calibration technique for analog-to-digital converters based on neural network
High-performance noise-tolerant DTMOS Domino Schmitt trigger logic gate design
Two-stage fuzzy inference system for symbolic simplification of analog circuits
Recent directions in netlist partitioning: a survey
Transistor sizing for large combinational digital CMOS circuits
Fast and accurate FPGA-based framework for processor architecture vulnerability analysis
Tree placement in Cascode-Switch macros
Circuit delay calculation considering data dependent delays
A new algorithm for tile generation
Error expectation-driven design and energy optimization of approximate multipliers
FPGA implementation of a near computation free image compression scheme based on adaptive decimation
Design and implementation of virtual-single-length turbo decoder for multi-user parallel decoding
Transceiver design for LVSTL signal interface with a low power on-chip self calibration scheme
A memristive chaotic system with rich dynamical behavior and circuit implementation
Design and implementation of a real-time SDR-FPGA-based versatile radio frequency OFDM system
Iterative skew minimization for low swing clocks
DVFS-aware motion estimation design scheme based on bandwidth-rate-distortion optimization in application processor systems
A GA with heuristic-based decoder for IC floorplanning
Low-power hardware architecture of optimized logarithmic square rooter with enhanced error compensation for error-tolerant systems
Fixed-time cross-combination synchronization of complex chaotic systems with unknown parameters and perturbations
A statistics-based digital background calibration technique for pipelined ADCs
A compact and modular VLSI design for the solution of general sparse linear systems
Design and implementation of a totally self-checking 16 × 16 bit array multiplier
Design of multi-mode application-specific cores based on high-level synthesis
Automated topology synthesis of analog and RF integrated circuits: A survey
Design and research of grounding current monitoring device for converter transformer core and clamp
Why current secure scan designs fail and how to fix them?
On the design of hybrid routing mechanism for mesh-based network-on-chip
Semi-adaptive distributed approach for triplet-based architecture inter-core communication Network-on-Chip
Design space exploration of low-power flip-flops in FinFET technology
Automation of clock distribution network design for digital integrated circuits using divide and conquer technique
VLSI implementation of adaptable threshold and projection aware OMP with reconfigurable LUT-based MAC unit for ECG signal reconstruction
Few-shot learning GNN-EQL model with gm/ID method for analog integrated circuit design
Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode
A 0.004% resolution & SAT
Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques
Generating pseudo-random numbers with a Brownian system
Robust optimization algorithm of RF MEMS switches considering uncertainties
Planar subset of multi-terminal nets
On supporting rapid prototyping of embedded systems with reconfigurable architectures
Post-training quantization for efficient FPGA-based neural network acceleration
EASY: Exploring zero-cost watermarking using voice image features for hardware security
Statistical analysis of asynchronous pipelines in presence of process variation using formal models
Self-timed, minimum latency circuits for the internet of things
An efficient and reliable MRF-based methodology for designing low-power VLSI circuits
Area-time efficient end-around inverted carry adders
A new circuit configuration for emulating charge/flux controlled memelements
Dynamics and circuit implementation of a novel coupled discrete memristive system
Energy efficient and high throughput prefix-based pattern matching technique on TCAMs for NIDS
A fast near optimum VLSI implementation of FFT using residue number systems
1-V quasi constant-gm input/output rail-to-rail CMOS op-amp
On compiling behaviour to silicon: a formal language approach
A discrete formalization of switch-level circuit behavior
1GigaRad TID impact on 28 nm HEP analog circuits
Statistical power supply dynamic noise prediction in hierarchical power grid and package networks
Compacted channel routing with via placement restrictions
Low-loss active inductor with independently adjustable self-resonance frequency and quality factor parameters
A 70 pJ/b configurable 64-QAM soft MIMO detector
A hybrid cellular automaton/neural network classifier for multi-valued patterns and its VLSI implementation
Single-layer obstacle-aware routing for substrate interconnections
Implementing probabilistic algorithms on VLSI architectures
SAMURAI: A general and efficient simulated-annealing schedule with fully adaptive annealing parameters
IP protection through gate-level netlist security enhancement
A parameterized graph-based framework for high-level test synthesis
Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach
Redundant arithmetic, algorithms and implementations
Exclusive or Sum of Complex Terms expressions minimization
Energy efficient computing by multi-mode addition
GPU-based Ising computing for solving max-cut combinatorial optimization problems
High-performance CORDIC-based approximate MAC architectures for FPGA platforms
Large scale P/G grid transient simulation using hierarchical relaxed approach
High-performance anti-series diode ring amplifier for switched capacitor circuits
FPGA realization of an image encryption system using the DCSK-CDMA technique
A protocol converter for nonblocking protocols
Advanced fault diagnosis in analog and digital VLSI circuits utilizing multi-anchor space-aware temporal convolutional neural network for efficient circuit reliability assessment
Development and validation of a 64-channel ROIC prototype for SWIR line scan sensor applications
Synthesis of integer multipliers in sum of pseudoproducts form
NV-TCAM: Alternative designs with NVM devices
Access to rows and columns of a rectangular array in a concentricloop bubble memory
Network flow based buffer planning
Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK
A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000
Design and optimization of phase frequency detector through Taguchi and ANOVA statistical techniques for fast settling low power frequency synthesizer
Ultra8T: A sub-threshold 8T SRAM with leakage detection
A read-decoupled gated-ground SRAM architecture for low-power embedded memories
High performance set associative translation lookaside buffers for low power microprocessors
A rail-to-rail high speed comparator with LVDS output in 0.18-μm SiGe BiCMOS Technology
Reliability- and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation
Hardware implementation of subtractive clustering for radionuclide identification
StarSync: An extendable standard-cell mesochronous synchronizer
Simulated annealing assisted NSGA-III-based multi-objective analog IC sizing tool
Low-power multi-core ATPG to target concurrency
Design of a high performance Binary Edwards Curve based processor secured against side channel analysis
A GALS design based on multi-frequency clocking for digital switching noise reduction
Design and application of CMOS active inductor in bandpass filter and VCO for reconfigurable RF front-end
Gain-controlled noise-reduction LNA design using source-bulk resistors and double common-source topology
An efficient hierarchical timing-driven Steiner tree algorithm for global routing
Bus-driven floorplanning with thermal consideration
Explicit formulae of polynomial basis squarer for pentanomials using weakly dual basis
Hardware designs for convolutional neural networks: Memoryful, memoryless and cached
An efficient algorithm for optimal PLA folding
High-efficiency CMOS charge pump for ultra-low power RF energy harvesting applications
AI/ML algorithms and applications in VLSI design and technology
Efficient modulo 2 n +1 adder architectures
A hardware implementation of realloc function
Transconductance improvement method for low-voltage bulk-driven input stage
Testability conditions for two-dimensional bilateral arrays
An energy-efficient single-cycle RV32I microprocessor for edge computing applications
A survey on machine learning-based routing for VLSI physical design
Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs
A new adaptive selection strategy for reducing latency in networks on chip
Two terminal channel routing using at most density plus two tracks
Analog behavioral equivalence boundary computation under the effect of process variations
VHDL-AMS based modeling and simulation of mixed-technology microsystems: a tutorial
A power efficient and simple scheme for dynamically biasing cascode amplifiers and telescopic op-amps
A novel design of a ternary coded decimal adder/subtractor using reversible ternary gates
A low-power two-step gray-code counter for single-slope ADC in CMOS image sensors
A robust recognition error recovery for micro-flow cytometer by machine-learning enhanced single-frame super-resolution processing
A simulation optimization method for Verilog-AMS IBIS model under overclocking
Low-power design techniques for scaled technologies
AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation
A variation resilient keeper design for high performance domino logic applications
Reliability simulation for analog ICs: Goals, solutions, and challenges
Erratum to: Regular partitioning for synthesizing fixed-size systolic arrays
An improved reconfigurable logic in resistive random access memory
Power efficient multi-stage CMOS rectifier design for UHF RFID tags
A wide-output buck DC-DC power management IC
New advances of high-level synthesis for efficient and reliable hardware design
A lossless floating capacitance multiplier based on the single DDCC-
Genetic algorithm-based FSM synthesis with area-power trade-offs
A corner-based hierarchical circuit extractor
Incremental/decremental memristor utilizing solely a voltage controlled second-generation current conveyor
Efficient hardware implementations of lightweight Simeck Cipher for resource-constrained applications
Content-addressable memory using selective-charging and adaptive-discharging scheme for low-power hardware search engine
Super current recycling folded cascode amplifier with ultra-high current efficiency
Hardware architectures for public key cryptography
Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution
Dynamic electromigration modeling for transient stress evolution and recovery under time-dependent current and temperature stressing
Optimizing code allocation for hybrid on-chip memory in IoT systems
An efficient lower bound algorithm for channel routing
Complete design approach of a 3rd order continuous-time sigma-delta ADC with FIR feedback and low-noise low-distortion op-amp achieving 101.8 dB SNDR and -110dB THD
Bio-inspired fault tolerant network on chip
New bit-parallel Montgomery multiplier for trinomials using squaring operation
A real-time pseudo-background gain calibration strategy for residue amplifiers of pipeline ADCs
A fine-grained mixed precision DNN accelerator using a two-stage big-little core RISC-V MCU
A 1Gpixel 10FPS CMOS image sensor using pixel array high-speed readout technology
A 10-Gb/s low-power inverter-based optical receiver front-end in 0.13-μm CMOS process
A new clock network synthesizer for modern VLSI designs
Predicting reconfigurable interconnect performance in distributed shared-memory systems
A large-scale in-memory computing for deep neural network with trained quantization
A flexible bottom-up approach for layout generation
An efficient terminal and model order reduction algorithm
A timing-driven floorplanning algorithm with the Elmore delay model for building block layout
Energy and relevance-aware adaptive monitoring method for wireless sensor nodes with hard energy constraints
lambda, an integrated master-slice LSI CAD system
Multi-parameter clock skew scheduling
Planar CMOS to multi-gate layout conversion for maximal fin utilization
A low-power switched-current CDMA matched filter employing MOS linear matching cell with on-chip A/D converter
Comparison of integer-order chaotic attractors as randomness source in collision-free robotic exploration methods
Adaptable I/O pad circuit for multiple voltage units bus operation
Surrogating circuit design solutions with robustness metrics
An improved algorithm for accelerating reconfiguration of VLSI array
Fast and scalable parallel layout decomposition in double patterning lithography
Minimizing total wire length during 1-dimensional compaction
Design of dynamic prairie dog optimization based variable length conditional counter enabled multiplier with improved slack time and power
TA-denseNet: Efficient hardware trust and assurance model based on feature extraction and comparison of SEM images and GDSII images
A feed-forward compensated FVF LDO regulator with no on-chip compensation capacitors
Efficient automatic parallelization of a single GPU program for a multiple GPU system
An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition
Hardware design for blind source separation using fast time-frequency mask technique
Massive parallelism in multi-level simulation of VLSI circuits
Design of CMOS VCO with XNOR and transmission gate based delay stages
Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures
An aggregating based model order reduction method for power grids
Constructing minimal spanning/Steiner trees with bounded path length
Hardware implementation of tag-reader mutual authentication protocol for RFID systems
A precision programmable multilevel voltage output and low-temperature-variation CMOS bandgap reference with area-efficient transistor-array layout
A new write assist technique for SRAM design in 65 nm CMOS technology
A computational design of a versatile microchamber for in vitro nanosecond pulsed electric fields experiments
Approximate subtractors designed for image processing applications
Cross-regulation characteristics of non-ideal single-inductor dual-output buck converter with voltage controlled
SoC interconnection protection through formal verification
Fast timing analysis of clock networks considering environmental uncertainty
Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability
Modeling and design of 3-D MPPT for ultra low power RF energy harvesters
A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands
Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials
A digital predistortion assisted hybrid supply modulator for envelope tracking power amplifiers
Brownian distance correlation-directed search: A fast feature selection technique for alternate test
Sizing of multi-stage Op Amps by combining design equations with the gm/ID method
Causal reasoning mining approach to analog circuit verification
Capture-power-aware test data compression using selective encoding
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis
HW/SW co-design of a hyperelliptic curve cryptosystem using a microcode instruction set coprocessor
Insertion of jog series in layout compaction
Energy efficient computation: A silicon perspective
A new hybrid algorithm for analog ICs optimization based on the shrinking circles technique
ASG: Automatic schematic generator
Improving the thermal reliability of photonic chiplets on multicore processors
A high-efficiency feedforward compensation method for capacitor-less LDO
Testable design of large random access memories
A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs
Enhancement of fault collection for embedded RAM redundancy analysis considering intersection and orphan faults
An effective routability-driven packing algorithm for large-scale heterogeneous FPGAs
Design of CMOS current-mode multi-operand addition circuit based on carry stack
OPCoSA: an Optimized Product Code for space applications
A graph-based heuristic channel router
Highly stable soft-error immune SRAM with multi-node upset recovery for aerospace applications
Implementation of two new 10-bit 1 GS/s hybrid DACs with a novel gain error calibration technique
Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper)
About folded-PLA area and folding evaluation
Efficient FPGA implementation of RNS Montgomery multiplication using balanced RNS bases
On the minimization of multiplier-adders for powers-of-two filter using a novel right to left (R2L) algorithm
Efficient high dimensional yield analysis for SRAM circuits via stack model and adaptive sampling
(Pen)-ultimate tiling?
Path-delay-fault testability properties of multiplexor-based networks
Improving power and performance of on-chip network through virtual channel sharing and power gating
Digital predistorter with improving index accuracy of lookup table based on FPGA
Signal resynchronization in VLSI systems
Area and power efficient hard multiple generator for radix-8 modulo 2 n - 1 multiplier
Output capacitor-less LDO regulator with dual-pass adaptive biasing and dynamic current generation for ultra-low-power IoT
Bisection trees and half-quad trees: Memory and time efficient data structures for VLSI layout editors
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework
An efficient runtime power allocation scheme for many-core systems inspired from auction theory
Performance-driven scheduling of behavioural specifications
Automatic synthesis of large Moore sequencers
Technology mapping for area and speed
Microelectronic architectures and devices for signal and symbol processing
Analytic estimation of jitter and eye diagram based on transmission line time domain response considering skin effect and stochastic crosstalk
Architectural implications of spatial thermal filtering
A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level
Characterizing SRAM and FF soft error rates with measurement and simulation
Switch box routing: a retrospective
Raspberry-Pi based system for propofol monitoring
SIAR: Customized real-time interactive router for analog circuits
RDMM: Runtime dynamic migration mechanism of distributed cache for reconfigurable array processor
Low-latency QYOLOv10-based FPGA implementation for real-time object detection
Mixed-signal on-chip timing measurements
High-performance OTFS transmitter on FPGA: A hybrid HLS/VHDL design
New algorithms for increased efficiency in hierarchical design rule checking
Two-level logic minimization: an overview
Performance enhancement of advanced recycling folded cascode operational transconductance amplifier using an unbalanced biased input stage
Techniques for dual forms of Reed-Muller expansion conversion
Reconfigurable very high throughput low latency VLSI (FPGA) design architecture of CRC 32
WDP-BNN: Efficient wafer defect pattern classification via binarized neural network
Signal compression through spatial frequency-based motion estimation
Reducing random-dopant fluctuation impact using footer transistors in many-core systems
Realizations of fractional-order PID loop-shaping controller for mechatronic applications
Switchbox routing using score function
A closed-loop ASIC design approach based on logical effort theory and artificial neural networks
Design and performance analysis of wrap-gate CNTFET-based ring oscillators for IoT applications
Wakeup scheduling and its buffered tree synthesis for power gating circuits
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology
A dual front-end for the new GPS/GALILEO generation in a 0.35 µm SiGe process
Nonlinear analysis, circuit implementation, and application in image encryption of a four-dimensional multi-scroll hyper-chaotic system
Low-power state encoding for partitioned FSMs with mixed synchronous/asynchronous state memory
Hardware implementation of a novel chaos-based cryptosystem for secure image transmission
An improved communication scheme for non-HOL-blocking wireless NoC
Design and analysis of faithful parallel mean filter using approximate adders and 4:2 compressors for low-power VLSI architectures
A novel bus transfer mode (AS transfer) and a performance evaluation methodology
Secure image encryption scheme using 4D-Hyperchaotic systems based reconfigurable pseudo-random number generator and S-Box
Detection and identification of input/output stuck-at and bridging faults in combinational and sequential VLSI networks by universal tests
VLSI based fuzzy logic controller enabled adaptive interactive multiple model for target tracking
Diagnosis of interconnects using a structured walking-1 approach
Performance planning
All-digital background calibration technique for timing mismatch of time-interleaved ADCs
Erratum to the Special Section on DCIS 2006 [Integration, the VLSI Journal, Volume 42, Issue 3, June 2009]
MICSim: A modular pre-circuit simulator for mixed-signal compute-in-memory accelerators in CNNs and transformers
Rapid estimation of the probability of SRAM failure via adaptive multi-level sliding-window statistical method
A nature-inspired firefly algorithm based approach for nanoscale leakage optimal RTL structure
Investigating the influence of adiabatic load on the 4-phase adiabatic system design
Design of analog front-end integrated circuit of tactile sensor for human-machine interface
PLMAP - A piecewise linear MOS circuit analysis program
An enhanced logistic chaotic map based tweakable speech encryption algorithm
Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration
Implementation of a thermal management unit for canceling temperature-dependent clock skew variations
Online detection of hardware Trojan enabled packet tampering attack on network-on-chip: A Bayesian approach
Thermal and Congestion-aware Deadlock-free Application-specific Novel Halted Routing Strategy in 3D NoCs
An improved KFDD based reversible circuit synthesis method
Necessary and sufficient conditions for the routability of classical channels
Test generation through logic programming
FPGA based multi-standard configurable FSK demodulator
An area-efficient timing closure technique for FPGAs using Shannon's expansion
Ultra-low power linearized FVF based BD double diffusor double differential pair transconductor
TRACK: An algorithm for fault-tolerant, dynamic and scalable 2D mesh network-on-chip routing reconfiguration
A dual adaptive bias based low-dropout regulator with nonlinear current mirror loop for fast transient response
Impact of various NBTI distributions on SRAM performance for FinFET technology
Post-routing layer assignment for double patterning with timing critical paths consideration
A novel class-E class-D doherty power amplifier based on past matching network with linearity region extension and flat output power