yusuke1997/dblp-id-title huggingface dataset:
Applying infinite state model checking and other analysis techniques to tabular requirements specifications of safety-critical systems
Special issue on recent advancements in machine learning algorithms for internet of things
A scheduler synthesis methodology for joint SW/HW design exploration of SoC
HDTLib: an efficient implementation of SystemC data types for fast simulation at different abstraction levels
A simultaneous multithreading processor architecture with predictable timing behavior
CAD synthesis tools for floating-gate SoC FPAAs
Implementation and validation of architectural space exploration techniques for domain-specific reconfigurable computing
The Agamid design-space exploration framework - Task-accurate simulation of hardware-enhanced run-time management for many-core
Modeling a Mobile Cellular Network Using a Discrete-Event Simulator
System-Level Synthesis Using Evolutionary Algorithms
Testing real-time embedded systems using high level architecture
C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems
On the impact of hardware-related events on the execution of real-time programs
Locality optimization in a compiler for wireless applications
Accurate age counter for wear leveling on non-volatile based main memory
Target software generation: an approach for automatic mapping of SystemC specifications onto real-time operating systems
A methodology aimed at better integration of functional verification and RTL design
A Theory for Co-Scheduling Hardware and Software Pipelines in ASIPs and Embedded Processors
Integrating the SysML and the SystemC-UML profiles in a model-driven embedded system design flow
Efficient placement and migration policies for an STT-RAM based hybrid L1 cache for intermittently powered systems
Model predictive-based DNN control model for automated steering deployed on FPGA using an automatic IP generator tool
Special issue with selected papers from 2016 Brazilian Symposium on Computer Engineering (SBESC 2016)
Formal verification of component-based designs
Exploration of energy efficient memory organisations for dynamic multimedia applications using system scenarios
Data pattern aware FTL for SLC+MLC hybrid SSD
Hot sparing for lifetime-chip-performance and cost improvement in application specific SIMT processors
Special Issue on Networks-on-Chips: Design Flows and Case Studies
A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile
High-level customization framework for application-specific NoC architectures
Computational reflection and its application to platform verification
A hardware/software partitioning method based on graph convolution network
System Level Virtual Prototyping of DSP SOCs Using Grammar Based Approach
Efficient schedulability tests for real-time embedded systems with urgent routines
Optimizing control flow in loops using interval and dependence analysis
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Prototyping
Design, synthesis and verification of a smart imaging core using SystemC
Towards closing the specification gap by integrating algorithm-level and system-level design
Markov decision process (MDP) framework for software power optimization using call profiles on mobile phones
Systematic Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in ACROPOLIS: A Pre-Compiler for Multimedia Applications
Towards automated implementation of adaptive systems from abstract SystemC specifications - From SystemC adaptive processes to embedded software and to synthesizable hardware descriptions
Architectural Re-engineering of Janus using Object Modeling and Rapid Prototyping
Optimizing Leakage Energy Consumption in Cache Bitlines
Centaur: a hybrid network-on-chip architecture utilizing micro-network fusion
Low-cost modular devices for on-road vehicle detection and characterisation
Memphis: a framework for heterogeneous many-core SoCs generation and validation
A novel Gini index decision tree data mining method with neural network classifiers for prediction of heart disease
On fast development of FPGA-based SOA services - machine vision case study
Functional Validation of Mixed Hardware/Software Systems based on Specification, Partitioning, and Simulation of Test Cases
Optimal mapping of program overlays onto many-core platforms with limited memory capacity
VLIW Processor Codesign for Video Processing
A distributed algorithm to schedule TSCH links under the SINR model
Synthesis of Hard Real-Time Application Specific Systems
Simplified introduction of power intent into a register-transfer level model
Research on effects of input servitization on export technological complexity of manufacturing industry of China
Developing self-adaptive automotive systems - On the integration of service-orientation into automotive development processes
Towards SoC Validation Through Prototyping: A Systematic Approach Based on Reconfigurable Platform
Automated software attack recovery using rollback and huddle
A Remote Methodology for Embedded Systems Design and Validation
The OMLP family of optimal multiprocessor real-time locking protocols
Network design and planning of wireless embedded systems for industrial automation - Applications and case studies in oil refineries
Algorithmic aspects for functional partitioning and scheduling in hardware/software co-design
A self-adaptive fault-tolerant systems for a dependable Wireless Sensor Networks
Hybrid Cache Analysis in Running Time Verification of Embedded Software
An integrated high-level hardware/software partitioning methodology
Verification of fixed-point digital controllers using direct and delta forms realizations
An effective state-based predictive approach for leakage energy management on embedded systems
Performance analysis and modeling of SQLite embedded databases on flash file systems
Formal Verification for Embedded System Designs
SBESC 2013 guest editor's introduction
SoC based floating point implementation of differential evolution algorithm using FPGA
ImGA: an improved genetic algorithm for partitioned scheduling on heterogeneous multi-core systems
Machine-Description Driven Compilers for EPIC and VLIW Processors
Squashing code size in microcoded IPs while delivering high decompression speed
Single Source Design Environment for Embedded Systems Based on SystemC
Intermediate Representations for Design Automation of Multiprocessor DSP Systems
A CoDesign case study with the MCSE methodology
RELSPEC: a framework for reliability aware design of component based embedded systems
Test data compression for digital circuits using tetrad state skip scheme
SystemQ: Bridging the gap between queuing-based performance evaluation and SystemC
Very Rapid Prototyping of Wearable Computers: A Case Study of VuMan 3 Custom versus Off-the-Shelf Design Methodologies
Automatic low-cost IP watermarking technique based on output mark insertions
Reward-based voltage scheduling for dynamic-priority hard real-time systems
Loop transformations for flash memory: cost models and performance effects
Energy efficient semi-partitioned scheduling for embedded multiprocessor streaming systems
Efficient fuzzy c-means based multilevel image segmentation for brain tumor detection in MR images
Float-to-fixed and fixed-to-float hardware converters for rapid hardware/software partitioning of floating point software applications to static and dynamic fixed point coprocessors
Code Optimization Techniques in Embedded DSP Microprocessors
Deploying human activity recognition in embedded RISC-V processors
Improving Java performance and energy dissipation through efficient code caching
Automating functional unit and register binding for synchoros CGRA platform
Design exploration of a NVM based hybrid instruction memory organization for embedded platforms
RTOS modeling in SystemC for real-time embedded SW simulation: A POSIX model
LusSy: An open tool for the analysis of systems-on-a-chip at the transaction level
A time Petri net-based method for embedded hard real-time software synthesis
An optimization based design for integrated dependable real-time embedded systems
New paradigm of FPGA-based computational intelligence from surveying the implementation of DNN accelerators
Private reliability environments for efficient fault-tolerance in CGRAs
FPGA automatic re-synchronisation for pipelined, floating point control systems applications
Combining static and dynamic array detection for binary synthesis with multiple memory ports
Physics-informed neural networks for monitoring dynamic systems: ring bearing system study case
Processor Utilization Bounds for Real-Time Systems With Precedence Constraints
Design and implementation of a uniformity-improving page allocation scheme for flash-based storage systems
Efficient hierarchical bus-matrix architecture exploration of processor pool-based MPSoC
Inter-FPGA interconnect topologies exploration for multi-FPGA systems
Codesign analysis of a computer graphics application
Application-aware deduplication for performance improvement of flash memory
Scheduling for Concept-Oriented Rapid Prototyping
Automated design space exploration for FPGA-based heterogeneous interconnects
LSB-Tree: a log-structured B-Tree index structure for NAND flash SSDs
Runtime deadlock analysis for system level design
An energy aware buffer mapping technique on hybrid STT-MRAM memories with multiple retention time for stream applications
A model of architecture for estimating GPU processing performance and power
A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library
A survey on partitioning models, solution algorithms and algorithm parallelization for hardware/software co-design
ATLeS-SN
Embedded system design
Estimating data bus size for custom processors in embedded systems
Special issue with selected papers from 2019 Brazilian Symposium on Computer Engineering (SBESC 2019)
The fast evolving landscape of on-chip communication - Selected future challenges and research avenues
Control-schedule co-design for fast stabilization in real time systems facing repeated reconfigurations
Multiprovision: a Design Space Exploration tool for multi-tenant resource provisioning in CPU-GPU environments
Optimistic chordal coloring: a coalescing heuristic for SSA form programs
Synthetic image generation for training deep learning-based automated license plate recognition systems on the Brazilian Mercosur standard
New Alternatives to the Estimation Problem in Hardware-Software Codesign of Complex Embedded Systems: The H.261 Video Co-dec Case Study
MEMCOP: memory-aware co-operative power management governor for mobile games
Phase distance mapping: a phase-based cache tuning methodology for embedded systems
Hardware-accelerated service-oriented communication for AUTOSAR platforms
Efficient test case generation for validation of UML activity diagrams
A co-synthesis approach to embedded system design automation
Progressive and explicit refinement of scheduling for multidimensional data-flow applications using UML MARTE
Exploiting UML based validation for compliance checking of TLM 2 based models
CASES 2009 guest editor's introduction
A hierarchical run-time adaptive resource allocation framework for large-scale MPSoC systems
Effective file data-block placement for different types of page cache on hybrid main memory architectures
SBESC 2014 guest editors' introduction
A framework for reliability-aware design exploration on MPSoC based systems
Hardware-Software Partitioning for Real-Time Embedded Systems
Editorial introduction - Special issue on languages, models and model based design for embedded systems
An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling
A SystemC-only design methodology and the CINE-IP multimedia platform
Modular static scheduling of synchronous data-flow networks - An efficient symbolic representation
Redundancy optimization for error recovery in digital microfluidic biochips
CaPPS: cache partitioning with partial sharing for multi-core embedded systems
Implementation of high precision/low latency FP divider using Urdhva-Tiryakbhyam multiplier for SoC applications
Moduli Set Selection and Cost Estimation for RNS-Based FIR Filter and Filter Bank Design
Rethinking the synthesis of buses, data mapping, and memory allocation for MPSoC
Torque regression using machine learning techniques in automotive ECUs
Enhanced Image Detection on an ARM based Embedded System
Data-assemblage: a translation-page-aware data block allocation strategy for flash-based solid state drives
LUT based realization of fixed-point multipliers targeting state-of-art FPGAs
Trace-driven and processing time extensions for Noxim simulator
QOS distributed routing protocol for mobile ad-hoc wireless networks using intelligent packet carrying systems
An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design
SystemC co-simulation for core-based embedded systems
Simulation is essential for embedded control systems with task jitter
Supporting single and multi-core resource access protocols on object-oriented RTOSes
The Extended Partitioning Problem: Hardware/Software Mapping, Scheduling, and Implementation-bin Selection
A low-cost fluid-level synthesis for droplet-based microfluidic biochips integrating design convergence, contamination avoidance, and washing
DOL-BIP-Critical: a tool chain for rigorous design and implementation of mixed-criticality multi-core systems
Deep learning parallel computing and evaluation for embedded system clustering architecture processor
Introductions to special issue on ESWEEK 2011
Recent trends in embedded system software performance estimation
Embedded System Design Using Formal Model Refinement: An Approach Based on the Combined Use of UML and the B Language
A rule-based availability-driven cosynthesis scheme
An Integrated Cosimulation Environment for Heterogeneous Systems Prototyping
Fault buffers - Enabling near-true voltage scaling in variation-sensitive L1 caches
ESWEEK 2007 special issue introduction
Scheduling and energy savings for small scale embedded FreeRTOS-based real-time systems
Selective register-file cache: an energy saving technique for embedded processor architecture
Representation of synchronous, asynchronous, and polychronous components by clocked guarded actions
A Framework for Data Partitioning for C++ Data-Intensive Applications
Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems
Simulating Hardware, Software and Electromechanical Parts Using Communicating Simulators
Signal multiplexing approach to improve inter-FPGA bandwidth of prototyping platform
An adaptive CFAR embedded system architecture for target detection
Instruction set independent program encoding
An Overview of Rapid System Prototyping Today
Reducing the complexity of instruction-level power models for VLIW processors
Special issue with selected papers from 2018 Brazilian Symposium on Computer Engineering (SBESC 2018)
Retraction Note to: Online measurement of water quality and reporting system using prominent rule controller based on aqua care-IOT
Code generation for distributed embedded systems with VDM-RT
On the hard-real-time scheduling of embedded streaming applications
Compilation Methods for the Address Calculation Units of Embedded Processor Systems
A Compositional Framework for Hardware/Software Co-Design
A fast and accurate hybrid fault injection platform for transient and permanent faults
A novel input data transition aware dynamic voltage scaling based low power MAC architecture for DSP applications
FTL algorithms for NAND-type flash memories
Special issue with selected papers from 2017 Brazilian Symposium on Computer Engineering (SBESC 2017)
Optimization of multitask parallel mobile edge computing strategy based on deep learning architecture
A novel algorithm for real-time framework in multiprocessor environment
Progressive and explicit refinement of scheduling for multidimensional data-flow applications using uml marte
Extending the Kernighan/Lin Heuristic for Hardware and Software Functional Partitioning
Design and analysis of an adaptive radiation resilient RRAM subsystem for processing systems in satellites
Prototyping of Tightly Coupled Hardware/Software-Systems
Energy efficient scheduling algorithm for the multicore heterogeneous embedded architectures
MEMOCODE 2006 guest editors' introduction
Reducing neighbor discovery time in sensor networks with directional antennas using dynamic contention resolution
Synthesis for Mixed Arithmetic
Retraction Note to: QOS distributed routing protocol for mobile ad-hoc wireless networks using intelligent packet carrying systems
TAPES - Trace-based architecture performance evaluation with SystemC
Power Estimation Using Probability Polynomials
A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks
LYCOS: the Lyngby Co-Synthesis System
Towards Automatic Validation of Dynamic Behavior in Pipelined Processor Specifications
An energy efficient multi-target binary translator for instruction and data level parallelism exploitation
Self-aware Memory: an adaptive memory management system for upcoming manycore architectures and its decentralized self-optimization process
ARTS: A SystemC-based framework for multiprocessor Systems-on-Chip modelling
On embedding a hardware description language in Isabelle/HOL
FACE: Fine-tuned Architecture Codesign Environment for ASIP Development
Issues for low-power CAD tools: A system-level design study
Reliability analysis of real-time fault-tolerant task models
Scheduling real-time systems with cyclic dependence using data criticality
A method for partitioning applications in hybrid reconfigurable architectures
System level modeling methodology of NoC design from UML-MARTE to VHDL
Revisiting the battery level indicator of mobile devices
Retraction Note to: Test data compression for digital circuits using tetrad state skip scheme
Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC
Energy-efficient instruction compression with programmable dictionaries
A model-driven framework for design and verification of embedded systems through SystemVerilog
Communication-aware VFI partitioning for GALS-based networks-on-chip
Transparent integration of autonomous vehicles simulation tools with a data-centric middleware
A Survey on IP Watermarking Techniques
A generic conceptual framework based on formal representation for the design of continuous/discrete co-simulation tools
Subclass based parallel learning neural network for classification of masses in mammograms
Erratum: A rule-based availability-driven cosynthesis scheme
Run-time parallelization switching for resource optimization on an MPSoC platform
Hardware/Software Communication and System Integration for Embedded Architectures
TEE based session key establishment protocol for secure infotainment systems
Deterministic reversible MPSoC debugger based on virtual platform execution traces
On applying multiple criteria decision analysis in embedded systems design
Embedded systems security - an overview
Model-based design verification for embedded systems through SVOCL: an OCL extension for SystemVerilog
Multi-Valued Performance Metrics for Real-Time Embedded Systems
Virtual Prototyping For Modular And Flexible Hardware-Software Systems
A Framework for Modeling and Estimating the Energy Dissipation of VLIW-Based Embedded Systems
ISDL: An Instruction Set Description Language for Retargetability and Architecture Exploration
Instruction scheduling with k-successor tree for clustered VLIW processors
IMPACCT: Methodology and Tools for Power-Aware Embedded Systems
SBESC 2015 guest editors' introduction
A survey on estimating the timing constraints of hard real-time systems
Hardware/Software Co-Design of Complex Embedded Systems: An Approach Using Efficient Process Models, Multiple Formalism Specification and Validation via Co-Simulation
Synthesis and Time Partitioning for Reconfigurable Systems
Guest editorial for special issue on embedded system security
Novel adaptive quantization methodology for 8-bit floating-point DNN training
HASoC - Towards a New Method for System-on-a-Chip Development
Fast Prototyping Methodology for Distributed and Heterogeneous Architectures: Application to Mpeg-4 Video Tools
Monitoring the performance of multicore embedded systems without disrupting its timing requirements
Fast and Time-Accurate Cosimulation with OS Scheduler Modeling
Co-synthesis and co-simulation of control-dominated embedded systems
Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths
An analysis of the Gateway Integrity Checking Protocol from the perspective of Intrusion Detection Systems
An embedded automatic license plate recognition system using deep learning
Hybrid Multi-FPGA Board Evaluation by Permitting Limited Multi-Hop Routing
DesertFD: a finite-domain constraint based tool for design space exploration
Specification and Validation of Embedded Systems using LUSTRE and ARGOS. Case Study: The Automatic Headlight Leveling System
Model-based implementation of distributed systems with priorities
CAD tool for hardware software co-synthesis of heterogeneous multiple processor embedded architectures
Design and evaluation of an energy efficient DiamondMesh topology for on-chip interconnection networks
Automatic VHDL-C Interface Generation for Distributed Cosimulation: Application to Large Design Examples
Adaptive run-time scheduling of dependent services for service-oriented IoT systems
An integrated memory-disk system with buffering adapter and non-volatile memory
A multiple-ISA reconfigurable architecture
Guest Editor Introduction
Optimizing Timed Cosimulation by Hybrid Synchronization
EMSOFT 2009 guest editors' introduction
Assertion Based Verification and Analysis of Network Processor Architectures
Cyber-physical systems design: transition from functional to architectural models
Design methodology for on-chip-based processor debugger
Hardware-Assisted Signal Activity Analysis for Power Estimation in Rapid Prototyped Systems
An overview of today's high-level synthesis tools
HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors
Design Methodology for a DVB Satellite Receiver ASIC
Message from the editors-in-chief
Visitor-based application analysis methodology for early design space exploration
Tuning of Cache Ways and Voltage for Low-Energy Embedded System Platforms
Codesign of a parallel architecture and an optimizing compiler backend: SIN rete processing as a case study
Compilation From Matlab to Process Networks Realized in FPGA
FoRTReSS: a flow for design space exploration of partially reconfigurable systems
CODES+ISSS 2007 guest editors' introduction
Interfacing Software Libraries from Nondeterministic Prototypes
Improving Software Performance with Configurable Logic
Efficient architecture/compiler co-exploration using analytical models
Stack Size Minimization for Embedded Real-Time Systems-on-a-Chip
Sequential equivalence checking between system level and RTL descriptions
Emulation and verification framework for MPSoC based on NoC and RISC-V
Non deterministic caches: a simple and effective defense against side channel attacks
Using method interception for hardware/software co-development
UML for electronic systems design: a comprehensive overview
Dynamic concurrency throttling on NUMA systems and data migration impacts
Reprogrammable Platforms for High-Speed Data Acquisition
Experimental evaluation and comparison of latency-optimized opticaland conventional multi-FPGA systems
Efficient Memory Management for High-Speed ATM Systems
Randomizing task placement and route selection do not randomize traffic (enough)
On the Utilization of Java Technology in Embedded Systems
Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors
An efficient management scheme for updating redundant information in flash-based storage system
A content-aware writing mechanism for reducing energy on non-volatile memory based embedded storage systems