yusuke1997/dblp-id-title huggingface dataset:
A CatBoost Based Approach to Detect Label Flipping Poisoning Attack in Hardware Trojan Detection Systems
The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs
Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops
Single Event Upset Evaluation for a 28-nm FDSOI SRAM Type Buffer in an ARM Processor
A Bulk Built-In Voltage Sensor to Detect Physical Location of Single-Event Transients
A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects
The Coupling Model for Function and Delay Faults
Using At-Speed BIST to Test LVDS Serializer/Deserializer Function
Calibration Impact on the Characterization of Components at Temperature
Low Cost On-Line Testing Strategy for RF Circuits
IDDT Testing versus IDDQ Testing
Low Power Memory Built in Self Test Address Generator Using Clock Controlled Linear Feedback Shift Registers
HIST: A hierarchical self test methodology for chips, boards, and systems
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism
Novel Practical Built-in Current Sensors
Efficient March Tests for a Reduced 3-Coupling and 4-Coupling Faults in Random-Access Memories
On the Impact of Performance Faults in Modern Microprocessors
Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip
Deep Soft Error Propagation Modeling Using Graph Attention Network
Compaction of IDDQ Test Sequence Using Reassignment Method
Multiple fault detection in two-level multi-output circuits
A Novel Noise-assisted Prognostic Method for Linear Analog Circuits
Modern Test Techniques: Tradeoffs, Synergies, and Scalable Benefits
An efficient design of embedded memories and their testability analysis using Markov chains
Golden-Free Processor Hardware Trojan Detection Using Bit Power Consistency Analysis
New Editors - 2016
Design of a Low Noise Amplifier Based on Novel Monolayer Graphene FET
On Non-Statistical Techniques for Fast Fault Coverage Estimation
Combined probabilistic testability calculation and compact test generation for PLAs
A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area
MT-SIM a mixed-level transition fault simulator based on parallel patterns
Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints
Testing Methods for PUF-Based Secure Key Storage Circuits
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test
Verification and Validation with Prototype Chip Implemented with Layout Level Scan C-Elements
Design and Verification of an Asynchronous NoC Router Architecture for GALS Systems
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs
BIST/Digital-Compatible Testing of RF Devices Using Distortion Model Fitting
Guest Editorial: Special Issue on Analog, Mixed-Signal, RF, and MEMS Testing
On-Line Fault Resilience Through Gracefully Degradable ASICs
A 1-MHz Area-Efficient On-Chip Spectrum Analyzer for Analog Testing
Investigating and Improving the Performance of Radiation-Hardened SRAM Cell with the Use of Multi-Voltage Transistors
Process-Variation and Temperature Aware SoC Test Scheduling Technique
Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG
Impact of Total Ionizing Dose on Bulk Built-In Current Sensors with Dynamic Storage Cell
Designing Nanoscale Logic Circuits Based on Markov Random Fields
Functionally Fault-tolerant DSP Microprocessor using Sigma-delta Modulated Signals
2018 JETTA Reviewers
Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTAC TM eFlash Memories
Failure Probability due to Radiation-Induced Effects in FinFET SRAM Cells under Process Variations
Construction and Analysis of Augmented Time Compactors
Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB®
An Efficient Contact Screening Method and its Application to High-Reliability Non-Volatile Memories
Analytical Low Frequency NBTI Compact Modeling with H2 Locking and Electron Fast Capture and Emission
Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs
An Investigation into the Failure Characteristics of External PCB Traces with Different Angle Bends
Deterministic BIST with Partial Scan
High-Level Controllability and Observability Analysis for Test Synthesis
Bounds on the sizes of irredundant test sets and sequences for combinational logic networks
On the Tolerance to Manufacturing Defects in Molecular QCA Tiles for Processing-by-wire
2012 JETTA Reviewers
SRAM-Based FPGAs: Testing the Embedded RAM Modules
A Novel Built-in Current Sensor for N-WELL SET Detection
Correlation of Heavy-Ion and Laser Testing on a DC/DC PWM Controller
On local transformations and path delay fault testability
Signature analysis for fault detection of mixed-signal ICs based on dynamic power-supply current
A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging
A Numeral System Based Framework for Improved One-Lambda Crosstalk Avoidance Code Using Recursive Symmetry Formula
Hazard simulation of sequential circuits
A unified approach for fault simulation of linear mixed-signal circuits
Memory Fault Modeling Trends: A Case Study
Reliability Limits of TMR Implemented in a SRAM-based FPGA: Heavy Ion Measures vs. Fault Injection Predictions
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data
2015 JETTA-TTTC Best Paper Award
Critical Path Selection for Delay Testing Considering Coupling Noise
RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences
The OR-k method for on-line checking of programmable logic arrays
Test Technology Newsletter April 2007
Remaining Useful Life Prediction of Analog Circuit Using Improved Unscented Particle Filter
Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors
Neural Network-based Online Fault Diagnosis in Wireless-NoC Systems
A Buffer-Oriented Methodology for Microarchitecture Validation
AFIA: ATPG-Guided Fault Injection Attack on Secure Logic Locking
Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing
Diagnosis Strategies for Hardware or Software Systems
High Speed On-Chip Signal Generation for Debug and Diagnosis
Reducing the CMOS RAM test complexity with I DDQ and voltage testing
Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting
ADC Dynamic Parameter Testing Scheme Under Relaxed Conditions
A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages
C -Testable modified-Booth multipliers
A Comprehensive Framework for Counterfeit Defect Coverage Analysis and Detection Assessment
A Simplified Calibration Methodology for On-Chip Couplers
Evaluating the Effectiveness of D-chains in SAT-based ATPG and Diagnostic TPG
Fault Diagnosis in Lab-on-Chip Using Digital Microfluidic Logic Gates
A Comprehensive FPGA-Based Assessment on Fault-Resistant AES against Correlation Power Analysis Attack
Delay Test Generation: A Hardware Perspective
A Passive Authentication System Based on Optical Variable Nano/Micro-Structures
Known Good Die
An Accurate Combination of on-the-fly Interface Trap and Threshold Voltage Methods for NBTI Degradation Extraction
A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard
AC strength of a pattern generator
Link Testing: a Survey of Current Trends in Network on Chip
Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests
Circuit Level Concurrent Error Detection in FSMs
An approach to sequential circuit diagnosis based on formal verification techniques
Distributed Test Pattern Generation for Stuck-At Faults in Sequential Circuits
A High-Performance Quadruple-Node-Upset-Tolerant Latch Design and an Algorithm for Tolerance Verification of Hardened Latches
Decoupling Capacitor Estimation and Allocation using Optimization Techniques for Power Supply Noise Reduction in System-on-Chip
Separate I DDQ testing of signal and bias paths in CMOS ICs for defect diagnosis
Efficient Worst-Case Temperature Evaluation for Thermal-Aware Assignment of Real-Time Applications on MPSoCs
High Level Test Economics Advisor (Hi-TEA)
Design and Verification of a SAR ADC SystemVerilog Real Number Model
A parity-preserving multi-input signature analyzer and its application for concurrent checking and BIST
Classification of Activated Faults in the FlexRay-Based Networks
An Efficient Reverse Engineering Hardware Trojan Detector Using Histogram of Oriented Gradients
Redundancy effect on yield of binary tree RAMs
Low-Area Wrapper Cell Design for Hierarchical SoC Testing
Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests
An Efficient Critical Path Tracing Algorithm for Designing High Performance Vlsi Systems
Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test
Fault simulation of linear analog circuits
Reducing Test Time Using an Enhanced RF Loopback
Simulation-based Fault Injection with QEMU for Speeding-up Dependability Analysis of Embedded Software
Custom-Adaptive Kernel Strategies for Gaussian Process Regression in Wafer-Level Modeling and FPGA Delay Analysis
A Near-Threshold Soft Error Resilient 7T SRAM Cell with Low Read Time for 20 nm FinFET Technology
Novel MEMS Piezoresistive Sensor with Hair-Pin Structure to Enhance Tensile and Compressive Sensitivity and Correct Non-Linearity
Cross-PUF Attacks: Targeting FPGA Implementation of Arbiter-PUFs
Synthesis of Sequential Circuits by Redundancy Removal and Retiming
Investigation into the Use of Hybrid Solutions for SigmaDelta A/D Converter Testing
Formal Quantification of the Register Vulnerabilities to Soft Error in RTL Control Paths
Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation
2022 JETTA-TTTC Best Paper Award
Distributed Diagnosis of Interconnections in SoC and MCM Designs
Multi-Threaded Mitigation of Radiation-Induced Soft Errors in Bare-Metal Embedded Systems
Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor
An Automotive CD-Player Electro-Mechanics Fault Simulation Using VHDL-AMS
Four-Port Network Parameters Extraction Method for Partially Depleted SOI with Body-Contact Structure
Fatigue Life Based Study of Electronic Package Mounting Locations on Printed Circuit Boards Subjected to Random Vibration Loads
ACM: An Energy-Efficient Accuracy Configurable Multiplier for Error-Resilient Applications
A BICS for CMOS OpAmps by Monitoring the Supply Current Peak
A decomposition approach for testing large analog networks
Synchronous Full-Scan for Asynchronous Handshake Circuits
Combining Scan Test and Built-in Self Test
Learning-oriented Property Decomposition for Automated Generation of Directed Tests
GPUs Neutron Sensitivity Dependence on Data Type
Optimization of SEU Simulations for SRAM Cells Reliability under Radiation
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs
Adaptive Debug and Diagnosis Without Fault Dictionaries
Detection and Diagnosis of Multi-Fault for through Silicon Vias in 3D IC
Effect of Sizing and Scaling on Power Dissipation and Resilience of an RHBD SRAM Circuit
Exact ordered binary decision diagram size when representing classes of symmetric functions
Design Development and Testing of High Performance Microwave Frequency Up-Converter
Scalability of Globally Asynchronous QCA (Quantum-Dot Cellular Automata) Adder Design
2017 JETTA-TTTC Best Paper Award
Adaptive Modeling of Analog/RF Circuits for Efficient Fault Response Evaluation
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift
The Use of Software Engineering Methods for Efficacious Test Program Creation: A Supportive Evidence Based Case Study
Hardware Obfuscation for IP Protection of DSP Applications
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies
New Boolean Equation for Orthogonalizing of Disjunctive Normal Form based on the Method of Orthogonalizing Difference-Building
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation
Self-Testing Embedded Borden t -UED Code Checkers for t = 2 k q - 1 with q = 2 m - 1
Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification
Design of Self-Testing Checkers for m-out-of-n Codes Using Parallel Counters
Eliminating the Timing Penalty of Scan
Built-in Self Test Based on Multiple On-Chip Signature Checking
Investigation of Silicon Aging Effects in Dopingless PUF for Reliable Security Solution
A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs
Yield fluctuations and defect models
Dynamic Power Supply Current Testing of CMOS SRAMs
On the design of random pattern testable PLA based on weighted random pattern testing
2024 JETTA-TTTC Best Paper Award
A Practical Vector Restoration Technique for Large Sequential Circuits
Test Flow Selection for Stacked Integrated Circuits
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing
Thermal-aware Test Data Compression for System-on-Chip Based on Modified Bitmask Based Methods
2014 JETTA Reviewers
New Method for Determining and Predicting Test Interconnect Pin Current Carrying Capacity
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing
A Comparative Evaluation of Designs for Reliable Memory Systems
Techniques for estimating test length under random test
Using Distortion Shaping Technique to Equalize ADC THD Performance Between ATEs
Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey
Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations
Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost
Soft Fault Diagnosis in Analog Circuits Based on Bispectral Models
Phase Noise Testing of Analog/IF Signals Using Digital ATE: A New Post-Processing Algorithm for Extended Measurement Range
New JETTA Editors, 2006
An Efficient Technique to Detect Stealthy Hardware Trojans Independent of the Trigger Size
MATLAB-Open Source Tool Based Framework for Test Generation for Digital Circuits Using Evolutionary Algorithms
Metric-Driven Verification Methodology with Regression Management
SNF-YOLOv8: A Lightweight PCB Defect Detection Algorithm base on Multiscale Feature Fusion and Attention Scale Sequence Fusion
On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression
Analysis of the Lifecycles of Automotive Resistor Lead in Random Vibration
Instant Test and Repair for TSVs using Differential Signaling
High Performance Static Segment On-Chip Memory for Image Processing Applications
A Survey and Recent Advances: Machine Intelligence in Electronic Testing
Analyzing Vulnerability of Asynchronous Pipeline to Soft Errors: Leveraging Formal Verification
Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications
Incorporating testability considerations in high-level synthesis
Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction
An Analog Checker with Input-Relative Tolerance for Duplicate Signals
Design of Embedded Self-Testing Checkers for t -UED and BUED Codes
Hardware reduction in continuous checksum-based analog checkers: Algorithm and its analysis
A Framework for Automated Detection of Power-related Software Errors in Industrial Verification Processes
A Novel Built-In Self-Repair Approach for Embedded RAMs
Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits
Enhanced Monte Carlo-Based Uncertainty Quantification in Electronic Circuits
A New Testability Calculation Method to Guide RTL Test Generation
Artificial Neural Network Based Prediction Model for IR Drop Measurement in a VLSI Power Delivery Network
IDDQ Testing of Submicron CMOS - by Cooling?
Detection of Delay Faults in Memory Address Decoders
Generation Methodology for Good-Enough Approximate Modules of ATMR
Revisit to Histogram Method for ADC Linearity Test: Examination of Input Signal and Ratio of Input and Sampling Frequencies
Finding Multiple Equivalence-Preserving Transformations in Combinational Circuits through Incremental-SAT
Testability Enhancement for Control-Flow Intensive Behaviors
Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations
Software and Hardware Techniques for SEU Detection in IP Processors
Parametric testing of mixed-signal circuits by ANN processing of transient responses
Behavioral Testability Insertion for Datapath/Controller Circuits
Parameterizable Real Number Models for Mixed-Signal Designs Using SystemVerilog
Integrated Temperature Sensors for On-Line Thermal Monitoring of Microelectronic Structures
IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection
A Java Framework to Specify Faultloads for Fault Injection Campaigns
Test Case Optimization using Machine Learning based Hybrid Meta-Heuristic Approach
Probabilistic fault grading based on activation checking and observability analysis
An Automatic Functional Coverage for Digital Systems Through a Binary Particle Swarm Optimization Algorithm with a Reinitialization Mechanism
Automated Bug Resistant Test Intent with Register Header Database for Optimized Verification
On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up
An Efficient Test Set Construction Scheme for Multiple Missing-Gate Faults in Reversible Circuits
A High Performance SEU Tolerant Latch
A test generation program for sequential circuits
Single Particle Fault Injection Signal Generation Method Using Gaussian Cloud Model
On Chip Signal Generators for Low Overhead ADC BIST
Monomer Control for Error Tolerance in DNA Self-Assembly
A Weighted-Bin Difference Method for Issue Site Identification in Analog and Mixed-Signal Multi-Site Testing
Design considerations for Parallel pseudoRandom Pattern Generators
Fault Detection Structures of the S-boxes and the Inverse S-boxes for the Advanced Encryption Standard
Module Level Weighted Random Patterns
An analytical approach to the partial scan problem
Guest Editorial: Special Issue on Analog, Mixed-Signal, and RF Testing
Detectability Challenges of Bridge Defects in FinFET Based Logic Cells
Enhanced Authentication Using Hybrid PUF with FSM for Protecting IPs of SoC FPGAs
Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs
Developing Inherently Resilient Software Against Soft-Errors Based on Algorithm Level Inherent Features
FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications
Concurrent Error Detection in a Bit-Parallel Systolic Multiplier for Dual Basis of GF(2 m )
Calibrating On-chip Thermal Sensors in Integrated Circuits: A Design-for-Calibration Approach
Checkers' No-Harm Alarms and Design Approaches to Tolerate Them
ADC Multi-Site Test Based on a Pre-test with Digital Input Stimulus
Comparison of Single Event Effect and Space Electrostatic Discharge Effect on FPGA Signal Transmission
A Test Time Theorem and its Applications
Diagnosis of Incipient Faults in Nonlinear Analog Circuits Based on High Order Moment Fractional Transform
An Efficient Wavelet Based Transient Current Test towards Detection of Data Retention Faults in SRAM
Research on the Mechanical Properties of Magnetorheological Damping and the Performance of Microprobe Test Process
Proton Beam Validation of a New Single Event Transient Mitigation Technique
IDDQ testing in CMOS digital ASICs
A Behavioral Model of MEMS Convective Accelerometers for the Evaluation of Design and Calibration Strategies at System Level
A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis
Control and Observation Structure for Analog Circuits with Current Test Data
Diagnosis of Analog and Digital Circuit Faults Using Exponential Deep Learning Neural Network
Learning from Constraints for Formal Property Checking
Survey and Evaluation of Automated Model Generation Techniques for High Level Modeling and High Level Fault Modeling
Exploiting Multi-Phase On-Chip Voltage Regulators as Strong PUF Primitives for Securing IoT
Analog Sinewave Signal Generators for Mixed-Signal Built-in Test Applications
Estiamtion and Correction of Mismatch Errors in Time-Interleaved ADCs
Failure Mechanism and Sampling Frequency Dependency on TID Response of SAR ADCs
Design of an Integrated System for On-line Test and Diagnosis of Rotary Actuators
Logic Locking Based Configurable Obfuscation Cell for Enhanced IC Security
A State Machine Encoding Methodology Against Power Analysis Attacks
The dangers of simplistic delay models
A Fault Tolerant Technique for FPGAs
Counter-based compaction: An analysis for BIST
Process Deviations and Spot Defects: Two Aspects of Test and Test Development for Mixed-Signal Circuits
Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays
Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors
An optimal scheduling algorithm for testing interconnect using boundary scan
Built-In Self-Test Design for the 3D-Stacked Wide-I/O DRAM
The Newsletter of the Test Technology Technical Council of the IEEE Computer Society
Alternate Testing of RF Transceivers Using Optimized Test Stimulus for Accurate Prediction of System Specifications
RTL Test Justification and Propagation Analysis for Modular Designs
Detection and Evaluation of Deterministic Jitter Causes in CP-PLL's Due to Macro Level Faults and Pre-Detection Using Simple Methods
Differential Thermal Testing: An Approach to its Feasibility
Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits
A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis
Finite state machine synthesis with fault tolerant test function
Magnetic In-circuit Testing of Multiple Power and Ground Pins for Open Faults
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family
Sine-Wave Signal Characterization Using Square-Wave and SigmaDelta-Modulation: Application to Mixed-Signal BIST
Performance Efficient and Fault Tolerant Approximate Adder
Power-Driven Routing-Constrained Scan Chain Design
Multi-PVT-Point Analysis and Comparison of Recent Small-Delay Defect Quality Metrics
A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards
Reusing Scan Chains for Test Pattern Decompression
Efficient Realization of Parity Prediction Functions in FPGAs
Erratum to An Algebra of Multiple Faults in RAMs
A class of two-dimensional cellular automata and their applications in random pattern testing
Test strategy planning using economic analysis
Research on the Reliability of Interconnected Solder Joints of Copper Pillars under Random Vibration
Hybrid Fault Simulation for Synchronous Sequential Circuits
Ensembles of Neural Networks for Fault Diagnosis in Analog Circuits
Modeling and Parasitic Extraction of the MM9 Transistor for GHz/THz CMOS RF Circuit Design
On-Line Test of Pin-Constrained Digital Microfluidic Biochips with Connect-5 Structure
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments
Effective march algorithms for testing single-order addressed memories
Initialization of Sequential Circuits and its Application to ATPG
IEEE standard 1149.1-1990 on boundary scan: History, literature survey, and current status
Chiba Scan Delay Fault Testing with Short Test Application Time
Layout-based Single Event Mitigation Techniques for Dynamic Logic Circuits
Embedded System Level Self-Test for Mixed-Signal IO Verification