yusuke1997/dblp-id-title huggingface dataset:
An Analysis of Image Features Extracted by CNNs to Design Classification Models for COVID-19 and Non-COVID-19
A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture
Multi-rate Polyphase DSP and LMS Calibration Schemes for Oversampled ADCs
A modular distributed-arithmetic implementation of the inner product and its application to digital filters
Hardware-Efficient Interpolation-Based QR Decomposition and Lattice Reduction Processor for MIMO-OFDM Receivers
Parallel HEVC Decoding on Multi- and Many-core Architectures - A Power and Performance Analysis
Clustering and DCT Based Color Point Cloud Compression
Partially Constrained Blind Source Separation for Localization of Unknown Sources Exploiting Non-homogeneity of the Head Tissues
Properties of Self-Timed Ring Architectures for Deadlock-Free and Consistent Configuration Reaching Maximum Throughput
Implementation of Six Bit ADC and DAC Using Quantum Dot Gate Non-Volatile Memory
Systolic inner product arrays with automatic word rounding
Nonparametric Regression Modeling with Equiprobable Topographic Maps and Projection Pursuit Learning with Application to PET Image Processing
A Comparison of Single- and Multi-Objective Programming Approaches to Problems with Multiple Design Objectives
A New Sequential Block Partial Update Normalized Least Mean M-Estimate Algorithm and its Convergence Performance Analysis
A Modified Minimum Classification Error (MCE) Training Algorithm for Dimensionality Reduction
Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications
Backpropagation Computation for Training Graph Attention Networks
Filtering and Searching Vector Quantization
Sub-Band Detector for Wind-Induced Noise
Optimum Downlink Power Control of a DS-CDMA System via Convex Programming
Mean Field Approach for Configuring Population Dynamics on a Biohybrid Neuromorphic System
VHDL Design for Real Time Motion Estimation Video Applications
Automatic Artefact Removal from Event-related Potentials via Clustering
Improving Deep Neural Network Based Speech Synthesis through Contextual Feature Parametrization and Multi-Task Learning
Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications
Determining the Geographical Location of Image Scenes based on Object Shadow Lengths
Intelligent AUV Surfacing Control in Network Attack Scenario
Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition
A Model to Detect the Fraud of Electronic Payment Card Transactions Based on Stream Processing in Big Data
Guest Editorial: Special Issue on Embedded Computer Vision
Modelling ARQ for a High-Speed ATM-Based Wireless LAN
Development of Multi-Level Speech based Person Authentication System
Design and Implementation of a Low Complexity VLSI Turbo-Code Decoder Architecture for Low Energy Mobile Wireless Communications
Extending the Lifetime of Nano-Blimps via Dynamic Motor Control
Maximum a Posteriori Estimation of Coupled Hidden Markov Models
Parallel Algorithms Based on the Temporal-Window Method for Non-Alternating 3D-WT over Angiographies Using a Multicomputer
Specification and analysis of self-timed circuits
A LSTM-Based Anomaly Detection Model for Log Analysis
An Embedded Real-Time Surveillance System: Implementation and Evaluation
Temporal Frame Sub-Sampling for Video Object Tracking
Single-channel Dereverberation for Distant-Talking Speech Recognition by Combining Denoising Autoencoder and Temporal Structure Normalization
StreamDrive: a Dynamic Dataflow Framework for Clustered Embedded Architectures
Discovering Biclusters by Iteratively Sorting with Weighted Correlation Coefficient in Gene Expression Data
Guest Editorial: Special Section on Fast Fourier Transform (FFT) Hardware Implementations
A Regular VLSI Architecture of Motion Vector Prediction for Multiple-Standard MPEG-Like Video Codec
The RASSP Program: Origin, Concepts, and Status: An Introduction to the Issue
Parallel and pipelined VLSI implementation of a staged decoder for BCM signals
Independent Component Analysis by Using Joint Cumulants and its Application to Remote Sensing Images
Multiple Composite Hypothesis Testing: A Competitive Approach
A Simple Compressive Sensing Algorithm for Parallel Many-Core Architectures
Performance Analysis of Mobile Multiuser Cooperative Networks with TAS Schemes
System Level Design and Implementation for Region-of-Interest Segmentation
Introducing an Efficient Statistical Model for Automatic Modulation Classification
HHT-Based Security Enhancement Approach with Low Overhead for Coding-Based Reprogramming Protocols in Wireless Sensor Networks
Wireless Communications Transmitter Performance Enhancement Using Advanced Signal Processing Algorithms Running in a Hybrid DSP/FPGA Platform
General Architecture for MPEG-2/H.263/H.264 to H.264 Inter P Frame Video Transcoding
Gait Verification System Through Multiperson Signature Matching for Unobtrusive Biometric Authentication
Efficient Hardware Implementation Architectures for Long Integer Modular Multiplication over General Solinas Prime
A Survey on Pipelined FFT Hardware Architectures
Computing Moments by Prefix Sums
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
Realization of the Contrast Limited Adaptive Histogram Equalization (CLAHE) for Real-Time Image Enhancement
Digit-Serial Pipeline Sorter Architecture
Bayesian Segmentation of Hip and Thigh Muscles in Metal Artifact-Contaminated CT Using Convolutional Neural Network-Enhanced Normalized Metal Artifact Reduction
Priority-driven Coding and Transmission of Progressive JPEG Images for Real-Time Applications
Exploring New Search Algorithms and Hardware for Phylogenetics: RAxML Meets the IBM Cell
A Generic Intelligent Bearing Fault Diagnosis System Using Compact Adaptive 1D CNN Classifier
Design and Implementation of a Polynomial Basis Multiplier Architecture Over GF(2m)
Manifold Learning Based Cross-media Retrieval: A Solution to Media Object Complementary Nature
A Very Efficient Storage Structure for DWT and IDWT Filters
The Rate-Distortion Optimized Compressive Sensing for Image Coding
Nonlinear analog networks for image smoothing and segmentation
Encrypted Biography of Biomedical Image - a Pentalayer Cryptosystem on FPGA
A Dynamic Voltage Scaling Algorithm for Dynamic Workloads
Digit-Serial Complex-Number Multipliers on FPGAs
Depth Estimation and Video Synthesis for 2D to 3D Video Conversion
A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes
Efficient Security Processor for Mobile Applications
VLSI Architecture for MIMO Soft-Input Soft-Output Sphere Detection
Testing of programmable analog neural network chips
Efficient Design of Pruned Convolutional Neural Networks on FPGA
Blind Signal-to-Noise Ratio Estimation of Speech Based on Vector Quantizer Classifiers and Decision Level Fusion
Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications
Fast Low-Complexity Decoders for Low-Rate Polar Codes
Multi-core DSP-based Vector Set Bits Counters/Comparators
Fast Fourier Transforms Using the Complex Logarithmic Number System
A superfast algorithm for single-error correction in rrns and hardware implementation
A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems
Profile Guided Dataflow Transformation for FPGAs and CPUs
A fully pipelined RLS-based array for channel equalization
Signal processing architecture assessment
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores
Bit-level systolic arrays for modular multiplication
AI Based Network and Radio Resource Management in 5G HetNets
Millimeter-Wave Wideband Channel Estimation Using Analog True-Time-Delay Array Under Hardware Impairments
Evaluation of Low-Power Computing when Operating on Subsets of Multicore Processors
Opportunities and Challenges of Digital Signal Processing in Deeply Technology-Scaled Transceivers
A Hardware-Efficient Method for Extracting Statistic Information of Connected Component
Low Power Digital Frequency Conversion Architectures
Hyperchaining for LLVM-Based Binary Translators on the x86-64 Platform
A Systolic, High Speed Architecture for an RSA Cryptosystem
Non-Iterative Hierarchical Registration for Medical Images
A Survey on Deep Learning-Based Vehicular Communication Applications
A System-Level Design & FPGA Implementation for Real-Time Interception & Monitoring the Frequency-Agile Communication Signal
An Ensemble Deep Learning Approach Combining Phenotypic Data and fMRI for ADHD Diagnosis
High-speed 2-D convolution with a custom computing machine
An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems
Color-Aware Instructions for Embedded Superscalar Processors
Data Augmentation Using Spectral Warping for Low Resource Children ASR
Data Model Analysis and Integration Technology Based on Electric Power
Application of Reconfigurable Computing to a High Performance Front-End Radar Signal Processor
Efficient microcoded processor design for fixed rate DFT and FFT
Super Resolution of Multispectral Images using ℓ1 Image Models and Interband Correlations
Editorial: Special Issue on Computing Frontiers
Scenario Selection and Prediction for DVS-Aware Scheduling of Multimedia Applications
A Methodology for Design of Scalable Architectures in Software Radio Networks: a Unified Device and Network Perspective
Integration of Dataflow-Based Heterogeneous Multiprocessor Scheduling Techniques in GNU Radio
Towards Generic Embedded Multiprocessing for RVC-CAL Dataflow Programs
A Mersenne Twister Hardware Implementation for the Monte Carlo Localization Algorithm
Synthesis of Runtime Switchable Pareto Buffers Offering Full Range Fine Grained Energy/Delay Trade-Offs
DOA Estimation for Multiple Sparse Sources with Arbitrarily Arranged Multiple Sensors
A four megabit Dynamic Systolic Associative Memory chip
COD: Diversity-Adaptive Subspace Processing for Multipath Separation and Signal Recovery
An Efficient Software List Sphere Decoder for Polar Codes
Large File Security Outsourcing and Sharing Method Based on Blockchain
EasiTPQ: QoS-Based Topology Control in Wireless Sensor Network
Accelerating Mobile Video: A 64-Bit SIMD Architecture for Handheld Applications
Hardware Accelerators for Iris Localization
Signal Processing and Application of Six-axis Force/Torque Sensor Integrated in Humanoid Robot Foot
An adaptive tracking algorithm for direction finding and array shape estimation in a nonstationary environment
DA-Net: Dual Attention Network for Flood Forecasting
Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch
Synthesis of synchronous communication hardware in a multiprocessor architecture
Port Based Actor Model with Kahn Process Network Model and Decidable Dataflow Model
Learning Sparse Overcomplete Codes for Images
An Efficient VLSI Architecture for the Computation of 1-D Discrete Wavelet Transform
Correction: A Wavelet Optimized Video Copy Detection Using Content Fingerprinting
Computer Vision on the Edge to Reduce Network Bandwidth Consumption and Computing Resources in Multi-view 3D Industrial Inspection without Hidden Surfaces
Buffer and Register Allocation for Memory Space Optimization
Area Efficient Sequential Decimal Fixed-point Multiplier
A programmable floating-point cell for systolic signal processing
Cost Effective VLSI Architectures for Full-Search Block-Matching Motion Estimation Algorithm
Lower and Upper Bounds for Misclassification Probability Based on Renyi's Information
WASP: A WSI Associative String Processor
Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs
Investigation of Weighted Least Squares Methods for Multitarget Tracking with Multisensor Data Fusion
VLSI Implementation of the Multistage Detector for Next Generation Wideband CDMA Receivers
BER-based Power Scheduling in Wireless Sensor Networks
A Bit-Rate Aware Scalable H.264/AVC Deblocking Filter Using Dynamic Partial Reconfiguration
DART - a High Level Software-Defined Radio Platform Model for Developing the Run-Time Controller
Adaptive Learning Based View Synthesis Prediction for Multi-View Video Coding
An Integrated Approach to Image Watermarking and JPEG-2000 Compression
New algorithms for reconfiguring VLSI/WSI arrays
Big Data Architecture for Scalable and Trustful DNS based on Sharded DAG Blockchain
A Multiplication-Free Algorithm and A Parallel Architecture for Affine Transformation
CAL Dataflow Components for an MPEG RVC AVC Baseline Encoder
Framework for Digital Filter Design Optimization (DiFiDOT) using MCM Based Register Minimization Retiming for Noise Removal ECG Filters
Surface Electromyographic Activity of Extrinsic Laryngeal Muscles in Cantonese Tone Production
Agglomerative Learning Algorithms for General Fuzzy Min-Max Neural Network
An Efficient Picture-Rate Up-Converter
On the Stability of Source Separation Algorithms
A Highly Utilized Hardware-Based Merge Mode Estimation with Candidate Level Parallel Execution for High-Efficiency Video Coding
A Novel Design of Software System on Chip for Embedded System
Modeling and Evaluating Non-shared Memory CELL/BE Type Multi-core Architectures for Local Image and Video Processing
Editor's Note: Special Issue on Design and Implementation of Low-Power Transceivers
Mpeg2 Video Encoding in Consumer Electronics
Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs
A Low Power 8 x 8 Direct 2-D DCT Chip Design
Maximum Likelihood Unsupervised Source Separation in Gaussian Noise
Designing an Embedded Video Processing Camera Using a 16-bit Microprocessor for a Surveillance System
A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System
Single Chip Dual-Issue RISC Processor for Real-Time MPEG-2 Software Decoding
Symbolic Time Series Analysis of Temporal Gait Dynamics
Finding Quadratic Schedules for Affine Recurrence Equations Via Nonsmooth Optimization
Multimedia Corpus of In-Car Speech Communication
A Highly Parallel Joint VLSI Architecture for Transforms in H.264/AVC
Automated Segmentation of Cervical Intervertebral Disks from Videofluorography Using a Convolutional Neural Network and its Performance Evaluation
Sample Clock Offset Detection and Correction in the LTE Downlink
Hierarchical Resampling Algorithm and Architecture for Distributed Particle Filters
An Efficient IDCT Processor Design for HDTV Applications
Efficient Reconfigurable Implementation of Canonical and Normal Basis Multipliers Over Galois Fields GF (2 m ) Generated by AOPs
Temperature Minimization and Thermal-Driven Scheduling for Real-Time Periodic Tasks
Algorithm and Architecture of Fully-Parallel Associative Memories Based on Sparse Clustered Networks
Optimization of Big Data Parallel Scheduling Based on Dynamic Clustering Scheduling Algorithm
Acoustic Feature Analysis and Discriminative Modeling of Filled Pauses for Spontaneous Speech Recognition
Guest Editorial: JSPS Special Issue on 2018 IEEE Signal Processing Systems (SiPS) Workshop
Control generation in the design of processor arrays
Determining the minimum iteration period of an algorithm
Bias correction and forward-backward averaging in frequency/DOA tracking problems
Multiplication of complex numbers encoded as polynomials
A Rank Decomposed Statistical Error Compensation Technique for Robust Convolutional Neural Networks in the Near Threshold Voltage Regime
Optimal Speech Intelligibility Improvement for Varying Car Noise Characteristics
Efficient Low-Cost Fault-Localization and Self-Repairing Radix-2 Signed-Digit Adders Applying the Self-Dual Concept
Physical Layer Development Framework for OsmocomBB
Power Efficient Signal Processing for mmWave 5G Systems
An MPEG-4 Renderer for High Quality Video Composition and Texture Mapping
Skip Mode Coding for Nonsquare Prediction Blocks
An Active Contour Algorithm for Continuous-Time Cellular Neural Networks
High Speed Curve Interpolating D/A Converter
A Case Study of Simulation and Performance Evaluationof a SDR Baseband Architecture
Solving the Bottleneck Problem in Bioinformatics Computing: An Architectural Perspective
A Low-Complexity AEPDF-assisted Precoding Scheme for Massive MIMO Systems with Transmit Antenna Correlation
Application of the Bi-CoPaM Method to Five Escherichia Coli Datasets Generated under Various Biological Conditions
Survey of Low-Energy Techniques for Instruction Memory Organisations in Embedded Systems
Design and Implementation of the PAPRICA Parallel Architecture
Context-Preserving Region-Based Contrastive Learning Framework for Ship Detection in SAR
Using simulations of reduced precision arithmetic to design a neuro-microprocessor
Optical Clock Distribution in Electronic Systems
Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design
A Hardware-Efficient Algorithm for Real-Time Computation of Zadoff-Chu Sequences
Message-Passing Programming for Embedded Multicore Signal-Processing Platforms
Differential Time Signaling Data-Link Architecture
Interpolation-Free Fractional-Pixel Motion Estimation Algorithms with Efficient Hardware Implementation
Development of a Modular Real-time Shared-control System for a Smart Wheelchair
Density Peak Clustering Based on Cumulative Nearest Neighbors Degree and Micro Cluster Merging
A Fast Architecture for H.264/AVC Deblocking Filter Using a Clock Cycles Saving Process
A VLSI Implementation of Low Power, Low Data Rate UWB Transceiver for Location and Tracking Applications
An Efficient Method for Evaluating Complex Polynomials
The mapping of linear recurrence equations on regular arrays
Guest Editorial: Special Issue on Recent Advances in Content Analysis for Media Computing
Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions
The NITRDrone Dataset to Address the Challenges for Road Extraction from Aerial Images
Guest Editorial: Special Issue on Computing Frontiers
A Filter Bank Based Approach for Rotation Invariant Fingerprint Recognition
Useful-Skew Clock Routing with Gate Sizing for Low Power Design
Energy Efficient VLSI Architecture for Linear Turbo Equalizer
A QCIF Resolution Binary I/O CNN-UM Chip
iBlock: An Intelligent Decentralised Blockchain-based Pandemic Detection and Assisting System
A General Reconfigurable Architecture for the BLAST Algorithm
High Speed 4-Symbol Arithmetic Encoder Architecture for Embedded Zero Tree-Based Compression
Adaptive Duplicated Filters and Interference Canceller for DS-CDMA Systems
Linear-Time Computation of Indexing Based Stereo Correspondence for Cameras with Automatic Gain Control
Fusion of Map and Sensor Data in a Modern Car Navigation System
Visual Quality Assessment of Video and Image Sequences - A Human-based Approach
Analysis and Reproduction of Facial Expressions for Realistic Communicating Clones
Designing a Posture Analysis System with Hardware Implementation
A High Capacity Spatial Domain Data Hiding Scheme for Medical Images
Editor's Note: Signal Processing for Smart Sensors, Wearables, and IoTs
Software Defined Radio Implementation of CloudRAN GSM Emergency Service
Trend and Challenge on System-on-a-Chip Designs
Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures
A floating-point advanced cordic processor
Developing and Distributing Component-Level VHDL Models
Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design
Parallel algorithms/architectures for neural networks
Bubbles can make self-timed pipelines fast
A Computational Memory Architecture for MPEG-4 Applications with Mobile Devices
Power Analysis of a General Convolution Algorithm Mapped on a Linear Processor Array
Automatic Synthesis of Parsers and Validation of Bitstreams Within the MPEG Reconfigurable Video Coding Framework
Forward and Reverse Converters and Moduli Set Selection in Signed-Digit Residue Number Systems
PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing
Adversarial Data Augmentation Enhanced LSTM Autoencoder for Anomaly Detection in Industrial Pipeline Networks
Modified Low-Complexity Chase Soft-Decision Decoder of Reed-Solomon Codes
Novel Data Mining Analysis Method on Risk Prediction of Type 2 Diabetes
Analog VLSI signal processing: Why, where, and how?
A Low-Power Encoder For Pyramid Vector Quantization of Subband Coefficients
Partitioning Analog and Digital Processing in Mixed-Signal Systems
Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding
Unsupervised Texture Segmentation of Natural Scene Images Using Region-based Markov Random Field
An Emulated Digital CNN Implementation
A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications
Processor design for portable systems
Power-Aware 3D Computer Graphics Rendering
Analyze the Performance of the Cyclic Indexing Schemes for the Wireless Data Broadcast
On recoding in arithmetic algorithms
A Cost-Effective Design for MPEG-2 Audio Decoder with Embedded RISC Core
Putting Queens in Carry Chains, N o̱27
A VLSI neuroprocessor for image restoration using analog computing-based systolic architecture
Content-Based Pseudoscopic View Detection
IMAPCAR: A 100 GOPS In-Vehicle Vision Processor Based on 128 Ring Connected Four-Way VLIW Processing Elements
An Efficient Block Entropy Based Compression Scheme for Systems-on-a-Chip Test Data
Manifold Based Local Classifiers: Linear and Nonlinear Approaches
Hardware/Software co-design with the HMS framework
Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms
Base-Reconfigurable Segmented Logarithmic Quantization and Hardware Design for Deep Neural Networks
An Automated Design Flow for Adaptive Neural Network Hardware Accelerators
Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure
An Evaluation Study of Mobility Support in ZigBee Networks
MOST-Based Design and Scaling of Synaptic Interconnections in VLSI Analog Array Processing CNN Chips
Tools and Techniques for Implementation of Real-time Video Processing Algorithms
Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors
Parabolic Motion-Vector Re-estimation Algorithm for Compressed Video Downscaling
Exploration of Local Variability in Text-Independent Speaker Verification
Aggressive Dynamic Execution of Decoded Traces
Accelerating Image Processing Using Reduced Precision Calculation Convolution Engines
Linear programming for hazard elimination in asynchronous circuits
I/O and computation overlap on SIMD systolic arrays
Real-Time Vision Based Driver Drowsiness Detection Using Partial Least Squares Analysis
Evaluation of a Modular Approach to AES Hardware Architecture and Optimization
Energy Efficiency of Heterogeneous Networks in LTE-Advanced
Bilateral Filters with Adaptive Generalized Kernels Generated via Riemann-Lebesgue Theorem
Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs
Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A Survey
Complex Infomax: Convergence and Approximation of Infomax with Complex Nonlinearities
An Effective Segmentation Method for MRI Images Based on TV-L1 and GVF Model
DSP design tool requirements for embedded systems: A telecommunications industrial perspective
Efficient Systolic Array Mapping of FIR Filters Used in PAM-QAM Modulators
Principle of Learning Metrics for Exploratory Data Analysis
Quantitative Analysis of FPGA-based Database Searching
Echocardiographic Image Sequence Segmentation and Analysis Using Self-Organizing Maps
Semi-Supervised Deep Learning for Multi-Tissue Segmentation from Multi-Contrast MRI
Soft-Decision Error Correction of NAND Flash Memory with a Turbo Product Code
A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility
High-Speed CORDIC Based on an Overlapped Architecture and a Novel sigma-Prediction Method
A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures
A Faddeev Systolic Array for EKF-SLAM and its Arithmetic Data Representation Impact on FPGA
FPGA Implementation of Integer Transform and Quantizer for H.264 Encoder