yusuke1997/dblp-id-title huggingface dataset:
Effects of Copper Plasticity on the Induction of Stress in Silicon from Copper Through-Silicon Vias (TSVs) for 3D Integrated Circuits
Efficient Selective Image Fusion: A PCB Diagnosis Approach and Implementation
Modeling Custom Digital Circuits for Test
Mixed-Signal Circuit Classification in a Pseudo-Random Testing Scheme
An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment
Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs
On the Test and Mitigation of Malfunctions in Low-Power SRAMs
Optimization-based multifrequency test generation for analog circuits
Design for Delay Testability in High-Speed Digital ICs
Selection of Crosstalk-Induced Faults in Enhanced Delay Test
A Built-in-Self-Test Sigma-Delta ADC Prototype
Multi-TAP Controller Architecture for Digital System Chips
Memory Reliability Improvement Based on Maximized Error-Correcting Codes
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations
An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation
ITA: An algorithm for I DDQ testability analysis
An Efficient Algorithm for Optimizing the Test Path of Digital Microfluidic Biochips
Challenges for Semiconductor Test Engineering: A Review Paper
Application of Contactless Testing to PCBs with BGAs and Open Sockets
Design of a C-testable booth multiplier using a realistic fault model
Role of the Pulse Repetition Rate when Assessing Electromagnetic Immunity of Electronic Devices
2013 JETTA-TTTC Best Paper Award
Access Port Protection for Reconfigurable Scan Networks
Maximizing Parallel Testing in an FM Receiver
Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware
Algorithms for IDDQ measurement based diagnosis of bridging faults
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM
Testing the Local Interconnect Resources of SRAM-Based FPGA's
Modified Selective Huffman Coding for Optimization of Test Data Compression, Test Application Time and Area Overhead
DFS-KeyLevel: A Two-Layer Test Scenario Generation Approach for UML Activity Diagram
An Efficient SAT-Based Test Generation Algorithm with GPU Accelerator
A BIST Solution for Frequency Domain Characterization of Analog Circuits
A Unified DFT Approach for BIST and External Test
Fast and Automated Electromigration Analysis for CMOS RF PA Design
Evaluation of Ionizing Radiation Effects on Device Modules Used in Wireless-Based Monitoring Systems
A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors
Repeated Testing Applications for Improving the IC Test Quality to Achieve Zero Defect Product Requirements
Transparent random access memory testing for pattern sensitive faults
MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs
Distributed diagnosis for homogeneous systems
Fault Coverage on RF VCOs and BIST for Wafer Sort Using Peak-to-Peak Voltage Detectors
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Saleh Model and Digital Predistortion for Power Amplifiers in Wireless Communications Using the Third-Order Intercept Point
Analysis of Application of the IDDQ Technique to the Deep Sub-Micron VLSI Testing
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
Novel Self-Timed, Pipelined Clock Scan Architecture
Behavior model of mixed ADC systems
Selective SWIFT-R - A Flexible Software-Based Technique for Soft Error Mitigation in Low-Cost Embedded Systems
Test Technology Newsletter - October 2007
Estimation of RF PA Nonlinearities after Cross-correlating Current and Output Voltage
Error Correcting Strategy for High Speed and High Density Reliable Flash Memories
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy
High Resolution Pulse Propagation Driven Trojan Detection in Digital Systems
Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums
Hard-Fault Detection and Diagnosis During the Application of Model-Based Data Converter Testing
Equivalence Checking and Compaction of n-input Majority Terms Using Implicants of Majority
A Functional Decomposition Method for Redundancy Identification and Test Generation
Bounding fault detection probabilities in combinational circuits
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults
An RTN Variation Tolerant SRAM Screening Test Design with Gaussian Mixtures Approximations of Long-Tail Distributions
Experimental Results of Testing a BIST Σ-Δ ADC on the HOY Wireless Test Platform
Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences
A Self Test Program Design Technique for Embedded DSP Cores
Fault-Aware Dependability Enhancement Techniques for Phase Change Memory
Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System
Low Area FPGA Implementation of AES Architecture with EPRNG for IoT Application
The Comparative and Concurrent Simulation of discrete-event experiments
Smell Detection Agent Optimization Approach to Path Generation in Automated Software Testing
Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model
Erratum to: A Cost-Efficient Self-Configurable BIST Technique for Testing Multiplexer-Based FPGA Interconnect
A Two-Level Power-Grid Model for Transient Current Testing Evaluation
Logic Design Validation via Simulation and Automatic Test Pattern Generation
Self-Checking Voter for High Speed TMR Systems
Test Challenges in Nanometer Technologies
Erratum to: Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection
The optimistic update theorem for path delay testing in sequential circuits
Investigations on the Use of Ensemble Methods for Specification-Oriented Indirect Test of RF Circuits
Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications
Synchronizing sequences and symbolic traversal techniques in test generation
A Probabilistic Approach to Diagnose SETs in Sequential Circuits
Neural Network Guided Spatial Fault Resilience in Array Processors
Functional versus random test generation for sequential circuits
Efficient sensitization of multi-bit-paths for testing embedded modules in synchronous sequential circuits
On Design Validation Using Verification Technology
Automatic Vector Generation Using Constraints and Biasing
Study on Magnetic Probe Calibration in Near-field Measurement System for EMI Application
A Maximum Power Algorithm to Find Frequencies for Aperiodic Clock Testing
A Preliminary Study about SEU Effects on Programmable Interconnections of SRAM-based FPGAs
TBSA: Threshold-Based Simulation Accuracy Method for Fast Analog DC Fault Simulation
A Reliability Statistics Perspective on the Pitfalls of Standard Wafer-Level Electromigration Accelerated Test (SWEAT)
Investigations for Minimum Invasion Digital Only Built-In "Ramp" Based Test Techniques for Charge Pump PLL's
Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure
Low-Cost Specification Based Testing of RF Amplifier Circuits using Oscillation Principles
Production Realization of MTPR Test on Low-Cost ATE for OFDM Based Communication Devices
A test methodology for finite state machines using partial scan design
A Modified Charge Pumping Method for Measuring Interface States Up to the Ghz Range
Method of Implanting Hardware Trojan Based on EHW in Part of Circuit
Test Modules for Enhanced Testability of Single Flux Quantum Integrated Circuits
Analysis and Modeling of Single Event Transient Generation in Standard Combinational Cells
An Exact approach for Complete Test Set Generation of Toffoli-Fredkin-Peres based Reversible Circuits
Some observations from interrupted lifetest of GaInAsP/InP inverted-rib laser diodes
Modeling Feedback Bridging Faults with Non-Zero Resistance
Pre-Silicon Verification Using Multi-FPGA Platforms: A Review
A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect
Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment
IDDQ testing as a component of a test suite: The need for several fault coverage metrics
An Accurate and Cost-Effective Jitter Measurement Technique Using a Single Test Frequency
An ATE Filter Characterization ToolKit Using a Discrete Chirped Excitation Signal as Stimulus
Merging a DSP-Oriented Signal Integrity Technique and SW-Based Fault Handling Mechanisms to Ensure Reliable DSP Systems
Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing
Cell delay fault testing for iterative logic arrays
A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators
Security Extension for IEEE Std 1149.1
A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs
Test Generation for Mixed-Signal Devices Using Signal Flow Graphs
An Analytical Model for Deposited Charge of Single Event Transient (SET) in FinFET
A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms
An Effective Multi-Chip BIST Scheme
Fault Diagnosis of Analog Circuit Based on High-Order Cumulants and Information Fusion
Techniques for Disturb Fault Collapsing
Enhancing Digital VLSI Circuit Debugging with Unified Neighbor aware Graph Neural Network Based Automated Error Detection
Multiple-output parity bit signature for exhaustive testing
Golden-Free Hardware Trojan Detection with High Sensitivity Under Process Noise
Test Generation for Bridging Faults in Reversible Circuits Using Path-Level Expressions
A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency
Wavelet Neural Network Approach for Testing of Switched-Current Circuits
Investigation of Single Event Effects in a Resistive RAM Memory Array by Coupling TCAD and SPICE Simulations
Intrinsic Based Self-healing Adder Design Using Chromosome Reconstruction Algorithm
Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology
Determining Aliasing Probabilities in BIST by Counting Strings
Reliability-Aware Heterogeneous 3D Chip Multiprocessor Design
A New Optimal Test Node Selection Method for Analog Circuit
Diagnosis Method Using DeltaIDDQ Probabilistic Signatures: Theory and Results
Efficient Concurrent Self-Test with Partially Specified Patterns
Investigating and Reducing the Architectural Impact of Transient Faults in Special Function Units for GPUs
Radiation Tolerant SRAM Cell Design in 65nm Technology
On-chip Generation of Sine-wave Summing Digital Signals: an Analytic Study Considering Implementation Constraints
Testability of artificial neural networks: A behavioral approach
A Practical Approach to Single Event Transient Analysis for Highly Complex Design
Quality Determination for Gate Delay Fault Tests Considering Three-State Elements
Contact-Less Near-Field Test of Active Integrated RF Phased Array Antennas
Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems
An Integrated Framework for the Design and Optimization of SOC Test Solutions
Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design
Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation
Leveraging Balanced Logic Gates as Strong PUFs for Securing IoT Against Malicious Attacks
Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short
Test and Testability of a Monolithic MEMS for Magnetic Field Sensing
An advanced diagnostic method for delay faults in combinational faulty circuits
A DfT Strategy for Guaranteeing ReRAM's Quality after Manufacturing
Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths
A Parallel Test Application Method towards Power Reduction
New Editor - 2018
A Simulated Annealing Inspired Test Optimization Method for Enhanced Detection of Highly Critical Faults and Defects
A Functional Verification Methodology Based on Parameter Domains for Efficient Input Stimuli Generation and Coverage Modeling
Quietest: A methodology for selecting IDDQ test vectors
Reusing RTL Assertion Checkers for Verification of SystemC TLM Models
IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors
Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch
Fault-Aware Test Case Prioritization in Software Testing Using Jaya Archimedes Optimization Algorithm
Fault Detection, Diagnosis and Prediction in Electrical Valves Using Self-Organizing Maps
SSB Phase Noise Evaluation of Analog/IF Signals on Standard Digital ATE
Online Testing of MEMS Based on Encoded Stimulus Superposition
A Novel Approach for Analog Circuit Fault Prognostics Based on Improved RVM
FFI4SoC: a Fine-Grained Fault Injection Framework for Assessing Reliability against Soft Error in SoC
Trade-offs in scan path and BIST implementations for RAMs
Impact of Bias Temperature Instability (BTI) Aging Phenomenon on Clock Deskew Buffers
Constrained parity testing
Fault Tolerance Mechanisms for FPGA-Based Regular Expression Matching
Low Cost BIST for Static and Dynamic Testing of ADCs
Testing Multilayer Flexible Wireless Multisensor Platforms
Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy
Self-test of sequential circuits with deterministic test pattern sequences
A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers
An Efficient Logic Equivalence Checker for Industrial Circuits
Scaling of i DDT Test Methods for Random Logic Circuits
Sequential Circuit Test Generation Using a Symbolic/Genetic Hybrid Approach
Fault Detection of Linear Analog Integrated Circuit in Network
BIST Pattern Generators Using Addition and Subtraction Operations
An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation
Sahand: A Software Fault-Prediction Method Using Autoencoder Neural Network and K-Means Algorithm
LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds
Shorts in self-checking circuits
Model for Transient Fault Susceptibility of Combinational Circuits
PCB Defects: A Unified Survey of Trends, Detection Techniques, and Limitations through Systematic Literature Review
An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures
The Integration of On-Line Monitoring and Reconfiguration Functions into a Safety Critical Automotive Electronic Control Unit
Pseudo Functional Path Delay Test through Embedded Memories
Clock Faults Induced Min and Max Delay Violations
Multiple fault analog circuit testing by sensitivity analysis
RTOS Solution for NoC-Based COTS MPSoC Usage in Mixed-Criticality Systems
False Error Vulnerability Study of On-line Soft Error Detection Mechanisms
Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling
A BIST-DFT technique for DC test of analog modules
DVFS Based Error Avoidance Strategy in Wireless Network-on-Chip
New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters
A Fine-Grained Software-Implemented DMA Fault Tolerance for SoC Against Soft Error
Influence of Printed Circuit Board Dynamics on the Fretting Wear of Electronic Connectors: A Dynamic Analysis Approach
Search State Compatibility Based Incremental Learning Framework and Output Deviation Based X-filling for Diagnostic Test Generation
Evaluation of a Two-Tier Adaptive Indirect Test Flow for a Front-End RF Circuit
Design Flow Methodology for Radiation Hardened by Design CMOS Enclosed-Layout-Transistor-Based Standard-Cell Library
Part I: Evaluation for Hardware Trojan Detection Based on Electromagnetic Radiation
Reliability and Defect Tolerance in Metallic Quantum-dot Cellular Automata
A New Test Point Selection Method for Analog Continuous Parameter Fault
Verification Simulation Acceleration Using Code-Perturbation
Research on Analog Integrated Circuit Test Parameter Set Reduction Based on XGBoost
Fault Models and Test Procedures for Flash Memory Disturbances
Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults
FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction
Efficient board interconnect testing using the split boundary scan register
Robust tests for parity trees
Efficient Generation of Stimuli for Functional Verification by Backjumping Across Extended FSMs
An Automatic Software Testing Method to Discover Hard-to-Detect Faults Using Hybrid Olympiad Optimization Algorithm
Low-Cost Strategy for Bus Propagation Delay Reduction
A hierarchical test generation methodology for digital circuits
Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors
Partial scan design of register-transfer level circuits
On Composite Leakage Current Maximization
Dynamic Fault Mitigation for Space Radiation Using Fault Injection and Machine Learning
Automatic Generation of System Level Assertions from Transaction Level Models
Exploiting Behavioral Information in Gate-Level ATPG
A YOLOv9: Deep Learning-based Framework Defect Detection Method for PCBs
On-Line Testing for VLSI - A Compendium of Approaches
Partial scan flip-flop selection by use of empirical testability
A new reconfigurable Test Vector Generator for built-in self-test applications
RTL-Based Functional Test Generation for High Defects Coverage in Digital Systems
Exploring the Limitations of Software-based Techniques in SEE Fault Coverage
Fuzzy optimization models for analog test decisions
Band-Pass Filter Design with Diagnosis Facilities Based on Predictive Techniques
Design and Implementation of an FPGA-Based Data/Timing Formatter
Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults
Using Error Correcting Codes Without Speed Penalty in Embedded Memories: Algorithm, Implementation and Case Study
Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder
The minimum test set problem for circuits with nonreconvergent fanout
Structural Fault Testing of Embedded Cores Using Pipelining
Distributed BIST Architecture to Combat Delay Faults
The Newsletter of Test Technology Council of the IEEE Computer Society
Gate Oxide Short Defect Model in FinFETs
Tipping Point Analysis of Electrical Resistance Data with Early Warning Signals of Failure for Predictive Maintenance
Aging Prediction and Tolerance for the SRAM Memory Cell and Sense Amplifier
Correlation bounds for second-order MAPs with application to queueing network decomposition
A Generalized SBBP/G/1 Queue and its Applications
ASIP tandem queues with Lévy input and consumption
Delay analysis of downlink IP traffic on UMTS mobile networks
A refined mean field approximation of synchronous discrete-time population models
Exploring the Queueing Behaviour of ATM Switches
Distributions of the Interdeparture Times in FCFS and Nonpreemptive Priority MMAP [2]/G [2]/1 Queues
Performance analysis of threshold-based selective drop mechanism for high performance packet switches
Distributed best response dynamics with high playing rates in potential games
Statistical service assurances for applications in utility grid environments
Coalition formation resource sharing games in networks
Guest editor's forewords: Special issue on Valuetools 2017
Using cross-system diversity in heterogeneous networks: Throughput optimization
Performance evaluation of multicast communication in packet-switched networks
Reducing the expenses of geo-distributed data centers with portable containerized modules
Lookahead actions in dispatching to parallel queues
Fitting Mixtures of Exponentials to Long-Tail Distributions to Analyze Network
Parallel algorithms for fitting Markov arrival processes
Modeling and performance analysis of ad hoc broadcasting schemes
An Efficient Two-Stage Iterative Method for the Steady-State Analysis of Markov Regenerative Stochastic Petri Net Models
Bitcoin blockchain dynamics: The selfish-mine strategy in the presence of propagation delay
An open exponential queuing network with limited waiting spaces and losses: A method of approximate analysis
The Foreground-Background queue: A survey
ECOMA-9 - Ninth European conference on computer measurement
An Affinity-Based Dynamic Load Balancing Protocol for Distributed Tansaction Processing Systems
Discrete Bayesian Optimization via Machine Learning
Departure process analysis of the multi-type MMAP[K]/PH[K]/1 FCFS queue
On value functions for FCFS queues with batch arrivals and general cost structures
Analysis of the M/G/1 queue with discriminatory random order service policy
A generalized method of moments for closed queueing networks
Erratum to "A preemptive resume queue with an expiry time for retained service": [Performance Evaluation 54 (2003) 59-74]
Optimal pricing in multi server systems
Fast Parallel Solution of Fixed Point Equations for the Performance Evaluation of Circuit-Switched Networks
An analysis of naming conventions for distributed computer systems
Exploring mixed integer programming reformulations for virtual machine placement with disk anti-colocation constraints
Caching games between Content Providers and Internet Service Providers
On the performance of adaptive TDMA protocols in WDM passive star networks with fixed transmitters and tunable receivers
The impact of load comparison errors on the power-of-d load balancing
On the Arrival Theorem for Queueing Networks Operating Under a Just-in-Time Protocol
Surrogate models for performance evaluation of multi-skill multi-layer overflow loss systems
Distribution of the Delay in Polling Systems in Heavy Traffic
Generalized Worst-Case Bounds for an Homogeneous Multiprocessor Model with Independent Memories - Completion Time Performance Criterion
Bounding Steady-State Availability Models with Group Repair and Phase Type Repair Distributions
A Modelling and Analysis Tool for Discrete Events Systems: Continuous Petri Net
Computing system-time and system-length distributions for MAP/D/1 queue using distributional Little's law
Web prefetching performance metrics: A survey
Bayesian optimization for dynamic pricing and learning
Improved scalability of demand-aware datacenter topologies with minimal route lengths and congestion
Theoretical and experimental evaluation of communication-induced checkpointing protocols in F E and F Lazy-E families
"Pay bursts only once" does not hold for non-FIFO guaranteed rate nodes
Problems Using MD5 with IPv6
PEPA nets: a structured performance modelling formalism
Flow level performance analysis of a multi-service system supporting elastic and adaptive services
A model of transaction blocking in databases
Analysis of Discrete-Time TES/G/1 and TES/D/1-K Queueing Systems
Call packing bound for overflow loss systems
M/G/1 queue with deterministic reneging times
On the large deviations approximation for the stationary distribution of skip-free regulated queueing networks
Cycloid: A constant-degree and lookup-efficient P2P overlay network
Approximate Solution to Multichain Queueing Networks with State Dependent Service Rates
A Hybrid Access Method in a Multiple Access Channel
A new service overlays dimensioning approach based on stochastic geometry
Exploiting channel memory for multiuser wireless scheduling without channel measurement: Capacity regions and algorithms
A Perspective on Queueing Models of Computer Performance
Generalizing window flow control in bivariate network calculus to enable leftover service in the loop
On the interaction of multiple overlay routing
A performance analysis of a discrete-time priority queueing system with correlated arrivals
Analysis of a multi-server retrial queue with search of customers from the orbit
An Equivalent Random Method with hyper-exponential service
Asymptotic performance evaluation of battery swapping and charging station for electric vehicles
Hierarchical beamforming: Resource allocation, fairness and flow level performance
Virtual caching with apportioned objects for mobile virtual reality