yusuke1997/dblp-id-title huggingface dataset:
A Combined Trend Virtual Machine Consolidation Strategy for Cloud Data Centers
The Cost of Developing Large-Scale Software
System Description Languages
The Balanced Hypercube: A Cube-Based System for Fault-Tolerant Applications
On Variable Scope of Parity Protection in Disk Arrays
Optimal Self-Testing Embedded Parity Checkers
Tiler: An Autonomous Region-Based Scheme for SMR Storage
A Means for Achieving a High Degree of Compaction on Scan-Digitized Printed Text
Tight Lower Bounds on the Detection Probabilities of Single Faults at Internal Signal Lines in Combinational Circuits
B71-2 Introduction to Computer Organization
A Transform for NAND Network Design
The CORDIC Algorithm: New Results for Fast VLSI Implementation
Diagnosis of Faults in Modular Trees
Thermistors for the Gradual Application of Heater Voltage to Thermionic Tubes
Optimization of Memory Hierarchies in Multiprogrammed Computer Systems With Fixed Cost Constraint
Utilization Aware Power Management in Reliable and Aggressive Chip Multi Processors
Improved Time and Parallel Processor Bounds for Fortran-Like Loops
Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior
Nonorthogonal Projections for Feature Extraction in Pattern Recognition
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors
Feed-Forward Threshold Logic Nets for Digital Switching and Pattern Recognition
Real-Time Recognition of Spoken Words
A High-Speed Carry Circuit for Binary Adders
Task Scheduling on Adaptive Multi-Core
Associative Algebraic Structures in the Set of Boolean Functions and Some Applications in Automata Theory
"Cool" Load Balancing for High Performance Computing Data Centers
Fault-Tolerant Routing in Multistage Interconnection Networks
Exact Minimization of Binary Decision Diagrams Using Implicit Techniques
Analysis of Backward Congestion Notification with Delay for Enhanced Ethernet Networks
Efficient Design of Self-Checking Checker for any m -Out-of- n Code
Implementation of On-Line Distributed System-Level Diagnosis Theory
Adapting RVR Simulation Techniques for Residual Connectedness Network
Decentralized Task Offloading in Edge Computing: An Offline-to-Online Reinforcement Learning Approach
Comments on "Equational Logic"
Approximate Restoring Dividers Using Inexact Cells and Estimation From Partial Remainders
Comments on "A Note on Base -2 Arithmetic Logic"
Statistical Recognition Functions and the Design of Pattern Recognizers
UPP Graphs and UMFA Networks-Architecture for Parallel Systems
The Microdiagnostics for the IBM System 360 Model 30
Mobile RFID with a High Identification Rate
Low Latency Floating-Point Division and Square Root Unit
Memory-Aware Denial-of-Service Attacks on Shared Cache in Multicore Real-Time Systems
Parallel Sorting in a Ring Network of Processors
A High-Performance Deadlock-Free Multicast Routing Algorithm for K-Ary N-Cubes
Safety Levels-An Efficient Mechanism for Achieving Reliable Broadcasting in Hypercubes
A Stable Basic Logic Circuit
Comments on the Minimization of Stochastic Machines
Error Analysis in the Computer Simulation of Dynamic Systems: Variational Aspects of the Problem
Error Bounds for a Contextual Recognition Procedure
Parallel Hierarchical Subspace Clustering of Categorical Data
Simulation of Nonquiescent Third-Order Systems by a Single Operational Amplifier
Multiconstrained QoS Routing: A Norm Approach
Reliable Loop Topologies for Large Local Computer Networks
Synchronous Sequential Machines: A Modular and Testable Design
A 20 Bit Logarithmic Number System Processor
Design of Reliable Synchronous Sequential Circuits
Towards Controllable Distributed Real-Time Systems with Feasible Utilization Control
Lattice-Based Forward Secure Multi-User Authenticated Searchable Encryption for Cloud Storage Systems
Optimal Realization of Any BPC Permutation on K-Extra-Stage Omega Networks
Cooperating Reduction Machines
Multiplicative Complexity of XOR Based Regular Functions
Embedding of Cycles in Arrangement Graphs
DaemonGuard: Enabling O/S-Orchestrated Fine-Grained Software-Based Selective-Testing in Multi-/Many-Core Microprocessors
Edge Detection in Simple Scenes Using a Priori Information
Adaptive Incentivize for Federated Learning With Cloud-Edge Collaboration Under Multi-Level Information Sharing
On the Minimum Link-Length Rectilinear Spanning Path Problem: Complexity and Algorithms
Self-Adaptive Configuration of Visualization Pipeline Over Wide-Area Networks
A Flexible and Inexpensive Method of Monitoring Program Execution in a Digital Computer
Enhanced EM-Based Malware Detection for IoT Devices Using Clock Frequency Analysis
Serial/Parallel Convolvers
Design and Analysis of a Generalized Architecture for Reconfigurable m-ary Tree Structures
Real-Time Algorithms and Data Management on Illiac IV
Modeling Yield, Cost, and Quality of a Spare-Enhanced Multicore Chip
Dynamic DPU Offloading and Computational Resource Management in Heterogeneous Systems
R70-27 Tree Generating Regular Systems
An Analytic Framework for Detailed Resource Profiling in Large and Parallel Programs and Its Application for Memory Use
Cache Coherence in Intelligent Memory Systems
Theory of Transparent BIST for RAMs
Generalized Pulse Recording
Reliable Real-Time Communication in Cooperative Mobile Applications
On the Inherent Space Complexity of Fast Parallel Multipliers for GF(2/supm/)
Performance and Reliability Evaluation of BSM Broadcasting in DSRC with Multi-Channel Schemes
Introduction to the Special Section on High Performance Memory Systems
Comment on "Negative Radix Conversion"
Distributed Execution of Functional Programs Using Serial Combinators
On the Mapping Problem
CloudGenius: A Hybrid Decision Support Method for Automating the Migration of Web Application Clusters to Public Clouds
Arithmetical Improvement of the Round-Off for Cryptosystems in High-Dimensional Lattices
R68-51 The Design of an Automatic Patching System
On the Implementation of a Two-Dimensional FIR Filter Using a Single Multiplier
Modularity in Design: Skit Registers and Counters Used as System Building Blocks
An Algebraic Method for Designing Multivalued Logic Circuits using Principally Binary Components
Design of Self-Checking Sequential Machines
A Generalization of a Theorem of Quine for Simplifying Truth Functions
Algorithms for Image Component Labeling on SIMD Mesh-Connected Computers
MICROS, A Distributed Operating System for MICRONET, A Reconfigurable Network Computer
Multi-Node Acceleration for Large-Scale GCNs
BlockExplorer: Exploring Blockchain Big Data Via Parallel Processing
Area-Efficient VLSI Layouts for Binary Hypercubes
Increased Memory Performance During Vector Accesses Through the use of Linear Address Transformations
An Occlusion and Noise-Aware Stereo Framework Based on Light Field Imaging for Robust Disparity Estimation
Binary Decision Tree Test Functions
Real-Time I/O Management System with COTS Peripherals
Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Noncoherent Memory Blocks
Model-Driven System Capacity Planning under Workload Burstiness
Information Dissemination in Distributed Systems With Faulty Units
AQUILA: An Equivalence Checking System for Large Sequential Designs
System Modeling and Testing Procedures for Microdiagnostics
Real-Time Related-Key Attack on Full-Round Shadow Designed for IoT Nodes
An Efficient Rounding Boundary Test for {rm pow}(x, y) in Double Precision
$\mathtt{SFPoW}$SFPoW: Constructing Secure and Flexible Proof-of-Work Sidechains for Cross-Chain Interoperability With Wrapped Assets
Multiplicative Division Employing Independent Factors
A Cluster Structure as an Interconnection Network for Large Multimicrocomputer Systems
BIDEC - A Binary-to-Decimal or Decimal-to-Binary Converter
Can Nonlinear Compactors Be Better than Linear Ones
A Queueing Theory-Based Analytic Model of a Distributed Computer Network
A Method for Generating Prime Implicants of a Boolean Expression
Efficient Diminished-1 Modulo 2^n+1 Multipliers
Crash Resilient Communication in Dynamic Networks
Minimum-Congestion Hypergraph Embedding in a Cycle
Minimally Testable Reed-Muller Canonical Forms
Process-Variation-Aware Adaptive Cache Architecture and Management
An Online Mechanism for Resource Allocation and Pricing in Clouds
A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits
Properties of Propagating Structures with Variable Parameter Elements
Minimum-Perimeter Polygons of Digitized Silhouettes
An Extension of the Method of Cohn and Lindaman
Design of Totally Self-Checking Checker for 1-out-of-3 Code
Synthesis of Multivalued Multithreshold Functions for CCD Implementation
Truthful Mechanisms for Competitive Reward-Based Scheduling
Analysis and Optimization of a Queueing Model of a Real-Time Computer Control System
Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems
Experience with Multiprocessor Algorithms
On Fault Identification in Diagnosable Systems
Dual Systolic Architectures for VLSI Digital Signal Processing Systems
Guide to the Length of Buffer Storage Required for Random (Poisson) Input and Constant Output Rates
Isomorphic Strategy for Processor Allocation in k-Ary n-Cube Systems
FiDRL: Flexible Invocation-Based Deep Reinforcement Learning for DVFS Scheduling in Embedded Systems
Optimal Partitioning of Heterogeneous Traffic Sources in Mobile Communications Networks
A Pipeline-Based Genetic Algorithm Accelerator for Time-Critical Processes in Real-Time Systems
On the Analysis and Design of Group Theoretical T-syEC/AUED Codes
Adaptive Model-Based Scheduling in Software Transactional Memory
Power- and Cache-Aware Task Mapping with Dynamic Power Budgeting for Many-Cores
B72-20 Computers in Busines-An Introduction, 2nd ed
Efficient Error Detection for Matrix Multiplication With Systolic Arrays on FPGAs
Accelerating Hyperdimensional Computing on FPGAs by Exploiting Computational Reuse
Search for Editor-in-Chief of IEEE Transactions on Computers
Constructing Optimal Procedures for Testing Series Systems
Optimal Diagnosis of Heterogeneous Systems with Random Faults
A Simplified Definition of Walsh Functions
Efficient Conjunctive Geometric Range Query Over Encrypted Spatial Data With Learned Index
GRASP: A Search Algorithm for Propositional Satisfiability
On Minimally Testable Logic Networks
Evaluating Response Time in a Faulty Distributed Computing System
Waveform Segmentation Through Functional Approximation
Comments on "The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors"
Solutions to the Minimization Problem of Fault-Tolerant Logic Circuits
Deferrable Scheduling for Maintaining Real-Time Data Freshness: Algorithms, Analysis, and Results
On Information Lossless Automata of Finite Order
Comments on "A Nonparametric Partitioning Procedure for Pattern Classification" 1
Correction Games that Teach the Fundamentals of Computer Operation
Countering Power Analysis Attacks UsingReliable and Aggressive Designs
A High Performance and Memory Efficient LU Decomposer on FPGAs
Performance Analysis of a Message-Oriented Knowledge-Base
High-Speed Binary-to-Decimal Conversion
On the Acceleration of Test Generation Algorithms
A General Approach for Generating Natural Random Variables
Systolic Super Summation with Reduced Hardware
Fault-Tolerant Interleaved Memory Systems with Two-Level Redundancy
On Parallel Operations on Hexagonal Arrays
Vector Access Performance in Parallel Memories Using a Skewed Storage Scheme
Design of Self-Checking MOS-LSI Circuits: Application to a Four-Bit Microprocessor
General Models and a Reduction Design Technique for FPGA Switch Box Designs
A Microprocessor-Based Office Image Processing System-An Extension of Work
Correct DDA Register Transfers for Trapezoidal Integration When Solving Nonlinear Equations of the Form y = A y n
On the Minimization of Wordwidth in the Control Memory of a Microprogrammed Digital Computer
A Parity Structure for Large Remotely Located Replicated Data Files
Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs
Sorting by Parallel Insertion on a One-Dimensional Subbus Array
Analysis of the Fork-Join Queue
A New Family of Bridged and Twisted Hypercubes
On the Ordering of Connections for Automatic Wire Routing
Measurement of Pneumoconiosis by Computer
Fully Interconnecting Multiple Computers with Pipelined Sorting Nets
Tunable and Energy Efficient Bus Encoding Techniques
A Design Procedure for Radiation Hardening Certain NOR Gate Logic Circuits
Improved Methods of Maximum a Posteriori Restoration
Minimization of Logic Networks Under a Generalized Cost Function
Generating Robust DNN With Resistance to Bit-Flip Based Adversarial Weight Attack
DC-PCM: Mitigating PCM Write Disturbance with Low Performance Overhead by Using Detection Cells
Computing Display Conflicts in String Visualization
Performance Analysis of Real-Time Software Supporting Fault-Tolerant Operation
Enhanced Cluster k-Ary n-Cube, A Fault-Tolerant Multiprocessor
On the Multicast Lifetime of WANETs with Multibeam Antennas: Formulation, Algorithms, and Analysis
On Generating Multipliers for a Cellular Fast Fourier Transform Processor
Performance of Cooperative Loosely Coupled Microprocessor Architectures in an Interactive Data Base Task
Mutually Aware Prefetcher and On-Chip Network Designs for Multi-Cores
Joint Optimization of Task Scheduling and Image Placement in Fog Computing Supported Software-Defined Embedded System
Note on "Solution of Nonlinear Equations"
Accelerating GNN Training by Adapting Large Graphs to Distributed Heterogeneous Architectures
DVM: A Big Virtual Machine for Cloud Computing
Correction [to "An approach to single-threshold-element synthesis"]
Comparison between Binary and Decimal Floating-Point Numbers
Minimization of Switching Functions - A Fast Technique
Generation of Fault Tests for Linear Logic Networks
R68-41 Development of Executive Routines, Both Hardware and Software
Realization of an Arbitrary Switching Function with a Two-Level Network of Threshold and Parity Elements
Unequal Error Protection for Streaming Media Based on Rateless Codes
High-Performance Low-Power Left-to-Right Array Multiplier Design
On Proving Sequential Machine Designs
Efficient Data Gathering with Mobile Collectors and Space-Division Multiple Access Technique in Wireless Sensor Networks
Routing Multiterminal Nets Around a Rectangle
Error Detection Process - Model, Design, and Its Impact on Computer Performance
Discrete Basis and Computation of Elementary Functions
A Multilayer Iterative Circuit Computer
On the Design of Cost-Tables for Realizing Multiple-Valued Circuits
Using Decision Trees to Derive the Complement of a Binary Function with Multiple-Valued Inputs
A Programmed Algorithm for Assigning Internal Codes to Sequential Machines
Scalable Byzantine Consensus via Hardware-Assisted Secret Sharing
Per-Operation Reusability Based Allocation and Migration Policy for Hybrid Cache
Short-Memory Scalar Multiplication for Koblitz Curves
Cascade Realization of 3-Input 3-Output Conservative Logic Circuits
Utilization of the t* Partial Switching Properties of Ferroelectrics in Memory Devices
AdaptMD: Balancing Space and Performance in NUMA Architectures With Adaptive Memory Deduplication
Efficient Rule Engine for Smart Building Systems
The IBM 705 EDPM Memory System
Cipher Instruction Search Attack on the Bus-Encryption Security Microcontroller DS5002FP
Gem5Tune: A Parameter Auto-Tuning Framework for Gem5 Simulator to Reduce Errors
Functional Level Primitives in Test Generation
Cyclebite: Extracting Task Graphs From Unstructured Compute-Programs
Error Correcting Codes over Z_{2^m} for Algorithm Based Fault Tolerance
Modular LSI Control Logic Design with Error Detection
Design, Implementation, and Evaluation of a QoS-Aware Real-Time Embedded Database
On the Complexity of Sorting in Magnetic Bubble Memory Systems
Hardware Starting Approximation Method and Its Application to the Square Root Operation
Algorithmic Aspects of Hardware/Software Partitioning: 1D Search Algorithms
A New Hierarchical Data Cache Architecture for iSCSI Storage Server
Design and Implementation of Efficient Message Scheduling for Controller Area Network
A Note on the Remarkable Memory of Man
An Efficient Algorithm for Sequential Circuit Test Generation
Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control
Higher Radix Square Root with Prescaling
A Routing Algorithm for Signal Processing Networks
A Gaussian Noise Generator for Hardware-Based Simulations
A Current Mode, Parallel, Two-Rail Code Checker
Parallel CRC Realization
WOLF: Weight-Level OutLier and Fault Integration for Reliable LLM Deployment
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m)
Reliability-Aware Speedup Models for Parallel Applications with Coordinated Checkpointing/Restart
A Lightweight and Cooperative Multifactor Considered File Replication Method in Structured P2P Systems
The Logic Machine: A Modular Computer Design System
An improved reading system for magnetically recorded digital data
Design and Evaluation of a Window-Consistent Replication Service
Lazy Arithmetic
Swarm Intelligence Based File Replication and Consistency Maintenance in Structured P2P File Sharing Systems
A Simulative Study of Correlated Error Propagation in Various Finite-Precision Arithmetics
Software Multiplication Using Gaussian Normal Bases
Replication Cache: A Small Fully Associative Cache to Improve Data Cache Reliability
Worst-Case Considerations in Designing Logical Circuits
An Efficient Reconfiguration Algorithm for Degradable VLSI/WSI Arrays
Smoothing of Data by Least Squares Procedures and by Filtering
SEC-DED Nonbinary Code for Fault-Torelant Byte-Organized Memory Implemented with Quaternary Logic
Class-Based Decompressor Design for Compressed Instruction Memory in Embedded Processors
On the Testability of One-Dimensional ILA's for Multiple Sequential Faults
Thread Partitioning and Value Prediction for Exploiting Speculative Thread-Level Parallelism
Review of Electronic Computer Progress During 1954
On Data Center Network Architectures for Interconnecting Dual-Port Servers
An Efficient CRT-Based Bit-Parallel Multiplier for Special Pentanomials
A Technique for Generating Specialized Gray Codes
A New Algorithm for Multiplication in Finite Fields
Low Complexity Multiplication in a Finite Field Using Ring Representation
Satellite Packet Switching with Global Assignments and Batch Poisson Arrivals
Test Scheduling in High Performance VLSI System Implementations
Towards a New Theory of Sequential Switching Networks
Hyper-Real-Time Ice Simulation and Modeling Using GPGPU
An On-Chip Compare/Steer Bubble Sorter
Characteristics of a High-Speed Multipath Core for a Coincident-Current Memory
Estimation of Classification Error
On Polynomial-Time Testable Combinational Circuits
Pulse Generator and High-Speed Memory Circuit
A Comparative Study of System-Level Energy Management Methods for Fault-Tolerant Hard Real-Time Systems
A Formally Verified Sorting Certifier
A Study of Trigger Machines
Deadlock Verification of Cache Coherence Protocols and Communication Fabrics
Improving Disk Performance Via Latency Reduction
Better Circuits for Binary Polynomial Multiplication
Support for Recovery in Mobile Systems
COALA: A Compiler-Assisted Adaptive Library Routines Allocation Framework for Heterogeneous Systems
A Mutation-Enabled Proactive Defense Against Service-Oriented Man-in-The-Middle Attack in Kubernetes
Figure of Merit for Fault-Tolerant Space Computers
Reconfigurable Instruction-Based Multicore Parallel Convolution and Its Application in Real-Time Template Matching
On r-th Root Extraction Algorithm in 𝔽 q for q≍lr s +1;(mod; r s+1 ) with 0<l<r and Small s
Traffic Routing for Multicomputer Networks with Virtual Cut-Through Capability
Improving Flash Wear-Leveling by Proactively Moving Static Data
WICI: An Efficient Hybrid Routing Scheme for Scalable and Hierarchical Networks
Information Leakage Attacks Exploiting Cache Replacement in Commercial Processors
Parallel Sparse Matrix Solution for Circuit Simulation on FPGAs
A Novel Covert Timing Channel Based on Bitcoin Messages
Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs
Temperature-Aware DVFS for Hard Real-Time Applications on Multicore Processors
An Analysis of Instruction-Fetching Strategies in Pipelined Computers
Measuring and Optimizing CORBA Latency and Scalability Over High-Speed Networks
Functional Transformation in Simplification of Multivalued Switching Functions
Achieving DRAM-Like PCM by Trading Off Capacity for Latency
Symbol Error-Correcting Codes for Computer Memory Systems
SplitDB: Closing the Performance Gap for LSM-Tree-Based Key-Value Stores
Design and Analysis of Arbitration Protocols
Hazards in Asynchronous Sequential Circuits
Design and Analysis of a Self-Timed Duplex Communication System
Strategies for Managing the Register File in RISC
Calculation of Integrated Circuit Yields
Reconfigurable Data Planes for Scalable Network Virtualization
Meaningful Special Classes of Ternary Logic Functions - Regular Ternary Logic Functions and Ternary Majority Functions
March Test Generation Revealed
Multi-Granularity Locality-Sensitive Bloom Filter
Desgin and Performance Analysis of Load-Distributing Fault-Tolerant Network
Sublogarithmic Deterministic Selection on Arrays with a Reconfigurable Optical Bus
A Data Structure for Circular String Analysis and Visualization
An Asynchronous, Distributed Flow Control Algorithm for Rate Allocation in Computer Networks
The Design, Analysis and Simulation of a Fault-Tolerant Interconnection Network Supporting the Fetch-and-Add Primitive
A high-speed correlator
ALV: A New Data Redistribution Approach to RAID-5 Scaling
A Transistorized Four-Quadrant Time-Division Multiplier with an Accuracy of 0.1 Per Cent
Exploring and Exploiting the Multilevel Parallelism Inside SSDs for Improved Performance and Endurance
Comments on "On the Definition and Generation of Walsh Functions"
Provably Sublinear Point Multiplication on Koblitz Curves and Its Hardware Implementation
Balanced Modular Addition for the Moduli Set $ \{2^{q},2^{q}\mp 1,2^{2q}+1\}${2q,2q∓1,22q+1} via Moduli-($ 2^{q}\mp \sqrt{-1}$2q∓-1) Adders
SUGAR: Efficient Subgraph-Level Training via Resource-Aware Graph Partitioning
The Binary Tree as an Interconnection Network: Applications to Multiprocessor Systems and VLSI
R68-30 Monte Carlo Solution of Partial Differential Equations Using a Hybrid Computer
Generation of High Quality Tests for Robustly Untestable Path Delay Faults
A Microcomputer with a Shift-Register Memory
Analysis of Fractional Window Recoding Methods and Their Application to Elliptic Curve Cryptosystems
Effective Runtime Management of Tasks and Priorities in GNU OpenMP Applications
On Universal Logic Primitives
Algorithms for Modeling a Class of Single Timing Faults in Communication Protocols
Minimization of AND-EXOR Expressions Using Rewrite Rules
An Interleaving Structure for Guaranteed QoS in Real-Time Broadcasting Systems
An Algorithm for Testing Random Access Memories
A Note on Synchronizer or Interlock Maloperation
A Partial Scan Method for Sequential Circuits with Feedback
Effect of Fan-In and Fan-Out Limitations on the Value of Computer Circuits
Multiple-Valued Logic - Its Status and Its Future
Binary Search in a Multiprocessing Environment
Coordinated Power and Performance Guarantee with Fuzzy MIMO Control in Virtualized Server Clusters
Error Analysis of Two-Dimensional Recursive Digital Filters Employing Floating-Point Arithmetic
Rapid Prototyping and Evaluation of Intelligence Functions of Active Storage Devices
Inner Product Computers
Theoretical and Experimental Behavior of Synchronizers Operating in the Metastable Region
An Optimization Technique for the Design of Multiple Valued PLA's
Expected-Value Analysis of Two Single Fault Diagnosis Algorithms
Transistorized Multiplier and Divider and Its Applications
Vulnerability of Network Mechanisms to Sophisticated DDoS Attacks
On the Height of Height-Balanced Trees
Cache Hierarchy-Aware Query Mapping on Emerging Multicore Architectures
Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation