yusuke1997/dblp-id-title huggingface dataset:
Characterization of Fixed and Reconfigurable Multi-Core Devices for Application Acceleration
A Framework for Evaluating and Optimizing FPGA-Based SoCs for Aerospace Computing
GROK-LAB: Generating Real On-chip Knowledge for Intra-cluster Delays Using Timing Extraction
Introduction to the FPL 2021 Special Section
Elliptic Curve Cryptography on FPGA for Low-Power Applications
A comprehensive performance analysis of virtual routers on FPGA
Algorithm-hardware Co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA
Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs
Evaluation of Random Delay Insertion against DPA on FPGAs
Reconfiguration and Communication-Aware Task Scheduling for High-Performance Reconfigurable Computing
RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm
Virtualizable hardware/software design infrastructure for dynamically partially reconfigurable systems
Introduction to the Special Section on Security in FPGA-accelerated Cloud and Datacenters
Placement and Floorplanning in Dynamically Reconfigurable FPGAs
DFlows: A Flow-Based Programming Approach for a Polyglot Design-Space Exploration Framework
Introduction to the Special Section on FPGA 2023
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators
A Survey of Processing Systems for Phylogenetics and Population Genetics
FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-level Synthesis
Perfecto: A systemc-based design-space exploration framework for dynamically reconfigurable architectures
NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs
FOS: A Modular FPGA Operating System for Dynamic Workloads
An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems
A Scalable Many-core Overlay Architecture on an HBM2-enabled Multi-Die FPGA
Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis
Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models
Compressing Neural Networks using Learnable 1D Non-Linear Functions
Exploiting HBM on FPGAs for Data Processing
A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme
Introduction to special section FPGA 2009
A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core
Partitioning and Scheduling with Module Merging on Dynamic Partial Reconfigurable FPGAs
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators
HLPerf: Demystifying the Performance of HLS-based Graph Neural Networks with Dataflow Architectures
Particle graphics on reconfigurable hardware
General-Purpose Computing with Soft GPUs on FPGAs
PIMap: A Flexible Framework for Improving LUT-Based Technology Mapping via Parallelized Iterative Optimization
High-Throughput TRNG Design with Novelty Adjustable TDC Based on STR
Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures
RIFFA 2.1: A Reusable Integration Framework for FPGA Accelerators
Introduction to the Special Issue on FPT 2021
CORDIC-Based Enhanced Systolic Array Architecture for QR Decomposition
Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units
On the trade-off between power and flexibility of FPGA clock networks
JITPR: A framework for supporting fast application's implementation onto FPGAs
ExHiPR: Extended High-Level Partial Reconfiguration for Fast Incremental FPGA Compilation
Value State Flow Graph: A Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware
Fantastic Circuits and Where to Find Them - A Holistic ILP Formulation for Model-Based Hardware Design
Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators
A Partitioned CAM Architecture with FPGA Acceleration for Binary Descriptor Matching
RD-FAXID: Ransomware Detection with FPGA-Accelerated XGBoost
Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods
High-Level Abstractions and Modular Debugging for FPGA Design Validation
Rethinking Embedded Blocks for Machine Learning Applications
ODoST: Automatic Hardware Acceleration for Biomedical Model Integration
Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation
Low-Overhead FPGA Middleware for Application Portability and Productivity
Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform
Toward Software-like Debugging for FPGAs via Checkpointing and Transaction-based Co-Simulation
Test compression for dynamically reconfigurable processors
Multi-Tenant Cloud FPGA: A Survey on Security, Trust, and Privacy
Bandwidth Compression of Floating-Point Numerical Data Streams for FPGA-Based High-Performance Computing
TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA
Automated Real-Time Analysis of Streaming Big and Dense Data on Reconfigurable Platforms
Introduction to the Special Issue on the 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'12)
AutoScaleDSE: A Scalable Design Space Exploration Engine for High-Level Synthesis
Statistical Timing and Power Optimization of Architecture and Device for FPGAs
BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining
Design Space Exploration of Galois and Fibonacci Configuration Based on Espresso Stream Cipher
On the Impact of Replacing Low-Speed Configuration Buses on FPGAs with the Chip's Internal Configuration Infrastructure
Composing Multi-Ported Memories on FPGAs
Exploiting FPGA Block Memories for Protected Cryptographic Implementations
An Application Development Framework for ARISE Reconfigurable Processors
Guest Editorial ARC 2014
CoNFV: A Heterogeneous Platform for Scalable Network Function Virtualization
Turn on, Tune in, and Listen up: Maximizing Side-Channel Recovery in Cross-Platform Time-to-Digital Converters
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
Coordination of Independent Loops in Self-Adaptive Systems
QUEKUF: An FPGA Union Find Decoder for Quantum Error Correction on the Toric Code
The iDEA DSP Block-Based Soft Processor for FPGAs
Graph Minor Approach for Application Mapping on CGRAs
Analysis of Fixed, Reconfigurable, and Hybrid Devices with Computational, Memory, I/O, & Realizable-Utilization Metrics
Searching for Transient Pulses with the ETA Radio Telescope
Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs
A SDM-TDM-Based Circuit-Switched Router for On-Chip Networks
Hardware Optimizations of Fruit-80 Stream Cipher: Smaller than Grain
Dynamic Power and Thermal Management of NoC-Based Heterogeneous MPSoCs
Introduction to Special Section on FPGA 2020
A Computation of the Ninth Dedekind Number Using FPGA Supercomputing
Reconfigurable Framework for Resilient Semantic Segmentation for Space Applications
DVHetero: A Framework for Designing and Validating Heterogeneous SoC with RISC-V Processor and CGRA
Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays
Implementing Curve25519 for Side-Channel-Protected Elliptic Curve Cryptography
Exploiting FPGA-Aware Merging of Custom Instructions for Runtime Reconfiguration
Compact and On-the-Fly Secure Dynamic Reconfiguration for Volatile FPGAs
SARFUM: Security Architecture for Remote FPGA Update and Monitoring
AIgean : An Open Framework for Deploying Machine Learning on Heterogeneous Clusters
Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs
Design and analysis of adaptive processor
Introduction to the Special Section on FCCM 2022
XVDPU: A High-Performance CNN Accelerator on the Versal Platform Powered by the AI Engine
Design, Calibration, and Evaluation of Real-time Waveform Matching on an FPGA-based Digitizer at 10 GS/s
Throughput-Optimized FPGA Accelerator for Deep Convolutional Neural Networks
A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation for Dense Matrices
Self-Reconfigurable Constant Multiplier for FPGA
Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud
Stratix 10 NX Architecture
Dynamic Defragmentation of Reconfigurable Devices
DSPs, BRAMs, and a Pinch of Logic: Extended Recipes for AES on FPGAs
NCBI BLASTP on High-Performance Reconfigurable Computing Systems
Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration
Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow
An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures
ARC 2014: A Multidimensional FPGA-Based Parallel DBSCAN Architecture
WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging
A Scalable Systolic Accelerator for Estimation of the Spectral Correlation Density Function and Its FPGA Implementation
A Hardware Accelerator for the Semi-Global Matching Stereo Algorithm: An Efficient Implementation for the Stratix V and Zynq UltraScale+ FPGA Technology
Static and Dynamic Memory Footprint Reduction for FPGA Routing Algorithms
VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling
Toward FPGA Intellectual Property Encryption from Netlist to Bitstream
Approximate Constant-Coefficient Multiplication Using Hybrid Binary-Unary Computing for FPGAs
Accelerating In-memory Database Functionality with FPGAs
FPGA-Array with Bandwidth-Reduction Mechanism for Scalable and Power-Efficient Numerical Simulations Based on Finite Difference Methods
Performance of partial reconfiguration in FPGA systems: A survey and a cost model
The Future of FPGA Acceleration in Datacenters and the Cloud
Parallelizing Data Processing on FPGAs with Shifter Lists
Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs
FPGA Acceleration of RankBoost in Web Search Engines
Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System
SCF: A Framework for Task-Level Coordination in Reconfigurable, Heterogeneous Systems
Improving the Robustness of Ring Oscillator TRNGs
Automation Schemes for FPGA Implementation of Wave-Pipelined Circuits
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components
Reconfigurable Fault Tolerance: A Comprehensive Framework for Reliable and Adaptive FPGA-Based Space Computing
Guest Editorial FPL 2013
Domain-Specific Optimization of Signal Recognition Targeting FPGAs
Remote FPGA Lab for Enhancing Learning of Digital Systems
Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms
Choose-your-own-adventure routing: Lightweight load-time defect avoidance
Application-specific signatures for transactional memory in soft processors
Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference
Voltage Sensor Implementations for Remote Power Attacks on FPGAs
A Flexible SoC and Its Methodology for Parser-Based Applications
Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems
Introduction to Special Issue on FPGAs in Data Centers, Part II
An analytical model for multilevel performance prediction of Multi-FPGA systems
Program-Invariant Checking for Soft-Error Detection using Reconfigurable Hardware
Accelerating FPGA Routing Through Algorithmic Enhancements and Connection-aware Parallelization
Dependency Graph-based High-level Synthesis for Maximum Instruction Parallelism
Reducing the Performance Gap between Soft Scalar CPUs and Custom Hardware with TILT
NASCENT2: Generic Near-Storage Sort Accelerator for Data Analytics on SmartSSD
Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure
A Parallel Sliding-Window Generator for High-Performance Digital-Signal Processing on FPGAs
Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement
FINN- R : An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks
FPGA-Based Dynamically Reconfigurable SQL Query Processing
Floating-Point Exponentiation Units for Reconfigurable Computing
Exact and Practical Modulo Scheduling for High-Level Synthesis
An Analytical Model for Evaluating Static Power of Homogeneous FPGA Architectures
FDRA: A Framework for a Dynamically Reconfigurable Accelerator Supporting Multi-Level Parallelism
An OpenGL Compliant Hardware Implementation of a Graphic Processing Unit Using Field Programmable Gate Array-System on Chip Technology
FPGA Implementation of a Special-Purpose VLIW Structure for Double-Precision Elementary Function
BurstZ+: Eliminating The Communication Bottleneck of Scientific Computing Accelerators via Accelerated Compression
High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator
Improving Fault Tolerance for FPGA SoCs through Post-Radiation Design Analysis
Guest Editorial ARC 2009
Optimized System-on-Chip Integration of a Programmable ECC Coprocessor
Generating Efficient Context-Switch Capable Circuits through Autonomous Design Flow
Coarse-Grained Architecture for Fingerprint Matching
Benefits of Adding Hardware Support for Broadcast and Reduce Operations in MPSoC Applications
DONGLE 2.0: Direct FPGA-Orchestrated NVMe Storage for HLS
An All-digital Compute-in-memory FPGA Architecture for Deep Learning Acceleration
A Real-Time Deep Learning OFDM Receiver
CGRA-EAM - Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures
On the exploitation of a high-throughput SHA-256 FPGA design for HMAC
LW-GCN: A Lightweight FPGA-based Graph Convolutional Network Accelerator
VTR 7.0: Next Generation Architecture and CAD System for FPGAs
A Survey on Architectures, Hardware Acceleration and Challenges for In-Network Computing
AxOMaP : Designing FPGA-based Approximate Arithmetic Operators using Mathematical Programming
Eciton: Very Low-power Recurrent Neural Network Accelerator for Real-time Inference at the Edge
BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization
FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?
Secure Extension of FPGA General Purpose Processors for Symmetric Key Cryptography with Partial Reconfiguration Capabilities
Reconfigurable Framework for Environmentally Adaptive Resilience in Hybrid Space Systems
An Enhanced Adaptive Recoding Rotation CORDIC
Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication
In-Circuit Debugging with Dynamic Reconfiguration of FPGA Interconnects
Imprecise Datapath Design: An Overclocking Approach
High-Performance Quasi-Monte Carlo Financial Simulation: FPGA vs. GPP vs. GPU
Practical Model Checking on FPGAs
Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns
An Efficient Memory Partitioning Approach for Multi-Pattern Data Access via Data Reuse
Adaptive Selection and Clustering of Partial Reconfiguration Modules for Modern FPGA Design Flow
An Approach for Solving Large SAT Problems on FPGA
Introduction to the special section on 19th reconfigurable architectures workshop (RAW 2012)
VTR 9: Open-Source CAD for Fabric and Beyond FPGA Architecture Exploration
Compressor tree synthesis on commercial high-performance FPGAs
Quick-Div: Rethinking Integer Divider Design for FPGA-based Soft-processors
A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses
GraVF-M: Graph Processing System Generation for Multi-FPGA Platforms
Memory Interface Design for 3D Stencil Kernels on a Massively Parallel Memory System
High-Speed Hardware Partition Generation
Design and Evaluation of a Tunable PUF Architecture for FPGAs
Topgun: An ECC Accelerator for Private Set Intersection
Microkernel Architecture and Hardware Abstraction Layer of a Reliable Reconfigurable Real-Time Operating System (R3TOS)
Optimizing Soft Vector Processing in FPGA-Based Embedded Systems
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design
Introduction to Special Section on FPT'20
COFFE 2: Automatic Modelling and Optimization of Complex and Heterogeneous FPGA Architectures
Improving Loop Parallelization by a Combination of Static and Dynamic Analyses in HLS
A Novel Multicontext Coarse-Grained Reconfigurable Architecture (CGRA) For Accelerating Column-Oriented Databases
Hardware-Accelerated RNA Secondary-Structure Alignment
RAW 2014: Random Number Generators on FPGAs
Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation
High-performance and Configurable SW/HW Co-design of Post-quantum Signature CRYSTALS-Dilithium
Packing Techniques for Virtex-5 FPGAs
Dynamic Energy, Performance, and Accuracy Optimization and Management Using Automatically Generated Constraints for Separable 2D FIR Filtering for Digital Video Processing
Hardware-accelerated Real-time Drift-awareness for Robust Deep Learning on Wireless RF Data
Fast and Cycle-Accurate Emulation of Large-Scale Networks-on-Chip Using a Single FPGA
A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric
SPDFA: A Novel Dataflow Fusion Sparse Deep Neural Network Accelerator
Strega: An HTTP Server for FPGAs
A Hardware Design Framework for Computer Vision Models Based on Reconfigurable Devices
HopliteBuf: Network Calculus-Based Design of FPGA NoCs with Provably Stall-Free FIFOs
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs
A Design Flow Engine for the Support of Customized Dynamic High Level Synthesis Flows
Parallel Unary Computing Based on Function Derivatives
Design of Distributed Reconfigurable Robotics Systems with ReconROS
Physical Security Evaluation of the Bitstream Encryption Mechanism of Altera Stratix II and Stratix III FPGAs
Graph-Based Approaches to Placement of Processing Element Networks on FPGAs for Physical Model Simulation
Median Filters on FPGAs for Infinite Data and Large, Rectangular Windows
Optimizing FPGA Performance, Power, and Dependability with Linear Programming
A Performance-Oriented Algorithm with Consideration on Communication Cost for Dynamically Reconfigurable FPGA Partitioning
Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing
Introduction to the Special Section on FPL 2020
Note from the TRETS EiC about the new Journal-first track in FPT'21
ACE-GCN: A Fast Data-driven FPGA Accelerator for GCN Embedding
Introduction to the Special Issue ARC'08
A Reconfigurable Parallel Hardware Implementation of the Self-Tuning Regulator
Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow
Distributed Inference over Decision Tree Ensembles on Clusters of FPGAs
Introduction to the Special Issue on FPGA-based Embedded Systems for Industrial and IoT Applications
An Optimized Hardware Architecture of a Multivariate Gaussian Random Number Generator
CollectiveHLS: A Collaborative Approach to High-Level Synthesis Design Optimization
CTScan: A CGRA-based Platform for the Emulation of Power Side-Channel Attacks on Edge CPUs
RIPL: A Parallel Image Processing Language for FPGAs
The Open-source DeLiBA2 Hardware/Software Framework for Distributed Storage Accelerators
FPGA-Based Sparse Matrix Multiplication Accelerators: From State-of-the-Art to Future Opportunities
Guest Editors' Introduction to Security in Reconfigurable Systems Design
Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module
Introduction to Special Section on FCCM 2019
Enabling Adaptive Techniques in Heterogeneous MPSoCs Based on Virtualization
FiberFlex: Real-time FPGA-based Intelligent and Distributed Fiber Sensor System for Pedestrian Recognition
Near-memory Computing on FPGAs with 3D-stacked Memories: Applications, Architectures, and Optimizations
Detailed Placement for Dedicated LUT-Level FPGA Interconnect
A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs
Codesign of Reactor-Oriented Hardware and Software for Cyber-Physical Systems
SATTA: A Self-Adaptive Temperature-Based TDF Awareness Methodology for Dynamically Reconfigurable FPGAs
ReDCrypt: Real-Time Privacy-Preserving Deep Learning Inference in Clouds Using FPGAs
On the Malicious Potential of Xilinx's Internal Configuration Access Port (ICAP)
FPGA-accelerated Correspondence-free Point Cloud Registration with PointNet Features
Hardware Decompression Techniques for FPGA-Based Embedded Systems
Execution Trace-Driven Energy-Reliability Optimization for Multimedia MPSoCs
Dynamic-ACTS - A Dynamic Graph Analytics Accelerator For HBM-Enabled FPGAs
Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects
A Fully Pipelined FPGA Architecture of a Factored Restricted Boltzmann Machine Artificial Neural Network
fSEAD: A Composable FPGA-based Streaming Ensemble Anomaly Detection Library
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration
Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs
Graph-OPU: A Highly Flexible FPGA-Based Overlay Processor for Graph Neural Networks
FPGA HLS Today: Successes, Challenges, and Opportunities
Shared Memory Multicore MicroBlaze System with SMP Linux Support
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration
Memory Latency Hiding by Load Value Speculation for Reconfigurable Computers
Feel Free to Interrupt: Safe Task Stopping to Enable FPGA Checkpointing and Context Switching
Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA
Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning
Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams
Streaming Overlay Architecture for Lightweight LSTM Computation on FPGA SoCs
A Scalable Accelerator for Local Score Computation of Structure Learning in Bayesian Networks
Rock the QASBA: Quantum Error Correction Acceleration via the Sparse Blossom Algorithm on FPGAs
UNILOGIC: A Novel Architecture for Highly Parallel Reconfigurable Systems
An Efficient FPGA-based Depthwise Separable Convolutional Neural Network Accelerator with Hardware Pruning
Wotan: Evaluating FPGA Architecture Routability without Benchmarks
Implementation Approaches Trade-Offs for WiMax OFDM Functions on Reconfigurable Platforms
Network on Chip Architecture for Multi-Agent Systems in FPGA
An open-source HyperTransport core
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations
MEG: A RISCV-based System Emulation Infrastructure for Near-data Processing Using FPGAs and High-bandwidth Memory
Dynamic Task Mapping with Congestion Speculation for Reconfigurable Network-on-Chip
Enhancing Reconfigurable Platforms Programmability for Synchronous Data-Flow Applications
Applying dynamic reconfiguration in the mobile robotics domain: A case study on computer vision algorithms
Safe Dynamic Reshaping of Reconfigurable MPSoC Embedded Systems for Self-Healing and Self-Adaption Purposes
DyRecMul: Fast and Low-Cost Approximate Multiplier for FPGAs using Dynamic Reconfiguration
Fixed-point FPGA Implementation of the FFT Accumulation Method for Real-time Cyclostationary Analysis
Data and Computation Reuse in CNNs Using Memristor TCAMs
SQL2FPGA: Automated Acceleration of SQL Query Processing on Modern CPU-FPGA Platforms
FlexSaaS: A Reconfigurable Accelerator for Web Search Selection
Sparse Matrix-Vector Multiplication on a Reconfigurable Supercomputer with Application
Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing
FPGA Logic Block Architectures for Efficient Deep Learning Inference
Scientific Application Demands on a Reconfigurable Functional Unit Interface
A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs