yusuke1997/dblp-id-title huggingface dataset:
Multiprocessing: Y Paker 'Multi-microprocessor systems' Academic Press, London, UK (1983) £16.50 pp 204
Embedding functionally described abstract data types into MODULA-2 programs
Low cost scaleable parallel image processing system
Parallel techniques for solving large scale travelling salesperson problems
Parallelization of the stack
Hyper spectral dimensionality reduction using hybrid discriminative local metric learning
Superscalar architecture design for high performance DSP operations
Semicustom ASIC design facility based on logic cell arrays
Design of an optimal folding mechanism for Java processors
A guide to PL/M programming for microprocessor applications: D D McCracken, Addison-Wesley, London (1978) 262pp, £7.50
Fault tolerance: principles and practice: Anderson, T and Lee, P.A., Prentice-Hall Internation, New Jersey, USA (1981) 369 pp, £16.95
The C puzzle book: A R FuerPrentice-Hall Software Series, Prentice-Hall, Englewood Cliffs, NJ, USA (October 1982) £11, pp 173
A sophisticated semantic analysis framework using an intelligent tweet data clustering and classification methodologies
A high-performance fully reconfigurable FPGA-based 2D convolution processor
Hotel intelligent guidance system based on ZigBee Technology
The digital storage oscilloscope (DSO) as a cost-effective solution to measurements in digital circuits
Medical IoT system platform and elderly patients' femoral shaft fracture nursing
Optimization of cloud computing task execution time and user QoS utility by improved particle swarm optimization
Special issue on selected papers from NORCHIP 2013
Microprocessor control of road toll systems
A general jitter analysis of DLL considering the jitter accumulation effect of loop capacitor
Distributed industrial control systems: a fault-tolerant architecture
Using dynamic partial reconfiguration of FPGAs in real-Time systems
Integrated project support environments
Microprocessor survey
Breast thermography based unsupervised anisotropic- feature transformation method for automatic breast cancer detection
Hardware/software co-design of physical unclonable function based authentications on FPGAs
Application of microprocessors in instrumentation and control systems: 29-30 September, 1976, City University, London, organized by Sira Institute in association with Warren Spring Laboratory
Quantifying the impact of uncertainty in embedded systems mapping for NoC based architectures
A Petri-net based distributed monitoring system using PIC microcontrollers
An adaptive microphone array processing system
A design concept for radiation hardened RADFET readout system for space applications
Hardware Specification, Verification and Synthesis: Mathematical Aspects: Leeser, M and Brown, G (Eds) Springer-Verlag, Heidelberg, Germany (1989) DM 57 pp 408
IPA - a processing architecture based on the ISO network reference model
Energy-centric routing in wireless sensor networks
On designing endurance aware erasure code for SSD-based storage systems
Introduction to parallel programming: S Brawer Academic Press, NY, USA (1989) $39.95 pp 423
Corrigendum to 'A Fog-Cloud based cyber physical system for Ulcerative Colitis diagnosis and stage classification and management' [Journal Microprocessor and Microsystems, 72 (2020) /102929]
Microprocessor system design
On the global optimization of checking sequences for finite state machine implementations
FPGA for pseudorandom generator cryptanalysis
Asynchronous spatial division multiplexing router
Embedded fault diagnosis in digital systems with BIST
Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes
TRON project 1989: Sakamura, K (Ed.) (Proceedings of the sixth TRON Project Symposium) Springer-Verlag, Tokyo, Japan (1989) pp 324
Design and research on automatic recognition system of sports dance movement based on computer vision and parallel computing
Creating the universal computer
Design of the Kydon-RISC processor
FPGA based design and implementation of power conditioning unit for fuel cell powered vehicle using adaptive vector reference control method
Digital cassette-recorder interface
Processor-level reliability simulator for time-dependent gate dielectric breakdown
Cascade signature and syndrome compression
Communication between two microprocessors through common memory
Cascaded Write Amplification of LSM-tree-based Key-Value Stores underlying Solid-State Disks
General addressing mechanisms for microprocessors
Software systems need to be built with the same cost controls and personnel motivation as more conventional engineering projects: P Depledge (ed.) 'Software engineering for microprocessor systems' Peter Peregrinus, London, UK (1984) £13.95 pp 261
Design of a reversible floating-point square root using modified non-restoring algorithm
Image recognition of CT diagnosis for cholangiocarcinoma treatment based on FPGA processor and neural network
Analysis of early warning of corporate financial risk via deep learning artificial neural network
Performance analysis of disk cache write policies
Computerist's handy databook/dictionary: Clayton L Hallmark, Tab Books (1979), 96 pp, $3.95
Embedded context aware diagnosis for a UAV SoC platform
Efficient separable convolution using field programmable gate arrays
EQUITAS: A tool-chain for functional safety and reliability improvement in automotive systems
Flow-based anomaly intrusion detection using machine learning model with software defined networking for OpenFlow network
SoPHy+: Programming model and software platform for hybrid resource management of many-core accelerators
Fine grained sentiment polarity classification using augmented knowledge sequence-attention mechanism
The AQUAS ECSEL Project Aggregated Quality Assurance for Systems: Co-Engineering Inside and Across the Product Life Cycle
Digital signal processing (DSP) radios: trends, benefits and challenges
Achieving cost-efficient fail-operational behavior based on inherent redundancy at the system level
A hybrid network architecture by integrating both 2.4 GHz network and Sub-GHz network and its application in field environment surveillance system
High-throughput area-delay-efficient systolic multiplier over GF(2 m ) for a class of trinomials
Single-channel-based automatic drowsiness detection architecture with a reduced number of EEG features
Floppy disc file management
Optimizing the configuration of an heterogeneous architecture of sensors for activity recognition, using the extended belief rule-based inference methodology
A task graph execution manager for reconfigurable multi-tasking systems
Flexible interface based on the peripheral interface structure
Design and implementation of a protocol offload engine for TCP/IP and remote direct memory access based on hardware/software coprocessing
Ecological evolution path of smart education platform based on deep learning and image detection
Fast DSP-based system for topographic EEG analysis
Applications of the digital correlator
Hardware Implementation of Effective Framework for the Trade-off between Security and QoS in Wireless Sensor Networks
A run-time verification method with consideration of uncertainties for cyber-physical systems
Evaluation of a low overhead predication system for a deterministic VLIW architecture targeting real-time applications
Design and simulation of quantum-dot cellular automata serial decimal pipelined processor based on Turing machine model
Design and realization of area-efficient approximate multiplier structures for image processing applications
Active flow control using dense wireless sensor and actuator networks
Configurable network-on-chip router macrocells
Parallel programming model for the Epiphany many-core coprocessor using threaded MPI
Medical wireless sensor network coverage and clinical application of MRI liver disease diagnosis
SeVuc: A study on the Security Vulnerabilities of Capsule Networks against adversarial attacks
Development of smart english classroom system based on FPGA software and hardware co-simulation test
TMS32020 implementation of an adaptive recursive echo canceller
Real-time implementation of a dynamic fuzzy neural networks controller for a SCARA
VHDL '92: The new features of the VHDL hardware description language : Jean-Michel Bergé, Alain Fonkoua, Serge Maginot and Jacques Rouillard Kluwer Academic Publishers, Dortrecht, The Netherlands (1993) ISBN 0 7923 9356 2, Dfl 180.00, £65.50, pp214
Adaptive battery aware power management of a computer with self power-managed components
Modula-2 for microcomputer systems : Cooling, J E Van Nostrand Reinhold (1988) £11.95 pp 301
Application of radar signal processing and image display algorithm based on computer hardware system in intelligence processing
An optimal intrusion detection system using recursive feature elimination and ensemble of classifiers
International logistics taxation data monitoring based on 5G network and cloud computing platform
Parallel processing of robot arm dynamic control computation on multimicroprocessors
Developing and checking prescriptive specification for safety improvement
Runtime home mapping for effective memory resource usage
Comparing different architectures for real-time computing of special algorithms: A case study
Memory streaming acceleration for embedded systems with CPU-accelerator cooperative data processing
Improved GPU SIMD control flow efficiency via hybrid warp size mechanism
Real-time implementation of an efficient correlator for complementary sets of four sequences appl to ultrasonic pulse compression systems
CASE tool for microprocessing
Kernellized support vector regressive machine based variational mode decomposition for time frequency analysis of Mirnov coil
One-way quantum computer simulation
Image recognition of competitive aerobics movements based on embedded system and digital image processing
Microcomputer-based graphic display systems
The Magic of Modula-2: Hopper, K, Holmes, G and Rogers, W Addison-Wesley, Wokingham, UK (1991) £19.95 pp 529, ISBN 0 201 50993 8
Criticality based reliability against hardware Trojan attacks for processing of tasks on reconfigurable hardware
The error rate analyze and parameter measurement on LoRa communication for health monitoring
Modular hardware of reduced performance for dedicated microprocessor applications: examples and justification
National Computer Conference: 4-7 May 1981 McCormick Place, Chicago, USA
Automatic circuit partitioning in the Anyboard rapid prototyping system
VLSI architecture for parallel radix-4 CORDIC
Utilization of cache area in on-chip multiprocessor
Design of a low-area hardware architecture to predict early signs of sudden cardiac arrests
Performance comparison of some shared memory organizations for 2D mesh-like NOCs
MIL project: a microcomputer integrated laboratory
High-level synthesis, cryptography, and side-channel countermeasures: A comprehensive evaluation
Self-checking logic arrays
Algorithms, software and hardware of parallel computers: J Mikloško and V E Kotov (eds)Springer-Verlag, Berlin, FRG (1984) DM 89 pp 395
Coordination infrastructures for mobile agents
Reliable advanced encryption standard hardware implementation: 32- bit and 64-bit data-paths
Simulation of oil painting art design based on 5 G mobile network and dynamic image sampling
Mag news
Review of Elliptic Curve Cryptography processor designs
Intelligent Transportation System Based on Smart Soft-Sensors to Analyze Road Traffic and Assist Driver Behavior Applicable to Smart Cities
Retraction notice to "FPGA implementation of low power and high speed image edge detection algorithm" [Microprocessors and Microsystems 75, 2020, 103053]
P1396: a proposed standard communications bus
The Cascade Vulnerability Problem: the detection problem and a simulated annealing approach for its correction
Optimized Hardware Vision System for Vehicle Detection based on FPGA and Combining Machine Learning and PSO
Transputer-based feature extraction and shape analysis
Experience using an intermediate compiler target language for parallel machines
A novel approach to improve multimedia security utilizing 3D mixed chaotic map
Efficient integration of coprocessor in LEON3 processor pipeline for System-on-Chip design
Interfacing fundamentals in microprocessor-controlled systems: Chris GeorgopoulosKluwer, Dordrecht, The Netherlands (1985) £24.95 pp xix + 364
Microprocessors: D R McGlynn, John Wiley (1976) 207 pp, £8.00
Low-Cost Strategy to Detect Faults Affecting Scrubbers in SRAM-Based FPGAs
MARBLE: an asynchronous on-chip macrocell bus
BASIC: interpreter or compiler?
Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study
FPGA based tester tool for hybrid real-time systems
Measuring the power efficiency of subthreshold FPGAs for implementing portable biomedical applications
Free text retrieval on transputer networks
A study of distributed embedded thermal monitoring in electric coils based on FBG sensor multiplexing
Mechatronics in medical engineering: advanced control of a ventilation device
A time-triggered transducer network based on an enhanced IEEE 1451 model
Microprocessors and microcomputers: E Huggins, Macmillan (1979) 224 pp, £12.00 (hard), £4.75 (paper)
Computing reliability: On the differences between software testing and software fault injection techniques
FLIX environment for generation of custom-configurable machines in FPLDs for embedded applications
The death of smart sensors and effectors for future combat aircraft
CAD tools for semicustom IC design
A novel design and analysis of comparator with XNOR gate for QCA
A 5-10GHz SiGe BiCMOS FPGA with new configurable logic block
6800 coprocessor for a 6502 bus
A modular Vedic multiplier architecture for model-based design and deployment on FPGA platforms
Estimating fuel adulteration in automobiles using robust optical fiber sensors
A formally based hard real-time kernel
Real-time edge computing on multi-processes and multi-threading architectures for deep learning applications
Thesis gives first-hand insights into RISC design: Manolis G H Katevenls 'Reduced instruction set computer architectures for VLSI' MIT Press, Cambridge, MA, USA (1985) £33.50 pp 215
GWalloc: A self-adaptive generational wear-aware allocator for non-volatile main memory
Fault modeling for external energy or internal cell defect in quantum dot cellular automata
Sim-ARM1136: A case study on the accuracy of the cycle-accurate simulator
Dual-port RAMs simplify processor communications
An 8-bit systolic AES architecture for moderate data rate applications
Accelerating sequential programs on Chip Multiprocessors via Dynamic Prefetching Thread
A novel self-checking carry lookahead adder with multiple error detection/correction
Statically adaptive multi FIFO buffer architecture for network on chip
The ANTAREX domain specific language for high performance computing
A dynamic adaptive converter and management for PRAM-based main memory
Dynamic simulation modelling of software requirements change management system
Large multimicroprocessor systems
Retraction notice to "FPGA implementation of PMSG based AC conversion using soft switching twin-mode PWM/FPGA control for high power IM application" [Microprocessors and Microsystems 75 (2020) 103044]
FPGA accelerator for real-time SIFT matching with RANSAC support
Performance modeling of heterogeneous HW platforms
FPGA based spike-time dependent encoder and reservoir design in neuromorphic computing processors
Smart community management portable device design based on embedded wearable device technology
Instruction selection and scheduling for DSP kernels
High-level synthesis : D D Gajaski, N D Dutt, A C-H Wu and S Y-L Lin Kluwer Academic Publishers, Dordrecht, The Netherlands (1992) ISBN 0 7923 9194 2, £62.95, pp 359
Computation and power reduction techniques for H.264 intra prediction
Optimizing SMT processors for IP-packet processing
FPGA-based variable modulation-indexed-SPWM generator architecture for constant-output-voltage inverter applications
Task parallelism-based architectures on FPGA to optimize the energy efficiency of AI at the edge
A reconfigurable HexCell-based systolic array architecture for evolvable hardware on FPGA
Machine cycle simulator for a microprocessor
Rapid prototyping of DSP algorithms on VLIW TMS320C6701 DSP
Overview of a development environment
Performance evaluation for CC-NUMA multiprocessors using an OLTP workload
Hardware-oriented optimization of Bloom filter algorithms and architectures for ultra-high-speed lookups in network applications
Improvement of energy-efficiency in off-chip caches by selective prefetching
Comparison between cellular automata and linear feedback shift registers based pseudo-random number generators
Adaptive pooling-based convolution factorization for deploying CNNs on energy-constrained IoT edge devices
A switched memory decoding system for a multiple processor system
The Poverty Alleviation Effect of Smart Financial Services Based on FPGA and Wireless Sensors
Monitoring water quality metrics of ponds with IoT sensors and machine learning to predict fish species survival
Industrial structure technology upgrade based on 5G network service and IoT intelligent manufacturing
Efficient FPGA implementation of corrected reversible contrast mapping algorithm for video watermarking
Decision logic for diagnostic evaluation of ECG signals
Field prototyping for software - a practical approach to implementation
Heuristic Initialization Based Modified ACO (HIMACO) Mimicking Ant Safety Features for Multicast Routing and its Parameter Tuning
Microprocessor-based multichannel analyser developed using POLYFORTH
Languages for the programming of real-time embedded systems a survey and comparison
An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA
Optimized algorithms and architectures for fast non-cryptographic hash functions in hardware
Scalability evaluation of an FPGA-based multi-core architecture with hardware-enforced domain partitioning
On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata
Development of a real-time, 20 mega-samples per second, 32 channel data acquisition system
Identification of microbial pollution sources in high-humidity buildings based on deep learning and image particle recognition
Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC)
Area and power efficient post-quantum cryptosystem for IoT resource-constrained devices
Development of cultural tourism platform based on FPGA and convolutional neural network
A novel rising Edge Triggered Resettable D flip-flop using five input majority gate
Relocating loader for MS-DOS .EXE executable files
An evolving neural network approach in unit commitment solution
Middleware services for interoperability in open mobile agent systems
A family of fault-tolerant systems: electrical flight controls, from Airbus A320/330/340 to future military transport aircraft
On the construction of small fully testable circuits with low depth
FPGA-based implementation of a chirp signal generator using an OpenCL design
Improving performance and determinism of multitasking systems on the LEON architecture
Special Issue based on Mechatronics '98 - the Sixth UK Mechatronics FORUM International Conference
A CANbus-based safety-critical distributed aeroengine control systems architecture demonstrator
Smart IoT data platform in hospital and postoperative analgesic effects of orthopedic patients
Formal constraint-based compilation for noisy intermediate-scale quantum systems
Design of low power NFSR for RFID system with irregular clock pulse
Implementation of efficient SR-Latch PUF on FPGA and SoC devices
Hiding message delivery latency using Direct-to-Cache-Transfer techniques in message passing environments
Automotive electronics: state of the art and future perspectives
Current mode controlled fuzzy logic based inter leaved cuk converter SVM inverter fed induction motor drive system
Dynamic node influence tracking based influence maximization on dynamic social networks
The portable UCSD p-System
A systematic approach to analysis for assessing the security level of cyber-physical systems in the electricity sector
Reverse scheduling - an effective method for scheduling tasks of parallel programs employing a divide-and-conquer strategy onto multiprocessors
Mobile agents: an introduction
On chip interconnects for multiprocessor turbo decoding architectures
An area- and energy-efficient hybrid architecture for floating-point FFT computations
Building up a system architecture using VMEbus
Supporting concurrent memory access in TCF processor architectures
Microprocessor keyboard encoding
Database management in a microcomputer-controlled IC tester
A dynamically reconfigurable parallel processing system
FORTH and microprocessor applications at the Royal Greenwich Observatory
A novel sign detection method in residue number system based on Chinese remainder theorem with fractional values
FPGAs for expression level parallel processing
Microprocessors: O A R ComillieEPO Applied Technology Series, Vol 8, Pergamon, Oxford, UK (1985) £57.00 pp 442
Control of protocol for mobile radios
Constant-weight coding based software implementation of DPA countermeasure in embedded microcontroller
Design and benchmarking of an ASIC with five SHA-3 finalist candidates
Serial interface/tape recorder modem
A transputer-based parallel machine translation system for Indian languages
Microprocessor impact on commerce
A fusion fall detection algorithm combining threshold-based method and convolutional neural network
Multiprocessor SoPC-Core for FAT volume computation
Performance comparison of permanent magnet synchronous motor (PMSM) drive with delay compensated predictive controllers
Buscon/UK 1987
Broad treatment of micro-based measurement and control: George C Barney'Intelligent instrumentation' Prentice Hall, Englewood Cliffs, NJ, USA (1985) £12.95 pp 532
Mechanism for evaluating the effectiveness of software fault-tolerant structures
Deriving an NCD file from an FPGA bitstream: Methodology, architecture and evaluation
Exploiting large register sets
DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories
XSG-based HLS flow for optimized signal processing designs for FPGAs
Automatic compilation of parallelism in visual object recognition
Logic synthesis for FPGAs based on cutting of BDD
FPGA based string matching for network processing applications
Algorithms: R Sedgewick Addison-Wesley, Reading, MA, USA (1983) £13.95 pp 551
Special issue on DSD 2018
Memory considerations for a microprocessor video interface system
VLSI design of APT-VDF using novel variable block sized ternary adder and multiplier
Compiler-assisted energy reduction of java real-time programs
Retraction notice to "Optimization of Storage Location Assignment in Automated Warehouse" [Microprocessors and Microsystems 80 (2021)103356]
Design and dynamic management of hierarchical NoCs
Low-power and high-speed shift-based multiplier for error tolerant applications
Image recognition problems of fingerprint identification
A new scalable broadcast algorithm for multiport meshes with minimum communication steps
Enhanced architecture for programmable logic controllers targeting performance improvements
Savitzky-Golay filtering as image noise reduction with sharp color reset
FPGA-based implementation of recursive algorithms
Digital troubleshooting
Single-chip microcomputer for use in automotive instrumentation
Area and speed oriented synthesis of FSMs for PAL-based CPLDs
An inexpensive microprocessor development system
Token bus communications within a multiprocessor system
An automated, FPGA-based reconfigurable, low-power RFID tag
Offset FFT and its implementation on the TMS320C25 processor
D 2 ART: Direct Data Accessing from Passive RFID Tag for infra-less, contact-less, and battery-less pervasive computing
Basic human-robot interaction system running on an embedded platform
Quantum tunicate swarm algorithm based energy aware clustering scheme for wireless sensor networks
FPGA implementation of an OFDM-based WLAN receiver
Zero-load predictive model for performance analysis in deflection routing NoCs
An FPGA platform for on-line topology exploration of spiking neural networks