yusuke1997/dblp-id-title huggingface dataset:
Stabilization of Noisy Sampled-Data Networked Control Systems: Application to Interleaved Flyback Modular Integrated Converter Circuit
A Compact Single-Ended Inverter-Based Transceiver With Swing Improvement for Short-Reach Links
Power-Noise Trade-Offs in Continuous-Time Pipelined ADCs and Active Filters
Powerless Fractional-Order Tuning Wireless Power Transfer System With Zero Phase Angle Input
Fully Integrated Single-Input-Dual-Output Switch-Capacitor DC-DC Converter With Fast DVS Speed and Fast Transient Response
FPGA Implementation of Sparsity Independent Regularized Pursuit for Fast CS Reconstruction
An RF Modulation Based on k-th Order PWM Harmonic
Analysis and Design of Lossy Capacitive Over-Neutralization Technique for Amplifiers Operating Near f MAX
Prescribed Performance-Based Distributed Predefined Time Control for DC Microgrid Clusters
A Sub-Nanosecond Delay Floating Voltage Level Shifter With 300 V/ns Power Supply Slew Tolerance
PUF-CLGS: Application of Multi-Factor PUF Authentication Circuit Based on Lattice Group Signature in Drone-Assisted Communication
A Systematic Approach to Designing Broadband Millimeter-Wave Cascode Common-Source With Inductive Degeneration Low Noise Amplifiers
LiMo: A Framework Leveraging Machine Learning for Multi-Input Switching Timing Models of Complex Logic Gates
Adaptive Fault Estimation for Unmanned Surface Vessels With a Neural Network Observer Approach
Reconfigurable Filtering Power Divider With Arbitrary Operating Channels Based on External Quality Factor Control
GSLP-CIM: A 28-nm Globally Systolic and Locally Parallel CNN/Transformer Accelerator With Scalable and Reconfigurable eDRAM Compute-in-Memory Macro for Flexible Dataflow
Design of a Compact Superconducting RSFQ Register File
Accurate Design Method for Millimeter Wave Distributed Amplifier Based on Four-Port Chain (ABCD) Matrix Model
De-Correlation and De-Bias Post-Processing Circuits for True Random Number Generator
Memristor-Based Neural Network Circuit of Duple-Reward and Duple-Punishment Operant Conditioning With Time Delay
Penalty-Based Distributed Optimal Control of DC Microgrids With Enhanced Current Regulation Performance
Fast Supersingular Isogeny Diffie-Hellman and Key Encapsulation Using a Customized Pipelined Montgomery Multiplier
Design of a Mixed-Signal Compute-in-Memory Ising Solver With Sub-μs Time-to-Solution and Optimal Decaying Noise Profile
Hardware-Efficient and Short Sensing-Time Multicoset-Sampling Based Wideband Spectrum Sensor for Cognitive Radio Network
Differentiable Cost Model for Neural-Network Accelerator Regarding Memory Hierarchy
A Family of Current References Based on 2T Voltage References: Demonstration in 0.18-μm With 0.1-nA PTAT and 1.1-μA CWT 38-ppm/°C Designs
Distributed Fault Detection and Control for Markov Jump Systems Over Sensor Networks With Round-Robin Protocol
Generating Posit-Based Accelerators With High-Level Synthesis
Distributed Disturbance-and-Leader Estimation for Controlling Networks of Nonholonomic Mobile Robots
Folded Noise Prediction in Nonlinear Fractional-N Frequency Synthesizers
A 94.2% Peak Efficiency Full Duty Range Flying-Capacitor Sharing Dynamic Four-Path Hybrid Converter With Reduced Body Diode Loss Technique
A New Energy-Efficient and High Throughput Two-Phase Multi-Bit per Cycle Ring Oscillator-Based True Random Number Generator
Single Antenna and No Circulator Full-Duplex With 52 dB Wideband Self-Interference Suppression
A New Reconfigurable True Random Number Generator and Physical Unclonable Function Unified Chip With On-Chip Auto-Calibration
Single-Cycle Independent Component Analysis Processor for In-Band Full Duplex Systems
Analysis and Design of Capacitive Voltage Distribution Stacked MOS Millimeter-Wave Power Amplifiers
Integrating OFDM Into Switching Power Supplies for Visible Light Communications
A 26.5-29.5 GHz Doherty PA-LNA Implementation With Synthesized Transformer-Based Matching Network
A 3-Phase Resonant Switched-Capacitor Converter for Data Center 48-V Rack Power Distribution
Interpretable Deep Reinforcement Learning for Optimizing Heterogeneous Energy Storage Systems
Adaptive Fast Fault Location for Open-Switch Faults of Voltage Source Inverter
Approximate Belief-Selective Propagation Detector for Massive MIMO Systems
Control of Power Converters With Hybrid Affine Models and Pulse-Width Modulated Inputs
Power-Efficient Single-Stage Class-AB OTA Based on Non-Linear Nested Current Mirrors
WASENN: Wavelet Assisted Stochastic Enabled Neural Network for Human Activity Recognition
A Single-Stage, Capacitively-Coupled Instrumentation Amplifier With Complementary Transimpedance Boosting
A Balanced CMOS Compatible Ternary Memristor-NMOS Logic Family and Its Application
Modeling and Optimization of XOR Gate Based on Stochastic Thermodynamics
An Efficient FPGA-Based Dilated and Transposed Convolutional Neural Network Accelerator
Event-Triggered Quantized Input-Output Finite-Time Synchronization of Markovian Neural Networks
Accurate and Fast On-Wafer Test Circuitry Integrated With a 140-dB-Input-Range Current Digitizer for Parameter Tests in WAT
A 7.8-13.6 pJ/b Ultra-Low Latency and Reconfigurable Neural Network-Assisted Polar Decoder With Multi-Code Length Support
Neural Network Training With Stochastic Hardware Models and Software Abstractions
A 77.7 dB-SNDR 625 kHz-BW First-Order Noise-Shaping SAR ADC Using a Novel VCO-Based Charge-Accumulation Integrator
Design Space Exploration of Interconnect Materials for Cryogenic Operation: Electrical and Thermal Analyses
HAST: A Hardware-Efficient Spatio-Temporal Correlation Near-Sensor Noise Filter for Dynamic Vision Sensors
C4TERO: Configurable Cascaded Carry Chains for High Reliability TERO PUFs on FPGAs
Finite-Time Multisynchronization of Coupled Discontinuous Cohen-Grossberg Neural Networks and Its Application in Associative Memory
Phase Noise and Dynamic Range in Radar Arrays
A VCO-Based Modulation Low Ripple PFM-PWM Buck Converter With Seamless Mode Transition
A 5 μW Standard Cell Memory-Based Configurable Hyperdimensional Computing Accelerator for Always-on Smart Sensing
MINA: A Hardware-Efficient and Flexible Mini-InceptionNet Accelerator for ECG Classification in Wearable Devices
Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes
Booth-Assisted Mixed-Precision Reconfigurable Digital Computing-in-Memory Engine With Ternary-Input 1T2R ReRAM for Edge AI
A Triboelectric Energy Harvesting IC With High-Voltage Synchronous Electric Charge Extraction Strategy and Superior Systematic Efficiency
Compounding and Synchronization of Fractional Order Chaotic Systems With Prescribed Performance for Secure Communication
A Neural Network-Based Online Parameter Identification Method for Fractional-Order Power Electronics
A Low-Noise Class-F 23 VCO With Harmonic Resonance Expansion and 2nd/3rd-Harmonic Outputs for Multiband mm-Wave Applications
Hardware Implementations for Voice Activity Detection: Trends, Challenges and Outlook
Where Should Inverter-Based Resources Be Located in Power Networks?
Setting Up the State Equations of Switched Circuits Using Homogeneous Models
Automated Design Approximation to Overcome Circuit Aging
A MEMS-CMOS Microsystem for Contact-Less Temperature Measurements
Nash Equilibrium Seeking via Neurodynamic Optimization and Application to Analog Circuits
A 32 kb 55 nm Radiation-Hardened SRAM Chip With SEU ≤1.1 E-11 Upsets/Bit-Day, SEL >107.1 MeV ⋅ cm²/mg, and TID >100 Krad(Si) for Space Applications
Decentralized Secure Tracking Control for Nonlinear Interconnected Systems: A Synergetic Learning-Based Strategy
Instantaneous Power Theory Revisited With Classical Mechanics
AFibri-Net: A Lightweight Convolution Neural Network Based Atrial Fibrillation Detector
Distributed Fault Estimation and Fault-Tolerant Control of Interconnected Systems With Plug-and-Play Features
A Compact Memristor Model for Neuromorphic ReRAM Devices in Flux-Charge Space
Buck Circuit Design With Pseudo-Constant Frequency and Constant On-Time for High Current Point-of-Load Regulation
A 9.2-ns to 1-s Digitally Controlled Multituned Deadtime Optimization for Efficient GaN HEMT Power Converters
Design of a PAM-4 VCSEL-Based Transceiver Front-End for Beyond-400G Short-Reach Optical Interconnects
A ±0.5 dB, 6 nW RSSI Circuit With RF Power-to-Digital Conversion Technique for Ultra-Low Power IoT Radio Applications
High Precision Radiation Resistant Bandgap Voltage Regulator for Aerospace Applications
Switched-Capacitor-Based DC-AC Boosting Circuit: Synthesis and Operation
Defective Pixel Corrector for Line Scan and Area Scan Image Sensors
Delay Mismatch Insensitive Dead Time Generator for High-Voltage Switched-Mode Power Amplifiers
Analysis of RC Time-Constant Variations in Continuous-Time Pipelined ADCs
A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation
Stabilization and Synchronization Control of Multi Coupled Hyperbolic-Parabolic Partial Differential Systems Based on Backstepping Method
Bipartite Containment of Multi-Leader Multi-Agent Systems With Antagonistic Information and Measurement Noise
An Efficient Three-Phase Soft-Switching Inverter With Simplified Asymmetric Single Auxiliary Circuit on Each Bridge Arm for Low-Speed AC Motor Drive
An Energy-Efficient BNN Accelerator With Two-Stage Value Prediction for Sparse-Edge Gesture Recognition
Symmetric-Mapping LUT-Based Method and Architecture for Computing X Y -Like Functions
Output-Feedback Stabilization of Uncertain Nonlinear Systems With Multiple Unknown Control Directions via an Integrated Switching Controller
An Energy-Area-Efficient 3D Interleaved-Ring Accelerator With INT/FP Pipelined PE Array and 3D-SRAM Cube for On-Device CNN Training and DM Inference
A 1MHz 256kb Ultra Low Power Memory Macro for Biomedical Recording Applications in 22nm FD-SOI Using FECC to Enable Data Retention Down to 170mV Supply Voltage
BoostViT: Booth-Serial Skipping and Tunable Scaling for Vision Transformers
Adaptive Horizon Seeking for Generalized Predictive Control via Deep Reinforcement Learning With Application to DC/DC Converters
An Application Specific Vector Processor for Efficient Massive MIMO Processing
Low-Complexity and Low-Latency SVC Decoding Architecture Using Modified MAP-SP Algorithm
Design of High Gain and High Sensitivity Extremely-Low Frequency Magnetic Signal Receiving System
A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation
Distributed Frequency Interactive Damping Control for Multiple VSGs in Islanded Microgrids
CASCADE: A Framework for CNN Accelerator Synthesis With Concatenation and Refreshing Dataflow
A Three-Stage Charge Pump With Forward Body Biasing in 28 nm UTBB FD-SOI CMOS
Characterizing Approximate Adders and Multipliers for Mitigating Aging and Temperature Degradations
Power Bound Analysis of a Two-Step MASH Incremental ADC Based on Noise-Shaping SAR ADCs
Resilient Output Formation-Tracking of Heterogeneous Multi-Agent Systems Against Composite Attacks: A Fully-Distributed Event-Triggered Framework
Load Mismatch Compensation of Doherty Power Amplifier Using Dual-Input and Mode Reconfiguration Techniques
Finite-Time Sliding Mode Control for NPC Converters With Enhanced Disturbance Compensation
Multi-Prior Mixture Distribution and Arithmetic Average Fusion-Based Student's t Filter
Dynamical Analysis of Memristive HNN and Medical Image Encryption via Bi-Directional Permutation and Multi-Directional Diffusion to PACS
Consensus of Networked Fractional-Order Systems With Intermittent Sampled Position Measurements
GBSense: A GHz-Bandwidth Compressed Spectrum Sensing System
Data-Driven Control Algorithms for Unknown Discrete-Time Linear Periodic Systems
ESSR: An 8K@30FPS Super-Resolution Accelerator With Edge Selective Network
A Reconfigurable Passive Mixer-Based Sub-GHz Receiver Front-End for Fast Spectrum Sensing Functionality
Steady-State Cascading Failure Model With Voltage Instability Event Detection
Adaptive Boundary Observer Design for Coupled Parabolic PDEs With Different Diffusions and Parameter Uncertainty
CiTST-AdderNets: Computing in Toggle Spin Torques MRAM for Energy-Efficient AdderNets
A SPAD Image Sensor With Main-Sub-TDC-Based Coincidence Detection
DyGA: A Hardware-Efficient Accelerator With Traffic-Aware Dynamic Scheduling for Graph Convolutional Networks
Event-Triggered Fully Distributed Bipartite Containment Control for Multi-Agent Systems Under DoS Attacks and External Disturbances
In Situ Aging-Aware Error Monitoring Scheme for IMPLY-Based Memristive Computing-in-Memory Systems
Digital Time-Domain Predistortion of Linear Periodically Time-Varying Effects and Its Application to a 100-GS/s Time-Interleaved CMOS DAC
Efficient Learning Strategies for Machine Learning-Based Characterization of Aging-Aware Cell Libraries
Finite-Time Dissipative Tracking Control of Semi-Markov Jump Systems Under Multi-Channel Hybrid Attacks
High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion
Self-Shielded Single- and Dual-Band Quad-Mode Substrate Integrated Waveguide Bandpass Filters Based on Mixed-Mode Cavity
High-Accuracy Low-Cost Generalized Complex Pruned Volterra Models for Nonlinear Calibration
An 88.5 fs rms Integrated Jitter and -76.2 dBc Reference Spur mmW PLL Utilizing a Ripple Compensation Phase/Frequency Detector
SRAM-Based In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC for Processing Neural Networks
Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC
Compact Pixelated Microstrip Forward Broadside Coupler Using Binary Particle Swarm Optimization
Wideband Balanced Filters With Intrinsic Common-Mode Suppression on Coplanar Stripline-Based Multimode Resonators
Robust Hierarchical Pinning Control for Nonlinear Heterogeneous Multiagent System With Uncertainties and Disturbances
FPGA-Based Hardware Implementation of Blue-Noise Stacked Error Diffusion Multitoning
Wideband-Filtering Switches With Ultra-Wide Stopband Using P-I-N Diodes Loaded on Slotline
A 13.2-kSPS Data Rate, 5.1-G Ω Input Impedance Read-Out IC for DC Measurements
Routh Zero Location Tests Unhampered by Nonessential Singularities
A High-Performance Domain-Specific Processor With Matrix Extension of RISC-V for Module-LWE Applications
Portable CMOS NMR System With 50-kHz IF, 10-μs Dead Time, and Frequency Tracking
0.4-V Tail-Less Quasi-Two-Stage OTA Using a Novel Self-Biasing Transconductance Cell
Space-Time Sampled-Data Control for Memristor- Based Reaction-Diffusion Neural Networks With Nonhomogeneous Sojourn Probabilities
Ternary LDPC Error Correction for Arrhythmia Classification in Wireless Wearable Electrocardiogram Sensors
A 10MHz-BW 85dB-DR CT 0-4 Mash Delta-Sigma Modulator Achieving +5dBFS MSA
Design of High-Reliability Memory Cell to Mitigate Single Event Multiple Node Upsets
A Double-Memristor Hyperchaotic Oscillator With Complete Amplitude Control
A Continuous-Output-Current Buck-Boost Converter Without Right-Half-Plane-Zero (RHPZ)
A Real-Time 2D/3D Perception Visual Vector Processor for 1920 × 1080 High-Resolution High-Speed Intelligent Vision Chips
A Continuously-Tunable Optoelectronic Oscillator With Full Locking Range Utilizing Three Frequency Tuning Mechanisms
A Comprehensive and Unified Procedure for Symbolic Analysis of Analog Circuits
Mecha: Multiview Enhanced Characteristics via Series Shuffling for Time Series Classification and Its Application to Turntable Circuit
Matrix-Based Digital Calibration Technique for High-Performance SAR and Pipeline ADCs
MASH-Based Divider Controllers for Mitigation of Wandering Spurs in a Fractional-N Frequency Synthesizer
A Novel Module-Sign Low-Power Implementation for the DLMS Adaptive Filter With Low Steady-State Error
MF-Net: Compute-In-Memory SRAM for Multibit Precision Inference Using Memory-Immersed Data Conversion and Multiplication-Free Operators
AMPS: An Automated Mesochronous Pipeline Scheduler and Design Space Explorer for High Performance Digital Circuits
Optimization Schemes for In-Memory Linear Regression Circuit With Memristor Arrays
An Adaptive Fully Integrated Wide-Range Power Management Unit With Fractional Charge Pump for Micro-Scale Energy Harvesting Applications
Sparse Compressed Spiking Neural Network Accelerator for Object Detection
An SoC FPAA Based Programmable, Ladder-Filter Based, Linear-Phase Analog Filter
Average Controllability of Complex Networks With Laplacian Dynamics
Observability Verification System Analysis for Observability and Reconstructibility of Probabilistic Logical Control Networks
A Battery Management System Using Interleaved Pulse Charging With Charge and Temperature Balancing Based on NARX Network
Guest Editorial Special Issue on the IEEE International NEWCAS Conference 2022
Reliable Binarized Neural Networks on Unreliable Beyond Von-Neumann Architecture
A Simple Chaotic Model With Complex Chaotic Behaviors and Its Hardware Implementation
Enhancing Continuous Beam Angle Resolution for Next Generation Wireless Systems: A Multi-Stage Phase-Shifting Polyphase Filters Approach
Ripple Suppression in Capacitive-Gain Chopper Instrumentation Amplifier Using Amplifier Slicing
A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC
D-Band On-Chip Couplers With Multilayered Slow-Wave Unit Cell in Standard CMOS Process
TSUNAMI: Triple Sparsity-Aware Ultra Energy-Efficient Neural Network Training Accelerator With Multi-Modal Iterative Pruning
A Practical Design-Space Analysis of Compute-in-Memory With SRAM
FPGA-Based Relaxation D/A Converters With Parasitics-Induced Error Suppression and Digital Self-Calibration
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise
A Memristive Phase-Shifting Chaotic Oscillator
Event-Driven Approach With Time-Scale Hierarchical Automaton for Switching Transient Simulation of SiC-Based High-Frequency Converter
Dyn-Bitpool: A 28 nm 27 TOPS/W Two-Sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization
VSDCA: A Voltage Sensing Differential Column Architecture Based on 1T2R RRAM Array for Computing-in-Memory Accelerators
Nonlinear Capacitance Effect on Stability and Stabilization of SiGe Power Amplifiers for 17.3-21.2 GHz SATCOM
Finite-Time Stabilization of Semi-Markov Reaction-Diffusion Memristive NNs With Unbounded Time-Varying Delays
A Mode-Reconfigurable Second-Order NS-SAR ADC With NTF Synchronous Optimization
A Beyond 100-Gbps Polymer Microwave Fiber Communication Link at D-Band
SSM-CIM: An Efficient CIM Macro Featuring Single-Step Multi-bit MAC Computation for CNN Edge Inference
Analysis and Measurement of Noise Suppression in a Nonlinear Regenerative Amplifier
Reaching Distributed Interval State Estimation on Discrete-Time LTI Systems
Reply to Comments on "Architectural Evolution of Integrated M-Phase High-Q Bandpass Filters"
Generalized Analog-to-Information Converter With Analysis Sparse Prior
Stochastic Event-Based Distributed Fusion Estimation Over Sensor Networks With Fading Channel
Ultra-Low-Power Sub-1 V 29 ppm/°C Voltage Reference and Shared-Resistive Current Reference
Memristor-Assisted Background Calibration for SAR ADCs: A Feasibility Study
A Reference Oversampling PLL With a FoM REF of -240.1 dB Enabled By a Capacitive Parasitic-Proof Ring Oscillator and a Time-Multiplexed Gm Stage
A 10 mV-500 mV Input Range, 91.4% Peak Efficiency Adaptive Multi-Mode Boost Converter for Thermoelectric Energy Harvesting
FALSAx: An Integrated Framework for Accuracy and Logic Synthesis Estimation of Approximate Adders
Adaptive Cancellation of Inter-Symbol Interference in High-Speed Continuous-Time DACs
A Novel Control Approach Accommodating Dynamic Process and Steady-State Accuracy
VbPWM-Based ADT: An Iterative Deduction Approach Restricting the Traversal of MPWM at the Cost of In-Band SNR
Silicon CMOS Image Sensor With Wide Response Spectrum From 254 nm to 1310 nm Enabled by Photodiode-Body-Biased MOSFET
Robust H ∞ Control for ICPT Process With Coil Misalignment and Time Delay: A Sojourn-Probability-Based Switching Case
Fast Finite-Time Event-Triggered Consensus Control for Uncertain Nonlinear Multiagent Systems With Full-State Constraints
Attractor Dynamics of 2-Lobe Discrete Corsage Memristor-Coupled Neuron Map
Generalized Switched-Capacitor-Based Hybrid Multilevel Inverter With Reduced Components Count and Inrush Current
Input Phase Controlled Doherty Power Amplifier With Out-Phased Current Load Modulation for Arbitrary Output Back-Off
A CNN Inference Accelerator on FPGA With Compression and Layer-Chaining Techniques for Style Transfer Applications
PDE-Based Finite-Time Deployment of Heterogeneous Multi-Agent Systems Subject to Multiple Asynchronous Semi-Markov Chains
Pragmatic Evaluation of Process Corners in ULP Subthreshold Circuits With Quantum Confinement Effects in Junctionless Nanowire Transistor
Reconfigurable Bit-Serial Operation Using Toggle SOT-MRAM for High-Performance Computing in Memory Architecture
NOMA System Performance Improvement Using Chaos and Deep Learning
Hybrid Spatial and Temporal Computing Histogrammer in Soft Processor Core of a FPGA Device
Neuromorphic Dynamics of Chua Corsage Memristor
A Generalize Hardware Debugging Approach for Large Language Models Semi-Synthetic, Datasets
An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration
A Novel Transform Accelerator With Fast Kernel Selection and Efficient Transform Circuit
Output Feedback Predefined-Time Bipartite Consensus Control for High-Order Nonlinear Multiagent Systems
Input-Reflectionless Quasi-Elliptic-Type Single- and Dual-Band Bandpass Filters Based on Passive Channelized Principles
A Real-Time Hardware Emulator for 3D Non-Stationary U2V Channels
A Raw Image-Based End-to-End Object Detection Accelerator Using HOG Features
A 15-28 GHz Low-Noise Amplifier With 0.75-dB Gain Ripple Across the Full K-Band
A Path Statistical Delay Prediction Framework Based on Global Graph Neural Network
A 120-to-142-GHz Compact Balanced Power Amplifier Utilizing Novel Slow-Wave Coupled Line in 40-nm CMOS
Efficient Single- and Dual-Band Rectifiers With Wide Range of Load Variations
A Multi-Step ADC With Lightweight Input Buffer Distortion, Sub-Stage Coarse-Fine Gain, and Sampling Skew Background Calibrations
FPGA Implementation for Finite-Time and Fixed-Time Neurodynamic Algorithms in Constrained Optimization Problems
Guest Editorial Special Issue on Emerging Hardware Security and Trust Technologies - AsianHOST 2023
Synthesis of High-Order Continuously Tunable Low-Pass Active-R Filters
Robust PCL Discovery of Data-Driven Mean-Field Game Systems and Control Problems
One-Step Calculation Circuit of FFT and Its Application
Temperature-Aware Differential Programming for Performance and Energy Optimization on 3D NAND High-Density Flash Memory
Bumpless Transfer Control for Switched Linear Systems and its Application to Aero-Engines
Bipartite Flocking for Cucker-Smale Model on Cooperation-Competition Networks Subject to Denial-of-Service Attacks
A Sensorless Peak Current-Mode Controlled DC-DC Converter: Design and Robustness Analysis Using Time-Scale Decomposition
Implementation of Group-Approximate Expectation Propagation Algorithm for Uplink MIMO-SCMA Detection Using 16-Point Codebook
Random Sampling-and-Averaging Techniques for Single-Photon Arrival-Time Detections in Quantum Applications: Theoretical Analysis and Realization Methodology
Analog Multiply-Accumulate Cell With Multi-Bit Resolution for All-Analog AI Inference Accelerators
A Chronic Diseases Detection Integrated Interface With Anti-Drift Normalization and On-Chip Classification Schemes
WinTA: An Efficient Reconfigurable CNN Training Accelerator With Decomposition Winograd
LIMITA: Logic-in-Memory Primitives for Imprecise Tolerant Applications
Continuous-Time Incremental Delta-Sigma Modulators With FIR Feedback
A 2.1 mW 2 MHz-BW 73.8 dB-SNDR Buffer-Embedded Noise-Shaping SAR ADC
A High-Speed ANN-Based Data Acquisition Hardware Accelerator Targeting Electrical Impedance Tomography
A 180 nA Quiescent Current Digital Control Dual-Mode Buck Converter With a Pulse-Skipping Load Detector for Long-Range Applications