yusuke1997/dblp-id-title huggingface dataset:
Enabling Remote Testing: Embedded Test Controller and Mixed-signal Test Architecture
Diagnostic Test Set Minimization and Full-Response Fault Dictionary
Security Against Hardware Trojan Attacks Using Key-Based Design Obfuscation
Test quality of hierarchical defect-tolerant integrated circuits
Current State of the Mixed-Signal Test Bus 1149.4
Verilog HDL Simulator Technology: A Survey
A Bridged Contactless Measurement Technique for LC Tank Based Voltage-Controlled Oscillator
Total Ionizing Dose Effect and Single Event Burnout of VDMOS with Different Inter Layer Dielectric and Passivation
VI-Based Measurement System Focusing on Space Applications
Features of a Scan and Clock Resource chip for providing access to board-level test functions
Formal Verification of ECCs for Memories Using ACL2
Memory Defect Tolerance Architectures for Nanotechnologies
A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICs
Comparing quality assurance methods and the resulting design strategies: Experiences from complex designs
Failure Analysis of VLSI by I DDQ Testing
Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults
Manipulation of Training Sets for Improving Data Mining Coverage-Driven Verification
A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling
Cyclic code weight spectra and BIST aliasing
General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR using A Synchronization-before-Voting Scheme
Comparison of NIST and Wavelet Transform Test Point Selection Methods For a Programmable Gain Amplifier
Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing
RFID System On-line Testing Based on the Evaluation of the Tags Read-Error-Rate
A Flexible Concurrent Testing Scheme for Non-Feedback and Feedback Bridging Faults in Integrated Circuits
Radiation Hardened by Design-based Voltage Controlled Oscillator for Low Power Phase Locked Loop Application
A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs
Primitive polynomials of degree 301 through 500
2019 Reviewers
2021 JETTA-TTTC Best Paper Award
Fault Diagnosis for Linear Analog Circuits
Performances and Stability Analysis of a Novel 8T1R Non-Volatile SRAM (NVSRAM) versus Variability
A neural network algorithm for testing stuck-open faults in CMOS combinational circuits
Testability analysis in high level data path synthesis
Test Generation for Crosstalk-Induced Faults: Framework and Computational Results
16- Layer PCB Channel Design with Minimum Crosstalk and Optimization of VIA and TDR Analysis
Incipient Fault Diagnostics and Remaining Useful Life Prediction of Analog Filters
Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices
On Using Twisted-Ring Counters for Test Set Embedding in BIST
Reactant and Waste Minimization during Sample Preparation on Micro-Electrode-Dot-Array Digital Microfluidic Biochips using Splitting Trees
A Feature-Adaptive and Scalable Hardware Trojan Detection Framework For Third-party IPs Utilizing Multilevel Feature Analysis and Random Forest
Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise
Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit
Analog Circuits Soft Fault Diagnosis Using Rényi's Entropy
Overcoming Test Setup Limitations by Applying Model-Based Testing to High-Precision ADCs
Prognostics of Analog Filters Based on Particle Filters Using Frequency Features
Current Consumption and Power Integrity of CMOS Digital Circuits Under NBTI Wearout
Parallel pseudorandom number generation in GaAs cellular automata for high speed circuit testing
A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction of 3D Wafer-on-Wafer Stacked ICs
Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation
Fault macromodeling and a testing strategy for opamps
On the Harmonic Locking of Ring Oscillators under Single ElectroMagnetic Pulsed Fault Injection in FPGAs
Temperature and Humidity Controlled Test Bench for Temperature Sensor Characterization
Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction
Evaluation of the Impact of Technology Scaling on Delay Testing for Low-Cost AVS
Multiple Missing Cell Defect Modeling for QCA Devices
Applying Petri Nets to Modeling of Many-Core Processor Self-Testing when Tests are Performed Randomly
IDDQ testing: A review
Defect Analysis and Defect Tolerant Design of Multi-port SRAMs
Fault Diagnosis of Smart Grid Distribution System by Using Smart Sensors and Symlet Wavelet Function
An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR
EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement
Test Data Compression for System-on-chip using Flexible Runs-aware PRL Coding
Correction to: Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness
Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance
Multifault and delay-fault testability of multilevel circuits
A Low Power Online Test Method for FPGA Single Solder Joint Resistance
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores
Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach
A Low-Loss Built-In Current Sensor
Redundancies and don't cares in sequential logic synthesis
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
Phase Noise Analysis Performance Improvement, Testing and Stabilization of Microwave Frequency Source
Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop
Generation and evaluation of current and logic tests for switch-level sequential circuits
Improving the testability of switched-capacitor filters
Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations
Adaptive Fault Detection and Diagnosis of RAM Interconnects
A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits
Workload Distribution in Fault Simulation
Cross-Domain Multi-Label Prediction of Metamorphic Relation Patterns Leveraging Multimodal Features
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems
Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion
TA-PSV - Timing Analysis for Partially Specified Vectors
On the Duality of Probing and Fault Attacks
2015 JETTA Reviewers
Reducing Aging Impacts in Digital Sensors via Run-Time Calibration
Deterministic tests for detecting single V -coupling faults in RAMs
Soft Errors Sensitivity of SRAM Cells in Hold, Write, Read and Half-Selected Conditions
LPTest: a Flexible Low-Power Test Pattern Generator
Read & Write Stability of CNTFET 6T SRAM Cell: A Comprehensive Analysis
CMOS Implementation and Performance Analysis of Known Approximate 4: 2 Compressors
On-Line Error Detection for Bit-Serial Multipliers in GF(2m)
A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic
Advancing Low Power BIST Architecture with GAN-Driven Test Pattern Optimization
Enhanced Moth Flame Optimization Algorithm Entropy-Based Centroid SVM-Based Software Defect Prediction
Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip
Application of Supply Current Testing to Analogue Circuits, Towards a Structural Analogue Test Methodology
Digital Signature Proposal for Mixed-Signal Circuits
Soft Fault Diagnosis of Analog Circuits via Frequency Response Function Measurements
Three-Level Management Algorithm to Increase the SEU Emulation Rate in DPR Based Emulators
A New Built-In Defect-Based Testing Technique to Achieve Zero Defects in the Automotive Environment
A New Test Point Selection Method for Analog Circuit
Parallel sequence fault simulation for synchronous sequential circuits
Tungsten Lamps as an Affordable Light Source for Testing of Photovoltaic Cells
A Design-Based Structural Test Method for a Switched-Resistor DAC
Quantity Analysis Method for Text-Based Chip Test Datasets from Automated Test Equipment
Decentralized BIST Methodology for System Level Interconnects
Achieving Agility in Projects Through Hierarchical Divisive Clustering Algorithm
Stress-Aware Periodic Test of Interconnects
Fault modeling and fault equivalence in CMOS technology
On behavior fault modeling for digital designs
Pseudorandom Test of Nonlinear Analog and Mixed-Signal Circuits Based on a Volterra Series Model
Defect Detection Using Quiescent Signal Analysis
Enhancing on-line testability during synthesis
A Metaheuristic and Neural Network-Based Framework for Automated Software Test Oracles Under Limited Test Data Conditions
Classical Cryptanalysis Attacks on Logic Locking Techniques
New March Tests for Multiport RAM Devices
Test Planning for Core-based Integrated Circuits under Power Constraints
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes
Allocation Techniques for Reducing BIST Area Overhead of Data Paths
Diagnosis of Boards for Realistic Interconnect Shorts
A three-stage partial scan design method to ease ATPG
2023 JETTA Reviewers
Incremental Design Debugging in a Logic Synthesis Environment
A fault simulation method: Parallel pattern critical path tracing
A New Algorithm for the Selection of Control Cells in Boundary-Scan Interconnect Test
Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees
Electron Beam Probing - A Solution for MCM Test and Failure Analysis
A Robust 130 nm-CMOS Built-In Current Sensor Dedicated to RF Applications
Performance Degradation Tolerance Analysis and Design for Effective Yield Enhancement
Diagnosing Multiple Byzantine Open-Segment Defects Using Integer Linear Programming
A structure and technique for pseudorandom-based testing of sequential circuits
Testing and Diagnosis of Realistic Defects in Digital Microfluidic Biochips
The Faults Diagnostic Analysis for Analog Circuit Based on FA-TM-ELM
Partial scan and symbolic test at the register-transfer level
A Secure and Robust PUF-based Key Generation with Wiretap Polar Coset Codes
A Systematic Bit Selection Method for Robust SRAM PUFs
Equivalent Circuit and Damage Threshold Study of Communication Interfaces under HEMP
Maximal Connectivity Test with Channel-Open Faults in On-Chip Communication Networks
Intermediacy Prediction for High Speed Berger Code Checkers
On the exact ordered binary decision diagram size of totally symmetric functions
Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors
Thermal-aware SoC Test Scheduling with Voltage/Frequency Scaling and Test Partition
CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator
Security Enhancements of a Mutual Authentication Protocol Used in a HF Full-Fledged RFID Tag
Efficient LFSR Reseeding Based on Internal-Response Feedback
Design of ICs applying built-in current testing
Integration of partial scan and built-in self-test
2023 JETTA-TTTC Best Paper Award
Embedded RF Circuit Diagnostic Technique with Multi-Tone Dither Scheme
Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems Architectures
Review of Manufacturing Process Defects and Their Effects on Memristive Devices
Dynamic effects in the detection of bridging faults in CMOS ICs
SC-COTD: Hardware Trojan Detection Based on Sequential/Combinational Testability Features using Ensemble Classifier
Structural Fault Based Specification Reduction for Testing Analog Circuits
Evaluating the safety of self-checking circuits
From Design Validation to Hardware Testing: A Unified Approach
Oscillation Test Strategy: A Case Study
Error Detection Enhancement in PowerPC Architecture-based Embedded Processors
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits During Test Application
Fault Diagnosis of Nonlinear Analog Circuits Using Neural Networks with Wavelet and Fourier Transforms as Preprocessors
Multichip systems trade-off analysis tool
The economics of scan-path design for testability
Test Technology Newsletter - December 2007
Side-Channel Information Characterisation Based on Cascade-Forward Back-Propagation Neural Network
2018 JETTA-TTTC Best Paper Award
A Novel Formalism for Partially Defined Asynchronous Feedback Digital Circuits
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
Finite state machine synthesis with embedded test function
Analysis of Resistive Open Defects in Drowsy SRAM Cells
Design and Temperature Reliability Testing for A 0.6-2.14GHz Broadband Power Amplifier
Wide Dynamic Range CMOS Amplifier Design for RF Signal Power Detection via Electro-Thermal Coupling
Reversible Gates and Testability of One Dimensional Arrays of Molecular QCA
LLVMVF: A Generic Approach for Verification of Multicore Software
Improving quality: Yield versus test coverage
Diagnostics of Filtered Analog Circuits with Tolerance Based on LS-SVM Using Frequency Features
A Method for Designing a Deterministic Test Pattern Generator Based on Cellular Automata
Scalable Delay Fault BIST for Use with Low-Cost ATE
Software-Based Testing for System Peripherals
A System-layer Infrastructure for SoC Diagnosis
Hierarchical multi-level fault simulation of large systems
Estimating Operational Age of an Integrated Circuit
An introduction to the boundary scan standard: ANSI/IEEE Std 1149.1
Formal Verification of Universal Numbers using Theorem Proving
A Cascaded Multicasting Architecture for Test Data Compression
Efficient Techniques for Fault Detection and Correction of Reversible Circuits
How Many Test Vectors We Need to Detect a Bridging Fault?
Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients
An On-Chip Sensor to Monitor NBTI Effects in SRAMs
SD2CI: A Structure-driven Approach for Detecting Silent Data Corruption Instructions
On-chip testing of random access memories
A Tunable Concurrent BIST Design Based on Reconfigurable LFSR
Real-Time Adaptive Test Algorithm Including Test Escape Estimation Method
Test and Reliability in Approximate Computing
Replacing I DDQ Testing: With Variance Reduction
TTTC Newsletter
High Performance Modified Static Segment Approximate Multiplier based on Significance Probability
Estimation of BIST Resources During High-Level Synthesis
Impact of Aging on the Reliability of Delay PUFs
Prediction of Long-term Immunity of a Phase-Locked Loop
Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling
E 3 C Techniques for Protecting NAND Flash Memories
Simulation Based Framework for Accurately Estimating Dynamic Power-Supply Noise and Path Delay
A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design
Efficient Realization of a Threshold Voter for Self-Purging Redundancy
PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories
Characterization of Floating Gate Defects in Analog Cells
A Low-cost Dithering Method for Improving ADC Linearity Test Applied in uSMILE Algorithm
Automated Functional Test Generation for Digital Systems Through a Compact Binary Differential Evolution Algorithm
Generation of Electrically Induced Stimuli for MEMS Self-Test
PrecIRisc: A High-Precision and Low-Bloat Dynamic Binary Instrumentation Tailored for RISC Architectures
Leakage-Aware Droop Measurement Built-in Self-Test Circuit for Digital Low-Dropout Regulators
Theorems for Fault Collapsing in Combinational Circuits
A Low-Cost Test Methodology for Dynamic Specification Testing of High-Speed Data Converters
Identification of Unknown Electromagnetic Interference Sources Based on Siamese-CNN
Security Analysis and Improvement of the Pseudo-random Number Generator Based on Piecewise Logistic Map
Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling
Discrete logarithms a parallel pseudorandom pattern generator analysis method
Exploring System Availability During Software-Based Self-Testing of Multi-core CPUs
Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current
Past TTTC Events
Efficient Error-Tolerability Testing on Image Processing Circuits Based on Equivalent Error Rate Transformation
Healing DNA Self-Assemblies Using Punctures
Monitoring machine based synthesis technique for concurrent error detection in finite state machines
Firmware-Driven Adaptive Clock Tuning for Electromagnetic Interference Tolerance in Automotive Systems
On the Delay of a CNTFET with Undeposited CNTs by Gate Width Adjustment
Design of testable sequential circuits by repositioning flip-flops
An Integrated Framework for Application Independent Testing of FPGA Interconnect
Evaluating the Impact of Temperature on Dynamic Fault Behaviour of FinFET-Based SRAMs with Resistive Defects
A Modified Simulation-Based Multi-Signal Modeling for Electronic System
Interconnect Reliability Analysis for Power Amplifier Based on Artificial Neural Networks
Handling Unknown with Blend of Scan and Scan Compression
A Parallel Tester Architecture for Accelerometer and Gyroscope MEMS Calibration and Test
Applications of Mixed-Signal Technology in Digital Testing
Soft Fault Classification of Analog Circuits Using Network Parameters and Neural Networks
Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering
BIST TPG for Combinational Cluster Interconnect Testing at Board Level
Fault simulation using small fault samples
Automation of Test Program Synthesis for Processor Post-silicon Validation
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits
Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools
Experimental and Simulation Results of Wien Bridge Oscillator Circuıt Realized wıth Op-Amp Designed Using a Memristor
Blind Calibration Method for Two-Channel Time-Interleaved Analog-to-Digital Converters Based on FFT
Application-Specific Bridging Fault Testing of FPGAs
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test
The Detection of Malicious Modifications in the FPGA
Multi-modal Pre-silicon Evaluation of Hardware Masking Styles
A structure for interconnect testing on mixed-signal boards
Hardware Trojan Detection Based on Logical Testing
On-Chip Pseudorandom MEMS Testing
Masking of X-Values by Use of a Hierarchically Configurable Register
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems
Online Testable Approaches in Reversible Logic
Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems
Area Minimization of Exclusive-OR Intensive Circuits in FPGAs
Reducing Test Time in the High-Volume Production of Analog Circuits using Efficient Test-Vector Generation and Interpolation Techniques
LoBA: A Leading One Bit Based Imprecise Multiplier for Efficient Image Processing
Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Multiple Error Correction Coding
A Statistical Sampler for a New On-Line Analog Test Method
Oscillation Ring Delay Test for High Performance Microprocessors
On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs
Using both Stable and Unstable SRAM Bits for the Physical Unclonable Function
New Editors - 2019
Low Cost Sparse Multiband Signal Characterization Using Asynchronous Multi-Rate Sampling: Algorithms and Hardware
Next Generation ADC Massive Parallel Testing with Real Time Parameter Evaluation
A Level-Crossing Approach for the Analysis of RF Modulated Signals Using Only Digital Test Resources
Structural Test Approach for Embedded Analog Circuits Based on a Built-in Current Sensor
The probability of error detection in sequential circuits using random test vectors
An Asynchronous Design for Testability and Implementation in Thin-film Transistor Technology
Scalable and Optimized Hybrid Verification of Embedded Software
High-Level Test Synthesis for Behavioral and Structural Designs
Multiple Retest Systems for Screening High-Quality Chips
Generating Synthetic Layout Test Patterns using Deep Learning
A New Approximate 4-2 Compressor using Merged Sum and Carry
New Light Weight Threshold Voltage Defined Camouflaged Gates for Trustworthy Designs
Feedback-testing by using multiple input signature registers
A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology
An architectural level test generator based on nonlinear equation solving
Tree-Structured Linear Cellular Automata and Their Applications in BIST
Spot Defect Diagnosis in Analog Nonlinear Circuits with Possible Multiple Operating Points
Identifying Resistive Open Defects in Embedded Cells under Variations
Testing Signals for Electronics: Criteria for Synthesis
Fault Table Computation on GPUs
Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes
Noise-Insensitive Digital BIST for any PLL or DLL
A switch-level test generation system for synchronous and asynchronous circuits
An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic
Noise and Spur Comparison of Delta-Sigma Modulators in Fractional-N PLLs
A new DFT methodology for sequential circuits
An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch
On Efficiently Producing Quality Tests for Custom Circuits in PowerPC TM Microprocessors
Economic modeling of board test strategies
A Systematic Method for Arranging Diagnostic Tests in Linear Analog DC and AC Circuits
Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits
Speeding Up Logic Locking via Fault Emulation and Dynamic Multiple Fault Injection
Statistical Tolerance Analysis for Assured Analog Test Coverage
Crosstalk Induced Fault Analysis and Test in DRAMs
Zero aliasing ROM BIST
BISCC: A Novel Approach to Built In State Consistency Checking For Quick Volume Validation of Mixed-Signal/RF Systems
Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features
A general purpose design-for-test methodology at the analog-digital boundary of mixed-signal VLSI
A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models
Multi-Directional Space Tessellation to Improve the Decision Boundary in Indirect Mixed-Signal Testing
Practical Analog Circuit Diagnosis Based on Fault Features with Minimum Ambiguities
Enhanced Reduced Pin-Count Test for Full-Scan Design
An Output Response Analyzer Circuit for ADC Built-in Self-Test
Optimization Methods for Post-Bond Testing of 3D Stacked ICs
Testing of Low-cost Digital Microfluidic Biochips with Non-Regular Array Layouts
Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering
Initialization issues in asynchronous circuit synthesis
Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach
Exact probabilistic testability measures for multi-output circuits
Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing
On the Simulation of HCI-Induced Variations of IC Timings at High Level
Physics-Based Low-Cost Test Technique for High Voltage LDMOS
Improving Testability of Non-Scan Designs during Behavioral Synthesis
Diagnosis of leakage faults with IDDQ
Optimization of a Particles Detection Chain Based on a VCO Structure
Analog Circuits Fault Detection Using Cross-Entropy Approach
Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique
Autonomous Fault-Tolerant Systems onto SRAM-based FPGA Platforms
New Editor - 2020
Testing and Diagnosis Methodologies for Embedded Content Addressable Memories
Why is Combinational ATPG Efficiently Solvable for Practical VLSI Circuits?