yusuke1997/dblp-id-title huggingface dataset:
Improvement of Negative Bias Temperature Instability Circuit Reliability and Power Consumption Using Dual Supply Voltage
Selected Articles from the 6th International Workshop on CMOS Variability, Salvador, Bahia, Brazil, September 1-4, 2015
Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems
On-Chip Process Variability Monitoring Flow
A High Gain Dual Stage Converter for Driving Dielectric Elastomer Actuators in Microrobotic Applications
A Markovian Decision-Based Approach for Extending the Lifetime of a Network of Battery-Powered Mobile Devices by Remote Processing
Power Management Design and Verification
Design of a Ternary Edge-Sensitive D FFF for Multiple-Valued Sequential Logic
An Efficient Assignment of Voltages and Optional Cycles for Maximizing Rewards in Real-Time Systems with Energy Constraints
Energy-Efficient Retiming and Scheduling of Datapath-Dominant Digital Systems
Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques
Impact of High- Spacer on Junctionless Transistor in Sub-Threshold Regime
Design and Analysis of Location Caches in a NoC-Based Chip Multiprocessor System
Selected Peer-Reviewed Articles from the 4th European Workshop on CMOS Variability, Karlsruhe, Germany, September 9-11, 2013
Dielectric Losses Considerations for Piezoelectric Energy Harvesting
Robust Double Gate FinFET Based Sense Amplifier Design Using Independent Gate Control
Experimental RF Characteristics of Hot-Carrier-Stressed p-core Dual-Band VCO
Field Programmable Gate Array and System-on-Chip Based Implementation of Discrete Fast Walsh-Hadamard Transform Domain Image Watermarking Architecture for Real-Time Applications
Automatic and Correct Register Transfer Level Annotations for Low Power Microprocessor Design
A Bit-Interleaved 2-Port Subthreshold 6T SRAM Array with High Write-Ability and SNM-Free Read in 90 nm
Precision Low Voltage and Current References
Ensuring Power-Safe Application of Test Patterns Using an Effective Gating Approach Considering Current Limits
Achieving High Efficiency Under Micro-Watt Loads with Switching Buck DC-DC Converters
Low Power and Area Efficient Carry Select Adder
Switched-Capacitor Based Buck Converter Design Using Current Limiter
Low Energy Bus Design with Error Tolerant Coding
A Multi-Stage Low-Dropout Regulator with 1 pF Compensation Capacitor for System-on-Chip Applications
A Load-Store Queue Design Based on Predictive State Filtering
Low-Power Coding: Trends and New Challenges
Design Techniques for Micro-Power Algorithmic Analog-to-Digital Converters
Design of a High Efficiency, Wide Input Range 500 kHz 25 W LLC Resonant Converter
Scan Shift Power Reduction by Gating Internal Nodes
Variability Characterisation of Nanoscale Si and InGaAs Fin Field-Effect-Transistors at Subthreshold
Probability-Based Optimal Sizing of Power-Gating Transistors in Full Adders for Reduced Leakage and High Performance
A 140 mV Self-Starting 10 mW DC/DC Converter for Powering Low-Power Electronic Devices from Low-Voltage Microbial Fuel Cells
Simulation of 2 Bit by 2 Bit Binary Multiplier Using Magnetic Tunnel Junction Device
Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test
Selected Articles from the IEEE ISED 2016 Conference
On the Interaction between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays
ARTL-Based Hardware Synthesis to Non-Heterogeneous Standard Cell ASIC Technologies
A 1 V 270 My-W 2 GHz CMOS Synchronized Ring Oscillator Based Prescaler
Low Power Flip-Flop Design Using Tri-State Inverter Logic
Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit
A Versatile High-Swing G m -C Filter with Process and Temperature Invariant Bandwidth and Gain for Neuro-Potential Signal Conditioning and Recording
Heuristics to Augment the Performance of Tetris Legalization: Making a Fast but Inferior Method Competitive
A Parallel and Randomized Algorithm for Large-Scale Discrete Dual-Vt Assignment and Continuous Gate Sizing
Noise Minimization for Low Power Bandgap Reference and Low Dropout Regulator Cores
Low Power Data Driven Conditional Precharge Dynamic Flip Flop
Improvement of Performance of Dynamically Reconfigurable Switched Capacitor Based Non-Overlap Rotational Time Interleaved Embedded DC-DC Converter
Complete Study for Diagonal Triboelectric Nanogenerators Based Energy Harvester with Computer Aided Design Tool
PAID: Process Aware Imprecise DCT Architecture Trading Quality for Energy Efficiency
Algorithm/Architecture Co-exploration for Designing Energy Efficient Wireless Channel Estimator
Energy-Aware Task Scheduling and Dynamic Voltage Scaling in a Real-Time System
Heterogeneous Interconnect for Low-Power Snoop-Based Chip Multiprocessors
A 50 μ W Microbial Fuel Cell Isolated Energy Harvesting Interface Based on Air Coupled Inductors
Design and Test of a Novel Programmable Clock Generator Semi-Custom Core for Energy-Efficient Systems-on-Chips
An Ultra-Low Power CMOS Temperature Sensor for Passive RFID Application
Low Energy ASIC Elliptic Curve Processor
A Comparative Analysis of Single Switch Soft-Switching Boost Converter and Interleaved Soft-Switching Boost Converter
A 46 nW Power Management Unit with Battery Extender for Solar Energy Harvesters Using 0.18 μ m CMOS
Evaluation of an Adaptive Dynamic Voltage Scaling Scheme for Hard Real-Time Applications
Architectural Optimization of Hierarchically Organized Wireless Sensor Networks for Energy, Cost, and Security
0.5V Sinh-Domain Design of Activation Functions and Neural Networks
On-Line Predictive Thermal Management Under Peak Temperature Constraints for Practical Multi-Core Platforms
A Novel Design for 4-Bit Code Converters in Quantum Dot Cellular Automata
Computation Partitioning and Reuse for Power Efficient High Performance Digital Signal Processing
Low Power Approximate Multipliers for Energy Efficient Data Processing
A Novel Low Power Oriented Design Methodology for Analog Blocks
Resilient Cache Design for Mobile Processors in the Near-Threshold Regime
An Architecture Using Lighter-Than-Air Platforms for Retail Power Beaming and Communications
A New High Radix-2 r ( r ≥ 8) Multibit Recoding Algorithm for Large Operand Size ( N ≥ 32) Multipliers
Design and Characterization of Low Power and Low Noise Truly All-Digital Clock and Data Recovery Circuit for SERDES Devices
On-Line BIST for Performance Failure Prediction Under NBTI-Induced Aging in Safety-Critical Applications
A Low-Power and Highly Linear Merged Low Noise Amplifier-Mixer for Wireless Sensor Network Applications
A Retrospective View on the Technology Evolution to Support Low Power Mobile Application
An Efficient Energy Estimation Methodology for Quasi Delay Insensitive Template-Based Asynchronous Circuits
Scan-Based Structure with Reduced Static and Dynamic Power Consumption
Comparing Leakage Reduction Techniques for an Asynchronous Network-on-Chip Router
Studying the Influence of Chip Temperatures on Timing Integrity Using Improved Power Modeling
A Charge Amplifier Based Complementary Metal-Oxide-Semiconductor Analog Front End for Piezoelectric Microphones in Hearing Aid Devices
Differential AC Boosting Compensation for Power-Efficient Multistage Amplifiers
Energy and Power Consumption Estimation for Embedded Applications and Operating Systems
Trading Time and Space on Low Power Embedded Architectures with Dynamic Instruction Merging
Performance Evaluation and Design Optimization for Flexible Multiple Instruction Multiple Data Elliptic Curve Cryptography Crypto Architecture
A Novel Design of Seven Segment Decoder Using Cyclic Combinational Technique
Compact and Secured Primitives for the Design of Asynchronous Circuits
Low Area and Low Power Implementation for Competition for Authenticated Encryption, Security, Applicability, and Robustness Authenticated Ciphers
A Paradigm Shift in Passive Radio Frequency Identification Tag Development and Manufacturing Flexibility to Provide Active Tag Functionality
12th "IEEE Latin-American Test Workshop" Porto de Galinhas, Brazil, 27-30 March 2011
Low Power Test for Nanometer System-on-Chips (SoCs)
Fully Differential Operational Transconductance Amplifier with Enhanced Phase Margin and Gain for Ultra-Low-Power Circuits
Energy Saving Mechanism Based on 4-Mode Dynamic Bandwidth Optimization for Software Defined Distribution Optical Networks
Thermal Model with Metal Consideration for System-on-Chip Testing
Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels
A Special Issue on the "22nd IEEE International Conference on VLSI Design" New Delhi, India, 5-9 January 2009
Multiclock Domain and Dynamic Frequency Scaling Applied to the Control Unit of a Battery Powered for 1 cm3 Microrobot
Selected Peer-Reviewed Articles from the 14th IEEE Latin-American Test Workshop, Cordoba, Argentina, April 3-5, 2013
Design and Implementation of a USB Device Controller with the Power Management Unit
VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder
Layout-Aware Transition-Delay Fault Pattern Generation with Evenly Distributed Switching Activity
Ultra-Low Power Successive Approximation Analog-to-Digital Converter Using Emerging Tunnel Field Effect Transistor Technology
Selecting Error Correcting Codes to Minimize Power in Memory Checker Circuits
Exploring Very Low-Energy Logic: A Case Study
DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM
2-Channel Electroencephalography Sensor Frontend for Portable Health Condition Monitoring Applications
Specialization: A New Path Towards Low Power
A Low-Power High-Efficiency Inductive Link Power Supply for Neural Recording and Stimulation System-on-Chip
Power Consumption versus Hardware Security: Feasibility Study of Differential Power Attack on Linear Feedback Shift Register Based Stream Ciphers and Its Countermeasures
Selected Articles from the 7th International Workshop on CMOS Variability Bremen, Germany, September 21-23, 2016
Low-Power Hierarchical Scan Test for Multiple Clock Domains
RF Module Design of Passive UHF RFID Tag Implemented in CMOS 90-nm Technology
Cooperative Relay Transmission in Advanced Metering Infrastructure with Wireless Attacks
Hybrid-CV Modeling for Estimating the Variability in Dynamic Power
A 0.5 V Low-Power All-Digital Phase-Locked Loop in 65 nm Complementary Metal-Oxide-Semiconductor Process
Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs
Reducing Instruction Translation Look-Aside Buffer Energy Through Compiler-Directed Resizing
A Low Cost System for Self Measurements of Power Consumption in Field Programmable Gate Arrays
An Efficient Methodology for Full Chip Signal ElectroMigration Analysis for Advanced Technology Node Designs
Energy-Efficient Techniques for Disk-Based Mobile Systems
Design of a New Electrical Model of Integrated LC Filter in DC-DC Converter
Design Equivalent Scaling on Double Gate FinFET Towards Analog and RF Figures of Merits: A Technology Computer Aided Design Estimation
State Assignment and Polarity Selection for Low Dynamic Power and Testable Finite State Machine Synthesis
Energy-Aware Dual-Rail Bit-Wise Completion Pipelined Arithmetic Circuit Design
Strategies of Maximum Power Point Tracking for Sub-mW Benthic Microbial Fuel Cells
An Optimal Resource Binding Algorithm with Inter-Transition Switching Activities for Low Power
Characterization of Variation Aware Nanoscale Static Random Access Memory Designs
Design and Analysis of Clocked CMOS Differential Adiabatic Logic (CCDAL) for Low Power
XStat: Statistical X -Filling Algorithm for Peak Capture Power Reduction in Scan Tests
Novel SAT-Based Peak Dynamic Power Estimation for Digital Circuits
Online Inertia-Based Temperature Estimation for Reliability Enhancement
An On-Board Step-Down DC/DC Converter for System-On-Chip Power-Supply Strategy
Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies
Differential Cascode Adiabatic Logic Structure for Low Power
An Efficient Single Phase Adiabatic Logic and Its Application to Combinational and Sequential Design
Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns
Energy-Efficient Reconfigurable Hardware Accelerators for Data-Intensive Applications
Spintronic Memristor: Compact Model and Statistical Analysis
Co-Exploration of Unit-Time Leakage Power and Latency Spaces for Leakage Energy Minimization in High-Level Synthesis
Design of a Low Voltage High Symmetrical Slew Rate Opamp Based on Self Cascode in UMC 0.18 μ m
Low Cost Dynamic Architecture Adaptation Schemes for Drowsy Cache Management
A Low Power Design Space Exploration Methodology Based on High Level Models and Confidence Intervals
Design of Cascode Mixer Based on Bulk Injection and Switched Biasing Techniques in 180 nm CMOS Process for a High Performance Receiver Front End
Asymmetric Underlap Dual Material Gate DG-FET for Low Power Analog/RF Applications
An Asynchronous Sigma Delta Analog to Digital Converter for Broadband Wireless Receiver with Adaptive Digital Filtering Technique
Log-Domain Implementation of QRS Detection System Using the Pan-Tompkins Algorithm with Fractional-Order Differentiator for Improved Noise Rejection
Design and Implementation of an Area and Power Efficient Switched-Capacitor Based Embedded DC-DC Converter
Modified Design and Analysis of a Performance Optimized Common Gate LNA for Low Power Wireless Sensor Network Applications
Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce
Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology
Sub-Threshold Delay and Power Analysis of Complementary Metal-Oxide Semiconductor Buffer Driven Interconnect Load for Ultra Low Power Applications
Investigation and Optimization of Spiral Inductor Design for On-Chip Buck Converter
Test Strategies for Low-Power Devices
Low Power Task Scheduling and Mapping for Applications with Conditional Branches on Heterogeneous Multi-Processor System
Fuzzy Control of Coding Schemes for Reducing Energy Dissipation in Off-Chip Buses
Energy Efficient Array Computations Using Loop Unrolling with Partial Gray Code Sequence
Variability Influence on FinFET-Based On-Chip Memory Data Paths
On Reliability Trojan Injection and Detection
Accurate Polynomial Metamodeling-Based Ultra-Fast Bee Colony Optimization of a Nano-CMOS Phase-Locked Loop
Low Power Current Conveyor Based Continuous Time Sigma Delta Modulator
Selected Articles from the ISED 2018 Conference
A Novel Shared Active Pixel Architecture (SAPA) with Low Dark Current and High Fill-Factor (FF) for CMOS Image Sensors
Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions
Ultra-Low-Power Digital Design with Body Biasing for Low Area and Performance-Efficient Operation
Analyzing and Improving Performance and Energy Efficiency of Android
Magnetic Tunnel Junction Reliability Assessment Under Process Variations and Activity Factors and Mitigation Techniques
Reinforcement-Learning Approach Guidelines for Energy Management
CNOT Gate Optimizations via Qubit Permutations for IBM's Quantum Architectures
2-Bit Full Adder Implementation Using Single Spin Logic Paradigm
Selected Articles from VDAT 2017 Conference
Digital Sliding Mode Control of DC-DC Buck Converters
Low-Voltage Low-Power Broadband CMOS Analogue Circuit for White Gaussian Noise Generation
Improved Wire Length-Driven Placement Technique for Minimizing Wire Length, Area and Timing
Prospects of 2D Junctionless Channel Transistor (JLCT) Towards Analog and RF Metrics Using Si and SiGe in Device Layer
The Design of Reversible Signed Multiplier Using Ancient Indian Mathematics
Impact of Operating System Behavior on Battery Life
Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata
ReMap: A Novel Automated Peephole Optimization Based Approach for Logic, Delay and Power Minimization
Power-Efficiency of Signal Processing Circuits in Implantable Multichannel Brain-Machine Interface
Smart Coulomb Counter for Self-Metering Wireless Sensor Nodes Consumption
Novel Adaptive Body Biasing Techniques for Energy Efficient Subthreshold CMOS Circuits
Diagnostic Test Sets with Increased Switching Activity for Transition Faults
Cyber-Physical Thermal Management of 3D Multi-Core Cache-Processor System with Microfluidic Cooling
A Compact Two Dimensional Analytical Modeling of Nanoscale Fully Depleted Dual Material Gate Strained SOI/SON MOSFETs for Subdued SCEs
A 12-Bit Ultra-Low Voltage Noise Shaping Successive-Approximation Register Analogto-Digital Converter Using Emerging TFETs
A Design Technique for Power Constrained CMOS Low-Noise Amplifier Dedicated to Wireless Sensor Networks
Design Matrix Analysis for Capacitive Interpolation Flash ADC
An Integrated Approach for Fine-Grained Power and Peak Temperature Management During High-Level Synthesis
Pushing Adaptive Voltage Scaling Fully on Chip
Temperature Effects on Practical Energy Optimization of Sub-Threshold Circuits in Deep Nanometer Technologies
Automation of Switch Insertion and Power Network Generation in 28 nm Power-Switched Designs
Design of an Ultra-Low-Power Multi-Stage AC/DC Voltage Rectifier and Multiplier Using a Fully-Automated and Portable Design Methodology
Novel ASIC Design Flow Using Dynamic Libraries for Reducing Design Time
Instruction-Based Voltage Scaling for Power Reduction in SIMD MPSoCs
Thermal Modeling of a Spiral Planar Inductor
Scheduling on CPU + GPU Processors Under Dynamic Conditions
Lethargic Cache: A Low Leakage Direct Mapped Cache
A Scalable and Adaptive Technique for Compensating Process Variations and Controlling Leakage and Delay in the FPGA
A Modular Framework for Battery Modeling in Electronic Designs
Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific Multiprocessor System-on-Chip
Ćuk Step-Down Converter Design for Optimum Transient Performance and Minimum Ripple
Low Power Electronic System for Tactile Sensory Feedback for Prosthetics
An Optimum Body Biasing for Gain and Linearity Control in CMOS Low-Noise Amplifiers
Low-Energy and Secure Aggregation of Uncorrelated Data in Clustered Sensor Network
A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter
Gated Clock Tree Circuit to Reduce the Noise in Silicon Chip
An Innovative Low Power Full Adder Design in Nano Technology Based Quantum Dot Cellular Automata
Smart and Fault-Tolerant LED-Based Street Lamps
A Novel Methodology for Design of Cyclic Combinational Circuits
A Novel Error Detection Strategy for a Low Power Low Noise All-Digital Phase-Locked Loop
A Workload Based Lookup Table for Minimal Power Operation Under Supply and Body Bias Control
Investigations on Short-Circuit Power Dissipation in Repeater Loaded VLSI Interconnects
Energy-Aware Compilation for Embedded Processors with Technology Scaling Considerations
MemExplorer: From C Code to Memory Allocation
Subthreshold to Above Threshold Level Shifter Design
Energy Management in Wireless Mobile Systems Using Dynamic Task Assignment
Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems
Impact of Power Consumption and Temperature on Processor Lifetime Reliability
Design of Low Power Systems Using Inexact Logic Circuits
Leakage Current Improvement for a Voltage Doubler Charge Pump
Selected Peer-Reviewed Articles from the LPonTR 2008 Workshop
A Sub-1 V 100 mA Wide Capacitive Load Based Flipped Voltage Follower Low-Dropout Regulator Using Transient-Assisted Embedded Driving Stage
Read and Write Analysis for Balanced Pattern Memristor Crossbar Array
On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores
Early Quality Assessment for Low Power Behavioral Synthesis
Low-Power Bluetooth Receiver Front End Design with Oscillator Leakage Reduction Technique
Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations
Designing Energy-Efficient Arithmetic Operators Using Inexact Computing
An Efficient Heuristic for Peak Capture Power Minimization During Scan-Based Test
Lithography Simulation Basics and a Study on Impact of Lithographic Process Window on Gate and Path Delays
Non-Volatile Flip-Flop Based on Unipolar ReRAM for Power-Down Applications
Low Power Radio Frequency Transceiver with Built-In-Tuning of the Local Oscillator for Open Loop Modulation
An Enhanced Design Methodology for Resonant Clock Trees
Pre-Layout Decoupling Capacitance Estimation and Allocation for Noise-Aware Crypto-System on Chip Applications
Reducing Electromagnetic Interference Using Globally Asynchronous Locally Synchronous Approach
An Efficient Analog-to-Digital Converter Based on Carbon Nanotube FETs
Resource Management in Heterogeneous Wireless Sensor Networks
Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures
Energy-Efficient Value Based Selective Refresh for Embedded DRAMS
Research of Optimization for Transmission Power and Transfer Efficiency of the Loosely Coupled Wireless Charging System
Design of Low Power Adiabatic SRAM Using DTGAL, CPAL and ACPL: A Comparative Study
A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops
A Versatile High Swing Current Mode Instrumentation Amplifier with an Integrated Band-Pass Filter for Bio-Potential Signal Acquisition
1.2 V Single Supply CMOS Level-Up Shifter for Low Energy Systems
Tuning V th Hopping for Aggressive Runtime Leakage Control
A Novel Approach of Full Adder and Arithmetic Logic Unit Design in Quantum Dot Cellular Automata
On-line Power Optimization of Data Flow Multi-Core Architecture Based on Vdd-Hopping for Local Dynamic Voltage and Frequency Scaling
Thermal-Aware Design Techniques for Nanometer CMOS Circuits
Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits
Effect of Traps on the Performance of Nanowire Si Junctionless Tunnel FET
Field Programmable Gate Array Softcore Processors Optimised for Digital Signal Processing Applications
PVT: Unified Reduction of Test Power, Volume, and Test Time Using Double-Tree Scan Architecture
Selected Articles from the PATMOS 2010 Workshop
Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells
Performance Analysis of Subthreshold Cascode Current Mirror in 130 nm CMOS Technology
Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply
Selected Articles from the IEEE ISED 2014 Conference
Design of a Low Leakage, Low Power and High Performance Search and Read Memory Using CAM and SRAM
Selective Clock-Gating for Low-Power Synchronous Counters
Multi-Stage Noise Shaping ΔΣ Modulator with Enhanced Noise Shaping for Low Power Wideband Applications
Power-Yield Enhancement for Field Programmable Gate Arrays Under Process Variations
A Profile for GPS Data Reliable Transmission Based on Bluetooth Low Energy
A New Recursive Multibit Recoding Algorithm for High-Speed and Low-Power Multiplier
Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage Variation on the Timing
Energy Consumption by Reversible ircuits in the 130 nm and 65 nm Nodes
A Framework to Compare Estimated and Measured Power Consumption on FPGAs
Low Power and High Performance Arithmetic Circuits in Feedthrough CMOS Logic Family for Low Power Applications
An Advanced Low Power and Versatile CMOS Current Driver for Multi-Electrode Cochlear Implant Microstimulator
Inclusion of Power Consumption Information in High-Level Modeling of Linear Analog Blocks
A Novel Integrated Circuit Design Methodology Using Dynamic Library Concept with Reduced Non-Recurring Engineering Cost and Time-to-Market
Ultra-Low-Power Audio Communication System for Cochlear Implant Application
Low-Power Circuit Techniques for Charge-Scaling Successive Approximation Register ADC Design