yusuke1997/dblp-id-title huggingface dataset:
Microprocessor based distributed control systems: Kalani, G Prentice-Hall, Hemel Hempstead, UK (1988) £19.95
Advanced C 2 MOS speech synthesizers
Microcomputer position control system
Searching and learning english translation long text information based on heterogeneous multiprocessors and data mining
SOP restructuring by exploiting don't cares
Automated design debugging in a testbench-based verification environment
Design and coverage-driven verification of a novel network-interface IP macrocell for network-on-chip interconnects
Big data application in exchange rate financial prediction platform based on FPGA and human-computer interaction
Annex cache: a cache assist to implement selective caching
Finding small feedback vertex sets for VLSI circuits
Parallel implementations of convolution and moments algorithms on a multi-transputer system
The routing problem in transputer-based parallel systems
Designing an ultra-efficient Hamming code generator circuit for a secure nano-telecommunication network
A conceptual framework for quantum accelerated automated design optimization
BACH: a hardware monitor for tracing microprocessor-based systems
Software for a simple two-axis numerical control system
On the nature of deadlines
CNFET-based approximate ternary adders for energy-efficient image processing applications
Wearable sensors for gait pattern examination in glaucoma patients
CalmRISC TM : a low power microcontroller with efficient coprocessor interface
VLSI implementation of ultra power optimized adiabatic logic based full adder cell
A parallel solution to linear systems
Energy-aware preemptive scheduling algorithm for sporadic tasks on DVS platform
Three counter value based ROPUFs on FPGA and their properties
Register port complexity reduction in wide-issue processors with selective instruction execution
Powerful trace facility for the MC68000 microprocessor system
Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware
A novel modified GDI method-based clocked M/S-TFF for future generation microprocessor chips in nano schemes
LOGO as a programming environment: Martin Lesser 'LOGO for micros' Newnes Books, Feltenham, UK (1985) £7.95 pp 186
DGA: Distributed geographic-sensing addressing method for linear-zone internet of things
An adaptive write error detection technique in on-chip caches of multi-level caching systems
An efficient adaptive block pinning for multicore architectures
Compact FPGA architectures for the two-band fast discrete Hartley transform
BEE: a special-purpose machine for hardware description languages
Application of CTRON to communication networks
VME bus user's handbook: Heath, S Heinemann Newnes, Oxford, UK (1989) pp266
Rising above the run-of-the-mill introduction to microprocessors: H S Stone 'Microcomputer interfacing' Addison Wesley (1982) £9.95, pp 383
Microprocessors and microcomputers: The 6800 family: Ronald J Tocci and Lester P Laskowski Prentice-Hall, Englewood Cliffs, NJ, USA (1986) £36.35 pp xiii + 497
Operating system power minimization through run-time processor resource adaptation
Introduction to the special section on "Sustainable processor architectures and applications"
High performance hardware architecture for singular spectrum analysis of Hankel tensors
Motivated humans for reliable software products
Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs
Microcomputing into the 80s
Low-cost A/D and D/A interface card for the Apple II microcomputer
SmartDelta project: Automated quality assurance and optimization across product versions and variants
TOPSIS model with entropy weight for eco geological environmental carrying capacity assessment
STi 3220 motion estimation processor
Resource optimized quantum architectures for surface code implementations of magic-state distillation
An energy-aware self-adaptive System-on-Chip architecture for real-time Harris corner detection with multi-resolution support
P4-To-VHDL: Automatic generation of high-speed input and output network blocks
Implementation of a microcontroller-based simplified FITA-FIS model
Proactive deadlock prevention based on traffic classification sub-graphs for triplet-based NoC TriBA-cNoC
Mapping artificial neural networks to a tree shape neurocomputer
Securing VPN from insider and outsider bandwidth flooding attack
Cyber-physical systems security: Limitations, issues and future trends
Corpus English word detection and image recognition algorithm based on improved convolutional neural network
Intelligent control for new topological structure of Z-Source inverter based on ARM
Optimized high-order finite difference wave equations modeling on reconfigurable computing platform
Bitmask-based code compression methods for balancing power consumption and code size for hard real-time embedded systems
Leak-Gauge: A late-mode variability-aware leakage power estimation framework
Optimizing function distribution in a terminal network
FFT - fRISCy fourier transforms?
Improved ring oscillator PUF on FPGA and its properties
ARM3 - a study in design for compatibility
Stability degree of switches with finite buffers and non-negligible round-trip time
Image singular points extraction in wavelet domain based on key exchange algorithm
A DSP-based video compression test-bed
Template attack vs. stochastic model: An empirical study on the performances of profiling attacks in real scenarios
Real-time emulation and analysis of multiple NAND flash channels in solid-state storage device
Modeling of an efficient high power wind energy conversion system using self-excited multi-phase machines
Evaluation of dynamic branch predictors for modern ILP processors
A real-time heuristic search technique for fixed channel allocation (FCA) in mobile cellular communications
Simulation study of the impact of technology on cache memory performance
Superlattices
Mechanism of rainfall induced landslides in Yunnan Province using multi-scale spatiotemporal analysis and remote sensing interpretation
An efficient VLSI implementation of IDEA encryption algorithm using VHDL
MLC NAND Flash memory: Aging effect and chip/channel emulation
Data flow oriented control law design with the graphical language HOSTESS
Research on recognition of ice and snow athletes based on feature extraction and cloud computing platform
CoNNa-Hardware accelerator for compressed convolutional neural networks
ASIC implementation of a programmable error-trapping decoder for binary codes of length 15
Simulation of police shooting stability training based on FPGA and sensors
Traffic shaper: required system for an ATM microprocessor adapter
Denoising method of low illumination underwater motion image based on improved canny
Sports image detection based on FPGA hardware system and particle swarm algorithm
Modular approach to colour graphics system design: hardware aspects
Design and implementation of fault-tolerant multimicrocomputer systems
Target detection algorithm and data model optimization based on improved Gaussian mixture model
A robust wire crossing design for thermostability and fault tolerance in quantum-dot cellular automata
The poplog program development system
A gateway development system
Transputer applications in robotics for dynamic modelling and path planning
Research on the HRM performance assessment model based on FPGA embedded system and bayesian network
TRESC: Towards redesigning existing symmetric ciphers
Communications in microprocessor industrial implementation
An on-chip instruction cache design with one-bit tag for low-power embedded systems
A robust secure speech communication system using ITU-T G.723.1 and TMS320C6711 DSP
Failures in fault-tolerant FPGA-based controllers - A case study
Multicomputer-controlled terminal switching system
Systems integration with reliability in mind
Object-oriented experiences with ERIC
Concurrent Programming in Occam 2: Wexler, J Ellis Horwood (1989) £33.50, ISBN 013-161-7389
Example of design using structured programming
Implementation of a modified Fuzzy C-Means clustering algorithm for real-time applications
Scenario-based quasi-static task mapping and scheduling for temperature-efficient MPSoC design under process variation
Computer architecture - software and hardware, volumes 1 and 2: R Y Kain Prentice Hall, Englewood Cliffs, NJ, USA (1989) £19.95 (each volume)
Effects of RPL objective functions on the primitive characteristics of mobile and static IoT infrastructures
Embedding Recurrent Neural Networks in Wearable Systems for Real-Time Fall Detection
logo programming: P RossAddison-Wesley, Reading, MA, USA (July 1983) £8.95, pp 249
Model and analysis of single event transient sensitivity based on uncertainty quantification
Low-overhead inverted LUT design for bounded DNN activation functions on floating-point vector ALUs
An efficient and scalable parallel mapping of pulse-Doppler radar signal processing chain on a multi-core DSP
A prototype model of unmanned automatic level crossing system using piezoelectric sensor
Design and simulation of priority based dual port memory in quantum dot cellular automata
An early-stage statement-level metric for energy characterization of embedded processors
Adaptive voltage scaling in a heterogeneous FPGA device with memory and logic in-situ detectors
CISC, RISC and DSP processors in real-time signal processing and control
Programming language methodologies: Carol A Ziegler, Prentice-Hall, Englewood Cliffs, NJ, USA (1983) £20.65 pp 260
1, 2, 3, my computer and me: D BeardenPrentice-Hall, Englewood Cliffs, NJ, USA (August 1983) £9.85
Selected papers from the 2nd IEEEE Nordic Circuits and Systems Conference (NorCAS), 2016
A processor for IoT applications: An assessment of design space and trade-offs
Technology choice for high-speed applications - GaAs or silicon
A low-area dynamic reconfigurable MDC FFT processor design
Overview of CP/M assembler programming will serve newcomers to the system: L E Hughes 'System programming under CP/M-80' Reston Publishing Co., Reston, VA, USA (1983) £13.55 pp 197
Memory system design
High throughput unified architecture of LEA algorithm for image encryption
CRANarch: A feasible processor micro-architecture for Cloud Radio Access Network
A cost-effective design for a mid-range microcontroller-based lock-in amplifier
Message replication on IEEE 1355 serial links
Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration
Civil engineering stability inspection based on computer vision and sensors
Extending MODULA-2 for object-oriented programming
Route manipulation aware Software-Defined Networks for effective routing in SDN controlled MANET by Disney Routing Protocol
Tradeoff between the cycle complexity and the fairness of ring networks
Higher security of ASIC fabrication process against reverse engineering attack using automatic netlist encryption methodology
Applying frame layout to hardware design in FPGA for seamless support of cross calls in CPU-FPGA coupling architecture
Two-bit microcomputer for educational use
Regional agricultural industry economic development based on embedded system and Internet of Things
Microprocessor design faults
Research on nano-CT medical image processing based on embedded system
Reconfigurable address generator for multi-standard interleaver
Full wireless goniometer design with activity recognition for upper and lower limb
The AXIOM platform for next-generation cyber physical systems
Self-healing reconfigurable logic using autonomous group testing
Processor architecture exploration and synthesis of massively parallel multi-processor accelerators in application to LDPC decoding
A performance evaluation of cache injection in bus-based shared memory multiprocessors
Advanced 16-bit operating system handles multiple tasks in real time
Testing semiconductor memories, theory and practice: van de Goor, A J John Wiley, Chichester, UK (1991) £34.99 pp 536 ISBN 0 471 92586 1, 0 471 92587 X (disc)
Using the 54/74LS610-13 memory mapping units
A microprocessor based fully digital AC servo drive
Design of Differential LNA and Double Balanced Mixer using 180 nm CMOS Technology
Transputer-based dataflow multiprocessor for robot arm control
Design techniques with microprocessors
AE-LEACH: An Incremental Clustering Approach for Reducing the Energy Consumption in WSN
Design of an efficient dual mode reconfigurable FIR filter architecture in speech signal processing
Energy-aware fixed priority scheduling with shared resources in standby-sparing systems
Reusable generic design patterns for mixed-criticality systems based on DREAMS
Next generation antivirus endowed with bitwise morphological extreme learning machines
Microprocessor programming and applications for scientists and engineers: R R Smardzewski Elsevier, Amsterdam, The Netherlands (1984) $37.75 pp 354
Designing microprocessor-based equipment for immunity from electrical interference
Programs in BASIC for electronic engineers, technicians and experimenters
Transputer communication link
A MapReduce scratchpad memory for multi-core cloud computing applications
A system-level communication synthesis approach for hardware/software systems
Interrupt replay: a debugging method for parallel programs with interrupts
Holistic big data integrated artificial intelligent modeling to improve privacy and security in data management of smart cities
Formal verification of fault-tolerant software design: the CSP approach
Distributed systems design : G von Bochmann Springer-Verlag, New York, USA (1983) $19.00, pp 259
A design methodology for PC-expansion card development
A comparison of heuristic algorithms for custom instruction selection
C - an alternative to assembly programming
Robot Learning : Edited by J H Connell and S Mahadevan Kluwer Academic, Dordrecht, The Netherlands (1993) ISBN 0 7923 9365 I, £65.75, Dfl.185.00, pp 256
Personal computers in automation systems
Preview of the IEEE P896 draft specification
Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip
Real-time simulated testing with a development system
On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology
Interfacing considerations for Mitsubishi memory cards
Introduction to Special Issue on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE)
VLSI based orthogonal diagonal cross hair search (ODCHS) algorithm implementation for efficient image compression
Multiobjective GPU design space exploration optimization
State-based switching multi-rate controller for improving resource utilization on predictable and composable platforms
Dynamic fault-tolerant VLIW processor with heterogeneous Function Units
OPTS: increasing branch prediction accuracy under context switch
New technology: society, employment and skill: Council for Science and Society (CSS), UK (1981) pp 103, £7.50, £2.50
An efficient wideband low noise amplifier (WLNA) using advanced design system based industrial micro strip antenna
Embedded microprocessor software: case study of an automatic computer exchange
ABC optimized neural network model for image deblurring with its FPGA implementation
Design of a simulation platform for intelligent marine search and rescue based on wireless sensors
Edge computing-enabled secure and energy-efficient smart parking: A review
A Hybrid Semantic Similarity Measurement for Geospatial Entities
Design of high-performance QCA incrementer/decrementer circuit based on adder/subtractor methodology
The IoT-based real-time image processing for animal recognition and classification using deep convolutional neural network (DCNN)
Application of Machine Learning and Big Data in Doubly Fed Induction Generator based Stability Analysis of Multi Machine System using Substantial Transformative Optimization Algorithm
Research on the coordinated development of tourism economy based on embedded dynamic data
Design of parallel computing system for embedded network distributed load tasks
A smart telemetry compression system for a space instrument: MARS-96 ELISMA instrument complex
Architecture of a ladder solving processor for programmable controllers
Efficient security zones implementation through hierarchical group key management at NoC-based MPSoCs
Variation aware power management for GPU memories
Parity driven reconfigurable duplex system
Advances in computer communication networks and applications
Scalable fully coupled annealing processing system and multi-chip FPGA implementation
Development of Island tourism resources based on distributed database and embedded system
Design and evaluation of low power and area efficient approximate Booth multipliers for error tolerant applications
Multi-prediction metropolis hastings resampling filtering algorithm based on CUDA
Multichannel software event counter for the MC6809
Modified algorithm of unimodal thresholding for FPGA implementation
FPGA based substantial power evolution controlling strategy for solar and wind forecasting grid connected system
Editable video creation based on embedded simulation engine and GAN
Design and deployment of android based mobile application for performance analysis of micro strip patch antenna
An adaptive adjusting mechanism for agent distributed blackboard architecture
Performance of the Hough transform on a distributed memory multiprocessor
A high performance, area efficient TTA-like vertex shader architecture with optimized floating point arithmetic unit for embedded graphics applications
Clock tree generation by abutment in synchoros VLSI design
Random access schemes for efficient FPGA SpMV acceleration
Automated synthesis of asynchronous interface circuits
Hybridization of Pigeon inspired with glowworm' swarm optimization based clustering technique in wireless sensor networks
Near-memory computing: Past, present, and future
Test generation algorithm for QCA circuits targeting novel defects and its corresponding fault models
Transputer-based simulation tool for performance evaluation of wide area telecommunications networks
Microprocessor systems design: Edwin E Klingman, Prentice Hall, New Jersey, USA, 480pp, £18.60 (1977)
M6805 HMOS/IM 146805 CMOS family microcomputer/microprocessor user's manual: Prentice-Hall, Englewood Cliffs, NJ, USA (1983) $17.95, pp 249
MGWO-PI controller for enhanced power flow compensation using unified power quality conditioner in wind turbine squirrel cage induction generator
Implementation of STAP algorithms on IBM SP2 and on ADSP 21062 dual digital signal processor systems
Testing methodology: implications for the circuit designer
A Fast 2-D Otsu lung tissue image segmentation algorithm based on improved PSO
Material database management system based on heterogeneous multi-processor and computer embedded system
A microcontroller based machine vision approach for tomato grading and sorting using SVM classifier
Combined compression of multiple correlated data streams for online-diagnosis systems
An on-line fault diagnosis scheme for linear processor arrays
Remote classroom system for Chinese linguistics teaching based on FPGA and embedded system
A design methodology for optimally folded, pipelined architectures in VLSI applications using projective space lattices
Design of a CCITT V.22 modem
FORTH on the BBC microcomputer : R De Grandis-Harrison John Wiley, New York, USA (1983) £7.50, pp 280
Emerging local area network technologies
Determining the necessity of fault tolerance techniques in FPGA devices for space missions
ARINC 629 digital communication system - application on the 777 and beyond
A two-stage stacked ensemble intrusion detection system using five base classifiers and MLP with optimal feature selection
Structured analysis and design: Infotech state of the art report, Infotech International, Maidenhead, Berks, UK (1978) Volume 1: 273pp, Volume 2: 373pp, £120 ($225)
An efficient modeling attack for breaking the security of XOR-Arbiter PUFs by using the fully connected and long-short term memory
Big Data Development of Tourism Resources Based on 5G Network and Internet of Things System
GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses
Development of 32-bit microprocessor Gmicro F32 family products
Low-power subthreshold to above threshold level shifters in 90 nm and 65 nm process
Indirect Branch Validation Unit
2-pass crossassembler for the 8080 microprocessor
Investigation of modified multilevel inverter topology for PV system
Hospital wireless system processing optimization and clinical efficacy of type 2 diabetes nursing prevention
Reliability and accuracy requires detailed hardware design
Towards refresh-optimized EDRAM-based caches with a selective fine-grain round-robin refresh scheme
Verification and fault synthesis algorithm at switch-level
Computer architecture and parallel processing: K Hwang and F A BriggsMcGraw-Hill, New York, USA (1984) £33.25 pp 846
Driving Votrax SCOI with microcomputers
An embedded co-processor for accelerating window joins over uncertain data streams
Parallel processing speed increase of the one-bit auto-correlation function in hardware
Microprocessor teaching
Computer systems and technology: 29-31 March 1977, University of Sussex, UK. Organized by the Institution of Electrical and Radio Engineers
Template-based mapping of reversible circuits to IBM quantum computers
Urban environment art design simulation based on FPGA and neural network
FPGA implementation of SRAM PUFs based cryptographically secure pseudo-random number generator
Reliability-Aware Energy-Efficient Scheduling for ( m, k )-Constrained Real-Time Systems Through Shared Time Slots
A linear approximation based hybrid approach for binary logarithmic conversion
Microprocessor controlled colour vision tester
An integrated state assignment and flip-flop selection technique for FSM synthesis
Multi-resource scheduling for FPGA systems
A low-power wireless-assisted multiple network-on-chip
Multichannel real-time data acquisition system using dual ported FIFO buffers
A dsPIC based optimal sizing of solar PV plant using ultra capacitors for transient power delivery
Intelligent medical diagnosis and misoprostol medical abortion nursing based on embedded system
A fast integrated deblocking filter and sample-adaptive-offset parameter estimation architecture for HEVC
Processor components: data path and control circuits
Generating test sequences using symbolic execution for event-driven real-time systems
On the performance of adaptive wormhole routing in the bi-directional torus network: a hot spot analysis
A modular and efficient hardware architecture for particle swarm optimization algorithm
Memory models for behavioral modeling and digital predistortion of envelope tracking power amplifiers
High-speed FPGA implementation of full-word Montgomery multiplier for ECC applications
Design and VLSI implementation of an ASIC for real-time manipulation of digital colour images
A methodology for reconfigurable hardware design based upon evolutionary computation
Understanding the 68000: Leon HellerCentury, London, UK £7.95 pp 108
A modified asymmetric cascaded multilevel DC-AC converter with switched diodes using FPGA processor implementation
Editorial notes: Special issue on on-chip parallel and network-based systems
Universal RS232C cable
Scheduling driven circuit partitioning algorithm for multiple FPGAs using time-multiplexed, off-chip, multi-casting interconnection architecture
High-speed divider using multiplication
Look-up table based I-V model for GaN HEMT devices for Microwave Applications
Training fully recurrent neural networks on a ring transputer array
Improving hardware Trojan detection using scan chain based ring oscillators
A high throughput 3D-bus interconnect for network processors
Fifth generation water architecture: Shute, M J Prentice-Hall, Hemel Hempstead, UK (1988) £45.95, pp 316
Efficient algorithmic evaluation of correlation power analysis: Key distinguisher based on the correlation trace derivative
RISC architecture: D Tabak Research Studies Press, Letchworth, UK (1987) £19.95 pp 175
Heterogeneity of abstractions in EDA tools: Reviewing models of computation for many-core systems targeting intensive signal processing applications
Implementation of moving TDM slots for voice transmission on Ethernet