yusuke1997/dblp-id-title huggingface dataset:
An Efficient Dynamic Regulated Fuzzy Neural Network for Human Motion Retrieval and Analysis
A New Form of Convolution Theorem for One-Dimensional Quaternion Linear Canonical Transform and Application
Integrated Optimization of Stop Location and Route Design for Community Shuttle Service
A Vulnerability Measure of k-Uniform Linear Hypergraphs
A Simple Semi-Analytic Contact Mechanical Model for Tangential and Torsional Fretting Wear of Axisymmetric Contacts
Exact Solutions of the Oberbeck-Boussinesq Equations for the Description of Shear Thermal Diffusion of Newtonian Fluid Flows
Multi-Objective Assembly Line Balancing Problem with Setup Times Using Fuzzy Goal Programming and Genetic Algorithm
Relativistic Formulation in Dual Minkowski Spacetime
Circuit Complexity from Supersymmetric Quantum Field Theory with Morse Function
Mitigation of Privacy Threats due to Encrypted Traffic Analysis through a Policy-Based Framework and MUD Profiles
A Review of Different Components of the Intelligent Traffic Management System (ITMS)
Swing-By Applications and Estimation of the Van Allen Belts' Radiation Exposure for a Spacecraft in a Low Thrust Transfer to the Moon
Continuity and Analyticity for the Generalized Benjamin-Ono Equation
Carlitz's Equations on Generalized Fibonacci Numbers
Two New Rb3Sc(IO3)6 Polytypes in Proposed Nonlinear Optical Family A3M(IO3)6 (A = K, Rb; M = Sc, In): Topology-Symmetry Analysis, Order-Disorder and Structure-Properties Relation
Smile Reanimation with Masseteric-to-Facial Nerve Transfer plus Cross-Face Nerve Grafting in Patients with Segmental Midface Paresis: 3D Retrospective Quantitative Evaluation
Thioureas Derived from (S)-1-(2-pyridyl)ethylamine Enantiomer: Synthesis and Selected Applications as an Organocatalyst
Asymptotically Stable Solutions of Infinite Systems of Quadratic Hammerstein Integral Equations
A Class of Discrete Memristor Chaotic Maps Based on the Internal Perturbation
Design of a Secure System Considering Quality of Service
Observability and Symmetries of Linear Control Systems
Use of Precise Area Fraction Model for Fine Grid DEM Simulation of ICFB with Large Particles
Second-Order Cone Approximation for Voltage Stability Analysis in Direct-Current Networks
T-Spherical Fuzzy Rough Interactive Power Heronian Mean Aggregation Operators for Multiple Attribute Group Decision-Making
Complexity Reduction Approach for Solving Second Kind of Fredholm Integral Equations
Geometric Structures Generated by the Same Dynamics. Recent Results and Challenges
Positive Radial Symmetric Solutions of Nonlinear Biharmonic Equations in an Annulus
On the Partition Temperature of Massless Particles in High-Energy Collisions
Non-Linear Dynamic Feature Analysis of a Multiple-Stage Closed-Loop Gear Transmission System for 3D Circular Braiding Machine
Symmetric and Asymmetric Synapses Driving Neurodegenerative Disorders
Test Case Selection through Novel Methodologies for Software Application Developments
Strongly Lensed Supernovae in Well-Studied Galaxy Clusters with the Vera C. Rubin Observatory
Symmetries, Lagrangians and Conservation Laws of an Easter Island Population Model
Detecting Word-Based Algorithmically Generated Domains Using Semantic Analysis
Optimal Energy Efficiency Used DDPG in IRS-NOMA Wireless Communications
Symmetry of the Non-Analytic Solution of the Dirac Equation Inside the Proton of Hydrogen Atoms
Heat Transfer Characteristics of an Electric Motor with Oil-Dripping Cooling under Overload Conditions
Research on Person Pose Estimation Based on Parameter Inverted Pyramid and High-Dimensional Feature Enhancement
Asymmetrical Property of the Subproportionality of Weighting Function in Prospect Theory: Is It Real and How Can It Be Achieved?
A New Approach to the Solution of the Fredholm Integral Equation via a Fixed Point on Extended b -Metric Spaces
Prediction of Tunnel Earthquake Damage Based on a Combination Weighting Analysis Method
5G Network Data Migration Service Based on Edge Computing
Complex Networks and Symmetry II: Reciprocity and Evolution of World Trade
Derivatives, Integrals, and Polynomials Arising from the Inhomogeneous Airy Equation
A Selective Video Encryption Scheme Based on Coding Characteristics
Charge Conjugation Symmetry in the Finite Basis Approximation of the Dirac Equation
Study on an Automatic Parking Method Based on the Sliding Mode Variable Structure and Fuzzy Logical Control
Development of Optimal Iterative Methods with Their Applications and Basins of Attraction
Quasi-Double Diagonally Dominant H-Tensors and the Estimation Inequalities for the Spectral Radius of Nonnegative Tensors
Secure, Remote, Dynamic Reconfiguration of FPGAs
Guest Editorial RAW 2014
The Unified Accumulator Architecture: A Configurable, Portable, and Extensible Floating-Point Accumulator
Introduction to the Special Section on FCCM'16
Introduction to the Special Issue on the 11 th International Conference on Field-Programmable Technology (FPT'12)
Mitigating Electrical-level Attacks towards Secure Multi-Tenant FPGAs in the Cloud
A Survey on FPGA Cybersecurity Design Strategies
On the Evolution of Hardware Circuits via Reconfigurable Architectures
Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-specific LLVM Passes for Compute-Intensive FPGA Accelerators
A Simulation Framework for Rapid Analysis of Reconfigurable Computing Systems
VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster
Mercury BLASTP: Accelerating Protein Sequence Alignment
Fine-Grained Module-Based Error Recovery in FPGA-Based TMR Systems
L-FNNG: Accelerating Large-Scale KNN Graph Construction on CPU-FPGA Heterogeneous Platform
SHMEM+: A multilevel-PGAS programming model for reconfigurable supercomputing
DGMF: A Unified Dynamic Mapping Framework for Graph Neural Networks
CHIP-KNNv2: A Configurable and High-Performance K-Nearest Neighbors Accelerator on HBM-based FPGAs
Scheduling and Placement of Hardware/Software Real-Time Relocatable Tasks in Dynamically Partially Reconfigurable Systems
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures
Vector Processing as a Soft Processor Accelerator
TR-FSM: Transition-Based reconfigurable finite state machine
Modular Switched Multiported SRAM-Based Memories
Optimal Loop Unrolling and Shifting for Reconfigurable Architectures
Efficient Assembly for High-Order Unstructured FEM Meshes (FPL 2015)
Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA
Microarchitectural Comparison of the MXP and Octavo Soft-Processor FPGA Overlays
Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators
High-efficiency Compressor Trees for Latest AMD FPGAs
The Table-Hadamard GRNG: An Area-Efficient FPGA Gaussian Random Number Generator
Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap between Academic and Commercial CAD
A Systematic Review of Fast, Scalable, and Efficient Hardware Implementations of Elliptic Curve Cryptography for Blockchain
POWER-MODES: POWer-EmulatoR- and MOdel-Based DEpendability and Security Evaluations
Instruction Driven Cross-layer CNN Accelerator for Fast Detection on FPGA
Impact of Parallelism and Memory Architecture on FPGA Communication Energy
ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems
An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor
Hipernetch: High-Performance FPGA Network Switch
Designing an IEEE-Compliant FPU that Supports Configurable Precision for Soft Processors
Reprogrammable Non-Linear Circuits Using ReRAM for NN Accelerators
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs
Open-Source Variable-Precision Floating-Point Library for Major Commercial FPGAs
Self-Measurement of Combinatorial Circuit Delays in FPGAs
Productively Generating a High-Performance Linear Algebra Library on FPGAs
ULP-SRP: Ultra Low-Power Samsung Reconfigurable Processor for Biomedical Applications
Introduction to the Special Section on FPL 2015
Introduction to the Special Section on FPGA 2022
PipeArch: Generic and Context-Switch Capable Data Processing on FPGAs
DANSEN: Database Acceleration on Native Computational Storage by Exploiting NDP
A Desktop Computer with a Reconfigurable Pentium®
Tensor Slices: FPGA Building Blocks For The Deep Learning Era
Extending UML/MARTE to Support Discrete Controller Synthesis, Application to Reconfigurable Systems-on-Chip Modeling
A Retargetable Compilation Framework for Heterogeneous Reconfigurable Computing
Networks-on-Chip for FPGAs: Hard, Soft or Mixed?
Analyzing System-Level Information's Correlation to FPGA Placement
A Novel FPGA Implementation of a Time-to-Digital Converter Supporting Run-Time Estimation and Compensation
Unrolling Ternary Neural Networks
A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms
Processing Grid-format Real-world Graphs on DRAM-based FPGA Accelerators with Application-specific Caching Mechanisms
The Strong Scaling Advantage of FPGAs in HPC for N-body Simulations
Design and Analysis of Configurable Ring Oscillators for True Random Number Generation Based on Coherent Sampling
PQA: Exploring the Potential of Product Quantization in DNN Hardware Acceleration
Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks
An FPGA-based accelerator for LambdaRank in Web search engines
Advantages of a Statistical Estimation Approach for Clock Frequency Estimation of Heterogeneous and Irregular CGRAs
A Self-Aware Tuning and Self-Aware Evaluation Method for Finite-Difference Applications in Reconfigurable Systems
Framework for Rapid Performance Estimation of Embedded Soft Core Processors
Exploiting Partial Runtime Reconfiguration for High-Performance Reconfigurable Computing
Area-Efficient Near-Associative Memories on FPGAs
Molecular Dynamics Simulations on High-Performance Reconfigurable Computing Systems
An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks
VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling
Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks
Leveraging Incremental Machine Learning for Reconfigurable Systems Modeling under Dynamic Workloads
Montgomery Multiplication Scalable Systolic Designs Optimized for DSP48E2
HierCGRA: A Novel Framework for Large-scale CGRA with Hierarchical Modeling and Automated Design Space Exploration
NC-Library: Expanding SystemC Capabilities for Nested reConfigurable Hardware Modelling
Reconfigurable architecture for VBSME with variable pixel precision
Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-Dilithium
ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs
Virtual networks - distributed communication resource management
Isolated WDDL: A Hiding Countermeasure for Differential Power Analysis on FPGAs
Enhancing the Security of FPGA-SoCs via the Usage of ARM TrustZone and a Hybrid-TPM
Efficient Reconfigurable Architecture for Pricing Exotic Options
Highly Parallel Multi-FPGA System Compilation from Sequential C/C++ Code in the AWS Cloud
BlastFunction: A Full-stack Framework Bringing FPGA Hardware Acceleration to Cloud-native Applications
In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms
Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware
FPGA Architecture Exploration for DNN Acceleration
Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration
Improving Energy Efficiency of CGRAs with Low-Overhead Fine-Grained Power Domains
VERSATILE: Very Fast Partial Reconfiguration Controller
Net-length-based routability-driven power-aware clustering
High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design
Introduction to Special Section on FPGA 2021
The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware
A Runtime FPGA Placement and Routing Using Low-Complexity Graph Traversal
FPGA-based Acceleration of FT Convolution for Pulsar Search Using OpenCL
Constraint-Aware Multi-Technique Approximate High-Level Synthesis for FPGAs
Parallelising Control Flow in Dynamic-scheduling High-level Synthesis
A Comparison Study on Implementing Optical Flow and Digital Communications on FPGAs and GPUs
The ExaNeSt Prototype: Evaluation of Efficient HPC Communication Hardware in an ARM-based Multi-FPGA Rack
A Reconfigurable Architecture for Real-time Event-based Multi-Object Tracking
MPI as a Programming Model for High-Performance Reconfigurable Computers
Adaptive Parallelism Exploitation under Physical and Real-Time Constraints for Resilient Systems
FPGA-based Acceleration of Time Series Similarity Prediction: From Cloud to Edge
Inducing Non-uniform FPGA Aging Using Configuration-based Short Circuits
Leveraging reconfigurability in the hardware/software codesign process
RLUT: A Reduced LUT Architecture with Fine-Grained Scalability and Its Automatic Design Flow for Large Frequent Functions
MCoreOPU: An FPGA-based Multi-Core Overlay Processor for Transformer-based Models
The Cibola Flight Experiment
You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application
Security Primitives for Reconfigurable Hardware-Based Systems
FeatherNet: An Accelerated Convolutional Neural Network Design for Resource-constrained FPGAs
A Scalable and Programmable Modular Traffic Manager Architecture
Guest Editorial: TRETS Special Edition on the 15th International Symposium on FPGAs
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs
Accelerating Weather Prediction Using Near-Memory Reconfigurable Fabric
NeuroHSMD: Neuromorphic Hybrid Spiking Motion Detector
Towards development of an analytical model relating FPGA architecture parameters to routability
FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA
Performance Scalability of Adaptive Processor Architecture
Introduction to Special Issue on Reconfigurable Components with Source Code
Optimizing Wait States in the Synthesis of Memory References with Unpredictable Latencies
Improved Reliability of FPGA-Based PUF Identification Generator Design
Multi-FPGA Designs and Scaling of HPC Challenge Benchmarks via MPI and Circuit-switched Inter-FPGA Networks
Space Optimization on Counters for FPGA-Based Perl Compatible Regular Expressions
GraphScale: Scalable Processing on FPGAs for HBM and Large Graphs
ARC 2014: Towards a Fast FPGA Implementation of a Heap-Based Priority Queue for Image Coding Using a Parallel Index-Aware Tree
Pipelined Parallel Join and Its FPGA-Based Acceleration
FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation
SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs
Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs
Efficient and Versatile FPGA Acceleration of Support Counting for Stream Mining of Sequences and Frequent Itemsets
A Protection and Pay-per-use Licensing Scheme for On-cloud FPGA Circuit IPs
Low-precision Floating-point Arithmetic for High-performance FPGA-based CNN Acceleration
UNTANGLED: A Game Environment for Discovery of Creative Mapping Strategies
Efficient Fine-grained Processor-logic Interactions on the Cache-coherent Zynq Platform
Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines
FRoC 2.0: Automatic BRAM and Logic Testing to Enable Dynamic Voltage Scaling for FPGA Applications
RWRoute: An Open-source Timing-driven Router for Commercial FPGAs
Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm
A BNN Accelerator Based on Edge-skip-calculation Strategy and Consolidation Compressed Tree
ThunderGP: Resource-Efficient Graph Processing Framework on FPGAs with HLS
The Impact of Terrestrial Radiation on FPGAs in Data Centers
PTME: A Regular Expression Matching Engine Based on Speculation and Enumerative Computation on FPGA
Exploiting Self-Reconfiguration Capability to Improve SRAM-based FPGA Robustness in Space and Avionics Applications
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs
Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA
RIVER: Reconfigurable Flow and Fabric for Real-Time Signal Processing on FPGAs
Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing
Acceleration of k-Means Algorithm Using Altera SDK for OpenCL
ProgramGalois: A Programmable Generator of Radix-4 Discrete Galois Transformation Architecture for Lattice-Based Cryptography
Automatic Creation of High-bandwidth Memory Architectures from Domain-specific Languages: The Case of Computational Fluid Dynamics
Identification of Dynamic Circuit Specialization Opportunities in RTL Code
Separation Logic for High-Level Synthesis
Accelerated Phylogenetics on the AMD Versal Adaptive SoC
SuperDragon: A Heterogeneous Parallel System for Accelerating 3D Reconstruction of Cryo-Electron Microscopy Images
The FPOA, a Medium-grained Reconfigurable Architecture for High-level Synthesis
Large-scale Cellular Automata on FPGAs: A New Generic Architecture and a Framework
Design Tools for Implementing Self-Aware and Fault-Tolerant Systems on FPGAs
Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores
(FPL 2015) Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies
FPGA Implementation of Compact Hardware Accelerators for Ring-Binary-LWE-based Post-quantum Cryptography
NAPOLY: A Non-deterministic Automata Processor OverLaY
Hoplite: A Deflection-Routed Directional Torus NoC for FPGAs
FPGA-Based Large-Scale Sorting with Optimized Bandwidth Utilization
Fast and Accurate Stereo Vision System on FPGA
RAiSD-X: A Fast and Accurate FPGA System for the Detection of Positive Selection in Thousands of Genomes
FPGA Implementations of Kernel Normalised Least Mean Squares Processors
Novel Congestion-estimation and Routability-prediction Methods based on Machine Learning for Modern FPGAs
FPGA-based Block Minifloat Training Accelerator for a Time Series Prediction Network
Algorithmic-Level Design Partitioning for Latency Minimization in Multi-Chip and Multi-Die Systems
Kernel Normalised Least Mean Squares with Delayed Model Adaptation
Cross-VM Covert- and Side-Channel Attacks in Cloud FPGAs
Efficient SpMM Accelerator for Deep Learning: Sparkle and Its Automated Generator
R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA
Approaches for FPGA Design Assurance
A Speculative Loop Pipeline Framework with Accurate Path Modeling for High-Level Synthesis
Fast Turnaround HLS Debugging Using Dependency Analysis and Debug Overlays
Reconfigurable Hardware Architecture for Authenticated Key Agreement Protocol Over Binary Edwards Curve
Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs
ZyPR: End-to-end Build Tool and Runtime Manager for Partial Reconfiguration of FPGA SoCs at the Edge
Techniques for Design and Implementation of Secure Reconfigurable PUFs
RAT: RC Amenability Test for Rapid Performance Prediction
Titan-R: A Multigigabit Reconfigurable Combined Compression/Decompression Unit
A Microcoded Kernel Recursive Least Squares Processor Using FPGA Technology
Cloud Building Block Chip for Creating FPGA and ASIC Clouds
Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware
Programmable Analog System Benchmarks Leading to Efficient Analog Computation Synthesis
Demystifying the Soft and Hardened Memory Systems of Modern FPGAs for Software Programmers through Microbenchmarking
Asymmetric Cache Coherency: Policy Modifications to Improve Multicore Performance
Tailor: Altering Skip Connections for Resource-Efficient Inference
Fast Adjustable NPN Classification Using Generalized Symmetries
A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications
Application-Specific FPGA using heterogeneous logic blocks
[DL] A Survey of FPGA-based Neural Network Inference Accelerators
Recent Attacks and Defenses on FPGA-based Systems
Introduction to the Special Section on Deep Learning in FPGAs
Scalable Phylogeny Reconstruction with Disaggregated Near-memory Processing
FPGA Acceleration of MultiFactor CDO Pricing
Compute Bound and I/O Bound Cellular Automata Simulations on FPGA Logic
FPGA technology mapping with encoded libraries and staged priority cuts
An Optimized GIB Routing Architecture with Bent Wires for FPGA
ADAS: A High Computational Utilization Dynamic Reconfigurable Hardware Accelerator for Super Resolution
Introduction to the Special Issue on FPL 2022
CHIRP: Compact and High-Performance FPGA Implementation of Unified Hardware Accelerators for Ring-Binary-LWE-based PQC
DF-BETA: An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination
Optimizing memory bandwidth use and performance for matrix-vector multiplication in iterative methods
Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy
Model-based Design of Hardware SC Polar Decoders for FPGAs
ARC 2014 Over-Clocking KLT Designs on FPGAs under Process, Voltage, and Temperature Variation
ScalaBFS2: A High-performance BFS Accelerator on an HBM-enhanced FPGA Chip
Design and Implementation of Hardware-Software Architecture Based on Hashes for SPHINCS+
Quipu: A Statistical Model for Predicting Hardware Resources
Leakier Wires: Exploiting FPGA Long Wires for Covert- and Side-channel Attacks
High-Efficiency Convolutional Ternary Neural Networks with Custom Adder Trees and Weight Compression
Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis
Deterministic Approach for Range-enhanced Reconfigurable Packet Classification Engine
CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design
Solving the Global Atmospheric Equations through Heterogeneous Reconfigurable Platforms
Evaluating the Impact of Using Multiple-Metal Layers on the Layout Area of Switch Blocks for Tile-Based FPGAs in FinFET 7nm
Platform-aware bottleneck detection for reconfigurable computing applications
Stream Aggregation with Compressed Sliding Windows
Fast, Efficient Floating-Point Adders and Multipliers for FPGAs
Fast Optical Reconfiguration of a Nine-Context DORGA Using a Speed Adjustment Control
Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays
Special-Purpose Hardware for Solving the Elliptic Curve Discrete Logarithm Problem
AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-Based Lightweight PQC
A Reconfigurable Architecture for the Detection of Strongly Connected Components
xDNN: Inference for Deep Convolutional Neural Networks
Introduction to the Special Issue on RAW 2024
QiCells: A Modular RFSoC-based Approach to Interface Superconducting Quantum Bits
Guest Editors' Introduction: ICFPT 2007
Reducing Memory Constraints in Modulo Scheduling Synthesis for FPGAs
VFloat: A Variable Precision Fixed- and Floating-Point Library for Reconfigurable Hardware
TATAA: Programmable Mixed-Precision Transformer Acceleration with a Transformable Arithmetic Architecture
Autonomous Soft-Error Tolerance of FPGA Configuration Bits
An FPGA-Based Accelerator for Frequent Itemset Mining
Introduction to the Special Issue on ReCoSoC 2011
Automating Elimination of Idle Functions by Runtime Reconfiguration
Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs
FPGADefender: Malicious Self-oscillator Scanning for Xilinx UltraScale + FPGAs
Across Time and Space: Senju's Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs
A Unified FPGA Virtualization Framework for General-Purpose Deep Neural Networks in the Cloud
Introduction to Special Issue on FPGAs in Data Centers