yusuke1997/dblp-id-title huggingface dataset:
A Generalized Message-Passing Mechanism for Communicating Sequential Processes
On the Apparent Continuity of Processing in a Paging Environment
Mesh Computer Algorithms for Computational Geometry
Adapt Burstable Containers to Variable CPU Resources
The Conditional Diagnosability of k-Ary n-Cubes under the Comparison Diagnosis Model
Feature Enhancement of Vectorcardiograms by Linear Normalization
Cascaded Binary Counters with Feedback
Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost
Generalized Elastic Scheduling for Real-Time Tasks
A Note on Base -2 Arithmetic Logic
Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations
Conic Display Generator Using Multiplying Digital-Analog Converters
Heuristic Minimization of MVL Functions: A Direct Cover Approach
Achieving Fault-Tolerant Multicast in Injured Wormhole-Routed Tori and Meshes Based on Euler Path Construction
A Fault-Tolerant Tree Communication Scheme for Hypercube Systems
Threshold-Based Mechanisms to Discriminate Transient from Intermittent Faults
NV-Clustering: Normally-Off Computing Using Non-Volatile Datapaths
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment
Parallel Graph Algorithms Based Upon Broadcast Communications
Converting to and from Dilated Integers
An Experimental Study of Memory Fault Latency
A Synthesis Technique for Minimal State Sequential Machines
SVDE: Serverless Framework for Low-Latency Video Analytic Queries With Hardware Disaggregation
An Asynchronous Circuit Design Language (ACDL)
Bandwidth Availability of Multiple-Bus Multiprocessors
Aliasing Error for a Mask ROM Built-In Self-Test
Single Disk Failure Recovery forX-Code-Based Parallel Storage Systems
NStore: A High-Performance NUMA-Aware Key-Value Store for Hybrid Memory
Truth-Table Verification of an Iterative Logic Array
Joint Design of Asynchronous Sleep-Wake Scheduling and Opportunistic Routing in Wireless Sensor Networks
Communication Links for Distributed Quantum Computation
Evaluation of On-Chip Static Interconnection Networks
Tremors: Privacy-Breaching Inference of Computing Tasks Using Vibration-Based Condition Monitors
Optimal Diagnosis Procedures for k-out-of-n Structures
The Design Problems of a Megabit Storage Matrix for Use in a High-Speed Computer
Exploiting Refresh Effect of DRAM Read Operations: A Practical Approach to Low-Power Refresh
A Computer Algorithm for the Synthesis of Memoryless Logic Circuits
Fast Burst Error-Correction Scheme with Fire Code
Scheduling Trees in Parallel/Pipelined Processing Environments
A Computing Perspective on Smart City [Guest Editorial]
High-Radix Division and Square-Root with Speculation
Test Pattern Generation for API Faults in RAM
Time Loss Through Gating of Asynchronous Logic Signal Pulses
On Load Balancing in Multicomputer/Distributed Systems Equipped with Circuit or Cut-Through Switching Capability
VLSI Performance Comparison of Banyan and Crossbar Communications Networks
Performance Evaluation of the Computer Network Dynamic Congestion Table Algorithm
Quality-of-Control Management in Overloaded Real-Time Systems
A Nonblocking Algorithm for Shared Queues Using Compare-and-Swap
Fuzzy Systems as Universal Approximators
Extending Real-Time Analysis for Wormhole NoCs
Computing Optimal Checkpointing Strategies for Rollback and Recovery Systems
An Algebraic Proof of the Paull-Unger Theorem
From the Cloud to the Atmosphere: Running MapReduce across Data Centers
On Communications and Networks
A Cost-Effective Random Testing Method for Programs with Non-Numeric Inputs
The Burroughs Scientific Processor (BSP)
An Approach to Designing Modular Extensible Linear Arrays for Regular Algorithms
Frame-Based Proportional Round-Robin
Analog-To-Digital Converter Utilizing an Esaki Diode Stack
Decision Diagram Method for Calculation of Pruned Walsh Transform
On Bufferless Routing of Variable Length Messages in Leveled Networks
A Fast-Converging Algorithm for Nonlinear Mapping of High-Dimensional Data to a Plane
An Iteratively Structured General-Purpose Digital Computer
Non-Triangular Self-Synchronizing Stream Ciphers
Pin Limitations and Partitioning of VLSI Interconnection Networks
Hierarchical Ring Network Configuration and Performance Modeling
Content-addressed memory using magneto- or electro-optical interrogation
Electrodeposited Twistor and Bit Wire Components
A Matrix Method for Determining All Pairs of Compatible States of a Sequential Machine
A Note on "Generalized Hypercube and Hyperbus Structures for a Computer Network"
Unified Interval Classification and Unified 3-Classification for Associative Memories
Noise Modeling Effects in Redundant Synchronizers
Cache Invalidation and Replacement Strategies for Location-Dependent Data in Mobile Environments
An Electronic Generator of Random Numbers
A Fault-Tolerant Routing Strategy in Hypercube Multicomputers
Guaranteeing Synchronous Message Deadlines with the Timed Token Medium Access Control Protocol
Temporal Consistency Maintenance Upon Partitioned Multiprocessor Platforms
End-to-End Flow Control in Computer Networks with Noisy Channels and Quasi-Cut-Through Switching
An Efficient and Unified RTL Accelerator Design for HQC-128, HQC-192, and HQC-256
Performance Evaluation of a Threshold Policy for Scheduling Readers and Writers
On Calculating Multiplicative Inverses Modulo $2^{m}$
Ternary Counters
Flow-Based Microfluidic Biochips With Distributed Channel Storage: Synthesis, Physical Design, and Wash Optimization
Comments on "A Characterization of Binary Decision Diagrams"
Multiple Fault Detection in Fan-Out Free Circuits Using Minimal Single Fault Test Set
INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing
Guest Editorial: IEEE TC Special Issue On Software, Hardware and Applications for Neuromorphic Computing
Asymptotic Expansions for Large Closed Queueing Networks with Multiple Job Classes
A Hybrid Multicast Routing Approach with Enhanced Methods for Mesh-Based Networks-on-Chip
Anole: A Pragmatic Blend of Classic and Learning-Based Algorithms in Congestion Control
Distribution of Runs in Binary Words
Processor Allocation in an N -Cube Multiprocessor Using Gray Codes
Image Boundary Estimation
Logic Design of Multivalued I 2 L Logic Circuits
GAS: General-Purpose In-Memory-Computing Accelerator for Sparse Matrix Multiplication
k-Level Truthful Incentivizing Mechanism and Generalized k-MAB Problem
A Comparison of Higher-Order Difference Methods in the Solution of Beam-Vibration Problems
Hardware-Software Coherence Protocol for the Coexistence of Caches and Local Memories
Properties of Transparent Shortened Codes for Memories With Stuck-at Faults
Design and Analysis of On-Chip Networks for Large-Scale Cache Systems
A Simple High-Speed Magnetic Access Switch Matrix
Guaranteeing the End-to-End Latency of an IMA System with an Increasing Workload
Graphfire: Synergizing Fetch, Insertion, and Replacement Policies for Graph Analytics
Learning Patterns and Pattern Sequences by Self-Organizing Nets of Threshold Elements
Contradiction Equations in a B Matrix of Vertex Weight Method and Their Correspondence with the k-Summability Property of Vertices
Chip-Level RAID with Flexible Stripe Size and Parity Placement for Enhanced SSD Reliability
Time-Delay Circuits
Exploiting Heterogeneity in P2P Video Streaming
The Balanced Tree and Its Utilization in Information Retrieval
The Maximum Rate Accumulator
Encoding and Decoding for Cyclic Permutation Codes
Rapid Technique of Manual or Machine Binary-to-Decimal Integer Conversion Using Decimal Radix Arithmetic
Reliability Evaluation of Fault-Tolerant Systems - Effect of Variability in Failure Rates
A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation
Optimal Preemptive Scheduling on Two-Processor Systems
A Novel Type of Isograph (Algebraic Equation Solver)
Protection Circuit against Differential Power Analysis Attacks for Smart Cards
A Classifier Design Technique for Discrete Variable Pattern Recognition Problems
TREEHOUSE: A Secure Asset Management Infrastructure for Protecting 3DIC Designs
Skip Techniques for High-Speed Carry-Propagation in Binary Arithmetic Units
An Efficient Test Method for Rate Monotonic Schedulability
Architectural Yield Optimization for WSI
Serial Adders with Overflow Correction
Reliable Real-Time Communication in CAN Networks
Design Verification of the S3.mp Cache-Coherent Shared-Memory System
An Adaptive Search Optimization Algorithm
Improving Performance of Large Physically Indexed Caches by Decoupling Memory Addresses from Cache Addresses
Virtual Resource Allocation Based on Link Interference in Cayley Wireless Data Centers
The Information Structure of Indulgent Consensus
Hypergraph Coloring and Reconfigured RAM Testing
Differential Fault Attack against Grain Family with Very Few Faults and Minimal Assumptions
Sytare: A Lightweight Kernel for NVRAM-Based Transiently-Powered Systems
B74-21 Patern Classification and Scene Analysis
Sequential Network Design Using Extra Inputs for Fault Detection
Distance-Constrained Scheduling and Its Applications to Real-Time Systems
Parallel Signatur Analysis Design with Bounds on Aliasing
Sensitivity-Function Calculation in Linear Systems Using Time-Shared Analog Integration
On the Hough Technique for Curve Detection
An Electronic Analog Multiplier
B73-12 Fault Detection in Digital Circuits
Analyzing the Galbraith-Lin-Scott Point Multiplication Method for Elliptic Curves over Binary Fields
Hardware Designs for Binary Integer Decimal-Based Rounding
A Truth Table Method for the Synthesis of Combinational Logic
Techniques to Reduce the Inherent Limitations of Fully Digit On-Line Arithmetic
Processor Interconnection Strategies
MalFox: Camouflaged Adversarial Malware Example Generation Based on Conv-GANs Against Black-Box Detectors
Instruction Set Processor Specifications (ISPS): The Notation and Its Applications
The Hardware Simulator: A Tool for Evaluating Computer Systems
B74-43 Evaluation and Measurement Techniques for Digital Computer Systems
Character Recognition with a Coherent Opticatl Multichannel Correlator
Eliminating Conflict Misses Using Prime Number-Based Cache Indexing
The FDP, a Fast Programmable Signal Processor
Optimal Systolic Design for the Transitive Closure and the Shortest Path Problems
A Method of Increasing the Number of Orders in a Digital Computer
The MU5 Multicomputer Communication System
A Method of Solution for Multiple-Valued Logic Expressions
Statistical Analysis of Paged and Segmented Computer Systems
Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption
Multichannel Minimum-Amplitude Comparator
OpenHD: A GPU-Powered Framework for Hyperdimensional Computing
Testing a Collaborative DDoS Defense In a Red Team/Blue Team Exercise
Another Proof of the Two-Dimensional Cayley-Hamilton Theorem
Some Automatic Digital Computers in Western Europe
Per-Node Multithreading and Remote Latency
AEML: An Acceleration Engine for Multi-GPU Load-Balancing in Distributed Heterogeneous Environment
ANTELOPE: A Semantic-Aware Data Cube Scheme for Cloud Data Center Networks
Thread Progress Equalization: Dynamically Adaptive Power-Constrained Performance Optimization of Multi-Threaded Applications
Tree Search in Major/Minor Loop Magnetic Bubble Memories
(t, k)-Diagnosability for Regular Networks
An Optimal Worst Case Algorithm for Reporting Intersections of Rectangles
The StenowriterߞA System for the Lexical Processing of Stenotypy
STORM: Scalable Resource Management for Large-Scale Parallel Computers
Arbitrary-State Attribute-Based Encryption with Dynamic Membership
Statistical Analysis of a Differential Threshold Logic Circuit Configuration
Secondary State Assignment for Sequential Machines
Reliable High-Speed Arbitration and Synchronization
A Pipelined Distributed Arithmetic PFFT Processor
FlexiPair: An Automated Programmable Framework for Pairing Cryptosystems
B74-19 Pattern Recognition Techniques
Adaptive SAT Modeling for Optimal Pattern Retargeting in IEEE 1687 Networks
Broadcast Communications and Distributed Algorithms
Measuring Designer Performance to Verify Design Automation Systems
Combined Binary Code Translation and Parallel-to-Serial Conversion Using Stored Logic Arrays
A Functional Counter
Modular Arithmetic Using Low Order Redundant Bases
Analysis of Sequential Machines
Verified Real Number Calculations: A Library for Interval Arithmetic
LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification
Lightweight Side Channel Resistance: Threshold Implementations of Simon
Performance Characteristics and Guidelines of Offloading Middleboxes Onto BlueField-2 DPU
Locality-Sensitive Bloom Filter for Approximate Membership Query
L-Networks: A Topological Model for Regular 2D Interconnection Networks
On Nonlinear Binary Sequential Circuits and Their Inverses
Computer and Database Location in Distributed Computer Systems
A Fast Hardware Pseudorandom Number Generator Based on xoroshiro128
Path Sensitization, Partial Boolean Difference, and Automated Fault Diagnosis
Heating Dispersal for Self-Healing NAND Flash Memory
NeST: A Neural Network Synthesis Tool Based on a Grow-and-Prune Paradigm
Q -Modules: Internally Clocked Delay-Insensitive Modules
New Results on Non-Normalized Floating-Point Formats
Picture Processing and Overlapping Blobs
On Homomorphic Signatures for Network Coding
A Reliable Spaceborne Memory with a Single Error and Erasure Correction Scheme
Computer-Controlled Teaching Instrumentation for Linguistic Studies with the Great Apes
Use of SPOOF's in the Analysis of Faulty Logic Networks
Comments on "Algorithmic Aspects of Hardware/Software Partitioning: 1D Search Algorithms"
On the Fundamental Structure of Galois Switching Functions
A Branch-and-Bound Algorithm for Solving the Multiprocessor Scheduling Problem with Improved Lower Bounding Techniques
B72-4 System/360 Job Control Language
Arithmetic Approaches for Rigorous Design of Reliable Fixed-Point LTI Filters
Checkpoint Repair for High-Performance Out-of-Order Execution Machines
Accelerating Parallel Applications in Cloud Platforms via Adaptive Time-Slice Control
Semisystolic Array Implementation of Circular, Skew Circular, and; Linear Convolutions
Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip
SPARE: Spiking Neural Network Acceleration Using ROM-Embedded RAMs as In-Memory-Computation Primitives
Computer-Aided Synthesis or Multiple-Output Multilevel NAND Networks witk Fan-in and Fan-out Constraints
An Algorithmic and Architectural Study on Montgomery Exponentiation in RNS
DC Accuracy in a Fast Boxcar Circuit Via a Comparator
Reduction of Average Path Length in Binary Decision Diagrams by Spectral Methods
Analysis, Modeling and Optimization of Equal Segment Based Approximate Adders
Spline Fit Made Easy
Input-Aware Sparse Tensor Storage Format Selection for Optimizing MTTKRP
Guest Editors' Introduction - Special Issue on Network-on-Chip
A Nonbinary Neural Network Design
Robust Scheduling of Task Graphs under Execution Time Uncertainty
Symmetry, Automorphism, and Test
Testability of Convergent Tree Circuits
Low-Cost Solutions for Preventing Simple Side-Channel Analysis: Side-Channel Atomicity
Comments on "Decomposition of Permutation Networks"
Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs
Multidimensional Rotations in Feature Selection
On the Generalized Binary System
General Modeling and Performance Analysis for Location Management in Wireless Mobile Networks
B74-45 Computer-Communication Networks
Efficient Exact Test for Rate-Monotonic Schedulability Using Large Period-Dependent Initial Values
Hybrid Computation Techniques Inferred from Functional Analysis
Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead
Computing Robust Walsh-Fourier Transform by Error Product Minimization
Subcube Fault Tolerance in Hypercube Multiprocessors
Classification of Faults in Synchronous Sequential Circuits
Threshold Synthesis of Ternary Digital Systems
Simulation of a Word Recognition System on Two Parallel Architectures
Synthesis of Multiple Sequential Machines Having Different Inputs
A Contextual Postprocessing System for Error Correction Using Binary n-Grams
Antiparallel Control Logic
Evolutionary Computing and Particle Filtering: A Hardware-Based Motion Estimation System
CAP: Communication-Aware Automated Parallelization for Deep Learning Inference on CMP Architectures
High-Accuracy Multiply-Accumulate (MAC) Technique for Unary Stochastic Computing
A/D Conversion Using Geometric Feedback AGC
Generation of Finely-Pipelined GF( P P) Multipliers for Flexible Curve Based Cryptography on FPGAs
Throughput Enhancement for Phase Change Memories
Garbage Collection for Flexible Hard Real-Time Systems
A Local Selection Algorithm for Switching Function Minimization
On the Relationship Between Two Systolic Array Design Mehodologies
Recursive Operators for Prime Implicant and Irredundant Normal Form Determination
Guided Self-Scheduling: A Practical Scheduling Scheme for Parallel Supercomputers
Comment on Review of Operating Systems Survey
Exact Response Time Analysis for Fixed Priority Memory-Processor Co-Scheduling
A Binary Floating-Point Resistor
STT-MRAM-Based Reliable Weak PUF
Theory and Design of Mixed-Mode Sequential Machines
Constant Current Source for Anlog Computer Use
${\sf FORESEE}$FORESEE: An Effective and Efficient Framework for Estimating the Execution Times of IO Traces on the SSD
Computation of the Transition Matrix of a Linear Sequential Circuit
A Note on Automatic Detection of Texture Gradients
An Algorithm for Grey-Level Transformations in Digitized Images
Fourier Preprocessing for Hand Print Character Recognition
Iterative Arrays ror Radix Conversion
Effect of Fault Tolerance on Response Time-Analysis of the Primary Site Approach
Comments on "Availability of k-Coterie"
The Formal Description and Verification of Hardware Timing
N-Dimensional Twin Torus Topology
The Hearsay- I Speech Understanding System: An Example of the Recognition Process
A Two-Level Microprogrammed Multiprocessor Computer with Nonnumeric Functions
Optimizing File Systems with a Write-Efficient Journaling Scheme on Non-Volatile Memory
Circuit Simulation on Shared-Memory Multiprocessors
Comments on "Decomposition Method of Determining Maximum Compatibles"
Collaborative Adaptation for Energy-Efficient Heterogeneous Mobile SoCs
A High-Speed Analog-Digital Computer for Simulation
Sorting Implicit Outputs in Digital Simulation
A User Mobility-Based Data Placement Strategy in a Hybrid Cloud/Edge Environment Using a Causal-Aware Deep Learning Network
Performing Arithmetic Operations on Round-to-Nearest Representations
An Efficient NAND Flash File System for Flash Memory Storage
Pipelined Computation of Scalar Multiplication in Elliptic Curve Cryptosystems (Extended Version)
Low-Latency Multi-Flow Cooperative Broadcast in Fading Wireless Networks
A Novel Algorithmic Approach to Aid Post-Silicon Delay Measurement and Clock Tuning
A Mechanically Checked Proof of the AMD5 K 86 TM Floating Point Division Program
A Trace Cache Microarchitecture and Evaluation
Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing
Note on a Proposed Test for Random Number Generators
A Method for Finding Feedback Partitions for Sequential Machines
Static and Dynamic Numerical Characteristics of Floating-Point Arithmetic
A Multiple-Stream Registerless Shared-Resource Processor
Weakly Hard Real-Time Systems
On the Complexity of Single Fault Set Diagnosability and Diagnosis Problems
A Distributed Channel-Access Protocol for Fully-Connected Networks with Mobile Nodes
The Reconfigurable Ring of Processors: Fine-Grain Tree-Structured Computations
Comments on "Minimal Fault Tests for Combinational Networks"
Area-Time Efficient Architecture of FFT-Based Montgomery Multiplication
A Rollback Interval for Networks with an Imperfect Self-Checking Property
Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays
Algorithmics of Cost-Driven Computation Offloading in the Edge-Cloud Environment
Efficient Static Schedules for Fault-Tolerant Transmissions on Shared Media
Convergence of an Identification Technique for Nonlinear Systems
Analytical Miss Rate Calculation of L2 Cache from the RD Profile of L1 Cache
Large-Capacity High-Throughput Low-Cost Pipelined CAM Using Pipelined CTAM
A New Hybrid Algorithm for Computing a Fast Discrete Fourier Transform
A Low-Cost Burn-In Tester Architecture to Supply Effective Electrical Stress
Comments on "High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits"
A Linear Vector Recognition Function
Study of "Look-Aside" Memory
Easily Testable Two-Dimensional Cellular Logic Arrays
Connection Assignments for Probabilistically Diagnosable Systems
Pipeline Design Tradeoffs in a 32-bit Gallium Arsenide Microprocessor
Comments on "Design and Evaluation of a Fault-Tolerant Multiprocessur Using Hardware Recovery Blocks"
Radar Reflectivity Plots - Digital Method
On the Interplay between Global DVFS and Scheduling Tasks with Precedence Constraints
FluxlokߞA Nondestructive, Random-Access Electrically Alterable: High-Speed Memory Technique Using Standard Ferrite Memory Cores
Scalable Tree-Based Architectures for IPv4/v6 Lookup Using Prefix Partitioning
Contention-Aware Fair Scheduling for Asymmetric Single-ISA Multicore Systems
Guest Editorial: IEEE TC Special Issue On Communications for Many-core Processors and Accelerators
Recognition of Monotonic and Unate Cascade Realizable Functions Using an Informational Model of Switching Circuits
A Novel Sequence Generation Approach to Diagnose Faults in Reconfigurable Scan Networks
On the Logical Design of Noiseless Load-Sharing Matrix Switches
Distributed Diagnosis and the System User
Parallelization and Performance Analysis of the Cooley-Tukey FFT Algorithm for Shared-Memory Architectures
WAL-SSD: Address Remapping-Based Write-Ahead-Logging Solid-State Disks
Optimal Unidirectional Error Detecting/Correcting Codes
Searching, Merging, and Sorting in Parallel Computation
Synthesis of Combinational Logic Using Decomposition and Probability
Building an Intrusion Detection System Using a Filter-Based Feature Selection Algorithm
SIMD Machines and Cellular d -Graph Automata
Fast Radix-10 Multiplication Using Redundant BCD Codes
The Reconstruction of Three-Dimensional Objects from Two Orthogonal Projections and its Application to Cardiac Cineangiography
Characterizing and Exploiting Small-Value Memory Instructions
Some Properties of Minimal Threshold Approximations
On Minimizing the Lengths of Checking Sequences
A New Bit-Serial Systolic Multiplier Over GF (2 m )
Reliability Analysis of Systems with Concurrent Error Detection
Population-Based MCMC on Multi-Core CPUs, GPUs and FPGAs
New Approach for Efficient IP Address Lookup Using a Bloom Filter in Trie-Based Algorithms
Performance Model for a Prioritized Multiple-Bus Multiprocessor System
Determining Fault Ratios in Multilevel Delayed-Staging Storage Hierarchies
The Strict Time Lower Bound and Optimal Schedules for Parallel Prefix with Resource Constraints
Threshold Logic Design of Pulse-Type Sequential Networks
Applying Probability Measures to Abstract Languages
Array Regrouping and Its Use in Compiling Data-Intensive Embedded Applications
Statistical Independence and Threshold Functions
Efficient Multibyte Floating Point Data Formats Using Vectorization
Comment on "Realization of Arbitrary Logical Functions Using Majority Elements
On Instruction Sets and Their Formats
A Family of Efficient Regular Arrays for Algebraic Path Problem
Distributed Execution of Recovery Blocks: An Approach for Uniform Treatment of Hardware and Software Faults in Real-Time Applications
An Algorithm for a Fast Hadamard Matrix Transform of Order Twelve
The Production of Completion Signals by Asynchronous, Iterative Networks
Complementary Function Approach to the Synthesis of Three-Level NAND Network
Comb Architectures for Finite Field Multiplication in F(2^m)
A Microprogrammed Intelligent Graphics Terminal
Efficient 4-Way Vectorizations of the Montgomery Ladder
A Prewired Storage Unit
Experience with the Parallel Solutions of Partial Differential Equations on a Distributed Computing System