yusuke1997/dblp-id-title huggingface dataset:
The CBP Parameter: A Module Characterization Approach for DSP Software Optimization
Heterogeneous Simulation - Mixing Discrete-Event Models with Dataflow
VLSI parallel architecture for Kalman filter An algorithm specific approach
A Parallel Architecture for the 2-D Discrete Wavelet Transform with Integer Lifting Scheme
Implementing division with field programmable gate arrays
The Impact of Rate Control Algorithms on System-Level VLSI Design
PUMA: From Simultaneous to Parallel for Shared Memory System in Multi-core
A generalized state assignment theory for transformations on signal transition graphs
Hardware Implementation of Reconfigurable 1D Convolution
Tackling Critical Challenges towards Efficient CyberPhysical Components & Services Interconnection: The ATLAS CPS Platform Approach
A Fully Implantable, Programmable and Multimodal Neuroprocessor for Wireless, Cortically Controlled Brain-Machine Interface Applications
An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding
Implementation of the Exponential Function in a Floating-Point Unit
A Novel Mitigation Scheme for JTIDS Impulsive Interference on LDACS System Based on Sensing and Symbol Retransmission
Use of window addressable memories for high speed geometrical analysis
The ALPHA language and its use for the design of systolic arrays
A Review of Codebook Models in Patch-Based Visual Object Recognition
Energy-Efficient Digital Front-End Processor for 60 GHz Polar Transmitter
Memory Performance Optimizations For Real-Time Software HDTV Decoding
Two Fast and Robust Modified Gaussian Mixture Models Incorporating Local Spatial Information for Image Segmentation
CMOS current-mode implementation of spatiotemporal probabilistic neural networks for speech recognition
On the Design of Second Order Dynamics Reaction-Diffusion CNNs
Tradeoff Between Complexity and Memory Size in the 3GPP Enhanced aacPlus Decoder: Speed-Conscious and Memory-Conscious Decoders on a 16-Bit Fixed-Point DSP
Efficient Wordlength Reduction Techniques for DSP Applications
A Speaker-Dependent Approach to Single-Channel Joint Speech Separation and Acoustic Modeling Based on Deep Neural Networks for Robust Recognition of Multi-Talker Speech
An Analog/Digital Baseband Processor Design of a UWB Channelized Receiver for Transmitted Reference Signals
Design and Implementation of a Blind Adaptive Equalizer Using Frequency Domain Improved Square Contour Algorithm
On Hardware Implementations Of DCT and Quantization Blocks for H.264/AVC
Diffusion-Driven Image Denoising Model with Texture Preservation Capabilities
Application of Linear Discriminant Analysis to Ultrasound Signals for Automatic Microstructural Characterization and Classification
Hardware Efficient Reconfigurable Digital Hearing aid using Pascal Structure
Energy Efficient Low Latency Multi-issue Cores for Intelligent Always-On IoT Applications
General Architecture for MPEG-2/H.263/H.264/AVC to H.264/AVC Intra Frame Transcoding
Optimization Design of Biorthogonal Wavelet Filter Banks for Extending JPEG 2000 Standard Part-2
Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN
Pedestrian Navigation Based on Inertial Sensors, Indoor Map, and WLAN Signals
Joint Estimation of Location and Scatter in Complex Elliptically Symmetric Distributions
FPGA Implementation of a Pipelined On-Line Backpropagation
An Area-efficient Non-uniform Filter Bank for Low Overhead Reconfiguration of Multi-standard Software Radio Channelizers
Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis
FARM: A Flexible Accelerator for Recurrent and Memory Augmented Neural Networks
Independent Component Analysis Applied to fMRI Data: A Generative Model for Validating Results
A New Learning Algorithm for the Fusion of Adaptive Audio-Visual Features for the Retrieval and Classification of Movie Clips
SFF - The Single-Stream FPGA-Optimized Feedforward FFT Hardware Architecture
Learning Incoherent Subspaces: Classification via Incoherent Dictionary Learning
Machine Health Indicator Construction Framework for Failure Diagnostics and Prognostics
Resource-constrained loop list scheduler for DSP algorithms
An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV
Graph Normalized-LMP Algorithm for Signal Estimation Under Impulsive Noise
A Maximum Entropy Approach for Collaborative Filtering
Speaker Adaptation of Hybrid NN/HMM Model for Speech Recognition Based on Singular Value Decomposition
Configurable Data Memory for Multimedia Processing
Increasing the Robustness of Boosting Algorithms within the Linear-programming Framework
Analysis and Hardware Architecture Design of Global Motion Estimation
Tradeoff between Approximation Accuracy and Complexity for Range Analysis using Affine Arithmetic
Analyzing the Next Generation Software Defined Radio for Future Architectures
Algorithmic Exploration and Implementation of a MIMO-OFDM Equalizer
Guest Editorial: Field-Programmable Technology
Reliability-aware Co-synthesis for Embedded Systems
Preface to the Special Issue on Signal Processing, Data Acquisition and Front-end Systems for Radiation Detection and Measurements
A Low Power DSP Engine for Wireless Communications
Guest Editorial: Special Issue on Machine Learning Implementations
Computationally Efficient Motion Estimation Algorithm for HEVC
Pipelined IIR Filter Architecture Using Pole-Radius Minimization
Compiled Simulation of Programmable DSP Architectures
Greedy Detection
A Novel Multi-Feature Descriptor for Human Detection Using Cascaded Classifiers in Static Images
VLSI in picture coding
eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex
Compression and Speed-up of Convolutional Neural Networks Through Dimensionality Reduction for Efficient Inference on Embedded Multiprocessor
FPGA-Based Fast Response Image Analysis for Orientational Control in Aerial Manipulation Tasks
Design techniques for fault-tolerant systolic arrays
Performance of H.26L Video Encoder on General-Purpose Processor
Automatic Target Recognition with Dynamic Reconfiguration
Data Mining and Risk Prediction Based on Apriori Improved Algorithm for Lung Cancer
Low Complexity Antenna Selection Scheme for Multicarrier MIMO Broadcast Communication
Research on Distributed Search Technology of Multiple Data Sources Intelligent Information Based on Knowledge Graph
Quasi-Linear allocation functions for efficient array design
Using Feature-Based Models with Complexity Penalization for Selecting Features
Text-Independent Speaker Identification Using Vowel Formants
ASM1D-GAN: An Intelligent Fault Diagnosis Method Based on Assembled 1D Convolutional Neural Network and Generative Adversarial Networks
Towards Real-time 3D Visualization with Multiview RGB Camera Array
beta-bit serial/parallel multipliers
A Gbps IPSec SSL Security Processor Design and Implementation in an FPGA Prototyping Platform
RASSP Enterprise Technologies for Signal Processor Life-Cycle Support
Detection of Retinal Blood Vessels Based on Nonlinear Projections
An Improved Ant Colony Optimization for Solving Task Scheduling Problem in Radar Signal Processing System
Adaptive Neural Network for Nuclear Medicine Image Restoration
Hardware efficient fast computation of the discrete fourier transform
Research on Remote Sensing Image De-haze Based on GAN
Self-sustained UWB Sensing: A Link and Energy Adaptive Approach
Unmixing of Hyperspectral Images using Bayesian Non-negative Matrix Factorization with Volume Prior
High-speed digital filtering: Structures and finite wordlength effects
PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design
IEEE-Compliant IDCT on FPGA-Augmented TriMedia
Efficient Recursive IDFT Scheme for Complex-valued Signals in Tap-selective Maximum-likelihood Channel Estimation
Cryptographic Algorithms on the GA144 Asynchronous Multi-Core Processor - Implementation and Side-Channel Analysis
Complexity-Aware Gabor Filter Bank Architecture Using Principal Component Analysis
A Query-oriented Adaptive Indexing Technique for Smart Grid Big Data Analytics
Data Intensive Computing: From Modeling to Implementation
A Novel FPGA Architecture of a 2-D Wavelet Transform
Introduction to the Special Issue on Signal Processing Systems
VLSI Implementation of an Adaptive Multiuser Detector for Multirate WCDMA Systems
Implicit vs. Explicit Approximate Matrix Inversion for Wideband Massive MU-MIMO Data Detection
Configurable array logic circuits for computing network error detection codes
Broadband Network Delivery of Interactive Digital Video Using ATM
Real-Time Automatic Obstacle Detection method for Traffic Surveillance in Urban Traffic
Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors
Network-Adaptive Video Communication Using Packet Path Diversity and Rate-Distortion Optimized Reference Picture Selection
Comparison Between Equivalent Architectures of Complex-valued and Real-valued Neural Networks - Application on Polarimetric SAR Image Segmentation
Vehicle Attribute Recognition by Appearance: Computer Vision Methods for Vehicle Type, Make and Model Classification
Register Allocation - A Hierarchical Reduction Approach
Multimodal Event Detection in Twitter Hashtag Networks
A Neuromorphic Architecture for Context Aware Text Image Recognition
A Floating-point Extended Kalman Filter Implementation for Autonomous Mobile Robots
Efficient Spatially-Variant Single-Pixel Imaging Using Block-Based Compressed Sensing
A Review of Region-Based Image Retrieval
Parallel Scalability of Video Decoders
SDR OFDM Waveform Design for a UGV/UAV Communication Scenario
Direct Digital Frequency Synthesis Based on a Two-Level Table-Lookup Scheme
Guest Editorial: Field Programmable Technology
Hardware Specialization in Low-power Sensing Applications to Address Energy and Resilience
Reconfigurable Architecture for Deinterlacer based on Algorithm/Architecture Co-Design
An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors
Detection and Leasing of Joint Space and Spectrum Opportunities by Multiple Secondary Network Operators in Cognitive Radio Systems
Design and Implementation of the MorphoSys Reconfigurable Computing Processor
Zero-Power Defense Done Right: Shielding IMDs from Battery-Depletion Attacks
Low-Power Constant-Coefficient Multiplier Generator
Deep Model Compression and Architecture Optimization for Embedded Systems: A Survey
Correction to: Multicore Performance Prediction with MPET
Cordic based parallel/pipelined architecture for the Hough transform
Registration of Brain Atlas to MR Images Using Topology Preserving Front Propagation
Building 3-D Human Face Models from Two Photographs
Model Uncertainty Based Annotation Error Fixing for Web Attack Detection
Medical Big Data Analysis with Attention and Large Margin Loss Model for Skin Lesion Application
Area efficient computing structures for concurrent error detection in systolic arrays
Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis
3D Video Based Segmentation and Motion Estimation with Active Surface Evolution
Regular Expression Matching in Reconfigurable Hardware
A Latency-Aware Multiple Data Replicas Placement Strategy for Fog Computing
Design Space Exploration of Distributed Loop Buffer Architectures with Incompatible Loop-Nest Organisations in Embedded Systems
Fast SOLA-Based Time Scale Modification Using Envelope Matching
Special Issue on Recent Innovations in Wireless Software-Defined Radio Systems
SSIM-based Error Resilient Video Coding Over Packet-Switched Networks
The Navy's new standard digital signal processor, the AN/UYS-2
Options for Denormal Representation in Logarithmic Arithmetic
A square root covariance algorithm for constrained recursive least squares estimation
Machine Learning Based Stress Monitoring in Older Adults Using Wearable Sensors and Cortisol as Stress Biomarker
A JPEG Chip for Image Compression and Decompression
Author Rebuttal to Rocha et al. "Comments on Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks"
HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing
High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function
Age Estimation from Speech Using Tuned CNN Model on Edge Devices
ASP modules: cost-effective building-blocks for real-time DSP systems
Parallel counter implementation
Embedded Hypercube Graph Applied to Image Analysis Problems
An Adaptive Heterogeneous Runtime Framework for Irregular Applications
A Flexible PCB Inspection System Based on Statistical Learning
Code Parallelization for Multi-Core Software Defined Radio Platforms with OpenMP
A Fast Algorithm-Based Cost-Effective and Hardware-Efficient Unified Architecture Design of 4 × 4, 8 × 8, 16 × 16, and 32 × 32 Inverse Core Transforms for HEVC
Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results
Implementing the square-root information Kalman filter on a Jacobi-type systolic array
Subspace scheduling and parallel implementation of non-systolic regular iterative algorithms
Overcoming Smart City Barriers Using Multi-Modal Interpretive Structural Modeling
A High Throughput Configurable SDR Detector for Multi-user MIMO Wireless Systems
An Automatic Approach for Accurate Edge Detection of Concrete Crack Utilizing 2D Geometric Features of Crack
Improving the Decoding Efficiency of Deep Neural Network Acoustic Models by Cluster-Based Senone Selection
Performance Analysis of General-Purpose Computation on Commodity Graphics Hardware: A Case Study Using Bioinformatics
A Robust Bimodal Speech Section Detection
Interoperable Protection for Digital Multimedia Content
A Linear-Complexity Channel-Independent Code Construction Method for List Sphere Polar Decoder
Hierarchical Design of a Secure Image Sensor with Dynamic Reconfiguration
On partitioning and fault tolerance issues for neural array processors
Compiler-Based Performance Evaluation of an SIMD Processor with a Multi-Bank Memory Unit
Pipeline Reconfigurable FPGAs
Mobile Agent Protection with Self-Modifying Code
Synthesis of hazard-free control circuits from asynchronous finite state machines specifications
A block algorithm and optimal fixed-size systolic array processor for the algebraic path problem
FPGA Design of Transposed Convolutions for Deep Learning Using High-Level Synthesis
Architecture and Finite Precision Optimization for Layered LDPC Decoders
One-Class Classification Framework Based on Shrinkage Methods
Instrumentation-Driven Validation of Dataflow Applications
DG2VHDL: A Tool to Facilitate the High Level Synthesis of Parallel Processing Array Architectures
A Secure Modular Division Algorithm Embedding with Error Detection and Low-Area ASIC Implementation
Guest Editorial: Real-Time and Embedded Systems
Dynamic Reconfiguration Technologies Based on FPGA in Software Defined Radio System
A chip-set for the Generalized Hough Transform
Ambulatory Hip Angle Estimation using Gaussian Particle Filter
Two Countermeasures Against Hardware Trojans Exploiting Non-Zero Aliasing Probability of BIST
High-Throughput Reconfigurable Variable Length Coding Decoder for MPEG-2 and AVC/H.264
Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic
VLSI Design of FM0/Manchester Encoder with Reuse-Oriented Boolean Simplification Technique for DSRC Applications
Performance Characterization of AES Datapath Architectures in 90-nm Standard Cell CMOS Technology
Efficient Timing Budget Management for Accuracy Improvement in a Collaborative Object Tracking System
Reconfigurable Coprocessor for Multimedia Application Domain
Analysis of Lifting and B-Spline DWT Implementations for Implantable Neuroprosthetics
A VLSI design methodology for distributed arithmetic
Distributed Spectrum Sensing Using Low Cost Hardware
A Technique with Low Memory and Computational Requirements for Dynamic Tracking of Quantiles
The Good, the Bad and the Ugly: Practices and Perspectives on Hardware Acceleration for Embedded Image Processing
Two-Symbol FPGA Architecture for Fast Arithmetic Encoding in JPEG 2000
Design of Complex Non-Linear Adaptive Equalizer in Mitigating Severe Intersymbol Interferences
Split and Merge EM Algorithm for Improving Gaussian Mixture Density Estimates
OpenDwarfs: Characterization of Dwarf-Based Benchmarks on Fixed and Reconfigurable Architectures
Non-rigid Registration for Large Sets of Microscopic Images on Graphics Processors
Fast-Converging and Low-Power LDPC Decoding: Algorithm, Architecture, and VLSI Implementation
Dynamic Sensor Self-Organization for Distributive Moving Target Tracking
Software Defined Radio - Guest Editorial
New Efficient Algorithms for Multiplication Over Fields of Characteristic Three
Rijndael FPGA Implementations Utilising Look-Up Tables
Macroblock Level Bits Allocation for Depth Maps in 3-D Video Coding
delta-Bit serial binary addition with linear threshold networks
Design and Optimization of Multiplierless FIR Filters Using Sub-Threshold Circuits
Self-timed logic using Current-Sensing Completion Detection (CSCD)
Energy-Delay Efficient Data Storage and Transfer Architectures and Methodologies: Current Solutions and Remaining Problems
Parallel reduced area multipliers
Feature-rich Regular Expression Matching Accelerator for Text Analytics
Performance Analysis of Weakly-Consistent Scenario-Aware Dataflow Graphs
Guest Editorial: Special Section on Multimedia Semantics
Low-error, High-speed Approximation of the Sigmoid Function for Large FPGA Implementations
Extraction of Video Objects via Surface Optimization and Voronoi Order
Edge-Fitting Based Energy Detection for Cognitive Radios
Naturalistic Scene Modelling: Deep Learning with Insights from Biology
On the Rapid Prototyping of a Portable Multi Media Acquisition System for Intelligent Meeting Capture
Loop Parallelization Techniques for FPGA Accelerator Synthesis
Power Optimization in VLSI Layout: A Survey
Evaluation of the Exact Throughput of a Synchronous DataFlow Graph
Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing
The design of wave digital filters using fully pipelined bit-level systolic arrays
A Fractional Sample Rate Converter with Parallelized Multiphase Output: Algorithm and FPGA Implementation
Reconfigurable Filter Coprocessor Architecture for DSP Applications
A ROM-less DDFS Based on a Parabolic Polynomial Interpolation Method with an Offset
CSP-based object-oriented description and simulation of a reconfigurable adaptive beamforming architecture using the OODRA workbench
Robust Multimodal Registration Using Local Phase-Coherence Representations
A Comparison of Fuzzy Clustering Approaches for Quantification of Microarray Gene Expression
Distribution Network Anomaly Detection Based on Graph Contrastive Learning
Configurable FFT Processor Using Dynamically Reconfigurable Resource Arrays
Projecting Gene Expression Trajectories through Inducing Differential Equations from Microarray Time Series Experiments
Real-Time Light Field Video Focusing and GPU Accelerated Streaming
High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard
Ontology-Based Event Modeling and High-Confidence Processing in IoT-Enabled High-Speed Train Control System
Wafer Scale Integration: A university perspective
Automatic Abstract Tag Detection for Social Image Tag Refinement and Enrichment
FPGA Parallel Recognition Engine for Handwritten Arabic Words
Cooperative Space-Time Coding with Amplify-and- Forward Relaying
Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs
Analysis and Evaluation of Various Fraud Detection Methods for Electronic Payment Cards Transactions in Big Data
Error Analysis and Efficient Realization of the Multiplier-Less FFT-Like Transformation (ML-FFT) and Related Sinusoidal Transformations
Automatic Recognition of Human Walking in Monocular Image Sequences
Fixed-Interval Kalman Smoothing Algorithms in Singular State-Space Systems
Microarray Image Processing and Quality Control
A Multi-Mode Sigma-Delta ADC for GSM/WCDMA/WLAN Applications
Grid-Based Storage Architecture for Accelerating Bioinformatics Computing
A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis
High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator
Energy Aware Algorithm and Implementation of SDR Oriented HSDPA Chip Level Equalizer
Automated Renal Cell Carcinoma Subtype Classification Using Morphological, Textural and Wavelets Based Features
Novel Heart Rate Detection Method Using UWB Impulse Radar
Inferring Nonstationary Gene Networks from Longitudinal Gene Expression Microarrays
A Diversity-based Selfish Node Detection Algorithm for Socially Aware Networking
A 2 MHz Wireless CMOS Transceiver for Implantable Biosignal Sensing Systems
Real-time, Robust and Adaptive Universal Adversarial Attacks Against Speaker Recognition Systems
A Systolic Design Methodology with Application to Full-Search Block-Matching Architectures
A Fast Mode Decision Algorithm Using Hierarchical and Skip Methods for Intra Prediction in HEVC
Combination of Amplitude and Frequency Modulation Features for Presentation Attack Detection
IMG: Deep Representation Graph Learning for Anomaly Detection in Industrial Control System
Reconstruction-Based Subband Image Coding for UDP Transmissions over the Internet
A 90 nm All-digital Smart Temperature Sensor with Wireless Body Area Network Baseband Transceiver for Biotelemetry Applications
Loop Transforming for Reducing Data Alignment on Multi-Core SIMD Processors
A 0.8V 40 Gb/s Novel CMOS Regulated Cascode Trans-impedance Amplifier for Optical Sensing Applications
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering
An Area-Efficient 4-Stream FIR Interpolation/Decimation for IEEE 802.11n WLAN
Non-Rigid Image Registration by Neural Computation
A Low-Power Multithreaded Processor for Software Defined Radio
Strategies for design automation of high speed digital filters
Characterization and Implementation of A Dynamic Neutron Imaging System at the PULSTAR Reactor
Predicting the Disulfide Bonding State of Cysteines with Combinations of Kernel Machines
A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing
A Custom Image Convolution DSP with a Sustained Calculation Capacity of >1 GMAC/s and Low I/O Bandwidth
Compressed-domain Fall Incident Detection for Intelligent Homecare
A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100 Gb/s Optical Communications
Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality
Graph Representation Learning for Similarity Stocks Analysis
Deterministic Time-Varying Packet Fair Queueing for Integrated Services Networks
Efficient Parallelization of Polyphase Arbitrary Resampling FIR Filters for High-Speed Applications
A 13 Gbps, 0.13 μm CMOS, Multiplication-Free MIMO Detector
Realization of a Reaction-Diffusion CNN Algorithm for Locomotion Control in an Hexapode Robot
Robust Human Tracking Based on DPM Constrained Multiple-Kernel from a Moving Camera
A Hybrid Simulation Approach for Fast and Accurate Timing Analysis of Multi-Processor Platforms Considering Communication Resources Conflicts
CBS: Contourlet-Based Steganalysis Method
A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI
A multi-ASIC real-time implementation of the two dimensional affine transform with a bilinear interpolation scheme
Simulation and Spectral Analysis of the Scrambler for 56Kbps Modem
Linear-Phase Lattice FIR Digital Filter Architectures Using Stochastic Logic
Fast multiplier bit-product matrix reduction using bit-ordering and parity generation
The Video Spatial Error Concealment Algorithm Using Separately-Directional Interpolation Technique
Vasculature Segmentation in MRA Images Using Gradient Compensated Geodesic Active Contours
An Intelligent Digital Microfluidic Processor for Biomedical Detection
New Models of Prefix Adder Topologies
Architectural Decomposition of Video Decoders by Meansof an Intermediate Data Stream Format