yusuke1997/dblp-id-title huggingface dataset:
Active Charge Balancer With Adaptive 3.3 V to 38 V Supply Compliance for Neural Stimulators
Designing Low-Power RISC-V Multicore Processors With a Shared Lightweight Floating Point Unit for IoT Endnodes
Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking
Disturbance-Observer-Based Finite-Time Antidisturbance Control for Markov Switched Descriptor Systems With Multi-Disturbances and Intermittent Measurements
Modular Multilevel Converter Impedance Computation Based on Periodic Small-Signal Analysis and Vector Fitting
A Thermal and Power Integrity Co-Optimization Framework for 2.5-D Integrated Microsystem
A 0.7-V Sub-mW Type-II Phase-Tracking Bluetooth Low Energy Receiver in 28-nm CMOS
An E-Band SiGe High Efficiency, High Harmonic Suppression Amplifier Multiplier Chain With Wide Temperature Operating Range
0.4-V Supply, 12-nW Reverse Bandgap Voltage Reference With Single BJT and Indirect Curvature Compensation
Low Delay Short Word Length Sigma Delta Active Noise Control
Low-Power Capacitively Coupled AC Amplifiers With Tunable Ultra Low-Frequency Operation
Approximate Equivalent Circuits to Understand Tradeoffs in Geometry of On-Chip Inductors
Saturated Sampled-Data Control of DAB DC-DC Converters via LPV Approach With Consideration of Mismatched Time-Varying Parameters
Digital Low-Cost FPGA Implementation of Two-Coupled and Grid-Based Network of 2D Artificial Cochlea Using the Hopf Resonator Approach
Finite-Time Decentralized Sliding Mode Control for Interconnected Systems and Its Application to Electrical Power Systems: A GA-Assisted Design Method
Adaptive Integral-Type NTSMC for DC-DC Buck Converters With Zero-Crossing Gain Under Matched and Mismatched Uncertainties
Weak Nonlinearities in Active Filters and Continuous-Time Pipeline ADCs
A Novel Single-Stage Single-Phase Dual-Output Hybrid Converter
An Analog SiPM Based Receiver With On-Chip Wideband Amplifier Module for Direct ToF LiDAR Applications
Chopper Instrumentation Amplifier Design With Fully Symmetric Loops for Input Impedance Boosting
A 1.25 μJ per Measurement Ultrasound Rangefinder System in 65 nm CMOS for Explorations With a Swarm of Sensor Nodes
Fixed-Time Fuzzy Control for Uncertain Nonlinear Systems With Prescribed Performance and Event-Triggered Communication
A Low Phase Noise Oscillator Employing Weakly Coupled Cavities Using SISL Technology
Side-Channel Analysis of Integrate-and-Fire Neurons Within Spiking Neural Networks
Continuation-Based Method to Find Periodic Windows in Bifurcation Diagrams With Applications to the Chua's Circuit With a Cubic Nonlinearity
Memristor-Based Selective Convolutional Circuit for High-Density Salt-and-Pepper Noise Removal
Prescribed-Time Control of Nonlinear Systems With Global Prescribed Performance for State Errors
Universal Finite-Time Observer-Based ITSMC for Converter-Driven Motor Systems With Disturbances
A Reliable Low Standby Power 10T SRAM Cell With Expanded Static Noise Margins
Accuracy-Configurable Radix-4 Adder With a Dynamic Output Modification Scheme
NS-FDN: Near-Sensor Processing Architecture of Feature-Configurable Distributed Network for Beyond-Real-Time Always-on Keyword Spotting
Frequency Selective Impedance Transformer With High-Impedance Transforming Ratio and Extremely High/Low Termination Impedances
Unified Adaptive Performance Control of MIMO Input-Quantized Nonlinear Systems
Reverse Calculation-Based Low Memory Turbo Decoder for Power Constrained Applications
Energy Efficient Resistor-Transconductor Hybrid-Based Full-Duplex Transceiver for Serial Link
Secure Estimation Against Malicious Attacks for Lithium-Ion Batteries Under Cloud Environments
Incoming Editorial
Broadband Doherty Power Amplifier Using Short Ended λ/4 Transmission Lines Based on the Analysis of Negative Characteristic Impedance
Signal Integrity Augmentation Techniques for the Design of 64-GBaud Coherent Transimpedance Amplifier in 90-nm SiGe BiCMOS
Simulation of Switched-Mode Power Conversion Circuits With Extended Impedance Method
Robust Formation Control for Multi-Agent Systems: A Reference Correction Based Approach
A Novel Memcapacitive-Synapse Neuron: Bionic Modeling, Complex Dynamics Analysis and Circuit Implementation
A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing
Decoupling Control of Fuel Cell Air Supply System Based on Data-Driven Feedforward and Adaptive Generalized Supertwisting Algorithm
Using Strictly Dissipative Impedance Coupling in the Waveform Relaxation Method for the Analysis of Interconnect Circuits
CMOS Full-Duplex Mixer-First Receiver With Adaptive Self-Interference Cancellation
A Dual-Domain Dynamic Reference Sensing for Reliable Read Operation in SOT-MRAM
Secure and Efficient Two-Party Quantum Scalar Product Protocol With Application to Privacy-Preserving Matrix Multiplication
Fixed-Time Backstepping Fractional-Order Sliding Mode Excitation Control for Performance Improvement of Power System
A Capacitor-Cross-Connected Boost Converter With Duty Cycle < 0.5 Control for Extended Conversion-Ratio and Soft Start-Up
Circuit-Level Exploration of Ternary Logic Using Memristors and MOSFETs
Modeling and Analysis of Spike Signal Sequence for Memristor Crossbar Array in Neuromorphic Chips
A 50-Gb/s PAM-4 Receiver With Adaptive Phase-Shifting CDR in 28-nm CMOS
A Single-Inductor Multiple-Output DC-DC Converter With Fixed-Frequency Victim-Last Charge Control for Reduced Cross Regulation
Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme
How to Build a Memristive Integrate-and-Fire Model for Spiking Neuronal Signal Generation
Adaptive Low-Order Harmonic Currents Suppression in AC Power System Using Fractional-Order Circuit
Efficient Hardware Architecture of Convolutional Neural Network for ECG Classification in Wearable Healthcare Device
An 85.1% Peak Efficiency, Low Power Class H Audio Amplifier With Full Class H Operation
Hardware Accelerator of Fractional-Order Operator Based on Phase Optimized Filters With Applications
A 132 dBSPL 67.34 dB-A SNR Single-Ended MEMS Microphone Using Self-Adaption Loop With 1.5-V Supply Voltage
Memory Technologies for Crossbar Array Design: A Comparative Evaluation of Their Impact on DNN Accuracy
DetectX - Adversarial Input Detection Using Current Signatures in Memristive XBar Arrays
Tsetlin Machine-Based Image Classification FPGA Accelerator With On-Device Training
Low-Voltage Low-Noise High-CMRR Biopotential Integrated Preamplifier
Exploring Speed Maximization of Frequency-to-Digital Conversion for Ultra-Low-Voltage VCO-Based ADCs
Efficient Adaptive Multi-Level Privilege Partitioning With RTrustSoC
Bayes2IMC: In-Memory Computing for Bayesian Binary Neural Networks
Uniformly Distributed CORDIC
Reconstructing Aliased Frequency Spectra by Using Multiple Sample Rates
Prescribed-Time Output Feedback Control for Nonlinear Systems via the Switched High-Order Sliding Mode
Investigation of ReRAM Variability on Flow-Based Edge Detection Computing Using HfO 2 -Based ReRAM Arrays
Dynamic Phasor and Nonstationary Power Theory as an Extension of Classical Phasor Theory
An Efficient Window-Based Vision Transformer Accelerator via Mixed-Granularity Sparsity
A 0.065 mm² Inductive Coupling Based Dual Core mm-Wave VCO With 183 dBc/Hz FoM T
Time Domain Solution Analysis and Novel Admissibility Conditions of Singular Fractional-Order Systems
A High Precision CV Control Scheme for Low Power AC-DC BUCK Converter Controller
A dB-Linear Programmable Gain Amplifier With Mixed-Signal Control for Wide-Gain Range and Low-Power Applications
Model-Based Power Management for Smart Farming Wireless Sensor Networks
A 46-nF/10-MΩ Range 114-aF/0.37-Ω Resolution Parasitic- and Temperature-Insensitive Reconfigurable RC-to-Digital Converter in 0.18-μm CMOS
The Charge Non-Conservation Paradox Implied by Loss Free Resistors
NASA-F: FPGA-Oriented Search and Acceleration for Multiplication-Reduced Hybrid Networks
Comments on "Analytical Design Equations for Class-E Power Amplifier"
Average Controllability of Cartesian Product Networks
Impact of Aging and Process Variability on SRAM-Based In-Memory Computing Architectures
Unfolding Nonlinear Dynamics in Analogue Systems With Mem-Elements
Anti-Piracy Design of RF Transceivers
A Detailed Model of Cyclostationary Noise in Switched-Resistor Circuits
A 1.5-2.7 GHz 3-dB NF 32-dB Notch-Depth Channel-Selection Balun-LNA Employing Dual Feedback and Feedforward N-Path Filter Loops for Advanced Cellular Application
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems - ISICAS 2023
Design of Adaptive SOSM Controller Subject to Disturbances With Unknown Magnitudes
Interleaved Challenge Loop PUF: A Highly Side-Channel Protected Oscillator-Based PUF
SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree
Optimization of the Power Flow Generated by an AC Energy Harvester for Variable Operating Conditions
An Investigation on the Three-Dimensional Memristive Morris-Lecar Model With Magnetic Induction Effects: Simulation of Biological Behaviors and Cost-Effective Digital Circuit Implementation
A Four-Channel TDM Clocked-Analog LDO Using a Shared Compensation Block for Thermo-Optic Tuning
Probabilistic-Constrained H ∞ Tracking Control for a Class of Stochastic Nonlinear Systems Subject to DoS Attacks and Measurement Outliers
Exploring Applications of STT-RAM in GPU Architectures
A Wideband Balanced Amplifier Using Edge-Coupled Quadrature Couplers in 0.13-μm SiGe HBT Technology
Quantum Tunneling Based Ultra-Compact and Energy Efficient Spiking Neuron Enables Hardware SNN
Finite-Time Event-Triggered Control for Semi-Markovian Switching Cyber-Physical Systems With FDI Attacks and Applications
Utilizing Multi-Body Interactions in a CMOS-Based Ising Machine for LDPC Decoding
Hardware-Efficient Emulation of Leaky Integrate-and-Fire Model Using Template-Scaling-Based Exponential Function Approximation
A Reconfigurable Full-Digital Architecture for Angle of Arrival Estimation
A Level Shifter With Almost Full Immunity to Positive dv/dt for Buck Converters
Experimental Study of Fractional-Order RC Circuit Model Using the Caputo and Caputo-Fabrizio Derivatives
A 16-bit 1-MS/s SAR ADC With Asynchronous LSB Averaging Achieving 95.1-dB SNDR and 98.1-dB DR
A V M -Terminated PAM-3 Transmitter Using Floating Middle Level With Enhanced Signal Integrity and Energy Efficiency for Low-Power Memory Interfaces
Design and Analysis of a Coupled-Line-Based Load-Modulated Balanced Amplifier MMIC With Enhanced Bandwidth Performance
A 92.6% Efficiency Rotated Hybrid Step-Down Converter With Rotated Parallel Operation for Flying Capacitor Charge Balance and Fast Transient Response
Physics-Guided Multi-Agent Deep Reinforcement Learning for Robust Active Voltage Control in Electrical Distribution Systems
Dual Memristive Chua's Circuit
A Synchronous Current Inversion and Energy Extraction Circuit for Electromagnetic Energy Harvesting Enhancement
Class-E Power Amplifiers Incorporating Fingerprint Augmentation With Combinatorial Security Primitives for Machine-Learning-Based Authentication in 65 nm CMOS
A 7.2-29.8 GHz LNA With 1.35-2.67-dB NF Using Coupled-Line-Based Transformers in 0.15- μm GaN-on-SiC Technology
Design of a Quadband Doherty Power Amplifier With Large Power Back-Off Range
A 270 nW Switched-Capacitor Acoustic Feature Extractor for Always-On Voice Activity Detection
Algorithm and Architecture Design of Random Fourier Features-Based Kernel Adaptive Filters
Analog Foreground Calibration of High-Resolution SAR ADC
28 GHz Compact LNAs With 1.9 dB Minimum NF Using Folded Three-Coil Transformer and Dual-Feedforward Techniques for Phased Array Systems
Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T SRAM With Multi-Node Upset Recoverability for Aerospace Applications
A Study on Noise Folding Due to Nonlinearity in Fractional-N CP PLL
An Efficient Implementation of Convolutional Neural Network With CLIP-Q Quantization on FPGA
Design of Soft-Error-Aware SRAM With Multi-Node Upset Recovery for Aerospace Applications
Memory Access Optimization for On-Chip Transfer Learning
A Robust Time-Based Multi-Level Sensing Circuit for Resistive Memory
A Low-Complexity and High-Throughput Hardware Design for Lempel-Ziv 4 Compression Algorithm
Constant Off-Time-Based Current-Balancing Technique With Accuracy and Transient Optimization in Wide I/O Range for Multi-Phase Regulator
Effect of Device Mismatches in Differential Oscillatory Neural Networks
Accurately Modeling Zero-Bias Diode-Based RF Power Harvesters With Wide Adaptability to Frequency and Power
A -31 dBm Sensitivity High-Efficiency RF Energy Harvesting System With Burst Charging Mode for IoT Applications
A 94.6 dB-SNDR 20 μW Extended-Counting Incremental ADC Based on Dynamic Amplifier With Gain Calibration
An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme
State Bumpless Transfer Control for a Class of Switched Descriptor Systems
A Switched Capacitor Modified Fibonacci Cell Used for a DC-AC Circuit Supplied by Solar Energy
Area-Efficient QC-LDPC Decoding Architecture With Thermometer Code-Based Sorting and Relative Quasi-Cyclic Shifting
An Efficient Image Encryption Algorithm Based on Innovative DES Structure and Hyperchaotic Keys
An Active Resistor for Ultra Low Power Applications
Guest Editorial A New Exciting Year Ahead for TCAS-I
Accurate Design of Output Filter for DC-DC PWM Buck Converter and Derived Topologies
FACET: On-the-Fly Activation Compression for Efficient Transformer Training
Chimera States in Neuro-Inspired Area-Efficient Asynchronous Cellular Automata Networks
NTT Architecture for a Linux-Ready RISC-V Fully-Homomorphic Encryption Accelerator
A Sneak Current Compensation Scheme With Offset Cancellation Sensing Circuit for ReRAM-Based Cross-Point Memory Array
Capacitance-to-Digital Converter for Harvested Systems Down to 0.3 V With No Trimming, Reference, and Voltage Regulation
Balanced and Unbalanced Duplexers Using Common Oval Dielectric Resonators
Data-Driven Passivity Analysis and Fault Detection Using Reinforcement Learning
Design of a Novel Self-Test-on-Chip Interface ASIC for Capacitive Accelerometers
Controller Synthesis of Aperiodic Sampled-Data Networked Control System With Application to Interleaved Flyback Module Integrated Converter
Distributed Composite Learning Dynamic Event-Triggered Control for Nonlinear Multi-Agent Power Systems
Sampled-Data-Based Bipartite Leader-Follower Synchronization of Cooperation-Competition Neural Networks via Interval-Scheduled Looped-Functions
FAPSO: Fast Adaptive Particle Swarm Optimization-Based Background Timing Skew Calibration for TI-ADCs
Improved Hopfield Network Optimization Using Manufacturable Three-Terminal Electronic Synapses
An Active EMI Cancellation Technique Achieving a 25-dB Reduction in Conducted EMI of LIN Drivers
High Logic Density Cyclic Redundancy Check and Forward Error Correction Logic Sharing Encoding Circuit for JESD204C Controller
Distributed Hybrid Dynamic Event-Triggered Bipartite Consensus Control for Multi-Agent Systems Against DoS Attacks
Practically Finite-Time ADRC for a 3-DOF Parallel Mechanism of PMAs With Couplings
Reciprocity and Inter-Reciprocity: A Tutorial - Part II: Linear Periodically Time-Varying Networks
Dynamic Dataflow Scheduling and Computation Mapping Techniques for Efficient Depthwise Separable Convolution Acceleration
Multi-Memristor Based Distributed Decision Tree Circuit for Cybersecurity Applications
A 70-to-2 V Triboelectric Energy Harvesting System Utilizing Parallel-SSHI Rectifier and DC-DC Converters
A Neuromorphic Transformer Architecture Enabling Hardware-Friendly Edge Computing
An Advanced Fault-Tolerant HANPC Converter With Neutral-Point Voltage Balancing for Full Power Factor Range Under Multi-Switch Open-Circuit Fault
Squeezing Area of the Versatile GF (2 m ) GNB Arithmetic Operators
Impact of Nonideal Auxiliary Current Profile on Linearity of Microwave Doherty Amplifiers: Theory and Experiments
A Self-Matching Rectifier Based on an Artificial Transmission Line for Enhanced Dynamic Range
Digital Residual Alias Cancellation for Filtering-by-Aliasing Receivers
Fault-Tolerant H ∞ Output Regulation of Uncertainty Multi-Agent Systems via Anti-Saturation Policy Learning
A Power-Efficient Active-RC Filter Using Passive Integrator and OTA With Push-Pull Output
Two-Phase Hybrid Buck-Boost Converter With Coupled-Inductors Under ZVS Operation for USB PD Bidirectional Conversion
GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy
A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS
A Novel Nociceptor Functional Circuit for Tactile Applications
Extracting RLC Parasitics From a Flexible Electronic Hybrid Assembly Using On-Chip ESD Protection Circuits
Fast and Accurate Inference on Microcontrollers With Boosted Cooperative Convolutional Neural Networks (BC-Net)
An 8-Bit 800 MS/s Loop-Unrolled SAR ADC With Common-Mode Adaptive Background Offset Calibration in 28 nm FDSOI
An 11uW, 0.08 mm 2 , 125dB-Dynamic-Range Current-Sensing Dynamic CT Zoom ADC
Spatial-Temporal Hybrid Neural Network With Computing-in-Memory Architecture
An Adaptive 56-Gb/s Duo-PAM4 Detector Using Reduced Branch Maximum Likelihood Sequence Detection in a 28-nm CMOS Wireline Receiver
Stabilization of Impulsive Systems With Beyond-Interval Impulse Delays
Analysis and Design of a Broadband Output Stage With Current-Reuse and a Low Insertion-Loss Bypass Mode for CMOS RF Front-End LNAs
A Linear High-Efficiency Distributed Power Amplifier Utilizing Class-AB and Inverse-Class-C Complementary Structure
Design of Multi-Port With Desired Reference Impedances Using Y-Matrix and Matching Networks
Differential Flatness of Single-Input Commensurate Delay Systems With Applications to Trajectory Planning, Tracking, and Transformation to Fully Actuated Systems
Virtual-Sensor-Based Model-Free Adaptive Fault-Tolerant Constrained Control for Discrete-Time Nonlinear Systems
A Fast and Fully Parallel Analog CMOS Solver for Nonlinear PDEs
A Time-to-Voltage Converter-Based MPPT With 440 μs Online Tracking Time, 99.7% Tracking Efficiency for a Battery-Less Harvesting Front-End With Cold-Startup and Over-Voltage Protection
Maestro: A 302 GFLOPS/W and 19.8GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing
Design and Characterization of 10 Gb/s and 1 Grad TID-Tolerant Optical Modulator Driver
Guest Editorial Special Issue on the IEEE Latin American Symposium on Circuits and Systems (LASCAS 2023)
Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur
Machine Learning Methodologies to Predict the Results of Simulation-Based Fault Injection
FAS-NoC: A Real-Time Fused Approximation Scheme Coordinating Communication and Computation for NoC-Based NN Accelerators
Area and Power-Efficient Variable-Sized DCT Architecture for HEVC Using Muxed-MCM Problem
Initial-Boosted Behaviors and Synchronization of Memristor-Coupled Memristive Systems
Optimized Algorithms for FPGA Implementation of PDCCH Chain for 5G-NR Base Station
Positivity and Stability of Cohen-Grossberg-Type Memristor Neural Networks With Unbounded Delays
Optimized MASH-SR Divider Controller for Fractional-N Frequency Synthesizers
A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler
Interconnection, Reciprocity and a Hierarchical Classification of Generalized Multiports
A Dual-Branch Series-Parallel Hybrid Buck DC-DC Converter With Flying Capacitor Voltage Auto-Balancing
Tunable CMOS Pseudo-Resistors for Resistances of Hundreds of GΩ
A Multi-Stage RC Compensation Technique for Decoupling the Transimpedance and BW: Creating High Speed and Low Noise TIA Designs
Process, Bias, and Temperature Scalable CMOS Analog Computing Circuits for Machine Learning
A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM
Model Order Reduction for Delayed PEEC Models With Guaranteed Accuracy and Observed Stability
A Signal Flow Graph Approach to the Resolution of Spherical Triangles Using CORDIC
Polytopic Event-Triggered Robust Model Predictive Control for Constrained Linear Systems
Theory and Low-Power Design of Moving Accumulative Sign Filter
A 20.3μW 1.9GΩ Input Impedance Capacitively-Coupled Chopper-Stabilized Amplifier for Bio-Potential Readout
Model Predictive Control of Overloaded Stand-Alone Hybrid AC/DC Microgrids
Adaptive Practical Fixed-Time Tracking Control With Prescribed Boundary Constraints
TT-CIM: Tensor Train Decomposition for Neural Network in RRAM-Based Compute-in-Memory Systems
Pursuit-Evasion Game for Spacecraft With Incomplete Information Under J₂ Perturbation
Impact of Analog Non-Idealities on the Design Space of 6T-SRAM Current-Domain Dot-Product Operators for In-Memory Computing
A Dual Slope Boosted Relaxation Oscillator With 2.93 μJ/Cycle Energy Efficiency and 0.068% Period Jitter in 180 nm CMOS
A Symmetrical Impedance Compensation Configuration for Optimized IPT Systems
Nonlinear Control Design and Stability Analysis of Single Phase Half Bridge Interleaved Buck Shunt Active Power Filter
A High-Efficiency RFEH System With Feedback-Free Fast (F 3 ) MPPT Over a Wide Input Range
Adaptive Filtering Over Complex Networks in Intricate Environments
A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < -80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging
17-aF rms Resolution Noise-Immune Fingerprint Scanning Analog Front-End for Under-Glass Mutual-Capacitive Fingerprint Sensors
A Novel Distributed Predefined-Time Sliding Mode Controller for Performance Enhancement of Power System Under Input Saturation
Nonlinear Analysis of Charge-Pump Phase-Locked Loop: The Hold-In and Pull-In Ranges
LSTM-NN-Enhanced Tracking Control for PAM-Driven Parallel Robot Systems With Guaranteed Performance
LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies
Energy Efficiency of Opportunistic Refreshing for Gain-Cell Embedded DRAM
Analysis and Design of Broadband Balance-Compensated Transformer Baluns for Silicon-Based Millimeter-Wave Circuits
Ultra-Fast FPGA Implementation of Graph Cut Algorithm With Ripple Push and Early Termination
Design and Analysis of Flexible Capacitive Power Transfer With Stable Output Capability
An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors
BSViT: A Bit-Serial Vision Transformer Accelerator Exploiting Dynamic Patch and Weight Bit-Group Quantization
Relation Between INL and ACPR of RF DACs
Analog/Digital Multiplierless Implementations for Nullcline-Characteristics-Based Piecewise Linear Hindmarsh-Rose Neuron Model
Multi-Stage Speculative PAM4 Decision Feedback Equalizer for Short Reach Applications
A 76-81-GHz Four-Channel Digitally Controlled CMOS Receiver for Automotive Radars
ENAP: An Efficient Number-Aware Pruning Framework for Design Space Exploration of Approximate Configurations
A Sub-1/°C Bandgap Voltage Reference With High-Order Temperature Compensation in 0.18-μm CMOS Process
C2PAx: Complexity-Aware Constant Parameter Approximation for Energy-Efficient Tree-Based Machine Learning Accelerators
Characterization of Inter-Cell Interference in 3D NAND Flash Memory
High Efficiency Active Rectifier Using SAR Digital-to-Time Converter for Wireless Power Transfer System
Event-Triggered H ∞ Filtering for Discrete-Time Switched Systems Under Denial-of-Service
Flexible Quadrature Spatial Modulation: Transmission, Detection, and Implementation
Byzantine-Resilient Impulsive Control for Bipartite Consensus of Heterogeneous Multiagent Systems
H ∞ Filter and Extended State Observer-Based Disturbance Rejection Control for Systems With Uncertainty and Noise
A 75.6 Gb/s 22-bit Floating-Point Coarse-Grained Versatile DSP Embedding 26K-Point Baseband Signal Processing and 2048 × 256-Point Complex FFT
Global Event-Triggered Output Feedback Stabilization for a Class of Nonlinear Time-Delay Systems
Multi-Valued Model for Generating Complex Chaos and Fractals
Bandwidth-Enhanced Mixed-Mode Outphasing Power Amplifiers Based on the Analytic Role-Exchange Doherty-Chireix Continuum Theory