yusuke1997/dblp-id-title huggingface dataset:
LWRpro: An Energy-Efficient Configurable Crypto-Processor for Module-LWR
A Heterogeneous Parallel Non-von Neumann Architecture System for Accurate and Efficient Machine Learning Molecular Dynamics
Predicting Higher-Order Dynamics With Unknown Hypergraph Topology
Modeling and Simulation of Variable Limits on Conditional Anti-Windup PI Controllers for VSC-Based Devices
Adaptive Protocol-Based Control for Nonhomogeneous Stochastic Jump Systems With DoS Attacks and Applications
Filter-Based Fully Distributed Output Regulation of Heterogeneous Learning Agents
Designing Low-Loss Single-Inductor Multiple-I/O (SL-MI/O) CMOS Power Supplies
The Intrinsic Communication in Power Systems: A New Perspective to Understand Synchronization Stability
An Entropy-Source-Preselection-Based Strong PUF With Strong Resilience to Machine Learning Attacks and High Energy Efficiency
A 0.85mm 2 BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch
An Efficient Unified Polynomial Arithmetic Unit for CRYSTALS-Dilithium
An Efficient CNN Inference Accelerator Based on Intra- and Inter-Channel Feature Map Compression
An Energy-Efficient Stream-Based FPGA Implementation of Feature Extraction Algorithm for LiDAR Point Clouds With Effective Local-Search
An Automated Circuit Topology Generation and Optimization Method for CMOS Low-Noise Amplifiers
A Wireless-Powered Battery-Less Electrical Stimulator With Delay-Shift Keying (DSK) Based Downlink Data Communication
Max-Pooling PD: A Machine Learning-Based Timing Recovery Method
Which Kind of Power Network Topology Is More Robust? Case Study for Design of Power Grids
Distributed Consensus Control of Nonlinear Multiagent Systems With Actuator Deception Attacks
A 97 dB-CMRR Gm-Controlled Inverter-Based Amplifier Employing Multi-CMFB Loops for Multi-Channel Bio-Signal Recording
An Interleaved Hybrid-Module Step-Up Converter With Reduction of Switching Frequency and Output Ripple
An 800 nW Switched-Capacitor Feature Extraction Filterbank for Sound Classification
A 6.15-10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With "Phase Reset" Scheme
A Hybrid Single-Inductor Bipolar Triple-Output DC-DC Converter With High-Quality Positive Outputs for AMOLED Displays
Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior
Multiple-Resolution Decoding Architecture for QC-LDPC Codes
Design and Analysis of Approximate Compressors for Balanced Error Accumulation in MAC Operator
Fully Integrated Galvanic Isolation Interface in GaN Technology
A 36-55 V Input 0.6-2.5 V Output Bypass-Assist Series-Capacitor Power Converter With 93.1% Peak Efficiency and 1.5 mA-5 A Load Range
A Fixed Latency ORBGRAND Decoder Architecture With LUT-Aided Error-Pattern Scheduling
Research on an Inference Algorithm for a Series of Three-Port Converter Topologies
28-nm CMOS Ultrasound AFE With Split Attenuation for Optimizing Gain-Range, Noise, and Area
The Parallel Chaotification Map and Its Application
Leaderless Cluster Consensus of Second-Order General Nonlinear Multiagent Systems Under Directed Topology
A Foreground Mismatch and Memory Harmonic Distortion Calibration Algorithm for TIADC
Joint Resource Allocation for RIS-Assisted Heterogeneous Networks With Centralized and Distributed Frameworks
A High-Performance Memristive Circuit Design for DCGAN in Edge Computing
A Wide Dynamic Range Multi-Sensor ROIC for Portable Environmental Monitoring Systems With Two-Step Self-Optimization Schemes
Bio-Inspired Neuromorphic Circuit Design of Nonassociative Learning for Multisensory Enhancement and Depression
Finite-Time Event-Triggered Adaptive Fault-Tolerant Tracking for Semi- Bounded Non-Affine Systems
A 50-ps Gated VCRO-Based TDC With Compact Phase Interpolators for Flash LiDAR
A Hybrid Bridge Push-Pull Forward Resonant Converter With Fixed Frequency PWM Control for High-Reliability Application
A Self-Matched Multi-Band Rectifier for Efficient Electromagnetic Energy Harvesting
Workload Compression Techniques to Scale Defect-Centric BTI Models to the Circuit Level
Leader-Follower Formation Control via Fixed-Time Distributed Observer Over Directed Topology: Theories and Applications
An 18-Tb/s/mm PAM-3 On-Chip Link With Jitter-Suppressing 3T4T Coding and FFE-Based Crosstalk Cancellation for Memory Interfaces
A 2.4-GHz Ring-VCO-Based Sub-Sampling PLL With a -70-dBc Reference Spur by Adopting a Capacitor-Multiplier-Based Sub-Sampling DLL
Hybrid Stochastic-Binary Computing for Low-Latency and High-Precision Inference of CNNs
Brain-Inspired Recognition System Based on Multimodal In-Memory Computing Framework for Edge AI
An Energy-Efficient Neuromorphic Accelerator Based on Deformable Spiking Transformer for Dynamic Vision Sensor
Low-Latency 64-Parallel 4096-Point Memory-Based FFT for 6G
A 0.88 e‾ rms 8-Mpixel 3D-Stacked Low Temporal-Noise CMOS Image Sensor With Auto-Zero Single-Slope ADC, Fast Correlated Multi-Sampling, Row-Wise Noise Reduction, and Dark Current Non-Uniformity Calibration Techniques
CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration
Design Method of Reconfigurable N-Way Power Divider Based on Reconfigurable Impedance Matching Network
Arithmetic and Logic Circuits Based on ITO-Stabilized ZnO TFT for Transparent Electronics
Design of a Contingent Decision Equalizer Using Analog-in-Time Processing for PAMN Wireline Receivers
An Ultra-Low Quiescent Current Tri-Mode DC-DC Buck Converter With 92.1% Peak Efficiency for IoT Applications
A 1.2-A Calibration-Free Hybrid LDO With In-Loop Quantization and Auxiliary Constant Current Control Achieving High Accuracy and Fast DVS
On-Chip Configurable RF Energy Harvester for Biomedical Implantable Devices
Hardware-Efficient Multipliers With FPGA-Based Approximation for Error-Resilient Applications
Domain-Specific Hyperdimensional RISC-V Processor for Edge-AI Training
Parasitic Mismatch Mitigation for Fast Switching Modular Power Semiconductor Devices
A Sensitivity Analysis Method for a Class of Cyber-Physical Systems and Its Application to Parameter Optimization
Energy and Bandwidth Efficient Sparse Programmable Dataflow Accelerator
Load Frequency Control of Power Systems With Multiple Transmission Delays Under Aperiodic Sampled-Data
Comments on "Architectural Evolution of Integrated M-Phase High-Q Bandpass Filters"
A Study of BER and EVM Degradation in Digital Modulation Schemes Due to PLL Jitter and Communication-Link Noise
Inverse Modelling Techniques as Dynamic Digital Pre-Distortion for Broadband Systems for CS-DACs Based on Volterra Series Expansion
A 6-to-7.5-GHz 54-fs rms Jitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction
Experimental Verification of Disturbance Observer-Based Backstepping Control for DC-DC Boost Converter
In-Memory Acceleration of Hyperdimensional Genome Matching on Unreliable Emerging Technologies
A New Approach of Formation Control for Multi-Agent Systems With Environmental Changes
FastGW: A Machine Learning-Based Early Skip for the AV1 Global Warped Motion Compensation
Stability of Logical Dynamic Systems With a Class of Constrained Switching
Resilience-Based Output Formation-Containment Control of Nonlinear MASs Against DOS Attacks
A 90-GHz Asymmetrical Single-Pole Double-Throw Switch With >19.5-dBm 1-dB Compression Point in Transmission Mode Using 55-nm Bulk CMOS Technology
Globally Coupled Private Image Encryption Algorithm Based on Infinite Interval Spatiotemporal Chaotic System
A High Linearity TDC With a United-Reference Fractional Counter for LiDAR
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems - ISICAS 2025
Signal and Noise Analysis of an Open-Circuit Voltage Pixel for Uncooled Infrared Image Sensors
A 0.65 V 4 dB NF 2.4 GHz Sub-Passive RF Down-Converter With Trans-Frequency Current-Reusing Scheme Achieving Low Flicker Noise and High Linearity
A 0.22-μW Single-Bit VCO-Based Time-Domain Sensor-to-Digital Front-End With Reduced Supply Sensitivity
Multilayer Financial Complex Networks and Their Applications
Adaptive Event-Triggered Control for PDE-ODE Cascade Systems via Hierarchical Sliding Mode
Synthesis and Design of Shunt Resonator-Based Phase Shifters With Reduced Phase Error and In-Band Magnitude Ripple
A Sub-Electron-Noise Multi-Channel Cryogenic Skipper-CCD Readout ASIC
A Novel Design Method for CML Frequency Divider Based on C/I d and G/I d and Application for Quadrature-Injection CML Frequency Dividers
A Two-Level Energy Management Strategy for Multi-Microgrid Systems With Interval Prediction and Reinforcement Learning
A Collaborative Design of Broadband, High Linearity, and Flat Gain GaAs On-Chip Limiting LNA With Filtering Characteristic
A 10.4-16-Gb/s Reference-Less Baud-Rate Digital CDR With One-Tap DFE Using a Wide-Range FD
A Continuously-Scalable-Conversion-Ratio Step-Up/Down SC Energy-Harvesting Interface With MPPT Enabled by Real-Time Power Monitoring With Frequency-Mapped Capacitor DAC
Non-Singular Fixed-Time Tracking Control of Uncertain Nonlinear Pure-Feedback Systems With Practical State Constraints
Adaptive Anti-Disturbance Bumpless Transfer Control for Switched Neural Network Systems With Its Application to Switched Circuit Model
Novel Finite-Time Reliable Control Design for Memristor-Based Inertial Neural Networks With Mixed Time-Varying Delays
An Energy-Efficient Capacitive-RRAM Content Addressable Memory
Dynamic Event-Triggered Control for Hierarchical Differential Games
A Novel 9T1C-SRAM Compute-In-Memory Macro With Count-Less Pulse-Width Modulation Input and ADC-Less Charge-Integration-Count Output
Fixed-Time Neurodynamic Approach With Limited Interaction for Variable-Coupled Resource Allocation
A 0.0022 mm² 10 bit 20 MS/s SAR ADC With Passive Single-Ended-to-Differential-Converter
Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories
Polynomial Sliding Surfaces to Control a Boost Converter With Constant Power Load
Attention Mechanism Combined With Deep Recurrent Network for Nonlinear Circuit Macromodeling
The Advances in Conversion Techniques in Triboelectric Energy Harvesting: A Review
A Multi-Channel Neural Recording System With Neural Spike Scan and Adaptive Electrode Selection for High-Density Neural Interface
Generalized FRM-Based P-L Band Multi-Channel Channelizers for Array Signal Processing System
Machine Learning for On-the-Fly Reliability-Aware Cell Library Characterization
A 2 nJ/bit, 2.3% FSK Error Fully Integrated Sub-2.4 GHz Transmitter With Duty-Cycle Controlled PA for Medical Band
More is Less: Domain-Specific Speech Recognition Microprocessor Using One-Dimensional Convolutional Recurrent Neural Network
An Active-Under-Coil RFDAC With Analog Linear Interpolation in 28-nm CMOS
A Wideband and Highly Efficient Circulator Load Modulated Power Amplifier Architecture
A Single-Ended PAM-4 Transmitter Using Unstacked Tailless CML Driver and Coefficient-Corrected FFE for Memory Interfaces
A Low-Power Hybrid-Precision Neuromorphic Processor With INT8 Inference and INT16 Online Learning in 40-nm CMOS
ZDD: A Zero Delay Deviation Variability-Aware Golden Free Hardware Trojan Detection Using Physical Unclonable Function
Adaptive Tracking Control for Nonlinear Fully Actuated Systems With Input Quantization
A 43.9 μs IRS Controller SoC With Grid-Based Phase-Shift Optimization in 28 nm CMOS Technology for Next- Generation Communication
Hamilton Energy Characteristics of Chaotic Systems and Energy Flow in Magnetically Coupled Circuits
Miniaturization of a Nuclear Magnetic Resonance System: Architecture and Design Considerations of Transceiver Integrated Circuits
Optimization of Quantum Circuits for Stabilizer Codes
Average Controllability of Complex Networks With Exponential Degree Distribution
A Combined Analytical and Simulation-Based Methodology for Quantifying the Noise-Power-Area Trade-Offs in Biomedical Amplifiers
Modeling and Nonlinear Dynamic Behavior Analysis of Photovoltaic-Energy Storage DC Microgrid
Voltage Control Ratiometric Readout Technique With Improved Dynamic Range and Power-Efficiency for Open-Loop MEMS Capacitive Accelerometer
A High Accuracy and Bandwidth Digital Background Calibration Technique for Timing Skew in TI-ADCs
A Novel Method for Authentication Using Chaotic Behaviour of Chua's Oscillator in (n,k) Secret Shared Data Scheme for Secure Communication
Failure in Ring Oscillators With Capacitive Load
A Cascaded Mode-Switching Sub-Sampling PLL With Quadrature Dual-Mode Voltage Waveform-Shaping Oscillator
Distributed Nash Equilibrium Seeking for Aggregative Games With Directed Communication Graphs
Flexible FPGA Gaussian Random Number Generators With Reconfigurable Variance
Carry Disregard Approximate Multipliers
A 20 MHz-2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS
Quaternion Recursive Maximum Correntropy and Versoria Criterion Algorithm for Channel Estimation Under Impulsive Noise
Analysis and Mitigation of Excess Phase Noise and Spurs in Digital-to-Time-Converter-Enhanced Fractional- N Frequency Synthesizers
Enhancing All-to-All RRAM Ising Machines With Randomized Granular Update Strategies for Solving Combinatorial Optimization Problems
Self-Contained Dual-Input Interferometric Receiver for Paralleled-Multichannel Wireless Systems
An Efficient Flash-Based Computing-in-Memory (CIM) Demonstration of High-Precision (32-bit) Nonlinear Partial Differential Equation (PDE) Solver With Ultra-High Endurance and Reliability
Generating Grid Multiscroll Memristive Chua's Circuit and Its Predefined-Time Synchronization for Secure Communication
A 5.6-dB Noise Figure, 63-86-GHz Receiver Using a Wideband Noise-Cancelling Low Noise Amplifier With Phase and Amplitude Compensation
Transient Stability Enhancement Control for Virtual Synchronous Generator Controlled Isolated Power Grid
An Efficient CNN Accelerator Exploiting Novel Tile-Based Near-Structured Sparsity to Achieve Multi-Level Irregularity Elimination
Fixed-Time Stabilization for Nonlinear Systems With Low-Order and High-Order Nonlinearities via Event-Triggered Control
Event-Based Neural Networks Adaptive Control of Nonlinear Systems: A Fully Actuated System Approach
A High Precision Analog Temperature Compensated Crystal Oscillator Using a New Temperature Compensated Multiplier
An Efficient, Dynamically Adjustable, Multipurpose Ultrasound Digitizer Array in 40 nm CMOS
A Universal Discrete Memristor With Application to Multi-Attractor Generation
A K-/Ka-Band Broadband Low-Noise Amplifier Based on the Multiple Resonant Frequency Technique
A Heterogeneous System With Computing in Memory Processing Elements to Accelerate CNN Inference
Detection and Mitigation of nBTI Aging of a High Precision Current Comparator in 16 nm FinFET Technology
A 14 GHz Integer-N Sub-Sampling PLL With RMS-Jitter of 85.4 fs Occupying an Ultra Low Area of 0.0918 mm 2
Bidirectional High Step-Up/Down DC/DC Converter With a Coupled Inductor and Switched Capacitor
A New Kind of Locked Circuit: The Quasi-Periodic Locked Loop (Q-PLL)
A Critical-Set-Based Multi-Bit Successive Cancellation List Decoder for Polar Codes: Algorithm and Implementation
Generating Any Number of Diversified Hidden Attractors via Memristor Coupling
Adaptive Event-Triggered Output Feedback for Nonlinear Systems With Unknown Polynomial-of-Output Growth Rate
DPCrypto: Acceleration of Post-Quantum Cryptography Using Dot-Product Instructions on GPUs
A 120-MHz Broadband Differential Linear Driver With Channel Mismatch Cancellation and Bandwidth Extension for B-PLC Applications
A 5-MS/s 93.4-dB-DR Three-Step Incremental Zoom ADC With Single Sampling
A 6-12 GHz Wideband Low-Noise Amplifier With 0.8-1.5 dB NF and ±0.75 dB Ripple Enabled by the Capacitor Assisting Triple-Winding Transformer
A New Message Expansion Structure for Full Pipeline SHA-2
An Approach to Estimate Lithium-Ion Battery State of Charge Based on Adaptive Lyapunov Super Twisting Observer
Design and Analysis of a 28 GHz Bandwidth DC Coupled Active Balun With Phase-Amplitude Compensation in 40-nm CMOS
Highly-Isolated RF Power and Information Receiving System Based on Dual-Band Dual-Circular-Polarized Shared-Aperture Antenna
A Real-Time and Efficient Optical Flow Tracking Accelerator on FPGA Platform
FPGA-NHAP: A General FPGA-Based Neuromorphic Hardware Acceleration Platform With High Speed and Low Power
Low-Power and Scalable BEOL-Compatible IGZO TFT eDRAM-Based Charge-Domain Computing
Fractionally-Spaced Equalizers as Clock and Data Recovery Loops
Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization
Fast Hardware Architecture With Efficient Matrix Computations for the Key Generation of Classic McEliece
HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems
An Integrated Tradeoff Design of Reduced-Order Diagnostic Observer for Event-Triggered Fault Detection
Triple Ladder Lumped Circuit With Sixth Order Modal Exceptional Degeneracy
A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS
Reinforcement Learning-Based Fault Tolerant Control Design for Aero-Engines With Multiple Types of Faults
VSLAM-BA: Algorithm and Hardware Co-Design for High Performance and Energy-Efficient Visual SLAM Backend Hardware Accelerator
Analog Solutions of Discrete Markov Chains via Memristor Crossbars
Distributed Moving Horizon Estimation Over Energy Harvesting Wireless Sensor Networks: A Switching Topology Approach
Taxonomy and Benchmarking of Precision-Scalable MAC Arrays Under Enhanced DNN Dataflow Representation
Delay Difference Feedback Memristive Map: Dynamics, Hardware Implementation, and Application in Path Planning
Comprehensive Analysis of Voltage Step-Up Techniques for Isolated SEPIC
Multi-Stream Spatial Digital Predistortion for Fully-Connected Hybrid Beamforming Massive MIMO Transmitters
Passive Frequency Shifting of N-Path Filters Through Rotary Clocking: Analysis and Design
Area-Efficient Number Theoretic Transform Architecture for Homomorphic Encryption
Spiral-Transform-Based Fractal Sorting Matrix for Chaotic Image Encryption
Adaptive Filtering With Reduced Computational Complexity Using SOPOT Arithmetic
Stabilization of Time Scale-Type Nonlinear Systems With Stochastic Impulses
A Fully Probabilistic Model for Sigmoid Approximation and Its Hardware- Efficient Implementation
Side Channel Security Oriented Evaluation and Protection on Hardware Implementations of Kyber
Intermittent Dynamic Output Feedback Control for State-Based Stochastic Switched Systems and Its Application to Electronic Circuits
Improving Coding Efficiency of Massive Parallel Intra Prediction Using Alternative References
FPGA-Type Configurable Coprocessor Implementation Scheme of Recurrent Neural Network for Solving Time-Varying QP Problems
FlexDCIM: A 400 MHz 249.1 TOPS/W 64 Kb Flexible Digital Compute-in-Memory SRAM Macro for CNN Acceleration
Circuit Transfer Matrix: A Novel Approach to Enhancing Circuit Analysis Efficiency by Extending the Transfer Matrix Method for Multibody System
Dynamic Event-Triggered Byzantine-Resilient Output Regulation in Continuous-Time High-Order Multiagent Systems With Static/Dynamic Leader
Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors
Nonovershooting Tracking Control for Nonlinear Output Feedback Systems With Application to DC Motor
Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques
Digital Hardware Implementation of Morris-Lecar, Izhikevich, and Hodgkin-Huxley Neuron Models With High Accuracy and Low Resources
An All-Digital, 1.92-7.32 mV/LSB, 0.5-2 GS/s Sample Rate, and 0-Latency Prediction Voltage Sensor With Dynamic PVT Calibration for Droop Detection and AVS System
EPHIC Models: General SPICE Photonic Models for Closed-Loop Electronic-Photonic Co-Simulation
Fixed-Complexity Tree Search Schemes for Detecting Generalized Spatially Modulated Signals: Algorithms and Hardware Architectures
NoPUF: A Novel PUF Design Framework Toward Modeling Attack Resistant PUFs
Optimal Resource Allocation Between Two Nonfully Cooperative Wireless Networks Under Malicious Attacks: A Gestalt Game Perspective
The Impact of Distorted Signals on the Resistance of the Current Path in a Mechanical Connector
Continuous-Mode Hybrid Asymmetrical Load- Modulated Balanced Amplifier With Three-Way Modulation and Multi-Band Reconfigurability
Hardware Acceleration and Implementation of Fully Homomorphic Encryption Over the Torus
A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems - ISICAS 2024
A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration
Training Neural Networks With In-Memory-Computing Hardware and Multi-Level Radix-4 Inputs
Discrete-Time General Nonlinear Robust Control: Stabilization With Closed-Loop Robust DOA Enlargement Based on Interval Analysis
Heterogeneous and Homogeneous Attractors in 2D Sine-Based Hyperchaotic Map and Its High-Precision FPGA Implementation
DQ-STP: An Efficient Sparse On-Device Training Processor Based on Low-Rank Decomposition and Quantization for DNN
AxOCS: Scaling FPGA-Based Approximate Operators Using Configuration Supersampling
A New Macromodeling Method Based on Deep Gated Recurrent Unit Regularized With Gaussian Dropout for Nonlinear Circuits
Analysis and Design of a Novel Gain-Boosting Technique Based on Lossy Series Embedding Network for Near-f max Embedded Amplifier
Hybrid Pass Transistor Logic With Ambipolar Transistors
Modeling the Effect of Air-Gap Length and Number of Turns on Ferrite-Core Inductors Working up to Magnetic Saturation in a Buck Converter
Optimized Synthesis Method for Ultra-Low Power Multi-Input Material Implication Logic With Emerging Non-Volatile Memories
Macromodeling of Nonlinear High-Speed Circuits Using Novel Hybrid Bidirectional High-Order Deep Recurrent Neural Network
Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks
Realizable Reduction of Multi-Port RCL Networks by Block Elimination
A Single-Stage Four-Phase Hybrid Boost Converter With 11-to-20 VCRs for LiDAR Driver Applications
Optimizing FPGA-Based DNN Accelerator With Shared Exponential Floating-Point Format
A 130nm CMOS Programmable Analog Standard Cell Library
Low Complexity Distributed Synchronization of Uncertain Nonlinear Multi-Agent Systems With Global Funnel Performance
SuperHCA: An Efficient Deep-Learning Edge Super-Resolution Accelerator With Sparsity-Aware Heterogeneous Core Architecture
In Situ Wide-Range Permittivity Measurement: Compact, Cost-Effective, and Highly Sensitive Sensor Using Reconfigurable Phase Shifter
Lightweight Hardware Accelerator for Post-Quantum Digital Signature CRYSTALS-Dilithium
An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage
A 9.84-μW 148.9-dB Total DR Light-to-Digital Converter With Current-Integration SAR Quantizer for Multi-Wavelength PPG Applications
A Comprehensive Study on the Design Methodology of Level Shifter Circuits
Hybrid Force/Position Control of Multi-Mobile Manipulators for Cooperative Operation Without Force Measurements
Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme
Novel Sensorless Current Multimode Control for PSR Double-Clamp ZVS (DCZVS) Flyback Converter in DCM and CrCM
A Nonlinear Stream Cipher for Encryption of Test Patterns in Streaming Scan Networks
Phase Modulated Bistatic Radar With an Analog Correlator: A Systematic Study
High-Order HTS Dual-Band Differential Bandpass Filter Using Stub-Loaded Twin-Ring Resonator With Fully Controllable Passbands
ANSA: Adaptive Near-Sensor Architecture for Dynamic DNN Processing in Compact Form Factors
Fast FPGA Prototyping to Explore and Compare New SPWM Strategies
A Low-Power Indirect Time-of-Flight CMOS Image Sensor With Fixed Depth Noise Compensation and Dual-Mode Imaging for Depth Dynamic Range Enhancement
Fixed-Time Dynamic Surface Disturbance Rejection Control for Pneumatic Soft Bending Actuators