yusuke1997/dblp-id-title huggingface dataset:
Guest Editorial: Special Section on Embracing Artificial Intelligence for Network and Service Management
Network Volume Anomaly Detection and Identification in Large-Scale Networks Based on Online Time-Structured Traffic Tensor Tracking
CNAME Cloaking-Based Tracking on the Web: Characterization, Detection, and Protection
Stability and Accuracy-Aware Learning for Task Offloading in UAV-MEC-Assisted Smart Farms
Efficient Cross-Shard Blockchain Atomic Submission Scheme Based on Pledge Transactions
Single and Multi-Domain Adaptive Allocation Algorithms for VNF Forwarding Graph Embedding
A Heuristically Assisted Deep Reinforcement Learning Approach for Network Slice Placement
Traffic Trend Estimation for Profit Oriented Capacity Adaptation in Service Overlay Networks
Sustainable Energy-Efficient Multi-Objective Task Processing Based on Edge Computing
A Novel Approach for Profile Optimization in DOCSIS 3.1 Networks Exploiting Traffic Information
Efficiency of BIER Multicast in Large Networks
z-TORCH: An Automated NFV Orchestration and Monitoring Solution
Topology-Aware Prediction of Virtual Network Function Resource Requirements
Network Intrusion Detection and Comparative Analysis Using Ensemble Machine Learning and Feature Selection
Spillover Today? Predicting Traffic Overflows on Private Peering of Major Content Providers
AVCast: New Approaches for Implementing Generic Availability-Dependent Reliability Predicates for Multicast Receivers
CARRAS: Combined AOA and RBFNN for Resource Allocation in Single Site 5G Network
Malicious DNS Tunnel Tool Recognition Using Persistent DoH Traffic Analysis
Contrastive Learning Enhanced Intrusion Detection
DLLF-2EN: Energy-Efficient Next Generation Mobile Network With Deep Learning-Based Load Forecasting
An Incrementally-Deployable P4-Enabled Architecture for Network-Wide Heavy-Hitter Detection
A Learned Bloom Filter-Assisted Scheme for Packet Classification in Software-Defined Networking
Unknown Attack Traffic Classification in SCADA Network Using Heuristic Clustering Technique
Robust Anomaly-Based Insider Threat Detection Using Graph Neural Network
Improving Quality-of-Service in Cluster-Based UAV-Assisted Edge Networks
Energy-Efficient and Privacy-Preserved Incentive Mechanism for Mobile Edge Computing-Assisted Federated Learning in Healthcare System
Few-Shot Learning and Self-Training for eNodeB Log Analysis for Service-Level Assurance in LTE Networks
STAD: Spatio-Temporal Anomaly Detection Mechanism for Mobile Network Management
Consistent Network Management for Software-Defined Networking Based Multicast
Orchestrating Virtualized Network Functions
Intelligent EV Charging for Urban Prosumer Communities: An Auction and Multi-Agent Deep Reinforcement Learning Approach
Distributed Model Training Task Migration for Hotspot Management in Intelligent Computing Center Interconnection With Tidal Characteristics
A Graph Partitioning Game Theoretical Approach for the VNF Service Chaining Problem
Federated Learning Approach Decouples Clients From Training a Local Model and With the Communication With the Server
A Novel Framework of Federated and Distributed Machine Learning for Resource Provisioning in 5G and Beyond Using Mobile-Edge SCBS
DQN Dynamic Pricing and Revenue Driven Service Federation Strategy
Detection of Malicious Domains With Concept Drift Using Ensemble Learning
A Novel Access and Handover Authentication Scheme in UAV-Aided Satellite-Terrestrial Integration Networks Enabling 5G
Traffic Engineering for Software-Defined LEO Constellations
Managing Data Retention Policies at Scale
Communication-Efficient Personalized Federated Meta-Learning in Edge Networks
Deep Reinforcement Learning-Based Dual-Timescale Service Caching and Computation Offloading for Multi-UAV Assisted MEC Systems
DDoS Detection System: Using a Set of Classification Algorithms Controlled by Fuzzy Logic System in Apache Spark
FTMaster: A Detection and Mitigation System of Low-Rate Flow Table Overflow Attacks via SDN
Three-Dimensional Tradeoffs for Consensus Algorithms: A Review
Unavailability-Aware Shared Virtual Backup Allocation for Middleboxes: A Queueing Approach
Dynamic Joint Functional Split and Resource Allocation Optimization in Elastic Optical Fronthaul
Grouper: Accelerating Hyperparameter Searching in Deep Learning Clusters With Network Scheduling
GASTO: A Fast Adaptive Graph Learning Framework for Edge Computing Empowered Task Offloading
Energy and Interference-Aware Scheduling for Minimizing the Age of Aggregate Information in Multi-Hop IoT Networks
Traffic Management and Net Neutrality in Wireless Networks
Urban Mobile Data Prediction With Geospatial Clustering and Dual Residual Learning
FortunChain: EC-VRF-Based Scalable Blockchain System for Realizing State Sharding
MEC-Based Super-Resolution Enhanced Adaptive Video Streaming Optimization for Mobile Networks With Satellite Backhaul
Scalable and Energy-Efficient Service Orchestration in the Edge-Cloud Continuum With Multi-Objective Reinforcement Learning
Attention-Based Deep Reinforcement Learning for Edge User Allocation
Proactive and AoI-Aware Failure Recovery for Stateful NFV-Enabled Zero-Touch 6G Networks: Model-Free DRL Approach
Design, Modeling, and Implementation of Robust Migration of Stateful Edge Microservices
A Comprehensive Evaluation of Networked Music Performance Using LEO Satellite Internet: The Starlink Use Case
Survivability and Disaster Recovery Modeling of Cellular Networks Using Matrix Exponential Distributions
MPCN-RP: A Routing Protocol for Blockchain-Based Multi-Charge Payment Channel Networks
Efficient Batch Authentication Scheme Based on Edge Computing in IIoT
Flexible Traffic Splitting in OpenFlow Networks
A Novel Scheme to Improve the Scalability of Bitcoin Combining IPFS With Block Compression
A Security Management Architecture for Supporting Routing Services on WANETs
A Configuration Complexity Model and Its Application to a Change Management System
Multi-Granularity Abnormal Traffic Detection Based on Multi-Instance Learning
2020 Reviewers for IEEE Transactions on Network and Service Management (TNSM)
Re-Scheduling IoT Services in Edge Networks
Heterogeneous Radios Meet Intelligence: DRL-Based Delay Minimization in Multi-Hop Wireless Networks
Cybersecurity Threat Assessment Integrating Qualitative Differential and Evolutionary Games
MLSNet: A Policy Complying Multilevel Security Framework for Software Defined Networking
RASCAR: Recovery-Aware Switch-Controller Assignment and Routing in SDN
Machine Learning for Failure Management in Microwave Networks: A Data-Centric Approach
How Polynomial Regression Improves DeNATing
A Biology-Based Algorithm to Minimal Exposure Problem of Wireless Sensor Networks
Using Session Modeling to Estimate HTTP-Based Video QoE Metrics From Encrypted Network Traffic
SNS: Smart Node Selection for Scalable Traffic Engineering in Segment Routing Networks
A UAV-Assisted Traceable and Hierarchical Trust Management in VANET for Disaster Data Collection
Service Chain Provisioning With Sub-Chain-Enabled Coordinated Protection to Satisfy Availability Requirements
Adaptive Placement and Routing for Service Function Chains With Service Deadlines
Dynamic QoS-Aware Traffic Planning for Time-Triggered Flows in the Real-Time Data Plane
Causal Genetic Network Anomaly Detection Method for Imbalanced Data and Information Redundancy
A Fairness-Based Adaptive Explicit Congestion Control Protocol in Microburst Traffic Scenarios
A New Approach to Dimensionality Reduction for Anomaly Detection in Data Traffic
Tamper-Proof Network Traffic Measurements on a NIC for Intrusion Detection
Routing Algorithms for Network Function Virtualization Enabled Multicast Topology on SDN
End-Edge-Cloud Heterogeneous Resources Scheduling Method Based on RNN and Particle Swarm Optimization
A Path Generation Approach to Embedding of Virtual Networks
A Split Architecture Approach to Terabyte-Scale Caching in a Protocol-Oblivious Forwarding Switch
DRL-Based Service Function Chain Edge-to-Edge and Edge-to-Cloud Joint Offloading in Edge-Cloud Network
Yuz: Improving Performance of Cluster-Based Services by Near-L4 Session-Persistent Load Balancing
ARENA: A Data-Driven Radio Access Networks Analysis of Football Events
Design and evaluation of a new multi-path incremental routing algorithm on software routers
Inter-Controller Traffic to Support Consistency in ONOS Clusters
UaaS-SFL: Unlearning as a Service for Safeguarding Federated Learning
Toward Heterogeneous Environment: Lyapunov-Orientated ImpHetero Reinforcement Learning for Task Offloading
Recommendation Model Based on Dynamic Interest Group Identification and Data Compensation
Large-Scale Dynamic Controller Placement
CRP: A Cluster-Based Routing Protocol for Lightweight Nodes in Payment Channel Networks
Multimodal Multitask Control Plane Verification Framework
Machine Learning-Based Radio Coverage Prediction in Urban Environments
Counteracting New Attacks in CPS: A Few-Shot Class-Incremental Adaptation Strategy for Intrusion Detection System
FedPot: A Quality-Aware Collaborative and Incentivized Honeypot-Based Detector for Smart Grid Networks
Metis: Selecting Diverse Atlas Vantage Points
A Novel Lightweight Dynamic Trust Evaluation Model for Edge Computing
Service Function Chain Embedding Meets Machine Learning: Deep Reinforcement Learning Approach
Efficient and Secure Multi-User Multi-Task Computation Offloading for Mobile-Edge Computing in Mobile IoT Networks
Converging Game Theory and Reinforcement Learning For Industrial Internet of Things
Noisy Neighbour Impact Assessment and Prevention in Virtualized Mobile Networks
Blockchain-Aided and Privacy-Preserving Data Governance in Multi-Stakeholder Applications
2021 Reviewers for IEEE Transactions on Network and Service Management (TNSM)
Atomicity and Non-Anonymity in Population-Like Games for the Energy Efficiency of Hybrid-Power HetNets
A Virtualization Layer Approach to Survivability
Intelligent Beam Blockage Prediction for Seamless Connectivity in Vision-Aided Next-Generation Wireless Networks
Measuring Business Process Consistency Across Different Abstraction Levels
In-Network Volumetric DDoS Victim Identification Using Programmable Commodity Switches
Group Mobility Detection and User Connectivity Models for Evaluation of Mobile Network Functions
On the Implications of Routing Models on Network Optimization
AI Anomaly Detection for Cloudified Mobile Core Architectures
Forecasting Quality of Service for Next-Generation Data-Driven WiFi6 Campus Networks
Cell ID Management in Multi-Vendor and Multi-RAT Heterogeneous Networks
OFLoad: An OpenFlow-Based Dynamic Load Balancing Strategy for Datacenter Networks
Foureye: Defensive Deception Against Advanced Persistent Threats via Hypergame Theory
Sustainable Task Offloading in Secure UAV-Assisted Smart Farm Networks: A Multi-Agent DRL With Action Mask Approach
Efficient Coupling Diffusion of Positive and Negative Information in Online Social Networks
MOE/RF: A Novel Phishing Detection Model Based on Revised Multiobjective Evolution Optimization Algorithm and Random Forest
Automated Concept Drift Handling for Fault Prediction in Edge Clouds Using Reinforcement Learning
SFCache: Hybrid NF Synthesization in Runtime With Rule-Caching in Programmable Switches
Reliable BIER With Peer Caching
Network Abnormal Traffic Detection Model Based on Semi-Supervised Deep Reinforcement Learning
Mitigating Mimicry Attacks Against the Session Initiation Protocol
HiAuth: Hidden Authentication for Protecting Software Defined Networks
Impact of Worst-Case Excitation for DDR interface Signal and Power Integrity Co-Simulation
Efficient Design of Rounding-Based Approximate Multiplier Using Modified Karatsuba Algorithm
2019 JETTA-TTTC Best Paper Award
Aliasing properties of circular MISRs
Bilateral Testing of Nano-scale Fault-Tolerant Circuits
Tolerating Soft Errors with Horizontal-Vertical-Diagonal-N-Queen (HVDNQ) Parity
Utilizing On-chip Resources for Testing Embedded Mixed-signal Cores
A Low Bit Instability CMOS PUF Based on Current Mirrors and WTA Cells
Evaluating Different Strategies for Testing Software Product Lines
A methodology for testability enhancement at layout level
Efficient Design of Rounding Based Static Segment Imprecise Multipliers for Error Tolerance Application
Towards Fault-Tolerant RF Front Ends
Multi-bit Sigma-Delta TDC Architecture with Improved Linearity
Fault Analysis and Evaluation of a True Random Number Generator Embedded in a Processor
A characterization of robust test-pairs for stuck-open faults
Test Data Compression for System-on-a-Chip using Count Compatible Pattern Run-Length Coding
Characterization of a Passive Telemetric System for ISM Band Pressure Sensors
Computing the Detection Probability for Small Delay Defects of Nanometer ICs
Error Diagnosis of Sequential Circuits Using Region-Based Model
Phase Shifter Merging
Avoiding linear dependencies in LFSR test pattern generators
Low-Cost Testing of 5 GHz Low Noise Amplifiers Using New RF BIST Circuit
A Layout-Aware Pattern Grading Procedure for Critical Paths Considering Power Supply Noise and Crosstalk
Aliasing probability transients
Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI's Using Universal Rad-SPICE MOSFET Model
Proportional BIC sensor for current testing
A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis
A Methodology for Identification of Internal Nets for Improving Fault Coverage in Analog and Mixed Signal Circuits
Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults
A System Level Boundary Scan Controller Board for VME Applications
Test Technology Technical Council Newsletter
Oscillation Test Scheme of SC Biquad Filters Based on Internal Reconfiguration
Characterization Method for Integrated Magnetic Devices at Lower Frequencies (up to 110 MHz)
A SLvT Adaptive Test Method for Integrated Circuit Test Parameter Sets without Yield Loss
An End-to-End Mutually Exclusive Autoencoder Method for Analog Circuit Fault Diagnosis
On Boosting the Accuracy of Non-RF to RF Correlation-Based Specification Test Compaction
Robust Coupling Delay Test Sets
A Behavior Model for Next Generation Test Systems
A Distortion Shaping Technique to Equalize Intermodulation Distortion Performance of Interpolating Arbitrary Waveform Generators in Automated Test Equipment
Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints
Mixed current/voltage observation towards effective testing of analog and mixed-signal circuits
CEP: Correlated Error Propagation for Hierarchical Soft Error Analysis
A Test Methodology for High Performance MCMs
A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits with Dynamic and Static C-elements
A New Design-for-Testability Method Based on Thru-Testability
Hardware Generation of Random Single Input Change Test Sequences
Testability-based partial scan analysis
Design for Test of Crystal Oscillators: A Case Study
Time-Constraint-Aware Optimization of Assertions in Embedded Software
Partial Scan Testing on the Register-Transfer Level
An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation
Test Technology Newsletter
High Performance Significance Approximation Error Tolerance Adder for Image Processing Applications
Editorial - Special issue on partial scan design
Fault Modeling and Fault Simulation in Mixed Micro-Fluidic Microelectronic Systems
Functional Constraints vs. Test Compression in Scan-Based Delay Testing
New Calibration Technique of Contact-less Resonant Biosensor
Mitigating Soft Errors in SRAM Address Decoders Using Built-in Current Sensors
Testability Trade-Offs for BIST Data Paths
On Random Pattern Testability of Cryptographic VLSI Cores
Thermal Testing of Analogue Integrated Circuits: A Case Study
2016-2017 JETTA Reviewers
A BIST Scheme for SNDR Testing of SigmaDelta ADCs Using Sine-Wave Fitting
Efficient Fault Detection by Test Case Prioritization via Test Case Selection
Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection
Test program synthesis for modules and chips having boundary scan
PCB Defect Recognition by Image Analysis using Deep Convolutional Neural Network
Logic Locking: A Survey of Proposed Methods and Evaluation Metrics
Offline Error Detection in MEDA-Based Digital Microfluidic Biochips Using Oscillation-Based Testing Methodology
Scan Test Response Compaction Combined with Diagnosis Capabilities
Topological Considerations for the Diagnosability Conditions of Analogue Circuits Using a Pair of Conjugate Trees
Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods
A Fully-Settled Linear Behavior Plus Noise Model for Evaluating the Digital Stimuli of the Design-for-Digital-Testability Sigma-Delta Modulators
Detecting Hardware Trojans using On-chip Sensors in an ASIC Design
A Determinate Radiation Hardened Technique for Safety-Critical CMOS Designs
A Semantics-based Translation Method for Automated Verification of SystemC TLM Designs
On minimizing aliasing in scan-based compaction
Simulation Techniques for the Manufacturing Test of MCMs
A HW/SW Cross-Layer Approach for Determining Application-Redundant Hardware Faults in Embedded Systems
A Formalization of the IEEE 1149.1-1990 Diagnostic Methodology as Applied to Multichip Modules
Investigation of the Impact of BTI Aging Phenomenon on Analog Amplifiers
Qualifying Serial Interface Jitter Rapidly and Cost-effectively
A Biased Random Instruction Generation Environment for Architectural Verification of Pipelined Processors
Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy
On Selecting Testable Paths in Scan Designs
A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs
Single Event Resilient Dynamic Logic Designs
A Module for BiST of CMOS RF Receivers
Defining and Providing Coverage for Assertion-Based Dynamic Verification
Integrated Design and Test of Mixed-Signal Circuits
Cost/Quality Trade-off in Synthesis for BIST
A probability density estimation algorithm on multiwavelet for the high-resolution ADC
Real-time Embedded System Fault Injector Framework for Micro-architectural State Based Reliability Assessment
Search strategy switching: A cost model and an analysis of backtracking
Analysis of Hamming count compaction scheme
Speed-Up in Test Methods Using Probabilistic Merit Indicators
Designing "Dual Personality" IEEE 1149.1 Compliant Multi-Chip Modules
State and Fault Information for Compaction-Based Test Generation
Testing for Function and Performance: Towards an Integrated Processor Validation Methodology
Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects
A methodology for the design of SFS/SCD circuits for a class of unordered codes
Design of INV/BUFF Logic Locking For Enhancing the Hardware Security
Connectivity Test for System in Package Interconnects
A First Step for an INL Spectral-Based BIST: The Memory Optimization
Contactless Testing of Circuit Interconnects
Defect Simulation Methodology for i DDT Testing
Balance testing and balance-testable design of logic circuits
Digital-Compatible Testing Scheme for Operational Amplifier
Sensitivity analysis in economics based test strategy planning
Optimization of Test Power and Data Volume in BIST Scheme Based on Scan Slice Overlapping
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction
Component Value Calculations and Characterizations for Measurements in the IEEE 1149.4 Environment
An implicitly testable boundary scan TAP controller
A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique
A Design of Linearity Built-in Self-Test for Current-Steering DAC
Hardware Trojan Detection Method Based on Dual Discriminator Assisted Conditional Generation Adversarial Network
Testing of Current Carrying Capacity of Conducting Tracks in High Power Flexible Printed Circuit Boards
Fault Diagnosis Method of Low Noise Amplifier Based on Support Vector Machine and Hidden Markov Model
Exhaustive and Near-Exhaustive Memory Testing Techniques and their BIST Implementations
Timing Jitter Measurement of Intrinsic Random Jitter and Sinusoidal Jitter Using Frequency Division
Effective Timing Error Tolerance in Flip-Flop Based Core Designs
Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead
Testing VLSI regular arrays
Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs
A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores
An Efficient VLSI Test Data Compression Scheme for Circular Scan Architecture Based on Modified Ant Colony Meta-heuristic
A Novel Defect Model Induced by a Single Dust Particle Contamination in the FinFET Gate Fingers
A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding
Fundamentals of MCM Testing and Design-for-Testability
ADC Spectral Testing with Signal Amplitude Drift and Simultaneous Non-coherent Sampling
An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization
An IEEE 1149.1 Compliant Test Control Architecture
Modelling, Simulation, and FPGA Implementation of an Augmented Memory Built-in Self-Test Based Design for Bit-Oriented Memory
On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power
A New BIST-based Test Approach with the Fault Location Capability for Communication Channels in Network-on-Chip
Fault-Tolerant Memory Architecture Against Radiation-Dependent Errors: A Mixed Error Control Approach
Catastrophic Short and Open Fault Detection in Bipolar CML Circuits: A Case Study
Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits
An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging Effects
Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects
Analog Circuit Fault Detection Using Location of Poles
Survey of Robustness Enhancement Techniques for Wireless Systems-on-a-Chip and Study of Temperature as Observable for Process Variations
Reliability Model for Multiple-Error Protected Static Memories
Unified built-in self-test for fully differential analog circuits
A Power Efficient BIST TPG Method on Don't Care Bit Based 2-D Adjusting and Hamming Distance Based 2-D Reordering
Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM
Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells
Off-Chip Diagnosis of Aperture Jitter in Full-Flash Analog-to-Digital Converters
Yield enhancement and manufacturing throughput of redundant memories by repairability/unrepairability detection
A language for describing boundary scan devices
A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures
Test of Mechanical Failure for Via Holes and Solder Joints of Complex Interconnect Structure
BISTing Datapaths under Heterogeneous Test Schemes
A Classification Approach for an Accurate Analog/RF BIST Evaluation Based on the Process Parameters
FPGA-based Novel Adaptive Scheme Using PN Sequences for Self-Calibration and Self-Testing of MEMS-based Inertial Sensors
Checkpoints in irredundant two-level combinational circuits
An Optimized NS2 Module for UHF Passive RFID Systems
Self-timed is self-checking
Structural Test and Diagnosis for Graceful Degradation of NoC Switches
Benefits of Partitioning in a Projection-based and Realizable Model-order Reduction Flow
Methodology to Replace Sensitivity BER and Transmit Power Production Tests in Bluetooth Devices with BiSTs
Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults
High Speed Energy Efficient Static Segment Adder for Approximate Computing Applications
Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability
Guest Editorial - Special Issue on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN)
On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check
On Reducing Test Data Volume for Circular Scan Architecture Using Modified Shuffled Shepherd Optimization