yusuke1997/dblp-id-title huggingface dataset:
A Secure Fault-Tolerant Conference-Key Agreement Protocol
On the Efficiency of Voltage Overscaling under Temperature and Aging Effects
Period Selection for Minimal Hyperperiod in Periodic Task Systems
PrivAim: A Dual-Privacy Preserving and Quality-Aware Incentive Mechanism for Federated Learning
On Memory Contention Problems in Vector Multiprocessors
The Twisted N-Cube with Application to Multiprocessing
Characterization of the Magnetic Second-Harmonic Analog Memory
Parallel Processing in a Restructurable Computer System
The Effects of Emerging Technology and Emulation Requirements on Microprogramming
Modified Pseudorandom Number Generators
A Parapropagation Pattern Classifier
A Diode Multiplexer for Analog Voltages
Efficient All-to-All Broadcast in Gaussian On-Chip Networks
The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations
Sequential Machines Having Quasi-Stable States
On the Design of Approximate Restoring Dividers for Error-Tolerant Applications
Control Performance Optimization for Application Integration on Automotive Architectures
On Using Lossy Compression for Repeatable Experiments during Silicon Debug
A Special Purpose Computer for Solution of Partial Differential Equations and Other Iterative Algorithms
Access Characteristic Guided Read and Write Regulation on Flash Based Storage Systems
RACCOOM: A Rate-Based Congestion Control Approach for Multicast
On Optimal Ierative Schemes for High-Speed Division
Estimation, Prediction, and Smoothing in Discrete Parameter Systems
Tensor Product DFT Codes vs Standard DFT Codes
Performance Analysis of Multilevel Bus Networks for Hierarchical Multiprocessors
Signed Binary Addition Circuitry with Inherent Even Parity Outputs
Express Cubes: Improving the Performance of k-Ary n-Cube Interconnection Networks
Finding Interferences Between Rectangular Paths
Logic Testing of Bridging Faults in CMOS Integrated Circuits
Comment on "Canonical Programming of Nonlinear and Time-Varying Differential Equations"
An Optimal Systolic Array for the Algebraic Path Problem
Fault Tolerance in Binary Tree Architectures
Comparative Analysis of Different Implementations of Multiple-Input Signature Analyzers
Implementing Precise Interrupts in Pipelined Processors
Quasi-Universal Switch Matrices for FPD Design
Design, Implementation and Verification of Cloud Architecture for Monitoring a Virtual Machine's Security Health
Xen and Co.: Communication-Aware CPU Management in Consolidated Xen-Based Hosting Platforms
Two Statistical Feature Evaluation Techniques Applied to Speaker Identification
Resource Conservation in a Mobile Transaction System
GRIP: A Graph Neural Network Accelerator Architecture
A Theorem on the State Reduction of Synthesized Stochastic Machines
A Generalized Record Organization
Bounded-Latency Content Distribution: Feasibility and Evaluation
A Priori Worst Case Error Bounds for Floating-Point Computations
A Generalized Hybrid Simulation for an Aerospace Vehicle
Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications
Minimizing Area Cost of On-Chip Cache Memories by Caching Address Tags
R70-4 Analysis of Algorithms for the Zero-One Programming Problem
Cellular Logic-in-Memory Arrays
Design of a High-Speed Square Generator
Minimum Two-Level Threslold Gate Realizations
Comments on "Multiple-Radix Gray Codes in Lee Metric"
Function Approximation by Walsh Series
New Metrics for the Reliability of Approximate and Probabilistic Adders
R68-40 Sequential Machines and Automata Theory
Principal Component Analysis Based Filtering for Scalable, High Precision k-NN Search
A Systematic (12, 8) Code for Correcting Single Errors and Detecting Adjacent Errors
Fuzzy Logic and its Application to Switching Systems
AutoDiagn: An Automated Real-Time Diagnosis Framework for Big Data Systems
A Versatile Family of Consensus Protocols Based on Chandra-Toueg's Unreliable Failure Detectors
Adder With Distributed Control
A Variation on the Hypercube with Lower Diameter
Edge Disjoint Hamiltonian Cycles in Gaussian Networks
R68-50 Multiprogramming System Performance Measurement and Analysis
Fault Tolerance in Linear Systolic Arrays Using Time Redundancy
A Performance Evaluation of RAID Architectures
A Fast Poisson Solver Amenable to Parallel Computation
On the Diagnosability of Multicomputer Systems with Homogeneous and Incomplete Tests
On Computation of the Hadamard Transform and the R Transform in Ordered Form
DC m Codes for Constructing t -EC/AUED Codes
Provably Conservative Approximations to Complex Reliability Models
On Mod-2 Sums of Products
R70-29 Uniform Synthesis of Sequential Circuits
By-Passing Infected Areas in Wireless Sensor Networks Using BPR
On-Line Diagnosis of Unrestricted Faults
Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemtive Scheduling
Energy-Efficient Data Dissemination Schemes for Nearest Neighbor Query Processing
Comments on "A Systematic (16, 8) Code for Correcting Double Errors and Detecting Triple-Adjacent Errors"
B73-9 Introduction to Computer Organization and Data Structures
A Light-Weight White-Box Encryption Scheme for Securing Distributed Embedded Devices
Design and Evaluation of Hardware Strategies for Reconfiguring Hypercubes and Meshes Under Faults
A Measurement Center for the NBS Local Area Computer Network
A Reconfiguration Scheme for Yield Enhancement of Large Area Binary Tree Architectures
High-Speed Parallel-Prefix Modulo 2n-1 Adders
A Fortran Extension for Data Display
Readily Programmable Procedures for the Analysis of Nonlinear Feedback Shift Registers
Derivation of Minimal Complete Sets of Test-Input Sequences Using Boolean Differences
A Parallelization Domain Oriented Multilevel Graph Partitioner
The Timely Computing Base Model and Architecture
Achieving Load Balance for Parallel Data Access on Distributed File Systems
Random-Pulse Machines
Unit-Distance Binary-Decimal Code Translators
Algorithm and Architecture for Logarithm, Exponential, and Powering Computation
$\mathsf{Aurora}$Aurora: Leaderless State-Machine Replication With High Throughput
The Effect of Code Expanding Optimizations on Instruction Cache Design
SD3: An Efficient Dynamic Data-Dependence Profiling Mechanism
The Use of Walsh Functions in the Wiener Analysis of Nonlinear Systems
R70-5 The Effect of IC's on the Design of Analog Computers
Iterative Solution of Large, Sparse Linear Systems on a Static Data Flow Architecture: Performance Studies
Organization for Execution of User Microprograms from Main Memory: Synthesis and Analysis
On the State Assignment Problem for Sequential Machines II
Periodic Representations and T-Partitionable Equivalents of Sequential Machines
Intra- and Inter-Layer Scheduling Exploration and Optimization for ReRAM-Based DNN Accelerators
A Design for a List Merging Network
Adaptation of the Mactaggart and Jack Complex Multiplication Algorithm for Floating-Point Operators
Ameliorate Performance of Memristor-Based ANNs in Edge Computing
A Lightweight and Efficient GPU for NDP Utilizing Data Access Pattern of Image Processing
Clustering Driven Iterated Hybrid Search for Vertex Bisection Minimization
Synthesis Algorithm for 2-level MOS Networks
R68-16 A Mathematical Model for the Investigation of Three-Dimensional Fields with Asymmetric Boundaries
The "Braid" Transformer Memory
Using Digital Computers in the Design and Maintenance of New Computers
Minimizability of Random Boolean Functions
On the Decomposition of Periodic Representations of Sequential Machines
Systems of Asynchronously Operating Modules
Borrow: A Fault-Tolerance Scheme for Wavefront Array Processors
Pattern Recognition by Convolution Polynomial
A Variable-Length Code for an Incremental Display System
Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams
WEC: Improving Durability of SSD Cache Drives by Caching Write-Efficient Data
Distributed Diagnosis Algorithms for Regular Interconnected Structures
The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques
Efficient Software Implementation of the SIKE Protocol Using a New Data Representation
Universal Delay-Insensitive Circuits with Bidirectional and Buffering Lines
Developing Large Binary to BCD Conversion Structures
The Design of a Highly Parallel Computer Organization
DNSGreen: A Comprehensive Defense System Against Bounce-Style DNS DDoS Attacks With P4
A Ring Model for the Study of Multiplication for Complement Codes
B71-3 Microprogramming: Principles and Practices
Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator
Computer Design of Multiple-Output Logical Networks
Efficient Internode Commucations in Reconfigurable Binary Trees
A Fast Digital Computer Method for Recursive Estimation of the Mean
BLADE: An in-Cache Computing Architecture for Edge Devices
Symbolic Treatment of Certain Selector Functions
Efficient Mapping of ANNs on Hypercube Massively Parallel Machines
Broadcasting on Incomplete Hypercubes
High-Speed Hardware Architectures and FPGA Benchmarking of CRYSTALS-Kyber, NTRU, and Saber
Logic Design of Programmable Logic Arrays
Uniformity and Independence of H3 Hash Functions for Bloom Filters
The Movement and Permutation of Columns in Magnetic Bubble Lattice Files
A Survey of the Characteristics of Currently Used Bistable Multivibrators
Enabling Consistent Sensing Data Sharing Among IoT Edge Servers via Lightweight Consensus
Content Adressable Read/Write Memories for Image Analysis
Load-Sharing Core Switches Based on Block Designs
Incorporating Data Flow Ideas into von Neumann Processors for Parallel Execution
Indirect Star-Type Networks for Large Multiprocessor Systems
Slicing Distributed Systems
Game-Based Adaptive FLOPs and Partition Point Decision Mechanism With Latency and Energy-Efficient Tradeoff for Edge Intelligence
Strong Diagnosability and Conditional Diagnosability of Multiprocessor Systems and Folded Hypercubes
System Fault Diagnosis: Closure and Diagnosability with Repair
On-Chip Fault Monitoring Using Self-Reconfiguring IEEE 1687 Networks
Integrated Analysis of Power and Performance for Pipelined Microprocessors
Sift-Out Modular Redundancy
Efficient Multiplication Beyond Optimal Normal Bases
Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies
A Compact High-Speed Parallel Multiplication Scheme
A Parallel Algorithm for Solving Sparse Triangular Systems
Malware-on-the-Brain: Illuminating Malware Byte Codes With Images for Malware Classification
In-the-Field Mitigation of Process Variability for Improved FPGA Performance
Abstract Specification of Synchronous Data Types for VLSI and Proving the Correctness of Systolic Network Implementations
Soft Error Tolerant Count Min Sketches
Mining Associated Patterns from Wireless Sensor Networks
The Effect of Program Behavior on Fault Observability
On an Ordering of Walsh Functions
Target Association Rules: A New Behavioral Patterns for Point of Coverage Wireless Sensor Networks
Memory Package Error Detection and Correction
A Proposal for Input of Hand-Drawn Information to a Digital System
TLB Index-Based Tagging for Reducing Data Cache and TLB Energy Consumption
Analog Computation of Fourier Series and Integrals
A Fault Diagnosis Algorithm for Asymmetric Modular Architectures
Statistical Resistance to Detection
CID: Co-Architecting Instruction Cache and Decompression System for Embedded Systems
B74-11 Abstract Automata
Decomposition of Complex Multipliers Using Polynomial Encoding
Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits
Distributed Fault Diagnosis in Multistage Network-Based Multiprocessors
New Classes for Parallel Complexity: A Study of Unification and Other Complete Problems for P
On Combinational Networks with Restricted Fan-Out
Improving Blockchains With Client-Assistance
SparCE: Sparsity Aware General-Purpose Core Extensions to Accelerate Deep Neural Networks
General Reuse-Centric CNN Accelerator
Reconfiguration for Repair in a Class of Universal Logic Modules
Clustering Using a Similarity Measure Based on Shared Near Neighbors
Parallelism and Representation Problems in Distributed Systems
Low Cost NBTI Degradation Detection and Masking Approaches
Systematic Unidirectional Burst Detecting Codes
Hardware Algorithms for Determining Similarity Between Two Strings
A Fundamental Error Theory for Analog Computers
Boolean Minimization of Projected Sums of Products via Boolean Relations
Uniqueness of Weighted Code Representations
An Equational Axiomatization for the Disjoint System of Post Algebras
Holistic and Opportunistic Scheduling of Background I/Os in Flash-Based SSDs
Observing the Invisible: Live Cache Inspection for High-Performance Embedded Systems
High-Performance and Fault-Tolerant 3D NoC-Bus Hybrid Architecture Using ARB-NET-Based Adaptive Monitoring Platform
An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging
Test Generation with Dynamic Probe Points in High Observability Testing Environment
A Simple Mechanism for Detecting Ineffectual Instructions in Slipstream Processors
An Optimal Fault-Tolerant Routing Algorithm for Double-Loop Networks
The PMC System Level Fault Model: Cardinality Properties of the Implied Faulty Sets
Fault Detection of Binary Sequential Machines Using R-Valued Test Machines
A Network Flow Approach to the Reconfiguration of VLSI Arrays
Secure Auditing and Deduplicating Data in Cloud
Hyte: A Hotness-Aware Hybrid DRAM-PM Native Table Storage Engine
Kronecker Product Factorization of the FFT Matrix
Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach
Computing Packet Loss Probabilities in Multiplexer Models Using Rational Approximation
A Projection Pursuit Algorithm for Exploratory Data Analysis
Bi-Objective Optimization of Data-Parallel Applications on Homogeneous Multicore Clusters for Performance and Energy
Stereo: Assignment and Scheduling in MPSoC Under Process Variation by Combining Stochastic and Decomposition Approaches
On the Lower Bound to the VLSI Complexity of Number Conversion from Weighted to Residue Representation
PC-DUOS+: A TCAM Architecture for Packet Classifiers
A Theory of Nonlinear Autonomous Sequential Nets Using z Transforms
New Efficient Structure for a Modular Multiplier for RNS
The Minimization of Assimilations in Binary Carry-Storage Arithmetic Units
An Online Failure Detection Method for Data Buses Using Multithreshold Receiving Logic
Mathematical Analysis of Ferrite Core Memory Arrays
The Decomposition of the States of a Linear Feedback Shift Register Into Cycles of Equal Length
Risk-Resilient Heuristics and Genetic Algorithms for Security-Assured Grid Job Scheduling
B72-26 Computer Organization and the System/370
TOPI - A Special-Purpose Computer for Boolean Analysis and Synthesis
On a Ternary Model of Gate Networks
Capability Based Tagged Architectures
Data Handling for the Geometric Correction of Large Images
Scalable Multi-Match Packet Classification Using TCAM and SRAM
Modified Mesh-Connected Parallel Computers
On Computer Self-Diagnosis Part I-Experimental Study of a Processor
Protein Sequence Pattern Matching: Leveraging Application Specific Hardware Accelerators
Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines"
Probabilistic Value-Deviation-Bounded Source-Dependent Bit-Level Channel Adaptation for Approximate Communication
On Signal Deterioration in Digital Computers
Simplified Decomposition of Boolean Functions
Correction to the Proof of Theorem 2 in "Parallel Signature Analysis Design with Bounds on Aliasing"
STEP: A Time-Efficient Tag Searching Protocol in Large RFID Systems
Towards a Unified Framework for Modeling and Analyzing User-Defined Online Non-Preemptive Scheduling Policies
Implementing Parallel Counters with Four-Valued Threshold Logic
EXR: Greening Data Center Network with Software Defined Exclusive Routing
Composition of Schedulability Analyses for Real-Time Multiprocessor Systems
DCGG: A Dynamically Adaptive and Hardware-Software Coordinated Runtime System for GNN Acceleration on GPUs
A Statistical Failure/Load Relationship: Results of a Multicomputer Study
Transmission Delays in Hardware Clock Synchronization
Optimal Networks of NOR-OR Gates for Functions of Three Variables
Heuristics for Flexible CMP Synthesis
Concurrent Asynchronous Broadcast on the MetaNet
Evaluation of A + B = K Conditions Without Carry Propagation
Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials
An Interacting Stochastic Models Approach for the Performance Evaluation of DSRC Vehicular Safety Communication
Distributed Nodes Organization Algorithm for Channel Access in a Multihop Dynamic Radio Network
Performance Analysis of a Database Filter Search Hardware
Comments on "A Massive Memory Machine"
PowerTracer: Tracing Requests in Multi-Tier Services to Reduce Energy Inefficiency
The Design of Optimal Systolic Arrays
Error-Correcting Tree Automata for Syntactic Pattern Recognition
On the Security of Public-Key Algorithms Based on Chebyshev Polynomials over the Finite Field $Z_N$
Synchronization and Matching in Redundant Systems
Minimal Order Loop-Free Routing Strategy
R68-52 The Structure of the "The"-Multiprogramming System
Comments on "Multiple Fault Detection in Combinational Network"
Using System-Level Models to Evaluate I/O Subsystem Designs
Scattering and Gathering Messages in Networks of Processors
Random CFI (RCFI): Efficient Fine-Grained Control-Flow Integrity Through Random Verification
Parallel Image Processing
Arithmetic Operations for Digital Computers Using a Modified Reflected Binary Code
A Hybrid Multispectral Feature Selection Criterion
Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks
Detection of Global Edges in Textured Images
Workload Adaptive Shared Memory Management for High Performance Network I/O in Virtualized Cloud
CADAC: A Controlled-Precision Decimal Arithmetic Unit
Microarchitectural Online Testing for Failure Detection in Memory Order Buffers
A Programmable Data Concentrator for a Large Computing System
Parallel Cryptographic Arithmetic Using a Redundant Montgomery Representation
Iterative Realization of Multivalued Logic Systems
Continuous Regression Techniques Using Analog Computers
IIPS: Infrastructure IP for Secure SoC Design
Analysis of Cells
Near Optimality of Chebyshev Interpolation for Elementary Function Computations
Characterization of Branch and Data Dependencies in Programs for Evaluating Pipeline Performance
Assumptions in the Threshold Synthesis of Symmetric Switching Functions
A Recurrence Technique for Expanding a Function in Spherical Harmonics
On Some Open Problems in the Theory of Cellular Automata
Fast, Best-Effort Real-Time Scheduling Algorithms
Binary Noise Sources Incorporating Modulo-N Dividers
Performance Analysis of Multistage Interconnection Networks with Hierarchical Requesting Model
Energy-Efficient, Delay-Constrained Edge Computing of a Network of DNNs
Multiple-Valued Counter
A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing
End-to-End Communication Delay Analysis in Industrial Wireless Networks
Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support
An Energy Efficient and Runtime Reconfigurable Accelerator for Robotic Localization
Comments on "An Augmented Iterative Array for High Speed Division"
A Radix-2 Digit-by-Digit Architecture for Cube Root
Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems
Guest Editors' Introduction: Special Section on Science of Design for Safety Critical Systems
Continuous Program Optimization: Design and Evaluation
JBNN: A Hardware Design for Binarized Neural Networks Using Single-Flux-Quantum Circuits
Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes
Time-Triggered Co-Scheduling of Computation and Communication with Jitter Requirements
Estimation of Intermodule Communication (IMC) and Its Applications in Distributed Processing Systems
Longest Fault-Free Paths in Star Graphs with Edge Faults
Majority Gate Networks
WBMatrix: An Optimized Matrix Library for White-Box Block Cipher Implementations
GreedW: A Flexible and Efficient Decentralized Framework for Distributed Machine Learning
Localization Attacks to Internet Threat Monitors: Modeling and Countermeasures
Application of Fuzzy Logic to Approximate Reasoning Using Linguistic Synthesis
Guidelines for Scheduling Some Common Computation-Dags for Internet-Based Computing
Lightweight and Holistic-Scalable Serverless Secure Container Runtime for High-Density Deployment and High-Concurrency Startup
The Kappa Network with Fault-Tolerant Destination Tag Algorithm
Closed-Loop Control Systems Containing a Digital Computer
Computation of Concave Piecewise Linear Discriminant Functions Using Chebyshev Polynomials
An Approach to the Optimal Specification of Read-Only Memories in Microprogrammed Digital Computers
Multiprefix Trie: A New Data Structure for Designing Dynamic Router-Tables
A CORDIC Arithmethic Processor Chip
Simple Binary Identification Problems
Exploiting Core Working Sets to Filter the L1 Cache with Random Sampling
A Method for Evaluating Stieltjes Integrals on the Analog Computer
A Hybrid Walsh Transform Computer
Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems
Area-Time Efficient Implementation of the Elliptic Curve Method of Factoring in Reconfigurable Hardware for Application in the Number Field Sieve
B74-14 Data Base Systems
An Efficient LUT6-Based Montgomery Modular Multiplication Using Radix-16 Booth Method
A Unified and Fully Automated Framework for Wavelet-Based Attacks on Random Delay
Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring
Esaki Diode Logic Circuits
Determination of an Optimal Retry Time in Multiple-Module Computing Systems
A High-Speed Algorithm for the Generation of Straight Lines and Circular Arcs
High-Speed and Reduced-Area Modular Adder Structures for RNS
A Throughput-Oriented NVMe Storage Virtualization With Workload-Aware Management
Combinatorial Merging
Addendum to "The Focus Number System"
FLOTT - A Fast, Low Memory T-TransformAlgorithm for Measuring String Complexity
Mapping Trigger Conditions onto Trigger Units during Post-silicon Validation and Debugging
Some Comments on the Fast Hadamard Transform of Order Twelve
Accelerate RDP RAID-6 Scaling by Reducing Disk I/Os and XOR Operations
Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment
Efficient Parallel Convex Hull Algorithms
FTCAM: An Area-Efficient Flash-Based Ternary CAM Design
Remarks on the SHR-Optimal State Assignment Procedure
An Efficient Channel Routing Algorithm to Yield an Optimal Solution
Synthesis of Asynchronous Machines Using Minxed-Operation Mode
R68-35 Optimal Generation of Arbitrary Functions
Tests and Tolerances for High-Performance Software-Implemented Fault Detection
GPU Instruction Hotspots Detection Based on Binary Instrumentation Approach
Subcube Allocation in Hypercube Computers
Fault-Tolerant Decoders for Cyclic Error-Correcting Codes
Microprogramming and Numerical Analysis
The Indirect Binary n -Cube Microprocessor Array
Equational Logic
GFBE: A Generalized and Fine-Grained Blockchain Evaluation Framework
Towards Effective Local Search for Qubit Mapping
Emulation of Hypercube Architecture on Nearest-Neighbor Mesh-Connected Processing Elements
Introduction: Tutorial on Resolution
LUT Input Reordering to Reduce Aging Impact on FPGA LUTs
An Improved Stochastic Modeling of Opportunistic Routing in Vehicular CPS
An Instruction Set for Evaluating Expressions
A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs
General Bootstrapping Approach for RLWE-Based Homomorphic Encryption
Operational Amplifiers Using Controlled Superconductors
A Deductive Method for Simulating Faults in Logic Circuits
A Versatile Mechanism to Move Data in an Array Processor
Group Averaged Linear Transforms that Detect Corners and Edges
(t, k) - Diagnosis for Matching Composition Networks under the MM* Model
An Approach for the Synthesis of Multithreshold Threshold Elements
Semipermanent Storage by Capacitive Coupling