yusuke1997/dblp-id-title huggingface dataset:
Event-Triggered Optimized Control for Nonlinear Delayed Stochastic Systems
Impacts of Physical-Layer Information on Epidemic Spreading in Cyber-Physical Networked Systems
A Wide Air Gap IPT System for Distribution Insulator Applications Based on Reconfigurable Autotransformer Coupling Structure
Event-Triggered Predefined-Time Synchronization for Complex Networks With Markov Switching Topologies Under Stochastic DoS Attacks
Knowledge-Aided Automated Synthesis for Broadband Power Amplifier With Transformer-Coupled Resonators
Hardware Self-Organizing Map Based on Digital Frequency-Locked Loop and Triangular Neighborhood Function
S-QRD-ELM: Scalable QR-Decomposition-Based Extreme Learning Machine Engine Supporting Online Class-Incremental Learning for ECG-Based User Identification
Multi-Functional Single/Multi-Band Bandpass Filters With Co-Integrated RF Isolator, Variable Phase Shifter or Variable Attenuator Functionalities
Neural Network Training on In-Memory-Computing Hardware With Radix-4 Gradients
A Predictive SAR ADC Architecture
Exploration of Ternary Logic Using T-CMOS for Circuit-Level Design
Fault Modeling and Efficient Testing of Memristor-Based Memory
Analyzing the Impact of Memristor Variability on Crossbar Implementation of Regression Algorithms With Smart Weight Update Pulsing Techniques
A Maximum Logarithmic Maximum a Posteriori Probability Based Soft-Input Soft-Output Detector for the Coded Spatial Modulation Systems
Highly-Efficient Hardware Architecture for CRYSTALS-Kyber With a Novel Conflict-Free Memory Access Pattern
Enhanced ISI Analysis and Fast Circuit Simulation of High-Speed Current-Steering DACs
UFBBR: A Unified Frequency and Back-Bias Regulation Unit for Ultralow-Power Microcontrollers in 28-nm FDSOI
Adaptive Switching Control for Nonlinear Uncertain Systems With Sensor Faults and Quantization
A 32Gb/s Time-Based PAM-4 Transceiver for High-Speed DRAM Interfaces With In-Situ Channel Loss and Bit-Error-Rate Monitors
Re-Assessment of Steep-Slope Device Design From a Circuit-Level Perspective Using Novel Evaluation Criteria and Model-Less Method
A Fractional Order Notch Filter to Compensate the Attenuation-Loss Due to Change in Order of the Circuit
Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout
Bi-Directional Gated Ring Oscillator Time Integrator
DS-CIM: A 40nm Asynchronous Dual-Spike Driven, MRAM Compute-In-Memory Macro for Spiking Neural Network
A Compact 321-343-GHz Integrated CMOS Radiator by Co-Designing Ring Oscillator and Multifunctional Antenna
Current Zero-Crossing Shift During Compensation of Dead-Time Distortion in PWM VSI and Its Corrective Action in Current Sensor-Less Compensation
Gradient-Adaptive Spline-Interpolated LUT Methods for Low-Complexity Digital Predistortion
Fixed-Time Distributed Consensus Optimization Control of High-Order Nonlinear Multi-Agent Systems via a Penalty-Function-Based Method
A 6.78-MHz Wireless Power Transfer System With Dual-Output Resonant Current-Mode Regulating Rectifier and Transmission Power Regulation
Lattice Trajectory Piecewise Linear Method for the Simulation of Diode Circuits
A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers
Wideband Tunable N-Path Mixer With Calibrated Harmonic Rejection Including the 7th LO Harmonic
A "2 + 1" Cores Triple-Mode Oscillator
Synthetic Diversity for Artifact Suppression and Simultaneous Multi-Band Down-Conversion in Widely-Tunable Receivers
Offset Boosting-Oriented Construction of Multi-Scroll Attractor via a Memristor Model
Configurable Quasi-Optimal Sphere Decoding for Scalable MIMO Communications
Low-Power High Precision Floating-Point Divider With Bidimensional Linear Approximation
Analytical Model and Robust Design of PT-Symmetric CLLC Coreless Transformers With Non-Ideal Parameters
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS
A Multi-Step Incremental Analog-to-Digital Converter With a Single Opamp and Two- Capacitor SAR Extended Counting
Event-Triggered Prescribed-Time Tracking Control for Nonlinear Systems With Asynchronous Switching
Finite-Time Intra-Layer and Inter-Layer Quasi-Synchronization of Two-Layer Multi-Weighted Networks
A Low-Complexity Soft-Output Massive MIMO Detector With Near-Optimum Performance
Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network
Edge-Based Sender-Receiver Event-Triggered Schemes for Distributed Filtering
Event-Based Output Feedback Consensus Control for Multiagent Systems With Unknown Non-Identical Control Directions
Multilayer Reflectionless RF Bandpass Filters With Wideband Quasi-Constant Group-Delay Responses
Stability Assessment for Multi-Infeed Grid-Connected VSCs Modeled in the Admittance Matrix Form
Frequency-Flexible High Selectivity Multichannel Filtering Crossover Based on Slow-Wave Substrate Integrated Waveguide
An 80 MS/s 70.8 dB-SNDR Radiation-Tolerant Semi-Time-Interleaved Pipelined-SAR ADC for Space Applications
Iterative Guessing Random Additive Noise Decoder for Universal Decoding of Product Codes
Power Scaling Laws for Radio Receiver Front Ends
From MOSFETs to Ambipolar Transistors: Standard Cell Synthesis for the Planar RFET Technology
Online Distributed Convex Optimization for Unbalanced Varying Graphs With Delayed Feedback
A New Adaptive Sparse Pseudospectral Approximation Method and its Application for Stochastic Power Flow
Eyelet: A Cross-Mesh NoC-Based Fine-Grained Sparse CNN Accelerator for Spatio-Temporal Parallel Computing Optimization
THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs
A 870 ppm/V 53 ppm/ ° C 7 MHz Non-Trimmed RC Relaxation Oscillator Using Mixed-Signal Compensation Loop From - 40 ∘ C to 165 ∘ C
RRAM for Compute-in-Memory: From Inference to Training
Dynamical Analysis and Fixed-Time Synchronization for Secure Communication of Hidden Multiscroll Memristive Chaotic System
Memristor Synapse-Driven Simplified Hopfield Neural Network: Hidden Dynamics, Attractor Control, and Circuit Implementation
A Bio-Inspired Energy- and Area-Efficient Sound Localization Neural Network
On the Use of Artificial Neural Networks for the Automated High-Level Design of ΣΔ Modulators
Modular Modeling of Analog Organic Neuromorphic Circuits: Toward Prototyping of Hardware-Level Spiking Neural Networks
Adaptive Intelligent Control for Nonlinear Stochastic Cyber-Physical Systems With Unknown Deception Attacks: Switching Event-Triggered Scheme
FPGA Synthesis of Ternary Memristor-CMOS Decoders for Active Matrix Microdisplays
A 95.2% Efficiency DC-DC Boost Converter Using Peak Current Fast Feedback Control (PFFC) for Improved Load Transient Response
Bipartite Event-Triggered Output Tracking Consensus of Heterogeneous Linear Multi-Agent Systems Under Switching Directed Topologies
Radix-2 w Arithmetic for Scalar Multiplication in Elliptic Curve Cryptography
Frequency Design of Lossless Passive Electronic Filters: A State-Space Formulation of the Direct Synthesis Approach
Correntropy-Based Data Selective Adaptive Filtering
Dithering Concepts for Spur-Free Nonlinear DTC-Based Frequency Synthesizers
Analysis of Injection-Locked Ring Oscillators for Quadrature Clock Generation in Wireline or Optical Transceivers
Prespecified-Time Bipartite Consensus of Multi-Agent Systems via Intermittent Control
VLSI Architectures and Hardware Implementation of Ultra Low-Latency and Area-Efficient Pietra-Ricci Index Detector for Spectrum Sensing
CARLA: A Convolution Accelerator With a Reconfigurable and Low-Energy Architecture
A 3.5 GS/s 1-1 MASH VCO ADC With Second-Order Noise Shaping
A 296 nJ Energy-per-Measurement Relaxation Oscillator-Based Analog Front-End for Chemiresistive Sensors
PAM-4 Receiver With 1-Tap DFE Using Clocked Comparator Offset Instead of Threshold Voltages for Improved LSB BER Performance
Feedback Stabilization of Switched Linear Systems: A Quantization and Triggering Joint Event-Triggered Mechanism
Triple-Mode Reciprocal Doherty Power Amplifier With Multi-Band Operation and Extended High Efficiency Range
Hardware Architecture Design for Iterative Reconstruction Algorithms Toward Palm-Size Photoacoustic Tomography
A Simple Method for Constructing a Family of Hamiltonian Conservative Chaotic Systems
On Synchronization Design and State Observer Design of (Singular) Boolean Networks
An Ultra-Low Phase Noise Dual-Tank Oscillator Featuring Tank Impedance Scaling
Finite-Time State Zonotopes Design for Asynchronously Switched Systems With Application to a Switched Converter
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop
Fast Beam Training With True-Time-Delay Arrays in Wideband Millimeter-Wave Systems
Cyber-Physical Systems With Multiple Denial-of-Service Attackers: A Game-Theoretic Framework
Synchronization of Dynamical Networks With Heterogeneous Delays via Time-Varying Pinning
SymBIST: Symmetry-Based Analog and Mixed-Signal Built-In Self-Test for Functional Safety
Plesiochronous Spread Spectrum Clocking With Guaranteed QoS for In-Band Switching Noise Reduction
Synthesizing Step-Down Switched Capacitor Power Converter Topologies
Impedance Transparency and Performance Metrics of HBT-Based N-Path Mixers for mmWave Applications
Composite Velocity-Tracking Control for Flexible Gimbal System With Multi-Frequency-Band Disturbances
ReZK: A Highly Reconfigurable Accelerator for Zero-Knowledge Proof
Hardware Architecture for Supersingular Isogeny Diffie-Hellman and Key Encapsulation Using a Fast Montgomery Multiplier
Low-Overhead Triple-Node-Upset Self-Recoverable Latch Design for Ultra-Dynamic Voltage Scaling Application
A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers
An Output-Capacitor-Free NMOS Digital LDO Using Gate Driving Strength Modulation and Droop Detector
Vector Wave Digital Filters and Their Application to Circuits With Two-Port Elements
Firefly: A Versatile Experimental Platform for Oscillator-Based Ising Machines
Fast Algorithms for Resistance Distances on Signed Graphs
Design and Analysis of Energy Efficient Approximate Multipliers for Image Processing and Deep Neural Network
A 2941-TOPS/W Charge-Domain 10T SRAM Compute-in-Memory for Ternary Neural Network
State-of-the-Art ASCON ASIC Achieving 4.3 Gbps@0.8V and 3.5Tb/J@0.6V Outperforming AES by 25 Times
Highly Efficient Filtering Power Amplifier Using Impedance Area-Based Optimization
Memristive Circuit Design of Evolution and Decay of Emotion and Its Implementation in PAD Emotional Space
A Fully Symmetric Oscillator-Based CMOS Ising Machine Architecture With Successive Approximation Sampling and Power Efficient Solution Refinement
Event-Based Fuzzy Adaptive Consensus FTC for Microgrids With Nonlinear Item via Prescribed Fixed-Time Performance
FAB: FPGA-Accelerated Fully-Pipelined Bottleneck Architecture With Batching for High-Performance MobileNetv2 Inference
Parallel Implementation of SPHINCS+ With GPUs
Complex Motion Behavior and Synchronization Analysis of Heterogeneous Neural Network
Adaptive Neural Stochastic Control With Lipschitz Constant Optimization
Battery-Free Hybrid Ambient RF and Wind Energy Harvester for Outdoor IoTs
SPP-CNN: An Efficient Framework for Network Robustness Prediction
An Eight-Channel Switching-Linear Hybrid Dynamic Regulator With Dual-Supply LDOs for Thermo-Optic Tuning
Distributed Optimization of Uncertain Multiagent Systems With Disturbances and Actuator Faults via Exosystem Observer-Based Output Regulation
Broadband High-Efficiency Dual-Mode Doherty Power Amplifier Using Hybrid F/F -1 Continuous-Mode Technology
Cross-Layer Reliability Modeling of Dual-Port FeFET: Device-Algorithm Interaction
Enhanced Jitter Analysis and Minimization for Digital PLLs With Mid-Rise TDCs and its Impact on Output Phase Noise
Sampled-Data Control for Buck-Boost Converter Using a Switched Affine Systems Approach
A Dual-Entropy-Superposed PUF With In-Cell Entropy Sign-Based Stabilization
A 0.59-mW 78.7-dB SNDR 2-MHz Bandwidth Active-RC Delta-Sigma Modulator With Relaxed and Reduced Amplifiers
Floating-Domain Integrated GaN Driver Techniques for DC-DC Converters: A Review
Prescribed Time Recovery From State Constraint Violation via Approximation-Free Control Approach
Model-Independent Observer-Based Critically Damped Terminal Voltage Stabilization for Single Machine Infinite Bus Systems via High-Order Pole-Zero Cancellation Approach
FPGA Implementation of Threshold Projection Orthogonal Matching Pursuit Algorithm for Compressed Sensing Reconstruction
Robust Adaptive Control of High-Order Fully-Actuated Systems: Command Filtered Backstepping With Concurrent Learning
Analysis and Design of a Broadband Receiver Front End for 0.1-to-40-GHz Application
An Improved Hybrid Si/SiC CCM Totem-Pole Bridgeless PFC Rectifier With Active Power Decoupling
A New Boosted Active-Capacitor With Negative-G m for Wide Tuning Range VCOs
Exploring Hybrid FitzHugh-Rinzel (FHR) Neuron Model Behavior: Cost-Effective FPGA Implementation for High-Frequency and High-Precision Matching by Electromagnetic Flux Effects
Model-Free Adaptive Control for Nonlinear Systems Under Dynamic Sparse Attacks and Measurement Disturbances
Analysis and Design of Baseband Circuits for Higher-Order Reflection-Mode N-Path Filters
Application of Envelope-Following Techniques to the Simulation of Hybrid Power Systems
A 182.9-dB FoM 108.2-dB SFDR Power/Bandwidth Configurable Fully Dynamic Switched-Capacitor Zoom ADC With Interstage Leakage Shaping
High-Resolution Wideband Vector-Sum Digital Phase Shifter With On-Chip Phase Linearity Enhancement Technology
Fixed-Time Disturbance Observer-Based Control for Quadcopter Suspension Transportation System
Stabilization for a General Class of Fractional-Order Systems: A Sampled-Data Control Method
Design and Implementation of FRM-Based Wideband Channelizer for Passive Detection and Jamming Integrated Processor
BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars
A Highly Stable Low-Energy 10T SRAM for Near-Threshold Operation
A 4-Element Passive-Beamforming CT- ΔΣ ADC for Spatial Selectivity in Automotive Radar
ISCAS Guest Editorial Special Issue Based on the 2025 IEEE International Symposium on Circuits and Systems
A Reconfigurable and Area-Efficient Polynomial Multiplier Using a Novel In-Place Constant-Geometry NTT/INTT and Conflict-Free Memory Mapping Scheme
Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms
Analysis and Optimization for Voltage Overload Resilience of Hybrid Transformers Under Grid Voltage Fluctuations
Distributed Time-Varying Economic Dispatch via a Prediction-Correction Method
Consensus of Multi-Agent Systems via Aperiodically Intermittent Sampling Stochastic Noise
A 2 A Dual Loop LDO With Dynamic Negative Feedback Loop and G m Boosting Error Amplifier for Off-Chip and Cap-Less Applications
Temporal Frame Filtering for Autonomous Driving Using 3D-Stacked Global Shutter CIS With IWO Buffer Memory and Near-Pixel Compute
Resilient Synchronization for Insecure Markovian Jump Neural Networks to Mitigate Dual Cyber Attacks
Parameter-Estimate-First False Data Injection Attacks in AC State Estimation Deployed With Moving Target Defense
Calculation of the Worst-Case Voltage Noise for a Power Distribution Network Based on Ramp Current
Slew-Rate Booster and Frequency Compensation Circuit for Automotive LDOs
P 3 ViT: A CIM-Based High-Utilization Architecture With Dynamic Pruning and Two-Way Ping-Pong Macro for Vision Transformer
A 0.4 V, 6.4 nW, -75 dBm Sensitivity Fully Differential Wake-Up Receiver for WSNs Applications
Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects
A Consistency Enhancement Technique for MIMO Power Amplifier Modules
Bipartite Synchronization of Fractional-Order Multi-Layer Signed Network With a Non-Autonomous Leader
Neural ODE Model of Power Electronic Converters With Accelerated Computation and High Fidelity
Knowledge Transfer Framework for PVT Robustness in Analog Integrated Circuits
An Ultra Low-Power Programmable Voltage Reference for Power-Constrained Electronic Systems
Impedance-Circuit-Based Stability Analysis for PLL-Synchronized Voltage Source Converter in Weak Grid
Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS
Efficient FPGA Implementation of Multi-Channel Pipelined Large FFT Architectures Based on SA-MDF Algorithm
A Memcapacitor Biomimetic Circuit Realizing Classical Conditioning and Fear Learning
High-Speed Nonlinear Circuit Macromodeling Using Hybrid-Module Clockwork Recurrent Neural Network
A Cryo-CMOS Oscillator With an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications
Dynamic Deadband Event-Triggered Strategy for Distributed Adaptive Consensus Control With Applications to Circuit Systems
Ferroelectric Compute-in-Memory Framework for Solving Pure and Mixed Strategy Nash Equilibrium
Real-Time 5.7-5.8 GHz 32-Beam Approximate Discrete Fourier Transform Spectrum Sensor for RF Perception on Xilinx Sx475T
Local Activity Principle: Cause of Insulin Secretion by Pancreatic β-cells
A 2.85-mm 2 Wideband RF Transceiver in 40-nm CMOS for IoT Micro-Hub Applications
Unified Performance Control of Spacecraft Attitude Tracking With Relaxed Quaternion Conditions
Adaptive Cooperative Terminal Sliding Mode Control for Distributed Energy Storage Systems
12-bit Delta-Sigma ADC Operating at a Temperature of Up to 250 ° C in Standard 0.18 μm SOI CMOS
Data-Driven Fuzzy Constant Voltage Regulation of Inductive Power Transfer Systems
A RISC-V Domain-Specific Processor for Deep Learning-Based Channel Estimation
Adaptive Iterative Learning Prescribed Performance Control of Uncertain Strict-Feedback Systems With Improved Parameter Estimation
Energy Efficient Memristive Transiently Chaotic Neural Network for Combinatorial Optimization
AC-PM: An Area-Efficient and Configurable Polynomial Multiplier for Lattice Based Cryptography
Fully Actuated System Approach Based Prescribed-Time Fault-Tolerant Formation Control for Unmanned Helicopters Under Fixed and Switching Topologies
TDPRO: Time-Domain-Based Computing-in Memory Engine for Ultra-Low Power ECG Processor
A High-PSRR NMOS LDO Regulator With Intrinsic Gain-Tracking Ripple Cancellation Technique
Dilate-Invariant Temporal Convolutional Network for Real-Time Edge Applications
An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge
Dual-Mode Analog Counter With Precise Step Regulation and Successive Approximate Calibration Circuit for SPAD Image Sensors
Scalable Multi-Stage CMOS OTAs With a Wide C L -Drivability Range Using Low-Frequency Zeros
WDVR-RAM: A 0.25-1.2 V, 2.6-76 POPS/W Charge-Domain In-Memory-Computing Binarized CNN Accelerator for Dynamic AIoT Workloads
Robot Strategy Transfer Based on Shared Feature Space for Search and Insertion Assembly
Advancements in Content-Addressable Memory (CAM) Circuits: State-of-the-Art, Applications, and Future Directions in the AI Domain
X-NVDLA: Runtime Accuracy Configurable NVDLA Based on Applying Voltage Overscaling to Computing and Memory Units
Non-Reduced Order Method to Parameterized Sampled-Data Stabilization of Inertial Neural Networks With Actuator Saturation
A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces
A Fast and Energy-Efficient SNN Processor With Adaptive Clock/Event-Driven Computation Scheme and Online Learning
Synaptic and Myelin Plasticity and Their Synergistic Effects in Neuromorphic Networks
A High-Throughput and Flexible CNN Accelerator Based on Mixed-Radix FFT Method
In Vitro Study of Artifact-Recovery Using a 32-Channel Neuromodulator Platform
Identification of Nonlinear State-Space Systems With Skewed Measurement Noises
A Galvanic Isolated Amplifier Based on CMOS Integrated Hall-Effect Sensors
Highly Efficient Wideband GaN MMIC Doherty Power Amplifier Considering the Output Capacitor Influence of the Peaking Transistor in Class-C Operation
Emerging Terahertz Integrated Systems in Silicon
A Compact Broadband Voltage-Combined Doherty Power Amplifier With Shorted Transmission Line for 5G Millimeter-Wave
Grid Homogeneous Coexisting Hyperchaos and Hardware Encryption for 2-D HNN-Like Map
Full-Circuit Implementation of Transformer Network Based on Memristor
A Low-Profile Autonomous Interface Circuit for Piezoelectric Micro-Power Generators
VLSI Architecture Design for Compact Shortcut Denoising Autoencoder Neural Network of ECG Signal
An Integer-N Reference-Double-Sampling PLL for Frequency-Multiplied Octa-Phase Clock Generation Achieving -251.9 dB FOM Jitter-N
Reservoir Computing Based on Memristor Arrays in Random States
Attack-Defense Evolutionary Game Strategy for Uploading Channel in Consensus-Based Secondary Control of Islanded Microgrid Considering DoS Attack
Multi-Mode QC-LDPC Decoding Architecture With Novel Memory Access Scheduling for 5G New-Radio Standard
A Single Stage Integrated Interface Circuit for Triboelectric Energy Harvester for Wearable Applications
Set-Based Obfuscation for Strong PUFs Against Machine Learning Attacks
Reliable and Efficient Parallel Checkpointing Framework for Nonvolatile Processor With Concurrent Peripherals
Memristor-Based Neural Network Circuit of Operant Conditioning Accorded With Biological Feature
A Reconfigurable Floating-Point Division and Square Root Architecture for High-Precision Softmax
A Hardware-Friendly Approach Towards Sparse Neural Networks Based on LFSR-Generated Pseudo-Random Sequences
Multi-Frequency-Band Uncertainties Rejection Control of Flexible Gimbal Servo Systems via a Comprehensive Disturbance Observer
DRGA-Based Second-Order Block Arnoldi Method for Model Order Reduction of MIMO RCS Circuits
A High-Accuracy Single-Photon Time-Interval Measurement in Mega-Hz Detection Rates With Collaborative Variance Reduction: Theoretical Analysis and Realization Methodology
A 28-nm 135.19 TOPS/W Bootstrapped-SRAM Compute-in-Memory Accelerator With Layer-Wise Precision and Sparsity
Design and Implementation of Grid-Wing Hidden Chaotic Attractors With Only Stable Equilibria
Gate-Source Voltage Peak Analysis and Prediction of eGaN HEMT in Turn-On Switching Transient
A Low-Power Graph Convolutional Network Processor With Sparse Grouping for 3D Point Cloud Semantic Segmentation in Mobile Devices
Low-Power Row Driver for Digitally Driven OLEDoS Microdisplay
Modeling and Control of Islanded DC Microgrid Clusters With Hierarchical Event-Triggered Consensus Algorithm
Sampled-Data-Based Dynamic Event-Triggered Synchronization of Semi-Markov Jump Complex Networks With Conic-Type Nonlinearity
SWPU: A 126.04 TFLOPS/W Edge-Device Sparse DNN Training Processor With Dynamic Sub-Structured Weight Pruning
Non-Weighted L 2 -Gain Analysis for Synchronization of Switched Nonlinear Time-Delay Systems With Random Injection Attacks
Architectural Trade-Off Analysis for Accelerating LSTM Network Using Radix-r OBC Scheme
A 0.2-V 10-Bit 5-kHz SAR ADC With Dynamic Bulk Biasing and Ultra-Low-Supply-Voltage Comparator
Model-Free Adaptive Containment Control for Unknown Multi-Input Multi-Output Nonlinear MASs With Output Saturation
Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs
Accelerated Nash Equilibrium Seeking for Constrained Multi-Cluster Games With Time-Varying Communication
Co-Design of Fault Detection and Consensus Control Protocol for Multi-Agent Systems Under Hidden DoS Attack
On the Damping of Ringing Affecting Power Transistors by Means of Active Gate Drivers
Advanced Quantization Schemes to Increase Accuracy, Reduce Area, and Lower Power Consumption in FFT Architectures
Design and Analysis of a Type-II Sampling PLL With Automatic Frequency and Phase Calibrations Achieving 0.62-μs Locking Time
Proportional-Integral and Nonlinear Cubic Control to Enhance Small-Signal and Transient Stability of EV Charging Station and DC Microgrid
A 0.92-pJ/b 112-Gb/s PAM-4 Transmitter With Bandwidth and Linearity Enhanced Quasi-Voltage-Mode Driver and Reconfigurable Three-Tap T/2-T Variable Fractional-Spaced FFE in 28-nm CMOS
A Low-Noise and Low-Power Multi-Channel ECG AFE Based on Orthogonal Current-Reuse Amplifier