yusuke1997/dblp-id-title huggingface dataset:
An Area Optimization Approach for Large-Scale RM-TB Dual Logic Circuits Based on a Multitasking Optimization Algorithm
Design and Analysis of Dynamic Redundancy Networks
A Benes-like Theorem for the Shuffle-Exchange Graph
General Model for Memory Interference in Mulitprocessors and Mean Value Analysis
ReViT: Vision Transformer Accelerator With Reconfigurable Semantic-Aware Differential Attention
Wildcard Dimensions, Coding Theory and Fault-Tolerant Meshes and Hypercubes
Fault Detecting Test Sets for Reed-Muller Canonic Networks
Integer Division in Residue Number Systems
On the Encoding of Arbitrary Geometric Configurations
Design and Analysis of Area and Power Efficient Approximate Booth Multipliers
Comments on "An O(n) Parallel Multiplier with Bit-Sequential Input and Output"
On the Minimization of READ-ONLY Memories in Microprogrammed Digital Computers
Analysis and Synthesis of Asynchronous Sequential Networks Using Edge-Sensitive Flip-Flops
A New Hardware Architecture for Operations in GF(2m)
Area Efficient and Fast Combined Binary/Decimal Floating Point Fused Multiply Add Unit
All-to-All Broadcasting in Faulty Hypercubes
A Performance Study of Discrete-Error-Checking Scheme (DECS) with the Optimal Division Locations for IEEE 802.16-Based Multihop Networks
Leakage-Free Dissemination of Authenticated Tree-Structured Data With Multi-Party Control
The Application of Filtered Transforms to the General Classification Problem
A High-Performance Memory Allocator for Object-Oriented Systems
Representing the Effect of Instruction Prefetch in a Microprocessor Performance Model
HiCoCS: High Concurrency Cross-Sharding on Permissioned Blockchains
Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design
Memory Versus Error Characteristics for Inexact Representations of Linear Orders
Fault-Tolerant Features in the HaL Memory Management Unit
RFID Support for Accurate 3D Localization
An Experimental Result on Character Recognition
PyTracer: Automatically Profiling Numerical Instabilities in Python
GAMMON: A Load Balancing Strategy for Local Computer Systems with Multiaccess Networks
Fail-Safe Asynchronous Sequential Machines
A Hardware Algorithm for Modular Multiplication/Division
Zero-Jitter Chains of Periodic LET Tasks via Algebraic Rings
Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance
An Efficient and Trustworthy P2P and Social Network Integrated File Sharing System
A Fast Faddeev Array
A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders
Large Response to "Comments on 'An O(n^2.5) Fault Identification Algorithm for Diagnosable Systems"'
Energy Reduction in Consolidated Servers through Memory-Aware Virtual Machine Scheduling
Generalized Measures of Fault Tolerance with Application to N-Cube Networks
The Circulating Processor Model of Parallel Systems
Distributed Fault-Tolerant Ring Embedding and Reconfiguration in Hypercubes
Hypernet: A Communication-Efficient Architecture for Constructing Massively Parallel Computers
A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories
Automated Synthesis of Digital Hardware
Diversified Test Methods for Local Control Units
Mixed-Radix Gray Codes in Lee Metric
Some Problems in Certifying Microprograms
Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting
AEIS: A New Energy Efficiency Improvement Scheme for MLC STT-MRAM
Characterization of Connection Assignment of Diagnosable Systems
Conditions for the Existence of Fast Number Theoretic Transforms
Continuous Shading of Curved Surfaces
Computation of Time-Phase Displacements of Binary Linear Sequence Generators
User Collusion Avoidance Scheme for Privacy-Preserving Decentralized Key-Policy Attribute-Based Encryption
Percolation of Code to Enhance Parallel Dispatching and Execution
On Identification of Redundancy and Symmetry of Switching Functions
Fuzzy Multiple-Input Maximum and Minimum Circuits in Current Mode and Their Analyses Using Bounded-Difference Equations
Guest Editors' Introduction to the Special Section on Cryptographic Hardware and Embedded Systems
UCFS-A Novel User-Space, High Performance, Customized File System for Web Proxy Servers
A Structure-Aware Storage Optimization for Out-of-Core Concurrent Graph Processing
FPGA Designs with Optimized Logarithmic Arithmetic
A Simple Probability Model Yielding Performance Bounds for Modular Memory Systems
LAMP: Improving Compression Ratio for AMR Applications via Level Associated Mapping-Based Preconditioning
On Switching Policies for Modular Redundancy Fault-Tolerant Computing Systems
Analysis of the Effects of Delays on Load Sharing
Non-Blocking Testing for Network-on-Chip
Truthful Scheduling Mechanisms for Powering Mobile Crowdsensing
Asymmetrically Decentralized Federated Learning
On the Security of Quotient Filters: Attacks and Potential Countermeasures
Pattern Matching Under Affine Transformation
An Evaluation of an Implementation of Qualified Hyperresolution
Computation of sqrt(x/d) in a Very High Radix Combined Division/Square-Root Unit with Scaling
A Tabular Minimization Procedure for Ternary Switching Functions
On Universal Single Transition Time Asynchronous State Assignments
Comments on "Error Bounds for a Contextual Recognition Procedure"
A Group-Theoretic Model for Symmetric Interconnection Networks
The Orientation of Modules Based on Graph Decomposition
Digit Stability Inference for Iterative Methods Using Redundant Number Representation
Algorithms for Calculating Correctly Rounded Exponential Function in Double-Precision Arithmetic
A Design of a Fast Cellular Associative Memory of Ordered Retrieval
MANIP - A Multicomputer Architecture for Solving Combinatorial Extremum-Search Problems
Minimizing Sum of Completion Times and Makespan in Master-Slave Systems
Amnesiac DRAM: A Proactive Defense Mechanism Against Cold Boot Attacks
Adaptive Resource Allocation Control for Fair QoS Management
Problems and Experiments for and with Automated Theorem-Proving Programs
B72-18 Computers and Their Uses, 2nd ed
Modeling the Reliability of a Class of Fault-Tolerant VLSI/WSI Systems Based on Multiple-Level Redundancy
A Design for Multiple-Valued Logic Gates Based on MESFET's
A Closed-Form Solution for the Performance Analysis of Multiple-Bus Multiprocessor Systems
Operand-Oriented Virtual Memory Support for Near-Memory Processing
An Algorithm for the Automatic Approximate Minimization of Boolean Functions
A Reliable Fail-Safe System
MOS Test Pattern Generation Using Path Algebras
Pipelined Computation of Very Large Word-Length LNS Addition/Subtraction with Polynomial Hardware Cost
Hybrid Method for Minimizing Service Delay in Edge Cloud Computing Through VM Migration and Transmission Power Control
Clocking Schemes for High-Speed Digital Systems
On the Design of Easily Testable Iterative Systems of Combinational Cells
Online Adaptive Compression in Delay Sensitive Wireless Sensor Networks
Scientific and Technical Conventions
Page Reusability-Based Cache Partitioning for Multi-Core Systems
A Partitioning Strategy for Nonuniform Problems on Multiprocessors
Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations
A VLSI Architecture for Fast Inversion in GF(2^m)
Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory
Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers
Traffic-Aware Design of a High-Speed FPGA Network Intrusion Detection System
Redundancy by Coding Versus Redundancy by Replication for Failure-Tolerant Sequential Circuits
Similarity-Based Load Adjustment for Static Real-Time Transaction Systems
On an Approximation of Mutual Information
Parallel Algorithms for Generating Harmonised State Identifiers and Characterising Sets
DACO: A High-Performance Disk Architecture Designed Specially for Large-Scale Erasure-Coded Storage Systems
Truthful Mechanisms for Allocating a Single Processor to Sporadic Tasks in Competitive Real-Time Environments
Tolerating Multiple Faults in Multistage Interconnection Networks with Minimal Extra Stages
Fault-Tolerant Meshes and Hypercubes with Minimal Numbers of Spares
An Algorithm for NAND Decomposition Under Network Constraints
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
COFTA: Hardware-Software Co-Synthesis of Heterogeneous Distributed Embedded Systems
MAR: A Novel Power Management for CMP Systems in Data-Intensive Environment
High-Precision Error Bit Prediction for 3D QLC NAND Flash Memory: Observations, Analysis, and Modeling
CEnT: An Efficient Architecture to Eliminate Intra-Array Write Disturbance in PCM
Accuracy vs. Precision in Digital VLSI Architectures for Signal Processing
Cutpoint Cellular Logic
Representation of Concurrency with Ordering Matrices
A Survey of Preprocessing and Feature Extraction Techniques for Radiographic Images
Study of a Parametron on an Analog Computer
On-Line AP Association Algorithms for 802.11n WLANs with Heterogeneous Clients
A Mathematical Model Characterizing Four-Phase MOS Circuits for Logic Simulation
The Application of Shift Registers to Secondary State Assignment: Part II
Fault-Tolerant Distributed Algorithm for Election in Complete Networks
Basic Operations in an Unnormalized Arithmetic System
Berger Check Prediction for Array Multipliers and Array Dividers
A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits
Digital Hardware for Sine-Cosine Function
On Simplifying Truth Functions: A Preliminary Reduction of Coreless Formulas
A Note on the Linear Space Automata Stability Problem
Author's Reply 4
An Improved Upper Bound for the Finite Delay of Graphs
HRT-PLRU: A New Paging Schemefor Executing Hard Real-Time Programson NAND Flash Memory
Computational Geometry - A Survey
An Exponentiation Unit for an OpenGL Lighting Engine
TreeFTL: An Efficient Workload-Adaptive Algorithm for RAM Buffer Management of NAND Flash-Based Devices
A Theory of Totally Self-Checking System Design
A Measure of Guaranteed Availability and its Numerical Evaluation
Progressive Congestion Management Based on Packet Marking and Validation Techniques
A Simulation Method for Computer Control Systems
An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory
An Improved Algorithm for the Simplification of Switching Functions Using Unique Identifiers on a Karnaugh Map
Performance Optimization Using Partitioned SpMV on GPUs and Multicore CPUs
DPR, LPR: Proactive Resource Allocation Algorithms for Asynchronous Real-Time Distributed Systems
Automated Test Cases Generator for IEC 61131-3 Structured Text Based Dynamic Symbolic Execution
Adaptive Cache Design to Enable Reliable Low-Voltage Operation
Time Series Characterization of Gaming Workload for Runtime Power Management
System Design of a Small, Fast Digital Computer
The Complexity of Monotone Networks for Certain Bilinear Forms, Routing Problems, Sorting, and Merging
A Hyper Optimal Encoding Scheme for Self-Checking Circuits
An Efficient Sorting Algorithm on the Multi-Mesh Network
Static Classification of Value Predictability Using Compiler Hints
Combinational and Sequential Cellular Structures
Enabling Secure and Space-Efficient Metadata Management in Encrypted Deduplication
On Self-Fault Diagnosis of the Distributed Systems
Cloudlets Activation Scheme for Scalable Mobile Edge Computing with Transmission Power Control and Virtual Machine Migration
B72-11 An Introduction to Switching System Design
File Assignment in Parallel I/O Systems with Minimal Variance of Service Time
On Diagnosability of Large Fault Sets in Regular Topology-Based Computer Systems
Exploiting Implementation Diversity and Partial Connection of Routers in Application-Specific Network-on-Chip Topology Synthesis
An Adaptive Algorithm to Ensure Differential Service in aToken-Ring Network
The Counting Recursive Digital Filter
Proposal for Magnetic Domain-Wall Storage and Logic
Anonymous Multireceiver Identity-Based Encryption
Guest Editors' Introduction: Special Section on Design and Test of Systems-on-Chip (SoC)
Theory of Clocking for Maximum Execution Overlap of High-Speed Digital Systems
Space-Efficient and Fault-Tolerant Message Routing in Outerplanar Networks
Comments on "The Anomalous Behavior of Flip-Flops in Synchronizer Circuits"
Recursive Methods for Matrix Inversion in Pattern Recognition Environments
Efficient Stack Simulation for Set-Associative Virtual Address Cache with Real Tags
VMT: Virtualized Multi-Threading for Accelerating Graph Workloads on Commodity Processors
Definite Asynchronous Sequential Circuits
A Stochastic Optimization Algorithm Minimizing Expected Flow Times on Uniform Processors
Fault-Tolerant Multiprocessor Link and Bus Network Architectures
TCOT-A Timeout-Based Mobile Transaction Commitment Protocol
On Dictionary-Based Fault Location in Digital Logic Circuits
Conditional (t, k)-Diagnosis in Graphs by Using the Comparison Diagnosis Model
Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework
A Graph Partitioning Approach to Sequential Diagnosis
Transition Logic Circuits and a Synthesis Method
Latch-Based Structure: A High Resolution and Self-Reference Technique for Hardware Trojan Detection
Periodic Binary Time Series and Their Relation to Boolean Functions
On Minimal Test Sets for Locating Single Link Failures in Networks
Reliability-Driven System-Level Synthesis for Mixed-Critical Embedded Systems
Quality-Driven Dynamic Scheduling for Real-Time Adaptive Applications on Multiprocessor Systems
A New Method for Generating a Function of Two Independent Variables
Bitonic Sort on a Mesh-Connected Parallel Computer
A Test for Unate Truth Functions
Relationship of Poisson Transform to Laguerre Expansions
A Deep Neural Network Training Architecture With Inference-Aware Heterogeneous Data-Type
Effective Hardware Based Data Prefetching for High-Performance Processors
Theoretical Consideration of Computing Errors of a Slow Type Electronic Analog Computer
State-Space Methods for Designing Digital Simulations of Continuous Fixed Linear Systems
Building Expressive and Area-Efficient Directories with Hybrid Representation and Adaptive Multi-Granular Tracking
NetMod: Toward Accelerating Cloud RAN Distributed Unit Modulation Within Programmable Switches
Fault Diagnosos in a Boolean n Cube Array of Microprocessors
ParBFT: An Optimized Byzantine Consensus Parallelism Scheme
Bubble Budgeting: Throughput Optimization for Dynamic Workloads by Exploiting Dark Cores in Many Core Systems
A Machine Learning-Empowered Cache Management Scheme for High-Performance SSDs
RGKV: A GPGPU-Empowered Compaction Framework for LSM-Tree-Based KV Stores With Optimized Data Transfer and Parallel Processing
R70-3 On Stochastic Languages
Adaptive Algorithms for Maximal Diagnosis of Wiring Interconnects
Comments on "Fault Diagnosis of MOS Combinational Networks"
Optimal Skewed Data Allocation on Multiple Channels with Flat Broadcast per Channel
Monotone Functions in Sequential Circuits
Error Analysis of Certain Floating-Point On-Line Algorithms
DCAS-BMT: Dynamic Construction and Adjustment of Skewed Bonsai Merkle Tree for Performance Enhancement in Secure Non-Volatile Memory
The Correspondence Between Methods of Digital Division and Multiplier Recoding Procedures
The Sign/Logarithm Number System
Cohorts Structures for Fault-Tolerant k Entries to a Critical Section
B72-27 The Fourth Generation
Error Detection and Correction by Product Codes in Residue Number Systems
A Versatile Problem-Oriented Language for Engineers
Packet Switching Networks for Multiprocessors and Data Flow Computers
Comment on "A Nonlinear Mapping for Data Structure Analysis"
Adaptive ECC Scheme for Hybrid SSD's
Design of a Radix 4 Division Unit with Simple Selection Table
A Note on State Minimization of a Special Class of Incomplete Sequential Machines
Hardware Architecture for High-Performance Regular Expression Matching
Two-Dimensional Static Test Compaction for Functional Test Sequences
New Hardware Implementations of WG(29, 11) and WG-16 Stream Ciphers Using Polynomial Basis
Enforcing Pontryagin's Maximum Principle by Continuous Steepest Descent
A General Communication Cost Optimization Framework for Big Data Stream Processing in Geo-Distributed Data Centers
A Trace-Capable Instruction Cache for Cost-Efficient Real-Time Program Trace Compression in SoC
Measures of the Effectiveness of Fault Signature Analysis
Perfect Shifters
On the Existence of a Periodic Analog of a Finite Connected Automaton
Formally Verified Argument Reduction with a Fused Multiply-Add
Composite Parallel Counters
Optimum Time Sharing of a Digital Communication Channel
Efficient and Strategyproof Spectrum Allocations in Multichannel Wireless Networks
Greedy, Prohibition, and Reactive Heuristics for Graph Partitioning
Complexity-Effective Reorder Buffer Designs for Superscalar Processors
Improved Area-Time Tradeoffs for Field Multiplication Using Optimal Normal Bases
On the Generation of SIC Pairs in Optimal Time
Enhancing Instruction TLB Resilience to Soft Errors
Finding the Core Point in a Fingerprint
Four State Asynchronous Architectures
Comment on "An Algorithm for a Fast Hadamard Matrix Transform of Order Twelve"
Data Sharing in the Metaverse With Key Abuse Resistance Based on Decentralized CP-ABE
ICCI: In-Cache Coherence Information
An Approach to Unified Methodology of Combinational Switching Circuits
A Self-Testing Nonincreasing Order Checker
A New Quorum-Based Scheme for Managing Replicated Data in Distributed Systems
External Mergesort for Flash-Based Solid State Drives
Recognition of Spoken Words and Phrases in Multitalker Environment Using Syntactic Methods
Synthesis of N-Valued Switching Circuits
Rad-Hard Designs by Automated Latching-Delay Assignment and Time-Borrowable D-Flip-Flop
Loop-Abort Faults on Lattice-Based Signature Schemes and Key Exchange Protocols
Comments on "A pattern recognition experiment with near-optimum results" and "Pattern classification by iteratively determined linear and piecewise linear discriminant functions'"
Minimal-Memory Requirements for Pearl-Necklace Encoders of Quantum Convolutional Codes
Low Diameter Interconnections for Routing in High-Performance Parallel Systems
Integer Codes Correcting Burst Errors within a Byte
Carry-Save Multiplication Schemes without Final Addition
Design of Efficient Balanced Codes
Realizing Transparent OS/Apps Compression in Mobile Devices at Zero Latency Overhead
Concurrent Error Detection on Programmable Systolic Arrays
Electrical delay lines for digital computer applications
Stateless Multicasting in Mobile Ad Hoc Networks
Remarks on "Comments on 'An Algorithm for Synthesis of Multiple-Output Combinational Logic'"
Towards Optimal Customized Architecture for Heterogeneous Federated Learning With Contrastive Cloud-Edge Model Decoupling
CONET: A Connection Network Model
Bandwidth-Aware On-Line Scheduling in SMT Multicores
Diodeless Magnetic Shift Registers Utilizing Transfluxors
SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems
dAElite: A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up
Novel Convolutions Using First-Order Moments
Active CTDaaS: A Data Service Framework Based on Transparent IoD in City Traffic
Attacking the Privacy of Approximate Membership Check Filters by Positive Concentration
Coping with Erroneous Information while Sorting
Universal Logic Modules of a New Type
Square-Rooting Algorithms for High-Speed Digital Circuits
A Robust Matrix-Multiplication Array
Dynamic Testing of Redundant Logic Networks
Modification of "A Least Mean Squares CUBIC Algorithm for On-Line Differential of Sampled Analog Signals"
Fast Algorithms for the 2-D Discrete Cosine Transform
A Sequential Circuit for Algebraic Statement Translation
Optimal and Near-Optimal Checking Experiments for Output Faults in Sequential Machines
Programmable Industrial Automation
RvDfi: A RISC-V Architecture With Security Enforcement by High Performance Complete Data-Flow Integrity
Highlights of a Study of Floating-Point Instructions
Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning
Recursively Partitioned Static IP Router Tables
Identifying Efficient Combinations of Error Detection Mechanisms Based on Results of Fault Injection Experiments
Footprint-Based DIMM Hotplug
Optimized Broadcast Protocol for Sensor Networks
Improving the Performance of Buddy Systems
Matrix Operations on a Multicomputer System with Switchabel Main Memory Modules and Dynamic Control
Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs
Nationwide Prediction of Drought Conditions in Iran Based on Remote Sensing Data
Concurrent Error Detection Methods for Asynchronous Burst-Mode Machines
An Infinite-Resolution Function Generator
1960 PGEC Membership Report
R68-21 System Architecture for Large Scale Integration
Aging-Aware Boosting
A Study of k-Coverage and Measures of Connectivity in 3D Wireless Sensor Networks
Models for the Combined Logical and Physical Design of Databases
Optimal Dynamic Remapping of Data Parallel Computations
Direct Execution of Programs in Floating Code by Address Interpretation
Soviet Cybernetics and Computer Sciencesߞ1960
Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Softcore Processor
A Theorem for Deriving Majority-Logic Networks Within an Augmented Boolean Algebra
Incendio: Priority-Based Scheduling for Alleviating Cold Start in Serverless Computing
Memory Allocation for Multiprocessors
A Linear Decomposition for Sequential Machines
Sustaining Availability of Web Services under Distributed Denial of Service Attacks
The IRE "Affiliate" PlanߞA New Venture in Engineering Society Structure and Service
A Digital Integrator for On-Line Signal Processing
LAWC: Optimizing Write Cache Using Layout-Aware I/O Scheduling for All Flash Storage
Optimal Replacement Is NP-Hard for Nonstandard Caches
Karatsuba Matrix Multiplication and Its Efficient Custom Hardware Implementations
Equilibrium Point Analysis of Memory Interference in Multiprocessor Systems
A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits
Observations Concerning the Complexity of a Class of On-Line Algebraic Problems
New Architectures for Digit-Level Single, Hybrid-Double, Hybrid-Triple Field Multiplications and Exponentiation Using Gaussian Normal Bases
FFT Length in Digital Filtering
Improving Quality of VoIP Streams over WiMax
Comments on "A Minimization Technique for TANT Networks"
Corrections to "A Secure Fault-Tolerant Conference-Key Agreement Protocol"
A New Interconnection Network for SIMD Computers: The Sigma Network
Algorithms in Numerical Geometry System
High Speed Decimal Addition
KDN-Based Adaptive Computation Offloading and Resource Allocation Strategy Optimization: Maximizing User Satisfaction
Data Flow Representation of Iterative Algorithms for Systolic Arrays
Schedulability Analysis for Self-Suspending Tasks Under EDF-Like Scheduling
Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs
First-and Second-Order Ferrite Memory Core Characteristics and Their Relationship to System Performance
Multilanguage Parallel Programming of Heterogeneous Machines
Monte Carlo Solution of Partial Differential Equations by Special Purpose Digital Computer
A New Class of Single Burst Error Correcting Codes with Parallel Decoding
Constructing Performance-Predictable Clusters with Performance-Varying Resources of Clouds
An Incremental Server for Scheduling Overloaded Real-Time Systems
Isomorphism of Conflict Graphs in Multistage Interconnection Networks and Its Application to Optimal Routing
On the Equivalence of Two Algorithms for Finding All Maximal Compatibles
Late Allocation and Early Release of Physical Registers
Schedulability Envelope for Real-Time Radar Dwell Scheduling
On the Modeling of Demand Paging Algorithms by Finite Automata
Improving Data Locality by Array Contraction
New Outlook on Processing Radiation Received From Objects Viewed Through Randomly Fluctuating Media
On-Chip Communication Network for Efficient Training of Deep Convolutional Networks on Heterogeneous Manycore Systems