yusuke1997/dblp-id-title huggingface dataset:
Privacy Preserving Deep Computation Model on Cloud for Big Data Feature Learning
A Generalized Pipeline Array
Importance of Coherence Protocols with Network Applications on Multicore Processors
A Self-Routing Benes Network and Parallel Permutation Algorithms
Signature Tree Generation for Polymorphic Worms
On the Rearrangeability of 2(log 2 N ) - 1 Stage Permutation Networks
Design of a Massively Parallel Processor
Line Digraph Iterations and the ( d, k ) Digraph Problem
Radix-2 Multioperand and Multiformat Streaming Online Addition
Flux Divison in a Saturable Multipath Core
A Redundant Representation of GF(q^n) for Designing Arithmetic Circuits
A Modified TRAM Architecture
On the Selection of Management/Monitoring Nodes in Highly Dynamic Networks
Efficient Repair Analysis Algorithm Exploration for Memory With Redundancy and In-Memory ECC
Multi-Objective Hardware-Mapping Co-Optimisation for Multi-DNN Workloads on Chiplet-Based Accelerators
Combined Modular Key and Data Error Protection for Content-Addressable Memories
An Algebra for Switching Circuits
Defying Multi-Model Forgetting in One-Shot Neural Architecture Search Using Orthogonal Gradient Learning
2 n RNS Scalers for Extended 4-Moduli Sets
Saca-AVF: A Quantitative Approach to Analyze the Architectural Vulnerability Factors of CNN Accelerators
The Design of New Journaling File Systems: The DualFS Case
A Novel Parallel Binary Counter Design with Parity Prediction and Error Detection Scheme
Reinforcement Learning-Based Resource Partitioning for Improving Responsiveness in Cloud Gaming
An Abstract Model of Behavior for Hardware Descriptions
Hybrid-Memcached: A Novel Approach for Memcached Persistence Optimization With Hybrid Memory
On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan
Fast Garbage Collection in Erasure-Coded Storage Clusters
Indexing Mapping Approach of Deriving the PM DFT Algorithms
A Holistic Approach Towards Intelligent Hotspot Prevention in Network-on-Chip-Based Multicores
LayeredTrees: Most Specific Prefix-Based Pipelined Design for On-Chip IP Address Lookups
Primary Processor and Data Storage Equipment for the Orbiting Astronomical Observatory
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation
On the Computation of Common Test Data for Broadside and Skewed-Load Tests
Coda: A Highly Available File System for a Distributed Workstation Environment
Linearity Testing and Realization of Sequential Machines
Application of Digital Computers to Solve Analytically a Class of Second-Order Non-linear Ordinary Differential Equations
Optimal Partitioning of Cache Memory
EaseCAM: An Energy and Storage Efficient TCAM-Based Router Architecture for IP Lookup
Improving Write Performance on Cross-Point RRAM Arrays by Leveraging Multidimensional Non-Uniformity of Cell Effective Voltage
New Systolic Architectures for Inversion and Division in GF(2^m)
Further Comments on "Synthesis of Symmetric Switching Functions Using Threshold Logic Networks" 1
A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits
An Algorithm to Design Finite Field Multipliers Using a Self-Dual Normal Basis
MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory
Subquadratic Space Complexity Binary Field Multiplier Using Double Polynomial Representation
APC: A Novel Memory Metric and Measurement Methodology for Modern Memory Systems
Design Space Exploration for Efficient Quantum Most-Significant Digit-First Arithmetic
Inverses of Linear Sequential Circuits
An Update Algorithm for Replicated Signaling Databases in Wireless and Advanced Intelligent Networks
Endurance-Aware Flash-Cache Management for Storage Servers
Algorithm-Based Fault Tolerance for FFT Networks
Optimal Algorithms for the Intersection and the Minimum Distance Problems Between Planar Polygons
Three-Dimensional Stacked Nanophotonic Network-on-Chip Architecture with Minimal Reconfiguration
Path-Dividing Based Scheduling Algorithm for Reducing Energy Consumption of Clustered VLIW Architectures
B73-7 Theory of Machines and Computations
Automated Test Generation for Debugging Multiple Bugs in Arithmetic Circuits
A Single Chip Parallel Multiplier by MOS Technology
R70-20 Sequential Boolean Equations
A digital voltage encoder
Computer Definitions [Guest Editorial]
Traffic Characterization Based Stochastic Modelling of Network-on-Chip
Fast Parallel-Prefix Modulo 2^n+1 Adders
Introduction to the Special Section on Energy Efficient Computing
Coexistence Wi-Fi MAC Design for Mitigating Interference Caused by Collocated Bluetooth
A Context-Awareness and Hardware-Friendly Sparse Matrix Multiplication Kernel for CNN Inference Acceleration
Single Multiscale-Symbol Error Correction Codes for Multiscale Storage Systems
Exploring Truss Maintenance in Fully Dynamic Graphs: A Mixed Structure-Based Approach
Performance Modeling and Evaluation of Circuit Switching Using Clos Networks
An Improved Vector-Reduction Method
Secure Broadcast Encryption With Reverse Firewalls on Corrupted Machines
Improving Reliability of a Sequential Machine by Error-Correcting State Assignments
Distance-2 Cyclic Chaining of Constant-Weight Codes
A Stochastic Syntax Analysis Procedure and Its Application to Pattern Classification
A Shared Memory Computer Display System
Database Computers - A Step Towards Data Utilities
Enhancing and Exploiting the Locality
Cooperative Vision Integration Through Data-Parallel Neural Computations
Towards Optimal Multi-Level Checkpointing
Modified Faddeeva Algorithm for Concurrent Execution of Linear Algebraic Operations
Fault-Tolerance of Dynamic-Full-Access Interconnection Networks
An Algorithm for Solving Boolean Equations
A Fast Algorithm for Testing Isomorphism of Permutation Networks
Exact Path Delay Fault Coverage Calculation of Partitioned Circuits
A Division Algorithm for a Digital Differential Analyzer
High-Performance In-Memory Bayesian Inference With Multi-Bit Ferroelectric FET
Slave Memories and Segmentation
On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults
An Application of Bayesian Decision Theory to Decentralized Control of Job Scheduling
A Systematic Methodology to Generate Decomposable and Responsive Power Models for CMPs
Analysis of Performability for Stochastic Models of Fault-Tolerant Systems
Control Speculation for Energy-Efficient Next-Generation Superscalar Processors
A New Systolic Architecture for Modular Division
Addressing, Routing, and Broadcasting in Hexagonal Mesh Multiprocessors
Learning Matrices and Their Applications
Optimized Synthesis of Concurrently Checked Controllers
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits
Ten Years of Computer Simulation
A Parallel Computer Organization and Mechanizations
Distortion Invariant Object Recognition in the Dynamic Link Architecture
High-Performance and Lightweight Transaction Support in Flash-Based SSDs
Byte Unidirectional Error Correcting and Detecting Codes
Location-Aided Flooding: An Energy-Efficient Data Dissemination Protocol for Wireless Sensor Networks
Adding Time to Synchronous Process Communications
Optimal VLSI Sorting with Reduced Number of Processors
An Efficient Fault Diagnosis Algorithm for Symmetric Multiple Processor Architectures
A New Parallel Algorithm for Time-Slot Assignment in Hierarchical Switching Systems
The Realization of Symmetric Switching Functions with Linear-Input Logical Elements
Sequential Decision-Making Device for Information-Processing Applications
On the Complete Convergence of Bordered Nets
A Computer for Solving Linear Simultaneous Equations Using the Residue Number System
Minimizing the Maximum Firewall Rule Set in a Network with Multiple Firewalls
A Pipeline Fast Fourier Transform
Tunable Floating-Point Adder
The Design of Totally Self-Checking TMR Fault-Tolerant Systems
On Complete Systems and Finite Automata
Supporting Demanding Hard-Real-Time Systems with STI
Self Synchronized Asynchronous Sequential Pass Transistor Circuits
Design and Evaluation of the Rollback Chip: Special Purpose Hardware for Time Warp
RV-CURE: A RISC-V Capability Architecture for Full Memory Safety
High Throughput Disk Scheduling with Fair Bandwidth Distribution
Improved Division by Invariant Integers
Optimal Curve Fitting With Piecewise Linear Functions
Design and Application of Optimal Velocity Filters in Seismic Exploration
Some Binary Output Sequence Properties of Deterministic Autonomous Finite-State Machines with Probabilistic Initialization
Design and Simulation of a Hybrid Architecture for Edge Computing in 5G and Beyond
Solution of Linear Inequalities
Minimization of Fuzzy Functions
Coverage in Wireless Ad Hoc Sensor Networks
Aliasing Probabilities for Feedback Signature Compression of Test Data
Approximation, Dimension Reduction, and Nonconvex Optimization Using Linear Superpositions of Gaussians
Distributed Parameter Vibration with Structural Damping and Noise Excitation
Parallel Modular Multiplication Using Variable Length Algorithms
New Fault Tolerant Techniques for Residue Number Systems
Estimation of Mutual Information in Two-Class Pattern Recognition
A New Design of In-Memory File System Based on File Virtual Address Framework
A Comprehensive Scan Test Cost Model to Optimize the Production of Very Large SoCs
Leader Election in Asynchronous Distributed Systems
Vectorization of the Calculation of a Moving Sum
Reconfigurable Computing Approach for Tate Pairing Cryptosystems over Binary Fields
Polymorphic Accelerators for Deep Neural Networks
A Novel Reordering Write Buffer to Improve Write Performance of Log-Structured File Systems
Decoder Reduction Approximation Scheme for Booth Multipliers
The Boolean Difference and Multiple Fault Analysis
Mixed Radix Reed-Muller Expansions
A Note on Fast Base Extension for Residue Number Systems with Three Moduli
String Searching Engine for Virus Scanning
Location of a Faulty Module in a Computing System
Carry-Save Representation Is Shift-Unsafe: The Problem and Its Solution
Introducing Safety Requirements Traceability Support in Model-Driven Development of Robotic Applications
An Information Theoretic Approach to Digital Fault Testing
Algorithm and Implementation Details for Complementary Error Function
Applications Considerations in the System Design of Highly Concurrent Multiprocessors
Performance Evaluation of the Slotted Ring Multiprocessor
Arithmetic Networks and Their Minimization Using a New Line of Elementary Units
Fault Containment in Cache Memories for TMR Redundant Processor Systems
Sequential Functions and Linear Sequential Machines
Efficient Online and Offline Testing of Embedded DRAMs
Eliminating Overflow for Large-Scale Mobility Databases in Cellular Telephone Networks
Fast Multipliers
Concurrent Detection of Control Flow Errors by Hybrid Signature Monitoring
Evaluation of the Amplitude Distribution of Quasi-Gaussian Signals Obtained From Pseudorandom Noise
Multiple Fault Detection in Combinational Circuits: Algorithms and Computational Results
Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test
Parallel Implementation of Multidimensional Transforms without Interprocessor Communication
Line (Block) Size Choice for CPU Cache Memories
Curve Segmentation by Relaxation Labeling
Simple Bounds on Serial Signature Analysis Aliasing for Random Testing
A Numerical Algorithm for Identifying Spread Functions of Shift-Invariant Imaging Systems
Compositional Model Checking of Concurrent Systems
On the Properties of Irredundant Logic Networks
Election in Asynchronous Complete Networks with Intermittent Link Failures
On the Augmented Data Manipulator Network in SIMD Environments
Modular Error Detection for Bit-Serial Multiplication
Efficient and Scalable FPGA Design of GF($2^m$2m) Inversion for Post-Quantum Cryptosystems
OSC: An Online Self-Configuring Big Data Framework for Optimization of QoS
Coding Analog Variables for Threshold Logic Discrimination
Application of Intensity-Modulated Ink Jets to Alphanumeric Printing Devices
A Readily Computable Decision Rule with Variable Dimensionality
NFRA: Generalized Network Flow-Based Resource Allocation for Hosting Centers
On the Assignment Problem of Arbitrary Process Systems to Heterogeneous Distributed Computer Systems
Hardware Verification
How to Launch a Powerful Side-Channel Collision Attack?
FileDAG: A Multi-Version Decentralized Storage Network Built on DAG-Based Blockchain
The Determination of Carry Propagation Length for Binary Addition
Performance Models of Timestamp-Ordering Concurrency Control Algorithms in Distributed Databases
Fast Hybrid Computer Implementation of the Dynostat Algorithm
Comparison of Reconfiguration Schemes for the C2SC MIN Operating in the Broadcast Mode
HIPED AP : Energy-Efficient Hardware Accelerators for Hidden Periodicity Detection
Analysis of Self-Stabilizing Clock Synchronization by Means of Stochastic Petri Nets
A Spanning Tree Carry Lookahead Adder
Complexity Based on Partitioning of Boolean Circuits and Their Relation to Multivalued Circuits
Some Results on a SRT Type Division Scheme
Interrupt Handling for Out-of-Order Execution Processors
Layer Assignment Problem for Three-Layer Routing
Stabilizing Communication Protocols
R70-16 Unate Cellular Logic
Building Survivable Services Using Redundancy and Adaptation
Comments on "A Computer Algorithm for Calculating the Product AB Modulo M"
Vector Space Theoretic Analysis of Additive Cellular Automata and Its Application for Pseudoexhaustive Test Pattern Generation
Serial Interfaces for Minicomputers
Arithmetic Interpolation Search for Alphabetic Tables
Comments on "Checking Experiments for Sequential Machines"
Diagnosis by Signature Analysis of Test Responses
nvramdisk: A Transactional Block Device Driver for Non-Volatile RAM
A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations
GREEN Cache: Exploiting the Disciplined Memory Model of OpenCL on GPUs
PermCNN: Energy-Efficient Convolutional Neural Network Hardware Architecture With Permuted Diagonal Structure
A Scalable Destination-Oriented MulticastProtocol with Incremental Deployability
Digital Interpolation of Discrete Images
An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories
Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis
STAR : An Efficient Coding Scheme for Correcting Triple Storage Node Failures
Directional Couplers as Microwave Logic
ECDR$^{2}$2: Error Corrector and Detector Relocation Router for Network-on-Chip
Band-Pass Quadrature Filters
The Effect of Operation Scheduling on the Performance of a Data Flow Computer
Functional Testing of Microprocessors
TOP: Towards Open & Predictable Heterogeneous SoCs
Bipartite Modular Multiplication Method
Logical Design of Analog-to-Digital Converters
Enabling Efficient Deep Learning on MCU With Transient Redundancy Elimination
Research and Application of General Information Measures Based on a Unified Model
Higher Radix Square Rooting
Efficient Double Bases for Scalar Multiplication
CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units
Minimal Negative Gate Networks
Parallel Signature Analyzers Using Hybrid Design of Their Linear Feedbacks
NV-Tree: A Consistent and Workload-Adaptive Tree Structure for Non-Volatile Memory
A Parallel Virtual Machine for Programs Composed of Abstract Data Types
Program Behavior and the Performance of Interleaved Memories
An Adaptive Procedure for Multiclass Pattern Classification
Automated Model-Based Testing of Role-Based Access Control Using Predicate/Transition Nets
AUV Surfacing Control With Adversarial Attack Against DLaaS Framework
MorphoSys : An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications
A Decomposition Approach for Balancing Large-Scale Acyclic Data Flow Graphs
Configurable-ECC: Architecting a Flexible ECC Scheme to Support Different Sized Accesses in High Bandwidth Memory Systems
New and Improved Methods to Analyze and Compute Double-Scalar Multiplications
Fast CRCs
Relay Essential Hazards
Multicategory Classification of Patterns Represented by High-Order Vectors of Multilevel Measurements
A Logical Reading System for Nonreturn-to-Zero Magnetic Recording
Multiple Fault Detection in Combinational Networks
Further Results on the Performance Evaluation of the Split Channel Reservation Multiple Access Protocol ATP-2 for Local Area Networks
GroPipe: A Grouped Pipeline Hybrid Parallel Method for Accelerating DCNNs Training
Pictorial Output with a Line Printer
High-Speed Multiplication Systems
Stress Effects on Thin-Film Parametrons
Efficient Server Provisioning and Offloading Policies for Internet Data Centers with Dynamic Load-Demand
A Note on an Adaptive Hypersphere Decision Boundary
Associative Nets: A Graph-Based Parallel Computing Net
An Incremental Computer
On k -Nearest Neighbor Voronoi Diagrams in the Plane
Some Notes on the Walsh Functions
Peer-Assisted On-Demand Streaming: Characterizing Demands and Optimizing Supplies
The Design of a Class of Fast Fourier Transform Computers
Guest Editors' introduction: Special section on optimizing the cloud
Waterwave: A GPU Memory Flow Engine for Concurrent DNN Training
A Feasible IP Traceback Framework through Dynamic Deterministic Packet Marking
Dynamic Sustainability Games for Renewable Resources-A Computational Approach
A Gracefully Degrading Massively Parallel System Using the BSP Model, and Its Evaluation
Comments on "Modular Replacement of Combinational Switching Networks"
Correction to "Methods Used in an Automatic Logic Design Generator (ALERT)"
An Approach to Gate Assignment and Module Placement for Printed Wiring Boards
Cellular Array for Extraction of Squares and Square Roots of Binary Numbers
BHerd: Accelerating Federated Learning by Selecting Beneficial Herd of Local Gradients
Speculatively Redundant Continued Logarithm Representation
RT-CRM: Real-Time Channel-Based Reflective Memory
Efficient Ancilla-Free Reversible and Quantum Circuits for the Hidden Weighted Bit Function
Promoting the Harmony between Sparsity and Regularity: A Relaxed Synchronous Architecture for Convolutional Neural Networks
Secure and Private RFID-Enabled Third-Party Supply Chain Systems
Spatial Planning: A Configuration Space Approach
A General Framework for Parameterized Schedulability Bound Analysis of Real-Time Systems
Efficient Testing of Optimal Time Adders
An Improved Min-Cut Algorithm for Partitioning VLSI Networks
A Computer Program for the Synthesis of Switching Circuits by Decomposition
Efficient Tridiagonal Solvers on Multicomputers
Detection of Denial-of-Service Attacks Based on Computer Vision Techniques
Guest Editorial: IEEE TC Special Issue On Smart Edge Computing and IoT
Crosstalk (Noise) in Digital Systems
QoE-Based Server Selection for Content Distribution Networks
A Cellular Threshold Array
Floating-Point Computation of Functions with Maximum Accuracy
A Multiprocessor Architecture for Two-Dimensional Digital Filters
On Range-Transformation Techniques for Division
Elementary Functions Hardware Implementation Using Constrained Piecewise-Polynomial Approximations
On the Correctness of Inside-Out Routing Algorithm
Error Detection and Correction in Content Addressable Memories by Using Bloom Filters
Cayley Graphs with Optimal Fault Tolerance
Bidirectional Multi-Constrained Routing Algorithms
Geometric Mapping of Switching Functions
On Division by Functional Iteration
PACE: A New Approach to Dynamic Voltage Scaling
Fourier Descriptors for Plane Closed Curves
A Performance and Cost Analysis of Applying Superscalar Method to Mainframe Computers
Design of Easily Testable Bit-Sliced Systems
Synthesis of Communication Protocols: Survey and Assessment
Testability Conditions for Bilateral Arrays of Combinational Cells
On the Choice of Smoothing Parameters for Parzen Estimators of Probability Density Functions
Stochastic High-Level Petri Nets and Applications
The Edge Flag Algorithm - A Fill Method for Raster Scan Displays
Performance of Parallel Branch-and Bound Algorithms
Comparison of Duplex and Triplex Memory Reliability
A Testable Design of Logic Circuits under Highly Observable Condition
A New CPU Availability Prediction Model for Time-Shared Systems
Quantum Secret Permutating Protocol
Evaluating High Performance Pattern Matching on the Automata Processor
Stochastic Model for the Browning-Bledsoe Pattern Recognition Scheme
A Dynamic Priority Assignement Technique for Streams with (m, k)-Firm Deadlines
Deleting Vertices to Bound Path Length
Evaluation of Maintenance Software in Real-Time Systems
Priority Assignment on Partitioned Multiprocessor Systems With Shared Resources
A Modification of Lee's Path Connection Algorithm
Iterative Local Solutions for Connected Dominating Set in Ad Hoc Wireless Networks
Response-Time Analysis of Engine Control Applications Under Fixed-Priority Scheduling
A Fast Z Transformation Algorithm for System Identification
A Binary Single-Key-Lock System for Access Control
Optimal Dyadic Models of Time-Invariant Systems
An Evaluation of Several Two-Summand Binary Adders
DRAM Refresh Mechanisms, Penalties, and Trade-Offs
Analog Multipliers and Squarers Using a Multigrid Modulator
A Digital Decoding Technique
Reducing the Computation Time in (Short Bit-Width) Two's Complement Multipliers
A digital computer for airborne control systems
Self-Dual Symmetric Switching Functions with a Certain a-Number Constraint
Uniform Shift Multiplication Algorithms Without Overflow
Method of Folding a Piecewise Polynomial Function in the Delta Function Integral Representation
AppATP: An Energy Conserving Adaptive Mobile-Cloud Transmission Protocol
A Systematic Methodology for Optimization of Applications Utilizing Concurrent Data Structures
Mobility-Aware Utility Maximization in Digital Twin-Enabled Serverless Edge Computing
Functional Microprogramming as a Logic Design Aid
A High-Speed Direct-Coupled Magnetic Memory Sense Amplifier Employing Tunnel-Diode Discriminators
VV-NET: A Versatile Network Architecture for Flexible Delay Guarantees in Real-Time Networks
Self-Checking Combinational Logic Binary Counters
A Note on Fast Cyclic Convolution
A Practical Data Classification Framework for Scalable and High Performance Chip-Multiprocessors
Safe Data Parallelism for General Streaming
Theory of Computer Addition and Overflows
The Performance of Parallel Prolog Programs
Joint Management of CPU and NVDIMM for Breaking Down the Great Memory Wall
A Serial Memory by Quantum-Dot Cellular Automata (QCA)
Comments on "Basic Properties and a Construction Method for Fail-Safe Logical Systems"
High-Performance FPGA Accelerator for SIKE
A Recognition Method Using Neighbor Dependence
Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption
Application of Digital Computers to Three-Dimensional Field Determination
An Oblivious Spanning Tree for Single-Sink Buy-at-Bulk in Low Doubling-Dimension Graphs
A Quantising Encoder
On the Twiddling Factors
Reducing Flash Memory Write Traffic by Exploiting a Few MBs of Capacitor-Powered Write Buffer Inside Solid-State Drives (SSDs)
Efficient Scheduling for Multi-Block Updates in Erasure Coding Based Storage Systems
Chronology of Computing Devices
Two Problems on Boolean Memories
An Efficient Parallel Algorithm for the Solution of Large Sparse Linear Matrix Equations
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
A Low-Power, High-Performance Speech Recognition Accelerator
Regular Ternary Logic Functions - Ternary Logic Functions Suitable for Treating Ambiguity
Karnaugh Map Method for Memristive and Spintronic Asymmetric Basis Logic Functions
Low-Storage Verifiable Data Streaming With Efficient Revocation Approach
High-Radix Generalized Hyperbolic CORDIC and Its Hardware Implementation
K-Way Bitonic Sort
A Relationship Between Output Symbol Occurrence Rate and Observability of Autonomous Machines
An Efficient Method of Computing Generalized Reed-Muller Expansions from Binary Decision Diagram
Fault Detection in Bilateral Arrays of Combinational Cells
Novel Test Pattern Generators for Pseudoexhaustive Testing
Design of an Error-Tolerance Scheme for Discrete Wavelet Transform in JPEG 2000 Encoder
VRBC: A Verifiable Redactable Blockchain With Efficient Query and Integrity Auditing