yusuke1997/dblp-id-title huggingface dataset:
Residual-Based Detections and Unified Architecture for Massive MIMO Uplink
Coefficient Elimination Algorithm for Low Energy Distributed Arithmetic DCT Architectures
Design and Implementation of a Joint Data Compression and Digital Watermarking System in an MPEG-2 Video Encoder
A Data-driven Approach for Reverse Engineering Electric Power Protocols
Special Issue: Dynamic Data-Driven Applications Systems (DDDAS) Concepts in Signal Processing
Reliability-Guaranteed Task Assignment and Scheduling for Heterogeneous Multiprocessors Considering Timing Constraint
Characterization of subthreshold MOS mismatch in transistors for VLSI systems
A Flexible Architecture for Modular Arithmetic Hardware Accelerators based on RNS
Automated Design Flow for Multi-Functional Dataflow-Based Platforms
Bayesian Sparse Topic Model
Fault-Tolerant Mesh-Based NoC with Router-Level Redundancy
A Hopfield Neural Classifier and Its FPGA Implementation for Identification of Symmetrically Structured DNA Motifs
DCT-Domain Embedded Memory Compression for Hybrid Video Coders
Efficient Object Detection Using Embedded Binarized Neural Networks
Systolic Algorithms and Architectures for High-Throughput Processing Applications
A Low-power and Low-complexity Baseband Processor for MIMO-OFDM WLAN Systems
A Real-Time Implementation of the Mobile WiMAX ARQ and Physical Layer
A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems
Special-purpose digital hardware for neural networks: An architectural survey
New Complexity Results on Array Contraction and Related Problems
VLSI Implementation of Computation Efficient Color Image Compression Scheme Based on Adaptive Decimation for Portable Device Application
One Instruction Set Computers for Image Processing
A Multimodal Hypovigilance Detection System Based on Fuzzy Logic and Transfer Learning
Hardware Multi-Threaded System for High-Performance JPEG Decoding
Design and Implementation of Flexible Resampling Mechanism for High-Speed Parallel Particle Filters
Architecture and Evaluation of an Asynchronous Array of Simple Processors
Research and Design on Cognitive Computing Framework for Predicting Judicial Decisions
Subspace Identification of Closed-Loop EIV System Based on Instrumental Variables Using Orthoprojection
Correction to: Joint Motion Compensation and MC-Reused Spatial Error Concealment on Hardware Architecture Design
Missing Data Imputation for Time-Frequency Representations of Audio Signals
Non-parametric Blind Spectrum Sensing Based on Censored Observations for Cognitive radio
Convex Optimization-Based Bit Allocation for Video Coding
Downward Facing Directional Antennas for Ultra-High Density Indoor Small Cells
Compression of Deep Neural Networks with Structured Sparse Ternary Coding
A Regularized Clustering Algorithm Based on Calculus of Variations
Measuring and Modeling the Power Consumption of Energy-Efficient FPGA Coprocessors for GEMM and FFT
Correlated Noise: How it Breaks NMF, and What to Do About it
A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture
Tunable Mismatch Shaping for Quadrature Bandpass Delta-Sigma Data Converters
Implementation, Scheduling, and Adaptation of Partial Expansion Graphs on Multicore Platforms
SIGMA System: A Multi-OS Environment for Embedded Systems
Quantization Index Modulation Methods for Digital Watermarking and Information Embedding of Multimedia
Novel Pipelined Architecture for Efficient Evaluation of the Square Root Using a Modified Non-Restoring Algorithm
Fully Complex Multi-Layer Perceptron Network for Nonlinear Signal Processing
A Fast Modified CORDIC - Implementation of Radial Basis Neural Networks
Parallel video signal processor configuration based on overlap-save technique and its LSI processor element: VISP
Clock Skew Minimization in Multiple Dynamic Supply Voltage with Adjustable Delay Buffers Restriction
Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis
Quality Map Thresholding for De-noising of Complex-Valued fMRI Data and Its Application to ICA of fMRI
An Internet of Agents Architecture for Training and Deployment of Deep Convolutional Models
Compositional, Dynamic Cache Management for Embedded Chip Multiprocessors
Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management
FPGA-based System for Real-Time Video Texture Analysis
A Multi-Channel Wireless Active Noise Control Headphone With Coherence-Based Weight Determination Algorithm
Robust Adaptive Microphone Array with Mainlobe and Response Ripple Control
FPGA Implementation of Cross Virtual Concatenation Transmitter/ Receiver for Data Transmission over Next Generation SDH Systems
The Negative Two's Complement Number System
An Efficient Architecture for a Lifted 2D Biorthogonal DWT
Speech Enhancement Using Perceptual Wavelet Packet Decomposition and Teager Energy Operator
High Performance Clock Distribution Networks
Special Issue on Machine Learning for Signal Processing
A Practical FPGA-Based Architecture for Arbitrary-Ratio Sample Rate Conversion
Energy-performance Exploration of a CGA-based SDR Processor
Guest Editorial: Machine Learning for Signal Processing
A Novel Cotransformation for LNS Subtraction
SVD-updating using orthonormal mu-rotations
Joint Motion Compensation and MC-Reused Spatial Error Concealment on Hardware Architecture Design
A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception
Detection of Transient Signals in Lung Sounds: Local Approach Using a Markovian Tree with Frequency Selectivity
Low Area High-speed Hardware Implementation of Fast FIR Algorithm for Intelligent Signal Processing application in Complex Industrial Systems
Real-Time Embedded Motion Detection via Neural Response Mixture Modeling
Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices
Low-Area/Power Parallel FIR Digital Filter Implementations
Model-Driven Approach for Early Power-Aware Design Space Exploration of Embedded Systems
Scalable VLSI implementations for neural networks
An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology
Advanced RNN Based NARMA Predictors
Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems
Hardware Implementation of the Joint Precoding Sub-System and MIMO Detection Preprocessor in IEEE 802.11n/ac WLAN
Guest Editorial for Special Issue on Machine Learning for Signal Processing
A general-purpose signal processor architecture for neurocomputing and preprocessing applications
Mapping Parameterized Cyclo-static Dataflow Graphs onto Configurable Hardware
Special Issue on "Wireless Sensor Networks"
A VLSI architecture for the real time computation of discrete trigonometric transforms
Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers
A systolic algorithm and architecture for solving sets of linear equations with multi-band coefficient matrix
Detection of Clustered Microcalcifications on Mammograms Using Surrounding Region Dependence Method and Artificial Neural Network
Focused-Region Segmentation for Refocusing Images from Light Fields
Deployment of Run-Time Reconfigurable Hardware Coprocessors Into Compute-Intensive Embedded Applications
Quantitative measurements of FPGA utility in special and general purpose processors
Hardware Efficient Double Diamond Search Block Matching Algorithm for Fast Video Motion Estimation
Anonymizing Big Data Streams Using In-memory Processing: A Novel Model Based on One-time Clustering
Beam Tracking Particle Filter for Hybrid Beamforming and Precoding Systems
Improvements in IITG Assamese Spoken Query System: Background Noise Suppression and Alternate Acoustic Modeling
Real-time high-energy physics applications on DECPeRLe-1 programmable active memory
A Multimodal Approach to Communicative Interactivity Classification
Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors
An Algorithm-Hardware-System Approach to VLIW Multimedia Processors
A Principal Component Clustering Approach to Object-Oriented Motion Segmentation and Estimation
A New Variable-Regularized Transform-Domain NLMS Algorithm with Automatic Step-Size Selection for Adaptive System Identification/ Filtering
Symbolic Mapping of Loop Programs onto Processor Arrays
Wavelet-based Burst Event Detection and Localization in Water Distribution Systems
Analog VLSI for robot path planning
A Speech Recognition IC Using Hidden Markov Models with Continuous Observation Densities
Research on Context-Awareness Mobile Tourism E-Commerce Personalized Recommendation Model
Exploring Domain-Specific Architectures for Energy-Efficient Wearable Computing
A Hardware Acceleration Platform for Digital Holographic Imaging
Automated Breast Cancer Diagnosis Based on GVF-Snake Segmentation, Wavelet Features Extraction and Fuzzy Classification
VLSI Photonic Ring Multicomputer Interconnect: Architecture and Signal Processing Performance
Systolic implementations of up/down-dating cholesky factorization using vectorized Gram-Schmidt pseudo orthoganalization
A New Ontology Convolutional Neural Network for Extorting Essential Elements in Video Mining
AEx: Automated High-Level Synthesis of Compiler Programmable Co-Processors
A High Quality Depth Map Upsampling Method Robust to Misalignment of Depth and Color Boundaries
Overcomplete Independent Component Analysis via Linearly Constrained Minimum Variance Spatial Filtering
An optimal methodology for synthesis of DSP multichip architectures
A FAST Hardware Decoder Optimized for Template Features to Obtain Order Book Data in Low Latency
Systolic algorithms for some scheduling and graph problems
Trade-Off Analysis of a Low-Power Image Coding Algorithm
Robust Downlink Beamforming for Multiuser SWIPT Systems with Imperfect CSI
Trends and Challenges of Processing Measurements from Wearable Devices Intended for Epileptic Seizure Prediction
An Efficient Gradient-based Approach to Optimizing Average Precision Through Maximal Figure-of-Merit Learning
Decision-Directed Channel Estimation Implementation for Spectral Efficiency Improvement in Mobile MIMO-OFDM
Flexible Implementation of a WCDMA Rake Receiver
Sound Source DOA Estimation and Localization in Noisy Reverberant Environments Using Least-Squares Support Vector Machines
Ultrasound Image Sequence Registration and its Application for Thyroid Nodular Disease
Special Issue on Efficiency in Wireless Software-Defined Radio Systems
Wideband Beamspace Processing Using Orthogonal Modal Beamformers
A Configurable Architecture for Fast Moments Computation
A New Neuro-Fuzzy Classifier with Application to On-Line Face Detection and Recognition
Intra Prediction for the Hardware H.264/AVC High Profile Encoder
Fast and Accurate Edge Computing Energy Modeling and DVFS Implementation in GEM5 Using System Call Emulation Mode
On MSE Exit Chart Analysis and Real Time DSP Implementation for Iterative (Turbo) Detection
Generalized I-vector Representation with Phonetic Tokenizations and Tandem Features for both Text Independent and Text Dependent Speaker Verification
A Reconfigurable Index FLASH Memory tailored to Seed-Based Genomic Sequence Comparison Algorithms
On Stability of Cellular Neural Networks
Towards Automatic Creation of Realistic Anthropomorphic Models for Realtime 3D Telecommunication
Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System
A resource-efficient reconfiguration algorithm of VLSI 2-D processor arrays
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic
A Compact DSP Core with Static Floating-Point Arithmetic
Compute and Memory Efficient Universal Sound Source Separation
Rate Control Algorithms for Non-Embedded Wavelet-Based Image Coding
Survey on Video Colorization: Concepts, Methods and Applications
Algorithms & Architectures at the Boundary of Signal Processing & Machine Learning
DirectSVM: A Simple Support Vector Machine Perceptron
Approximate Signal Processing
Real-Time Speaker Verification System Implemented on Reconfigurable Hardware
Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications
Support OpenCL 2.0 Compiler on LLVM for PTX Simulators
High-Level Cache Modeling for 2-D Discrete Wavelet Transform Implementations
High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices
Implementation of lattice gases using FPGAs
Visual tracking based on depth cross-correlation and feature alignment
Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders
Palm-Dorsal Vein Recognition Method Based on Histogram of Local Gabor Phase XOR Pattern with Second Identification
Prediction of Bus Passenger Traffic using Gaussian Process Regression
AI and Conventional Methods for UCT Projection Data Estimation
A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications
Miniaturized CMOS Imaging Module with Real-time DSP Technology for Endoscope and Laryngoscope Applications
Modeling of Block-Based DSP Systems
Models for Architectural Power and Power Grid Noise Analysis on Data Bus
An Architecture for Asymmetric Numeral Systems Entropy Decoder - A Comparison with a Canonical Huffman Decoder
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
A Novel Smart Contract Reentrancy Vulnerability Detection Model based on BiGAS
A Nonlinear Wave Metric and its CNN Implementation for Object Classification
The Harmonized Parabolic Synthesis Methodology for Hardware Efficient Function Generation with Full Error Control
A Novel Kernel Correlation Coefficient with Robustness Against Nonlinear Attenuation and Impulsive Noise
A 16 × 8 Hybrid Beamforming and Precoding Processor for 2D Planar Antenna Array in mmWave MIMO Systems
Animated Talking Head with Personalized 3D Head Model
GPU-Based Iterative Medical CT Image Reconstructions
Frame-based Programming, Stream-Based Processing for Medical Image Processing Applications
Implementation of the PointPillars Network for 3D Object Detection in Reprogrammable Heterogeneous Devices Using FINN
Multimodality Image Registration Using Spatial Procrustes Analysis and Modified Conditional Entropy
Non-overlapping Distributed Tracking System Utilizing Particle Filter
CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks
A Compute Cache System for Signal Processing Applications
The CAM-Brain Machine (CBM): Real Time Evolution and Update of a 75 Million Neuron FPGA-Based Artificial Brain
A LTE Receiver Framework Using GNU Radio
Guest Editorial: Special Issue on Signal Processing Systems: Part I
SAPT: Saliency Augmentation and Unsupervised Pre-trained Model Fusion for Few-Shot Object Detection
Nonlinear transformations for high level regular array ASIC synthesis
Color Correction for Multi-view Images Using Relative Luminance and Chrominance Mapping Curves
Pipelined Architecture for Additive Range Reduction
Exploiting Tightly-Coupled Cores
Lightweight Stereo Image Super-Resolution Using modified Parallax Attention
A Framework for High Level Estimations of Signal Processing VLSI Implementations
Hardware Emulation of Wideband Correlated Multiple-Input Multiple-Output Fading Channels
Models for Audiovisual Fusion in a Noisy-Vowel Recognition Task
Accelerating AI Applications with Sparse Matrix Compression in Halide
FPGA-Based Soft-Core Processors for Image Processing Applications
Novel Digital Signal Processing Unit Using New Digital Baseline Wander Corrector for Fast Ethernet
AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations
Superpositional HMM-Based Intonation Synthesis Using a Functional F0 Model
Detection of Structural Features in Biological Signals
Full-Hardware Architectures for Data-Dependent Superimposed Training Channel Estimation
Design of Two Channel Biorthogonal Filterbanks using Euler Frobenius Polynomial
Gradient Adaptive Algorithms for Contrast-Based Blind Deconvolution
Real-time Visual Tracker by Stream Processing
Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes
Worst-Case Communication Delay Analysis for NoC-Based Many-Cores Using a Limited Migrative Model
A Meta-Heuristic Optimization Based Less Imperceptible Adversarial Attack on Gait Based Surveillance Systems
DLOOPT: An Optimization Assistant on AutoTVM for Deep Learning Operators
Complex +/-1 Multiplier Based on Signed-Binary Transformations
The PAPIA system
Hardware Implementation of Successive-Cancellation Decoders for Polar Codes
LightSpMV: Faster CUDA-Compatible Sparse Matrix-Vector Multiplication Using Compressed Sparse Rows
Canonic Composite Length Real-Valued FFT
Low-complexity, Multi Sub-band Digital Predistortion - Novel Algorithms and SDR Verification
Design of 100 µW Wireless Sensor Nodes for Biomedical Monitoring
An Approach to T&E of Military SDR Platforms and Waveforms: the LANCERS Lab
Multilevel Reverse-Carry Addition: Single and Dual Adders
Sparse Coding with Anomaly Detection
Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization
Requirements for Interfacing IP-Components in Re-configurable Platforms
A low-power high performance polygon renderer for computer graphics
Electromagnetic Compatibility Test Signal Prediction Method Based on LSTM Network
OpenVVC Decoder Parameterized and Interfaced Synchronous Dataflow (PiSDF) Model: Tile Based Parallelism
Carry-save architectures for high-speed digital signal processing
Histopathological Image Analysis Using Model-Based Intermediate Representations and Color Texture: Follicular Lymphoma Grading
The TaPaSCo Open-Source Toolflow
Adaptive Preconditioned Iterative Linear Detection and Architecture for Massive MU-MIMO Uplink
An Efficient Design of H.264 Inter Interpolator with Bandwidth Optimization
An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor
Erratum to: Parabolic Motion-Vector Re-estimation Algorithm for Compressed Video Downscaling
Boosting Proximal Dental Caries Detection via Combination of Variational Methods and Convolutional Neural Network
Editorial Note: Signal Processing Systems
Guest Editorial: Signal Processing for Wireless Communication Systems
In Vivo Short Echo Time Localized 1 H MRS of the Rat Brain at 7 T: Influence of Two Strategies of Background-accommodation on the Metabolite Concentration Estimation using QUEST
Modeling MPEG Coded Video Traffic by Markov-Modulated Self-Similar Processes
Very-High Radix CORDIC Rotation Based on Selection by Rounding
Transposed-Memory Free Implementation for Cost-Effective 2D-DCT Processor
An Improved Boundary Uncertainty-Based Estimation for Classifier Evaluation
A Parallel VLSI Video/Communication Controller
Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System
Algorithmic-level Specification and Characterization of Embedded Multimedia Applications with Design Trotter
Special Issue on Increasing Flexibility in Wireless Software Defined Radio Systems
Reproducibility of Laplacian Wall Thickness Measurements of the Gallbladder with Varying CT Slice Thickness
Correction to: Journal of Signal Processing Systems, Volume 91, issue 10
A KNN-Scoring Based Core-Growing Approach to Cluster Analysis
Parallel Memory Accessing for FFT Architectures
The Symmetric Table Addition Method for Accurate Function Approximation
Image Multi-human Behavior Analysis Based on Low Rank Texture Direction
Energy Efficient Multi-User Millimeter Wave MIMO Systems Using Tree Search Hybrid Precoding and Few-Bit ADCs
Constrained Adaptive Linear Multiuser Detection Schemes
POWER-Area-Performance Characteristics of FPGA-based Sigma-Delta FIR Filters
Design a Low-Power H.264/AVC Baseline Decoder at All Abstraction Levels - A Showcase
Automatic Generation of Modular Time-Space Mappings and Data Alignments
A Cooperative Learning Scheme for Interactive Video Search
Power Efficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital Communications
Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System
Software Defined Radio Implementation of a Digital Self-interference Cancellation Method for Inband Full-Duplex Radio Using Mobile Processors
An expandable column fft architecture using circuit switching networks
A Cross-Layer Adaptive Modulation and Coding Scheme for Energy Efficient Software Defined Radio
A Multi-Shared Register File Structure for VLIW Processors
Design of Reconfigurable FRM Channelizer using Resource Shared Non-maximally Decimated Masking Filters
Calibration of Abstract Performance Models for System-Level Design Space Exploration
Using Graphics Processing Units in an LTE Base Station
Automatic Assessment of Pathological Voice Quality Using Multidimensional Acoustic Analysis Based on the GRBAS Scale
Text-Informed Audio Source Separation. Example-Based Approach Using Non-Negative Matrix Partial Co-Factorization
ULE-Net: Unsupervised Low-Light Enhancement without Paired Data
Second Order Nonstationary Source Separation
Architecture Concepts for Multimedia Signal Processing
Early Termination of Intra Mode Decision Based on Most Probable Mode and SATD for H.264/AVC encoding
Highly Parallelable Bidimensional Median Filter for Modern Parallel Programming Models
A Software-Hardware Co-Implementation of MPEG-4 Advanced Video Coding (AVC) Decoder with Block Level Pipelining
An Integrated Systolic Array Design for Video Compression
Effective Parametric Estimation of Non-Gaussian Autoregressive Moving Average Processes Exhibiting Noise with Impulses
Reconfigurable Antenna and Dynamic Spectrum Access Algorithm: Integration in a Cognitive Radio Platform for Reliable Communications
MB-based Decoder Buffer Reduction for Multi-view Video Coding
Efficient Partitioning of Algorithms for Long Convolutions and their Mapping onto Architectures
Performance of NLMS-based Parallel Interference Cancellation (PIC) For Up-Link CDMA Systems
A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption
A Fault Diagnosis Method of Rotor System Based on Parallel Convolutional Neural Network Architecture with Attention Mechanism
Hardware-Software Implementation of a Sensor Network for City Traffic Monitoring Using the FPGA- and ASIC-Based Sensor Nodes
Second Order Taylor Polyphase Reconstruction of Periodic-Nonuniform Samples in Time-Interleaved ADCs
Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing
Real-time Stereo Face Recognition by Fusing Appearance and Depth Fisherfaces
Optimization of the Adaptive Computationally-Scalable Motion Estimation and Compensation for the Hardware H.264/AVC Encoder
Mapping dynamic programming onto a linear systolic array
Analyzing the Performance-Hardware Trade-off of an ASIP-based SIFT Feature Extraction
AIGCN: Attack Intention Detection for Power System Using Graph Convolutional Networks
Signal Processing Techniques for 6G
Evolutionary Algorithms for Instruction Scheduling, Operation Merging, and Register Allocation in VLIW Compilers
GPU Accelerated Belief Propagation Decoding of Non-Binary LDPC Codes with Parallel and Sequential Scheduling
Tracking Forecast Memories for Stochastic Decoding
Robust Channel Estimation and Multiuser Detection for MC-CDMA Systems Under Narrowband Interference
Spectrum Occupancy Statistics and Time Series Models for Cognitive Radio
Prediction of Soil Fertility Change Trend Using a Stochastic Petri Net
Gaussian Noise Filtering from ECG by Wiener Filter and Ensemble Empirical Mode Decomposition
Design and Synthesis of a Multiprocessor System-on-Chip Architecture for Real-Time Biomedical Signal Processing in Gamma Cameras
Implementation of a High-Speed MIMO Soft-Output Symbol Detector for Software Defined Radio
Computational Complexity Reduction for Volumetric Cardiac Deformation Recovery
High throughput VLSI DSP using replicated finite rings
Robust and Efficient Pattern Classification using Large Geometric Margin Minimum Classification Error Training
Data Allocation with Minimum Cost under Guaranteed Probability for Multiple Types of Memories
A case for digit serial VLSI signal processors