yusuke1997/dblp-id-title huggingface dataset:
Systolic s²-Way Merge Sort is Optimal
On Routability for FPGAs under Faulty Conditions
Optimal and Efficient Probabilistic Distributed Diagnosis Schemes
Synthesis of Hazard-Free Asynchronous Circuits Based on Characteristic Graph
Translation of a DDL Digital System Specification to Boolean Equations
State Assignments in Combinational Networks
How to Make a Correct Multiprocess Program Execute Correctly on a Multiprocessor
A Note on the Interruption of Extended Core Storage Transfers
Reliability of an Air Defense Computing System: Marginal Checking and Maintenance Programming
Shared Block Contention in a Cache Coherence Protocol
Logically Micro-Programmed Computers
Theory and Applications of Cellular Automata in Cryptography
Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing Joint Special Section on Innovation in Reconfigurable Computing Fabrics from Devices to Architectures
Minimizing the Computation Time for Using the Technique of Sectioning for Digital Filtering of Pictures
Towards Accurate Statistical Analysis of Security Margins: New Searching Strategies for Differential Attacks
New Hybrid Fault Models for Asynchronous Approximate Agreement
Algorithmic Mapping of Neural Network Models onto Parallel SIMD Machines
EaD: ECC-Assisted Deduplication With High Performance and Low Memory Overhead for Ultra-Low Latency Flash Storage
Performance Analysis of Single Stage Interconnection Networks
Bibliography on Switching Circuits and Logical Algebra
An Analysis of a Reliability Model for Repairable Fault-Tolerant Systems
Comments on "Fault Testing and Diagnosis in Combinational Digital Circuits"
A New Approach to Permanent Memory
Hybrid Load-Value Predictors
Strum: Structured Microprogram Development System for Correct Firmware
Further Comments on "Closure Partition Method for Minimizing Incomplete Sequential Machines"
On Equivalence of State Assignments
On Causal Broadcasting with Positive Acknowledgments and Bounded-Length Counters
Workload-Efficient Deadline and Period Assignment for Maintaining Temporal Consistency under EDF
Optimal Task Placement with QoS Constraints in Geo-Distributed Data Centers Using DVFS
Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines
Specification-Driven Conformance Checking for Virtual/Silicon Devices Using Mutation Testing
On the Accuracy of Operational Amplifiers Utilizing Controlled Superconductors
Modularized Morphing of Deep Convolutional Neural Networks: A Graph Approach
BLAKE-512-Based 128-Bit CCA2 Secure Timing Attack Resistant McEliece Cryptoprocessor
Configuration of Locally Spared Arrays in the Presence of Multiple Fault Types
A Characterization and Analysis of Parallel Processor Interconnection Networks
An Efficient Predicate Encryption with Constant Pairing Computations and Minimum Costs
R70-24 A Procedure for Selecting Diagnostic Tests
DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs
Test Point Insertion with Control Points Driven by Existing Functional Flip-Flops
Measuring Concavity on a Rectangular Mosaic
On Practical Discrete Gaussian Samplers for Lattice-Based Cryptography
A Tabular Method for the Synthesis of Multithreshold Threshold Elements
Secure Memory Accesses on Networks-on-Chip
Deferring Real-Time Traffic for Improved Non-Real-Time Communication in FDDI Networks
Correction to "Two-Level Correlation of an Analog Computer"
Generating fractal-like surfaces on general purpose mesh-connected computers
On Mapping Algorithms to Linear and Fault-Tolerant Systolic Arrays
A Study of Data Interlock in Computational Networks for Sparse Matrix Multiplication
A Special-Purpose Computer for Digital Signal Processing
Ferromagnetic Wire Memory
Probabilistic Miss Equations: Evaluating Memory Hierarchy Performance
Efficient Online Self-Checking Modulo 2^n+1 Multiplier Design
Mesh Connected Computers with Fixed and Reconfigurable Buses: Packet Routing and Sorting
A Transistorized Digital Analog Converter with Ac Amplification
On a Homomorphism of the de Bruijn Graph and its Applications to the Design of Feedback Shift Registers
A Proximal Iteratively Reweighted Approach for Efficient Network Sparsification
Multibit Correcting Data Interface for Fault-Tolerant Systems
CACC: A Cooperative Approachto Cache Consistency in WMNs
Thread Criticality Assisted Replication and Migration for Chip Multiprocessor Caches
A Recursive Partitioning Decision Rule for Nonparametric Classification
On the Extraction of Pattern Features from Imperfectly Identified Samples
A Canonical Bit-Sequential Multiplier
Multimedia File Allocation on VC Networks Using Multipath Routing
Whirl Decomposition of Stochastic Systems
Computer Simulation of Pulse Propagation Through a Periodic Loaded Transmission Line
Differential Fault Attack on Kreyvium & FLIP
Parallel Regognition and Parsing on the Hypercube
A Radix-4FFT Using Complex RNS Arithmetic
Comments on "Can Redundancy and Masking Improve the Performance of Synchronizers?"
Efficient Design Diversity Estimation for Combinational Circuits
Comment on "An Electronic Generator of Random Numbers
Efficient Software Implementation of Ring-LWE Encryption on IoT Processors
Bound Computation of Dependability and Performance Measures
Note on Binary Input-Binary Output Finite-Memory Sequential Machines
An Analysis of Cache Performance of Multimedia Applications
High-Performance Tensor Learning Primitives Using GPU Tensor Cores
Sequential Diagnosability is Co-NP Complete
A Synthesizing Method for Large Parallel Counters with a Network of Smaller Ones
On Combining Temporal Partitioning and Sharing of Functional Units in Compilation for Reconfigurable Architectures
The Size of Reduced OBDD's and Optimal Read-Once Branching Programs for Almost All Boolean Functions
Emulation of a FMA and Correctly Rounded Sums: Proved Algorithms Using Rounding to Odd
Enabling Large-Scale Simulation of CAM on the Sunway TaihuLight Supercomputer
Finite Field Arithmetic on an Array Processor
Mesh-Connected Computers with Broadcasting
R70-17 Asynchronous Sequential Circuits with Feedback
The Anticipatory Control of a Cyclically Permutable Memory
Implementation of FFT Structures Using the Residue Number System
Generalized Integration on the Analog Computer
Continuous Models for Communication Density Constraints on Multiprocessor Performance
An Upper Bound on Expected Clock Skew in Synchronous Systems
An Adaptive Hierarchical Routing Protocol
On the Reliability of FeFET On-Chip Memory
The Well-Connected Processor Array
BIRDS: A Bare-Metal Recovery Systemfor Instant Restoration of Data Services
Bit-Parallel Polynomial Basis Multiplier for New Classes of Finite Fields
Conditional Diagnosability of Alternating Group Graphs
Adaptive Unanimous Voting (UV) Scheme for Distributed Self-Diagnosis
Computational Geometry on a Systolic Chip
Pseudonoise with Arbitrary Amplitude Distribution-Part I: Theory
Fault-Tolerant Rearrangeable Permutation Network
A Remark on Uniform Distribution
Comparison of Some Classification Techniques
Diagnosis and Repair of Memory with Coupling Faults
On Augmenting Trace Cache for High-Bandwidth Value Prediction
On the Number of Distinct State Assignments for a Sequential Machine
Vector Computer Memory Bank Contention
Fast Computational Techniques for Pseudoinverse and Wiener Image Restoration
The Design and Analysis of BucketSort for Bubble Memory Secondary Storage
On Designing Protocols for Noncooperative, Multiradio Channel Assignment in Multiple Collision Domains
The Reliability of Single-Error Protected Computer Memories
Topological Embedding into WDM Optical Passive Star Networks with Tunable Transmitters
Guest Editorial: IEEE Transactions on Computer, Special Issue on Hardware Security
Sandbox Computing: A Data Privacy Trusted Sharing Paradigm Via Blockchain and Federated Learning
An Empirical Study of Task Switching Locality in MVS
Configurable XOR Hash Functions for Banked Scratchpad Memories in GPUs
Near-Memory Caching for Improved Energy Consumption
Affine Modeling of Program Traces
A Lightweight Virtualization Solution for Android Devices
VLSI Array Design Under Constraint of Limited I/O Bandwidth
Parallel AES Encryption Engines for Many-Core Processor Arrays
Some Results of Amplitude Distribution Experiments on Shift Register Generated Pseudo-Random Noise
ADir_pNB: A Cost-Effective Way to Implement Full Map Directory-Based Cache Coherence Protocols
A Coding Approach for Detection of Tampering in Write-Once Optical Disks
Designing a Resilient L1 Cache Architecture to Process Variation-Induced Access-Time Failures
Fault Equivalence in Combinational Logic Networks
Application of the Karhunen-Loève Expansion to Feature Selection and Ordering
Formal Verification Using Edge-Valued Binary Decision Diagrams
Optimizing Structured-Sparse Matrix Multiplication in RISC-V Vector Processors
Upper Bounds on Walsh Transforms
On Dependability Evaluation of Mesh-Connected Processors
A Multilevel Approach to Sequential Detection of Pictorial Features
Detecting Outlier Machine Instances Through Gaussian Mixture Variational Autoencoder With One Dimensional CNN
Some algebraic properties of multi-threshold functions
Exploiting In-Memory and On-Disk Redundancy to Conserve Energy in Storage Systems
The Simulation of Variable Delay
Hardware-Efficient Realization of Prime-Length DCT Based on Distributed Arithmetic
Efficient Implementation of Cryptographically Useful 'Large' Boolean Functions
A Multiaccess Frame Buffer Architecture
Comments on "The Extraction of Pattern Features from Imperfectly Identified Samples"
Decomposition of Polygons Into Simpler Components: Feature Generation for Syntactic Pattern Recognition
On Input/Output Speedup in Tightly Coupled Multiprocessors
Analytical Modeling of Wormhole-Routed k-Ary n-Cubes in the Presence of Hot-Spot Traffic
On the Asymptotic Improvement in the Out- come of Supervised Learning Provided by Additional Nonsupervised Learning
A Small Coincident-Current Magnetic Memory
A Note on the Linear Transformation Method for Systolic Array Design
A Hardwired Generalized Algorithm for Generating the Logarithm Base- k by Iteration
Performance of Operational Amplifiers With Electronic Mode Switching
Discussion of Some Flaws in the Classical Theory of Two-Level Minimization of Multiple-Output Switching Networks
A Detailed Historical and Statistical Analysis of the Influence of Hardware Artifacts on SPEC Integer Benchmark Performance
IOPS: A Unified SpMM Accelerator Based on Inner-Outer-Hybrid Product
A New Technique for the Fast Minimization of Switching Functions
The Implementation of Fast Radix 2 Transforms on Array Processors
A Generalized RNS Mclaughlin Modular Multiplication with Non-Coprime Moduli Sets
Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis
Scaling Up the Atlas Chip-Multiprocessor
A Programmed Algorithm for Designing Multifont Character Recognition Logics
Exhaustive Test Pattern Generation Using Cyclic Codes
A computer for flaw plotting
Cacomp: A Cloud-Assisted Collaborative Deep Learning Compiler Framework for DNN Tasks on Edge
On a Pin Versus Block Relationship For Partitions of Logic Graphs
Parallel Decoding Cyclic Burst Error Correcting Codes
Minimization Algorithms for Multiple-Valued Programmable Logic Arrays
A Boolean Neural Network Approach for the Traveling Salesman Problem
Connectivity Considerations of Graphs Representing Discrete Sequential Systems
Fast State Minimization of Incompletely Specified Sequential Machines
BKM: A New Hardware Algorithm for Complex Elementary Functions
Networks Composed of Ternary Majority Elements
Identity-Based Encryption with Outsourced Revocation in Cloud Computing
SPAR: A New Architecture for Large Finite Element Computations
Representational and Denotational Semantics of Digital Systems
Sim-D: A SIMD Accelerator for Hard Real-Time Systems
A Magnetically Scanned Magnetic Tape Transducer
Performance Modeling of Hierarchical Crossbar-Based Multicomputer Systems
A Method for the Design of Pattern Recognition Logic
Benchmarking Quantum(-Inspired) Annealing Hardware on Practical Use Cases
On Reducing Data Synchronization in Multiprocessed Loops
Optimal Joining of Compacted Cells
The Design of a General-Purpose Microprogam-Controlled Computer with Elementary Structure
Architectural Supports for Block Ciphers in a RISC CPU Core by Instruction Overloading
Inessentiality in Minimal Networks and Formulas
A VLSI Implementation of the Simplex Algorithm
Incomplete Hypercubes
A Data Structure for Parallel L/U Decomposition
Two Complementary Approaches for Microcode Bit Optimization
Minimal Redundant Logic for High Reliability and Irredundant Testability
Self-Timed Carry-Lookahead Adders
Power Control for Crossbar-Based Input-Queued Switches
A Geometric Synthesis Method of Three-Input Majority Logic Networks
Improved n-Term Karatsuba-Like Formulas in GF(2)
The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors
A Profit Maximization Scheme with Guaranteed Quality of Service in Cloud Computing
Recognition of Waveforms Using Autoregressive Feature Extraction
Scheduling Weakly Consistent C Concurrency for Reconfigurable Hardware
Uncertainty, Energy, and Multiple-Valued Logics
Optimal Parallel Routing in Star Networks
A Measure of Quality for n-Detection Test Sets
Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring
Minimization of Linear Sequential Machines
Optimization of Pulse and Digital Circuits by Use of the Lagrange Multiplier Technique
Fault Location Techniques for Distributed Control Interconnection Networks
Synthesizing Robust Data STructures - An Introduction
Silent Stores and Store Value Locality
On the Problem of Finding d, t, r, and j Type Partition Pairs of a Sequential Machine
Performance/Reliability-Aware Resource Management for Many-Cores in Dark Silicon Era
New Results and Techniques in Resolution Theory
Distributed Differentially Private Matrix Factorization for Implicit Data via Secure Aggregation
Computing En-Route for Near-Data Processing
Modeling Wireless Local with General Call Holding Times and Finite Number of Subscribers
Practical Deadlock-Free Fault-Tolerant Routing in Meshes Based on the Planar Network Fault Model
A New PLA Design for Universal Testability
Matrix Transformations for N -Tuple Analysis of Binary Patterns
Abstractions for Node Level Passive Fault Detection in Distributed Systems
Accurate and Reliable Energy Measurement and Modelling of Data Transfer Between CPU and GPU in Parallel Applications on Heterogeneous Hybrid Platforms
A Fast Radix-4 Division Algorithm and Its Architecture
"Uniform-access" time - a needed concept
Load Redistribution Under Failure in Distributed Systems
Rational Approximants for Some Performance Analysis Problems
Utility Functions and Resource Management in an Oversubscribed Heterogeneous Computing Environment
A Topological Method for the Determination of the Minimal Forms of a Boolean Function
Computational Complexity of Partitioned List Algorithms
Towards a Cryptographic Minimal Design: The sLiSCP Family of Permutations
Low-Power Unsigned Divider and Square Root Circuit Designs Using Adaptive Approximation
The Superthreaded Processor Architecture
Predictive Heterogeneity-Aware Application Scheduling for Chip Multiprocessors
Test Strategies for Reliable Runtime Reconfigurable Architectures
Impact of the LSI on High-Speed Computer Packaging
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
Architecture for a Low Complexity Rate-Adaptive Reed-Solomon Encoder
A Multicomputer System with Dynamic Architecture
System Design of a Dynamic Microprocessor
On the Realization of Functions in N-Valued Logic
Processor Control Flow Monitoring Using Signatured Instruction Streams
Binary Trees and Parallel Scheduling Algorithms
MTEC: A Microprocessor System for Astronomical Telescope and Instrument Control
A Family of Variable-Precision Interval Arithmetic Processors
The J-K Gate
Minimizing Staleness and Communication Overhead in Distributed SGD for Collaborative Filtering
Dynamic Memory Interconnections for Rapid Access
A Digital Processor to Generate Spectra in Real Time
A Design for (d, k) Graphs
An Analysis of a Tandem Queueing System for Flow Control in Computer Networks
A Blockchain-Based Decentralized, Fair and Authenticated Information Sharing Scheme in Zero Trust Internet-of-Things
Automata-Based Symbolic Scheduling for Looping DFGs
A Near-Optimal Heuristic Algorithm for Single-Row Routing
Minimizing External Wires in Generalized Single-Row Routing
A Systematic Design of Cellular Permutation Arrays
Real-Number Codes for Bault-Tolerant Matrix Operations On Processor Arrays
System Dependability Evaluation via a Fault List Generation Algorithm
Mathematical Foundation of Computer Arithmetic
Neural Network Simulation and Evolutionary Synthesis of QCA Circuits
Merit's Evolution - Statistically Speaking
Stochastic Contention Level Simulation for Single-Chip Heterogeneous Multiprocessors
Feature Extraction by Golay Hexagonal Pattern Transforms
Switching Codes for Delta-I Noise Reduction
Towards Formal Evaluation and Verification of Probabilistic Design
Notes on Multiple Input Signature Analysis
A New Technique for Fast Number Comparison in the Residue Number System
Techniques for Efficient Encoding of Features in Pattern Recognition
A Digital Comparator for Use with Computer Displays
Modeling of Gaussian Network-Based Reconfigurable Network-on-Chip Designs
Formal Non-Fragile Stability Verification of Digital Control Systems with Uncertainty
Improving Space Efficiency With Path Length Prediction for Finding k Shortest Simple Paths
t-TDA-Diagnosable Systems
A Transverse-Read-Assisted Fast Valid-Bits Collection in Stochastic Computing MACs for Energy-Efficient in-RTM DNNs
Circuit Optimization by Rewiring
Comments on "Some Additions to Solution of Switching Equations Based on a Tabular Algebra"
Symmetry Types in Threshold Logic
Computer Simulation of Space-Filling Molecular Models
The Universality of the Shuffle-Exchange Network
An Implementation of Mixed-Radix Conversion for Residue Number Applications
Linear, Passive, Matched Filter for Digital Magnetic Recording
Detection of Unidirectional Multiple Errors Using Low-Cost Arithmetic Codes
Draco: Efficient Resource Management for Resource-Constrained Control Tasks
An Automatic Self-Checking and Fault-Locating Method
Vulnerability of Sensor Networks to Unauthorized Traversal and Monitoring
Representation of Uncertainty in Computer Vision Using Fuzzy Sets
Centralized and Clustered k-Coverage Protocols for Wireless Sensor Networks
Comment on "Solution of Nonlinear Equations"
A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis
Improving Computer Architecture Simulation Methodology by Adding Statistical Rigor
Some Properties of Iterative Square-Rooting Methods Using High-Speed Multiplication
Tunnel Diode Logic Circuits
Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors
Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks
Hazard Correction in Synchronous Sequential Circuits
iBuddy: Inverse Buddy for Enhancing Memory Allocation/Deallocation Performanceon Multi-Core Systems
The Focus Number System
Single Precision Logarithm and Exponential Architectures for Hard Floating-Point Enabled FPGAs
Error Codes for Arithmetic Operations
Complex Disjunctive Decomposition of Incompletely Specified Boolean Functions
Multiple Stuck-Open Fault Detection in CMOS Logic Circuits
Fail-Safe Asynchronous Machines with Multiple-Input Changes
Single Residue Error Correction in Residue Number Systems
Fast Converter for 3 Moduli RNS Using New Property of CRT
Operating experience with UNIVAC SYSTEMS
Error/Secure/Propagating Concept and its Application to the Design of Strongly Fault-Secure Processors
Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement
On Internal Variable Assignments for Sequential Switching Circuits
The Error Characteristics of the Binary Rate Multiplier
Time-Predictable Out-of-Order Execution for Hard Real-Time Systems
Constructing Test Cases for Partitioning Heuristics
Lower Bounds on Crosspoints in Concentrators
Resilient Scheduling of Moldable Parallel Jobs to Cope With Silent Errors
Regularity-Based Virtualization Under the ARINC 653 Standard for Embedded Systems
Greedy Diagnosis of Hybrid Fault Situations
Time-Memory Trade-Offs for Saber+ on Memory-Constrained RISC-V Platform
CMOS VLSI Implementation of a Low-Power Logarithmic Converter
Load Balancing Problems for Multiclass Jobs in Distributed/Parallel Computer Systems
Architecture Scalability of Parallel Vector Computers with a Shared Memory
An Application of Formal Analysis to Software in a Fault-Tolerant Environment
Correction to "A Modulo Two Adder for Three Inputs Using a Single Tunnel Diode"
Counting with Nonlinear Binary Feedback Shift Registers
Optimizing Soft Error Reliability Through Scheduling on Heterogeneous Multicore Processors
An Approach for Simplifying Switching Functions by Utilizing the Cover Table Representation
A Fast Carry-Propagation Circuit for Base 3 Signed Non redundant Arithmetic
DS3: A System-Level Domain-Specific System-on-Chip Simulation Framework
Timing Constraint Remapping to Achieve Time Equi-Continuity in Distributed Real-Time Systems
Generalized Transforms for Multiple Valued Circuits and Their Fault Detection
Fault Coverage and Test Length Estimation for Random Pattern Testing
On the Use of "Importance Weights" in Assessing Subsystem Reliability
G101 - A Remote Time Share Terminal with Graphic Output Capabilities
Investigating Black-Box Function Recognition Using Hardware Performance Counters
Survival Reliability of Some Double-Loop Networks and Chordal Rings
Active Memory Processor for Network-on-Chip-Based Architecture
A New Solution to Coherence Problems in Multicache Systems
An ALU-Based BIST Scheme for Word-Organized RAMs
Frequency Analysis of Truncation Errors in RC Networks
On the Minimum Logical Complexity Required for a General Purpose Computer
Edge-Centric Programming for IoT Applications With Automatic Code Partitioning
A Simple Convergent Algorithm for Rapid Solution of Polynomial Equations
A Novel Weighted-Graph-Based Grouping Algorithm for Metadata Prefetching
CINDA: Using Cache-Coherent Interconnects for Accelerating Databases by Enabling Near-Data Processing of Update Transactions
Evaluation of Performability for Degradable Computer Systems
A Randomized Parallel Backtracking Algorithm
Design of Efficient Error-Correcting Balanced Codes
Area and System Clock Effects on SMT/CMP Throughput
The Realization of Polylinear Sequential Circuits Using Flip-Flop Memory
B74-7 Basic Programming
A Parallel Mechanism for Detecting Curves in Pictures
Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding
An Exploration of the Effects of State Granularity through (m, k) Real-Time Streams
Biophysically Accurate Foating Point Neuroprocessors for Reconfigurable Logic
Uniprocessor Virtual Memory without TLBs
Comments on "On the Floating Point Representation of Complex Numbers"
Detection of Pattern-Sensitive Faults in Random-Access Memories
Some Experiments in Local Microcode Compaction for Horizontal Machines
Maximum Entropy Image Reconstruction
High-Speed, Interlaced WRITE and READ-Only Operation of a Plated-Wire Memory System
On an Optimally Fault-Tolerant Multiprocessor Network Architecture
A Signed Bit-Sequential Multiplier
Modeling Live and Dead Lines in Cache Memory Systems
Multivariate Statistical Analysis of Audit Trails for Host-Based Intrusion Detection
The Recording and Reproduction of Signals on Magnetic Medium Using Saturation-Type Recording
On k-Stable Feedback Shift Registers
R68-49 Virtual Memory Processes and Sharing in Multics
NoC-Based Hardware Accelerator for Breakpoint Phylogeny
Array Access Bounds for Block Storage Memory Systems
Diagnosability of Enhanced Hypercubes
Unateness Test of a Boolean Function and Two General Synthesis Methods Using Threshold Logic Elements
EIHDP: Edge-Intelligent Hierarchical Dynamic Pricing Based on Cloud-Edge-Client Collaboration for IoT Systems
Distributed Sketch Deployment for Software Switches
Design and Analysis of Approximate Redundant Binary Multipliers
Clustered Worst-Case Execution-Time Calculation