yusuke1997/dblp-id-title huggingface dataset:
Transparent Fault Tolerance of Device Drivers for Virtual Machines
(t, k)-Diagnosis for Matching Composition Networks
Towards a Theory of Universal Speed-Independent Modules
StageNet: A Reconfigurable Fabric for Constructing Dependable CMPs
Unified Mixed Radix 2-4 Redundant CORDIC Processor
On Error Indication for Totally Self-Checking Systems
On the Delay-Sensitivity of Gate Networks
State Assignment Selection in Asynchronous Sequential Circuits
Interface Optimization: An Algorithm for the Detection of Data Path Redundancy and Reconfigurability Towards Obtaining Minimal Bus Interfaces
The Synthesis of Minimal Hazardless TANT Networks
A Modified Fixed-Increment Training Algorithm
An Isomorphic Notation of Switching Circuits
Locally Subcube-Connected Hypercube Networks: Theoretical Analysis and Experimental Results
Multiple-Read Single-Write Memory and Its Applications
Cellular-Automata-Array-Based Diagnosis of Board Level Faults
Real-Time Scheduling and Analysis of OpenMP DAG Tasks Supporting Nested Parallelism
The LX-1 Microprocessor and Its Application to Real-Time Signal Processing
On Fault-Tolerant Distributor Communication Architecure
CIRRUS, An Economical Multiprogram Computer with Microprogram Control
Credit-Based Runtime Placement of Virtual Machines on a Single NUMA System for QoS of Data Access Performance
"Ratchet" Circuits for Electronic Analog Storage
A Gray Code Counter
Locality as a Visualization Tool
Reliable Butterfly Distributed-Memory Multiprocessors
Speeding up the Synthesis of Programs from Traces
On Coding the States of Sequential Machines with the Use of Partition Pairs
On Translation Algorithms in Residue Number Systems
Learning-Based Modeling and Optimization for Real-Time System Availability
Analog Computer Techniques for Problems in Complex Variables
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
Efficient Approximation Algorithms for Server Allocation to Minimize Total Capacity under Server Failure
Secure Deep Learning in Defense in Deep-Learning-as-a-Service Computing Systems in Digital Twins
Portable and Efficient Parallel Computing Using the BSP Model
Parallel Counters
On the Analysis of Parallel Real-Time Tasks With Spin Locks
Esaki Diode NOT-OR Logic Circuits
Memory and Communication Profiling for Accelerator-Based Platforms
Simulation-Based Verification of Floating-Point Division
Note on Finite-Memory Sequential Machines
Data for Character Recognition Studies
Rearrangeable Three-Stage Interconnection Networks and Their Routing Properties
Split: A Hash-Based Memory Optimization Method for Zero-Knowledge Succinct Non-Interactive Argument of Knowledge (zk-SNARK)
A Piecewise Linear Approximation of log 2 x with Equal Maximum Errors in All Intervals
On the Number of Multivalued Switching Functions Realizable by Cascades
On Suboptimal Sequential Pattern Recognition
Routing Schemes for the Augmented Data Manipulator Network in an MIMD System
On the Existence of Combinational Logic Circuits Exhibiting Multiple Redundancy
Spatio-Temporal Optimization of Deep Neural Networks for Reconfigurable FPGA SoCs
Good Layouts for Pattern Recognizers
Dependability Measurement and Modeling of a Multicomputer System
Computation and Formal Verification of SRT Quotient and Square Root Digit Selection Tables
Error-Correcting Codes in Binary-Coded Radix- r Arithmetik
On the Bandwidth and Interference in Interleaved Memory Systems
A Video Display System for Image Processing by Computer
Comments on "Sequential Machine Identification"
PR-SSD: Maximizing Partial Read Potential by Exploiting Compression and Channel-Level Parallelism
Response to "One-Bit Delay in Ring Networks"
Improving Cache Locality by a Combination of Loop and Data Transformation
A Multi-Resolution FPGA-Based Architecture for Real-Time Edge and Corner Detection
PFed-NS: An Adaptive Personalized Federated Learning Scheme Through Neural Network Segmentation
Some Properties of Boolean Equations
Efficient Generation of Statistically Good Pseudonoise by Linearly Interconnected Shift Registers
Delay and Throughput Analysis for Computer Communications with Balanced HDLC Procedures
Functional Characteristics of a Multilingual Processor
Parameter Space for the Architecture of FFT-Based Montgomery Modular Multiplication
A Performance Analysis of Times Synchronous Communication Primitives
An Algorithm for Intercell Communication in a Tesselated Automaton
The Design and Evaluation of a Self-Organizing Superpeer Network
Designing Checksums for Detecting Errors in Fast Unitary Transforms
A Unified Parallel CORDIC-Based Hardware Architecture for LSTM Network Acceleration
Exploring Server Redundancy in Nonblocking Multicast Data Center Networks
A Heuristically-Aided Algorithm for Mutual Exclusion in Distributed Systems
A Unifying Service Discipline for Providing Rate-Based Guaranteed and Fair Queuing Services Based on the Timed Token Protocol
Improvement to Montgomery Modular Inverse Algorithm
Resilience of Randomized RNS Arithmetic with Respect to Side-Channel Leaks of Cryptographic Computation
Efficient Construction of Pipelined Multibit-Trie Router-Tables
Hardware Complexity of Modular Multiplication and Exponentiation
On the Access Pricing and Network Scaling Issues of Wireless Mesh Networks
Time-Driven Priority Router Implementation: Analysis and Experiments
High Throughput Hardware/Software Heterogeneous System for RRPN-Based Scene Text Detection
A New ECC Configuration Method for DRAM System Considering Metadata
A Hardware Device for Generalized Mapping Functions
A Formal Model to Manage the InfiniBand Arbitration Tables Providing QoS
Computer Interpretation of English Text and Picture Patterns
Buffer Assignment Algorithms on Data Driven ASICs
Field Inversion and Point Halving Revisited
Interleaving in Systolic-Arrays: A Throughput Breakthrough
A Binary Feature Extraction Technique
A Systematic Approch for Mapping Application Tasks in Hypercubes
Cellular Logic Array for High-Speed Signed Binary Number Multiplication
O(n)-Depth Modular Exponentiation Circuit Algorithm
A Simplified General Method for Static Hazard Detection
A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs
Serving MoE Models on Resource-Constrained Edge Devices via Dynamic Expert Swapping
Automatic Generation of Modular Multipliers for FPGA Applications
Design of Pattern Classifiers with the Updating Property Using Stochastic Approximation Techniques
Designing Optimum One-Level Carry-Skip Adders
Use of Fault Dropping for Multiple Fault Analysis
Optimal Algorithms for Well-Conditioned Nonlinear Systems of Equations
Least Squares Image Restoration Using Spline Basis Functions
On Minimizing Internal Data Migrations of Flash Devices via Lifetime-Retention Harmonization
Ensuring Cache Reliability and Energy Scaling at Near-Threshold Voltage With Macho
Scheduling to Optimize Cache Utilization for Non-Volatile Main Memories
An Adaptive Replacement Algorithm for Paged-Memory Computer Systems
On "A New Representation of Elements of Finite Fields GF (2 m ) Yielding Small Complexity Arithmetic Circuits"
Comments on "Identification of Totally Symmetric Boolean Functions"
Generalized Clustering for Problem Localization
Generation of Products and Quotients Using Approximate Binary Logarithms for Digital Filtering Applications
Scheduling Precedence Constrained Tasks with Reduced Processor Energy on Multiprocessor Computers
On the Complexity of Designing Optimal Branch-and-Combine Clock Networks
Multi-Grained Trace Collection, Analysis, and Management of Diverse Container Images
MAGIC: Making IMR-Based HDD Perform Like CMR-Based HDD
Concurrent Linguistic Error Detection (CLED): A New Methodology for Error Detection in Large Language Models
Built-In Testing of Integrated Circuit Wafers
Algorithms for Multiple Shift Register Realizations of Sequential Machines
Sensitivity of Dynamic Systems to Parameters Which Increase the Order of Mathematical Models
An Adaptive Associative Memory Principle
RC-MAC: A Receiver-Centric MAC Protocol for Event-Driven Wireless Sensor Networks
Avalanche Characteristics of Substitution-Permutation Encryption Networks
Improving SSD Read Latency via Coding
Revisiting Fault Adversary Models - Hardware Faults in Theory and Practice
Compilation Techniques for Recognition of Parallel Processable Tasks in Arithmetic Expressions
On-Line Scheduling Policies for a Class of IRIS (Increasing Reward with Increasing Service) Real-Time Tasks
Analysis of Reliability Dynamics of SSD RAID
A Modified Matrix Algorithm for Determining the Complete Connection Matrix of a Switching Network
A Balanced Pipelining Approach to Multiprocessing on an Instruction Stream Level
On Functional Testing of Array Processors
Constant Geometry Fast Fourier Transforms on Array Processors
Detecting the Capacitance-Based Gamepad for Protecting Mobile Game Fairness
Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
Embedding Star Networks into Hypercubes
A Fully-Pipelined Hardware Design for Gaussian Mixture Models
Dynamic Memories with Fast Random and Sequential Access
Automatic Debugging of Real-Time Systems Based on Incremental Satisfiability Counting
Improving Availability of RAID-Structured Storage Systems by Workload Outsourcing
The Design of Small-Diameter Networks by Local Search
2-1 Additions and Related Arithmetic Operations with Threshold Logic
Cost-Effective Flow Table Designs for High-Speed Routers: Architecture and Performance Evaluation
A Differential Fault Attack on Plantlet
Orthogonal Matrices, Error-Correcting Codes and Load-Sharing Matrix Switches
New Bounds on the Reliability of Augmented Shuffle-Exchange Networks
Dual-Homing Based Scalable Partia Multicast Protection
Exploiting Operand Availability for Efficient Simultaneous Multithreading
Algorithm and Hardware Co-Design of Energy-Efficient LSTM Networks for Video Recognition With Hierarchical Tucker Tensor Decomposition
A Fast-Serial-Parallel Binary Multiplier
Computation of the Hadamard Transform and the R- Transform in Ordered Form
Optimum Logic Modules
Memory Hardware for High Speed Job Selection
Algorithm-Based Fault Tolerance for Matrix Operations
SmashGuard: A Hardware Solution to Prevent Security Attacks on the Function Return Address
Parallel Permutations of Data: A Benes Network Control Algorithm for Frequently Used Permutations
Multi-threshold building blocks
RAMS: DRAM Rank-Aware Memory Scheduling for Energy Saving
Systematic Design of Fault-Tolerant Multiprocessors with Shared Buses
Fair Scheduling in Internet Routers
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests
Minimal Complexity Machines Under Weight Quantization
A Declustering Criterion for Feature Extraction in Pattern Recognition
Improving Availability of Multicore Real-Time Systems Suffering Both Permanent and Transient Faults
On the Optimal Allocation of Virtual Resources in Cloud Computing Networks
A New Voltage to Frequency Converter
Revisiting Vulnerability Analysis in Modern Microprocessors
Modeling and Performance Analysis of Single-Bus Tightly-Coupled Multiprocessors
Computer Analysis of Planar Curvilinear Moving Images
An Introduction to the Direct Emulation of Control Structures by a Parallel Microcomputer
Fair Round-Robin: A Low Complexity Packet Schduler with Proportional and Worst-Case Fairness
Design of an All-Magnetic Computing System: Part I-Circuit Design
Community-Based Event Dissemination with Optimal Load Balancing
Low Latency Time CORDIC Algorithms
Protecting the CCSDS 123.0-B-2 Compression Algorithm Against Single-Event Upsets for Space Applications
R68-26 Some Techniques for Accuracy Improvement in Analog Computation
A Quantitative Analysis of the Performance and Scalability of Distributed Shared Memory
Cholla: A Framework for Composing and Coordinating Adaptations in Networked Systems
Exhaustive Test Pattern Generation with Constant Weight Vectors
An Empirical Architecture-Centric Approach to Microarchitectural Design Space Exploration
Evaluation of a Diagnosis Algorithm for Regular Structures
Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation
A Note on Strongly Fault-Secure Sequential Circuits
Differential Fault Attack on Rasta and $\text{FiLIP}_{\text{DSM}}$
Computing Machine Aids to a Development Project
Optimal Query Processing for Distributed Database Systems
Static-Hazard-Free T -Gate for Ternary Memory Element and Its Application to Ternary Counters
An Operator Factorization Method for Restoration of Blurred Images
Multiphase Complete Exchange: A Theoretical Analysis
Richard B. Worrell: A Prime Implicant Algorithm with Factoring
Performance Evaluation of Service Differentiating Internet Servers
High-Speed M -Sequence Generators
Low-Latency ASIC Algorithms of Modular Squaring of Large Integers for VDF Evaluation
A Scalable Dual-Field Elliptic Curve Cryptographic Processor
Zombie Chasing: Efficient Flash Management Considering Dirty Data in the Buffer Cache
R70-43 Lattice Functions, Pair Algebras, and Finite-State Machines
DyNNamic: Dynamically Reshaping, High Data-Reuse Accelerator for Compact DNNs
On Bit Steering in the Minimization of the Control Memory of Microprogrammed Processors
The editor
Lightweight Key Encapsulation Using LDPC Codes on FPGAs
An Algorithm for Selecting an Optimum Set of Diagnostic Tests
Machine Learning Computers With Fractal von Neumann Architecture
SCC: Synchronization Congestion Control for Multi-Tenant Learning Over Geo-Distributed Clouds
Convergence in Iteratively Formed Correlation Matrix Memories
Processor Utilization in a Linearly Connected Parallel Processing System
Aging-Aware Workload Management on Embedded GPU Under Process Variation
Scheduling Superblocks with Bound-Based Branch Trade-Offs
Algorithm, Architecture, and Floating-Point Unit Codesign of a Matrix Factorization Accelerator
Use of Functional Approximation Methods in the Computer Solution of Initial Value Partial Differential Equation Problems
On the Problem of Evaluating the Performance of Multiprogrammed Workloads
The Vertex-Frame Method for Obtaining Minimal Proposition-Letter Formulas
Design and Architectural Implications of a Spatial Information System
Privacy-Preserving Vehicular Communication Authentication with Hierarchical Aggregation and Fast Response
MARS : Mobile Application Relaunching Speed-Up through Flash-Aware Page Swapping
Design of Reliable and Secure Devices Realizing Shamir's Secret Sharing
Compressed Test Pattern Generation for Deep Neural Networks
Experiments with the n-tuple Method of Pattern Recognition
A Privacy-Preserving Outsourced Functional Computation Framework Across Large-Scale Multiple Encrypted Domains
Author's reply 2
A Rectilinear-Monotone Polygonal Fault Block Model for Fault-Tolerant Minimal Routing in Mesh
Privacy-Enhanced Decentralized Federated Learning at Dynamic Edge
Fast Microwave Logic Circuits
A Native APIs Protection Mechanism in the Kernel Mode against Malicious Code
Future Scaling of Memory Hierarchy for Tensor Cores and Eliminating Redundant Shared Memory Traffic Using Inter-Warp Multicasting
PICAP - A System Approach to Image Processing
A New Approach to Resistor-Transistor-Tunnel-Diode Nanosecond Logic
Textural Boundary Analysis
On Generating a Line "Parallel" to a Digital Line - A Sequential Approach
Considering Solder Connections, Does Triplicated Majority Voting Apply to Integrated Circuits
Using Application Benefit for Proactive Resource Allocation in Asynchronous Real-Time Distributed Systems
Excel-NUMA: Toward Programmability, Simplicity, and High Performance
Threshold-Logic Synthesis by Algebraic Methods
Disaggregation and Sharing of I/O Devices in Cloud Data Centers
Characterization and Cardinality of Universal Functions
Binary-Ternary Plus-Minus Modular Inversion in RNS
Three Variable Multiple Output Tree Circuits
The Self-Diagnosability of a Computer
Allspark: Workload Orchestration for Visual Transformers on Processing In-Memory Systems
Another Comment on "A Variable Counter Design Technique"
R68-12 An Experimental Model of System/ 360
Evaluation of Communication Architectures for Switched Real-Time Ethernet
Signal Probabilities in AND-OR Trees
Component-Composition Graphs: (t, k)-Diagnosability and Its Application
Exploring Fine-Grained Heterogeneity with Composite Cores
Fault-Tolerant Computers Using "Dotted Logic" Redundancy Techniques
Efficient Instruction Sequencing with Inline Target Insertion
Power-Aware Scheduling for Periodic Real-Time Tasks
Genetic Algorithm and Graph Partitioning
A Prototype Intelligent Robot that Assembles Objects from Plan Drawings
A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation
A3C-DO: A Regional Resource Scheduling Framework Based on Deep Reinforcement Learning in Edge Scenario
Guest Editorial: IEEE Transactions on Computers Special Section on Emerging Non-Volatile Memory Technologies: From Devices to Architectures and Systems
Efficient and Scalable External Sort Framework for NVMe SSD
Cross Coupling in High Speed Digital Systems
Implications of Charge-Coupled Devices for Pattern Recognition
Bit-Stuffing Algorithms for Crosstalk Avoidance in High-Speed Switching
Conditional Connectivity Measures for Large Multiprocessor Systems
R68-15 Trajectory Computation by a Hybrid Computer for the Apollo Midcourse Abort Simulation
The Lens Interconnection Strategy
On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance
AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures
Effective Reconstruction of Data Perturbed by Random Projections
Diagnosability of Hypercubes and Enhanced Hypercubes under the Comparison Diagnosis Model
Scaling Laws of Multicast Capacity for Power-Constrained Wireless Networks under Gaussian Channel Model
Multifunction Monolithic Thin-Film Compatible DTL Logic Circuits for Data Processing
Parametric Module Allocation on Partial k-Trees
Theory and Application of Nongroup Cellular Automata for Synthesis of Easily Testable Finite State Machines
R68-24 A Proposal for Definitions in ALGOL
Secondary Radix Recodings for Higher Radix Multipliers
Optimizing the Performance of a Drum-Like Storage
On the Construction of Communication Networks Satisfying Bounded Fan-In of Service Ports
Design and Implementation of an SAN System Based on the Fiber Channel Protocol
An Efficient Algorithm for Identifying the Most Likely Fault Set in a Probabilistically Diagnosable System
A Storage Efficient Way to Implement the Discrete Cosine Transform
On Multivalued Symmetric Functions
Dynamic Scheduling of Hybrid Real-Time Tasks on Clusters
A New Method for Automatic Character Recognition
Mapping Multidimensional Space to One Dimension for Computer Output Display
A High-Efficiency Parallel Mechanism for Canonical Polyadic Decomposition on Heterogeneous Computing Platform
RT-ByzCast: Byzantine-Resilient Real-Time Reliable Broadcast
Smart Cloud Storage Service Selection Based on Fuzzy Logic, Theory of Evidence and Game Theory
Incorporating Yield Enhancement into the Floorplanning Process
Cross-Section Reconstruction with a Fan-Beam Scanning Geometry
On the Polynomial Multiplication in Chebyshev Form
Local Properties of Binary Images in Two Dimensions
Diagnosability of Nonlinear Circuits and Systems - Part II: Dynamical Systems
Minimization of Exclusive or and Logical Equivalence Switching Circuits
General Division in the Symmetric Residue Number System
A Deadline-Floor Inheritance Protocol for EDF Scheduled Embedded Real-Time Systems with Resource Sharing
A Flow Analysis Procedure for the Translation of High-Level Languages to a Data Flow Language
Performance Analysis of Cluster-Based Multiprocessors
An O(n+k) Algorithm for Ordered Retrieval from an Associative Memory
Tapered Floating Point: A New Floating-Point Representation
Condition Adaptation in Synchronous Consensus
On Testing Isomorphism of Permutation Networks
New Techniques for Constructing EC/AUED Codes
A Method for the Selection of Prime Implicants
B74-1 Complexity of Computer Computations
TeeRollup: Efficient Rollup Design Using Heterogeneous TEE
Reaping Both Latency and Reliability Benefits With Elaborate Sanitization Design for 3D TLC NAND Flash
DC-ORAM: An ORAM Scheme Based on Dynamic Compression of Data Blocks and Position Map
Decision-Directed Estimation of a Two-Class Decision Boundary
Vector-Reduction Techniques for Arithmetic Pipelines
Monotonicity of Multi-term Floating-Point Adders
Many-to-Many Disjoint Path Covers in the Presence of Faulty Elements
Ordered Round-Robin: An Efficient Sequence Preserving Packet Scheduler
A New Measure for Hybrid Fault Diagnosability
Algorithms for Recognizing Contour-Traced Handprinted Characters
The Effects of Interconnections on High-Speed Logic Circuits
Contention and Locality-Aware Work-Stealing for Iterative Applications in Multi-Socket Computers
Correction to "A Division Method Using a Parallel Multiplier"
Properties and Transformations of Single Threshold Element Functions
On the Complexity of Optimal Bused Interconnections
BFT-DSN: A Byzantine Fault-Tolerant Decentralized Storage Network
Hazards in Pulse Sequential Circuits
A Distributed Control Algorithm for Reliably and Consistently Updating Replicated Databases
Power-Efficient Direct-Voting Assurance for Data Fusion in Wireless Sensor Networks
Potential Functions in Mathematical Pattern Recognition
Iterative Algorithms for Solution of Large Sparse Systems of Linear Equations on Hypercubes
Hybrid Signed-Digit Number Systems: A Unified Framework for Redundant Number Representations With Bounded Carry Propagation Chains
Optimization of Polynomial Expressions by Using the Extended Dual Polarity
Trust-Preserving Mechanism for Blockchain Assisted Mobile Crowdsensing
VLSI Architectures for Multidimensional Transforms
Joint Optimal Data Rate and Power Allocation in Lossy Mobile Ad Hoc Networks with Delay-Constrained Traffics
Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2 m )
R70-44 Synchronization and General Repetitive Machines, with Applications to Ultimate Definite Automata
Test Procedure Optimization for Layered Protocol Implementations
AMBEA: Aggressive Maximal Biclique Enumeration in Large Bipartite Graph Computing
Fault-Tolerant Multiprocessors with Redundant-Path Interconnection Networks
LogSay: An Efficient Comprehension System for Log Numerical Reasoning
Security Information Flow in Multidimensional Arrays
Dual-Mode Logic for Function-Independent Fault Testing
On Newton-Raphson Iteration for Multiplicative Inverses Modulo Prime Powers
Two-Phase Deadlock Detection Algorithm
STFL-DDR: Improving the Energy-Efficiency of Memory Interface
Tackling Biased PUFs Through Biased Masking: A Debiasing Method for Efficient Fuzzy Extractor
A Functional Approach to Efficient Fault Detection in Iterative Logic Arrays
Maintaining Strong Cache Consistency in the World Wide Web
R70-33 Fuzzy Events Realized by Finite Probabilistic Automata
Design and Implementation of an Out-of-Band Virtualization System for Large SANs
Efficient Design-for-Test Approach for Networks-on-Chip
Coding for Random-Access Memories
The Design of a Reliable Remote Procedure Call Mechanism
A New Adaptive Hardware Tree-Based Multicast Routing in K-Ary N-Cubes
Optimal Centralized Algorithms for Store-and-Forward Deadlock Avoidance
On the Characteristics of a Simple Architecture for Finite Impulse Response Digital Filtering
Sequential Hierarchical Scene Matching
Deploying Wireless Sensor Networks with Fault-Tolerance for Structural Health Monitoring
Sieve Method for Real-Time Computer-Aided Extraction of Multivalued Analog Signals in the Presence of Noise
Reducing the Energy Consumption of Ethernet with Adaptive Link Rate (ALR)
PRRQ: Privacy-Preserving Resilient RkNN Query Over Encrypted Outsourced Multiattribute Data
Three-Dimensional Structured Networks for Matrix Equation Solving
Message-Optimal Protocols for Fault-Tolerant Broadcasts/Multicasts in Distributed Systems with Crash Failures
Automated Cloud Tracking Using Precisely Aligned Digital ATS Pictures
An Optimal Retry Policy Based on Fault Classification