yusuke1997/dblp-id-title huggingface dataset:
Signed Digit Representations of Minimal Hamming Weight
A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach
Cost-Efficient Mapping for Fault-Tolerant Virtual Networks
A Multiple Seed Linear Feedback Shift Register
Opara: Exploiting Operator Parallelism for Expediting DNN Inference on GPUs
Comments on "The Use of the Simplex Algorithm in the Mechanization of Boolean Switching Functions by Means of Magnetic Cores
Generalized Inverse Approach to Adaptive Multiclass Pattern Classification
Distribution of Programs for a System with Dynamic Architecture
Fault-Tolerant Computing: An Introduction and a Viewpoint
Spectral Fault Signatures for Internally Unate Combinational Networks
PC-TRIO: A Power Efficient TCAM Architecture for Packet Classifiers
GCoDE: Efficient Device-Edge Co-Inference for GNNs via Architecture-Mapping Co-Search
The MECRA: A Self-Reconfigurable Computer for Highly Reliable Process
ADLPT: Improving 3D NAND Flash Memory Reliability by Adaptive Lifetime Prediction Techniques
Computer-Aided Digital System Design and Analysis Using a Register Transfer Language
R68-8 Language Directed Computer Design
Design of Testable Structures Defined by Simple Loops
Reliability-Aware Optimization of Task Offloading for UAV-Assisted Edge Computing
An Algebraic Method for Minimizing the Number of States in an Incomplete Sequential Machine
On t-Error Correcting/All Unidirectional Error Detecting Codes
Programming Language Support for Writing Fault-Tolerant Distributed Software
Using Decision Diagrams to Design ULMs for FPGAs
NBBM: An Efficient SmartNIC-Based Architecture for Bare-Metal Management in Cloud Platforms
Reservation Channel Access Protocol for High Speed Local Networks with Star Configurations
The Accelerated Relaxation Method for Linear Inequalities
B74-23 Numerical Control-Mathematics and Applications
Some Applications of Magnetic Film Parametrons as Logical Devices
Testing Strategy and Technique for Macro-Based Circuits
Accelerating Generative Neural Networks on Unmodified Deep Learning Processors - A Software Approach
A Recovery Cache for the PDP-11
Determining Redundancy Levels for Fault Tolerant Real-Time Systems
Graph Theoretical Analysis and Design of Multistage Interconnection Networks
A Digital Static Magnetic Wire Storage with Nondestructive Read-Out
PABC: Power-Aware Buffer Cache Management for Low Power Consumption
Comments on "Real-Time Analog-Digital Computation"
LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update
CryptSQLite: SQLite With High Data Security
Protecting Core Memory Circuits with Error Correcting Cyclic Codes
Scheduling Precedence Constrained Stochastic Tasks on Heterogeneous Cluster Systems
Performance and Reliability of Tree-Structured Grid Services Considering Data Dependence and Failure Correlation
Static Assignment of Stochastic Tasks Using Majorization
A Deterministic Built-In-Self-Test Generator Based on Cellular Automata Structures
A Fast Algorithm for the Disjunctive Decomposition of Switching Functions
Reliability Analysis of N -Modular Redundancy Systems with Intermittent and Permanent Faults
The Number of Intersections Between Two Rectangular Paths
Degrees of Freedom and Modular Structure in Matrix Multiplication
A Totally Self-Checking Checker for a Parallel Unordered Coding Scheme
An STT-MRAM Based in Memory Architecture for Low Power Integral Computing
Compression-Based Program Characterization for Improving Cache Memory Performance
Performance Evaluation and Cost Analysis of Cache Protocol Extensions for Shared-Memory Multiprocessors
GANDAFL: Dataflow Acceleration for Short Read Alignment on NGS Data
Robustness Results Concerning EDF Scheduling upon Uniform Multiprocessors
Guest Editors' Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems
A Local Parallel Search Approach for Memory Failure Pattern Identification
Exploring Shared Virtual Memory for FPGA Accelerators with a Configurable IOMMU
On the Minimization of the Width of the Control Memory of Microprogammed Processors
Location Consistency-A New Memory Model and Cache Consistency Protocol
Multivariate Extension of Univariate Distributions
Start Simple and then Refine: Bias-Variance Decomposition as a Diagnosis Tool for Leakage Profiling
GDP: A Greedy Based Dynamic Power Budgeting Method for Multi/Many-Core Systems in Dark Silicon
Branch Target Buffer Design and Optimization
FedRFQ: Prototype-Based Federated Learning With Reduced Redundancy, Minimal Failure, and Enhanced Quality
EcoFlow: Efficient Convolutional Dataflows on Low-Power Neural Network Accelerators
Packet Classification Using Dynamically Generated Decision Trees
Computing the Shortest Network under a Fixed Topology
A New Class of Error-Correcting/Detecting Codes for Fault-Tolerant Computer Applications
Bounds on the Performance of Message Routing Heuristics
Computer Arithmetic: An Introduction and Overview
Maintaining Temporal Consistency of Discrete Objects in Soft Real-Time Database Systems
Residues of Binary Numbers Modulo Three
A permanent high speed store for use with digital computers
Sorting with Linear Speedup on a Pipelined Hypercube
Reducing Jitter in Embedded Systems Employing a Time-Triggered Software Architecture and Dynamic Voltage Scaling
The Status of Investigations into Computer Hardware Design Based on the Use of Continued Fractions
Easily Tested Three-Level Gate Networks for T or More of N Symmetric Functions
On Error Control in Sequential Machines
SEA: A Striping-Based Energy-Aware Strategy for Data Placement in RAID-Structured Storage Systems
Design of Optimal Scan Tree Based on Compact Test Patterns for Test Time Reduction
Generation of Digit Reversed Address Sequences for Fast Fourier Transforms
R68-33 PHENO: A New Concept of Hybrid Computing Elements
Definition and Design of Strongly Language Disjoint Checkers
Cache Invalidation Patterns in Shared-Memory Multiprocessors
A Fault Identification Algorithm for t i -Diagnosable Systems
Contextual Word Recognition Using Binary Digrams
Transient Failures in Triple Modular Redundancy Systems with Sequential Modules
Linear-Segment Function Generator
The Parallel Solution of Triangular Systems of Equations
On the Design of Bayesian Storage Allocation Algorithms for Paging and Segmentation
Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories"
TSS: Efficient Term Set Search in Large Peer-to-Peer Textual Collections
Performance and Power-Efficient Design of Dense Non-Volatile Cache in CMPs
Minimization of Boolean Functions
Multirate VLSI Arrays and Their Synthesis
Distributed Deep Convolutional Neural Networks for the Internet-of-Things
A System of Magnetic Bubble Logic
An Adaptive Random Search Algorithm for Constrained Minimization
On Maximum Inversion with Minimum Inverters
PAnDA: A Reconfigurable Architecture that Adapts to Physical Substrate Variations
Efficient Data Allocation over Multiple Channels at Broadcast Servers
Packet Classification Using Space-Efficient Pipelined Multibit Tries
Software-Based Self-Testing of Symmetric Shared-Memory Multiprocessors
Evaluation and Optimization of Distributed Machine Learning Techniques for Internet of Things
A Variable Function Delay for Analog Computers
Radix 2 Division with Over-Redundant Quotient Selection
An Advanced Fault Isolation System for Digital Logic
Comments on "Closure Partition Method for Minimizing Incomplete Sequential Machines"
Test Data Decompression for Multiple Scan Designs with Boundary Scan
Leaking Secrets Through Modern Branch Predictors in the Speculative World
IEEE TC Special Issue on Real-Time Systems
A Parallel Accumulator for a General-Purpose Computer
Bounding the Mean Response Time of the Minimum Expected Delay Routing Policy: An Algorithmic Approach
Data Similarity-Aware Computation Infrastructure for the Cloud
Minimizing Probing Cost and Achieving Identifiability in Probe-Based Network Link Monitoring
System Diagnosis with Repair
A Hybrid Digital/Optical Computer System
ReAAP: A Reconfigurable and Algorithm-Oriented Array Processor With Compiler-Architecture Co-Design
Current Steering in Magnetic Circuits
Reciprocation, Square Root, Inverse Square Root, and Some Elementary Functions Using Small Multipliers
A Criterion and an Algorithm for Grouping Data
Boosting Degraded Reads in Heterogeneous Erasure-Coded Storage Systems
Optimization Using Neural Networks
Embedding Hamiltonian Paths in $k$-Ary $n$-Cubes With Exponentially-Many Faulty Edges
A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing
Switching Strategies in Shuffle-Exchange Packet-Switched Networks
Modeling of a Bubble-Memory Organization with Self-Checking Translators to Achieve High Reliability
Retiming-Based Partial Scan
Architecture Exploration of High-Performance PCs with a Solid-State Disk
A Case for Partitioned Bloom Filters
The InfoPad Multimedia Terminal: A Portable Device for Wireless Information Access
An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks
Heterogeneity-Aware Gradient Coding for Tolerating and Leveraging Stragglers
Introduction to the Special Issue on Computer Arithmetic
Comments on "The Synthesis of Binary Sequence Detectors"
Probabilistic Error Analysis of Approximate Recursive Multipliers
Automatic Parallelization of Compiled Event Driven VHDL Simulation
Functional Test Generation Based on Unate Function Theory
Dynamic Time Warp Pattern Matching Using an Integrated Multiprocessing Array
Microprogram Transformations
Comments on "An Optimal Shortest-Path Routing Policy for Network Computers with Regular Mesh-Connected Topologies"
Comments on "Algorithm for Fast Evaluation of Time Functions"
A Direct Method of Nonparametric Measurement Selection
Optimizing the Level of Confidence for Multiple Jobs
Extending Backward Error Assertions to Tolerance of Large Errors in Floating Point Computations
Online Machine Learning for Energy-Aware Multicore Real-Time Embedded Systems
Parallel Communication in a Large Distributed Environment
Fast Bit-Parallel GF(2^n) Multiplier for All Trinomials
Comments on H.J. Heijf's Review of "The SOLOMON Computer
An Easily Mechanized Scheme for an Adaptive Pattern Recognizer
Elastic Bloom Filter: Deletable and Expandable Filter Using Elastic Fingerprints
Local Area Prediction-Based Mobile Target Tracking in Wireless Sensor Networks
Reliability, Reconfiguration, and Spare Allocation Issues in Binary-Tree Architectures Based on Multiple-Level Redundancy
A New Optoelectronic Hybrid Network Based on Scheduling Optimization of Optical Links
Interlock Collapsing ALU's
An Analog-Digital Real-Time Computer
Evaluating the Use of Register Queues in Software Pipelined Loops
GPGPU-MiniBench: Accelerating GPGPU Micro-Architecture Simulation
Realization of Logical Functions by a Network of Threshold Components with Specified Sensitivity
Improving Efficiency in Multi-Modal Autonomous Embedded Systems Through Adaptive Gating
Design of a Bufferless Photonic Clos Network-on-Chip Architecture
Compiler-Assisted Multiple Instruction Rollback Recovery Using a Read Buffer
Towards a Tractable Exact Test for Global Multiprocessor Fixed Priority Scheduling
Ordering of Implicants
The Switch Reordering Contagion: Preventing a Few Late Packets from Ruining the Whole Party
Redundancy in Feature Extraction
VCMalloc: A Virtually Contiguous Memory Allocator
Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded Systems
HighP: In-Memory Acceleration of SpGEMM With High Bank-Level Parallelism
Hardware-Based Malware Detection Using Low-Level Architectural Features
Characteristics of Microstrip Transmission Lines
An fptas for Response Time Analysis of Fixed Priority Real-Time Tasks with Resource Augmentation
Problems of Designing Supersystems with Dynamic Architectures
Efficient and Secure Storage Verification in Cloud-Assisted Industrial IoT Networks
A Logarithmic Transcoder
Optimal Routing in a Packet-Switched Computer Network
Understanding Why Correlation Profiling Improves the Predictability of Data Cache Misses in Nonnumeric Applications
Wearable Computers: A New Paradigm in Computer Systems and Their Applications
Optimizations Enabled by a Decoupled Front-End Architecture
A Layout System for the Random Logic Portion of an MOS LSI Chip
"Ideal" Directly Executed Languages: An Analytical Argument for Emulation
Solution of Linear Differential Equations with Variable Coefficients by the Electronic Differential Analyzer
A Method to Simplify a Boolean Function into a Near Minimal Sum-of-Products for Programmable Logic Arrays
Present and Future State-of-the-Art in Computer Memories
Micromultiprocessing: An Approach to Multiprocessing at the Level of Very Small Tasks
Suboptimal Sequential Decision Schemes With On-Line Feature Ordering
V-WAFA: An Endurance Variation Aware Fine-Grained Allocator for Persistent Memory
Self-Adjusting Networks for VLSI Simulation
Computer Simulation of the Electrical Properties of Memory Arrays
Powering by a Table Look-Up and a Multiplication with Operand Modification
Concurrent Application Bias Scheduling for Energy Efficiency of Heterogeneous Multi-Core Platforms
A Dynamically Reconfigurable System for Closed-Loop Measurements of Network Traffic
RRR: Rapid Ring Recovery Submillisecond Decentralized Recovery for Ethernet Ring
The Concept of Coverage and Its Effect on the Reliability Model of a Repairable System
On the Switching Activity and Static Test Compaction of Multicycle Scan-Based Tests
Minimum Storage Sorting Networks
Design and Evaluation of a Synchronous Triangular Interconnection Scheme for Interprocessor Communications
Design of Pseudoexhaustive Testable PLA with Low Overhead
Modeling Detection Latency with Collaborative Mobile Sensing Architecture
Enriched View Synchrony: A Programming Paradigm for Partitionable Asynchronous Distributed Systems
Humas: A Heterogeneity- and Upgrade-Aware Microservice Auto-Scaling Framework in Large-Scale Data Centers
A Numerical Procedure for Determination of the Prime Implicants of a Boolean Function
Complete Solution of Boolean Equations
A Class of Test Generators for Built-In Testing
IVP: An Intelligent Video Processing Architecture for Video Streaming
Calculation of Bayes' Recognition Error for Two Multivariate Gaussian Distributions
COBLOC-A Program for All-Digital Simulation of a Hybrid Computer
Accelerating Deep Neural Network In-Situ Training With Non-Volatile and Volatile Memory Based Hybrid Precision Synapses
TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems
B 74-26 Discrete Mathematical Structures and Their Applications
SOLߞA Symbolic Language for General-Purpose Systems Simulation
Big-Computing and Little-Storing STT-MRAM PIM Architecture With Charge Domain Based MAC Operation
Fast Parallel Algorithms for Binary Multiplication and Their Implementation on Systolic Architectures
Characterization of Binary Patterns and Their-Projections
Extraction of Connected Edges from Knee Radiographs
CHERI Concentrate: Practical Compressed Capabilities
Conditional Privacy-Preserving Transaction for the Unspent Transaction Output-Based Multi-Chain Blockchain System
Comments on "Interference Analysis of Shuffle/Exchange Networks"
Distributed Detection of Minimum Cuts in Wireless Multi-Hop Networks
A Communicating Finite Automata Approach to Modeling Distributed Computation and Its Application to Distributed Decision-Making
A Design for Directed Graphs with Minimum Diameter
An Analytical Model for Designing Memory Hierarchies
Efficient Determination of Maximum Incomplete Subcubes in Hypercubes with Faults
Adaptive Coding for Self-Clocking Recording
A Stable, Two-Multiplies-per-Cycle Algorithm for Digital Generation of Sinusoids in Real Time
Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining
DHTS: A Dynamic Hybrid Tiling Strategy for Optimizing Stencil Computation on GPUs
A Partitioning Method for Combinational Synthesis
A Random-Walk Model of a Queue Storage Problem
A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms
ForestDB: A Fast Key-Value Storage System for Variable-Length String Keys
Correction to "State-Space Methods for Designing Digital Simulations of Continuous Fixed Linear Systems"
Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes
Accelerating Finite-Field and Torus Fully Homomorphic Encryption via Compute-Enabled (S)RAM
Approximate DCT Image Compression Using Inexact Computing
A Simulation-Based Method for Generating Tests for Sequential Circuits
Modular Replacement of Combinational Switching Networks
A Pulse Position Modulation Analog Computer
On a Class of Multistage Interconnection Networks
Using Indexing Functions to Reduce Conflict Aliasing in Branch Prediction Tables
A Way to Find a Lower Bound for the Minimal Solution of the Covering Problem
An Adaptive Idle-Time Exploiting Method for Low Latency NAND Flash-Based Storage Devices
iAware: Making Live Migration of Virtual Machines Interference-Aware in the Cloud
The Autocorrelation Structure of Tausworthe Pseudorandom Number Generators
Enabling Fine-Grained Spatial Multitasking on Systolic-Array NPUs Using Dataflow Mirroring
A Heuristic Procedure for the Partitioning and Mapping of Computer Logic Graphs
Cache-Based Memory Copy Hardware Accelerator for Multicore Systems
LPAH: Illustrating Efficient Live Patching With Alignment Holes in Kernel Data
Self-Diagnosis of Faelures in VLSI Tree Array Processors
SpiNNaker - Programming Model
Correction to "Efficient Mapping of ANNs on Hypercube Massively Parallel Machines"
Analyzing Arm's MPAM From the Perspective of Time Predictability
A Two-Stage Deanonymization Attack against Anonymized Social Networks
Detecting Sneak Paths in Transistor Networks
A Radix-16 Combined Complex Division/Square Root Unit with Operand Prescaling
Pulse Powered Circuits
Design of a High-Speed Square Root Multiply and Divide Unit
Generalization of an Enhanced ECC Methodology for Low Power PSRAM
A Novel Heuristic Method for Application-Dependent Testing of a SRAM-Based FPGA Interconnect
A Method for the Determination of a Differential Equation Model for Simple Nonlinear Systems
Analysis and Synthesis of Dynamic Multicomputer Networks that Reconfigure into Rings, Trees, and Stars
Stochastic Optimal Control for Participatory Sensing Systems with Heterogenous Requests
Maximum Lifetime Broadcasting in Wireless Networks
Transistor characteristics for direct-coupled transistor logic circuits
Some Parametric Techniques in the Analog Solution of Ordinary Differential Equation
New Public-Key Cipher System Based Upon the Diophantine Equations
S-SMART++: A Low-Latency NoC Leveraging Speculative Bypass Requests
PETCAM - A Power Efficient TCAM Architecture for Forwarding Tables
Image Restoration, Modelling, and Reduction of Dimensionality
Optimal File Allocation in a Multiple Computer System
An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital Converter
New Analog-Computer Setup for a Bistable Element Permitting Symmetrical Triggering
On Scheduling Mesh-Structured Computations for Internet-Based Computing
An FPGA-Based Reconfigurable Mesh Many-Core
A Hybrid Quantum-Classical Approach to Mitigating Measurement Errors in Quantum Algorithms
Sparse-Insertion Write Cache to Mitigate Write Disturbance Errors in Phase Change Memory
DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores
DeyPoS: Deduplicatable Dynamic Proof of Storage for Multi-User Environments
A Memory-Efficient TCAM Coprocessor for IPv4/IPv6 Routing Table Update
Algebraic Properties of 3-Valued Compositions
Addition Related Arithmetic Operations via Controlled Transport of Charge
Public Integrity Auditing for Shared Dynamic Cloud Data with Group User Revocation
A Residue Number System Implementation of the LMS Algorithm Using Optical Waveguide Circuits
On Evaluating the Cumulative Performance Distribution of Fault-Tolerant Computer Systems
Diagnostic Keys as a Representation for Context in Pattern Recognition
Merging and Sorting Networks with the Topology of the Omega Network
Realization of Arbitrary Logical Functions Using Majority Elements
A New Empirical Test for the Quality of Random Integer Generators
An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems
Pulse Reflection in Transmission Lines
Optimal Chaining in Expression Trees
Some Variations of Lee's Algorithm
On the Equivalence of Cost Functions in the Design of Circuits by Costtable
SymPLFIED: Symbolic Program-Level Fault Injection and Error Detection Framework
New Transistorized Dc-Ac Amplitude Converter
High Performance Fault-Tolerant Digital Neural Networks
Handauth: Efficient Handover Authentication with Conditional Privacy for Wireless Networks
Minimum Cost Placement of Bistatic Radar Sensors for Belt Barrier Coverage
A High Speed and Accuracy Digital Gaussian Generator of Pseudorandom Numbers
An Analysis of Processor-Memory Interconnection Networks
Stochastic Neural Computation I: Computational Elements
Distributed Memory Compiler Design for Sparse Problems
Roll-Forward Checkpointing Scheme: A Novel Fault-Tolerant Architecture
A Many-Valued Algebra for Switching Systems
P-N-Π-N Triode Switching Applications
Integrated Devices Using Direct-Coupled Unipolar Transistor Logic
On a New Mechanism of Trigger Generation for Post-Silicon Debugging
Unsupervised Spiking Instance Segmentation on Event Data Using STDP Features
Design, Analysis and Implementation of a Novel Multiple Resource Scheduler
An Approach for Detecting Multiple Faulty FPGA Logic Blocks
Time-Space Tradeoffs on Back-to-Back FFT Algorithms
GATe: Efficient Graph Attention Network Acceleration With Near-Memory Processing
Private Inference for Deep Neural Networks: A Secure, Adaptive, and Efficient Realization
A Multiclass Priority-Based Slotted-Ring LAN and Its Analysis
Opportunistic Offloading of Deadline-Constrained Bulk Cellular Traffic in Vehicular DTNs
Global Optimization for Multi-Channel Wireless Data Broadcast with AH-Tree Indexing Scheme
An Energy-Efficient GPGPU Register File Architecture Using Racetrack Memory
Computer Languages for Symbol Manipulation
Thinning Schemes for Call Admission Control in Wireless Networks
WaFS: A Workflow-Aware File System for Effective Storage Utilization in the Cloud
Hardware Compressed Main Memory: Operating System Support and Performance Evaluation
Dynamically Restructurable Fault-Tolerant Processor Network Architectures
Memory-Link Compression Schemes: A Value Locality Perspective
Polynomial Time Testability of Circuits Generated by Input Decomposition
Multiple Stuck-Fault Detection and Location in Multivalued Linear Circuits
Enlarging Instruction Streams
Reliability Modeling for Fault-Tolerant Computers
Streaming BDD Manipulation
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)
RISC-V Custom Instructions of Elementary Functions for IoT Endpoint Devices
Novel Totally Self-Checking Berger Code Checker Designs Based on Generalized Berger Code Partitioning
Hardware Designs for Exactly Rounded Elemantary Functions
Algorithm-Based Fault Location and Recovery for Matrix Computations on Multiprocessor Systems
Optimal Assignments in Broadcast Networks
Testing Schemes for FIR Filter Structures
A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression
Empirical Exploration of the Performance of the Alpha Beta Tree-Searching Heuristic
Randomized Algorithms: A System-Level, Poly-Time Analysis of Robust Computation
Object-Level Memory Allocation and Migration in Hybrid Memory Systems
R70-30 Fuzzy Logic and Its Application to Switching Systems
Comments on "The Application of Filtered Transforms to the General Classification Problem"
Schedulability Analysis of Global Scheduling for Multicore Systems With Shared Caches
Modular Design of High-Throughput, Low-Latency Sorting Units
Design of Sequential Machines with Fault-Detection Capabilities
Automatic Checkout Systems for Titan III and Apollo Guidance Computer Programs