yusuke1997/dblp-id-title huggingface dataset:
The Reliability of a Fault-Tolerant Configuration Having Variable Coverage
Quality of Service Issues in Internet Web Services
Multiple Reflections on Pulse Signal Transmission Lines-Model for Computer Solution
Optimal Design of Multilevel Storage Hierarchies
Uncover Secrets Through the Cover: A Deep Learning-Based Side-Channel Attack Against Kyber Implementations With Anti-Tampering Covers
Energy-Efficient Floating-Point Unit Design
Systematic Scaling for Digital Differential Analyzers
Fault-Tolerant Single-Stage Interconnection Networks
Increasing Digital Computer Efficiency with the Aid of Error-Correcting Analog Subroutines
B74-10 Computer Semantics, Studies of Algorithms, Processors and Languages
On Information-Lossless Discrete-Time Systems
Testing SRAM-Based Content Addressable Memories
Synthesis of Minimal-State Machines
Deadline and Period Assignment for Update Transactions in Co-Scheduling Environment
Contextual Postprocessing System for Cooperation with a Multiple-Choice Character-Recognition System
Efficient VLSI Layouts for Homogeneous Product Networks
KPU: Kernel Processing Unit for in-Memory Analytical Query Processing
Energy Efficient Comparators for Superscalar Datapaths
On Wafer-Packing Problems
Autocorrelation Peaks in Congruential Pseudorandom Number Generators
An Efficient Byzantine-Resilient Tuple Space
A Method of Generating Functions of Several Variables Using Analog Diode Logic
Interactive Orthogonal Graph Drawing
Optimal Application Mapping and Scheduling for Network-on-Chips with Computation in STT-RAM Based Router
High-Performance Scalable Flash File System Using Virtual Metadata Storage with Phase-Change RAM
Approximating Rate-Distortion Graphs of Individual Data: Experiments in Lossy Compression and Denoising
Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs
Optimal Wiring of Movable Terminals
Enabling Fast and Memory-Efficient Acceleration for Pattern Matching Workloads: The Lightweight Automata Processing Engine
Dynamic Sparse Attention for Scalable Transformer Acceleration
A New Approach to 2-Asummability Testing
A Theory of Wormhole Routing in Parallel Computers
Localized Routing Approach to Bypass Holes in Wireless Sensor Networks
PackCache: An Online Cost-Driven Data Caching Algorithm in the Cloud
Performance/Power Space Exploration for Binary64 Division Units
A Sign Detector for a Group of Three-Moduli Sets
A Reduced-Area Scheme for Carry-Select Adders
An Idealized Over-All Error-Correcting Digital Computer Having Only an Error-Detecting Combinational Part
A Class of Binary Divisions Yielding Minimally Represented Quotients
A Comment on 'Graph-Based Algorithm for Boolean Function Manipulation'
B73-8 Systems Programming
Economical Iterative and Range-Transformation Schemes for Division
Modeling Toroidal Networks with the Gaussian Integers
Read-Only Memory Implementation of Discrete Function
Analysis and Simulation of Buffered Delta Networks
An experiment in musical composition
Use Bit Scanning in Replacement Decisions
Comments on "Parallel Processing Algorithms for the Optimal Control of Nonlinear Dynamic Systems"
New Self-Routing Permutation Networks
Wait-Free Programming for General Purpose Computations on Graphics Processors
Analysis of Periodic and Intermediate Boundary 90/150 Cellular Automata
RapidSnail: Improve Scalability of Blockchain Under High Contention Workload
The Application of Transistor Technology to Computers
Analog Solutions of Nonlinear Boundary-Value Problems by the Continuation Method
The Effect of Temperature on Amdahl Law in 3D Multicore Era
Computing Reliability Intervals for k-Resilient Protocols
Maintaining Data Freshness in Distributed Cyber-Physical Systems
Ozone (O3): An Out-of-Order Flash Memory Controller Architecture
Toward a Scalable Working Set Size Estimation Method and Its Application for Chip Multiprocessors
Low-Latency Digit-Serial Systolic Double Basis Multiplier over $\mbi GF{(2^m})$ Using Subquadratic Toeplitz Matrix-Vector Product Approach
Analog-Computer Simulation of a Frequency Detector
Loss of Significance in Floating Point Subtraction and Addition
R68-29 Hydro System Optimization Model
Multivariate TVLA - Efficient Side-Channel Evaluation Using Confidence Intervals
A Utilization Bound for Aperiodic Tasks and Priority Driven Scheduling
Guest Editorial: IEEE TC Special Section on Compiler Optimizations for FPGA-Based Systems
Modeling Energy-Time Trade-Offs in VLSI Computation
An Iterative Montgomery Modular Multiplication Algorithm With Low Area-Time Product
Some New Results on Average Worst Case Carry
Low Space Complexity Multiplication over Binary Fields with Dickson Polynomial Representation
Hybrid Solution of Partial Differential Equations
Modified Booth Modulo 2 n -1 Multipliers
Realization of Minimum Circuits with Two-Input Conservative Logic Elements
Beyond Amdahl's Law: An Objective Function That Links Multiprocessor Performance Gains to Delay and Energy
Randomized Quasi-Random Testing
Cryo-CACTI: Cryogenic-Aware CACTI for Cache Modeling Down to 10K in Advanced 7nm FinFETs
Practical Signature-Free Multivalued Validated Byzantine Agreement and Asynchronous Common Subset in Constant Time
On the Decomposition of Fuzzy Functions
Plated Wire Content-Addressable Memories with Bit-Steering Technique
A TCAM-Based Parallel Architecture for High-Speed Packet Forwarding
A Minimization Technique for Multiple-Valued Logic Systems
Some Topological Properties of Bitonic Sorters
On the Design of Three-Valued Asynchronous Modules
LSDedup: Layered Secure Deduplication for Cloud Storage
The Measurement of Performance on a Highly Parallel System
Complexity in Electronic Switching Circuits
Task Splitting and Load Balancing of Dynamic Real-Time Workloads for Semi-Partitioned EDF
A Universal STT State Assignment Method for Pulse Input Asynchronous Sequential Circuits
Optimizing the Length of Checking Sequences
Enumeration of Seven-Argument Threshold Functions
The Automatic Counting of Asbestos Fibers in Air Samples
An Architectural Framework for Runtime Optimization
Priority Assignment in a Network of Computers
Value of Information: A Comprehensive Metric for Client Selection in Federated Edge Learning
A Quantization Approximation for Modeling Computer Network Nodal Queueing Delay
MGARD+: Optimizing Multilevel Methods for Error-Bounded Scientific Data Reduction
An RNS Montgomery Modular Multiplication Algorithm
Delay-Constrained Multicast Routing Using the Noisy Chaotic Neural Networks
MDev-NVMe: Mediated Pass-Through NVMe Virtualization Solution With Adaptive Polling
Extending the Operational Time of Analog Integrators
Partition of Boolean Functions ror Realization with Multithreshold Threshold Logic Elements
Towards Hard Real-Time and Energy-Efficient Virtualization for Many-Core Embedded Systems
Stencils and Problem Partitionings: Their Influence on the Performance of Multiple Processor Systems
A Mapping Strategy for Parallel Processing
The Reliability of Systems with Two Levels of Fault Tolerance: The Return of the "Birthday Surprise"
Minimum Mean Running Time Function Generation Using Read-Only Memory
The Theory of Definite Automata
CSMT: Simultaneous Multithreading for Clustered VLIW Processors
A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields
An Absorbing Markov Chain Based Model to Solve Computation and Communication Tradeoff in GPU-Accelerated MDRUs for Safety Confirmation in Disaster Scenarios
A Fast Circulating Memory
Serial Array Time Slot Interchangers and Optical Implementations
DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs
Secure and Efficient Broadcast Authentication in Wireless Sensor Networks
Pseudo-Differential Sensing Framework for STT-MRAM: A Cross-Layer Perspective
On Synthesis of Easily Testable (k, K) Circuits
Testing by Verifying Walsh Coefficients
Analysis of a Crossed-Film Cryoton Shift Register
Logical Machine Design II: A Selected Bibliography
A Partitioning Algorithm with Application in Pattern Classification and the Optimization of Decision Trees
Fast Multiplication Without Carry-Propagate Addition
A Framework for Truthful Online Auctions in Cloud Computing with Heterogeneous User Demands
A Pipeline Design for the Realization of the Prime Factor Algorithm Using the Extended Diagonal Structure
A Performance Analysis of Minimum Laxity and Earliest Deadline Scheduling in a Real-Time System
Generalized Wiener Filtering Computation Techniques
Static and Dynamic Configurable Systems
Optimal Data Scheduling for Uniform Multidimensional Applications
Reducing Inerference Among Vector Accesses in Interleaved Memories
Optimal Parallelization of Single/Multi-Segment Real-Time Tasks for Global EDF
Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling
Linear Sum Codes for Random Access Memories
Guest Editors' Introduction: Special Section on Fault Diagnosis and Tolerance in Cryptography
Some Characterizations of Functions Computable in On-Line Arithmetic
Fault Diagnosis as a Graph Coloring Problem
Texture Characterization and Texture-Based Image Partitioning Using Two-Dimensional Linear Estimation Technique
An Optimal Discriminant Plane
Polygonal Approximations by Newton's Method
Comments on "The Buffer Behavior in Computer Communication Systems"
Traffic-Specific Interconnection Networks for Multicomputers
Stability of a Method of Smoothing in a Digital Control Computer
Fault Detection in Combinational Networks by Reed-Muller Transforms
A Readily Implemented Single-Error-Correcting Unit-Distance Counting Code
Performance Analysis of k-Ary n-Cube Interconnection Networks
Modeling the Weather with a Data Flow Supercomputer
Biological Computers
Comments on "Optimal Design of Distributed Information Systems"
Galaxy: An Elastic FaaS Control Plane for Highly-Scalable Instance Scheduling
FAWA: Fast Adversarial Watermark Attack
Comments on "Next-State Equations of Asynchronous Sequential Machines"
HW/SW Co-Design for Reliable TCAM- Based In-Memory Brain-Inspired Hyperdimensional Computing
On Improving Real-Time Interrupt Latencies of Hybrid Operating Systems with Two-Level Hardware Interrupts
DMA++: On the Fly Data Realignment for On-Chip Memories
D -Script: A Computational Theory of Descriptions
Efficient Embedded Software Migration towards Clusterized Distributed-Memory Architectures
Constructing Parallel Paths Betweesn Two Subcubes
Attribute-Based Access Control with Hidden Policies and Hidden Credentials
Using Horizontal Prefetching to Circumvent the Jump Problem
The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors
Numerical Technique for the Convolution of Piecewise Polynomial Functions
Increasing the Reliability of Software Timing Analysis for Cache-Based Processors
Smart ECC Allocation Cache Utilizing Cache Data Space
On Improving the Analog Computer Solutions of Linear Systems
An Adaptive CPU-GPU Governing Framework for Mobile Games on big.LITTLE Architectures
A Configurable Statistical Lossless Compression Core Based on Variable Order Markov Modeling and Arithmetic Coding
Model Checking Safety-Critical Systems Using Safecharts
The CrossoverNet LAN System Using an Intelligent Head-End
Microprogramming: An Introduction and a Viewpoint
A Highly Accurate Method for Assessing Reliability of Redundant Arrays of Inexpensive Disks (RAID)
Differential Fault Attack on HE-Friendly Stream Ciphers: Masta, Pasta, and Elisabeth
A High-Level Language for Horizontal Microprogramming
Worst-Case Analysis of a Resistor Memory Matrix
Flip-Flops for Multiple-Valued Logic
Natural, Dyadic, and Sequency Order Algorithms and Processors for the Walsh-Hadamard Transform
Spatial Reusability-Aware Routing in Multi-Hop Wireless Networks
On the Construction of (d, k) Graphs
Improving Networked File System Performance Using a Locality-Aware Cooperative Cache Protocol
A Hardware-Oriented Algorithm for Floating-Point Function Generation
Formalization of Protocol Engineering Concepts
Optimal BPC Permutations on a Cube Connected SIMD Computer
Processing Concurrent Graph Analytics with Decoupled Computation Model
Disjunctively Linear Logic Nets
Virtual Wall: Filtering Rootkit Attacks To Protect Linux Kernel Functions
TSE: Two-Step Elimination for MLC STT-RAM Last-Level Cache
Incentive Mechanisms for Community Sensing
The Design of Easily Tastabel VLSI Array Multipliers
A Critical Comparison of Two Kinds of Adaptive Classification Networks
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
Design Considerations for Single-Chip Computers of the Future
A Fast Asymmetric Extremum Content Defined Chunking Algorithm for Data Deduplication in Backup Storage Systems
Optimal Elections in Faulty Loop Networks and Applications
A Study of Refill Phenomena in Williams' Tube Memories
Topological Solution of Bilateral Switching Networks
Comment on "A Fundamental Error Theory for Analog Computers
Optimizing Contiguous-Element Region Selection for Virtual Memory Systems
Exploiting Buffered Updates for Fast Streaming Graph Analysis
Construction of a Generalized Connector with 5.8 n log 2 n Edges
Comments on "Discrete Cosine Transform"
Efficient Embeddings of Binary Trees in VLSI Arrays
Generalized Snake-in-the-Box Codes
A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation
The Representation and Matching of Pictorial Structures
Experiences with Performance Measurement and Modeling of a Processor Array
Optimal Design of Checks for Error Detection and Location in Fault-Tolerant Multiprocessor Systems
Boolean Network Probabilities and Network Design
A Slide Rule Device for Checking 2-Summability
Hierarchical Probabilistic Macromodeling for QCA Circuits
Synthesis of UP-DOWN Counters
An Optimal Algorithm for Assigning Cryptographic Keys to Control Access in a Hierarchy
COP: A Combinational Optimization Power Budgeting Method for Manycore Systems in Dark Silicon
Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations
On Separable Unordered Codes
CBANA: A Lightweight, Efficient, and Flexible Cache Behavior Analysis Framework
Scalable Dynamic Instruction Scheduler through Wake-Up Spatial Locality
Implementation of Four Common Functions on an LNS Co-Processor
STABLE: Stress-Aware Boolean Matching to Mitigate BTI-Induced SNM Reduction in SRAM-Based FPGAs
Improved Simulation of Pulse Propagation Between Digital Circuits
Hardware Assisted Fully Homomorphic Function Evaluation and Encrypted Search
Optimization of Teleprocessing Networks with Concentrators and Multiconnected Terminals
On the Performance of Interleaved Memories with Multiple-Word Bandwidths
A Note on Nondeterminism in Small, Fast Parallel Computers
GPS-Free, Boundary-Recognition-Free, and Reliable Double-Ruling-Based Information Brokerage Scheme in Wireless Sensor Networks
An Analog Method for the Solution of Probability of Hit and Related Statistical Problems
Performability Evaluation of Multipurpose Multiprocessor Systems: The "Separation of Concerns" Approach
FREM: A Fast Restart Mechanism for General Checkpoint/Restart
Correction [to "Symbolic Programming" by N. Rochester]
A Preliminary Evaluatin of Trace Scheduling for Global Microcode Compaction
The Two's Complement Quasi-Serial Multiplier
Exploring the Interplay between Computation and Communication in Distributed Real-Time Scheduling
Parallel Computer Architectures and Problem Solving Strategies for the Consistent Labeling Problem
Performance Analysis of Transaction Driven Computer Systems via Queueing Analysis of Polling Models
High-Speed Computer Multiplication Using a Multiple-Bit Decoding Algorithm
The Relative Merits of Minimization Techniques for Switching Circuits
HYTREM - A Hybrid Text-Retrieval Machine for Large Databases
Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems
Analysis of Server Provisioning for Distributed Interactive Applications
High-Speed Digital Multiplication
Arithmetic Algorithms in a Negative Base
Modular Minicomputers Using Microprocessors
Deep Learning-Based Cloud Security: Innovative Attack Detection and Privacy Focused Key Management
Mix-GEMM: Extending RISC-V CPUs for Energy-Efficient Mixed-Precision DNN Inference Using Binary Segmentation
Faster Key Compression for Isogeny-Based Cryptosystems
TE-Shave: Reducing Data Center Capital and Operating Expenses with Thermal Energy Storage
Hot-Spot Contention in Binary Hypercube Networks
A Simplified Summation Array for Cellular Logic Modules
Flip-Trees: Fault-Tolerant Graphs with Wide Containers
Error-Control Techniques for Logic Processors
Fast Arithmetic for Public-Key Algorithms in Galois Fields with Composite Exponents
Connectivity of Random Logic
A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields
Thank-You State of the Journal Editorial by the Outgoing Editor-in-Chief
An Optical/Digital Processor: Hardware and Applications
A Cube-Connected Cycles Architecture with High Reliability and Improved Performance
Multiprocessing Systems
Throughput Analysis of B-Networks
A Special Function Unit for Database Operations (SFU-DB): Design and Performance Evaluation
EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks
Converter Placement Supporting Broadcast in WDM Optical Networks
Big-Data Streaming Applications Scheduling Based on Staged Multi-Armed Bandits
An Ontology-Based Method for HW/SW Architecture Reconstruction
A Signal-Dependent Error Arising in Digitally Processed Images Due to Quantization
Adaptive Load Control of the Central Processor in a Distributed System with a Star Topology
Asynchronous Operation of an Iteratively Structured General-Purpose Digital Computer
Efficient Representation Scheme for Multidimensional Array Operations
Brain-Inspired Computing for Circuit Reliability Characterization
On the Memory Conflict Problem in Multiprocessor Systems
Design and Performance Evaluation of Queue-and-Rate-Adjustment Dynamic Load Balancing Policies for Distributed Networks
Optimizing DNNs With Partially Equivalent Transformations and Automated Corrections
Path Finding with Associative Memory
An Algorithm for the Accurate Reliability Evaluation of Triple Modular Redundancy Networks
Parallel Implementation of the Schur Belekamp-Massey Algorithm on a Linearly Connected Processor Array
Simplicity Versus Accuracy in a Model of Cache Coherency Overhead
Adaptive Pattern Recognition and Signal Detection Using Stochastic Approximation
A General Hardware-Oriented Method for Evaluation of Functions and Computations in a Digital Computer
Resource Conscious Diagnosis and Reconfiguration for NoC Permanent Faults
Multiple Fault Detection in Programmable Logic Arrays
A Discrete Logarithm Number System for Integer Arithmetic Modulo 2 k : Algorithms and Lookup Structures
Mapping Homogeneous Graphs on Linear Arrays
On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures
Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition
A Triangulation Method for the Sequential Mapping of Points from N -Space to Two-Space
Thermal Safe Power (TSP): Efficient Power Budgeting for Heterogeneous Manycore Systems in Dark Silicon
An operational-digital feedback divider
Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits
Improving Design Dependability by Exploiting an Open Model-Based Specification
HASP: Hierarchical Asynchronous Parallelism for Multi-NN Tasks
Computing System Failure Frequencies and Reliability Importance Measures Using OBDD
Stream: Design Space Exploration of Layer-Fused DNNs on Heterogeneous Dataflow Accelerators
The Jitter Model for Metastability and Its Application to Redundant Synchronizers
Batch-Fabricated Three-Dimensional Planar Coaxial Interconnections for Microelectronic Systems
Unate Cellular Logic
Uncovering the Intricacies and Synergies of Processor Microarchitecture Mechanisms Using Explainable AI
Optimizing Vertex Pressure Dynamic Graph Partitioning in Many-Core Systems
A Dual-Clock Multiple-Queue Shared Buffer
The Mixed-Radix Chinese Remainder Theorem and Its Applications to Residue Comparison
Configuring BlueStars: Multihop Scatternet Formation for Bluetooth Networks
Rate 1/2 and 2/3 Majority Logic Decodable Binary Burst Error-Correcting Codes
The BALLAST Methodology for Structured Partial Scan Design
Segmentation of Plane Curves
A Nonlinear Feature Extraction Algorithm Using Distance Transformation
Enhancing Graph Random Walk Acceleration via Efficient Dataflow and Hybrid Memory Architecture
Minimization by the D Algorithm
Foresighted Instruction Scheduling Under Timing Constraints
Comprehensive Testing of Multistage Interconnection Networks
Cascade-Parallel Decompositions of Sequential Machines
Optimality Study of Existing Quantum Computing Layout Synthesis Tools
FPC: A High-Speed Compressor for Double-Precision Floating-Point Data
Constructing a Message-Pruning Tree with Minimum Cost for Tracking Moving Objects in Wireless Sensor Networks Is NP-Complete and an Enhanced Data Aggregation Structure
Quantum Existence Testing and Its Application for Finding Extreme Values in Unsorted Databases
A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip
Scheduling for Overload in Real-Time Systems
Strongly Diagnosable Product Networks Under the Comparison Diagnosis Model
Overflow/Underflow-Free Floating-Point Number Representations with Self-Delimiting Variable-Length Exponent Field
Multigate Synthesis of General Boolean Functions by Threshold Logic Elements
Evaluating Reliability Improvements of Fault Tolerant Array Processors Using Algorithm-Based Fault Tolerance
Pseudo-Boolean Logic Circuits
Precise Scientific Computation with a Microprocessor
Velocity Analysis: An Application of Deterministic Estimation to Reflection Seismology
A Note on Radially Moore Digraphs
Buffer Behavior for Poisson Arrivals and Multiple Synchronous Constant Outputs
Efficient Software-Based Encoding and Decoding of BCH Codes
A Wireless Interconnection Framework for Seamless Inter and Intra-Chip Communication in Multichip Systems
Design and Evaluation of a Fault-Tolerant Multiprocessur Using Hardware Recovery Blocks
Fault Diagnosis of RAM's from Random Testing Experiments
Dandelion: Boosting DNN Usability Under Dataset Scarcity
A Computer Organization and Programming System for Automated Maintenance
Design for Testability - A Survey
Circ-Tree: A B+-Tree Variant With Circular Design for Persistent Memory
Soft Error Effects on Arm Microprocessors: Early Estimations versus Chip Measurements
Fast Deep Packet Inspection with a Dual Finite Automata
Modulo 3 Residue Checker: New Results on Performance and Cost
A Ternary Storage Element Using a Conventional Ferrite Core
A Functional Approach to Testing Bit-Sliced Microprocessors
Fast and Efficient Circuit Topologies forFinding the Maximum of n k-Bit Numbers
Energy-Efficient Permanent Fault Tolerance in Hard Real-Time Systems
Introducing a New Cache Design into Vector Computers
More Efficient Use of the F Matrix in Practical Circuit Analysis Programs
Minimal Input Solutions
An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders
A Programmable Dynamic Memory Allocation System for Input/Output of Digital Data into Standard Computer Memories at 40 Megasamples/s
Digital Image Registration Method Using Boundary Maps
Comparison of Single- and Dual-Pass Multiply-Add Fused Floating-Point Units
The Necessity of Feedback in Minimal Monotone Combinational Circuits
Decomposing Banyan Networks for Performance Analysis
The Identification of Maximal Parallelism in Straight-Line Microprograms
DFSP: A Data Flow Signal Processor
The Computer System Issue
Technology Scaling Effects on Multipliers
Deno: A Decentralized, Peer-to-Peer Object-Replication System for Weakly Connected Environments
Complexity Analysis of Checkpoint Scheduling with Variable Costs
Towards Adaptive Parallel Storage Systems
Reliability Modeling of Compensating Module Failures in Majority Voted Redundancy
A Search Technique for Clause Interconnectivity Graphs
Special-Purpose Computer Organization for Double-Precision Realization of Digital Filters
Precomputation Methods for Hash-Based Signatures on Energy-Harvesting Platforms