yusuke1997/dblp-id-title huggingface dataset:
Design of a low-power CMOS transceiver for semi-passive wireless sensor network application
An efficient image encryption scheme based on double affine substitution box and chaotic system
A hybrid entropy source scheme for true random number generator
Automatic correction of RTL designs using a lightweight partial high level synthesis
Variable radix-2 multibit coding for 400 Mpixel/s DCT/IDCT of HDTV video decoder
A CAFVF-based output-capacitor-less LDO with PSRR improvement by feed forward and negative capacitance
A three-layer over-the-cell multi-channel router for a new cell model
An efficient tool for the assisted design of SAR ADCs capacitive DACs
Power Gated-SRAM and novel header-footer multiplexer based ultra low power Look-Up Table design
Low power current-mode hybrid computing architecture signal processing circuit
Hierarchical power management of a system with autonomously power-managed components using reinforcement learning
Memory customisations for image processing applications targeting MPSoCs
Dynamical behaviors of the simple chaotic system with coexisting attractors and its synchronous application
Synthesis of resonance-based common-gate fully differential band-pass filters
A reversible carry-look-ahead adder using control gates
Low-temperature-drift voltage reference design using magnetic tunnel junctions
Mixed-radix, virtually scaling-free CORDIC algorithm based rotator for DSP applications
An improved circuit-partitioning algorithm based on min-cut equivalence relation
Neurochaos feature transformation for Machine Learning
A folded-cascode mixer for mixing-spur suppressions in a 2.4-to-5.8 GHz transmitter
Resource-efficient and ultra-high throughput LDPC decoder for CCSDS near-earth standard
A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic
Collision-free arbitrary-order chaotic path generator for differential robots
A reference sampling ΔΣ subsampling PLL
Reconfigurable multi-mode sigma-delta modulator for 4G mobile terminals
Low-cost methodology for fault diagnosis and localization in pipelined ADCs
A PSRR enhanced capacitorless LDO with gate capacitance cancellation technique
Synthesis of biochemical applications on digital microfluidic biochips with operation execution time variability
Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints
A precision low-power analog front end in 180 nm CMOS for wireless implantable capacitive pressure sensors
A low-voltage MOS translinear loop, biased using FVF and its applications in realizing square-rooter and squarer circuits
All pass transformation based variable digital filter design using low power approximate floating point adder and low power compressor based approximate multiplier
Efficient algorithms for fast IR drop analysis exploiting locality
Design exploration of a Symmetric Pass Gate Adiabatic Logic for energy-efficient and secure hardware
Design of a SRAM memory cell with enhanced stability and variability for embedded biomedical applications
gm/ID methodology applied to ring oscillators
VLSI for the new era
A pre-placement individual net length estimation model and an application for modern circuits
Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis
Very compact 3D-printed folded branch-line hybrid coupler based on loaded helical-microstrip transmission lines
Predictive analysis of energy dissipation in Layered-T QCA circuits under cell displacement defects and polarization: A machine-learning approach
IP and design reuse
Configurable memristive logic block for memristive-based FPGA architectures
A fuzzy search block-matching chip for motion estimation
Generation of representative input vectors for parametric designs: from low precision to high precision
Low power active shunt feedback CMOS low noise amplifier for wideband wireless systems
CMOS VLSI circuits of pipeline sections for 32 and 64-point Fermat number transformers
A fast temperature-aware fixed-outline floorplanning framework using convex optimization
Design of high-speed two-stage cascode-compensated operational amplifiers based on settling time and open-loop parameters
A 28-GHz wideband power amplifier with dual-pole tuning superposition technique in 55-nm RF CMOS
A novel low power hybrid cache using GC-EDRAM cells
Network traffic inspection to enhance anomaly detection in the Internet of Things using attention-driven Deep Learning
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations
A loadless 6T SRAM cell for sub- & near- threshold operation implemented in 28 nm FD-SOI CMOS technology
CPCA: An efficient wireless routing algorithm in WiNoC for cross path congestion awareness
A novel dual mode configurable and tunable high-gain, high-efficient CMOS power amplifier for 5G applications
High-speed full adder based on minority function and bridge style for nanoscale
Systolic multiplier for Montgomery's algorithm
Fixed-point implementations for feed-forward artificial neural networks
A biphasic current-mode stimulator integrated circuit with a novel residual charge compensation mechanism
LBDR: A load-balanced deadlock-free routing strategy for chiplet systems
Self-Organized Sub-bank SHE-MRAM-based LLC: An energy-efficient and variation-immune read and write architecture
Cell-based interconnect migration by hierarchical optimization
Special issue on System-Level Interconnect Prediction
Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer
Applying stochastic modeling to bus arbitration for systems-on-chip
Power density aware application mapping in mesh-based network-on-chip architecture: An evolutionary multi-objective approach
Efficient and cost-effective maximum power point tracking technique for solar photovoltaic systems with Li-ion battery charging
Fault detection in TFCMOS/DFCMOS combinational gates
ARS-Flow 2.0: An enhanced design space exploration flow for accelerator-rich system based on active learning
A non-autonomous chaotic system with no equilibrium
Multi-objective algebraic rewriting in XOR-majority graphs
Statistical traffic pattern for mixed torus topology and pathfinder based traffic and thermal aware routing protocol on NoC
Electronically tunable third-order dual-mode quadrature sinusoidal oscillators employing VDCCs and all grounded components
FPGA implementation of a chaotic oscillator with odd/even symmetry and its application
Image encryption/decryption accelerator based on Fast Cosine Number Transform
Switched pseudo-current mirror inverter for low-power, thermally stable and robust ring oscillator
A quadrature RC-oscillator with capacitive coupling
An LA-group based design of the non-linear component of block cipher
Method for designing two levels RNS reverse converters for large dynamic ranges
Analysis of a linearly constrained least squares algorithm for adaptive beamforming
Fault tolerance in memristive crossbar-based neuromorphic computing systems
Resource-efficient hardware architecture for low-light image enhancement
Methods for evaluating and covering the design space during early design development
Matching constraint extraction for analog integrated circuits layout via edge classify
Delay caused by resistive opens in interconnecting lines
Fast multidimensional optimization of analog circuits initiated by monodimensional global Peano explorations
Standard-compliant parallel SystemC simulation of loosely-timed transaction level models: From baremetal to Linux-based applications support
Construction and implementation of discrete memristive hyperchaotic map with hidden attractors and self-excited attractors
New methods for coloring and clique partitioning in data path allocation
A low dropout regulator design with 20.4 μA quiescent current and high power supply rejection
Microprogramming implementation of timed Petri nets
On programming VLSI concurrent array processors
A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS
Hybrid TFET-MOSFET circuit: A solution to design soft-error resilient ultra-low power digital circuit
Reinforcement learning in integrated circuits: Design, synthesis, layout, and hardware security
Designing soft-edge flip-flop-based linear pipelines operating in multiple supply voltage regimes
Quaternary to binary bit conversion CMOS integrated circuit design using multiple-input floating gate MOSFETS
ANAS: Software-hardware co-design of approximate neural network accelerators via neural architecture search
High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator
Automatic generation of harmonious music using cellular automata based hardware design
A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link
A hardware accelerator for hierarchical VLSI routing
A computer-aided design framework for modeling and simulation of VLSI interconnections and packaging
Aging mitigation of L1 cache by exchanging instruction and data caches
A very fast multiplication algorithm for VLSI implementation
High-performance area-efficient polynomial ring processor for CRYSTALS-Kyber on FPGAs
A low-overhead and high-reliability physical unclonable function (PUF) for cryptography
A parametric VLSI architecture for video motion estimation
Power-efficient ReRAM-aware CNN model generation
Analysis of frequency and amplitude in CMOS differential ring oscillators
Robust power grid network design considering EM aging effects for multi-segment wires
Full-chip leakage analysis for 65 nm CMOS technology and beyond
Physical design for microfluidic biochips considering actual volume management and channel storage
Enhancement of test data compression with multistage encoding
Efficient IC hotspot thermal analysis via low-rank Model Order Reduction
A recursive design methodology for VLSI: Theory and example
Reliability-aware design of Integrate-and-Fire silicon neurons
Analysis of a new three-dimensional jerk chaotic system with transient chaos and its adaptive backstepping synchronous control
VLSI design of 1-D DWT architecture with parallel filters
A generalized numerical method for ferrite inductors analysis in high current ripple operation
VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000
Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application
Integrated circuit packaging review with an emphasis on 3D packaging
A hybrid equivalent source - particle swarm optimization model for accurate near-field to far-field conversion
A hybrid method for signal probability and reliability estimation with combinational circuits
Logic-level mapping of high-level faults
An automated parallel simulation flow for cyber-physical system design
VDTA and DO-CCII based incremental/decremental floating memductance/meminductance simulator: A novel realization
Semantics of a hardware specification language and related transformation rules
Flexible design and implementation of QC-Based LDPC decoder architecture for on-line user-defined matrix downloading and efficient decoding
Construction of algebraic complex 9-bit lookup tables using non-chain-ring and its applications in data security
Comparison of QMC-based yield-aware pareto front techniques for multi-objective robust analog synthesis
iCETD: An improved tag generation design for memory data authentication in embedded processor systems
Read operation performance of large selectorless cross-point array with self-rectifying memristive device
RapidPnR: Accelerating the physical design for FPGAs via design-level parallelism
Partitioning and floor-planning for data-path chip (microprocessor) layout
Improving performance of FPGA-based SR-latch PUF using Transient Effect Ring Oscillator and programmable delay lines
Assignment of inter-die signals in a simplified wiring model for die-stacking SiP designs
An efficient channel clustering and flow rate allocation algorithm for non-uniform microfluidic cooling of 3D integrated circuits
Low-complex processing element architecture for successive cancellation decoder
Security-oriented printed-circuit-board routing with deep reinforcement learning
A new multi-scroll Chua's circuit with composite hyperbolic tangent-cubic nonlinearity: Complex dynamics, Hardware implementation and Image encryption application
A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme
Design and implementation of a digital down/up conversion directly from/to RF channels in HDL
A battery-less BLE smart sensor for room occupancy tracking supplied by 2.45-GHz wireless power transfer
Probability-driven routing in a datapath environment
Lagrangian relaxation-based routing path allocation for application-specific network-on-chips
An exquisitely sensitive variant-conscious post-silicon Hardware Trojan detection
Delay based hardware Trojan detection exploiting spatial correlations to suppress variations
Scheduling and optimal voltage selection with multiple supply voltages under resource constraints
True random number generator design based on the fractional-order Sprott H chaotic system with statistical validation
Low area/power decimal addition with carry-select correction and carry-select sum-digits
Mirroring: a technique for pipelining semi-systolic and systolic arrays
Optimization of programmable logic arrays
A new technique for IDDQ testing in nanometer technologies
Implementation of a fast maximum-likelihood decoding algorithm for the extended Nordstrom-Robinson code
Efficient design of decimation filter using linear programming and its FPGA implementation
SafeResynth: A new technique for physical synthesis
Special issue on IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2016
Quantitative comparison and performance evaluation of deep learning-based object detection models on edge computing devices
Non-equilibrium oscillator with a diode: Dynamics and application
Advanced fault detection and localization in cross-referencing digital micro-fluidic biochips
Systolic Galois field exponentiation in a multiple-valued logic technique
Three-dimensional switchbox multiplexing in emerging 3D-FPGAs to reduce chip footprint and improve TSV usage
Metastability immune and area efficient error masking flip-flop for timing error resilient designs
New approach to design for reusability of arithmetic cores in systems-on-chip
Data path synthesis
Design of an output-capacitorless low-dropout regulator with high-pass feed-forward compensation
An on-chip temperature sensor with 0.5 °C resolution and 0.34% linearity error using 180-nm CMOS process
Hardware-assisted Verilog simulation system using an application specific microprocessor
mMIG: Inversion optimization in majority inverter graph with minority operations
A CMOS rectified linear unit operating in weak inversion for memristive neuromorphic circuits
ACE: A congestion estimator for wiring custom chips
Algorithms for permutation channel routing
An inductorless wideband common-gate LNA with dual capacitor cross-coupled feedback and negative impedance techniques
Generating more compactable channel routing solutions
Innovative nonlinear component generator inspired by squirrel search algorithm
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
Statistical full-chip total power estimation considering spatially correlated process variations
A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer
Energy estimation in SystemC with Powersim
GATOR: A Graph Neural Network based Design Anomaly Predictor
ANTIGONE: Top-down creation of analog-to-digital converter architectures
A greedy switch-box router
Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs
Fully redundant decimal addition and subtraction using stored-unibit encoding
Fast algorithms for test optimization of core based 3D SoC
A new 4D Memristor chaotic system: Analysis and implementation
Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs
A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects
Lightweight high-throughput true random number generator based on state switchable ring oscillator
Giant Spin-Hall assisted STT-RAM and logic design
Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing
CMOS Analog Rank Order Filters using positive feedback comparators
LA-ring based non-linear components: Application to image security
Design of novel SMS4-BSK encryption transmission system
Optimization of the dielectric layer for electrowetting on dielectric
Design of novel low cost triple-node-upset self-recoverable hardened latch
Enumerating catastrophic fault patterns in VLSI arrays with both uni- and bidirectional links
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths
A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback
Double-node-upset-hardened full-subtractor applying MTJ for the high energy physics experiments
Bus-driven floorplanning with bus pin assignment and deviation minimization
Computation of capacitance matrix for integrated circuit interconnects using semi-analytic Green's function method
Indirect test of M-S circuits using multiple specification band guarding
Algorithm and hardware implementation for visual perception system in autonomous vehicle: A survey
Exploiting bounds optimization for the semi-formal verification of analog circuits
An adaptive simulation framework for AMS-RF test quality
Directly performance-constrained template-based layout retargeting and optimization for analog integrated circuits
FAST: FFT ASIC automated synthesis
A low-power fast tag comparator by modifying charging scheme of wide fan-in dynamic OR gates
Design and analysis of sum-prediction adder
Contributions to VLSI computational complexity theory from bounds on current density
The effect of gate voltage boosting on the power efficiency of multi-context FPGAs
Scaling of analog LDPC decoders in sub-100 nm CMOS processes
An efficient numerical simulation method based on practical 1T1R devices measurement for compute in memory chip design
Comments on "Dual-rail asynchronous logic multi-level implementation"
Partial evaluation based triple modular redundancy for single event upset mitigation
A differential in-memory computing 12T SRAM macro with enhanced flexibility and reliability for XNOR-network
A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC
VLSI circuit reconstruction from mask topology
On VLSI design of rank-order filtering using DCRAM architecture
On Minimizing Charge Injection Error Using Multi-Dummy Switches With Enhanced Linearity
Exploratory design of on-chip power delivery for 14, 10, and 7 nm and beyond FinFET ICs
Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFET technologies due to atmospheric radiation
Efficient modulo 2 n ±1 squarers
On-chip oscillator based temperature-to-digital converter exploiting channel length modulation coefficient λ
Boolean satisfiability and equivalence checking using general Binary Decision Diagrams
VLSI systolic arrays for band matrix multiplication
Design-time exploration of voltage switching against power analysis attacks in 14 nm FinFET technology
A complete testing strategy based on interacting and hierarchical FSMs
An accurate model for the transient simulation of lossy interconnects based on a novel discretization formula
Optimized mapping algorithm to extend lifetime of both NoC and cores in many-core system
CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications
An analysis of ternary simulation as a tool for race detection in digital MOS circuits
Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis
A logic device based on memristor-diode crossbar and CMOS periphery as spike router for hardware neural network
High-level parameterizable area estimation modeling for ASIC designs
Testing with decision diagrams
Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms
Experimental analysis of irregularly shaped octagonal on-chip inductors for improving area-efficiency in CMOS RFICs for millimeter wave applications
Multiplication/ division/ square root module for massively parallel computers
A contribution towards model-based design of application-specific MEMS
Dingo-XT: A technology description language for analog and digital IC layout
Heuristic circuit simulation using PROLOG
A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration
Architectures and algorithms for on-device user customization of CNNs
O.O: Optimized one-die placement for face-to-face bonded 3D ICs
Hybrid offset compensated latch-type sense amplifier for tri-gated FinFET technology
A fully integrated 23.2dBm P 1dB CMOS power amplifier for the IEEE 802.11a with 29% PAE
Some results on the design of regular structured sequential circuits
A routing framework for technology migration with bump encroachment
Semi-supervised lithography hotspot detection based on feature fusion and residual attention
VLSI implementations of number theoretic techniques in signal processing
Design and practical implementation of a novel hyperchaotic system generator based on Apéry's constant
SmipRef: An efficient method for multi-domain clock skew scheduling
High-performance FIR filter designs using Brent Kung Adder and pipelined Vedic multiplier
Impact of technology scaling on the tuning range and phase noise of mm-wave CMOS LC-VCOs
High Throughput Asynchronous NoC Design under High Process Variation
PV-MAC: Multiply-and-accumulate unit structure exploiting precision variability in on-device convolutional neural networks
Mixed-cell-height legalization considering complex minimum width constraints and half-row fragmentation effect
Dynamic differential self-timed logic families for robust and low-power security ICs
Detection of counterfeited ICs via on-chip sensor and post-fabrication authentication policy
A hardened network-on-chip design using runtime hardware Trojan mitigation methods
SPICE Rack - the newsletter of the SPICE users group : Volume 4, number 1, fall 1985
History-based dynamic BDD minimization
A reconfigurable wiring algorithm for three-layer maze routing
Automating the design of systolic arrays
PIXAR: A performance-driven X-architecture router based on a novel multilevel framework
An optimal energy co-scheduling framework for smart buildings
On the testability of iterative logic arrays
Finite-point method for efficient timing characterization of sequential elements
A novel low-power full-adder cell for low voltage
Design automation for continuous-flow microfluidic biochips: A comprehensive review
A closer look at VLSI multiplication
Spherical chaotic trajectory tracking and formation of unmanned aerial vehicles in master-slave configuration with intermediary system
Automated path selection technique while incorporating multiple assay operations and cross-contamination avoidance in cross-referencing DMFBs
Exact custom instruction enumeration for extensible processors
Neural network ℒ1 adaptive control for a class of uncertain fractional order nonlinear systems
Third-order nonlinearity vs. load impedance for CMOS low-noise amplifiers
FTROM: A Silicon Compiler for Fault-tolerant ROMs
Incremental algorithms for digital simulation
Reveal the correlation between randomness and Lyapunov exponent of n -dimensional non-degenerate hyper chaotic map
A low-voltage and low-power PLL for Sub-GHz IoT applications
Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries
A high precise E-nose for daily indoor air quality monitoring in living environment
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm
High-level test synthesis: a survey