yusuke1997/dblp-id-title huggingface dataset:
Novel logic and memory synthesis algorithm for Memristive Hardware Description Language (HDL)
SyReC: A hardware description language for the specification and synthesis of reversible circuits
A new CMOS wideband low noise amplifier with gain control
VLSI implementation of an M-array image filter based on shift register array
Accelerating Deep Convolutional Neural Network base on stochastic computing
Digital synchronization of the MACM chaotic system by using PIC24-microcontrollers and the SPI-protocol
High accurate approximate adders using hybrid gates
On-chip implementation of a low-latency bit-accurate reciprocal square root unit
Wire shaping of RLC interconnects
A highly dependable self-adaptive mixed-signal multi-core system-on-chip architecture
A fast model for analysis and improvement of gate-level circuit reliability
A high-performance convolution block oriented accelerator for MBConv-Based CNNs
Data-path aware high-level ECO synthesis
A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow
Establishing latch correspondence for sequential circuits using distinguishing signatures
Power-performance enhancement of two-dimensional RNS-based DWT image processor using static voltage scaling
CMOS multifunctional structure, with applications in analog signal processing
A low-power dynamic comparator for low-offset applications
A high isolation 16-19 GHz down-conversion mixer in 0.18-μm SiGe Bi-CMOS
A wide speed range and high precision position and velocity measurements chip with serial peripheral interface
READ: A fixed restoring array based accuracy-configurable approximate divider for energy efficiency
Modelling and design of asynchronous receptive circuit for cone pathways
A flexible hierarchical piecewise linear simulator
A 0.2-V 1.2 nW 1-KS/s SAR ADC with a novel comparator structure for biomedical applications
Adaptive power gating of 32-bit Kogge Stone adder
A BDD-based verification method for large synthesized circuits
Single-pair bulk-driven CMOS input stage: A compact low-voltage analog cell for scaled technologies
The art of temporal decoupling
In-sensor time-domain classifiers using pseudo sigmoid activation functions
Untrimmed 6.2 ppm/°C bulk-isolated curvature-corrected bandgap voltage reference
MOS based pseudo-resistors exhibiting Tera Ohms of Incremental Resistance for biomedical applications: Analysis and proof of concept
On the analysis and optimization of selftimed processor arrays
Quantitative simulations of Spiking Neural Networks on an event-driven FPGA cluster
A new control strategy for an artificial intelligence approach to VLSI layout compaction
Measuring the uniqueness and variety of analog circuit design features
Exploring N 3 ASIC technology for microwave imaging architectures
Corrigendum to "High throughput asynchronous NoC design under high process variation" [Integr. VLSI J. (2015) 1-13]
A design space exploration methodology for customizing on-chip communication architectures: Towards fractal NoCs
An integrated 2D systolic array for spelling correction
Electronic equivalent of a pump-modulated erbium-doped fiber laser
Deep reinforcement learning assisted reticle floorplanning with rectilinear polygon modules for multiple-project wafer
Low discharge precharge free matchline structure for energy-efficient search using CAM
Hierarchical rotated binary placement for nonlinearity reduction in digital-to-analog converters
A framework for post-disaster communication using wireless ad hoc networks
Detailed placement for pulse quenching enhancement in anti-radiation combinational circuit design
Simulation and design of an UWB imaging system for breast cancer detection
A low power SAR ADC with fine-tuned time based adaptive sampling technique for ECG monitoring application in 180 nm CMOS
A constant loop bandwidth in delta sigma fractional-N PLL frequency synthesizer with phase noise cancellation
On the design of a high-performance, expandable, sorting engine
A secure scan architecture using parallel latch-based lock
Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach
A bandwidth enhancement method of VTA based on paralleled memory access design
Memristor-cascaded hopfield neural network with attractor scroll growth and STM32 hardware experiment
Energy efficient EEG acquisition and reconstruction for a Wireless Body Area Network
A low-overhead and reliable switch architecture for Network-on-Chips
A hybrid approach for the sensitivity analysis of integrated inductors
Mixed-criticality scheduling on heterogeneous multicore systems powered by energy harvesting
A formal model for proving hardware timing properties and identifying timing channels
Synchronization of fractional-order chaotic networks in Presnov form via homogeneous controllers
A novel hybrid static offset voltage calibration technique for dynamic comparators using bulk voltage and shunt current trimming techniques
A unified approach for scheduling and allocation
Using ANNs to predict the evolution of spectrum occupancy in cognitive-radio systems
Low power synthesizable register files for processor and IP cores
Enhancing sensitivity-based power reduction for an industry IC design context
DAGNN-RE: Directed acyclic graph neural network for functional reverse engineering of gate-level netlist
A novel low-hardware-cost scan chain architecture resilient to scanSAT attack
On reverse converters for arbitrary multi-moduli RNS
A fast force-directed simulated annealing for 3D IC partitioning
Assignment and allocation of highly testable data paths under scan optimization
Sensor based adaptive voltage scaling on FPGAs: Calibration and parametrization
Optimized FPGA-based elliptic curve cryptography processor for high-speed applications
Run-time management of systems with partially reconfigurable FPGAs
Wave-pipelined intra-chip signaling for on-FPGA communications
PASSIOT: A Pareto-optimal multi-objective optimization approach for synthesis of analog circuits using Sobol' indices-based engine
A novel switchable pin method for regulating power in chip-multiprocessor
Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications
3D thermal-aware floorplanner using a MOEA approximation
VLSI with a very low scale investment
A fast approach for bitcoin blockchain cryptocurrency mining system
A fast transient response capless low-dropout regulator with NMOS-FVF structure
A test set embedding approach based on twisted-ring counter with few seeds
Reconfigurable DeltaSigma modulator topology design through hierarchical mapping and constraint extraction
An embedded, FPGA-based computer graphics coprocessor with native geometric algebra support
Multi-mode parallel and folded VLSI architectures for 1D-fast Fourier transform
Efficient processor verification by tautologies-derived universal properties model checking
Stochastic-based placement template generator for analog IC layout-aware synthesis
Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC
Capacitor matching insensitive algorithmic ADC requiring no calibrations
Flexible optimal channel routing for critical nets
New lightweight Anti-SAT block design and obfuscation technique to thwart removal attack
A 10T SRAM architecture with 40 % enhanced throughput for IMC applications benchmarked with CIFAR-10 dataset
Achieving optimality for gate matrix layout and PLA folding: a graph theoretic approach
Electromigration-aware analog Router with multilayer multiport terminal structures
Universal syndrome-testable design of programmable logic arrays
Deep learning aided efficient yield analysis for multi-objective analog integrated circuit synthesis
An innovative HLS framework for all network architectures: From Python to SoC
Content-addressable memory core cells A survey
A very low output resistance and wide-swing class-AB level-shifted folded flipped voltage follower cell
Modified restoring array-based power efficient approximate square root circuit and its application
IDDQ testing: state of the art and future trends
A variable frequency link for a power-aware network-on-chip (NoC)
Several weaknesses of the implementation for the theoretically secure masking schemes under ISW framework
A broadband low-noise VCO circuit based on a hybrid analog-digital control loop
A systolic algorithm for block-regularized RLS identification
Assessing partitioning/ scheduling/storage trade-offs for regular iterative algorithms
A VLSI router design for hypercube multiprocessors
Temperature and data size trade-off in dictionary based test data compression
Simulation environment for link energy estimation in networks-on-chip with virtual channels
Hop-CIM: An all-digital two-level approximate SRAM-CIM macro for high energy-efficient HNN acceleration with data-aware early exit and column-wise partial-sum reuse
Time-domain writing architecture for multilevel RRAM cells resilient to temperature and process variations
Op-Amp sizing via behavioral constraint generation and Gm/ID sampling
Two-phase synchronization with sub-cycle latency
2.3-21 GHz broadband and high linearity distributed low noise amplifier
Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures
A parallel VLSI architecture of Kalman-filter-based algorithms for signal reconstruction
A new three-dimensional conservative system with non - Hamiltonian energy and its synchronization application
Computer vision algorithms and hardware implementations: A survey
FPGA implementations of the ICEBERG block cipher
Synthesis of low-power CMOS circuits using hybrid topologies
Compact low-power implementation for continuous-time ΣΔ modulators
Symmetric synchronization behavior of multistable chaotic systems and circuits in attractive and repulsive couplings
Metro-on-FPGA: A feasible solution to improve the congestion and routing resource management in future FPGAs
Fast-response low-ripple envelope follower
Lossless grounded capacitance multipliers using two CFOAs and a grounded capacitor
On-chip charge pump design for 3D non-volatile flash memory: from industry perspective
Approximate multipliers based on a novel unbiased approximate 4-2 compressor
Minimizing the dynamic and sub-threshold leakage power consumption using least leakage vector-assisted technology mapping
The Post Office experience: designing a large asynchronous chip
A high-efficiency charge pump with charge recycling scheme and finger boost capacitor
Fully hardware based WFQ architecture for high-speed QoS packet scheduling
Jitter tolerance calibration for high-speed serial interfaces
Low power wide gates for modern power efficient processors
Module grouping to reduce the area of test wrappers in SoCs
System-level synthesis of multi-ASIP platforms using an uncertainty model
Boundary optimization of buffered clock trees for low power
Genetic algorithm-optimized fuzzy controller for the calibration of pipelined ADCs
High performance energy efficient radiation hardened latch for low voltage applications
Optimal two-terminal α-β wire routing
Combinatorial cell design for CMOS libraries
BonnLogic: Delay optimization by And-Or Path restructuring
Information flow in VLSI design
Exploiting distribution of unknown values in test responses to optimize test output compactors
Design of a low-power, low-PDP dual modulus CML frequency divider for ZigBee application
Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach
Synthesis of Dual Mode Logic
Strategies for the integration of hardware and software IP components in embedded systems-on-chip
Current-flow and current-density-aware multi-objective optimization of analog IC placement
VLFF - A very low-power flip-flop with only two clock transistors
Design of a real-time face detection architecture for heterogeneous systems-on-chips
On circuit developments to enable large scale circuit design while computing with noise
Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction
A survey on attack vectors in stack cache memory
A VLSI system for string matching
Reducing idle time in event-triggered software execution via runnable migration and DPM-Aware scheduling
Design of an adaptive winner takes all circuit explaining features of binocular rivalry in visual brain
FSMformer: An efficient direction-aware graph transformer for state register detection of gate-level netlist
Scalable parallel processor array for Jacobi-type matrix computations
PUFPass: A password management mechanism based on software/hardware codesign
Invasive weed optimization based scheduling for digital microfluidic biochip operations
Nano-CMOS thermal sensor design optimization for efficient temperature measurement
Hybrid Radix-16 booth encoding and rounding-based approximate Karatsuba multiplier for fast Fourier transform computation in biomedical signal processing application
Performance of signature analysis: a survey of bounds, exact, and heuristic algorithms
An accurate sparse-matrix based framework for statistical static timing analysis
Characterization, testing and reconfiguration of faults in mesh networks
A dynamic jitter model to evaluate uncertainty trends with technology scaling
A 16-bit specialized processor design
A sequential strong PUF architecture based on reconfigurable neural networks (RNNs) against state-of-the-art modeling attacks
Analysis of false lock in Mueller-Muller clock and data recovery system
Qualitative data augmentation for performance prediction in VLSI circuits
Accurate and efficient power simulation strategy by compacting the input vector set
VLSI design and implementation of a reconfigurable hardware-friendly Polar encoder architecture for emerging high-speed 5G system
Modeling and design of CMOS analog circuits through hierarchical abstraction
Design and implementation of filterbank for MPEG-2/4 AAC system
Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths
A novel intrinsic-parameters-correlation enhancement technology applied to accurately extract GaN HEMT small-signal model parameters
SIEAA: Significant input extraction-based error optimized approximate adder for error resilient application
LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs
Automated pre-placement phase as a part of robust analog-mixed signal physical design flow
State assignment based on two-dimensional placement and hypercube mapping
Phase Change Memory lifetime enhancement via online data swapping
A novel current controlled configurable RO PUF with improved security metrics
Optimization of via distribution and stacked via in multi-layered P/G networks
On the identification of modular test requirements for low cost hierarchical test path construction
Scalable layout decomposition implemented by a distribution evolutionary algorithm
Rich dynamics and analog implementation of a Hopfield neural network in integer and fractional order domains
TeRa: Ternary and Range based packet classification engine
High-performance and low-power decoder circuits for SRAMs using mixed-logic scheme
Introduction to the special issue on algorithms and architectures
Analog perceptron circuit with DAC-based multiplier
Multi-frequency weak signal detection based on Liu-like chaotic synchronization system and its hardware circuit implementation
Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS
Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/row Compression
Vulnerability modeling of cryptographic hardware to power analysis attacks
Nyquist-criterion based design of a CT SigmaDelta-ADC with a reduced number of comparators
Design of a systolic-pipelined architecture for real-time enhancement of color video stream based on an illuminance-reflectance model
An incremental algorithm for identification of longest (shortest) paths
Development of micro computer based mobile random number generator with an encryption application
A backtracing-oriented procedure for the analysis of combinational gate-level designs
Real-time infrared small target detection network and accelerator design
On malicious implants in PCBs throughout the supply chain
A novel systolic array processor with dynamic dataflows
A progressive self-training semi-supervised model to enhance discontinuous change detection
Exploring redundant arithmetics in computer-aided design of arithmetic datapaths
A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction
Optimizing the control-unit through the resynchronization of operations
Integration of retiming with architectural floorplanning
Scheduling with register constraints for DSP architectures
Efficient scalable VLSI architecture for Montgomery inversion in GF( p )
Fractional-Order PI/PD and PID Controllers in Power Electronics: The step-down converter case
A hardware version of the RSA using the Montgomery's algorithm with systolic arrays
Constrained resource sharing and conflict resolution in Hebe
Second-order compensation BGR with low TC and high performance for space applications
An orchestrated NoC prioritization mechanism for heterogeneous CPU-GPU systems
Classification of analog synthesis tools based on their architecture selection mechanisms
Minimizing the cost of repairing WSI memories
An efficient architecture of truncated booth multiplier for AI application
FPGA-based test bed for measurement of AM/AM and AM/PM distortion and modeling memory effects in RF PAs
FPGA-based pipelined kNN accelerator with early termination optimization
Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA
Proposal and analysis of relative stability in mixed CNT bundle for sub-threshold interconnects
The synthesis of control signals for one-dimensional systolic arrays
High-speed serial interface equalization tuning using metaheuristics
Workload- and process-variation aware voltage/frequency tuning for energy efficient performance sustainability of NTC manycores
Passivity-based non-fragile control of a class of uncertain fractional-order nonlinear systems
A new CMOS pseudo approximation exponential function generator by modified particle swarm optimization algorithm
Synchronization in scale-free neural networks with heterogeneous time delay
A novel test compression algorithm for analog circuits to decrease production costs
Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching
Exploiting the Logic-In-Memory paradigm for speeding-up data-intensive algorithms
Ensuring safety and efficiency in networks-on-chip
An automatic cell pattern generation system for CMOS transistor-pair array LSI
Minimal stretching of a layout to ensure 2-layer wirability
HDHL: A hybrid GSP lightweight block cipher with two-round high diffusion
A two-directional grid multiscroll hidden attractor based on piecewise linear system and its application in pseudo-random bit generator
AT 2 -optimal VLSI integer division and integer square rooting
Toward automated reasoning for analog IC design by symbolic computation - A survey
EE DC-DB PFAL: A novel two-phase adiabatic logic family for low-power 14 nm FinFET-Based hybrid full adders
An efficient memristor crossbar architecture for mapping Boolean functions using Binary Decision Diagrams (BDD)
An area-efficient 1st order noise shaping SAR using C-2C ladder DAC for biomedical applications
A fully floating memristor emulator with long-term memory
Asymmetry dual-LFSR reseeding for low power BIST
Constant addition with flagged binary adder architectures
Fast modulo 2 n +1 multi-operand adders and residue generators
FPGA-based implementation of classification techniques: A survey
Low-Gm tunable CMOS transconductors for simultaneous multi-sine bioimpedance spectroscopy
A low power offset voltage calibration method for flash ADCs
Accuracy recovery: A decomposition procedure for the synthesis of partially-specified Boolean functions
An algorithm for computing the signal propagation on lossy VLSI interconnect systems in the time domain
Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths
On whitespace and stability in physical synthesis
FPGA-based control system for real-time driving of UHD Micro-LED display with color calibration
Millimeter wave wireless interconnects in deep submicron chips: Challenges and opportunities
DP-Nets: Dynamic programming assisted quantization schemes for DNN compression and acceleration
Improving linearity in MOS varactor based VCOs by means of the output quiescent bias point
An analytical approach and fine-tuning strategy for PCB placement optimization
A note on architectures for large-capacity CAMs
Lorenz's state equations as RC filters
Design of robust analog integrated circuit based on process corner performance variability minimization
Research progress of time-interleaved analog-to-digital converters
Verification and revision of the power-down mode for hierarchical analog circuits
Approximate squaring circuits exploiting recursive architectures
Delay-insensitive multi-ring structures
Chip design of MFCC extraction for speech recognition
Implementation of an IoT system with a security scheme to predict indoor CO2 levels and mitigate COVID-19 using time series algorithms
Improved throughput bit-serial multiplier for GF(2 m ) fields
An Inductor-less Sub-mW Low Noise Amplifier for Wireless Sensor Network Applications
High performance parallel turbo decoder with configurable interleaving network for LTE application
Design of 1T2R ReRAM array for in memory element-wise multiplication with distributed and majority logics
Design and implementation of deep learning-based object detection and tracking system
Zero-temperature-coefficient-powered design technology co-optimization for temperature-immune digital circuits
On nominal delay minimization in LUT-based FPGA technology mapping
Ultra-low power m -sequence code generator for body sensor node applications
MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems
Graph-based techniques to speed up floorplan area optimization
Integrated electrical silicon interconnects for short-range high-speed millimeter-wave and terahertz communications
An all-digital self-calibrated delay-line based temperature sensor for VLSI thermal sensing and management
WHDVI: A wireless high definition video interface technique for digital home
VLSI architecture and implementation for FS1016 CELP decoder with reduced power and memory requirements
A near-threshold 10T differential SRAM cell with high read and write margins for tri-gated FinFET technology
A systematic review of machine learning-driven design space exploration in high-level synthesis
Improved adaptive sliding mode control for non-ideal single-inductor dual-output boost converter
Active inductor-based tunable impedance matching network for RF power amplifier application
Constant-time addition with hybrid-redundant numbers: Theory and implementations
Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017
Adaptable quad tree techniques
Secure split test techniques to prevent IC piracy for IoT devices
Hessian-driven N:M sparsity and quantization co-optimization for edge device deployment
A new low-power dynamic circuit for wide fan-in gates
A Machine Learning approach for anomaly detection on the Internet of Things based on Locality-Sensitive Hashing
Post-silicon debugging of PMU integration errors using behavioral models
Reliability and wirability optimizations for module placement on a convectively cooled printed wiring board
High-speed binary coded decimal digit multipliers with multiple error detection
Stochastic circuit synthesis via satisfiability
Artificial synapse topologies using arbitrary-order memristors
An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications
PE-based high throughput and low power polar encoder for 5G-NR PBCH channel
Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC
A TVWS receiver with balanced output self-calibrated IIP2 LNTA employing a low-noise current multiplier