yusuke1997/dblp-id-title huggingface dataset:
Embedding Rectangular Grids into Square Grids with Dilation Two
Systolic Processing and an Implementation for Signal and Image Processing
A Survey of Multivalued Memories
The Granularity Metric for Fine-Grain Real-Time Scheduling
Analysis of Rounding Methods in Floating-Point Arithmetic
A Formal Language for Describing Machine Logic, Timing, and Sequencing (LOTIS)
Design of an Energy-Efficient CMOS-Compatible NoC Architecture with Millimeter-Wave Wireless Interconnects
Poolpo - A Pool of Processors for Process Control Applications
Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores
ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees
ERA-BS: Boosting the Efficiency of ReRAM-Based PIM Accelerator With Fine-Grained Bit-Level Sparsity
Bit-Serial Parallel Processing Systems
Frequency-to-Period-to-Analog Computer for Flowrate Measurement
On the Synthesis of Signal Switching Networks with Transient Blocking
Correction to "Towards a New Theory of Sequential Switching Networks" 1
Floating-Point Arithmetic Algorithms in the Symmetric Residue Number System
The Partial Line Digraph Technique in the Design of Large Interconnection Networks
SongC: A Compiler for Hybrid Near-Memory and In-Memory Many-Core Architecture
Pre-Defined Sparsity for Low-Complexity Convolutional Neural Networks
Hierarchical Execution to Speed Up Pipeline Interlock in Mainframe Computers
An Inverted File Processor for Information Retrieval
Using an Efficient Sparse Minor Expansion Algorithm to Compute Polynomial Subresultants and the Greatest Common Denominator
Transistors in Current-Analog Computing
Decomposition of Polygons into Convex Sets
NTTU: An Area-Efficient Low-Power NTT-Uncoupled Architecture for NTT-Based Multiplication
Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations
Errors in Regular Languages
Analytical Performance Modeling of Hierarchical Mass Storage Systems
Java Runtime Systems: Characterization and Architectural Implications
Error Analysis and Detection Procedures for a Hardware Implementation of the Advanced Encryption Standard
Improving Digital Computer Performance Using Residue Number Theory
Incremental Distance and Diameter Sequences of a Graph: New Measures of Network Performance
On Area and Yield Considerations for Fault-Tolerant VLSI Processor Arrays
QoS Control for Pipelines of Tasks Using Multiple Resources
Simulation of Third-Order Systems by a Single Operational Amplifier
A Note on t-Unidirectional Error Correcting and d(d>=t)-Unidirectional Error Detecting (t-UEC and d-UED) Codes
Data Exchange Optimization in Reconfigurable Binary Trees
Where the Sidewalk Ends: Extending the Internet AS Graph Using Traceroutes from P2P Users
WaWoT: Towards Flexible and Efficient Web of Things Services via WebAssembly on Resource-Constrained IoT Devices
Design of Ternary COS/MOS Memory and Sequential Circuits
Single and Group Agent Migration: Algorithms, Bounds, and Optimality Issues
Detection and Location of Multiple Faults in Baseline Interconnection Networks
Design of Crosspoint-Irredundant PLA's Using Minimal Number of Control Inputs
Hardware and Software Techniques for Controlling DRAM Power Modes
On the Threshold Order of a Boolean Function
Structure Handling in Data-Flow Systems
The Testability of Generalized Counters Under Multiple Faulty Cells
The Generation of Minimal Threshold Nets by an Integer Program
More On Squaring and Multiplying Large Integers
An Optimal Encoding to Represent a Single Set in an ROBDD
A Formalism for Description and Synthesis of Logical Algorithms and their Hardware Implementation
A Theorem on the Cyclic Correlations of Walsh Functions
Dynamic Prioritized Conflict Resolution on Multiple Access Broadcast Networks
Efficient Composited de Bruijn Sequence Generators
Optimal Parallel Merging and Sorting Without Memory Conflicts
Novel RNS Parameter Selection for Fast Modular Multiplication
A Dilated-Diagonal-Based Scheme for Broadcast in a Wormhole-Routed 2D Torus
Evaluation and Mitigation of Radiation-Induced Soft Errors in Graphics Processing Units
Solution and Optimization of Systems of Pseudo-Boolean Constraints
READ: Reliability Enhancement in 3D-Memory Exploiting Asymmetric SER Distribution
A Unified View of Test Compression Methods
zPerf: A Statistical Gray-Box Approach to Performance Modeling and Extrapolation for Scientific Lossy Compression
LUNA-CiM: A Programmable Compute-in-Memory Fabric for Neural Network Acceleration
SLA: A Stage-Level Latency Analysisfor Real-Time Communicationin a Pipelined Resource Model
The Partitioned Multiprocessor Scheduling of Deadline-Constrained Sporadic Task Systems
Measuring the Accuracy of ROM Reciprocal Tables
Concrete Analysis and Trade-Offs for the (Complete Tree) Layered Subset Difference Broadcast Encryption Scheme
Tree Systems for Syntactic Pattern Recognition
A Ferroelectric-Based Volatile/Non-Volatile Dual-Mode Buffer Memory for Deep Neural Network Accelerators
Control Units for Sequencing Complex Asynchronous Operations
DISCO: Time-Compositional Cache Coherence for Multi-Core Real-Time Embedded Systems
Fast Coflow Scheduling via Traffic Compression and Stage Pipelining in Datacenter Networks
Automated Verification of Behavioral Equivalence for Microprocessors
Bounds on the Number of Pseudothreshold Functions
HyWin: Hybrid Wireless NoC with Sandboxed Sub-Networks for CPU/GPU Architectures
Some Aspects of the Dynamic Behavior of Hierarchical Memories
Power Minimization Problems of Logic Networks
Communication-Aware Load Balancing for Parallel Applications on Clusters
Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks
An Algorithm for the Efficient Utilization of Bandwidth in the Slotted Ring
An Energy-Delay Tunable Task Allocation Strategy for Collaborative Applications in Networked Embedded Systems
A Framework for Computer Performance Evaluation Using Benchmark Sets
A Resolution-Based Proof Procedure Using Deletion-Directed Search
A Graph-Theoretic Approach for Timing Analysis and its Implementation
Evaluation of Design Options for the Trace Cache Fetch Mechanism
A Syscall-Level Binary-Compatible Unikernel
Boolean Memories
Practical Multiprocessor Scheduling Algorithms for Efficient Parallel Processing
An Experimental System for Computer Controlled Mechanical Assembly
Detection of Totally Symmetric Boolean Functions
Comparisons of Seven Neural Network Models on Traffic Control Problems in Multistage Interconnection Networks
Task Mapping and Scheduling for OpenVX Applications on Heterogeneous Multi/Many-Core Architectures
Area-Efficient Multipliers Based on Multiple-Radix Representations
Disturbance Relaxation for 3D Flash Memory
B71-6 System Structure in Data, Programs, and Computers
Redactable Blockchain From Decentralized Chameleon Hash Functions, Revisited
On the Parallel Evaluation of Polynomials
Choices of Operand Truncation in the SRT Division Algorithm
A Decision-Directed Clustering Algorithm for Discrete Data
A Note on 'A Tight Lower Bound on the Number of Channels Required for Deadlock-Free Wormhole Routing'
Improving the Performance of the Sense-Amplifier Circuit Through Pre-Amplification Strobing and Noise-Matched Clipping
Analysis of a Class of Recovery Procedures
A Construction Method of High-Speed Decoders Using ROMS's for Bose-Chaudhuri-Hocquenghem and Reed-Solomon Codes
Practical and Secure SVM Classification for Cloud-Based Remote Clinical Decision Services
A Real-Time Ubiquitous System for Assisted Living: Combined Scheduling of Sensing and Communication for Real-Time Tracking
Efficient Sorting with CCD's and Magnetic Bubble Memories
Computation Off-Loading in Resource-Constrained Edge Computing Systems Based on Deep Reinforcement Learning
IC Bridge Fault Modeling for IP Blocks Using Neural Network-Based VHDL Saboteurs
Analysis of Asynchronous Binary Arbitration on Digital Transmission-Line Busses
An Alternative to the Distributed Pipeline
Juliet: A Configurable Processor for Computing on Encrypted Data
Property Learning Techniques for Efficient Generation of Directed Tests
Encryption and Error-Correction Coding Using D Sequences
On System Diagnosability in the Presence of Hybrid Faults
The Quadratic Utilization Upper Bound for Arbitrary Deadline Real-Time Tasks
R68-43 Two Continuous System Modelling Programs
A Testable Design of Iterative Logic Arrays
Guest Editors' Introduction: Special Section on Computational Sustainability: Where Computer Science meets Sustainable Development
Analyzing Errors with the Boolean Difference
MTHAEL: Cross-Architecture IoT Malware Detection Based on Neural Network Advanced Ensemble Learning
Coding Techniques for Failure-Tolerant Counters
Energy-Delay Efficient Segmented Approximate Adder With Smart Chaining
Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition
A Symmetric Cosine Transform
Accurate Floating-Point Product and Exponentiation
Analysis and FPGA Implementation of Image Restoration under Resource Constraints
A Synthesis Algorithm for Reconfigurable Interconnection Networks
An Organization for a Highly Survivable Memory
Improving the Availability of Mutual Exclusion Systems on Incomplete Networks
Design and Analysis of Dual-Rail Circuits for Security Applications
Opportunistic Flooding in Low-Duty-Cycle Wireless Sensor Networks with Unreliable Links
Improving the Performance of Block-based DRAM Caches Via Tag-Data Decoupling
Nearest-Neighbor Mapping of Finite Element Graphs onto Processor Meshes
GF(2 n ) Shifted Polynomial Basis Multipliers Based on Subquadratic Toeplitz Matrix-Vector Product Approach for All Irreducible Pentanomials
Scheduling Real-Time Systems with End-to-End Timing Constraints Using the Distributed Pinwheel Model
Magnetic Analogs of Relay Contact Networks for Logic
Next-State Equations of Asynchronous Sequential Machines
Optimal Test Generation in Combinational Networks by Pseudo-Boolean Programming
An Energy-Efficient Accelerator Based on Hybrid CPU-FPGA Devices for Password Recovery
On the Input Impedance Network Error in Operational Amplifiers
Fault-Tolerant FFT Networks
SEED: A Statically Greedy and Dynamically Adaptive Approach for Speculative Loop Execution
Series Connected Tunnel-Diode Multilevel Register
On the Load Balancing Bus Accessing Scheme
Advancing CMOS-Type Ising Arithmetic Unit into the Domain of Real-World Applications
A Generalization of Addition Chains and Fast Inversions in Binary Fields
Realization of Boolean Expressions by Atomic Digraphs
An Algebraic Approach to Boolean Equations
Measuring Parallelism in Computation-Intensive Scientific/Engineering Applications
Optimizing Locality-Aware Memory Management of Key-Value Caches
On Theory and Fast Algorithms for Error Correction in Residue Number System Product Codes
Probabilistic Analysis of Scheduling Precedence Constrained Parallel Tasks on Multicomputers with Contiguous Processor Allocation
Recognition of Printed Chinese Characters
COUNTDOWN: A Run-Time Library for Performance-Neutral Energy Saving in MPI Applications
Experience with CONSER: A System for Server Control through Fluid Modeling
A Characterization of the Variation in Time of Workload Arrival Patterns
Comparison of Computational Speeds of Digital Differential Analyzers and General Purpose Computers
A Lower Bound on the Number of Corrections Required for Convergence of the Single Threshold Gate Adaptive Procedure
ASHL: An Adaptive Multi-Stage Distributed Deep Learning Training Scheme for Heterogeneous Environments
TranSim: A Simulation Framework for Cache-Enabled Transparent Computing Systems
MultiFunction Threshold Gates
Efficient Detection for Malicious and Random Errors in Additive Encrypted Computation
Automatic Accurate Cost-Bound Analysis for High-Level Languages
Mathematical Models for Predicting Pulse Characteristics in Digital Logic Systems
An Algorithm to Dualize a Regular Switching Function
A Nine-Valued Circuit Model for Test Generation
An Observation on the Bisectional Interconnection Networks
PMDB: A Range-Based Key-Value Store on Hybrid NVM-Storage Systems
Endogenous Trusted DRL-Based Service Function Chain Orchestration for IoT
Fast Rounding in Multiprecision Floating-Slash Arithmetic
Fields in Strip-Lines for Film Memory Application
Olympus: Reaching Memory-Optimality on DNN Processors
Towards Energy Efficient Duty-Cycled Networks: Analysis, Implications and Improvement
Efficient Encoding Algorithm for Second-Order Spectral-Null Codes Using Cyclic Bit Shift
A VLSI Architecture for Approximate Tree Matching
Operation Shipping for Mobile File Systems
Dynamic Access Ordering for Streamed Computations
A Model for Pattern Recognition Systems with Binary Pattern Vectors
COSMO: COmpressed Sensing for Models and Logging Optimization in MCU Performance Screening
Fast and Scalable Multi-Way Analysis of Massive Neural Data
Retrofitting the VAX-11/780 Microarchitecture for IEEE Floating Point Arithmetic - Implementation Issues, Measurements, and Analysis
Crossing Minimization in Linear Embeddings of Graphs
Systolic Arrays with Embedded Tree Structures for Connectivity Problems
Feedback in Synchronous Sequential Switching Circuits
Diagnosis of Systems with Asymmetric Invalidation
Polynomial Division on Systolic Arrays
Distinguishing Sets for Optimal State Identification in Checking Experiments
A Survey and Assessment of Progress in Switching Theory and Logical Design in the Soviet Union
SenSpire OS: A Predictable, Flexible, and Efficient Operating System for Wireless Sensor Networks
A Combinatorial Problem Concerning Processor Interconnection Networks
Low Complexity Concurrent Error Detection for Complex Multiplication
The Logic of Bidirectional Binary Counters
FasDL: An Efficient Serverless-Based Training Architecture With Communication Optimization and Resource Configuration
On Determining Optimum Simple Golay Marking Transformations for Binary Image Processing
Testing and Realization of Threshold Functions by Successive Higher Ordering of Incremental Weights
Implementation of Threshold Nets by Integer Linear Programming
A Novel Node Placement for Long Belt Coverage in Wireless Networks
Nonlinear Sequential Circuits
HiBid: A Cross-Channel Constrained Bidding System With Budget Allocation by Hierarchical Offline Deep Reinforcement Learning
Transformations Among Switching Function Canonical Forms
THEMIS: Time, Heterogeneity, and Energy Minded Scheduling for Fair Multi-Tenant Use in FPGAs
Virtual Configuration Management: A Technique for Partial Runtime Reconfiguration
A Predictable Framework for Safety-Critical Embedded Systems
Majority-Logic Synthesis by Geometric Methods
Watchdog Processors and Structural Integrity Checking
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units
An Efficient Dynamic Algorithm for Maintaining All-Pairs Shortest Paths in Stochastic Networks
Montgomery Multiplier and Squarer for a Class of Finite Fields
On the Lower Bound to the Memory of Finite State Machines
General Schedulers for the Pinwheel Problem Based on Double-Integer Reduction
Pseudorandom Testing
Design Trade-Offs for User-Level I/O Architectures
Partial Scan Design Based on Circuit State Information and Functional Analysis
Flexible and Efficient Routing Based on Progressive Deadlock Recovery
Dependability Modeling and Evaluation of Software Fault-Tolerant Systems
Fault Masking in Combinational Logic Circuits
NDSTRNG: Non-Deterministic Sampling-Based True Random Number Generator on SoC FPGA Systems
Parallel Multipliers Based on Special Irreducible Pentanomials
Software Trace Cache
Minimum Universal Logic Module Sequential Circuits with Decoders
Silent Data Corruptions: Microarchitectural Perspectives
Fast Suboptimal Wiener Filtering of Markov Sequences
Analytical Calculation of the Maximum Error for a Family of Truncated Multipliers Providing Minimum Mean Square Error
Efficient Multi-Input/Multi-Output VLSI Architecture for Two-Dimensional Lifting-Based Discrete Wavelet Transform
Sizing Cleancache Allocation for Virtual Machines' Transcendent Memory
The Block-Oriented Computer
Shared Logic Realizations of Dynamically Self-Checked and Fault-Tolerant Logic
The I/O Performance of Multiway Mergesort and Tag Sort
Power-Efficient Heterogeneous Many-Core Design With NCFET Technology
The Interplay of Power Management and Fault Recovery in Real-Time Systems
Polynomial Testing of Packet Switching Networks
Randomized Cache Placement for Eliminating Conflicts
Rank-Augmented LU-Algorithm for Computing Generalized Matrix Inverses
Input Tolerance Considerations for Multithreshold Threshold Elements
Temporal Predicate Detection Using Synchronized Clocks
2-by-n Hybrid Cellular Automata with Regular Configuration: Theory and Application
Towards Globally Optimal Design of Multipliers for FPGAs
An Experimental Delay Test Generator for LSI Logic
A Lower Bound of the Number of Threshold Functions
An Overflow Detection and Correction in Digital Filters
Convolution Computer
The Questions of Systems Implementation with Large-Scale Integration
Using a Decision-Table Structure as the Input Language Format for Programming Automatic Test Equipment Systems
Scheduling Heuristics in a Multiprogramming Environment
Adaptive Systems in Pattern Recognition
Modeling Cyber-Physical Production Systems With SystemC-AMS
The Load-Sharing Banyan Network
Nonparametric Curves
A Real-Time Parallel Optical Processing Technique
A Semicausal Model for Recursive Filtering of Two-Dimensional Images
Variable Time Delay by Padé Approximation
Finding Multi-Constrained Multiple Shortest Paths
A High-Performance and Scalable Hardware Architecture for Isogeny-Based Cryptography
Correction to "Nonlinear Feedback Shift Registers"
Optimality of a Two-Phase Strategy for Routing in Interconnection Networks
The Prime Memory System for Array Access
Generalized Hypercubes: Edge-Disjoint Hamiltonian Cycles and Gray Codes
Functional Memory and Its Microprogramming Implications
Error-Correcting Codes for Ternary Content Addressable Memories
Optimal Detection of Bridge Faults and Stuck-At Faults in Two-Level Logic
The Number of Equivalence Classes of Functions Realizable by Generalized Tributary Networks
A Proof of Convergence for Two Parallel Jacobi SVD Algorithms
A Simple Display for Characters and Graphics
A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits
Optimization of Asynchronous Sequential Circuit Realizations
Algorithms and Arithmetic Operators for Computing the etaT Pairing in Characteristic Three
The Weighted Syndrome Sums Approach to VLSI Testing
RuYi: Optimizing Burst Buffer Through Automated, Fine-Grained Process-to-BB Mapping
Comments on "Higher-Radix Division Using Estimates of the Divisor and Partial Remainder"
A Highly Reliable Multiplexing Scheme in Hypercube-Structured Hierarchical Networks
A Solution to the Euler Angle Transformation Equations
TPDA-DRAM: A Variation-Aware DRAM Improving System Performance via In-Situ Timing Margin Detection and Adaptive Mitigation
High-Performance DRAMs in Workstation Environments
A Parallel QR Algorithm for Symmetric Tridiagonal Matrices
Prune and Plant: Efficient Placement and Parallelism of Virtual Network Functions
Performance Enhancements of Ad Hoc Networks with Localized Route Repair
Computation of the Fast Fourier Transform from Data Stored in External Auxiliary Memory for Any General Radix r=2 n , n ≥ 1
Computer Analysis of Moving Polygonal Images
LAWS: Locality-AWare Scheme for Automatic Speech Recognition
The Comparison Approach to Multiprocessor Fault Diagnosis
A Note on the Number of Internal Variable Assignments for Sequential Switching Circuits
SECRET: Semantically Enhanced Classification of Real-World Tasks
R70-15 Realization of Sequential Machines with Threshold Elements
Rational Numbers and Regular Events
An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set
Impact of NCFET Technology on Eliminating the Cooling Cost and Boosting the Efficiency of Google TPU
A Correspondence Between Equivalence Classes of Switching Functions and Group Codes
Derivation of Minimum Test Sets for Unate Logical Circuits
A Property of N-Graphs
A On-Line Square Root Algorithm
Multi-Grained Block Management to Enhance the Space Utilization of File Systems on PCM Storages
Design and Implementation of a Journaling File System for Phase-Change Memory
Compact CA-Based Single Byte Error Correcting Codec
On 3-Extra Connectivity and 3-Extra Edge Connectivity of Folded Hypercubes
A New Parallel VLSI Architecture for Real-Time Electrical Capacitance Tomography
MDTUpdate: A Multi-Block Double Tree Update Technique in Heterogeneous Erasure-Coded Clusters
FLiMS: A Fast Lightweight 2-Way Merger for Sorting
Decimal Multiformat Online Addition
A Report on the International Analogy Computation Meeting
Efficient Partitioning of Sequences
R70-34 Unateness Test of a Boolean Function and Two General Synthesis Methods Using Threshold Logic
A Special-Function Unit for Sorting and Sort-Based Database Operations
The CORDIC Trigonometric Computing Technique
Guest Editorial for Special Section on Advanced Techniques for Efficient and Reliable Cloud Storage
Acoustic Ray Tracing on the General-Purpose Electronic-Analog Computer
An Architecture for Bitonic Sorting with Optimal VLSI Performance
An Algebraic Model for the Analysis of Logical Circuits
Neural-PIM: Efficient Processing-In-Memory With Neural Approximation of Peripherals
Bit-Serial Multipliers and Squarers
An Analysis of High-Speed, Linear-Passive Binary, Read-Only Stores
Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles
Fast Division Using Accurate Quotient Approximations to Reduce the Number of Iterations
Computer Diagnosis Using the Blocking Gate Approach
On the Time Required for Timing - The Halting Problem Rephrased
Detection of Hazards in Combinational Switching Circuits
Fast Evaluation of the Elementary Functions in Single Precision
A Generalized Dictionary Machine for VLSI
Constant-Factor Redundant CORDIC for Angle Calculation and Rotation
A High-Speed Threshold Gate Multiplier
A Hybrid Multicast Routing for Large Scale Sensor Networks with Holes
LOCS: An EDP Machine Logic and Control Simulator
Correction to "Minimization of Switching Circuits Subject to Reliability Conditions"
Variable-Mode Counting with Straight Binary Counters
Some Aspects of the Logical Design of a Control Computer: A Case Study
Fast Self-Routing Permutation Switching on an Asymptotically Minimum Cost Network
Guest Editors' introduction: Special section on adaptive hardware and systems
A Parallel Neuromorphic Text Recognition System and Its Implementation on a Heterogeneous High-Performance Computing Cluster