yusuke1997/dblp-id-title huggingface dataset:
On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement
Minimal Shift-Register Realizations of Sequential Machines
Least Upper Bounds an OBDD Sizes
NIPD: Non-Intrusive Power Disaggregation in Legacy Datacenters
Coordinated En-Route Web Caching
High Fidelity Simulation of Hybrid Systems using Higher Order Hybrid Automata
On Minimum Cost Recovery from System Deadlock
Aircraft Identification by Moment Invariants
NetKG: Synthesizing Interpretable Network Router Configurations With Knowledge Graph
Processor Testability and Design Consequences
FaaSBatch: Boosting Serverless Efficiency With In-Container Parallelism and Resource Multiplexing
Multilevel Diskless Checkpointing
Fast and Efficient Convolutional Accelerator for Edge Computing
Toward Finding S-Box Circuits With Optimal Multiplicative Complexity
Secure Cloud Storage Meets with Secure Network Coding
Graph Functions of Boolean Functions
On the Addition of Binary Numbers
Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms
Multisize Sliding Window in Workload Estimation for Dynamic Power Management
Applying Features of IEEE 754 to Sign/Logarithm Arithmetic
A Max-Min Measure for Image Texture Analysis
A Router Architecture for Real-Time Communication in Multicomputer Networks
CFHider: Protecting Control Flow Confidentiality With Intel SGX
An Analog Computer Realization of the Euclidean Tools
Non-Parametric RSS Prediction Based Energy Saving Scheme for Moving Smartphones
A Novel Division Algorithm for the Residue Number System
STEMS: Spatial-Temporal Mapping for Spiking Neural Networks
Some Studies in the Interactive Design of Character Recognition Systems
State Assignments for Asynchronous Sequential Machines
A Comparison of FPGA and GPU for Real-Time Phase-Based Optical Flow, Stereo, and Local Image Features
R70-36 Maximin Automata
ROCKY: A Robust Hybrid On-Chip Memory Kit for the Processors With STT-MRAM Cache Technology
A Highly Scalable Network Architecture for Optical Data Centers
Acceleration of Fast Sample Entropy for FPGAs
On the Design of Multiple Fault Diagnosable Networks
Comparison of Saturated and Nonsaturated Switching Circuit Techniques
Embedding Complete Binary Trees into Butterfly Networks
The Calculation of Multiplicative Inverses Over GF(P) Efficiently Where P is a Mersenne Prime
On Optimal Single Jog River Routing
The VLSI Design of an Error-Trellis Syndrome Decoder for Certain Convolutional Codes
Parallel Algorithms for Joining Two Points by a Straight-Line Segment
A Characterization of Bent Functions in Terms of Strongly Regular Graphs
A Neuron-Weighted Learning Algorithm and Its Hardware Implementation in Associative Memories
Performance-Measurement Tools in a Multiprocessor Environment
Real-Power Computing
Test Generation Algorithms for Computer Hardware Description Languages
A Variable Counter Design Technique
PySchedCL: Leveraging Concurrency in Heterogeneous Data-Parallel Systems
Comments on "Theoretical Comparison of a Class of Feature Selection Criteria in Pattern Recognition"
Heuristic Technique for Processor and Link Assignment in Multicomputers
Offset DMR: A Low Overhead Soft Error Detection and Correction Technique for Transform-Based Convolution
On the Design of Self-Checking Controllers with Datapath Interactions
Correct and Almost Complete Diagnosis of Processor Grids
3D-Integrated SRAM Components for High-Performance Microprocessors
Efficient Fault Identification of Diagnosable Systems under the Comparison Model
A Set of Invariants Within the Power Spectrum of Unitary Transformations
Virtualizing Network I/O on End-Host Operating System: Operating System Support forNetwork Control and Resource Protection
Latency, Occupancy, and Bandwidth in DSM Multiprocessors: A Performance Evaluation
The Theory of Nets
Automatic Design of Area-Efficient Configurable ASIC Cores
Dedicated LSI for a Microprocessor-Controlled Hand-Carried OCR System
Gracefully Degradable Processor Arrays
Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time
DCCS: Double Circular Caching Scheme for DRAM/PRAM Hybrid Cache
A VLSI-Based I/O Formatting Device
Low Complexity Word-Level Sequential Normal Basis Multipliers
An Inductive Assertion Method for Register Transfer Level Design Verification
Efficient CP-ABE Scheme With Shared Decryption in Cloud Storage
Analysis of a New Retransmission Control Algorithm for Slotted CSMA/CD LAN's
LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference
Memory Latency Effects in Decoupled Architectures
Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing
Interval Availability Analysis Using Denumerable Markov Processes: Application to Multiprocessor Subject to Breakdowns and Repair
Application-Guided Power-Efficient Fault Tolerance for H.264 Context Adaptive Variable Length Coding
FESTAL: Fault-Tolerant Elastic Scheduling Algorithm for Real-Time Tasks in Virtualized Clouds
A Self-Refreshable Bit-Cell for Single-Cycle Refreshing of Embedded Memories
Parallel Reproducible Summation
DownShift: Tuning Shift Reduction With Reliability for Racetrack Memories
Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses
Execution Architecture: The DELtran Experiment
FeFET-Based Binarized Neural Networks Under Temperature-Dependent Bit Errors
DESCO: Decomposition-Based Co-Design to Improve Fault Tolerance of Security-Critical Tasks in Cyber Physical Systems
Improving the Speed of Parallel Decimal Multiplication
Regular Expressions for Linear Sequential Circuits
Lock-Free Triangle Counting on GPU
Sequential Machines with Less Delay Elements than Feedback Paths
On the Number of Operations Simultaneously Executable in Fortran-Like Programs and Their Resulting Speedup
Efficient MSI Partitioning for a Digital Computer
Fast Haar Transform Algorithms
A Digital Synthesis Procedure Under Function Symmetries and Mapping Methods
Augmented Parity Check Codes for Encoding of Asynchronous Sequential Machines
Parallelism and Array Processing
A Contention-Based Bus-Control Scheme for Multiprocessor Systems
Parallel Multiplicative Algorithms for Some Elementary Functions
An Interactive System for Reading Unformatted Printed Text
Optimization of Tree Modes for Parallel Hash Functions: A Case Study
Alternative Tower Field Construction for Quantum Implementation of the AES S-Box
Interconnection Networks Based on a Generalization of Cube-Connected Cycles
On the Design of Combinational Totally Self-Checking I-out-of3 Code Checkers
Bounds on the Length of Terminal Stuck-Fault Test
Bounds on the Capacity of the Unidirectional Channels
Modeling and Tools for Power Supply Variations Analysis in Networks-on-Chip
SCIRTSS: A Search System for Sequential Circuit Test Sequences
A Pattern Search Algorithm for Feedback-Control System Parameter Optimization
The Method of Decomposition for Unstable Two-Point Boundary Value Problems
Exploiting Security Dependence for Conditional Speculation Against Spectre Attacks
Critical pairs and set systems
A Dynamically Microprogammable Computer with Low-Level Parallelism
Routing Virtual Circuits with Temporal QoS Requirements in Virtual Path-Based ATM Networks
Easily Testable Iterative Logic Arrays
The Generation of Permutations in Magnetic Bubble Memories
A Variational Approach to Digital Integration
Security Protection and Checking for Embedded System Integration against Buffer Overflow Attacks via Hardware/Software
Introducing the New Editor-in-Chief of the IEEE Transactions on Computers
Cross-Layer Software Dependability on Unreliable Hardware
Efficient Normal Basis Multipliers in Composite Fields
Optimal Graph Algorithms on a Fixed-Size Linear Array
Self-Complementary Symmetry Types of Boolean Functions
Evaluating Dynamic Failure Probability for Streams with (m, k)-Firm Deadlines
Real-Time Schedulability Analysis and Enhancement of Transiently Powered Processors With NVMs
TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration
An Algorithm for Pattern Classification Using Eigenvectors
PIT: Processing-In-Transmission With Fine-Grained Data Manipulation Networks
A Multiple Computer Linkage
Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption
Transformation of an Arbitrary Switching Function to a Totally Symmetric Function
A Note on Logical Gain
Comments on "Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks"
New Techniques to Reduce the Execution Time of Functional Test Programs
Synthesis of Diagnosable FET Networks
New Multiplicative Inverse Architectures Using Gaussian Normal Basis
Comments on "Multiple Fault Detection in Combinational Networks"
An Analog Computer Technique for Solving a Class of Nonlinear Ordinary Differential Equations
Connection-Oriented Versus Connectionless Protocols: A Performance Study
Unidirectional Error Codes for Shift-Register Memories
Scaling Power and Performance viaProcessor Composability
Generation of Prime Implicants from Subfunctions and a Unifying Approach to the Covering Problem
Design of Two-Level Fault-Tolerant Networks
Is a Bird in the Hand Worth More than Two in the Bush? Limitations of Priority Cognizance in Conflict Resolution for Firm Real-Time Database Systems
Fixed Resistor-Card Memory
A Limited-Global-Informatin-Based Multicasting Scheme for Faulty Hypercubes
A Multiple-Sequence Generator Based on Inverted Nonlinear Autonomous Machines
A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay
A Power- and Performance-Aware Software Framework for Control System Applications
BSR-FL: An Efficient Byzantine-Robust Privacy-Preserving Federated Learning Framework
On Modular Networks Satisfying the Shift-Register Rule
Cyclic Codes in Multiple Channel Parallel Systems
Phase-Change Memory Optimization for Green Cloud with Genetic Algorithm
Reflected Number Systems
A Secondary-Emission Pulse Circuit, Its Analysis and Application
One Attack to Rule Them All: Collision Timing Attack versus 42 AES ASIC Cores
A Management Scheme of Multi-Level Retention-Time Queues for Improving the Endurance of Flash-Memory Storage Devices
On the Performance of Certain Multiprocessor Computer Organizations
Design and Behavior of TSS/8: a PDP-8 Based Time-Sharing System
Management of Partially Safe Buffers
A Novel Security-Driven Scheduling Algorithm for Precedence-Constrained Tasks in Heterogeneous Distributed Systems
Parallel Processing Algorithms for the Optimal Control of Nonlinear Dynamic Systems
CoreRank: Redeeming "Sick Silicon" by Dynamically Quantifying Core-Level Healthy Condition
An Approach to Organizing Microinstructions which Minimizes the Width of Control Store Words
Accelerating Large-Scale Graph-Based Nearest Neighbor Search on a Computational Storage Platform
Thermal-Aware Design for Approximate DNN Accelerators
A Multiple Fault-Tolerant Processor Network Architecture for Pipeline Computing
On the Performance of Synchronous Multiprocessors
Selecting an Optimal Fault Tolerance Strategy for Reliable Service-Oriented Systems with Local and Global Constraints
Delay Approximations for Correlation Measurements Using Analog Computers
A Modular Fault-Tolerant Binary Tree Architecture with Short Links
A new method of generating functions
A Generalization of Hybrid Fault Diagnosability
The Design of Program-Modifiable Micro-Programmed Control Units
Realization of Fault-Tolerant and Fail-Safe Sequential Machines
A Circular Binary Search
Comments on "Computing Irredundant Normal Forms from Abbreviated Presence Functions"
B-Cubing: New Possibilities for Efficient SAT-Solving
Optimal Data Retrieval Scheduling in the Multichannel Wireless Broadcast Environments
A New Hybrid Fault Detection Technique for Systems-on-a-Chip
Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks
Magnetostrictive Ultrasonic Delay Lines for a PCM Communication System
Architectural Support for System Protection and Database Security
Average Path Length of Binary Decision Diagrams
Maximum Performance Pipelines With Switchable Reservation Tables
KnightSim: A Fast Discrete Event-Driven Simulation Methodology for Computer Architectural Simulation
A Variation-Aware Quantum Circuit Mapping Approach Based on Multi-Agent Cooperation
Layered "Recognition Cone" Networks That Preprocess, Classify, and Describe
Arithmetic Co-Transformations in the Real and Complex Logarithmic Number Systems
The B-Network: A Multistage Interconnection Network with Backward Links
On the Generation of High-Quality Random Numbers by Two-Dimensional Cellular Automata
Multidimensional magnetic memory selection systems
Efficient Fault Locations for Globally Controlled and Comparison-Based Multistage Interconnection Networks
Universal Modular Trees: A Design Procedure
On a Covering Problem for Partially Specified Switching Functions
Magnetic Core Logic in a High-Speed Card-to-Tape Converter
Design of triode flip-flops for long-term stability
RSA Speedup with Chinese Remainder Theorem Immune against Hardware Fault Cryptanalysis
The Origin of the Method of Iterated Consensus
On Efficient Computation of Matrix Chain Products
Providing Balanced Mapping for Multiple Applications in Many-Core Chip Multiprocessors
Hardware Specification with Temporal Logic: En Example
Low Overhead Soft Error Mitigation Techniques for High-Performance and Aggressive Designs
One-Bit Delay in Ring Networks
AutoPipe-H: A Heterogeneity-Aware Data-Paralleled Pipeline Approach on Commodity GPU Servers
Negative Radix Conversion
Isolating Short-Lived Operands for Energy Reduction
Generalized Hypercube and Hyperbus Structures for a Computer Network
Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications
Modified Redundant Representation for Designing Arithmetic Circuits with Small Complexity
Counting Sequences with Large Local Distance
Distributed Fault-Tolerance of Tree Structures
A Multi-UAV Cooperative Task Scheduling in Dynamic Environments: Throughput Maximization
An Algorithm for Path Connections and Its Applications
The t/k-Diagnosability of the BC Graphs
A Routing Methodology for Achieving Fault Tolerance in Direct Networks
Enabling Secure NVM-Based in-Memory Neural Network Computing by Sparse Fast Gradient Encryption
Comparator with Completion Signal
An Algorithm for Finding Secondary Assignments of Synchronous Sequential Circuits
In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs)
R68-34 Hybrid Apollo Docking Simulation
2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets
Pairwise Reduction for the Direct, Parallel Solution of Sparse, Unsymmetric Sets of Linear Equations
Improving Energy Efficiency of GPUs through Data Compression and Compressed Execution
UKFaaS: Lightweight, High-Performance and Secure FaaS Communication With Unikernel
Denial-of-Service Vulnerability of Hash-Based Transaction Sharding: Attack and Countermeasure
A Study of Pipelining in Computing Arrays
T-SPaCS - A Two-Level Single-Pass Cache Simulation Methodology
Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip
GIER-A Danish Computer of Medium Size
System Organization of a Multiple-Cockpit Digital Operational Flight Trainer
Reliability and Availability Models for Maintained Systems Featuring Hardware Failures and Design Faults
From Determinacy to Systaltic Arrays
Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity
OurRocks: Offloading Disk Scan Directly to GPU in Write-Optimized Database System
A Versatile Machine Vision System for Complex Industrial Parts
Correlation Attacks on Clock-Controlled Shift Registers in Keystream Generators
Portable Video Supercomputing
Design of Testable VLSI Circuits with Minumum Area Overhead
Symmetric Ternary Switching Functions
Access and Alignment of Data in an Array Processor
The DIMOND: A Component for the Modular Construction of Switching Networks
Automatic Time-Mark Generation for Analog Computer Phase-Plane Trajectories
A Distance Criterion for Figural Pattern Recognition
On the Use of Redundant Integrators in Analog Computers
On the Design of 4-Valued Digital Systems
Fault-Tolerant Networks Based on the de Bruijn Graph
A Compact Definition of Walsh Functions
PCN Equivalence Class Invariants and Information Quantities
A Reconfigurable Wireless NoC for Large Scale Microbiome Community Analysis
An Optimal O(NlgN) Algorithm for Permutation Admissibility to Extra-Stage Cube-Type Networks
Householder CORDIC Algorithms
An Error-Detecting Binary Adder: A Hardware-Shared Implementation
Reduced Length Checking Sequences
A Possibly Misleading Conclusion as to the Inferiority of One Method for Pattern Recognition to a Second Method to which it is Guaranteed to be Superior
Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization
Improved Methods of Simulating Time Delays
CD-Xbar: A Converge-Diverge Crossbar Network for High-Performance GPUs
rePLay: A Hardware Framework for Dynamic Optimization
An Interpolating Memory Unit for Function Evaluation: Analysis and Design
The Nonuniform Distribution of Instruction-Level and Machine Parallelism and Its Effect on Performance
Coordinated Multilevel Buffer Cache Management with Consistent Access Locality Quantification
Weighting Method for the Determination of the Irredundant Set of Prime Implicants
A Programmable Logic Approach for VLSI
The Stochastic Rendezvous Network Model for Performance of Synchronous Client-Server-like Distributed Software
On the Use of Counters for Reproducing Deterministic Test Sets
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip
Representation of Nonlinear Functions by Means of Operational Amplifiers
On Totally Self-Checking Checkers for Separable Codes
PaRS: A Popularity-Aware Redundancy Scheme for In-Memory Stores
The Run-Time Efficiency of Parallel Asynchronous Algorithms
The Use of Parenthesis-Free Notation for the Automatic Design of Switching Circuits
Generalization of Min-Cut Partitioning to Tree Structures and Its Applications
A Universal Four-State Cellular Computer
PHASEPLOT: An On-Line Graphical Display Technique
RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses
Representation of Associated Data by Matrix Operators
Previous Investigation of Realization of an Arbitrary Switching Function with a Network of Threshold and Parity Elements
Predictable Performance in SMT Processors: Synergy between the OS and SMTs
A New Placement-Ideal Layout for Multiway Replication Storage System
Exploring Hyperdimensional Computing Robustness Against Hardware Errors
Comments on "Low Diameter Interconnections for Routing in High-Performance Parallel Systems, " with Connections and Extensions to Arc Coloring of Coset Graphs
Fast Execution of Loops with IF Statements
Tunnel-Diode Threshold Discriminator Tolerance Analysis
Comments on "Hybrid Computer Solution of Optimal Control Problems by the Maximum Principle"
Towards Hardware IIR Filters Computing Just Right: Direct Form I Case Study
Stress-Based and Path-Based Fault Injection
Power Budgeting Techniques for Data Centers
Binary Decision Diagram Assisted Modeling of FPGA-Based Physically Unclonable Function by Genetic Programming
Reed-Muller Canonical Forms in Multivalued Logic
Logic Design for Dynamic and Interactive Recovery
On Connecting Modules Together Uniformly to Form a Modular Computer
Computer-Aided Logic Design of Two-Level MOS Combinational Networks with Statistical Results
General Repetitive Events and Machines
Casting Out Threes in Binary Numbers
Scalable Encrypted Deduplication Based on Location-Hiding Secret Sharing of Data Keys
Unequal Error Protection of Memories in LDPC Decoders
A Distributed VLSI Architecture for Efficient Signal and Data Processing
An Algorithm for Constrained Maximization of the Trace of a Matrix
On Multidimensional Arrays of Processors
An Asynchronous Dataflow FPGA Architecture
A Formalization of Floating-Point Numeric Base Conversion
The Transduction Method-Design of Logic Networks Based on Permissible Functions
Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations
Reconfigurable Hardware Implementations of Tweakable Enciphering Schemes
The Performance of Parity Placements in Disk Arrays
On the Limit Sets of the 2 × 1 Homogeneous Nets
A Logic Design for a Microwave Computer
Efficient Processing of Sparse Tensor Decomposition via Unified Abstraction and PE-Interactive Architecture
Utilizing Multidimensional Loop Parallelism on Large-Scale Parallel Processor Systems
Redundant Radix Representations of Rings
A Power and Throughput-Efficient Packet Classifier with n Bloom Filters
Optimal Circuits for Parallel Multipliers
Energy-Efficient Instruction Delivery in Embedded Systems With Domain Wall Memory
B72-21 Data Structures and Management
Branch Prediction Attack on Blinded Scalar Multiplication
New Connectivity and MSF Algorithms for Shuffle-Exchange Network and PRAM
Succinct Greedy Geometric Routing Using Hyperbolic Geometry
DIA: A Complexity-Effective Decoding Architecture
On the Unavoidability of Metastable Behavior in Digital Systems
Universal Multicode STT State Assignments for Asynchronous Sequential Machines
Reconfiguration of VLSI/WSI Mesh Array Processors with Two-Level Redundancy
Analysis of Preventive Maintenance in Transactions Based Software Systems
mRT-PLRU: A General Framework for Real-Time Multitask Executions on NAND Flash Memory
A General Proof for Overlapped Multiple-Bit Scanning Multiplications
Analog/Hybrid Storage and Pulse Modulation
Fool Me If You Can: Mimicking Attacks and Anti-Attacks in Cyberspace
Complementary Two-Way Algorithms for Negative Radix Conversions
Model Based Verification of Spiking Neural Networks in Cyber Physical Systems
Stochastic SOT Device Based SNN Architecture for On-Chip Unsupervised STDP Learning
Adaptive Memory-Enhanced Time Delay Reservoir and its Memristive Implementation
The Fabrication of Low Resistances at Liquid Helium Temperatures
ReCREW: A Reliable Flash-Dissemination System
Olive-Like Networking: A Uniformity Driven Robust Topology Generation Scheme for IoT System
A Feedback-Driven DNN Inference Acceleration System for Edge-Assisted Video Analytics
Two Approximate Voting Schemes for Reliable Computing
Accurate Model for Application Failure Due to Transient Faults in Caches
A RAM Architecture for Concurrent Access and On-Chip Testing
A New Method for Initial Estimates in the Numerical Solution of Laplace's Equation
Power and Delay Aware Management of Packet Switches
Code Transformation in Sequential Machines
A Geometric Transversal Approach to Analyzing Track Coverage in Sensor Networks
A Simplified Method to Calculate Failure Times in Fault-Tolerant Systems
Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis
Transference of Learning Between Recognition Classes
On Crossbar Switch and Multiple Bus Interconnection Networks with Overlapping Connectivity
Creating Disjoint Paths in Gamma Interconnection Networks
New Multipliers Modulo 2^N - 1
Hybrid Obfuscation to Protect Against Disclosure Attacks on Embedded Microprocessors
DRES: Dynamic Range Encoding Scheme for TCAM Coprocessors
Complexity-Effective Contention Management with Dynamic Backoff for Transactional Memory Systems
Thread Row Buffers: Improving Memory Performance Isolation and Throughput in Multiprogrammed Environments
Area-Time Optimal VLSI Circuits for Convolution
Synthesis and Optimization of Programs by Means of P -Funktions
Microprogramming: Perspective and Status
Control Storage Use in Implementing an Associative Memory for a Time-Shared Processor
Sharing Logic for Built-In Generationof Functional Broadside Tests
Cascaded Finite-State Machines
An Approach for Error Detection and Error Correction in Distributed Systems Computing Numerical Functions
A Control Unit for a DEC PDP-8 Computer and a Burroughs Disk
Content Aware Refresh: Exploiting the Asymmetry of DRAM Retention Errors to Reduce the Refresh Frequency of Less Vulnerable Data
Deductive Fault Simulation with Functional Blocks
Database Machines: An Introduction