yusuke1997/dblp-id-title huggingface dataset:
Optimizing machine learning logic circuits with constant signal propagation
Novel tunable current feedback instrumentation amplifier based on BBFC OP-AMP for biomedical applications with low power and high CMRR
Routability-wirelength co-guided cell inflation with explainable multi-task learning for global placement optimization
Synthesis and optimization of multiple-valued combinational and sequential reversible circuits with don't cares
Hardware implementation of a sub-pixel algorithm for real-time saw blade deflection monitoring
A novel design of hybrid-time-interleaved current steering digital to analog converter and its behavioral simulation considering non-ideal effects
Full-wave analysis and analytical formulas for the line parameters of transmission lines on semiconductor substrates
A TCAD system for VLSI implementation of the CVD process using VHDL
Lightweight FPGA acceleration framework for structurally tailored multi-version MobileNetV1
A new leakage-tolerant high speed comparator based domino gate for wide fan-in OR logic for low power VLSI circuits
Efficient parasitic-aware hybrid sizing methodology for analog and RF integrated circuits
Simulation for a novel vertical SOI configuration
A rapid turnaround design of a high speed VLSI search processor
Exact ESCT minimization for functions of up to six input variables
Novel techniques for memristive multifunction logic design
Decomposition based estimation of distribution algorithm for high-level synthesis design space exploration
ALAMO: FPGA acceleration of deep learning algorithms with a modularized RTL compiler
Design of a 3-bit 2.2 ps step 357.5 ps range 0.247 μm2 0.85 μW 45 nm All-MOS delay element
Analog circuits optimization based on evolutionary computation techniques
Modeling and designing silicon thin-film inductors and transformers using HSPICE for RFIC applications
Comparative evaluation of background-rejection techniques for SPAD-based LiDAR systems
Model of a switched-capacitor programmable voltage reference for ultra low-power applications
Enhanced functional verification models that ensure the full functionality of an A-PLL device
Variable wordlength soft-decision Viterbi decoder for power-efficient wireless LAN
Automated diagnostics for manufacturing machinery based on well-regularized deep neural networks
Testing framework for on-board verification of HLS modules using grey-box technique and FPGA overlays
A survey on nonlinear analog-to-digital converters
A real-time integrated eye tracker with in-pixel image processing in 0.18-μm CMOS technology
Ensemble learning model for effective thermal simulation of multi-core CPUs
An all-digital low ripples capacitive DC-DC converter with load tracking controller
Design and analysis of DTMOS based RFC with controlled positive feedback OTA using HSCCM and adaptive biasing technique
Hardware design of LIF with Latency neuron model with memristive STDP synapses
A cellular automata guided two level obfuscation of Finite-State-Machine for IP protection
A reconfigurable test method based on LFSR for 3D stacking integrated circuits
A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras
An aging monitoring scheme for SRAM decoders
A dual basis bit-serial systolic multiplier for GF(2 m )
Hardware architecture design for complementary ensemble empirical mode decomposition algorithm
Evaluation of a prototype VLSI tester
Clock mesh synthesis through dynamic programming with physical parameters consideration
Machine-learning-driven prediction of thin film parameters for optimizing the dielectric deposition in semiconductor fabrication
Rail-to-rail constant-gm operational amplifier for video applications
Design and implementation of reconfigurable and flexible test access mechanism for system-on-chip
Improved thermal network modeling of die stacking DRAM and optimization
A quantitative design methodology for high-speed interpolation/averaging ADCs
An S to Ku band wideband low-voltage low-power up-conversion mixer in 0.18-μm CMOS technology
Register Pre-Allocation based Folded Discrete Tchebichef Transformation Technique for Image Compression
A fault-tolerant CCSDS 123 hardware accelerator for space applications
CCTA based four different pairs of mutually coupled circuit using single topology
A 8.83 ppm/°C temperature coefficient, 75 dB PSRR subthreshold CMOS voltage reference with piecewise curvature compensation
Comments on "Improved designs of digit-by-digit decimal multiplier"
SARPAR: Systolic ARray Pallet-Integrated AcceleratoR for YOLO models on FPGA
Cost considerations in network on chip
BJT induced dark current in CMOS image sensors
VLSI implementation of low-power and area efficient parallel memory allocation with EC-TCAM
A fast piecewise image encryption scheme combining NC1DNSM and P-Box
A dual precision IEEE floating-point multiplier
Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes
An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning
A simple built-in current sensor for IDDQ testing of CMOS data converters
Development of slope detection ASIC for on-chip current sensing in voltage converters
Introduction to the special issue on Radio Frequency Integrated Circuits (RFIC) design techniques
Provably good moat routing
Maximizing pin alignment in semi-custom chip circuit layout
A PLL-based synthesizer for tunable digital clock generation in a continuous-time SigmaDelta A/D converter
Lifetime improvement by exploiting aggressive voltage scaling during runtime of error-resilient applications
Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies
Yielding optimized dependability assurance through bit inversion
Bio-inspired NoC fault tolerant techniques using guaranteed throughput and best effort services
Finding the longest delay paths for the array-form multipliers using a genetic algorithm
An optimised hardware architecture of the angular-domain cyclostationary detector for cognitive radio communications
Path reuse-aware routing for non-volatile memory based FPGAs
Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications
A lightweight FPGA accelerator for onboard processing of hyperspectral anomaly detection based on optimized TinyYOLOv3 model
Average latency and link utilization analysis of heterogeneous wormhole NoCs
Dynamics analysis, FPGA implementation, and application in image encryption of a quadruple-wing chaotic system based on hyperbolic sine functions
Optimal synthesis of control logic from behavioral specifications
Systolic architectures for inversion/division using AB2 circuits in GF(2m)
An 8-bit 19 MS/s low-power 0.35 μm CMOS pipelined ADC for DVB-H
Design of synthesizable period-jitter sensor IP with high power reduction and variation resiliency
Two-level clustering-based techniques for intelligent droplet routing in digital microfluidic biochips
A novel IEEE rounding algorithm for high-speed floating-point multipliers
Expandable arithmetic block macrocell
SYSIM: a simulation tool for systolic processors
Area-efficient architectures of Midori lightweight block cipher for resource constrained devices
Dimensional optimisation of a MEMS BPSK to ASK converter in SOIMUMPs
Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated Circuits
A mathematical formulation to design and implementation of a low voltage swing transceiver circuit
Mathematical analysis and circuit emulator design of the three-valued memristor
Achieving superior segmented CAM efficiency with pre-charge free local search based hybrid matcher for high speed applications
A heuristic approach for near Pareto-optimal design space exploration in Approximate High-Level Synthesis
Factored spherical subspace tracking
Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption
Chaotic encryption of real-time ECG signal in embedded system for secure telemedicine
Enhancing cell delay accuracy in post-placed netlists using ensemble tree-based algorithms
Efficient modulo 2 n +1 multiply and multiply-add units based on modified Booth encoding
Design and implementation of congestion aware router for network-on-chip
CompreCity: Accelerating the Traveling Salesman Problem on GPU with data compression
Design of high-efficiency complex multiplier for fault-tolerant computation
A survey of hardware Trojan threat and defense
Low-complexity bit-parallel systolic multipliers over GF(2 m )
A hybrid 16-bit Ripple Carry Adder with Doublet Transmission Gate-based Compressor for performance boost
A high-level information flow tracking method for detecting information leakage
Efficient co-planar adder designs in quantum dot cellular automata: Energy and cost optimization with crossover elimination
A survey on multi-net global routing for integrated circuits
VLSI implementation of iterative methods for the solution of linear systems
Fast analytical approximations of the transient response of coupled lossy interconnects in VLSI circuits with frequency-dependent parameters for higher hierarchical simulation levels
NeSTAR: Hardware Trojans and its mitigation strategy in NoC routers
A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS
SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty
Robust analog/RF circuit design via Cycle-Consistent Generative Adversarial Networks
PLA logic minimization by simulated annealing
Adaptive prediction resolution video coding for reduced DRAM bandwidth
An automated high-level topology generation procedure for continuous-time SigmaDelta modulator
A 0.3nV/√Hz input-referred-noise analog front-end for radiation-induced thermo-acoustic pulses
Improved Shimizu-Morioka system and its application in image encryption
Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes
Simulation-based analog and RF circuit synthesis using a modified evolutionary strategies algorithm
A balanced power analysis attack resilient adiabatic logic using single charge sharing transistor
Sorting on defective VLSI-arrays
Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs
The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs
A comprehensive analysis on differential cross-coupled CMOS LC oscillators via multi-objective optimization
Comparison of two new chaos-based pseudorandom number generators implemented in microcontroller
A dual-function mixed-signal circuit for LDPC encoding/decoding
DAFA: Dynamic approximate full adders for high area and energy efficiency
NBTI alleviation on FinFET-made GPUs by utilizing device heterogeneity
Implementing and clustering modules with complex delays
Compact thermal modeling for packaged microprocessor design with practical power maps
A novel memristor based physically unclonable function
Incremental analysis of large VLSI Layouts
GaAs pipelined dynamic logic
VLSI implementation of a systolic database machine for relational algebra and hashing
Exploring XOR-based Full Adders and decoupling cells to variability mitigation at FinFET technology
Low test cost adaptive testing method for high yield IC products
FPGA-based parallel implementation to classify Hyperspectral images by using a Convolutional Neural Network
A general and accurate pattern search method for various scenarios
SAT based timing analysis for fixed and rise/fall gate delay models
Timing-driven variation-aware synthesis of hybrid mesh/tree clock distribution networks
Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load
Towards accelerating irregular EDA applications with GPUs
Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection
Lorenz system manufacturing with a Butterworth filter
A dynamic S-box algorithm based on special supersingular elliptic curve
Serial diagnostic fault simulation for synchronous sequential circuits
Monolithic 3D stacked multiply-accumulate units
Sequential test generators: past, present and future
Switch-level simulation based on local decisions
Offline Testing of Reversible Logic Circuits: An Analysis
Unified chip hardware architecture of KD-tree mean-based trainer and speeding-up classifier with repeat-point searching for various applications
A compact low-power 4-port register file with grounded write bitlines and single-ended read operations
Substrate model extraction using finite differences and parallel multigrid
A 65 nm CMOS key establishment core based on tree parity machines
Analysis, modeling and design of a CMOS Super-Regenerative Receiver for implanted medical devices under square and sinusoidal quench signals
HOP: A process model for synchronous hardware; semantics and experiments in process composition
Second-order cascode-based filters
On chip novel video streaming system for bi-network multicasting protocols
Design, simulation, and implementation of an integrated, hybrid photocurrent-to-digital converter in CMOS technology
Dynamically adaptive real-time disparity estimation hardware using iterative refinement
Systolic block LU decompositions
Temperature variation aware multi-scale delay, power and thermal analysis at RT and gate level
A 1.4×FO4 self-clocked asynchronous serial link in 0.18 µm for intrachip communication
Design rule checking and VLSI
A memory efficient parallel layered QC-LDPC decoder for CMMB systems
Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test
An optimal analytical solution for maximizing expected battery lifetime using the calculus of variations
An accurate model of domain-wall-based spintronic memristor
Parallel implementations of direction finding algorithms on networks of general purpose DSP processors
Formally verified synthesis of combinational CMOS circuits
Design of a delay-insensitive multiply-accumulate unit
VLSI implementation of a 16-state coset code
A new methodology to implement the AES algorithm using partial and dynamic reconfiguration
156 dB low-voltage low-power CMOS exponential function generator circuit
A novel autozeroing technique for flash Analog-to-Digital converters
Hardware/software security co-verification and vulnerability detection: An information flow perspective
A comparative study on performance and reliability of 32-bit binary adders
A self-training end-to-end mask optimization framework based on semantic segmentation network
A Noise-Aware Real-Time Processing Approach for Electroencephalogram Signal Classification
Efficient RC low-power bus encoding methods for crosstalk reduction
Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology
Optimization on operation sorting for HLS scheduling algorithms
Ultra-low latency communication channels for FPGA-based HPC cluster
An MTCMOS technology for low-power physical design
Design of FIR filter ISOTA with the aid of genetic algorithm
Step-by-Step Design of memory hierarchy for heterogeneously-integrated SCM/NAND flash storage
g m -boosted flat gain UWB low noise amplifier with active inductor-based input matching network
Issues in the development of a practical NoC: the Proteo concept
Safe integration of parameterized IP
An open-source compiler and PCB synthesis tool for digital microfluidic biochips
Comparison of the VLSI cost/performance properties of two Reed-Solomon decoding algorithms1
A quality-configurable approximate cache design based on NAND-like SOT MRAM with high energy efficiency
Reconfiguration of hexagonal arrays by diagonal deletion
High quality hypergraph partitioning for logic emulation
Boolean function representation and spectral characterization using AND/OR graphs
Sensor-based M2M Agriculture Monitoring Systems for Developing Countries: State and Challenges
Emerging Technologies for Smart Devices
Protocols and Algorithms for the Next Generation 5G Mobile Systems
Channel Aware Scheduling Algorithm for LTE Uplink and Downlink
An Experimental Study of SCTP in NS2
Intelligent Algorithm for Enhancing MPEG-DASH QoE in eMBMS
Protection of data in unsecured public cloud environment with open, vulnerable networks using threshold-based secret sharing
Precise Time System Efficiency of a Frame Slotted Aloha based Anti-Collision Algorithm in a RFID System
Chain Based Fault Tolerant Routing Protocols
A Generic Algorithm to Determine Maximum Bottleneck Node Weight-based Data Gathering Trees for Wireless Sensor Networks
Framed ALOHA Protocol with FIFO-Blocking and LIFO-Push out Discipline
Network Selection Algorithm for Heterogeneous Wireless Networks: from Design to Implementation
Inferring User-perceived Performance of Network by monitoring TCP Interruptions
Multilayer Traffic Engineering in Interworking Multihop wireless networks
A New Framework for Request-driven Data Harvesting in Vehicular Sensor Networks
PMIPv6 Assistive Cross-Layer Design to reduce handover latency in VANET Mobility for Next Generation Wireless Networks
Routing Protocols for Structural Health Monitoring of Bridges Using Wireless Sensor Networks
Mobility and Network Selection in Heterogeneous Wireless Networks: User Approach and Implementation
The Dynamics of Salsa: A Robust Structured P2P System
A2CDC: Area Coverage, Connectivity and Data Collection in Wireless Sensor Networks
Relative Localization of Wireless Sensor Nodes by Using the RSSI Data
Resource Allocation for Heterogeneous Cloud Computing
Mobile Agent Based Routing in Manets - Attacks & Defences
QoS-oriented Admission Control in HSDPA networks
Spectrum Aggregation: Overview and Challenges
Sensor Network Proposal for Greenhouse Automation placed at the South of Algeria
A New EIFS Strategy for Performance Improvement of IEEE 802.11 Wireless LANs
An Efficient Fast Handoff and Route Optimization Protocol for the Nested Mobile Networks
Wireless Technologies for IoT in Smart Cities
User-Level Quality Assessment of a Delay-Aware Packet Dropping Scheme for VoIP
A Bloom Filter with the Integrated Hash Table Using an Additional Hashing Function
Handover Latency Measurement using Variant of Capwap Protocol
Scriptable Sensor Network Applications for Rapid Development of Internet of Things
Performance Evaluation of WPAN MAC Protocol with Improved Backoff Algorithm
Security issues and threats that may affect the hybrid cloud of FINESCE
Survey of Transportation of Adaptive Multimedia Streaming service in Internet
Improving Throughput in SCTP via Dynamic Optimization of Retransmission Bounds
Adherence to a treatment of cranial deformities with a sensorised brace device
ZigBee Based Optimal Scheduling System for Home Appliances in the United Arab Emirates
Study and Performance of Interior Gateway IP routing Protocols
Routing Protocols in Vehicular Ad hoc Networks: Survey and Research Challenges
Design and Implementation of ForCES Protocol
Emergency Services Control Model for Next Generation Networks
Cross Layer Design for Efficient Video Streaming over LTE Using Scalable Video Coding
Adaptative control of packetization to improve the energy efficiency of VoIP applications in IEEE 802.11 networks
Revisiting VoIP QoE assessment methods: are they suitable for VoLTE?
Special Issue on Advances in Computing and Communications
Introduction to Network Protocols and Algorithms
Survey of the Protection Mechanisms to the SSL-based Session Hijacking Attacks
A Modified IEEE 802.15.4 Superframe Structure for Guaranteed Emergency Handling in Wireless Body Area Network
Architectural Evolution of Monitor and Control Systems - Issues and Challenges
Modified WRR Scheduling Algorithm for WiMAX Networks
Study of Multimedia Delivery over Software Defined Networks
A Reliable Wireless System for Water Quality Monitoring and Level Control
Anomaly Base Network Intrusion Detection by Using Random Decision Tree and Random Projection: A Fast Network Intrusion Detection Technique
Secure Trust Management with Source Routing Protocol for MANETs
Interconnected Chord-rings
Performance Analysis of Quality of Service in Software-Defined Networking
T-RBAC based Multi-domain Access Control Method in Cloud
Localization Algorithms in Wireless Sensor Networks: Current Approaches and Future Challenges
Automatic Network Service Discovery and Selection in Virtualization-Based Future Internet
QoS Traffic Mapping between WiMAX and DiffServ Networks
A Survey of Energy-aware Routing protocols in Mobile Ad-hoc Networks: Trends and Challenges
A New Packet Scheduling Algorithm for Real-Time Multimedia Streaming
Energy-Efficient Cell Partition of 3D Space for Sensor Networks with Location Information
Master/Slave assignment optimization for high performance computing in an EC2 cloud using MPI
Achieving Security by Intrusion-Tolerance Based on Event Correlation
Energy-aware Virtual Ring Routing in Wireless Sensor Networks
An approach to a cross layer-based QoE improvement for MANET routing protocols
A Unicast Stable Path Routing Protocol for Mobile Ad hoc Networks based on the Inverse of Link Expiration Time
Routing Engine Architecture for Next Generation Routers: Evolutional Trends
Distributed Bottleneck Flow Control in Mobile Ad Hoc Networks
Centrality-based Connected Dominating Sets for Mobile Ad hoc Networks
Green Communications and Networking
Wavelength Preference in GMPLS-controlled Wavelength Switched Optical Networks
Pervasive sensors network for wellness based-on Raspberry Pi
Overview on Multi-Channel Communications in Wireless Sensor Networks
QoS-aware Routing in Multi-rate Ad hoc Networks Based on Ant Colony Optimization
Link aware and Energy efficient Routing Algorithm in Wireless Body Area Networks
A Precise Indoor Localization Approach based on Particle Filter and Dynamic Exclusion Techniques
Context capturing in smart space applications
Security and Surveillance System for Drivers Based on User Profile and learning systems for Face Recognition
Multi-Agent based Framework for Secure and Reliable Communication among Open Clouds
REST service testing based on inferred XML schemas
Quality of Service and security negotiation for autonomous management of Next Generation Networks
A Robust and Energy Efficient Cooperative Spectrum Sensing Scheme in Cognitive Wireless Sensor Networks
Full Geo-localized Mobile Video in Android Mobile Telephones
A Research Framework for Analyzing High Speed Transport Protocols Based on Control-theory
Practical Design of a WSN to Monitor the Crop and its Irrigation System
A review of the architecture of admission control schemes in the Internet
On the Impact of Virtual Private Network Technologies on the Operational Costs of Cellular Machine-to-Machine Communications Platforms for Smart Grids
Coverage in Wireless Sensor Networks: A Survey
The Performances of Complex SSC/MRC Combiner in the Presence of Rayleigh Fading
TCP Performance Enhancement over Wireless Mesh Networks by means of the Combination of Multi-RAT Devices and the MPTCP Protocol
A Hierarchical Multi-hop Multimedia Routing Protocol for Wireless Multimedia Sensor Networks
Consumption of Energy and Routing Protocols in Wireless Sensor Network
Scatternet Formation Protocol for Environmental Monitoring in a Smart Garden
Pheromone-based In-Network Processing for Wireless Sensor Network Monitoring Systems
A Multifactor Hash Digest Challenge-Response Authentication Scheme for Session Initiation Protocol
Spectrum Occupancy Information in Support of Adaptive Spectrum Sensing for Cognitive Radio
Botnet Forensic: Issues, Challenges and Good Practices
An eVoting System Based on Ring Signatures
STASR A New Task Scheduling Algorithm For Cloud Environment
A Smartphone Design Approach to User Communication Interface for Administering Storage System Network
Integration of protocols FHAMIPv6/AODV in Ad hoc networks
Inter-domain Proxy Mobile IPv6 based Vehicular Network
Smart Grid ICT Research Lines out of the European Project INTEGRIS
Wireless Sensor Networks for Industrial Process Monitoring and Control: A Survey
Performance Analysis of Scheduling Algorithms for Web QoE Optimization in Wireless Networks
Algorithms and Protocols in Information and Communication Systems
Survey of Real-Time Communication in CSMA-Based Networks