yusuke1997/dblp-id-title huggingface dataset:
A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems
A Data Layout and Fast Failure Recovery Scheme for Distributed Storage Systems With Mixed Erasure Codes
Placement of the Processors of a Hypercube
Routing in Outer Space: Fair Traffic Load in Multihop Wireless Networks
Correction to "A Fast Binary Adder with Conditional Carry Generation" IEEE Transaction on Computers 46(2) 248-253 (1997)
Adaptive Coherence Granularity for Multi-Socket Systems
Design of Weighted Counters with Rational Scale Using Continued Fraction Expansion
An Approach for the Realization of Linearly-Separable Switching Functions
Heterogeneity-Aware Collective I/O for Parallel I/O Systems with Hybrid HDD/SSD Servers
Configurable Flash-Memory Management: Performance versus Overheads
On Asymmetric Invalidation with Partial Tests
Decentralized Decision Making for Task Reallocation in a Hard Real-Time System
Observations on the Effects of Fault Manifestation as a Function of Workload
Augmented Binary Hypercube: A New Architecture for Processor Management
LAShards: Low-Overhead and Self-Adaptive MRC Construction for Non-Stack Algorithms
Understanding Selective Delay as a Method for Efficient Secure Speculative Execution
Customizing Clos Network-on-Chip for Neural Networks
Understanding Shape: Angles and Sides
Novel Table Lookup-Based Algorithms for High-Performance CRC Generation
FPGA-Based Data Storage System on NAND Flash Memory in RAID 6 Architecture for In-Line Pipeline Inspection Gauges
A Nand Model ror Fault Diagnosis in Combinational Logic Networks
Faster Numerical Algorithms via Exception Handling
An Adjacent Switching Activity Metric under Functional Broadside Tests
The use of a reflected code in digital control systems
The Design of Diode-Transistor NOR Circuits
Test Schedules for VLSI Circuits Having Built-In Test Hardware
B73-1 An Introduction to Cobol Programming
Optimally Balanced Spanning Tree of the Star Network
Neural Network-Based Performance Prediction for Task Migration on S-NUCA Many-Cores
Data Collection Maximization in Renewable Sensor Networks via Time-Slot Scheduling
Linearity of Sequential Machines
Comments on "Algorithms for Reporting and Counting Geometric Intersections"
Linear Automata Approximation Problem
WooKong: A Ubiquitous Accelerator for Recommendation Algorithms With Custom Instruction Sets on FPGA
Improvements to an Algorithm for Equipartitioning
Birds of the Same Feather Flock Together: A Dual-Mode Circuit Candidate for Strong PUF-TRNG Functionalities
Magnetic film memories, a survey
An Integrated Instrumentation Environment for Multiprocessors
Sign Detection in Residue Number Systems
Timerlat: Real-Time Linux Scheduling Latency Measurements, Tracing, and Analysis
Constraint Networks in Vision
Numerical Reproducibility and Parallel Computations: Issues for Interval Algorithms
Magnetic Core Pulse-Switching Circuits for Standard Packages
A Perturbation Technique for Analog Computers
Priority Tries for IP Address Lookup
The Avoidance and Elimination of Function Hazards in Asynchronous Sequential Circuits
A Stochastic Model for Closed-Loop Preemptive Microprocessor I/O Organizations
Correction to Editor's Note
Fast Hardware Fourier Transformation Through Counting
A Note on State Minimization of Asynchronous Sequential Functions
A Class of Odd-Weight-Column SEC-DED-S b ED Codes for Memory System Applications
Processor Tradeoffs in Distributed Real-Time Systems
Comments on "An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System''
Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
Direct-Coupled Transistor Logic Circuitry
Large Dynamic Range Computations over Small Finite Rings
Coordinating Garbage Collectionfor Arrays of Solid-State Drives
An 0( n ) Parallel Multiplier with Bit-Sequential Input and Output
Efficient Hardware Malware Detectors That are Resilient to Adversarial Evasion
Sanitizer: Mitigating the Impact of Expensive ECC Checks on STT-MRAM Based Main Memories
A Compiler that Increases the Fault Tolerance of Asynchronous Protocols
Adaptive-Length Coding of Image Data for Low-Cost Approximate Storage
A Double Track Error-Correction Code for Magnetic Tape
Minimization of Contact Networks Subject to Relibility Specifications
An Improvement on a Theorem of E. F. Moore
Area Time Trade-Offs in Micro-Grain VLSI Array Architectures
Comments on "A Design of a Fast Cellular Associative Memory for Ordered Retrieval"
Checking Completeness of Tests for Finite State Machines
Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor
Cost Effective Protection Techniques for TCAM Memory Arrays
A Highly Regular and Scalable AES Hardware Architecture
Dynamic Backlight Scaling Optimization: A Cloud-Based Energy-Saving Service for Mobile Streaming Applications
ROLoad-PMP: Securing Sensitive Operations for Kernels and Bare-Metal Firmware
A TMDTO Attack Against Lizard
Data Coherence Problem in a Multicache System
Outline of the Logical Design of the ZAM-41 Computer
Models for Dynamic Load Balancing in a Heterogeneous Multiple Processor System
Application of Approximating Algorithms to Boolean Matrix Multiplication
Feature Selection with a Linear Dependence Measure
A Reduced Architecture for ReRAM-Based Neural Network Accelerator and Its Software Stack
A VLSI Modulo m Multiplier
An Efficient Routing Algorithm for Realizing Linear Permutations on p^t-Shuffle-Exchange Networks
Bounding Signal Probabilities in Combinational Circuits
An End-to-End Learning-Based Metadata Management Approach for Distributed File Systems
Transistor Circuitry for Digital Computers
Fast En/Decoding of Reed-Solomon Codes for Failure Recovery
Generalized Connection Networks for Parallel Processor Intercommunication
A Note on the Polynomial Form of Boolean Functions and Related Topics
On the Minimization of the Control Store in Microprogrammed Computers
Scheduling Multiprocessor Tasks to Minimize Schedule Length
Incremental Computation of Squares and Sums of Squares
On Permuting Properties of Regular Rectangular SW-Banyans
Failure Transparency in Remote Procedure Calls
Fast Bit-Parallel Binary Multipliers Based on Type-I Pentanomials
Comment on "The Determination of the Maximum Compatibility Classes"
A Fault-Tolerant Broadcast Scheme in the Star Graph under the Single-Port, Half-Duplex Communication Model
Bit-Parallel Finite Field Multipliers for Irreducible Trinomials
wrJFS: A Write-Reduction Journaling File System for Byte-addressable NVRAM
Parallel Minimal Norm Method of Tridiagonal Linear Systems
Application of Iterative Consensus to Multiple-Output Functions
Floating-ECC: Dynamic Repositioning of Error Correcting Code Bits for Extending the Lifetime of STT-RAM Caches
Logic Design Using EFL Structures
On the average speed of a multiple-module storage system
Fast Algorithms for Routing Around Faults in Multibutterflies and Randomly-Wired Splitter Networks
Effects of Multithreading on Cache Performance
Selective Neuron Re-Computation (SNRC) for Error-Tolerant Neural Networks
Intra-Cluster Coalescing and Distributed-Block Scheduling to Reduce GPU NoC Pressure
ALPINE: Analog In-Memory Acceleration With Tight Processor Integration for Deep Learning
Measures of Op-Code Utilization
Allocation of Operations in Distributed Database Access
Programmable Array Realizations of Synchronous Sequential Machines
An 11-Cryotron Full Adder
A Novel Rotate and Shift Circuit Using Bidirectional Gates
Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions
Optimum Design of a Diode Squarer by Applying the Criterion of Square Root of the Integral of Per Cent Error Squared
Digital Adaptive-Element Building Blocks for MOS Large-Scale Integration
Integrated-Circuit Logarithmic Arithmetic Units
Enhanced Interval Trees for Dynamic IP Router-Tables
H-SVM: Hardware-Assisted Secure Virtual Machines under a Vulnerable Hypervisor
Comment on "When to Use Random Testing"
A Two-Dimensional Display for the Classification of Multivariate Data
An Anlysis of Scatter Decomposition
Programming Cellular Permutation Networks Through Decomposition of Symmetric Groups
Fault Tolerance in Collaborative Sensor Networks for Target Detection
PerfBound: Conserving Energy with Bounded Overheads in On/Off-Based HPC Interconnects
A March Test for Functional Faults in Semiconductor Random Access Memories
A Low Complexity Scaling Method for the Lanczos Kernel in Fixed-Point Arithmetic
Lookahead Scheduling Requests for Multisize Page Caching
Adder and Multiplier Design in Quantum-Dot Cellular Automata
An Algorithm for Total Symmetric OBDD Detection
Gene McDaniel, Severo M. Ornstein: An Instruction Fetch Unit for a High-Performance Personal Conmputer
Light amplifiers and inverters for digital application employing negative conductance devices
Row/Column Replacement for the Control of Hard Defects in Semiconductor RAM's
An Almost-Optimal Algorithm for the Assembly Line Scheduling Problem
Cache Noise Prediction
The Complexity of Computational Circuits Versus Radix
Designing and Modeling of Covert Channels in Operating Systems
Load Balancing in Compute Clusters With Delayed Feedback
New Block Recombination for Subquadratic Space Complexity Polynomial Multiplication Based on Overlap-Free Approach
Mapping Petri Nets with Inhibitor Arcs onto Basic LOTOS Behavior Expressions
On Variable Ordering and Decomposition Type Choice in OKFDDs
R68-47 Computer Scheduling Methods and Their Countermeasures
Efficient Computing of Relational Algebraic Primitives in a Database Machine Architecture
The Representation of Constraints by Means of an Electronic Differential Analyzer
Communication Structures for Large Networks of Microcomputers
An Annotated Bibliography on NOR and NAND Logic
Task Optimization Allocation in Vehicle Based Edge Computing Systems With Deep Reinforcement Learning
Unified Design of Self-Checking and Fail-Safe Combinational Circuits and Sequential Machines
On the Design of Logic Networks with Redundancy and Testability Considerations
Anomalous Response Times of Input Synchronizers
Introduction to FORMAC
Systematic t -Error Correcting/All Unidirectional Error Detecting Codes
Flow Problems in Multi-Interface Networks
Tree-Based Broadcasting in Multihop Radio Networks
Sequence Detection Using All-Magnetic Circuits
Signal Strength-Aware Adaptive Offloading with Local Image Preprocessing for Energy Efficient Mobile Devices
A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays
Sequential Machines Capable of Fault Diagnosis
An Alpha-State Finite Automaton for Multiplication by Alpha
Low-Cost Error Containment and Recovery for Onboard Guarded Software Upgrading and Beyond
Synchronizing Sequences for Incompletely Specified Flow Tables
Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware
Transparent (Cut-Through) Bridging of CSMA/CD Networks: Performance Analysis and Implementation
Self-Modifiable Color Petri Nets for Modeling User Manipulation and Network Event Handling
Two Operand Binary Adders with Threshold Logic
A Note on the Design of Digital-to-Analog Converters
A Theory of Reduced and Minimal Procedural Dependencies
A Flexible Software-Based Framework for Online Detection of Hardware Defects
Shuttle: Facilitating Inter-Application Interactions for OS-Level Virtualization
Two-Level Minimization of Multivalued Functions with Large Offsets
A desk-model electronic analog computer
High-Performance Architecture of Elliptic Curve Scalar Multiplication
Faster Interleaved Modular Multiplication Based on Barrett and Montgomery Reduction Methods
A Characterization of t/s-Diagnosability an Sequential t-Diagnosability in Designs
The Connection Network Class for Fault Tolerant Meshes
Computation of Cold-Start Miss Ratios
A Customized Processor for Energy Efficient Scientific Computing
DBMS-Assisted Live Migration of Virtual Machines
Decrypting a Stream Cipher Based on J-K Flop-Flops
Encryption Schemes for Computer Confidentiality
A Sword with Two Edges: Propagation Studies on Both Positive and Negative Information in Online Social Networks
UniCoX: A Unified Cost Model for Tensorized Program Tuning Across Ubiquitous Accelerators
New Low-Complexity Bit-Parallel Finite Field Multipliers Using Weakly Dual Bases
Performance Analysis of Multistage Interconnection Network Configurations and Operations
A Remark on Determining the Number of States of a Sequential Machine
A Systematic Approach to Programming an Analog Computer to Generate a Large Class of Trajectories
Performance Analysis for Dual Band PCS Networks
Interconnection of High-Speed Logic Circuits
Improved Arrangement of a Decimal Multiplier
Low-Complexity Multiplier Architectures for Single and Hybrid-Double Multiplications in Gaussian Normal Bases
Thermoplastic Holographic Recording of Binary Patterns in PLZT Line Composer
State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores
An Optimal Solution for the Channel-Assignment Problem
Universal System Diagnosis Algorithms
On Models for Diagnosable Systems and Probabilistic Fault Diagnosis
Sequential Fault Diagnosis in Combinational Networks
Decoupling Link Scheduling Constraints in Multihop Packet Radio Networks
Run-Time Resource Management in CMPs Handling Multiple Aging Mechanisms
A Glow Counting Tube Read-Out Technique and Its Application
A Hybrid Multiple-Access Protocol for Data and Voice-Packet Over Local Area Networks
Limon: A Scalable and Stable Key-Value Engine for Fast NVMe Devices
Application of Homing Sequences to Synchronous Sequential Circuit Testing
New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference
Equally Spaced Polynomials, Dual Bases, and Multiplication in F 2 n
The Reliability Impact of Mission Abort Strategies on Redundant Flight Computer Systems
An Edge-Side Real-Time Video Analytics System With Dual Computing Resource Control
Computation-Based Reliability Analysis
Randomized Throughput-Optimal Oblivious Routing for Torus Networks
A Response-Time Bound in Fixed-Priority Scheduling with Arbitrary Deadlines
Bounding the Maximum Size of a Packet Radio Network
Synthesis and Asynchronous Implementation of Algorithms Using a Generalized P -Function Concept
R68-17 Synthesis of Resistive Digital-to-Analog Conversion Ladders for Arbitrary Codes with Fixed Positive Weights
Assessing Reliability of Multistage Interconnection Networks
Predicting Signal Degeneration and Gate Compatibility in Logic Circuits
Sequency Domain Design of Frequency Filters
B71-4 Mathematical Programming in Practice
Frame-Based Packet-Mode Scheduling for Input-Queued Switches
A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms
Test Vector Omission for Fault Coverage Improvement of Functional Test Sequences
Improved Basic Block Reordering
Dynamic Resolution of Memory Access Conflicts
Nondestructive Readout of Metallic-Tape Computer Cores
Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing
A Word-Level Finite Field Multiplier Using Normal Basis
Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches
Permutations on Illiac IV-Type Networks
Construction of Multistep Integration Formulas for Simulation Purposes
Simulation of Transistor Switching Circuits on the IBM 704
Lookaside Techniques for Minimum Circuit Memory Translators
Performability Analysis Using Semi-Markov Reard Processes
B74-3 Design Automation of Digital Systems-Volume 1, Thoery and Techniques
Using Flexibility in P-Circuits by Boolean Relations
On Transaction Processing with Partial Validation and Timestamp Ordering in Mobile Broadcast Environments
Diagnosis of Single-Gate Failures in Combinational circuits
Analysis and Compensation of High-Speed Electronic Analog-Computer Errors
Efficient Fault-Tolerant Consensus for Collaborative Services in Edge Computing
Extended Generalized Feistel Networks Using Matrix Representation to Propose a New Lightweight Block Cipher: Lilliput
On the Guaranteed Throughput of Multizone Disks
Orchestration of Network-Wide Active Measurements for Supporting Distributed Computing Applications
Basis Sets for Synthesis of Switching Functions
An Electro-Optical Shift Register
Metastability-Containing Circuits
Correction to "An Application of Relaxation Labeling to Line and Curve Enhancement"
Efficient Runtime Detection and Toleration of Asymmetric Races
Cellular Automata for Weighted Random Pattern Generation
An Efficient Algorithm-Based Concurrent Error Detection for FFT Networks
Power Analysis Attacks and Algorithmic Approaches to Their Countermeasures for Koblitz Curve Cryptosystems
Diagnosability of t-Connected Networks and Product Networks under the Comparison Diagnosis Model
Introduction to the Special Section on Nano Systems and Computing
A Resource Reservation Algorithm for Power-Aware Scheduling of Periodic and Aperiodic Real-Time Tasks
A Novel Coding Scheme for Secure Communications in Distributed RFID Systems
Comments on "A New Random-Error-Correction Code"
Fault Models and Test Methods for Subthreshold SRAMs
Minimal Multiplexed Threshold Gate Realizations
Logical Design of Ternary Switching Circuits
Scaling Machine Arithmetic
Solution to Harrison's Problem
Impact Printing
A Note on Q-Universal Logic Modules
Incorporating Knowledge Sources Into a Statistical Acoustic Model for Spoken Language Communication Systems
On the Computational Security of a Distributed Key Distribution Scheme
Closed Form Solutions for Bus and Tree Networks of Processors Load Sharing a Divisible Job
A Provably Secure True Random Number Generator with Built-In Tolerance to Active Attacks
Edge and Curve Detection: Further Experiments
Resident-Bubble Cellular Logic Using Magnetic Domains
A Reputation-Based Energy-Efficient Transaction Propagation Mechanism for Blockchain-Enabled Multi-Access Edge Computing
Single-Reference Multiple Intermediate Signature (SREMIS) Analysis for BIST
LMChain: An Efficient Load-Migratable Beacon-Based Sharding Blockchain System
Fast Boundary Detection: A Generalization and a New Algorithm
Adaptive Techniques for Photomosaicking
Timing Analysis Using Functional Analysis
Application of Arithmetic Coding to Compression of VLSI Test Data
Chebyshev Approximation and Threshold Functions
Strategic Testing Environment with Formal Description Techniques
Two Algorithms for Piecewise-Linear Continuous Approximation of Functions of One Variable
Ensuring Fault Tolerance of Phase-Locked Clocks
Comments on "Synthetic Traces for Trace-Driven Simulation of Cache Memories"
COFFA: A Co-Design Framework for Fused-Grained Reconfigurable Architecture Towards Efficient Irregular Loop Handling
An Adaptive and Fault Tolerant Wormhole Routing Strategy for k-Ary n-Cubes
Adaptive Routing Algorithms for Lifetime Reliability Optimization in Network-on-Chip
Performance Modelling and Comparisons of Global Shared Buffer Management Policies in a Cluster Environment
Dynamic Fault Tolerance in Fat Trees
Design of the Arithmetic Units of ILLIAC III: Use of Redundancy and Higher Radix Methods
Transition Count Testing of Combinational Logic Circuits
Supporting System Consistency with Differential Transactions in Flash-Based SSDs
CAMDNN: Content-Aware Mapping of a Network of Deep Neural Networks on Edge MPSoCs
Totally Self-Checking Checkers for Low-Cost Arithmetic Codes
Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations
Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics
High Density Integrated Computing Circuitry with Multiple Valued Logic
Performance Prediction for Large-Scale Parallel Applications Using Representative Replay
Multistage Interconnection Network Reliability
An Improved Algorithm for Constructing k th-Order Voronoi Diagrams
Enabling Concurrent Failure Recovery for Regenerating-Coding-Based Storage Systems: From Theory to Practice
Performance Analysis of Timing-Speculative Processors
Concurrent Error Detection Using Watchdog Processors - A Survey
Block-Based Multi-Version B + -Tree for Flash-Based Embedded Database Systems
Partitioning Techniques for Large-Grained Parallelism
A Study of Optimal 4-Bit Reversible Toffoli Circuits and Their Synthesis
The Complexity of Horizontal Word Encoding in Microprogrammed Machines
VALIANT: An EDA Flow for Side-Channel Leakage Evaluation and Tailored Protection
Counterexample-Guided Assume-Guarantee Synthesis through Learning
Synthesis of Minimal Threshold Logic Networks
Speed Up Statistical Spam Filter by Approximation
Architecture for VLSI Design of Reed-Solomon Encoders
Multiple-Seed TPG Structures
Interlaced Partition Multiplier
3-D Partitioning for Large-Scale Graph Processing
A Note on Atrubin's Real-Time Iterative Multiplier
Note on Feedforward Inverses for Linear Sequential Circuits
A Decoder Scheme Using Magnetic-Core Matrices for Systematic Codes
Optimization of Computation Time for Systolic Arrays
Node Scaling Analysis for Power-Aware Real-Time Tasks Scheduling
Theoretical Comparison of a Class of Feature Selection Criteria in Pattern Recognition
Refresh Now and Then
A Traffic-Balanced Adaptive Wormhole-Routing Scheme for Two-Dimensional Meshes
Meet and Join Derivatives and Their Use in Switching Theory
Canonical Form and Synthesis of Cellular Cascades
Analysis of Errors and Erasures in Parity Sharing RS Codecs
How to Integrate Precedence Constraints and Shared Resources in Real-Time Scheduling
GPUvm: GPU Virtualization at the Hypervisor
The Completion Time of Programs on Processors Subject to Failure and Repair
Fault Folding for Irredundant and Redundant Combinational Circuits
Microprocessor Utilization in Satellite-Born Packet Switching
Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices
On the Characterizing Parameters of a Threshold Function
Low-Transition Test Pattern Generation for BIST-Based Applications
Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures
Distributed Minimum Spanning Tree Maintenance for Transient Node Failures
Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility
A Dual Amplifier Differentiator
A Survey of Proposed Architectures for the Execution of Functional Languages
Design and Analysis of Cache Coherent Multistage Interconnection Networks
Computer Science and Engineering Education
Design and Analysis of Block-Level Snapshots for Data Protection and Recovery
Representation of Multivalued Functions Using the Direct Cover Method
Marginal Performance: Formalizing and Quantifying Power Over/Under Provisioning in NoC DVFS
A Two-Level Diagnostic Model for Digital Systems
The Montgomery Modular Inverse-Revisited
On the Delay Required to Realize Boolean Functions
Simulating Essential Pyramids
Many to Many Multicast Routing With Temporal Quality of Service Guarantees
A Mobile Agent-Based Advanced Service Architecture for Wireless Internet Telephony: Design, Implementation, and Evaluation
Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module
Use of Routing Capability for Fault-Tolerant Routing in Hypercube Multicomputers
Simultaneous Multiple Response in Associative Memories and Readout of the Detector Matrix
Subquadratic Computational Complexity Schemes for Extended Binary Field Multiplication Using Optimal Normal Bases
An Energy-Efficient Memory Unit for Clustered Microarchitectures
Design of Fail-Safe Sequential Machines Using Separable Codes
The Derivation and Experimental Verification of Clock Synchronization Theory
Complete Sets of Functions of Two and Three Binary Variables
A Two's Complement Parallel Array Multiplication Algorithm
An Online Learning Methodology for Performance Modeling of Graphics Processors
Comment on "An Analog Photoresistive Multiplier"
Fast Architectures for the \eta_T Pairing over Small-Characteristic Supersingular Elliptic Curves
A Self-Test Hardwired Control Section
An Improved Lower Bound on Polynomial Multiplication
Real-Time Task Scheduling for Machine Perception in Intelligent Cyber-Physical Systems
The Graph Structure of the Generalized Discrete Arnold's Cat Map