yusuke1997/dblp-id-title huggingface dataset:
Universal Tests for Detection of Input/Output Stuck-At and Bridging Faults
Polysynchronous Clocking: Exploiting the Skew Tolerance of Stochastic Circuits
Secure Communication with Chaotic Systems of Difference Equations
PyQUBO: Python Library for Mapping Combinatorial Optimization Problems to QUBO Form
Mapping Monotone Boolean Functions into Majority
A Markovian Dependability Model with Cascading Failures
An Efficient Homomorphic MAC with Small Key Size for Authentication in Network Coding
Dependability of COTS Microkernel-Based Systems
Minimization of Multidimensional Linear Iterative Circuits
Minimizing the Number of States in Incompletely Specified Sequential Switching Functions
Generalized Parity Checking
On the Computational Cost of Approximating and Recognizing Noise-Perturbed Straight Lines and Quadratic Arcs in the Plane
Iterative Switching Networks Composed of Combinational Cells
On Identification of Totally Symmetric Boolean Functions
A Method for Compressing Test Data Based on Burrows-Wheeler Transformation
Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets
A Linear Algebraic Model of Algorithm-Based Fault Tolerance
The GUS Multicomputer System
Hardware/Software Co-Design of an Accelerator for FV Homomorphic Encryption Scheme Using Karatsuba Algorithm
Fast Generation of RSA Keys Using Smooth Integers
A Note on the nth Shortest Path Problem
A Novel Approach to Incremental Functional Diagnosis for Complex Electronic Boards
High-Performance 3-1 Interlock Collapsing ALU's
Applying Network Coding to Peer-to-Peer File Sharing
A Mathematical Model of Finite Random Sequential Automata
Relating Static and Dynamic Machine Code Measurements
Maxterm Type Expressions of Switching Functions and Their Prime Implicants
Dual Fast-Track Cache: Organizing Ring-Shaped Racetracks to Work as L1 Caches
An Error Analysis of Electronic Analog Computers
The Printing of Octal Numerals
A Delay-Line Push-Down List
Multilevel Logical Networks
Longevity Framework: Leveraging Online Integrated Aging-Aware Hierarchical Mapping and VF-Selection for Lifetime Reliability Optimization in Manycore Processors
A Performance Bound of Multistage Combining Networks
Parallel d-Pipeline: A Cuckoo Hashing Implementation for Increased Throughput
Determination of Priority in Associative Memories
On Soft Error Reliability of Virtualization Infrastructure
Systematic Procedures for Realizing Synchronous Sequential Machines Using Flip-Flop Memory: Part I
On Structured Digraphs and Program Testing
PMLiteDB: Streamlining Access Paths for High-Performance Persistent Memory Document Database Systems
Partitions and Edge-Weighted Pair-Graphs
Reliability of Mobile Processes with Noisy Channels
Error Detection in Digital Devices and Computer Programs with the Aid of Linear Recurrent Equations Over Finite Commutativs Groups
Design of an All-Magnetic Computing System: Part II-Logical Design
Distributed Control of Computer Systems
Enabling Verifiable Search and Integrity Auditing in Encrypted Decentralized Storage Using One Proof
Some New Results on the Convergence, Oscillation, and Reliability of Polyfunctional Nets
A Fast Distributed Shortest Path Algorithm for a Class of Hierarchically Clustered Data Networks
On the Loop- and Node-Analysis Approaches to the Simulation of Electrical Networks
Prefender: A Prefetching Defender Against Cache Side Channel Attacks as a Pretender
Further Comments on "Detection of Faults in Programmable Logic Arrays"
MINOTAuR: A Timing Predictable RISC-V Core Featuring Speculative Execution
Vertical Migration of Software Functions and Algorithms Using Enhanced Microsequencing
Adaptive System-Level Diagnosis for Hypercube Multiprocessors
A Framework for Crossing Temperature-Induced Timing Errors Underlying Hardware Accelerators to the Algorithm and Application Layers
On a Varistructured Array of Microprocessors
A New Algorithm for the Discrete Cosine Transform of Arbitrary Number of Points
Multilayer Bus Optimization for Real-Time Embedded Systems
The CSX-l Computer
Inessential Errors in Sequential Machines
Pattern Recognition Signal Processing for Mechanical Diagnostics Signature Analysis
The Architecture of SM3: A Dynamically Partitionable Multicomputer System
On Finite-Memory Sequential Machines
An Algorithm for Fast Evaluation of Time Functions
On the Properties of Sensitized Paths
Harnessing CPU Electromagnetic Emanations for Resonance-Induced Voltage-Noise Characterization
A Novel Cache Architecture and Placement Framework for Packet Forwarding Engines
CloudChain: A Cloud Blockchain Using Shared Memory Consensus and RDMA
GPU Computing for Parallel Local Search Metaheuristic Algorithms
Comments on "Area-Time Optimal Adder Design"
Task Preloading Schemes for Reconfigurable Parallel Processing Systems
Optimal Lexicographic Shaping of Aggregate Streaming Data
Near-Perfect Codes for Binary-Coded Radix- r Arithmetic Units
On the Equivalence Between One-Dimensional Discrete Walsh-Hadamard and Multidimensional Discrete Fourier Transforms
Caravan: Incentive-Driven Account Migration via Transaction Aggregation in Sharded Blockchain
Algorithms for Designing Fault-Detection Experiments ror Sequential Machines
Understanding and Mitigating Twin Function Misuses in Operating System Kernel
Logic Circuit for Cycle Detection in a State Diagram
On Techniques for Coping with the Information Explosion
Comments on a Character Recognition Method of Bledsoe and Browning
A Novel High-Order Tree for Secure Multicast Key Management
Process Recovery in Heterogeneous Systems
Threshold Logic Asymptotes
Sequential Estimation Technique for Enhancement of Noisy Images
Analog-to-Gray Code Conversion
Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors
An Algorithm for Non-Parametric Pattern Recognition
DAP: Domain Adaptive Performance Predictor for Efficient Neural Architecture Search
Schedulability Analysis of Hierarchical Real-Time Systems under Shared Resources
Dynamic Voltage Scaling in Multitier Web Servers with End-to-End Delay Control
Optimal Power Allocation and Load Distribution for Multiple Heterogeneous Multicore Server Processors across Clouds and Data Centers
Approximating Elementary Functions with Symmetric Bipartite Tables
Dependent Task Offloading for Edge Computing based on Deep Reinforcement Learning
Safe Asynchronous Sequential Circuits
Failsafe Logic Nets
On the OBDD-Representation of General Boolean Functions
Comments on "The Design of a Reliable Remote Procedure Call Mechanism"
Another Method for Constructing t-EC/AUED Codes
Transition Factors of Power Consumption Models for CPA Attacks on Cryptographic RISC-V SoC
Guest Editors' Introduction-Mobile Computing: When Mobility Meets Computation
An Analysis of Certain Errors in Electronic Differential Analyzers I-Bandwidth Limitations
ShortPath: A Network-on-Chip Router with Fine-Grained Pipeline Bypassing
Hardware and Software Normal Basis Arithmetic for Pairing-Based Cryptography in Characteristic Three
Multi-Source Information Fusion Based DLaaS for Traffic Flow Prediction
CAM 2 : A Highly-Parallel Two-Dimensional Cellular Architecture
B74-17 The Theory of Parsing, Translation, and Compiling - Volume II: Compiling
Theory and Design of t-Error Correcting, k-Error Detecting and d-Unidirectional Error Detecting Codes with d > k > t
Codesign Tradeoffs for High-Performance, Low-Power Linear Algebra Architectures
Hysteresis-Free Tunnel-Diode Amplitude Comparator
An Efficient Unsorted VLSI Dictionary Machine
An Optimal Instruction-Scheduling Model for a Class of Vector Processors
A Generic Construction of Quantum-Oblivious-Key-Transfer-Based Private Query with Ideal Database Security and Zero Failure
vCUDA: GPU-Accelerated High-Performance Computing in Virtual Machines
Authors' Reply 5
Reliable Unicasting in Faulty Hypercubes Using Safety Levels
Redundancy in Unipolar Field-Effect Transistor Circuits
On The Advantages of Tagged Architecture
An Improved Algorithm for the Generation of Nonparametric Curves
Improved Design of High-Performance Parallel Decimal Multipliers
Error-Detection Schemes for Analog Content-Addressable Memories
Accelerating Pattern Matching Using a Novel Parallel Algorithm on GPUs
New Efficient MDS Array Codes for RAID Part II: Rabin-Like Codes for Tolerating Multiple (greater than or equal to 4) Disk Failures
Privacy Protection for Preventing Data Over-Collection in Smart City
Calculations of Speed of Ladder Network for Superconductive Associative Memories
SMT Malleability in IBM POWER5 and POWER6 Processors
An Algorithm for Detecting Unimodal Fuzzy Sets and Its Application as a Clustering Technique
Evolutionary Pattern Recognition in Incomplete Nonlinear Multithreshold Networks
Long and Fast Up/Down Counters
A Novel Indirect Methodology Based on Execution Traces for Grading Functional Test Programs
Two VLSI Structures for the Discrete Fourier Transform
Implementing Exact Calculations in Hardware
The Role of Operational Simulation to Communications System Design
An Extended XQDD Representation for Multiple-Valued Quantum Logic
Power Efficient Division and Square Root Unit
An Approach for the Realization of Threshold Functions of Order r
The Differential CORDIC Algorithm: Constant Scale Factor Redundant Implementation without Correcting Iterations
Performance Analysis of IEEE 802.15.6 MAC Protocol under Non-Ideal Channel Conditions and Saturated Traffic Regime
Online Container Scheduling With Fast Function Startup and Low Memory Cost in Edge Computing
DARE: A Deduplication-Aware Resemblance Detection and Elimination Scheme for Data Reduction with Low Overheads
B72-25 Artificial Intelligence: The Heuristic Programming Approach
Concurrent Structure-Independent Fault Detection Schemes for the Advanced Encryption Standard
A Machine Organization for a General Purpose List Processor
Three Architecutral Models for Compiler-Controlled Speculative Execution
On a Consistency Testing Model and Strategy for Revealing RISC Processor's Dark Instructions and Vulnerabilities
Remora: A Low-Latency DAG-Based BFT Through Optimistic Paths
Towards Secure Runtime Customizable Trusted Execution Environment on FPGA-SoC
Reliability Evaluation of BC Networks
Some Comments on Postcorrections for Nonrestoring Division
A Note on the Reduction of Switching Functions
The Set Theory of Arithmetic Decomposition
A VLSI Solution to the Vertical Segment Visibility Problem
The Reduction of Redundancy in Solving Prime Implicant Tables
The ILLIAC IV Processing Element
Folding of Symmetric Functions
The Weighted Random Test-Pattern Generator
Content-Aware Low-Power Configurable Aging Mitigation for SRAM Memories
Analysis of Update Synchronization for Multiple Copy Data Bases
Multiple Match Resolvers: A New Design Method
A Measure of Computational Work
Cost-Efficient Delay-Bounded Dependent Task Offloading With Service Caching at Edges
Signal Flow Graph Techniques for Sequential Circuit State Diagrams
Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching
Accelerating Random Forest on Memory-Constrained Devices Through Data Storage Optimization
A function generator for the solution of engineering design problems
B74-40 Digital Systems: Hardware Organization and Design
Algorithms-Based Fault Detection for Signal Processing Applications
A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures
Queueing Network Models for Parallel Processing with Asynchronous Tasks
A New Benes Network Control Algorithm
Suggestion for a Fast Binary Sine/Cosine Generator
k-Approximating Circuits
The Topology of Cellular Partitioning Networks
A General Model for Performance Investigations of Priority Based Multiprocessor System
Analysis of Linear Sequential Circuits by Confluence Sets
Rate-Selective Caching for Adaptive Streaming Over Information-Centric Networks
An Inproved Method for Constructing Multiphase Communications Protocols
A New Method of Formulating a Minimum Edge Set
SIGNED: A Challenge-Response Scheme for Electronic Hardware Watermarking
Autotesting Speed-Independent Sequential Circuits
Comment on "Computing the Shortest Network under a Fixed Topology"
Zero-Aliasing Space Compaction of Test Responses Using a Single Periodic Output
A One-Microsecond Adder Using One-Megacycle Circuitry
A stabilized electronic multiplier
Iterative Combinational Switching Networksߞ General Design Considerations
A Method for Equijoin Queries in Distributed Relational Databases
The NYU Ultracomputer - Designing an MIMD Shared Memory Parallel Computer
Integrated Coverage and Connectivity in Wireless Sensor Networks: A Two-Dimensional Percolation Problem
Identification and Minimization of Linear Machines
Generation of Minimal Vertex Covers for Row/Column Allocation in Self-Repairable Arrays
Statistical Analysis of Second Order Differential Power Analysis
Manipulating General Vectors on Synchronous Binary N-Cube
On the Measurement of Curvature in a Quantized Environment
Working Set and Page Fault Frequency Paging Algorithms: A Performance Comparison
Enabling Efficient Random Data Insertion/Deletion on Block-Based File Systems
Comment on "Some New Results on Average Worst Case Carry"
A Magnetic Core Parallel Adder
Parameter Selection for Server-Aided RSA Computation Schemes
Optimizing Parallel I/O Accesses through Pattern-Directed and Layout-Aware Replication
Learned FBF: Learning-Based Functional Bloom Filter for Key-Value Storage
Solving Boolean Equations Using ROSOP Forms
DEPEND: A Simulation-Based Environment for System Level Dependability Analysis
A Note on the Location of the Binary Point in a Computing Machine
New Characterizations of 2D Discrete Cosine Transform
Modified Twisted-Ring Counter Circuit
Fault-Diagnosis for a Class of Multistage Interconnection Networks
Size-Aware Cache Management for Compressed Cache Architectures
μ*-Tree: An Ordered Index Structure for NAND Flash Memory with Adaptive Page Layout Scheme
Relationship Between P -Valued Majority Functions and P -Valued Threshold Functions
Computing Point Enclosures
Matrix Processors Using p -adic Arithmetic for Exact Linear Computations
Aspects of the Upper Bounds of Finite Input-Memory and Finite Output-Memory Sequential Machines
The Application of Constrained Least Squares Estimation to Image Restoration by Digital Computer
Fast Algorithms for Constructing Minimal Spanning Trees in Coordinate Spaces
LedgerMaze: An Efficient Privacy-Preserving Noninteractive Zero-Knowledge Scheme Over Account-Model Blockchain
Architecture Support for 3D Obfuscation
Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM)
Hybrid Binary-Ternary Number System for Elliptic Curve Cryptosystems
Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding
Investigations of magnetic amplifiers with feedback
A Tree Representation of Combinational Networks
A Two-Space Solution to the Hidden Line Problem for Plotting Functions of Two Variables
A Simple Derivation of the MVA and LBANC Algorithms from the Convolution Algorithm
On Symmetric Error Correcting and All Unidirectional Error Detecting Codes
Schedulability Analysis for Memory Bandwidth Regulated Multicore Real-Time Systems
Counter-Based Compaction: Delay and Stuck-Open Faults
Reliability Enhanced Heterogeneous Phase Change Memory Architecture for Performance and Energy Efficiency
Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems
KVSTL: An Application Support to LSM-Tree Based Key-Value Store via Shingled Translation Layer Data Management
A Voting Approach for Adaptive Network-on-Chip Power-Gating
Lightweight Hardware Transactional Memory for GPU Scratchpad Memory
Sequential Logic and its Application to the Synthesis of Finite Automata
On the Periodic Register Need in Software Pipelining
Improved Affine Arithmetic-Based Precision Analysis for Polynomial Function Evaluation
A Tradeoff Study of Switching Systems in Computer Communication Networks
Fast Random and Sequential Access to Dynamic Memories of Any Size
Comments on "RST Flip-Flop Input Equations"
Random Noise Generation by Hybrid Computer
Aggregation Capacity of Wireless Sensor Networks: Extended Network Case
Control Overhead - A Performance Metric for Evaluating Control-Unit Designs
R68-22 Current Status of Large Scale Integration Technology
Burst Unidirectional Error-Detecting Codes
Adaptive Kernel Fusion for Improving the GPU Utilization While Ensuring QoS
Performance Analysis of Static Locking in Distributed Database Systems
On the Numerical Complexity of Short-Circuit Faults in Logic Networks
A Fault-Tolerant GEQRNS Processing Element for Linear Systolic Array DSP Applications
Stability and Performance of the R-ALOHA Packet Broadcast System
Some Theoretical Properties of Multithreshold Realizable Functions
Computing the Singular Value Decomposition on the Connection Machine
Complexity Analysis of the Cost-Table Approach to the Design of Multiple-Valued Logic Circuits
Hypertree: A Multiprocessor Interconnection Topology
On Implementing Large Binary Tree Architectures in VLSI and WSI
Synergy of Dynamic Frequency Scaling and Demotion on DRAM Power Management: Models and Optimizations
A Simulation Study of Decoupled Architecture Computers
Maximal Autonomous Clocks of Sequential Machines
Design and Analysis of High Performance Multistage Interconnection Networks
Hybrid CORDIC Algorithms
Design and Control of a Three-Stage Switch Matrix in the Presence of Fan-Out
B73-11 Digital Circuits and Devices
Schedulability Analysis for Real-Time Task Set on Resource with Performance Degradation and Dual-Level Periodic Rejuvenations
Partitioning and Permuting Properties of CC-Banyan Networks
Comments on Armstrong's State Assignment Techniques
Conflict Resolution and Fault-Free Path Selection in Multicast-Connected Cube-Based Networks
Dynamic Accuracy as a Design Criterion of Linear Electronic-Analog Differential Analyzers
The Further Reduction of CC-Tables
A Semantically Guided Deductive System for Automatic Theorem Proving
Aliasing Probability for Multiple Input Signature Analyzer
Protection Against External Errors in a Dedicated System
An Iterative Cell Switch Design for Hybrid Redundancy
Enhanced Utilization Bounds for QoS Management
Guest Editors' Introduction: Special Issue on Computer Arithmetic
Computing Functions cos^{-1} and sin^{-1} Using Cordic
On the Tradeoff Between Response and Preemption Costs in a Foreground-Background Computer Service Discipline
On Control Memory Minimization in Microprogrammed Digital Computers
Effect of Finite Gain on One-Amplifier Circuits
An Application of Relaxation Labeling to Line and Curve Enhancement
Online Test of Control Flow Errors: A New Debug Interface-Based Approach
A 3D Skewing and De-skewing Scheme for Conflict-Free Access to Rays in Volume Rendering
Comparison of Parallel and Deductive Fault Simulation Methods
Technology and Design Tradeoffs in the Creation of a Modern Supercomputer
Dynamic Caching Dependency-Aware Task Offloading in Mobile Edge Computing
Error Correcting Properties of Redundant Residue Number Systems
R68-11 Intercommunication of Processors and Memory
Enforcing Predictability of Many-Cores With DCFNoC
Comments on "Inner Product Computers"
Experiments in Automatic Microcode Generation
Parallel Balancing of Binary Search Trees
FutureDID: A Fully Decentralized Identity System With Multi-Party Verification
Toggle-Registers Generating in Parallel k k th Decimations of m -Sequences x p + x k + 1 Design Tables
Incrementing a Bit-Reversed Integer
A Look-Up Scheme for Scaling in the RNS
Piecewise-Functional Broadside Tests Based on Reachable States
B74-5 Computer-Oriented Approaches to Pattern Recognition
Accelerating Coverage Estimation Through Partial Model Checking
Tensor Recurrent Neural Network With Differential Privacy
ProgressFace: An Algorithm to Improve Routing Efficiency of GPSR-Like Routing Protocols in Wireless Ad Hoc Networks
Iterative Analog Computation and the Representation of Signals
Guest Editorial: IEEE TC Special Issue on Domain-Specific Architectures for Emerging Applications
Detecting Spectre Attacks Using Hardware Performance Counters
Rigorous Treatments of Variable Time Delays
On the Fast Fourier Transform on Finite Abelian Groups
Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems
Computer Model of Gambling and Bluffing
Asymptotic Aproximations for the Number of Fanout-Free Functions
Symmetric Latin Squares
Solving the Subset Sum Problem via Quantum Walk Search
Parallel Sorting with Serial Momories
Design, Implementation, and Performance Evaluation of a Detection-Based Adaptive Block Replacement Scheme
Exploiting Parallelism in Geometry Processing with General Purpose Processors and Floating-Point SIMD Instructions
Reliability Index of Teleprocessing Tree Networks
A Parallel Time/Hardware Tradeoff T . H = O(2^{n/2}) for the Knapsack Problem
Comments on "Network Resilience: A Measure of Network Fault Tolerance"
Low-Weight Polynomial Form Integers for Efficient Modular Multiplication
Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation
Impact of Checkpoint Latency on Overhead Ratio of a Checkpointing Scheme
Implementation and Test of the ACRITH Facility in a System/370
Minimizing Conflicts Between Vector Streams in Interleaved Memory Systems
An Algorithm for Optimal Logic Design Using Multiplexers
A Transistor-Driven Magnetic-Core Memory
The Parallel Multi-Mode Digraph Task Model for Energy-Aware Real-Time Heterogeneous Multi-Core Systems
A Fast and Flexible Thinning Algorithm
B74-24 Computer Simulation of Dynamic Systems
Semantically Reliable Multicast: Definition, Implementation, and Performance Evaluation
SAHYB-A Program for Simulation of Analog and Hybrid Computers
Performability Modeling Based on Real Data: A Case Study
The Illinois Pattern Recognition Computer-ILLIAC III
Fault Tolerant Sequential Machines
CloudMon: Monitoring Virtual Machines in Clouds
Cryosar Memory Design
Microprogram Optimization: A Survey
The Use of Hybrid Computing in the Analysis of Steel Rolling
A Method to Increase the Accuracy of Fast-Serial-Parallel Analog-to-Digital Converters
Analysis of Memory Interference in Multiprocessors
Load Sharing with Consideration of Future Task Arrivals in Heterogeneous Distributed Real-Time Systems
Bypass Switching for Cellular Cascades
A Nonlinear Mapping for Data Structure Analysis
Comments on "Minimization of Fuzzy Functions"
Diagnosis of Large Combinational Networks
Identifying Minimal Shift Counters: A Search Technique
On Complete Sets of Logic Primitives
Content Discovery and Caching in Mobile Networks with Infrastructure
A Class of Algorithms for Fast Digital Image Registration
Quality Configurable Approximate DRAM
A Card-Changeable Permanent-Magnet-Twistor Memory of Large Capacityt
Logical Networks of Flexible Cells
Optimal Task Assignment in Linear Array Networks
Applications of the Charge-Control Theory
Correct-by-Construction Design of Custom Accelerator Microarchitectures
A Testable PLA Design with Low Overhead and High Fault Coverage
Multiple Operand Addition and Multiplication
An Algorithm for High-Speed Digital Filters
Alternative Strategies for Improving the Fairness in and an Analytical Model of the DQDB Network
Snitch: A Tiny Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads
On Fault Simulation for Synchronous Sequential Circuits
Privacy and Security Issues in Information Systems
Probabilistic Error Modeling for Approximate Adders
Theory and Design of t-Unidirectional Error-Correcting and d-Unidirectional Error-Detecting Code
Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache
On the Three-Valued Simulation of Digital Systems
A Stochastic Model for Estimating the Power Consumption of a Processor
A Systolic Algorithm for the k-Nearest Neighbors Problem
Efficient Techniques for Binary-to-Multidigit Multidimensional Logarithmic Number System Conversion Using Range-Addressable Look-Up Tables
Efficient Resource Placement in Hypercubes Using Multiple-Adjacency Codes
New Parallel-Sorting Schemes
A Note on "A Systematic (12, 8) Code for Correcting Single Errors and Detecting Adjacent Errors"
Hyperneural Network-An Efficient Model for Test Generation in Digital Circuits