yusuke1997/dblp-id-title huggingface dataset:
Design of Oscillator-Based Reconfigurable Modulator With High-Q FBAR Resonators Supporting Fast OOK/BFSK/ BPSK Modulation
Fuzzy-Based Bipartite Quasi-Synchronization of Fractional-Order Heterogeneous Reaction-Diffusion Neural Networks via Intermittent Control
A 2.793 μW Near-Threshold Neuronal Population Dynamics Trajectory Filter for Reliable Simultaneous Localization and Mapping
Novel Design Space of Broadband High-Efficiency Parallel-Circuit Class-EF Power Amplifiers
Modular Expansion Method for Wireless Power Transfer Systems With Arbitrary Topologies
A 555 Timer IC Chaotic Circuit: Chaos in a Piecewise Linear System With Stable but No Unstable Equilibria
A 94-GHz 16T1R Hybrid Integrated Phased Array With ±50° Scanning Range for High-Date-Rate Communication
A Persistent-Excitation-Free Method for System Disturbance Estimation Using Concurrent Learning
Almost Sure Synchronization of Multilayer Networks via Intermittent Pinning Noises: A White-Noise-Based Time-Varying Coupling
Monolithic GaN-Based Multiple-Phase Bidirectional Energy Transfer With Seamless Control Applied on High-Voltage and Low-Voltage Batteries
Toward Efficient Eye Tracking in AR/VR Devices: A Near-Eye DVS-Based Processor for Real-Time Gaze Estimation
A 701.7 TOPS/W Compute-in-Memory Processor With Time-Domain Computing for Spiking Neural Network
A Decentralized Resilient Control Scheme for DC Microgrids Against Faults on Sensor and Actuator
An Efficient Digital Realization of Retinal Light Adaptation in Cone Photoreceptors
Circuit Solutions Toward Broadband Piezoelectric Energy Harvesting: An Impedance Analysis
Wave Digital Extended Fixed-Point Solvers for Circuits With Multiple One-Port Nonlinearities
An Analog Circuit Building Block Generator via Nested Multi-Fidelity Modeling
Joint Digital Online Compensation of TX and RX Time-Varying I/Q Mismatch and DC-Offset in mmWave Transceiver System
A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing
A 0.35mm 2 94.25μ W Fully Integrated NFC Tag IC Using 0.13μ m CMOS Process
A 28-/60-GHz Dual-Band Receiver Front-End With Sideband-Selection Technique in 65-nm CMOS
Real-Time Block-Based Embedded CNN for Gesture Classification on an FPGA
An Energy-Efficient, High-Frame-Rate, and Reconfigurable EKF-SLAM Processor With Full Acceleration for Autonomous Mobile Robots
ARV-Q: An Adaptive RISC-V Vector Processor for Unified Support of Post-Quantum Standards and Side-Channel Protection on the Edge
A 50-V 50-MHz High-Noise-Immunity Capacitive-Coupled Level Shifter With Digital Noise Blanker for GaN Drivers
An 8-MS/s 16-bit SAR ADC With Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process
A Half-Schmitt Trigger-Based 9T1R Nonvolatile Robust SRAM Cell for Instant On-Off Application
A Scalable Precoding Processor for Large-Scale MU-MIMO Systems
Noise-Assisted Graph Multivariate Empirical Mode Decomposition With Non-Uniform Projections
Fixed-Time Consensus Tracking of Multiagent System Under DOS Attack With Event-Triggered Mechanism
Analysis of Conditional Stability and Unconditional Stability and Instability for Microwave 3-Ports
Measurement-Based Quantum Sealed-Bid Auction
Non-Binary Spin Wave Based Circuit Design
Fully Distributed Output Regulation of Linear Discrete-Time Multi-Agent Systems With Markov Switching Topology
NbO 2 -Mott Memristor: A Circuit- Theoretic Investigation
A 10-Bit 2.5-GS/s Two-Step ADC With Selective Time-Domain Quantization in 28-nm CMOS
An On-Board Satellite Multispectral and Hyperspectral Compressor (MHyC): An Efficient Architecture of a Simple Lossless Algorithm
Dynamic Self-Triggered Robust Distributed Model Predictive Control for Coupled Nonlinear Systems
Secure State Estimation-Based Stabilization of IoT-Enabled Wireless Power Transfer Systems
A 0.4-0.9 V Supply Voltage-Flexible Third-Order Passive ΔΣ Modulator With Switched-Capacitor Loop Filter Achieving 71.9 dB Peak SNDR at 4 MHz Bandwidth
Revisiting Dynamic Logic - A True Candidate for Energy-Efficient Cryogenic Operation in Nanoscaled Technologies
Time-Synchronized Control of Chaotic Systems in Secure Communication
Circular Wireless RF Systems With Recyclable and Degradable Components Based on Additively-Manufactured Liquid Metal Interconnects
Distributed Meta-Deep Reinforcement Learning for Wide Area Frequency Control of Interconnected Grid Considering Multi-Time Scale Coordination
CHAMP: Channel Merging Process for Cost-Efficient Highly-Pruned CNN Acceleration
AM-CIM: Approximate Memory Based Near Sensor Compute-in-Memory Architecture for Keyword Spotting
A Reduced-Area Capacitor-Only Loop Filter With Polarity-Switched G m for Large Multiplication Factor Millimeter-Wave Sub-Sampling PLLs
An Ultra-Low-Power Widely-Tunable Complex Band-Pass Filter for RF Spectrum Sensing
A Reconfigurable FeFET Content Addressable Memory for Multi-State Hamming Distance
Enhancing Voltage Control Stability of Grid-Forming VSCs Under PWM Delays: A Study on Feedforward Damping Methods
Efficient Memristive Stateful Logic Exploring Boolean Expressions in the Sum-of-Products Form
Enclosing Control of UAV Swarm With Distributed Neighbor Selection and Finite-Time Observer in Three-Dimensional Environment
Active Circuits With Diodes: Topological Conditions Sufficient to Determine the State of a Diode
Design and Analysis of Passive-Integrated Absorptive Flat-Group-Delay RF Bandpass Filters in GaAs Technology for Digital Communications
Synchronization and Coupling Dynamics in Memristive Homogeneous and Heterogeneous Hopfield Neural Networks
A 0.6 V, 1.74 mW, 2.9 dB NF Inductorless Wideband LNA in 28-nm CMOS Exploiting Noise Cancellation and Current Reuse
Correction to "Design of Multi-Port With Desired Reference Impedances Using Y-Matrix and Matching Networks"
Energy- and Area-Efficient CMOS Synapse and Neuron for Spiking Neural Networks With STDP Learning
Accurate Hardware Predictor for Epileptic Seizure
ASC: Adaptive Scale Feature Map Compression for Deep Neural Network
Stackelberg and Nash Equilibrium Computation in Non-Convex Leader-Follower Network Aggregative Games
Transient Fault Detection and Failure Effect Analysis Based on Design for Test and Fault Tree Analysis for Automotive Chips
Method to Determine Quantization-Related Parameters of the Digital-to-Time Converter in a Fractional-N Frequency Synthesizer
A Capacitively Coupled CT Δ ΣM With Chopping Artifacts Rejection for Sensor Readout ICs
Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs
SSHI and Analog MPPT Integration-Based Self-Powered Interfacing Circuit for Piezoelectric Vibration Energy Harvester
A 10-bit 563-fs Step Constant-Slope Digital-to-Time Converter in 40-nm CMOS With Nonlinearity Cancellation and Range Extension Techniques
Interpretable Memristive LSTM Network Design for Probabilistic Residential Load Forecasting
Privacy-Preserving Consensus for Multi-Agent Systems via Node Decomposition Strategy
Over-the-Air Linearization of Phased Array Transmitters Affected by Load Modulation
A 3.78-GHz Type-I Sampling PLL With a Fully Passive K PD -Doubled Primary-Secondary S-PD Measuring 39.6-fs RMS Jitter, -260.2-dB FOM, and -70.96-dBc Reference Spur
Logic Neural Networks for Efficient FPGA Implementation
An Energy-Efficient Accelerator for Medical Image Reconstruction From Implicit Neural Representation
Improved Vertex Coloring With NbOₓ Memristor-Based Oscillatory Networks
An Efficient Approximate Expectation Propagation Detector With Block-Diagonal Neumann-Series
First Demonstration of Power-Linear Regulator for Thermo-Optic Phase Tuning
A Charge-Domain Scalable-Weight In-Memory Computing Macro With Dual-SRAM Architecture for Precision-Scalable DNN Accelerators
Programmable In-Memory Computing Circuit for Solving Combinatorial Matrix Operation in One Step
SHMT: An SRAM and HBM Hybrid Computing-in-Memory Architecture With Optimized KV Cache for Multimodal Transformer
Q/V-Band CMOS Beamforming ICs and Integrated Phased-Array Antennas
Capacitive Wireless Power Transfer System With Inductorless Receiver Side
A Knowledge Distillation Online Training Circuit for Fault Tolerance in Memristor Crossbar Array-Based Neural Networks
Fixed-Time Generalized VGESO-Based Trajectory Tracking Control for WMRs on Uneven Road: A Fully Actuated System Approach
Energy-Quality Scalable Design Space Exploration of Approximate FFT Hardware Architectures
Hybrid Event-Triggered Approach for Quasi-Consensus of Uncertain Multi-Agent Systems With Impulsive Protocols
Rethinking the Designing of Convolution Engine for Reconfigurable CNN Accelerator Using Sparse-Based Design Scheme
Neural-Network-Based Control With Dynamic Event-Triggered Mechanisms Under DoS Attacks and Applications in Load Frequency Control
Guest Editorial Special Issue on the International Symposium on Integrated Circuits and Systems - ISICAS 2021
Single-Sided Interspiraled Inductive Impedance Matching for Magnetic Resonance Wireless Power Transfer
Fixed-Time Stabilization of Multi-Weighted Complex Networks via Novel Adaptive Pinning Chatter-Free Control and Its Applications
Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K
ARBiS: A Hardware-Efficient SRAM CIM CNN Accelerator With Cyclic-Shift Weight Duplication and Parasitic-Capacitance Charge Sharing for AI Edge Application
Hybrid-Bridge-Based Dual-Active-Bridge Converter With an Asymmetric Active-Neutral-Point-Clamped Three-Level Bridge
A Subgraph-Based Hierarchical Q-Learning Approach to Optimal Resource Scheduling for Complex Industrial Networks
A Universal Methodology of Complex Number Computation for Low-Complexity and High-Speed Implementation
Phase Noise Analysis of Separately Driven Ring Oscillators
A Novel ASIC Design Flow Using Weight-Tunable Binary Neurons as Standard Cells
An Energy Efficient STDP-Based SNN Architecture With On-Chip Learning
Observer-Based Bipartite Containment Control for Singular Multi-Agent Systems Over Signed Digraphs
A 7700-PPI 640 × 480 Micro-LED Display Backplane Driver Chip With 1.15-Transistor Pixel Circuits by Using 0.18-μm CMOS Technology
Accurate Modeling of the Effective Parasitic Parameters for the Laminated Busbar Connected With Paralleled SiC MOSFETs
CorTile: A Scalable Neuromorphic Processing Core for Cortical Simulation With Hybrid-Mode Router and TCAM
Variation-Tolerant and Low R-Ratio Compute-in-Memory ReRAM Macro With Capacitive Ternary MAC Operation
FPGA Implementation of Memristor Emulators Using Fractional Order Calculus: A High-Precision Reconfigurable Approach
Multi-Estimator Framework for Robust FDI Attack Detection in Smart Grids
An Improved Predictive Current Control of Eight Switch Three-Level Post-Fault Inverter With Common Mode Voltage Reduction
A Complexity-Efficient Quantum Architecture and Simulation for Eigen Spectrum Estimation of Vandermonde System in a Large Antenna Array
Toward the Multiple Constant Multiplication at Minimal Hardware Cost
A Novel Digital Control Method of Primary-Side Regulated Flyback With Active Clamping Technique
Gauss Hermite Fourier Features Based on Maximum Correntropy Criterion for Adaptive Filtering
Scalable Machine Learning to Estimate the Impact of Aging on Circuits Under Workload Dependency
Impact of Non-Volatile Memory Cells on Spiking Neural Network Annealing Machine With In-Situ Synapse Processing
A 28-nm 3.32-nJ/Frame Compute-in-Memory CNN Processor With Layer Fusion for Always-on Applications
BitS-Net: Bit-Sparse Deep Neural Network for Energy-Efficient RRAM-Based Compute-In-Memory
Transmission and Decision-Making Co-Design for Active Support of Region Frequency Regulation Through Distribution Network-Side Resources
Dynamic Composite Nonlinear Output Feedback Control of ICPT System: When Markov Jumping Systems Meet Event-Triggering Mechanism
Inner Product Computation In-Memory Using Distributed Arithmetic
Robust Guaranteed Synchronization for Chaotic Systems With Incremental Quadratic Constraints
LLD: Lightweight Latency Decrease Scheme of LDPC Hard Decision Decoding for 3-D TLC NAND Flash Memory
A 7-Bit 7-GHz Multiphase Interpolator-Based DPC for CDR Applications
Novel Optimized Implementations of Lightweight Cryptographic S-Boxes via SAT Solvers
High Efficiency Multiply-Accumulator Using Ternary Logic and Ternary Approximate Algorithm
A Wide Tracking Range Heterodyne Phase-Tracking Receiver With 1-bit Phase-Domain Demodulation
Analog Optimization Circuit for Embedded Model Predictive Control
Quantum Protocol for Secure Multiparty Logical AND With Application to Multiparty Private Set Intersection Cardinality
EO-Shield: A Shield-Based Protection Scheme Against Both Invasive and Non-Invasive Attacks
Evaluating Performances and Importance of Venture Capitals: A Complex Network Approach
Asynchronous Event-Triggered Sliding Mode Control for Semi-Markov Jump Systems Within a Finite-Time Interval
Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits
High Dynamic Range Digital Neuron Core With Time-Embedded Floating-Point Arithmetic
A Parallel Read-Write Circuit With Fast Amplitude-Adaptive Matching Scheme to Memristor Crossbar Array
Guest Editorial Special Issue on the Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2022)
Probabilistic Compute-in-Memory Design for Efficient Markov Chain Monte Carlo Sampling
Extended Dissipative Scalable Control for AC Islanded Microgrids
A 216 × 216 Global-Shutter CMOS Image Sensor With Embedded Analog Memory and Automatic Exposure Control for Under-Display Optical Fingerprint Sensing Applications
A 593nJ/Inference DVS Hand Gesture Recognition Processor Embedded With Reconfigurable Multiple Constant Multiplication Technique
Full-Analog Reservoir Computing Circuit Based on Memristor With a Hybrid Wide-Deep Architecture
A 2-6 GHz Reconfigurable High Dynamic Range Receiver With Wideband Variable Gain LNA
The Constant Multiplier FFT
Finite-Time Adaptive Neural Network Observer-Based Output Voltage-Tracking Control for DC-DC Boost Converters
A Constant gₘ Current Reference Generator With Pseudo Resistor-Based Compensation
Memristor Crossbar Arrays Performing Quantum Algorithms
Prescribed Performance Control for Double-Integrator Multi-Agent Systems: A Unified Event- Triggered Consensus Framework
Dominant-Node Theory and Monitoring-Rescue Method for Eliminating Undesired Operating Points in the Self-Biased Reference Generators
A 2-20-GHz 360° Variable Gain Phase Shifter MMIC With Reverse-Slope Phase Compensation
Generalized Multilevel Code-Shifted Differential Chaos Shift Keying Modulation System
ARYABHAT: A Digital-Like Field Programmable Analog Computing Array for Edge AI
Dynamic Event/Self-Triggered Full-State Bipartite Containment Control for Nonlinear Multi-Agent Systems Under Switching Topologies
A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW 2 Pipeline and Adaptive-Resolution Quantization
A Low-Cost Error-Tolerant Flip-Flop Against SET and SEU for Dependable Designs
A High-Current Scalable Parallel LDO Scheme With Analog-Digital Merged Control for Small Current-Sharing Mismatch
Design and Implementation of Dual-Mode Support Vector Machine (SVM) Trainer and Classifier Chip Architecture for Human Disease Detection Applications
An Energy Efficient Coherent IR-UWB Receiver With Non-Coherent-Assisted Synchronization
VLSI Architectures of Approximate Arithmetic Units Applied to Parallel Sensors Calibration
A Shallow Neural Network for Real-Time Embedded Machine Learning for Tensorial Tactile Data Processing
Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators
A Single-Ended Phase and Impedance Invariant mm-Wave VGPA Based on Shunt CS-CG Topology
The Digital-Assisted Charge Amplifier: A Digital-Based Approach to Charge Amplification
FDSOI-Based Analog Computing for Ultra-Efficient Hamming Distance Similarity Calculation
Voltage Boosted Fail Detecting Circuit for Selective Write Assist and Cell Current Boosting for High-Density Low-Power SRAM
Low-Voltage CMOS Capacitor-Less LDOs: Bulk-Driven Versus Gate-Driven Comparative Study
Adaptive Tracking Control of Constrained Nonlinear Systems and Its Application to Circuit Systems
A Graph-Based Accelerator of Retinex Model With Bit-Serial Computing for Image Enhancements
A Timing-Constrained Design Methodology for Radix- 2 k NTT in Polynomial Arithmetic
MARLIN: A Co-Design Methodology for Approximate ReconfigurabLe Inference of Neural Networks at the Edge
Rectifying Network Common Items Extraction for Complex Multi-Band Rectifiers: Theory, Design, and Experimental Verification
Hybrid Precoding Baseband Processor for 64 × 64 Millimeter Wave MIMO Systems
Finite-Time Fault Estimation and Tolerant Control for Nonlinear Interconnected Distributed Parameter Systems With Markovian Switching Channels
CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization
Stabilization of Markov Jump Systems With Delay by Discrete-Time Aperiodically Intermittent Stochastic Control Based on Lévy Noise
Incorporating Directionality in Transversal-Resonator-Based Bandpass Filters With Tunable Transfer Function Characteristics
Selectivity Versus Noise Trade-Offs in Resistively Driven Passive Switched-Capacitor Infinite Impulse Response Low-Pass Filters
A SiPM-Based Gamma Spectrometer With Field-Programmable Energy Binning for Data-Efficient Isotope Analysis
Adaptive Prescribed-Time Control of Switched Nonlinear Systems With False Data Injection Attacks
Analysis and Design of Fourth Harmonic Boosting Technique for THz Signal Generation
A SPAD-Based Hybrid Time-of-Flight Image Sensor With PWM and Non-Linear Spatiotemporal Coincidence
Simultaneous Optimization of Various-Sized SRAM Instances Through Machine Learning-Driven Transistor Sizing and Leafcell Circuit Pool Construction
A Wide-Range Inter-Wire De-Skewing for IL Warping Mitigation in Spatially Correlated Coded Signaling-Based Transceiver
Efficient Implementation of Spontaneous Calcium Oscillations in the Central Nervous System on Reconfigurable Digital Boards
An Optimized Radiation Tolerant Baseline Correction Filter for HEP Using AI Methodologies
A Fast, Energy Efficient and Tunable Magnetic Tunnel Junction Based Bitstream Generator for Stochastic Computing
An 8T PA Attack Resilient NVSRAM for In-Memory-Computing Applications
An Energy-Efficient SAR ADC With a Coarse-Fine Bypass Window Technique
Duty-Cycle-Optimized Voltage Predictive Control for Four-Leg Inverters With Over-Modulation Capability
Quasi-Synchronization of Heterogeneous LC Circuits in Grid-Connected Systems With Intentionally Time-Varying Lumped Delays
A 0.14-nJ/b 200-Mb/s 2.7-3.5-GHz Quasi-Balanced FSK Transceiver With PLL-Based Modulation and Sideband Energy Detection
A Dynamic Capacitance Matching (DCM)-Based Current Response Algorithm for Signal Line RC Network
Memristor-Based Circuit Design of Biological Behavior Chain
Event-Driven Vision Sensor With In-Pixel Spatial Contrast Computation Capabilities and On-Chip AER Sequencer
Modeling, Analysis, and Design of Phase Synchronization Loop for BIPT System Considering Operating Point Parameters Variation
FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge
An Integrator-Differentiator Transimpedance Amplifier Using Tunable Linearized High-Value Multi-Element Pseudo-Resistors
A 76-82 GHz VCO in 65 nm CMOS With 189.3 dBc/Hz PN FOM and -0.6 dBm Harmonic Power for mm-Wave FMCW Applications
Concurrent Learning Adaptive Command Filtered Backstepping Control for High-Order Strict-Feedback Systems
A Comprehensive Framework for the Thévenin-Norton Theorem Using Homogeneous Circuit Models
Fault-Tolerant Consensus of Multi-Agent Systems Subject to Multiple Faults and Random Attacks
A 71.2-μW Speech Recognition Accelerator With Recurrent Spiking Neural Network
Series Loss-Free Resistor as Stabilizing Active Damping of Constant-Power Load Systems
FireFly-S: Exploiting Dual-Side Sparsity for Spiking Neural Networks Acceleration With Reconfigurable Spatial Architecture
Nonlinear Analysis of Cross-Coupled Super-Regenerative Oscillators
Soft-Error-Immune Read-Stability-Improved SRAM for Multi-Node Upset Tolerance in Space Applications
A 5-mW 30-GHz Quasi-Rotary Traveling-Wave Oscillator With Extrinsic-Q-Enhanced Transmission Line
Constructing Higher-Dimensional Digital Chaotic Systems via Loop-State Contraction Algorithm
Grid Hyperchaotic System With Stable Equilibria
Energy-Efficient Data Transmitters Achieving Energy Per Bit Beyond CV 2 Limitation
Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL
An Integrated Dual-Mode Precise Bias Circuit and a Low-Noise and Wideband AFE for Fly Height Sensors in Hard Disk Drives
Practical Prescribed-Time Synchronization for Multiweighted Complex Networks
Dynamic Event-Triggered Secure Cooperative Control of Second-Order Nonlinear Multi-Agent Systems Under DoS Attacks
77.3-GHz Standing-Wave Oscillator Based on an Asymmetrical Tunable Slow-Wave Coplanar Stripline Resonator
A 0.15-μs/V Buck-Boost Symbol-Power-Tracking Supply Modulator With Dual Auxiliary Current Paths and EPP Scheme for 5G NR Power Amplifiers
Prescribed Performance Control for a Nonlinear System With Actuator Saturation via Anti-Windup Design
MC-CIM: Compute-in-Memory With Monte-Carlo Dropouts for Bayesian Edge Intelligence
Multi-Objective Digital Design Optimization via Improved Drive Granularity Standard Cells
MGARoute: Efficient Analog Routing With Multi-Stage Rip-Up and Rerouting Under Geometric and Symmetry Constraints
DCiROM: A High-Density Fully-Digital Compute-in-Read-Only-Memory Macro for Energy-Efficient Task-Level DNN Inference
Ultra-Low-V IN Dual-Dimensional Reconfigurable Charge Pump With Enhanced Power Conversion Efficiency and Extended Power Dynamic Range for Micro-Energy Harvesting Applications
A Real-Time Architecture for Pruning the Effectual Computations in Deep Neural Networks
Dual Input Digitally Controlled Broadband Three-Stage Doherty Power Amplifier With Back-Off Reconfigurability
Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications
MobileSP: An FPGA-Based Real-Time Keypoint Extraction Hardware Accelerator for Mobile VSLAM
A High Current NMOS LDO Handles a Wide Range of Load Capacitors With Output Impedance Shaping Technique
Analysis of Off-Resonant Flexible Tertiary Coils in Biomedical Implants for Back Telemetry Detection
Modeling and Signal Integrity Analysis of RRAM-Based Neuromorphic Chip Crossbar Array Using Partial Equivalent Element Circuit (PEEC) Method
An Efficient Fault-Tolerant Protection Method for L0 BTB
Energy-Efficient Single-Ended Read/Write 10T Near-Threshold SRAM
An Efficient and Accurate Memristive Memory for Array-Based Spiking Neural Networks
A Heterogeneous and Reconfigurable Decoder for the IEEE 1901 Standard
SecureX: Strategically Securing Designs Against Oracle-Less Attacks Using GNN-Based Explainers
FPGA Implementation of Reconfigurable CORDIC Algorithm and a Memristive Chaotic System With Transcendental Nonlinearities
A 64 Kb Reconfigurable Full-Precision Digital ReRAM-Based Compute-In-Memory for Artificial Intelligence Applications
Event-Based Extended Dissipative State Estimation for Memristor-Based Markovian Neural Networks With Hybrid Time-Varying Delays
An Adaptive On-Off-Delay Compensation Scheme Based on Dead-Time and Rectified-Current Sampling for Ampere-Current-Level Series-Series Wireless Power Receivers
Statistical Observations of Three Co-Existing NBTI Behaviors in 28 nm HKMG by On-Chip Monitor With Less Recovery Impact
A Mixed-Signal Quantized Neural Network Accelerator Using Flash Transistors
A 500-kS/s Continuous-Time Linear-Exponential Incremental ADC Achieving 90.1-dB DR and 103.1-dB SFDR
Exploiting Body-Driven Feedbacks in Physical Unclonable Functions for Ultra Low Voltage, Ultra Low Power Applications: A 0.3 V Weak-PUF
NASA+: Neural Architecture Search and Acceleration for Multiplication-Reduced Hybrid Networks
A Dynamic System Approach to Spiking Second Order Memristor Networks
A 0.5-1.7 V Efficient and PVT-Invariant Constant Subthreshold g m Reference Circuit in CMOS
Anomaly Detection in Graph Signals With Complex Wavelet Packet Correlation Mining