yusuke1997/dblp-id-title huggingface dataset:
Multioperand Redundant Adders on FPGAs
An Optimum Character Recognition System Using Decision Functions
New Strategies for Assigning Real-Time Tasks to Multiprocessor Systems
A Novel Distributed Sensor Positioning System Using the Dual of Target Tracking
A Real-Time Locking Protocol
Principles of Data Structure Error Correction
Roundings in Floating-Point Arithmetic
Micro-Architectural Analysis of Time-Driven Cache Attacks: Quest for the Ideal Implementation
A Continous-Parameter Markov Model and Detection Procedures for Intermittent Faults
Distributed Assignment Algorithms for Multihop Packet Radio Networks
Logic Circuits Using Square-Loop Magnetic Devices: A Survey
Energy-Aware Scenario-Based Mapping of Deep Learning Applications Onto Heterogeneous Processors Under Real-Time Constraints
Transient Analysis of Some Rewarded Markov Models Using Randomization with Quasistationarity Detection
Internal State Assignments for Asynchronous Sequential Machines
Folding BIKE: Scalable Hardware Implementation for Reconfigurable Devices
Optimal Configuring of Multiple Scan Chains
Comment on "A method for the selection of prime implicants"
Efficient and Fast High-Performance Library Generation for Deep Learning Accelerators
Thermal Modeling and Management of DRAM Systems
Comments on "Monotone Functions in Sequential Circuits"
Guaranteeing Delay of Live Virtual Machine Migration by Determining and Provisioning Appropriate Bandwidth
Lightweight Blockchain-Empowered Secure and Efficient Federated Edge Learning
Variable Latency Goldschmidt Algorithm Based on a New Rounding Method and a Remainder Estimate
Scavenger+: Revisiting Space-Time Tradeoffs in Key-Value Separated LSM-Trees
An Executable Specification and Verifier for Relaxed Memory Order
AR-Light: Enabling Fast and Lightweight Multi-User Augmented Reality via Semantic Segmentation and Collaborative View Synchronization
Additional Comments on " An Optimal Solution for the Channel-Assignment Problem"
3D Integration of CMOL Structures for FPGA Applications
GPU-to-GPU and Host-to-Host Multipattern String Matching on a GPU
Closed-Form Expression for the Average Weight of Signed-Digit Representations
Ferrite Toroid Core Circuit Analysis
Negative Base Number Systems
PODTherm-GP: A Physics-Based Data-Driven Approach for Effective Architecture-Level Thermal Simulation of Multi-Core CPUs
An Efficient State Minimization Algorithm for Some Special Classes of Incompletetly Specified Sequential Machines
Semiconductor Parametric Diodes in Microwave Computers
Exploring Design Challenges in Getting Solid State Drives Closer to CPU
Comments on "Fault-Tolerant Asynchronous Networks"
Fourier Transforms in VLSI
Kronecker Products and Shuffle Algebra
Modeling Unusual Behavior of Parallel Algorithms
An Efficient Method for Improving Reliability of a Pipeline FFT
Data Flow Computing - Software Development
Analysis of a Local-Area Bus System with Controlled Access
The Design of a Testable Parallel Multiplier
Hardware Design of an Advanced-Feature Cryptographic Tile Within the European Processor Initiative
Comments on "Design and Analysis of Arbitration Protocols"
The Discrete Equation of the Straight Line
Utilizing Bandwidth Sharing in the Slotted Ring
New Parallel Approaches for Scalar Multiplication in Elliptic Curve over Fields of Small Characteristic
Truncated Online Arithmetic with Applications to Communication Systems
Multiple Fault Detection in Parity Checkers
Performance Analysis and Optimization of Distributed Workflows in Heterogeneous Network Environments
Minimal Closed Partitions for Incompletely Specified Flow Tables
A Conflict Sense Routing Protocol and Its Performance for Hypercubes
A Hypergraph Model for Fault-Tolerant VLSI Processor Arrays
Automatic Application of Power Analysis Countermeasures
OFEI: A Semi-Black-Box Android Adversarial Sample Attack Framework Against DLaaS
Layout Influences Testability
A Fault Tolerant Hybrid Memory Structure and Memory Management Algorithms
PBC: A Partially Buffered Crossbar Packet Switch
Comparative Performance Analysis of Single Bus Multiprocessor Architectures
Enhancing Neural Network Reliability: Insights From Hardware/Software Collaboration With Neuron Vulnerability Quantization
A Versatile Architecture for the Distributed Sensor Integration Problem
A Practical Adversarial Attack Against Sequence-Based Deep Learning Malware Classifiers
Design and Analysis of Efficient Maximum/Minimum Circuits for Stochastic Computing
Construction of Systematic Codes for Unidirectional Error Control
Overlapped Operation with Microprogramming
A Method for Transposing Externally Stored Matrices
The Carry-Dependent Sum Adder
Simply Invertible Matrices
A Routing and Broadcasting Scheme on Faulty Star Graphs
A Real/Complex Logarithmic Number System ALU
Compound Synthesis of Threshold-Logic Network for the Realization of General Boolean Functions
DMACN: A Dynamic Multi-Attribute Caching Mechanism for NDN-Based Remote Health Monitoring System
Quantization Complexity and Independent Measurements
On Transposing Large 2 n × 2 n Matrices
Restricted Checking Sequences for Sequential Machines
BEAST-GNN: A United Bit Sparsity-Aware Accelerator for Graph Neural Networks
A radio-frequency nondestructive readout for magnetic-core memories
Objective Methods for Registering Landmarks and Determining Cloud Motions from Satellite Data
Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs
Feedback Reconstruction and Implementations of Pseudorandom Number Generators from Composited De Bruijn Sequences
Test Algorithms for ECC-Based Memory Repair in Ultimate CMOS and Post-CMOS
HEAWS: An Accelerator for Homomorphic Encryption on the Amazon AWS FPGA
Scheduling Periodic Jobs That Allow Imprecise Results
A Faster Software Implementation of the Supersingular Isogeny Diffie-Hellman Key Exchange Protocol
A Nanosecond Monolithic TTL Gate
Average Values of Quantities Appearing in Boolean Function Minimization
Optimizing GPU-Based Graph Sampling and Random Walk for Efficiency and Scalability
A Karatsuba-Based Algorithm for Polynomial Multiplication in Chebyshev Form
Optimistic Make
Low-Complexity Bit-Parallel Square Root Computation over GF(2^{m}) for All Trinomials
B 74-34 Fortran and Algol: A Programmed Course for Students of Science and Technology
Algorithmic Aspects of MOS VLSI Switch-Level Simulation with Race Detection
BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms
An Efficient Directed Localization Recursion Protocol for Wireless Sensor Networks
Diversity Analysis in the Presence of Delay Faults Affecting Duplex Systems
Analysis and Implementation of Branch-and Bound Algorithms on a Hypercube Multicomputer
Cascaded Switching Networks of Two-Input Flexible Cells
A Synthesis of Combinational Logic with NAND or NOR Elements
An Analog Computer for the Solution of Tangents
Parallel Logic with Charge Storage Techniques
A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets
Generalized Earliest-First Fast Addition Algorithm
The Use of Software Simulators in the Testing and Debugging of Microprogram Logic
A time-sharing analog multiplier
Linear-Input Logic
Dynamic Problem-Oriented Redefinition of Computer Architecture via Microprogramming
Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator
A Novel Architecture for Galois Fields GF(2^m) Multipliers Based on Mastrovito Scheme
Discrete Tracks for Saturation Magnetic Recording
Performance-Power Tradeoff in Heterogeneous SaaS Clouds With Trustworthiness Guarantee
Valved Routing: Efficient Flow Control for Adaptive Nonminimal Routing in Interconnection Networks
Sequential Boolean Equations
Quicksort for Equal Keys
The KR-Benes Network: A Control-Optimal Rearrangeable Permutation Network
Structured Design of Substitution-Permutation Encryption Networks
Switch Complexity in Systems with Hybrid Redundancy
Algorithmic Synthesis of MVL Functions for CCD Implementation
Bit Storage via Electro-optical Feedback
On the Linearity of Sequential Machines
A Complexity-Effective Out-of-Order Retirement Microarchitecture
A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields
Minimum Search Tree Structures for Data Partitioned into Pages
Scheduling Parallel Processable Tasks for a Uniprocessor
Nonlinear Feedback Shift Registers
Mean Value Analysis by Chain of Product Form Queueing Networks
R70-32 Tessellation Automata
Addendum to "A New Hybrid Algorithm for Computing a Fast Discrete Fourier Transform"
Storage-Efficient, Deadlock-Free Packet Routing Algorithms for Torus Networks
A New Weighted Generalized Inverse Algorithm for Pattern Recognition
Unequal Error Protection Codes Derived from Double Error Correction Orthogonal Latin Square Codes
On the Connection Assignment Problem of Diagnosable Systems
Multiple Fault Detection in Arrays of Combinational Cells
Comments on "A Signed Bit-Sequential Multiplier"
Architectures for Exponentiation Over GF(2^n) Adopted for Smartcard Application
An Empirical Analysis of The Lilith Instruction Set
Fault Tolerance Capabilities in Multistage Network-Based Multicomputer Systems
Efficient Algorithms for Testing Semiconductor Random-Access Memories
A Note On High-Speed Generation of Maximal Length Sequences
A Partitioning Approach to the Design of Selection Networks
Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocessors
PLA Implementation of k -out-of- n Code TSC Checker
Analytic Multi-Core Processor Model for Fast Design-Space Exploration
OPSILA: A Vector and Parallel Processor
An Efficient Memory System for Image Processing
Energy-Efficient Cooperative Communications for Multimedia Applications in Multi-Channel Wireless Networks
A Note on Conditional-Sum Addition for Base - 2 Systems
Reducing Paging and Exit Overheads in Intel SGX for Oblivious Conjunctive Keyword Search
Testability Analysis and Scalable Test Generation for High-Speed Floating-Point Units
PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization
HotGraph: Efficient Asynchronous Processing for Real-World Graphs
The MAFT Architecture for Distributed Fault Tolerance
Optimizing Serverless Performance Through Game Theory and Efficient Resource Scheduling
On the Mean Accuracy of Hierarchical Classifiers
Time Optimal Linear Schedules for Algorithms with Uniform Dependencies
Self-Synchronizing Circuits and Nonfundamental Mode Operation
A Systematic Approach to the Design of Distributed Wearable Systems
DVFS-Based Quality Maximization for Adaptive Applications With Diminishing Return
Global Commutative and Associative Reduction Operations in Faulty SIMD Hypercubes
Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture
Interconnections for Parallel Memories to Unscramble p-Ordered Vectors
Distributed Instruction Set Computer Architecture
Energy Efficient Target-Oriented Scheduling in Directional Sensor Networks
A Parallel Jacobi Diagonalization Algorithm for a Loop Multiple Processor System
Design for Autonomous Test
DIVIDE: Efficient RowHammer Defense via In-DRAM Cache-Based Hot Data Isolation
A Hierarchical, Path-Oriented Approach to Fault Diagnosis in Modular Combinational Circuits
Tight Upper Bounds on the Minimum Precision Required of the Divisor and the Partial Remainder in High-Radix Division
A Graph Model for Pattern-Sensitive Faults in Random Access Memories
B715 APL Users' Glide
Algorithmic Phase Diagrams
A New Algorithm for Computing Correlations
Grid-Oriented Storage: A Single-Image, Cross-Domain, High-Bandwidth Architecture
Dynamic On-the-Fly Minimum Cost Benchmarking for Storing Generated Scientific Datasets in the Cloud
Optimized Modular Multiplication for Supersingular Isogeny Diffie-Hellman
Application of Boolean algebra to switching circuit design and to error detection
Fault Detection in Fanout-Free Combinational Networks
Analysis of Sequential Machines II
Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model
Counting Sequences
Predicting Transient Downtime in Virtual Server Systems: An Efficient Sample Path Randomization Approach
SurgeNAS: A Comprehensive Surgery on Hardware-Aware Differentiable Neural Architecture Search
Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2^m)
An Efficient Protocol for Call Setyp and Path Migration in IEEE 802.6 Based Personal Communication Networks
Magnetic-Field Design Considerations for a Plated-Wire Memory
Recovery and Diagnostics in the Central Control of the AXE Switching System
Conversion Algorithms and Implementations for Koblitz Curve Cryptography
Development Flow for On-Line Core Self-Test of Automotive Microcontrollers
Logic Properties of Unate Discrete and Switching Functions
Pseudonoise with Arbitrary Amplitude Distribution-Part II: Hardware Implementation
Two Designs of a Fault-Tolerant Clocking System
Recursive Moving Window DFT Algorithm
EC2P: Cost-Effective Cross-Chain Payments via Hubs Resisting the Abort Attack
Analysis of Logic Circuits with Faults Using Input Signal Probabilities
Scheduling Multipipeline and Multiprocessor Computers
Distributed Computing on Regular Networks with Anonymous Nodes
Amplifier and Driver Circuits for Thin Film Memories with 15 Nanoseconds Read Cycle Time
Dynamic Segment Trees for Ranges and Prefixes
Efficient Microarchitectural Vulnerabilities Prediction Using Boosted Regression Trees and Patient Rule Inductions
Two's Complement Multiplication in Binary Parallel Digital Computers
A Suggestion for a High-Speed Parallel Binary Divider
A Computational Algorithm for Solving a System of Coupled Algebraic Matrix Riccati Equations
On Supporting High-Quality 3D Geometry Multicasting over IEEE 802.11 Wireless Networks
Stateful DRF: Considering the Past in a Multi-Resource Allocation
Routing in a Three-Dimensional Chip
New Hardware Architectures for Montgomery Modular Multiplication Algorithm
Hazards, Critical Races, and Metastability
An Iterative-Improvement Approach to the Numerical Solution of Vector Toeplitz Systems
The H Diagram: A Graphical Approach to Logic Design
Error Free Computation: A Direct Method to Convert Finite-Segment p -Adic Numbers into Rational Numbers
Symbolic Model Checking for Incomplete Designs with Flexible Modeling of Unknowns
Division-Free Binary-to-Decimal Conversion
Some Additions to "Solution of Switching Equations Based on a Tabular Algebra"
A Note on Aliasing Probability for Multiple Input Signature Analyzer
Parameters for System Effectiveness Evaluation of Distributed Systems
Deductive Fault Simulation of Internal Faults of Inverter-Free Circuits and Programmable Logic Arrays
Decimal-to-Binary Conversion Using Octal Radix Arithmetic
The SOLOMON Computer
Efficient Deadline-Based QoS Algorithms for High-Performance Networks
An Optimal Algorithm for Permutation Admissibility to Multistage Interconnection Networks
R3TOS: A Novel Reliable Reconfigurable Real-Time Operating System for Highly Adaptive, Efficient, and Dependable Computing on FPGAs
Enabling Smart Transportation Systems: A Parallel Spatio-Temporal Database Approach
New Designs for Dense Processor Interconnection Networks
Adaptive Routing for N-Dimensional Twin Torus
A Minimization Technique for Tant Networks
Essential Hazard Correction Without the Use of Delay Elements
Computational Vector-Magnitude-Based Range Determination for Scientific Abstract Data Types
coreSNP: Parallel Processing of Microarray Data
Comments on "Parallelism and Representation Problems in Distributed Systems"
Inherently Lower-Power High-Performance Superscalar Architectures
Multi-threshold threshold elements
Reducing Iteration Time When Result Digit is Zero for Radix 2 SRT Division and Square Root with Redundant Remainders
Frames: A Simple Characterization of Permutations Realized by Frequently Used Networks
UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration
A Fast Pessimistic Diagnosis Algorithm for Hypercube-Like Networks under the Comparison Model
A Practical Algorithm for the Solution of Triangular Systems on a Parallel Processing System
Reliability Optimization on Multi-Core Systems with Multi-Tasking and Redundant Multi-Threading
Design and Analysis of a Highly User-Friendly, Secure, Privacy-Preserving, and Revocable Authentication Method
Erasure and Error Decoding for Semiconductor Memories
A Systematic Method for Division with High Average Bit Skipping
Swap-Time Considerations in Time-Shared Systems
Information Security Tools and Practices: What Works?
Lyra2: Efficient Password Hashing with High Security against Time-Memory Trade-Offs
Square Root Computation over Even Extension Fields
An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research
Accelerating Loss Recovery for Content Delivery Network
Multi-Inherited Search Tree for Dynamic IP Router-Tables
Optimizing I/O Operations in File Systems for Fast Storage Devices
An Optical-Digital Computer for Parallel Processing of Images
Testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs
A pattern recognition experiment with near-optimum results
Survivable Cloud Network Mapping for Disaster Recovery Support
The t/k-Diagnosability for Regular Networks
Reducing Computing Time for Synchronous Binary Division
Parallelism in Artificial Intelligence Problem Solving: A Case Study of Hearsay II
AVL Function Table for LeafHooks Insertion With Obfuscated Control Flow Integrity
Linear Algebra Approach to Neural Associative Memories and Noise Performance of Neural Classifiers
An Improved Cell Memory
An Efficient I/O-Redirection-Based Reconstruction Scheme for Erasure-Coded Storage Clusters
Model Poisoning Attack on Neural Network Without Reference Data
A Fast Karhunen-Loeve Transform for Digital Restoration of Images Degraded by White and Colored Noise
Subspace Snooping: Exploiting Temporal Sharing Stability for Snoop Reduction
Spectral Properties of Waveforms Generated by Smooth Sequences
Power Density-Aware Resource Management for Heterogeneous Tiled Multicores
Performability Evaluation of the SIFT Computer
Testing of Fault-Tolerant Hardware Through Partial Control of Inputs
Pike: Two-Phase BFT With Linearity and Flexible View Change
On TSC Checkers for m-out-n Codes
Feedback in Asynchronous Sequential Circuits
Minimal Input-Memory and Output-Memory Finite-State Machines
Cellular Automata-Based Signature analysis for Built-in Self-Test
An Efficient SuperGrid Protocol for High Availability and Load Balancing
A Pipeline Design of a Fast Prime Factor DFT on a Finite Field
A Procedure-Oriented Machine Language
VLSI Computational Architectures for the Arithmetic Cosine Transform
Optimal Robust Compression of Test Responses
Digital Information Processing for Machine-Tool Control
A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model
A New Subclass of Integer Linear Programming Problems and Its Applications
About Transfer Functions with Approximately Constant Time-Delay
An Algorithm for the Optimal Solution of Linear Inequalities and its Application to Pattern Recognition
Generating Reliable Code from Hybrid-Systems Models
Reconfiguration Procedures for a Polymorphic and Partitionable Multiprocessor
Weighted Realizations of Switching Functions
A New Residue Arithmetic Error Correction Scheme
Two-Stage Template Matching
Minimal Fault Tests for Redundant Combinational Networks
The Synthesis of Multivalued Cellular Cascades and the Decomposability of Group Functions
Task Allocation and Precedence Relations for Distributed Real-Time Systems
Fault Diagnosis and Repair of Cutpoint Cellular Arrays
Loop Properties and Controllability of Linear Congruential Sequences
Correction [to "On the realizability of special classes of autonomous sequential networks"]
ECO-CRYSTALS: Efficient Cryptography CRYSTALS on Standard RISC-V ISA
Some Conditional Cube Testers for Grain-128a of Reduced Rounds
A High-Speed Algorithm for the Computer Generation of Fourier Transforms
Fast Encoding Algorithms for Reed-Solomon Codes With Between Four and Seven Parity Symbols
Simulation of a Horizontal Bit-Sliced Processor Using the ISPS Architecture Simulation Facility
Constructing One-to-Many Disjoint Paths in Folded Hypercubes
Resource Scheduling for Local Computer Systems with a Multiaccess Network
Applying In-Transit Buffers to Boost the Performance of Networks with Source Routing
A Formal Definition of Data Flow Graph Models
Computationally Efficient and Numerically Stable Reliability Bounds for Repairable Fault-Tolerant Systems
Modeling Defect Spatial Distribution
Efficient Bit-Parallel GF(2^m) Multiplier for a Large Class of Irreducible Pentanomials
Guest Editors' Introduction - Special Issue on Computer Arithmetic
A Proposal for an Associative Memory Using Magnetic Films
An Optimal Channel Access Protocol with Multiple Reception Capacity
Corrections [to "An algorithm for linear inequalities and applications" and to "Logical design of analog-to-digital converters"]
NUDA: A Non-Uniform Debugging Architecture and Nonintrusive Race Detection for Many-Core Systems
Resource-Efficient Byzantine Fault Tolerance
An Orthogonal Multiprocessor for Parallel Scientific Computations
Systematic Procedures for Realizing Synchronous Sequential Machines Using Flip-Flop Memory: Part II
Comments on "An Approach to Highly Integrated Computer-Maintained Cellular Arrays"
Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs
High-Speed Multioperand Decimal Adders
Computer Analysis of Chromosome Patterns: Feature Encoding for Flexible Decision Making
System design of the SEAC and DYSEAC
Design Techniques of a Delay-Line Content-Addressed Memory
High Performance Dense Ring Generators
On the Construction of Sequential Machines from Regular Expressions
On the Detection of Terminal Stuck-Faults
Improved State Assignment Selection Tests
Fluid Kernels: Seamlessly Conquering the Embedded Computing Continuum
Low-Power High-Performance Reconfigurable Computing Cache Architectures
Convolutional Neural Networks With Discrete Cosine Transform Features
Image Segmentation by Pixel Classification in (Gray Level, Edge Value) Space
Improved Construction Techniques for (d, k) Graphs
Implications of Clock Distribution Faults and Issues with Screening Them during Manufacturing Testing
Bit-Width Optimization by Divide-and-Conquer for Fixed-Point Digital Signal Processing Systems
Measurement and Application of Fault Latency
Inference of Finite-State Probabilistic Grammars
Syndrome-Testable Design of Combinational Circuits
Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC
Competition-Style Sorting Networks (CSN): A Framework for Hardware-Based Sorting Operations
A Unified Approach to Combinational Hazards
Cyclic Staggered Scheme: A Loop Allocation Policy for DOACROSS Loops
Designing Sets of Fault-Detection Tests ror Combinational Logic Circuits
OmpSs@FPGA Framework for High Performance FPGA Computing
Disjoint Paths Construction and Fault-Tolerant Routing in BCube of Data Center Networks
A Reduction Technique for Prime Implicant Tables
Software-Based Self-Test of Set-Associative Cache Memories
Modular Decomposition of Combinational Multiple-Valued Circuits
Energy-Efficient Pattern Recognition Hardware With Elementary Cellular Automata
A Computing-in-Memory-Based One-Class Hyperdimensional Computing Model for Outlier Detection
All-Digital Control-Theoretic Scheme to Optimize Energy Budget and Allocation in Multi-Cores
A Computing Resource Management Framework for Software-Defined Radios
Static-dynamc design of flip-flop circuits
Dynamic Guardband Selection: Thermal-Aware Optimization for Unreliable Multi-Core Systems
Optimization of Message Encryption for Real-Time Applications in Embedded Systems
Filtering Memory References to Increase Energy Efficiency
SLIDE: An I/O Hardware Descriptive Language
Synthesis of Error-Tolerant Counters Using Minimum Distance Three State Assignments
ATP: A Microprotocol Approach to Autonomic Communication
A Multiple-Access Pipeline Architecture for Digital Signal Processing
A Unified Approach to a Class of Data Movements on an Array Processor
Complexity of Fault Diagnosis in Comparison Models
CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM Arrays
Dynamic Profile of Instruction Sequences for the IBM System/370