yusuke1997/dblp-id-title huggingface dataset:
Analysis of Convergence of a Frequency-Domain LMS Adaptive Filter Implemented as a Multi-Stage Adaptive Filter
Constant Number Serial Pipeline Multipliers
Distributed Arithmetic based Split-Radix FFT
Robust Voice Activity Detection Based on Concept of Modulation Transfer Function in Noisy Reverberant Environments
A Graphics Processing Unit Accelerated Genetic Algorithm for Affine Invariant Matching of Broken Contours
Pulse Pile-up Correction by Particle Swarm Optimization with Double-layer Parameter Identification Model in X-ray Spectroscopy
Fast MPEG-4 Motion Estimation: Processor Based and Flexible VLSI Implementations
Fast Implementation of Binary Morphological Operations on Hardware-Efficient Systolic Architectures
1080p 60 Hz Intra-Frame Video CODEC Chip Design and Its Implementation
QVGA/CIF Resolution MPEG-4 Video Codec Based on a Low-Power and General-Purpose DSP
Recent Advances in Design and Implementation of Signal Processing Systems
Multimedia Communications Using a Fast and Flexible DVC to H.264/AVC/SVC Transcoder
Non-negative Matrix Factorization with Orthogonality Constraints and its Application to Raman Spectroscopy
Interactive Content-aware Video Streaming System with Fine Granularity Scalability
Localized Video Coding
Cooperative Transmissions in 5G Large-scale Relay Systems: How to Keep a Balance Between Performance and Complexity?
Simultaneous Wireless Information and Power Transfer in Multi-antenna Systems
HGExplainer: Toward Interpretable Heterogeneous Graph Neural Networks via Meta-path Perturbation
Design and Implementation of Viterbi Decoder with FPGAs
CNN-Applications in Toll Driving
High Performance Real-Time Pedestrian Detection Using Light Weight Features and Fast Cascaded Kernel SVM Classification
A Systolic Architecture and Implementation of Feedback Network for Blind Source Separation
Prediction of Human Eye Fixation by a Single Filter
Determining the Number of Clusters in Clinical Response of TMS Treatment using Hyperdimensional Computing
Unequal Loss Protection for H.264/AVC Video Streaming Over Wireless Networks
Designs of Low Power Snoop for Multiprocessor System on Chip
Multistage Nonlinear Blind Interference Cancellation for DS-CDMA Systems
Variable Length Pattern Matching for Hardware Network Intrusion Detection System
Uniform Local Derivative Patterns and Their Application in Face Recognition
An FPGA-Based Accelerated Optimization Algorithm for Real-Time Applications
Artificially Intelligent Adaptive Search Fast Motion Estimation Algorithm for HD Video
An FPGA-based Integrated MapReduce Accelerator Platform
Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors
Architecture Considerations for Multi-Format Programmable Video Processors
Light-Weight Video Codec at Terminal for Video Coding in the Cloud
Computing with Front Propagation: Active Contour And Skeleton Models In Continuous-Time CNN
Guest Editorial - Special Issue on Signal Processing Circuits and Systems for Broadband Communications
2D grid architectures for the DFT and the 2D DFT
Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model
Design of an Application-specific VLIW Vector Processor for ORB Feature Extraction
ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA
Privacy-Preserving Data Communication Through Secure Multi-Party Computation in Healthcare Sensor Cloud
Double-Trapezium Cylinder Codebook Model Based on YUV Color Model for Foreground Detection with Shadow and Highlight Suppression
Introductory Note
MAET: A Generalizable Masked Autoencoding Framework for Anomaly Detection in Time-Series Data
A Hybrid CPU-GPU Multifrontal Optimizing Method in Sparse Cholesky Factorization
Elementary Function Computing Method for Floating-Point Unit
Top Down Implementation of Joint MODEM and CODEC Transceiver Design for DSRC Coded-FSK Systems Over High Mobility Fading Channels
Energy-Scalable Protocols for Battery-Operated MicroSensor Networks
Efficient realizations of squaring circuit and reciprocal used in adaptive sample rate notch filters
Feedforward architectures for parallel Viterbi decoding
Lightweight Graph Convolutional Hand Gesture Recognition Algorithm Based on Multistream Fusion
The 3-D Computer
Construction Methods of Knowledge Mapping for Full Service Power Data Semantic Search System
Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination
Multichannel Online Blind Speech Dereverberation with Marginalization of Static Observation Parameters in a Rao-Blackwellized Particle Filter
Real-Time 3D Depth Generation for Stereoscopic Video Applications with Thread-Level Superscalar-Pipeline Parallelization
Advances In Peer-To-Peer Content Search
Numerical Aspects of MIMO OFDM PHY Layer Applications on SDR Platforms
Blind Separation of Orthogonal Mixtures of Spatially-Sparse Sources with Unknown Sparsity Levels and with Temporal Blocks
A Novel Low-Cost Multi-Mode Reed Solomon Decoder Design Based on Peterson-Gorenstein-Zierler Algorithm
A video-rate JPEG chip set
An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems
Structured Output SVM for Remote Sensing Image Classification
Multi-Modal Speech Recognition Using Optical-Flow Analysis for Lip Images
A Big-data Inspired Precision Improvement Algorithm for Autonomous Navigation Based on Period Variable Stars
Systolic FFT Processors: A Personal Perspective
A Radar Signal Processing Case Study for Dataflow Programming of Manycores
Low Power Motion Estimation Design Based on Non-Uniform Pixel Truncation
Error detection in arrays via dependency graphs
FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers
CLA Formula and its Acceleration of Architecture Design for Clustered Look-Ahead Pipelined Recursive Digital Filter
Evolutionary Extreme Learning Machine and Its Application to Image Analysis
Special issue on VLSI neural networks
Special Issue on Signal Processing for Software Defined Radio Handsets
Fast Algorithm and Efficient Implementation of GMM-Based Pattern Classifiers
SROC: A Speaker Recognition with Data Decision Level Fusion Method in Cloud Environment
Real-Time Automated Video and Audio Capture with Multiple Cameras and Microphones
Efficient Sensing Topology Management for Spatial Monitoring with Sensor Networks
Design Space Exploration for an ASIP/Co-Processor Architecture used in GNSS Receivers
Decomposition Algorithms for Solving NP-hard Problems on a Quantum Annealer
Enhancement of JPEG-Compressed Images by Re-application of JPEG
Using Transposition to Efficiently Solve Constant Matrix-Vector Multiplication and Sum of Product Problems
Generic signal processor implementation with VHSIC
Power Efficient SDR Implementation of IEEE 802.11a/p Physical Layer
Improved Speech-Signal Based Frequency Warping Scale for Cepstral Feature in Robust Speaker Verification System
Heuristic Search Space Generation for Maximum Clique Problem Inspired in Biomolecular Filtering
Low Complexity Intercarrier Interference Cancellation for DVB-SH Receivers
Simultaneous EEG Source and Forward Model Reconstruction (SOFOMORE) Using a Hierarchical Bayesian Approach
Modeling and Analysis of FPGA Accelerators for Real-Time Streaming Video Processing in the Healthcare Domain
Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems
Fault diagnosis in reconfigurable VLSI and WSI processor arrays
Hybrid Domain Analysis of Noise-Aided Contrast Enhancement Using Stochastic Resonance
Special Issue on Wireless Powered Communications Networks
A Robust and Secure Media Signature Scheme for JPEG Images
The U.S. Digital Television Standard and its Impact on VLSI
VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization
Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput
A Low Power Approach to Floating Point Adder Design for DSP Applications
Analysis of BICM-ID Receivers Exploiting Transformations of Extrinsic Information
Constant Coefficient Multiplication Using Look-Up Tables
Range Analysis of Matrix Factorization Algorithms for an Overflow Free Fixed-point Design
Automatic Generation of Ortho-Photo Texture from Digital Elevation Model
Using semi-definite programming for multi-constrained H 2 controller design in active noise and vibration control
An Efficient Adaptive Channel Estimation Algorithm for MIMO OFDM Systems - Study of Doppler Spread Tolerance
Parallel Memory Architecture for Elliptic Curve Cryptography over GF(p) Aimed at Efficient FPGA Implementation
New LTE-A Low-Latency Detectors for Cognitive Radio on Low-Cost FPGA SoC
Design strategies for optimal hybrid final adders in a parallel multiplier
TDD LoRa and Delta Encoding in Low-Power Networks of Environmental Sensor Arrays for Temperature and Deformation Monitoring
A Configurable Architecture for the Wavelet Packet Transform
Audio Quality Requirements and Comparison of Multimodal vs. Unimodal Perception of Impairments for Long Duration Content
Nonlinear System Identification Using Varying Exponential Even Mirror Fourier Nonlinear Filters
Optimizing Data Placement of Loops for Energy Minimization with Multiple Types of Memories
Closed-loop Feedback Network with Cross Back-Projection for Lightweight Image Super-Resolution
From Low-Level Features to Semantic Classes: Spatial and Temporal Descriptors for Video Indexing
Impact of Approximation Error on the Decisions of LDPC Decoding
Field Trial of Licensed Shared Access with Enhanced Spectrum Controller Power Control Algorithms and LTE Enablers
Online SVR Training by Solving the Primal Optimization Problem
Computationally Efficient Exact Calculation of Kernel Density Derivatives
The Story of Unified Cordic
POLYBiNN: Binary Inference Engine for Neural Networks using Decision Trees
A Big Data Privacy Respecting Dissemination Method for Social Network
Deep Unfolded Extended Conjugate Gradient Method for Massive MIMO Processing with Application to Reciprocity Calibration
Online Acoustic System Identification Exploiting Kalman Filtering and an Adaptive Impulse Response Subspace Model
Low-Latency Software Polar Decoders
Adaptive Interference Suppression for the Downlink of a Direct Sequence CDMA System with Long Spreading Sequences
A Statistic and Analysis of Access Pattern for Online VoD Multimedia
Digital Design of Discrete Exponential Bidirectional Associative Memory
Evaluation of Fast Rotation Methods
Entropy Power Inequality for Learning Optimal Combination of Kernel Functions
Performance Modeling of System Architectures
IFODHD: Improved Feature Selection Based Outlier Detection using Hyperdimensional Computing
A Custom Instruction Approach for Hardware and Software Implementations of Finite Field Arithmetic over F 2 163 using Gaussian Normal Bases
Determining the Order of Processor Transactions in Statically Scheduled Multiprocessors
DressBoard: An Embedded Virtual Try-On System for Ties and Bowties
Low-Power Application-Specific Processor for FFT Computations
Low Duty Cycle, Energy-Efficient and Mobility-Based Boarder Node - MAC Hybrid Protocol for Wireless Sensor Networks
Instruction Set Extensions for Matrix Decompositions on Software Defined Radio Architectures
Design of a processing board for a programmable multi-VSP system
Guest Editorial: Special Section on the Design and Implementation of Signal Processing Systems
ASIP Approach for Implementation of H.264/AVC
Master Interface for On-chip Hardware Accelerator Burst Communications
Machinery Fault Diagnosis Based on Deep Learning for Time Series Analysis and Knowledge Graphs
A Fast H.264 Intra Frame Encoder with Serialized Execution of 4 × 4 and 16 × 16 Predictions and Early Termination
New Cost-Effective Simplified Euclid's Algorithm for Reed-Solomon Decoders
Reconfigurable Blocks Based on Balanced Ternary
Real-time and Resource-efficient Embedded Computer Vision Via Optimizing Lightweight CNNs for FPGA Acceleration
Secure Video Streaming Using Dedicated Hardware
Effect of Number of Coupled Structures on the Segmentation of Brain Structures
A mixed-signal VLSI competitive neuroprocessor for video motion detection
An Improved Floating-to-Fixed-Point Conversion Scheme for DCT Quantization Algorithm
Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems
Cloud Computation Processing for Oilfield Block Data and Chain Drive Pumping Unit Polished Rod Motion Model
Conventional and on-line arithmetic designs for high-speed recursive digital filters
A design synthesis system for recursive DSP algorithms represented by fully specified flow graphs
FPGA-Based Real-Time Implementation of Detection Algorithm for Automatic Traffic Surveillance Sensor Network
Language-Dependent Contribution Measuring and Weighting for Combining Likelihood Scores in Language Identification Systems
Rotation Invariance in 2D-FRFT with Application to Digital Image Watermarking
Assessment of Endothelial Function Using Arterial Pressure Signals
Implementation of the Longstaff and Schwartz American Option Pricing Model on FPGA
Automatic Facial Expression Exaggeration System with Parallelized Implementation on a Multi-Core Embedded Computing Platform
Guest Editorial: Special Issue on Multi-Core Enabled Multimedia Applications & Architectures
A High-Throughput JPEG XR Encoder
Memory Aware Design Optimisation for High-Level Synthesis
Memory Access Optimized Implementation of Cyclic and Quasi-Cyclic LDPC Codes on a GPGPU
The Birth of Cordic
Audio Coding for Representation in MIDI via Pitch Detection Using Harmonic Dictionaries
Generalized trace-back techniques for survivor memory management in the Viterbi algorithm
Parameterized Sets of Dataflow Modes And Their Application to Implementation of Cognitive Radio Systems
Adaptive Streaming of Layer-Encoded Multimedia Presentations
DDFSGEN
VLSI architectures for vector quantization
Failure-Aware Task Scheduling of Synchronous Data Flow Graphs Under Real-Time Constraints
3-D Heart Modeling and Motion Estimation Based on Continuous Distance Transform Neural Networks and Affine Transform
Narrow-band FIR filtering with FPGAs using sigma-delta modulation encoding
Generating Efficient FPGA-based CNN Accelerators from High-Level Descriptions
A New Overlap Save Algorithm for Fast Block Convolution and Its Implementation Using FFT
A Hardware/Software Prototype of EEG-based BCI System for Home Device Control
Cost Minimization with HPDFG and Data Mining for Heterogeneous DSP
GPU Acceleration of a Configurable N-Way MIMO Detector for Wireless Systems
Erratum to: Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications
FPGA Implementation of SDR Based CFO Estimation and Compensation Circuit for OFDM System
Model-Based Systems Engineering: Lessons Learned from the Joint Tactical Radio System
A Survey on Lifting-based Discrete Wavelet Transform Architectures
Mapping of Trellises Associated with General Encoders onto High-Performance VLSI Architectures
Belief Propagation Decoding of Polar Codes Using Intelligent Post-Processing
Guest Editorial Special Issue on Advances in Multimedia Computing, Communications and Applications
Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs
Towards Accelerated Genome Informatics on Parallel HPC Platforms: The ReneGENE-GI Perspective
Video Compression for Screen Recorded Sequences Following Eye Movements
2-D DWT System Architecture for Image Compression
Streaming Data Movement for Real-Time Image Analysis
Learning Compact DNN Models for Behavior Prediction from Neural Activity of Calcium Imaging
Multinomial Sampling of Latent Variables for Hierarchical Change-Point Detection
BrainSort: a Machine Learning Toolkit for Brain Connectome Data Analysis and Visualization
Guest Editorial: MLSP 2020 Special Issue
Analysis and Design of Low-Cost Bit-Serial Architectures for Motion Estimation in H.264/AVC
Downlink Specific Linear Equalization for Frequency Selective CDMA Cellular Systems
Thermal Modeling of Hybrid Storage Clusters
Monitoring of Ball Bearing Based on Improved Real-Time OPTICS Clustering
Learning capacitive weights in analog CMOS neural networks
RASSP Methodology Evaluation and Lessons Learned Developing IRST Signal Processor
Power dissipation of VLSI array processing systems
Accelerating Multiresolution Gabor Feature Extraction for Real Time Vision Applications
Polynomial Multiplication Architecture with Integrated Modular Reduction for R-LWE Cryptosystems
Interference avoidance and cancellation in automotive OFDM radar networks
A gate-level reconfigurable Monte carlo processor
Real-Time Adaptive Multiple Transforms for the Next Generation Software Video Decoders
Evaluation of an Adaptive Resource Allocation for LoRaWAN
Robust Numerical Features for Description and Classification of Subcellular Location Patterns in Fluorescence Microscope Images
Stealthy Energy Consumption-oriented Attacks on Training Stage in Deep Learning
Real-Time Adaptive Background Modeling for Multicore Embedded Systems
A Simplified Active Contour Model with Free Endpoints
A method for calculation of the square root using combinatorial logic
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators
Sequential Data Fusion via Vector Spaces: Fusion of Heterogeneous Data in the Complex Domain
An optimization technique for lowering the iteration bound of DSP programs
Features Based Spatial and Temporal Blotch Detection for Archive Video Restoration
EOG Signal Processor: An SVM-based Multiclass Classifier to Detect Eye Movements
Low Power Semi-systolic Architectures for Polynomial-Basis Multiplication over GF(2 m ) Using Progressive Multiplier Reduction
A Low-Latency Multi-layer Prefix Grouping Technique for Parallel Huffman Decoding of Multimedia Standards
Editorial Note: Machine Learning for Signal Processing
Blind Source Separation and Equiprobabilistic Topographic Maps
Instruction level power analysis and optimization of software
Pipelined systolic architectures for DLMS adaptive filtering
Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories
Optimized Hardware Implementation for Forward Quantization of H.264/AVC
Fast Multibit Decision Polar Decoder for Successive-Cancellation List Decoding
Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration
Efficient Computation Techniques and Hardware Architectures for Unitary Transformations in Support of Quantum Algorithm Emulation
Image Processing Units on Ultra-low-cost Embedded Hardware: Algorithmic Optimizations for Real-time Performance
Generalized Restart Mechanism for Successive-Cancellation Flip Decoding of Polar Codes
Programmable CMOS CNN Cell Based on Floating-gate Inverter Unit
A Hybrid Message-level Modeling Approach for Fast Yet Accurate Simulation of Multiprocessor Shared Bus Effects on Data Flow Applications Execution
Application of Reconfigurable CORDIC Architectures
A New Class of Efficient Block-Iterative Interference Cancellation Techniques for Digital Communication Receivers
Reconfigurable Morphological Image Processing Accelerator for Video Object Segmentation
Accelerating OpenVX through Halide and MLIR
A Compiler-Friendly RISC-Based Digital Signal Processor Synthesis and Performance Evaluation
Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture
A High-level Microprocessor Power Modeling Technique Based on Event Signatures
A Novel Encoding Method for P-frames
Maximizing Limited Resources: a Limit-Based Study and Taxonomy of Out-of-Order Commit
An Efficient Hillclimbing-based Watershed Algorithm and its Prototype Hardware Architecture
Systematic generation of linear allocation functions in systolic array design
Improving Mandarin Tone Recognition Based on DNN by Combining Acoustic and Articulatory Features Using Extended Recognition Networks
Enhanced Configurable DCT Cordic Loeffler Architectures for Optimal Power-PSNR Trade-Off
MPEG-4 Video and Image Coding on Digital Signal Processors
Fast RNS Implementation of Elliptic Curve Point Multiplication on FPGAs
A New Low Latency Parallel FIR Filter Scheme
Quadtree Optimization for Image and Video Coding
Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead
FPGA-Based Vision Processing System for Automatic Online Player Tracking in Indoor Sports
Processor Enhancements for Media Streaming Applications
Adaptive Crowd Segmentation Based on Coherent Motion Detection
DBiT: A High-Precision Binarized ViT FPGA Accelerator
A Method for Windows Malware Detection Based on Deep Learning
Subspace tracking with adaptive threshold rank estimation
Reconfigurable Carry Look-Ahead Adder Trading Accuracy for Energy Efficiency
Traceback-Based Optimizations for Maximum a Posteriori Decoding Algorithms
G729 Voice Decoder Design
Fault Detection and Automated Fault Diagnosis for Embedded Integrated Electrical Passives
Motion Estimation Based on Spline Interpolation in H.264/AVC Video Coder for Videoconferencing Application: Performance Versus Computation Load
Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques - Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies
A Hybrid Task Graph Scheduler for High Performance Image Processing Workflows
Clock Skew Optimization for Peak Current Reduction
Bounds on FSM Switching Activity
Saliency Combined Particle Filtering for Aircraft Tracking
Image Segmentation Using Excess Entropy
The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer
A Low Complexity Reconfigurable Non-uniform Filter Bank for Channelization in Multi-standard Wireless Communication Receivers
The Role of Context in Cognitive Systems
Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks
A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters
Coarse-to-Fine Speech Emotion Recognition Based on Multi-Task Learning
Auxiliary Features from Laser-Doppler Vibrometer Sensor for Deep Neural Network Based Robust Speech Recognition
Efficient Berlekamp-Massey Algorithm and Architecture for Reed-Solomon Decoder
Advanced Low Power High Speed Nonlinear Signal Processing: An Analog VLSI Example
Spatially Enhanced Bags of Visual Words Representation to Improve Traffic Signs Recognition
Biometric-oriented Iris Identification Based on Mathematical Morphology
Recent Collaborative R&D in Medical Imaging in Asia
A Single Clocked Adiabatic Static Logic - A Proposal for Digital Low Power Applications
Segmented Successive Cancellation List Polar Decoding with Tailored CRC
Parallel Digital Predistortion Design on Mobile GPU and Embedded Multicore CPU for Mobile Transmitters
Knowledge Propagation in Collaborative Tagging for Image Retrieval
Comparing the Performance of NB-IoT, LTE Cat-M1, Sigfox, and LoRa for IoT End Devices Moving at High Speeds in the Air
A Fast Recursive Algorithm and Architecture for Pruned Bit-reversal Interleavers
RCSoS: An IEC 61508 Compatible Server Model for Reliable Communication
Practical Considerations for Full Duplex Enabled 5G Integrated Access and Backhaul
Exploiting Quadtree Template Matching for Enhanced Hybrid Video Coding
A Novel Method for Partially Adaptive Broadband Beamforming
Platform-Based MPEG-4 SOC Design for Video Communications
Function-Level Processor (FLP): A Novel Processor Class for Efficient Processing of Streaming Applications
A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic
Power-Aware Design of An 8-Bit Pipelining ANT-Based CLA Using Data Transition Detection
Edge Curve Scaling and Smoothing with Cubic Spline Interpolation for Image Up-Scaling
An Efficient Human Identification Through Iris Recognition System
Internet Distance Learning: The Problems, the Pitfalls, and the Future
Low Power Blockchain in Industry 4.0 Case Study: Water Management in Tunisia
Dynamic Resource Allocation in Non-orthogonal Multiple Access Using Weighted Maximin Fairness Strategy for a UAV Network
Auto-regularized Gradients of Adaptive Interpolation for MRI Super-Resolution
A Special Purpose Array Processor Architecture for the Molecular Dynamics Simulation of Point-Mutated Proteins