yusuke1997/dblp-id-title huggingface dataset:
Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip
FPGA Implementation for GMM-Based Speaker Identification
Burst-Mode Asynchronous Controllers on FPGA
An Adaptive Message Passing MPSoC Framework
A Hardware-Accelerated ECDLP with High-Performance Modular Multiplication
Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT
Hardware Middleware for Person Tracking on Embedded Distributed Smart Cameras
Modules for Pipelined Mixed Radix FFT Processors
Multi-Softcore Architecture on FPGA
Partial Reconfigurable FIR Filtering System Using Distributed Arithmetic
Experiencing a Problem-Based Learning Approach for Teaching Reconfigurable Architecture Design
Analysis and Design of a Context Adaptable SAD/MSE Architecture
Answer Set versus Integer Linear Programming for Automatic Synthesis of Multiprocessor Systems from Real-Time Parallel Programs
Comment on "High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs"
Using Statistical Assertions to Guide Self-Adaptive Systems
A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance
A Vector-Like Reconfigurable Floating-Point Unit for the Logarithm
FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture
A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems
Enabling Self-Organization in Embedded Systems with Reconfigurable Hardware
Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding
A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation
An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-Dimensional Reconfigurable Architectures
Mechanism of Resource Virtualization in RCS for Multitask Stream Applications
Floorplacement for Partial Reconfigurable FPGA-Based Systems
Automatic Pipelining and Vectorization of Scientific Code for FPGAs
Design Patterns for Self-Adaptive RTE Systems Specification
Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions
An Interface for a Decentralized 2D Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing
Cellular Automata-Based Parallel Random Number Generators Using FPGAs
Dynamic Circuit Specialisation for Key-Based Encryption Algorithms and DNA Alignment
FPGA Interconnect Topologies Exploration
Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders
Robotic Mapping and Localization with Real-Time Dense Stereo on Reconfigurable Hardware
An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing
Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs
AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation
Traversal Caches: A Framework for FPGA Acceleration of Pointer Data Structures
FPGA Implementation of A∗ Algorithm for Real-Time Path Planning
Modeling and Implementation of a Power Estimation Methodology for SystemC
An Automatic Design Flow for Data Parallel and Pipelined Signal Processing Applications on Embedded Multiprocessor with NoC: Application to Cryptography
SIFO: Secure Computational Infrastructure Using FPGA Overlays
A Convolve-And-MErge Approach for Exact Computations on High-Performance Reconfigurable Computers
OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions
Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography
Multiobjective Optimization for Reconfigurable Implementation of Medical Image Registration
QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection
Reaction Diffusion and Chemotaxis for Decentralized Gathering on FPGAs
Dynamic Hardware Development
Real-Time Control System for Improved Precision and Throughput in an Ultrafast Carbon Fiber Placement Robot Using a SoC FPGA Extended Processing Platform
Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs
An FPGA-Based Omnidirectional Vision Sensor for Motion Detection on Mobile Robots
Placing Multimode Streaming Applications on Dynamically Partially Reconfigurable Architectures
HwPMI: An Extensible Performance Monitoring Infrastructure for Improving Hardware Design and Productivity on FPGAs
High-Speed FPGA 10's Complement Adders-Subtractors
Selected Papers from ReconFig 2009 International Conference on Reconfigurable Computing and FPGAs (ReconFig 2009)
Operating System for Runtime Reconfigurable Multiprocessor Systems
An ESL Approach for Energy Consumption Analysis of Cache Memories in SoC Platforms
Corrigendum to "An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization"
A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture
A Service-Oriented Component-Based Framework for Dynamic Reconfiguration Modeling Targeting SystemC/TLM
vMAGIC - Automatic Code Generation for VHDL
A Top-Down Optimization Methodology for Mutually Exclusive Applications
Current Trends on Reconfigurable Computing
Operating System Concepts for Reconfigurable Computing: Review and Survey
FPGA Implementation of a Pipelined Gaussian Calculation for HMM-Based Large Vocabulary Speech Recognition
Distance-Ranked Fault Identification of Reconfigurable Hardware Bitstreams via Functional Input
A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation
Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
Space-Based FPGA Radio Receiver Design, Debug, and Development of a Radiation-Tolerant Computing System
HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture
Sustainable Modular Adaptive Redundancy Technique Emphasizing Partial Reconfiguration for Reduced Power Consumption
On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors
A Genetic Programming Approach to Reconfigure a Morphological Image Processing Architecture
Low-Cost Fault Tolerant Methodology for Real Time MPSoC Based Embedded System
Self-Adaptive On-Chip System Based on Cross-Layer Adaptation Approach
High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures
TreeBASIS Feature Descriptor and Its Hardware Implementation
A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback
Dynamic Reliability Management for FPGA-Based Systems
A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime
Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique
FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method
Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration
An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture
On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays
Design of a Mathematical Unit in FPGA for the Implementation of the Control of a Magnetic Levitation System
New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA
Montgomery Modular Multiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation
A Method for Run-Time Prediction of On-Chip Thermal Conditions in Dynamically Reconfigurable SOPCs
An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories Only: Design and Benchmarking with Intel Movidius Neural Compute Stick
A Security Scheme for Dependable Key Insertion in Mobile Embedded Devices
An Improved Diffusion Based Placement Algorithm for Reducing Interconnect Demand in Congested Regions of FPGAs
Representing Tactics for Fault Recovery: A Reconfigurable, Modular, and Hierarchical Approach
A Heuristic Scheduler for Port-Constrained Floating-Point Pipelines
Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices
On Self-Timed Circuits in Real-Time Systems
Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates
Area Optimisation for Field-Programmable Gate Arrays in SystemC Hardware Compilation
Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues
Dynamic Application Model for Scheduling with Uncertainty on Reconfigurable Architectures
Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis
Selected Papers from ReCoSoC 2008
Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units
Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs
FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis
Combining SDM-Based Circuit Switching with Packet Switching in a Router for On-Chip Networks
Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection
Speeding Up FPGA Placement via Partitioning and Multithreading
A Memory Hierarchy Model Based on Data Reuse for Full-Search Motion Estimation on High-Definition Digital Videos
Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems
A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks
Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems
Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based System Designs Accelerated by FPGA Logic
High level modeling of Dynamic Reconfigurable FPGAs
Reconfigurable Hardware Implementation of a Multivariate Polynomial Interpolation Algorithm
A High-Throughput Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Targeting High-Definition Videos
Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification
Reconfigurable Network Stream Processing on Virtualized FPGA Resources
RapidRadio: A Domain-Specific Productivity Enhancing Framework
Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010)
NCOR: An FPGA-Friendly Nonblocking Data Cache for Soft Processors with Runahead Execution
A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications
Pipeline FFT Architectures Optimized for FPGAs
Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels
Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics
Toward the Implementation of an ASIC-Like System on FPGA for Real-Time Video Processing with Power Reduction
A Hardware Efficient Random Number Generator for Nonuniform Distributions with Arbitrary Precision
OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms
Selected Papers from ReConFig 2008
True-Randomness and Pseudo-Randomness in Ring Oscillator-Based True Random Number Generators
Optimizing Investment Strategies with the Reconfigurable Hardware Platform RIVYERA
Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency
Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain
A Protein Sequence Analysis Hardware Accelerator Based on Divergences
Implementing and Evaluating an Heterogeneous, Scalable, Tridiagonal Linear System Solver with OpenCL to Target FPGAs, GPUs, and CPUs
Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices
Corrigendum to "Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm"
Prime Field ECDSA Signature Processing for Reconfigurable Embedded Systems
Optimization of Lookup Schemes for Flow-Based Packet Classification on FPGAs
Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation
From FPGA to Support Cloud to Cloud of FPGA: State of the Art
Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010)
A Streaming High-Throughput Linear Sorter System with Contention Buffering
Reduced-Precision Redundancy on FPGAs
A Programmable Look-Up Table-Based Interpolator with Nonuniform Sampling Scheme
An Asynchronous FPGA Block with Its Tech-Mapping Algorithm Dedicated to Security Applications
Neuromorphic Configurable Architecture for Robust Motion Estimation
High Performance Biological Pairwise Sequence Alignment: FPGA versus GPU versus Cell BE versus GPP
Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application
FPGAs for Domain Experts
Dynamic Task Distribution Model for On-Chip Reconfigurable High Speed Computing System
Challenges in Clock Synchronization for On-Site Coding Digital Beamformer
Novel Dynamic Partial Reconfiguration Implementation of K-Means Clustering on FPGAs: Comparative Results with GPPs and GPUs
An Efficient FPGA Implementation of Optimized Anisotropic Diffusion Filtering of Images
On a Real-Time Blind Signal Separation Noise Reduction System
Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs
How to Efficiently Reconfigure Tunable Lookup Tables for Dynamic Circuit Specialization
FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach
Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis Tools
Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA
RP-Ring: A Heterogeneous Multi-FPGA Accelerator
DMPDS: A Fast Motion Estimation Algorithm Targeting High Resolution Videos and Its FPGA Implementation
Software-Defined Radio FPGA Cores: Building towards a Domain-Specific Language
A Fault Injection Analysis of Linux Operating on an FPGA-Embedded Platform
An Optimization-Based Reconfigurable Design for a 6-Bit 11-MHz Parallel Pipeline ADC with Double-Sampling S&H
A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips
On the Use of Magnetic RAMs in Field-Programmable Gate Arrays
Runtime Scheduling, Allocation, and Execution of Real-Time Hardware Tasks onto Xilinx FPGAs Subject to Fault Occurrence
Providing Memory Management Abstraction for Self-Reconfigurable Video Processing Platforms
Hardware Obfuscation Based Watermarking Technique for IPR Ownership Identification
High-Performance Reconfigurable Computing
High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis
ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures
Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology
Selected Papers from SPL 2009: Programmable Logic and Applications
Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment
Algorithm and Architecture Optimization for 2D Discrete Fourier Transforms with Simultaneous Edge Artifact Removal
Occam-pi for Programming of Massively Parallel Reconfigurable Architectures
Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform
A Hardware Filesystem Implementation with Multidisk Support
The Potential for a GPU-Like Overlay Architecture for FPGAs
Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise - Designing a Computer Architecture via HLS)
Implementation of Ring-Oscillators-Based Physical Unclonable Functions with Independent Bits in the Response
Rainbow: An Operating System for Software-Hardware Multitasking on Dynamically Partially Reconfigurable FPGAs
A Scalable Unsegmented Multiport Memory for FPGA-Based Systems
Parameterized Hardware Design on Reconfigurable Computers: An Image Processing Case Study
Practical Education Fostered by Research Projects in an Embedded Systems Course
Corrigendum to "PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability"
Performance Analysis Techniques for Multi-Soft-Core and Many-Soft-Core Systems
Evaluation of Runtime Task Mapping Using the rSesame Framework
High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs
Low-Complexity Online Synthesis for AMIDAR Processors
Design of a Reconfigurable Pulsed Quad-Cell for Cellular-Automata-Based Conformal Computing
Selected Papers from the Southern Programmable Logic Conference (SPL2010)
3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans
Concurrent Calculations on Reconfigurable Logic Devices Applied to the Analysis of Video Images
Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm
AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC
Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs
Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms
A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip
Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures
A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance
A Reconfigurable System Approach to the Direct Kinematics of a 5 D.o.f Robotic Manipulator
A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips
PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability
A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA
A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors
Multiloop Parallelisation Using Unrolling and Fission
Two-phase real-time rendering method for realistic water refraction
Effects of immersive virtual reality-based exercise on quality of life, stress, anxiety, depression, and handgrip strength in fibromyalgia: A pilot study
Three-dimensional virtual-real mapping of aircraft automatic spray operation and online simulation monitoring
Motivation Effect of Animated Pedagogical Agent's Personality and Feedback Strategy Types on Learning in Virtual Training Environment
Novel learning framework for optimal multi-object video trajectory tracking
STDNet: Improved lip reading via short-term temporal dependency modeling
Deep inside molecules - digital twins at the nanoscale
VEGO: A novel design towards customizable and adjustable head-mounted display for VR
Laser Scanned Real Environment for Intelligent Virtualization of Crane Lifting
Audio2AB: Audio-driven collaborative generation of virtual character animation
MKEAH： Multimodal knowledge extraction and accumulation based on hyperplane embedding for knowledge-based visual question answering
Exploring the effect of fingertip aero-haptic feedforward cues in directing eyes-free target acquisition in VR
Gesture interaction in virtual reality
3D scene graph prediction from point clouds
View Interpolation Networks for Reproducing Material Appearance of Specular Objects
A haptic feedback glove for virtual piano interaction
Building the Metaverse by Digital Twins at All Scales, State, Relation
RealFuVSR: Feature Enhanced Real-World Video Super-Resolution
Effective data transmission through energy-efficient clustering and Fuzzy-Based IDS routing approach in WSNs
Opening Design using Bayesian Optimization
Navigation in virtual and real environment using brain computer interface: a progress report
A smart assistance system for cable assembly by combining wearable augmented reality with portable visual inspection
Object registration using an RGB-D camera for complex product augmented assembly guidance
End-to-End Spatial Transform Face Detection and Recognition
Segmentation of CAD models using hybrid representation
Virtual Reality for Immersive Multi-User Firefighter Training Scenarios
Study on the adaptability of augmented reality smartglasses for astigmatism based on holographic waveguide grating
A review of edge-based 3D tracking of rigid objects
Stains on imperfect textile
Deconfounded fashion image captioning with transformer and multimodal retrieval
Face animation based on multiple sources and perspective alignment
InputJump: Augmented reality-facilitated cross-device input fusion based on spatial and semantic information
Prospects and challenges in augmented reality displays
Data-based real-time petrochemical gas diffusion simulation approach on virtual reality
Research on AGV task path planning based on improved A* algorithm
NPIPVis: A Visualization System Involving NBA Visual Analysis and Integrated Learning Model Prediction
A survey on image and video stitching
Validity of non-local mean filter and novel denoising method
Development and application of digital assistive teaching system for anatomy
AR-Assisted Children Book For Smart Teaching And Learning Of Turkish Alphabets
PartLabeling: A Label Management Framework in 3D Space
Self-attention transfer networks for speech emotion recognition
Multi-scale discrepancy adversarial network for crosscorpus speech emotion recognition
Data-driven simulation in fluids animation: A survey
Haptic feedback for virtual reality
Multidimensional image morphing-fast image-based rendering of open 3D and VR environments
Music-stylized hierarchical dance synthesis with user control
Designing social immersive virtual environments for the Metaverse: The case study of MetaLibrary
Virtual simulation experiment of the design and manufacture of a beer bottle-defect detection system
Adequate alignment and interaction for cross-modal retrieval
Advanced driver assistance system (ADAS) and machine learning (ML): The dynamic duo revolutionizing the automotive industry
S2ANet: Combining local spectral and spatial point grouping for point cloud processing
Optimal load frequency control system for two-area connected via AC/DC link using cuckoo search algorithm
Effect of prior gaming experience on cybersickness symptoms in a virtual reality environment
Influence of multi-modality on moving target selection in virtual reality
Virtual & augmented reality for biological microscope in experiment education
On the launch of Virtual Reality & Intelligent Hardware
FDCPNet:feature discrimination and context propagation network for 3D shape representation
Emotional dialog generation via multiple classifiers based on a generative adversarial network
Effects of Virtual-real fusion on immersion, presence, and learning performance in laboratory education
Dynamic load balancing for real-time multiview path tracing on multi-GPU architectures
Automatic detection of breast lesions in automated 3D breast ultrasound with cross-organ transfer learning
Interactive Hepatic Parenchymal Transection Simulation with Haptic Feedback
Design of a new kind of chemical experiment container with virtual reality fusion
Intelligent 3D garment system of the human body based on deep spiking neural network
A review of cable layout design and assembly simulation in virtual environments
Collaborative visual SLAM for multiple agents: A brief survey
Integrating models of real aboveground scene and underground geological structures at an open pit mine
Effect of haptic feedback on a virtual lab about friction
A survey of real-time rendering on Web3D application
Eye-around vibration haptics on VR immersion improvement
Efficient and lightweight 3D building reconstruction from drone imagery using sparse line and point clouds
Unrolling Rain-guided Detail Recovery Network for Single Image Deraining
COVAD: Content-Oriented Video Anomaly Detection using a Self-Attention based Deep Learning Model
Cumulus cloud modeling from images based on VAE-GAN
MatStick: Changing the material sensation of objects upon impact
Gamification and Virtual Reality for Digital Twins Learning and Training: Architecture and Challenges