yusuke1997/dblp-id-title huggingface dataset:
Power Management IC With a Three-Phase Cold Self-Start for Thermoelectric Generators
MDS-DOA: Fusing Model-Based and Data-Driven Approaches for Modular, Distributed, and Scalable Direction-of-Arrival Estimation
Memristor-Emulator-Based Crossbar Array for Object Detection and Recognition
Active Disturbance Rejection Formation Tracking Control for Uncertain Nonlinear Multi-Agent Systems With Switching Topology via Dynamic Event-Triggered Extended State Observer
Privacy-Preserved Distributed Optimization for Multi-Agent Systems With Antagonistic Interactions
A Time-Interleaved SAR ADC With Signal-Independent Background Timing Calibration
Stability-Oriented Minimum Switching/Sampling Frequency for Cyber-Physical Systems: Grid-Connected Inverters Under Weak Grid
A 7-bit 3.8-GS/s 2-Way Time-Interleaved 4-bit/Cycle SAR ADC 16× Time-Domain Interpolation in 28-nm CMOS
SoC Reconfigurable Architecture for Implementing Software Trained Recurrent Neural Networks on FPGA
A New Active Device Namely S-CCI and Its Applications: Simulated Floating Inductor and Quadrature Oscillators
Universal Dynamics Analysis of Locally-Active Memristors and its Applications
Protecting the Intellectual Property of Binary Deep Neural Networks With Efficient Spintronic-Based Hardware Obfuscation
A 40 nm Cryo-CMOS Homodyne-Demodulation Readout SoC for Superconducting Qubits
Load-Independent Class-E Frequency Multipliers
Generalized Discrete-Time Variable Gain ADRC for Nonlinear Systems and Its Application to Parallel Teleoperated Manipulators
Memristor-Based Neural Network Circuit of Operant Conditioning With Bridging and Conditional Reinforcement
An MTJ-Based Asynchronous System With Extremely Fine-Grained Voltage Scaling
Novel Radiation Hardened Pre-Discharge Sense Amplifier for Double Data Rate Magnetic Random Access Memory
Sensitivity Analysis of Free-Standing Columnar Magnetic Field Energy Harvester for Powering Wireless Monitoring Sensors
Compact Single-Ended Transceivers Demonstrating Flexible Generation of 1/N-Rate Receiver Front-Ends for Short-Reach Links
A Quasi-Steady-State Observer-Based Control Strategy for Grid-Friendly Repetitive Bipolar Pulse Generator
A 0.11-0.38 pJ/cycle Differential Ring Oscillator in 65 nm CMOS for Robust Neurocomputing
Optimizing Constrained Guidance Policy With Minimum Overload Regularization
A 44-μW, 91.3-dB SNDR DT Δ Σ Modulator With Second-Order Noise-Shaping SAR Quantizer
An 1 V Supply, 740 nW, 8.7 ppm/°C Bandgap Voltage Reference With Segmented Curvature Compensation
A 16-20 GHz Mixer First Receiver Architecture With Active Inductor-Based Low-Pass Elliptic Filter With High OOB-IIP3 in 180 nm CMOS
TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks
Area Efficient Asynchronous SFQ Pulse Round-Robin Distribution Network
Analysis and Design of Integrated Quadrature Balanced N-Path Transceivers for Frequency Division Duplex Systems
A 32-40 GHz 7-bit Bi-Directional Phase Shifter With 0.36 dB/1.6° RMS Magnitude/Phase Errors for Phased Array Systems
0.35-V SR-Enhanced Bulk-Driven OTA for Loads up to 10 nF
Secure Recursive Estimator-Based Command Filtered Event-Triggered Control for Islanded AC Microgrids Under Deception Attacks
WAGONN: Weight Bit Agglomeration in Crossbar Arrays for Reduced Impact of Interconnect Resistance on DNN Inference Accuracy
Almost Sure Finite-Time Control for Markovian Jump Systems Under Asynchronous Switching With Applications: A Sliding Mode Approach
An Automated Fault Attack Framework for Block Ciphers Through Property Mining and Verification
Secure Distributed State Estimation for Microgrids With Eavesdroppers Based on Variable Decomposition
Computing the Pursuing Control in Proximate Orbital Pursuit-Evasion Game by Polynomial Approximation
Linear Periodically Time-Variant Digital PLL Phase Noise Modeling Using Conversion Matrices and Uncorrelated Upsampling
Spurs in Fractional-N Frequency Synthesizers Resulting From Resolution Mismatch Between the Divider Controller and the DTC: Manifestations, Analysis, and Mitigation
0.4-V nW-Power High-Gain Bulk-Driven Two-Stage OTA With Self-Cascode Composite Transistors and Intrinsic Current-Buffer Miller Compensation
Small Signal Synchronizing Stability of PLL-Based Wind Turbine Converter During Current Injection to Low Voltage Grid Fault
Design and Implementation of Decision-Tree (DT) Online Training Hardware Using Divider-Free GI Calculation and Speeding-Up Double-Root Classifier
Low-Complexity High-Precision Method and Architecture for Computing the Logarithm of Complex Numbers
Reactive Power Evaluation for Non-Sinusoidal Single Phase Systems
Event-Triggered Control for a Second Order ODE-Heat System Coupling at Intermediate Point
Model-Free Game-Based Dynamic Event-Driven Safety-Critical Control of Unknown Nonaffine Systems
A 16-Bit Calibration-Free SAR ADC With Binary-Window and Capacitor-Swapping DAC Switching Schemes
High Frequency Response of Non-Volatile Memristors
Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic
Observer-Based Event-Triggered Formation Control of Multi-Agent Systems With Switching Directed Topologies
An Energy-Efficient Approximate Divider Based on Logarithmic Conversion and Piecewise Constant Approximation
A High Sensitivity CMOS Rectifier for 5G mm-Wave Energy Harvesting
Memristor-Based Operant Conditioning Neural Network Circuit With Emotion Transmission and Secondary Conditioned Reflex
Guest Editorial Special Issue on the International Symposium on Circuits and Systems - ISCAS 2024
Radiation Hardened 12T SRAM With Crossbar-Based Peripheral Circuit in 28nm CMOS Technology
A Single-Channel 8-bit 1.6-GS/s Alternate-Comparator SAR ADC With Dither-Based Background Offset Calibration in 28-nm CMOS
Analysis and Design of a 16-bit Continuous-Time Incremental Delta-Sigma ADC
Soft Fault Diagnosis of Analog Circuits Based on a ResNet With Circuit Spectrum Map
A 32 × 32-Pixel Flash LiDAR Sensor With Noise Filtering for High-Background Noise Applications
Analysis and Optimization Strategies Toward Reliable and High-Speed 6T Compute SRAM
A Two-Step Down Converter Based on Pseudo 4-Phase Mutual Operation for 48-to-1 Conversion
Serial-Stacked Single-Inductor Dual-Source Triple-Output Energy Harvesting Interface With 2D-MPPT for Battery-Free IoT Devices
A 36-Gb/s 1.6-pJ/b PAM-3 Transmitter Leveraging Digital Logic Cells and 4-Tap FFE in 22-nm CMOS
Neural Network Based Iterative Learning Control for Dynamic Hysteresis and Uncertainties in Magnetic Shape Memory Alloy Actuator
A 4.29nJ/pixel Stereo Depth Coprocessor With Pixel Level Pipeline and Region Optimized Semi-Global Matching for IoT Application
A Framework of Event-Triggered Prescribed-Time Stabilization of Time-Varying Nonlinear Systems and Its Application in Tunnel Diode Circuit
A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices
Technically Feasible Robust Complementary SOT-MRAM Design for Improving the Area and Energy Efficiency
A 900 MHz All-NMOS RF-DC Rectifier With Internal V TH Cancellation Technique for RF Energy Harvesting
A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias
Finite/Fixed-Time Synchronization of Multi-Layer Networks Based on Energy Consumption Estimation
Annealing Processing Architecture of 28-nm CMOS Chip for Ising Model With 512 Fully Connected Spins
Theoretical Analysis and Hardware Reproduction of the Hodgkin-Huxley Bifurcation Diagram in a LAM-Based Neuron on Edge of Chaos
Centralized System Identification of Multi-Rail Power Converter Systems Using an Iterative Decimation Approach
High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure
A 27-30 GHz T/R Module With Reflection-Type Phase Shifting and Machine-Learned Calibration
A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector
Two-Group Distributed Optimization Under Cooperative-Collaborative Networks With Linear Convergence
Editorial Special Issue for 50th Birthday of Memristor Theory and Application of Neuromorphic Computing Based on Memristor - Part II
Asynchronous Event-Driven Clocking and Control in Pipelined ADCs
A 24-29.5-GHz Scalable 2 × 2 I-Q TX/RX Chipset With Streamlined IF Interfaces for DBF Systems
A Dual 7T SRAM-Based Zero-Skipping Compute- In-Memory Macro With 1-6b Binary Searching ADCs for Processing Quantized Neural Networks
Compact Reconfigurable Dual-Band MMIC SPDT/SP4T Switches With On-Chip Coupled-Line Structure in GaN-on-SiC HEMT Technology
Design of a Leaky Integrate-and-Fire Model-Based SPAD Image Sensor for Efficient Edge Detection
Stochastic Dividers for Low Latency Neural Networks
Linearized Analysis and Quantization Error Minimization for Mid-Rise TDCs: A Tutorial
Lipschitz Stability Estimate for an Initial Wave Reconstruction Problem of Telegraph Type With Gaussian Noise
Model-Free Filter for Servo Drive Applications via Error Dynamics Diagonalization Technique
Control of a Buck DC/DC Converter Using Approximate Dynamic Programming and Artificial Neural Networks
An Efficient and Flexible Accelerator Design for Sparse Convolutional Neural Networks
A Soft-Switching Boost-Type Resonant Forward Converter With Load-Adaptive Efficiency Optimization
Fracmemristor Oscillator: Fractional-Order Memristive Chaotic Circuit
A Systematic Review of Voltage Reference Circuits: Spanning Room Temperature to Cryogenic Applications
Spatially Coupled Serially Concatenated Codes: Performance Evaluation and VLSI Design Tradeoffs
A Bias-Current-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation
Neural Bursting and Synchronization Emulated by Neural Networks and Circuits
A Single-Opamp Third Order CT ΔΣ Modulator With SAB-ELD-Merged Integrator and Three-Stage Hybrid Compensation Opamp
Automatic Tuning of Negative-R Circuit for High-Performance 95-dB DR 5-kHz Bandwidth Continuous-Time Delta-Sigma Modulator
Active Synchronization for Double-Integrator Network Systems Without Velocity Information
Asymmetric Voltage Latch Type and Ultra-Low Swing Bitline Sense Amplifiers for Low-Power High-Density 1R1W 8T SRAM in 14 nm FinFET
SpiMAM: CMOS Implementation of Bio-Inspired Spiking Multidirectional Associative Memory Featuring In-Situ Learning
Very-Low-Voltage Charge Pump Topologies for IoT Applications
Dynamics of the Hénon Map in the Digital Domain
High-Throughput FPGA-Compatible TRNG Architecture Exploiting Multistimuli Metastable Cells
An 840-to-970 MHz Multimodal Wake-Up Receiver With a Q-Equalized Antenna-ED Interface and 2-Dimensional Wake-Up Identification
A Variation-Robust 20-Gb/s Wireline Transceiver With Real-Time Calibration in 28-nm CMOS
Hybrid Ordered Statistics Decoding of Short-Length BCH Codes for URLLC Systems: Theoretical Analysis and Decoder Implementation
A Programmable On-Chip Hopf Bifurcation Circuit
Semi-Global Bounded Output Regulation of Linear Two-Time-Scale Systems With Input Saturation
DNN-Based Optimization to Significantly Speed Up and Increase the Accuracy of Electronic Circuit Design
Multi-Image Encryption Algorithm Based on Novel Spatiotemporal Chaotic System and Fractal Geometry
Prescribed-Time Asymptotic Tracking Control of Strict Feedback Systems With Time-Varying Parameters and Unknown Control Direction
A 55nA Quiescent Current Power-Wise Buck Converter With 1μA-600mA Load Range and 0.5V-1.8V Flexible Output Voltage Options
Correlated Channel-Oriented Expectation Propagation-Based Detector for Massive MIMO Systems
An Ultrahigh-Throughput and FPGA-Compatible TRNG Based on Dynamic Hybrid Metastability and Jitter Entropy Cells
Cryogenic Front-End ASICs for Low-Noise Readout of Charge Signals
Robust Wireless Interrogation of Fully-Passive RLC Sensors
General Efficient TMR for Combinational Circuit Hardening Against Soft Errors and Improved Multi-Objective Optimization Framework
A 28-nm Computing-in-Memory-Based Super-Resolution Accelerator Incorporating Macro-Level Pipeline and Texture/Algebraic Sparsity
Analysis and Design of a CMOS Bidirectional Passive Vector-Modulated Phase Shifter
A Linear-Array Receiver AFE Circuit Embedded 8-to-1 Multiplexer for Direct ToF Imaging LiDAR Applications
Shared Offset Cancellation and Chopping Techniques to Enhance the Voltage Accuracy of Multi-Amplifier Systems for Feedback Sensing in Power Management Applications
A 6.78-MHz Coupling Coefficient Sensorless Wireless Power Transfer System Charging Multiple Receivers With Efficiency Maximization by Adaptive Magnetic Field Distributor IC
MuGRA: A Scalable Multi-Grained Reconfigurable Accelerator Powered by Elastic Neural Network
Frequency-Transformation-Based Co-Designed Lowpass-Single/Multi-Passband-Highpass RF Filters
Distributed Observer-Based H ∞ Fault-Tolerant Control for DC Microgrids With Sensor Fault
Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness
FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging
Neuromorphic Circuit of Classical and Operant Conditioning Based on Tunable Neural Circuitry Motifs
A Robust Algorithm for the Design of Wideband Positive-Slope Linear Group Delay Filters
A Heterogeneous Platform for 3D NAND-Based In-Memory Hyperdimensional Computing Engine for Genome Sequencing Applications
Comprehensive Analytical Comparison of Ring Oscillators in FDSOI Technology: Current Starving Versus Back-Bias Control
A Secure Dynamic Event-Triggered Mechanism for Resilient Control of Multi-Agent Systems Under Sensor and Actuator Attacks
MPPT Multiplexed Hybrid Energy Harvesting Interface With Adaptive Switching Cycle and Single-Cycle Sampling for Wearable Electronics
ET-SRCKF-Based Dynamic State Estimation for Cyber-Physical Distribution Systems With Delayed Measurements
Fast Convolution Schemes for Piecewise Approximation of Large-Scale Electromagnetic Systems in Emerging Applications
A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory Interfaces
A 36 μW 2.8-3.4 dB Noise Figure Impedance Boosted and Noise Attenuated LNA for NB-IoT
Two-Dimensional Discrete Bi-Neuron Hopfield Neural Network With Polyhedral Hyperchaos
A Low-Latency FPGA Accelerator for YOLOv3-Tiny With Flexible Layerwise Mapping and Dataflow
Balanced Filtering Phase Shifters With Low Phase Deviation and High Common-Mode Suppression
Modeling and Design of Cold-Start Charge Pumps for Photovoltaic Energy Harvesters
Adaptive Cooperative Fault-Tolerant Control for Output-Constrained Nonlinear Multi-Agent Systems Under Stochastic FDI Attacks
Kalman Filters Based Distributed Cyber-Attack Mitigation Layers for DC Microgrids
Fully Integrated Analog Machine Learning Classifier Using Custom Activation Function for Low Resolution Image Classification
A Framework for Designing and Analyzing Margin Propagation-Based Analog Correlators
A 5-780-MHz Transceiver ASIC for Multinuclear NMR Spectroscopy in 0.13-μm BiCMOS
Modeling and Adaptive Parameter Estimation for a Piezoelectric Cantilever Beam
A 48-dB Range, 0.86-dB Step, and 0.06-dB Error dB-Linear PGA Based on Resistive Ladder Attenuator: Design Theory and Realization
HWSA: A High-Ratio Weight Sparse Accelerator for Efficient CNN Inference
Edge of Chaos Is Sine Qua Non for Turing Instability
Security-Based Event-Triggered Fuzzy Control for Multiarea Power Systems Under Cross-Layer DoS Attacks
Low-Latency SCL Polar Decoder Architecture Using Overlapped Pruning Operations
Transmission-Line Bandpass Filter Structures With Infinite Reflectionless Range
A High-Frequency CMOS Meminductor Emulator for Spiking Neuron
Remote Robust State Estimation for Nonlinear Cyber-Physical Systems Under Denial-of-Service Attacks
Secure Control for Photovoltaic Energy DC Circuit Conversion Systems With Modulated Chaotic Masking and Adaptive Weighting Techniques
All Digital Phase-Locked Loop Networks for Clock Generation and Distribution: Network Stability, Convergence and Performance
Multilogic Sense Amplifier With a Circuit for Dynamic Reference Voltage Generation
Special Transfer Section for Selective Rejecting and Amplification of Bands in Equalization
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode
Bearing-Based Adaptive Cooperative Elliptical Circumnavigation Control for Multi-Agent Systems
Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements
Global Full-State Prescribed Performance Control of Nonlinear Systems With Dead-Zone and 1-Bit-Triggered Input
A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation
A Compact and Continuous Reformulation of the Strachan TaO x Memristor Model With Improved Numerical Stability
Passive Post-Resonance Tuned Reflectors to Achieve Both 10-bit Phase-Shifting Resolution and Low Insertion Loss Across 20-30 GHz
A Rapid Circle Centre-Line Concept-Based MPPT Algorithm for Solar Photovoltaic Energy Conversion Systems
Self-Organizing Fuzzy Neural Nonsingular Fast Terminal Sliding Mode Control of DC-DC Buck Converter
L ∞ -Gain of Fractional-Order Positive Systems With Mixed Time-Varying Delays
Memristor-Based Neural Network Circuit of Full-Function Pavlov Associative Memory With Unconditioned Response Mechanisms
Analog Neural Computing With Super-Resolution Memristor Crossbars
A 2.5-A 3-ns-Response-Time Calibration-Free Hybrid LDO Using Scalable Self-Clocked Stochastic Flash-ADC for In-Loop Quantization
A CNN-Based Super-Resolution Processor With Short-Term Caching for Real-Time UHD Upscaling
High-Throughput Nanopore-FET Array Readout IC With 5-MHz Bandwidth and Background Offset/Drift Calibration
A Novel Adaptive Control Scheme for Automotive Electronic Throttle Based on Extremum Seeking
Bipartite Average Tracking for Multi-Agent Systems With Disturbances: Finite-Time and Fixed-Time Convergence
Huicore: A Generalized Hardware Accelerator for Complicated Functions
Predefined-Time Precise Tracking of Uncertain MIMO Nonlinear Systems With Time-Varying Input Delay
Modeling and Mitigating the Interconnect Resistance Issue in Analog RRAM Matrix Computing Circuits
Reconfigurable Receiver With Adaptive Output Voltage for Wireless Power Transfer
Efficient Circuit Performance Prediction Using Machine Learning: From Schematic to Layout and Silicon Measurement With Minimal Data Input
Multi-Frequency Multi-Amplitude Superposition Modulation Method With Phase Shift Optimization for Single Inverter of Wireless Power Transfer System
Fixed-Time Sliding Mode Control for DC/DC Buck Converters With Mismatched Uncertainties
ML-Based Fully-Numerical Design Method for Load-Independent Class-EF WPT Systems
Robust Open-Switch Fault Diagnosis of Bidirectional DC/DC Converters Based on Extended Kalman Filter With Multiple Corrections
A Delta Sigma Modulator-Based Stochastic Divider
Single-Reference-Based Multi-Level Cell Sensing Scheme for Spin-Orbit Torque MRAM
Hardware-Efficient Architecture for Multiple Quantized Gaussian Noise Generation
Event-Triggered Impulsive Controller Design of Continuous Nonlinear Systems Using Liquid-Updating ADP
Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers
Transmitter and Receiver for High Speed Polymer Microwave Fiber Communication at D-Band
Applying Lightweight Soft Error Mitigation Techniques to Embedded Mixed Precision Deep Neural Networks
Predictor Feedback Control for Discrete-Time Systems With Input Delays and Multiple State Delays via Bivariant Fundamental Matrices
Balanced-to-Unbalanced Quadrature Couplers With Wide-Band Common-Mode Suppression
A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS
An Ultra-Low Noise and Wide Output Range LDO With BJT Input Stage and Base Current Cancellation Technique
A Privacy-Preserving Federated Reinforcement Learning Method for Multiple Virtual Power Plants Scheduling
Analysis and Design of a Charge Sampler With 70-GHz 1-dB Bandwidth in 130-nm SiGe BiCMOS
Layer-Wise Mixed-Modes CNN Processing Architecture With Double-Stationary Dataflow and Dimension-Reshape Strategy
Parallel and Pipeline Multicore OFDM Baseband Processor for Wideband UOWC Systems
ImSTDP: Implicit Timing On-Chip STDP Learning
A Balanced Sparse Matrix Convolution Accelerator for Efficient CNN Training
3D SRAM Macro Design in 3D Nanofabric Process Technology
A 9-to-42-GHz High-Gain Low-Noise Amplifier Using Coupled Interstage Feedback in 0.15-μm GaAs pHEMT Technology
Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation
Distributed Secure Fusion Estimation With Lossless Data Compression Against Stochastic Event-Based Attacks in Power Systems
Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing
Walsh-Hadamard-Based Orthogonal Sampling Technique for Parallel Neural Recording Systems
Efficient Discrete Temporal Coding Spike-Driven In-Memory Computing Macro for Deep Neural Network Based on Nonvolatile Memory
A Neural-Network-Assisted Chaos-NOMA Scheme
Predictive Voltage Hierarchical Controller Design for Islanded Microgrids Under Limited Communication
NASH: Neural Architecture and Accelerator Search for Multiplication-Reduced Hybrid Models
A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Cross-Coupled Pre-Sensing
Reconfigurable 2.4/5.0-GHz Dual-Band CMOS Power Amplifier for WLAN 802.11ax
Interval Observer-Based Robust Coordination Control of Multi-Agent Systems Over Directed Networks
Comments on "Fractional-Order Sliding Mode Approach of Buck Converters With Mismatched Disturbances"
TROT: A Three-Edge Ring Oscillator Based True Random Number Generator With Time-to-Digital Conversion
An Integrated Gate Driver Based on SiC MOSFETs Adaptive Multi-Level Control Technique
A 1-16b Reconfigurable 80Kb 7T SRAM-Based Digital Near-Memory Computing Macro for Processing Neural Networks
A 50Gb/s CMOS Optical Receiver With Si-Photonics PD for High-Speed Low-Latency Chiplet I/O
Analysis of Back-Gate Bias Control on EVM Measurements of a Dual-Band Power Amplifier in 22 nm FD-SOI for 5G 28 and 39 GHz Applications
An Active Dead-Time Control Circuit With Timing Elements for a 45-V Input 1-MHz Half-Bridge Converter
Hybrid Convolution Architecture for Energy-Efficient Deep Neural Network Processing
Equivalence Between Geometric Frequency and Lagrange Derivative
An Efficient Resonant Pole Inverter With Reliability Improvement of Soft-Switching in the Case of Open Failure of Any Auxiliary Device on Each Bridge Arm
CLAT: A Clustering-Based Attention Transformer Accelerator for Low-Latency Text Generation in LLMs
BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory
Impedance Circuit Model of Voltage Source Converter With DC-Link Voltage Control Dynamics
A Doherty Power Amplifier With Extended High-Efficiency Range Using Three-Port Harmonic Injection Network
HD-CIM: Hybrid-Device Computing-In-Memory Structure Based on MRAM and SRAM to Reduce Weight Loading Energy of Neural Networks
SMC for Discrete Semi-Markov Switching Slow Sampling Singularly Perturbed Models With Applications
A 16-Channel Analog CMOS SiPM With On-Chip Front-End for D-ToF LiDAR
Adaptive Practical Optimal Time-Varying Formation Tracking Control for Disturbed High-Order Multi-Agent Systems
MA-Opt: Reinforcement Learning-Based Analog Circuit Optimization Using Multi-Actors
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs
Lookup Table-Based Computing-in-Memory Macro Approximating Dot Products Without Multiplications for Energy-Efficient CNN Inference
Differential Edge Modulation Signaling for Low-Energy, High-Speed Wireline Communication
An Open-Circuit Fault Diagnosis for Three-Phase PWM Rectifier Without Grid Voltage Sensor Based on Phase Angle Partition
AnGeL: Fully-Automated Analog Circuit Generator Using a Neural Network Assisted Semi-Supervised Learning Approach
Reinforcement Learning-Based Fault-Tolerant Control for Output-Constrained Nonlinear Systems With Preassigned-Time Performance
A Highly Stable Physically Unclonable Function Using Algorithm-Based Mismatch Hardening Technique in 28-nm CMOS