yusuke1997/dblp-id-title huggingface dataset:
Architectures and VLSI Implementations of the AES-Proposal Rijndael
Control Features of a Magnetic-Drum Telephone Office
Theory and Design of Adjacent Asymmetric Error Masking Codes
R68-5 Models of Computational Systems-Cyclic to Acyclic Graph Transformations
Nonlinear Intrinsic Dimensionality Computations
DONUT: A Threshold Gate Computer
Power Management for Wireless Data Transmission Using Complex Event Processing
Rethinking Control Flow in Spatial Architectures: Insights Into Control Flow Plane Design
Relationship between GF(2 m ) Montgomery and Shifted Polynomial Basis Multiplication Algorithms
A Low-Rate DoS Attack Mitigation Scheme Based on Port and Traffic State in SDN
An Intelligent Cache System with Hardware Prefetching for High Performance
Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures
Space/Time Trade-Offs for Higher Radix Modular Multiplication Using Repeated Addition
Hierarchical Scalable Photonic Architectures for High-Performance Processor Interconnection
Tunnel Diode Delay-Line Memory
Matrix Multiplication on the OTIS-Mesh Optoelectronic Computer
Characterizing the Performance of Algorithms for Lock-Free Objects
An Efficient Coordinate Rotation Algorithm
Classical Artificial Neural Network Training Using Quantum Walks as a Search Procedure
An Approach to the Diagnosability Analysis of a System
Improving NFS Performance Over Wireless Links
Comments on "Weighting Method for the Determination of the Irredundant Set of Prime Implicants"
On the Computational Complexity of a Generalized Scheduling Problem
Parallel High-Radix Nonrestoring Division
Outer Product Expansions and Their Uses in Digital Image Processing
The Separation Technique: A Method for Simulating Transistors to Aid Integrated Circuit Design
A Real-Time Hardware System for Digital Processing of Wide-Band Video Images
A Custom Accelerator for Homomorphic Encryption Applications
A Protocol for Multirendezvous of LOTOS Processes
Mastrovito Form of Non-Recursive Karatsuba Multiplier for All Trinomials
OOLU: An Operation-Based Optimized Sparse LU Decomposition Accelerator for Circuit Simulation
An Algorithm for the Solution of Linear Inequalities
Comments on "Design of Diagnosable Iterative Arrays"
A New Approach to the Design of Testable PLA's
An Overflow-Free Residue Multiplier
Design and Evaluation of the Optimal Cache Allocation for Content-Centric Networking
HRC: A 3D NoC Architecture with Genuine Support for Runtime Thermal-Aware Task Management
Low-Cost Modular Totally Self-Checking Checker Design for m-out-of-n Code
Reduced Precision DWC: An Efficient Hardening Strategy for Mixed-Precision Architectures
Optimizing Hardware Design by Composing Utility-Directed Transformations
Stochastic Neural Computation II: Soft Competitive Learning
System Segmentation for the Parallel Diagnosis of Computers
Job-Mix Modeling and System Analysis of an Aerospace Multiprocessor
A Generalized Technique for Spectral Analysis
A Fast Mode-Control Switch for Iterative Differential Analyzers
Graph Partitioning Using Learning Automata
Dynamic Checkpointing Policy in Heterogeneous Real-Time Standby Systems
R70-2 Nested Stack Automata
SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs
NDRec: A Near-Data Processing System for Training Large-Scale Recommendation Models
Determinacy of Generalized Schema
Improved Bounds for Algorithm-Based Fault Tolerance
TDM and TWDM de Bruijn Networks and ShuffleNets for Optical Communications
Distributed Ring Embedding in Faulty De Bruijn Networks
Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST
A Computer Architecture for Level Structured Systems
Compiler Optimizations for Enhancing Parallelism and Their Impact on Architecture Design
Digit Serial Methods with Applications to Division and Square Root
Computation of the Fast Walsh-Fourier Transform
Easily Testable Sequential Machines with Extra Inputs
Run-Time Cache Bypassing
Correction to "Subtraction by Minuend Complementation" l
Beyond the Limits of DPA: Combined Side-Channel Collision Attacks
An Approximation Algorithm for Diagnostic Test Scheduling in Multicomputer Systems
Generalizing the Square Root Rule for Optimal Periodic Scheduling in Push-Based Wireless Environments
Fairness-Aware Energy Efficient Scheduling on Heterogeneous Multi-Core Processors
On Some Dynamical Properties of Finite Cellular Automaton
B74-8 Design of Man-Computer Dialogues
Comments on "A Comparison of Seven Techniques for Choosing Subsets of Pattern Recognition Properties"
Maximizing Mean-Time to Failure in k-Resilient Systems with Repair
Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs
R68-7 Analog Simulation of Ferroresonant System Including Analysis of Hysteresis Loop
Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs
Arithmetic on the European Logarithmic Microprocessor
PITEM: Permutations-Based Instruction Tracking Via Electromagnetic Side-Channel Signal Analysis
DESA: Dataflow Efficient Systolic Array for Acceleration of Transformers
An Algorithm for Finding Nearest Neighbors
Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs
Design of a Universal Decoder Model Based on DNA Winner-Takes-All Neural Networks
Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems
An NMOS Microprocessor for Analog Signal Processing
Fair Edge Deletion Problems
On the Nondomination of Cohorts Coteries
A Technique for the Reduction of a Given Machine to a Minimal-State Machine
Optimum State Assignment for the D Flip-Flop
Implementing Automatic Location Update for Follow-Me Database Using VoIP and Bluetooth Technologies
Block Recombination Approach for Subquadratic Space Complexity Binary Field Multiplication Based on Toeplitz Matrix-Vector Product
Optimization Models for Configuring Distributed Computer Systems
A Multiprocessor Architecture for Generating Fractal Surfaces
R70-9 A Graph-Theoretic Model for Periodic Discrete Structures
Computers in Process Industry Control
Path Complexity of Logic Networks
Machine Learning-Based Microarchitecture- Level Power Modeling of CPUs
Lower Bounds on the Loading of Multiple Bus Networks for Binary Tree Algorithms
A Theory of Diagnosability of Digital Systems
Embedding an Arbitrary Binary Tree into the Star Graph
Formal Analysis and Synthesis of Bilateral Switching Networks
Ada-WL: An Adaptive Wear-Leveling Aware Data Migration Approach for Flexible SSD Array Scaling in Clusters
Algorithms for Triple-Word Arithmetic
Fast Inner-Product Algorithms and Architectures for Deep Neural Network Accelerators
A Quantitative Evaluation of Cache Types for High-Performance Computer Systems
The Butterfly Effect in Primary Visual Cortex
Data Distribution for Heterogeneous Storage Systems
A Formula for Ternary Network Cost
Guest Editors' Introduction to the Special Issue on Hardware Security
The Synthesis of Redundant Threshold- Logic Elements
The Extended Resolution Digital Differential Analyzer: A New Computing Structure for Solving Differential Equations
PRAM Processor Allocation: A Hidden Bottleneck in Sublogarithmic Algorithms
Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders
Reduction of CC-Tables Using Multiple Implication
AToM: Adaptive Token Merging for Efficient Acceleration of Vision Transformer
Sketch-Based Adaptive Communication Optimization in Federated Learning
Expanding the Range of Convergence of the CORDIC Algorithm
New Methods for Realizing Plural Near-Native Performance Virtual Machines
Performance of ARQ Schemes in Token Ring Networks
Dynamic Power Management for Nonstationary Service Requests
In-Situ NAS: A Plug-and-Search Neural Architecture Search Framework Across Hardware Platforms
An Experimental Nondestructive Microwave Ferrite Core Readout Using Stripline
Analysis of a BICS-Only Concurrent Error Detection Method
Small Diameter Symmetric Networks from Linear Groups
Efficient Algorithms and Architectures for Field Multiplication Using Gaussian Normal Bases
Localized Distance-Sensitive Service Discovery in Wireless Sensor and Actor Networks
A Heuristic for Suffix Solutions
Network Calculus With Flow Prolongation - A Feedforward FIFO Analysis Enabled by ML
ISPA: Exploiting Intra-SM Parallelism in GPUs via Fine-Grained Resource Management
Fast Identification of Undetectable Transition Faults under Functional Broadside Tests
A Design of Programmable Logic Arrays with Universal Tests
An Efficient Optimal Normal Basis Type II Multiplier
About Feedback and SR Flip-Flops
Striping-Aware Sequential Prefetching for Independency and Parallelism in Disk Arrays with Concurrent Accesses
Minimal TANT Networks of Functions with DONT CARE's and Some Complemented Input Variables
Load-Balancing Multipath Switching System with Flow Slice
Algorithms for Iterative Array Multiplication
An Investigation of the Potential of MOS Transistor Memories
Biresidue Error-Correcting Codes for Computer Arithmetic
On a New Class of Bounds on Bayes Risk in Multihypothesis Pattern Recognition
Enhancing Performance of HW/SW Cosimulation and Coemulation by Reducing Communication Overhead
On a Method of Sequential Pattern Recognition
Completely Pinpointing the Missing RFID Tags in a Time-Efficient Way
Divide-and-Conquer for Parallel Processing
Angle Detection on Digital Curves
CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation
Bottleneck Steiner Trees in the Plane
Generation of Grey Tones by Computer for Simulation of Visual Information Systems
Low Complexity Normal Elements over Finite Fields of Characteristic Two
Scroll Editing: An On-Line Algorithm for Manipulating Long Character Strings
A Method for Modulo-2 Minimization
Switching Circuits as Topological Models in Discrete Probability Theory
Linear Models for Keystream Generators
On-the-Fly Rounding
Exploiting Symmetrization and D-Reducibility for Approximate Logic Synthesis
Half-Hot State Assignments for Finite State Machines
A Design Diversity Metric and Analysis of Redundant Systems
Variable Field-Length Data Manipulation in a Fixed Word-Length Memory
Variable-Length Distinguishing Sequences and Their Application to the Design of Fault-Detection Experiments
Test for Planarity of a Circuit Given by an Expression
Memory Allocations for Multiprocessor Systems That Incorporate Content-Addressable Memories
A Study of the Electrochemical Cell as a Storage Element for the Memory Access Gap
On Nonblocking Multicast Fat-Tree Data Center Networks with Server Redundancy
Analysis of Asynchronous Circuits Under Different Delay Assumptions
Fixed Priority Scheduling with Limited Priority Levels
A Two's Complement Array Multiplier Using True Values of the Operands
System Fault Diagnosis: Masking, Exposure, and Diagnosability Without Repair
Routing or Computing? The Paradigm Shift Towards Intelligent Computer Network Packet Transmission Based on Deep Learning
An O(log 2 N) Depth Asymptotically Nonblocking Self-Routing Permutation Network
Influence of Workload on Error Recovery in Random Access Memories
On Necessary and Sufficient Conditions for Multiple Fault Undetectability
Pursuing Extreme Power Efficiency With PPCC Guided NoC DVFS
A Secure and Decentralized DLaaS Platform for Edge Resource Scheduling Against Adversarial Attacks
Analog Computer Applications in Predictor Design
A Decomposition Procedure for the Analysis of a Closed Fork/Join Queueing System
Split-Radix Based Compact Hardware Architecture for CRYSTALS-Kyber
An Efficient Simplex Coverability Algorithm in E 2 with Application to Stochastic Sequential Machines
The MPG System: A Machine-Independent Efficient Microprogram Generator
Error Tolerant Design of Multivalued Logic Functions
The Formal Specification and Design of a Distributed fElectronic Funds-Transfer System
Optimal Compression for Encrypted Key-Value Store in Cloud Systems
Wide-Sense Nonblocking Clos Networks Under Packing Strategy
An On-Chip IP Address Lookup Algorithm
Fault-Tolerant Asynchronous Sequential Machines
A First Look at RISC-V Virtualization From an Embedded Systems Perspective
Scheduling Security-Critical Real-Time Applications on Clusters
Processor Saving Scheduling Policies for Multiprocessor Systems
A Mutual-Influence-Aware Heuristic Method for Quantum Circuit Mapping
A Selective Trigger Scan Architecture for VLSI Testing
ED4I: Error Detection by Diverse Data and Duplicated Instructions
Schedulability Analysis of Conditional Parallel Task Graphs in Multicore Systems
Small Constant Mean-Error Imprecise Adder/Multiplier for Efficient VLSI Implementation of MAC-Based Applications
Synthesis and Analysis: A Flexible Technique for Processing Command Language
Comments on "A Fast and Efficient Processor Allocation Scheme for Mesh-Connected Multicomputers"
A Theory and Method for Correlation Analysis of Nonstationary Signals
Me-CLOCK: A Memory-Efficient Framework to Implement Replacement Policies for Large Caches
Better Adaptive Malicious Users Detection Algorithm in Human Contact Networks
Preudo-Kronecker Expressions for Symmetric Functions
Square Meshes are not always Optimal
A New Type of Ferroelectric Shift Register
Modular Concurrency Control and Failure Recovery
The Organization of High-Speed Memory for Parallel Block Transfer of Data
Architecture Technique Trade-Offs Using Mean Memory Delay Time
A Process Algebraic View of Latency-Insensitive Systems
Optimization of Weighted Finite State Transducer for Speech Recognition
Two-Level Correlation on an Analog Computer
A Modular Approach to Real-Time Supersystems
The Description and Use of Register-Transfer Modules (RTM's)®
Comment on "Solution of Nonlinear Equations" 1
Convergence Properties of Optimization Algorithms for the SAT Problem
Scalability in Computing and Robotics
Multidimensional Balanced Binary Trees
Hypercall-Oriented Abnormal VM Status Detection System: A Non-Intrusive Solution for Both Hypervisor and Guests
XPAND: An Efficient Test Stimulus Compression Technique
A Unified Framework for Simulating Markovian Models of Highly Dependable Systems
B 74-30 Foundation of the Theory of Learning Systems
Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation
A Transform for Logic Networks
Distributed Deadlock-Free Routing in Faulty, Pipelined, Direct Interconnection Networks
Use of Sparse and/or Complex Exponents in Batch Verification of Exponentiations
Bi-Level Reconfigurations of Fault Tolerant Arrays
Public-Key Encryption with Fuzzy Keyword Search: A Provably Secure Scheme under Keyword Guessing Attack
A New Core Switch for Magnetic Matrix Stores and Other Purposes
Residue Number System Truth-Table Look-Up Processing - Moduli Selection and Logical Minimization
Space-Optimal, Wait-Free Real-Time Synchronization
Optimal Distributed Algorithms for Sorting and Ranking
B74-9 Digital Computer Fundamentals
Minimum Achievable Utilization for Fault-Tolerant Processing of Periodic Tasks
Power Consumption Prediction and Power-Aware Packing in Consolidated Environments
Signed Digit Addition and Related Operations with Threshold Logic
A Segmentation Technique for Waveform Classification
Congestion Control of Packet Communication Networks by Input Buffer Limits - A Simulation Study
Aliasing Computation Using Fault Simulation with Fault Dropping
A Method for Solving Arbitrary-Wall Mazes by Computer
On the Optimal Pre-Computation of Window τ NAF for Koblitz Curves
A Queuing-Theoretic and Optimization-Based Model for Radio Resource Management in IEEE 802.16 Broadband Wireless Networks
Arithmetic Algorithms for Extended Precision Using Floating-Point Expansions
On the Space Requirement of Interval Routing
Computing and Error Matrices in Linear Differential Analyzers
On a Bit-Serial Input and Bit-Serial Output Multiplier
Correction [to "Some techniques of state assignment for synchronous sequential machines"]
Resource Allocation in a Client/Server System for Massive Multi-Player Online Games
An Experimental Word Decode and Drive System for a Magnetic Film Memory with 20-ns READ-Cycle Time
Asymtotically Optimal Interconnection Networks from Two-State Cells
Comment on 'On-Line Scheduling Policies for a Class of IRIS Real-Time Tasks'
Generation of Optimal Transition Count Tests
Arithmetic for Ultra-High-Speed Tomography
Throughput Analysis of Cache-Based Multiprocessors with Multiple Buses
Analysis and Efficient Implementations of a Class of Composited de Bruijn Sequences
Hydra: Deadline-Aware and Efficiency-Oriented Scheduling for Deep Learning Jobs on Heterogeneous GPUs
Robust Processing Rate Allocation for Proportional Slowdown Differentiation on Internet Servers
Combining Efficiency, Fidelity, and Flexibility in Resource Information Services
A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead
Scratchpad Memory Management Techniques for Code in Embedded Systems without an MMU
NUDA: Non-Uniform Directory Architecture for Scalable Chip Multiprocessors
A Fault-Tolerant Group Communication Protocol in Large Scale and Highly Dynamic Mobile Next-Generation Networks
Determination of Multipliers Mapping an Arbitrary Integer into a Range of Certain Type
Fault Tolerant Computing: An Introduction and a Perspective
Buffered Banks in Multiprocessor Systems
CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-Based CIM Architectures
Digital and Hybrid Computational Aspects of the Discrete Representation Theorem of Nonlinear Estimation
Comments on "Nonlinear Sequential Circuits"
Extending Performance-Energy Trade-offs Via Dynamic Core Scaling
Maximizing I/O Throughput and Minimizing Performance Variation via Reinforcement Learning Based I/O Merging for SSDs
The Timewheel Group Communication System
A Note on the Restricted Range Cutting Algorithm
Logical Network Cost and Entropy
Designing Storage Efficient Decision Trees
Performance Analysis of Distributed Routing Strategies Free of Ping-Pong-Type Looping
A Novel Computational Model for Non-Linear Divisible Loads on a Linear Network
A Dynamic Slack Management Technique for Real-Time Distributed Embedded Systems
Random Pattern Testing Versus Deterministic Testing of RAM's
Guest Editorial: Special Section on Data Management Systems and Mobile Computing
Signed Modified Reflected Binary Code
Lightweight Power Monitoring Framework for Virtualized Computing Environments
Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors
FPGA-Based High-Performance and Scalable Block LU Decomposition Architecture
LPC: An Error Correction Code for Mitigating Faults in 3D Memories
The Effect of Spatial Variations in Voltage and Temperature in Emitter Coupled Logic Systems
Circuits Using Tunnel Diode Flip-Flops and PNPN Diodes
Coupled Incomplete Cholesky and Jacobi Preconditioned Conjugate Gradient on the New Generation of Sunway Many-Core Architecture
Synthesis of Generalized Parallel Counters
Comment on "Computation of Time-Phase Displacements of Binary Linear Sequence Generators"
A Framework for Carbon-Aware Real-Time Workload Management in Clouds Using Renewables-Driven Cores
Memory Interference Models with Variable Connection Time
Dynamic Binary Translation and Optimization
The Cambridge Fast Ring Networking System
Generating Neural Networks for Diverse Networking Classification Tasks via Hardware-Aware Neural Architecture Search
Double Point Compression with Applications to Speeding Up Random Point Multiplication
Some New Error Bounds and Approximations for Pattern Recognition
NORNAND Maitra Cascades
CRAT: Enabling Coordinated Register Allocation and Thread-Level Parallelism Optimization for GPUs
A Privacy-Preserving Comparison Protocol
Fast Carry-Propagation Iterative Networks
A Fully Parallel Mixed-Radix Conversion Algorithm for Resedue Number Applications
TransMap: Transformation Based Remapping and Parallelism for High Utilization and Energy Efficiency in CGRAs
Energy-Efficient Stream Compaction Through Filtering and Coalescing Accesses in GPGPU Memory Partitions
A Carry-Free Architecture for Montgomery Inversion
An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors
CEDA: Control-Flow Error Detection Using Assertions
Transport Time-Delay Simulation for Transmission Line Representation
Fault tolerance in a systolic residue arithmetic processor array
Performability Analysis of Large-Scale Multi-State Computing Systems
VisualNet: An End-to-End Human Visual System Inspired Framework to Reduce Inference Latency of Deep Neural Networks
Achieving Simple, Secure and Efficient Hierarchical Access Control in Cloud Computing
The Design or Multipoint Linkages in a Teleprocessing Tree Network
Post-Silicon Code Coverage for Multiprocessor System-on-Chip Designs
Extending the Scope of Golub's Method Beyond Complex Multiplication
Comment on "Counting with Majority-Logic Networks"
Comment on "Computation of the Fast Walsh-Fourier Transform" 1
Area-Time Optimal Adder Design
A Software Cost Model with Warranty and Risk Costs
Reading gapless tape
Fault-Tolerant Wormhole Routing Algorithms for Mesh Networks
A Preliminary Evaluation of the Critical Path Method for Scheduling Tasks on Multiprocessor Systems
On Tracey's Internal State Assignment Method
Comments on "Multiway Splitting Method for Toeplitz Matrix Vector Product"
A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing
Fast Addition of Large Integers
An Iterative Computational Technique for Performance Evaluation of Networks-on-Chip
Iterative Solution of Large-Scale Systems by Hybrid Techniques
Comment on "The Focus Number System"
Early Register Deallocation Mechanisms Using Checkpointed Register Files
Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors
Techniques to Reduce Switching and Leakage Energy in Unrolled Block Ciphers
Self-Diagnosing Cellular Implementations of Finite-State Machines
Balancing Privacy and Accuracy Using Significant Gradient Protection in Federated Learning
Transferable FORTRAN Subroutine for Rapid Extended Sorting
Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures
Single Row Routing
A Modeling Framework for Reliability of Erasure Codes in SSD Arrays
A Sweeping Line Approach to Interconnect Testing
A General Class of Maximal Codes ror Computer Applications
Matrix Switch and Drive System for a Low-Cost Magnetic-Core Memory
A Programming System for Detection and Diagnosis of Machine Malfunctions
Recursive Coverage Projection of Test Sets
Leveraging Hardware-Assisted Virtualization for Deterministic Replay on Commodity Multi-Core Processors
Test Vector Embedding into Accumulator-Generated Sequences: A Linear-Time Solution
On Tohma's Decompositions of Logical Functions
Double Step Branching CORDIC: A New Algorithm for Fast Sine and Cosine Generation
Multiplicative Algorithms for Ternary Arithmetic Using Binary Logic
Odd Binary Asynchronous Counters
Syndrome-Testability Can be Achieved by Circuit Modification
Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays
Run-Time Recovery Mechanism for Transient and Permanent Hardware Faults Based on Distributed, Self-Organized Dynamic Partially Reconfigurable Systems
Low-latency Hardware Architecture for VDF Evaluation in Class Groups
Construction of Irredundant Multilevel Switching Functions
A PROBE-Based Heuristic for Graph Partitioning
A Low-Error, Cost-Efficient Design Procedure for Evaluating Logarithms to Be Used in a Logarithmic Arithmetic Processor
A Primary-Backup Channel Approach to Dependable Real-Time Communication in Multihop Networks
A Minimum Table Size Result for Higher Radix Nonrestoring Division
The Minimization of TANT Networks
Fault Detection in Iterative Logic Arrays
Professional group on electronic computers system organization of the DYSEAC
Design Principles for Practical Self-Routing Nonblocking Switching Networks with O(N log N) Bit-Complexity
Packed AES-GCM Algorithm Suitable for AES/PCLMULQDQ Instructions
Efficient Approximate Wordlength Optimization
Adaptive Fault-Tolerant Routing in Hypercube Multicomputers
Effects of Adaptation Parameters on Convergence Time and Tolerance for Adaptive Threshold Elements
Completely Periodic Multithreshold Functions
A Systolic Array Implementation of the Feng-Rao Algorithm