yusuke1997/dblp-id-title huggingface dataset:
Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools
Radiation Hardened Click Controllers for Soft Error Resilient Asynchronous Architectures
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link
Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications
An Analysis of Determinacy Using a Trace-Theoretic Model of Asynchronous Circuits
Innovations in MTNCL Gate Design: An Alternative MTCMOS Power-Gating Approach
A High Speed Asynchronous Multi Input Pipeline for Compaction and Transfer of Parallel SIMD Data
Relative Timing
An Asynchronous Low-Power 80C51 Microcontroller
An asynchronous pipelined lattice structure filter
Modular Redundancy in a GALS System Using Asynchronous Recovery Links
High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths
Synthesis of QDI FSMs from Synchronous Specifications
Integrated Fanout Optimization and Slack Matching of Asynchronous Circuits
Qualifying Relative Timing Constraints for Asynchronous Circuits
Single-track handshake signaling with application to micropipelines and handshake circuits
Data Synchronization Issues in GALS SoCs
Symbolic Techniques for Performance Analysis of Timed Systems Based on Average Time Separation of Events
Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis
Adaptive Pipeline Structures fo Speculation Control
Automatic Clock: A Promising Approach toward GALSification
Modelling Mixed 4phase Pipelines: Structures and Patterns
Transistor-Level Analysis of Dynamic Delay Models
Control resynthesis for control-dominated asynchronous designs
Formal Verification of Safety Properties in Timed Circuits
A Frameless Imaging Sensor with Asynchronous Pixels: An Architectural Evaluation
Real-Time Merging
Recursive Formulations for N Input Asynchronous First Come First Served Arbiters
Fault Classification of the Error Detection Logic in the Blade Resilient Template
Using partial orders for trace theoretic verification of asynchronous circuits
Stretching quasi delay insensitivity by means of extended isochronic forks
Counterflow pipeline based dynamic instruction scheduling
Performance Optimization and Analysis of Blade Designs under Delay Variability
Asynchronous Architectures for Nanometer Scales
Contacting Biological Cells with Electronic Circuits
Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions
26th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2020, Salt Lake City, UT, USA, May 17-20, 2020
Static scheduling of instructions on micronet-based asynchronous processors
Clockless Design Performance Monitoring for Nanometer Technologies
Logic Decomposition of Asynchronous Circuits Using STG Unfoldings
A Low Power Asynchronous GPS Baseband Processor
Pipeline synchronization
A low-power asynchronous data-path for a FIR filter bank
22nd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2016, Porto Alegre, Brazil, May 8-11, 2016
Delay Insensitive Logic for RSFQ Superconductor Technology
Design and Performance Analysis of Buffers: A Constructive Approach
AES Hardware-Software Co-design in WSN
Response Time Properties of Some Asynchronous Circuits
Energy and Performance Models for Clocked and Asynchronous Communication
Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs
Self-Timed Meshes Are Faster Than Synchronous
ARAS: asynchronous RISC architecture simulator
An Asynchronous FPGA with Two-Phase Enable-Scaled Routing
24th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2018, Vienna, Austria, May 13-16, 2018
Hierarchical gate-level verification of speed-independent circuits
Pulse-driven dual-rail logic gate family based on rapid single-flux-quantum (RSFQ) devices for asynchronous circuits
Gradual Synchronization
AnARM: A 28nm Energy Efficient ARM Processor Based on Octasic Asynchronous Technology
Asynchronous Serial Infrastructure Using FPIO
Capacitor Discharging Through Asynchronous Circuit Switching
A Self-Timed Ring based PUF
MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures
Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL
The Lackey Self-Timed Switch-Fabric Design Framework
Partial order based approach to synthesis of speed-independent circuits
Performance and Area Optimization of a Bundled-Data Intel Processor through Resynthesis
Opportunistic Merge Element
WAITX: An Arbiter for Non-persistent Signals
Asynchronous circuits based on multiple localised current-sensing completion detection
Efficient Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication
Asynchronous Design Using Commercial HDL Synthesis Tools
How to Achieve Worst-Case Performance
Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism
An Event Spacing Experiment
17th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2011, Cornell University, Ithaca, New York, USA, 27-29 April 2011
Performance Bounds of Asynchronous Circuits with Mode-Based Conditional Behavior
Analyzing Isochronic Forks with Potential Causality
Efficient Metastability Characterization for Schmitt-Triggers
11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 14-16 March 2005, New York, NY, USA
Efficient building blocks for delay insensitive circuits
Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus
Demystifying Data-Driven and Pausible Clocking Schemes
A New Class of Asynchronous A/D Converters Based on Time Quantization
Synthesis of All-Digital Delay Lines
Technology mapping of timed circuits
Bringing Handshake Technology to the Open Market
Model-Checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits
Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication
Reconfigurable ASIC Implementation of Asynchronous Recurrent Neural Networks
Metastability Tolerant Computing
On Directed Transformations of Delay-Insensitive Specifications, Alternations and Dynamic Nondeterminism
An Efficient Data Structure for Sparse Bit-Vectors with Applications in Neuromorphic Computing
Congestion and Starvation Detection in Ripple FIFOs
A Cycle-Based Decomposition Method for Burst-Mode Asynchronous Controllers
SPA - A Synthesisable Amulet Core for Smartcard pplications
Synthesis from Waveform Transition Graphs
Membership Test Logic for Delay-Insensitive Codes
Building fast bundled data circuits with a specialized standard cell library
Relative liveness: from intuition to automated verification
25th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2019, Hirosaki, Japan, May 12-15, 2019
Efficient Self-Timed Interfaces for Crossing Clock Domains
Easy async for busy engineers: AFSM-based design of low-latency robust controllers in Workcraft *
20th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2014, Potsdam, Germany, May 12-14, 2014
CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder
A delay-controlled phase-locked loop to reduce timing errors in synchronous/asynchronous communication links
A 28nm Energy-efficient Asynchronous SNN Accelerator with On-chip Learning for Gas Recognition
Single-rail handshake circuits
Improving Dependability and Performance of Fully Asynchronous On-chip Networks
The Metastable Behavior of a Schmitt-Trigger
FLEETzero: An Asynchronous Switching Experiment
Analysis and Applications of the XDI model
Optimal and Heuristic Scheduling Algorithms for Asynchronous High-Level Synthesis
Optimising Bundled-Data Balsa Circuits
Utilising dynamic logic for low power consumption in asynchronous circuits
Concurrency-Enhancing Transformations for Asynchronous Behavioral Specifications: A Data-Driven Approach
Designing an Asynchronous Bus Interface
Asynchronous Nano-Electronics: Preliminary Investigation
Formal Deadlock Verification for Click Circuits
Analyzing Specifications for Delay-Insensitive Circuits
Data-Loop-Free Self-Timed Circuit Verification
NanoMesh: An Asynchronous Kilo-Core System-on-Chip
PID (Partial Inversion Data): An M-of-N Level-Encoded Transition Signaling Protocol for Asynchronous Global Communication
13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 12-14 March 2006, Berkeley, California, USA
A Configurable Asynchronous Pseudorandom Bit Sequence Generator
Muller C-Element for NEMS
7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA
Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects
Towards Asynchronous A-D Conversion
Verifying Timed, Asynchronous Circuits using ACL2
The AMULET2e cache system
On the Threat of Metastability in an Asynchronous Fault-Tolerant Clock Generation Scheme
Bottleneck Analysis and Alleviation in Pipelined Systems: A Fast Hierarchical Approach
Built-In Self-Testing of Micropipelines
Low-Latency Asynchronous FIFO's Using Token Rings
Clock Generator with Clock Domain Crossing
Distributed Locally Synchronous Grid Oscillator via Perpetual Token Exchange
A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits
A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure
Asynchronous Design and the Pursuit of Low Power
A Clock-Less Ultra-Low Power Bit-Serial LVDS Link for Address-Event Multi-chip Systems
The Eventual C-Element Theorem for Delay-Insensitive Asynchronous Circuits
4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA
Notes On Pulse Signaling
Naturalized Communication and Testing
Delay Insensitive Encoding and Power Analysis: A Balancing Act
MTBF Estimation in Coherent Clock Domains
Low Power Monolithic 3D IC Design of Asynchronous AES Core
An Instruction Buffer for a Low-Power DSP
Design of High-Performance Power-Aware Asynchronous Pipelined Circuits in MOS Current Mode Logic
Coping with Soft Errors in Asynchronous Burst-Mode Machines
Efficient Exact Two-Level Hazard-Free Logic Minimization
Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages
Tools for validating asynchronous digital circuits
Modeling and Verifying Circuits Using Generalized Relative Timing
The Design of a Genetic Muller C-Element
Loadable Kessels Counter
Timing Measurements of Synchronization Circuits
Behavior and Synthesis of Two-Input Gate Asynchronous Circuits
Optimal Technology Mapping and Cell Merger for Asynchronous Threshold Networks
An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism
Asynchronous, event-driven readout for large-scale imaging devices
Asynchronously Controlled Frequency Locked Loop
Non-Uniform Access Asynchronous Register Files
Adapting Asynchronous Circuits to Operating Conditions by Logic Parametrisation
Slack Matching Quasi Delay-Insensitive Circuits
Handshake Verification in WORKCRAFT
Composable specifications for asynchronous systems using UNITY
New CMOS VLSI linear self-timed architectures
Where are the Async Millionaires?
Ultra Low Power Booth Multiplier Using Asynchronous Logic
SAS: Source Asynchronous Signaling Protocol for Asynchronous Handshake Communication Free from Wire Delay Overhead
New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems
Post-Placement Timing Optimisations on Asynchronous Designs
On-Chip Structures for Timing Measurements and Test
Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines
Verification of Delayed-Reset Domino Circuits Using ATACS
GasP Control for Domino Circuits
On the correctness of the Sproull counterflow pipeline processor
Dynamic hazards and speed independent delay model
Low-Latency Contro Structures with Slack
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip
Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks
15th IEEE Symposium on Asynchronous Circuits and Systems, ASYNC 2009, Chapel Hill, NC, USA, May 17-20, 2009
Synthesis of Speed Independent Circuits Based on Decomposition
A Jitter Attenuating Timing Chain
A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems
Bolstering Faith in GasP Circuits through Formal Verification
An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm
Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers
An Asynchronous PRBS Error Checker for Testing High-Speed Self-Clocked Serial Links
A High-Speed Clockless Serial Link Transceiver
Squaring the FIFO in GasP
PALS: Plesiochronous and Locally Synchronous Systems
An Operand-Optimized Asynchronous IEEE 754 Double-Precision Floating-Point Adder
DD1: A QDI, Radiation-Hard-by-Design, Near-Threshold 18uW/MIPS Microcontroller in 40nm Bulk CMOS
Timing Driven Placement for Quasi Delay-Insensitive Circuits
Explaining Metastability in Real Synchronizers
A Low Power Zero-Overhead Self-Timed Division and Square Root Unit Combining a Single-Rail Static Circuit with a Dual-Rail Dynamic Circuit
Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs
Heterogeneous Latch-Based Asynchronous Pipelines
Self-timed Reinforcement Learning using Tsetlin Machine
A Transmission Line Enabled Deadlock Free Toroidal Network-on-Chip using Asynchronous Handshake Protocols
A Multi-Radix Approach to Asynchronous Division
A General Purpose Behavioural Asynchronous Synthesis System
Handshake Protocols for De-Synchronization
A Novel Power Delivery Method for Asynchronous Loads in Energy Harvesting Systems
Designing asynchronous circuits from behavioural specifications with internal conflicts
A Synthesis Toolflow for the Predictable Implementation of High-Performance Bundled-Data Asynchronous NoCs on FPGA
12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 13-15 March 2006, Grenoble, France
DVFS Based on Voltage Dithering and Clock Scheduling for GALS Systems
Long-Distance On-chip Communication Using GasP
Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis
Verification of Speed-Dependences in Single-Rail Handshake Circuits
Performance comparison of asynchronous adders
BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor
Metastability-Aware Memory-Efficient Time-to-Digital Converters
Synthesis and Timing Constraints for Reliable MTNCL Asynchronous Circuits
Slack Matching Asynchronous Designs
A 72-Port 10G Ethernet Switch/Router Using Quasi-Delay-Insensitive Asynchronous Design
Designing Self-timed Asynchronous Circuits with Chisel
14th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2008, Newcastle upon Tyne, UK, April 7-10, 2008
Accelerating Markovian Analysis of Asynchronous Systems using String- based State Compression
A Practical Framework for Specification, Verification, and Design of Self-Timed Pipelines
Sequencer circuits for VLSI programming
A Programmable Adaptive Router for a GALS Parallel System
A Single Chip Low Power Asynchronous Implementation of an FFT Algorithm for Space Applications
An asynchronous hybrid pixel image sensor
3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 7-10 April 1997, Eindhoven, The Netherlands
Asynchronous Design: An Enabler for Flexible Microelectronics
Formal Verification of Mixed Synchronous Asynchronous Systems Using Industrial Tools
Latency Improvement of an Industrial SoC System Interconnect using an Asynchronous NoC Backbone
Distributed Phase Correction Technique
23rd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2017, San Diego, CA, USA, May 21-24, 2017
Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction
Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis
Dynamic logic in four-phase micropipelines
Hiding Synchronization Delays in a GALS Processor Microarchitecture
Request-Driven GALS Technique for Wireless Communication System
Shared-Staticizer for Area-Efficient Asynchronous Circuits
Opportunistic Mutual Exclusion
Address-Event Communication Using Token-Ring Mutual Exclusion
Asynchronous DRAM Design and Synthesis
An Eight-Bit Divider Implemented in Asynchronous Pulse Logic
AMULET3i - An Asynchronous System-on-Chip
Action Systems in Pipelined Processor Design
Continuous-Time Digital Signal Processors
Synchronous Handshake Circuits
Reconditioning: Automatic Power Optimization of QDI Circuits
Micronets: a model for decentralising control in asynchronous processor architectures
More Accurate Polynomial-Time Min-Max Timing Simulation
Statistical Analysis and Optimization of Asynchronous Digital Circuits
Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits
Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model
Block-Level Relaxation for Timing-Robust Asynchronous Circuits Based on Eager Evaluation
A single-rail re-implementation of a DCC error detector using a generic standard-cell library
FPGA Implementation of an Asynchronous Processor with Both Online and Offline Testing Capabilities
The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver
The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core
Transistor Sizing: How to Control the Speed and Energy Consumption of a Circuit
Priority Arbiters
On-chip samplers for test and debug of asynchronous circuits
Bounded delay timing analysis of a class of CSP programs with choice
High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells
VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player
A FIFO Ring Performance Experiment
Using Metrics for Proof Rules for Recursively Defined Delay-insensitive Specifications
Case Study for Skewing MTNCL Circuits
Timing-reliability evaluation of asynchronous circuits based on different delay models
An efficient algorithm for deriving logic functions of asynchronous circuits
GasP: A Minimal FIFO Control
Two-Phase Asynchronous Pipeline Control
Retargeting a hardware compiler proof using protocol converters
An Automatic Approach to Generate Haste Code from Simulink Specifications
The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller
Test Margin and Yield in Bundled Data and Ring-Oscillator Based Designs
A High-Throughput Asynchronous Multi-resource Arbiter Using a Pipelined Assignment Approach
Effect of Dynamic Frequency Scaling on Interface Design for Rationally-Related Multi-clocked Systems
A Scalable Counterflow-Pipelined Asynchronous Radix-4 Booth Multiplier
Long Wires and Asynchronous Control
Chronos Link: A QDI Interconnect for Modern SoCs
On the Realisation of Delay-Insensitive Asynchronous Circuits with CMOS Ternary Logic
A Low-Power Self-Timed Viterbi Decoder
The Devolution of Synchronizers
Inverting Martin Synthesis for Verification
21st IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2015, Mountain View, CA, USA, May 4-6, 2015
Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis
High-performance asynchronous pipeline circuits
Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits
High-level test evaluation of asynchronous circuits
Predicting Performance of Micropipelines Using Charlie Diagrams
9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 12-16 May 2003, Vancouver, BC, Canada
Self-Timed Circuitry for Global Clocking
Asynchronous Communication Mechanisms Using Self-Timed Circuits
A Self-Timed Implementation of Boolean Functions
A Timing Verifier and Timing Profiler for Asynchronous Circuits
Formal design of an asynchronous DSP counterflow pipeline: a case study in handshake algebra
A Fast Hierarchical Approach to Resource Sharing in Pipelined Asynchronous Systems
An Investigation into the Security of Self-Timed Circuits
Optimization and Comparison of Synchronizers
Efficient FPGA Implementation of Time-Domain Popcount for Low-Complexity Machine Learning
Timing Closure in Relative Timed Asynchronous Designs using Deep Reinforcement Learning
Timed Signalling Processes
Yak: An Asynchronous Bundled Data Pipeline Description Language
Click Elements: An Implementation Style for Data-Driven Compilation
The Vortex: A Superscalar Asynchronous Processor
A Multiplexor Based Test Method for Self-Timed Circuits
Measuring Metastability with Free-Running Clocks
A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET
GALS Partitioning Methodology for Substrate Noise Reduction in Mixed-Signal Integrated Circuits
A Fast, asP*, RGD Arbiter
Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology
MTBF Bounds for Multistage Synchronizers
Verification-Driven Design for Asynchronous VLSI
Efficient Metastability-Containing Gray Code 2-Sort
Multiple-Rail Phase-Encoding for NoC
Two-Phase Asynchronous Wave-Pipelines and Their Application to a 2D-DCT
From STG to Extended-Burst-Mode Machines
Interface Design for Rationally Clocked GALS Systems
AMULET2e: An Asynchronous Embedded Controller
Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters
Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications
An Asynchronous Router for Multiple Service Levels Networks on Chip
An Asynchronous 2-D Discrete Cosine Transform Chip
Complete state encoding based on the theory of regions
Formal Verification of C-element Circuits
Cyclone: A Static Timing and Power Engine for Asynchronous Circuits
Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow
Design and Verification of Speed-Independent Circuits with Arbitration in Workcraft
A Practical Comparison of Asynchronous Design Styles
Statistical Static Timing Analysis of Conditional Asynchronous Circuits Using Model-Based Simulation
Designing Fast Asynchronous Circuits
High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism
A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits
Testing C-elements is not elementary
Adding Synchronous and LSSD Modes to Asynchronous Circuits
Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic
A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines
Delay-insensitive solutions to the committee problem
SNAP: A Sensor-Network Asynchronous Processor
18th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2012, Kgs. Lyngby, Denmark, May 7-9, 2012
Measuring Deep Metastability
Efficient Timing Analysis Algorithms for Timed State Space Exploration
Performance evaluation of asynchronous logic pipelines with data dependent processing delays
Timed Trace Theoretic Verification Using Partial Order Reduction
Coarse Grained versus Fine Grained Architectures for Asynchronous Reconfigurable Devices
Flexible Compilation and Refinement of Asynchronous Circuits
Adapting Synchronizers to the Effects of on Chip Variability
A Delay-Insensitive Address-Event Link
Allocation and scheduling of relief materials based on GIS
Reclamation impact on coastal topography in Sheyang estuary
A method based on spatial analyst to detect hot spot of urban component management events
Development of three dimensional digital tourism presentation system based on Google Earth API
Predicting migration system dynamics with conditional and posterior probabilities
Study of the extension to BPEL4Grid for grid service composition
An algorithm for clustering spatial lines based on connectivity for GML data
The application of Transient Electromagnetic Method in detection of coal mine goaf
QuCOM: K nearest features neighborhood based qualitative spatial co-location patterns mining algorithm