yusuke1997/dblp-id-title huggingface dataset:
Randomizing task placement does not randomize traffic (enough)
DynaVLC - Towards Dynamic GTS Allocation in VLC Networks (Invited Paper)
Using Dynamic Binary Instrumentation to Generate Multi-platform SimPoints: Methodology and Accuracy
Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, RAPIDO@HiPEAC 2015, 21 January, 2015, Amsterdam, The Netherlands
Fine-Grained Link Locking Within Power and Latency Transaction Level Modelling in Wormhole Switching Non-Preemptive Networks On Chip
Software-defined board- and chip-level optical interconnects for multi-socket communication and disaggregated computing
High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings
Directly characterizing cross core interference through contention synthesis
Accelerating XML Query Matching through Custom Stack Generation on FPGAs
Stack size estimation on machine-independent intermediate code for OpenCL kernels
Supercomputing for the Future, Supercomputing from the Past (Keynote)
Moore's law implications on energy reduction
Fetch Gating Control Through Speculative Instruction Window Weighting
Proceedings of the 3rd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS 2018, Manchester, United Kingdom, January 22-22, 2018
StatTask: reuse distance analysis for task-based applications
PhoenixSim: Crosslayer Design and Modeling of Silicon Photonic Interconnects
Design space exploration for complex automotive applications: an engine control system case study
A new Definition and Classification of Physical Unclonable Functions
The Significance of Affectors and Affectees Correlations for Branch Prediction
SP-IMPact: A Framework for Static Partitioning Interference Mitigation and Performance Analysis
Split Register Allocation: Linear Complexity Without the Performance Penalty
Detecting positive voltage attacks on CMOS circuits
Variation-Aware Software Techniques for Cache Leakage Reduction Using Value-Dependence of SRAM Leakage Due to Within-Die Process Variation
Adaptive Energy Minimization of OpenMP Parallel Applications on Many-Core Systems
TrustZone-backed bitcoin wallet
Fast Instruction Cache Simulation is Trickier than You Think
12th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and 10th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2021, Budapest, Hungary, January 19, 2021
Runtime resource management for embedded and HPC systems
A Cautionary Note: Side-Channel Leakage Implications of Deterministic Signature Schemes
Event-Based Control Enters the Real-Time World: Perspectives and Pitfalls
Mode-based Obfuscation using Control-Flow Modifications
Drug Design Issues on the Cell BE
AEGIS-Based Efficient Solution for Secure Reconfiguration of FPGAs
Buffer Sizing for Self-timed Stream Programs on Heterogeneous Distributed Memory Multiprocessors
Accomodating Diversity in CMPs with Heterogeneous Frequencies
Replacement policies for shared caches on symmetric multicores: a programmer-centric point of view
Memory-Centric Security Architecture
Collective Optimization
Recent Processor Technologies and Co-Scheduling
Terrible Twins: A Simple Scheme to Avoid Bad Co-Schedules
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions
Co-Scheduling of HPC Applications [extended versions of all papers from COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016]
Distributed MILS (D-MILS) Specification, Analysis, Deployment, and Assurance of Distributed Critical Systems
High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings
EDF Scheduling and Minimal-Overlap Shortest-Path Routing for Real-Time TSCH Networks
High-Speed Optical Cache Memory as Single-Level Shared Cache in Chip-Multiprocessor Architectures
Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC 2020, Bologna, Italy, January 21, 2020
DroneSE and RAPIDO '21: Methods and Tools, Budapest, Hungary, January 18, 2021
M2OS-Mc: An RTOS for Many-Core Processors
Parallel LDPC Decoding on the Cell/B.E. Processor
An accurate simulation framework for thermal explorations and optimizations
Run-Time Power Modelling in Embedded GPUs with Dynamic Voltage and Frequency Scaling
Current Trends and Solutions in Securing Automotive Software
Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks
Developing Assurance Cases for D-MILS Systems
Tagged Procedure Calls ( TPC ): Efficient Runtime Support for Task-Based Parallelism on the Cell Processor
Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array
MPSoC Design Using Application-Specific Architecturally Visible Communication
Foreword / Workshop Description
An approach to Separation of Duties validation for MILS security configurations
Proceedings of the 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 4th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2015, Amsterdam, Netherlands, January 21, 2015
High throughput data redundancy removal algorithm with scalable performance
Sixth Workshop on Next Generation Real-Time Embedded Systems, NG-RES 2025, Barcelona, Spain, January 20, 2025
Evaluation of the Parallel Features of Rust for Space Systems
Integrated Modulo Scheduling for Clustered VLIW Architectures
Security Type Checking for MILS-AADL Specifications
The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges
A stream-computing extension to OpenMP
An Analytical Model of Configurable Systolic Arrays to find the Best-Fitting Accelerator for a given DNN Workload
International Workshop on MILS: Architecture and Assurance for Secure Systems, MILS 2017, Nürnberg, Germany, March 14, 2017
Cybersecurity in the Railway Sector
Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation
A survey of low power NoC design techniques
Interest of MIA in frequency domain?
Towards attacks on restricted memory areas through co-processors in embedded multi-OS environments via malicious firmware injection
Monolithic Optical Interconnects in Zero-Change CMOS
A Low Energy FPGA Platform for Real-Time Event-Based Control
Stretching the limits of Programmable Embedded Devices for Public-key Cryptography
Exploring the Vulnerability of R-LWE Encryption to Fault Attacks
Experiences with Parallelizing a Bio-informatics Program on the Cell BE
All routes to efficient datacenter fabrics
Second Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC 2021, Budapest, Hungary, January 20, 2021
Large scale characterization of SRAM on infineon XMC microcontrollers as PUF
Integrated Vivaldi antennas, an enabling technology for optical wireless networks on chip
The Security for Safety Problem in Cyberphysical Systems
Datapath Optimization for Embedded Signal Processing Architectures utilizing Design Space Exploration
Implications of Process-Migration in Virtualized Environments
Co-scheduling on Upcoming Many-Core Architectures
Scalable Shared-Cache Management by Containing Thrashing Workloads
Asset-Centric Security Risk Assessment of Software Components
Branch History Matching: Branch Predictor Warmup for Sampled Simulation
A Low-Power DSP-Enhanced 32-Bit EISC Processor
Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors
An Architecture-Centric Process for MILS Development
Node Sharing for Increased Throughput and Shorter Runtimes - an Industrial Co-Scheduling Case Study
A cycle-accurate synthesizable MIPS simulator in Simulink
13th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 11th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2022, Budapest, Hungary, June 22, 2022
Channel Allocation Protocol for Reconfigurable Optical Network-on-Chip
Proceedings of the 8th International Workshop on Interconnection Network Architecture - On-Chip, Multi-Chip, INA-OCMC 2014, Vienna, Austria, January 22, 2014
Heterogeneous network design for effective support of invalidation-based coherency protocols
Towards a Lightweight RDMA Para-Virtualization for HPC
Modeling Information Routing with Noninterference
Sequential and Parallel Code Sections are Different: they may require different Processors
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
A Software-defined SoC Memory Bus Bridge Architecture for Disaggregated Computing
Complementing Missing and Inaccurate Profiling Using a Minimum Cost Circulation Algorithm
A Parallel Gauss-Seidel Algorithm on a 3D Torus Network-on-Chip Architecture
Virtual prototyping of floating point units
H-MBR: Hypervisor-Level Memory Bandwidth Reservation for Mixed Criticality Systems
Third Workshop on Next Generation Real-Time Embedded Systems, NG-RES@HiPEAC 2022, Budapest, Hungary, June 22, 2022
Maestro: Orchestrating Lifetime Reliability in Chip Multiprocessors
Compiler-Assisted Memory Encryption for Embedded Processors
Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems
Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS
Proceedings of the Fifth Workshop on Cryptography and Security in Computing Systems, CS2 2018, Manchester, United Kingdom, January 24, 2018
Characterization and cost-efficient selection of NoC topologies for general purpose CMPs
PetaBricks: a language and compiler based on autotuning
Formal Methods for MILS: Formalisations of the GWV Firewall
Hardware enforced separation in embedded multicore SoCs
Ahead-Of-Real-Time (ART): A Methodology for Static Reduction of Worst-Case Execution Time
Proceedings of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2018, Manchester, United Kingdom, January 23-23, 2018
System Simulation for Autonomous UAV Design
Entropy-Based Analysis of Benchmarks for Instruction Set Simulators
High-End Security Features for Low-End Microcontrollers
16th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 14th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2025, Barcelona, Spain, January 22, 2025
Fifth Workshop on Next Generation Real-Time Embedded Systems, NG-RES 2024, Munich, Germany, January 17-19, 2024
Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2017, Stockholm, Sweden, January 25, 2017
Adjacent LSTM-Based Page Scheduling for Hybrid DRAM/NVM Memory Systems
Real-Time Task Migration for Dynamic Resource Management in Many-Core Systems
Parallel points-to analysis for multi-core machines
Coffee: COmpiler Framework for Energy-Aware Exploration
Practical Aspects of Quantization and Tamper-Sensitivity for Physically Obfuscated Keys
PRO3D: programming for future 3D manycore architectures
Towards an Ontological Methodology for Dynamic Dependability Management of Unmanned Aerial Vehicles
Microserver + micro-switch = micro-datacenter
Arc3D: A 3D Obfuscation Architecture
Non-Intrusive Runtime Monitoring for Manycore Prototypes
Interconnects for next generation SoC designs
Offload - Automating Code Migration to Heterogeneous Multicore Systems
Proceedings of the 1st COSH Workshop on Co-Scheduling of HPC Applications, COSH@HiPEAC 2016, Prague, Czech Republic, January 19, 2016
Flexible resource allocation and management for application graphs on ReNÉ MPSoC
Filtering-based CPA: a successful side-channel attack against desynchronization countermeasures
DroneSE and RAPIDO '22: System Engineering for constrained embedded systems, Budapest Hungary, January 17 - 19, 2022
Cache equalizer: a placement mechanism for chip multiprocessor distributed shared caches
On the performance of freescale i.MX6 cryptographic acceleration and assurance module
Proceedings of the Fourth Workshop on Cryptography and Security in Computing Systems, CS2@HiPEAC 2017, Stockholm, Sweden, January 24, 2017
Low-cost fault-tolerant switch allocator for network-on-chip routers
SWEEP: evaluating computer system energy efficiency using synthetic workloads
Performance implications of remote-only load balancing under adversarial traffic in Dragonflies
Ninth International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC@HiPEAC 2015, Amsterdam, Netherlands, January 19, 2015
Instruction Set Extension Generation with Considering Physical Constraints
Fault-Tolerant Online Scheduling Algorithms for CubeSats
ReconfROS: Running ROS on Reconfigurable SoCs
Optimizing built-in pseudo-random self-testing for network-on-chip switches
Placement Security Analysis for Side-Channel Resistant Dual-Rail Scheme in FPGA
A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management
Can We Trust AI-Powered Real-Time Embedded Systems? (Invited Paper)
Extending a Run-time Resource Management framework to support OpenCL and Heterogeneous Systems
Buffered deflection routing for networks-on-chip
Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling
Adaptive routing framework for network on chip architectures
Improving Performance by Reducing Aborts in Hardware Transactional Memory
Revisiting Cache Block Superloading
System-Level Timing Performance Estimation Based on a Unifying HW/SW Performance Metric
Just-In-Time Composition of Reconfigurable Overlays (Invited Talk)
Proceedings of the Second Workshop on Cryptography and Security in Computing Systems, CS2@HiPEAC 2015, Amsterdam, Netherlands, January 19-21, 2015
Allocation-Internal Co-Scheduling - Interaction and Orchestration of Multiple Concurrent MPI Sessions
Simultaneous mutual localization of transmitters and receivers from time difference of arrival measurements
Speaker Recognition from Distance Using X-Vectors with Reverberation-Robust Features
Style Transfer for Detecting Vehicles with Thermal Camera
Comparison of ANN and CNN models for misfire detection in vehicle engine at different RPMs with low-cost ADXL1002 accelerometer
Automatic detection of SSVEP using independent component analysis
Selection and tests of lossless and lossy video codecs for advanced driver-assistance systems
Deep Learning for Natural Language Processing and Language Modelling
Elimination of distortions in the recorded sound of the violin using cascade-integrator-comb filters based on Gabor transform and pitch-shifting algorithm
Gaussian 2D IIR filters with multiple orientation
Tangled Program Graphs as an alternative to DRL-based control algorithms for UAVs
Observability coefficient for 2D dynamical systems
A new Android application for blind and visually impaired people
Vision for Vision - Deep Learning in Retinal Image Analysis
Determination of the Vehicles Speed Using Acoustic Vector Sensor
Issue Based OCR Error Prediction in Video Streams
Vehicle detection with image conversion into point representation
Detection and Classification of Cardiovascular Diseases Using Neural Networks
Geospatial Coverage and Signal Quality Measurements of Terrestrial DAB+ Network in Northern Poland
Automated Classification of VMT Pathology from Optical Coherence Tomography B-scans
CCTV based system for detection of anti-virus masks
Radio transmission masking on the example of FSK modulation
Detecting the Number of Speakers in Speech Mixtures by Human and Machine
Energy Band Analysis for Screening Patients Diagnosed with ALS
Accuracy and cross-sensitivity analysis of the PMS5003 formaldehyde sensor
Adjusting automatically marked voiced English allophone borders
Analysis of fast prototyping of microcontroller-based ML software for acoustic signal classification
Clutter reflection suppression algorithm in synthetic-aperture radar
Vision system for automatic recognition of Polish historic vehicles
AI-Supported Pneumonia Diagnosis: Performance of Deep Learning Models and Synthetic Data Generation
Real and Virtual Instruments in Machine Learning -Training and Comparison of Classification Results
Graph Neural Networks for Natural Language Processing in Human-Robot Interaction
A hybrid relaying protocol for wireless cooperative networks based on the log-likelihood ratio
Design and implementation of multi - Touch Tujia brocade virtual weaving system
On Using Quaternionic Rotations for Indpendent Component Analysis
HDR tonal mapping algorithm for mobile devices
Estimation of singing voice types based on voice parameters analysis
Memory-Efficient Graph Convolutional Networks for Object Classification and Detection with Event Cameras
A Survey on Machine Learning Approaches to ECG Processing
Complexity reduced turbo differential decoding based on layered LDPC decoding
Switched-capacitor finite impulse response rotator filter
Analytic Design of Uniform Circular Filter Banks
Test signals used in electroacoustics and speech technology
Analytics of air samples collected with an apparatus coupled to UAV in air quality monitoring
Dictionary-based through-plane interpolation of prostate cancer T2-weighted MR images
Canonic Goertzel algorithm and drawbacks of various Goertzel algorithm formulations
Signal Processing: Algorithms, Architectures, Arrangements, and Applications, SPA 2024, Poznan, Poland, September 25-27, 2024
Marking the Allophones Boundaries Based on the DTW Algorithm
Texture analysis of 2D spatial distribution of blood pharmacokinetic model parameters for endometrial carcinoma classification
Crowd counting using complex convolutional neural network
Prototypical Networks for Remote Sensing Scene Classification : Episodic Versus Classical Training
Classification of emotions from speech signal
Interactive sonification of images on mobile devices for the visually impaired
Signal Processing: Algorithms, Architectures, Arrangements, and Applications SPA 2022, Poznan, Poland, September 21-22, 2022
Vehicle detector training with labels derived from background subtraction algorithms in video surveillance
Algorithm for Human Fall Detection Based on Acceleration Measurement
Voice pathologies identification speech signals, features and classifiers evaluation
Hybrid Voice Spectrogram-Chromogram Based Deep Learning (HVSC-DL) Model for the Detection of Parkinson's Disease
A critique of some rough approximations of the DCT
Methods of Enriching The Flow of Information in The Real-Time Semantic Segmentation Using Deep Neural Networks
Non-fiducial based ECG biometric authentication using one-class Support Vector Machine
Active tone elimination algorithm using FFT with interpolation and zero-padding
MRI image reconstruction approach for partial K-space based on the Discrete Fourier Transform in the least square sense
Optimized Cluster Head Placement for Minimize Energy Consumption in Transmit-Only Wireless Sensor Networks
Automated Audio Time Alignment for Multi-Microphone Setups: An Open-Source Approach
Segmentation of Retina Vessels in 2D OCT-Reconstructed Fundus Images with 3D UNet
Towards sensor position-invariant hand gesture recognition using a mechanomyographic interface
Synthetic Image Generation With a Fine-Tuned Latent Diffusion Model for Organ on Chip Cell Image Classification
Determining the stroke volume of the artificial ventricle using the numerical integration method
Gentle Adaboost algorithm for weld defect classification
DIAST variability illuminated thermal and visible ear images datasets
Ontology based expert system for Barley grain classification
An enhancement of software metrics as failure predictors
Improved pedestrian detection by adjustment of segmented ROI in thermal night vision
Exploiting FPGA Capabilities for Accelerated Biomedical Computing
Application of demons image registration algorithms in resected breast cancer lodge localization
SMART4ALL Open Calls, the right funding instrument to boost technology and business development in South, East and Central Europe
A Multiple Layer Security Scheme Utilizing Information Matrices
HDR Image Tone Mapping Approach based on Near Optimal Separable Adaptive Lifting Scheme
Efficient HDR tone-mapping for ADAS applications
Deep learning for face anti-spoofing: An end-to-end approach
Active elimination of tonal components in acoustic signals
Low-level audio descriptors-based analysis of music mixes from different Digital Audio Workstations - case study
Foreign Object Debris detection at aerodromes using YOLOv5
Weighted Robust Sage-Husa Adaptive Kalman Filtering for Angular Velocity Estimation
Approach to local contrast enhancement
Contemporary technologies and techniques for processing of human eye images
Image and video processing with tensor methods
Objective assessement of equalization methods using acoustic parameters
Embedded system for acquisition and enhancement of audio signals
Pedestrian detection in low resolution night vision images
Adaptive edge-based stereo block matching algorithm for a mobile Graphics Processing Unit
Stationary environment models for Advanced Driver Assistance Systems
Audio/speech coding using the matching pursuit with frame-based psychoacoustic optimized time-frequency dictionaries and its performance evaluation
Algorithm of DFT leakage minimization by using optimization methods
Efficient pedestrian detection with enhanced object segmentation in far IR night vision
Understanding aesthetics in photography using deep convolutional neural networks
Robotic Manipulation of Elongated and Elastic Objects
Speaker verification with TIMIT corpus - some remarks on classical methods
An application of acoustic sensors for the monitoring of road traffic
Sound Analysis of Drop Characteristics by Evaluation of Impact on Water Pool
A cardinal-based algorithm for automatically roaming in virtual scene
Implementation of an advanced lung nodule classification system using optimized ConvMixer and AdamW-based CNN architecture
A novel objective function based on a generalized kelly criterion for deep learning
CRF-Based Clustering of Pharmacokinetic Curves from Dynamic Contrast-Enhanced MR Images
Machine Learning for sEMG Facial Feature Characterization
Analysis of myocardial texture in resting echocardiographic images predicts recovery one year after myocardial infarction
Stereoscopic Image Coding Using a Global Disparity Estimation Algorithm Optimizing the Compensation Scheme Impact
Application of recurrent U-net architecture to speech enhancement
Feature matching and ArUco markers application in mobile eye tracking studies
Classification of basic footwork in fencing using accelerometer
Image Encryption Based on Chen Chaotic System, OpenSSL S-Box and the Fibonacci Q-Matrix
Implementation aspects of speaker recognition using Python language and Raspberry Pi platform
On using tensors in the areas of circuit theory, signal processing, and telecommunications
A novel inverted index file based searching strategy for video copy detection
Multichannel Wiener Filter with Early Reflection Raking for Automatic Speech Recognition in Presence of Reverberation
Multithreaded Java approach to speaker recognition
Image Completion with Filtered Alternating Least Squares Tucker Decomposition
Full Duplex Relaying with Co-Channel Interference and Channel Estimation Error
Accurate robust nonlinear surface registration with simultaneous point cloud and triangular mesh representation
A Novel Quasi-Spherical Nested Microphone Array and Multiresolution Modified SRP by GammaTone Filterbank for Multiple Speakers Localization
Delay Estimation for Time Synchronization of a Bistatic Transfer Function Measurement Setup to Single Received Pulses
Migrating Electronic Systems from Fault Tolerant Computing to Error Resilience
A study on signal processing methods applied to hearing aids
Spatial Transformations in Deep Neural Networks