yusuke1997/dblp-id-title huggingface dataset:
Optimization of a piezoelectric energy harvester for environmental broadband vibrations
A 6 GHz low-noise quadrature Colpitts VCO
Fused modulo 2 n - 1 add-multiply unit
Workcell concatenation using wifi-based Wireless Networked Control Systems
RF-LNA circuit synthesis by genetic algorithm-specified artificial neural network
Multi-correlator based multipath mitigation technique for a GPS receiver
Pitch and formants extraction algorithm for speech processing
A 2.4GHz IEEE 802.15.6 Compliant 1.52nJ/bit TX & 1.32nJ/bit RX Multiband Transceiver for Low Power Standards
Efficient implementation of embedded zero-tree wavelet encoding
Resistorless tuneable KHN-filter in current mode with CCCIIs and grounded capacitors
A MEMS low-IF IQ-mixer in metal MUMPs: Modelling and simulation
A Memristor-CMOS Braun Multiplier Array for Arithmetic Pipelining
Computer-aided design of a mass production circuit
A 4 GHz CMOS multiple modulus prescaler
Linear and nonlinear crosstalk in MIMO OFDM transceivers
A fuel cell-based hybrid power supply for portable electronics devices
Configurable pulse routing architecture for accelerated multi-node neuromorphic systems
Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2003, Sharjah, United Arab Emirates, December 14-17, 2003
Efficient LDPC codes for joint source-channel coding
Deterministic maximum likelihood method for the localization of near-field sources: algorithm and performance analysis
Innovative current sensitive differential low noise preamplifier in CMOS
New impulse sampled IIR switched-capacitor interpolators
A 10 Gsamples/s SiGe Track-and-Hold Amplifier with 8-bit Resolution
A true logarithmic analog-to-digital pipeline converter with 1.5 bit/stage and digital correction
A novel frequency compensation scheme for on-chip low-dropout voltage regulators
Psychophysiological Approach for Measuring Social Presence in A Team-Based Activity: A Comparison Between Real and Virtual Environments
Structure optimization for efficient AlN piezoelectric energy harvesters
Contact and Slippage Detection Algorithm using a Soft PVDF-based Sensing System
On complex non-linear systems with symmetries: controllability preserving decomposition
A 65 nm CMOS - Stacked Folded Fully Differential (SFFD) PA structure for W-CDMA application
A self-disable sense technique with differential NAND cell for content-addressable memories
Design and FPGA Implementation of UAV Simulator for Fast Prototyping
A closed-form energy model for VLSI circuits under wide voltage scaling
Support Vector Machine for Internet Traffic Identification
Interferer performance dependency on analog-digital-conversion of GNSS-class signals in GPS receivers
Performance evaluation for a new implementation of multirate optical fast frequency hopping CDMA system for multimedia transmission
Design of a wideband CMOS LNA for low frequency band SKA application
Synthesis of companding systems by component to component substitution: an alternative method
An improved comparison circuit for low power pre-computation-based content-addressable memory designs
Architectural Trade-Offs in the Design of High-Speed PAM-3 Wireline Transmitters
A low power and high performance core for planar object overlaying
Design of a Hardware-Efficient Accumulator for Applications with Large Guard Bit Requirements
Adaptive ZCDPLL for QPSK detection
Using multiple attractor chaotic systems for communication
A new variable length LMS algorithm: theoretical analysis and implementations
Tighter WCET analysis of input dependent programs with classified-cache memory architecture
Computer aided design using CGH of a three-dimensional objects
Using Neural Networks for Optimum band selection in Cognitive-Radio Systems
Offset reduction on memristor emulator circuits
High-Precision Biomagnetic Measurement System Based on Tunnel Magneto-Resistive Effect
Design of IoT Microchip AVR Programmer for FOTA Updates based on Unified Programming and Debug Interface using Wi-Fi and LoRa
Capacitance to frequency converter suitable for sensor applications using telemetry
A low-power high-speed charge-steering ADC-based equalizer for serial links
A 4GHz CMOS 130 nm IR-UWB dual front-end transceiver for IEEE802.15 standards
Maximizing the fundamental period of a dithered digital delta-sigma modulator with constant input
VLSI design approach of complex motor control, case of direct torque control of AC machine
Dynamic power management in an AMBA-based battery-powered system
Fully integrated rectification and bin-integration analog circuit for biomedical signal processing
Second order current mode circuits based on the general current conveyor
Accurate current mirror with high output impedance
A greedy algorithm for wire length optimization
A Segmented Analog Calibration Scheme for Low-Power Multi-Bit Pipeline ADCs
Reconfigurable Linear Amplifier for Envelope-Tracking Hybrid Supply Modulator
A novel pixel topology for on-the-fly programmable image processing
A constraint-driven methodology for placement of analog and mixed-signal integrated circuits
A True Full-Duplex IO for High-Density High-Speed Interconnects
An affordable implantable VNS for use in animal research
Modeling and analysis of through silicon via: Electromagnetic and device simulation approach
Estimation of Displacement Vector Field from Noisy Data using Maximum Likelihood Estimator
8-GHz Low-Power Voltage-Mode Second-Order Allpass Filter in 65-nm CMOS
Efficient post-layout timing verification via RLC trees and explicit PWL timing integration
An All-Digital Clock Frequency Caputring Circuitry For NRZ Data Communications
Decentralized clustering in VANET using adaptive resonance theory
Optimized Design of a Digital IQ Demodulator Suitable for Adaptive Predistortion of 3rd Generation Base Station PAs
A repeater timing model and insertion algorithm to reduce delay in RC tree structures
Design of a generic and high performance CMOS burst mode laser driver
An ultra-low-voltage, semi-floating-gate, domino, dual-rail, NOR gate
CMOS BDJ detector array with charge preamplifiers for sensitive biochemical analysis
3D power grid modeling
Coherence modulation of light for mathematical operations
A Low-Power and Low Silicon Area Testable CMOS LNA Dedicated to 802.15.4 Sensor Network Applications
ADISI- An efficient tool for the automatic design of integrated spiral inductors
Organic memristive devices: Architecture, properties and applications in neuromorphic networks
A fully integrated MOS-C current-mode IF filter for Bluetooth
CBSC-based pipelined analog-to-digital converters: Power dissipation bound analysis
MMSE based single user timing acquisition in CDMA
Embedded software implementation of an adaptive baseband predistorter
Secure scan chain using test port for tester authentication
A 11.3-ppm/°C, Two Temperature Points Trimmed Current Generator for Precise RC Oscillators
Multi-electrode system for pacemaker applications
Implementation of a combined high-speed interpolation and decimation wave digital filter
High-performance bivariate numeric function approximation for hardware-efficient QR-decomposition
A new compensation technique for two-stage CMOS operational transconductance amplifiers
Skin-based adaptive background subtraction for hand gesture segmentation
A 0.35 μm CMOS DCS front-end with fully integrated VCO
Reduced Model Size Deep Convolutional Neural Networks for Small-Footprint Keyword Spotting
Determination of circuit topology and element values from desired characteristics by machine learning
Equivalence checking of hierarchical combinational circuits
Modeling of Saturable Inductors for Application in DC-DC Converters
Low Power 38-GHz UWB Tunable LNA Design Using SiP Technology
A Real-time Control System for Home/Office appliances automation, from mobile device through GPRS network
SiGe Power Amplifier Module for 5G FR2 Beamforming
Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options
Quantitative Assessment of Extensor Carpi Radialis Muscle Thickness Change Using the Pulse-Echo Method
An optimal reordering schema of homotopy equations for the analysis of nonlinear resistive circuits
Investigations of on-line/off-line tests for sensors
Low-power hardware implementation of SNN with decision block for recognition tasks
Dynamic Mapping for Many-cores using Management Application Organization
Devil's staircases, quasiperiodicity and chaos in a driven nonlinear fourth-order electric circuit
Asynchronous logic design with subcells with an application for space
A 1.4 GHz/2.7 V programmable frequency divider for DRRS standard in 0.6 μm CMOS process
Determination of run-length smoothing values for document segmentation
Analysis of ADMM-LP algorithm for LDPC decoding, a first step to hardware implementation
Scalable low cost architecture for analysis of Lab-on-Chip data
Technology-agnostic power optimization for AES block cipher
Low-IF 5 GHz WLAN linearized transmitter using baseband digital predistorter
Bit-level architectures for Montgomery's multiplication
Power scalable implementation of Artificial Neural Networks
Simscape and LTspice models of HP ideal generic memristor based on finite closed form solution for window functions
Unbalanced FIFO sorting for FPGA-based systems
SOI SRAM design advances & considerations
A multi-GOPS SIMD core for systematic signal processing
An effective procedure for multi-tone steady-state analysis of mixers
A low power 0.13µm ADC for drift chambers
The simple RS232 hub to interface microcontroller peripheral devices with the central processor
On orthogonal parallel realization for adaptive IIR filters
Classification of hand bones for bone age assessment
Current Bleeder-Based Mixer with -8.4 dB FoM, 10 dB NF, 18.5 dB Conversion Gain at 4.6 GHz
Spline nonlinear adaptive filter with cross-terms
Shift-add neural architecture
Dual-edge triggered sense amplifier flip-flop utilizing an improved scheme to reduce area, power, and complexity
Improved procedures for testing analog and mixed-signal systems using a microcontroller
Craig representation of the product of two Gaussian Q functions and its application
Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughput
High data rate synchronizers operating at low speed
Current mode AB class WTA circuit
Accelerating electromagnetic simulations: A hardware emulation approach
A fast scheme and implementation for n-bit squarer
Harmonic distortion in switched current cells due to settling error
Cascaded coefficient number systems lead to FIR filters of striking computational efficiency
VLSI implementation of password (PIN) authentication unit
Modeling micromelodic effects in standard Arabic using MOMEL
Experimental results of an optimised voltage tripler
Ontology-based forensic analysis of mobile devices
CAR: On the highway towards de-synchronization
Electrical Bio-Stimulation, Practical Safety for Circuits in Clinical Use
An observer performance study of the effect of using the body contour in reconstructing cardiac SPECT images from truncated projection data
Grand challenges in spatial-temporal computing on image flows
A 1.8 V low-power CMOS high-speed four quadrant multiplier with rail-to-rail differential input
Mathematical programming and resistor transformer diode networks
Design and analysis of memristor-based min-max circuit
A current mode maximum winner-take-all circuit with low voltage requirement for min-sum analog iterative decoders
The Effect of Stator Resistance Variation on DTFC of Induction Motor and its Compensation
Integrated recursive least square lattice and neuro-fuzzy modules for mobile multi-sensor data fusion
A 3μW 500 kb/s ultra low power analog decoder with digital I/O in 65 nm CMOS
Full-custom VLSI design of a new high-speed modular adder structures
Comparison of large-signal behavior of control schemes for high-output voltage modular DC-DC converters
On the trade-off between resolution time and delay times in bistable circuits
A Low Phase Noise Fractional-N PLL for mmWave Telecom and RADAR Applications
Performance and ExIT chart analysis of BICM-ID for physical layer network coding
A 900 MHz Multiphase LC Oscillator with Sinusoidal Outputs in SiGe Technology
Ultra-low distortion linearized pseudo-RC low-pass filter
Speech compression with wavelet packets
Quaternion Gated Recurrent Units for Renewable Energy: Improving Power Forecasting
New architectures for modulo 2N - 1 adders
A Fast Switchable and Band-Tunable 5-7.5 GHz LNA in 45 nm CMOS SOI Technology for Multi-Standard Wake-up Radios
A high-speed, current-steering digital-to-analog converter in 0.6-μm CMOS
Content-based video sequence editing: a client-server Java system for user-assisted segmentation
Distributed RLC Interconnect: Analytical Modelling Expressions for Crosstalk Noise Estimation
A dynamic thermal management circuit for system-on-chip designs
Delay-lines jitter modeling and efficiency analysis in FinFET technology
Design of the Microstrip Antennas λ/8 for Wireless Communications "by TLM Model"
Variable Length Quantization based Design of Polar Codes Decoder for Resource-Limited IoT Devices
A 11b 5.1µW multi-slope ADC with a TDC using multi-phase clock signals
An instrument with a DSP for monitoring human biological parameters
Amplify and forward relaying optimization for uplink CDMA communications subject to constant multiple access interference cost
10W Power Amplifier Design for sub-6GHz 5G Band via Virtual Gain Optimization
A bandgap voltage reference using digital CMOS process
Tutorial 1: Lab-on-a-chip based on CMOS technology: Parts, applications, challenges and future trends
Residue signed-digit arithmetic circuit with a complement of modulus and the application to RSA encryption processor
A Lightweight Full Homomorphic Encryption Scheme on Fully-connected Layer for CNN Hardware Accelerator achieving Security Inference
Hardware Mitigation and Verification For Rogue In-Flight Data Load Attacks
A New Blind Image Watermarking Technique for Dual Watermarks Using Low-Frequency Band DCT Coefficients
High PSR output-capacitor-less LDO with double buffers technique
Performance study of nonlinearities blind correction in wideband receivers
Towards an automatic path from Java TM bytecodes to hardware through high-level synthesis
Analog CMOS implementation of feature detection operators for automatic real-time optical character recognition systems
State-Space Modeling of a Novel 2-output, single-L Driver for PZT Actuators with Charge Recovery
On-chip synchronous detection for CMOS photodetector
Lossless compression of bathymetric data using an improved nonlinear discrete wavelet transform
Trends in reconfigurable logic and reconfigurable computing
New CMOS universal constant-Gm input stage
Coefficient, Pass and Code-Block Parallel Architecture for FBP Coding in JPEG2000
Application of the superregenerative principle to UWB pulse generation and reception
Software BIST capabilities of a symmetric cipher
Electrical characterization and modeling of thin-film humidity sensors
Hybrid Memristor-CMOS Based Up-Down Counter Design
Estimation of line parameters using SLIDE algorithm and TF representations
Design of a digital pixel image sensor array with adaptive quantization and pseudo Huffman coding
Discrete Time Analysis of Phase Detector Timing Nonidealities in Type-I Sub-Sampling PLL
Power efficient Networks on Chip
Design of a reference voltage for A/D converters
Sensorless position estimation using asymmetries in A.C. machines
Migrate Levinson-Durbin based Linear Predictive Coding algorithm into FPGAS
Instruction-level programming approach for very long instruction word digital signal processors
Coupling capacitance extraction in through-silicon via (TSV) arrays
Leveraging NoC-based Many-core Performance Through Runtime Mapping Defragmentation
Efficient FPGA implementation of Gaussian noise generator for communication channel emulation
Modeling and minimization of energy consumption in wireless sensor networks
Perspectives on scaling theory and CMOS technology - understanding the past, present, and future
Low phase noise reference oscillator with integrated PMOS varactors for digital satellite receivers
Control for high-speed archimedean spiral nanopositioning
A learning automata-based bus arbitration scheme for scalable shared-medium ATM switches
Instrumented glove for in-hand movement tracking in neurosurgical simulation
An Integrated Circuit for Galvanostatic Electrodeposition of on-chip Electrochemical Sensors
Internet of Energy Applications for Intelligent Microgrid and Smart Grid Management
Joint secured and robust technique for OFDM systems
Enhancement of mobile development of brain-computer platforms
Performances of an highly parallel image processing chain for capturing high dynamic range video
Person identification based on parametric processing of the EEG
Logarithmic AD conversion using latched comparators and a time-to-digital converter
An FPGA-based accelerator for rapid simulation of SC decoding of polar codes
Minimum settling time voltage regulation of single-phase PFC converters
Ka-band MMIC Variable Gain Low Noise Amplifier for Electronic Scanning Antenna
Efficient clock recovery architecture
Settling accuracy and noise performances in switched current grounded gate class AB memory cells
Hardware PCA for gas identification systems using high level synthesis on the Zynq SoC
A study on the relationship between initial node-edge pairs entropy and mincut circuit partitioning
Design of an 8Gsps, 65nm CMOS wideband flash ADC
Relaxed decimation filter specifications for wireless transceivers
Performance comparison of driver architectures in submicron CMOS and BiCMOS technologies for low voltage operation
Optimal resizing of bus wires in layout migration
Losses analysis and performance improvement of a rectenna for RFID systems
Application of adaptive circuit partitioning algorithm to reduction of interconnections length between elements of VLSI circuit
Detailed Solution Curves and Bifurcation Boundaries of the Forced van der Pol Oscillator
Dynamic routing strategy for embedded distributed architectures
Security mechanisms to improve the availability of a Network-on-Chip
Room equalization based on iterative simple complex smoothing of acoustic impulse responses
A successive approximation A/D converter with 16 bit 200 kS/s in 0.6 μm CMOS using self calibration and low power techniques
Standardization of JPEG quantization table for medical ultrasonic echo images
An application oriented short-course in image recognition
New natural selection process and chromosome encoding for the design of multiplierless lattice QMF using genetic algorithm
Adaptive distributed bus arbitration schemes for shared-medium ATM switches
Adaptive multirate signal estimation with lattice orthogonalization
A two-bit-per-cycle successive-approximation ADC with background offset calibration
High Performance Timing-Driven Rank Filter
Providing granted rights with anonymous certificates
Mismatched compression filter for improved radar range resolution
A 6-bit, two-step, successive approximation logarithmic ADC for biomedical applications
Construction of polyvalent error control codes for multilevel memories
A highly linear second-order stage for 500-MHz third-order and fifth-order filters
A new quantum random generator based on a single photon position sensitive device
A 100 MHz-1 GHz Adaptive Bandwidth PLL Using TDC Technique
A 10-bit high-speed low-power CMOS D/A converter in 0.2 mm 2
Design and convergence analysis of a multirate structure for adaptive filtering
A RF/DC current-mode detector for BiST and digital calibration of current-driven mixers
An 8 bits 2GS/s ADC in 180 nm CMOS process for healthcare multichannel instruments
SAD-Based Stereo Matching Circuit for FPGAs
Comparison of DEM and BEET linearization techniques for flash analog-to-digital converters using a SFDR metric
Hardware implementation of BFNN and RBFNN in FPGA technology: Quantization issues
A novel chopping-spinning MAGFET device
Transient Response of a 0.35µm CMOS SPAD with Thick Absorption Zone
A test pattern generation unit for memory NPSF built-in self test
The using of complex mixers in order to achieve RF frequency synthesis
Improved Transient Frequency Response of IIR Filters with Multiple Frequency Initialization
Improving perceptual quality and network performance for transmission of H.263 video over ATM
Novel output buffer designs for universal serial bus IC applications
A Schmitt trigger to benchmark the performance of a new zero-cost transistor
A 5GHz CMOS digitally controlled oscillator with a 3GHz tuning range for PLL applications
A methodology to design a multimedia processor core
Low-power, high-data-rate, BPSK demodulator for implantable biomedicai applications
Fuzzy c-mean clustering using evolutionary self-organizing
Evaluation of DrMOS-Based Buck Converter Operating in Diode Emulation Mode
z-Domain analysis of Dickson charge pumps
Reconfigurable Ultra Low Power LNA for 2.4GHz Wireless Sensor Networks
Shot-Noise Analysis in Circuits with Large Signal Excitations using Harmonic Balance Simulators
Saliency oriented object image re-ranking
Simulated analysis and hardware implementation of voiceband circular microphone array
Fully integrated AFE for WCDMA
A current steering architecture for 12-bit high-speed D/A converters
Low Cost Real-time Eye Tracking System for Motorsports
Parameterized test patterns methodology for layout design rule checking verification
A flexible subband-based computation scheme for generalized discrete time-frequency distributions
Leveraging Convolutional Autoencoders for Post-Layout Performance Estimation of Analog ICs
Diagnostic analysis of bandwidth mismatch in time-interleaved systems
Analog-Mixed-Signal Simulation of DC-DC Boost-Based MPPT System Taking into Account Weather Conditions Variations
Polymer Microwave Fiber: a New Communication Concept That Blends Wireless, Wireline and Optical Communication
A Hybrid Rexception Network for COVID-19 Classification from Chest X-Ray Images
Average multicast delay for FEC/DIFFSERV over IP and MPLS homogeneous networks
Wideband reconfigurable CMOS Gm-C filter For wireless applications
Multi-level MPSoC modeling for reducing software development cycle
Steady state analysis of class-E amplifier with non-linear capacitor by means of discrete-time techniques
Low-Noise Wide-Frequency Tunable Amplifier for Bioimpedance Spectroscopy Applications
Asynchronous Linear Pipelines: An efficient-optimal pipelining algorithm
An alternative two-port feedback analysis approach
Spiking Liquid Time-Constant Networks (sLTC): An Energy-Efficient and Adaptive Neuromorphic Approach
Scalability evaluation in many-core systems due to the memory organization
Minimum area in wheels [VLSI floorplanning]
Blind signal separation and speech recognition in the frequency domain
A power efficient 3-Gbits/s 1.8V PMOS-based LVDS output driver
Adaptive multifovea sensors for mobiles tracking
Energy evaluation in RLC tree circuits with exponential input
Switching functions of a data center Top-of-Rack (ToR)
FPGA-based implementation of a frequency spreading FBMC-OQAM baseband modulator
A design method for separable-denominator 2D IIR filters using a stability criterion based on the system matrix
An efficient shared-buffer for high speed ATM networks
All-digital 0.016mm 2 reconfigurable sensor-ADC using 4CKES-TAD in 65nm digital CMOS
High performance median FPGA implementation for machine vision applications
Design and fabrication of a miniaturized three-axis accelerometer for measuring heart wall motion
VHDL-based modeling of a DC-DC boost converter
Towards Solution-Processed RF Rectennas: Experimental Characterization and Non-Linear Modelling based on ZnO Nanogap Diodes
Phase and magnitude extraction using cepstrum and higher order statistics
All-digital 400∼900 MHz power amplifier consuming 0.03 mW/MHz using 0.18 μm CMOS
Current feedback operational amplifier (CFOA) based fractional order oscillators
Giant magnetoresistive sensors for rotational speed control and current monitoring applications
Humidity and Temperature Dual Flexible Microwave Sensor
Theoretical connection between PN-sequences and chaos makes simple FPGA pseudo-chaos sources possible
Can Approximate Computing Reduce Power Consumption on FPGAs?