yusuke1997/dblp-id-title huggingface dataset:
FMEA-based analysis of a Network-on-Chip for mixed-critical systems
DART: A programmable architecture for NoC simulation on FPGAs
Efficient Timing Channel Protection for On-Chip Networks
NoC's at the center of chip architecture: Urgent needs (today) and what they must become (future)
Implementing DSP Algorithms with On-Chip Networks
Bubble sharing: Area and energy efficient adaptive routers using centralized buffers
A Network Congestion-Aware Memory Controller
A comprehensive Networks-on-Chip simulator for error control explorations
Multi-Layer Test and Diagnosis for Dependable NoCs
Dynamic decentralized mapping of tree-structured applications on NoC architectures
Networks-on-chip in emerging interconnect paradigms: Advantages and challenges
Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors
Addressing Extensibility and Fault Tolerance in CAN-based Automotive Systems
Exploiting Transmission Lines on Heterogeneous Networks-on-Chip to Improve the Adaptivity and Efficiency of Cache Coherence
Flow-centric computing leveraged by photonic circuit switching for the post-moore era
Scalability-oriented multicast traffic characterization
BINDU: deadlock-freedom with one bubble in the network
Extending bufferless on-chip networks to high-throughput workloads
Mathematical Modeling and Control of Multifractal Workloads for Data-Center-on-a-Chip Optimization
Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures
Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip
Energy and reliability oriented mapping for regular Networks-on-Chip
A New Binomial Mapping and Optimization Algorithm for Reduced-Complexity Mesh-Based On-Chip Network
MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect
Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network
14th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2020, Hamburg, Germany, September 24-25, 2020
Transient queuing models for input-buffered routers in Network-on-Chip
DUB: dynamic underclocking and bypassing in nocs for heterogeneous GPU workloads
NoC Symbiosis : (Special Session Paper)
Highly Fault-tolerant NoC Routing with Application-aware Congestion Management
High-performance energy-efficient NoC fabrics: Evolution and future challenges
Tenth IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016, Nara, Japan, August 31 - September 2, 2016
Extending networks from chips to flexible and stretchable electronics
User Cooperation Network Coding Approach for NoC Performance Improvement
A built-in self-testing framework for asynchronous bundled-data NoC switches resilient to delay variations
Modeling and Design of High-Radix On-Chip Crossbar Switches
Brownian Bubble Router: Enabling Deadlock Freedom via Guaranteed Forward Progress
On-Chip photonic interconnects for scalable multi-core architectures
Networking Challenges and Prospective Impact of Broadcast-Oriented Wireless Networks-on-Chip
Twelfth IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018, Torino, Italy, October 4-5, 2018
A Study of NoC Exit Strategies
The design of a latency constrained, power optimized NoC for a 4G SoC
Fault-Tolerant 3D-NoC Architecture and Design: Recent Advances and Challenges
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
MapPro: Proactive Runtime Mapping for Dynamic Workloads by Quantifying Ripple Effect of Applications on Networks-on-Chip
STORM: A Simple Traffic-Optimized Router Microarchitecture for Networks-on-Chip
Recursive partitioning multicast: A bandwidth-efficient routing for Networks-on-Chip
Contention-free on-chip routing of optical packets
Parka: Thermally Insulated Nanophotonic Interconnects
Leveraging the geometric properties of on-chip transmission line structures to improve interconnect performance: A case study in 65nm
Unbiased Regional Congestion Aware Selection Function for NoCs
JAMS: Jitter-Aware Message Scheduling for FlexRay Automotive Networks
Single-cycle collective communication over a shared network fabric
Hybrid Automotive In-Vehicle Networks
NOCS 2011, Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, Pennsylvania, USA, May 1-4, 2011
TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers
A Power and Energy Exploration of Network-on-Chip Architectures
Using adaptive routing to compensate for performance heterogeneity
ClusCross: a new topology for silicon interposer-based network-on-chip
SpinNNaker: The world's biggest NoC
Modeling and Power Evaluation of On-Chip Router Components in Spintronics
DAPPER: Data Aware Approximate NoC for GPGPU Architectures
Channel Characterization for Chip-scale Wireless Communications within Computing Packages
Energy and Area Efficient Near Field Inductive Coupling: A Case Study on 3D NoC
An Efficient Multicast Router using Shared-Buffer with Packet Merging for Dataflow Architecture
Fast, Accurate and Detailed NoC Simulations
Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures
Printed circuits on flexible substrates: opportunities and challenges (invited paper)
Fairness-Oriented and Location-Aware NUCA for Many-Core SoC
Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC
Towards Open Network-on-Chip Benchmarks
On the Design of a Photonic Network-on-Chip
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2019, New York, NY, USA, October 17-18, 2019
Semiconductor Industry: Perspective, Evolution and Challenges
Multilayer NoC firewall services: case-study on e-health
Design of multi-channel wireless NoC to improve on-chip communication capacity!
Eighth IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, Ferrara, Italy, September 17-19, 2014
Approximate Networks on Chip
PROSA: protocol-driven NoC architecture
NEWROMAP: mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI
Delay analysis of wormhole based heterogeneous NoC
On self-tuning networks-on-chip for dynamic network-flow dominance adaptation
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance
Designing High-Performance, Power-Efficient NoCs With Embedded Silicon-in-Silica Nanophotonics
A deadlock-free routing algorithm requiring no virtual channel on 3D-NoCs with partial vertical connections
Technology assessment of silicon interposers for manycore SoCs: Active, passive, or optical?
An efficient Network-on-Chip (NoC) based multicore platform for hierarchical parallel genetic algorithms
An Analytical Approach for Dimensioning Mixed Traffic Networks
First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
Energy-efficient adaptive wireless NoCs architecture
An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links
Combinatorics and Geometry for the Many-ported, Distributed and Shared Memory Architecture
Average shortest path length of graphs of diameter 3
Securing Photonic NoC Architectures from Hardware Trojans
Analysis of photonic networks for a chip multiprocessor using scientific applications
PROBE: Prediction-based optical bandwidth scaling for energy-efficient NoCs
An Optimal Control Approach to Power Management for Multi-Voltage and Frequency Islands Multiprocessor Platforms under Highly Variable Workloads
NoC-enabled software/hardware co-design framework for accelerating k-mer counting
Using packet information for efficient communication in NoCs
Reflections on 10 Years as a Commercial On-Chip Interconnect Provider
A software framework for trace analysis targeting multicore platforms design
A novel non-minimal/minimal turn model for highly adaptive routing in 2D NoCs
Dual-Channel Access Mechanism for Cost-Effective NoC Design
An Efficient Implementation of Distributed Routing Algorithms for NoCs
Performance Evaluation of a Multicore System with Optically Connected Memory Modules
HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks
Challenges and promises of nano and bio communication networks
Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases
Network Simplicity for Latency Insensitive Cores
DyAFNoC: Characterization and analysis of a dynamically reconfigurable NoC using a DOR-based deadlock-free routing algorithm
Performance Evaluation of NoC Architectures for Parallel Workloads
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
Rethinking NoCs for Spatial Neural Network Accelerators
NoC: Network or Chip?
Effective abstraction for response proof of communication fabrics
Critical Packet Prioritisation by Slack-Aware Re-Routing in On-Chip Networks
Runtime Detection of a Bandwidth Denial Attack from a Rogue Network-on-Chip
Dark Silicon: From Computation to Communication
Energy-efficient and high-performance NoC architecture and mapping solution for deep neural networks
CDMA-based multiple multicast communications on WiNOC for efficient parallel computing
NoC-based DNN accelerator: a future design paradigm
Inter/intra-chip optical interconnection network: opportunities, challenges, and implementations
Reconfiguration of a 3GPP-LTE telecommunication application on a 22-core NoC-based system-on-chip
Dynamic synchronizer flip-flop performance in FinFET technologies
Scalability of network-on-chip communication architecture for 3-D meshes
Third International Symposium on Networks-on-Chips, NOCS 2009, May 10-13 2009, La Jolla, CA, USA. Proceedings
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs
Connection-centric network for spiking neural networks
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel
Sharing and placement of on-chip laser sources in silicon-photonic NoCs
A Diversity Scheme to Enhance the Reliability of Wireless NoC in Multipath Channel Environment
Adaptive stochastic routing in fault-tolerant on-chip networks
NoCs: It is about the memory and the programming model
Challenges and Opportunities for Edge Cloud Architectures
Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture
Hybrid large-area systems and their interconnection backbone (invited paper)
Reconfigurable Network-on-Chip for 3D Neural Network Accelerators
Securing network-on-chips via novel anonymous routing
The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs
A Low-Cost Deadlock-Free Design of Minimal-Table Rerouted XY-Routing for Irregular Wireless NoCs
An analytical model for worst-case reorder buffer size of multi-path minimal routing NoCs
HiRA: A methodology for deadlock free routing in hierarchical networks on chip
Constructing large-scale low-latency network from small optimal networks
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture
Design Technologies for Networks on Chips
A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip
Detection and prevention protocol for black hole attack in network-on-chip
Implementing Low-Diameter On-Chip Networks for Manycore Processors Using a Tiled Physical Design Methodology
An OFDMA based RF interconnect for massive multi-core processors
Toward exa-scale photonic switch system for the future datacenter (invited paper)
Flow-aware allocation for on-chip networks
Power reduction through physical placement of asynchronous routers
Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings
Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
The Power of Priority: NoC Based Distributed Cache Coherency
A vertical bubble flow network using inductive-coupling for 3-D CMPs
Bubble budgeting: throughput optimization for dynamic workloads by exploiting dark cores in many core systems
3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters
Low-Cost VC Allocator Design for Virtual Channel Wormhole Routers in Networks-on-Chip
QuaLe: A Quantum-Leap Inspired Model for Non-stationary Analysis of NoC Traffic in Chip Multi-processors
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017, Seoul, Republic of Korea, October 19 - 20, 2017
Interconnect Physical Analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for Cryptographic accelerators
FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations
Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model
Circuit-Switched Coherence
Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC Performance
Sampling-based approaches to accelerate network-on-chip simulation
Evaluating Bufferless Flow Control for On-chip Networks
An area-efficient TDM NoC supporting reconfiguration for mode changes
ElastiNoC: A self-testable distributed VC-based Network-on-Chip architecture
A low-latency adaptive asynchronous interconnection network using bi-modal router nodes
Denial-of-service attack detection using machine learning in network-on-chip architectures
Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations
The XMOS XK-XMP-64 development board
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
Complex network inspired fault-tolerant NoC architectures with wireless links
Impact of Process and Temperature Variations on Network-on-Chip Design Exploration
Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip
Synchoricity and NOCs could make Billion Gate Custom Hardware Centric SOCs Affordable
An accurate and scalable analytic model for round-robin arbitration in network-on-chip
Synthesis of NoC Interconnects for Custom MPSoC Architectures
Improving DVFS in NoCs with Coherence Prediction
Accurate Channel Models for Realistic Design Space Exploration of Future Wireless NoCs
A Mixed Verification Strategy Tailored for Networks on Chip
Quadrisection-based task mapping on many-core processors for energy-efficient on-chip communication
Two-hop Free-space based optical interconnects for chip multiprocessors
Design of a low power NoC router using Marching Memory Through type
Keynote Talk: Many-Core SoC in Nanoscale CMOS: Challenges & Opportunities
SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks
Implementation and Evaluation of a Dynamically Routed Processor Operand Network
DiAMOND: Distributed alteration of messages for on-chip network debug
Reducing the Interconnection Network Cost of Chip Multiprocessors
All-optical wavelength-routed NoC based on a novel hierarchical topology
Distributed and Dynamic Shared-Buffer Router for High-Performance Interconnect
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling
Proceedings of the 9th International Symposium on Networks-on-Chip, NOCS 2015, Vancouver, BC, Canada, September 28-30, 2015
Fault-tolerant architecture and deflection routing for degradable NoC switches
Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation
Worst-case latency analysis for the versal NoC network packet switch
Approximate Arithmetic Circuits and Their Applications
Distributed Sequencing for Resource Sharing in Multi-applicative Heterogeneous NoC Platforms
A greedy approach for latency-bounded deadlock-free routing path allocation for application-specific NoCs
Implementation of Wave-Pipelined Interconnects in FPGAs
Analysis of application-aware on-chip routing under traffic uncertainty
PIugSMART: a pluggable open-source module to implement multihop bypass in networks-on-chip
Achievable Performance Enhancements with mm-Wave Wireless Interconnects in NoC
Introduction to the special session on "Interconnect enhances architecture: Evolution of wireless NoC from planar to 3D"
Reducing Interconnect Cost in NoC through Serialized Asynchronous Links
A Framework for Combining Concurrent Checking and On-Line Embedded Test for Low-Latency Fault Detection in NoC Routers
Prevention flow-control for low latency torus networks-on-chip
On-Chip Millimeter Wave Antennas and Transceivers
Channel mapping strategies for effective protection switching in fail-operational hard real-time NoCs
FreewayNoC: A DDR NoC with Pipeline Bypassing
SMART: A Scalable Mapping And Routing Technique for Power-Gating in NoC Routers
Exploiting Dark Cores for Performance Optimization via Patterning for Many-core Chips in the Dark Silicon Era
Invited Talk 2 - Optical Interconnects for Backplane and Chip-to-Chip Photonics
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs
Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips
Low-Power Bioelectronics for Massively Parallel Neuromonitoring
Dynamic power management of voltage-frequency island partitioned Networks-on-Chip using Intel's Single-chip Cloud Computer
3D NoC-Enabled Heterogeneous Manycore Architectures for Accelerating CNN Training: Performance and Thermal Trade-offs
ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC
Power efficient photonic network-on-chip for a scalable GPU
NoC Design and Implementation in 65nm Technology
3D NoCs with active interposer for multi-die systems
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Copenhagen, Denmark, 9-11 May, 2012
BiNoCHS: Bimodal Network-on-Chip for CPU-GPU Heterogeneous Systems
Accurate System-level TSV-to-TSV Capacitive Coupling Fault Model for 3D-NoC
The Impact of Higher Communication Layers on NoC Supported MP-SoCs
VLSI micro-architectures for high-radix crossbar schedulers
NoC Communication Strategies Using Time-to-Digital Conversion
NOC-centric Security of Reconfigurable SoC
Time-dependent adaptive changes of hippocampal place cells in the simulated microgravity exposure
An ERP-based cognitive disorders detection method using a multi-scale dilated convolutional neural network (MSDCNN)
Super resolution estimation of B0 field map of brain MRI using model-based methods employing intrinsic priors
Simulating the First Breath: Design of the Respiratory Reflex in a Fetal Manikin
A Methodology for Quantifying Neurological Adaptation to Physiotherapy in ACL-Injured Patients through Muscle Activity and Brain Connectivity Analysis
Numerical Study on Flow Behavior of Red Blood Cells through Symmetric Capillary Bifurcations
Exploration of SSVEP Classification Performance Based on Acousto-Electric Brain Imaging
Indexing Biosignal for Integrated Health Social Networks
Towards Practical Facial Video-based Remote Heart Rate Estimation via Cross Domain rPPG Adaptation
Predicting Synthetic Lethal Genetic Interactions in Breast Cancer using Decision Tree
Rotator cuff injuries in overhead sports
Enhanced Osteoblastic Differentiation Using Graphene Oxide Coating on Anodized Titanium
Implementation of SMART on FHIR in Developing Countries Through SFPBRF
Proceedings of the 2024 11th International Conference on Biomedical and Bioinformatics Engineering, ICBBE 2024, Osaka, Japan, November 8-11, 2024
Investigating The Possible Effect of Gak-3βinhibitor on Macrophage Transformation Via TLR3 and 4 Signaling Pathway
The cross-subject locomotion transition prediction during previous double-stance phases with SHAP feature selection
A Study on Self-tapping Design of Cortical Screw for Orthopaedic Application by Using Finite Element Analysis on Pull-out Strength and Bending Strength
Measurement and Analysis of Calcaneus Morphometric Parameters from Computed Tomography Images
Proceedings of the 9th International Conference on Biomedical and Bioinformatics Engineering, ICBBE 2022, Kyoto, Japan, November 10-13, 2022
Prediction of protein interactions based on CT-DNN
Study on Traditional Chinese Medicine for Treating COVID-19
ICBBE 2021: 8th International Conference on Biomedical and Bioinformatics Engineering, Kyoto, Japan, November 12 - 15, 2021
Complaint Handling Training VR System using Customer Agent
Synthesis of Lower Limbs Exoskeleton for the Rehabilitation of Patients with Disorders of Motor and Proprioceptive Systems
Deep Fusion Models of Brain CT and Clinical Data for Predicting Stroke-Associated Pneumonia
The Intermittent Theta-Burst Stimulation Induces a Lasting Motor Learning Improvement In Healthy Young Subjects
Transcutaneous electrical nerve stimulation in stroke postural control and phase synchronization based on EEG
Ensemble-Based Brain Tissue Segmentation in CT Scans
Muscle Synergy Analysis on Upper Limb Movements of Human Arms
Expression and Methylation of Tumor Suppressor Gene DKK3 in Nasopharyngeal Carcinoma: A Datamining Study
HSILDNet: A Novel Deep Learning-based Method for Cervical Lesions Detection
Revisiting the K-Fold Approach for a Stable Model on Amyotrophic Lateral Sclerosis Prediction Scheme using LSTM and Attention Mechanism
Pseudo Labeling based Consistency Learning for Semi-supervised Medical Image Segmentation
Optimization of Acoustic Noise for Single-Shot Echo-Planar Imaging by Varying Echo Spacing
Acoustoelectric Signal Analysis of Sciatic Nerve Currents in Living Rats
The Molecular Dynamics Study on the stability of Elk Prion Protein
The Molecular Dynamics Study on the PATHOGENICITy of Cystatin C Mutant
Differences in Visual Cortical Responses of Different Brain Functional States
Biosensor-based Rapid Detection for Harmful Foodborne Pathogens
Recent Insights into Proteomics in Plant Pathology
A Novel Method for Estimating Respiration Rate based on Ensemble Empirical Mode Decomposition and EKG Slope
Research on High-Instruction-Set Visual Brain-Computer Interface Based on Eye-Tracking Monitoring
A Study on the Texture Quality of Vietnamese Catfish (Pangasius Hypophthalmus) Fillets after Different Freezing Processes
Efficacy of N-acetyl-L-cysteine and Budesonide/Formoterol Combination for the Treatment of Patients with BCO from China
Prediction of drug effectiveness in rheumatoid arthritis patients based on machine learning algorithms
Fast Multislice Chemical Exchange Saturation Transfer (CEST) MRI with Dual-channel RF Irradiation
Assessing the Efficacy of CEA and CA19.9 in Predicting Ovarian Cancer: Based on Logistic Regression Analysis
Pharmacokinetics Analysis of Controlled Insulin Delivery from Biodegradable Polymer Matrix
Detection of Abnormal Opacity on Chest CT Images Using A 3D-CNN
Automated Syncope Prediction from Physiological Signals Acquired during Tilt-Table Testing using Deep Learning Approach
HiCTF: A Transformer Model for enhancing Hi-C data resolution
Deep-learning algorithm for rib fracture detection in low-dose chest CT images
A Platform for the Necessities Distribution and Circulation of Residents in the Control Community During COVID-19 Outbreak Period
Discussion on the law of acupuncture point selection for the treatment of menstrual headache based on data mining technology
Characteristics Measurement of Ballistic Pressure Pulse in Phantom Using a PVDF Sensor
Study of functional and metabolic changes in subregions of precuneus in mild cognitive impairment patients using hybrid FDG-PET/fMRI
Deep Learning Models to Predict Hip Joint Kinetics From Kinematics During Gait
Fine-Grained Classification of Colposcopic Images with Multi-Modality
Predicting the Types of Striking and Thrusting Motions by using Deep Learning
Comparing vascular integrity and density of mouse tissues using whole-mount labeling vascular vessels
A Novel Linear B-cell Epitope Prediction Method based on Position Entropy of Amino Acids
Electrochemical Characteristics of Graphene Oxide Coated on Anodized Titanium for Bone Protein Detection