yusuke1997/dblp-id-title huggingface dataset:
Semantic Interoperability in Multi-Disciplinary Domain. Applications in Petroleum Industry
TALES: Test Set of Portuguese Lexical-Semantic Relations for AssessingWord Embeddings
Face Recognition Using Novel LDA-Based Algorithms
Consolidating Modal Knowledge Bases
On the Consistency of Knowledge Bases: The COVADIS System
WeaGAN: Weather-Aware Graph Attention Network for Traffic Prediction
Evaluating the feasibility of storage class memory as main memory
Synchronization for CXL Based Memory
Secure IVSHMEM: End-to-End Shared-Memory Protocol with Hypervisor-CA Handshake and In-Kernel Access Control
Enabling scalable chiplet-based uniform memory architectures with silicon photonics
Split Write DRAM: Reducing DRAM Access Latency by Mitigating Read-Write Interference
PIM-Potential: Broadening the Acceleration Reach of PIM Architectures
A comprehensive memory analysis of data intensive workloads on server class architecture
Extending the Life of Old Systems with More Memory
Understanding Energy Aspects of Processing-near-Memory for HPC Workloads
A load balancing technique for memory channels
Fast validation of DRAM protocols with timed petri nets
Driving into the memory wall: the role of memory for advanced driver assistance systems and autonomous driving
Evaluating Gather and Scatter Performance on CPUs and GPUs
FAPS-3D: feedback-directed adaptive page management scheme for 3D-stacked DRAM
DRAMScale: Mechanisms to Increase DRAM Capacity
Predicting memory accesses: the road to compact ML-driven prefetcher
Static Reuse Profile Estimation for Array Applications
Write Locality and Optimization for Persistent Memory
SMART: STT-MRAM architecture for smart activation and sensing
ZipCache: A DRAM/SSD Cache with Built-in Transparent Compression
Analyzing Consistency Issues in HMC Atomics
E-ECC: Low Power Erasure and Error Correction Schemes for Increasing Reliability of Commodity DRAM Systems
Dynamic fine-grained sparse memory accesses
Evaluation of intel 3D-xpoint NVDIMM technology for memory-intensive genomic workloads
Contention aware DRAM caching for CXL-enabled pooled memory
HUB: hugepage ballooning in kernel-based virtual machines
Challenges of Programming a System with Heterogeneous Memories and Heterogeneous Processors: A Programmer's View
Profile-guided scope-based data allocation method
The impact of cache inclusion policies on cache management techniques
ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processors
NCAM: Near-Data Processing for Nearest Neighbor Search
Proceedings of the International Symposium on Memory Systems, MEMSYS 2024, Washington, DC, USA, 30 September 2024 - 3 October 2024
Proceedings of the 2022 International Symposium on Memory Systems, MEMSYS 2022, Washington, DC, USA, October 3-6, 2022
CoMerge: toward efficient data placement in shared heterogeneous memory systems
MEMSYS 2021: The International Symposium on Memory Systems, Washington, USA, September 27 - 30, 2021
ConGen: An Application Specific DRAM Memory Controller Generator
In-memory Bulk Bitwise Logic Operation for Multi-level Cell Non-volatile Memories
k-Means Clustering on Two-Level Memory Systems
Replacement Policies for Heterogeneous Memories
DRAM-related challenges in task scheduling with timing predictability on COTS multi-cores for safety-critical systems
Large-scale Graph Processing on Commodity Systems: Understanding and Mitigating the Impact of Swapping
Dynamic Memory Pressure Aware Ballooning
Leveraging MLC STT-RAM for energy-efficient CNN training
Towards a scatter-gather architecture: hardware and software issues
Instruction Offloading with HMC 2.0 Standard: A Case Study for Graph Traversals
Software Assisted Hardware Cache Coherence for Heterogeneous Processors
Near-Memory & In-Memory Detection of Fileless Malware
Measuring Data Access Latency in Large CPU Caches
Herniated Hash Tables: Exploiting Multi-Level Phase Change Memory for In-Place Data Expansion
Decentralized Offload-based Execution on Memory-centric Compute Cores
Evaluating HPC Kernels for Processing in Memory
VMem: Enabling Application Management of Physical Memory Resources
SAME-Infer: Software Assisted Memory Resilience for Efficient Inference at the Edge
Logging in persistent memory: to cache, or not to cache?
Studying CPU and memory utilization of applications on Fujitsu A64FX and Nvidia Grace Superchip
A performance & power comparison of modern high-speed DRAM architectures
Bucket-Based Expiration Algorithm: Improving Eviction Efficiency for In-Memory Key-Value Database
Inference engine benchmarking across technological platforms from CMOS to RRAM
HMCTherm: a cycle-accurate HMC simulator integrated with detailed power and thermal simulation
Odd-ECC: on-demand DRAM error correcting codes
Statistical caching for near memory management
E=MC^2: Efficient Mobility Centric Caching
Evaluating hybrid memory cube infrastructure to support high-performance sparse algorithms
The Potential and Perils of Multi-Level Memory
PreFAM: Understanding the Impact of Prefetching in Fabric-Attached Memory Architectures
Hybrid Cache Design Under Varying Power Supply Stability - A Comparative Study
Performance characterization of a DRAM-NVM hybrid memory architecture for HPC applications using intel optane DC persistent memory modules
Characterizing the Performance of Hybrid Memory Cube Using ApexMAP Application Probes
PEPERONI: Pre-Estimating the Performance of Near-Memory Integration
Fast in-memory CRIU for docker containers
Addressing DRAM Performance Analysis Challenges for Network-on-Chip (NoC) Design
An Empirical Analysis on Memcached's Replacement Policies
Towards Application-Specific Address Mapping for Emerging Memory Devices
Hopscotch: a micro-benchmark suite for memory performance evaluation
Exploring Tag-Bit Memory Operations in Hybrid Memory Cubes
Things to Consider to Enable Dynamic Graphs in Processing-in-Memory
Integrating DRAM power-down modes in gem5 and quantifying their impact
Improving SSD lifetime with byte-addressable metadata
A Precise Measurement Platform for LPDDR4 Memories
Analysis of the Usage Models of System Memory Management Unit in Accelerator-attached Translation Units
Architecting a hardware-managed hybrid DIMM optimized for cost/performance
Opportunities and Challenges: Hardware Vulnerability descriptions with Hybrid Logic
Sadram Arithmetic in C++
DRAMPersist: Making DRAM Systems Persistent
Main memory latency simulation: the missing link
The sparse data reduction engine: chopping sparse data one byte at a time
Hardware-Software Co-Development for Emerging CXL Architectures
Data Access Complexity: Monotonicity and Proportionality
Hybrid Refresh: Improving DRAM Performance by Handling Weak Rows Smartly
Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance
CramSim: controller and memory simulator
STT-MRAM for real-time embedded systems: performance and WCET implications
3D photonics as enabling technology for deep 3D DRAM stacking
Evaluating the effectiveness of program data features for guiding memory management
TAPAS: Temperature-aware Adaptive Placement for 3D Stacked Hybrid Caches
CMOS+X: Stacking Memories based on Oxide Transistors upon GPGPU Platforms
The Feasibility of Utilizing Low-Power DRAM in Disaggregated Systems
Mitigating bitline crosstalk noise in DRAM memories
Rock: a framework for pruning the design space of hybrid main memory systems
Runtime Estimation of Application Memory Latency for Performance Analysis and Optimization
AIM: accelerating computational genomics through scalable and noninvasive accelerator-interposed memory
A Workflow for the Synthesis of Irregular Memory Access Microbenchmarks
Predicting Uncorrectable Memory Errors from the Correctable Error History: No Free Predictors in the Field
Processing Acceleration with Resistive Memory-based Computation
MEMST: Cloning Memory Behavior using Stochastic Traces
Page migration support for disaggregated non-volatile memories
Scaling the capacity of memory systems; evolution and key approaches
Performance Study of CXL Memory Topology
Omitting Refresh: A Case Study for Commodity and Wide I/O DRAMs
CLAM: Compiler Lease of Cache Memory
Concurrent Dynamic Memory Coalescing on GoblinCore-64 Architecture
Zoned FTL: Achieve Resource Isolation via Hardware Virtualization
A Data Centric Perspective on Memory Placement
Unveiling the Real Performance of LPDDR5 Memories
A Framework for Formal Verification of DRAM Controllers
Proceedings of the International Symposium on Memory Systems, MemSys 2025, Washington, USA, October 6-8, 2025
Co-DIMM: Inter-Socket Data Sharing via a Common DIMM Channel
Using Isoefficiency as a Metric to Assess Disaggregated Memory Systems for High Performance Computing
Toward Computer Vision-based Machine Intelligent Hybrid Memory Management
The interaction of last-level-cache mechanisms on modern processors
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs
Demonstration of superconducting memory for an RQL CPU
Using Many Small 1T1C Memory Arrays in a Large and Dense Multicore Processor
Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine
Design guidelines for high-performance SCM hierarchies
Writeback Modeling: Theory and Application to Zipfian Workloads
Achieving Yield, Density and Performance Effective DRAM at Extreme Technology Sizes
Proceedings of the International Symposium on Memory Systems, MEMSYS 2023, Alexandria, VA, USA, October 2-5, 2023
PROLONG: Priority based Write Bypassing Technique for Longer Lifetime in STT-RAM based LLC
A Side-channel Framework and Microarchitectural Analysis Application
Modeling Data Movement in the Memory Hierarchy in HPC Systems
DRAM errors in the field: a statistical approach
M&MMs: navigating complex memory spaces with hwloc
Memory system characterization of deep learning workloads
Languages Must Expose Memory Heterogeneity
Memory reliability for cells with strong bit-coupling interference
Writing without Disturb on Phase Change Memories by Integrating Coding and Layout Design
A Neural Network Approach for Calibrating Memristor Crossbars
Integrated Thermal Analysis for Processing In Die-Stacking Memory
Building Efficient Neural Prefetcher
Task replication and control for highly parallel in-memory stores
Opportunistic compression for direct-mapped DRAM caches
Analytical Study on Bandwidth Efficiency of Heterogeneous Memory Systems
Thermal-aware, heterogeneous materials for improved energy and reliability in 3D PCM architectures
CLARA: Circular Linked-List Auto and Self Refresh Architecture
On the Use of DRAM with Unrepaired Weak Cells in Computing Systems
Optically connected and reconfigurable GPU architecture for optimized peer-to-peer access
UpDown: A Novel Architecture for Unlimited Memory Parallelism
Towards detection of modified firmware on solid state drives via side channel analysis
Software Techniques for Scratchpad Memory Management
Transitioning scientific applications to using non-volatile memory for resilience
Composing lifetime enhancing techniques for non-volatile main memories
Memory Sandbox 2.0: A Framework for Enabling HBM2e vs HBM2 Performance and Telemetry Analysis on Xilinx FPGAs
Memory-system requirements for convolutional neural networks
Low-Latency Modulation Scheme for Solid State Drive
SIMT-based Logic Layers for Stacked DRAM Architectures: A Prototype
CARDR: DRAM Cache Assisted Ransomware Detection and Recovery in SSDs
Near memory data structure rearrangement
Interconnect-Memory Challenges for Multi-chip, Silicon Interposer Systems
Opportunities and Challenges of Performing Vector Operations inside the DRAM
Dense Footprint Cache: Capacity-Efficient Die-Stacked DRAM Last Level Cache
Simultaneously reducing cost and improving performance of NVM-based block devices via transparent data compression
Opportunities to Upgrade Main Memory
Dynamically Configuring LRU Replacement Policy in Redis
Cryogenic-DRAM based memory system for scalable quantum computers: a feasibility study
Improving Memory Reliability by Bounding DRAM Faults: DDR5 improved reliability features
LLAMA - automatic memory allocations: an LLVM pass and library for automatically determining memory allocations
Performance analysis for using non-volatile memory DIMMs: opportunities and challenges
A study of unnecessary write backs
Inter-APU Communication on AMD MI300A Systems via Infinity Fabric: A Deep Dive
Co-ML: a case for <u>co</u>llaborative <u>ML</u> acceleration using near-data processing
Design space exploration of near memory accelerators
Towards Workload-Aware Page Cache Replacement Policies for Hybrid Memories
Prefetching as a Potentially Effective Technique for Hybrid Memory Optimization
Efficient Cache Utilization via Model-aware Data Placement for Recommendation Models
Probabilistic replacement strategies for improving the lifetimes of NVM-based caches
IMPRINT: In-Memory Processing with Indirect Addressing Techniques for GPU-hosted HBM-PIM
AWARD: Approximation-aWAre Restore in Further Scaling DRAM
MMC: a Many-core Memory Connection Model
RAMPART: RowHammer Mitigation and Repair for Server Memory Systems
GraphIA: an in-situ accelerator for large-scale graph processing
PPT-GPU: performance prediction toolkit for GPUs identifying the impact of caches: extended abstract
A raspberry pi operating system for exploring advanced memory system concepts
MEMSYS 2020: The International Symposium on Memory Systems, Washington, DC, USA, September, 2020
Security and Forensics-Is Solid State Drive a Friend or a Foe?
Efficient Generation of Application Specific Memory Controllers
HOME: A Hierarchy-Oriented Memory Evaluation Framework for Fast Contention Analysis
Memory equalizer for lateral management of heterogeneous memory
Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC
Proceedings of the Second International Symposium on Memory Systems, MEMSYS 2016, Alexandria, VA, USA, October 3-6, 2016
Online Working Set Change Detection with Constant Complexity: The Cornerstone for Memory Management Algorithms in Scalable Systems
ENTS: Flush-and-Fence-Free Failure Atomic Transactions
Implications of Memory Interference for Composed HPC Applications
Proceedings of the International Symposium on Memory Systems, MEMSYS 2018, Old Town Alexandria, VA, USA, October 01-04, 2018
Reliability and Performance Trade-off Study of Heterogeneous Memories
CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip training
MC-ELMM: Multi-Chip Endurance-Limited Memory Management
Statistical DRAM modeling
A bandwidth accurate, flexible and rapid simulating multi-HMC modeling tool
Data-Centric Computing Frontiers: A Survey On Processing-In-Memory
Understanding the Impact of Air and Microfluidics Cooling on Performance of 3D Stacked Memory Systems
Stream-Aware Intelligent Memory Controller through HW/SW Co-Design
MAPCP: Memory Access Pattern Classifying Prefetcher
The Case for Associative DRAM Caches
Learning to Rank Graph-based Application Objects on Heterogeneous Memories
Reverse Engineering of DRAMs: Row Hammer with Crosshair
Exploring multi-level cache prefetching for fabric attached memory
A computation-in-memory accelerator based on resistive devices
Memory failure prediction using online learning
Scalable Analytical Memory Modeling of AI Accelerators
MicroRefresh: Minimizing Refresh Overhead in DRAM Caches
Neural Network Weight Compression with NNW-BDI
Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?
Data Prefetching on Processors with Heterogeneous Memory
ObfusGEM: Enhancing Processor Design Obfuscation Through Security-Aware On-Chip Memory and Data Path Design
An LPDDR4 Safety Model for Automotive Applications
Open2C: open-source generator for exploration of coherent cache memory subsystems
Portable application guidance for complex memory systems
The Semantic Gap Between Software and the Memory System
Dynamic Page Policy Using Perceptron Learning
Multi-Valued Physical Unclonable Functions based on Dynamic Random Access Memory
Lightweight SIMT core designs for intelligent 3D stacked DRAM
ECC-Map: A Resilient Wear-Leveled Memory-Device Architecture with Low Mapping Overhead
Improving DRAM Bandwidth Utilization with MLP-Aware OS Paging
FPGA-accelerated simulation of variable latency memory systems
Proceedings of the International Symposium on Memory Systems, MEMSYS 2019, Washington, DC, USA, September 30 - October 03, 2019
Checkpointing Exascale Memory Systems with Existing Memory Technologies
Critical Issues in Advanced ReRAM Development
Toward Classification of Phase Change Memory and 3D NAND Flash SSDs Using Power-based Side-channel Analysis in the Time-domain
Data broker: a case for workflow enablement using a key/value approach
HAPPY: Hybrid Address-based Page Policy in DRAMs
Exploring Time and Energy for Complex Accesses to a Hybrid Memory Cube
To Cache or not to Cache? Exploring the Design Space of Tunable, HLS-generated Accelerators
Speculative paging for future NVM storage
Enabling a reliable STT-MRAM main memory simulation
WAL-assisted Tiering: Painlessly Improving Your Favorite Log-Structured KV Store Instead of Building a New One
Revisiting Pebble Games for Modeling and Efficient Use of Disaggregated Memory Systems
Machine learning based design space exploration for hybrid main-memory design
Endurance enhancement of write-optimized STT-RAM caches
An In-Storage Processing Architecture with 3D NAND Heterogeneous Integration for Spectra Open Modification Search
Energy Efficient Scale-In Clusters with In-Storage Processing for Big-Data Analytics
Error Detecting and Correcting Codes for DRAM Functional Safety
How Many MLCs Should Impersonate SLCs to Optimize SSD Performance?
Cybersecurity Architecture: The Case for Teaching Computer Hardware and Computer Security Together
Performance Modeling and Evaluation of a Production Disaggregated Memory System
Architecture Exploration for Data Intensive Applications
Combining error statistics with failure prediction in memory page offlining
Implementation of a Two-Level Programmable Cache Emulation and Test System
RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism
On the Thermal Vulnerability of 3D-Stacked High-Bandwidth Memory Architectures
Demonstration of superconducting memory with passive transmission line-based reads
Linking parallel algorithmic thinking to many-core memory systems and speedups for boosted decision trees
Pimacolaba: Collaborative Acceleration for FFT on Commercial Processing-In-Memory Architectures
SMS: Solving Many-sided RowHammer
Cocoa: synergistic cache compression and error correction in capacity sensitive last level caches
A unifying abstraction for data structure splicing
NEMESYS: near-memory graph copy enhanced system-software
NEMO: an energy-efficient hybrid main memory system for mobile devices
Streaming Sparse Data on Architectures with Vector Extensions using Near Data Processing
Large-Memory Nodes for Energy Efficient High-Performance Computing
Photonic Interconnects for Interposer-based 2.5D/3D Integrated Systems on a Chip
Benchmarking Cache Programming Against Optimal Caching
SprBlk cache: enabling fault resilience at low voltages
The Case for Optimizing the Frequency of Periodic Data Movements over Hybrid Memory Systems
ECC Replay: A Practical and Efficient Scheme To Tolerate High Stuck Bit Rate
A Low Power In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions
Precision Aware Bank Separated Data Placement
REMAP: a reliability/endurance mechanism for advancing PCM
PIMS: a lightweight processing-in-memory accelerator for stencil computations
Analyzing allocation behavior for multi-level memory
A Mathematical Model for XOR-Based Application Specific DRAM Address Mapping Schemes
The Need for Precise and Efficient Memory Capacity Budgeting
DELTA: Validate GPU Memory Profiling with Microbenchmarks
Shared Last-Level Caches and The Case for Longer Timeslices
Nswap2L: Transparently Managing Heterogeneous Cluster Storage Resources for Fast Swapping
Adaptive Row Addressing for Cost-Efficient Parallel Memory Protocols in Large-Capacity Memories
Hardware transactional persistent memory
Near Data Processing: Impact and Optimization of 3D Memory System Architecture on the Uncore
Attacking memory-hard scrypt with near-data-processing
Data-driven spatial locality
Compile Time Prediction of Cache Reuse for Array Applications with Multiple Loop Nests
Design for ReRAM-based main-memory architectures
HpMC: An Energy-aware Management System of Multi-level Memory Architectures
Parallel Hash Table Design for NDP Systems
PPT-SASMM: Scalable Analytical Shared Memory Model: Predicting the Performance of Multicore Caches from a Single-Threaded Execution Trace
Stake: a coupled simulation environment for RISC-V memory experiments
S-L1: A Software-based GPU L1 Cache that Outperforms the Hardware L1 for Data Processing Applications
Cronus: Computer Vision-based Machine Intelligent Hybrid Memory Management
Efficient Orchestration of Host and Remote Shared Memory for Memory Intensive Workloads
Fine-grained data usage analysis by access sampling: seeing the data that is not there
A comparison of modern memory management schemes in HPC
Multi-Level Memory Policies: What You Add Is More Important Than What You Take Out
Fast full system memory checkpointing with SSD-aware memory controller
Cooperative NV-NUMA: prolonging non-volatile memory lifetime through bandwidth sharing
Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits
Anatomy of GPU Memory System for Multi-Application Execution
TriPIM - Exact Triangle Counting on UPMEM Processing-in-Memory for Graph Analytics
Efficient coding scheme for DDR4 memory subsystems
Modeling and Characterizing Shared and Local Memories of the Ampere GPUs
Using run-time reverse-engineering to optimize DRAM refresh
Proceedings of the International Symposium on Memory Systems, MEMSYS 2017, Alexandria, VA, USA, October 02 - 05, 2017
Programming the Future: the Essential Role of System Topology Awareness in Heterogeneous Disaggregated Environments
Digital-based processing in-memory: a highly-parallel accelerator for data intensive applications
MemFriend: Understanding Memory Performance with Spatial-Temporal Affinity
DRAM Refresh with Master Wordline Granularity Control of Refresh Intervals: Position Paper
Rethinking Design Metrics for Datacenter DRAM
Quantify the performance overheads of PMDK
PIMSys: A Virtual Prototype for Processing in Memory
Inefficiencies in the Cache Hierarchy: A Sensitivity Study of Cacheline Size with Mobile Workloads
Protean: Resource-efficient Instruction Prefetching
Long short term memory based hardware prefetcher: a case study
An Empirical Evaluation of PTE Coalescing
A Holistic View of Memory Utilization on HPC Systems: Current and Future Trends
Exposing the Locality of Heterogeneous Memory Architectures to HPC Applications
Do superconducting processors really need cryogenic memories?: the case for cold DRAM
Rethinking cycle accurate DRAM simulation
Multifidelity Memory System Simulation in SST
Thoughts on Merging the File System with the Virtual Memory System: Design decisions and their ramifications in developing the Osprey kernel
Low Latency, High Bisection-Bandwidth Networks for Exascale Memory Systems
System evaluation of the Intel optane byte-addressable NVM
Achieving transparency mapping parallel applications: a memory hierarchy affair
Pagevault: securing off-chip memory using page-based authentication
RAOP: Recurrent Neural Network Augmented Offset Prefetcher
Exploiting Data Source Distribution to Enhance NVM Reliability
A Case for Amplifying Row Hammer Attacks via Cell-Coupling in DRAM Devices
WDBT: Wear Characterization, Reduction, and Leveling of DBT Systems for Non-Volatile Memory
DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance
Proceedings of the 2015 International Symposium on Memory Systems, MEMSYS 2015, Washington DC, DC, USA, October 5-8, 2015
AWGR-based optical processor-to-memory communication for low-latency, low-energy vault accesses
Memory Workload Synthesis Using Generative AI
High Performance Computing Co-Design Strategies
Hierarchical Framework for Multi-node Compute eXpress Link Memory Transactions