yusuke1997/dblp-id-title huggingface dataset:
Some Estimates of Labor Contribution for Creating Digital Libraries
A Classification of Process Mining Bottleneck Analysis Techniques for Operational Support
Decoding IPaaS: Investigation of User Requirements for Integration Platforms as a Service
A Study on APT in IoT Networks
Blockchains and DLTs: Too Complex for Quick Wins?
Exploring Dashboards as Socio-technical Artifacts: Literature Review-based Insights
Propositions towards the Impact of Moral Values in Information System Design on Information System Success Depicted by the DeLone & McLean Information System Success Model
User-centric Business Process Transformations: Challenges and First Solutions
Business Model Scenarios for Engendering Trust in Smart City Data Collaborations
Process Science: Discovering New Ways to Do Things
Business Model Innovation to Enhance the Efficiency of Freight Logistics in the Maritime Supply Chain through Blockchain-based Industry Platforms
Automated Extraction of Citation Data in a Distributed Digital Library
Measurement Metric and Performance of Messaging Systems
Identifying the Subject of Documents in Digital Libraries Automatically Using Frequently Occurring Words - Study and Findings
An Optimised Partial-Order Approach to the Verification of System Components
Formal Verification of Component-Based Software Systems
Standards for Digital Libraries and Archives: Digital Longevity
A Digital Library Application Generator
High-Level Data Races
An Automated Classification System and Associated Digital Library Services
Exploring Spatial-Temporal Information in Digital Library
ArgoPN: a CASE Tool Merging UML and Petri Nets
Virtual Ontologies for Browsing Interfaces in Digital Libraries
A Framework For Integration Of Heterogeneous Systems
Deposit of Scientific and Technical Gray Literature in Portugal: a Case Study
Personalization to improve searching in a Digital Library
New Developments in Digital Libraries, Proceedings of the 2nd International Workshop on New Developments in Digital Libraries, NDDL 2002, In conjunction with ICEIS 2002, Ciudad Real, Spain, April 2002
Categorizing Photographs for User-Adapted Searching in a News Agency E-Commerce Application
How to Display Search Results in Digital Libraries - User Study
Access Evaluation of Digital Libraries: Characteristics and Performance of Web OPACs
Indexing Broadcast News
Improving Display of Search Results in Information Retrieval Systems Users Study
Web Site Naming and Search Engines
Document Indexing With a Concept Hierarchy
New Developments in Digital Libraries, Proceedings of the 1st International Workshop on New Developments in Digital Libraries, NDDL 2001, In conjunction with ICEIS 2001, Setúbal, Portugal, July 6-7, 2001
CHROMA: An Experimental Image Retrieval System
Programs for Ever
The Paulo Freire's Digital Library Project
Filtering Duplicate Publications in Bibliographic Databases
Evaluating Summarisation Technologies: A Task Oriented Approach
Integration and Interoperability Accessing Electronic Information Resources in Science and Technology: The Proposal of Brazilian Digital Library
Organisational Usability and the BT Digital Library
WapSearch: A System for Searching the Web Using WAP Enabled Devices
New Technologies for Information Systems, Proceedings of the 3rd International Workshop on New Developments in Digital Libraries, NDDL 2003, and the 1st International Workshop on Validation and Verification of Software for Enterprise Information Systems, VVEIS 2003, In conjunction with ICEIS 2003, Angers, France, April 2003
An Electronic Archive for Academic Communities
A Discussion Lists Survey on Awareness of Metadata Formats and Metadata Registries among Diverse Scientific Communities
Building Blocks for Durable Metadata of Visual Sources
An Area Efficient Wide Range On-Chip Delay Measurement Architecture
Timing-driven Steiner tree construction on uniform λ-geometry
Low Leakage Noise Tolerant 10T SRAM Cell
Reusable and Scalable Verification Environment for Memory Controllers
Intuitive design of PTAT and CTAT circuits for MOSFET based temperature sensor using Inversion Coefficient based approach
Classification based scheduling in Heterogeneous ISA Architectures
Secure key exchange protocol and storage of logic locking key
CMOS Implementations of Rectified Linear Activation Function
Loop unrolling with fine grained power gating for runtime leakage power reduction
Fast FPGA Placement Using Analytical Optimization
Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power application
Architectural Level Sub-threshold Leakage Power Estimation of SRAM Arrays with its Peripherals
High-Performance Stacked Dynamic Comparator for Analog to Digital Converters
Design of Energy-Efficient TSPC based D Flip-flop for CNTFET Technology
Fault-Tolerant Routing Algorithm for Mesh based NoC using Reinforcement Learning
Design of 635 MHz Bandpass Filter Using High-Q Floating Active Inductor
Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence
A Robust Low-Power Write-Assist Data-Dependent-Power-Supplied 12T SRAM Cell
A Realistic Configurable Level Triggered Flip-Flop in Quantum-Dot Cellular Automata
Design, integration and performance analysis of ΣΔ ADC for capacitive sensor interfacing
High speed self biased current sense amplifier for low power CMOS SRAM's
Design of High Speed 5: 2 and 7: 2 Compressor Using Nanomagnetic Logic
A RISC-V ISA Compatible Processor IP
Source Hotspot Management in a Mesh Network on Chip
3D-NoCNN: NoC based Clustered Architecture for Neural Networks
FPGA based disk controller and photon counter of optical polarimeter
Artificial neural network modelling of ADS designed Double Pole Double Throw switch
Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology
A Novel Design Methodology for High Tuning Linearity and Wide Tuning Range Ring Voltage Controlled Oscillator
A 32×32 CMOS image sensor: Tested using process and temperature compensated voltage controlled current source
VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases
MATLAB-Simulink based Framework for Combinational ATPG Applied to Testing of Digital Blocks in Analog and Mixed-Signal Circuits
Hardware accelerator for real-time image resizing
An Improved Circuit Transformation Technique for Nearest Neighbor Implementation of Quantum Circuits
Optimal design flow of CMOS doubler-based rectifiers
Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips
Dynamic Precision Scaling in MAC Units for Energy-Efficient Computations in Deep Neural Network Accelerators
Robust SRAM Cell Development for Single-Event Multiple Effects
Power Efficient ASIC Design for Vision Transformer using Systolic Array Matrix Multiplier
Design of tunnel FET based low power digital circuits
Quantum Circuit Design of RECTANGLE Lightweight Cipher
Design, Validation and Characterization of Number Theoretic Transform IP Core
Metastable SR Flip-Flop Based True Random Number Generator Using QCA Technology
An 8T TG-DTMOS Based Subthreshold SRAM Cell with Improved Write Ability and Access Times
A Low Power, Frequency-to-Digital Converter CMOS Based Temperature Sensor in 65 nm Process
On minimization of test power through modified scan flip-flop
Implementation of high speed radix-10 parallel multiplier using Verilog
Optimization of Test Wrapper Length for TSV Based 3D SOCs Using a Heuristic Approach
Deadlock Detection in Digital Microfluidics Biochip Droplet Routing
Automations and Methodologies for Efficient and Quality Conscious Analog Layout Implementation
High-performance multiplierless DCT architecture for HEVC
Synapse Circuits Implementation and Analysis in 180 nm MOSFET and CNFET Technology
Technology Characterization Model and Scaling for Energy Management
Machine Learning Based Computationally Efficient Approach for Accurate Prediction of Power Integrity Performance of Power Distribution Networks
Sensitivity analysis of DRV for various configurations of SRAM
Smart System with Descriptive Video Service and Spoken Dialogue System for Visually Impaired Individuals
Demonstration of a Vertically Stacked Junctionless Forksheet as Dielectric Modulated Biosensor
Automatic real-time extraction of focused regions in a live video stream using edge width information
Performance study of side block oxide band gap engineered SONOS: A device simulation approach
Efficient FPGA Implementation of Montgomery Multiplier Using DSP Blocks
TSV aware standard cell placement for 3D ICs
A True Single-Phase Error Masking Flip-Flop with Reduced Clock Power for Near-Threshold Designs
Bipolar voltage level shifter
Fast Architecture of Modular Inversion Using Itoh-Tsujii Algorithm
Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology
GaAs-SiGe Based Novel Device Structure of Doping Less Tunnel FET
Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array
An Efficient Wireless Charging Technique Using Inductive and Resonant Circuits
FPGA-Based Smart Camera System for Real-Time Automated Video Surveillance
Pipelined FFT architectures for real-time signal processing and wireless communication applications
An Improved Highly Efficient Low Input Voltage Charge Pump Circuit
A robust 8T FinFET SRAM cell with improved stability for low voltage applications
An ultra low power MICS/ISM band transmitter in 0.18 μm CMOS
Workload Driven Power Domain Partitioning
LightFPGA: Scalable and Automated FPGA Acceleration of LightGBM for Machine Learning Applications
Artificial Neural Network Model for Design Optimization of 2-stage Op-amp
User Guided Register Manipulation in Digital Circuits
A 36 nW Power Management Unit for Solar Energy Harvesters Using 0.18 \upmu m CMOS
Effectiveness of High Permittivity Spacer for Underlap Regions of Wavy-Junctionless FinFET at 22 nm Node and Scaling Short Channel Effects
An efficient reversible cryptographic circuit design
Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization
MANA: Multi-Application Mapping onto Mesh Network-on-Chip using ANN
Design of a Low-Voltage Charge-Sensitive Preamplifier Interfaced with Piezoelectric Tactile Sensor for Tumour Detection
28th International Symposium on VLSI Design and Test, VDAT 2024, Vellore, India, September 1-3, 2024
Splitting and Transport of a Droplet with No External Actuation Force for Lab on Chip Devices
Threshold Voltage Investigation of Recessed Dual-Gate MISHEMT: Simulation Study
i-MAX: Just-In-Time Wakeup of Maximally Gated Router for Power Efficient Multiple NoC
Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder Using Reduced Input Transitions
A Novel Approach to Voltage-Drop Aware Placement in Large SoCs in Advanced Technology Nodes
Golden IC free methodology for hardware Trojan detection using symmetric path delays
3D CORDIC Algorithm Based Cartesian to Spherical Coordinate Converter
Independent Gate SRAM Based on Asymmetric Gate to Source/Drain Overlap-Underlap Device FinFET
Digital Architecture for Instantaneous V/UV/S Classification of Noise Free Speech Segments
A 10 MHz, 42 ppm/ °C, 69 μW PVT Compensated Latch Based Oscillator in BCD9S Technology for PCM
VLSI Design and Test - 26th International Symposium, VDAT 2022, Jammu, India, July 17-19, 2022, Revised Selected Papers
An Efficient Multiplexer in Quantum-dot Cellular Automata
Fabrication of Molybdenum MEMs Structures Using Dry and Wet Etching
Influence of Synaptic Device Properties on the Performance of Artificial Neural Networks
25th International Symposium on VLSI Design and Test, VDAT 2021, Surat, India, September 16-18, 2021
Efficient implementation of concurrent lookahead decision feedback equalizer using offset binary coding
Surface Drift Debris Segmentation and Visualization through YCbCr Colour Space Thresholding using Low Power FPGA
Brain Inspired One Shot Learning Method for HD Computing
A Low-Power Wideband High Dynamic Range Single-Stage Variable Gain Amplifier
Chaotic Ring Oscillator Based True Random Number Generator Implementations in FPGA
Routing in NoC on Diametrical 2D Mesh Architecture
A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach for High Speed Applications
A low-power subthreshold LNA for mobile applications
Implementation of a high speed multiplier for high-performance and low power applications
A Framework for Automated Feature Based Mixed-Signal Equivalence Checking
A Synthesis Method for Quaternary Quantum Logic Circuits
CNTFET Based Low Power Repeaters for On-Chip Interconnect System
A Hamming code based technique to resolve the bit flip impact on compressed VLSI test data in IP core based SoC
Design methodology of closed loop MEMS capacitive accelerometers based on ΣΔ modulation technique
Faulty TSVs Identification in 3D IC Using Pre-bond Testing
Guided shifting of test pattern to minimize test time in serial scan
Parameter Extraction of PSP MOSFET Model Using Particle Swarm Optimization - SoC Approach
Hardware Acceleration of SpMV Multiplier for Deep Learning
An improved AES Hardware Trojan benchmark to validate Trojan detection schemes in an ASIC design flow
A Unified Methodology for Hardware Obfuscation and IP Watermarking
Analysis of regeneration time constant of dynamic latch using Adomian Decomposition method
Analysis of Standard Cells performance for In0.53Ga0.47As FinFET with underlap fin length for High Speed Applications
An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity Effect
Temperature dependent IR-drop and delay analysis in side-contact multilayer graphene nanoribbon based power interconnects
Reinforcement Learning based Droplet Routing Algorithm for Digital Microfluidic Biochips
Efficient Data Compression Scheme for Secured Application Needs
Speech Processor Design for Cochlear Implants
Evaluation of Face Recognition Schemes for Low-computation IoT System Design
A regular network of symmetric functions in quantum-dot cellular automata
A 0.47V-1.17V 32KB Timing Speculative SRAM in 28nm HKMG CMOS
SCL 180nm CMOS foundry: High reliability ASIC design for aerospace applications
Design of a Two-Step Low-Power and High-Speed CMOS Flash ADC Architecture
A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology
Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm
Three Stage Operational Amplifier with Split Length Differential Input Pair for IoT Applications
An integrable trench LDMOS transistor on SOI for RF power amplifiers in PICs
Modelling and analysis of wireless communication over Networks-on-Chip
Design and ASIC Implementation of Area Efficient UART Core in SCL 180nm Technology
Detection and analysis of hardware trojan using scan chain method
A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications
A Fast FPGA Based Architecture for Sobel Edge Detection
A Randomized Montgomery Powering Ladder Exponentiation for Side-Channel Attack Resilient RSA and Leakage Assessment
Post-bond Stack Testing for 3D Stacked IC
A Multi-Octave Frequency Range SerDes with a DLL Free Receiver
Efficient Closely-Coupled Integration of AES Coprocessor with LEON3 Processor
Congestion Balancing Global Router
A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip
2D-Transitional Metal Dichalcogenide Materials for Bio-sensors Application: A DFT-based approach
A novel VLSI design of DCTQ processor for FPGA implementation
Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture
Analysis of Electrolyte-Insulator-Semiconductor Tunnel Field-Effect Transistor as pH Sensor
A Complete Hardware Advent on IEEE 802.15.4 Based Mac Layer and a Comparison with Open-ZB
On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits
An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area Network
ACAM: Application Aware Adaptive Cache Management for Shared LLC
Design of a Fault-Tolerant Conditional Sum Adder
Rapid Prototyping of CRYSTALS-Kyber Primitives on FPGA using Python-only HW-SW Flow
A strategy for fault tolerant reconfigurable Network-on-Chip design
Synthesis of scheduler automata guaranteeing stability and reliability of embedded control systems
An Adaptive Strategy for Dynamic Resource Allocation and Scheduling for Multitasking NoC based Multicore Systems
A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts
Real Time Implementation of Convolutional Neural Network to Detect Plant Diseases Using Internet of Things
A Configurable and Area Efficient Technique for Implementing Isolation Cells in Low Power SoC
Measurement of de-assertion threshold of power-on-reset circuits
High performance bit-sliced pipelined comparator tree for FPGAs
Leveraging ReRAM Sequence Graphs for Efficient Mapping of Binary Adders in ReRAM Crossbars
New stable loadless 6T dual-port SRAM cell design
Performance Enhancement of NoCs Using Single Cycle Deflection Routers and Adaptive Priority Schemes
On-Chip Dilution from Multiple Concentrations of a Sample Fluid Using Digital Microfluidics
Flexible Composite Galois Field GF((2^m)^2) Multiplier Designs
FSK demodulator and FPGA based BER measurement system for low IF receivers
Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies
Hardware Implementation of Hyperbolic Tangent Activation Function for Floating Point Formats
Reducing FIFO buffer power using architectural alternatives at RTL
A TCAD Performance Analysis of an Inverter with 80% Non-Alignment in Gate in sub-45 nm Technology
Exploring Hard to Detect Sequential Hardware Trojans
Modeling and synthesis of molecular memory
Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects
EG0N: Portable in-situ energy measurement for low-power sensor devices
A novel low power 6-bit FLASH ADC using charge steering amplifier for RF applications
ReARM: A Reconfigurable Approximate Rounding-Based Multiplier for Image Processing
Side Channel Leakage Assessment Strategy On Attack Resistant AES Architectures
Performance Analysis of OLED with Hole Block Layer and Impact of Multiple Hole Block Layer
A 1.8 V Gain Enhanced Fully Differential Doubly-Recycled Cascode OTA with 100 dB Gain 200 MHz UGB in CMOS
Design of Content Addressable Memory Architecture Using Carbon Nanotube Field Effect Transistors
Adaptive Packet Throttling Technique for Congestion Management in Mesh NoCs
Network-on-chip: Current issues and challenges
Fault Aware Dynamic Adaptive Routing Using LBDR
Pass Transistor XOR Gate Based Radiation Hardened RO-PUF
Pioneering accessibility: Development of a cost-efficient optical imaging system
A Design Approach for ZigBee Compatible CML-based 2/3 Dual Modulus Frequency Divider
A Low Power Analog-to-Information Converter for Wireless Receivers
A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design
Performance Analysis of Disability Based Fault Tolerance Techniques for Permanent Faults in Chip Multiprocessors
Classification Algorithm for VLSI Test Cost Reduction
An analytic potential and threshold voltage model for short-channel symmetric double-gate MOSFET
Novel design for wideband piezoelectric vibrational energy harvester (P-VEH)
Net weighing based timing driven standard cell placer
Test Time Reduction with Data Throttling Techniques in a Multi Core SoC Design
JSCAN: A joint-scan DFT architecture to minimize test time, pattern volume, and power
Realistic dynamic timing verification for complex mixed signal hard macro's using UVM
A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection
A Hardware Accelerator for Convolutional Neural Network Using Fast Fourier Transform
FPGA Implementation of a Novel Area Efficient FFT Scheme Using Mixed Radix FFT
High Performance Ternary Full Adder in CNFET-Memristor Logic Technology
Real-time embedded systems analysis - From theory to practice
A new row decoding architecture for fast wordline charging in NOR type Flash memories
A re-router for optimizing wire length in two-and four-layer no-dogleg channel routing
VLSI Design and Test, 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Revised Selected Papers
A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips
Dynamic Resistance Reduction Methods for Voltage Clamp Lowering to Enhance GGNMOS ESD Protection
CSD Optimized DWT Filter for ECG Denoising
Planning based guided reconstruction of corner cases in architectural validation
CAR: Community Aware Graph Reordering for Efficient Cache Utilization in Graph Analytics
VLSI Implementation of Throughput Efficient Distributed Arithmetic Based LMS Adaptive Filter
A Photonic Network on Chip with CDMA Links
A method to design a comparator for sampled data processing applications
Analytical investigation of the Drain Current and Surface Potential in NC- FETs considering the doping concentration and Interface Trap Charge Effect
Hardware Design of Two Stage Reference Free Adaptive Filter for ECG Denoising
BDD based synthesis technique for design of high-speed memristor based circuits
Skip-scan: A methodology for test time reduction
Deterministic seed selection and pattern reduction in Logic BIST
Virtual Droplet Routing Algorithm for Digital Microfluidic Biochips
Hardware optimizations for crypto implementations (Invited paper)
A low-power high-speed hybrid full adder
LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits
Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High- k Spacers
An effective and efficient algorithm to analyse and debug clock propagation issues
Area optimized CMOS layouts of a 50 Gb/s low power 4: 1 multiplexer
An efficient FPGA-based function profiler for embedded system applications
Kapees: A New Tool for Standard Cell Placement
Low-offset Voltage Error and Low Noise Based CMOS Push-pull Operational Amplifier for Biomedical Applications in 180-nm CMOS Technology
An Energy-Efficient Core Mapping Algorithm on Network on Chip (NoC)
Arithmetic Algorithms for Ternary Number System
LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS Circuits
Fabrication and characterization of pressure sensor, and enhancement of output characteristics by modification of operating pressure range
Design and Implementation of Ternary Content Addressable Memory (TCAM) Based Hierarchical Motion Estimation for Video Processing
Design of a Programmable Delay Line with On-Chip Calibration to Achieve Immunity Against Process Variations
SAT: A new application mapping method for power optimization in 2D - NoC
Highly Non-linear Feed-Forward Arbiter PUF Against Machine Learning Attacks
A Lightweight VLSI Architecture for RECTANGLE Cipher and its Implementation on an FPGA
Design of A Custom IP Core for Concatenated SVM Model to Classify Multi-class Handwritten Numerical Characters
Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance
On Generation of Delay Test with Capture Power Safety
Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models
Disrupting Low-Write-Energy vs. Fast-Read Dilemma in RRAM to Enable L1 Instruction Cache
A Novel Input Capacitance Modeling Methodology for Nano-Scale VLSI Standard Cell Library Characterization
Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees
Post Synthesis-Optimization of Reversible Circuit using Template Matching
Realization of Multiplier Using Delay Efficient Cyclic Redundant Adder
A novel two phase heuristic routing technique in digital microfluidic biochip
Design and Analysis for Power Reduction with High SNM of 10T SRAM Cell
A Dynamic Window Size-Based VLSI Architecture Design of Moving Average Filter and Its Vulnerability to Hardware Trojans
C 2 -DLM: Cache coherence aware dual link mesh for on-chip interconnect
PRESENT Crypto-core as Closely-coupled Coprocessor for Efficient Embedded SoCs
An Efficient VLSI Architecture for PRESENT Block Cipher and Its FPGA Implementation