yusuke1997/dblp-id-title huggingface dataset:
A 0.186-pJ per Bit Latch-Based True Random Number Generator with Mismatch Compensation and Random Noise Enhancement
High-level video analytics PC subsystem using SoC with heterogeneous multi-core architecture
SNAP: A 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor for Unstructured Sparse Deep Neural Network Inference in 16nm CMOS
A 785nW Multimodal (V/I/R) Sensor Interface IC for Ozone Pollutant Sensing and Correlated Cardiovascular Disease Monitoring
A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS
4×12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS
A 5.5W AC input converter-free LED driver with 82% low-frequency-flicker reduction, 88.2% efficiency and 0.92 power factor
A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI
A 1.74.12 mm 3 Fully Integrated pH Sensor for Implantable Applications using Differential Sensing and Drift-Compensation
A 0.0046mm 2 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero
A 6.78 MHz Wireless Power Transfer System Enabling Perpendicular Wireless Powering with Efficiency Increase from 0.02% to 48.2% by Adaptive Magnetic Field Adder IC Integrating Shared Coupling Coefficient Sensor
A 1.2µW SIMO energy harvesting and power management unit with constant peak inductor current control achieving 83-92% efficiency across wide input and output voltages
A 3D stacked CMOS image sensor with 16Mpixel global-shutter mode and 2Mpixel 10000fps mode using 4 million interconnections
Battery-Less IoT Sensor Node with PLL-Less WiFi Backscattering Communications in a 2.5-μW Peak Power Envelope
Energy-efficient continual learning in hybrid supervised-unsupervised neural networks with PCM synapses
Superconducting quantum computer: a hint for building architectures
A 9.84-73.2 nJ, 0.048 mm 2 time-domain impedance sensor that provides values of resistance and capacitance
A 5nm Fin-FET 2G-search/s 512-entry x 220-bit TCAM with Single Cycle Entry Update Capability for Data Center ASICs
Resonant clock mega-mesh for the IBM z13 TM
Caching mechanisms towards single-level storage systems for Internet of Things
A TDD/FDD SAW-less superheterodyne receiver with blocker-resilient band-pass filter and multi-stage HR in 28nm CMOS
A 247 and 272 GHz Two-Stage Regenerative Amplifiers in 65 nm CMOS with 18 and 15 dB Gain Based on Double-Gmax Gain Boosting Technique
Adaptive multi-pulse program scheme based on tunneling speed classification for next generation multi-bit/cell NAND FLASH
A High Current efficiency Stacked Digital Low Dropout Array with True-Random-Noise Injection and Ultralow Output Ripple for Power-Side Channel Attack Protection
Full chip integration of 3-d cross-point ReRAM with leakage-compensating write driver and disturbance-aware sense amplifier
A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS
A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects
A 6.78MHz 92.3%-Peak-Efficiency Single-Stage Wireless Charger with CC-CV Charging and On-Chip Bootstrapping Techniques
Chiplet-Based Advanced Packaging Technology from 3D/TSV to FOWLP/FHE
A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS
A millimeter-scale wireless imaging system with continuous motion detection and energy harvesting
Circuits evening panel discussion 1: Is university circuit design research and education keeping up with industry needs?
Solar energy harvesting system with integrated battery management and startup using single inductor and 3.2nW quiescent power
PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference
An inductor-less fractional-N injection-locked PLL with a spur-and-phase-noise filtering technique
A 1.9MW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control
A 1.40mm 2 141mW 898GOPS sparse neuromorphic processor in 40nm CMOS
A Light Tolerant Neural Recording IC for Near-Infrared-Powered Free Floating Motes
A 14 nm SoC platform technology featuring 2 nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um 2 SRAM cells, optimized for low power, high performance and high density SoC products
A 0.25V 460nW asynchronous neural signal processor with inherent leakage suppression
An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibration
A 48-mW 18-Gb/s fully integrated CMOS optical receiver with photodetector and adaptive equalizer
A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm 2
SleepTalker: A 28nm FDSOI ULV 802.15.4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shape
A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration
A 33 nJ/vector descriptor generation processor for low-power object recognition
An RF-Ultrasound Relay for Powering Deep Implants Across Air-Tissue Interfaces with a Multi-Output Regulating Rectifier and Ultrasound Beamforming
Early detection and repair of VRT and aging DRAM bits by margined in-field BIST
Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices
Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS
New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications
A 19.6-Gbps CMOS optical receiver with local feedback IIR DFE
An Automated SerDes Frontend Generator Verified with a 16NM Instance Achieving 15 GB/S at 1.96 PJ/Bit
Low-power embedded ReRAM technology for IoT applications
A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering
Automated driving - Impacts on the vehicle architecture
A power-harvesting pad-less mm-sized 24/60GHz passive radio with on-chip antennas
A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR and High Efficiency
A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC
A low power and ultra high reliability LDPC error correction engine with Digital Signal Processing for embedded NAND Flash Controller in 40nm COMS
A 4K×2K@60fps multi-standard TV SoC processor with integrated HDMI/MHL receiver
A 99nW 70.4kHz resistive frequency locking on-chip oscillator with 27.4ppm/ºC temperature stability
A 250mW 5.4G-Novel-Pixel/s Photorealistic Refocusing Processor for Full-HD Five-Camera Applications
A 0.5-to-0.75V, 3-to-8 Gbps/lane, 385-to-790 fJ/b, bi-directional, quad-lane forwarded-clock transceiver in 22nm CMOS
A 1200×1200 8-Edges/Vertex FPGA-Based Motion-Planning Accelerator for Dual-Arm-Robot Manipulation Systems
A 14-bit 8.9GS/s RF DAC in 40nm CMOS achieving >71dBc LTE ACPR at 2.9GHz
Uniform Spin Qubit Devices with Tunable Coupling in an All-Silicon 300 mm Integrated Process
An Ultra-Low Power, Fully Integrated Wake-Up Receiver and Digital Baseband with All-Digital Impairment Correction and -92.4dBm Sensitivity for 802.11ba
A Fully Integrated 700MA Event-Driven Digital Low-Dropout Regulator with Residue-Tracking Loop for Fine-Grained Power Management Unit
A 0.87 V 12.5 Gb/s Clock-Path Feedback Equalization Receiver with Unfixed Tap Weighting Property in 65 nm CMOS
A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFET
A 1024-Channel Simultaneous Recording Neural SoC with Stimulation and Real-Time Spike Detection
A 27 Gb/s 5.39 pJ/bit 8-ary Modulated Wireline Transceiver Using Pulse Width and Amplitude Modulation Achieving 9.5 dB SNR Improvement over PAM-8
An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS
OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dualmode Weight Compression and On-chip Sparse Weight Transposer
A 108dB DR Hybrid-CTDT Direct-Digitalization ΔΣ-ΣM Front-End with 720mVpp Input Range and >300mV Offset Removal for Wearable Bio-Signal Recording
Monolithic Microring-based WDM Optical I/O for Heterogeneous Computing
Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer
A BJT-based temperature-to-digital converter with ±60mK (3σ) inaccuracy from -70°C to 125°C in 160nm CMOS
A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution
A Battery-Powered Opto-Electrophysiology Neural Interface with Artifact-Preventing Optical Pulse Shaping
A 60GHz wireless transceiver employing hybrid analog/digital beamforming with interference suppression for multiuser gigabit/s radio access
A 2.4GHz ternary sequence spread spectrum OOK transceiver with harmonic spur suppression and dual-mode detection architecture for ULP wearable devices
A 95.3% Peak Efficiency, 135NA Quiescent Current Buck-Boost DC-DC Converter with Current-Slope-Based Mode Control
A 28nm CMOS ultra-compact thermal sensor in current-mode technique
A 4.84mW 30fps dual frequency division multiplexing electrical impedance tomography SoC for lung ventilation monitoring system
High-resolution sensing sheet for structural-health monitoring via scalable interfacing of flexible electronics with high-performance ICs
Symposium on VLSI Circuits, VLSIC 2015, Kyoto, Japan, June 17-19, 2015
A 0.9um 2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating
A monolithically-integrated chip-to-chip optical link in bulk CMOS
A 66pW discontinuous switch-capacitor energy harvester for self-sustaining sensor applications
Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization
A single-chip encrypted wireless 12-lead ECG smart shirt for continuous health monitoring
Semiconductor Technologies Accelerate Our Future Vision: "ANSHIN Platform"
A harmonic-rejecting CMOS LNA for broadband radios
A 4GHz 16nm SRAM Architecture with Low-Power Features for Heterogeneous Computing Platforms
A 4×112 Gb/s ADC-DSP Based Multistandard Receiver in 7nm FinFET
±3% voltage variation and 95% efficiency 28nm constant on-time controlled step-down switching regulator directly supplying to Wi-Fi systems
An oscillator collapse-based comparator with application in a 74.1dB SNDR, 20KS/s 15b SAR ADC
Energy Efficient Adiabatic FRAM with 0.99 PJ/Bit Write for IoT Applications
An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM
A 300mA BGR-Recursive Low-Dropout Regulator Achieving 102-to-80dB PSR at Frequencies from 100Hz to 0.1MHz with Current Efficiency of 99.98%
A 16-channel noise-shaping machine learning analog-digital interface
A low-power Gm-C-based CT-ΔΣ audio-band ADC in 1.1V 65nm CMOS
A 22nm dynamically adaptive clock distribution for voltage droop tolerance
A -121.5 dB THD Class-D Audio Amplifier with 49 dB Suppression of LC Filter Nonlinearity and Robust to +/-30% LC Filter Spread
A 3.14 um 2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture
A 2.4-GHz 6.4-mW fractional-N inductorless RF synthesizer
Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm
A 370-fJ/b, 0.0056 mm 2 /DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop
A 31 pW-to-113 nW Hybrid BJT and CMOS Voltage Reference with 3.6% ±3σ-inaccuracy from 0 ○ C to 170 ○ C for Low-Power High-Temperature IoT Systems
A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS
A 0.5V, 6.2μW, 0.059mm 2 Sinusoidal Current Generator IC with 0.088% THD for Bio-Impedance Sensing
A 69mW 140-meter/60fps and 60-meter/300fps intelligent vision SoC for versatile automotive applications
0.65-0.73THz quintupler with an on-chip antenna in 65-nm CMOS
A 12-Bit 31.1UW 1MS/S SAR ADC with On-Chip Input-Signal-Independent Calibration Achieving 100.4DB SFDR Using 256FF Sampling Capacitance
A SiPM Readout IC Embedded in a Boost Converter for Mobile Dosimeters
A 16-core voltage-stacked system with an integrated switched-capacitor DC-DC converter
An Auxiliary-Channel-Sharing Background Distortion and Gain Calibration Achieving >8dB SFDR Improvement over 4 th Nyquist Zone in 1GS/s ADC
A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW
Managing Chip Design Complexity in the Domain-Specific SoC Era
4.2 pW timer for heavily duty-cycled systems
A 0.094um 2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist
Lensless Smart Sensors: Optical and thermal sensing for the Internet of Things
CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference
A chopping switched-capacitor RF receiver with integrated blocker detection, +31dBm OB-IIP3, and +15dBm OB-B1dB
Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme
Multipurpose, Fully-Integrated 128×128 Event-Driven MD-SiPM with 512 16-Bit TDCs with 45 PS LSB and 20 NS Gating
Features of retinal prosthesis using suprachoroidal transretinal stimulation from an electrical circuit perspective
A 144MHz integrated resonant regulating rectifier with hybrid pulse modulation
A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET
A +22dBm IIP3 and 3.5dB NF wideband receiver with RF and baseband blocker filtering techniques
A 12-Bit Mobile OLED/μLED Display Driver IC with Cascaded Loading-Free Capacitive Interpolation DAC and 6.24V/μs-Slew-Rate Buffer Amplifier
A 2D-SPAD Array and Read-Out AFE for Next-Generation Solid-State LiDAR
An Adaptive Body-Biaslna SoC Using in Situ Slack Monitoring for Runtime Replica Calibration
Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment
A 0.029MM2 17-FJ/Conv.-Step CT $\Delta\Sigma$ ADC with 2 nd -Order Noise-Shaping SAR Quantizer
A 128×120 5-Wire 1.96mm 2 40nm/90nm 3D Stacked SPAD Time Resolved Image Sensor SoC for Microendoscopy
A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS
Terahertz RF Front-End Employing Even-Order Subharmonic MOS Symmetric Varactor Mixers in 65-NM CMOS for Hydration Measurements at 560 GHz
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times
A 2.7mW/Channel 48-to-1000MHz Direct Sampling Full-Band Cable Receiver
A self-referenced VCO-based temperature sensor with 0.034°C/mV supply sensitivity in 65nm CMOS
A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures
A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS
A 4.78mm 2 fully-integrated neuromodulation SoC combining 64 acquisition channels with digital compression and simultaneous dual stimulation
A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology
A 1MW -101DB THD+N Class-AB High-Fidelity Headphone Driver in 65NM CMOS
A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS
A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications
A >3GHz ERBW 1.1GS/S 8B Two-Sten SAR ADC with Recursive-Weight DAC
A 24MB Embedded Flash System Based on 28nm SG-MONOS Featuring 240MHz Read Operations and Robust Over-The-Air Software Update for Automotive
x11 performance increase, x6.9 endurance enhancement, 93% energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression
A 7nm Leakage-Current-Supply Circuit for LDO Dropout Voltage Reduction
Energy-Efficient Reliable HZO FeFET Computation-in-Memory with Local Multiply & Global Accumulate Array for Source-Follower & Charge-Sharing Voltage Sensing
A 177mW 10GS/s NRZ DAC with Switching-Glitch Compensation Achieving > 64dBc SFDR and < -77dBc IM3
B-Face: 0.2 MW CNN-Based Face Recognition Processor with Face Alignment for Mobile User Identification
A 50.6-Gb/s 7.8-mW/Gb/s -7.4-dBm sensitivity optical receiver based on 0.18-µm SiGe BiCMOS technology
Fugaku and A64FX: the First Exascale Supercomputer and its Innovative Arm CPU
A configurable TCAM/BCAM/SRAM using 28nm push-rule 6T bit cell
Toward 1024-channel parallel neural recording: Modular Δ-ΔΣ analog front-end architecture with 4.84fJ/C-s·mm 2 energy-area product
A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm 2 per channel in 65-nm CMOS
A Photon-Counting 4Mpixel Stacked BSI Quanta Image Sensor with 0.3e- Read Noise and 100dB Single-Exposure Dynamic Range
A 0.76MM 2 0.22NJ/Pixel DL-Assisted 4K Video Encoder LSI for Quality-of-Experience Over Smart-Phones
A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS
Hybrid driver IC for real-time TFT non-uniformity compensation of ultra high-definition AMOLED display
A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range
A 26-42 GHz Broadband, Back-off Efficient and Vswr Tolerant CMOS Power Amplifier Architecture for 5G Applications
A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS
A 0.5-degree error 10mW CMOS image sensor-based gaze estimation processor with logarithmic processing
A 190GFLOPS/W DSP for energy-efficient sparse-BLAS in embedded IoT
A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS
A 0.7 V 256 μW ΔΣ modulator with passive RC integrators achieving 76 dB DR in 2 MHz BW
Buried nanomagnet realizing high-speed/low-variability silicon spin qubits: implementable in error-correctable large-scale quantum computers
A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC
A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes
Voltage droop reduction using throttling controlled by timing margin feedback
A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS
A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS
Sub-μW standby power, <18 μW/DMIPS@25MHz MCU with embedded atom-switch programmable logic and ROM
An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28NM CMOS
Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, USA, June 13-15, 2012
A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range
A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration
A high-density CMOS multi-modality joint sensor/stimulator array with 1024 pixels for holistic real-time cellular characterization
A 28nm 10Mb Embedded Flash Memory for IoT Product with Ultra-Low Power Near-1V Supply Voltage and High Temperature for Grade 1 Operation
A Cost-Effective On-Chip Power Impedance Measurement (PIM) System in 7nm FinFET for HPC Applications
On-Silicon Photonic Integrated Circuit toward On-chip Interconnection and Distributed Computing
A 114GHz Biosensor with Integrated Dielectrophoresis for Single Cell Characterization
High-Speed Voltage Control Spintronics Memory (VoCSM) Having Broad Design Windows
A 100-GbE reverse gearbox IC in 40nm CMOS for supporting legacy 10- and 40-GbE standards
A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement
Room-Temperature Quantum Sensing in CMOS: On-Chip Detection of Electronic Spin States in Diamond Color Centers for Magnetometry
A 16-GB/S 0-DB Power Back-Off 16-QAM Transmitter at 28 GHZ in 65-NM CMOS
A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with -76dBm sensitivity for high data rate wireless sensor networks
An Ultra-Low Latency 7.8-13.6 pJ/b Reconfigurable Neural Network-Assisted Polar Decoder with Multi-Code Length Support
A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor
Estimating human 3D pose from Time-of-Flight images based on geodesic distances and optical flow
Emotion or expressivity? An automated analysis of nonverbal perception in a social dilemma
Automated Facial Expression Recognition Based on FACS Action Units
HR-xNet: A Novel High-Resolution Network for Human Pose Estimation with Low Resource Consumption
Photo-Realistic Exemplar-Based Face Ageing
Hierarchical Recognition of Daily Human Actions Based on Continuous Hidden Markov Models
SAMM Long Videos: A Spontaneous Facial Micro- and Macro-Expressions Dataset
Design and Evaluation of Gesture Interface of an Immersive Walk-through Application for Exploring Cyberspace
Face recognition with Neighboring Discriminant Analysis
Design sparse features for age estimation using hierarchical face model
Extraction of relations between behaviors by lecturer and students in lectures
Dominant and Complementary Multi-Emotional Facial Expression Recognition Using C-Support Vector Classification
iSAM: Personalizing an Artificial Intelligence Model for Emotion with Pleasure-Arousal-Dominance in Immersive Virtual Reality
Facial feature localization usingweighted vector concentration approach
Multi-attribute Residual Network (MAResNet) for Soft-Biometrics Recognition in Surveillance Scenarios
An Approach Based on Phonemes to Large Vocabulary Chinese Sign Language Recognition
Pairwise linear regression: An efficient and fast multi-view facial expression recognition
Action unit detection using sparse appearance descriptors in space-time video volumes
Children's sensitivity to configural cues in faces undergoing rotational motion
Local Feature Tensor Based Deep Learning for 3D Face Recognition
IndicSideFace: A Dataset for Advancing Deepfake Detection on Side-Face Perspectives of Indian Subjects
3D Shape Constraint for Facial Feature Localization Using Probabilistic-like Output
Fast Face and Saliency Aware Collage Creation for Mobile Phones
Subsurface scattering deconvolution for improved NIR-visible facial image correlation
MGRFormer: A Multimodal Transformer Approach for Surgical Gesture Recognition
Improving Performance of Facial Biometrics With Quality-Driven Dataset Filtering
Foreign Shadow Robust Makeup Transfer via Hierarchical Deep Aggregation and Disentangled Representation
Typical and Reverse Other-Race Effect on Tibetan Students' Emotional Face Recognition
Empirical Remarks on Output Coding Methods for Face Recognition
Lie to Me: Deceit detection via online behavioral learning
Face recognition with occlusion using Dynamic Image-to-Class Warping (DICW)
Skeleton-Based Self-Supervised Feature Extraction for Improved Dynamic Hand Gesture Recognition
Spatially Constrained GAN for Face and Fashion Synthesis
Non-Contact Vital Sign Monitoring in the Clinic
Haar Features for FACS AU Recognition
A Study of the Human Perception of Synthetic Faces
Chasing Shadows: Solving Deepfake Detection Benchmarks Using Irrelevant Features Only
Toward Marker-Free 3D Pose Estimation in Lifting: A Deep Multi-View Solution