yusuke1997/dblp-id-title huggingface dataset:
Emergent Properties & Security: The Complexity ofSecurity as a Science
Principles-driven forensic analysis
Is the Future of Authenticity All In Our Heads?: Moving Passthoughts From the Lab to the World
An insecurity flow model
The ecology of Malware
The multipolicy paradigm for trusted systems
Public security: simulations need to replace conventional wisdom
Quality of security service
A profitless endeavor: phishing as tragedy of the commons
On Security Singularities
Security is fuzzy!: applying the fuzzy logic paradigm to the multipolicy paradigm
Sherlock holmes' evil twin: on the impact of global inference for online privacy
Gaming security by obscurity
Privacy is a process, not a PET: a theory for effective privacy practice
The New Security Paradigms Workshop - boom or bust?: a panel
Designing Through The Stack: The Case for a Participatory Digital Security By Design
Use of diversity as a defense mechanism
Fuzzy sets and secure computer systems
The future of biologically-inspired security: is there anything left to learn?
The New Security Paradigms Workshop, NSPW '12, Bertinoro, Italy - September 18 - 21, 2012
Argumentation logic to assist in security administration
Bell and LaPadula axioms: a "new" paradigm for an "old" model
Positive feedback and the madness of crowds
Handling Pandemic-Scale Cyber Threats: Lessons from COVID-19
The sisterhood of the traveling packets
On the functional relation between security and dependability impairments
Neighborhood data and database security
Disarming offense to facilitate defense
Spector: An OpenCL FPGA benchmark suite
Algorithm-Hardware Co-Optimization for Energy-Efficient Drone Detection on Resource-Constrained FPGA
Power estimation of a LUT-based MPGA
A Method and FPGA Architecture for Real-Time Polymorphic Reconfiguration
Towards Asynchronously Triggered Spiking Neural Network on FPGA for Event-based Vision
Exploiting memory customization in FPGA for 3D stencil computations
Evaluation of SNMP-like protocol to manage a NoC emulation platform
Design space exploration for sparse matrix-matrix multiplication on FPGAs
Power supply noise aware evaluation framework for side channel attacks and countermeasures
A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform
A greedy algorithm for tolerating defective crosspoints in nanoPLA design
Single-chip FPGA implementation of a cryptographic co-processor
Pipelining Saturated Accumulation
An adaptive and predictive architecture for parameterised PIV algorithms
Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards
An FPGA Model for Developing Dynamic Circuit Computing
An Extremely Pipelined FPGA-based accelerator of All Adder Neural Networks for On-board Remote Sensing Scene Classification
Kyokko: a Virtual channel capable Aurora 64B/66B compatible Serial Communication Controller
Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China
A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs
Accelerated FPGA architecture design: Capabilities and limitations of analytical models
An adaptive pattern recognition hardware with on-chip shift register-based partial reconfiguration
Power modelling and capping for heterogeneous ARM/FPGA SoCs
Specification and integration of software and reconfigurable hardware using Hardware Join Java
An improved Montgomery modular inversion targeted for efficient implementation on FPGA
A Regression-Based Approach Towards Estimating the Area, Delay and Leakage Power of Synthesizable FPGA Tiles
An Accelerated OpenVX Overlay for Pure Software Programmers
Improving the reliability of RO PUF using frequency offset
Evaluating software and hardware implementations of signal-processing tasks in an FPGA
Efficient custom instructions generation for system-level design
An implementation of a watershed algorithm based on connected components on FPGA
A stochastic method for security evaluation of cryptographic FPGA implementations
FPGA as service in public Cloud: Why and how
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, Brisbane, Australia, December 6-8, 2004
Design of a Vehicle-to-Vehicle communication system on reconfigurable hardware
A Markovian Approach for Detecting Failures in the Xilinx SEM core
Dataflow design for optimal incremental SVM training
FPGA implementation of digital upconversion using distributed arithmetic FIR filters
Fanout decomposition dataflow optimizations for FPGA-based Sparse LU factorization
MPD - Multi-Project Die Sharing Enabled by an Embedded FPGA
Modelling and compensating for clock skew variability in FPGAs
FPGA implementation of a real-time super-resolution system with a CNN based on a residue number system
An investigation into the design of high-performance shared buffer architectures based on FPGA technology with embedded memory
Parallel CRC On An FPGA At Terabit Speeds
FLUD: A Scalable and Configurable Systolic Array Design for LU Decomposition on FPGAs
Design of low cost FPGA based PCI Bus Sniffer
Power-aware technology mapping for LUT-based FPGAs
A statistical framework for dimensionality reduction implementation in FPGAs
Mobile GPU shader processor based on non-blocking Coarse Grained Reconfigurable Arrays architecture
Accelerating HMMER on FPGA using parallel prefixes and reductions
Hardware/software co-simulation environment for CSoC with soft processors
Enabling technologies for reconfigurable system-on-chip
Logic synthesis of multi-output functions for PAL-based CPLDs
Quad-level bit-stream signal processing on FPGAs
Productivity of High-Level Languages on Reconfigurable Computers: An HPC Perspective
DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis
TableCache: An Open-Source, Configurable, Last-Level Cache for FPGA Systems
ACS: An Addressless Configuration Support for efficient partial reconfigurations
SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis
Automatic synthesis of processor arrays with local memories on FPGAs
A transition probability based delay measurement method for arbitrary circuits on FPGAs
Temporal task clustering for online placement on reconfigurable hardware
Customizable FPGA OpenCL matrix multiply design template for deep neural networks
Customising parallelism and caching for machine learning
Designing a hardware in the loop wireless digital channel emulator for software defined radio
Transforming write collisions in block RAMs into security applications
High-speed regular expression matching with pipelined automata
Adaptive FIR filter architectures for run-time reconfigurable FPGAs
Zyndroid: An Android platform for software/hardware coprocessing
FPGA Based Router for Cognitive Packet Networks
APIR-DSP: An approximate PIR-DSP architecture for error-tolerant applications
Unrolling-based loop mapping and scheduling
An Efficient Dataflow for Convolutional Generative Models
FPGA Framework Improvements for HPC Applications
ESSPER: Elastic and Scalable System for High-Performance Reconfigurable Computing with Software-bridged APIs
An FPGA-based floating-point processor array supporting a high-precision dot product
Scaling Up Loop Pipelining for High-Level Synthesis: A Non-iterative Approach
Injecting FPGA Configuration Faults in Parallel
PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference
Reducing latency times by accelerated routing mechanisms for an FPGA gateway in the automotive domain
A High-Speed Constant-Time Hardware Implementation of NTRUEncrypt SVES
Technology research and development in Hong Kong: hype or reality
An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming
Parallel dataflow execution for sequential programs on reconfigurable hybrid MPSoCs
Optimised single pass connected components analysis
Efficient FPGA implementation of digit parallel online arithmetic operators
Modeling FPGA-based Architectures for Robotics
Covert-channels in FPGA-enabled SmartSSDs
A modular architecture for dynamically reconfigurable middlebox with customized reconfiguration handler
Field programmable gate array implementation of a generalized decoder for structured low-density parity check codes
Acceleration of fault attack emulation by consideration of fault propagation
Low Latency Elliptic Curve Cryptography Accelerators for NIST Curves Over Binary Fields
A scalable hybrid architecture for high performance data-parallel applications
Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAs
A speculative gather system for Cool Mega-Array
Exploring pipe implementations using an OpenCL framework for FPGAs
FPGA design productivity a discussion of the state of the art and a research agenda
FPGA platforms leading the way in the application of 'more than Moore's' technology
VLIW-SCORE: Beyond C for sequential control of SPICE FPGA acceleration
Resource Dependency-Aware Scheduling for High-Level Synthesis with GNN and SDC
Software-Specified FPGA Accelerators for Elementary Functions
A System-Level Design Methodology for Reconfigurable Computing Applications
Acceleration of control flow on CGRA using advanced predicated execution
Recent advances in die stacking and 3D FPGA
Scrubbing-based SEU mitigation approach for Systems-on-Programmable-Chips
Multi-personality partitioning for heterogeneous systems
A new architecture of field programmable analog arrays for reconfigurable instantiation of continuous-time filters
Doing FPGA in a former software company
Design re-use for compile time reduction in FPGA high-level synthesis flows
Deep pipelined one-chip FPGA implementation of a real-time image-based human detection algorithm
Reconfigurable FLUX networks
A temporal partitioning approach based on reconfiguration granularity estimation for dynamically reconfigurable systems
Dynamic Voltage Scaling for Commercial FPGAs
From software threads to parallel hardware in high-level synthesis for FPGAs
Extended genetic algorithm for codesign optimization of DSP systems in FPGAs
Development of a Robot Car by Single Line Search Method for White Line Detection with FPGA
A survey of NoC evaluation platforms on FPGAs
The configurable cloud - accelerating hyperscale datacenter services with FPGAs
High-level language extensions for run-time reconfigurable systems
An island-style-routing compatible fault-tolerant FPGA architecture with self-repairing capabilities
TMM-DSE: Topology-Aware MLP-Mixer for QoR Prediction in HLS Design Space Exploration
An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor
An energy-efficient, fast FPGA hardware architecture for OpenCV-Compatible object detection
Maximum flow algorithms for maximum observability during FPGA debug
Compass: A Collaborative HLS Design Space Exploration Framework via Graph Representation Learning and Ensemble Bayesian Optimization
Hardware-Efficient Homogenized Key-Point Selection for Visual SLAM
ASIF: Application Specific Inflexible FPGA
SOC implementation of wave-pipelined circuits
TAS-MRAM based Non-volatile FPGA logic circuit
Elastic Sample Filter: An FPGA-based Accelerator for Bayesian Network Structure Learning
High performance lattice regression on FPGAs via a high level hardware description language
Memory Footprint Reduction for FPGA Routing Algorithms
A system-level stochastic circuit generator for FPGA architecture evaluation
Introducing the NAIL Accelerator Interface Layer for Low Latency FPGA Offload
Instruction driven cross-layer CNN accelerator with winograd transformation on FPGA
EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA
Reconfigurable chip advantage compared with GPGPU from the compiler perspective
Guppy: A GPU-like soft-core processor
Design of an imaging system based on FPGA technology and CMOS imager
International Conference on Field Programmable Technology, ICFPT 2024, Sydney, Australia, December 10-12, 2024
High throughput, tree automata based XML processing using FPGAs
FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator
LETA: A lightweight exchangeable-track accelerator for efficientnet based on FPGA
An FPGA implementation of a special purpose processor for steganography
Clustered programmable-reconfigurable processors
Local-and-global stall mechanism for systolic computational-memory array on extensible multi-FPGA system
An FPGA based generic prototyping platform employed in a CMOS laser Doppler blood flow camera
Debug methods for hybrid CPU/FPGA systems
Post-Silicon Debug Using Programmable Logic Cores
Kernel sharing on reconfigurable multiprocessor systems
GRAPE-DR Project: a combination of peta-scale computing and high-speed networking
International Conference on Field-Programmable Technology, (IC)FPT 2022, Hong Kong, December 5-9, 2022
Hardware join Java: a unified hardware/software language for dynamic partial runtime reconfigurable computing applications
A Dynamically Reconfigured UMTS Multi-Channel Complex Code Matched Filter
FPGA based memory efficient high resolution stereo vision system for video tolling
Speed and Resource Optimization of BFGS Quasi-Newton Implementation on FPGA Using Inexact Line Search Method for Neural Network Training
A memory-efficient parallel single pass architecture for connected component labeling of streamed images
In-Storage Computation of Histograms with differential privacy
International Conference on Field-Programmable Technology, (IC)FPT 2021, Auckland, New Zealand, December 6-10, 2021
Optimizing Bayesian Recurrent Neural Networks on an FPGA-based Accelerator
Implementation of fault tolerant techniques into FPNNs
FPGA power consumption measurements and estimations under different implementation parameters
AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs
StreamZip: Compressed Sliding-Windows for Stream Aggregation
Evaluating The Highly-Pipelined Intel Stratix 10 FPGA Architecture Using Open-Source Benchmarks
Floating-point exponential functions for DSP-enabled FPGAs
Parallel resampling for particle filters on FPGAs
High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences
MaxEVA: Maximizing the Efficiency of Matrix Multiplication on Versal AI Engine
Source-directed transformations for hardware compilation
Efficient Mesh of Tree Interconnect for FPGA Architecture
The TransC process model and interprocess communication
SoC FPGA implementation of an unmanned mobile vehicle with an image transmission system over VNC
High-Speed Hardware Architectures of the Whirlpool Hash Function
A Balanced Vector-Quantization Processor Eliminating Redundant Calculation for Real-Time Motion Picture Compression
FPGA Defect Tolerance: Impact of Granularity
Real-Time Segmentation of Color Images based on the K-means Clustering on FPGA
A novel HDL coding style to reduce power consumption for reconfigurable devices
FPGA education and research activities in Taiwan
Instrumented Multi-Stage Word-Length Optimization
Variable and clause elimination in SAT problems using an FPGA
Digital Transformation of Automobile and Mobility Service
Gigabyte-scale alignment acceleration of biological sequences via Ethernet streaming
Resource-saving FPGA Implementation of the Satisfiability Problem Solver: AmoebaSATslim
Comparing the cost of protecting selected lightweight block ciphers against differential power analysis in low-cost FPGAs
Hardalign: a parallel pairwise alignment hardware application
The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms
A reconfigurable future
Strassen's matrix multiplication for customisable processors
Diagnosis of open defects in FPGA interconnect
Into the Third Dimension: Architecture Exploration Tools for 3D Reconfigurable Acceleration Devices
FADES: a fault emulation tool for fast dependability assessment
Ultra-Low-Latency and Flexible In-memory Key-Value Store System Design on CPU-FPGA
Optimal set of body bias voltages for an FPGA with field-programmable V th components
Multithreaded virtual-memory-enabled reconfigurable hardware accelerators
FPGA implementation of convolutional neural network based on stochastic computing
Efficient hardware task reuse and interrupt handling mechanisms for FPGA-based partially reconfigurable systems
Compact implementations of BLAKE-32 and BLAKE-64 on FPGA
DP-Pack: Distributed Parallel Packing for FPGAs
Wireless sensors networks emulator implemented on a FPGA
An optimal PCM codec soft IP generator and its application
Lower precision for higher accuracy: Precision and resolution exploration for shallow water equations
Implementation and Improvement of Autonomous Robot Car using SoC FPGA with DPU
FPGA implementation of spiking neural networks - an initial step towards building tangible collaborative autonomous agents
Leveraging FPGA Primitives to Improve Word Reconstruction during Netlist Reverse Engineering
Single bit error correction implementation in CRC-16 on FPGA
Effective system and performance benchmarking for reconfigurable computers
A highly parameterizable parallel processor array architecture
An FPGA-based Mix-grained Sparse Training Accelerator
Prototyping Automatic Cloud Cover Assessment (ACCA) Algorithm for Remote Sensing On-Board Processing on a Reconfigurable Computer
Partially reconfigurable flux calculation scheme in advection term computation
Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design
An FPGA chip identification generator using configurable ring oscillator
On-line scheduling of real-time tasks for reconfigurable computing system
Reconfigurable implementation of radiosity distribution computation
Gradient-Aware Depth Sensitivity Scoring for Optimizing Neural Network Pruning: (PhD Forum Paper)
Multiply Accumulate Unit Optimised for Fast Dot-Product Evaluation
Parallelized Technology Mapping to General PLBs by Adaptive Circuit Partitioning
Implementation of a highly scalable blokus duo solver on FPGA
Deterministic multi-core parallel routing for FPGAs
FPGA Acceleration of a Supervised Learning Method for Hyperspectral Image Classification
HW acceleration of multiple applications on a single FPGA
BSTMSM: A High-Performance FPGA-based Multi-Scalar Multiplication Hardware Accelerator
FPGA implementation of GZIP compression and decompression for IDC services
HIDE: a logic based hardware intelligent description environment
ADH: An Aspect Described Hardware Programming Language
FPGA-GPU-CPU heterogenous architecture for real-time cardiac physiological optical mapping
QuickDough: A rapid FPGA loop accelerator design framework using soft CGRA overlay
Minimalistic architecture for reconfigurable audio Beamforming
Extending Data Flow Architectures for Convolutional Neural Networks to Multiple FPGAs
GE3: A single FPGA client-server architecture for Golomb Ruler derivation
Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks
High-Performance Hardware Implementation of CRYSTALS-Dilithium
A task-level OoO framework for heterogeneous systems
A multiplier-less FPGA core for image algebra neighbourhood operations
A parameterized automatic cache generator for FPGAs
RotoRouter: Router support for endpoint-authorized decentralized traffic filtering to prevent DoS attacks
A FPGA implementation of the two-dimensional Digital Huygens' Model
sAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface
Hough transform line reconstruction on FPGA using back-projection
An Overview of High-Level Synthesis of Multiprocessors for Logic Programming
FPGAs as meta-platforms for embedded systems
A crystal-based digital ring oscillator
A hardware implementation of Bag of Words and Simhash for image recognition
Parametric reconfigurable designs with Machine Learning Optimizer
Design and validation of execution schemes for dynamically reconfigurable architectures
An FPGA-specific approach to floating-point accumulation and sum-of-products
The Image Forest Transform Architecture
Optimizing coarse-grained units in floating point hybrid FPGA
Optimizing residue arithmetic on FPGAs
A reconfigurable macro-pipelined systolic accelerator architecture
Automated Generation and Orchestration of Stream Processing Pipelines on FPGAs
Zytlebot : FPGA integrated ros-based autonomous mobile robot
Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC
ATB: Area-Time response Balancing algorithm for scheduling real-time hardware tasks
Synthesizing datapath circuits for FPGAs with emphasis on area minimization
Robust and real-time automatic target recognition using partial hausdorff distance measure on reconfigurable hardware
SqueezeBlock: A Transparent Weight Compression Scheme for Deep Neural Networks
Energy-aware scheduling for task adaptive FPGAs
Design methodology for analog circuit designs using proposed field programmable basic analog building blocks
Automatic rectification of design errors in complex processors with programmable hardware
Evolutionary analog circuit design on a programmable analog multiplexer array
HopliteRT: An efficient FPGA NoC for real-time applications
Within-die delay variability in 90nm FPGAs and beyond
Investigation of NBTI and PBTI induced aging in different LUT implementations
Sensing Timing Margin Contingencies in the Programmable Fabric of FPGAs
Wire congestion aware synthesis for a dynamically reconfigurable processor
An energy efficient approach for C4.5 algorithm using OpenCL design flow
FPGA implementation of HDR synthesis processing with image compression techniques
SMEFF: A scalable memory extension fabric for FPGA
Pass a pointer: Exploring shared virtual memory abstractions in OpenCL tools for FPGAs
Serial-parallel tradeoff analysis of all-pairs shortest path algorithms in reconfigurable computing
Three video applications using an FPGA based pyramid implementation: Tracking, Mosaics and Stabilization
Architecture and tools for programmable QCA
FPGA implementation of a phased array DBF using polyphase filters
FPGA implementation of real-time image convolutions with three level of memory hierarchy
A dynamically reconfigurable Field Programmable Gate Array hardware foundation for security applications
Toward a new HLS-based methodology for FPGA benchmarking of candidates in cryptographic competitions: The CAESAR contest case study
An approach for downscaling images for real-time pattern detection
FPGA-based high-performance time-to-digital converters by utilizing multi-channels looped carry chains
A Novel Asynchronous e-FPGA Architecture for Security Applications
ZIP-IO: Architecture for application-specific compression of Big Data
A 42fps full-HD ORB feature extraction accelerator with reduced memory overhead
ac 2 SLAM: FPGA Accelerated High-Accuracy SLAM with Heapsort and Parallel Keypoint Extractor
A high-performance low-power near-Vt RRAM-based FPGA
Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays
Testing reliability techniques for SoCs with fault tolerant CGRA by using live FPGA fault injection
VMODEX: A visualization tool for multi-objective Design Space Exploration
AMMC: Advanced Multi-Core Memory Controller
A circuit to synchronize high speed serial communication channel
Improved carry chain mapping for the VTR flow
A concurrent multi-bank memory arbiter for dynamic IP cores using idle skip round robin
Efficient Inter-Kernel Communication for OpenCL Database Operators on FPGAs
FPGA Architecture Enhancements for Efficient BNN Implementation
Real-time detection of line segments using the line Hough transform
Rapid synthesis and simulation of computational circuits in an MPPA
A Single-Chip FPGA Implementation of Real-Time Adaptive Background Model
Explore the Feedback Interconnects in Intra-Cluster Routing for FPGAs
Interconnect driver design for long wires in field-programmable gate arrays
Demonstration of Full-Duplex Packet Transfers Over PCI Express with Sustained 200 Gbps Throughput
Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memory
A threat-based Connect6 implementation on FPGA
Improved SVD systolic array and implementation on FPGA
Braiding: A scheme for resolving hazards in kernel adaptive filters