yusuke1997/dblp-id-title huggingface dataset:
On generation of a universal path candidate set containing testable long paths
Production Experience with Built-In Self-Test in the IBM ES/9000 System
Keynote address Wednesday: Hardware inference accelerators for machine learning
QML (qualified manufacturing line): a method of providing high quality integrated circuits
An AC/DC Test Generation System for Gate Array LSIs
A BIST approach for very deep sub-micron (VDSM) defects
Low power test application with selective compaction in VLSI designs
Timing Accuracy Enhancement by a New Calibration Scheme for Multi-Gbps ATE
Guaranteed by design or guaranteed to fail or guaranteed by test? or ... neither?
Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing
Testing a DSP-Based Mixed-Signal Telecommunications Chip
Small-Bridging-Fault-Aware Built-In-Self-Repair for Cycle-Based Interconnects in a Chiplet Design Using Adjusted Pulse-Vanishing Test
Pattern-directed circuit virtual partitioning for test power reduction
The PXI Modular Instrumentation Architecture
ATE-Customer Perspectives & Requirements Panel
Lower Overhead Design for Testability of Programmable Logic Arrays
Calibration of a flexible high precision Power-On Reset during production test
High Speed Redundancy Processor
Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement
Frequency/Phase Movement Analy i by Orthogonal Demodulation
A technique for fault diagnosis of defects in scan chains
A Method for Testing Subnanosecond ECL
Memory repair logic sharing techniques and their impact on yield
STIL from the Users Perspective
Considerations for STIL Data Application
A high-level BIST synthesis method based on a region-wise heuristic for an integer linear programming
Unleashing the Power of Anomaly Data for Soft Failure Predictive Analytics
Chain Cell-Aware Diagnosis
Unit Testing Versus Integration Testing
A Pragmatic Test Data Management System
Test methodology for the McKinley processor
Managing Quality : Today's Opportunities, Tomorrow's Challenges
A Novel Tester-Based Approach for Functional Testing of Hardware Timers
Memory Chip Test Economics
Test Technology in the University
It Makes Sense to Combine DFT and DFR/DFY
The Impact of Commercial Off-The-Shelf (COTS) Equipment on System Test and Diagnosis
Direct access test scheme-design of block and core cells for embedded ASICs
A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs
Industrial Application of IJTAG Standards to the Test of Big-A/little-d devices
Combined Array and ADC Structural Test for RRAM-based Multiply-and-Accumulate Circuits
Outsourcing Test without Standards?
CHEETA: Composition of Hierarchical Sequential Tests Using ATKET
Implementation and Evaluation of Microinstruction-Controlled Self Test Using a Masked Microinstruction Scheme
Delay Test: The Next Frontier for LSSD Test Systems
Correlating Testability with Fault Detection
Utilizing ECC Analytics to Improve Memory Lifecycle Management
Testing of Sense Amplifier in Dynamic Memory
Detection of Control Flow Errors Using Signature and Checking Instructions
Fast Sequential ATPG Based on Implicit State Enumeration
Test Features ot the MC68881 Floating-Point Coprocessor
Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study
On Functional Controllability and Observability Analysis
BIST Fault Diagnosis in Scan-Based VLSI Environments
DFT-Enhanced Test Scheme for Spin-Transfer-Torque (STT) MRAMs
Fault Injection for Verifying Testability at the VHDL Level
CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator
The Challenges of Implementing an MBIST Interface: A Practical Application
Computing at the Crossroads (And What Does it Mean to Verification and Test?)
Testing CMOS VLSI: Tools, Concepts, and Experimental Results
Realistic Spring Probe Testing Methods and Results
Design for test and time to market-friends or foes
Latch Divergency In Microprocessor Failure Analysis
ASIC BIST Synthesis: A VHDL Approach
Test Setup Simulation - A High-Performance VHDL-Based Virtual Test Solution Meeting Industrial Requirements
Today's SOC test challenges
Secure and Efficient Sharing of On-Chip Resources
Distributed Implementation of an ATPG System Using Dynamic Fault Allocation
Failure mechanisms and fault classes for CMOS-compatible microelectromechanical systems
DOs and DON'Ts in Computing Fault Coverage
Improving Angle of Arrival Estimation Accuracy for mm-Wave Radars
TESLA: Testability Enhancement for Shift-Left Automation via Multi-LLM Collaboration
Packet-Based Input Test Data Compression Techniques
Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement
Linearity Test of Analog-to-Digital Converters Using Kalman Filtering
Enhanced delay defect coverage with path-segments
Testing and Remote Field Update of Distributed Base Stations in a Wireless Network
A Robust On-Chip Sensor for Online Monitoring of BTI-Induced Aging in Integrated Circuits
Testing Challenges of Future Wireless World
A BIST Design Methodology Experiment
12Gbps SerDes Jitter Tolerance BIST in production loopback testing with enhanced spread spectrum clock generation circuit
Diagnostic test generation for sequential circuits
Test Generation and Design for Test for a Large Multiprocessing DSP
Compaction Technique Universal Pin Electronics
Keep Alive - A New Requirement for High Performance uProcessor Test
G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of Backtracing
Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis
Efficient Identification of Non-Robustly Untestable Path Delay Faults
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM
Concurrent error detection in block ciphers
Towards Provably Secure Logic Locking for Hardening Hardware Security Dissertation Summary: IEEE TTTC E.J. McCluskey Doctoral Thesis Award Competition
Maximizing and Maintaining AC Test Accuracy in the Manufacturing Environment
DECOUPLE: defect current detection in deep submicron I_DDQ
Securing digital microfluidic biochips by randomizing checkpoints
A Software Architecture for Mixed-Signal Functional Testing
External memory BIST for system-in-package
Teaching Testing
Board Level Automated Fault Injection for Fault Coverage and Diagnostic Efficiency
CrossCheck: A Practical Solution for ASIC Testability
High Performance Electron Beam Tester for Voltage Measurement on Unpassivated and Passivated Devices
Pseudo fail bit map generation for RAMs during component test and burn-in in a manufacturing environment
BS 1149.1 extensions for an online interconnect fault detection and recovery
How (In)Adequate is One-time Testing
Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning
Efficient Fault Simulation of CMOS Circuits with Accurate Models
Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Multiprocessors
Periodic Jitter Injection with Direct Time Synthesis by SPPTM ATE for SerDes Jitter Tolerance Test in Production
A Proposed Benchmark Unit for Evaluating Electronic Troubleshooting Expert Systems
Power-supply noise in SoCs: ATPG, estimation and control
Problems Encountered in Developing VLSI Test Programs for COT (A Practical Outlook)
Testing Issues on High Speed Synchronous DRAMs
Testing Barrel Shifters in Microprocessors
Process monitoring through wafer-level spatial variation decomposition
Vernier Method for Calibration ot High-Speed Sampling System
An Expert Test Program Generation System for Per-Pin Testers
R96MFX Test Strategy
The Economics of Implementing Scan Compression to Reduce Test Data Volume and Test Application Time
P-PET: Partial pseudo-exhaustive test for high defect coverage
Justifying DFT with a Hierarchical Top-Down Cost-Benefit Model
Techniques for User Testing of the 68882
An Efficient Scheme to Diagnose Scan Chains
Improving Precision Using Mixed-level Fault Diagnosis
Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip
Logic Elements for Universally Testable Circuits
A picosecond external electro-optic prober using laser diodes
At-Speed Structural Test For High-Performance ASICs
Logic BIST for large industrial designs: real issues and case studies
Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis
"Low Cost Testers" : Are They Really Low Cost ?
Fast and Accurate CMOS Bridging Fault Simulation
The Uses and Costs of the Addition of Remote Operation Capability to New Products
Combining Internal Probing with Artificial Neural Networks for Optimal RFIC Testing
How many probes is enough? A low cost method for probe card depopulation with low risk
A Practical Approach to Fault Simulation and Test Generation for Bridging Faults
Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities
On the Design of Testable Domino PLAs
I DDQ Testing of CMOS Opens: An Experimental Study
MCM Foundry Test Methodology and Implementation
CAE Functionality for Verification of Diagnostic Programs
Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data
Open Architecture Test System: System Architecture and Design
Optimal Interconnect ATPG Under a Ground-Bounce Constraint
Pseudo-Exhaustive Testing of Sequential Machines Using Signature Analysis
SEC-CiM: Selective Error Compensation for ReRAM-based Compute-in-Memory *
Test structure verification of logical BIST: problems and solutions
ALAPTF: A new Transition Faultmodel and the ATPG Algorithm
Recognizing Wafer Map Patterns Using Semi-Supervised Contrastive Learning with Optimized Latent Representation Learning and Data Augmentation
DFT, DFY, DFR: Who Cares?
A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis
Solving In-Circuit Defect Coverage Holes with a Novel Boundary Scan Application
Different experiments in test generation for XILINX FPGAs
Automatic Calibration for a VLSI Test System
SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level
Welcome Message ITC 2023
Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator
Full Enablement of Very-Low Voltage Testing to Deliver Zero Defect Quality Automotive Products
IEEE 1149.1: How to Justify Implementation
An architecture for high-speed analog in-circuit testing
Fault Coverage Tools: Case Studies
Launch-on-Shift-Capture Transition Tests
A Suite of Novel Digital ATE Timing Calibration Methods
Hierarchical Failure Modeling and Machine Learning Assisted Correction of Electro-Mechanical Subsystem Failures in Autonomous Vehicles
HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs
On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits
Time-dependent Behaviour of Full Open Defects in Interconnect Lines
FPGA Test and Coverage
The Effects of Backdrive Stressing Fast IC Technologies
Robustness IPs for Reliability and Security of SoCs
Electrical Modeling of STT-MRAM Defects
Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors
Fault Localization using Time Resolved Photon Emission and STIL Waveforms
CAD-Driven High-Precision E-Beam Positioning
Fault Diagnosis using Functional Fault Models for VHDL descriptions
Static test sequence compaction based on segment reordering and accelerated vector restoration
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
Design Optimization for N-port RF Network Reflectometers under Noise and Gain Imperfections
Digital Synchronization for Reconfigurable ATE
Testabilty Features of the MC 68060 Microprocessor
Unsupervised Root-Cause Analysis for Integrated Systems
On using IEEE P1500 SECT for test plug-n-play
On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs
Do You Practice Safe Tests? What We Found Out About Your Habits
A Method of Jitter Measurement
Methods for improving transition delay fault coverage using broadside tests
A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets
Identification and Test Generation for Primitive Faults
DFFT : Design For Functional Testability
Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT
Methods of Test Waveform Synthesis for High-Speed Data Communication Devices
Modeling, verification and pattern generation for reconfigurable scan networks
IJTAG (internal JTAG): a step toward a DFT standard
Parametric Failures in CMOS ICs - A Defect-Based Analysis
Embedded Core Test Plug-n-Play: Is It Achievable?
Jitter measurements of a PowerPC TM microprocessor using an analytic signal method
Test Structure and Testing of the Microsoft XBOX 360 TM Processor High Speed Front Side Bus
Test to Eliminate Test
A structured and scalable mechanism for test access to embedded reusable cores
A novel built-in self-repair approach to VLSI memory yield enhancement
GRAAL: a new fault tolerant design paradigm for mitigating the flaws of deep nanometric technologies
Known-good-die test methods for large, thin, high-power digital devices
Fault mitigation strategies for CUDA GPUs
The Waveform and Vector Exchange Specification (WAVES)
Modeling the impact of process variation on resistive bridge defects
Complete testing of receiver jitter tolerance
Integrated Test Solutions and Test Economics for MCMs
SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits
Language Independent Test Generation
A Novel Ganged DAC Solution for Multi-Site Testing
IEEE 1149.1 Applied to Mixed TTL-ECL and Differential Logic
The Future is Now: Extending CAE into Test of Custom VLSI
The Impact of On-chip Training to Adversarial Attacks in Memristive Crossbar Arrays
Trends in SLI design and their effect on test
Simply-Track-and-Refresh: Efficient and Scalable Rowhammer Mitigation
Linearity Testing of Precision Analog-to-Digital Converters Using Stationary Nonlinear Inputs
A Small Test Generator for Large Designs
2015 IEEE International Test Conference, ITC 2015, Anaheim, CA, USA, October 6-8, 2015
A digital method for phase noise measurement
An Automated Optical On-Wager Probing System for Ultra-High-Speed ICs
Testing a system-on-a-chip with embedded microprocessor
A pattern mining framework for inter-wafer abnormality analysis
A Practical System for Mutation Testing: Help for the Common Programmer
High-Speed I DDQ Measurement Circuit
High speed testing-have the laws of physics finally caught up with us?
An Optimized DFT and Test Pattern Generation Strategy for an Intel High Performance Microprocessor
A test case for 3Gbps serial attached SCSI (SAS)
Electron Beam Prober for LSI Testing with 100ps Time Resolution
Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCs
Test Data Quality Assurance
Simulation Based System Level Fault Insertion Using Co-verification Tools
Efficient Test-Response Compression for Multiple-Output Cicuits
A diagnosis-friendly LBIST architecture with property checking
Convolutional Compaction of Test Responses
Testing the Integrity of the Boundary Scan Test Infrastructure
A novel approach to improve test coverage of BSR cells
New methods for receiver internal jitter measurement
Testing the Dynamic Performance of High-Speed A/D Converters
Test Coverage: What Does It Mean When a Board Test Passes?
WM-Graph: Graph-Based Approach for Wafermap Analytics
Leveraging existing power control circuits and power delivery architecture for variability measurement
Optimizing delay tests at the memory boundary
Memory Test-Debugging Test Vectors Without ATE
Case Study - Using STIL as Test Pattern Language
Test Generation: A Boundary Scan Implementation for Module Interconnect Testing
Determination of Safe Back-Driving Currents in Bond Wires and Dice
Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks
Isometric test compression with low toggling activity
Improving test compression with scan feedforward techniques
A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems
Test Generation and Concurrent Error Detection in Current-Mode A/D Converters
Scan based guided probe technology delivers Cyclone to the market
Robust testability of primitive faults using test points
A General Purpose ATE Based I DDQ Measurement Circuit
Detectable CMOS Faults in Switch-Level Simulation
Two Fault Injection Techniques for Test of Fault Handling Mechanisms
Dynamic Memory Array Card Burn-In and High Speed Functional Card Testing
End-to-end error correction and online diagnosis for on-chip networks
Optical interferometric probing of advanced microprocessors
The ITC Lecture Series: An Experiment
MCM Compute Node Thermal Failure - Design or Test Problem?
Efficient Low Cost Alternative Testing of Analog Crossbar Arrays for Deep Neural Networks
Hierarchical Test Pattern Generation Based on High-Level Primitives
Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing
Partial Scan at the Register-Transfer Level
Fault Coverage Estimation for Non-Random Functional Input Sequences
Data-driven fault model development for superconducting logic
Testability of the Philips 80C51 micro-controller
State Diagram Approach for Functional Testing of Control Section
System Level Interconnect Test in a Tristate Environment
Integration of SRAM Redundancy into Production Test
One-Pass Redundancy Identification and Removal
A Methodology for Designing Optimal Self-Checking Sequential Circuits
An optimal test pattern selection method to improve the defect coverage
DFM - A Fabless Perspective
Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability
Having FUN with Analog Test
Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA
Higher than Nyquist test waveform synthesis and digital phase noise injection using time-interleaved mixed-mode data converters
Case-based reasoning: diagnosis of faults in complex systems through reuse of experience
Application and Analysis of IDDQ Diagnostic Software
Static Component Interconnection Test Technology (SCITT)
Probe Card Ground Noise Canceling Circuit
Is High-Level Test Synthesis Just Design for Test?
X-Press Compactor for 1000x Reduction of Test Data
Flip-flops fanout splitting in scan designs
Silicon IP And Successful DFM
Functional and I DDQ testing on a static RAM
Defect Level Estimation of Random and Pseudorandom Testing
The Analysis of Parallel BIST by the Combined Markov Chain (CMC) Model
Development of a software framework for open architecture ATE
Microelectronic Device Electrical Test Implementation Problems on Automated Test Equipment
Hierarchical DFT with enhancements for AC scan, test scheduling and on-chip compression - a case study
Improving Analog Functional Safety Using Data-Driven Anomaly Detection
Precise Pulse Width Measurement in Write Pre-compensation Test
Test Station Workcell Controller and Resource Relationship Design
A Hierarchical, Desgin-for-Testability (DFT) Methodology for the Rapid Prototyping of Application-Specific Signal Processors (RASSP)
A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs
STAFAN Takes a Middle Course
A Technique for Testing Large Distributed Systems
Test Generation for Interconnect Opens
A systems perspective on the R&D of industrial technology
An ALU-Based Programmable MISR/Pseudorandom Generator for a MC68HC11 Family Self-Test
Principal Component Analysis-based compensation for measurement errors due to mechanical misalignments in PCB testing
Increasing Test Coverage in a VLSI Design Course
Hardware Root of Trust for SSN-basedDFT Ecosystems
High throughput multiple device diagnosis system
Increasing Scan Compression by Using X-chains
Automated Contactless Digital Test System for VLSI
The Impact of Outsourcing on Test
Redefining ATE: "Data Collection Engines that Drive Yield Learning and Process Optimization"
Test SPC: A Process to Improve Test System Integrity
COMET: A Testability Analysis and Design Modification Package
Efficient Functional In-Field Self-Test for Deep Learning Accelerators
Integrated Test Logic for Video ICs
Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run
Actual implementation of multi domain test: Further reduction of cost of test
Inside a Modern Test Language Compiler
An On-Lined Laser Probing System for Diagnosing Scaled VLSI
STIL: the device-oriented database for the test development lifecycle
On the testing of hazard activated open defects
Diagnosis in Modern Design - Just the Tip of the Iceberg
A design-for-reliability approach based on grading library cells for aging effects
Testing for resistive opens and stuck opens
Military Burn-In Requirements - One Perspective
A High Performance, 10-Volt Integrated Pin Electronics Driver
Characterization of Locked Combinational Circuits via ATPG
A high linearity compact timing vernier for CMOS timing generator
Correlating Defects to Functional and I DDQ Tests
High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation Algorithms
A Single Board Test System: Changing the Test Paradigm
Defining ATPG rules checking in STIL
Testing Micropipelined Asynchronous Circuits
Compact two-pattern test set generation for combinational and full scan circuits
Yiel Learning via Functional Test Data
A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling
Certification Trails and Software Design for Testability
AVM TM a more usable way to execute vectors at double speed
From specification to measurement: the bottleneck in analog industrial testing
Bitline contacts in high density SRAMs: design for testability and stressability
Random Pattern Testability of Delay Faults
Cost effective manufacturing test using mission mode tests
Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65nm CMOS Technologies
Board-level fault diagnosis using an error-flow dictionary
Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes
Low capture power at-speed test in EDT environment
Cost-Effective Test Method for screening out Unexpected Failure in High Speed Serial Interface IPs
On-Die DFT Based Solutions are Sufficient for Testing Multi-GHz Interfaces in Manufacturing (and Are Also Key to Enabling Lower Cost ATE Platforms)
Using LSSD to test modules at the board level
Vulnerability-based Interleaving for Multi-Bit Upset (MBU) protection in modern microprocessors
Switch-Level Concurrent Fault Simulation Based on a General Purpose List Traversal Mechanism
Analog test requirements of linear echo cancellation ISDN devices
Solder Bead on High Density Interconnect Printed Circuit Board
Characterization and Control of PLCC and MQFP Lead Inspection Systems
Optimized BIST Strategies for Programmable Data Paths Based on Cellular Automata
An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques
Portable simulation/emulation stimulus on an industrial-strength SoC
Test Program Debugging Environment for Linear IC Testers
Testing Highly Integrated Wireless Circuits and Systems with Low Cost Tester: How to Overcome the Challenge?
A "Three Mode" Command Language for ATE
Just how real is the SIA roadmap
Method for Adjusting Termination Resistance Using PMU in DC Test
nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications
Mix Test: A Mixed-Signal Extension to a Digital Test System
Partial Scan Using Reverse Direction Empirical Testability
New Concepts of Applying Thermographic Testing to Printed Circuit Boards and Finished Products
Generation of Compact Delay Tests by Multiple-Path Activation
A Case Study of the Test Development for the 2nd Generation ColdFire® Microprocessors
Backplane Interconnect Test in a Boundary-Scan Environment
At-speed capture power reduction using layout-aware granular clock gate enable controls
Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor
Test Data Automation: An ATE Distributed Processing Application in a Multi-Vendor Environment
A High Level Test Pattern Generation Algorithm
A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs
SPC on the IC-Production Test Process