yusuke1997/dblp-id-title huggingface dataset:
Hypersort: High-performance Parallel Sorting on HBM-enabled FPGA
An FPGA-based Othello endgame solver
An FPGA based coprocessor for large matrix product implementation
A parallel FPGA design of the Smith-Waterman traceback
Super fast hardware string matching
A novel FPGA-based SVM classifier
Message from the General Chair and Program Co-Chairs
RBSA: Range-based simulated annealing for FPGA placement
A Programmable Load/Store Unit on C-based Hardware Design for FPGA
Efficient Queue-Balancing Switch for FPGAs
Processor customization for wearable bio-monitoring platforms
Automating formal verification of customized soft-processors
Development framework for firewall processors
Reconfigurable I/O interface for mobile equipments
FPGA implementation of a SIMD-based array processor with torus interconnect
Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping
A scalable reconfiguration mechanism for fast dynamic reconfiguration
The Quartus University Interface Program: enabling advanced FPGA research
Introduction of MNSTbot
Total-ionizing-dose tolerance evaluation of an optoelectronic field programmable gate array VLSI during operation
Minimizing peak power for application chains on architectures with partial dynamic reconfiguration
A Domain Specific Language for Reconfigurable Path-based Monte Carlo Simulations
High-Speed Computation of CRC Codes for FPGAs
An adaptive Viterbi decoder on the dynamically reconfigurable processor
Hardware/Software Co-design of a General-Purpose Computation Platform in Particle Physics
K-way partitioning based packing for FPGA logic blocks without input bandwidth constraint
A scalable FPGA architecture for non-linear SVM training
StreamSVD: Low-rank Approximation and Streaming Accelerator Co-design
A prototyping system for hardware distributed objects with diversity of programming languages design and preliminary evaluation
Smart camera for Trax playing robot
3D implication logic: Preliminary results
Reconfigurable filtered acceleration of short read alignment
Generating hardware from OpenMP programs
Activity-based power estimation and characterization of DSP and multiplier blocks in FPGAs
2016 International Conference on Field-Programmable Technology, FPT 2016, Xi'an, China, December 7-9, 2016
Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs
SOAP: Structural optimization of arithmetic expressions for high-level synthesis
Artificial intelligence of Blokus Duo on FPGA using Cyber Work Bench
Large Utility Sorting on FPGAs
AXI over Ethernet; a protocol for the monitoring and control of FPGA clusters
Asymmetric Multi-Processor Architecture for Reconfigurable System-on-Chip and Operating System Abstractions
An embedded in-circuit emulator generator for SOC platform
Co-optimisation of datapath and memory in outer loop pipelining
Characterization of IOBUF-based Ring Oscillators
Concept and implementation of run-time resource management system operating on autonomously reconfigurable architecture
A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning
OpenPipes: Making distributed hardware systems easier
An FPGA-based object detector with dynamic workload balancing
Famous: Flexible Accelerator for the Attention Mechanism of Transformer on Ultrascale+ FPGAs
Reducing the overhead of dynamic partial reconfiguration for multi-mode circuits
FPGA Resource-aware Structured Pruning for Real-Time Neural Networks
Development of a Trax Artificial Intelligence algorithm using path and edge
An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network
Autonomous Driving System implemented on Robot Car using SoC FPGA
Comparing performance, productivity and scalability of the TILT overlay processor to OpenCL HLS
Area constraint propagation in high level synthesis
A memory-based realization of a binarized deep convolutional neural network
Towards a balanced ternary FPGA
Mixing Low-Precision Formats in Multiply-Accumulate Units for DNN Training
ReSim: A reusable library for RTL simulation of dynamic partial reconfiguration
Resource-aware run-time elaboration of behavioural FPGA specifications
International Conference on Field-Programmable Technology, FPT 2018, Naha, Okinawa, Japan, December 10-14, 2018
Defining neighborhood relations for fast spatial-temporal partitioning of applications on reconfigurable architectures
Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computing
HLS-based fault tolerance approach for SRAM-based FPGAs
The Liquid Metal Blokus Duo Design
Cyclic reconfiguration for pipelined applications on coarse-grain reconfigurable circuits
Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration
High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applications
Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware
An autonomous driving system utilizing image processing accelerated by FPGA
Energy-efficient FPGA-accelerated LiDAR-based SLAM for embedded robotics
Checking for Electrical Level Security Threats in Bitstreams for Multi-tenant FPGAs
Hardware SAT Solver-based Area-efficient Accelerator for Autonomous Driving
Fast Boolean matching based on NPN classification
Solving Sudokus through an incidence matrix on an FPGA
Testing for resistive open defects in FPGAs
Side-channel resistant AES architecture utilizing randomized composite field representations
A pure-CMOS nonvolatile multi-context configuration memory for dynamically reconfigurable FPGAs
Maximizing speed and density of tiled FPGA overlays via partitioning
Fast simulation of Digital Spiking Silicon Neuron model employing reconfigurable dataflow computing
Accelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments
Exploring shared SRAM tables among NPN equivalent large LUTs in SRAM-based FPGAs
Efficient key-dependent message authentication in reconfigurable hardware
Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation
FPGA implementation of MFNN for image registration
Fixed-ratio DXT format Frame Buffer Compressor for mobile graphics systems
High Performance Channel Model Hardware Emulator for 802.11n
Simulation of a QCA-based CLB and a multi-CLB application
High-level synthesis of dynamic data structures: A case study using Vivado HLS
An analog reconfiguration-period adjustment technique for optically reconfigurable gate arrays
Memory security in reconfigurable computers: Combining formal verification with monitoring
Accelerating validation of time-triggered automotive systems on FPGAs
FPGA optimized packet-switched NoC using split and merge primitives
Introducing irregularity to routing architecture of structured ASIC for better routability
Efficiently Removing Sparsity for High-Throughput Stream Processing
An FPGA based prototyping platform for imager-on-chip applications
FPGA implementation of Blokus Duo player using hardware/software co-design
Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique
System-level FPGA device driver with high-level synthesis support
Energy Efficient Design of Coarse-Grained Reconfigurable Architectures: Insights, Trends and Challenges
The hardware implementation of a genetic algorithm model with FPGA
FPGA core watermarking based on power signature analysis
A co-design approach for accelerated SQL query processing via FPGA-based data filtering
FPGA timing, power, signal integrity and other challenges at 65 and 45 nm
A datapath classification method for FPGA-based scientific application accelerator systems
Power and the Future FPGA Architectures
Using FPGA to implement a n-channel arbitrary waveform generator with various add-on functions
Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates
SATAY: A Streaming Architecture Toolflow for Accelerating YOLO Models on FPGA Devices
Application-specific customisation of market data feed arbitration
Advanced partial run-time reconfiguration on Spartan-6 FPGAs
Efficient implementation of greyscale morphological filters
Design and implementation of a high performance financial Monte-Carlo simulation engine on an FPGA supercomputer
Stochastic Implementation of Simulated Quantum Annealing on PYNQ
Compiling to FPGAs via an EPIC compiler's intermediate representation
Low Precision Networks for Efficient Inference on FPGAs
Programming a hyper-programmable architecture for networked systems
An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA
QoS-Aware Cross-Layer Reliability-Integrated FPGA-Based Dynamic Partially Reconfigurable System Partitioning
Fast controling autonomous vehicle based on real time image processing
High performance relevance vector machine on HMPSoC
Performing speech recognition on multiple parallel files using continuous hidden Markov models on an FPGA
A State-Serial Viterbi Decoder Architecture for Digital Radio on FPGA
Accelerating signal processing algorithms in digital holography using an FPGA platform
Analyzing the impact of heterogeneous blocks on FPGA placement quality
Improving clock-rate of hard-macro designs
gNBX - reconfigurable hardware acceleration of self-organizing maps
2011 International Conference on Field-Programmable Technology, FPT 2011, New Delhi, India, December 12-14, 2011
A streaming hardware architecture for real-time SIFT feature extraction
Low FPGA area multiplier blocks for full parallel FIR filters
iDEA: A DSP block based FPGA soft processor
Fine-grained characterization of process variation in FPGAs
FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs
Integrated Multi-Ported Memory Distribution for Temporal-Multiplexing Workloads on FPGAs
RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable Devices
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, FPT 2005, 11-14 December 2005, Singapore
Exploring FPGA technology mapping for fracturable LUT minimization
An improved FPGA-based specific processor for Blokus Duo
A low power reconfigurable heterogeneous architecture for a mobile SDR system
Memory security management for reconfigurable embedded systems
On-board satellite image compression using reconfigurable FPGAs
Customizable FPGA-based architecture for video applications in real time
An Approach for Applying Large Filters on Large Images using FPGA
p-VEX: A reconfigurable and extensible softcore VLIW processor
Optimized high-level synthesis of SMT multi-threaded hardware accelerators
Efficient Table-Lookup Inference of Binarized Convolutions with Kernel-Level Binding on FPGA
Optimal FFT Architecture Selection for OFDM Receivers on FPGA
Using C to implement high-efficient computation of dense optical flow on FPGA-accelerated heterogeneous platforms
Accelerated Real-Time Classification of Evolving Data Streams using Adaptive Random Forests
An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming data
Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation
Heuristics for Context-Caches in 2-Level Reconfigurable Architectures
GraphNoC: Graph Neural Networks for Application-Specific FPGA NoC Performance Prediction
Hardware-accelerated execution of Pi-calculus reconfiguration schedules
A state machine block for high-level synthesis
SW and HW co-design of Connect6 accelerator with scalable streaming cores
Very Massive Hardware Merge Sorter
Hardware architecture of bi-cubic convolution interpolation for real-time image scaling
Acceleration of Fast Sample Entropy Towards Biomedical Applications on FPGAs
Respect the Difference: Reinforcement Learning for Heterogeneous FPGA Placement
Identification of Trax threats using pattern matching
An MLIR-Based Compiler for Hardware Acceleration with Recursion Support: (PhD Forum Paper)
StML: Bridging the gap between FPGA design and HDL circuit description
Reconfigurable Acceleration for Monte Carlo Based Financial Simulation
General routing architecture modelling and exploration for modern FPGAs
FPGA Organization for the Fast Path-Based Neural Branch Predictor
Scalable structured data access by combining autonomous memory blocks
An FPGA-Based Infant Monitoring System
Efficient FPGA-based Accelerator for Post-Processing in Object Detection
Implementation of Gabor-Type Filters on Field Programmable Gate Arrays
FPGA architecture extensions for preemptive multitasking and hardware defragmentation
Hardware module reuse and runtime assembly for dynamic management of reconfigurable resources
Development of a Control Target Recognition for Autonomous Vehicle Using FPGA with Python
Investigating How Hardware Architectures are Expressed in High-Level Languages for an SKA Algorithm
FPGA acceleration of TreePM N-body simulations for Modified Newton Dynamics
Behavioral-level IP integration in high-level synthesis
Floating-point mixed-radix FFT core generation for FPGA and comparison with GPU and CPU
The feasibility study of designing a FPGA multiplier-core on finite field
A flexible interface architecture for reconfigurable coprocessors in embedded multicore systems using PCIe Single-root I/O virtualization
FPGA implementation of hierarchical memory architecture for network processors
Bandwidth Efficient Homomorphic Encrypted Matrix Vector Multiplication Accelerator on FPGA
Real-time detection of line segments on FPGA
Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor
DSLUT: An Asymmetric LUT and its Automatic Design Flow Based on Practical Functions
Approaching overhead-free execution on FPGA soft-processors
Objective-driven workload allocation in heterogeneous computing systems
Real-time 3D reconstruction for FPGAs: A case study for evaluating the performance, area, and programmability trade-offs of the Altera OpenCL SDK
Design space exploration with A Stream Compiler
2014 International Conference on Field-Programmable Technology, FPT 2014, Shanghai, China, December 10-12, 2014
FPGA Core Network Implementation and Optimization: A Case Study
Efficient 4-input LUTs FPGA implementation of combinatorial multiplier over canonical base GF(16)
A novel architecture for a secure update of cryptographic engines on trusted platform module
Enhancing communication on automotive networks using data layer extensions
A robust reconfigurable logic device based on less configuration memory logic cell
A Highly Customizable and Efficient Hardware Implementation for Parallel Matrix Inversion
Comparing the bitstreams of applications specified in Hardware Join Java and HandelC
A fine-grained reconfigurable logic array based on double gate transistors
In search for better silicon and human efficiency
Using function folding to improve silicon efficiency of reconfigurable arithmetic arrays
Streaming sorting network based BWT acceleration on FPGA for lossless compression
A reconfigurable vision system for real-time applications
Accelerator-in-Switch: A Novel Cooperation Framework for FPGAs and GPUs
The Transmogrifier-4: An FPGA-Based Hardware Development System with Multi-Gigabyte Memory Capacity and High Host and Memory Bandwidth
Compiler-Directed Design Space Exploration for Caching and Prefetching Data in High-Level Synthesis
Bitwidth-optimized hardware accelerators with software fallback
Trax solver on Zynq with Deep Q-Network
An Energy-Efficient K-means Clustering FPGA Accelerator via Most-Significant Digit First Arithmetic
FPGA implementation of a real-time super-resolution system using a convolutional neural network
Have GPUs Made FPGAs Redundant in the Field of Video Processing?
An automated flow for the High Level Synthesis of coarse grained parallel applications
Performance-driven recursive multi-level clustering
Incremental programming for reconfigurable engines
A leakage aware design methodology for power-gated programmable architectures
Modeling of glitch effects in FPGA based arithmetic circuits
An FPGA implementation of a modified version of RED algorithm
IC security evaluation against fault injection attack based on FPGA emulation
Correlation-Based Fingerprint Matching Using FPGAs
A novel design flow for tamper-resistant self-healing properties of FPGA devices without configuration readback capability
Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method
A partially reconfigurable architecture supporting hardware threads
Multiple data set reduction on FPGAs
2007 International Conference on Field-Programmable Technology, ICFPT 2007, Kitakyushu, Japan, December 12-14, 2007
Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs
FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm
Reconfigurable computing - evolution of Von Neumann architecture
Hardware channel model for ultra wideband systems
An acceleration method of short read mapping using FPGA
Designing and accelerating spiking neural networks using OpenCL for FPGAs
Accelerating transfer entropy computation
Decoy circuits for FPGA design protection
Parallelizing FPGA placement using Transactional Memory
Spatiotemporal Simulation of a Single Living Cell
Achieving higher performance of memcached by caching at network interface
A field-customizable and runtime-adaptable microarchitecture
An FPGA implementation of full-search variable block size motion estimation
Swift: A Multi-FPGA Framework for Scaling Up Accelerated Graph Analytics
Enriching C-based High-Level Synthesis with parallel pattern templates
Abstractions and primitives enabling runtime resource allocation for dynamic IP cores using virtual platform FPGAs
Assessing scrubbing techniques for Xilinx SRAM-based FPGAs in space applications
Multiqueue-Based FPGA Routing: Relaxed A* Priority Ordering for Improved Parallelism
A flexible DSP block to enhance FPGA arithmetic performance
Analysis of transient voltage fluctuations in FPGAs
Sensitivity of FPGA power evaluation
Debug methodology for arithmetic circuits on FPGAs
Synthesis of a unified unit for evaluating an application-specific set of elementary functions
Efficient DSP Packing Method for Neural Network Accelerator
An FPGA Connect6 Solver with a two-stage pipelined evaluation
Novel reconfigurable hardware implementation of polynomial matrix/vector multiplications
A hardware acceleration of a phylogenetic tree reconstruction with maximum parsimony algorithm using FPGA
FPGA Implementation of Low-Latency Recursive Median Filter
HBMalloc: Dynamic Memory Management in High-Level Synthesis for FPGA HBM
An FPGA-based re-configurable 24-bit 96kHz sigma-delta audio DAC
High performance Deformable Part Model accelerator based on FPGA
PERG: A scalable FPGA-based pattern-matching engine with consolidated Bloomier filters
A moving object extraction and classification system based on Zynq and IBM SuperVessel
An FPGA-based specific processor for Blokus Duo
A light-weight hardware/software co-design for pairing-based cryptography with low power and energy consumption
A compression method for inverted index and its FPGA-based decompression solution
Real-Time Object Detection and Semantic Segmentation Hardware System with Deep Learning Networks
Partial reconfiguration logic synthesis by temporal slicing
CarlOthello : An FPGA-Based Monte Carlo Othello player
A fully-pipelined expectation-maximization engine for Gaussian Mixture Models
Design and Implementation of an FPGA Architecture for High-Speed Network Feature Extraction
An open source PXIe ecosystem based on FPGA modules
Reconfigurable array for transcendental functions calculation
A study of adaptable co-processors for Cyclic Redundancy Check on an FPGA
StateLink: FPGA System Debugging via Flexible Simulation/Hardware Integration
An FPGA implementation of a threat-based strategy for Connect6
Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays
Lowering dynamic power in stream-based harris corner detection architecture
Double precision floating-point arithmetic on FPGAs
Hardware design of a fast, parallel Random Tree path planner
Hybrid hard NoCs for efficient FPGA communication
A Deep-Learning Data-Driven Approach for Reducing FPGA Routing Runtimes
A High-Precision Flexible Symmetry-Aware Architecture for Element-Wise Activation Functions
A hardware security module for quadrotor communication
A Tenant Side Compilation Solution for Cloud FPGA Deployment
Operational mode exploration for reconfigurable systems with multiple applications
A complementary architecture for high-speed true random number generator
ZCluster: A Zynq-based Hadoop cluster
An approach to realize time-sharing of flip-flops in time-multiplexed FPGAs
Task Placement for Heterogeneous Reconfigurable Architectures
FPGA-based acceleration of FDAS module using OpenCL
A Short-Transfer Model for Tightly-Coupled CPU-FPGA Platforms
AMAH-Flex: A Modular and Highly Flexible Tool for Generating Relocatable Systems on FPGAs
An architecture for asynchronous FPGAs
Optimize MinMax algorithm to solve Blokus Duo game by HDL
Obstacle-free two-dimensional online-routing for run-time reconfigurable FPGA-based systems
Implementations of Reconfigurable Logic Arrays on FPGAs
A floating-point solver for band structured linear equations
Dynamic scheduling of voter checks in FPGA-based TMR systems
Runtime hardware/software task transition scheduling for data-adaptable embedded systems
A low latency kernel recursive least squares processor using FPGA technology
Scheduling Algorithms for High Performance Network Switching on FPGAs: A Survey
Optimizing time and space multiplexed computation in a dynamically reconfigurable processor
Pipelined high precision beamforming delay calculator for ultrasound imaging
Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storages
True random number generation in block memories of reconfigurable devices
Implementation of an Autonomous Driving System for FPT2018 FPGA Design Competition Using the Zynqberry Processing Board
Low complexity and hardware-friendly spectral modular multiplication
An adaptive virtual overlay for fast trigger insertion for FPGA debug
Bayesian digital terrain model reconstruction on Virtex-II FPGA
Packets everywhere: The great opportunity for field programmable technology
Image processing by A 0.3V 2MW coarse-grained reconfigurable accelerator CMA-SOTB with a solar battery
Evaluation of variable precision computing with variable precision FFT implementation on FPGA
A 64-context MEMS optically reconfigurable gate array
Lattice-Based Scheduling for Multi-FPGA Systems
Size aware placement for island style FPGAs
Asymmetry in Butterfly Fat Tree FPGA NoC
Wave-pipelined signaling for on-FPGA communication
A comprehensive hardware/software infrastructure for IP cores design protection
A Multiprocessor System-on-Chip Implementation of a Laser-based Transparency Meter on an FPGA
Fuzzy modular multiplication architecture and low complexity IPR-protection for FPGA technology
A unified emulation/simulation environment for reconfigurable system-on-chip development
Derivation of efficient FSM from loop nests
Scalable acceleration of inductive logic programs
Run-Time Management of Reconfigurable Hardware Tasks Using Embedded Linux
A Highly Parallel FPGA based IEEE-754 Compliant Double-Precision Binary Floating-Point Multiplication Algorithm
A Parameterized Floating-Point Exponential Function for FPGAs
A VLIW softcore processor with dynamically adjustable issue-slots
Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow Clusters
Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits
High Throughput CNN Accelerator Design Based on FPGA
A Portable Memory Access Framework on Reconfigurable Computers
FPGA Trax Solver based on a neural network design
Minimizing the error: A study of the implementation of an Integer Split-Radix FFT on an FPGA for medical imaging