yusuke1997/dblp-id-title huggingface dataset:
FlexACC: A Programmable Accelerator with Application-Specific ISA for Flexible Deep Neural Network Inference
Compiling Image Processing Applications to Reconfigurable Hardware
ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation
Integer and floating-point constant multipliers for FPGAs
Migration-aware loop retiming for STT-RAM based hybrid cache for embedded systems
Systolic evaluation of functions: Digit-level algorithm and realization
Optimal mapping of systolic algorithms by regular instruction shifts
Application Specific Transistor Sizing for Low Power Full Adders
Determining longest common subsequences of two sequences on a linear array of processors
A practical constant time sorting network
Logic Models Supporting the Design of MOBILE-based RTD Circuits
Architectures for lattice structure based orthonormal discrete wavelet transforms
Timing speculation-aware instruction set extension for resource-constrained embedded systems
A simple expert system for the reasoning of systolic designs
Completeness of automatically generated instruction selectors
A formal design methodology for parallel architectures
OpenCL-based erasure coding on heterogeneous architectures
Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of x
P3FSM: Portable Predictive Pattern Matching Finite State Machine
LLM Based End-to-end Branch Predictor Optimization Generator
A Component Architecture for FPGA-Based, DSP System Design
Fast linear Hough transform
CHIME: Energy-Efficient STT-RAM-Based Concurrent Hierarchical In-Memory Processing
Systolic normalization of rational numbers
The MGAP's programming environment and the *C++ language
A Visual Computing Environment for Very Large Scale Biomolecular Modeling
Artificial Deadlock Detection in Process Networks for ECLIPSE
Optimal design-space exploration of streaming applications
Combining GPU and FPGA technology for efficient exhaustive interaction analysis in GWAS
Power, Performance and Area Consequences of Multi-Context Support in CGRAs
Rapid estimation of instruction cache hit rates using loop profiling
IMEC: A Memory-Efficient Convolution Algorithm For Quantised Neural Network Accelerators
SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC
Design of a high performance FPGA based fault injector for real-time safety-critical systems
FAQ: A Flexible Accelerator for Q-Learning with Configurable Environment
Event-Based Re-configurable Hierarchical Processors for Smart Image Sensors
Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes
An efficient real-time data pipeline for the CHIME Pathfinder radio telescope X-engine
Acceleration of Frequent Itemset Mining on FPGA using SDAccel and Vivado HLS
Real-time FPGA-implementation for blue-sky Detection
Accelerating K-means clustering on a tightly-coupled processor-FPGA heterogeneous system
Synthesis of application-specific multiprocessor systems including memory components
An Efficient Disk-Array-Based Server Design for a Multicast Video Streaming System
A decoupled access/execute processor for matrix algorithms: architecture and programming
PERMAP: A performance-aware mapping for application-specific SoCs
A High-Rate, Low-Power, ASIC Speech Decoder Using Finite State Transducers
A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors
Domain-specific augmentations for High-Level Synthesis
GPU Acceleration of Advanced k-mer Counting for Computational Genomics
A Parallel-friendly Majority Gate to Accelerate In-memory Computation
Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control
Eliminating Sorting in IP Lookup Devices using Partitioned Table
Architecture model for approximate tandem repeat detection
MicRun: A framework for scale-free graph algorithms on SIMD architecture of the Xeon Phi
Modular Multiplication for FPGA Implementation of the IDEA Block Cipher
A Compile Time Based Approach for Solving Out-of-Order Communication in Kahn Process Networks
A Low Power Branch Prediction for Deep Learning on RISC-V Processor
HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis
A distributed CPU-GPU framework for pairwise alignments on large-scale sequence datasets
A Customized Processing-in-Memory Architecture for Biological Sequence Alignment
Mapping Monte Carlo-Metropolis algorithm onto a double ring architecture
Complex Square Root with Operand Prescaling
A Programmable Processor for Approximate String Matching with High Throughput Rate
A Design Methodology for Post-Moore's Law Accelerators: The Case of a Photonic Neuromorphic Processor
A Low Power High Performance Radix-4 Approximate Squaring Circuit
OpenVX Graph Optimization for Visual Processor Units
Real-Time High-Quality Stereo Matching System on a GPU
Algorithm and Hardware Co-Design for FPGA Acceleration of Hamiltonian Monte Carlo Based No-U-Turn Sampler
Real Processing-in-Memory with Memristive Memory Processing Unit (mMPU)
Parallel Stateful Logic in RRAM: Theoretical Analysis and Arithmetic Design
Simple Instruction-Set Computer for Area and Energy-Sensitive IoT Edge Devices
PAI-FCNN: FPGA Based Inference System for Complex CNN Models
Efficient Floating-Point Implementation of the Probit Function on FPGAs
A Processor for Staggered Interval Arithmetic
A massively parallel implementation of the watershed based on cellular automata
HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming
Design space exploration of parametric pipelined designs
FPGA-based lossless compressors of floating-point data streams to enhance memory bandwidth
Quantitative Analysis of Embedded FPGA-Architectures for Arithmetic
A high-performance, low-power linear algebra core
Fast custom instruction identification by convex subgraph enumeration
A Retargetable Framework for Automated Discovery of Custom Instructions
Temporal frequent value locality
Software Configurable Processors
An efficient embedded processor for object detection using ASIP methodology
Sparstition: A Partitioning Scheme for Large-Scale Sparse Matrix Vector Multiplication on FPGA
Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm
An Overview of Systolic Array Concepts and Applications for Linear Algebra and Signal Processing
Aspect driven compilation for dataflow designs
LightSpMV: Faster CSR-based sparse matrix-vector multiplication on CUDA-enabled GPUs
High parallel variation Banyan network based permutation network for reconfigurable LDPC decoder
Matrix Engine for Signal Processing Applications Using the Logarithmic Number System
Design and Implementation of a Parallel Image Processor Chip for a SIMD Array Processor
High-throughput area-efficient processor for 3GPP LTE cryptographic core algorithms
Memory Access Acceleration Through Architecture Design for Edge SoCs
Performance optimization of Jacobi stencil algorithms based on POWER8 architecture
Instruction Stream Mutation for Non-Deterministic Processors
Voltage Range Evaluation of An Optically Reconfigurable Gate Array VLSI
GISP: A Transparent Superpage Support Framework for Linux
Combining Clock and Voltage Noise Countermeasures Against Power Side-Channel Analysis
High-Radix Logarithm with Selection by Rounding
The PAPRICA SIMD array: Critical reviews and perspectives
Simple 4-Bit Processor Based On Quantum-Dot Cellular Automata (QCA)
Towards a Framework for System-Level Design of Multiprocessor SoC Platforms for Media Processing
On energy efficiency of reconfigurable systems with run-time partial reconfiguration
HelmGemm: Managing GPUs and FPGAs for Transprecision GEMM Workloads in Containerized Environments
A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications
A New FFT Architecture and Chip Design for Motion Compensation based on Phase Correlation
Table-based polynomials for fast hardware function evaluation
The Processing Graph Method Tool (PGMT)
A Quantitative Approach for Refactoring NFV-based Mobile Core Networks
Architectural Extensions for Elliptic Curve Cryptography over GF(2 m ) on 8-bit Microprocessors
Reduced Power Consumption for MPEG Decoding with LNS
Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures
A fast and accurate logarithm accelerator for scientific applications
Hardware-accelerated CCD readout smear correction for Fast Solar Polarimeter
CGRA-ME: An Open-Source Framework for CGRA Architecture and CAD Research : (Invited Paper)
Revisiting the Decomposition of Karp, Miller and Winograd
A graph-based approach to map matrix algorithms onto local-access processor arrays
A metamorphotic Network-on-Chip for various types of parallel applications
Adaptively Banded Smith-Waterman Algorithm for Long Reads and Its Hardware Accelerator
Customisable Control Policy Learning for Robotics
Dynamic-SIMD for lens distortion compensation
OpenASIP 2.0: Co-Design Toolset for RISC-V Application-Specific Instruction-Set Processors
Dual-rail active protection system against side-channel analysis in FPGAs
20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2009, July 7-9, 2009, Boston, MA, USA
Run-Time Detection of Malwares via Dynamic Control-Flow Inspection
A practical runtime test method for parallel lattice-gas automata
High Level Modeling for Parallel Executions of Nested Loop Algorithms
An Efficient Real-Time Object Detection Framework on Resource-Constricted Hardware Devices via Software and Hardware Co-design
Fault tolerant matrix triangularization and solution of linear systems of equations
Solving Maxwell's Equations with Modern C++ and SYCL: A Case Study
A highly-parallel match architecture for AI production systems using application-specific associative matching processors
Communication-Centric SoC Design for Nanoscale Domain
Synthesisable recursion for C++ HLS tools
The case for application specific computing
Edge-disjoint spanning trees in the line graph of hypercubes
A Processor-Time-Minimal Schedule for 3D Rectilinear Mesh Algorithms
Function flattening for lease-based, information-leak-free systems
A real-time implementation of the Total Focusing Method for rapid and precise diagnostic in non destructive evaluation
Resource constrained scheduling of uniform algorithm
Application-specific coprocessor computer architecture
A Residue Logarithmic Number System ALU using interpolation and cotransformation
Decimal Floating-Point Square Root Using Newton-Raphson Iteration
ASP modules: building-blocks for application-specific massively parallel processors
Statistical Performance Prediction for Multicore Applications Based on Scalability Characteristics
I/O data management on SIMD systolic arrays
An FPGA architecture for CABAC decoding in manycore systems
3D stacked wide-operand adders: A case study
FPGA-based PairHMM Forward Algorithm for DNA Variant Calling
VLSI array synthesis for polynomial GCD computation
Customizing Reconfigurable On-Chip Crossbar Scheduler
Precision Adaptation for Fast and Accurate Polynomial Evaluation Generation
On the Advantages of Serial Architectures for Low-Power Reliable Computations
Display power reduction for mobile closed-source games
Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform
An array processor for inner product computations using a Fermat number ALU
On cycle borrowing analyses for interconnected chips driven by clocks having different but commensurable speeds
High-Performance AKAZE Implementation Including Parametrizable and Generic HLS Modules
Hardware support for embedded operating system security
Application Specific Architecture for Hardware Accelerating HOG-SVM to Achieve High Throughput on HD Frames
Systolic architectures for decoding Reed-Solomon codes
Bit-level systolic algorithm for the symmetric eigenvalue problem
$k$-Way In-Place Merge by CPU-GPU Cooperative Processing
Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers
On the Removal of Anti and Output Dependences
Behavioral specification of control interface for signal processing applications
Dynamically reconfigurable regular expression matching architecture
On-chip networks for mixed-criticality systems
Synthesis of dedicated SIMD processors
Configurable Computing Platforms - Promises, Promises
Area optimized H.264 Intra prediction architecture for 1080p HD resolution
2006 IEEE International Conference on Application-Specific Systems, Architecture and Processors (ASAP 2006), 11-13 September 2006, Steamboat Springs, Colorado, USA
Verification of regular architectures using ALPHA: a case study
Dual-Processor Design of Energy Efficient Fault-Tolerant System
Training Neural Nets using only an Approximate Tableless LNS ALU
FPGA-based hardware accelerator of the heat equation with applications on infrared thermography
A Triplet-based Computer Architecture Supporting Parallel Object Computing
Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture
An application specific processor for implementing stack filters
Polynomial Evaluation on Multimedia Processors
The naive execution of affine recurrence equations
Bank-selective Strategy for Gate-based Ternary Content-addressable Memory on FPGAs
An Energy-Delay Efficient Subword Permutation Unit
Exploration Framework for IDS Optimization on FPGA
PASIC. A sensor/processor array for computer vision
RNS modular multiplication through reduced base extensions
A Generic Multi-Phase On-Chip Traffic Generation Environment
Low discrepancy sequences for Monte Carlo simulations on reconfigurable platforms
Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA
Virtual Circuit-Switching Network with Flexible Topology for High-Performance FPGA Cluster
Transformation techniques for serial array design
PAMA: Large-Scale GNN Acceleration with Pre-Aggregation in Multi-Node Architecture
Multi-task support for security-enabled embedded processors
A formal specification of fault-tolerance in prospecting asteroid mission with Reactive Autonomie Systems Framework
Meta-implementation of vectorized logarithm function in binary floating-point arithmetic
Automatic frame rate-based DVFS of game
A Programmable Architecture for Robot Motion Planning Acceleration
Memory-aware Efficient Deep Learning Mechanism for IoT Devices
Selective validations for efficient protections on Coarse-Grained Reconfigurable Architectures
Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT
Arbitrary Bit Permutations in One or Two Cycles
Efficient custom instruction enumeration for extensible processors
A Flexible Motion Estimation Chip for Variable Size Block Matching
Real-Time and Approximate Iterative Optical Flow Implementation on Low-Power Embedded CPUs
Performance Estimation of Deeply Pipelined Fluid Simulation on Multiple FPGAs with High-speed Communication Subsystem
Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis
PreCog: Near-Storage Accelerator for Heterogeneous CNN Inference
The 1D Discrete Cosine Transform For Large Point Sizes Implemented On Reconfigurable Hardware
Complex Fixed-Point Matrix Inversion Using Transport Triggered Architecture
SimPyler: A Compiler-Based Simulation Framework for Machine Learning Accelerators
Efficient Architectures and Implementation of Arithmetic Functions Approximation Based Stochastic Computing
19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium
Sparse Matrix to Matrix Multiplication: A Representation and Architecture for Acceleration
Efficient 1D Grouped Convolution for PyTorch a Case Study: Fast On-Device Fine-Tuning for SqueezeBERT
Motion Estimation Algorithms on Fine Grain Array Processor
Energy-Efficient Near-Sensor Convolution using Pulsed Unary Processing
Combining Fixed-Point and SORN Arithmetic in a MIMO BPSK-Symbol Detection Architecture
Spatzformer: An Efficient Reconfigurable Dual-Core RISC-V V Cluster for Mixed Scalar-Vector Workloads
How to Reach Real-Time AI on Consumer Devices? Solutions for Programmable and Custom Architectures
Optimal design of lower dimensional processor arrays for uniform recurrences
1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland
FMM-X3D: FPGA-Based Modeling and Mapping of X3D for Human Action Recognition
SpiRec: Soft-Logic Architecture Exploration of Reconfigurable Systems for Spiking Neural Networks
Loop transformations for interface-based hierarchies IN SDF graphs
Design space exploration for an embedded processor with flexible datapath interconnect
Modeling and evaluation for gather/scatter operations in Vector-SIMD architectures
Data flow graphs granularity for overhead reduction within a PE in multiprocessor systems
Real-Time Zero-Day Intrusion Detection System for Automotive Controller Area Network on FPGAs
BitShare: An Efficient Precision-Scalable Accelerator with Combining-Like-Terms GEMM
On metrics of 'super performance' [signal processing systems]
28th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2017, Seattle, WA, USA, July 10-12, 2017
A Suite of Division Algorithms for Posit Arithmetic
Analog VLSI arrays for morphological image processing
Efficient Finite Field Serial/Parallel Multiplication
Implementation of binary edwards curves for very-constrained devices
Instruction Set Architecture Enhancements for Video Processing
Optimizing Grouped Convolutions on Edge Devices
MDCRA: A Reconfigurable Accelerator Framework for Multiple Dataflow Lanes
An efficient VLSI architecture for digital geometry
Efficient scalable architectures for Viterbi decoders
Partial Expansion Graphs: Exposing Parallelism and Dynamic Scheduling Opportunities for DSP Applications
Systolic architecture for adaptive eigenstructure decomposition based on simultaneous iteration method
Constant capacity signal flow signal processor architecture benchmark
Realization of a nonlinear digital filter on a DSP array processor
A real-time software programmable processor for HDTV and stereo scope signals
On-line Multioperand Addition Based on On-line Full Adders
DeepPump: Multi-pumping deep Neural Networks
A dedicated circuit for charged particles simulation using the Monte Carlo method
Fast and efficient implementation of Convolutional Neural Networks on FPGA
Bit Permutation Instructions for Accelerating Software Cryptography
Lightweight DMA management mechanisms for multiprocessors on FPGA
Optimizing Behavioral Near On-Chip Memory Computing Systems
Reconfigurable acceleration of fitness evaluation in trading strategies
Accelerating Path Planning for Autonomous Driving with Hardware-Assisted Memorization
Nanocomputing with Delays
A Full-System Approach to Multi-Valued Logic Design: (PhD Forum Paper)
A Template-based Framework for Exploring Coarse-Grained Reconfigurable Architectures
Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals
A 64-bit Decimal Floating-Point Comparator
Domain-specific processor with 3D integration for medical image processing
Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications
AIRES: Accelerating Out-of-Core GCNs via Algorithm-System Co-Design
Processing of variable size images on a cellular array: Performance analysis with the Abingdon Cross Benchmark
Matrix computations in arrays of DSPs
Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit
On-Chip Lookup Tables for Fast Symmetric-Key Encryption
Fault-tolerant dynamically reconfigurable NoC-based SoC
FPGA-Accelerated Time Series Mining on Low-Power IoT Devices
Two-level tiling for MPSoC architecture
(M, p, k)-Friendly Points: A Table-Based Method for Trigonometric Function Evaluation
Implementing decimal floating-point arithmetic through binary: Some suggestions
BlueDBM: A multi-access, distributed flash store for Big Data analytics
FPGA SAR Processor with Window Memory Accesses
Access and alignment of arrays for a bidimensional parallel memory
Monitoring and Debugging a Hard Real-Time Distributed Computer for Aircraft Industry
OpenCGRA: Democratizing Coarse-Grained Reconfigurable Arrays
ImpEDE: A multidimensional design-space exploration framework for biomedical-implant processors
Design and implementation of a belief propagation detector for sparse channels
Evaluating Hardware Support for Reference Counting Using Software Configurable Processors
A Linear Algebra Core Design for Efficient Level-3 BLAS
Viterbi Accelerator for Embedded Processor Datapaths
A projective geometry architecture for scientific computation
A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors
Scheduling partitioned algorithms on processor arrays with limited communication supports
Interface Design for Mapping a Variety of RSA Exponentiation Algorithms on a HW/SW Co-design Platform
Register transfer modeling and simulation for array processors
MOVIE: A Building Block for the Design of Real Time Simulator of Moving Pictures Compression Algorithms
Design Automation Framework for Application-Specific Logic-in-Memory Blocks
A TSP engine for performing tabu search
Decentralized dynamic resource management support for massively parallel processor arrays
Bio-Inspired Event Cameras for Robust Edge System in Challenging Environments
Microphone Array for Hearing Aid and Speech Enhancement Applications
Modeling and synthesis of communication subsystems for loop accelerator pipelines
A C++-embedded Domain-Specific Language for programming the MORA soft processor array
MITRACA: Manycore Interlinked Torus Reconfigurable Accelerator Architecture
Assessing Robustness of Hyperdimensional Computing Against Errors in Associative Memory : (Invited Paper)
Raising Compute Density of Molecular Dynamics Simulation Through Approximate Memoization
RVNet: A fast and high energy efficiency network packet processing system on RISC-V
A design method for on-line reconfigurable array processors
Novel Multi-Layer Network Decomposition boosting acceleration of multi-core algorithms
A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture
The Logic Description Generator
Optimal synthesis of application specific heterogeneous pipelined multiprocessors
Integral Parallel Architecture & Berkeley's Motifs
A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes
Parallel array architectures for motion estimation
GPU acceleration of Data Assembly in Finite Element Methods and its energy implications
CATERPILLAR: Coarse Grain Reconfigurable Architecture for accelerating the training of Deep Neural Networks
Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal Systems
Algorithms and architectures for hierarchical compression of video
Hardwiring the OS kernel into a Java application processor
soft-NEON: A study on replacing the NEON engine of an ARM SoC with a reconfigurable fabric
Molecular Dynamics Range-Limited Force Evaluation Optimized for FPGAs
Hamamu: Specializing FPGAs for ML Applications by Adding Hard Matrix Multiplier Blocks
A prototype for a fault tolerant parallel digital signal processor
Comparing the robustness of fault-tolerant enhancements when applied to lookup tables and random logic for nano-computing
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter
A new high-performance scalable dynamic interconnection for FPGA-based reconfigurable systems
Embedding pyramids in array processors with pipelined busses
Automatic Generation of Modular Mappings
RELACS for systolic programming
Challenges in the Design of Security-Aware Processors
An embedded scalable linear model predictive hardware-based controller using ADMM
The tunnel vision syndrome: Massively delaying progress
Mapping algorithms onto the TUT cellular array processor
A Reading Comprehension Style Question Answering Model Based On Attention Mechanism
Hardware Acceleration for 3-D Radiation Dose Calculation
A Packet Scheduling Algorithm for IPSec Multi-Accelerator Based Systems