yusuke1997/dblp-id-title huggingface dataset:
Parameter identification of a DC motor: an experimental approach
Memory addressing organization for stream-based reconfigurable computing
An embedded IDDQ testing circuit and technique
Validation and analysis of negative differential resistance of single-electron transistor with conductance model
A Low Power 16 Gbps CTLE and Quarter-Rate DFE With Single Adaptive System
Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os
A 2.77μW, 80 ppm/°C Temperature Coefficient Voltage Reference for Biomedical Implants
A Hardware-Friendly and Configurable Heuristic Targeting VVC Inter-Frame Prediction
Cell biasing and balancing in E-cell based single-ended log filters
Solving constraints in FPGA detailed routing using SMT
Delay-Locked Loop Based Multiphase Clock Generator for Time-Interleaved ADCs
A topological approach for determining the uniqueness of the DC solution
Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication
Accurate models for Frequency Synthesizers
The dynamic supervised forward-propagation neural network for handwritten character recognition using Fourier descriptors and incremental training
LMI based stability analysis for 2D continuous systems
Global exponential stability of Cohen-Grossberg neural networks with multiple time-varying delays
13th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2006, Nice, France, December 10-13, 2006
An efficient time step control method in transient simulation for DAE system
A charge sampling baseband filter using a new high linearity Gm for multimode receiver
Turbo-decoder synchronisation procedure: application to the CAS5093 integrated circuit
Simulation study for routing protocols in sensor networks
Router buffering and caching techniques for multisession reliable multicast
Mixed signal decoder for audio frequency applications
Short-circuit energy dissipation model for sub-100nm CMOS buffers
Hierarchical energy monitoring for many-core systems
Model of tilt sensor system
FPGA-based architecture for real-time synaptic plasticity computation
An all digital phase-locked loop with modified binary search of frequency acquisition
Temperature dependence of the programmed states in GST-based multilevel phase-change memories
Improved linearity CMOS active resistor based on complementary computational circuits
Finding the Number of Clusters in a Dataset Using an Information Theoretic Hierarchical Algorithm
A hybrid approach to design error detection and correction [VLSI digital circuits]
A fully complementary and fully differential self-biased asynchronous CMOS comparator
Thermal Noise Analysis of Accumulation-based S/H Circuit for Shunt Current Sensing
Enhanced genetic algorithm kernel applied to a circuit-level optimization E-design environment
On the receiver system feasibility for mobile DVB - S applications in the Ku - band (10.7 - 12.75 GHz)
Object-oriented approach to video compression via Cellular Neural Networks
New Design Paradigms: New Architectures for New technologies
Detection-based video surveillance using Deep Neural Networks on STM32 microcontroller
A combined FPAA-FPGA platform for mixed-signals design space exploration
Optimal cooperative primary user localization in Cognitive Radio networks
A wire segment reassignment algorithm for minimizing crosstalk for strait-type river routing
Synchronization of chaotic Colpitts oscillators with applications to binary communications
A design procedure for 2-channel mixed analog and digital filter banks for A/D conversion using minimax optimization
On a Multiplierless FIR Decimation Filter Design
A modular approach for high Q microwave CMOS active inductor design
Automatic impedance control for chip-to-chip interconnections
A short gate length pseudomorphic HEMT process for mm wave applications
Universal eight-port RC network
Characterization of the allowable perturbations for disturbance rejection and data sensitivity
Fuzzy adaptive control: a hyperstability approach
A programmable active-RC complex filter for wireless communications
Design and implication of a rule based weight sparsity module in HTM spatial pooler
Control strategy of a solar power inverter (analysis of a seventh order system-II)
A complete behavioral system model for a novel phase shifter technique
Interference cancellation in multi-path CDMA systems
A Comparative Study of Noise Behavior in Single-Opamp Resonators in Delta-Sigma Modulators
Performance of 155Mbps clock/data recovery circuits on heavy loaded PLDs
Complex mismatch shaper for tree-structured DAC in multi-bit complex sigma-delta modulators
A multipurpose testbed for full-duplex wireless communications
Phoneme classification in hardware implemented neural networks
Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuits
A 4Gb/s CMOS fully-differential analog dual delay-locked loop clock/data recovery circuit
A Low-Power Multi-Frequency Chopper-Stabilized Readout with Time-Domain Delta-Sigma Modulator Suitable for Neural Recording
Control of saturated systems with sliding mode
Analysis of clock distribution networks in the presence of crosstalk and groundbounce
Digital testing and reliability education (DTRE) computer tool
A Low Power and Smart Power Unit for Kinetic Self-Sustainable Wearable Devices
New reader anti-collision algorithm for dense RFID environments
3D floorplanning with nets-to-TSVs assignment
A Squarewave-Based Multi-Frequency Impedance Analyzer Based on the Heterodyne Architecture
Efficient Sequence Generation for Hardware Verification Using Machine Learning
Algorithm for facial weight-change [image weight-change simulator]
A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor
An RNS modular multiplication algorithm
Fractal image coding combined with subband decomposition
Design Space Exploration for Approximate Implementations of Arithmetic Data Path Primitives
A continuous-time field programmable analog array with 1 GHz GBW
A low-power time-based phase-domain analog-to-digital converter
Design of a rad-hard library of digital cells for space applications
Design of optimum high order crossover coefficients
On the maximum number of DC solutions of general transistor networks
A novel design methodology for multiplierless filters applied on ΔΣ decimators
Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory
Efficient Gabor expansion using non minimal dual Gabor windows
A High Linearity 5-GHz 4-Bit Sub 1ps-DNL Phase Interpolator
Affine-invariant description of keypoint bundles for detecting partial near-duplicates in random images
A PVT Tolerant sub-mA PLL in 65nm CMOS process
Towards an IEEE 802.15.4 SDR transceiver
Efficiency Of Components' Region-Constrained Placement To Reduce FPGA's Dynamic Power Consumption
A Fully-Integrated 60-GHz Voltage-Controlled Oscillator Synchronized by Optoelectronic Signal
An L 2 based method for the design of one dimensional FIR digital filters
On the influence of strong magnetic field on MOS transistors
A Compact 5 GHz Lumped-Element Wilkinson Power Combiner on 28 nm Bulk CMOS
Stochastic Behavior of a CMOS Inverter
A 79dB THD CMOS low power THA circuit using pseudo differential source follower and common-mode management
Towards Efficient and Adaptive Cyber Physical Spiking Neural Integrated Systems
A smart energy extraction interface for electrostatic vibrational energy harvester
General-purpose piecewise-linear DC analysis
An Untrimmed 14-bit Non-Binary SAR-ADC Using 0.37 fF-Capacitors in 180 nm for 1.1 µW at 4 kS/s
A 4 GHz fractional-N frequency synthesizer
A spike-based adaptive filter
A fourth order CMOS band pass filter for PIR sensors
Efficient complex-number multipliers mapped on FPGA
Speech signal processing in order to increase recognition of spoken language
A high-performance active adder
MEMS packaging on a budget (fiscal and thermal)
A high speed and low voltage BiCMOS tristate buffer with positive and negative charge pump
3/2 Fractional Bennet's multiplier for capacitive energy harvesters based on Dickson charge-pump
MMG/EMG Mapping with Reservoir Computing
WineNote: an IoT project to enhance the wine taste
Frame detection in high bit-rate CMOS systems
An Evolutionary Synthesis Algorithm to Design Optimum Performance CMOS RFSSCAs
FPGA Implementation of Area-Time Aware ECC Scalar Multiplication Core
Optimal training sequence length for soft iterative channel estimation
Common mode voltage in DTC drives using matrix converters
Localization using wireless sensing for future healthcare
2×192 Pixel CMOS SPAD-Based Flash LiDAR Sensor with Adjustable Background Rejection
DFTT: Design for Trojan Test
Millimeter-wave high-Q active inductor in 65nm CMOS
Nyquist-criterion based design of a CT ΣΔ-ADC with a reduced number of comparators
MPSoC design of RT control applications based on FPGA SoftCore processors
Design-space exploration of a cryptography algorithm
Project based learning objectives and experiences in electronic education: a memory controller design experiment
A Reading Scheme for 3T3R RRAM and Their Arrays Recognizing 64 States
Power efficient architecture for motion estimation using the QSDS-DIC algorithm
MogaMap: An application of multi-objective genetic algorithm for LUT-based FPGA technology mapping
A product-oriented collaborative program in NCUE to promoting the excellence in education on electronic design technique
Efficient Standard-Cell Legalization for Minimization of Total Movement
Low voltage SC TDM correlator for the extraction of time delay
An evaluation of BTI degradation of 32nm standard cells
Design of divergence-free protocol converters using supervisory control techniques
Synthesis Method for BAW Filters Computation
Neuromorphic Analog Implementation of Reservoir Computing for Machine Learning
Wavelet transform approach to the detection of the breaking point of the transient signal in the circuit
Joint linear multi-sensor reception in downlink TD/CDMA
orBDDs Direct Mapping for Structured Logic Circuits
A Self-tracked High-dielectric Wireless Power Transfer System for Neural Implants
TFMCC-based on a new equation for multicast rate control
Fast elliptic curve cryptographic processor architecture based on three parallel GF(2 k ) bit level pipelined digit serial multipliers
Canonic structures of odd-order elliptic G m -C filters
A CMOS focal-plane retinal sensor designed for shear motion detection
A triple-standard transceiver architecture for GSM, WCDMA and WI-FI applications
Fault-tolerant linear finite state machines
Some thoughts on the word error rate measurement of A/D converters
An analytical approach to the estimation of the spurious-free dynamic range in pipeline A/D converters
Electromigration-dependent parametric yield estimation
Simulating the Effects of Process Variations on Capacitive Crosstalk
Temperature considerations on Hall Effect sensors current-related sensitivity behaviour
Bipolar and CMOS low voltage-supply reduced-power voltage followers
Influence of gate length on the performance of GaAs MESFETs by a physical I-V model
High-speed receivers for on-chip interconnections in deep-submicron process
Fully Integrated CMOS-PMUT Transceiver
High-Efficiency Regulated Charge Pump for Non-Volatile Memories
A 10-Gb/s low-power low-voltage CTLE using gate and bulk driven transistors
A 0.46 nV/√Hz JFET Low-Noise Amplifier for Characterization of Nanoelectrode Coating Materials
Design of a multi-threaded distributed telerobotic framework
A B-s complement continuous valued digit adder
VLSI implementation of CRC-32 for 10 Gigabit Ethernet
A Current Balanced Multi-Phase Class-D Amplifier for Wideband Supply Modulator
General Model for the Deployment of Time-Delay Elements in Transistorized Electronic Circuits
A VCO-free low-power fully digital BPSK demodulator for implantable biomedical microsystems
An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation ADC in 0.18µm CMOS
Investigating Floating-Point Implementations in a Softcore GPU under Radiation-Induced Faults
Hardware implementation of the median-rational hybrid filters
A 150MHz 3rd-order single Opamp continuous-time analog filter in 28nm CMOS technology
A low power fault secure timer implementation based on the Gray encoding scheme
Analytical design of FIR filters
Low power BIN integrator dedicated to neural signal processing
A 2.45GHz power harvesting circuit in 90nm CMOS
Implementation of frequency domain digital filter for speech enhancement
The 1: 10 phased demultiplexer circuit
Synthesis of data transmission circuits starting from behavioral HW descriptions
Visualising Climate Change using Extended Reality: A Review
Low-cost fault-tolerant routing for regular topology NoCs
MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit
A practical method for modeling amplifier nonlinearities
Influence of Refresh Circuits Connected to Low Power Digital Quasi-Floating Gate Designs
15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008
Exploring the range of transitions in idealized switched networks
Optical NoC design-parameters exploration and analysis
Joint Bayesian estimation of DOA and frequency of BPSK (binary phase shift keying) signals in α-stable noise
Design of high gain CMOS LNA with improved linearity using modified derivative superposition
On searching of all occurrences of a word in a string
Active pixel sensor with on-chip normal flow computation on the read out
DEC ECC design to improve memory reliability in Sub-100nm technologies
Optimum bandwidth IIR notch filters with multiple frequency initializations
Enhanced analytical model and output dynamic response of SiPM-Based electronic read-outs
A study on switched-capacitor blocks for reconfigurable ADCs
Single-chip mixed-radix FFT processor for real-time on-board SAR processing
Modeling and simulation of electrical vehicle in VHDL-AMS
A 0.3 V floating-gate differential amplifier input stage with tunable gain
A readout circuit implementation to reduce the flicker noise in MEMS electrothermal sensors
Implementation methodology of acoustic echo cancellation based on FELMS adaptive algorithm
An Integrated Flow for Predicting Radiation Effects in CubeSat Onboard Electronics
Efficient micro-bump assignment for RDL routing in 3DICs
Low voltage low power techniques in design of zero IF CMOS receivers
An efficient synchronization method for OFDM systems in multipath channels
Exploring Approximate Arithmetic Units for a Power-Efficient Kalman Gain VLSI Design
State-of-the-art continuous-time filters from scratch
Pre-Silicon Yield Estimation using Machine Learning Regression
Traceability from "farm to fork" using RFID technology
ILP formulation for hybrid FPGA MPSoCs optimizing performance, area and memory usage
30GHz Amplifiers with 0.25μm SiGe BiCMOS
A Low Power Pulsed Edge-Triggered Latch for Survivor Memory Unit of Viterbi Decoder
SDPPM: An IP traceback scheme for MANET
A 54.8-nW, 256-bit Codeword Temperature-Robust Wake-Up Receiver minimizing False Wake-Ups for Ultra-Low-Power IoT Systems
Power Modeling and Efficient FPGA Implementation of Color Space Conversion
Low harmonic distortion class AB CMOS current output stage
HLS design flow for the synthesis of multimode systems under multiple constraints
Measuring system of the slab's position in a metallurgical plant using artificial vision techniques
Multi-band dual-mode antenna tunable matching network for broadband applications
An adaptive multimedia approach to e-learning
Test setup and spurious replicas identification in time-quantized pseudorandom sampling-based ADC in SDR multistandard receiver
Self-modulation in SISO nonlinear systems with inertial damping described by Duffing equation
Adaptive Compressed Sensing Image Reconstruction Using Binary Measurement Matrices
Novel designs for high-efficiency millimeter-wave zero-bias detectors
System-Level ESD Protection Design with On-Chip Transient Detection Circuit
A 1-mW current reuse quadrature RF front-end for GPS L1 band in 0.18µm CMOS
A low drift, low noise detection IC applied to MEMS gyros
A hybrid event-based pixel for low-power image sensing
Multi-Bank Memory Allocation for Multimedia Application
A 2-GS/s 0.35μm SiGe track-and-hold amplifier with 7-GHz analog bandwidth using a novel input buffer
Expand Reuse Strategy to ESL Power Modeling in SystemC/TLM
Energy scavenging and storage using through silicon vias to reduce power consumption in 3D ICs
Implementation of sign detection in RNS using mixed radix representation
Characterization of Single Event Transient Effects in Standard Delay Cells
A 340 nA/MHz Low Power FLL-based RC Oscillator with < 1.5 % variation from -40 °C to 175 °C
A 1V low-power low-noise biopotential amplifier based on flipped voltage follower
Privacy enhanced access control mechanism for home networks
A novel dynamically programmable arithmetic array using code division multiple access bus
A Dual Phase Charge Pump with Compact Size
Architecture of an Efficient Area and Flexible Multi-CODEC Processor
A 0.35 μm SiGe BiCMOS front end for GSM low IF cellular receiver applications
An analytical model for delay and crosstalk estimation in interconnects under general switching conditions
A Compact Near-Infrared Spectrometer based on an FR4 Electromagnetic Scanning Grating
Combined adaptive system for identification of unknown systems with varying parameters in a noisy environment
Error rate performance analysis of cooperative MRC receivers over generalized fading channels
SystemC-defined SIMD instructions for high performance SoC architectures
A Capacitor Mismatch- and Nonlinearity-Insensitive 1.5-bit Residue Stage for Pipelined ADCs
A Column Streaming-Based Convolution Engine and Mapping Algorithm for CNN-based Edge AI Accelerators
Assistive Cobot for E-Waste Disassembly: Multi-Sensor HRC with Tool Recommendation
A two op-amps third-order ΣΔ modulator with complex conjugate NTF zeros
A test bed for wireless optical LANs
An Integrated Low Drop Out Regulator with Independent Self Biasing Start Up Circuit
Efficient high quality restoration of missing blocks in images
Network-aware resource allocation for cloud elastic applications
Improving effective yield through error tolerant system design
Tamper Resistivity Analysis for Nano-meter LSI with Process Variations
Magnetotactic bacteria as controlled components in microelectronic circuits
Mixed symbolic-numerical techniques in fault diagnosis using fault rubber stamps
CRP: Context-directed Replacement Policy to Improve Cache Performance for Coarse-Grained Reconfigurable Arrays
Considering layout for test scheduling of core-based SoCs
Differential GPS performance: ground versus geostationary satellite
Output feedback sliding mode control of fractional systems
Fullwave-mode analysis of shielded microstrip discontinuities on anisotropic substrates
High level modelling and performance evaluation of address mapping in NAND flash memory
A 100 dB CMRR CMOS operational amplifier with single-supply capability
FPGA implementation of a parameterized Fourier synthesizer
Ultra low voltage semi-floating-gate transconductance amplifier based on binary inverters
An advanced bipolar device-the fully depleted camel structure
Magnetic microsystem with extended dynamic range and absolute accuracy
Threshold-gates in arithmetic circuits
Efficient self-timed circuits based on weak NMOS-trees
Ultra-Low Power Silicon Neuron Circuit for Extreme-Edge Neuromorphic Intelligence
Effective neural network training with a different learning rate for each weight
Current Regulated Matrix Converter for Field Oriented Control of Permanent Magnet Synchronous Machines
Enhanced Arbiter PUFs using custom sized structures for reduced noise sensitivity
Efficient wearable real-time vital signs monitoring system
sMDT Detectors Read-Out in 28nm technology
A restriction on the power system by theoretical requisitions of the BCU method
Computational complexity control for HEVC based on coding tree spatio-temporal correlation
Statistical region measures for separation of figure from ground
Performance Evaluation of FPGA-Embedded Web Servers
Study of two-memristor circuit model with explicit composition method
An ultra-low power consumption 1-V, 10-bit succesive approximation ADC
Current source based standard-cell model for accurate timing analysis of combinational logic cells
AR-based method for change detection using dynamic cumulative sum
Programmable time-multiplexed SC filters without dynamic range degradation
Design flow of a Multi-path Nested Miller Compensation three-stage amplifier: frequency domain and large input signal response
General synthesis method for cylindrical antenna arrays for directive and conformal pattern
Novel Arithmetics to Accelerate Machine Learning Classifiers in Autonomous Driving Applications
K-band SiGe dual-input LNA and detector for SoC radiometers for remote sensing of atmosphere
Challenges in CMOS imager design
Critical path minimized raster scan hardware architecture for computation of the Generalized Hough Transform
Extended CNN topologies and VLSI implementations
A fault diagnosis mechanism for a proactive maintenance scheme for wireless systems
Novel compensated CMOS buffer
Multidimensional matched filters
Combinational verification by simulations, SAT and BDDs
A Fast-Locking Agile Frequency Synthesizer for MIMO Dual-mode WiFi / WiMAX Applications
Space-time trellis code simulator for high data rate wireless communications
A robust and low-power synchronization technique of coarse-and-fine conversion parts in ring-oscillator-based time-to-digital converters
Constant multiplier design using specialized bit pattern adders
Hardware/software co-design of a dynamically configurable SHA-3 System-on-Chip (SoC)
Using efficient adder compressors with a split-radix butterfly hardware architecture for low-power IoT smart sensors
24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017, Batumi, Georgia, December 5-8, 2017
Dual data pulse width modulator for wireless Simultaneous Measurement of Redox Potential and Temperature using a Single RFID Chip
Phase error determination in GMSK modulated fractional-N PLL
Efficient modulo 2 n + 1 multi-operand adders
Exact Analytical Expressions of Graëtz Bridge Currents and Voltages Using Lambert W Function
An ultra low power continuous-time sigma delta modulator
Position Sensing of Electrostatic MEMS Actuator
A new Block-XOR precomputation-based CAM design for low-power embedded system
A Computationally Efficient Model of MEMS Stopper for Reliability Optimization
CMOS Unity-Gain Voltage Amplifier for Low-Voltage Applications
A new non-recursive algorithm for binary search tree traversal
An Integrated LC Oscillator with Self Compensation for Frequency Drift and PVT Corners Variations
Recursive optimization of an extended Fisher discriminant criterion
A new approach for the fractional sample delay filters
A Novel Bootstrapped Switch Design, Applied in a 400 MHz Clocked ΔΣ ADC
Modelling the XOR/XNOR Boolean Functions Complexity Using Neural Network
Design of active-only highpass and bandpass leapfrog filters using multi-current-output differentiators
Impact of a fully reconfigurable LNA on an RF front-end: A system level analysis
Torwards Variability Immune Scalable FeFET-based Macros for IMC DNN Accelerators
Locking techniques for RF oscillators at 5-6 GHz frequency range
Grand challenges in image processing and analysis
Autoassociative memory using refractory period of neurons and its on-line learning
Investigating the Advantages of Magnetomyography in Assistive Healthcare Technology
Two-Archive Evolutionary Algorithm (TAEA)-Based Multi&Many Objective Analog IC Optimization
Electro-Enzymatic Glucose Sensor Using Hybrid Polymer Fabrication Process
An algebraic approach for transistor circuit synthesis
Analog Design Considerations For Independently Driven Double Gate MOSfets And Their Application in a Low-Voltage OTA
New circuit techniques based on a high performance frequency-to-voltage converter
Travelling wave LiNbO 3 electro-optic modulator with quasi-phase-match coplanar waveguide structure for time-domain applications
An original approach for the design of a Class D power switching amplifier - an audio application