yusuke1997/dblp-id-title huggingface dataset:
A General Attribute based RBAC Model for Web Service
Trust-Aware Service Recommendation via Exploiting Social Networks
Drivers for SOA in the Transaction Banking Domain
OdinTools-Model-Driven Development of Intelligent Mobile Services
Automated Pattern-Based Recommendation for Improving API Operation Performance and Reliability in Cloud-Based Architectures
A WSLA-based monitoring system for Grid Service-GSMon
Incomplete Preference-driven Web Service Selection
A Cost-Effective Certification-Based Service Composition for the Cloud
Effective Detection of SQL/XPath Injection Vulnerabilities in Web Services
Discovering Hierarchical Patterns in Event-Based Systems
Promoting Reuse via Extraction of Domain Concepts and Service Abstractions from Design Diagrams
Integrated Topic Modeling and User Interaction Enhanced WebAPI Recommendation using Regularized Matrix Factorization for Mashup Application Development
Research on Business Goal Oriented Process Knowledge Retrieving
Constructing an Authentication Token to Access External Services in Service Aggregation
Fostering Active Learning: A Study on Anonymous Q&A Software in Undergraduate Education
Verifying Semantic Business Process Models in Inter-operation
A Transaction-Oriented Framework for Composing Transactional Web Services
Optimistic Fair-exchange Protocols Based on DSA Signatures
PoEM - Potsdam Encoding for Models
Modelling Sound Conflict Management for Virtual-Enterprise Collaboration
A Resource-Oriented Model for Services Management and Discovering in SOA
Full Solution Indexing Using Database for QoS-Aware Web Service Composition
A Context Model for B2B Collaborations
Analytics on Health of Mobile Software Ecosystem Based on the Internal Operating Mechanism
Private and Anonymous Data Storage and Distribution in Cloud
Reputation-Based Selection of Language Services
Social Engineering in Social Networking Sites: The Art of Impersonation
An Approach for Modeling and Ranking Node-Level Stragglers in Cloud Datacenters
The Research of Link Prediction in Knowledge Graph based on Distance Constraint
Regularizing Matrix Factorization with Implicit User Preference Embeddings for Web API Recommendation
BTx-Net: A Token Based Dynamic Model for Supporting Consistent Collaborative Business Transactions
Toward Mobile Application of Cyber Argumentation with Social Networking
A Design Pattern for Reliable HTTP-Based Applications
XYZ Indoor Navigation through Augmented Reality: A Research in Progress
Fine-Grain, End-to-End Security for Web Service Compositions
Correlating Business Objectives with Services: An Ontology-Driven Approach
Abacus: A Service-Oriented Programming Language for Grid Applications
Cilia: An Autonomic Service Bus for Pervasive Environments
Automatic Composition of Service-Based Image Processing Applications
Columbus: Enabling Scalable Scientific Workflows for Fast Evolving Spatio-Temporal Sensor Data
A System of Systems Service Design for Social Media Analytics
Reducing the Number of Comatose Servers: Automatic Tuning as an Opportunistic Cloud-Service
Large Language Model Aided QoS Prediction for Service Recommendation
IT Service Infrastructure for Integrative Systems Biology
Towards Providing Data Validation as a Service
On the Quantification of Global Team Performance and Profitability
MASSIVE: A Multidisciplinary Applications-Oriented Simulation and Visualization Environment
Optimizing DaaS Web Service Based Data Mashups
Predicting the Quality of Web Services Based on User Stability
A Model for Digital Business Ecosystem and Topological Analysis
How Physical Objects and Business Workflows Can Be Correlated
A Situations & Goals Semantic Model for Designing and Implementing Semantic Web Services-based Processes
Constructing a Creative Software with Services
A Services Lifecycle to Support the Business Processes Lifecycle: From Modeling to Execution and Beyond
Precise Mappings between Business Process Models in Versioning Scenarios
Job Scheduling of Savant for Grid Computing on RFID EPC Network
An Investigation on Service-Oriented Architecture for Constructing Distributed Web GIS Application
Robust Web Service Discovery in Large Networks
Supporting Intercultural Collaboration: An Agent Coordination Workflow Model
Evaluating Service Identification with Design Metrics on Business Process Decomposition
Rule-based XML Mediation for Data Validation and Privacy Anonymization
A Secure Model for Network-Attached Storage on the Grid
A Field Perspective on the Interoperability of Web Services
Sharing with a Difference: Realizing Service-Based SaaS Applications with Runtime Sharing and Variation in Dynamic Software Product Lines
A Novel Approach for Process Mining Based on Event Types
Extreme Topic Model for Market eAlert Service
Services Oriented Knowledge-based Supply Chain Application
IsV2C: An Integrated Road Traffic-Network-Cloud Simulator for V2C Connected Car Services
Service-Oriented Architecture Based e-Engineering Framework to Support Collaborative Design
A Service-Friendly Approach to Discover Traveling Companions Based on ANPR Data Stream
Code Will Speak: Early detection of Ponzi Smart Contracts on Ethereum
Service-Oriented Architecture for SPDFLOW: A Healthcare Workflow System for Sterile Processing Departments
F-LaaS: A Control-Flow-Attack Immune License-as-a-Service Model
2012 IEEE Ninth International Conference on Services Computing, Honolulu, HI, USA, June 24-29, 2012
QoS Support for Media Broadcast in a Services Oriented Architecture
Supporting Geosciences Web Services Metadata Management and Discovery
Exploring GitHub Topics: Unveiling Their Content and Potential
A Policy-Based Approach for QoS Specification and Enforcement in Distributed Service-Oriented Architecture
Social-Based Semantic Framework for Cloud Resource Management in Business Processes
GSPN-Based Reliability-Aware Performance Evaluation of IoT Services
A Framework for the Evaluation of Mashup Tools
A Privacy Agreement Model for Web Services
Providing Map and GPS Assistance to Service Composition in Bioinformatics
Accelerating the Deployment of Security Service Infrastructure with Collective Intelligence and Analytics
Zazen: A Mediating SOA between Ajax Applications and Enterprise Data
Automatic Web Service Composition
Building a Service-Oriented eBanking Platform
Ontology Reconciliation for Service-Oriented Computing
A Framework for Situation-Aware Access Control in Federated Data-as-a-Service Systems Based on Query Rewriting
An Approach to Design and Analyze the Framework for Preventing Cyberbullying
Towards Self-Composing, Prioritized and Consequential Services
A Formal Approach for Enforcing Transactional Requirements in Web Service Compositions
XOA: Web-Enabled Cross-Ontological Analytics
A Folksonomy-Based Model of Web Services for Discovery and Automatic Composition
A Human-Asset-Compromised Allocation Model of Multiple Emergency Projects in Service-Focused Enterprises
A Survey on Automated Service Composition Methods and Related Techniques
Handling Concept Drift in Predictive Process Monitoring
Checking e-service consistency using Description Logics
Enhancing Asset Search and Retrieval in a Services Repository using Consumption Contexts
Recommending Energy-Efficient Data Mining Services with Data as Contextual Factors
A General Service-Oriented Grid Computing Framework for Global Optimization Problem Solving
Microservices and Their Design Trade-Offs: A Self-Adaptive Roadmap
On Assessing the Competitiveness of IT Service Solutions
The Mining of Activity Dependence Relation Based on Business Process Models
QoS Analysis and Service Selection for Composite Services
A Framework for Detecting Anomalous Services in OSGi-Based Applications
A Microservice Framework for Efficient Navigation Service
Workflow Model Distribution or Code Distribution? Ideal Approach for Service Composition of the Internet of Things
Engineering Resilient Collaborative Edge-Enabled IoT
A Meta-model for QoS Monitoring in a Dynamic Service-Component Platform
desc2tag: A Reinforcement Learning Approach to Mashup Tag Recommendation
A Clustering Based Schema Matching Scheme for Improving Matching Correctness of Web Service Interfaces
A Comparison of Several Ensemble Methods for Text Categorization
Incentive-Based Selection and Composition of IoT Energy Services
A Service Interoperability Assessment Model for Service Composition
Hybrid Role Mining for Security Service Solution
Study on the Behavior-based Trust Model in Grid Security System
SOA based Context Aware Services Infrastructure
Web 2.0 Services for Identifying Communities of Practice through Social Networks
A 3-level e-Business Registry Meta Model
Reliability estimation at block-level granularity of spin-transfer-torque MRAMs
Approximate Memory Protection Against Double-Adjacent Bit Errors with Low Redundancy SEC-DAEC Codes
Software-Based Hardware Fault Tolerance for Many-Core Architectures
Low-Power Testing for Low-Power Devices
Test Challenge for Deep Sub-micron Era - Test & Diagnosis Platform: STARCAD-Clouseau
1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 1995, Lafayette, LA, USA, November 13-15, 1995
A fast and scalable fault injection framework to evaluate multi/many-core soft error reliability
Using memristor state change behavior to identify faults in photovoltaic arrays
Material Fatigue and Reliability of MEMS Accelerometers
A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits
Defect Tolerance for a Capacitance Based Nanoscale Biosensor
Single-Event-Upset Trends in Advanced CMOS Technologies
Special Session Paper: Application of Functional Verification Techniques in Hardware Trust
Design of a Fault Tolerant Multistage Interconnection Network with Parallel Duplicated Switches
25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010
A design flow for protecting FPGA-based systems against single event upsets
New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs
Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes
Fault-Tolerant Ring- and Toroidal Mesh-Connected Processor Arrays Able to Enhance Emulation of Hypercubes
Challenges in Machine Learning Techniques to Estimate Reliability from Transistors to Circuits
Yield Modeling of a WSI Telecom Router Architecture
An on-line soft error mitigation technique for control logic of VLIW processors
Built-in generation of multi-cycle broadside tests
A Self Aware Security Approach for Real Time Neural Network Applications from Row Hammer Attacks in Multi FPGA Multi User Environment
Exploration of system availability during software-based self-testing in many-core systems under test latency constraints
Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits
Design and Implementation of a Merged On-Line and Off-Line Self Textable Architecture
Special Session: Enhancing Reliability in Digital Computing-in-Memory Architectures Through Approximation and Fault Tolerance Methods
On-Board Satellite Telemetry Forecasting with RNN on RISC-V Based Multicore Processor
Input Ordering in Concurrent Checkers to Reduce Power Consumption
Modular Fault Simulation of Mixed Signal Circuits with Fault Ranking by Severity
19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 10-13 October 2004, Cannes, France, Proceedings
On Attacking Scan-based Logic Locking Schemes
Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream
Accurate Fault Modeling and Fault Simulation of Resistive Bridges
How to Tune the MTTF of a Fail-Silent System
Image Degradation in Time Due to Interacting Hot Pixels
CAL: Exploring cost, accuracy, and latency in approximate and speculative adder design
Should Illinois-Scan Based Architectures be Centralized or Distributed?
Reliability Estimation for Time Redundant Error Correcting Adders and Multipliers
Run-time mapping for reliable many-cores based on energy/performance trade-offs
Novel Control Pattern Generators for Interconnect Testing with Boundary Scan
A probabilistic analysis of resilient reconfigurable designs
Diagnostic self-test for dynamically scheduled superscalar processors based on reconfiguration techniques for handling permanent faults
Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model
Special Session: Testing of Digital Computing-In Memories with MAC Function
A Novel Hardened Design of a CMOS Memory Cell at 32nm
A Statistical Parametric and Probe Yield Analysis Methodology
Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells
On the design of two single event tolerant slave latches for scan delay testing
Radiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWL
Protecting Large Word Size Memories against MCUs with 3-bit Burst Error Correction
An In-Depth Vulnerability Analysis of RISC-V Micro-Architecture Against Fault Injection Attack
Scheduling algorithm in datapath synthesis for long duration transient fault tolerance
Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources
Integrated Approach for Circuit and Fault Extraction of VLSI Circuits
An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture
Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design
Error Tolerance of DNA Self-Assembly by Monomer Concentration Control
An Application-Independent Delay Testing Methodology for Island-Style FPGA
A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices
A Prototype of a VHDL-Based Fault Injection Tool
Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes
Characterization of CMOS Defects using Transient Signal Analysis
SoC Mixed-Signal Dependability Enhancement: A Strategy from Design to End-of-Life
Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor
Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers
Yield Model for ASIC and Processor Chips
Soft-Error Detection Using Control Flow Assertions
Software exploitable hardware Trojans in embedded processor
A Self-Healing, High Performance and Low-Cost Radiation Hardened Latch Design
Analog Design for a Power Transmission Line Sensing and Analysis VLSI Chip
Configurable Spare Processors: A New Approach to System Level-Fault Tolerance
On the Functional Qualification of a Platform Model
Scan-Based BIST Diagnosis Using an Embedded Processor
Parameter Variability in Nanoscale Fabrics: Bottom-Up Integrated Exploration
Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains
Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller
An Asymmetric Checkpointing and Rollback Error Recovery Scheme for Embedded Processors
Scan Architecture for Shift and Capture Cycle Power Reduction
Fault-Tolerant Shuffle-Exchange and de Bruijn Networks Capable of Quick Broadcasting
Repairability Evaluation of Embedded Multiple Region DRAMs
Management of Critical Areas and Defectivity Data for Yield Trend Modeling
On-line detection of intermittent faults in digital-to-analog converters
Using digital imagers to characterize the dependence of energy and area distributions of SEUs on elevation
Monitoring Methodology for TID Damaging of SDRAM Devices based on Retention Time Analysis
LAD-IXoC: Loop-Based Attack Detection with Integrated Xor Filter and CMS
A Tool for Injecting SEU-Like Faults into the Configuration Control Mechanism of Xilinx Virtex FPGAs
On the Hardware Implementation of Lala's 64-bit SEcDED Codes
Compact and Highly Testable Error Indicator for Self-Checking Circuits
Efficient Exact Spare Allocation via Boolean Satisfiability
A Low Power Soft Error Suppression Technique for Dynamic Logic
Case Studies on Transition Fault Test Generation for At-speed Scan Testing
ADTS: an array defect-tolerance scheme for wafer scale gate arrays
A Switch Box Architecture to Mitigate Bridging and Short Faults in SRAM-Based FPGAs
A Digital BIST for Phase-Locked Loops
Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines
Minimization of CTS of k-CNOT Circuits for SSF and MSF Model
Hierarchical Fault Compatibility Identification for Test Generation with a Small Number of Specified Bits
Differential analysis of Round-Reduced AES faulty ciphertexts
Impact of PVT variation on delay test of resistive open and resistive bridge defects
A Software-Based Error Detection Technique Using Encoded Signatures
Design and Evaluation of Burst-Mode Asynchronous 8-Bit Microprocessor Using Standard FPGA Development System
QCA-Based Majority Gate Design under Radius of Effect-Induced Faults
Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit
Fault-Tolerant Sorting Using VLSI Processor Arrays
A New Approach to Linear Connections Building BIST Structure Based on CSTP Structure
Device Mismatch Limitations on the Performance of a Hamming Distance Classifier
Parity-Based Concurrent Error Detection Schemes for the ChaCha Stream Cipher
Real Time Fault Injection Using Enhanced OCD -- A Performance Analysis
Impact of Image Sensor Input Faults on Pruned Neural Networks for Object Detection
GPGPUs ECC efficiency and efficacy
Evaluation of Single Event Upset Mitigation Schemes for SRAM Based FPGAs Using the FLIPPER Fault Injection Platform
A Pipelined Multi-Level Fault Injector for Deep Neural Networks
An Estimation Method of Defect Types Using Artificial Neural Networks and Fault Detection Information
Hot spare components for performance-cost improvement in multi-core SIMT
Test Generation for Open Defects in CMOS Circuits
Multi-Site and Multi-Probe Substrate Testing on an ATE
Yield Estimates for the TESH Multicomputer Network
A Yield Improvement Program Using Process Control and Process Optimization for Particle Reduction Using In Situ Particle Monitoring on a Semitool Magnum
Reliability Evaluation of Digital Channelizers Implemented on SRAM - FPGAs
A Multifunctional Laser Linking and Cutting Structure for Standard 0.25 mum CMOS-Technology
Layout Level Design for Testability Strategy Applied to a CMOS Cell Library
A New Light-Based Logic IC Screening Method
Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects
Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture
Effective Checkpoint and Rollback Using Hardware/OS Collaboration
Reliability-Driven System-Level Synthesis of Embedded Systems
Yield Enhancement with Particle Defects Reduction
Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests
Architectural Vulnerability Factor (or, does a soft error matter?)
Towards SRAM leakage power minimization by aggressive standby voltage scaling - Experiments on 40nm test chips
Relation between Reliability and Yield of IC's Based on Discrete Defect Distribution Model
Compacting output responses containing unknowns using an embedded processor
Minimizing Observation Points for Fault Location
Modeling Open Defects in Nanometric Scale CMOS
A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of Defects
Charge sharing aware NCL gates design
Impact of Simulation Parameters on Critical Area Analysis
On Reducing Circuit Malfunctions Caused by Soft Errors
A Lightweight Reconfigurable RRAM-based PUF for Highly Secure Applications
On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router
A cross-layer approach to online adaptive reliability prediction of transient faults
Probabilistic Balancing of Fault Coverage and Test Cost in Combined Built-In Self-Test/Automated Test Equipment Testing Environment
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024, Didcot, United Kingdom, October 8-10, 2024
Error Correcting Codes for Crosstalk Effect Minimization
A study of time redundant fault tolerance techniques for superscalar processors
Yield and Routing Objectives in Floorplanning
A fast TCAD-based methodology for Variation analysis of emerging nano-devices
Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels
Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST
Functional Testing of Linear Circuits Using Transient Response Analysis
Accelerated microarchitectural Fault Injection-based reliability assessment
Partial Error Masking to Reduce Soft Error Failure Rate in Logic Circuits
Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults
CMOS Standard Cells Characterization for Defect Based Testing
Prioritization of Paths for Diagnosis
On the Reconfigurable Operation of Arrays with Defects for Image Processing
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, Austin, TX, USA, October 19-21, 2022
Model for Thermal Behavior of Shaded Photovoltaic Cells under Hot-Spot Condition
On the multiple fault detection of a nano crossbar
Increasing the Efficiency and Efficacy of Selective-Hardening for Parallel Applications
XOR-based Low Cost Checkers for Combinational Logic
Effects of Voltage and Temperature Variations on the Electrical Masking Capability of Sub-65 nm Combinational Logic Circuits
Generation and Verification of Tests for Analogue Circuits Subject to Process Parameter Deviations
Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling
36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2021, Athens, Greece, October 6-8, 2021
Transient Current Testing of Dynamic CMOS Circuits
Recovery Schemes for Mesh Arrays Utilizing Dedicated Spares
A Novel Digitisation Method for Pulse Switchable Memristive Chemical Sensors
A Fault-Tolerant 176 Gbit Solid State Mass Memory Architecture
A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-Based FPGA Systems
Redundancy, Repair, and Test Features of a 90nm Embedded SRAM Generator
Fault Tolerant Design Using Error Correcting Code for Multilayer Neural Networks
Extraction of critical areas for opens in large VLSI circuits
Storage-Based Logic Built-In Self-Test with Variable-Length Test Data
Chip-level anti-reverse engineering using transformable interconnects
Automatic Modification of Sequential Circuits for Self-Checking Implementation
Low Power SoC Memory BIST
Arithmetic Operators Robust to Multiple Simultaneous Upsets
Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring
Can flexible, domain specific programmable logic prevent IP theft?
On-Chip Test Embedding for Multi-Weighted Random LFSRs
VLSI Concurrent Error Correcting Adders and Multipliers
An Approach to Minimizing Functional Constraints
Novel Berger code checker
Bounding error detection latency in safety critical systems with enhanced Execution Fingerprinting
Test Selection Policies for Faster Incremental Fault Detection
Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities
Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage
Yield Modeling and Analysis of a Clockless Asynchronous Wave Pipeline with Pulse Faults
Transient Fault and Soft Error On-die Monitoring Scheme
Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture
Unified 3D test architecture for variable test data bandwidth across pre-bond, partial stack, and post-bond test
Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations
Diagnosis of segment delay defects with current sensing
FFT-based test of a yield monitor circuit
Testing the Configurability of Dynamic FPGAs
Challenges in Delay Testing of Integrated Circuits
Built-in-Self-Diagnostics for a NoC-Based Reconfigurable IC for Dependable Beamforming Applications
An Integrated Fault-Tolerant Design Framework for VLIW Processors
On-Chip Sensors Data Collection and Analysis for SoC Health Management