yusuke1997/dblp-id-title huggingface dataset:
A Design Environment for Bio-Inspired Cellular Architectures
Mapping Wireless Communication Algorithms to a Reconfigurable Architecture
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2005, Las Vegas, Nevada, USA, June 27-30, 2005
Simulation Framework for Performance Prediction in the Engineering of Reconfigurable Systems and Applications
Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs
A Fault Tolerant Multi-Agent System with Non-Deterministic Decision-Making for Task Allocation
Multi-Criteria Optimization and Performance Measurement of Domain-Specific Reconfigurable Architectures Targeting Image and Video Processing Applications
Distributed Reconfiguration
Overview of the Tool-flow for the Montium Processor Tile
An Introduction to Radiation-Induced Failure Modes and Related Mitigation Methods For Xilinx SRAM FPGAs
Harnessing Human Computation Cycles for the FPGA Placement Problem
High Efficiency Reconfigurable Cache for Image Processing
Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture
Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware
Computing Lennard-Jones Potentials and Forces with Reconfigurable Hardware
A Study of Mapping Generalized Sliding Window Operations on Reconfigurable Computers
Performance Visualization and Exploration for Reconfigurable Computing Applications
Parameterized AND-OR Trees for FPGA Design Space Exploration
A Reconfigurable Parallel Disk System for Filtering Genomic Banks
FPGA Resource Management Using Internal RAM as Aata Cache
FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation
The GOmputer: Accelerating GO with FPGAs
Algorithm Design for Reconfigurable Computing Systems
Reducing the reconfiguration overhead: a survey of techniques
Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning
Optimizing Interface Implementation Costs Using Runtime Reconfigurable Systems
SystemC-based Custom Reconfigurable Cores for Wireless Applications
A Comparative Study on System Approaches for Partially Reconfigurable Architectures
Differential Reconfiguration Architecture suitable for a Holographic Memory
Gradient Run-length Data Compression for Real-time Airborne Image Processing
Design and Evaluation of a Software Infrastructure for the Runtime Management of Reconfigurable Resources
Integrating Application Specification and Performance Prediction for Strategic Design-Space Exploration
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2007, Las Vegas, Nevada, USA, June 25-28, 2007
Compiling Stream-Language Applications to a Reconfigurable Array Processor
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays
Modeling Abstractions for Next Generation Reconfigurable Computing
Performance Monitoring for Run-time Management of Reconfigurable Devices
Task Scheduling of Control-Data Flow Graphs for Reconfigurable Architectures
Egret: A Flexible Platform for Real-Time Reconfigurable Systems on Chip
Nanocomputing Block based Multi-Context FPGA
Genetic Algorithms in Hardware-Software Partitioning
A Multi-Application Mapping Framework for Network-on-Chip Based MPSoC: An FPGA Implementation Case Study
A Reconfigurable Antialiasing Filter Design Using Multi-Abstraction Design Exploration Approach
A Scalable H.264/AVC Variable Block Size Motion Estimation Engine Using Partial Reconfiguration
Reconfigurable 1-Bit Processor Array with Reduced Wirng Area
Increasing Efficiency by Partial Hardware Reconfiguration: Case Study of a Multi-Controller System
TMR with More Frequent Voting for Improved FPGA Reliability
Area Reclamation Strategies and Metrics for SRAM-Based Reconfigurable Devices
Instance-Specific Solutions to Accelerate the CKY Parsing
A Formal Semantics for Control and Data flow in the Gannet Service-based System-on-Chip Architecture
Energy-Efficient Dynamic Task Scheduling Algorithm for Reconfigurable System-on-Chip Architectures
Process Isolation for Reconfigurable Hardware
Metamorphic Memory Based Bio-Inspired Reconfigurable Celluar Systems
Self-reconfigurable Embedded Systems: From Modeling to Implementation
JBits Based Fault Tolerant Framework for Evolvable Hardware
Aspect Ratio Effects on Reconfigurable Computing
Next Generation Architecture for Heterogeneous Embedded Systems
Autonomous Computing Systems: A Proposed Roadmap
Resource Management for Hw Multitasking in Three Dimensional FPGAs
CliffoSor, an Innovative FPGA-based Architecture for Geometric Algebra
A Scalable and Reconfigurable Shared-Memory Graphics Cluster Architecture
Fast Design Space Exploration Method for Reconfigurable Architectures
Feasibility of Hardware Acceleration of a Neocortex Model
Towards Run-Time Re-Configurable Techniques for Real-Time Embedded Applications
Code Partitioning for Reconfigurable High-Performance Computing: A Case Study
VTSim: A Virtex-II Device Simulator
Evolvable Hardware: A Functional Level Evolution Framework Based on ImpulseC
Hardware Software Codesign of the Xilinx Microkernel
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2009, July 13-16, 2009, Las Vegas Nevada, USA
Computer Architecture and Technology: Some Thoughts on the Road Ahead
MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration - a 6502 Perspective
Instance-Specific Versus Parameter-Specific Circuit Generation
Autonomous Computing Systems: A Proof-of-Concept
Selection and Use of Programmable Logic in Flight Applications
Design Framework for Partial Run-Time FPGA Reconfiguration
Run-Time Adaptation of a Reconfigurable Mobile UMTS Receiver
FPGA Prototyping Approach for the Validation of Efficient Iterative Decoders in Digital Communication Systems
A Parallel Array to Accelerate GFA Modeling in Video Coding
On the Use of FPGAs for OFDM Signal Processing
A Cellular Automata ASIC for Conformal Computing
Fast Real-Time LIDAR Processing on FPGAs
Reconfigurable Instruction Set Computing for Embedded Processing
A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and Routability
A Sandbox for Exploring the OpenFire Processor
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2006, Las Vegas, Nevada, USA, June 26-29, 2006
Cache Architectures for Reconfigurable Hardware
Configuration and Data Scheduling for Executing Dynamic Applications onto Multi-Context Reconfigurable Architectures
An Implementation of Security Extensions for Data Integrity and Confidentiality in Soft-Core Processors
Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
Producer and Consumer: Roles of a Microprocessor and a Configurable Logic in a Configurable SoC
Better Languages for More Effective Designing
Performance Evaluation of Two Allocation Schemes for Combinatorial Group Testing Fault Isolation
FPGA-Based High-Order Finite Difference Algorithm for 2D Acoustic Wave Propagation Problems
Transformable Vertexes Information based Algorithm for Online Task Placement in Reconfigurable System
Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor
The Era of Reconfigurable Computing
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2008, Las Vegas, Nevada, USA, July 14-17, 2008
Implementing Multi Threaded System Support for Hybrid FPGA/CPU Computational Components
Novo-G: A View at the HPC Crossroads for Scientific Computing
Optimization of Reconfiguration-speed Control Bits for an Optically Reconfigurable Gate Array
Scientific Computing using Reconfigurable Hardware
GifT: A Gravity-Directed and Life-Time Based Algorithm for Temporal Partitioning of Data Flow Graphs
Area Evaluation for Parallel Execution in Reconfigurable Processor Architectures
High-efficiency FPGA Fully-Based Implementation of the Conjugate Gradient Method
Industrial Workshop - Architectural Synthesis for Reconfigurable Computing
Declarative Programming with Handel-C
An FPGA-Based Accelerator for Multiphysics Modeling
Towards Effective Modeling and Programming Multi-core Tiled Reconfigurable Architectures
Searching RC5-Keys with Distributed Reconfigurable Computing
A Preliminary Study of Molecular Dynamics on Reconfigurable Computers
A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA
Power Efficient Domain-Specific Reconfigurable Architectures for System-on-Chip Applications
Using configurable processors for high-efficiency multiple-processor systems
Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations
PyHDL: Hardware Scripting with Python
Energy Performance of Floating-Point Matrix Multiplication on FPGAs
Future Directions in Reconfigurable Computing
Area-Efficient Evaluation of a Class of Arithmetic Expressions Using Deeply Pipelined Floating-Point Cores
A SoPC Architecture of MIMO Sphere Decoder for Mobile Communications
Standards for Sustainability - Growing Markets and Improving Access for Reconfigurable Supercomputing
Energy-Efficient Discrete Cosine Transform on FPGAs
Implementing Error Detection and Error Correction with Explicit Area Constraints
Distinguished Paper: Automatic Local Memory Architecture Generation for Data Reuse in Custom Data Paths
A Methodology to Implement Real-Time Applications on Reconfigurable Circuits
Optimizing the FPGA Memory Design for a Sobel Edge Detector
Optimizing Pipelining in HDL Generated Automatically from C Source Codes
FPGA Implementation of an Analytical Design Method for A Cycle-Optimal 2D-DCT/IDCT
Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity
Lost in Space! Quantifying the Elements of FPGA Speedup
It's Like Deja-Vu All over Again ... Again
Computing Without Processors
Application-Independent FPGA-based Profiling
Prototyping of a Two-Phase Micropipeline on FPGAs
Memory Hierarchy for MCSoPC Multithreaded Systems
Bio-inspired Systems: Self-adaptability from Chips to Sensor-network Architectures
Application Specific Reconfigurable Architecture Design
Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array
Agent-Based Reconfigurability for Fault-Tolerance in Network-on-Chip
How Constrains Programming Can Help You in the Generation of Optimized Application Specific Reconfigurable Processor Extensions
A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs
A Non-LIinear Function Generator Using BRM
Intrinsic Embedded Hardware Evolution of Block-based Neural Networks
Floating-Point Unit Reuse in an FPGA Implementation of a Ray-Triangle Intersection Algorithm
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23 - 26, 2003, Las Vegas, Nevada, USA
Accelerating Exact Stochastic Simulation Using Reconfigurable Computing
An Efficient Comparative Evaluation to Buffering Methods for Window-based Image Processing Using Semi-programmable Hardware
Partial Block-by-Block Reconfiguration for a Dynamic Optically Reconfigurable Gate Array
Promises and Pitfalls of Reconfigurable Supercomputing
Flexible Core Reallocation for Virtex II Structures
Coarse-Grained Reconfigurable Computing for Power Aware Applications
A Multi-Pattern Scheduling Algorithm
SiLLis: A Simplified Language for Monitoring and Debugging of Reconfigurable Systems
Supporting Operating Systems for Reconfigurable Computing: A Distributed Service Oriented Approach
A 770ns Holographic Reconfiguration of a Four-Context DORGA
A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management
A Constant Complexity Allocation Algorithm for Reconfigurable Systems Management Adapted to Heterogeneous Workload Profiles
A Combined Hardware-Software Architecture for Network Flow
Output Serialization for FPGA-based and Coarse-grained Processor Arrays
Architectural Support for Runtime 2D Partial Reconfiguration
A Reconfigurable Approach to Structural Engineering Design Computations
Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs
A Framework to Improve IP Portability on Reconfigurable Computers
A Hardware Implementation of a Dynamically Adjustable Block-based Neural Network
Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX
Group-Alignment based Accurate Floating-Point Summation on FPGAs
Elemental Computing for High Reliability
Distinguished Paper: High-Visibility Debug-by-Design for FPGA Platforms
A Hardware Accelerator for k-th Nearest Neighbor Thinning
RTOS-Based Hardware Software Communications and Configuration Management in the Context of a Smart Camera
Experiences with a Reconfigurable Computer
Distinguished Paper: Automated Combination of Simulation and Hardware Prototyping
FFT Mapping on MathStar's FPOATM FilterBuilderTM Platform
High-Level Specification of Runtime Reconfigurable Designs
An Operation and Interconnection Sharing Algorithm for Partially Reconfigurable Architectures
A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System
An Adaptive Load Distribution Model and Design on Self-Reconfigurable Logic Device
Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation
Design Enumeration of Mapping 2D FFT onto FPGA Based Reconfigurable Computers
Configurable Processors and the Evolution of System-on-Chip Design
On Implicit Modelling for Fitting Purposes
A Feature-based Deformable Model for Photo-Realistic Head Modelling
Communicative Autonomous Agents
Constructing Virtual Human Life Simulations
Parametrization and Range of Motion of the Ball-and-Socket Joint
A Vector-Space Representation of Motion Data for Example-based Motion Synthesis
Animated Heads: From 3D Motion Fields to Action Descriptions
Deformable Avatars, IFIP TC5/WG5.10 DEFORM'2000 Workshop, November 29-30, 2000, Geneva, Switzerland and AVATARS'2000 Workshop, November 30-December 1, 2000, Lausanne, Switzerland
Efficient Muscle Shape Deformation
A Muscle-based 3D Parametric Lip Model for Speech-Synchronized Facial Animation
Towards the Ultimate Motion Capture Technology
PECS - A Reference Model for Human-Like Agents
Soft Tissue Modeling from 3D Scanned Data
Multiresolution Modeling and Interactive Deformation of Large 3D Meshes
Object-Oriented Reformulation and Extension of Implicit Free-Form Deformations
Locally Interpolating Subdivision Surfaces Supporting Free-Form 2D Deformations
Interactive Modelling of MPEG-4 Deformable Human Body Models
Towards Behavioral Consistency in Animated Agents
Delaunay Triangles Model for Image-Based Motion Retargeting
Contextually Embodied Agents
Design Issues for Conversational User Interfaces: Animating and Controlling 3D Faces
Feature Point Based Mesh Deformation Applied to MPEG-4 Facial Animation
Power optimization for multimedia transcoding on multicore servers
Disaggregation: The New Way to Build Mega (and Micro) Data Centers
Caesar: High-Speed and Memory-Efficient Forwarding Engine for Future Internet Architecture
ECOS: leveraging software-defined networks to support mobile application offloading
Proceedings of the 2010 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2010, San Diego, California, USA, October 25-26, 2010
Distributed adaptive routing for big-data applications running on data center networks
O3FA: A Scalable Finite Automata-based Pattern-Matching Engine for Out-of-Order Deep Packet Inspection
Performance scalability of a multi-core web server
On pending interest table in named data networking
SpliceNP: a TCP splicer using a network processor
Range hash for regular expression pre-filtering
Design of a network architecture with inherent data path security
FlowOS: a pure flow-based vision of network traffic
Toward Fabric: A Middleware Implementing High-level Description Languages on a Fabric-like Network
High performance multi-field packet classification using bucket filtering and GPU processing
A Software Defined Sketch System for Traffic Monitoring
On reducing false positives of a bloom filter in trie-based algorithms
Designing Virtual Network Functions for 100 GbE Network Using Multicore Processors
High throughput architecture for packet classification using FPGA
Cyclostationary codec: A framework to enable alternative network architectures
Transparent Cloud Access Performance Augmentation via an MPTCP-LISP Connection Proxy
Design of a scalable nanophotonic interconnect for future multicores
P4-NetFPGA-based network slicing solution for 5G MEC architectures
Linux XIA: An Interoperable Meta Network Architecture to Crowdsource the Future Internet
Network traffic adaptive S-MAC protocol for wireless sensor network
LAMP: prompt layer 7 attack mitigation with programmable data planes
Software is the future of networking
Theoretic analysis of finite automata for memory-based pattern matching
HPC-Mesh: A Homogeneous Parallel Concentrated Mesh for Fault-Tolerance and Energy Savings
Scalable high-speed NDN name lookup
The scope for Online Social Network aided caching in web CDNs
Detecting Remote Access Trojans through External Control at Area Network Borders
Network monitoring probe based on Xilinx Zynq
Heavy Hitter Detection on Multi-Pipeline Switches
Achieving End-to-End Network Visibility with Host-INT
An effective network processor design framework: using multi-objective evolutionary algorithms and object oriented techniques to optimise the intel IXP1200 network processor
Cuckoo Counter: A Novel Framework for Accurate Per-Flow Frequency Estimation in Network Measurement
Chimpp: a click-based programming and simulation environment for reconfigurable networking hardware
High-throughput linked-pattern matching for intrusion detection systems
Fast and flexible: Parallel packet processing with GPUs and click
400 Gb/s Programmable Packet Parsing on a Single FPGA
On the feasibility of completely wireless datacenters
Framework for supporting multi-service edge packet processing on network processors
Fast longest prefix name lookup for content-centric network forwarding
A path combinational method for multiple pattern matching
Bayesian factor analysis and performance measurement of the Linux forwarding architecture
TnT: transparent network tracker for P2P applications
Virtual Network Functions Instantiation on SDN Switches for Policy-Aware Traffic Steering
GAMT: A fast and scalable IP lookup engine for GPU-based software routers
Galois field hardware architectures for network coding
Fast Content Distribution on Datacenter Networks
Kubernetes Load-balancing and related network functions using P4
Cuckoo++ hash tables: high-performance hash tables for networking applications
Design considerations for network processor operating systems
WASP: a software-defined communication layer for hybrid wireless networks
ANCS '21: Symposium on Architectures for Networking and Communications Systems, Layfette, IN, USA, December 13 - 16, 2021
SWSL: SoftWare Synthesis for network Lookup
Packet Classification Using a Bloom Filter in a Leaf-Pushing Area-based Quad-Trie
Divide and discriminate: algorithm for deterministic and fast hash lookups
Parsing Application Layer Protocol with Commodity Hardware for SDN
Statistical Optimal Hash-Based Longest Prefix Match
OpenSched: Programmable Packet Queuing and Scheduling for Centralized QoS Control
Malacoda: towards high-level compilation of network security applications on reconfigurable hardware
Sequence-preserving adaptive load balancers
Design of a secure packet processor
Synchronizing Namespaces with Invertible Bloom Filters
Efficient regular expression evaluation: theory to practice
An operating system architecture for network processors
A remotely accessible network processor-based router for network experimentation
Efficient buffering and scheduling for a single-chip crosspoint-queued switch
SPC-FA: synergic parallel compact finite automaton to accelerate multi-string matching with low memory
On Data Plane Latency and Pseudo -TCP Congestion in Software-Defined Networking
Low-latency modular packet header parser for FPGA
Secure remote sensing and communication using digital pufs
Progressive hashing for packet processing using set associative memory
ZeroSDN: A Highly Flexible and Modular Architecture for Full-Range Network Control Distribution
Laying out interconnects on optical printed circuit boards
PFCA: a programmable FIB caching architecture
Experimenting with buffer sizes in routers
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Fair multithreading on packet processors for scalable network virtualization
A purely functional approach to packet processing
High Throughput Forwarding for ICN with Descriptors and Locators
Hardware support for dynamic protocol stacks
Towards a Framework for One-sided RDMA Multicast
Multiplexing endpoints of HCA to achieve scalability for MPI applications: design, implementation and performance evaluation with uDAPL
Adaptive scheduling to maximize NIC throughput in a COTS router
DiFS: distributed flow scheduling for adaptive routing in hierarchical data center networks
Optimal networks from error correcting codes
Towards an efficient switch architecture for high-radix switches
ORange: Multi Field OpenFlow based Range Classifier
Caesar: a content router for high-speed forwarding on content names
PFPSim: A Programmable Forwarding Plane Simulator
A Canonical Multicore Architecture for Network Routers
The Cost of Stateless Network Functions in 5G
Segmented hash: an efficient hash table implementation for high performance networking subsystems
Blueswitch: Enabling Provably Consistent Configuration of Network Switches
Improving PC-based OpenFlow switching performance
Building Fast but Flexible Software Routers
On the Latency Benefits of Edge NFV
E-AHRW: An Energy-Efficient Adaptive Hash Scheduler for Stream Processing on Multi-core Servers
Experiences in Co-designing a Packet Classification Algorithm and a Flexible Hardware Platform
A block-based reservation architecture for the implementation of large packet buffers
SimNP: a flexible platform for the simulation of a network processing system
An adaptive hash-based multilayer scheduler for L7-filter on a highly threaded hierarchical multi-core server
A Traffic Anomaly Detection Method based on Multi-scale Decomposition and Multi-Channel Detector
Fast Path Performance of Packet Cache Router Using Multi-core Network Processor
Using Indirect Routing to Recover from Network Traffic Scheduling Estimation Error
Speeding up packet I/O in virtual machines
TED: tool for testing and debugging uDAPL
An architecture for software defined cognitive radio
Motivating future interconnects: a differential measurement analysis of PCI latency
Balancing authentication and location privacy in cooperative authentication
Binary search on levels using a Bloom filter for IPv6 address lookup
ClassBench-ng: Recasting ClassBench after a Decade of Network Evolution
INetCEP: In-Network Complex Event Processing for Information-Centric Networking
Structural compression of packet classification trees
Efficient packet classification algorithm based on entropy
M-DFA (multithreaded DFA): an algorithm for reduction of state transitions and acceleration of REGEXP matching
Evaluating Information-Centric Networks in Disconnected, Intermittent, and Low-Bandwidth Environments
LEISURE: A Framework for Load-Balanced Network-Wide Traffic Measurement
Time Pattern Analysis of Malware by Circular Statistics
Marlin: a memory-based rack area network
Automated task distribution in multicore network processors using statistical analysis
Mind the Gap - A Comparison of Software Packet Generators
Cache-aware affinitization on commodity multicores for high-speed network flows
High-speed detection of unsolicited bulk emails
Evaluating the performance of software NICs for 100-gb/s datacenter traffic control
Symposium on Architecture for Networking and Communications Systems, ANCS '13, San Jose, CA, USA, October 21-22, 2013
Design principles for packet parsers
Low-latency scheduling in large switches
ParaRegex: Towards Fast Regular Expression Matching in Parallel