yusuke1997/dblp-id-title huggingface dataset:
The PowerPC 603 TM Microprocessor: An Array Built-In Self-Test Mechanism
Optimization methods for post-bond die-internal/external testing in 3D stacked ICs
Test process optimization: closing the gap in the defect spectrum
FASTrust: Feature analysis for third-party IP trust verification
Testability Measures : What Do They Do for ATPG ?
Automatic Delay Calibration Method for Multi-channel CMOS Formatter
A Comparison of Stuck-At Fault Coverage and I DDQ Testing on Defect Levels
California scan architecture for high quality and low power testing
High-Coverage DfT and Reliability Enhancements for Automotive Floating Gate OTP Beyond AEC-Q100
On-chip diagnosis for early-life and wear-out failures
Built-In Self-Test of the VLSI Content Addressable Filestore
Power-aware NoC Reuse on the Testing of Core-based Systems
TSG: A Test System Generator for Debugging and Regression Test of High-Level Behavioral Synthesis Tools
Built-in EVM measurement for OFDM transceivers using all-digital DFT
Debug and Diagnosis in the Age of System-on-a-Chip
Testing VLSI Microprocessor with New Functional Capability
Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study
Towards Robust Deep Neural Networks Against Design-Time and Run-Time Failures
An Easily Computed Functional Level Testability Measure
Testing Trends in Automotive Electronics
Testing Properties and Applications of Inverter-Free PLA's
Current ratios: a self-scaling technique for production I_DDQ testing
Is there a STIL for mixed signal testing?
Analysis of failure sources in surface-micromachined MEMS
Achieving Zero-Defects for Automotive Applications
I DDQ and Voltage Testable CMOS Flip-flop Configurations
First IC Validation of IEEE Std. 1149.6
ITC 2004 Panel: Cost of Test - Taking Control
The dynamic reduction of fault simulation
An Improved Search Algorithm
An Analysis of Tungsten Probes' Effect on Yield in a Production Wafer Probe Environment
High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning Techniques
Switch-Level ATPG Using Constraint-Guided Line Justification
Test Pattern Generation with Restrictors
A Novel Omnidirectional 3D Test Access Architecture for Advanced System-on-Wafer (SoW) Applications
Highly reliable and low-cost symbiotic IOT devices and systems
Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model
Low Current and Low Voltages-The High-End OP AMP Testing Challenge
Detection and Correction of Systematic Type 1 Test Errors Through Concurrent Engineering
A novel scheme to reduce power supply noise for high-quality at-speed scan testing
Power-aware test: Challenges and solutions
Building An RF Source For Low Cost Testers Using An ADPLL Controlled By Texas Instruments Digital Signal Processor (DSP) TMS320C5402
On the charge sharing problem in CMOS stuck-open fault testing
BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learning
Applying Test Theory to VLSI Testing
Continuous Signature Monitoring: Efficient Concurrent-Detection of Processor Control Errors
On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences
Built-In Self-Test for System-on-Chip: A Case Study
Total Fault Testing Using the Bipartite Transformation
Sequential Redundancy Identification Using Verification Techniques
P1149.4-Problem or Solution for Mixed-Signal IC Design?
Test the test experts: do we know what we are doing?
Behavioral Simulation of VLSI Test System Aids Debugging and Analysis of Test Programs
A Strategy for Enhancing Fault Coverage on VLSI Circuit Boards Using Performance In-Circuit Test Techniques
DORA : A System of CAD Post-Processors Providing Test Programs and Automatic Diagnostics Data for Digital Device and Board Manufacture
Scan Latch Design for Delay Test
Detection of CMOS address decoder open faults with March and pseudo random memory tests
R4X/D4X - Formatters for Flexible Test System Architecture
Incremental Diagnosis of Multiple Open-Interconnects
Do the Designs Work ?
SCITT: Bringing DRAMs Into the Test Fold
A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks *
MBIST Supported Multi Step Trim for Reliable eMRAM Sensing
On RTL scan design
Automated Selection of Optimal EDT Input Configuration
Low-Contact-Force Probing on Copper Electrodes
Topological Testing
Non-intrusive BIST for systems-on-a-chip
Hardware and Software Tools for Microprocessor Functional Test
Testing for Timing Faults in Synchronous Sequential Integrated Circuits
ATE Data Collection - A comprehensive requirements proposal to maximize ROI of test
The MC6804P2 Built-In Self-Test
Analog neural network design for RF built-in self-test
Calibrating clock stretch during AC scan testing
AdaTest: An efficient statistical test framework for test escape screening
Simulating Resistive Bridging and Stuck-At Faults
Scan Chain Diagnosis in Advanced Process Nodes: The Art of Balancing Resolution, Repairability, and Cost
Flexible ATE module with reconfigurable circuit and its application [to CMOS imager test]
Test time reduction with SATOM: Simultaneous AC-DC Test with Orthogonal Multi-excitations
Evaluation of TSV and micro-bump probing for wide I/O testing
Zero-overhead self test and calibration of RF transceivers
Wafer/Package Test Mix for Optimal Defect Detection
Subtle Anomaly Detection of Microscopic Probes using Deep learning based Image Completion
Concurrent test planning
Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems
Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode
Predicting Fault Coverage from Probabilistic Testability
DPDAT: data path direct access testing
Test/Agent: CAD-integrated Automatic Generation of Test Programs
Cross-layer approaches for an aging-aware design of nanoscale microprocessors: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist
Industrial evaluation of stress combinations for march tests applied to SRAMs
A Structure for Board-Level Mixed-Signal Testability
Diagnosing Double Faulty Chains through Failing Bit Separation
Test-access-mechanism optimization for multi-Vdd SoCs
Functional Test Sequences for Inducing Voltage Droops in a Multi-Threaded Processor
Frequency scaled segmented (FSS) scan architecture for optimized scan-shift power and faster test application time
Functional vs. multi-VDD testing of RF circuits
2011 IEEE International Test Conference, ITC 2011, Anaheim, CA, USA, September 20-22, 2011
DVTS: Design Verification Techniques for Functional Simulation
Plenary keynote address Tuesday: The business of test: Test and semiconductor economics
I DDQ testing in deep submicron integrated circuits
Self-Testing of Embedded RAMs
Relating linearity test results to design flaws of pipelined analog to digital converters
Automated testing of bare die-to-die stacks
Deep Sub-micron I DDQ Test Options
IJTAG Through a Two-Pin Chip Interface
Modeling the future of semiconductors (and test!)
Testing and Diagnosis of Interconnects Using Boundary Scan Architecture
Soft Failure Detection and Correction in Microprocessor Characterization
VAST: Virtualization-Assisted Concurrent Autonomous Self-Test
An effective functional safety solution for automotive systems-on-chip
A Parameterized VHDL Library for On-Line Testing
A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability
Thin Gate Oxide Reliability
The Linear Array Systolic Tester (LAST)
The HASS development process
A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter
Microelectromechanical systems (MEMS) tutorial
A built-in timing parametric measurement unit
Automatic Location of IC Design Errors Using Beam System
An Algorithmic Approach to the Testing of a Wafer Scale Integrated (WSI) Circuit
Achieving Sub 100 DPPM Defect Levels on VDSM and Nanometer ASICs
Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005
Stress, Test, and Simulation of Analog IOs on Automotive ICs
Design and test of analog circuits towards sub-ppm level
System reliability evaluation using concurrent multi-level simulation of structural faults
Gate delay ratio model for unified path delay analysis
Higher Certainty of Error Coverage by Output Data Modification
Improving Board and System Test: A Proposal to Integrate Boundary Scan and I DDQ
Practical active compensation techniques for ATE power supply response for testing of mixed signal data storage SOCs
A Roadmap for Boundary-Scan Test Reuse
An Algorithm to Test Rams for Physical Neighborhood Pattern Sensitive Faults
The Sequential ATPG: A Theoretical Limit
Critical roles of RF and microwave electromagnetic field solver simulators in multi-gigabit high-speed digital applications
A generic and reconfigurable test paradigm using Low-cost integrated Poly-Si TFTs
System Test: What is it? Why Bother Defining It?
System Test: Applications of Control Interface Testing
Collaboration and teamwork obstacles
MCM Test Trade-Offs
Effective and Efficient Test Architecture Design for SOCs
Systematic defect screening in controlled experiments using volume diagnosis
Optimizing Boundary Scan in a Proprietary Environment
Small Delay Defect Diagnosis via Timing-Aware Fault Simulation with Variant Delay Insertion
Faster defect localization in nanometer technology based on defective cell diagnosis
Test Grading the 68332
Testing DSM ASIC With Static, \DeltaIDDQ, And Dynamic Test Suite: Implementation And Results
Tabular Mechanisation for Flexible Testing of Microprocessors
Why Automate Optical Inspection?
Improving Test Quality of Memory Chips by a Decision Tree-Based Screening Method
Partnering with customer to achieve high yield
A Detailed Analysis of GOS Defects in MOS Transistors: Testing Implications at Circuit Level
Optimal production test times through adaptive test programming
Doing more with less - An IEEE 1149.7 embedded tutorial : Standard for reduced-pin and enhanced-functionality test access port and boundary-scan architecture
Safe AI for CPS (Invited Paper)
An outlier detection based approach for PCB testing
PGTOOL: An Automatic Interactive Program Generation Tool for Testing New-Generation Memory Devices
New Directions for VLSI Test Systems
Capacitive sensing testability in complex memory devices
Distributed Layout Verification Using Sequential Software and Standard Hardware
Is Scan (Alone) Sufficient to Test Today?s Microprocessors? Not Quite, but We Can?t Get the Job Done Without It
On Behavior Fault Modeling for Combinational Digital Designs
Smart Sampling for Efficient System Level Test: A Robust Machine Learning Approach
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test
Using EDIF for Transfer of Test Data: Practical Experience
Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Scan Testing
RF Introduction and Analog Junction Techniques for Finding Opens
China Test Conference (CTC) - Extending the Global Test Forum to China
Scan Design Oriented Test Technique for VLSI's Using ATE
A Common Pascal Test Language: Reality or Pipedream
Multiple Distributions for Biased Random Test Patterns
Functional test and diagnosis: a proposed JTAG sample mode scan tester
A Unique Methodology for At-Speed Test of cDSP TM and ASIC Devices
Effectiveness Improvement of ECR Tests
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
An interactive environment for the transparent logic simulation and testing of integrated circuits
Diagnosing multiple faulty chains with low pin convolution compressor using compressed production test set
Applications of the IEEE P1149.5 Module Test and Maintenance Bus
The Heisenberg Uncertainty of Test
Position Statement: Testing in a VLSI Design Course
Cultural Evolution in Software Testing
On-chip constrained random stimuli generation for post-silicon validation using compact masks
Complete self-test architecture for a coprocessor [cryptography]
Effects of Multi-Product, Small-Sized Production of LSIs Packaged in Various Packages on the Final Test Process Efficiency and Cost
An Efficient and Effective Methodology on the Multiple Fault Diagnosis
Detecting memory faults in the presence of bit line coupling in SRAM devices
Testability Features of the SuperSPARC tm
On Accurate Modeling and Efficient Simulation of CMOS Opens
Will Testability Analysis Replace Fault Simulation ?
Multi-site test of RF transceivers on low-cost digital ATE
Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains
ATWIG, An Automatic Test Pattern Generator with Inherent Guidance
Deep Submicron: Is Test Up to the Challenge?
Towards a Test Standard for Board and System Level Mixed-Signal Interconnects
Low Overhead Built-In Testable Error Detection and Correction with Excellent Fault Coverage
ATE-based functional ISDN testing
Fast and accurate testing of ISDN S/T interface devices using pseudo error rate techniques
Digital Integrated Circuit Testing using Transient Signal Analysis
Hidden Cost Considerations in Long Term Use of ATE Programs
Influence of Automated Test Equipment Drift on Process Capability Studies
Test and debug solutions for 3D-stacked integrated circuits
A BIST scheme for the detection of path-delay faults
Low Cost Concurrent Error Detection for the Advanced Encryption Standard
Time Specification Conformance of VLSI Test Systems O5
True non-intrusive sensors for RF built-in test
Compositional verification using formal analysis for a flight critical system
Optimized Circuit Failure Prediction for Aging: Practicality and Promise
Turning Test Data into Information
CMOS IC diagnostics using the luminescence of OFF-state leakage currents
Automated Testing of Open Software Standards
Fixed-Biased Pseudorandom Built-In Self-Test for Random-Pattern-Resistant Circuits
A good excuse for reuse: "open" TAP controller design
An Effective BIST Scheme for Arithmetic Logic Units
Designing Testable Synchronous Logic
Modular Mixed Signal Testing: High Speed or High Resolution
Thwarting analog IC piracy via combinational locking
An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs
Understanding Vmin Failures for Improved Testing of Timing Marginalities
Brain-inspired computing
Membrane Probe Card Technology (the Future for High Performance Wafer Test)
Characterization and optimization of the production probing process
Method of reducing contactor effect when testing high-precision ADCs
Detection of Internal Stuck-open Faults in Scan Chains
IEEE P1687: Toward Standardized Access of Embedded Instrumentation
Enhanced ML-Based Approach for Functional Safety Improvement in Automotive AMS Circuits
Automotive keynote: Look Mom! No hands!
Memory Embedded VLSI Gate Array Testing
To Measure Quality in the Manufacturing of Printed Circuit Boards
Multiple tests for each gate delay fault: higher coverage and lower test application cost
MRAM Defect Analysis and Fault Modeli
Probabilistic mixed-model fault diagnosis
Protecting against emerging vmin failures in advanced technology nodes
The Search for the Universal Probe Card Solution
Will "Heisenberg Uncertainty Principle" Hold For Designing and Testing Multiple GB/s ICs?
Testing high speed high accuracy analog to digital converters embedded in systems on a chip
Testability Features of the MC68020
Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications
Direct Cell-Stability Test Techniques for an SRAM Macro with Asymmetric Cell-Bias-Voltage Modulation
On static test compaction and test pattern ordering for scan designs
Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis
Upset-Tolerant CMOS SRAM Using Current Monitoring: Prototype and Test Experiments
Tolerance of performance degrading faults for effective yield improvement
CMOS Checkers with Testable Bridging and Transistor Stuck-on Faults
A practical scan re-use scheme for system test
Autonomous Yet Deterministic Test of SOC Cores
Applying Vstress and defect activation coverage to produce zero-defect mixed-signal automotive ICs
Power Supply Noise Testing of VLSI Chips
SMART: Scalable and Modular Architecture for Routing-Aware Testing of Fan-out Wafer-Level Packages *
Advances in Probe Technology: Best Sessions of the'97 Southwest Test Workshop
ATE and test equipment vendors; Hardware not software
A Low-Cost High-Performance CMOS Timing Vernier for ATE
The KARL/KARATE System: Automatic Test Pattern Generation Based on RT Level Descriptions
X-alignment techniques for improving the observability of response compactors
A Discussion of Methods for Measuring Low-Amplitude Jitter
Selection of potentially testable path delay faults for test generation
RF Calibration in ATE Systems
Estimating burn-in fall-out for redundant memory
Achieving higher yield through diagnosis
Guided Inconsistent Path Sensitization: Method And Experimental Results
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
Versatile BIST: an integrated approach to on-line/off-line BIST
Measuring jitter of high speed data channels using undersampling techniques
TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning
XLBIST: X-Tolerant Logic BIST
A novel array-based test methodology for local process variation monitoring
A Hybrid A/D Converter with 120dB SNR and -125dB THD
NoC Reconfiguration for Utilizing the Largest Fault-free Connected Sub-structure
AutoRex: An automated post-silicon clock tuning tool
The future of delta I_DDQ testing
A Critical Path Selection Method for Delay Testing
Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board
Failure modes for stiction in surface-micromachined MEMS
Deterministic Self-Test of a High-Speed Embedded Memory and Logic Processor Subsystem
Power Supply Noise in Delay Testing
Modeling Test Escape Rate as a Function of Multiple Coverages
IEEE P1149.5 to 1149.1 Data and Protocol Conversion
Data-driven models for statistical testing: measurements, estimates and residuals
Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing
Embedded Memory Field Returns - Trials and Tribulations
Background Receiver IQ Imbalance Correction for in-Field and Post-Production Testing and Calibration
34.1Gbps Low Jitter, Low BER High-Speed Parallel CMOS Interface for Interconnections in High-Speed Memory Test System
Extracting gate-level networks from simulation tables
ADC linearity testing method with single analog monitoring port
Novel Eye Diagram Estimation Technique to Assess Signal Integrity in High-Speed Memory Test
A test point selection method for data converters using Rademacher functions and wavelet transforms
Case History of Networking a Wafer-Sort Area
IEEE International Test Conference, ITC 2019, Washington, DC, USA, November 9-15, 2019
Testing of interposer-based 2.5D integrated circuits
A New Hardware Fault Insertion Scheme for System Diagnostics Verification
Ned Kornfield Memorial
A Generic Test Path and DUT Model for DataCom ATE
Maintaing Quality, Poductivity and Profit in a Changing Bell System
Minimal area test points for deterministic patterns
IEEE P1581 - Getting More Board Test Out of Boundary Scan
Novel Optical Probing System with Submicron Spatial Resolution for Internal Diagnosis of VLSI Circuits
Low Cost Testing of High Density Logic Components
LSI Self-Test Using Level Sensitive Scan Design and Signature Analysis
2014 International Test Conference, ITC 2014, Seattle, WA, USA, October 20-23, 2014
Multi-cell characterization: Developing robust cells and abstraction for Rapid Single Flux Quantum (RSFQ) Logic
Writing Correct and Usable Specifications for Board Test: A Case Study
A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs
Facilitating Rapid First Silicon Debug
The Design and Construction of a Rule Base and an Inference Engine for Test System Diagnosis
SRAM-based FPGA's: testing the LUT/RAM modules
Automating ASIC Design-for-Testability: The VLSI Test Assistant
A Test Methodology for VLSI Chips on Silicon
A Hybrid Fault Simulator for Synchronous Sequential Circuits
Testing Fully Testable Systems: A Case Study
Parity-Scan Design to Reduce the Cost of Test Application
A/MS BISTs: The FACTS, Just the Facts
Artificial Intelligence in Semiconductor Manufacturing for Process Development, Functional Diagnostics, and Yield Crash Prevention
Interconnect testing of boards with partial boundary scan
VLSI Test Exercise Courses for Students in EE Department
Defect level prediction for I_DDQ testing
X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture
Test Strategies for Nanometer Technologies
An Evaluation of the 2816 EEPROM
Analog/Digital Testing of Loaded Boards Without Dedicated Test Points
On the Integration of Design and Manufacturing for Improved Testability
Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues
Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM
Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing
International Test Conference in Asia (ITC-Asia) - Bridging ITC and Test Community in Asia
Silicon Photonic Test-Point Selection by Integrating Design Parameters with Hypergraph Partitioning
LSSD Compatible and Concurrently Testable Ram
Functional Test Coverage Effectiveness on the Decline
Realizing High Test Quality Goals with Smart Test Resource Usage
3B21D BIST/Boundary-Scan System Diagnostic Test Story
A novel combinational testability analysis by considering signal correlation
Design of an Efficient Weighted-Random-Pattern Generation System
TRIM : Testability Range by Ignoring the Memory
Modular Extension of ATE to 5 Gbps
Test support processors for enhanced testability of high performance circuits
Today a Collection of Modules: Tomorrow a System
Neighbor selection for variance reduction in I_DDQ and other parametric data
Security EDA Extension through P1687.1 and 1687 Callbacks
Optimal placement of IEEE 1149.1 test port and boundary scan resources for wafer scale integration
Statistical Yield Modeling for Sub-wavelength Lithography
HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk
An Improved Method of ADC Jitter Measurement
Industrial Relevance of Analog IFA: A Fact or a Fiction
On New Class of Test Points and Their Applications
A Working Approach to Volume CODEC Testing
A DLL-based test solution for through silicon via (TSV) in 3D-stacked ICs
Built-in System Test and Fault Location
Faster, Better, Cheaper: What Does This Mean For The Test Industry?
An Advanced Data Compaction Approach for Test During Burn-In
VDD Ramp Testing for RF Circuits
Stepped parity: A low-cost multiple bit upset detection technique
Mask versus Schematic - an enhanced design-verification flow for first silicon success
The Series/1 as a Test System Controller for System Verification and Calibration
Transparent BIST for RAMs
RTRAM: Reconfigurable and Testable Multi-Bit RAM Design
IEEE P1687 IJTAG a presentation of current technology
Interconnect Test Pattern Generation Algorithm For Meeting Device and Global SSO Limits With Safe Initial Vectors
In circuit test (ICT): The king is dead; long live the king!
FakeFault: a silicon debug software tool for microprocessor embedded memory arrays
Which defects are most critical? optimizing test sets to minimize failures due to test escapes
Self Diagnostics on System Level by Design
Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits
High speed digital transceivers: A challenge for manufacturing
A Concurrent Testing Strategy for PLAs
PowerPC TM Array Verification Methodology using Formal Techniques
Cost Analysis of Test Method Environments
Simulation of transients caused by single-event upsets in combinational logic
Novel technique for built-in self-test of FPGA interconnects
FPGA Synthesis of Arbitrary Jitter Injection for Multi-GHz Test Signals
Embedded Trace: A Key Enabler for Silicon Lifecycle Management
Online Fault Detection in ReRAM-Based Computing Systems by Monitoring Dynamic Power Consumption
ATPG for ultra-large structured designs
Emerging Technologies Drive Domain-Specific Solutions