yusuke1997/dblp-id-title huggingface dataset:
Improving Wireless Product Testing: An Opportunity for University and Industry Collaboratio
Circuit Design for Built-in Current Testing
High-Density CMOS Multichip-Module Testing and Diagnosis
Data Verification: A Prerequisite for Heuristic Diagnostics
Experimental Comparison of Multiplexing Methods for 28 to 64 Gbps NRZ Test Signals
Programmable Daisychaining of Microelectrodes for IP Protection in MEDA Biochips
Modeling TSV open defects in 3D-stacked DRAM
SoC Security Verification using Property Checking
Is Backside the New Backdoor in Modern SoCs?: Invited Paper
Methods of Assignment of Nodes to Pins for Multiplexed Testers
Finding Opens with Optics
Accuracy and Repeatability with DSP Test Methods
An automated formal-based approach for reducing undetected faults in ISO 26262 hardware compliant designs
Multi-Port Test Data Supply System
Bridging the gap between embedded test and ATE
Statistical analysis and optimization of parametric delay test
Multiscan-Based Test Compression and Hardware Decompression Using LZ77
A test probe for TSV using resonant inductive coupling
Enhancing Device Test Programming Productivity: The CATalyst Automated Test Program Generator
Consequences of port restrictions on testing two-port memories
Approaches to Circuit Level Design for Testability
Wafer probe test cost reduction of an RF/A device by automatic testset minimization - A case study
Teaching Llamas to Test: A Language-Based Approach
Current testing
CP-Bench: A PyTorch Test Suite to Detect AI Hardware Failure, Performance Degradation, and Silent Data Corruption
Applications of Hierarchical Test
Proceedings IEEE International Test Conference 1994, TEST: The Next 25 Years, Washington, DC, USA, October 2-6, 1994
Finding power/ground defects on connectors - a new approach
A comparison of classical scheduling approaches in power-constrained block-test scheduling
Back Annotation of Physical Defects into Gate-Level, Realistic Faults in Digital ICs
An Open Architecture for Semiconductor Test: Enablers and Challenges
Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests
Risk Assessment Sampling Plans for Non-Standard (Maverick) Material
A method to calculate necessary assignments in algorithmic test pattern generation
ATPG Padding And ATE Vector Repeat Per Port For Reducing Test Data Volume
A Self-Test System Architecture for Reconfigurable WSI
On automatic testpoint insertion in sequential circuits
Decision Selection and Learning for an All-Solutions ATPG Engine
An Intelligent Approach to Automatic Test Equipment
Testability Features of the MC68851 PMMU
Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard
Unraveling Variability for Process/Product Improvement
Standardization of ATE Timing Accuracy Specifications
Testing high-frequency and low-power designs: Do the standard rules and tools apply?
Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment
Structural Test and Functional Test for Digital Acoustofluidic Biochips
A stand-alone integrated test core for time and frequency domain measurements
Semiconductor Test Equipment Viewed as an Auto-Alignment System
TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning
Inhomogeneous Cellular Automata for Weighted-Random-Pattern Generation
Achieving higher yield through diagnosis?
A kernel-based approach for functional test program generation
Self-Learning Signature Analysis for Non-Volatile Memory Testing
IEEE 1149.1 Growing Pains
Waveform: A Software Tool for Efficient Test Program Development
Co-development of test electronics and PCI Express interface for a multi-Gbps optical switching network
Test Quality: Required Stuck-at Fault Coverage with the Use of I DDQ Testing
Top ten challenges in Big Data security and privacy
Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation
Active Tester Interface Unit Design For Data Collection
On Close-to-Functional Test Sequences
Hierarchical DFT Methodology - A Case Study
PXI: A Solution For Board Functional Test?
Industrial evaluation of DRAM SIMM tests
Practical Application of Statistical Process Control in Semiconductor Manufacturing
The Error Latency of Delay Faults in Combinational and Sequential Circuits
Field System Test Strategies for the 1980's
EAGLE: A regression model for fault coverage estimation using a simulation based metric
Fine pitch (45 micron) P4 probing
Testability Design for Micro/370, a System/370 Single Chip Microprocessor
Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems
Impact of Radial defect clustering on 3D stacked IC yield from wafer to wafer stacking
Testing the IBM Power 7™ 4 GHz eight core microprocessor
Efficient O(sqrt(n)) BIST Algorithms for DDNPS Faults in Dual-Port Memories
On-chip Timing Uncertainty Measurements on IBM Microprocessors
Analysis and Definition of Overall Timing Accuracy in VLSI Test System
Evaluating Vulnerability of Chiplet-Based Systems to Contactless Probing Techniques
Multi-GHz loopback testing using MEMs switches and SiGe logic
System Test Visibility Or Why Can't You Test Your Electronics
Observations on the 1149.x Family of Standards
Vesuvius-3D: A 3D-DfT demonstrator
An LSSD Pseudo Random Pattern Test System
ARNOLD: Applying an AI Workstation to Production Test Code Generation
IC Burn-In : The Changing Scene
Techniques for Concurrent Testing of VLSI Processor Operation
Fault diagnosis for embedded read-only memories
Chasing subtle embedded RAM defects for nanometer technologies
Next-Generation PowerPC TM Microprocessor Test Strategy Improvements
ASIC jeopardy-diagnosing without a FAB
An histogram based procedure for current testing of active defects
Functional Test Generation for LSI Circuits Described by Binary Decision Diagrams
Analyzing the Effectiveness of Multiple-Detect Test Sets
A Testable Realization of CMOS Combinational Circuits
Revisit to Accurate ADC Testing with Incoherent Sampling Using Proper Sinusoidal Signal and Sampling Frequencies
An Automated F-Beam Tester with CAD Interface, "Finder": A Powerful Tool for Fault Diagnosis of ASICs
Efficient Testing of Software Modifications
Multiplexing test system channels for data rates above 1 Gb/s
Plug and Play or Plug and Pray: We Have a Right to Know It Will Work (Or Why It Won't)
Data Mining Integrated Circuit Fails with Fail Commonalities
Safely backdriving low voltage devices at in-circuit test
Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ
RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage
Case Study and Advanced Functional Safety Solution for Automotive SoCs
Improved wafer-level spatial analysis for I_DDQ limit setting
Design-For-Testability Economics
Control and Observation of Analog Nodes in Mixed-Signal Boards
Analyzing ATE interconnect performance for serial links of 10 Gbps and above
Programmable Logic: Testability by Design
Error prediction and detection methodologies for reliable circuit operation under NBTI
A scalable and efficient methodology to extract two node bridges from large industrial circuits
On invalidation mechanisms for non-robust delay tests
Early-life-failure detection using SAT-based ATPG
Operations Management and Analysis in the Management of Electronic Testing
Definitions of jitter measurement terms and relationships
Machine learning-based defense against process-aware attacks on Industrial Control Systems
The testability features of the MCF5407 containing the 4th generation ColdFire(R) microprocessor core
Teaching an old dog new tricks: Views on the future of mixed-signal IC design
A Novel Instrument for Accurate Time Measurement in Automatic Calibration of Test Systems
A Tag based solution for efficient utilization of efuse for memory repair
CMOS Built-In Test Architecture for High-Speed Jitter Measurement
Delayed-RF Based Test Development for FM Transceivers Using Signature Analysis
An enhanced procedure for calculating dynamic properties of high-performance DAC on ATE
Lightweight Timing Channel Protection for Shared DRAM Controller
2013 IEEE International Test Conference, ITC 2013, Anaheim, CA, USA, September 6-13, 2013
A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories
Test point insertion for compact test sets
Automated mapping of pre-computed module-level test sequences to processor instructions
Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs
A Sequential Circuit Test Generation System
The Key to Concurrent Engineering is Design Tools
High-Performance Production Test Contractors for Fine-Pitch Integrated Circuits
Experimental Results for Current-Based Analog Scan
Position of Component Testing in Total Quality Management (TQM)
Design and analysis of multiple weight linear compactors of responses containing unknown values
Rule Based Testability Checker and Test Generator
Best paper award winners
Robust Design-for-Productization Practices for High Quality Automotive Products
DFM-aware fault model and ATPG for intra-cell and inter-cell defects
Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects
Is an Open Architecture Tester Really Achievable?
Virtual Prototyping: Closing the digital gap between product requirements and post-Si verification
BISTing data paths at behavioral level
Exploiting Application Tolerance for Functional Safety
Implementing a Self-Managed Test Vector Memory with One Million Elements
A New Pin Electronics Architecture for High Performance Functional Module Testing
Kernel based clustering for quality improvement and excursion detection
Soft error reliability aware placement and routing for FPGAs
Which concurrent error detection scheme to choose ?
Architecture for Testing Multi-Voltage Domain SOC
Enhancing Timing Predictability in Automotive Electronics: Addressing Aging and Temperature Distributions
Parallel Delay Fault Coverage and Test Quality Evaluation
EDT bandwidth management - Practical scenarios for large SoC designs
Design of a New Test Generation System for Performance Testing of LSI Digital Printed Circuit Boards
Active reliability monitor: Defect level extrinsic reliability monitoring on 22nm POWER8 and zSeries processors
Proceedings International Test Conference 1989, Washington, D.C., USA, August 1989
On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressing
High-Level Test Generation Using Symbolic Scheduling
Testing for parametric faults in static CMOS circuits
Testability Analysis and ATPG on Behavioral RT-Level VHDL
On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults
The Economics of Scan Design
A fully digital-compatible BIST strategy for ADC linearity testing
Towards Microagent based DBIST/DBISR
Self-Test for Microprocessors
Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology
Panel Synopsis - Diagnosis Meets Physical Failure Analysis: How Long Can We Succeed?
Yield optimization using advanced statistical correlation methods
DARS: An EDA Framework for Reliability and Functional Safety Management of System-on-Chips
A novel scan segmentation design method for avoiding shift timing failure in scan testing
FeTest: Defect Analysis and March Test Solution for FeFETs *
Low cost automatic mixed-signal board test using IEEE 1149.4
High Performance Pin Electronics with GaAs, A Contradiction in Terms?
Push-on mating 57- to 81- GHz mm-Wave interface with high repeatability for ATE application
IEA-Plot: Conducting Wafer-Based Data Analytics Through Chat
An SOC Test Integration Platform and Its Industrial Realization
Built-In Test for CMOS Circuits
An Effective BIST Scheme for Booth Multipliers
Generating Tests for Physical Failures in MOS Logic Circuits
The Consequences of an Open ATE Architecture
Diagnostic techniques for the IBM S/390 600 MHz G5 microprocessor
WTPGA : A Novel Weighted Test Pattern Generation Approach for VLSI Built-In Self-Test
A Digital Polarity Correlator Featuring Built-In Self Test and Self Repair Mechanisms
A phase noise spectrum test solution for high volume mixed signal/wireless automatic test equipments
Constructive Multi-Phase Test Point Insertion for Scan-Based BIST
Transistor Fault Coverage for Self-Testing CMOS Checkers
Testing the Sperry 36/72 Bit CMOS Micromainframe Chip Set
Increasing the performance of arbitrary waveform generators using sigma-delta coding techniques
The IBM Maintenance Device
The Role of Test in a Highly Outsourced Business Model
PADRE: Physically-Aware Diagnostic Resolution Enhancement
State transition graph analysis as a key to BIST fault coverage
Test Strategies for a Family of Complex MCMs
Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance
Key Impediments to DFT-Focused Test and How to Overcome Them
A graph-based algorithm for NVM address decoders testing
Test and on-line debug capabilities of IEEE Std 1149.1 in UltraSPARC-III microprocessor
Column parity and row selection (CPRS): a BIST diagnosis technique for multiple errors in multiple scan chains
Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS Circuits
Towards an automatic diagnosis for high-level design validation
A Flexible Database System and Its Application in VLSI Process Development
Test connections - tying application to process
An efficient diagnosis-aware pattern generation procedure for transition faults
Signal Generation Using Periodic Single-and Multi-Bit Sigma-Delta Modulated Streams
A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects
An Autonomous System View To Apply Machine Learning
Automotive Industry: The Next DFT Challenge
Syndrome-Testable Design of Programmable Logic Arrays
A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time
FFT Based Troubleshooting of 120dB Dynamic Range ADC Systems
Analog AC Harmonic Method for Detecting Solder Opens
Practical optical waveform probing of flip-chip CMOS devices
Using ILA Testing for BIST in FPGAs
AXIe®: Open architecture test system standard
Don't Eliminate Incoming Test - Move It
A test site thermal control system for at-speed manufacturing testing
Test methodology for a microprocessor with partial scan
An Intelligent Knowledge-Based System Tool for High-Level BIST Design
An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists
Systematic and Structured Methods for Digital Board Testing
Testing an Audio Spectrum Analyzer for Speech Recognition Systems
Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques
Delay Testing with Clock Control: An Alternative to Enhanced Scan
Thoughts on VLSI Burn-in
Two-Stage Fault Location
What Do You Mean My Board Test Stinks?
Scan Test for 99% Defect Coverage of R-2R DACs
Embedded At-Speed Test Probe
A scanisland based design enabling prebond testability in die-stacked microprocessors
The PXI carrier: a novel approach to ATE instrument development
Divide and Conquer based Fast Shmoo algorithms
SASPL: A Test Program Productivity Analysis Tool
Design-for-reliability: A soft error case study
A Testing Technique to Characterize E^2PROM's Aging and Endurance
Testing of Analog Circuits using Statistical and Machine Learning Techniques
FANTESTIC: Towards a Powerful Fault Analysis and Test Pattern Generator for Integrated Circuits
Clustering-based failure triage for RTL regression debugging
Multiple-Fault Simulation and Coverage of Deterministic Single-Fault Test Sets
Fast co-test of linearity and spectral performance with non-coherent sampled and amplitude clipped data
Welcoming Message
An NBS Calibration Service for A/D and D/A Converters
Transfer Functions For The Reference Clock Jitter In A Serial Link: Theory And Applications
Testability-Oriented Hardware/Software Partitioning
Reduction of errors due to source and meter in the nonlinearity test
Advancements in at-speed array BIST: multiple improvements
On the Testing of Multiplexers
Modeling and Testing Process Variation in Nanometer CMOS
Early Testing of Memory Redundant Row Elements
On concurrent test of wrapped cores and unwrapped logic blocks in SOCs
Test/ATE vision 2020 - Entrepreneurship in test CEO panel
Gate exhaustive testing
Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits
GPU-Based Concurrent Static Learning
Error masking in self-testable circuits
The design-for-testability features of a general purpose microprocessor
The Critical Need For Open ATE Architecture
Extending Calibration Intervals
The boundary-scan master: target applications and functional requirements
On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums
Characterization of Library Cells for Open-circuit Defect Exposure: A Systematic Methodology
Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation
Hardware for production test of RFID interface embedded into chips for smart cards and labels used in contactless applications
EE Curriculum - Continuous Process Improvement?
Hybrid Design for Testability Combining Scan and Clock Line Control and Method for Test Generation
Some considerations on choosing an outlier method for automotive product lines
Impact of Boundary Scan Design on Delay Test
Test Pattern Development and Evaluation for DRAMs with Fault Simulator RAMSIM
Beyond 10 Gbps? Challenges of Characterizing Future I/O Interfaces with Automated Test Equipment
Microgrids as a resiliency resource
Test Strategy Cost Model Innovations
Testing System for Redundant Memory
An accurate simulation model of the ATE test environment for very high speed devices
Cost of Test - Taking Control
On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability
Test Generation In Lamp2: Concepts and Algorithms
A Predictable Robust Fully Programmable Analog Gaussian Noise Source for Mixed-Signal/Digital ATE
Testability Features in the TMS370 Family of Microcomputers
Test features of a core-based co-processor array for video applications
Practical random sampling of potential defects for analog fault simulation
Using transition test to understand timing behavior of logic circuits on UltraSPARC TM T2 family
Designing the VLSI Device-to-Board Test Ukraine Translator
Logic Test Vehicles for High Resolution Diagnosis of Systematic FEOL/MEOL Yield Detractors
21-Bit Precision and High-Speed DC Measurement System
RF test accuracy and capacity enhancement on ATE for silicon TV tuners
Using symbolic canceling to improve diagnosis from compacted response
An Automatic Post Silicon Clock Tuning System for Improving System Performance based on Tester Measurements
The Many Faces of Test Synthesis
What is IEEE P1149.8.1 and why?
Complete, Contactless I/O Testing - Reaching the Boundary in Minimizing Digital IC Testing Cost
A Generic Method to Develop a Defect Monitoring System for IC Processes
Software Solutions Enhance ATE Networking Capabilities
Learning to knit SOCs profitably
Practical Instrumentation Integration Considerations
Solving Known Good Die (and Substrate) Test Issues
Diagnosis of Logic-to-chain Bridging Faults
Four Multi Probing Test for 16 Bit DAC with Vertical Contact Probe Card
The Challenge of Testing VLSI in the 1980's
IEEE P1149.4-Almost a Standard
When zero picoseconds edge placement accuracy is not enough
Electrical Stimulus Based Calibration of MEMS Accelerometer
SOC Test Optimization with Compression-Technique Selection
Exploiting defect clustering to screen bare die for infant mortality failures: an experimental study
Measuring code edges of ADCs using interpolation and its application to offset and gain error testing
Non-Conventional Faults in BiCMOS Digital Circuits
An improved Test Control Architecture and Test Control Expansion for Core-Based System Chips
DFX of a 3 rd Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor
Design for testability: it is time to deliver it for Time-to-Market
High Performance Monolithic Verniers for VLSI Automatic Test Equipment
CAD Tools for Supporting System Design for Testability
Design-for-test methods for stand-alone SRAMs at 1 Gb/s/pin and beyond
Design Goals and Implementation Techniques for Time-Based Digital Simulation and Hazard Detection
System Testing: The Future for All of Us
Board Test DFT Model for Computer Products
Board Life-Cycle Testing For Effective NPI Management of Wireless Products
Timing-Per-Pin Flexibility at Shared-Resource Cost
End-to-End Test Strategy for Wireless Systems
Scan Diagnostic Strategy for the Series 10000 Prism Workstation
Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application
At-speed structural test
Easing the Transition from Design to Test
I-Q signal generation techniques for communication IC testing and ATE systems
The DASS Needs You ! : An Update on the Activities of the DASS
A Real-Time Delta-Time-to-Voltage Converter for Clock Jitter Measurement
Security vs. Test Quality: Fully Embedded Test Approaches Are the Key to Having Both
Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests
Testing in the Data Communications Industries
Testing the Digital Modulation of PHS Devices
Achieving Complete Delay Fault Testability by Extra Inputs
Languages to Support Boundary-Scan Test
Optimized EVM Testing for IEEE 802.11a/n RF ICs
Data jitter measurement using a delta-time-to-voltage converter method
High-level ATPG for Early Power Analysis
Concurrent Testing of Flow of Control in Simple Microprogrammed Control Units
Global Control Signal Defect Diagnosis in Volume Production Environment
Fundamentals of timing information for test: How simple can we get?
Thermal Management in System Level Test: Analysis of existing solutions and an introduction to advanced liquid cooled memory solutions
Test evaluation and data on defect-oriented BIST architecture for high-speed PLL
Test Application Timing: The Unexplored Issue in AC Test
A new test/diagnosis/rework model for use in technical cost modeling of electronic systems assembly
Merging Concurrent Checking and Off-line BIST
Test: when is enough enough?
Criteria for analyzing high frequency testing performance of VLSI automatic test equipment
Analysis of interconnect crosstalk defect coverage of test sets
Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal
Future Trends in Test: The Adoption and Use of Low Cost Structural Testers
Plan Ahead for Yield
Space and time compaction schemes for embedded cores
Design for soft-error robustness to rescue deep submicron scaling
A Mixed-Mode Built-In Self-Test Technique Using Scan Path and Signature Analysis
Test Program Optimization Techniques for a High Speed Performance VLSI Tester
Microprocessor silicon debug based on failure propagation tracing
Economic Impact of Type I Test Errors at System and Board Levels
IEEE International Test Conference, ITC 2025, San Diego, CA, USA, September 20-26, 2025
A fine pitch probe technology for VLSI wafer testing
Robust Pattern Generation for Small Delay Faults Under Process Variations
Implicit test generation for behavioral VHDL models
SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states
Effective oscillation-based test for application to a DTMF filter bank
Implementing Boundary-Scan and Pseudo-Random BIST in an Asynchronous Transfer Mode Switch
Fault Modeling and Testing of Chiplet-to-Chiplet Interconnects in Fan-out Wafer-Level Packaging *
A low-cost ATE phase signal generation technique for test applications
Testing Issues at the University of Texas
A practical perspective on reducing ASIC NTFs
Mission Possible? Open Architecture ATE
Accessing 1687 systems using arbitrary protocols
: Test Scheduling for High Performance VLSI System Implementations
An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264
Post-manufacturing ECC customization based on Orthogonal Latin Square codes and its application to ultra-low power caches
A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing
A Methodology for Testing Content Addressable Memories
Symbolic Test Generation for Hierarchically Modeled Digital Systems