yusuke1997/dblp-id-title huggingface dataset:
Production test enhancement techniques for MB-OFDM ultra-wide band (UWB) devices: EVM and CCDF
Application of under-approximation techniques to functional test generation targeting hard to detect stuck-at faults
Sequential Test Generation Based on Real-Value Logic
A Path Selection Flow for Functional Path Ring Oscillators using Physical Design Data
Soft errors: is the concern for soft-errors overblown?
On Freedom from Interference in Mixed-Criticality Systems: A Causal Learning Approach
Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data
Distractions in Design for Testability and Built-Is Self-Test
Streamlining programmable device and system test using IEEE Std 1532
Design for In-System Programming
Unsupervised Learning Provides Intelligence for Testing Hard to Detect Faults
The Best Flip-Flops to Scan
Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion
Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique
Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients
Designing Characterization Tests for Bipolar Array Performance Verification
Computational intelligence based testing for semiconductor measurement systems
Stochastic timing error rate estimation under process and temporal variations
Elegant construction of SSC implemented signal by AWG and organized under-sampling of wideband signal
Screening customer returns with multivariate test analysis
AXIe® 2.0 and MVP-C: Open ATE software standards
Disc Drive Testing Instrument
Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems
New Perspectives on Core In-field Path Delay Test
A Suitable Test System for Gate Array
An I DDQ Based Built-in Concurrent Test Technique for Interconnects in a Boundary-Scan Environment
Enhanced launch-off-capture transition fault testing
Design, test & repair methodology for FinFET-based memories
Implementation of Mixed Current/Voltage Testing Using the IEEE P1149.4 Infrastructure
DIST-based detection and diagnosis of multiple faults in FPGAs
Estimating the Required Size of an Automated Test and Repair System from Subassembly Volume and Failure Information
Automated system level functional test program generation on ATE from EDA using Functional Test Abstraction
Overdriving NMOS and CMOS VLSI Circuits
Fault Grading FPGA Interconnect Test Configurations
Design for Test and the Cost of Quality
Designing for Software Testability Using Automated Oracles
2008 IEEE International Test Conference, ITC 2008, Santa Clara, California, USA, October 26-31, 2008
An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures
Programming for Parallel Pattern Generators
Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current
Hard to find, easy to find systematics; just find them
On Accelerating Path Delay Fault Simulation of Long Test Sequences
Mutation-based diagnostic test generation for hardware design error diagnosis
A Conditional Resource-Sharing Method for Behavior Synthesis of Highly- Testable Data Paths
Methodology for and Results from the Use of a Hardware Logic Simulation Engine for Fault Simulation
When Does It Make cents to Give Up Physical Test Access?
The implementation of IEEE Std 1149.1 boundary scan test strategy within a cellular infrastructure production environment
The scan-DFT features of AMD's next-generation microprocessor core
Test Features of the HP PA7100LC Processor
On Test Generation for Iddq Testing of Bridging Faults in CMOS Circuits
Analysis of failures on memories using expert system techniques
Automated Analysis of Static RAM Failures
Jitter Models and Measurement Methods for High-Speed Serial Interconnects
Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor
The Effects of Backdriving Digital Integrated Circuits during In-Circuit Testing
A Realistic Self-Test Machine for Static Random Access Memories
Reducing test cost through the use of digital testers for analog tests
An Analysis of ATE Testing Costs
Testing interconnects for noise and skew in gigahertz SoCs
A Scalable Design Flow for Performance Monitors Using Functional Path Ring Oscillators
An Efficient Self-Test Structure for Sequential Machines
Generation of Optimized Single Distributions of Weights for Random Built-in Self-Test
A random access scans architecture to reduce hardware overhead
Fault distinguishing pattern generation
A Structured Graphical Tool for Analyzing Boundary Scan Violations
Remote access to engineering test-a case study in providing engineering/diagnostic IC test services to Canadian universities
Proceedings IEEE International Test Conference 1997, Washington, DC, USA, November 3-5, 1997
Design of Scan-Based Path-Delay-Testable Sequential Circuits
Structural Testing on SLT Platform with HSAT IP & High-Speed I/O Access
CCD Image Sensor Test Using Cellular Automation-Type Pattern Recognition System
Built-In Self Test Input Generator for Programmable Logic Arrays
A Variation of LSSD and Its Implications on Design and Test Pattern Generation in VLSI
A Tutorial on STDF Fail Datalog Standard
Feature based similarity search with application to speedpath analysis
Performance Characterization of Mixed-Signal Circuits Using a Ternary Signal Representation
System JTAG Initiative Group Advancements
Test access and the testability features of the Poulson multi-core Intel Itanium® processor
LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment
Machine Intelligence for Efficient Test Pattern Generation
FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defects
Testable design and support tool for cell based test
Test Challenges of Nanometer Technology
Logic soft errors: a major barrier to robust platform design
Polynomial Chaos modeling for jitter estimation in high-speed links
AMLETO: a multi-language environment for functional test generation
Self test architecture for testing complex memory structures
Efficient SAT-based ATPG techniques for all multiple stuck-at faults
Scan-Encoded Test Pattern Generation for BIST
Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies
Scalable BIST for Linearity Testing of Sigma-Delta Modulators
Utilizing Boundary Scan to Implement BIST
In Search of the Optimum Test Set - Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost
At-speed logic BIST using a frozen clock testing strategy
Delay Test Generation 1: Concepts and Coverage Metrics
Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits
Test and Repair of Nonvolatile Commodity and Embedded Memories
How are we going to test SoCs on a board?: the users viewpoint
Improving fault diagnosis accuracy by automatic test set modification
Software Convergence of Test Program Parameters
High-Performance Circuit Testing with Slow-Speed Testers
Time margin issues in disk drive testing
Analyss of Dynamic Effects of Resistive Bridging Faults in CMOS and BiCMOS Digital ICs
Pseudo Random Patterns Using Markov Sources for Scan BIST
On-line detection of logic errors due to crosstalk, delay, and transient faults
An on-line monitoring technique for electrode degradation in bio-fluidic microsystems
Partial Hardware Partitioning: A New Pseudo-Exhaustive Test Implementation
Device Models : A New Methodology for a Perennial Problem
System design verification tests - an overview
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations
Realizing the Benefits of Structural Test for Intel Microprocessors
Improving Error Tolerance and Scalability in Pseudo-Boolean SAT-based Generic Side-Channel Analysis
Testing-Based Analysis of Real-Time System Models
Test Pattern Considerations for Fault Tolerant High Density DRAM
A unified test and fault-tolerant multicast solution for network-on-chip designs
A concurrent BIST scheme for on-line/off-line testing based on a pre-computed test set
A built-in self-repair scheme for DRAMs with spare rows, columns, and bits
Structural Tests for Jitter Tolerance in SerDes Receivers
A High-Throughput 5 GBps Timing and Jitter Test Module Featuring Localized Processing
IEEE International Test Conference, ITC 2017, Fort Worth, TX, USA, October 31 - Nov. 2, 2017
Test Quality Improvement with Timing-aware ATPG: Screening small delay defect case study
An economical, precise and limited access In-Circuit Test method for pulse-width modulation (PWM) circuits
An Effective BIST Scheme for Datapaths
The Interaction of Test and Quality
Robust Design-for-Testability Scheme for Conventional and Unique Defects in RRAMs
Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation
A new approach to scan chain reordering using physical design information
Total Critical Area Based Testing
Advanced Test System Software Architecture Blends High Speed with User Friendliness
Lessons from at-speed scan deployment on an Intel® Itanium® microprocessor
Optimal Use of Timing Resources: A Crucial Step in Test Program Generation
Automatic Design of Exhaustively Self-Testing Chips with Bilbo Modules
Is your secure test infrastructure secure enough? : Attacks based on delay test patterns using transient behavior analysis
A Method to Derive Compact Test Sets for Path Delay Faults in Combinational Circuits
On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures
Coping with Re-usability Using Sequential ATPG: A Practical Case Study
Finite state machine synthesis with concurrent error detection
A novel multisite testing techniques by using frequency synthesizer
Advanced fault model, diagnosis and applications for deep nanometer process
Towards Structural Testing of Superconductor Electronics
Random Pattern Testability by Fast Fault Simulation
A Procedural Interface to Test
Concurrent Simulation at the Switch, Gate, and Register Levels
Fast embedded A/D converter testing using the microcontroller's resources
Hardware-based Error Rate Testing of Digital Baseband Communication Systems
Locked-by-Design: Enhancing White-box Logic Obfuscation with Effective Key Mutation
Capture and Shift Toggle Reduction (CASTR) ATPG to Minimize Peak Power Supply Noise
Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis
Transient Power Supply Current Testing of Digital CMOS Circuits
A Layout Driven Design for Testability Technique for MOS VLSI Circuits
Virtual Test of Noise and Jitter Parameters
The Production Implementation of a Linear Error Modeling Technique
Sleuth: A Domain-Based Testing Tool
Domain-Specific Machine Learning Based Minimum Operating Voltage Prediction Using On-Chip Monitor Data
Invisible delay quality - SDQM model lights up what could not be seen
Artificial Intelligence Exchange and Service Tie to All Test Environments (AI-ESTATE)-A New Standard for System Diagnostics
GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs
XWRC: externally-loaded weighted random pattern testing for input test data compression
Linking Diagnostic Software to Hardware Self Test in Telecom Systems
In-Circuit Test Fixture
On efficient silicon debug with flexible trace interconnection fabric
On ATPG for multiple aggressor crosstalk faults in presence of gate delays
Finding a Small Set of Longest Testable Paths that Cover Every Gate
Backplane Test Bus Applications For IEEE STD 1149.1
Employing Multiple Test Techniques for Complex Telecommunications Devices
Latent defect detection in microcontroller embedded flash test using device stress and wordline outlier screening
Signature Testing of Sequential Machines
Critical path identification and delay tests of dynamic circuits
Automatic Linearity (IP3) Test with Built-in Pattern Generator and Analyzer
Towards an Effective I DDQ Test Vector Selection and Application Methodology
Non-Volatile Programmable Devices and In-Circuit Test
Understanding and Improving GPUs' Reliability Combining Beam Experiments with Fault Simulation
Application of non-parametric statistics of the parametric response for defect diagnosis
Robustness Enhancement and Detection Threshold Reduction in ATPG for Gate Delay Faults
A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates
At-Speed Test is not Necessarily an AC Test
Port interference faults in two-port memories
A/MS benchmark circuits for comparing fault simulation, DFT, and test generation methods
Fault Diagnosis in Scan-Based BIST
Overview of IEEE P1450.6.2 Standard; Creating CTL Model For Memory Test and Repair
Experiences with parametric BIST for production testing PLLs with picosecond precision
WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques
Adaptive Diagnosis Points for 100% Chain Diagnosis Coverage
Production Multivariate Outlier Detection Using Principal Components
An Efficient Test Strategy for Detection of Electromigration Impact in Advanced FinFET Memories
Economically Viable Automatic Insertion of Self-Test Features for Custom VLSI
Board Testing II
Zero defects or zero stuck-at faults-CMOS IC process improvement with I DDQ
A Method for Test Generation Directly from Testability Analysis
Functional ATE can meet the challenges
A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation
A 256Meg SDRAM BIST for Disturb Test Application
A suite of IEEE 1687 benchmark networks
Test and Evaluation of Multiple Embedded Mixed-Signal Test Cores
EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism
Fault Detection Effectiveness of Weighted Random Patterns
Delay Testing Using a Matrix of Accessible Storage
Fault Injection Boundary-Scan Design for Verification of Fault-Tolerant Systems
On the Design of Multiple-Input Shift-Registers for Signature Analysis Testing
Characterizing Corruptibility of Logic Locks using ATPG
Implementing bead probe technology for in-circuit test: A case study
A Hierarchical DFT Architecture for Chip, Board and System Test/Debug
: Identifying redundant gate replacements in verification by error modeling
Multiple-output propagation transition fault test
Control Strategies for Chip-Based DFT/BIST Hardware
Conversion of small functional test sets of nonscan blocks to scan patterns
Improving the Effectiveness of Board Test Programmers
Implications of the Technique for Dynamic High Speed Functional Testing
Future ATE for System on a Chip... Some Perspectives
An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit
Novel Architecture for On-Chip AC Characterization of I/Os
On the Evaluation of Software Inspections and Tests
HDL Program Slicing to Reduce Bounded Model Checking Search Overhead
Enabling yield analysis with X-compact
A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter
Using well/substrate bias manipulation to enhance voltage-test-based defect detection
Automated trace signals selection using the RTL descriptions
Digital signature proposal for mixed-signal circuits
Test Generation for an Iterative Design Flow with RTL Changes
Marginal PCB assembly defect detection on DDR3/4 memory bus
Fast Bring-Up of an AI SoC through IEEE 1687 Integrating Embedded TAPs and IEEE 1500 Interfaces
The Impact of a VLSI Test System on the Test Throughput Equation
Implementation of Solder-bead Probing in High Volume Manufacturing
Advanced functional safety mechanisms for embedded memories and IPs in automotive SoCs
PEPR: Pseudo-Exhaustive Physically-Aware Region Testing
A bead probe CAD strategy for in-circuit test
CMOS Design for Improved IC Testability
Dynamic Program Complexity and Software Testing
DIAL : An Automated ATE Service Support System
Training Tomorrow's Test Engineers: Experiences in Teaching an Undergraduate Course in VLSI Testing
Hardware Fault Tolerance for Binary RRAM Crossbars
Accurate anomaly detection using correlation-based time-series analysis in a core router system
On achieving complete coverage of delay faults in full scan circuits using locally available lines
DeepTPI: Test Point Insertion with Deep Reinforcement Learning
FRITS - A Microprocessor Functional BIST Method
Open-short Normalization Method for a Quick Defect Identification in Branched Traces with High-resolution Time-domain Reflectometry
Breaking Analog Locking Techniques via Satisfiability Modulo Theories
Multi-die Parallel Test Fabric for Scalability and Pattern Reusability
A Set of Benchmarks fo Modular Testing of SOCs
Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits
Test: The New Value-Added Field
Pin Margin Analysis
Front-end layout reflection for test chip design
CTL the language for describing core-based test
LESER-2: Detailed Consideration in Latch Design under Process Migration for Prevention of Single-Event Double-Node Upsets
Effects of Deterministic Jitter in a Cable on Jitter Tolerance Measurements
Design reflection for optimal test-chip implementation
Flexible Deep Memory Architecture Aids Program Development
Design for Yield and Reliability is MORE Important Than DFT
Test Logic Economic Considerations in a Commercial VLSI Chip Environment
Modeling trans-threshold correlations for reducing functional test time in ultra-low power systems
Extending the Digital Core-based Test Methodology to Support Mixed-Signal
CMOS IC Stuck-Open Fault Electrical Effects and Design Considerations
An Integrated Built-In Self-Testing and Self-Repair of VLSI/WSI Hexagonal Arrays
IBISTTM (Interconnect Built-in Self-Test) Architecture and Methodology for PCI Express: Intel?s Next-Generation Test and Validation Methodology for Performance IO
Optimizing redundancy design for chip-multiprocessors for flexible utility functions
Loopback or not?
Wireless Test Structure for Integrated Systems
9826A Computer Burn-In Program
Testing for a Solid-State Color Image Sensor
Fault Spectrum: An Analysis of System Level Test with Proposed Solutions
MCM Quality and Cost Analysis Using Economics Models
Fast Automatic Failbit Analysis for DRAMs
Functional Testing of Circuits and SMD Boards with Limited Nodal Access
Comprehensive Fault Model and Testing of CMOS Circuits
Improving Wireless Product Testing via University and Industry Collaboration
EVM Testing of Wireless OFDM Transceivers Using Intelligent Back-End Digital Signal Processing Algorithms
Testing a secure device: High coverage with very low observability
Optimization of Tests for Managing Silicon Defects in Data Centers
On the Measurement of Safe Fault Failure Rates in High-Performance Compute Processors
Coverage-Directed Management and Optimization of Random Functional Verification
The test requirements model (TeRM) communicating test information throughout the product life cycle
Si-emulation: system verification using simulation and emulation
BIST for Deep Submicron ASIC Memories with High Performance Application
Industry leaders panel - How will testing change in the next 10 years?
Test Synthesis in the Behavioral Domain
High Resolution I DDQ Characterization and Testing - Practical Issues
An embedded technique for at-speed interconnect testing
High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns
PROSPECT : A Production System for Partitioning and Evaluating Chip Testability
Detecting delay faults using power supply transient signal analysis
System chip test: are we there yet?
Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses
Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation
Open Architecture ATE: Dream or Reality?
Testing Methodology of Embedded DRAMs
Hardware Acceleration Alone Will Not Make Fault Grading ULSI a Reality
Fault Bundling: Reducing Machine Evaluation Activity in Hierarchical Concurrent Fault Simulation
Alternate Test of RF Front Ends with IP Constraints: Frequency Domain Test Generation and Validation
The Difference Fault Model : Using Functional Fault Simulation to Obtain Implementation Fault Coverage
The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack
Single-pin test control for Big A, little D devices
High quality, easy to use, on time ATE software Can it be done?
Application of Optoelectronic Techniques to High Speed Testing
Deterministic In-Fleet Scan Test for a Cloud Computing Platform
Scaling physically aware logic diagnosis to complex high volume 7nm server processors
Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits
BELLMACT-32 : A Testable 32 bit Microprocessor
Modeling Accuracy of Wideband Power Amplifiers with Memory effects via Measurements
Logic Fault Diagnosis of Hidden Delay Defects
Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital Circuits
Production Test Effectiveness of Combined Automated Inspection and ICT Test Strategies
On-chip versus off-chip test: an artificial dichotomy
EDIF Test - The Upcoming Standard for Test Data Transfers
Trends in manufacturing test methods and their implications
An accurate algorithm for computing mutation coverage in model checking
The Standard Mirror Boards (SMBs) Concept - An Innovative Improvement of Traditional ATE for up to 10 Mil Bare Board Testing
A Gate-Array-Based 666MHz VLSI Test System
The Coverage Problem for Random Testing
Symbol-based health-status analysis in a core router system
A design diversity metric and reliability analysis for redundant systems
A frequency measurement BIST implementation targeting gigahertz application
TRIBuTETM Board and Platform Test Methodology: Intel's Next-Generation Test and Validation Methodology for Platforms
Enhanced testing of clock faults
Looking for Functional Fault Equivalence
Testing for aging in advanced SRAM: From front end of the line transistors to back end of the line interconnects
Jitter minimization technique for mixed signal testing
Automatic Test Program Generation for Mixed Signal ICs via Design to Test Link
Noncontact wafer probe using wireless probe cards
Safe Operating Zones for Digital In-Circuit Testing
High-Speed Functional Testing of Microprocessor-Based Circuit Boards
DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies
Reduced Scan Shift: A New Testing Method for Sequential Circuit
Testability Features for a Submicron Voice-coder ASIC
Testing a 317K bit High Speed Video Memory with a VSLI Test System
Failure Analysis for Full-Scan Circuits
Reducing the Cost of Quality through Test Data Management
Proceedings International Test Conference 1988, Washington, D.C., USA, September 1988
Two New Techniques for Identifying Opens on Printed Circuit Boards: Analog Junction Test & Radio Frequency Induction Test
ScanBIST: A Multi-frequency Scan-based BIST Method
Informed Test Generation Guidance Using Partially Specified Fanout Constraints
Distributed Probabilistic Diagnosis of MCMs on Large Area
A New Array Architecture for Parallel Testing in VLSI Memories
In-system diagnosis of RF ICs for tolerance against on-chip in-band interferers
Reducing Test Costs Through Strategic Changes in Maintenance and Service
Fault-coverage Maximizing March Tests for Memory Testing
An extension to JTAG for at-speed debug on a system
Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme
Elimination of Traditional Functional Testing of Interface Timings at Intel
DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device
Challenge of design and test of ultra-large-scale circuits
Enhancing signal controllability in functional test-benches through automatic constraint extraction
AC IO Loopback Design for High Speed µProcessor IO Test
Using Custom Fault Models to Improve Understanding of Silicon Failures
Emulation and its connection to test
Integrating Guided Probe and Fault Dictionary: An Enhanced Diagnostic Approach
Locating Bridging Faults in Memory Arrays
Analyzing second-order effects between optimizations for system-level test-based model generation
Silicon Diagnosis