yusuke1997/dblp-id-title huggingface dataset:
Vertical slit transistor based integrated circuits (VeSTICs) paradigm
Hierarchical physical design methodology for multi-million gate chips
Cell density-driven detailed placement with displacement constraint
A fast algorithm for identifying good buffer insertion candidate locations
Calculation of ramp response of lossy transmission lines using two-port network functions
Accelerating the Design and Performance of Next Generation Computing Systems with GPUs
A study on unroutable placement recognition
Physical design challenges beyond the 22nm node
Transformation from ad hoc EDA to algorithmic EDA
Estimating routing congestion using probabilistic analysis
Timing-Driven Placement Based on Dynamic Net-Weighting for Efficient Slack Histogram Compression
FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction
Routability driven white space allocation for fixed-die standard-cell placement
Recursive bisection based mixed block placement
Timing driven force directed placement with physical net constraints
Physical Layout after Half a Century: From Back-Board Ordering to Multi-Dimensional Placement and Beyond
Recent Progress in the Analysis of Electromigration and Stress Migration in Large Multisegment Interconnects
What's So Hard About (Mixed-Size) Placement?
Process variation aware clock tree routing
3DIC system design impact, challenge and solutions
Probabilistic congestion prediction
Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs
Regularity-constrained floorplanning for multi-core processors
Implications of device timing variability on full chip timing
Session details: Lifetime Achievement Award Tribute to Professor Alberto Sangiovanni-Vicentelli
Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs
Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing
Abuttable Analog Cell Library and Automatic AMS Layout
A routing approach to reduce glitches in low power FPGAs
LEGO-Size: LLM-Enhanced GPU-Optimized Signoff-Accurate Differentiable VLSI Gate Sizing in Advanced Nodes
Reinforcement Learning for Electronic Design Automation: Successes and Opportunities
A matching based decomposer for double patterning lithography
The great interconnect buffering debate: are you a chicken or an ostrich?
From Hard-Coded Heuristics to ML-Driven Optimization: New Frontiers for EDA
Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height Designs
Decoupling capacitance allocation for power supply noise suppression
Lookahead Placement Optimization with Cell Library-based Pin Accessibility Prediction via Active Learning
Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes
Carbon nanotube interconnects
Differences in ASIC, COT and processor design (panel)
Challenges and Approaches in VLSI Routing
Challenges and principles of physical design
VIA design rule consideration in multi-layer maze routing algorithms
Accelerated design of analog, mixed-signal circuits in Titan
Proceedings of the 2024 International Symposium on Physical Design, ISPD 2024, Taipei, Taiwan, March 12-15, 2024
Incremental capacitance extraction and its application to iterative timing-driven detailed routing
Flexible self-aligned double patterning aware detailed routing with prescribed layout planning
Application of automated design migration to alternating phase shift mask design
RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm
Electromigration Assessment in Power Grids with Account of Redundancy and Non-Uniform Temperature Distribution
Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise
Planning buffer locations by network flows
Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy
Clock tree resynthesis for multi-corner multi-mode timing closure
PANEL: EDA Challenges at Advanced Technology Nodes B
Carbon nanotube computer: transforming scientific discoveries into working systems
ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27 - 30, 2022
Challenges for Automating PCB Layout
ISPD '21: International Symposium on Physical Design, Virtual Event, USA, March 22-24, 2021
Boosters for driving long on-chip interconnects: design issues, interconnect synthesis and comparison with repeaters
Challenges for Interconnect Reliability: From Element to System Level
Secure and Trustworthy Cyber-Physical System Design: A Cross-Layer Perspective
Voltage-Drop Optimization Through Insertion of Extra Stripes to a Power Delivery Network
Leakage current in low standby power and high performance devices: trends and challenges
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
Complexity and Diversity in IC Layout Design
Clock Design Methodology for Energy and Computation Efficient Bitcoin Mining Machines
A performance optimization method by gate sizing using statistical static timing analysis
Technology Inflection Points
Physical design: mathematical models and methods
Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design
Past, Present and Future of the Research
Local unidirectional bias for smooth cutsize-delay tradeoff in performance-driven bipartitioning
Benchmarking for research in power delivery networks of three-dimensional integrated circuits
An exact algorithm for solving difficult detailed routing problems
Physical design challenges for multi-million gate SoC's: an STMicroelectronics perspective
Invited: Modeling and Design Methodology for Backside Integration of Voltage Converters
Unified quadratic programming approach for mixed mode placement
Obstacle-aware clock-tree shaping during placement
Assembling 2D blocks into 3D chips
Lithography till the end of Moore's law
Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation
EDA and the Internet (panel session - title only)
Physical design for FPGAs
TPL-Aware Displacement-driven Detailed Placement Refinement with Coloring Constraints
A Fast Incremental Cycle Ratio Algorithm
New efficient algorithms for computing effective capacitance
Futures for partitioning in physical design (tutorial)
Robust gate sizing via mean excess delay minimization
On convex formulation of the floorplan area minimization problem
Droplet-routing-aware module placement for cross-referencing biochips
Layout tools for analog ICs and mixed-signal SoCs: a survey
Placement Optimization with Deep Reinforcement Learning
Timing slack aware incremental register placement with non-uniform grid generation for clock mesh synthesis
How to get real mad
Global wires: harmful?
Session details: New Advances in Placement
Current density aware power switch placement algorithm for power gating designs
A morphing approach to address placement stability
Addressing the EDA Roadblocks for Domain-specific Compilers: An Industry Perspective
Satisfying whitespace requirements in top-down placement
Circuit clustering using graph coloring
FPGA-based Computing in the Era of AI and Big Data
Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction
Closed form expressions for extending step delay and slew metrics to ramp inputs
Pin Access-Oriented Concurrent Detailed Routing
A Useful Skew Tree Framework for Inserting Large Safety Margins
Scaling Up Physical Design: Challenges and Opportunities
Integrated fluidic-chip co-design methodology for digital microfluidic biochips
ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules
Synthesis for advanced nodes: an industry perspective
Explicit gate delay model for timing evaluation
Stress aware layout optimization
Optimal reliable crosstalk-driven interconnect optimization
Physical design issues in biofluidic microchips
Placement driven synthesis case studies on two sets of two chips: hierarchical and flat
Opportunities in power distribution network system optimization: from EDA perspective
Total sensitivity based dfm optimization of standard library cells
Fusion: The Dawn of the Hyperconvergence Era in EDA
Automatic Cell Layout in the 7nm Era
Floorplan area minimization using Lagrangian relaxation
Reporting of standard cell placement results
An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors
A study of netlist structure and placement efficiency
Design and analysis of physical design algorithms
3Dblox: Unleash the Ultimate 3DIC Design Productivity
EDA and Quantum Computing: The key role of Quantum Circuits
Design-aware lithography
On-chip thermal engineering for peta-scale integration
Optimal partitioners and end-case placers for standard-cell layout
High-level Synthesis for Domain Specific Computing
Routing tree topology construction to meet interconnect timing constraints
ML-Based Fine-Grained Modeling of DC Current Crowding in Power Delivery TSVs for Face-to-Face 3D ICs
The four degrees of 3D
Routability-driven placement algorithm for analog integrated circuits
Developing Quantum Workloads for Workload-Driven Co-design
Session details: Patterning and Machine Learning
Optimality, scalability and stability study of partitioning and placement algorithms
Convergence of placement technology in physical synthesis: is placement really a point tool?
Mutual inductance extraction and the dipole approximation
Selective Sensor Placement for Cost-Effective Online Aging Monitoring and Resilience
Important placement considerations for modern VLSI chips
On optimal physical synthesis of sleep transistors
Power-grid (PG) analysis challenges for large microprocessor designs: (our experience with oracle sparc processor designs)
Tutorial on DFM for physical design
A snap-on placement tool
SafeChoice: a novel clustering algorithm for wirelength-driven placement
A method of measuring nets routability for MCM's general area routing problems
A compiler for scalable placement and routing of brain-like architectures
Exploration and Tradeoffs of different Kernels in FPGA Deep Learning Applications
GPU Acceleration in Physical Synthesis
Pin Assignment Optimization for Multi-2.5D FPGA-based Systems
Interconnect power and delay optimization by dynamic programming in gridded design rules
Drive Strength Aware Cell Movement Techniques for Timing Driven Placement
Synthesis of Clock Networks with a Mode Reconfigurable Topology and No Short Circuit Current
Pioneering Contributions of Professor Martin D. F. Wong to Automatic Floorplan Design
More realistic power grid verification based on hierarchical current and power constraints
C5M - a control logic layout synthesis system for high-performance microprocessors
Data mining in design and test processes: basic principles and promises
Partitioning by iterative deletion
An ECO algorithm for eliminating crosstalk violations
Analog Layout Synthesis: Are We There Yet?
From Electronic Design Automation to Automotive Design Automation
Dawn of computer-aided design: from graph-theory to place and route
Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimization
Influence of Professor T. C. Hu's Works on Fundamental Approaches in Layout
Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration
An integrated floorplanning with an efficient buffer planning algorithm
Variability aware hierarchical implementation of big chips
BonnPlace: A Self-Stabilizing Placement Framework
Pushing the boundaries of Moore's Law to transition from FPGA to All Programmable Platform
The future of logic synthesis and physical design in deep-submicron process geometries
Towards layout-friendly high-level synthesis
Hardware Security for and beyond CMOS Technology
Intelligent Design Automation for Heterogeneous Integration
Regular layout generation of logically optimized datapaths
ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement
Physical Design Challenges in Modern Heterogeneous Integration
Toward Intelligent Physical Design: Deep Learning and GPU Acceleration
SAMSON: a generalized second-order arnoldi method for reducing multiple source linear network with susceptance
Concurrent High Performance Processor Design: From Logic to PD in Parallel
Physical Design for 3D Chiplets and System Integration
Transistor-level layout of high-density regular circuits
What makes a design difficult to route
A Case for Open EDA Verticals
A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement
Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid
Towards Designing and Deploying Ising Machines
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization
Machine Learning Techniques in Analog Layout Automation
Topology optimization of structured power/ground networks
Moore's law and physical design of ICs
The quarter micron challenge: intergrating physical and logic design
Synthesizing a representative critical path for post-silicon delay prediction
mPL6: enhanced multilevel mixed-size placement
The deep sub-micron signal integrity challenge
The ISPD2005 placement contest and benchmark suite
A highly-efficient row-structure stencil planning approach for e-beam lithography with overlapped characters
Variation tolerant buffered clock network synthesis with cross links
Opportunities and challenges for high performance microprocessor designs and design automation
An Effective Timing-Driven Detailed Placement Algorithm for FPGAs
Provably good routing tree construction with multi-port terminals
Itanium processor clock design
Building up End-to-end Mask Optimization Framework with Self-training
Integrating dynamic thermal via planning with 3D floorplanning algorithm
The challenges of correlating silicon and models in high variability CMOS processes
International Symposium on Physical Design, ISPD'13, Stateline, NV, USA, March 24-27, 2013
Slack Redistributed Register Clustering with Mixed-Driving Strength Multi-bit Flip-Flops
One look into the future of CMOS chip design
Clock-Aware FPGA Placement Contest
Gate-All-Around Technology is Coming.: What's Next After GAA?
An effective clustering algorithm for mixed-size placement
Methodology of Resolving Design Rule Checking Violations Coupled with Fully Compatible Prediction Model
Minimization of chip size and power consumption of high-speed VLSI buffers
Panel: Given that SEMATECH is levelling the semiconductor technology playing field, will corporate CAD (in particular, PD) tools continue to serve as enablers/differentiators of technology in the future? (panel)
On improving optimization effectiveness in interconnect-driven physical synthesis
CHDStd - application support for reusable hierarchical interconnect timing views
Dragon2005: large-scale mixed-size placement tool
Design methodology and tools for NEC electronics' structured ASIC ISSP
Coupling aware timing optimization and antenna avoidance in layer assignment
EMI-noise analysis under ASIC design environment
Hardware Security: Physical Design versus Side-Channel and Fault Attacks
A performance-driven standard-cell placer based on a modified force-directed algorithm
Machine Learning for Feature-Based Analytics
A stable fixed-outline floorplanning method
Session details: Cyber-Physical Systems
Heterogeneous 3-d stacking, can we have the best of both (technology) worlds?
Net criticality revisited: an effective method to improve timing in physical design
MQT QMAP: Efficient Quantum Circuit Mapping
Invited: Automatic Die-to-Die Routing with Shielding
Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead
Sequence-pair based placement method for hard/soft/pre-placed modules
Impact of manufacturing on routing methodology at 32/22 nm
introduction to electromigration-aware physical design
Robust extraction of spatial correlation
Relative timing driven multi-synchronous design: enabling order-of-magnitude energy reduction
Crosstalk noise optimization by post-layout transistor sizing
Physical design with multiple on-chip voltages
Reinforcement Learning or Simulated Annealing for Analog Placement? A Study based on Bounded-Sliceline Grids
Machine Learning in Simulation-Based Analysis
Reticle enhancement technology trends: resource and manufacturability implications for the implementation of physical designs
Pioneer Research on Mathematical Models and Methods for Physical Design
Design synthesis and optimization for automotive embedded systems
Variations, margins, and statistics
Interconnect thermal modeling for determining design limits on current density
Construction of minimal functional skew clock trees
Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization
Beyond GORDIAN and Kraftwerk: EDA Research at TUM
Early Days of Circuit Placement
ISPD 2023 Lifetime Achievement Award Bio
Some Observations on the Physical Design of the Next Decade
Porosity aware buffered steiner tree construction
Invited: Physical Design Challenges for Design Technology Co-optimization
Arbitrary convex and concave rectilinear block packing using sequence-pair
Efficient obstacle-avoiding rectilinear steiner tree construction
Cell-Flex Metrics for Designing Optimal Standard Cell Layout with Enhanced Cell Layout Flexibility
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs
A Compressive-sensing based Testing Vehicle for 3D TSV Pre-bond and Post-bond Testing Data
The Law of Attraction: Affinity-Aware Placement Optimization using Graph Neural Networks
Placement and routing optimization in the brain
Reliability-driven chip-level design for high-frequency digital microfluidic biochips
Proceedings of the 2025 International Symposium on Physical Design, ISPD 2025, Austin, TX, USA, March 16-19, 2025
Quantum Challenges for EDA
The Need for Speed: From Electric Supercars to Cloud Bursting for Design
Design Rule Management and its Applications in 15nm FreePDK Technology
Multi-center congestion estimation and minimization during placement
A parallel algorithm for zero skew clock tree routing
X-Volt: Joint Tuning of Driver Strengths and Supply Voltages Against Power Side-Channel Attacks
Scalability and Generalization of Circuit Training for Chip Floorplanning
Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation At Advanced Process Nodes
A Perspective on Security and Trust Requirements for the Future
FastPass: Fast Pin Access Analysis with Incremental SAT Solving
A simple and effective greedy multilayer router for MCMs
A layout approach to monolithic microwave IC
Understanding Graphs in EDA: From Shallow to Deep Learning
Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002
Critical area computation for missing material defects in VLSI circuits
Invited: Toward an ML EDA Commons: Establishing Standards, Accessibility, and Reproducibility in ML-driven EDA Research
Electromigration and its impact on physical design in future technologies
ISPD 2021 Wafer-Scale Physics Modeling Contest: A New Frontier for Partitioning, Placement and Routing
Design and Tool Flow of IBM's TrueNorth: an Ultra-Low Power Programmable Neurosynaptic Chip with 1 Million Neurons
The Physical Design of Biological Systems - Insights from the Fly Brain
Partitioning using second-order information and stochastic-gain functions
Timing Driven Partition for Multi-FPGA Systems with TDM Awareness
Accelerated Path-Based Timing Analysis with MapReduce
Photonic Side-Channel Analyzer: Enabling Security-Aware Physical Design Methodology
Analog Circuit and Layout Synthesis Revisited
Reap what you sow: spare cells for post-silicon metal fix
How good are slicing floorplans?
Generalized Force Directed Relaxation with Optimal Regions and Its Applications to Circuit Placement
Challenges in Large FPGA-based Logic Emulation Systems
Solvers, Engines, Tools and Flows: The Next Wave for AI/ML in Physical Design
Technology migration technique for designs with strong RET-driven layout restrictions
Proceedings of the 2023 International Symposium on Physical Design, ISPD 2023, Virtual Event, USA, March 26-29, 2023
FreePDK15: An Open-Source Predictive Process Design Kit for 15nm FinFET Technology
Incremental transient simulation of power grid
Routability-driven repeater block planning for interconnect-centric floorplanning
GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected Delays
PLATON: A Force-Directed Placement Algorithm for 3D Optical Networks-on-Chip
An automatic optical-simulation-based lithography hotspot fix flow for post-route optimization
Impact of RET on physical layouts
Design and Optimization of Quantum Electronic Circuits
Adaptive Clustering and Sampling for High-Dimensional and Multi-Failure-Region SRAM Yield Analysis
Early-stage power grid analysis for uncertain working modes
Improving Programmability and Efficiency of Large-Scale Graph Analytics for FPGA Platforms
ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement
Modern Challenges in Constructing Clocks
Preserving HDL synthesis hierarchy for cell placement
An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles
Incremental delay change due to crosstalk noise
Routability Booster " Synthesize a Routing Friendly Standard Cell Library by Relaxing BEOL Resources
From Electronic Design Automation to Cyber-Physical System Design Automation: A Tale of Platforms and Contracts
Goal Driven PCB Synthesis Using Machine Learning and CloudScale Compute
FF-bond: multi-bit flip-flop bonding at placement
Fast buffering for optimizing worst slack and resource consumption in repeater trees
Design hierarchy guided multilevel circuit partitioning
Almost optimum placement legalization by minimum cost flow and dynamic programming
Double patterning layout decomposition for simultaneous conflict and stitch minimization
Triple-play of Hyperconvergency, Analytics, and AI Innovations in the SysMoore Era
AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies
Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles
The ALIGN Automated Analog Layout Engine: Progress, Learnings, and Open Issues
Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000
A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design
Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph
Optimization of AI SoC with Compiler-assisted Virtual Design Platform
Slicing floorplans with range constraint
A roadmap and vision for physical design
Optimal gate sizing for coupling-noise reduction
SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips
Semi-detailed bus routing with variation reduction
Synthesis of low power clock trees for handling power-supply variations
Proceedings of the 1999 International Symposium on Physical Design, ISPD 1999, Monterey, CA, USA, April 12-14, 1999
Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework
DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent
ISPD 2018 Initial Detailed Routing Contest and Benchmarks
Clock network sizing via sequential linear programming with time-domain analysis
A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems
Optimizing non-monotonic interconnect using functional simulation and logic restructuring
A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs
Industrial clock design
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Embracing Machine Learning in EDA
A methodology for interconnect dimension determination
Challenges in Floorplanning and Macro Placement for Modern SoCs