yusuke1997/dblp-id-title huggingface dataset:
High-Level Synthesis for side-channel defense
Enhanced Visual Loop Closing for Laser-Based SLAM
An efficient video decoder design for MPEG-2 MP@ML
Buffer and register allocation for memory space optimization
Sparm: A Sparse Matrix Multiplication Accelerator Supporting Multiple Dataflows
A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration
Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary Algorithms
Dynamic code mapping for limited local memory systems
Hardware Synthesis From Encapsulated Verilog Modules
Optimizing the Memory Bandwidth with Loop Morphing
Hodgkin-Huxley-Based Neural Simulation with Networks Connecting to Near-Neighbor Neurons
Efficient scheduling methods for partitioned systolic algorithms
Architecture design of an H.264/AVC decoder for real-time FPGA implementation
Contention-Conscious Transaction Ordering in Embedded Multiprocessors
Interval-related problems on reconfigurable meshes
Array processing on finite polynomial rings
An Input Triggered Polymorphic ASIC for H.264 Decoding
On-demand fault-tolerant loop processing on massively parallel processor arrays
Combining flexibility with low power: Dataflow and wide-pipeline LDPC decoding engines in the Gbit/s era
Multi-dimentsional Incremetal Loops Fusion for Data Locality
Improved-Throughput Networks of Basic On-Line Arithmetic Modules for DSP Applications
A Novel Sequencer Hardware for Application Specific Computing
A Combined Decimal and Binary Floating-Point Multiplier
An Overlay Architecture for Pattern Matching
Optimized software synthesis for synchronous dataflow
Using Group Theory to Specify Application Specific Interconnection Networks for SIMD DSPs
Scalable Multi-FPGA Platform for Networks-On-Chip Emulation
Libraries of schedule-free operators in Alpha
Relation-oriented resource allocation for multi-accelerator systems
An optimized NoC architecture for accelerating TSP kernels in breakpoint median problem
AERO: Towards Energy-Efficient Autonomous Flight in MAVs Using Approximate Execution
Design and Implementation of a High-Performance and Silicon Efficient Arithmetic Coding Accelerator for the H.264 Advanced Video Codec
A Compact Fading Channel Simulator Using Timing-Driven Resource Sharing
26th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2015, Toronto, ON, Canada, July 27-29, 2015
A VLSI System Architecture For Real-Time Intelligent Decision Making
Fast Arithmetic and Fault Tolerance in the FERMI System
Configuration technique for adaptability of multicore processors on FPGA
A low power fault-tolerance architecture for the kernel density estimation based image segmentation algorithm
Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline
ADPCM codec: from system level description to versatile HDL model
Guarding the guards: Enhancing LNS performance for common applications
Performance-Improved Computation of Very Large Word-Length LNS Addition/Subtraction Using Signed-Digit Arithmetic
A feedback concentrator for the Image Understanding Architecture
Recursive Filtering on a Vector DSP with Linear Speedup
Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective
A grain in the silicon: SCA-protected AES in less than 30 slices
14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands
Adaptive ILP control to increase fault tolerance for VLIW processors
A scheduling and binding heuristic for high-level synthesis of fault-tolerant FPGA applications
Low latency FPGA acceleration of market data feed arbitration
Implementing high-performance, low-power FPGA-based optical flow accelerators in C
Range reduction based on Pythagorean triples for trigonometric function evaluation
Resilient Neural Network Training for Accelerators with Computing Errors
Low Complexity Design of High Speed Parallel Decision Feedback Equalizers
Differential Power Analysis on Low-Energy Keystream Generating Hardware: Full-State Recovery in Dizy Implementation
Enhancing a Hearing Aid Processor with ISA Extensions Supporting Flexible Fixed-Point Formats
Evaluating Instruction Set Extensions for Fast Arithmetic on Binary Finite Fields
Mapping algorithms onto a multiple-chip data-driven array
Accelerating Radiative Transfer Simulation with GPU-FPGA Cooperative Computation
A Novel Highly Reliable Low-Power Nano Architecture When von Neumann Augments
Architectural Support for Accelerating Congestion Control Applications in Network Processors
The Midlifekicker Microarchitecture Evaluation Metric
A high performance IIR filter chip and its evaluation system
A VLSI architecture for simplified arithmetic Fourier transform algorithm
A Synthesis System For Bus-Based Wavefront Array Architectures
Design of the Distributed Architecture of a Machine-tool Using FIP Fieldbus
A High-Performance Hardware Architecture for Spectral Hash Algorithm
A New Euclidean Division Algorithm For Residue Number Systems
Accelerating nonlinear diffusion tensor estimation for medical image processing using high performance GPU clusters
Formal Verification for Microprocessors with Extendable Instruction Set
Evaluation of a High-Level-Language Methodology for High-Performance Reconfigurable Computers
Kestrel: A Programmable Array for Sequence Analysis
Low Power Memory Design
A massively parallel diagonal-fold array processor
CSIFA: A Configurable SRAM-based In-Memory FFT Accelerator
A fault-tolerant two-dimensional sorting network
Impact of Structural Faults on Neural Network Performance
A Parallelizing Compilation Method for the Map-oriented Machine
Filtering Global History: Power and Performance Efficient Branch Predictor
Acceleration of Multiresolution Imaging Algorithms: A Comparative Study
Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy
Low-Power ASIP Architecture Exploration and Optimization for Reed-Solomon Processing
Heterogeneous digital signal processing systems for sonar
Systolic architecture for 2-D rank order filtering
Efficient FPGA-based ECDSA Verification Engine for Permissioned Blockchains
Transformation of systolic algorithms for interleaving partitions
reMinMin: A novel static energy-centric list scheduling approach based on real measurements
Behavioral synthesis of high performance, low cost, and low power application specific processors for linear computations
A real-time systolic algorithm for on-the-fly hidden surface removal
Enabling development of OpenCL applications on FPGA platforms
Mapping high-dimension wavefront computations to silicon
Two-level pipelined implementation of systolic block Householder transformation with application to RLS algorithm
Flexible hardware/software co-design for scalable elliptic curve cryptography for low-resource applications
HW/SW-database-codesign for compressed bitmap index processing
Fast generation of long sorted runs for sorting a large file
A Low-Power Carry Skip Adder with Fast Saturation
Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filters
Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis
Potential of using block floating point arithmetic in ASIP-based GNSS-receivers
Permuting Accumulation Order for Low-Precision Machine Learning
Division Unit for Binary Integer Decimals
Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders
Large-scale packet classification on FPGA
Optimized Data-Reuse in Processor Arrays
An MLA-LLM Hardware Acceleration with Tensor-Train Decomposition on Group Vector Systolic Accelerator
A variable-precision interval arithmetic processor
DARM: A Low-Complexity and Fast Modular Multiplier for Lattice-Based Cryptography
Rapid prototyping with programmable control paths
iVAMS: Intelligent metamodel-integrated Verilog-AMS for circuit-accurate system-level mixed-signal design exploration
Address generation scheme for a coarse grain reconfigurable architecture
Performance modeling for highly-threaded many-core GPUs
Dynamic holographic reconfiguration on a four-context ODRGA
Clarifications and Optimizations on Rounding for IEEE-compliant Floating-Point Multiplication
Designing specific systolic arrays with the API15C chip
Decimal Floating-Point Division Using Newton-Raphson Iteration
A 1D linearly expandable interconnection network performance analysis
The systematic design of a motion estimation array architecture
FPGA and ASIC square root designs for high performance and power efficiency
Expression Synthesis in Process Networks generated by LAURA
0/1 Knapsack on Hardware: A Complete Solution
On the injectivity of modular mappings
A highly efficient, thread-safe software cache implementation for tightly-coupled multicore clusters
A hardware accelerator for the alignment of multiple DNA sequences in forensic identification
The VLSI design and implementation of the array processors of a multilayer vision system architecture
A Real-Time Learning-Based Super-Resolution System Using Direct Simple Functions
SIMD Vectorization of Histogram Functions
Dynamic Voltage Scaling for Power Efficient MPEG4-SP Implementation
Loop Transformation Methodologies for Array-Oriented Memory Management
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures
Efficient implementation of cryptographic primitives on the GA144 multi-core architecture
A Solid Translation Engine using Ray Representation
Iterative Methods for Logarithmic Subtraction
Architecture Support for Reconfigurable Multithreaded Processors in Programmable Communication Systems
XDIVINSA: eXtended DIVersifying INStruction Agent to Mitigate Power Side-Channel Leakage
Exploiting Subword Permutations to Maximize CNN Compute Performance and Efficiency
Mapping locally recursive SEGs upon a multiprocessor system in a ring network
A Mathematical Model of Trace Cache
Domain flow and streaming architectures
Analysing parametrised designs by non-standard interpretation
Synthesizing accurate floating-point formulas
Scheduling partitions in systolic algorithms
High Performance Soft Multi-Processor Arrays
Hyper-Programmable Architectures for Adaptable Networked Systems
Evaluating Various Branch-Prediction Schemes for Biomedical-Implant Processors
HICore1: "Safety on a chip" turnkey solution for industrial control
A floating-point CORDIC based SVD processor
Synthesis of Multirate VLSI Arrays
A Low-Power Processor Architecture Optimized forWireless Devices
gemV: A validated toolset for the early exploration of system reliability
Architectures for Sustainable Security in the Computing Continuum
Area and Time Efficient Modular Multiplication of Large Integers
Application Specific Array Processors, ASAP 1990. Proceedings of the International Conference on, Princeton, NJ, USA, 5-7 Sept., 1990
Horizontal Microcode Compaction for Programmable Systolic Accelerators
Design and Implementation of a Radix-4 Complex Division Unit with Prescaling
Linear algebra computations in heterogeneous systems
Efficient On-Chip Communications for Data-Flow IPs
Hybrid data structure for IP lookup in virtual routers using FPGAs
Heterogeneous BISR techniques for yield and reliability enhancement using high level synthesis transformations
ISA Support for Fingerprinting and Erasure Codes
An energy efficient adaptive event detection scheme for wireless sensor network
An ESL framework for low power architecture design space exploration
Parallel Algorithm And Architecture For Two-Step Division-Free Gaussian Elimination
Customized Instruction on RISC-V for Winograd-Based Convolution Acceleration
High speed implementation of 1-D and 2-D morphological operations
Design of the QBIC Wearable Computing Platform
Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router
Research on High-Efficiency Asynchronous Superscalar Processors: (PhD Forum Paper)
Loop program mapping and compact code generation for programmable hardware accelerators
Systolic array implementation of nested loop programs
An Efficient Implementation of High-Accuracy Finite Difference Computing Engine on FPGAs
Dynamic Sharing in Multi-accelerators of Neural Networks on an FPGA Edge Device
Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors
Communication-minimal mapping of uniform loop nests onto distributed memory architectures
A parallel system for photo realistic artificial scene rendering
An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbers
Optimum vectorization of scalable synchronous dataflow graphs
Efficiency in ILP processing by using orthogonality
Parallel Montgomery Multipliers
A Hardware Algorithm for Variable-Precision Logarithm
A System Framework for the Design of Embedded Software Targeting Heterogeneous Multi-core SoCs
Throughput-scalable hybrid-pipeline architecture for multilevel lifting 2-D DWT of JPEG 2000 coder
Loop-oriented metrics for exploring an application-specific architecture design-space
A novel architecture for a decision-feedback equalizer using extended signal-digit feedback
SCAL: An Open-Source Scalable Core Adaptation Layer for Interfacing RISC-V ISA Extensions
Comparison of Branching CORDIC Implementations
23rd IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2012, Delft, The Netherlands, July 9-11, 2012
Generation of Scheduling Functions Supporting LSGP-Partitioning
Polyhedral Modeling and Analysis of Memory Access Profiles
The Sarnoff Engine: a massively parallel computer for high definition system simulation
SPARKLE: A 1,024-Core/16,384-Thread Single FPGA Many-Core RISC-V Barrel Processor Overlay
Application Specific Array Processors, 1991. Proceedings of the International Conference on, Barcelona, Spain, 2-4 Sept., 1991
Register Organization for Enhanced On-Chip Parallelism
An improved multilayer neural model and array processor implementation
A SIMD solution to the sequence comparison problem on the MGAP
A parallel k-partition method to perform Montgomery Multiplication
Uniform but non-local DAGS: a trade-off between pure systolic and SIMD solutions
A High-Throughput Programmable Decoder for LDPC Convolutional Codes
On synthesizing application-specific array architectures from behavioral specifications
Design of an Automatic Target Recognition algorithm on the IBM Cell Broadband Engine
Parallelizing HMMER for Hardware Acceleration on FPGAs
A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies
An FPGA Implementation of a Fully Verified Double Precision IEEE Floating-Point Adder
Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler
Design and Evaluation of a Network-Based Asynchronous Architecture for Cryptographic Devices
Deep Learning-based Embedded Intrusion Detection System for Automotive CAN
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator
Design Flow of a Dedicated Computer Cluster Customized for a Distributed Genetic Algorithm Application
Long Residue Checking for Adders
Synthetic Data Approach for Classification and Regression
A VLSI Architecture for Image Geometrical Transformations Using an Embedded Core Based Processor
FARHAD: A Fault-Tolerant Power-Aware Hybrid Adder for add intensive applications
Application-Specific DSP Architecture For Fast Fourier Transform
An Efficient PIM (Processor-In-Memory) Architecture for Motion Estimation
Synthesis of systolic arrays by equation transformations
Noise Reduction in Hearing-Aid Processors: Traditional Methods vs. Neural Networks
Hybrid Invasive Weed Optimization and GA for Multiple Sequence Alignment
A Real Adjacency Matrix-Coded Differential Evolution Algorithm for Traveling Salesman Problems
Lung nodule classification combining rule-based and SVM
Cortical Neural P Systems
Intra- and inter-connectivity influences on event related changes in thalamocortical alpha rhythms
A Multi-objective Particle Swarm Algorithm Based on a Preference Strategy
Fault Diagnosis in Aluminium Electrolysis Using a Joint Method Based on Kernel Principal Component Analysis and Support Vector Machines
A very high accuracy handwritten character recognition system for Farsi/Arabic digits using Convolutional Neural Networks
The Intelligent Editing Based on Perception for Structuring Digital Ink
PSO Application in Power System: Low-Frequency Oscillation Fault Analysis
Visualize and Compress Single Logo Recognition Neural Network
Research on Unmanned Ship Collision Avoidance Algorithm Based on Improved Particle Swarm Optimization Algorithm
Software Defect Prediction Based on SMOTE-Tomek and XGBoost
Efficiency of Parallel Computing Based on .Net 4.5
Bio-Inspired Computing: Theories and Applications - 16th International Conference, BIC-TA 2021, Taiyuan, China, December 17-19, 2021, Revised Selected Papers, Part II
A Comparative Study of State Transition Algorithm with Harmony Search and Artificial Bee Colony
Fifth International Conference on Bio-Inspired Computing: Theories and Applications, BIC-TA 2010, University of Hunan, Liverpool Hope University, Liverpool, United Kingdom / Changsha, China, September 8-10 and September 23-26, 2010
Research on identification algorithm of Hammerstein model
An improved harmony search algorithm for multi-dimensional function optimization problem
A dynamical policy search model for matching law
An Analysis for Thermal Conductivity of Graphene/Polymer Nanocomposites
HCO-Based RFID Network Planning
A Method of Pathing for Underwater Glider Cluster Based on Optimization Algorithm
Application of FDTD and Harmony Search Algorithm for Inverse Scattering Problem
Boundedness for Multilinear Commutators of Calderón-Zygmund Operator on Herz-Hardy Spaces
Bio-Inspired Soft-Computational Framework for Speech and Image Application
Multi-Objective Fault Section Estimation in Distribution Systems Using Elitist NSGA
Continual Learning with a Memory of Non-similar Samples
Characterizing information transmission in cerebellar granule neuron
Algorithm for Generating Decision Tree Based on Adjoint Positive Region
A New Graphical Representation of Protein Sequences Based on Dual-Vector Model
Compactly and Weakly Compactly Strongly Exposed Properties in Musielak-Orlicz Sequence Spaces Equipped with the Orlicz Norm
Biomimicry of Plant Root Foraging for Distributed Optimization: Models and Emergent Behaviors
An Improved Trajectory Planning Method for Unmanned Aerial Vehicles in Complex Environments
Remarks on Invariant Method of the Second-Order Linear Differential Equations with Variable Coefficients
An Outlier Detection Method for Robust Manifold Learning
Identification system of the type of vehicle
A NSGA-II with ADMM Mutation for Solving Multi-objective Robust PCA Problem
Tabu search algorithm for solving No-idle permutation Flow Shop Scheduling Problem
A bio-inspired software for segmenting digital images
On the Convergence of Levenberg-Marquardt Method for Solving Nonlinear Systems
An Adaptive Brain Storm Optimization Algorithm Based on Heuristic Operators for TSP
Using Multi-objective Particle Swarm Optimization to Solve Dynamic Economic Emission Dispatch Considering Wind Power and Electric Vehicles
The research of fast recovery spatial information network
Design of Blood Group Pairing Logic Circuit Based on DNA Strand Displacement
A Generalized Multi-Attribute Group Decision Making with Intuitionistic Fuzzy Set
Research on Course Control Algorithm of Unmanned Craft Based on Model Predictive Control
The axial position sensing and signal processing in maglev artificial heart pump
Semantic-driven model of dynamic logistic services composition and optimization based on QoS
An Overview of the Applications of Particle Swarm in Water Resources Optimization
Aircraft Scheduling Problems Based on Genetic Algorithms
Hybrid Workflow Net Based Architecture for Modeling Huntington's Disease
Footplant Detection Based on Adjusting the Foot Height Threshold Automatically
Motor Imaginary EEG Signals Classification Based on Deep Learning
Implementation of tile sequencing for DNA logical computation toward next-generation information security
Solving Satellite Range Scheduling Problem with Learning-Based Artificial Bee Colony Algorithm
HGADC: Hierarchical Genetic Algorithm with Density-Based Clustering for TSP
Cooperative coevolutionary genetic algorithms to find optimal elimination orderings for Bayesian networks
Reinforcement Learning-Based Differential Evolution Algorithm with Levy Flight
A Three Input Look-Up-Table Design Based on Memristor-CMOS
A Picture Array Generating Model Based on Flat Splicing Operation
Multiple Depots Incomplete Open Vehicle Routing Problem Based on Carbon Tax
Molecular Model for Information Addressing and Transporting Based on DNA Nanotechnology
Properties of Binding-Blocking Automata: A Study
Non-time Synchronization and Localization Based on Seawater Movement
Enhancing MOEA with component-emphasizing mechanism for multi-objective optimization
A competitive co-evolutionary cultural differential evolution and its application to constrained optimization in butane alkylation process
A hybrid immune PSO for constrained optimization problems
Analysis of protein sequence similarity
Tentative Study on Solving Impulse Control Equations of Plant-pest-predator Model with Differential Evolution Algorithm
Ratio Estimation and Regression Estimation Method in Three-Stage Sampling
A Diversity Keeping Strategy for the Multi-objective Examination Timetabling Problem
One improved genetic algorithm applied in the problem of dynamic jamming resource scheduling with multi-objective and multi-constraint
Complex Logic Circuit of Three-Input and Nine-Output by DNA Strand Displacement
Multi-strategy Improved Kepler Optimization Algorithm
The Predictive Model of Esophageal Squamous Cell Carcinoma Differentiation
Visual Tracking by Sequential Cellular Quantum-Behaved Particle Swarm Optimization Algorithm
A novel Ant algorithm for permutation flow shop problem
Predictive Controller Design Using Ant Colony Optimization Algorithm for Unmanned Surface Vessel
Unsupervised feature selection based on clustering
Research on Target Value Assessment Method Based on Attention Mechanism
An Image Threshold Segmentation Algorithm with Hybrid Evolutionary Mechanisms Based on Membrane Computing
Constructive Solid Geometry Based Topology Optimization Using Evolutionary Algorithm
Membrane computing based particle swarm optimization algorithm and its application
Classification Based on Brain Storm Optimization Algorithm
A Hybrid Response Strategy for Dynamic Constrained Multi-objective Optimization
Multi-UUV Underwater Target Cooperative Detection Task Planning and Assignment
The Neutrophil's Morphology Classification Using Convolutional Neural Network
Nurse Scheduling Using Harmony Search
A Method for Security Evaluation in Cloud Computing Based on Petri Behavioral Profiles
A Multi-parent Crossover Based Genetic Algorithm for Bi-Objective Unconstrained Binary Quadratic Programming Problem
A novel model for splicing detection
Application of DNA Self-assembly for Maximum Matching Problem
A Differential Evolution Algorithm for Multi-objective Mixed-Variable Optimization Problems
Classification of schizophrenia's EEG based on high order pattern discovery
Molecular Dynamic Simulation for Heat Capacity of MgSiO 3 Perovskite
Image encryption algorithm based on DNA biological properties and chaotic systems
Discussion on the optimal allocate model about the sickbeds of ophthalmology based on multi-objective optimization method
A Sorting Based Selection for Evolutionary Multiobjective Optimization
Synthesis of frequency generator via spiking neurons network: A genetic algorithm approach
Approximation for preemptive scheduling stochastic jobs on identical parallel machines
Numerical P Systems with Thresholds and Petri Nets
Recent Bio-inspired Algorithms for Solving Flexible Job Shop Scheduling Problem: A Comparative Study
A Novel Attributes Partition Method for Decision Tree
Adaptive Constraint Multi-objective Differential Evolution Algorithm Based on SARSA Method
The Bilinear-MAC Network for Visual Reasoning
The Short-Term Traffic Flow Prediction Based on MapReduce