yusuke1997/dblp-id-title huggingface dataset:
Aspects of realizing the CFI design representation specification in the NELSIS framework
Modeling of real bistables in VHDL
Design automation of self checking circuits
SCHALLOC: an algorithm for simultaneous scheduling & connectivity binding in a datapath synthesis system
Locating logic design errors via test generation and don't-care propagation
SPAN: Tightly coupled thermal and electrical simulation
Extended timing diagrams as a specification language
Structured analysis and VHDL in embedded ASIC design and verification
Mixed electrical-thermal and electrical-mechanical simulation of electromechatronic systems using PSpice
Towards optimizing global MinCut partitioning
A Hierarchical Approach to Fault Collapsing
Spotlights on recent developments in microsystem technology
A VHDL reuse workbench
TINA: analog placement using enumerative techniques capable of optimizing both area and net length
Design for testability view on placement and routing
A system for floorplanning with hierarchical placement and wiring
A probabilistic fault model for analog faults
VHDL and cyclic corrector codes
Functional-level synthesis with VHDL
Unifying tool, data and process flow management
A hardware/software partitioning algorithm for pipelined instruction set processor
Layout-level design for testability rules for a CMOS cell library
VHDL 1076-1992 languages changes
An accurate model for ambiguity delay simulation
System design using an integrated specification and performance modeling methodology
M-Testability: An Approach for Data-Path Testability Evaluation
A general state graph transformation framework for asynchronous synthesis
Specification and management of timing constraints in behavioral VHDL
A new approach to layout of custom analog cells
Adaptive Cluster Growth (ACG): a new algorithm for circuit packing in rectilinear region
Reduced design time by load distribution with CAD framework methodology information
Optimal Operation Scheduling Using Resource Lower Bound Estimations
Functional Tests for Ring-Address SRAM-type FIFOs
Design management within a design environment
An improved layout verification algorithm (LAVA)
A new HW/SW partitioning algorithm for synthesizing the highest performance pipelined ASIPs with multiple identical FUs
Experiences and issues in VHDL-based synthesis
Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition Approach
KIR - a graph-based model for description of mixed analog/digital systems
On L × n boolean matrices with all L × k submatrices having 2 k distinct row vectors
Periodic signal suppression in a concurrent fault simulator
Simulation based verification of register-transfer level behavioral synthesis tools
Improved force-directed scheduling
Bottleneck removal algorithm for dynamic compaction and test cycles reduction
Exact and heuristic algorithms for the minimization of incompletely specified state machines
A new performance driven macro-cell placement algorithm
Cross-fertilizing FSM verification techniques and sequential diagnosis
Boundary Scan Testing Combined with Power Supply Current Monitoring
A Methodology for Analog Design Automation in Mixed-Signal ASICs
Application of Simple Genetic Algorithms to Sequential Circuit Test Generation
Switch-level timing models in the MOS simulator BRASIL
JESSI COMMON FRAMEWORK Design Management: the means to configuration and execution of the design process
A workbench for generation of component models
Instruction set extraction from programmable structures
Analysis of different protocol description styles in VHDL for high-level synthesis
Logic Synthesis and Verification of the CPU and Caches of a Mainframe System
Floorplanning strategy for mixed analog-digital VLSI integrated circuits
PLATO: a new piecewise linear simulation tool
An integrated approach to engineering computer systems
Storage optimization by replacing some flip-flops with latches
Performance-complexity analysis in hardware-software codesign for real-time systems
A VHDL-based bus model for multi-PCB system design
Latest benchmark results of VHDL simulation systems
Retiming by combination of relocation and clock delay adjustment
A framework for macro- and micro-time to model VHDL attributes
Path runner: an accurate and fast timing analyser
Glue-logic partitioning for floorplans with a rectilinear datapath
Switched Current Sigma-Delta A/D Converter for a CMOS Subscriber Line Analog Front End
Random current testing for CMOS logic circuits by monitoring a dynamic power supply current
Module synthesis for finite state machines
Timing optimization by an improved redundancy addition and removal technique
Implementing fuzzy control systems using VHDL and statecharts
Timing models for high-level synthesis
Distributed simulation for structural VHDL netlists
Parallel controller synthesis from a Petri net specification
Model-based fault diagnosis of sequential circuits and its acceleration
Extended 0/1 LP formulation for the scheduling problem in high-level synthesis
An OBDD-Representation of Statecharts
The design cube: a new model for VHDL designflow representation
GSA: scheduling and allocation using genetic algorithm
ACCORDO: second generation floor planning
Heuristics for branch-and-bound global allocation
Multirate integration in a direct simulation method
A formal model for coupling computer based system and physical systems
Fast simulation method for the detection of reflection - and crosstalk effects during the design of complex printed circuit boards
Flexible controlpath microarchitecture synthesis based on artificial intelligence
Design of complex systems with a VHDL based methodology
High-level synthesis and codesign methods: an application to a videophone codec
An architecture-independent approach to FPGA routing based on multi-weighted graphs
Reliability study of combinatorial circuits
The exact solution of timing verification
Interactive System-level Partitioning with PARTIF
A new switch-level test pattern generation algorithm based on single path over a graph representation
Maximizing the Throughput of High Performance DSP Applications Using Behavioral Transformations
The maximal VHDL subset with a cycle-level abstraction
Formulation and evaluation of scheduling techniques for control flow graphs
An improved relaxation approach for mixed system analysis with several simulation tools
Compiling VHDL into a high-level synthesis design representation
Assignment of storage values to sequential read-write memories
Control flow optimization for fast system simulation and storage minimization
New approach in gate-level glitch modelling
Gate sizing in MOS digital circuits with linear programming
An efficient verification algorithm for parallel controllers
Performance-oriented placement and routing for field-programmable gate arrays
Towards maximising the use of structural VHDL for synthesis
On the selection of a partial scan path with respect to target faults
CAD education and science in Ukraine after Perestroika
Automatic diagnosis may replace simulation for correcting simple design errors
Layout synthesis for datapath designs
On probabilistic switch-level simulation for asynchronous circuits
Controller optimization for protocol intensive applications
A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes
Search space reduction through clustering in test generation
A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits
Fast heuristic algorithms for finite state machine minimization
Use of embedded scheduling to compile VHDL for effective parallel simulation
Demosthenes-A technology-independent power DMOS layout generator
JOGM: A CMOS cell layout style using jogged transistor gates
Specification of timing constraints for controller synthesis
A unified discrete gate sizing/cell library optimization method for design and analysis of delay minimized CMOS and BiCMOS circuits
A new method for the state reduction of incompletely specified finite sequential machines
Formal verification of timing conditions
Circuit partitioning into small sets: a tool to support testing with further applications
A new algorithm for transistor sizing in CMOS circuits
Clean formal semantics for VHDL
MINT: a VHDL simulation system
An adaptive distributed algorithm for sequential circuit test generation
An efficient two-dimensional compaction algorithm for VLSI symbolic layout
Circuit partitioning for waveform relaxation
Technology mapping using boolean matching and don't care sets
An investigation of iterative routing algorithms
Component selection in resource shared and pipelined DSP applications
Introduction of Permissible Bridges with Application to Logic Optimization after Technology Mapping
Partitioning a network into n pieces with a time-efficient net cost function
Cell area minimization by transistor folding
Transient simulation of lossy coupled transmission lines
Hybrid compiled/interpreted simulation of MOS circuits
Design to test migration: a tester and a simulator
An event-driven transient simulation algorithm for MOS and bipolar circuits
An approach for classification of integrated circuits by a knowledge conserving library concept
Functional semantics of microprocessors at the microprogram level and correspondence with the machine instruction level
Test generation for IDDQ testing and leakage fault detection in CMOS circuits
An automatic synthesizer for CMOS operational amplifiers
Fault modeling of differential ECL
On the fault coverage of delay fault detecting tests
A VHDL-based design methodology: the design experience of a high performance ASIC chip
On the implementation of an efficient performance driven generator for conditional-sum-adders
Boolean matching based on Boolean unification
Closeness metrics for system-level functional partitioning
HERESY: a hybrid approach to automatic schematic generation
Proceedings EURO-DAC'94, European Design Automation Conference, Grenoble, France, September 19-22, 1994
Formal verification of behavioral VHDL specifications: a case study
Path breaker: a tool for the optimal design of speed independent asynchronous controllers
State-machine-development-tool for high-level-design entry and simulation
Generating pipelined datapaths using reduction techniques to shorten critical paths
Fully testable PLA design with minimal extra input
Non-reversible VHDL source-source encryption
Technology mapping for sequential circuits based on retiming techniques
Synthesis of Delay-Verifiable Two-Level Circuits
Layout optimization of planar CMOS cells regarding width-to-height trade-off
Linear time fault simulation algorithm using a content addressable memory
Best-so-far vs. where-you-are: New perspectives on simulated annealing for CAD
Using VHDL for HW/SW co-specification
Power analysis for sequential circuits at logic level
Analysis of multi-process VHDL specifications with a Petri net model
The use of computer-aided software engineering technology in systems and software design
Optimal synthesis of differential cascode voltage switch (DCVS) logic circuits using ordered binary decision diagrams (OBDDs)
Diagnosis oriented test pattern generation
Scheduling of behavioral VHDL by retiming techniques
Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring
PEAS-I: A hardware/software co-design system for ASIPs
MILEF: an efficient approach to mixed level automatic test pattern generation
Describing space-continuous models of microelectromechanical devices for behavioral simulation
A genetic algorithm for macro cell placement
Synchronous designs in VHDL
CAD: The numerical and analytical methods combined for the analysis of IC's thermal fields
Object-oriented hardware modelling - where to apply and what are the objects?
The concept of superprocesses for high-level synthesis and their VHDL modelling
Subtype concept of VHDL for synthesis constraints
Design technology research for the nineties: more of the same?
Design assistance for CAD frameworks
Technology mapping for a two-output RAM-based field programmable gate array
A new synthesis technique for multilevel combinational circuits
Optimization of micro-controllers by partitioning
VHDL switch level fault simulation
An optimal channel pin assignment with multiple intervals for building block layout
Efficient Calculation of Boolean Relations for Multi-Level Logic Optimization
Synthesis of Sequential Machines with Reduced Testing Cost
Experiments on the synthesis and testability of non-scan finite state machines
TATOO: an industrial timing analyzer with false path elimination and test pattern generation
Realizing expression graphs using table-lookup FPGAs
Advanced Analog Circuit Design on a Digital Sea-of-Gates Array
A distributed engineering database management system for IC design
Testing redundant asynchronous circuits by variable phase splitting
Efficient Path Identification for Delay Testing - Time and Space Optimization
A transformation for integrating VHDL behavioral specification with synthesis and software generation
Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization
Formal verification of pipeline conflicts in RISC processors
Entity overloading for mixed-signal abstraction in VHDL
Generation of embedded RAMs with built-in test using object-oriented programming
Graph based analysis of FPGA routing
The VHDL based design of the MIDA MPEG1 audio decoder
Verification of synthesized circuits at register transfer level with flow graphs
Concurrent MIN-MAX simulation
"Underground Capacitors" Very Efficient Decoupling for High Performance UHF Signal Processing ICs
Resolution-based correctness proofs of synchronous circuits
Test scheduling and controller synthesis in the CADDY-system
Design of a Real Time Geometric Classifier
Incremental switch-level simulation with zero/integer-delay
Speeding up test pattern generation from behavioral VHDL descriptions containing several processes
MILP based task mapping for heterogeneous multiprocessor systems
Symbolic Algorithms to Calculate Steady-State Probabilities of a Finite State Machine
Algorithms for behavioral test pattern generation from VHDL circuit descriptions containing loop language constructs
On the notion of the normal form register-level structures and its applications in design-space exploration
Petri nets as intermediate representation between VHDL and symbolic transition systems
Parallel algorithms for the simulation of lossy transmission lines
Distributed Computing, Automatic Design, and Error Recovery in the ULYSSES II Framework
Taking Advantage of ASICs to Improve Dependability with Very Low Overheads
PARAGON: a new package for gate matrix layout synthesis
ICM2 IC: a new ATM switching element for 2.48 Gb/s communications
An HDL approach to board-level BIST
Timing verification for asynchronous design
Using VHDL for simulation of SDL specifications
On Design Rule Correct Maze Routing
A VLSI floorplanner based on "balloon" expansion
Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996
A hardware design system based on object-oriented principles
High-level synthesis in a rapid-prototype environment for mechatronic systems
Generating several solutions for the scheduling problem in high-level synthesis
An Algorithm for Generation of Behavioral Shape Functions
Software architecture of universal hardware modeler
A unified approach to the extraction of realistic multiple bridging and break faults
A data-structuring technique for gridded VLSI layouts
FPGA Partitioning for Critical Paths
Metric-based transformations for self testable VLSI designs with high test concurrency
Symbolic exploration of large circuits with enhanced forward/backward traversals
Information model of a compound graph representation for system and architecture level design
Inheritance concept for signals in object-oriented extensions to VHDL
Industrial experimentation of high-level synthesis
Application-independent hierarchical synthesis methodology for analogue circuits
Verification of a production cell using an automatic verification environment for VHDL
Stepwise refinement of behavioral VHDL specifications by separation of synchronization and functionality
Software system for semiconductor devices, monolith and hybrid ICs thermal analysis
Optimization of Address Generator Hardware
OPERAS in a DSP CAD environment
An approach to multi-paradigm controller synthesis from timing diagram specifications
Using VHDL for datapath synthesis
Interest of a VHDL native environment
Device selection for system partitioning
Towards verifying VHDL descriptions of processors
Using C to write portable CMOS VLSI module generators
BiTeS: a BDD based test pattern generator for strong robust path delay faults
A performance evaluator for parameterized ASIC architectures
A flexible hierarchical 3-D module assembler
The MODES Global Control Environment - A tool for rapid prototyping
A VLSI Implementation of Parallel Fast Fourier Transform
PHIFACT a design space exploration program
Global stacking for analog circuits
Proceedings of the European Design Automation Conference 1993, EURO-DAC '93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993
PHIDEO: a silicon compiler for high speed algorithms
Instruction selection for embedded DSPs with complex instructions
An approach for integrated specification and design of real-time systems
A Development Environment for the Cosynthesis of Embedded Software/Hardware Systems
Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment
Symbolic implication in test generation
A Synthesis Method for Mixed Synchronous / Asynchronous Behavior
BIST Test Pattern Generators for Stuck-Open and Delay Testing
COMET: a hardware-software codesign methodology
Logic optimization on a concurrent processing computer
Towards a global solution to high level synthesis problems
Automatic structuring and optimization of hierarchical designs
PLFP256 A Pipelined Fourier Processor
FOGBUSTER: an efficient algorithm for sequential test generation
Multilevel Logic Synthesis of Very High Complexity Circuits
Scalable performance scheduling for hardware-software cosynthesis
High level synthesis: a data path partitioning method dedicated to speed enhancement
Proceedings of the conference on European design automation, EURO-DAC '92, Hamburg, Germany, September 7-10, 1992
An architecture for synthesis of testable finite state machines
Storage mechanism for VHDL intermediate form
VHDL fault simulation for defect-oriented test and diagnosis of digital ICs
Multiway netlist partitioning onto FPGA-based board architecture
ODE: output direct state machine encoding
LAST: a Layout Area and Shape function esTimator for high level applications
Model of conceptual design of complex electronic systems
Providing a VHDL-interface for proof systems
Object-oriented high-level modeling of system components for the generation of VHDL code
Routing algorithms for multi-chip modules
DONALD: a workbench for interactive design space exploration and sizing of analog circuits
Architectural tradeoffs in synthesis of pipelined controls
Communication based logic partitioning
State assignment for FSM low power design
SEESIM - a fast synchronous sequential circuit fault simulator with single event equivalence
A generic software system for drift reliability optimization of VLSI circuits
Efficient shape curve construction in floorplan design
Algorithms for a switch module routing problem
Design and Implementation of a High-Performance, Modular, Sorting Engine
An approach to module binding by fuzzy partitioning
A Low Cost BIST Methodology and Associated Novel Test Pattern Generator
GENVIEW: a portable source-level debugger for macrocell generators
A Functional Approach to Delay Faults Test Generation for Sequential Circuits
Modelling aspects of system level design
A procedural interface to CAD data based on EDIF
Chip assembly in the PLAYOUT VLSI design system
Design of a High Complexity Superscalar Microprocessor with the Portable IDPS ASIC Library
Hardware/software-cosimulation for mechatronic system design
Partial scan selection for user-specified fault coverage
A practical clock router that accounts for the capacitance derived from parallel and cross segments
A graphical system for hierarchical specifications and checkups of VLSI circuits
Concurrent path sensitization in timing analysis
An algorithm for improving optimal placement for river-routing
Electronic System Design: tools and methodology to meet the productivity challenge
State assignment of controllers for optimal area implementation
The Russian EDA Standards Activities
Affine transformations for multi-dimensional signal processing on ASIC regular arrays
Flow Management Requirements of a Test Harness for Testing the Reliability of an Electronic CAD System
A delay driven FPGA placement algorithm
Experience in functional-level test generation and fault coverage in a silicon compiler
Decomposing data machines
Correct interactive transformational synthesis of DSP hardware
Dynamic variable reordering for BDD minimization
Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping
Ghost/Spook: user interface and process management in the PACE framework
REGGEN-Test pattern generation on register transfer level
Goal oriented slicing enumeration through shape function clipping
GASTIM: A timing analyzer for GaAs digital circuits
A Genetic Algorithm for the Steiner Problem in a Graph
The semantics of behavioral VHDL '93 descriptions
Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing
Translating system specifications to VHDL
Multilevel logic optimization of very high complexity circuits
Accelerated test pattern generation by cone-oriented circuit partitioning
The CALLAS synthesis system and its application to mechatronic ASIC design problems
Fuzzy set based initial placement for IC layout
CAD of microsystems - a challenge for system engineering
Design and use of a system-level specification and verification methodology
Concepts and methods for version modeling
SIESTA: a multi-facet scan design system
A top down mixed-signal design methodology using a mixed-signal simulator and analog HDL
A State Space Decomposition Algorithm for Approximate FSM Traversal
A design system for special purpose processors based on architectures for distributed processing
Switch and logic-level modeling in EDIF 200: limitations and proposed solutions
Economics of point accelleration
Design of a persistent programming environment in an object oriented language using clustering and composite objects
Design of a Digital Neural Chip: Application to Optical Character Recognition by Neural Network
On the modeling and testing of VHDL behavioral descriptions of sequential circuits
Hardware/software partitioning and minimizing memory interface traffic
Functional abstraction of logic gates for switch-level simulation
An algebraic model for design space with applications to function module generation
SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits
Integration of SDL and VHDL for high-level digital design
SPI: an open interface integrating highly interactive electronic CAD tools
Synthesis of VHDL concurrent processes
Hierarchical behavioral partitioning for multicomponent synthesis
A time optimal robust path-delay-fault self-testable adder
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
The use of semantic information for control of a complex routing tool
Some relationships between delay testing and stuck-open testing in CMOS circuits
Synchronous parallel controller synthesis from behavioural multiple-process VHDL description
Quality considerations in delay fault testing
Implementation of a SDH STM-N IC for B-ISDN using VHDL based synthesis tools
VHDL quality: synthesizability, complexity and efficiency evaluation
Generating compilers for generated datapaths
Mickey: a macro cell global router
Practical inter-operation of CAD tools using a flexible procedural interface
Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST