yusuke1997/dblp-id-title huggingface dataset:
PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels
Energy management of highly dynamic server workloads in an heterogeneous data center
Edge effect aware crosstalk avoidance technique for 3D integration
A Calibration Procedure for Sensor Based Adaptive Voltage Scaling Approaches
Output Waveform Evaluation of Basic Pass Transistor Structure
Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform
A variation tolerant architecture for ultra low power multi-processor cluster
Transistor Level Synthesis Dedicated to Fast I.P. Prototyping
Table-Based Total Power Consumption Estimation of Memory Arrays for Architects
Comparison of low-voltage scaling in synchronous and asynchronous FD-SOI circuits
Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing
Effect of Post-oxidation Annealing on the Electrical Properties of Anodic Oxidized Films in Pure Water
Minimizing Spurious Switching Activities in CMOS Circuits
Framework for High-Level Power Estimation of Signal Processing Architectures
Power Aware Dividers in FPGA
Cost-Efficient C-Level Design of an MPEG-4 Video Decoder
The Most Complete Mixed-Signal Simulation Solution with ADVance MS
Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI
Low-power design methodology for CML and ECL circuits
Power Models for Semi-autonomous RTL Macros
High voltage recycling scheme to improve power consumption of regulated charge pumps
Ultra-Low Power Subthreshold Quasi Floating Gate CMOS Logic Family for Energy Harvesting
Low Effort, High Accuracy Network-on-Chip Power Macro Modeling
A power-efficient FPGA-based self-adaptive software defined radio
Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms
Switching Activity Estimation in Non-linear Architectures
Digital Hearing Aids: Challenges and Solutions for Ultra Low Power
An Integrated Environment for Embedded Hard Real-Time Systems Scheduling with Timing and Energy Constraints
26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, September 21-23, 2016
Analytical hold timing fixing for sub-threshold circuit based on its lognormal distribution
Evaluation and analysis of single-phase clock flip-flops for NTV applications
Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction
Enhanced GALS Techniques for Datapath Applications
Modelling Reversion Loss and Shoot-through Current in Switched-Capacitor DC-DC Converters with Petri Nets
The long way to power efficient, high performance DRAMs
Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis
Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels
Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors
Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices
Temperature-aware writing architecture for multilevel memristive cells
Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs
A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction
Hermes-A - An Asynchronous NoC Router with Distributed Routing
Optimized few layer graphene for heat spreading
Crosstalk Cancellation for Realistic PCB Buses
28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, Platja d'Aro, Spain, July 2-4, 2018
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level
Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual Platform
Power Efficient Vector Quantization Design Using Pixel Truncation
Zephyr: A Static Timing Analyzer Integrated in a Trans-hierarchical Refinement Design Flow
Convex optimization of resource allocation in asymmetric and heterogeneous SoC
Residue Arithmetic for Designing Low-Power Multiply-Add Units
Energy modeling of coupled interconnects including intrinsic misalignment effects
Performance estimation of program partitions on multi-core platforms
Clock Distribution Techniques for Low-EMI Design
Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction
Gate leakage current accurate models for nanoscale MOSFET transistors
A framework for analyzing the propagation of hardware-induced errors in non-recursive LTI blocks with finite wordlength effects
UVM-Based Verification of a Mixed-Signal Design Using SystemVerilog
Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs
A Generic Timing Mechanism for Using the APPLES Gate-Level Simulator in a Mixed-Level Simulation Environment
Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits
Low Energy Voltage Dithering in Dual V DD Circuits
Secure cryptographic hardware implementation issues for high-performance applications
A novel leakage power reduction technique for nano-scaled CMOS digital integrated circuits
Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse
Design of future integrated systems: A cyber-physical systems approach
Sleep-Transistor Based Power-Gating Tradeoff Analyses
Towards a Cross-Layer Framework for Accurate Power Modeling of Microprocessor Designs
Coarse-grained learning-based dynamic voltage frequency scaling for video decoding
A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses
An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC Architecture
Dynamic Power Management of a Computer with Self Power-Managed Components
A New Bounding Technique for Handling Arbitrary Correlations in Path-Based SSTA
Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings
Low-Power Asynchronous A/D Conversion
Clocking and Clocked Storage Elements in Multi-GHz Environment
Combined Analysis of Supply Voltage and Body-Bias Voltage for Energy Management
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005, Proceedings
Constraints, Hurdles, and Opportunities for a Successful European Take-Up Action
A CAD Platform for Sensor Interfaces in Low-Power Applications
Trends in Ultralow-Voltage RAM Technology
Switching-Activity Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs
Evaluating the impact of environment and physical variability on the ION current of 20nm FinFET devices
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits
PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI
Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications
A Formal Approach for Estimating Embedded System Execution Time and Energy Consumption
Optimizing the Configuration of Dynamic Voltage Scaling Points in Real-Time Applications
Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-V t Domain By Architectural Folding
Fast energy evaluation of embedded applications for many-core systems
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
Inferring custom architectures from OpenCL
Variability-Speed-Consumption Trade-off in Near Threshold Operation
ABeeMap: A mapping algorithm based on multi-objective Artificial Bee Colony
An unconventional computing technique for ultra-fast and ultra-low power data mining
Delay Constrained Register Transfer Level Dynamic Power Estimation
Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers
Throughput balancing for energy efficient near-threshold manycores
Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating
Performance Metric Based Optimization Protocol
GALSification of IEEE 802.11a Baseband Processor
Power Modeling, Estimation, and Optimization for Automated Co-design of Real-Time Embedded Systems
Exploiting Narrow Values for Energy Efficiency in the Register Files of Superscalar Microprocessors
1-D memristor-based cellular automaton for pseudo-random number generation
On Skin Effect in On-Chip Interconnects
Reservoir Computing Hardware for Time Series Forecasting
29th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2019, Rhodes, Greece, July 1-3, 2019
Optimization of Reliability and Power Consumption in Systems on a Chip
24th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS), Palma de Mallorca, Spain, September 29 - Oct. 1, 2014
A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates
Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips
Low Power Implementation of Trivium Stream Cipher
The First Quartz Electronic Watch
Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions
Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS
Power Supply Selective Mapping for Accurate Timing Analysis
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches
Compiling for performance and power efficiency
Interpreting SSTA Results with Correlation
Performance Comparison of VLSI Adders Using Logical Effort
Efficient Clock Distribution Scheme for VLSI RNS-Enabled Controllers
On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems
A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations
VLSI architecture design and implementation of a LDPC encoder for the IEEE 802.22 WRAN standard
Low-Power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters
Power-Aware Design via Micro-architectural Link to Implementation
Dynamic Data Type Optimization and Memory Assignment Methodologies
Effect of supply voltage on random telegraph noise of transistors under switching condition
A Power-Efficient and Scalable Load-Store Queue Design
Energy management via PI control for data parallel applications with throughput constraints
Transistor-Level Gate Modeling for Nano CMOS Circuit Verification Considering Statistical Process Variations
An efficient eye-diagram determination technique for multi-coupled interconnect lines
Fast Universal Synchronizers
Subthreshold-based m-sequence code generator for ultra low-power body sensor nodes
Analytical High-Level Power Model for LUT-Based Components
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings
Power Estimation for Ripple-Carry Adders with Correlated Input Data
Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies
Design of a flexible multi-source energy harvesting system for autonomously powered IoT : The PERPS project
Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library
Impact of Coarse-Grained Power Gate Placement on a Fine-Grained System Design
Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis
Power - Performance Optimization for Custom Digital Circuits
A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission
Low Power Distance Measurement Unit for Real-Time Hardware Motion Estimators
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines
Sleepy Stack Reduction of Leakage Power
Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor
Pulse controlled memristor-based delay element
Timing modeling at RT-level by separation of design- and stress related aging impacts
Interconnect Driven Low Power High-Level Synthesis
Early Power Estimation for System-on-Chip Designs
Advanced Cell Modeling Techniques Based on Polynomial Expressions
A fair comparison of adders in stochastic regime
Optimization for Real-Time Systems with Non-convex Power Versus Speed Models
Power Consumption Reduction Using Dynamic Control of Micro Processor Performance
Metric Definition for Circuit Speed Optimization
Architectural Challenges for the Next Decade Integrated Platforms
A Performance-Driven Multilevel Framework for the X-Based Full-Chip Router
Efficient Simulation of Power/Ground Networks with Package and Vias
Power Modeling of a NoC Based Design for High Speed Telecommunication Systems
3D Integration for Digital and Imagers Circuits: Opportunities and Challenges
Ultra low-power standard cell design using planar bulk CMOS in subthreshold operation
Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution
On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects
Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey
Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs
Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width
A global perspective on energy conservation in large data networks
Document classification systems in heterogeneous computing environments
An Adiabatic Charge Pump Based Charge Recycling Design Style
Exploiting Input Variations for Energy Reduction
Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits
User dependent aging prediction model for automotive controllers with power electronics
Weakness Identification for Effective Repair of Power Distribution Network
An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs
Exploiting Dynamic Workload Variation in Offline Low Energy Voltage Scheduling
MEMS-Based Runtime Idle Energy Minimization for Bursty Workloads in Heterogeneous Many-Core Systems
Data Dependences Critical Path Evaluation at C/C++ System Level Description
A Quick Method for Energy Optimized Gate Sizing of Digital Circuits
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1
A New Methodology to Design Low-Power Asynchronous Circuits
A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers
Instrumentation Set-up for Instruction Level Power Modeling
Efficient parallelization of the Discrete Wavelet Transform algorithm using memory-oblivious optimizations
A distributed VHDL compiler and simulator accessible from the web
A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates
Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation
Design and Implementation of a Memory Generator for Low-Energy Application-Specific Block-Enabled SRAMs
Application-aware scaling governor for wearable devices
A Standard Cell Optimization Method for Near-Threshold Voltage Operations
Minimizing Power for Neural Network Training with Logarithm-Approximate Floating-Point Multiplier
Efficient Post-layout Power-Delay Curve Generation
Hierarchical Modeling of a Fractional Phase Locked Loop
Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)
Low-Power Register File Based on Adiabatic Logic Circuits
Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip
A Physically Oriented Model to Quantify the Noise-on-Delay Effect
Power-efficient turbo-decoder design based on algorithm-specific power domain partitioning
Response time schedulability analysis for hard real-time systems accounting DVFS latency on heterogeneous cluster-based platform
Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications
Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level
Second Generation Delay Model for Submicron CMOS Process
Energy-efficient Level Shifter topology
A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI
An FPGA Power Aware Design Flow
LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNS
Green metadata based adaptive DVFS for energy efficient video decoding
Timing Modeling of Flipflops Considering Aging Effects
CMOS Gate Sizing under Delay Constraint
Low Power Design Techniques for Contactless Chipcards
Energy-Efficient Design of the Reorder Buffer
Asynchronous sub-threshold ultra-low power processor
Assertive Dynamic Power Management (AsDPM) Strategy for Globally Scheduled RT Multiprocessor Systems
Impact of Array Data Flow Analysis on the Design of Energy-Efficient Circuits
Open Multimedia Platform for Next-Generation Mobile Devices
Enabling environmentally-powered indoor sensor networks with dynamic routing and operation
Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers
A Simple MOSFET Parasitic Capacitance Model and Its Application to Repeater Insertion Technique
The Holy Grail of Holistic Low-Power Design
Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance
Application Analysis with Integrated Identification of Complex Instructions for Configurable Processors
Systematic Preprocessing of Data Dependent Constructs for Embedded Systems
An Activity Monitor for Power/Performance Tuning of CMOS Digital Circuits
Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers
Robust Low Power Embedded SRAM Design: From System to Memory Cell
Power Macro-Modelling for Firm-Macro
Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation
A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits
L0 Cluster Synthesis and Operation Shuffling
Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path
Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply
Power modeling and characterization of Graphene-based logic gates
Run-Time Software Monitor of the Power Consumption of Wireless Network Interface Cards
A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs
VCO Verilog AMS Model for Fast Simulation in VCO-Based ADC
Optimal content-dependent dynamic brightness scaling for OLED displays
A Design Space Comparison of 6T and 8T SRAM Core-Cells
Buffer Sizing for Crosstalk Induced Delay Uncertainty
Untraditional Approach to Computer Energy Reduction
A Comparison between Two Logic Synthesis Forms from Digital Switching Noise Viewpoint
A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling
Tutorial Hearing Aid Algorithms
A Scalable Power Modeling Approach for Embedded Memory Using LIB Format
Power Consumption in Reversible Logic Addressed by a Ramp Voltage
A framework for efficient evaluation and comparison of EES Models
A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems
White-Box Current Source Modeling Including Parameter Variation and Its Application in Timing Simulation
Speed Indicators for Circuit Optimization
Graph-Based STA for Asynchronous Controllers
Accurate PTV, State, and ABB Aware RTL Blackbox Modeling of Subthreshold, Gate, and PN-Junction Leakage
Memory Access Pattern Profiling for Streaming Applications Based on MATLAB Models
New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses
Dynamic current reduction of CMOS digital circuits through design and process optimization
Parametric yield optimization using leakage-yield-driven floorplanning
Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses
Impact of Voltage Scaling on Glitch Power Consumption
Noise Margin Based Library Optimization Considering Variability in Sub-threshold
A Bottom-Up Approach to On-Chip Signal Integrity
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings
Dynamic electrothermal macromodeling techniques for thermal-aware design of circuits and systems
Tejas: A java based versatile micro-architectural simulator
Low Power Elliptic Curve Cryptography
Structure Independent Representation of Output Transition Time for CMOS Library
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique
A High-Performance Neuron for Artificial Neural Network based on Izhikevich model
An Extended Metastability Simulation Method for Synchronizer Characterization
Energy efficiency of Zipf traffic distributions within Facebook's data center fabric architecture
A Low-Voltage Log-Domain Integrator Using MOSFET in Weak Inversion
Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment
Blade-OC Asynchronous Resilient Template ‡ This research has been supported in part by NSF Grant #1619415
Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-Cores
High Performance Accelerator for CNN Applications
A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults
Two Efficient Synchronous Û Asynchronous Converters Well-Suited for Network on Chip in GALS Architectures
Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis
Crown scheduling: Energy-efficient resource allocation, mapping and discrete frequency scaling for collections of malleable streaming tasks
A learning tool MOSFET model: A stepping-stone from the square-law model to BSIM4
Exploration of technology parameter values of integrated circuit technologies
Low-cost hardware implementation of Reservoir Computers
Optical versus Electrical Interconnections for Clock Distribution Networks in New VLSI Technologies
Design Space Exploration and Trade-Offs in Analog Amplifier Design
Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing
The Design and Implementation of a Power Efficient Embedded SRAM
PIRATE: A Framework for Power/Performance Exploration of Network-on-Chip Architectures
A Multi-level Validation Methodology for Wireless Network Applications
Low-Power Adaptive Bias Amplifier for a Large Supply-Range Linear Voltage Regulator
Smart Enumeration: A Systematic Approach to Exhaustive Search
Sensitivity of a Power Supply Damping Method to Resistance and Current Waveform Variations
Parallelization and energy evaluation of interframe compression technique for video images - QSDPCM
Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits
Estimation of Crosstalk Noise for On-Chip Buses
Clock Distribution Network Optimization under Self-Heating and Timing Constraints
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers
Stochastic Radial Basis Neural Networks
A High-Level DSM Bus Model for Accurate Exploration of Transmission Behaviour and Power Estimation of Global System Buses
A Novel Approach to the Design of a Linearized Widely Tunable Very Low Power and Low Noise Differential Transconductor
Optimizing the configuration and control of a novel human-powered energy harvesting system
A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning
Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports
Formal description of an approach for power consumption estimation of embedded systems
Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell
Case Studies of Logical Computation on Stochastic Bit Streams
Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study
Reducing Cross-Talk Induced Power Consumption and Delay
Mobile Terminals System-Level Memory Exploratio for Power and Performance Optimization