yusuke1997/dblp-id-title huggingface dataset:
A low-complexity bit-efficient Neuromorphic Astrocyte-Neuron Circuit
Human Body Communication Channel Characterization for Leadless Cardiac Pacemakers
Current trends in high-level synthesis of asynchronous circuits
Drift-driven investigation of phase distribution in phase-change memories
A Novel quasi-Newton with Momentum Training for Microwave Circuit Models using Neural Networks
Interactive verification of switched-current sigma-delta modulators
New Energy-Efficient 3-2 and 4-2 Approximate Adder Compressors Topologies
Analysis of the ideal SFDR limit for an N bit digital-to-analog converter
An 11Gb/s CMOS Demultiplexer Using Redundant Multi-valued Logic
An Analogue Counter Using Memristor for Single Photon Detectors
Novel precision full-wave rectifier
Temporal and System Level Modifications for High Speed VLSI Implementations of Cryptographic Core
Neural network based programmed pulse width modulation usable on voltage source inverters (VSIs)
An evolution model on the set of the populations of neurons
Benefits of Joint Optimization of Tunable Wake-up Radio Architecture and Protocols
Closed-loop simulation method for evaluation of static offset in discrete-time comparators
Model-based coding of SAR and ultrasound images
Operational deflection shape of rotating object using tracking laser Doppler vibrometer
Dispersion analysis and adaptive transformation of chaotic signal attractor
Predictive Energy-Aware Adaptive Sampling with Deep Reinforcement Learning
Efficient cascaded VLSI FFT architecture for OFDM systems
Dynamic analysis of Dickson charge pump circuits with a resistive load
Multibit CT SD modulators with pulse width modulation and FIR-DAC in the feedback path
Stability analysis of an adaptive structure for sigma delta modulation
Practical aspects of MOS transistor model "accuracy" in modern CMOS technology
Very low cost entropy source based on chaotic dynamics retrofittable on networked devices to prevent RNG attacks
A 0.7 μm CMOS clock recovery circuit for 622 Mb/s SDH systems
Adaptive digital pre-distortion for future wireless transmitters
Low power 2.5-Gb/s CMOS burst-mode transimpedance amplifier with fast response time using a novel peak detection circuit
Triple Band Wireless Transceiver demonstrating Reliable and Low Latency Communication
High performance 4H-SiC emitter coupled logic circuits
On the impact of encoding on the complexity of residue arithmetic circuits
Low-Cost Wi-Fi-based System Using Passive Microwave Sensors for Liquid Characterization
Weighted minimax design of sharpened CIC filters
A protection mechanism for intellectual property rights (IPR) in FPGA design environment
VLSI Implementation of digital frequency sensors as hardware countermeasure
A topological approach for determining the uniqueness of the DC solutions in MOS-transistor circuits
Frequency synchronization for wireless networks using field programmable gate arrays
Spectral purity analysis of integer-N PLL
A tool for transient fault analysis in combinational circuits
A 5 GHz low noise amplifier on 0.35 μm BiCMOS SiGe
New MTCMOS Flip-Flops with Simple Control Circuitry and Low Leakage Data Retention Capability
A method to improve the frequency characteristics in transition period for time-varying cosine modulated filter banks
Fast charging technique for Li-Ion battery charger
Low-cost PVDF High-Frequency Ultrasound Sensor Design and Manufacturing for Thermoacoustic Imaging Applications
New algorithm for parallelotope updating in output error bounding
Multiplier architecture power consumption characterization for low-power DSP applications
Miniature Dual Band Antenna for WPT application
TPQA: Three point quadrature approximation MPPT algorithm
Memristive systems analysis of 3-terminal devices
An analog median filter with fuzzy adaptation
Lock and Unlock: A Data Management Algorithm for A Security-Aware Cache
General design method for the filters based on the requirements and a filter design chart
Layout exploration of geometrically accurate arithmetic circuits
Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs
State-space equations of regular and strictly topologically degenerate linear lumped time-invariant networks: the implicit tree-tableau method
Two dimensional AR model of signing process and its application to on-line signature verification
On-line calibration for non-linearity reduction of delay-locked delay-lines
An 8-PSK receiver using an integrated low-noise amplifier & super-regenerative oscillator with digital detection technique
An algorithm for finding all the DC solutions of short-channel MOS transistor circuits
Comparative Thermal Analysis of Single vs. Arrayed Layouts for Integrated Power Transistors Using COMSOL
FinFET Variability and Near-threshold operation: Impact on Full Adders design using XOR Blocks
Modeling of analog circuits by using support vector regression machines
Modified Maximum and Minimum Spread estimation method for detection of neural spikes
80 GHz co-designed LNA and antenna for automotive radar
Design of ultra low-power analog cells with dynamic current biasing
Calibration of input-match and its center frequency for an inductively degenerated low noise amplifier
Digital correction of mismatches in time-interleaved ADCs for digital-RF receivers
Baseband predistorter for radio frequency power amplifiers based on a non-iterative, fast adaptation method
Practical works for on-line teaching design and test of digital circuits
Yield model characterization for analog integrated circuit using Pareto-optimal surface
Speaker identification system based on FPGA
A new approach for mobile manipulator motion control
Mechanical stress measurement electronics based on piezo-resistive and piezo-Hall effects
On the sensitivity of lattice wave digital filters versus block-optimal state-space structures
A sampled-analog rank-order-filter architecture
An Analog-Digital Neural Processor for Integrated Sensor Conditioning
A -102 dB PSRR 1.2V Bandgap Voltage Reference for use in a Standalone MPPT Boost Converter for Solar Submodules
A CMOS 0.13µm low power front-end for GEM detectors
Controllability of linear 2-D systems
On the accuracy of Elmore-based Delay Models
Proceedings of the 2000 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000, Jounieh, Lebanon, December 17-20, 2000
Power aware test-data compression for scan-based testing
PDF folding for stochastic flash ADCs
VLSI implementation of the keyed-hash message authentication code for the wireless application protocol
Electrocardiogram data compression algorithm based on the linear prediction of the wavelet coefficients
PVT variability analysis of FinFET and CMOS XOR circuits at 16nm
Multiplier-free polynomial-based FIR filters with an adjustable fractional delay
Active on-chip voltage regulator based on second generation current conveyor
System-level power optimizing data-flow transformations for multimedia applications realized on programmable multimedia processors
A new RC design for mixed-grain based dynamically reconfigurable architectures
An Area-Efficient Design Strategy for Dickson Charge Pumps on Flexible Substrate
Scene Context Classification with Event-Driven Spiking Deep Neural Networks
Low-Power Low-Complexity 10-Bit Single-Ended SAR ADC in 65-nm CMOS for Biomedical Applications
Novel high-speed dynamic differential ultra low voltage logic for supply-voltage below 300 mV
Generalized Pascal matrix of first order S-Z transforms
A novel half-band SC architecture for efficient analog impulse sampled interpolation
A 2.3-GHz to 5.8-GHz CMOS receiver front-end for WiMAX/WLAN
A 4 th -Order Continuous-Time $\Delta\Sigma$ Modulator with Improved Clock Jitter Immunity using RTZ FIR DAC
Design and characterization of a QLUT in a standard CMOS process
Defect-oriented testing of analogue and mixed signal ICs
Application of distributed control unit (DCU) in machine control area
Design and experimentation with low-power morphable multipliers
Development languages and environments for induction cooking system design and simulation
Dynamically reconfigurable analog circuit design automation through multiobjective optimization and direct execution
Reconfigurable multiband multimode LNA for LTE/GSM, WiMAX, and IEEE 802.11.a/b/g/n
A Fully Integrated 2.45-GHz Frequency Synthesizer and FSK Modulator
On the analysis of three-conductor transmission lines using Park transformation
Simulation of electromagnetic radiation produced by integrated circuits
Self-biased input common-mode generation for improving dynamic range and yield in inverter-based filters
Scalable, dynamic and growing hardware self-organizing architecture for real-time vector quantization
A Curious Result concerning Spur Generation in MASH 1-1-1 based Fractional-N CP-PLLs with a Second-Order Nonlinearity
Comb Types Channel Estimation in Multiple Access OFDM System
Fully-integrated, large-time-constant, low-pass, Gm-C filter based on current conveyors
Characterization of a temporal contrast microbolometer infrared sensor
A capacitance meter based on an oversampling sigma-delta modulator and its application to capacitive sensor interface
Development and comparison of reduced-order interconnect macromodels for time-domain simulation
A ROM-less direct digital frequency synthesizer based on 16-segment parabolic polynomial interpolation
35 dB/3 GHz LNA on 0.8 μm BiCMOS with 8 mW/2 V
An Analog CMOS Voltage-Controlled Phase-Shifter With A 100° Tuning Range For Telecommunication Baseband Signal Processing
A method for stability compensation of low-load-capacitor low-power LDO
An XML-based configuration management architecture for IP routers
Wideband Low Noise Amplifiers for mm-Wave 5G Application using Capacitive Feedback Technique in 22nm FDSOI
Track and hold circuit design and implementation in 65 nm CMOS technology for RF subsampling receivers
Formal specification of QoS parameters by hierarchical tree structure
A cell clustering technique to reduce transistor count
6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999, Pafos, Cyprus, September 5-8, 1999
Investigations of margins for the interplay using a digital testing tool dedicated to neutrons discrimination
PSP based DCG-FGT transistor model including characterization procedure
New design method for controlling power stages based on IGBT switching ferrite transformers: applied to an 8 kW small size light weight electric welding machine
A 2.4GHz to 6GHz active balun in GaN technology
An advance dynamic resource reservation algorithm for OBS networks: Design and performance
Design of electric filters in MAPLE and through WWW interface
Low complexity frequency-domain turbo-equalizer for ST-BICM over MIMO ISI channel
A C-embedded algorithm for real-time monocular SLAM
A new low power 2-2 cascaded sigma-delta modulator with the reduced number of op-amps for GSM transceiver applications
An approach for the measurement of distance travelled by blind and visually impaired people
Low Power Implementation of Decimation Filters in Multistandard Radio Receiver Using Optimized Multiplication-Accumulation Unit
Nonstandard sensitivity analyses in frequency and time domains
A 109dB PSRR, 31µW fully-MOSFET bandgap voltage reference in 0.13µm CMOS technology
IP-based design of custom field programmable network processors
Low-noise CMOS analog-to-digital interface for MEMS resistive microphone
Methodology for Analyzing the Vehicle System Data of the Onboard Power System Using Machine Learning Models as an Enabler of Data-Driven Development
Fuzzy and neuro-fuzzy designs of boost converter supplying DC motors
A Fully Integrated Light-Powering System with Integrated CMOS Photovoltaic Cell for Batteryless IoT Devices
Analytical methods to determine internal precisions of Viterbi decoders
A testbed for robotic visual servoing and catching of moving objects
Stability of a continuous-time state variable filter with ORA-L and current amplifier integrators
Mobile location in GSM using signal strength technique
The design of memristor based high pass filter circuit
On the Influence of the Laser Illumination on the Logic Cells Current Consumption : First measurement results
MASH DDSM-Induced Spurs in a Fractional-N Frequency Synthesizer
SoC design using behavioral level virtual components
Evaluation of adaptive management techniques in NoC-Based MPSoCs
Dynamic power of CMOS gates driving lossy transmission lines
A cost-effective hardware architecture for fail-safe autonomous underwater vehicles
Polymer-electrolyte-film-based humidity sensor with integrated signal conditioner
Isomorphism elimination to enhanced design centering of analog circuits using GA and the regionalization method
A transform domain approach in blocking effect detection
Multi-pulse/single-pulse design for maximizing SIR in partially equalized OFDM systems over highly dispersive channels
A Digital Frequency Shift Keying Demodulator
Design of clock-recovery GaAs ICs for high-speed communication systems
Xstream - a hardware accelerator for digital holographic imaging
On the existence of nonlinear equalizer
Noise analysis of current mode differential integrators
Analysis and design of Network on Chip under high process variation
A Low-noise Low-offset Op Amp in 0.35μm CMOS Process
Configurable logic style translation based on an openaccess engine
A low-power reconfigurable GFSK RF transceiver with sub-1GHz band for short range applications
Reconfigurable IR-UWB Current Mode Switched Receiver for IoT Applications
On the short-term predictability of fully digital chaotic oscillators for pseudo-random number generation
New iterative algorithms and architectures of modular multiplication for cryptography
Transient fault analysis of CORDIC processor
A 0.9 V wide-input-range bulk-input CMOS OTA for G m -C filters
28-nm CMOS Resistor-Less Voltage Reference with Process Corner Compensation
Breast cancer detection using non-invasive near-field microwave nondestructive testing techniques
Synthesis of Nonlinear Impedance Converters for Emulating Memory Elements
Analog triangular-to-sine converter using lateral-pnp transistors in CMOS process
A timed high level Petri net model for the automation scheme of a chemical process
HDC-IM: Hyperdimensional Computing In-Memory Architecture based on RRAM
Observations concerning "Horn Spurs" in a MASH-based Fractional-N CP-PLL
A 800MHz, O.21pJ, 1.2V to 6V Level Shifter Using Thin Gate Oxide Devices in 65nm LSTP
Design of A New CMOS Controllable Mixed-Signal Current Mode Fuzzy Logic Controller (FLC) Chip
Power Analysis Resistant Hardware Implementations of AES
Information processing in digital domain
Application of MO-TRIBES to the design of analog electronic circuits
Memory hierarchy layer assignment for data re-use exploitation in multimedia algorithms realized on predefined processor architectures
A 1.2 V companding current-mode integrator for standard digital CMOS processes
Impact of technology scaling on the minimum energy point for FinFET based flip-flops
Asynchronous low power VLSI implementation of the International Data Encryption Algorithm
Configurable and high-throughput architectures for Quasi-cyclic low-density parity-check codes
Structure of signal flow graph of OTA-C high-pass filters reduced in the number of OTAs
79 GHz Fully Integrated Fully Differential Si/SiGe HBT Amplifier for Automotive Radar Applications
Visual navigation of communicating vehicles in unknown and changing environment
Reconfigurable nanoscale logic cells : a comparison study
A modified dithered signed-error constant-modulus algorithm for blind adaptive equalizer
A 4 Gsps, 2-4 GHz input bandwidth, 3-bits flash A/D converter
A low noise CMOS image sensor with a 14-bit two-step single-slope ADC and a column self-calibration technique
Second order Sigma-Delta modulator realization
On designing digit multipliers
Low-voltage CMOS voltage squarer
An FPGA based co-processor for GLCM texture features measurement
An ADPLL-based fast start-up technique for sensor radio frequency synthesizers
Analogue radial basis function networks for phoneme recognition
Embedded testing for data communications circuits
Design and test of a digital system based on a CMOS 0.3 μm logarithmic pixel for pulsed laser optical detection
The development of a framework for multimedia courseware
FPGA-based Low-cost System for Automatic Tests on Digital Circuits
SDR waveform components implementation on single FPGA multiprocessor platform
Current output stage with improved CMRR
A 50 Mbps/pin 12-input/output 40 nsec Latency Wireless Connector Using a Transmission Line Coupler with Compact SERDES IC in 180 nm CMOS
A 400 MHz 0.934ps rms jitter multiplying delay lock loop in 90-nm CMOS process
A DDS synthesizer with time domain interpolator
Novel compact tunable bandpass filter using capacitively loaded H-shaped resonator
Analog fault diagnosis and testing by inverse problem technique
Polar Decoding Hardware Implementation
A mixed-signal front-end ASIC for EEG acquisition system
A generic FPGA emulation framework
CAD tools for fast analysis of parasitic coupling and mismatch effects in switched-capacitor circuits
An FFT core for DVB-T2 receivers
Characterization of In-Phase/Quad-Phase Digital Downconversion Via Special Sampling Scheme
Programmable incrementing/decrementing binary accumulator for high-speed calibration loops
Optimization and efficient implementation of fractional delay FIR filters
Transfer Learning for Efficient Analog Design Migration Across Process Nodes Using Reinforcement Learning
Embedded Linear Model Predictive Control Through Mesh Adaptive Direct Search Algorithm
Analysis of absolute photonic band gaps in two-dimensional photonic crystals based on CdSe rods embedded in TiO2 matrix
Minimal attractor embedding dimension for discrete dynamic system using state-space method: theoretical ground
VLSI architectures for multimedia
A radiation hardened 512 kbit SRAM in 180 nm CMOS technology
A 4 Hz low-pass continuous-time filter
DynPack: Dynamie multi-objective packing algorithm for optimization of post place-and-route metrics in FPGAs
Low cost data acquisition systems based on standard interfaces
A noise insensitive high speed versatile operational amplifier library cell
The electronics of a control system for micromirrors in a laser-scanning device
Bit rate control of internetworking video transcoders
VLSI implementations of the triple-DES block cipher
3D EM simulations and analysis of in-package metal plate interconnecting high-side and low-side FETs of DC-DC converter
Open graphics system for 3D-mapping validation on robotics
A PAE-Controlled Wideband Power Amplifier for Sub-6GHz 5G Applications in 28nm FDSOI Technology
An Open-Source eFPGA-based SoC Design for Computation Acceleration
A Bias-Controlled Noise-Canceling CMOS Tuned Low Noise Amplifier for UWB Transceivers
A low-complexity soft-decision decoding architecture for the binary extended Golay code
RF to Bits Highly Tunable Sub-1 pJ/bit Digital Beamforming Receiver Architectures for 5G Applications
A comparative study for real time scheduling
Effective estimation of the harmonic component of speech and speech-like signals
New design of RF-DC rectifier circuit for radio frequency energy harvesting
Live Demo: ShortCircuit: An Open-Source ChatGPT Driven Digital Integrated Circuit Front-End Design Automation Tool
CAD Modeling of mm-Wave Circuits Incorporating Avalanche Noise Diodes
Parallel overloaded CDMA interconnect (OCI) bus architecture for on-chip communications
DVFS method of memory hierarchy based on CPU microarchitectural information
Investigation on bond wire dedicated to integrated time base
Analysis of coupling capacitance between TSVs and metal interconnects in 3D-ICs
A contingent of autonomous marching robots: intricacies of system design and motion control
Chaos control in a transmission line model
Design considerations for a linear modulation DCSK chaos-based radio
Sub-images based image hashing with non-negative factorization
Memristor Based Integrated System for the Long-Term Analysis of Chronic Wounds: Design and Clinical Trial
k-terminal reliability of communication networks
Challenges in ultra deep submicrometer high performance VLSI circuits
An Energy-efficient and Fast KNN Search Accelerator for Large Scale Point Cloud Map
Technological and design constraints for multilevel flash memories
A CMOS radio receiver architecture for ISM/UNII multi-standard wireless applications
Low-voltage CMOS current feedback amplifier
Transformation of the systolic arrays from two-dimensional to linear form
Shuffled serial adder: an area-latency effective serial adder
High performance FIR filter design for 6-input LUT based FPGAs
Target-Aware Automated RTL Generation for RISC-V SoC Designs: A Model-Driven Approach
Mirror Full Adder SET Susceptibility on 7nm FinFET Technology
A new configuration of two-stage wide-band amplifier with matched input and output impedances
A special march test to detect delay coupling faults for RAMs
An energy-efficient FPGA-based matrix multiplier
A comparative study on the adaptive lattice filter structures in the context of texture defect detection
A flexible MIMD pixel processor for high quality MPEG-2 motion and vector processing
A novel modelling and optimisation of gain-boosted cascode amplifiers for high speed applications
High Speed High Precision Voltage-Mode MAX and MIN Circuits
A new architecture of CCK modem based on iterative differential-modulation and phase-detection
Study of low sensitivity property of delta operator based sampled-data filters
Analysis of an Inverter-Based CMOS Envelope Detector
A 1-V CMOS audio amplifier for low cost hearing aids
Capacitive Fingerprint Sensor for Contactless Payment Cards
Dynamical intelligent network based on group representation theory
Crosstalk-avoidance coding for low-power on-chip bus
High speed multi-channel data acquisition chip
The art of extracting circuit transfer functions with SuTra analyses
A CNFET-based characterization framework for digital circuits
Design of a portable microprocessor-based stimulator for the recreation of impaired gastrointestinal motility
Design methodology and integration of a 1.8GHz outphasing power amplifier for mobile terminals
Transducer interface for multichannel wired telemetry in high temperature environment
A CMOS based operational floating current conveyor and its applications
Time-Mode z -1 Programmable Multiplier
An improved transmission energy transformer for a non invasive rechargeable battery to artificial organs
Genetic algorithms for adaptive non-linear predictors
Digital self-tuning technique for continuous-time filters
A neuro-fuzzy approach for student performance modeling
A 32-channel ASIC for X-Ray detectors
Programmable sine wave generator employing a mismatch-shaping DAC
High frequency RC chaos generator
Dynamic tree-depth adjustment for low power HEVC encoders
On signal reconstruction from Fourier magnitude
Curvilinear Layout for CMOS Image Sensors Task-Specific Imaging
A novel 1V, 24µW, ΣΔ modulator using Amplifier & Comparator Based Switched Capacitor technique, with 10-kHz bandwidth and 64dB SNDR
Design of 65-nm CMOS Transformer-Based Impedance Matching for LTE Power Amplifier Applications
Power- and Area-optimized Neural Network IC-Design for Academic Education
An efficient implementation of the digital signature algorithm
Object based coding of video sequences at low bit rates using adaptively trained neural networks
On the current-mode current conveyor-based high-order filter realisations
Application-specific processor for local-binary-patterns generation
A low complexity coordinated FEXT cancellation for VDSL
High-pressure balloon catheter for real-time pressure monitoring in the esophagus
Realizing hardware accelerated AVS video playback on the Godson Platform
The application of multiwavelet transform to image coding
A multitransform architecture for the H.264/AVC standard and its design space exploration
A Variable Gain Multiband Shunt Feedback LNA for LTE
Impact of variability effects on FinFET transistors and combinational cells
Design of pseudo random keystream generator using fractals
A survey of thermal energy harvesting techniques and interface circuitry
Tearing techniques for symbolic simulation of large-scale analog circuits