yusuke1997/dblp-id-title huggingface dataset:
Dynamic V DD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction
Integrated Design Environment for Reconfigurable HPC
Application Specific Memory Access, Reuse and Reordering for SDRAM
A Control Data Acquisition System Architecture for MPSoC-FPGAs in Computed Tomography
An FPGA-Based Real-Time Event Sampler
A Configurable Multi-ported Register File Architecture for Soft Processor Cores
Comparison of Direct and Indirect Networks for High-Performance FPGA Clusters
Physical Design of FPGA Interconnect to Prevent Information Leakage
A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures
Accelerating Calculations on the RASC Platform: A Case Study of the Exponential Function
A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor
Hardware-Aware Optimizations for Deep Learning Inference on Edge Devices
Transparent Dynamic Reconfiguration as a Service of a System-Level Middleware
A Comprehensive Set of Schemes for PUF Response Generation
ArPALib: A Big Number Arithmetic Library for Hardware and Software Implementations. A Case Study for the Miller-Rabin Primality Test
A Dynamically Reconfigurable Mixed Analog-Digital Filter Bank
A Timing Driven Cycle-Accurate Simulation for Coarse-Grained Reconfigurable Architectures
Dynamic Partial Reconfigurable FIR Filter Design
Hardware/Software FPGA Architecture for Robotics Applications
Automatic Generation of FPGA-Specific Pipelined Accelerators
Open-Source SpMV Multiplication Hardware Accelerator for FPGA-Based HPC Systems
Hybrid-Mode Floating-Point FPGA CORDIC Co-processor
A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI
HoneyWiN: Novel Honeycomb-Based Wireless NoC Architecture in Many-Core Era
Dependability-Increasing Method of Processors under a Space Radiation Environment
FPGA-Based Parallel Pattern Matching
Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 20th International Symposium, ARC 2024, Aveiro, Portugal, March 20-22, 2024, Proceedings
A Custom Processor for a TDMA Solver in a CFD Application
The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems
Development Progress of SWLBM a Framework Based on Lattice Boltzmann Method for Fluid Dynamics Simulation
Highly Paralellized Architecture for Image Motion Estimation
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 18th International Symposium, ARC 2022, Virtual Event, September 19-20, 2022, Proceedings
Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs
Efficient Hardware Based Security Algorithm Implementation for WSN Medical Applications: The ARMOR Perspective
Hierarchical Optical Flow Estimation Architecture Using Color Cues
Adapting Processor Grain via Reconfiguration
Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning
Domain-Specific Modeling and Optimization for Graph Processing on FPGAs
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 17th International Symposium, ARC 2021, Virtual Event, June 29-30, 2021, Proceedings
A Dedicated Reconfigurable Architecture for Finite State Machines
On the OpenCL Support for Streaming Fixed-Function Accelerators on Embedded SoC FPGAs
Tile-Based Fault Tolerant Approach Using Partial Reconfiguration
Programmable Logic as Device Virtualization Layer in Heterogeneous Multicore Architectures
Design Space Exploration of a Particle Filter Using Higher-Order Functions
Data Parallel Application Adaptivity and System-Wide Resource Management in Many-Core Architectures
Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case Study
Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning
Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology Mapping
Embedded Reconfigurable Architectures
FPGA-Based High Performance AES-GCM Using Efficient Karatsuba Ofman Algorithm
Evaluating Schedulers in a Reconfigurable Multicore Heterogeneous System
AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications
Secure Local Configuration of Intellectual Property Without a Trusted Third Party
Real Time Simulation in Floating Point Precision Using FPGA Computing
The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA
A Scalable FPGA-Based Architecture for Depth Estimation in SLAM
Pipeline Optimization for Loops on Reconfigurable Platform
Exploring Dynamic Reconfigurable CORDIC Co-Processors Tightly Coupled with a VLIW-SIMD Soft-Processor Architecture
dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAs
Reconfigurable Multicore Architecture for Dynamic Processor Reallocation
Novel Arithmetic Architecture for High Performance Implementation of SHA-3 Finalist Keccak on FPGA Platforms
Optimal Unroll Factor for Reconfigurable Architectures
A Flexible Software Framework for Dynamic Task Allocation on MPSoCs Evaluated in an Automotive Context
Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA
Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors
NIM: An HMC-Based Machine for Neuron Computation
A Unified Framework for Over-Clocking Linear Projections on FPGAs under PVT Variation
Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations
Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud
Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures
Authentication of FPGA Bitstreams: Why and How
A Reconfigurable Implementation of the Tate Pairing Computation over GF (2 m )
A DSL and MLIR Dialect for Streaming and Vectorisation
A Vector Caching Scheme for Streaming FPGA SpMV Accelerators
Accurate Floating Point Arithmetic through Hardware Error-Free Transformations
Performance Analysis of Reconfigurable Processors Using MVA Analysis
A Design Methodology for the Next Generation Real-Time Vision Processors
Reconfigurable Computing for Accelerating Protein Folding Simulations
ROBoost: A Study of FPGA Logic-Based Power-Wasting Primitives
Exploring Functional Acceleration of OpenCL on FPGAs and GPUs Through Platform-Independent Optimizations
Parametric Optimization of Reconfigurable Designs Using Machine Learning
Hardware and a Tool Chain for ADRES
Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array
Radiation Tolerant Reconfigurable Hardware Architecture Design Methodology
Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer
Rapid Prototyping of Complex Micro-architectures Through High-Level Synthesis
Index to Constant Weight Codeword Converter
PISC: Polymorphic Instruction Set Computers
A Parallel Hardware Architecture for Image Feature Detection
Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider
Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing
Ultra-Low Latency and Extreme-Throughput Echo State Neural Networks on FPGA
Rapid Prototyping and Verification of Hardware Modules Generated Using HLS
FPGA Implementation of a Video Based Abnormal Action Detection System with Real-Time Cubic Higher Order Local Auto-Correlation Analysis
On the Use of (Non-)Cryptographic Hashes on FPGAs
Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures
FPGA-Based Computational Fluid Dynamics Simulation Architecture via High-Level Synthesis Design Method
HLS Algorithmic Explorations for HPC Execution on Reconfigurable Hardware - ECOSCALE
Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors
Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP Blocks
Architecture Reconfiguration as a Mechanism for Sustainable Performance of Embedded Systems in case of Variations in Available Power
Lookahead Memory Prefetching for CGRAs Using Partial Loop Unrolling
Graphtoy: Fast Software Simulation of Applications for AMD's AI Engines
Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs
Securely Sealing Multi-FPGA Systems
DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost
Reconfigurable Stream-Processing Architecture for Sparse Linear Solvers
Reducing Storage Costs of Reconfiguration Contexts by Sharing Instruction Memory Cache Blocks
Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture
Generic Systolic Array for Run-Time Scalable Cores
Runtime Adaptive Cache for the LEON3 Processor
Reconfigurable Computing and Task Scheduling for Active Storage Service Processing
HT-NoC: Reconfigurable High Throughput Network-on-Chip for AI Dataflow Accelerators
Hardware Task Scheduling for Partially Reconfigurable FPGAs
FPGA-Based Parallel DBSCAN Architecture
MicroACP - A Fast and Secure Reconfigurable Asymmetric Crypto-Processor - -Overhead Evaluation of Side-Channel Countermeasures-
A Resource Reduced Application-Specific FPGA Switch
Design of a Reversible PLD Architecture
Fast Optical Reconfiguration of a Nine-Context DORGA
ISA-DTMR: Selective Protection in Configurable Heterogeneous Multicores
Simulation of Complex Biochemical Pathways in 3D Process Space via Heterogeneous Computing Platform: Preliminary Results
Constructing Cluster of Simple FPGA Boards for Cryptologic Computations
Measuring Failure Probability of Coarse and Fine Grain TMR Schemes in SRAM-based FPGAs Under Neutron-Induced Effects
Automated Data Flow Graph Partitioning for a Hierarchical Approach to Wordlength Optimization
A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable Systems
DeSyRe: On-Demand Adaptive and Reconfigurable Fault-Tolerant SoCs
Parametric Design for Reconfigurable Software-Defined Radio
Ant Colony Optimization for Application Mapping in Coarse-Grained Reconfigurable Array
Updates on the Security of FPGAs Against Power Analysis Attacks
Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs
Efficient Hardware Acceleration of Recommendation Engines: A Use Case on Collaborative Filtering
A New Datapath Merging Method for Reconfigurable System
Reconfigurable Computing: Architectures, Tools and Applications - 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013. Proceedings
Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration
Fast Carry Chain Based Architectures for Two's Complement to CSD Recoding on FPGAs
Teaching SoC Using Video Games to Improve Student Engagement
TROUTE: A Reconfigurability-Aware FPGA Router
FPGA Optimizations for a Pipelined Floating-Point Exponential Unit
A Low-Cost BRAM-Based Function Reuse for Configurable Soft-Core Processors in FPGAs
Cryptographic Security Through a Hardware Root of Trust
Supporting Utilities for Heterogeneous Embedded Image Processing Platforms (STHEM): An Overview
Optimizing CNN-Based Hyperspectral Image Classification on FPGAs
UNITE: Uniform Hardware-Based Network Intrusion deTection Engine
Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs
On-Chip Ego-Motion Estimation Based on Optical Flow
3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices
Iterative Modular Division over GF(2 m ): Novel Algorithm and Implementations on FPGA
Partial Data Reuse for Windowing Computations: Performance Modeling for FPGA Implementations
From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing
Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow
A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece Accelerator
A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware
Teaching Hardware/Software Codesign on a Reconfigurable Computing Platform
Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems
Modular Acquisition and Stimulation System for Timestamp-Driven Neuroscience Experiments
FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores
Evaluation of Different Manual Placement Strategies to Ensure Uniformity of the V-FPGA
FLARE: An FPGA-Based Universal Large Flow Detection Engine
FPGA-Assisted Distribution Grid Simulator
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 21st International Symposium, ARC 2025, Seville, Spain, April 9-11, 2025, Proceedings
Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs
A Space Variant Mapping Architecture for Reliable Car Segmentation
General Purpose Real-Time Image Segmentation System
HTR: On-Chip Hardware Task Relocation for Partially Reconfigurable FPGAs
Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs
Entropy-Based Early-Exit in a FPGA-Based Low-Precision Neural Network
Update or Invalidate: Influence of Coherence Protocols on Configurable HW Accelerators
Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design
Exploiting Reconfigurable Vector Processing for Energy-Efficient Computation in 3D-Stacked Memories
The Q2 Profiling Framework: Driving Application Mapping for Heterogeneous Reconfigurable Platforms
Evaluating LULESH Kernels on OpenCL FPGA
Designing Heterogeneous FPGAs with Multiple SBs
Relocatable Hardware Threads in Run-Time Reconfigurable Systems
A Reconfigurable Audio Beamforming Multi-Core Processor
Providing Tamper-Secure SoC Updates Through Reconfigurable Hardware
Asynchronous ARM Processor Employing an Adaptive Pipeline Architecture
A Pipeline Interleaved Heterogeneous SIMD Soft Processor Array Architecture for MIMO-OFDM Detection
PDPR: Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs
Towards Analytical Methods for FPGA Architecture Investigation
Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023, Proceedings
An FPGA Stereo Matching Processor Based on the Sum of Hamming Distances
Memory-Aware Scheduling for a Resource-Elastic FPGA Operating System
FPGA-Extended General Purpose Computer Architecture
Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling Platform
High Level FPGA Modeling of an JPEG Encoder
FPGA Debugging with MATLAB Using a Rule-Based Inference System
Design Automation for Reconfigurable Interconnection Networks
A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware
Hardware Based Loop Optimization for CGRA Architectures
Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic
R-NoC: An Efficient Packet-Switched Reconfigurable Networks-on-Chip
Architectural Support for Multithreading on Reconfigurable Hardware
Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep
FPGA Implementation of QR Decomposition Using MGS Algorithm
A Lost Cycles Analysis for Performance Prediction using High-Level Synthesis
A Modified Merging Approach for Datapath Configuration Time Reduction
Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation
Improving the Performance of Adaptive Cache in Reconfigurable VLIW Processor
Algorithm Design Methodology for Embedded Architectures
Area/Performance Improvement of NoC Architectures
Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power
A Networked, Lightweight and Partially Reconfigurable Platform
Object Tracking and Motion Capturing in Hardware-Accelerated Multi-camera System
Embedded Vision Systems: A Review of the Literature
Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoC
A Dynamic Reconfigurable CPLD Architecture for Structured ASIC Technology
Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform
Run-Time Partial Reconfiguration Simulation Framework Based on Dynamically Loadable Components
An Acceleration Method for Evolutionary Systems Based on Iterated Prisoner's Dilemma
Transparent Near-Memory Computing with a Reconfigurable Processor
Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility
FPGA Implementation of Custom Floating-Point Logarithm and Division
HLS Tools for FPGA: Faster Development with Better Performance
Hierarchical Dynamic Power-Gating in FPGAs
A Modular Software Library for Effective High Level Synthesis of Convolutional Neural Networks
Dual CLEFIA/AES Cipher Core on FPGA
VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications
A Flexible Multilayer Perceptron Co-processor for FPGAs
An Almost Fully RRAM-Based LUT Design for Reconfigurable Circuits
An FPGA run-time parameterisable Log-Normal Random Number Generator
C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join
Boosting Single Thread Performance in Mobile Processors via Reconfigurable Acceleration
Light-Weight Permutation Generator for Efficient Convolutional Neural Network Data Augmentation
FPGA Soft-Core Processors, Compiler and Hardware Optimizations Validated Using HOG
An Analysis of Delay Based PUF Implementations on FPGA
RISC-V Based MPSoC Design Exploration for FPGAs: Area, Power and Performance
Multiplier-based double precision floating point divider according to the IEEE-754 standard
Chisel Usecase: Designing General Matrix Multiply for FPGA
Covid4HPC: A Fast and Accurate Solution for Covid Detection in the Cloud Using X-Rays
Hardware Index to Set Partition Converter
Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs
An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects
Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Experience
Adaptive Bandwidth Router for 3D Network-on-Chips
Complexity Analysis of Finite Field Digit Serial Multipliers on FPGAs
Evaluating High-Level Program Invariants Using Reconfigurable Hardware
HiFlipVX: An Open Source High-Level Synthesis FPGA Library for Image Processing
Efficient Multitasking on FPGA Using HDL-Based Checkpointing
Fast Partial Reconfiguration on SRAM-Based FPGAs: A Frame-Driven Routing Approach
Cycle-Accurate Debugging of Embedded Designs Using Recurrent Neural Networks
Real-Time FPGA Implementation of Connected Component Labelling for a 4K Video Stream
Genomic Data Clustering on FPGAs for Compression
Regular Expression Pattern Matching Supporting Constrained Repetitions
HLS-Based Acceleration Framework for Deep Convolutional Neural Networks
An Efficient Implementation of the Adams-Hamilton's Demosaicing Algorithm in FPGAs
An FPGA Acceleration for the Kd-tree Search in Photon Mapping
Efficient Buffer Design and Implementation for Wormhole Routers on FPGAs
Heterogeneous Systems for Energy Efficient Scientific Computing
FPGA-Based Anomalous Trajectory Detection Using SOFM
SqueezeJet: High-Level Synthesis Accelerator Design for Deep Convolutional Neural Networks
Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach
Profile-Guided Compilation of Scilab Algorithms for Multiprocessor Systems
Fast DSE for Automated Parallelization of Embedded Legacy Applications
PPMC: A Programmable Pattern Based Memory Controller
Switching Activity Models for Power Estimation in FPGA Multipliers
Reconfigurable Operator Based Multimedia Embedded Processor
Dataflow Graph Partitioning for Optimal Spatio-Temporal Computation on a Coarse Grain Reconfigurable Architecture
An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded Processors
FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor
Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization
Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip
A Fast Finite Field Multiplier
OCP2XI Bridge: An OCP to AXI Protocol Bridge
Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs
Applications of Small-Scale Reconfigurability to Graphics Processors
Spectral-Blaze: A High-Performance FFT-Based CNN Accelerator
Dynamic Spatial Multiplexing on FPGAs with OpenCL
Real Time Architectures for Moving-Objects Tracking
Creating the World's Largest Reconfigurable Supercomputing System Based on the Scalable ALTIX System Infrastructure and Benchmarking Life-Science Applications
Generic Network Interfaces for Plug and Play NoC Based Architecture
Stream Transfer Balancing Scheme Utilizing Multi-Path Routing in Networks on Chip
Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing
Hardware Sandboxing: A Novel Defense Paradigm Against Hardware Trojans in Systems on Chip
Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study
A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification
Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems
ReneGENE-Novo: Co-designed Algorithm-Architecture for Accelerated Preprocessing and Assembly of Genomic Short Reads
Simulation of the Dynamic Behavior of One-Dimensional Cellular Automata Using Reconfigurable Computing
Multiple Sequence Alignment Using Reconfigurable Computing
Application Specific FPGA Using Heterogeneous Logic Blocks
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 16th International Symposium, ARC 2020, Toledo, Spain, April 1-3, 2020, Proceedings [postponed]
Self Reconfiguring EPIC Soft Core Processors
Zynq Cluster for CFD Parametric Survey
New Partitioning Approach for Hardware Trojan Detection Using Side-Channel Measurements
Towards an Optimal Implementation of MLP in FPGA
Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications
Multiplication over F p m on FPGA: A Survey
FPGA Design of Delay-Based Digital Effects for Electric Guitar
Towards Performance Modeling of 3D Memory Integrated FPGA Architectures
Applied Reconfigurable Computing - 12th International Symposium, ARC 2016, Mangaratiba, RJ, Brazil, March 22-24, 2016, Proceedings
Hardware BLAST Algorithms with Multi-seeds Detection and Parallel Extension
Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability
SNN vs. CNN Implementations on FPGAs: An Empirical Evaluation
UltraSynth: Integration of a CGRA into a Control Engineering Environment
Supporting On-Chip Dynamic Parallelism for Task-Based Hardware Accelerators
A Run-Time Task Migration Scheme for an Adjustable Issue-Slots Multi-core Processor
Integrating Custom Instruction Specifications into C Development Processes
On the Suitability of Read only Memory for FPGA-Based CAM Emulation Using Partial Reconfiguration
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 14th International Symposium, ARC 2018, Santorini, Greece, May 2-4, 2018, Proceedings
An MLIR-Based Compilation Framework for CGRA Application Deployment
Accuracy, Training Time and Hardware Efficiency Trade-Offs for Quantized Neural Networks on FPGAs
Quality Driven Dynamic Low Power Reconfiguration of Handhelds
A Parallel Version of the Itoh-Tsujii Multiplicative Inversion Algorithm
ReM: A Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures
A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms
An Embedded Multi-camera System for Simultaneous Localization and Mapping
LiDAR 3D Object Detection in FPGA with Low Bitwidth Quantization
Task-Based Programming Models for Heterogeneous Recurrent Workloads
Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor