yusuke1997/dblp-id-title huggingface dataset:
Quantum Noise in the Flow of Time: A Temporal Study of the Noise in Quantum Computers
Scan Design and Secure Chip
Towards The Methodology of On-line Diagnosis
Designing dependable multicore system with unreliable components
A Low-Cost Soft Error Tolerant Read Circuit for Single/Multi-Level Cross-Point RRAM Arrays
Surviving to Errors in Multi-Core Environments
BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs
Performances VS Reliability: how to exploit Approximate Computing for Safety-Critical applications
Predictive error detection by on-line aging monitoring
SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping
Rise of the hardware Trojans
Validation of a Software Dependability Tool via Fault Injection Experiments
Evaluating ECC for Cache Reliability Under Multi-Bit Upsets: A Design Space Exploration
An Improved Technique for Reducing False Alarms Due to Soft Errors
A placement strategy for reducing the effects of multiple faults in digital circuits
Cross-layer early reliability evaluation: Challenges and promises
Adaptive IDDQ: How to Set an IDDQ Limit for any Device Under Test
Fault injection-based evaluation of a synchronous NoC router
15th IEEE International On-Line Testing Symposium (IOLTS 2009), 24-26 June 2009, Sesimbra-Lisbon, Portugal
Dynamic aging compensation and Safety measures in Automotive environment
In-depth analysis of digital circuits against soft errors for selective hardening
An effective fast and small-area parallel-pipeline architecture for OTM-convolutional encoders
TAURUM P2T: Advanced Secure CAN-FD Architecture for Road Vehicle
Permanent faults on LIN networks: On-line test generation
Revisiting software-based soft error mitigation techniques via accurate error generation and propagation models
Efficient on-line fault-tolerance for the preconditioned conjugate gradient method
Minimization of Timing Failures in Pipelined Designs via Path Shaping and Operand Truncation
Test and reliability concerns for 3D-ICs
Dose Effects and Mitigation in 28nm FD-SOI Advanced Interface Bus Chiplet Interconnect
Error detection and correction of single event upset (SEU) tolerant latch
Modeling and Simulation of Time Domain Faults in Digital Systems
SICTA: A superimposed in-circuit fault tolerant architecture for SRAM-based FPGAs
Radiation-induced Effects on DMA Data Transfer in Reconfigurable Devices
Automatic generation of stimuli for fault diagnosis in IEEE 1687 networks
Recovery of performance degradation in defective branch target buffers
Towards functional-safe timing-dependable real-time architectures
Flip-flop SEU reduction through minimization of the temporal vulnerability factor (TVF)
A Radiation Tolerant 10/100 Ethernet Transceiver for Space Applications
ICE-RADAR: In-situ, Cost-Effective Razor Flip-Flop Deployment for Aging Resilience
The future of fault tolerant computing
PLL Over-Clocking Through Repeated Fault Injections
Foundation of Combined Datapath and Controller Self-checking Design
A method for detecting resistive opens in buses
Verification and Analysis of Self-Checking Properties through ATPG
An Improved CMOS BICS for On-Line Testing
Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness
Accumulator based Test-per-Scan BIST
Soft error correction in embedded storage elements
Towards AI-Enabled Hardware Security: Challenges and Opportunities
Power-aware optimization of software-based self-test for L1 caches in microprocessors
A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits
A New Self-Checking and Code-Disjoint Non-Restoring Array Divider
Robust co-synthesis of embedded control systems with occasional deadline misses
Securing the Control of Digital Beamforming
Pilot symbol driven monitoring of electrical degradation in RF transmitter systems using model anomaly diagnosis
Investigation of critical path selection for in-situ monitors insertion
TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture
A Test Sensitization State Compaction Method on Controller Augmentation
A fast error correction technique for matrix multiplication algorithms
STT-MTJ-based TRNG with on-the-fly temperature/current variation compensation
Trustworthy computing in a multi-core system using distributed scheduling
Accelerating post silicon debug of deep electrical faults
ML-Based Online Design Error Localization for RISC-V Implementations
New byte error correcting codes with simple decoding for reliable cache design
Efficient Estimation of SEU Effects in SRAM-Based FPGAs
A COTS Wrapping Toolkit for Fault Tolerant Applications under Windows NT
Online error detection in multiprocessor chips: A test scheduling study
On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors
Designing FPGA based Self-Testing Checkers for m-out-of-n Codes
A generic platform for remote accelerated tests and high altitude SEU experiments on advanced ICs: Correlation with MUSCA SEP3 calculations
Design Tradeoffs in Bioimplantable Devices: A Case Study with Bladder Pressure Monitoring
An on-line memory state validation using shadow memory cloning
Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?
Localization of Faults in Radix-n Signed Digit Adders
Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation
Punctured Karpovsky-Taubin binary robust error detecting codes for cryptographic devices
REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture
12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy
Bit Flip Injection in Processor-Based Architectures: A Case Study
Wavelet analysis of measurements for on-line testing analog & mixed-signal circuits
Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates
On-Line Testing of Globally Asynchronous Circuits
SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations
Fault Tolerant Reversible Finite Field Arithmetic Circuits
Activity profiling: Review of different solutions to develop reliable and performant design
A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors
Towards Semantic Coherence: Understanding Cybersecurity and Digital Sovereignty in the Automotive Landscape
A Suitability Analysis of Software Based Testing Strategies for the On-line Testing of Artificial Neural Networks Applications in Embedded Devices
Detecting and Resolving Security Violations in Reconfigurable Scan Networks
Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits
Run-time Detection and Mitigation of Power-Noise Viruses
Fault Tolerance in Quantized and Pruned Convolutional Neural Networks
Side-Channel Attack with Fault Analysis on Memristor-based Computation-in-Memory
Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC
Self-Testing of FPGA Delay Faults in the System Environment
Reducing the area overhead of TMR-systems by protecting specific signals
SBST for on-line detection of hard faults in multiprocessor applications under energy constraints
TrISec: Training Data-Unaware Imperceptible Security Attacks on Deep Neural Networks
Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs
Modeling Clock Glitch Fault Injection Effects on a RISC-V Microcontroller
Accurate Analysis of Silent Data Corruptions in Programmable AI Accelerator Microarchitectures
Radiation test methodology for SRAM-based FPGAs by using THESIC
Yield Improvement, Fault-Tolerance to the Rescue?
On the Development of Prognostics and System Health Management (PHM) Techniques for ReRAM Applications
A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification
Trend in DRAM Soft Errors
Applicability of Energy Efficient Coding Methodology to Address Signal Integrity in 3D NoC Fabrics
Evaluation on Hardware-Trojan Detection at Gate-Level IP Cores Utilizing Machine Learning Methods
Power-side-channel analysis of carbon nanotube FET based design
Deterministic network on chip for deploying real time applications on many-core processors
Cache timing attacks countermeasures and error detection in Euclidean addition chains based scalar multiplication algorithm for elliptic curves
Workload characterization and prediction: A pathway to reliable multi-core systems
14th IEEE International On-Line Testing Symposium (IOLTS 2008), 7-9 July 2008, Rhodes, Greece
Real-Time Fault Analysis in RISC-V Processors: A Case Study Using the Internal State Monitor
In-Circuit Mitigation Approach of Single Event Transients for 45nm Flip-Flops
An effective functional safety infrastructure for system-on-chips
A New Radiation Hardened by Design Latch for Ultra-Deep-Sub-Micron Technologies
Using a WLFSR to Embed Test Pattern Pairs in Minimum Time
C-testable S-box implementation for secure advanced encryption standard
Do Radiation and Aging Impact DVFS? TCAD-based Analysis on 22 nm FDSOI Latches
At-speed BIST for interposer wires supporting on-the-spot diagnosis
AI-Based Classification of Adversarial Attacks vs. Hardware Fault Corruptions in the Split Computing Context
Analyzing the Effectiveness of Fault Hardening Procedures
EISFINN: On the Role of Efficient Importance Sampling in Fault Injection Campaigns for Neural Network Robustness Analysis
Can social media shape the security of next-generation connected vehicles?
Side-Channel Issues for Designing Secure Hardware Implementations
Deterministic Built-in TPG with Segmented FSMs
A software-based self-test methodology for in-system testing of processor cache tag arrays
Efficient fault tolerant parallel matrix-vector multiplications
A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies
On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs
LIN-MM: Multiplexed Message Authentication Code for Local Interconnect Network message authentication in road vehicles
An Hybrid Architecture for consolidating mixed criticality applications on multicore systems
The cost of cryptography: Is low budget possible?
Extending Moore's Law into the next Decade - the SER Challenge
Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms
23rd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2017, Thessaloniki, Greece, July 3-5, 2017
Understanding the Impact of Cutting in Quantum Circuits Reliability to Transient Faults
Basic Architecture for Logic Self Repair
Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode
On-Chip SRAM Disclosure Attack Prevention Technique for SoC
Experimental Evaluation of Delayed-Based Detectors Against Power-off Attack
On Post-Quantum Attribute-Based Encryption for Automotive Over-the-Air Software Updates
Fault-Robust Microcontrollers for Automotive Applications
Laser fault injection into SRAM cells: Picosecond versus nanosecond pulses
Selecting state variables for improved on-line testability through output response comparison of identical circuits
Diagnosis with transition faults on embedded segments
ISIS: A Fail-Safe Interface Realized in Smart Power Technology
Radiation Hardness Evaluations of a Stacked Flip Flop in a 22 nm FD-SOI Process by Heavy-Ion Irradiation
A New Laser System for X-Rays Flashes Sensitivity Evaluation
Refinement and Empirical Side-Channel Analysis of Inner Product Masking with Robust Error Detection
Evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations
Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation
Soft Error Resilient Deep Learning Systems Using Neuron Gradient Statistics
Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement
Evaluating a low cost robustness improvement in SRAM-based FPGAs
On-Line Self-Healing of Circuits Implemented on Reconfigurable FPGAs
On Realization of Fault-Tolerant Fuzzy Controllers
Managing SER costs of complex systems through Linear Programming
An on-line test solution for addressing interconnect shorts in on-chip networks
An Architecture for Self-Healing Digital Systems
Error detection encoding for multi-threshold capture mechanism
Transparent BIST for ECC-based memory repair
On Evaluating Test Response Obfuscation and Encryption Countermeasures
Comprehensive analysis of sequential circuits vulnerability to transient faults using SMT
Analytical Redundancy Based Approach for Concurrent Fault Detection in Linear Digital Systems
A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations
Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift
Power/Area-Optimized Fault Tolerance for Safety Critical Applications
Power Attacks on Secure Hardware Based on Early Propagation of Data
Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower α-SER in a 130 nm Bulk Process
Directed Random SBST Generation for On-Line Testing of Pipelined Processors
SEU sensitivity of robust communication protocols
Secure Scan Techniques: A Comparison
Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems
A Modulo p Checked Self-Checking Carry Select Adder
Algebraic manipulation detection codes and their applications for design of secure cryptographic devices
Selective Fault Tolerance by Counting Gates with Controlling Value
Self-Configuration and Reachability Metrics in Massively Defective Multiport Chips
Navigating the road to automotive cybersecurity compliance
Memory Built-In Self-Repair for Nanotechnologies
Evaluation and Mitigation of Faults Affecting Swin Transformers
Using test infrastructures for (remote) online evaluation of the sensitivity to SEUs of FPGAs
Automatic Fault Simulators for Diagnosis of Analog Systems
On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs
Reduced-Precision DWC for Mixed-Precision GPUs
An soft error propagation analysis considering logical masking effect on re-convergent path
A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems
OPUF: Obfuscation logic based physical unclonable function
FF-DICE: An 8T soft-error tolerant cell using Independent Dual Gate SOI FinFETs
Exploiting a fast and simple ECC for scaling supply voltage in level-1 caches
On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring
BIST-Based Delay-Fault Testing in FPGAs
Fault Injection in Digital Logic Circuits at the VHDL Level
Binary decision diagram to design balanced secure logic styles
Fault Modeling and Simulation of Memristor based Gas Sensors
Video decoder monitoring using non-linear regression
Budget-Dependent Control-Flow Error Detection
Soft Error Rates of Hardened Sequentials utilizing Local Redundancy
Analysis of Bit Transition Count for EDAC Encoded FSM
Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes
Soft Errors: Technology Trends, System Effects, and Protection Techniques
On the Proposition of an EMI-Based Fault Injection Approach
QuSecNets: Quantization-based Defense Mechanism for Securing Deep Neural Network against Adversarial Attacks
Using Concurrent and Semi-Concurrent On-Line Testing During HLS: An Adaptable Approach
Handling of permanent faults in dynamically scheduled processors
Mixed-Signal Circuit Classification in a Pseudorandom Testing Scheme
Bayesian network early reliability evaluation analysis for both permanent and transient faults
Concurrent Scan Monitoring and Multi-Pattern Search
Reducing DUE-FIT of caches by exploiting acoustic wave detectors for error recovery
Novel Process and Temperature-Stable BICS for Embedded Analog and Mixed-Signal Test
Integrating BIST Techniques for On-Line SoC Testing
Leveraging Open-Source Bitstream Documentation for FPGA Soft-Error Robustness Analysis
Ef 3 S: An evaluation framework for flash-based systems
On Using Deterministic Test Sets in BIST
Experimental evaluation of GPUs radiation sensitivity and algorithm-based fault tolerance efficiency
How to Cope with SEU/SET at System Level?
When processors get old: Evaluation of BTI and HCI effects on performance and reliability
Addressing Soft Error and Security Threats in DNNs Using Learning Driven Algorithmic Checks
A New Reseeding Technique for LFSR-Based Test Pattern Generation
Low-power memory repair for high defect densities
A Built-In Self-Test Scheme for Soft Error Rate Characterization
Customized cell detector for laser-induced-fault detection
Survivable Discrete Circuits Design
Neutron Beam Evaluation of Probabilistic Data Structure-based Online Checkers
On-Line Testing in Continuous Operation of Embedded Systems: Modeling and Performance Evaluation
NAPER: Fault Protection for Real-Time Resource-Constrained Deep Neural Networks
Characterization and Modeling of SET Generation Effects in CMOS Standard Logic Cells
IEEE Computer Society TTTC: Test Technology Technical Council
High-level Intellectual Property Obfuscation via Decoy Constants
Artificial Neural Network Accelerator for Classification of In-Field Conducted Noise in Integrated Circuits' DC Power Lines
A novel radiation tolerant SRAM design based on synergetic functional component separation for nanoscale CMOS
GRAAL: A Fault-Tolerant Architecture for Enabling Nanometric Technologies
LFSR Reseeding with Irreducible Polynomials
A noise-tolerant master-slave flip-flop
Single-event performance of differential flip-flop designs and hardening implication
Towards low-cost fault detection strategy of FPGA configuration memory in real-time systems
Strategic Use of SEE Mitigation Techniques for the Development of the ESA Microprocessors: Past, Present and Future
Compressed Learning in MCA Architectures to Tolerate Malicious Noise
On-Chip Delay Measurement for Degradation Detection And Its Evaluation under Accelerated Life Test
Increasing the Fault Coverage in Multiple Clock Domain Systems by Using On-Line Testing of Synchronizers
Automating wafer-level test of uncooled infrared detectors using wafer-prober
Self-Healing Imager Based on Detection and Conciliation of Defective Pixels
21st IEEE International On-Line Testing Symposium, IOLTS 2015, Halkidiki, Greece, July 6-8, 2015
Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip
A Configurable Built in Current Sensor for Mixed Signal Circuit Testing
Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study
Reduced Fault Coverage as a Target for Design Scaffolding Security
A Methodology for Test Replacement Solutions of Obsolete Processors
Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOS
Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers
9th IEEE International On-Line Testing Symposium (IOLTS 2003), 7-9 July 2003, Kos Island, Greece
Diophantine-Equation Based Arithmetic Test Set Embedding
A Watchdog Processor to Detect Data and Control Flow Errors
Structural Test Generation for AI Accelerators using Neural Twins
FPGA Checkpointing for Scientific Computing
Reliability And Performance Challenges Of Ultra-Low Voltage Caches: A Trade-Off Analysis
Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture
Error resilient video encoding using Block-Frame Checksums
BALoo: First and Efficient Countermeasure Dedicated to Persistent Fault Attacks
Weighted logic locking: A new approach for IC piracy protection
Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor
Modeling of Transients Caused by a Laser Attack on Smart Cards
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD
Transient Fault Emulation of Hardened Circuits in FPGA Platforms
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders
Scanning the strength of a test signal to monitor electrode degradation within bio-fluidic microsystems
Total Ionizing Dose Effects by alpha irradiation on circuit performance and SEU tolerance in thin BOX FDSOI process
Hot-carrier and BTI damage distinction for high performance digital application in 28nm FDSOI and 28nm LP CMOS nodes
Built-in Generation of m -Sequences with Irreducible Characteristic Polynomials
Preliminary results of SEU fault-injection on multicore processors in AMP mode
Supporting Fault Tolerance in an Industrial Environment: The AMATISTA Approach
On comparison of robust configurable FPGA encoders for dependable industrial communication systems
Modeling Soft-Error Susceptibility for IP Blocks
Reliability Challenges with Self-Heating and Aging in FinFET Technology
A new framework for the automatic insertion of mitigation structures in circuits netlists
SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation
Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs
6T CMOS SRAMs reliability monitoring through stability measurements
Designing fault tolerant FSM by nano-PLA
Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systems
Self-Checking FSM Design with Observing only FSM Outputs
Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours
Versatile architecture-level fault injection framework for reliability evaluation: A first report
On the testing of special memories in GPGPUs
Unsupervised Recycled FPGA Detection Based on Direct Density Ratio Estimation
On the robustness of DCT-based compression algorithms for space applications
Design of a Self Checking Reed Solomon Encoder
To Detect or to Correct?
Software Self-Testing of a Symmetric Cipher with Error Detection Capability
Early assessment of SEU sensitivity through untestable fault identification
Exploiting embedded FPGA in on-line software-based test strategies for microprocessor cores
Increasing Implementability of beta-driven Threshold Checkers
ACM: Accurate crosstalk modeling to predict channel delay in Network-on-Chips
Accelerating Soft Error Rate Testing Through Pattern Selection
Fault Diagnosis in ReCAM Arrays
Leveraging Image-Based Transformations to Mitigate Adversarial Attacks in AI-Based Safety-Critical Systems
Fault-based reliable design-on-upper-bound of electronic systems for terrestrial radiation including muons, electrons, protons and low energy neutrons
Power Cycling Body Diode Current Flow on SiC MOSFET Device
Broadside ATPG for Low Power Trojans Detection using Built-in Current Sensors
Improving On-Line BIST-Based Diagnosis for Roving STARs
An Overview of the Applications of a Pulsed Laser System for SEU Testing
Storage Based Built-In Test Pattern Generation Method for Close-to-Functional Broadside Tests
Online monitoring of the maximum angle error in AMR sensors
Impact of a Laser Pulse on a STT-MRAM Bitcell: Security and Reliability Issues
Impact of Aging on Soft Error Susceptibility in CMOS Circuits
A methodology for measuring transistor ageing effects towards accurate reliability simulation
Fault Tolerant Automotive Systems: An Overview
Representing Gate-Level SET Faults by Multiple SEU Faults at RTL
A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs
TIMA-PUF: Time Measurement Based Arbiter PUF
Nonlinear compression functions using the MISR approach for security purposes in automotive applications
Towards Trojan circuit detection with maximum state transition exploration
SCARF: Detecting Side-Channel Attacks at Real-time using Low-level Hardware Features
An efficient LDPC encoder architecture for space applications
Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems
Stuck-at-OFF Fault Analysis in Memristor-Based Architecture for Synchronization
Evaluation of machine learning algorithms for image quality assessment
Concurrent checking with split-parity codes
Robust Adaptive Read Scheme for 7nm Configuration SRAMs
Soft Error Rates in 65nm SRAMs--Analysis of new Phenomena