yusuke1997/dblp-id-title huggingface dataset:
An Approach using transformer architecture for emotion recognition through Electrocardiogram Signal(s)
A benchmarking study of deep learning techniques applied for breath analysis
EDGE Q 5G with an EDGE
Cerebras Architecture Deep Dive: First Look Inside the HW/SW Co-Design for Deep Learning : Cerebras Systems
Inuitive breakthrough solution for AR and VR worlds
Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET)
Design challenges in building an advanced NAND flash array controller for 19/20 nm MLC
2010 IEEE Hot Chips 22 Symposium, Stanford, CA, USA, August 22-24, 2010
Design of a high-density SoC FPGA at 20nm
Hardware-level thread migration in a 110-core shared-memory multiprocessor
Efficient, precise-restartable program execution on future multicores
Samsung PIM/PNM for Transfmer Based AI : Energy Efficiency on PIM/PNM Cluster
POWER8
The APP300 access network processor
ENABLING AI Infrastructure : Tomahawk Ultra - Ultra Low Latency, High Bandwidth Ethernet Switch for HPC & AI/ML applications
SPARC64™ X+: Fujitsu's next generation processor for UNIX servers
"Jaguar" AMD's next generation low power x86 core
NAND technology
Sapphire Rapids
Ouroboros: An Inference Engine for Deep Learning Based TTS on Embedded Devices
Introducing 28-nm stratix VFPGAs: Built for bandwidth
4 Tb/s Optical Compute Interconnect Chiplet for XPU-to-XPU Connectivity
A 1.19GHz 9.52Gsamples/sec Radix-8 FFT Hardware Accelerator in 28nm
The surround computing ERA
Khronos and the OpenCL standard
PEZY-SC4s : The Fourth Generation MIMD Many-core Processor with High Energy Efficiency and Flexibility for HPC and AI Applications
Xilinx Zynq-7000 EPP: An extensible processing platform family
A Scalable Bayesian Inference Accelerator for Unsupervised Learning
Xilinx Edge Processors
The new Xbox 360 250GB CPU GPU SoC
In silico vox: Towards speech recognition in silicon
ARM996HS™ the first licensable, clockless 32-bit processor core
The tulsa processor: A dual core large shared-cache Intel® Xeon processor 7000 sequence for the MP server market segment
XMOS architecture XS1 chips
SX-ACE processor: NEC's brand-new vector processor
Maker trends: The path of least resistance
Tutorial #1: Modern system interconnects
Managing the evolution of flash: beyond memory to storage
Myriad 2: Eye of the computational vision storm
The future of graphic and mobile memory for new applications
A 7-nm FinFET 1.2-TB/s/mm 2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers
Mobile 3D capture for professional applications
DaVinci: A Scalable Architecture for Neural Network Computing
A dynamically scheduled architecture for the synthesis of graph methods
POWER7: IBM's next generation server processor
Bit-Separable Transformer Accelerator Leveraging Output Activation Sparsity for Efficient DRAM Access
Mobile hardware security
HBM: Memory solution for bandwidth-hungry processors
M7: Next generation SPARC
AMD Ryzen ™ 7040 Series: Technology Overview
PNNPU: A Fast and Efficient 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access
RayChip®: Real-time ray-tracing chip for embedded applications
OmniDRL: An Energy-Efficient Mobile Deep Reinforcement Learning Accelerators with Dual-mode Weight Compression and Direct Processing of Compressed Data
Low-power, high-performance architecture of the PWRficient processor family
Driving Compute Scale-out Performance with Optical I/O Chiplets in Advanced System-in-Package Platforms
Supercharged AI Inference on Modern CPUs
Challenges of building personal robots
KLIMA: Low-latency mixed-signal In-Memory Computing accelerator for solving arbitrary-order Boolean Satisfiability
Software in Silicon in the Oracle SPARC M7 processor
Lakefield: Hybrid cores in 3D Package
Cool codes for hot chips: A quantitative basis for multi-core design
Alder Lake Architecture
Intel Agilex® 9 Direct RF-Series FPGAs with Integrated 64 Gsps Data Converters
Jintide®: A Hardware Security Enhanced Server CPU with Xeon® Cores under Runtime Surveillance by an In-Package Dynamically Reconfigurable Processor
36th IEEE Hot Chips Symposium, HCS 2024, Stanford, CA, USA, August 25-27, 2024
SDA: Software-defined accelerator for large-scale DNN systems
Xilinx Versal™ Premium
From model to FPGA: Software-hardware co-design for efficient neural network acceleration
Mozart: Designing for Software Maturity and the Next Paradigm for Chip Architectures
2022 IEEE Hot Chips 34 Symposium, HCS 2022, Cupertino, CA, USA, August 21-23, 2022
IEEE Hot Chips 33 Symposium, HCS 2021, Palo Alto, CA, USA, August 22-24, 2021
High-performance power-efficient x86-64 server and desktop processors using the core codenamed "Bulldozer"
Reducing transistor variability for high performance low power chips
Rethinking algorithms for future architectures: Communication-avoiding algorithms
Intel® Xeon® Processor D: The First Xeon processor optimized for dense solutions
Wireless in the home - opportunities and challenges
Specialized IC for World-Lock Rendering in Augmented and Mixed Reality Devices
An AI Compute ASIC with Optical Attach to Enable Next Generation Scale-Up Architectures
Towards optimal custom instruction processors
Silicon photonics and memories
A Smart Cache for a SmartNIC! Scaling End-Host Networking to 400Gbps and Beyond
The path to embedded vision & AI using a low power vision DSP
A new ×86 core architecture for the next generation of computing
A 50% lower power ARM Cortex CPU using DDC technology with body bias
Architecting for Flexibility and Value with Next Gen Intel® Xeon® Processors
Intel® QuickPath interconnect overview
Moffett Antoum ® : A Deep-Sparse AI Inference System-on-Chip for Vision and Large-language Models
AppliedMicro X-Gene2
An implementation of hardware accelerator using dynamically reconfigurable architecture
HW acceleration for volumetric applications
ThunderX3 Next-Generation Arm-Based Server
Deep Learning Training At Scale Spring Crest Deep Learning Accelerator (Intel® Nervana™ NNP-T)
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking
A Massive-Scale Brain Activity Decoding Chip
The model is not enough: Understanding energy consumption in mobile devices
Hanguang 800 NPU - The Ultimate AI Inference Solution for Data Centers
Dimensity 9000 - A Flagship Smartphone SoC
AMD Next-Generation FPGA Built from Chiplets
Built for the Edge: The Intel® Xeon® 6 SoC
Introducing "parker": Next-generation tegra system-on-chip
Energy efficient graphics and multimedia in 28NM Carrizo APU
Ultra-low-light CMOS biosensor helps tackle infectious diseases
HSAIL: Portable compiler IR for HSA
Solving 4G challenges for pico, micro and macrocell platforms
Arm Neoverse V2 platform: Leadership Performance and Power Efficiency for Next-Generation Cloud Computing, ML and HPC Workloads
Inside Intel® Core microarchitecture
Presto: A Unified RISC-V-Compatible SoC for Multi-Scheme FHE Acceleration over Module Lattice
Inside the Cerebras Wafer-Scale Cluster: Cerebras Systems
Hot Chips: Stacking tutorial
Hardware-accelerated text analytics
High Performance Low Power Controller for Data Center SSDs
Memory: Almost The Only Thing That Matters : A revolution in memory architecture for the data center
Sustainable Computing for AI & Cloud Native Workloads
World Largest Mobile Image Sensor with All Directional Phase Detection Auto Focus Function
Qualocmm® Hexagon™ NPU
IRIS: A 8.55 mJ/frame Spatial Computing SoC for Real-time Interactable-Rendering and Surface-aware-Modeling with 3D Gaussian Splatting
SPARC64™ XIfx: Fujitsu's next generation processor for HPC
"Overview of short-reach optical interconnects: From VCSELs to silicon nanophotonics"
The IBM z15 processor chip set
Quantum dot based imagers for multispectral cameras and sensors
Low-power high-density 10GBASE-T ethernet transceiver
Qualcomm Oryon™ CPU
Photonics and future datacenter networks
Storage class memory: Technology, systems and applications
4th generation Intel TM Core processor, codenamed Haswell
Universal parallel computing research center at Illinois
Power management challenges in wireless WAN SoCs
Baidu Kunlun An AI processor for diversified workloads
Applying AMD's Kaveri APU for heterogeneous computing
2009: The GPU computing tipping point
40Gb/s optical active cable using monolithic transceivers implemented in silicon photonics enabled 0.13-µm SOI CMOS Technology
Xilinx First 7nm Device: Versal AI Core (VC1902)
ProAptiv: Efficient performance on a fully-synthesizable core
The inevitable rise of NVM in computing
壁仞™ BR100 GPGPU: Accelerating Datacenter Scale AI Computing
High-level synthesis of memory bound and irregular parallel applications with Bambu
OMAP4430 architecture and development
Cloud transforms it Big Data transforms business
Performance characteristics of the POWER8 processor
The Cavium 32 Core OCTEON II 68xx
Newest additions to Altera's integrated transceiver portfolio
The bifrost GPU architecture and the ARM Mali-G71 GPU
Untether Ai : Boqueria
Flash trends: Challenges and future
Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure
5th generation touchscreen controller for mobile phones and tablets
Dataflow architectures for 10Gbps line-rate key-value-stores
Power constraints: From sensors to servers
Secure systems design
A low-power and real-time augmented reality processor for the next generation smart glasses
3D sensors for the rest of us
28nm generation programmable families
Micro manipulator array for nano-bioelectronics era
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner
Precision refinement for media-processor SoCs: fp32 -> fp64 on myriad
Meteor Lake and Arrow Lake Intel Next-Gen 3D Client Architecture Platform with Foveros
I/O virtualization and system acceleration in POWER8
Memory as we approach a new horizon
An Efficient High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient Cache
Goldstrike 1: Cointerra's first generation crypto-currency processor for bitcoin mining machines
Technology scaling at an inflection point what's next?
Ultra-low power wireless SoCs enabling a batteryless IoT
Samsung Neural Processing Unit : An AI accelerator and SDK for flagship mobile AP
GreenDroid: A mobile application processor for a future of dark silicon
Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs
2013 IEEE Hot Chips 25 Symposium (HCS), Stanford University, CA, USA, August 25-27, 2013
4th Gen AMD CDNA TM Generative AI Architecture Powering AMD Instinct M350 Series GPUs and Platforms
Intel Gaudi 3 AI Accelerator: Architected for Gen AI Training and Inference
Accelerating Graphic Rendering on Programmable RISC-V GPUs
An intelligent ADAS processor with real-time semi-global matching and intention prediction for 720p stereo vision
A 4.69mW LLM Processor with Binary/Ternary Weights for Billion-Parameter Llama Model
XiangShan: An Open-Source Project for High-Performance RISC-V Processors Meeting Industrial-Grade Standards
Bridge chip composing a PCIe switch over ethernet to make a seamless disaggregated computer in data-center scale
SOT-MRAM - Third generation MRAM memory opens new opportunities : Hot Chips Conference August 2021
Exploring manycore multinode systems for irregular applications with FPGA prototyping
High performance DSP for vision, imaging and neural networks
NFP-6xxx - a 22nm high-performance network flow processor for 200Gb/s Software Defined Networking
10G | 5G | 2.5G | 1G | 100M physical layer PHY: HOT CHIPS 2015 conference
MvEcho
Memory technology and applications
Heterogenous Integration Enables FPGA Based Hardware Acceleration for RF Applications
Silicon photonics: Optical connectivity at 25 Gbps and beyond
VR and AR anytime and everywhere: Contributions of PMD depth sensing to an evolving ecosystem
The OpenCL specification
LightTrader : World's first AI-enabled High-Frequency Trading Solution with 16 TFLOPS / 64 TOPS Deep Learning Inference Accelerators
Ivybridge server architecture: A converged server
HSA queueing
A Low-Power Large-Language-Model Processor with Big-Little Network and Implicit-Weight-Generation for On-Device AI
From High-Level Frameworks to custom Silicon with SODA
"Bobcat" AMD's new low power x86 core architecture
Qualcomm ® Cloud Al 100 : 12TOPS/W Scalable, High Performance and Low Latency Deep Learning Inference Accelerator
Transitioning the Intel® next generation microarchitectures (nehalem and westmere) into the mainstream
Blade computing with the AMD Opteron™ processor ("magny-cours")
Intel Tofino2 - A 12.9Tbps P4-Programmable Ethernet Switch
IEEE Hot Chips 37 Symposium, HCS 2025, Stanford, CA, USA, August 24-26, 2025
Intel C2000 atom microserver power efficient processing for the data center
ArcSoft multi-frame technologies
Smart memory
Z-RAM® ultra-dense memory for 90nm and below
Intel® Energy Efficiency Architecture
The era of high bandwidth memory
NeCTAr and RASoC: Tale of Two Class SoCs for Language Model Interference and Robotics in Intel 16
Who owns the living room?
Forging a future in memory: New technologies, new markets, new applications
Reconfigure your RTL with EFLX join the SoC revolution
LS2085/8A Freescale's new QorlQ Layerscape communications processor
Tesla Transport Protocol Over Ethernet (TTPoE): A New Lossy, Exa-Scale Fabric for the Dojo AI Supercomputer
Spring Hill (NNP-I 1000) Intel's Data Center Inference Chip
Intel's Ponte Vecchio GPU : Architecture, Systems & Software
Extensions to the ARMv7-A architecture
The Next Generation of High Performance, Energy-Efficient Computing: Intel® Xeon® Processors Built on Efficient-Core
The ultra small HDD for the mobile applications
ConnectX-8 SuperNIC
HyperTransport™ technology tutorial
SPARC64™ X: Fujitsu's new generation 16 core processor for the next generation UNIX servers
AMD Pensando TM Pollara 400 AI NIC Architecture and Application
Main SoC and XBOX one kinect
35th IEEE Hot Chips Symposium, HCS 2023, Palo Alto, CA, USA, August 27-29, 2023
CSS N2: Arm Neoverse N2 Platform, Delivered to Partners as a Fully Verified, Customizable Subsystem
NMI: A new memory interface to enable innovation
Photonic Interconnect for Accelerated Computing Celestial AI Photonic Fabric Module - The world's first SoC with in-die Optical IO
AMD "ZEN 2"
Atom™ - x5/x7 Series processor, codenamed Cherry Trail
Status and prospect for MRAM technology
AMD Next Generation 7NM Ryzen™ 4000 APU "Renoir"
AMD and OpenCL
Welcome to Hot Chips 24
Inside Maia 100
Heterogeneous computing to enable highest level of safety
A UCIe Optical I/O Retimer Chiplet for AI Scale-up
Being in the moment with Google glass
Xuantie-910: Innovating Cloud and Edge Computing by RISC-V
Lagopus FPGA - A reprogrammable data plane for high-performance software SDN switches
Implementing software defined radio on the paralella
Large-scale Graph Neural Network Services through Computational SSD and In-Storage Processing Architectures
X-Gene™: 64-bit ARM CPU and SoC
Inside 6th gen Intel ® Core™: New microarchitecture code named skylake
Spidergon STNoC: The technology that adds value to your System
Delivering the full potential of PCIe storage
Xilinx SSI technology concept to silicon development overview
NVIDIA ORIN System-On-Chip
Knights landing (KNL): 2nd Generation Intel® Xeon Phi processor
SPARC T5: 16-core CMT processor with glueless 1-hop scaling to 8-sockets
Trinity: End-to-End In-Database Near-Data Machine Learning Acceleration Platform for Advanced Data Analytics
The First Direct Mesh-to-Mesh Photonic Fabric
Electrons, photons, phonons, wave, bits, and industrial design: Microsoft kinect sensor: Hot chips 23
Intel's digital random number generator (DRNG)
Space-Mate: A 303.5mW Real-Time NeRF SLAM Processor with Sparse-Mixture-of-Experts-based Acceleration
Skydio Autonomy Engine: Enabling The Next Generation Of Autonomous Flight
POWER7: IBM's next generation, balanced POWER server chip
High performance State Retention with Power Gating applied to CPU subsystems - design approaches and silicon evaluation
"Bulldozer" a new approach to mult ithreaded compute performance
IBM's POWER10 Processor
HBM package integration: Technology trends, challenges and applications
Level-3 BLAS on myriad multi-core media-processor SoC
Microprocessors for roots-of-trust
Tessellation operating system: Building a real-time, responsive, high-throughput client OS for many-core architectures
IBM Telum ® II Processor and IBM Spyre ™ Accelerator Chip for AI
The AMD Opteron™ CMP NorthBridge architecture: Now and in the future
Passive dense stereo vision on the Myriad2 VPU
SM6: A 16nm System-on-Chip for Accurate and Noise-Robust Attention-Based NLP Applications : The 33 rd Hot Chips Symposium - August 22-24, 2021
ADI's revolutionary BF60x vision focused digital signal processor system on chip: 25 billion operations/sec @ 80 mW and zero bandwidth
The ARM® Mali-T880 Mobile GPU
SoC for car navigation systems with a 53.3 GOPS image recognition engine
Search by sight: Google™ goggles
The use and abuse of patents in the semiconductor industry
IBM zNext - the 3rd generation high frequency microprocessor chip
HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces
Rainbow falls sun's next generation CMT processor
Samsung exynos M1 processor
Blackhole & TT-Metalium: The Standalone AI Computer and its Programming Model
SOC programming tutorial
Efficient fetch mechanism by employing instruction register
Quantum Computing with Atoms
AMD RDNA 4 Radeon 9000 Series GPU
Deep learning & convolutional networks
Demonstration of a high speed 4-channel integrated silicon photonics WDM link with hybrid silicon lasers
Facebook: Efficient power distribution: 277Vac distribution w/o centralized UPS 95% high efficiency solution battery cabinet as distributed backup energy unit
IBM NorthPole Neural Inference Machine
Centip3De: A 64-core, 3D stacked, near-threshold system
Memory-Centric Computing with SK Hynix's Domain-Specific Memory
Fast storage for big data - tutorial 2 implications of using flash devices in an enterprise storage server
Flash adoption in the enterprise
Design of a low power SoC testchip for wearables and IoTs
High Density Si-IPD Technologies as Enabler for High-Performance and Low-Power Consumption Processor Chips
Going to the wire: The next generation financial risk management platform
Visconti2 - a heterogeneous multi-core SoC for image-recognition applications
2nd Generation Intel® Core Processor Family: Intel® Core i7, i5 and i3
Welcome to 2016 Hot Chips
Silicon Photonics for Artificial Intelligence Acceleration : HotChips 32
CORSAIR:An In-Memory Computing ChipletArchitecture for Inference-Time Compute Acceleration
Multi-Million Core, Multi-Wafer AI Cluster
Vision Perception Unit: Next-Generation Smart CMOS Image Sensor
The MIPS32® 34K processor: Ultimate design flexibility for embedded applications
High-efficient architecture of Godson-T many-core processor
FPGAs with 28Gb/s transceivers built with heterogeneous stacked-silicon interconnects
A Programmable Embedded Microprocessor for Bit-scalable In-memory Computing
Intel® Xeon Phi coprocessor (codename Knights Corner)
Facebook: The open compute project
The IBM POWER7 HUB module: A terabyte interconnect switch for high-performance computer systems
A Trusted Execution Environment RISC-V System on Chip
AMD Instinct MI300X Generative AI Accelerator and Platform Architecture
University research in hardware security
Practical power gating and dynamic voltage/frequency scaling
ARM processor evolution: Bringing high performance to mobile devices
The CA1024: A fully programmable system-on-chip for costeffective HDTV media processing
NeuGPU: A Neural Graphics Processing Unit for Instant Modeling and Real-Time Rendering on Mobile AR/VR Devices
Intel ® IPU E2200: Second Generation Infrastructure Processing Unit (IPU)
Built for the Edge: The Next-Generation Intel® Xeon D 2700 & 1700 processors
Enabling Scalable Application-Specific Optical Engines (ASOE) by Monolithic Integration of Photonics and Electronics
Hardware and applications of AsAP: An asynchronous array of simple processors
Have your cake in parallel and eat it sequentially too! Semantically sequential, parallel execution of multiprocessor programs
IEEE Hot Chips 32 Symposium, HCS 2020, Palo Alto, CA, USA, August 16-18, 2020
Transactional memory implementation overview
Nonvolatile memory seminar Hot Chips 2010
RTX ON - The NVIDIA TURING GPU
FSM™ femtocell station modem
2016 IEEE Hot Chips 28 Symposium (HCS), Cupertino, CA, USA, August 21-23, 2016
Westmere-EX: A 20 thread server CPU
Ironwood: Delivering Best in Class perf, perf/TCO and perf/Watt for Reasoning Model Training and Serving
Dynamic Neural Accelerator for Reconfigurable & Energy-efficient Neural Network Inference
SDA: Software-Defined Accelerator for general-purpose big data analysis system
System-on-Chip Implementation of Trusted Execution Environment with Heterogeneous Architecture
MN-Core 2: Second-Generation Processor of MN-Core Architecture for AI and General-Purpose HPC Application
Onyx: A Programmable Accelerator for Sparse Tensor Algebra
Measuring the gap between programmable and fixed-function accelerators: A case study on speech recognition
KiloCore: A 32 nm 1000-processor array
Home entertainment-quality multimedia experience whilst on the move
Zion: Facebook Next- Generation Large Memory Training Platform
PHEP: Paillier Homomorphic Encryption Processors for Privacy-Preserving Applications in Cloud Computing
SCORPIO: 36-core shared memory processor demonstrating snoopy coherence on a mesh interconnect
Deep compression and EIE: Efficient inference engine on compressed deep neural network
Welcome program chairs
Prototyping the DySER specialization architecture with OpenSPARC
Sereno: A second generation virtualized network interface controller
3D FPGA & 3D ASIC worlds first unified 3D IC design platform
A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect with 0.3V swing and 0.062pJ/bit power in InFO package
AMD 400G Adaptive SmartNIC SoC: Technology preview
BROCA: A Low-power and Low-latency Conversational Agent RISC-V System-on-Chip for Voice-interactive Mobile Devices
AI Compute Chip from Enflame
Multithreaded programming challenges, current practice, and languages/tools support
IBM's Next Generation POWER Processor
Deep learning: Architectures, algorithms, applications
2011 IEEE Hot Chips 23 Symposium (HCS), Stanford, CA, USA, August 17-19, 2011
The true Processing In Memory accelerator
Collaborative innovation; a new lever in information technology development
A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing
Industry's First 7.2 Gbps 512GB DDR5 Module
A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network
Next generation SPARC processor cache hierarchy
LiveSynth: Towards an interactive synthesis flow
Memory overview and RRAM materials development at SEMATECH
"Richland" client APU
ENIAD: A Reconfigurable Near-data Processing Architecture for Web-Scale AI-enriched Big Data Service
Taping Out Three Class Chips Per Semester in Intel 16 Technology
Westmere Xeon-56xx "Tick" CPU
Integrated inductors with magnetic materials for on-chip power conversion
Poulson: An 8 core 32 nm next generation Intel® Itanium® processor
Floating point processing using FPGAs
NVIDIA Blackwell Platform: Advancing Generative AI and Accelerated Computing
Experiences using a novel Python-based hardware modeling framework for computer architecture test chips
Azure Secure Hardware Architecture : A Robust Security Foundation for Cloud Workloads
New 3rd Gen Intel ® Xeon ® Scalable Processor (Codename: Ice Lake-SP)
Nahalem-EX CPU architecture
Optical interconnect circuits: Some design considerations
Predictable Scaling and Infrastructure
A few ways can take you a long way: Efficient and highly associative caches with scalable partitioning for many-core CMPs
Moorestown platform: Based on lincroft SoC designed for next generation smartphones
Agilex™ Generation of Intel® FPGAs
The world's first USB3.0 storage controller
PNX85500 single chip LCD TV system with integrated 120Hz HD frame rate converter