yusuke1997/dblp-id-title huggingface dataset:
TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools
Design and Optimization of Digital Circuits by Artificial Evolution Using Hybrid Multi Chromosome Cartesian Genetic Programming
Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks
Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server
Parametric Encryption Hardware Design
Hardware/Software Codesign for Embedded Implementation of Neural Networks
A Synthesizable Multicore Platform for Microwave Imaging
DIM-VEX: Exploiting Design Time Configurability and Runtime Reconfigurability
ARABICA: A Reconfigurable Arithmetic Block for ISA Customization
A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation
Energy Efficient DNN Compaction for Edge Deployment
Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform
FPGA-Based Memory Efficient Shift-And Algorithm for Regular Expression Matching
Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification
A Light-Weight Vision Transformer Toward Near Memory Computation on an FPGA
Exploiting 3D Memory for Accelerated In-Network Processing of Hash Joins in Distributed Databases
Hardware Acceleration of Matrix Multiplication over Small Prime Finite Fields
Super Semi-systolic Array-Based Application-Specific PLD Architecture
Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing
Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues
Instruction Set Optimization for Application Specific Processors
Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings
Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs
Operand-Value-Based Modeling of Dynamic Energy Consumption of Soft Processors in FPGA
Hardware Implementation of the Orbital Function for Quantum Chemistry Calculations
Clone-Resistant Secured Booting Based on Unknown Hashing Created in Self-Reconfigurable Platform
SEU Resilience of DES, AES and Twofish in SRAM-Based FPGA
Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays
A Multi-FPGA Scalable Framework for Deep Reinforcement Learning Through Neuroevolution
A Novel Encoder for TDCs
A Parameterisable FPGA-Tailored Architecture for YOLOv3-Tiny
Accelerating Convolutional Neural Networks in FPGA-based SoCs using a Soft-Core GPU
DynamIA: Dynamic Hardware Reconfiguration in Industrial Applications
ArchHDL: A Novel Hardware RTL Design Environment in C++
Deep Quantization of Graph Neural Networks with Run-Time Hardware-Aware Training
Automating Reconfiguration Chain Generation for SRL-Based Run-Time Reconfiguration
A New VLSI Architecture of Lifting-Based DWT
Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation
Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices
Feasibility Study of a Self-healing Hardware Platform
Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications
Domain-Specific Language and Compiler for Stencil Computation on FPGA-Based Systolic Computational-Memory Array
The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data Centres
VerCoLib: Fast and Versatile Communication for FPGAs via PCI Express
Optimized Generation of Memory Structure in Compiling Window Operations onto Reconfigurable Hardware
Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System
Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices
Synthesizing FPGA Circuits from Parallel Programs
Centralized and Software-Based Run-Time Traffic Management Inside Configurable Regions of Interest in Mesh-Based Networks-on-Chip
Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach
Applied Reconfigurable Computing - 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9-11, 2019, Proceedings
Simulation and Modelling for Network-on-Chip Based MPSoC
Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models
Reconfigurable Parallel Architecture for Genetic Algorithms: Application to the Synthesis of Digital Circuits
On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA's Configuration Infrastructure
A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem
FPGA Implementation of a Short Read Mapping Accelerator
Reconfigurable Computing: Architectures, Tools, and Applications - 10th International Symposium, ARC 2014, Vilamoura, Portugal, April 14-16, 2014. Proceedings
FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design
Architecture Based on FPGA's for Real-Time Image Processing
An FPGA Accelerator for Hash Tree Generation in the Merkle Signature Scheme
Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan
Virtualization within a Parallel Array of Homogeneous Processing Units
Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs
Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems
Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks
Efficient Camera Input System and Memory Partition for a Vision Soft-Processor
FPGA Applications in Unmanned Aerial Vehicles - A Review
TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs
Fast Approximation of the Top-k Items in Data Streams Using a Reconfigurable Accelerator
Accelerating Graph Neural Networks in Pytorch with HLS and Deep Dataflows
Analysis of Process Variation Within Clock Regions of AMD-Xilinx UltraScale+ Devices
High Performance Connected Components Accelerator for Image Processing in the Edge
ACCFS - Operating System Integration of Computational Accelerators Using a VFS Approach
A Protocol for Secure Remote Updates of FPGA Configurations
FPGA-Accelerated Molecular Dynamics Simulations: An Overview
Instruction Extension and Generation for Adaptive Processors
The von Neumann Syndrome and the CS Education Dilemma
Architectural Exploration of the ADRES Coarse-Grained Reconfigurable Array
Built-in 3-Dimensional Hamming Multiple-Error Correcting Scheme to Mitigate Radiation Effects in SRAM-Based FPGAs
SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms
IPEC: Open-Source Design Automation for Inter-Processing Element Communication
Reconfigurable Computing: Architectures, Tools and Applications, Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007
Configurable Fault-Tolerance for a Configurable VLIW Processor
A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs
Towards Dynamic Cache and Bandwidth Invasion
High Performance Programmable FPGA Overlay for Digital Signal Processing
FPGA-Based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments
Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture
High Level Synthesis Implementation of Object Tracking Algorithm on Reconfigurable Hardware
Reconfigurable Hardware Assist for Linux Process Scheduling in Heterogeneous Multicore SoCs
Analysis of Clock Tree Buffer Degradation Caused by Radiation
Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementations
Process Variability and Degradation: New Frontier for Reconfigurable
From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype
ScalableCore System: A Scalable Many-Core Simulator by Employing over 100 FPGAs
A Connection Router for the Dynamic Reconfiguration of FPGAs
Real-Time Multi-object Tracking Using YOLOv8 and SORT on a SoC FPGA
Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems
Efficient SR-Latch PUF
Dynamic Function Exchange in FPGA to Redefine RISC-V Multicore Architectures at Runtime
NEUROSEC: FPGA-Based Neuromorphic Audio Security
More Efficient CMMs on FPGAs: Instantiated Ternary Adders for Computation Coding
Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms
Design, Implementation, and Verification of an Adaptable Processor in Lava HDL
Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs
A Survey of Low Power Design Techniques for Last Level Caches
First Twenty Years of the International Symposium on Applied Reconfigurable Computing (ARC): A Selection of Papers
Neuromolecularware -- A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis
Reconfigurable Hardware Acceleration of Canonical Graph Labelling
An Efficient FPGA Implementation of the Big Bang-Big Crunch Optimization Algorithm
Acceleration of Data Streaming Classification using Reconfigurable Technology
The Implementation of a Coarse-Grained Reconfigurable Architecture with Loop Self-pipelining
A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA
Scalable Memory Hierarchies for Embedded Manycore Systems
Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA
Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC
On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach
A Machine Learning Methodology for Cache Recommendation
CGRA Tool Flow for Fast Run-Time Reconfiguration
Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL
Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support
Multi-layered NoCs with Adaptive Routing for Mixed Criticality Systems
Reconfigurable IP-Based Spectral Interference Canceller
Faster FPGA Debug: Efficiently Coupling Trace Instruments with User Circuitry
An Architecture for IPv6 Lookup Using Parallel Index Generation Units
Pipelined Microprocessors Optimization and Debugging
(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs
Combining Design Space Exploration with Task Scheduling of Moldable Streaming Tasks on Reconfigurable Platforms
EEG Feature Extraction Accelerator Enabling Long Term Epilepsy Monitoring Based on Ultra Low Power WSNs
Partial Reconfiguration for Dynamic Mapping of Task Graphs onto 2D Mesh Platform
A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU
Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing
Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES' Platform
A HyperTransport 3 Physical Layer Interface for FPGAs
ARISE Machines: Extending Processors with Hybrid Accelerators
VenOS: A Virtualization Framework for Multiple Tenant Accommodation on Reconfigurable Platforms
A CGRA Definition Framework for Dataflow Applications
Counting Heavy Items in Filtered Data Streams Using an HLS-Generated FPGA Kernel
A Reconfigurable Disparity Engine for Stereovision in Advanced Driver Assistance Systems
Optimising Performance of Quadrature Methods with Reduced Precision
Design and Implementation of a Multi-Core Crypto-Processor for Software Defined Radios
Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures
Coarse Grained Parallelism Optimization for Multicore Architectures: The ALMA Project Approach
Hierarchical Loop Partitioning for Rapid Generation of Runtime Configurations
Parallel Tempering MCMC Acceleration Using Reconfigurable Hardware
Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms
Fast Template-Based Heterogeneous MPSoC Synthesis on FPGA
SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures
Graph-Based Code Restructuring Targeting HLS for FPGAs
The Instruction-Set Extension Problem: A Survey
Thread Shadowing: Using Dynamic Redundancy on Hybrid Multi-cores for Error Detection
FPGA-Integrated Bag of Little Bootstraps Accelerator for Approximate Database Query Processing
Reconfigurable Hardware Evolution Platform for a Spiking Neural Network Robotics Controller
A Design-Space Exploration Framework for Application-Specific Machine Learning Targeting Reconfigurable Computing
FPGA-Based Acceleration of Pattern Matching in YARA
Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings
Out-of-the-Box Performance of FPGAs for ML Workloads Using Vitis AI
On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks
ArcvaVX: OpenVX Framework for Adaptive Reconfigurable Computer Vision Architectures
Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs
Judiciously Spreading Approximation Among Arithmetic Components with Top-Down Inexact Hardware Design
Programming Reconfigurable Decoupled Application Control Accelerator For Mobile Systems
Implementation of FM-Index Based Pattern Search on a Multi-FPGA System
About the Importance of Operation Grouping Procedures for Multiple Word-Length Architecture Optimizations
Implementation of a Perception System for Autonomous Vehicles Using a Detection-Segmentation Network in SoC FPGA
Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems
Trusted Computing Architectures for IoT Devices
A Dataflow Architecture for Real-Time Full-Search Block Motion Estimation
Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm
Systematic Customization of On-Chip Crossbar Interconnects
100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs
A Dynamic Partial Reconfigurable Overlay Framework for Python
Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator
An OpenCLTM Implementation of WebP Accelerator on FPGAs
Providing QoS Guarantees in a NoC by Virtual Channel Reservation
COSSIM: A Novel, Comprehensible, Ultra-Fast, Security-Aware CPS Simulator
Hardware Acceleration of Genetic Sequence Alignment
Dynamically Adapted Low Power ASIPs
Robots in Assisted Living Environments as an Unobtrusive, Efficient, Reliable and Modular Solution for Independent Ageing: The RADIO Perspective
Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods
A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters
Third Party CAD Tools for FPGA Design - A Survey of the Current Landscape
A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems
A Reconfigurable Stream-Based FPGA Accelerator for Bayesian Confidence Propagation Neural Networks
Hardware Benchmarking of Cryptographic Algorithms Using High-Level Synthesis Tools: The SHA-3 Contest Case Study
MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays
High-Level Synthesis of Memory Systems for Decoupled Data Orchestration
A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs
Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers
Design Space Exploration of Application Specific Number Formats Targeting an FPGA Implementation of SPICE
Efficient Communication for FPGA Clusters
A Dataflow Inspired Programming Paradigm for Coarse-Grained Reconfigurable Arrays
A Regular Expression Matching Circuit Based on a Decomposed Automaton
Exploring fpga Optimizations to Compute Sparse Numerical Linear Algebra Kernels
A GMM-Based Speaker Identification System on FPGA
Moving Target and Implementation Diversity Based Countermeasures Against Side-Channel Attacks
Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens
DNN Model Theft Through Trojan Side-Channel on Edge FPGA Accelerator
High Performance Reconfigurable Architecture for Double Precision Floating Point Division
The ARAMiS Project Initiative - Multicore Systems in Safety- and Mixed-Critical Applications
Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist
Technique for Vendor and Device Agnostic Hardware Area-Time Estimation
The Colour of Embedded Computation
Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA
Comparing C and SystemC Based HLS Methods for Reconfigurable Systems Design
Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings
An Efficient Hardware Architecture for Block Based Image Processing Algorithms
Comparing Register-Transfer-, C-, and System-Level Implementations of an Image Enhancement Algorithm
Exploring HLS Optimizations for Efficient Stereo Matching Hardware Implementation
ReneGENE-GI: Empowering Precision Genomics with FPGAs on HPCs
Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture Radar Imaging
A Flexible Mixed-Mesh FPGA Cluster Architecture for High Speed Computing
Image Processing Architecture for Local Features Computation
Effective Reconfigurable Design: The FASTER Approach
Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture
The Emergence of Non-von Neumann Processors
Applied Reconfigurable Computing - 13th International Symposium, ARC 2017, Delft, The Netherlands, April 3-7, 2017, Proceedings
Reconfigurable Accelerator for On-Board SAR Imaging Using the Backprojection Algorithm
A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem
Architecture Virtualization for Run-Time Hardware Multithreading on Field Programmable Gate Arrays
A Convolution Neural Network Based Displaced Vertex Trigger for the Belle II Experiment
Custom Framework for Run-Time Trading Strategies
Towards Secure and Efficient Multi-generation Cellular Communications: Multi-mode SNOW-3G/V ASIC and FPGA Implementations
A Correlation Power Analysis Attack against Tate Pairing on FPGA
Timing Optimization for Virtual FPGA Configurations
A Fully Parallel Particle Filter Architecture for FPGAs
Hybrid Prototyping for Manycore Design and Validation
QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection
A Reconfigurable PID Controller
A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads
StocNoC: Accelerating Stochastic Models Through Reconfigurable Network on Chip Architectures
Application-Specific Signatures for Transactional Memory in Soft Processors
A Hardware Accelerated Simulation Environment for Spiking Neural Networks
A Modular-Based Assembly Framework for Autonomous Reconfigurable Systems
StreamGrid - An AXI-Stream-Compliant Overlay Architecture
FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing
Optimising Operator Sets for Analytical Database Processing on FPGAs
Searching the Web with an FPGA Based Search Engine
Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture
Accelerating Heap-Based Priority Queue in Image Coding Application Using Parallel Index-Aware Tree Access
FPGA Design Productivity - A Discussion of the State of the Art and a Research Agenda
Empirical Evaluation of Fixed-Point Arithmetic for Deep Belief Networks
LP-P 2 IP: A Low-Power Version of P 1 IP Architecture Using Partial Reconfiguration
Soft Timing Closure for Soft Programmable Logic Cores: The ARGen Approach
Real-Time Embedded Object Tracking with Discriminative Correlation Filters Using Convolutional Features
A Redundant Design Approach with Diversity of FPGA Resource Mapping
Reconfigurable Computing Education in Computer Science
A Reconfigurable Architecture for MIMO Square Root Decoder
A Low-Power FPGA-Based Architecture for Microphone Arrays in Wireless Sensor Networks
Enabling FPGA and AI Engine Tasks in the HPX Programming Framework for Heterogeneous High-Performance Computing
Bridging the Gap in ECG Classification: Integrating Self-supervised Learning with Human-in-the-Loop Amid Medical Equipment Hardware Constraints
Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures
Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators
QUAD - A Memory Access Pattern Analyser
NVMulator: A Configurable Open-Source Non-volatile Memory Emulator for FPGAs
A New Self-Managing Hardware Design Approach for FPGA-based Reconfigurable Systems
Table-Based Division by Small Integer Constants
A Heterogeneous Embedded Platform for AI-Based Protocol Identification
Enhanced Radiation Tolerance of an Optically Reconfigurable Gate Array by Exploiting an Inversion/Non-inversion Implementation
Advanced SystemC Tracing and Analysis Framework for Extra-Functional Properties
Efficient Elliptic-Curve Cryptography Using Curve25519 on Reconfigurable Devices
A Hybrid FPGA Trojan Detection Technique Based-on Combinatorial Testing and On-chip Sensing
High-Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-Based Post-Quantum Cryptography Using Software/Hardware Codesign
Deriving Resource Efficient Designs Using the REFLECT Aspect-Oriented Approach - (Extended Abstract)
Reconfigurable FPGA-Based FFT Processor for Cognitive Radio Applications
Towards an Adaptable Multiple-ISA Reconfigurable Processor
Stand-Alone Memory Controller for Graphics System
Preemptive Hardware Multitasking in ReconOS
Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor
Hardware-Accelerated Data Compression in Low-Power Wireless Sensor Networks
Configurable Embedded Core for Controlling Electro-Mechanical Systems
On-FPGA Spiking Neural Networks for Multi-variable End-to-End Neural Decoding
Real-Time Audio Group Delay Correction with FFT Convolution on FPGA
Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator
Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA
An FPGA Configuration Scheme for Bitstream Protection
PROACT - Physical Attack Resistance of Cryptographic Algorithms and Circuits with Reduced Time to Market
A Compact Shader for FPGA-Based Volume Rendering Accelerators
Real Time Image Processing on a Portable Aid Device for Low Vision Patients
Area-Energy Aware Dataflow Optimisation of Visual Tracking Systems
Applied Reconfigurable Computing - 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings
Implementation of LPM Address Generators on FPGAs
Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural Network
Computing to the Limit with Heterogeneous CPU-FPGA Devices in a Video Fusion Application
An FPGA-Based Implementation of a Pipelined FFT Processor for High-Speed Signal Processing Applications
Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array
Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
Resource Efficient Dynamic Voltage and Frequency Scaling on Xilinx FPGAs
Architecture for Transparent Binary Acceleration of Loops with Memory Accesses
Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder
GPU vs FPGA: A Comparative Analysis for Non-standard Precision
FPGA-Based Adaptive Data Acquisition Scheduler-on-Chip (SchoC) for Heterogeneous Signals
Survey on Real-Time Network-on-Chip Architectures
MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment
SysIDLib: A High-Level Synthesis FPGA Library for Online System Identification