yusuke1997/dblp-id-title huggingface dataset:
27th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2017, Thessaloniki, Greece, September 25-27, 2017
Process Variation-Aware Analytical Modeling of Subthreshold Leakage Power
Modeling energy-performance tradeoffs in ARM big.LITTLE architectures
A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits
Power efficient digital IC design for a medical application with high reliability requirements
Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization
Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates
Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for V th Assignment and Path Balancing
Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique
Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study
Design and Test of Self-checking Asynchronous Control Circuit
Energy consumption savings in ZigBee-based WSN adjusting power transmission at application layer
A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors
Double-Latch Clocking Scheme for Low-Power I.P. Cores
Hierarchical Timing-Critical Paths Analysis in Sequential Circuits
Optimal Two-Level Delay - Insensitive Implementation of Logic Functions
System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters
Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic
A Study on CMOS Time Uncertainty with Technology Scaling
A new bank sensitive DRAMPower model for efficient design space exploration
The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics
Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective
Energy-Efficient Hardware Architecture for Variable N-point 1D DCT
Robust sub-powered asynchronous logic
Power Management for Low-Power Battery Operated Portable Systems Using Current-Mode Techniques
Towards a Software Power Cost Analysis Framework Using Colored Petri Net
Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems
Soft Error-Aware Power Optimization Using Gate Sizing
Crosstalk Measurement Technique for CMOS ICs
SWAT: Simulator for Waveform-Accurate Timing Including Parameter Variations and Transistor Aging
L1 Data Cache Power Reduction Using a Forwarding Predictor
Enhanced RF Harvesting System by the Utilization of Resonant Cavities
XEEMU: An Improved XScale Power Simulator
A Predictive Synchronizer for Periodic Clock Domains
Using Iddt current degradation to monitor ageing in CMOS circuits
Dynamic Memory Design for Low Data-Retention Power
A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization
Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid Cooling
A framework with temperature-aware accuracy levels for battery modeling from datasheets
Muller C-Element Metastability Containment
Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure
On-line thermal emulation: How to speed-up your thermal controller design
Energy efficiency of 2-step charging power-clock for adiabatic logic
Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology
UVM-based Verification of a Digital PLL Using SystemVerilog
Static Power Consumption in CMOS Gates Using Independent Bodies
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption
BSAA: A Switching Activity Analysis and Visualisation Tool for SoC Power Optimisation
Reduced Leverage of Dual Supply voltages in Ultra Deep Submicron Technologies
Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures
Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems
TSV Assignment of Thermal and Wirelength Optimization for 3D-IC Routing
A Genetic Bus Encoding Technique for Power Optimization of Embedded Systems
A Temperature Variation Tolerant CMOS-Only Voltage Reference for RFID Applications
Improving the Memory Bandwidth Utilization Using Loop Transformations
Energy profile analysis of Zynq-7000 programmable SoC for embedded medical processing: Study on ECG arrhythmia detection
A Low-Power Encoding Scheme for GigaByte Video Interfaces
Moderate Inversion: Highlights for Low Voltage Design
Analog Power Modelling
A CMOS Compatible Charge Recovery Logic Family for Low Supply Voltages
SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level
Nanoelectronics: Challenges and Opportunities
Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms
Power Consumption of Performance-Scaled SIMD Processors
Generating Worst-Case Stimuli for Accurate Power Grid Analysis
Approximate adder segmentation technique and significance-driven error correction
Logic Style Comparison for Ultra Low Power Operation in 65nm Technology
Probabilistic Power Estimation for Digital Signal Processing Architectures
Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis
Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model
Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks
Energy Efficient Register Renaming
Stand-by Power Reduction for Storage Circuits
A Unified Framework for Power-Aware Design of Embedded Systems
Empirical verification of fault models for FPGAs operating in the subcritical voltage region
Variability analysis of self-timed SRAM robustness
Frequency-domain modeling of ground bounce and substrate noise for synchronous and GALS systems
Pipelining for dual supply voltages
Handheld System Energy Reduction by OS-Driven Refresh
Analysis of the Contribution of Interconnect Effects in the Energy Dissipation of VLSI Circuits
Evaluating the impact of substrate on power integrity in industrial microcontrollers
SRAM CP: A Charge Recycling Design Schema for SRAM
PARCOURS - Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits
Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities
Wideband dynamic voltage sensing mechanism for EH systems
High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI
Compiler-Driven Leakage Energy Reduction in Banked Register Files
Analysis of stress effects on timing of nano-scaled CMOS digital integrated circuits
Unified Power Format (UPF) methodology in a vendor independent flow
The Power Forward Initiative
A Secure D Flip-Flop against Side Channel Attacks
A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR)
Fast modeling technique for nano scale CMOS inverter and propagation delay estimation
25th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2015, Salvador, Brazil, September 1-4, 2015
Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders
A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers
Thermoelectric effects in graphene and graphene-based nanostructures using atomistic simulation
Optimum Buffer Size for Dynamic Voltage Processors
Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications
Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings
Low Power Response Time Accelerator with Full Resolution for LCD Panel
Power saving policies for multipurpose WBAN
Design Optimization with Automated Cell Generation
Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components
Temperature Dependence in Low Power CMOS UDSM Process
Processor Customization for Software Implementation of the AES Algorithm for Wireless Sensor Networks
Data-Driven Clock Gating for Digital Filters
Design of Variable Input Delay Gates for Low Dynamic Power Circuits
PSK Signalling on NoC Buses
Model to Hardware Matching for nm Scale Technologies
The Emergency of Design for Energy Efficiency: An EDA Perspective
Direct Statistical Simulation of Timing Properties in Sequential Circuits
Low-Power Digital Filtering Based on the Logarithmic Number System
Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology
Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements
The Involution Tool for Accurate Digital Timingand Power Analysis
Correct Modelling of Nested Miller Compensated Amplifier for Discrete-Time Applications
Maximizing yield in Near-Threshold Computing under the presence of process variation
Worst Case Crosstalk Noise Effect Analysis in DSM Circuits by ABCD Modeling
Adaptive Transient Computing for Power-Neutral Embedded Devices
Semi-modular Latch Chains for Asynchronous Circuit Design
Efficient Dense and Sparse Matrix Multiplication on GP-SIMD
Threshold Mean Larger Ratio Motion Estimation in MPEG Encoding Using LNS
Analysis of Energy Consumed by Secure Session Negotiation Protocols in Wireless Networks
Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance
Power contracts: A formal way towards power-closure?!
Low Power Cache with Successive Tag Comparison Algorithm
Energy-Aware System-on-Chip for 5 GHz Wireless LANs
Power-Clock Gating in Adiabatic Logic Circuits
Low-Power Soft Error Hardened Latch
Architecture exploration of a fixed point computation unit using precise timing spiking neurons
Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs
High level tranforms toreduce energy consumption of signal and image processing operators
Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level
On Combined DVS and Processor Evaluation
Low-Power FSMs in FPGA: Encoding Alternatives
GALS design of ECC against side-channel attacks - A comparative study
Observability Conditions and Automatic Operand-Isolation in High-Throughput Asynchronous Pipelines
Area-Aware Pipeline Gating for Embedded Processors
Logic-Level Fast Current Simulation for Digital CMOS Circuits
Performance-Driven Clustering of Asynchronous Circuits
Optical and Electrical Simulations of Radiation-Hard Photodiode in 0.35μM High-Voltage CMOS Technology
Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources
Register Isolation for Synthesizable Register Files
Design of a Linear Power Amplifier with +/-1.5V Power Supply Using ALADIN
Combining Pel Decimation with Partial Distortion Elimination to increase SAD energy efficiency
A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling
Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs
Asynchronous Design for High-Speed and Low-Power Circuits
Crosstalk in High-Performance Asynchronous Designs
An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies
Noise Margin in Low Power SRAM Cells
Exploiting Metal Layer Characteristics for Low-Power Routing
An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs
Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor
The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems
On the Static CMOS Implementation of Magnitude Comparators
Near-Field Mapping System to Scan in Time Domain the Magnetic Emissions of Integrated Circuits
Power Management in Synopsys Galaxy Design Platform
Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures
Smart sensor system for leakage detection in pipes carrying oil products in noisy environment: The ESTHISIS Project
Design challenges for near and sub-threshold operation: A case study with an ARM Cortex-M0+ based WSN subsystem
NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode
Impact of Technology in Power-Grid-Induced Noise
Peak power demand analysis and reduction by using battery buffers for monotonic controllers
Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology
Moment-Based Estimation of Switching Activity for Correlated Distributions
A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements
Leakage current analysis in static CMOS logic gates for a transistor network design approach
Multi-scale electrothermal simulation and modelling of resistive random access memory devices
A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool
Settling Time Minimization of Operational Amplifiers
A Method to Design Compact Dual-rail Asynchronous Primitives
Subthreshold FIR Filter Architecture for Ultra Low Power Applications
FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework
Securing embedded systems and their IPs with digital reconfigurable PUFs
Energy Efficient Clock Distribution with Low-Leakage Multi-Vt Buffers
Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization
Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors
On-Chip NBTI and PBTI Tracking through an All-Digital Aging Monitor Architecture
Wireless Sensor Networks: A New Life Paradigm
Symmetric Power Analysis Attack Resilient Adiabatic Logic for Smartcard Applications
Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case
Reliability monitoring of digital circuits by in situ timing measurement
Template Vertical Dictionary-Based Program Compression Scheme on the TTA
Integration of Power Management Units onto the SoC
Low-Power Aspects of Nonlinear Signal Processing
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 22nd International Workshop, PATMOS 2012, Newcastle upon Tyne, UK, September 4-6, 2012, Revised Selected Papers
Enabling energy-aware design decisions for behavioural descriptions containing black-box IP-components
High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder
Cryptography: Circuits and Systems Approach
Energy aware Networks-on-Chip cortex inspired communication
Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures
Write scheme for multiple Complementary Resistive Switch (CRS) cells
Iterative Timing Analysis Considering Interdependency of Setup and Hold Times
Equivalence of clock gating and synchronization with applicability to GALS communication
Applying of Quality of Experience to system optimisation
Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs
Statistical Power Estimation of Behavioral Descriptions
High Level Synthesis of Asynchronous Circuits from Data Flow Graphs
Novel memristive logic architectures
Backlight Compensation Algorithms to Improve Power Consumption in LED- LCD Displays
An Information Privacy Culture Index Framework and Instrument to Measure Privacy Perceptions across Nations: Results of an Empirical Study
A Social Engineering Prevention Training Tool: Methodology and Design for Validating the SEADM
A Trust Domains Taxonomy for Securely Sharing Information: A Preliminary Investigation
South African Information Security Multi-Conference, SAISMC 2010, Port Elizabeth, South Africa, May 17-18, 2010. Proceedings
"Most Companies Share Whatever They Can to Make Money!": Comparing User's Perceptions with the Data Practices of IoT Devices
Using Actions and Intentions to Evaluate Categorical Responses to Phishing and Genuine Emails
Decreasing Physical Access Bottlenecks through Context-Driven Authentication
The Threat of Political Phishing
Factors Influencing Cybercrime Reporting Behaviour in South African State-Owned Entities
A Novel Framework for the Development of Age Appropriate Information Security Serious Games
Security and Privacy Perspectives on Using ChatGPT at the Workplace: An Interview Study
Key Elements for Cybersafety Education of Primary School Learners in South Africa
A Systematic Task and Knowledge-Based Process to Tune Cybersecurity Training to User Learning Groups: Application to Email Phishing Attacks
Linux Kernel Keyloggers and Information Security
To Catch a Thief: Examining Socio-technical Variables and Developing a Pathway Framework for IP Theft Insider Attacks
Towards Understanding Diagnostic Work During the Detection and Investigation of Security Incidents
A Model of Security Culture for e-Science
Understanding Security Practices Deficiencies: A Contextual Analysis
A Reference Point for Designing a Cybersecurity Curriculum for Universities
The Design and Evaluation of an Interactive Social Engineering Training Programme
Stakeholders’ Perspectives on Malleable Signatures in a Cloud-based eHealth Scenario
Involving Users in the Design of a Serious Game for Security Questions Education
Gamification in Cybersecurity Training: High-Level Properties of Cybersecurity Games
Alternative Graphical Authentication for Online Banking Environments
Studying Safe Online Banking Behaviour: A Protection Motivation Theory Approach
Which Individual, Cultural, Organisational and Interventional Factors Explain Phishing Resilience?
Survey of Users' Willingness to Adopt and Pay for Cybersecurity Training
Cyber Security Awareness and Education Support for Home and Hybrid Workers
An Educational Intervention Towards Safe Smartphone Usage
Cybersecurity Awareness and Education: A Necessary Parameter for Smart Communities
What Can We Learn from the Analysis of Information Security Policies? The Case of UK's Schools
A Practical Assessment of Social Engineering Vulnerabilities
Implications and Risks of MMORPG Addiction: Motivations, Emotional Investment, Problematic Usage and Personal Privacy
Digital Wellness: Concepts of cybersecurity presented visually for children
Cyber Range Exercises: Potentials and Open Challenges for Organizations
Secure Coding Practices in the Software Development Capstone Projects
You Have Three Tries Before Lockout. Why Three?
Cyber4Dev Security Culture Model for African Countries
Information System Security Compliance to FISMA Standard: A Quantitative Measure
Critical Analysis of Information Security Culture Definitions
The Socio-Technical Impact on Security of the Healthcare Internet of Things in the Use of Personal Monitoring Devices (PMDs)
Evaluation Strategies for Cybersecurity Training Methods: A Literature Review
Users can't be fooled - The role of existing vs. fictitious third party web assurance seals on websites
CAP: Patching the Human Vulnerability
Human Aspects of Information Security: An Empirical Study of Intentional versus Actual Behavior
"Your Cookie Disclaimer is Not in Line with the Ideas of the GDPR. Why?"
The Quest to Replace Passwords Revisited - Rating Authentication Schemes
An Implementation Process and Factor Model for Information Systems Security Engineering
Harnessing the Right Talent for SETA Programs: Cybersecurity Roles and Competencies that Make a Difference
Human Aspects of Information Security and Assurance - 16th IFIP WG 11.12 International Symposium, HAISA 2022, Mytilene, Lesbos, Greece, July 6-8, 2022, Proceedings
The Lemming Effect in Information Security
Human Aspects of Information Security and Assurance - 15th IFIP WG 11.12 International Symposium, HAISA 2021, Virtual Event, July 7-9, 2021, Proceedings
Why Open Government is good for cybersecurity and public trust - now would be a good time to start
The Development of a Multidisciplinary Cybersecurity Workforce: An Investigation
A Review of Information Security Aspects of the Emerging Covid-19 Contact Tracing Mobile Phone Applications
An Investigation into the Cybersecurity Skills Gap in South Africa
COLTRANE - Towards a Methodology and Platform Supported Educational Basis for Cybersecurity Education
Human excellence in the information security: a complexity theory perspective
Towards an Interdisciplinary Cyberbullying Campaign
Heuristic Attack on Graphic Password Generation
What Goes Around Comes Around; Effects of Unclear Questionnaire Items in Information Security Research
Are People with Cyber Security Training Worse at Checking Phishing Email Addresses? Testing the Automaticity of Verifying the Sender's Address
Human Aspects of Information Security and Assurance - 18th IFIP WG 11.12 International Symposium, HAISA 2024, Skövde, Sweden, July 9-11, 2024, Proceedings, Part II
A Machine Learning Approach to Detect Insider Threats in Emails Caused by Human Behaviours
Mismorphism: a Semiotic Model of Computer Security Circumvention
Digital Rights Management: The Four Perspectives of Developers, Distributors, Users, and Lawyers
Combating Digital Exclusion with Cybersecurity Training - An Interview Study with Swedish Seniors
Ethical Guidelines for Cyber-related Services Aimed at the Younger Generations
Towards Usable Privacy Policy Display & Management - The PrimeLife Approach
All About Phishing: Exploring User Research through a Systematic Literature Review
The BYOD Information Security Challenge for CIOs
Freegate: A Defence against the Pending Censorship of Australia?
Online Security Attack Experience and Worries of Young Adults in the United Kingdom
Combating Information Security Apathy By Encouraging Prosocial Organisational Behaviour
Validation of an Information Privacy Perception Instrument at a Zimbabwean University
Arguments For Anonymity
Risk Culture Influences in Internet Safety and Security
Organizational Risk using Network Analysis
Adapting Cyber-Security Training to Your Employees
To Risk Analyse, or Not to Risk Analyse: That's the Question
Using the IKEA Effect to Improve Information Security Policy Compliance
"There is a Damn Hello on the Social Media!" Insights into Public Risk Communication in the Digital Age
What Can Johnny Do?–Factors in an End-User Expertise Instrument
Exploring Information Security and Domestic Equality
Trusting digitized patient-related information: The need for a new approach
Tailoring Policies and Involving Users in Constructing Security Policies - A Mapping Study
Tracking Risky Behavior On The Web: Distinguishing Between What Users ‘Say' And ‘Do'
Analysis of Potential Problems in People Management concerning Information Security in Cross-cultural Environment -In the Case of Malaysia-
Improving internet banking security by using differentiated authentication based on risk profiling
Analysing Websites Privacy Policies: A Study of E-commerce Websites in South Africa
Education in the 'Virtual' Community: Can beating Malware Man teach users about Social Networking Security?
The cycle of deception - a model of social engineering attacks, defenses and victims
Responding to KRACK: Wi-Fi Security Awareness in Private Households
When Googling It Doesn't Work: The Challenge of Finding Security Advice for Smart Home Devices
A Conceptual Information Security Culture Framework for Higher Learning Institutions
Online Security Attack Experience and Worries of Young Adults in the Kingdom of Saudi Arabia
Factors Influencing the Use of Privacy Settings in Location-Based Social Networks
Making Access Control Easy in IoT
A Novel Support Vector Machine Approach to High Entropy Data Fragment Classification
Dynamic Rights Reallocation In Social Networks
End-User Perception and Usability of Information Security
Public Thoughts on Tackling Digital Crime in Society and by Law Enforcement
Inter-Organisational Information Sharing - Between a Rock and a Hard Place
The One-Eyed Leading the Blind: Understanding Differences Between IT Professionals and Non-IT Staff When Creating and Managing Passwords
Investigating the Factors Influencing Individuals' Self-sovereign Identity Adoption Intentions
Elicitation of Requirements for an Inter-Organizational Platform to Support Security Management Decisions
Defining and Modelling the Online Fraud Process
Rationalising Decision Making about Risk: A Normative Approach
SecSDM: A usable tool to support IT undergraduate students in secure software development