yusuke1997/dblp-id-title huggingface dataset:
DAEBI: A Tool for Data Flow and Architecture Explorations of Binary Neural Network Accelerators
Online Prediction of Applications Cache Utility
NanoController: A Minimal and Flexible Processor Architecture for Ultra-Low-Power Always-On System State Controllers
Distributed Training on a Highly Heterogeneous HPC System
Instrumentation techniques for cyber-physical systems using the targeted dataflow interchange format
High-Speed Event-Driven RTL Compiled Simulation
EasyHBM: Simple and Fast HBM Access for FPGAs Using High-Level-Synthesis
Programming Extremely Flexible Platforms
HARPA: Solutions for dependable performance under physically induced performance variability
An FPGA-based systolic array to accelerate the BWA-MEM genomic mapping algorithm
A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures
SIZALIZER: Multilevel Analysis Framework for Object Size Optimization
Special session on "Exposed data path architectures: Recent advances and applications"
Adaptive runtime exploiting sparsity in tensor of deep learning neural network on heterogeneous systems
Processor Architectures for Multimedia Applications
AivoTTA: an energy efficient programmable accelerator for CNN-based object recognition
ARAL-CR: An adaptive reasoning and learning cognitive radio platform
Resource conscious prefetching for irregular applications in multicores
Efficient Handover Mode Synchronization for NR-REDCAP on a Vector DSP
ASIP-eFPGA Architecture for Multioperable GNSS Receivers
VLSI Architecture for MRF Based Stereo Matching
Asynchronous parallel simulation with transaction events
Architecture Exploration for 3G Telephony Applications Using a Hardware-Software Prototyping Platform
Removal of unnecessary context switches from the systemc simulation kernel for fast VP simulation
A Logic-Based Physical Simulation Framework for Digital Microfluidic Biochips
Constraint-Driven Identification of Application Specific Instructions in the DURASE System
numap: A portable library for low-level memory profiling
FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability
An efficient realization of forward integer transform in H.264/AVC intra-frame encoder
Tervel: A unification of descriptor-based techniques for non-blocking programming
Automated dataflow graph merging
Application Server for Wireless Sensor Networks
Parallel Memory Architecture for TTA Processor
Benchmarking Mesh and Hierarchical Bus Networks in System-on-Chip Context
A Framework Introducing Model Reversibility in SoC Design Space Exploration
2011 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XI, Samos, Greece, July 18-21, 2011
The Virtex II Pro TM MOLEN Processor
Automatic FIR Filter Generation for FPGAs
Instruction buffer with limited control flow and loop nest support
ImpBench: A novel benchmark suite for biomedical, microelectronic implants
Design of 100 muW Wireless Sensor Nodes on Energy Scavengers for Biomedical Monitoring
Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs
FPGA-based evaluation platform for disaggregated computing
An Evolutionary Approach to Area-Time Optimization of FPGA designs
A UML Profile for Asynchronous Hardware Design
Integrated Instruction Scheduling and Fine-Grain Register Allocation for Embedded Processors
Power-Aware Branch Logic: A Hardware Based Technique for Filtering Access to Branch Logic
HW-EPOLL: Hardware-Assisted User Space Event Notification for Epoll Syscall
Design productivity of a high level synthesis compiler versus HDL
A timed HW/SW coemulation technique for fast yet accurate system verification
Offline Phase Analysis and Optimization for Multi-configuration Processors
A co-simulation approach for system-level analysis of embedded control systems
Real-time tasks and voltage/frequency controller collaboration on low power energy operational systems
AMAIX: A Generic Analytical Model for Deep Learning Accelerators
Real-Time Linux on RISC-V: Long-Term Performance Analysis of PREEMPT_RT Patches
Architecture design space exploration of run-time scalable issue-width processors
Efficiency Measures for Multimedia SOCs
Vitamin-V: Serverless Cloud Computing Porting on RISC-V
Advantages of Java Processors in Cache Performance and Power for Embedded Applications
Reconfigurable Computing in the New Age of Parallelism
Data Mining in System-Level Design Space Exploration of Embedded Systems
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project
SimGate: Full-System, Cycle-Close Simulation of the Stargate Sensor Network Intermediate Node
Safe cooperative CPS: A V2I traffic management scenario in the SafeCOP project
Strictly Periodic Scheduling of Cyclo-Static Dataflow Models
NoC links energy reduction through link voltage scaling
Exploring the semantic gap in compiling embedded DSLs
Generating ASIPs with reduced number of connections to the register-file
A performance evaluation of multi-FPGA architectures for computations of information transfer
Designing applications for heterogeneous many-core architectures with the FlexTiles Platform
High-throughput flexible constraint length Viterbi decoders on de Bruijn, shuffle-exchange and butterfly connected architectures
Implementing Synthetic Aperture Radar Backprojection in Chisel - A Field Report
Model and Validation of Block Cleaning Cost for Flash Memory
Workload-dependent relative fault sensitivity and error contribution factor of GPU onchip memory structures
Predictive Resource Management for Next-Generation High-Performance Computing Heterogeneous Platforms
Constraints Derivation and Propagation for Large-Scale Embedded Systems Exploration
Software Pipelining Support for Transport Triggered Architecture Processors
A Communication-Centric Design Flow for HIBI-Based SoCs
AutoSync Framework for Expressing Synchronization Intentions in Multithreaded Programs
RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration
Improving TriMedia Cache Performance by Profile Guided Code Reordering
High throughput and scalable architecture for unified transform coding in embedded H.264/AVC video coding systems
LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing
Survey of secure processors
An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures
Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs
Black box ESL power estimation for loosely-timed TLM models
Energy Optimization of a Multi-bank Main Memory
Hard Edges: Hardware-Based Control-Flow Integrity for Embedded Devices
Dedicated hardware accelerators for the epistatic analysis of human genetic data
A Novel Chaining-Based Indirect Addressing Mode in a Vertical Vector Processor
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2008), Samos, Greece, July 21-24, 2008
Characterization of a Coherent Hardware Accelerator Framework for SoCs
Perspectives on system-level MPSoC design space exploration
EXA2PRO programming environment: architecture and applications
Reconfigurable computing for future vision-capable devices
Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors
Power adaptive computing system design in energy harvesting environment
Quantum era challenges for classical computers
Methods for design and implementation of dynamic signal processing systems
Data centres for IoT applications: The M2DC approach (Invited paper)
A Novel System Simulation Framework for HBM2 FPGA Platforms
RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems
Algorithm-level approximation for fast (or not) embedded stereovision algorithm
Moving Up to the Modeling Level for the Transformation of Data Structures in Embedded Multimedia Applications
Modeling pipelined application with Synchronous Data Flow graphs
Application of Very Fast Simulated Reannealing (VFSR) to Low Power Design
System-Level Modeling and Simulation of MPSoC Run-Time Management Using Execution Traces Analysis
Automatic ADL-Based Assembler Generation for ASIP Programming Support
PMDI: An AI-Enabled Ecosystem for Cooperative Urban Mobility
On-chip network interfaces supporting automatic burst write creation, posted writes and read prefetch
Code generation for a novel STA architecture by using post-processing backend
Synthesis of Instruction Extensions on HyperCell, a reconfigurable datapath
Understanding MPSoCs: exploiting memory microarchitectural vulnerabilities of high performance NoC-based MPSoCs
Accelerating high-level engineering computations by automatic compilation of Geometric Algebra to hardware accelerators
Parallel program = operator + schedule + parallel data structure
An FPGA-based prototyping method for verification, characterization and optimization of LDPC error correction systems
Current analysis approaches and performance needs for whole slide image processing in breast cancer diagnostics
Scalable FFT Processors and Pipelined Butterfly Units
Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments
Hardware-Based IP Lookup Using n -Way Set Associative Memory and LPM Comparator
Lightweight resource estimation model to extend battery life in video playback
A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach
Generated DSP Cores for Implementation of an OFDM Communication System
Integrated model-driven design-space exploration for embedded systems
Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing
Code Size Reduction by Compiler Tuning
A Solid-State 2-D Wind Sensor
A Radix-8 Multiplier Design and Its Extension for Efficient Implementation of Imaging Algorithms
Architectural low-power design using transaction-based system modeling and simulation
A first-order approximation of microarchitecture energy-efficiency
Realizing FIFO Communication When Mapping Kahn Process Networks onto the Cell
On brain-inspired hybrid topologies for nano-architectures - a Rent's rule approach -
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design
From Algorithm to Implementation: Enabling High-Throughput CNN-Based Equalization on FPGA for Optical Communications
Microcoded Reconfigurable Embedded Processors: Current Developments
Memory-Centric Hardware Synthesis from Dataflow Models
Fast parallel simulation of a manycore architecture with a flit-level on-chip network model
Mixed Precision in Heterogeneous Parallel Computing Platforms via Delayed Code Analysis
Rescheduling for Optimized SHA-1 Calculation
Cross-domain Modelling of Verification and Validation Workflows in the Large Scale European Research Project VALU3S - Invited Paper
Sandbridge Software Tools
An architecture for the simultaneous execution of hard real-time threads
GPUburn: A system to test and mitigate GPU hardware failures
A Side-channel Attack Resistant Programmable PKC Coprocessor for Embedded Applications
Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS
A Framework for Fixed Priority Periodic Scheduling Synthesis from Synchronous Data-Flow Graphs
A hybrid ASIC/FPGA fault-tolerant artificial pancreas
Reconfigurable Multicore Server Processors for Low Power Operation
Exploration framework for Run-time Resource Management of embedded multi-core platforms
Energy and Performance Evaluation of an FPGA-Based SoC Platform with AES and PRESENT Coprocessors
Reconfigurable design with clock gating
Parallel implementation of real-time semi-global matching on embedded multi-core architectures
On tokens and signals: Bridging the semantic gap between dataflow models and hardware implementations
Distributed resource management for concurrent execution of multimedia applications on MPSoC platforms
s Mixed Virtual/Real Prototypes for Incremental System Design - A Proof of Concept
Parallelizing general histogram application for CUDA architectures
Incorporating rapid design assembly into a virtual prototyping environment
Trade-Offs Between Voltage Scaling and Processor Shutdown for Low-Energy Embedded Multiprocessors
Towards unified mechanisms for inter-processor communication
Resource Conflict Detection in Simulation of Function Unit Pipelines
The homogeneity of architecture in a heterogeneous world
Embedded Computer Systems: Architectures, Modeling, and Simulation - 24th International Conference, SAMOS 2024, Samos, Greece, June 29 - July 4, 2024, Proceedings, Part I
LATONA: An Advanced Server Architecture for Ubiquitous Sensor Network
Cycle Accurate Simulation Model Generation for SoC Prototyping
Secure and Authenticated Communication in Chip-Level Microcomputer Bus Systems with Tree Parity Machines
Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic
Embedded Software Architecture for Diagnosing Network and Node Failures in Wireless Sensor Networks
Using CoDeL to Rapidly Prototype Network Processsor Extensions
Hardware/Software Co-Design of an Automatically Generated Analog NN
Embedded Computer Systems: Architectures, Modeling, and Simulation - 23rd International Conference, SAMOS 2023, Samos, Greece, July 2-6, 2023, Proceedings
Risk and Architecture Factors in Digital Exposure Notification
SysRT: A modular multiprocessor RTOS simulator for early design space exploration
Speculative synchronization for coherence-free embedded NUMA architectures
A strong arbiter PUF using resistive RAM
Communication Optimization in Compaan Process Networks
CoDeL: Automatically Synthesizing Network Interface Controllers
Design of an Adaptive Architecture for Energy Efficient Wireless Image Communication
Memory sharing techniques for multi-standard high-throughput FEC decoder
Optimized FPGA Implementation of a Compute-Intensive Oil Reservoir Simulation Algorithm
ESL power estimation using virtual platforms with black box processor models
Performance evaluation of image noise reduction computing on a mobile platform
High performance computing and industry 4.0: experiences from the DISRUPT project
Modified Hotspot Cache Architecture: A Low Energy Fast Cache for Embedded Processors
Thermal characterization of next-generation workloads on heterogeneous MPSoCs
Is computer science dying?
SWAN-iCare: A smart wearable and autonomous negative pressure device for wound monitoring and therapy
A Survey of Software Implementations for the Number Theoretic Transform
Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study
Parallel implementation of convolution encoder for software defined radio on DSP architecture
On Compact Mappings for Multicore Systems
MOVE-Pro: A low power and high code density TTA architecture
Fine-grained application-specific instruction set processor design for the K-best list sphere detector algorithm
Challenges of multi- and many-core architectures for electronic system-level design
OpenMP extensions for FPGA accelerators
Towards Privacy-First Security Enablers for 6G Networks: The PRIVATEER Approach
Micro-architectural simulation of in-order and out-of-order ARM microprocessors with gem5
Delays and states in dataflow models of computation
ACRA: A Cutting-Edge Analytics Platform for Advanced Real-Time Corruption Risk Assessment and Investigation Prioritization
Fault Detection Mechanisms for COTS FPGA Systems Used in Low Earth Orbit
Pre-simulation elaboration of heterogeneous systems: The SystemC multi-disciplinary virtual prototyping approach
Energy-Driven Partitioning of Signal Processing Algorithms in Sensor Networks
Hardware/software specialization through aspects: The LARA approach
Generating Stream Based Code from Plain C
Efficient computing in cyber-physical systems
CoolSim: Statistical techniques to replace cache warming with efficient, virtualized profiling
Translating Imperative Affine Nested Loop Programs into Process Networks
Software Implementation of WiMAX on the Sandbridge SandBlaster Platform
Platform-aware dynamic data type refinement methodology for radix tree Data Structures
Synchronization on heterogeneous multiprocessor systems
Special session on "FPGA-based emulation of hardware architectures"
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies
CoD: Coherence-on-Demand - Runtime Adaptable Working Set Coherence for DSM-Based Manycore Architectures
Strategies for Compiling µ TC to Novel Chip Multiprocessors
Fault Sensitivity Analysis of Lattice-Based Post-Quantum Cryptographic Components
On the Evaluation of Dense Chip-Multiprocessor Architectures
WCET-aware scheduling optimizations for multi-core real-time systems
Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration
RT-LIFE: Portable RISC-V Interface for Real-Time Lightweight Security Enforcement
High Abstraction Level Design and Implementation Framework for Wireless Sensor Networks
Communication Architecture Simulation on the Virtual Synchronization Framework
BOSMI: a framework for non-intrusive monitoring and testing of embedded multithreaded software on the logical level
Interference-Aware Workload Placement for Improving Latency Distribution of Converged HPC/Big Data Cloud Infrastructures
Multiple Description Scalable Coding for Video Transmission over Unreliable Networks
The Impact of Dynamic Storage Allocation on CPython Execution Time, Memory Footprint and Energy Consumption: An Empirical Study
Hardware-based synchronization framework for heterogeneous RISC/Coprocessor architectures
MPSoCSim: An extended OVP simulator for modeling and evaluation of Network-on-Chip based heterogeneous MPSoCs
Software synthesis in the ESL methodology for multicore embedded systems
Design environment for the support of configurable Network Interfaces in NoC-based platforms
Supercomputing: Past, present, and a possible future
Mapping and Performance Evaluation for Heterogeneous MP-SoCs Via Packing
Platform Thinking in Embedded Systems
Towards a Transformation Chain Modeling Language
A High-Level Programming Paradigm for SystemC
On STM concurrency control for multicore embedded real-time software
SDR platform for 802.11n and 3-GPP LTE
Advancing Future 5G/B5G Systems: The Int5Gent Approach
Concurrent multi-level arrays: Wait-free extensible hash maps
Observations on Power-Efficiency Trends in Mobile Communication Devices
High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms
Design Space Exploration with Automatic Selection of SW and HW for Embedded Applications
Multi-FPGA prototyping board issue: the FPGA I/O bottleneck
Architectural and algorithm level fault tolerant techniques for low power high yield multimedia devices
Optimizing wait-states in the synthesis of memory references with unpredictable latencies
Low-power application-specific FFT processor for LTE applications
SafeFloatZone: Identify Safe Domains for Elementary Functions
The ANTAREX tool flow for monitoring and autotuning energy efficient HPC systems
Performance Evaluation of RISC-based SoC Platforms in Network Processing Applications
Hardware-Aware Evolutionary Filter Pruning
A just-in-time modulo scheduling for virtual coarse-grained reconfigurable architectures
A Hypervisor Based Platform for the Development and Verification of Reliable Software Applications
Quantum Computing Research Lines in the Italian Center for Supercomputing
CASA: An Approach for Exposing and Documenting Concurrency-Related Software Properties
Energy-Aware Partial-Duplication Task Mapping Under Real-Time and Reliability Constraints
Exploiting tightly-coupled cores
Mapping of PRP/HSR redundancy protocols onto a configurable FPGA/CPU based architecture
Parametrized hardware architectures for the Lucas primality test
Fast Dynamic Binary Rewriting for flexible thread migration on shared-ISA heterogeneous MPSoCs
OpenCL-based design methodology for application-specific processors
Design Space Exploration of Media Processors: A Parameterized Scheduler
Transpiling Python to Rust for Optimized Performance
Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems
Monitor-adapter coupling for NOC performance tuning
Special session on "adaptive systems"
Using VLIW softcore processors for image processing applications
Concurrent memory subsystem and application optimization for ASIP design
Thermal optimization for micro-architectures through selective block replication
An Analytical Model for Loop Tiling Transformation
COSMOS: A System-Level Modelling and Simulation Framework for Coprocessor-Coupled Reconfigurable Systems
The ODYSSEY Tool-Set for System-Level Synthesis of Object-Oriented Models
Instruction-set extension for an ASIP-based SIFT feature extraction
A Comparative Study of Different FFT Architectures for Software Defined Radio
Calibration and validation of software performance models for pedestrian detection systems
Design metrics and visualization techniques for analyzing the performance of MOEAs in DSE
Myrmec: FPGA-Accelerated SmartNIC for Cost and Power Efficient IoT Sensor Networks
Adaptive simulation sampling using an Autoregressive framework
Scaling usable computing capability
Dynamic function specialization
Designing Wireless Sensor Nodes
Mapping of modal applications given throughput and latency constraints
Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulator
DeePar-SCA: Breaking Parallel Architectures of Lattice Cryptography via Learning Based Side-Channel Attacks
Multi-Domain Virtual Prototyping in a SystemC SIL framework: A heating system case study
A lightweight infrastructure for the dynamic creation and configuration of virtual platforms
Memory-constrained Block Processing Optimization for Synthesis of DSP Software
Predictable dynamic embedded data processing
A Model-Driven Automatically-Retargetable Debug Tool for Embedded Systems
Multi-domain transformational design flow for embedded systems
Design of a flexible high-speed FPGA-based flow monitor for next generation networks
Heterogeneous and runtime parameterizable Star-Wheels Network-on-Chip
Study of DNN-Based Ragweed Detection from Drones
Low Precision Processing for High Order Stencil Computations
A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems
Bridging the semantic gap between heterogeneous modeling formalisms and FMI
Instruction Set Encoding Optimization for Code Size Reduction
MOUSE: A Shortcut from Matlab Source to SIMD DSP Assembly Code
Multi-objective routing and topology optimization in networked embedded systems
A configurable SIMD architecture with explicit datapath for intelligent learning
Profiling Driven Scenarion Detection and Prediction for Multimedia Applications
Decentralized diagnosis of permanent faults in automotive E/E architectures
What cloud computing can teach us about embedded many-core programming?
Iterative Compilation
An Open-Hardware Platform for MPSoC Thermal Modeling
The AXIOM project (Agile, eXtensible, fast I/O Module)
A framework for efficient cache resizing
Design space exploration in application-specific hardware synthesis for multiple communicating nested loops
Climate and Biological Sensor Network
Aggressively bypassing list scheduler for transport triggered architectures
Multi-view consistency for infinitary regular languages
On-chip network resource management design and validation
Two-Dimensional Fast Cosine Transform for Vector-STA Architectures
Profiling Dilithium Digital Signature Traces for Correlation Differential Side Channel Attacks
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007), Samos, Greece, July 16-19, 2007
Adaptive dynamic memory allocators by estimating application workloads
Multi-objective Optimal Controller Synthesis for Heterogeneous Embedded Systems
Using OpenMP superscalar for parallelization of embedded and consumer applications
Trends in embedded software synthesis
Hardware/Software Self-adaptation in CPS: The CERBERO Project Approach
A bypass first policy for energy-efficient last level caches