yusuke1997/dblp-id-title huggingface dataset:
The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA)
Low overhead test point insertion for scan-based BIST
A novel robust and accurate spectral testing method for non-coherent sampling
Using Analog Signature Analysis in Speech Synthesis Device Testing
Integration of IEEE Std. 1149.1 and Mixed-Signal Test Architectures
Seamless Physical Implementation of ASIC Hierarchical Integrated Scan Architecture
An industrial case study for X-canceling MISR
The DFT challenges and solutions for the ARM® Cortex™-A15 Microprocessor
Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base
Reliability and Electrical Properties of Gate Oxide Shorts in CMOS ICs
International Test Conference - Copyright
A new framework for generating optimal March tests for memory arrays
Contactless digital testing of IC pin leakage currents
Optimal INL/DNL testing of A/D converters using a linear model
Built-In Test Compiler in an ASIC Environment
Testing Functional Faults in Digital Systems Described by Register Transfer Language
An Operationally Efficient Scheme for Exhaustive Test-Pattern Generation Using Linear Codes
Test methodology for Freescale's high performance e600 core based on PowerPC© instruction set architecture
ECC-On-SIMM Test Challenges
Safety Design of a Convolutional Neural Network Accelerator with Error Localization and Correction
Innovative techniques for improved testability
Chroma Voltmeter Measurement Techniques for Analog LSI Devices
Testability features of the first-generation CELL processor
Probeless DfT Scheme for Testing 20k I/Os of an Automotive Micro-LED Headlamp Driver IC
On-line fault detection in DSP circuits using extrapolated checksums with minimal test points
Improvement of the Defect Level of Micro-computer LSI Testing
Reliability Modeling and Mitigation for Embedded Memories
Scan vs. functional testing - a comparative effectiveness study on Motorola's MMC2107 TM
Changing our Path to High Level ATPG
Test methodology for PCHB/PCFB Asynchronous Circuits
Synthesis of Self-Testing Finite State Machines from High-Level Specifications
Timing-Driven Test Point Insertion for Full-Scan and Partial-Scan BIST
An Off-chip I DDQ Current Measurement Unit for Telecommunication ASICs
Persistent High-Bandwidth IJTAG Data Delivery
Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications
Lithography aware critical area estimation and yield analysis
Precision audio nulling instrumentation achieves near -140dB measurements in a production environment
Modeling and testing the Gekko microprocessor, an IBM PowerPC derivative for Nintendo
Towards effective and compression-friendly test of memory interface logic
Test Programming Environment in a Modular, Open Architecture Test System
Triplet Convolutional Networks for Classifying Mixed-Type WBM Patterns with Noisy Labels
A Hybrid Coding Strategy For Optimized Test Data Compression
Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications
A Serially Addressable, Flexible Current Monitor for Test Fixture Based I DDQ /I SSQ Testing
The rise and fall of the ATE industry
Stress profile derivation-an empirical approach
Self-Test Scheduling with Bounded Test Execution
Non-contact Testing for SoC and RCP (SIPs) at Advanced Nodes
Towards a standard for embedded core test: an example
Failure Mechanisms in MEMS
Design for (physical) debug for silicon microsurgery and probing of flip-chip packaged integrated circuits
I DDQ test using built-in current sensing of supply line voltage drop
Automated synthesis of large phase shifters for built-in self-test
Ultra Low Cost Linear Testing
RF Testing on a Mixed Signal Tester
Detecting Delay Flaws by Very-Low-Voltage Testing
The PIN Module: A High Accuracy Concept in Very High Frequency Pin Electronics
Low Cost Test System Speeds Design Verification for Custom VLSI
I DDQ and AC Scan: The War Against Unmodelled Defects
Compact Functional Test Generation for Memristive Deep Learning Implementations using Approximate Gradient Ranking
The CAT-exact data transfer to DDS-generated clock domains in a single-chip modular solution
Commercial Design Verification: Methodology and Tools
Experiences with Implementation of I DDQ Test for Identification and Automotive Products
ATPG in practical and non-traditional applications
On the saturation of n-detection test sets with increased n
Defect-oriented testing of mixed-signal ICs: some industrial experience
On the use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs
DUT Capture Using Simultaneous Logic Acquisition
XMAX: a practical and efficient compression architecture
Impact of Multiple-Detect Test Patterns on Product Quality
Design and Test in the Universities
Pre-bond probing of TSVs in 3D stacked ICs
Efficient UBIST implementation for microprocessor sequencing parts
A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits
Optimization trade-offs for vector volume and test power
Scan chain design for test time reduction in core-based ICs
Structured Programming and the I.C. Test Engineer
New Test Paradigms for Yield and Manufacturability
Circular BIST with Partial Scan
Effective Path Selection for Delay Fault Testing of Sequential Circuits
Test features of the MC145472 ISDN U-transceivers
Reducing test data volume using external/LBIST hybrid test patterns
Logic Diagnosis-Diversion or Necessity?
A Serial-Scan Test-Vector-Compression Methodology
Electromigration Effects in VLSI Due to Various Current Types
2007 IEEE International Test Conference, ITC 2007, Santa Clara, California, USA, October 21-26, 2007
Test Vector Generation for Parametric Path Delay Faults
Fastpath: A Path-Delay Test Generator for Standard Scan Designs
The Evolving Role of Testing in Open Systems Standards
A Pursuit of Superior Cost-Per-Performance in General-Purpose Linear IC Test System
Filtering Methods for Fast Ultra-Low Distortion Measurements
Fully X-tolerant combinational scan compression
Challenging the "High Performance - High Cost" Paradigm in Test
Position Statement: ITC93 Boundary-Scan Panel
Test economics for homogeneous manycore systems
Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001
Correlations between path delays and the accuracy of performance prediction
A Fast Testing Method for Sequential Circuits at the State Trasition Level
Concurrent Test Generation Using AI Techniques
Dude! Where's my data? - Cracking Open the Hermetically Sealed Tester
SOC test: the devil is in the details of integration/implementation
Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier
Design for Test of Mbit DRAMs
A Code-less BIST Processor for Embedded Test and in-system configuration of Boards and Systems
Study on the Costs of On-site VLSI Testing
Fault simulation of logic designs on parallel processors with distributed memory
Parameter Monitoring: Advantages and Pitfalls
National Science Foundation Workshop on Future Research Directions in Testing of Electronic Circuits and Systems: executive summary of workshop report
Parametric Testing of Optical Interfaces
Investigation into voltage and process variation-aware manufacturing test
A Design for Machines with Built-In Tolerance to Soft Errors
Estimating the Failures and Silent Errors Rates of CPUs Across ISAs and Microarchitectures
Built-in Self Test for Error Vector Magnitude measurement of RF transceiver
Testability preserving transformations in multi-level logic synthesis
Logic Partitioning and Resynthesis for Testability
Challenges of high supply currents during VLSI test
Calculatoin of Multiple Sets of Weights for Weighted-Random Testing
A Novel Low-Cost Approach to MCM Interconnect Test
Design of Test Pattern Generators for Built-In Test
Challenges and best practices in advanced silicon debug
ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction
Testing for Coupled Cells in Random-Access Memories
Testing the design: the evolution of test simulation
Auto-Probing on the L200 Functional Tester
Achieving Accurate Timing Measurements on TTL/CMOS Devices in a Manufacturing/Incoming Inspection Environment
Planning for Test of Custom IC Devices
Fine-Grained Built-In Self-Repair Techniques for NAND Flash Memories
Test Quality of Asynchronous Circuits: A Defect-oriented Evaluation
Robustly Scan-Testable CMOS Sequential Circuits
Critical parameters for high-performance dynamic response measurements
Systematic Hardware Error Identification and Calibration for Massive Multisite Testing
C : An Important Tool for Test Software Development
Adapting JTAG for AC Interconnect Testing
QuEST: Quantitative Entropy based Security and Trojan Detection Framework for Confidentiality Verification
CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing
AC Test Quality: Beyond Transition Fault Coverage
Application of Built in Self-Test for Interconnect Testing of FPGAs
Mixed-signal ATE technology and its impact on today's electronic system
Scan-Based Test Chip Design with XOR-based C-testable Functional Blocks
Testing of UltraSPARC T1 Microprocessor and its Challenges
Boundary Scan: The ATE Vendors' View
Augmenting Boundary-Scan Tests for Enhanced Defect Coverage
Signature Analysis for IC Diagnosis and Failure Analysis
Methodology for fault grading high speed I/O interfaces used in complex Graphics Processing Unit
ASIC Test Cost/Strategy Trade-offs
Enhanced Data Pattern to Detect Defects in Flash Memory Address Decoder
An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes
I DDQ Characterization in Submicron CMOS
An Integration of Memory-Based Analog Signal Generation into Current DFT Architectures
Simultaneous Bidirectional Test Data Flow for a Low-cost Wafer Test Strategy
Analysis of cellular automata used as pseudorandom pattern generators
Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture
Agent Based DBIST/DBISR And Its Web/Wireless Management
An Efficient Pruning Method to Guide the Search of Precision Tests in Statistical Timing Space
An Automated Laser Prober to Determine VLSI Internal Node Logic States
Known Godd Die for MCMs: Enabling Technologies
Augmenting board test coverage with new intel powered opens boundary scan instruction
Defect Coverage of Boundary-Scan Tests: What does it mean when a Boundary-Scan test passes?
Optimizing the Use of Simulations for Commissioning with Systems Engineering Principles and Objective Analysis
Analysis and Simulation of Parallel Signature Analyzers
Concurrent built in test and tuning of beamforming MIMO systems using learning assisted performance optimization
Analog Fault Simulation: Key to Product Quality, or a Foot in the Door
Putting the Squeeze on Test Sequences
Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs
IEEE P1581 drastically simplifies connectivity test for memory devices
A wideband low-noise ATE-based method for measuring jitter in GHz signals
Jitter Test in Production for High Speed Serial Links
High-Performance CMOS-Based VLSI Testers: Timing Control and Compensation
The Pseudo-Exhaustive Test of Sequential Circuits
Recycled Analog and Mixed Signal Chip Detection at Zero Cost Using LDO Degradation
Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything?
A Methodology to Design Efficient BIST Test Pattern Generators
Boundary scan test used at board level: moving towards reality
The Economics of Harm Prevention through Design for Testability
A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test
Embedded deterministic test points for compact cell-aware tests
Jitter transformations in measurement instruments and discrepancies between measurement results
: Experiments on Aliasing in Signature Analysis Registers
Automatic electro-optical testing of automobile dashboard displays in a factory environment
A Correlation Study of Modern Techniques Applied to the Testing of Telecommunication Circuits
Low-capture-power test generation for scan-based at-speed testing
Functional-Level Test Generation for Stuck-Open Faults in CMOS VLSI
Architecting Millisecond Test Solutions for Wireless Phone RFIC's
An improved fault diagnosis algorithm based on path tracing with dynamic circuit extraction
IC Quality Control by the User
A Universal Framework for Managed Built-in Test
How Seriously Do You Take Your Possible-Detect Faults?
OCI: Open Compression Interface
Scalable and efficient integrated test architecture
Computer-Guided Probing Techniques
The Economics of the Memory Tester Decision
Enabling In-Field Parametric Testing for RISC-V Cores
A Comprehensive Approach to Assessing and Analyzing 1149.1 Test Logic
Self-Learning Health-Status Analysis for a Core Router System
Threading of Multiple Scan Paths in a VLSI Circuit
The Effect of Periof Generation Techniques on Period Resolution and Waveform Jitter in VLSI Test Systems
On the Design of Random Pattern Testable PLAs
Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism
On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs
Testability Features of the Alpha 21364 Microprocessor
Runtime Fault Diagnostics for GPU Tensor Cores
I DDQ Testing in CMOS Digital ASIC's - Putting it All Together
In-System Testing of Cache Memories
Power Supply Ramping for Quasi-static Testing of PLLs
Commanded Test Access Port operations
FPGA Interconnect Delay Fault Testing
Test implications of lead-free implementation in a high-volume manufacturing environment
Main Frame Diagnosis Support System
Test yield estimation for analog/RF circuits over multiple correlated measurements
Design Verification, Product Characterization and Production Testing of Hybrids and Printed Circuit Cards Using High-Sensitivity Thermography Systems
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
Signature Testing with Guaranteed Bounds for Fault Coverage
DFT Strategy for Intel Microprocessors
Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis
Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model
Fast extended test access via JTAG and FPGAs
An introduction to area array probing
CMOS IC reliability indicators and burn-in economics
Compaction of Functional Broadside Tests for Path Delay Faults Using Clusters of Propagation Lines
An Integrated Approach to Yield Loss Characterization
Systematic Defects in Deep Sub-Micron Technologies
Testing mixed signal SOCs
Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning
Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions
Resiliency of automotive object detection networks on GPU architectures
Challenges in AC Testability : Testing Gigahertz Logic
A BIST Solution for The Test of I/O Speed
Online slack-time binning for IO-registered die-to-die interconnects
A Persistent Diagnostic Technique for Unstable Defects
Functional Test Pattern Generation for Integrated Circuits
Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998
A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design
Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm
Software Test Data Generation Using the Chaining Approach
An analysis of power reduction techniques in scan testing
Defect Analysis for FeFETs using a Compact Model
Introduction to Applications and Industries for Microelectromechanical Systems (MEMS)
Timing Accuracy Measurement System
ANGEL : Algorithmic Pattern Generation System
Current ratios: a self-scaling technique for production IDDQ testing
An innovative Strategy to Quickly Grade Functional Test Programs
Is DFT right for you?
Selective and Accurate Fail Data Capture in Compression Environment for Volume Diagnostics
A Unified Framework for Design Validation and Manufacturing Test
Error-locality-aware linear coding to correct multi-bit upsets in SRAMs
Color reproduction test for CCD image sensors
JTAG-based vector and chain management for system test
Wafer Level Stress: Enabling Zero Defect Quality for Automotive Microcontrollers without Package Burn-In
Realizing a High Measure of Confidence for Defect Level Analysis of Random Testing
Feed Forward Test Methodology Utilizing Device Identification
Two-Dimensional Test Data Decompressor for Multiple Scan Designs
Test chip design for optimal cell-aware diagnosability
Backside E-Beam Probing on Nano scale devices
The effects of defects on high-speed boards
Design of a Class of Self-Exercising Combinational Circuits
A unified method for parametric fault characterization of post-bond TSVs
Security Compliance Analysis of Reconfigurable Scan Networks
Graph Attention Networks Based Fault Prediction Framework for Functional Safety Verification
A case study on the implementation of the Illinois Scan Architecture
Optical Diagnostics for IBM POWER6- Microprocessor
Diagnosis of Bridging Faults in Sequential Circuits Using Adaptive Simulation, State Storage, and Path-Tracing
IEEE 1149 Standards - Changing Testing, Silicon to Systems
Maximal Diagnosis for Wiring Networks
Early Capture for Boundary Scan Timing Measurements
Testing High Resolution ADCs with Low Resolution/Accuracy Deterministic Dynamic Element Matched DACs
Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan
Built in self repair for embedded high density SRAM
Checking sequence generation for asynchronous sequential elements
Contactless pre-bond TSV fault diagnosis using duty-cycle detectors and ring oscillators
Impedance Profile of a Commercial Power Grid and Test System
Algorithms for Switch Level Delay Fault Simulation
High-Speed In-Circuit Testing
Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCs
Event-driven framework for configurable runtime system observability for SOC designs
Test Pattern Generation for Circuits with Asynchronous Signals Based on Scan
DFT guidance through RTL test justification and propagation analysis
Functional test of small-delay faults using SAT and Craig interpolation
Hierarchical Test Program Development for Scan Testable Circuits
IC laser trimming speed-up through wafer-level spatial correlation modeling
Built-In Self-Diagnostic Read-Only-Memories
Effective Implementation of Statistical Process Control in an Integrated Circuit Test Environment
SiP-TAP: JTAG for SiP
Voltage transient detection and induction for debug and test
Hybrid selector for high-X scan compression
A General Method for Increasing Converter Accuracy and Resolution
Impact of Mixed-Mode Self Test on Life Cycle Cost of VLSI Based Design
Differential Virtual Instrumentation with Continuously
Spice up your life: simulate mixed-signal ICs!
Implementation of an Economic Jitter Compliance Test for a Multi-Gigabit Device on ATE
Integrating Boundary Scan into Multi-GHz I/O Circuitry
Safety analysis for integrated circuits in the context of hybrid systems
Compression based on deterministic vector clustering of incompatible test cubes
Pentium ® Pro Processor Design for Test and Debug
Wafer Map Defect Classification Based on the Fusion of Pattern and Pixel Information
Time-Slicing Soft Error Resilience in Microprocessors for Reliable and Energy-Efficient Execution
Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard
March-based RAM diagnosis algorithms for stuck-at and coupling faults
Current signatures: application [to CMOS]
An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design
Wafer Defect Pattern Classification with Explainable-Decision Tree Technique
DFT: Profit or Loss -- A Position Paper
Automatic Modelling of MOS Transistor Networks for Test Pattern Generation
How real is the new SIA roadmap for mixed-signal test equipment?
A Little DFT Goes a Long Way When Testing Multi-Gb/s I/O Signals
Mitigating voltage droop during scan with variable shift frequency
Algorithmic Extraction of BSDL from 1149.1-compliant Sample ICs
Trends in Testing Integrated Circuits
GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification
Development of an ATE Test Station for Mixed CATV/TELCO Products
A New Approach to DC Parameter Measurement in the Day of VLSI
A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test
B-algorithm: A Behavioral-Test Generation Algorithm
The capability of capability indices with an application to guardbanding in a test environment
Practical Considerations for Mixed-Signal Test Bus
An advanced optical diagnostic technique of IBM z990 eServer microprocessor
An Experimental Chip to Evaluate Test Techniques: Experiment Results
Can Concurrent Checkers Help BIST?
Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability
MEMS Fabrication
Accurate full spectrum test robust to simultaneous non-coherent sampling and amplitude clipping
Mixed-Mode BIST Using Embedded Processors
Logic mapping on a microprocessor
Using Distinguishing Bits to Improve Chain Diagnosis Coverage for Silicon Defects
Physical Principles of Interface Design
Fault Location with Current Monitoring
Application of deterministic logic BIST on industrial circuits
Development of Fault Model and Test Algorithms for Embedded DRAMs
H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial Designs
Reconfigurable Resource Architecture Improves VLSI Tester Utilization
A Practical Online Error Detection Method for Functional Safety Using Three-Site Implications
A new multiple weight set calculation algorithm
The test and debug features of the AMD-K7 microprocessor
An On-Line Data Collection and Analysis System for VLSI Devices at Wafer Probe and Final Test
BIST for Embedded Static RAMs with Coverage Calculation
Concurrent Off-Phase Built-in Self-Test of Dormant Logic
Improved volume diagnosis throughput using dynamic design partitioning
Low power BIST design by hypergraph partitioning: methodology and architectures
An On-Line Self-Testing Switched-Current Integrator
Scan test sequencing hardware for structural test
Testing beyond the green light
A Sequential Circuit Fault Simulation by Surrogate Fault Propagation
A Test System tor High Density and High Speed Digital Board
An Integrated Approach for Analog Ciruit Testing with a Minmum Number of Detected Parameters
Iterative Test Generation for Gate-Exhaustive Faults to Cover the Sites of Undetectable Target Faults
Test Time Impact of Redundancy Repair in Embedded Flash Memory
Limited access testing of analog circuits: handling tolerances
Relevant Signals and Devices for Failure Analysis of Analog and Mixed-signal Circuits
Testing beyond EPA: TDF methodology solutions matrix
Particulate failures for surface-micromachined MEMS
OLDEVDTP: A Novel Environment for Off-Line Debugging of VLSI Device Test Programs
Electrical package defect testing for volume production
Visualizing Test Information: A Novel Approach for Improving Testability
Catch the Ground Bounce Before It Hits your System
Automatic diagnostic tool for Analog-Mixed Signal and RF load boards
A Telecommunications Line Interface Test System Architecture
Two-dimensional test data compression for scan-based deterministic BIST
Cache RAM inductive fault analysis with fab defect modeling
High-level ATPG: a real topic or an academic amusement?
Compensation of Transmission Line Loss for Gbit/s Test on ATEs
A Method of Flexible Catch RAM Display for Memory Testing
An Interactive Sequential Test Pattern Generation System
Robust Tests for Parity Trees
On the Initialization of Sequential Circuits
A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs
Financial Implications of a Detailed Analysis of Test Floor Operations
Sequencer Per Pin test system architecture
Single-fault fault collapsing analysis in sequential logic circuits