yusuke1997/dblp-id-title huggingface dataset:
Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families
Reliability and Yield: A Joint Defect-Oriented Approach
Hierarchical extraction of critical area for shorts in very large ICs
Development of the Special Software Tools for the Defect/Fault Analysis in the Complex Gates from Standard Cell Library
Test Sequence Generation for Realistic Faults in CMOS ICs Based on Standard Cell Library
Low Power Dissipation in BIST Schemes for Modified Booth Multipliers
23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA
Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors
Software-based on-chip thermal sensor calibration for DVFS-enabled many-core systems
On the Test and Diagnosis of the Perfect Shuffle
Usability-based Cross-Layer Reliability Evaluation of Image Processing Applications
X ray nanoprobe for fault attacks and circuit edits on 28-nm integrated circuits
Reduced Precision Checking for a Floating Point Adder
Prolongation of Lifetime and the Evaluation Method of Dependable SSD
Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results
Hypervisor-Based Virtual Hardware for Fault Tolerance in COTS Processors Targeting Space Applications
1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 20-22 October 1997, Paris, France
Utilizing spares in multichip modules for the dual function of fault coverage and fault diagnosis
Selecting High-Quality Delay Tests for Manufacturing Test and Debug
Predicting the Yield Efficacy of a Defect-Tolerant Embedded Core
Performance Evaluation of Checksum-Based ABFT
Post-Quantum Cryptography: Challenges and Opportunities for Robust and Secure HW Design
Reliability Evaluation of Pruned Neural Networks against Errors on Parameters
Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment
Hardening a Real-Time Operating System for a Dependable RISC-V System-on-Chip
CROWNE: Current Ratio Outliers with Neighbor Estimator
Low Power BIST Based on Scan Partitioning
Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks
Special Session: In-Field ML-Assisted Intermittent Fault Localization and Management in RISC-V SoCs
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, Cambridge, United Kingdom, October 23-25, 2017
A novel low-overhead fault tolerant parallel-pipelined FFT design
Online Fault Detection in Reversible Logic
A Genetic Approach for the Reconfiguration of Degradable Processor Arrays
Improving Memory Repair by Selective Row Partitioning
Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects
Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS)
On the Error Effects of Random Clock Shifts in Quantum-Dot Cellular Automata Circuits
Defect and Fault Tolerant Scan Chains
Testing Digital Circuits with Constraints
Robustness improvement of an SRAM cell against laser-induced fault injection
At-Speed Functional Verification of Programmable Devices
Decimal Hamming: A Software-Implemented Technique to Cope with Soft Errors
A Low Capture Power Oriented X-filling Method Using Partial MaxSAT Iteratively
Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems
Data Dependent Jitter Characterization Based on Fourier Analysis
Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs
Emulation-Based Design Errors Identification
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits
An IDDQ Sensor for Concurrent Timing Error Detection
A unified approach for off-line and on-line testing of VLSI systems
Defects, Yield, and Design in Sublithographic Nano-electronics
REMORA: A hybrid low-cost soft-error reliable fault tolerant architecture
Exploring error-tolerant low-power multiple-output read scheme for memristor-based memory arrays
Designing Networks with Error Detection Properties through the Fault-Error Relation
Special Session: Effective Design, Modeling and Testing Techniques for Digital Computing-in Memories with MAC Function
On The Yield of Compiler-Based eSRAMs
Self-Reconfigurable Mesh Array System on FPGA
HW/SW Co-Design of a Reliable Deep Space System Exploiting Application-Profiled RAM Scrubbing
Switch level hot-carrier reliability enhancement of VLSI circuits
Industrial Approach for Dependability
Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique
Special Session Paper: Formal Verification Techniques and Reliability Methods for RRAM-based Computing-in-Memory
Fail-Safe Synchronization Circuit for Duplicated Systems
Yield Prediction by Sampling with the EYES Tool
Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults
A Comparison of Efficient Dot Throwing and Shape Shifting Extra Material Critical Area Estimation
Reliability Analysis of Self-Repairable MEMS Accelerometer
BIST Architectures Selection Based on Behavioral Testing
On the Criticality of Caches in Fault-Tolerant Processors for Space
A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths
Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits
MetaFS: Model-driven Fault Simulation Framework
Characterization of low power radiation-hard reed-solomon code protected serializers in 65-nm for HEP experiments electronics
Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding
Reducing Fault Sensitivity of Microprocessor-Based Systems by Modifying Workload Structure
Black-Box IP Validation with the SafeTI Traffic Injector: A Success Story
Model-Based Analysis of Single-Event Upset (SEU) Vulnerability of 6T SRAM Using FinFET Technologies
Balancing of Fault Tolerance in the New Version of the FERMI Channel Chip: a Functional Evaluation
Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks
Quest for a quantum search algorithm for testing stuck-at faults in digital circuits
Data Learning Techniques for Functional/System Fmax Prediction
Yield - Performance Tradeoffs for VLSI Processors with Partially Good Two-Level On-Chip Caches
Computing Cache Vulnerability to Transient Errors and Its Implication
A Hardware-Oriented Fault-Tolerant Routing Algorithm for Irregular 2D-Mesh Network-on-Chip without Virtual Channels
Self-Checking 1-out-of-n CMOS Current-Mode Checker
A Self-Correcting Active Pixel Camera
Binning for IC Quality: Experimental Studies on the SEMATECH Data
A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI
Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems
Special Session Paper: Simulation Methodologies and Experiments for Reliability Analysis of Devices in Radiation Harsh Environments
Uncovering hidden vulnerabilities in CNNs through evolutionary-based Image Test Libraries
A Schematic-Based Extraction Methodology for Dislocation Defects in Analog/Mixed-Signal Devices
Enhancing Silicon Debug via Periodic Monitoring
Validating fault tolerant designs using laser fault injection (LFI)
Hybrid On-Line Self-Test Strategy for Dual-Core Lockstep Processors
Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector
A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities
Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models
Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams
Predictive LBIST model and partial ATPG for seed extraction
On the resilience of representative and novel data formats in CNNs
On the Complexity of Sequential Testing in Configurable FPGAs
On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS
Low DPM: Why Do We Need it and What Does it Cost!
Artificial intelligence based task mapping and pipelined scheduling for checkpointing on real time systems with imperfect fault detection
Fast Signature Simulation for PPSFP Simulators
SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000
Yield Analysis of Compiler-Based Arrays of Embedded SRAMs
Improving test compression with multiple-polynomial LFSRs
Thread-level Parallelism in Fault Simulation of Deep Neural Networks on Multi-Processor Systems
On-Line Identification of Faults in Fault-Tolerant Imagers
Level-Hybrid Optoelectronic TESH Interconnection Network
Dependable real-time task execution scheme for a many-core platform
Fault injection in the process descriptor of a Unix-based operating system
A Novel Topology-Independent Router Architecture to Enhance Reliability and Performance of Networks-on-Chip
How Does Resource Utilization Affect Fault Tolerance?
Securing Scan Design Using Lock and Key Technique
Impact of Layers Selective Approximation on CNNs Reliability and Performance
A Method to Model Statistical Path Delays for Accurate Defect Coverage
Current Testing Viability in Dynamic CMOS Circuits
Guiding Genetic Algorithms using importance measures for reliable design of embedded systems
Defect-Tolerant Hybrid CMOS/Nanoelectronic Circuits
Special Session: Overcoming Transient Faults and Aging Effects in Digital Computing-in-Memory Architectures: Detection, Tolerance, and Mitigation Strategies
Application of a yield model merging critical areas and defectivity to industrial products
Quadruple Time Redundancy Adders
Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When do smaller less reliable devices make sense?
On the Reconfiguration of Degradable VLSI/WSI Arrays
Constrained ATPG for Broadside Transition Testing
Special Session: A Mixed Simulation-, Emulation-, and Formal-Based Fault Analysis Methodology for RISC-V
Testing of Switch Blocks in Three-Dimensional FPGA
A Fast Minimum Layout Perturbation Algorithm for Electromigration Reliability Enhancement
Built-in Self-Reconfiguring Systems for Mesh-Connected Processor Arrays with Spares on Two Rows/Columns
Low-Density Triple-Erasure Correcting Codes for Dependable Distributed Storage Systems
On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors
Defect Avoidance in a 3-D Heterogeneous Sensor
Efficient Two-Dimensional Error Codes for Multiple Bit Upsets Mitigation in Memory
A Machine Learning-driven EDAC Method for Space-Application Memory
Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults
On-chip error correction with unreliable decoders: Fundamental physical limits
Defect Analysis and a New Fault Model for Multi-port SRAMs
F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments
Selective Hardening of NanoPLA Circuits
Tree Checkers for Applications with Low Power-Delay Requirements
IntelliCAN: Attack-resilient Controller Area Network (CAN) for secure automobiles
State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines
A Speed-Dependent Approach for Delta IDDQ Implementation
Designing and implementing a Malicious 8051 processor
Zero-Memory-Overhead Clipping-Based Fault Tolerance for LSTM Deep Neural Networks
Reducing the performance overhead of resilient CMPs with substitutable resources
Testability Analysis of IDDQ Testing with Large Threshold Value
A Structural Approach for Space Compaction for Sequential Circuits
Design of Self-Parity Combinational Circuits for Self-testing and On-line Detection
Probabilistic Identification of Critical Components for Circuit Delays
Modelling a CNTFET with Undeposited CNT Defects
Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks
Layer Reassignment for Antenna Effect Minimization in 3-Layer Channel Routing
Security methods in fault tolerant modified line graph based networks
A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch
Accurate calculation of SET propagation probability for hardening
A State Assignment Method to Improve Transition Fault Coverage for Controllers
A Placement-Aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology
Neural Networks-Based Parametric Testing of Analog IC
Integration of DFM Techniques and Design Automation
Modeling and Evaluation of Threshold Defect Tolerance
The Impact of Faults on DNNs: A Case Study
Rebooting Computing: The Challenges for Test and Reliability
Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit
Aging Effects On Clock Gated Memory Phase Paths
Topological Optimization of PLAs for Yield Enhancement
GF-Flush: A GF(2) Algebraic Attack on Dynamically Secured Scan Chains
Roundoff Error-Free Tests in Algorithm-Based Fault Tolerant Matrix Operations on 2-D Processor Arrays
Characteristics of Fault Diagnosis for Analog Circuits Based on Preset Test
2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015, Amherst, MA, USA, October 12-14, 2015
Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR)
A Tunable Single Event Transient Filter Based on Digitally Controlled Capacitive Delay Cells
Testing for Path Delay Faults Using Test Points
Testing and Defect Tolerance: A Rent's Rule Based Analysis and Implications on Nanoelectronics
Wafer-scale integration defect avoidance tradeoffs between laser links and Omega network switching
A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS
Using RISC-V Extensions to Support Software-Implemented Hardware Fault Tolerance
18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings
Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes
A BIST approach for counterfeit circuit detection based on NBTI degradation
CodSim -- A Combined Delay Fault Simulator
An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers
BTI aware thermal management for reliable DVFS designs
TEh Reliability of the Integrated Circuits in Automotive Industry
Using the Berlekamp-Massey algorithm to obtain LFSR characteristic polynomials for TPG
Recovery Method for a Laser Array Failure on Dynamic Optically Reconfigurable Gate Arrays
Combined on-line lifetime-energy optimization for asymmetric multicores
System Level Policies for Fault Tolerance Issues in the FERMI Project
Hardware Accelerator Design with Supervised Machine Learning for Solar Particle Event Prediction
FPGA Design for Decimeter Scale Integration (DMSI)
Machine learning based test pattern analysis for localizing critical power activity areas
On the Reliability of Convolutional Neural Network Implementation on SRAM-based FPGA
In-field functional test programs development flow for embedded FPUs
A low power architecture for online detection of execution errors in SMT processors
Scheduling Policies for Fault Tolerance in a VLSI Processor
Yield projection from defect monitors: the influence of gross defects [BiCMOS process]
Optimization of Self Checking FIR filters by means of Fault Injection Analysis
RASSS: A perfidy-aware protocol for designing trustworthy distributed systems
Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling
Challenges of Reliability Assessment and Enhancement in Autonomous Systems
Time-Shared Modular Redundancy for Fault-Tolerant FFT Processors
DaemonGuard: O/S-assisted selective software-based Self-Testing for multi-core systems
Automated integration of fault injection into the ASIC design flow
Testing of Computing-In Memories: Faults, Test Algorithms, and Design-for-Testability
On the Modeling and Analysis of Jitter in ATE Using Matlab
Resistive RAM SET and RESET Switching Voltage Evaluation as an Entropy Source for Random Number Generation
Regressive Testing for System-on-Chip with Unknown-Good-Yield
Fine-Grained Vulnerability Analysis of Resource Constrained Neural Inference Accelerators
A Power Transmission Line Fault Distance Estimation VLSI Chip: Design and Defect Tolerance
Efficient Loop Abort Fault Attacks on Supersingular Isogeny based Key Exchange (SIKE)
Heterogeneous Redundancy for Fault and Defect Tolerance with Complexity Independent Area Overhead
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits
Analysis of Proton-induced Single Event Effect in the On-Chip Memory of Embedded Process
Path Delay Fault Testability Analysis
A Self Checking Reed Solomon Encoder: Design and Analysis
A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction
Evaluation of Hiding-based Countermeasures against Deep Learning Side Channel Attacks with Pre-trained Networks
Towards reliability and performance-aware Wireless Network-on-Chip design
Physics-Informed Machine Learning for DRAM Error Modeling
Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines
A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate
Evaluating the Resilience of Parallel Applications
SEU Evaluation of Hardened-by-Replication Software in RISC- V Soft Processor
Improved correction for hot pixels in digital imagers
Optimal Test Set Selection for Fault Diagnosis Improvement
Reliable Classification with Ensemble Convolutional Neural Networks
Efficient Determination of Fault Criticality for Manufacturing Test Set Optimization
Front-end Electronics in the Radiation Environment of LHC
The Other Side of the Timing Equation: a Result of Clock Faults
Testing Reversible 1D Arrays for Molecular QCA
Threshold Voltage Extraction Using Static NBTI Aging
A General Method to Design and Reconfigure Loop-Based Linear Arrays
Improving a Test Set to Cover Test Holes by Detecting Gate-Exhaustive Faults
Efficient Critical Area Algorithms and Their Application to Yield Improvement and Test Strategies
An ILP Formulation for Yield-driven Architectural Synthesis
Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies
Cost Models for Large File Memory DRAMs with ECC and Bad Block Marking
ATE-Amenable Test Data Compression with No Cyclic Scan
Lifetime memory reliability data from the field
Fault Diagnosis of Analog Circuits by Operation-Region Model and X-Y Zoning Method
Analysis and Testing for Error Tolerant Motion Estimation
Soft Error Study on Advanced Process Node DRAMs at Component and System Level
Fault-Tolerant Hierarchical Interconnection Networks Constructed by Additional Bypass Linking with Graph-Node Coloring
Scan-Based Delay Fault Tests for Diagnosis of Transition Faults
Generation and compaction of mixed broadside and skewed-load n-detection test sets for transition faults
Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs
A Polarity-Driven Radiation-Hardened Latch design for Single Event Upset Tolerance
Production Yield and Self-Configuration in the Future Massively Defective Nanochips
A data mining approach to incremental adaptive functional diagnosis
An instance-based SER analysis in the presence of PVTA variations
Co-Design and Refinement for Safety Critical Systems
A low overhead built-in delay testing with voltage and frequency adaptation for variation resilience
Designing for Yield: A Defect-Tolerant Approach to High-Level Synthesis
Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations
Safety Evaluation of NanoFabrics
Efficiency of Transient Bit-Flips Detection by Software Means: A Complete Study
On the Prediction of Hardware Security Properties of HLS Designs Using Graph Neural Networks
A scrubbing scheduling approach for reliable FPGA multicore processors with real-time constraints
Creating 35 mm Camera Active Pixel Sensors
Reliable Digital Circuits Design using Sigma-Delta Modulated Signals
Obtaining Microprocessor Vulnerability Factor Using Formal Methods
A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design
Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree
An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing Constraint
Exploiting an I-IP for In-Field SOC Test
Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based Systems
Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects
Test Cost Minimization for Hybrid Bist
On the Reliable Performance of Sequential Adders for Soft Computing
Are Robust Circuits Really Robust?
Amalgamated q-ary codes for multi-level flash memories
High-level Synthesis of Data Paths with Concurrent Error Detection
Analysis of Single Event Upsets Based on Digital Cameras with Very Small Pixels
Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects
A mechanism to verify cache coherence transactions in multicore systems
IC Critical Volume Calculation through Ray-Casting of CSG Trees
Optimizing High-Level Synthesis for Self-Checking Arithmetic Circuits
RAMSES: A Fast Memory Fault Simulator
ROM-Based Synthesis of Fault-Tolerant Controllers
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
Fast Run-Time Fault Location in Dependable FPGA-Based Applications
IC HTOL Test Stress Condition Optimization
AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects
Understanding time-varying vulnerability accross GPU Program Lifetime
A Highly Testable 1-out-of-3 CMOS Checker
Using Statistical Transformations to Improve Compression for Linear Decompressors
Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules
EVM measurement of RF ZigBee transceivers using standard digital ATE
Design of Fault-Tolerant Solid State Mass Memory
A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks
Reliable PUF design using failure patterns from time-controlled power gating
Fast and Low-Cost Clock Deskew Buffer
Reliability analysis of combinational circuits with the influences of noise and single-event transients
A Yield Study of VLSI Adders
Implicit Critical PDF Test Generation with Maximal Test Efficiency
Protecting RSA Hardware Accelerators against Differential Fault Analysis through Residue Checking
Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience
Realistic Fault Analysis of CMOS Analog Building Blocks
Evaluating Read Disturb Effect on RRAM based AI Accelerator with Multilevel States and Input Voltages
Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based Design
RAM-Based Fault Tolerant State Machines for FPGAs
Evaluating the impact of spike and flicker noise in phase change memories
On the Feasibility of Built-In Self Repair for Logic Circuits
Large Language Model-Based Optimization for System-Level Test Program Generation
Self-Reconfiguration Scheme of 3D-Mesh Arrays
Performance of Deadlock-Free Adaptive Routing for Hierarchical Interconnection Network TESH
Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs
Targeting "Zero DPPM" - Can we ever get there?
2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2012, Austin, TX, USA, October 3-5, 2012
Implementing defect tolerance in 3D-ICs by exploiting degrees of freedom in assembly
An Integrated Design Approach for Self-Checking FPGAs
Adaptive fault simulation on many-core microprocessor systems
Nanofabric PLA architecture with Redundancy Enhancement
Zoom-In Feature for Storage-Based Logic Built-In Self-Test
Failure Factor Based Yield Enhancement for SRAM Designs
Catastrophic Defects Oriented Testability Analysis of a Class AB Amplifier
Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard
On the Complexity of Switch Programming in Fault-Tolerant-Configurable Chips
Toward the hardening of real-time operating systems