yusuke1997/dblp-id-title huggingface dataset:
The Intersection of Continuous Mixing Polyhedra and the Continuous Mixing Polyhedron with Flows
Configuration Balancing for Stochastic Requests
Solving LP Relaxations of Large-Scale Precedence Constrained Problems
On the Rank of Mixed 0, 1 Polyhedra
The Integrality Number of an Integer Program
Extended Formulations from Communication Protocols in Output-Efficient Time
Reducing the Large Set Threshold for Oertel's Conjecture on the Mixed-Integer Volume
Efficient Separation of RLT Cuts for Implicit and Explicit Bilinear Products
Integer and Unsplittable Multiflows in Series-Parallel Digraphs
Canceling most helpful total submodular cuts for submodular flow
On Implementing Push-Relabel Method for the Maximum Flow Problem
Two NP-Hardness Results for Preemptive Minsum Scheduling of Unrelated Parallel Machines
Approximation Algorithms for Single and Multi-Commodity Connected Facility Location
Ancestor Tree for Arbitrary Multi-Terminal Cut Functions
A Branch and Bound Algorithm for Max-Cut Based on Combining Semidefinite and Polyhedral Relaxations
Integer Plane Multiflow Maximisation: Flow-Cut Gap and One-Quarter-Approximation
Sequence Independent, Simultaneous and Multidimensional Lifting of Generalized Flow Covers for the Semi-Continuous Knapsack Problem with Generalized Upper Bounds Constraints
Degree Bounded Matroids and Submodular Flows
Nonlinear Formulations and Improved Randomized Approximation Algorithms for Multicut Problems
A Coordinatewise Domain Scaling Algorithm for M-convex Function Minimization
Angle of Arrival Estimation Using SRS in 5G NR Uplink Scenarios
Enhancing GNSS Tracking Resilience: An SDR-based Approach with Four-Element Antenna Array
ILEO-PNT Performance Metrics: An Extensive Comparison Between Different Constellations
Preliminary Results of 5G Direction of Arrival Estimation using In-Situ Calibration with USRP
Proceedings of Work-in-Progress in Hardware and Software for Location Computation (WIPHAL 2024), Antwerp, Belgium, June 25-27, 2024
Will Edge Computing Enable Location based Extended/Mixed Reality Mobile Gaming? Demystifying Trade-off of Execution Time vs. Energy Consumption
k-NN Empowered LoRaWAN Localization for Surface and Underground Scenarios: Work-in-Progress Report
Estimation of GPS Block IIF Attitude Using Residual Signals
Secure Communication via GNSS-based Key Synchronization
Proceedings of Work-in-Progress in Hardware and Software for Location Computation (WIPHAL 2023), Castellon, Spain, June 06-08, 2023
Indoor Asset Tracking in Dense Industrial Environments Using Low-cost Wireless Technologies
A Graph-Based Model for Leveraging Spatial and Fingerprint Similarity in RF-based Indoor Positioning
Datasets for Indoor Positioning with Single-AP Wi-Fi Fingerprinting
Robust Inertial Post-Processing Aided by Trimble ProPoint GNSS Technology for Urban HD Mapping and Autonomous Navigation
GNSS Jammer Localization in Urban Areas Based on Carrier-to-Noise Ratio and Classification Methods
Raw GNSS Data Analysis for the LEDSOL Project - Preliminary Results and Way Ahead
Improvement of Precise Vehicle Location in Urban Areas Using Video-based Photogrammetry
On the Residual Errors Mitigation in Single-Frequency Code-Based Real-Time PPP
Machine Learning Assessment of Anti-Spoofing Techniques for GNSS Receivers
Privacy-Constrained Location Accuracy in Cooperative Wearable Networks in Multi-Floor Buildings
Using Theories and Best Practices to Bridge the Phishing Gap
Establishment of Security Knowledge Sharing in Organisations: An Empirical Study
An Ontological Framework for a Cloud Forensic Environment
Using Phishing Experiments and Scenario-based Surveys to Understand Security Behaviours in Practice
Visual Triage of Email Network Narratives for Digital Investigations
European Information Security Multi-Conference (EISMC 2013), Lisbon, Portugal, May 8-10, 2013. Proceedings
MetaFor: Metadata Signatures for Automated Remote File Identification in Forensic Investigations
Shrinking the Authentication Footprint
Contextualized Security Interventions in Password Transmission Scenarios
National Password Security Survey: Results
Visualisation of allocated and unallocated data blocks in digital forensics
Developing and Testing a Visual Hash Scheme
Towards a Brain-Compatible Approach for Web-Based, Information Security Education
An Analysis of Information Security Vulnerabilities at Three Australian Government Organisations
Health Monitoring in Sport Through Wearable Sensors: A Novel Approach Based on Heart-Rate Variability
Distributed Speech and Speaker Identification System for Personalized Domotic Control
The Role of ICT in the Italian Health Care System
Webcam and Smartphone for the Measure of Spatial-Temporal Parameters of Gait for Treadmill Use
A Method for Computing the Functional Ambulation Profile Score by Stereophotogrammetric Data
Preliminary Study of a Novel Shelving System for Nutrition Habits Measuring
Surface EMG Fatigue Analysis by Means of Homomorphic Deconvolution
Stress Determent via QRS Complex Detection, Analysis and Pre-processing
sEMG-Based Evaluation of Muscle Recruitment Variability During Walking in Terms of Activation Length and Occurrence Frequency
Implementing Steganocryptography in Scanner and Angio-Scanner Medical Images
Piezoelectric Energy Harvesting on Running Shoes
An OpenCV Based Android Application for Drowsiness Detection on Mobile Devices
Development of an Algorithm and a Sensor to Monitor the Heart Rate by Volumetric Measurement Techniques
State of Charge Monitor for Wireless Sensor Networks
The Wireless Surface Electromyographic Technique for Supporting the Assessment of Fall Risk in Diabetic Neuropathic Patients
Stress-Aware Generation of Recommendations in a Driving System to Increase User Acceptance
A New Segmented-Beat Modulation Algorithm for Maternal ECG Estimation from Abdominal Recordings
Stress Map Based Information System for Increasing Road Safety
Analyzing Environmental Conditions and Vital Signs to Increase Healthy Living
Fall Detection Using Wearable Accelerometers and Smartphone
Mobile Networks for Biometric Data Analysis - mBiDA 2016, Ancona, Italy, October 30-31, 2016
A Non-Intrusive Model for the Collection and Analysis of Data, Feedback and Needs
An Analog Front-End for Combined EMG/ECG Wireless Sensors
High Performance Dynamic Threshold Calibration for RR Interval Detection in a QRS Complex Using a Parallel Programing
A Rule-Based Assistant System for Managing the Clothing Cycle
Step Length Estimation for Freezing of Gait Monitoring in Parkinsonian Patients
Asynchronous Macrocell Interconnect using MARBLE
An Implicit Method for Hazard-Free Two-Level Logic Minimization
A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication
AMULET3i Cache Architecture
Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK
16th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2010, Grenoble, France, 3-6 May 2010
Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems
Partial-Order Correctness-Preserving Properties of Delay-Insensitive Circuits
High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators
Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes
A 28nm Configurable Asynchronous SNN Accelerator with Energy-Efficient Learning
Elastic Bundles: Modelling and Synthesis of Asynchronous Circuits with Granular Rigidity
Variation Tolerant AFPGA Architecture
10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece
Optimised state assignment for asynchronous circuit synthesis
State Encoding of Asynchronous Controllers Using Pseudo-Boolean Optimization
Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes
Normal Form in DI-Algebra with Recursion
Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment
Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach
Low-energy asynchronous memory design
Symbolic Time Separation of Events
An Asynchronous Divider Implementation
ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic
A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors
Keynote: Variation-tolerant adaptive and resilient designs in nanoscale CMOS
An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery
A Digital Neurosynaptic Core Using Event-Driven QDI Circuits
Introduction to Octasic Asynchronous Processor Technology
Testing self-timed circuits using partial scan
Surfing Interconnect
Investigating the Effects of Permanent Faults in QDI Circuits: A Formal Perspective
A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems
A Dual-Mode Synchronous/Asynchronous CORDIC Processor
Fast Asynchronous Shift Register for Bit-Serial Communication
Activity-Monitoring Completion-Detection (AMCD): a new single rail approach to achieve self-timing
From Signal Transition Graphs to Timing Closure: Application to Bundled-Data Circuits
Design and Verification of Speed-Independent Multiphase Buck Controller
Cyclic Timing Path Evaluation Using Commercial Static Timing Analysis Algorithms
A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow
A hybrid asynchronous system design environment
Designing Asynchronous Standby Circuits for a Low-Power Pager
Minimum-Energy Sub-threshold Self-Timed Circuits: Design Methodology and a Case Study
An SET Tolerant Tree Arbiter Cell
Proximity Communication and Time
Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors
Finding Glitches Using Formal Methods
Core Interface Optimization for Multi-core Neuromorphic Processors
Analog Micropipeline Rings for High Precision Timing
A New CMOS Topology for Low-Voltage Null Convention Logic Gates Design
Projection: A Synthesis Technique for Concurrent Systems
Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template
cellTK: Automated Layout for Asynchronous Circuits with Nonstandard Cells
Point to Point GALS Interconnect
A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations
Adding Conditionality to Resilient Bundled-Data Designs
Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors
Case Study of Process Variation-Based Domain Partitioning of GPGPUs
Hardware Trojan Insertion and Detection in Asynchronous Circuits
Improving Smart Card Security Using Self-Timed Circuits
AMC: An Asynchronous Memory Compiler
ECSTAC: a fast asynchronous microprocessor
An Asynchronous High-Throughput Control Circuit For Proximity Communication
How fast will the flip flop?
Automated Microarchitectural Exploration for Achieving Throughput Targets in Pipelined Asynchronous Systems
Modular Approach to Multi-resource Arbiter Design
Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic
Synthesis of Multiple Rail Phase Encoding Circuits
Timing Domain Crossing using Muller Pipelines
Gate-level modelling and verification of asynchronous circuits using CSPM and FDR
Test and Repair Flow for Shared BISR in Asynchronous Multi-processors
GALS at ETH Zurich: Success or Failure
Hierarchical Event Readout with Asynchronous Pipelined Opportunistic Merges
Design and Analysis of Testable Mutual Exclusion Elements
27th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2021, Beijing, China, September 7-10, 2021
Verification of the speed-independent circuits by STG unfoldings
An Approach for Efficient Metastability Characterization of FPGAs through the Designer
How to Synchronize a Pausible Clock to a Reference
Building Finite Automata from DI Specifications
Designing an asynchronous pipeline token ring interface
A technique for estimating power in asynchronous circuits
Synchronous Interlocked Pipelines
A QDI Interconnect for 3D Systems Using Industry Standard EDA and Cell Libraries
RAPPID: An Asynchronous Instruction Length Decoder
Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology
Metastability in Better-Than-Worst-Case Designs
Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?
Asynchronous Signalling Processes
Deriving Performance Bounds for Conditional Asynchronous Circuits Using Linear Programing
Design and Implementation of a GALS Adapter for ANoC Based Architectures
Asynchronous Charge Sharing Power Consistent Montgomery Multiplier
Low-latency asynchronous FIFO buffers
Fourteen Ways to Fool Your Synchronizer
Average-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits
Criticality and Sensitivity Analysis for Incremental Performance Optimization of Asynchronous Pipelines
Reconfigurable Latch Controllers for Low Power Asynchronous Circuits
Controlling Event Spacing in Self-Timed Rings
Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits
Loihi Asynchronous Neuromorphic Research Chip
Asynchronous Design of a Bitwise Elimination Argmax via High-Level Modeling in GraphRack
Performance Analysis of GALS Datalink Based on Pausible Clocking
Automatic Compilation of Data-Driven Circuits
Fault Tolerant Delay Insensitive Inter-chip Communication
A system for asynchronous high-speed chip to chip communication
Towards Hazard-Free Multiplexer Based Implementation of Self-Timed Circuits
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding
Memory Faults in Asynchronous Microprocessors
Characterizing speed-independence of high-level designs
Some limitations to speed-independence in asynchronous circuits
Formal Verification of an Arbiter Circuit
The Even/Odd Synchronizer: A Fast, All-Digital, Periodic Synchronizer
Low Power QDI Asynchronous FFT
General Testers for Asynchronous Circuits
Hierarchical Token Rings for Address-Event Encoding
Improving Synchronous Elastic Circuits: Token Cages and Half-Buffer Retiming
Design and FPGA-implementation of Asynchronous Circuits Using Two-Phase Handshaking
Testing micropipelines
Derivation of Monotonic Covers for Standard-C Implementation Using STG Unfoldings
Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles
Phase Alignment Using Asynchronous State Machines
A Pausible Bisynchronous FIFO for GALS Systems
Clock Synchronization through Handshake Signalling
Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits
Deep Pipelines vs. Risk and Power Walls
An Analysis of Reshuffled Handshaking Expansions
Verifying a Self-Timed Divider
An ultra-low energy asynchronous processor for Wireless Sensor Networks
A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation
A Unified Coding Framework for Delay-Insensitivity
A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems
Timing Analysis of Extended Burst-Mode Circuits
CPlace: A Constructive Placer for Synchronous and Asynchronous Circuits
Synchronizer Behavior and Analysis
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
Simple Circuits that Work for Complicated Reasons
A Low-Power, Low-Noise, Configurable Self-Timed DSP
An Asynchronous Floating-Point Multiplier
Register Communication between Mutually Asynchronous Domains
PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI
GHz Asynchronous SRAM in 65nm
Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks
DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous Circuits
High-Speed QDI Asynchronous Pipelines
A Serial H-Tree Router for Two-Dimensional Arrays
M-of-N Code Decomposition for Indicating Combinational Logic
Energy Efficient Surfing
An event controlled reconfigurable multi-chip FFT
Challenges in Building an Open-Source Flow from RTL to Bundled-Data Design
ATRS: An Alternative Roadmap for Semiconductors, Technology Evolution and Impacts on System Architecture
A Low-Latency, Energy-Efficient L1 Cache Based on a Self-Timed Pipeline
Glitch Sensitivity and Defense of Quasi Delay-Insensitive Network-on-Chip Links
A High Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
Design of a High-Speed Asynchronous Turbo Decoder
Can QDI Combinational Circuits be Implemented without C-elements?
A Design Flow for Shaping Electromagnetic Emissions in Micropipeline Circuits
Static Timing Analysis of Asynchronous Bundled-Data Circuits
Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, ASYNC 1994, Salt Lake City, UT, USA, November 3-5, 1994
GALS Design for On-chip Ground Bounce Suppression
AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation
General conditions for the decomposition of state holding elements
An Asynchronous Dataflow Signal Processing Architecture to Minimize Energy per Op
Waveform Transition Graphs: A Designer-Friendly Formalism for Asynchronous Behaviours
Unfaithful Glitch Propagation in Existing Binary Circuit Models
Delay/Phase Regeneration Circuits
ASIE: An Asynchronous SNN Inference Engine for AER Events Processing
Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults
A Level-Crossing Flash Asynchronous Analog-to-Digital Converter
Relative Timing Based Verification of Timed Circuits and Systems
A Negative-Overhead, Self-Timed Pipeline
The energy and entropy of VLSI computations
19th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2013, Santa Monica, CA, USA, May 19-22, 2013
ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor
Monotonic Circuits with Complete Acknowledgement
Blade - A Timing Violation Resilient Asynchronous Template
Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture
Hades-towards the design of an asynchronous superscalar processor
A Self-Timed Ring Based True Random Number Generator
Checking Delay-Insensitivity: 10 4 Gates and Beyond
Ring Oscillator Clocks and Margins
Metastable-robust self-timed circuit synthesis from live safe simple signal transition graphs
A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implemented with QDI Templates
Sharp - A Resilient Asynchronous Template
Improved State Assignment for Burst Mode Finite State Machines
Energy-Efficient Pipelines
Fluid: An Asynchronous High-level Synthesis Tool for Complex Program Structures
High-Speed Reduced Stack Dual Lock Circuits
Synchronous Latency Insensitive Design
Uncle - An RTL Approach to Asynchronous Design
Synthesising Heterogeneously Encoded Systems
Scaledmatx One : A Bundled-Data GALS Inference ASIC
Long-Range GasP with Charge Relaxation
On the Existence of Hazard-Free Multi-Level Logic
Theoretical Limits on the Data Dependent Performance of Asynchronous Circuits
Reducing Energy Consumption and Decentralizing Computing through Heat Redistribution
A Novel Asynchronous Network-On-Chip Based on Source Asynchronous Signaling
Optimizing average-case delay in technology mapping of burst-mode circuits
Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank
29th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2025, Portland, OR, USA, May 11-14, 2025
Timing Errors in STA-based Gate-Level Simulation
High-Level Asynchronous System Design Using the ACK Framework
A Hierarchical Approach to Self-Timed Circuit Verification
Synchronizers and Data Flip-Flops are Different
8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK
Automated Verification of Asynchronous Circuits Using Circuit Petri Nets
2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), March 18-21, 1996, Aizu-Wakamatsu, Fukushima, Japan
A Coarse-Grain Phased Logic CPU
Low Power Asynchronous VLSI with NEM Relays
The Family of 4-phase Latch Protocols
GALS Design for Spectral Peak Attenuation of Switching Current
VLSI System Design Using Asynchronous Wave Pipelines: A 0.35?m CMOS 1.5 GHz Elliptic Curve Public Key Cryptosystem Chip
A Fast and Energy-Efficient Stack
Specification Mining for Asynchronous Controllers
28th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2023, Beijing, China, July 16-19, 2023
Bundled Data Asynchronous Multipliers with Data Dependent Computation Times
Gate Sizing and Vth Assignment for Asynchronous Circuits Using Lagrangian Relaxation
An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults
An Asynchronous RISC-V-based SNN Processor with Custom ISA Extensions for Programmable On-Chip Learning
Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application
Testing Asynchronous Circuits: Help is on the Way!
Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols
Applying Asynchronous Circuits in Contactless Smart Cards
Static Power Reduction Techniques for Asynchronous Circuits
Heuristic Based throughput Analysis and Optimization of Asynchronous Pipelines
Synchronizer Performance in Deep Sub-Micron Technology
Partial scan test for asynchronous circuits illustrated on a DCC error corrector
Mount Sisyphus: Energy-Efficient Asynchronous RISC-V Microcontroller in Intel 3 Process
Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance
A FIFO Data Switch Design Experiment
A Behavioral Synthesis Frontend to the Haste/TiDE Design Flow
Self-Healing Asynchronous Arrays
Fred: an architecture for a self-timed decoupled computer
6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel
Asynchronous FIR Filters: Towards a New Digital Processing Chain
An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz
Bringing Robustness and Power Efficiency to Autonomous Energy Harvesting Microsystems
Characterization of Asynchronous Templates for Integration into Clocked CAD Flows
Concurrency Reduction of Untimed Latch Protocols - Theory and Practice
An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems
5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 19-22 April 1999, Barcelona, Spain
Probabilistic Timing Analysis of Asynchronous Systems with Moments of Delay
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems
Automated Decomposition of Concurrent Programs for Asynchronous Logic Synthesis
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
Sufficient conditions for correct gate-level speed-independent circuits
A Counterflow Pipeline Experiment
A Result Forwarding Mechanism for Asynchronous Pipelined Systems
A Bit of Analysis on Self-Timed Single-Bit On-Chip Links
Formal Verification of Flow Equivalence in Desynchronized Designs
AMULET3 Revealed
Low Latency Clock Domain Transfer for Simultaneously Mesochronous, Plesiochronous and Heterochronous Interfaces
Programmable/Stoppable Oscillator Based on Self-Timed Rings
High Level Synthesis of Timed Asynchronous Circuits
Delay Insensitivity Does Not Mean Slope Insensitivity!
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice
SEU-Tolerant QDI Circuits
A Fast Branch-and-Bound Approach to High-Level Synthesis of Asynchronous Systems
Speculative Completion for the Design of High-Performance Asynchronous Dynamic Adders
Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits
GALS Partitioning by Behavioural Decoupling Expressed in Petri Nets
Characterizing metastability
Translating General Slack Elastic Programs into Dataflow Circuits
Tiempo Asynchronous Circuits System Verilog Modeling Language
Extending Synchronization from Super-Threshold to Sub-threshold Region
Automatic Leakage Control for Wide Range Performance QDI Asynchronous Circuits in FD-SOI Technology