yusuke1997/dblp-id-title huggingface dataset:
Ant Colony Optimization for Feature Subset Selection
Face Recognition using Radial Basis Function Network based on LDA
Literature Review of Cross Language Information Retrieval
Data Transmission Reliability in Short Message Integrated Distributed Monitoring Systems
A Web Pages Automatic Filtering System
Techniques for Video Mosaicing
Fast Pattern Detection Using Neural Networks Realized in Frequency Domain
Choosing an Ontology Language
PEIBM- Perceiving Emotions Using an Intelligent Behavioral Model
A New Technique for Solar Activity Forecasting using Recurrent Elman Networks
The Design and Implementation of Classifying Bird Sounds
Diffusion of Mobile Entertainment in Malaysia: Drivers and Barriers
A Patricia-Tree Approach for Frequent Closed Itemsets
Interactive Concept-based Search using MOEA: The Hierarchical Preferences Case
Discovery of Production Rules with Fuzzy Hierarchy
PP-FSM: Peer to Peer File Share for Multimedia
Improving Location Management in Mobile IPv4 Networks
An Experimental Consideration of the Hybrid Architecture Based on the Situated Action Generator
Design, Implementation and Testing of Mobile Agent Protection Mechanism for MANETS
Adaptive Subchannel Allocation for MC-CDMA System
A New Approach for Merging Ontologies
Model-Based Person Tracking Through Networked Cameras
New Algorithms for Finding Short Reset Sequences in Synchronizing Automata
Precombining Adaptive LMMSE Detection for DS-CDMA Systems in Time Varying Channels: Non Blind and Blind Approaches
A New Iterative Method for Solving Nonlinear Equations
Using Genetic Algorithms in Closed Loop Identification of the systems with Variable Structure Controller
Video Mining for Creative Rendering
Comparison of Schema Matching Systems
Formal Contextual Ontologies for Intelligent Information Systems
System of Programs for Rapid Development and Execution of Palm OS Applications
Testing Visual Abilities of Machines - Visual Intelligence Tests
Database Compression for Intelligent On-board Vehicle Controllers
Artificial Neural Networks for Classifying Magnetic Measurements in Tokamak Reactors
Two Approaches to Code Mobility in an Agent-based E-commerce System
A Fuzzy System to Analyze SIVD Diseases Using the Transcranial Magnetic Stimulation
Evaluating Content Based Image Retrieval Techniques with the One Million Images CLIC TestBed
A Modified Spiral Search Algorithm and its Embedded Hardware Implementation
A Hybrid Approach to Fault Detection and Diagnosis in a Diesel Fuel Hydrotreatment Process
Using Fuzzy Controller in Induction Motor Speed Control with Constant Flux
New Approach for Manipulation of Stratified Programs
CPU ray tracing large particle data with balanced P-k-d trees
Visualize the universe: Interactive exploration of cosmological dark matter simulation data
Visualizing crossing probabilistic tracts
VRGE: An Immersive Visualization Application for the Geosciences
An evaluation of three methods for visualizing uncertainty in architecture and archaeology
QuFlow: Visualizing Parameter Flow in Quantum Circuits for Understanding Quantum Computation
Visual verification of space weather ensemble simulations
A classification of user tasks in visual analysis of volume data
OpenSpace: Public dissemination of space mission profiles
Biclusters Based Visual Exploration of Multivariate Scientific Data
3De Interactive Lenses for Visualization in Virtual Environments
Correlation analysis in multidimensional multivariate time-varying datasets
Multiresolution visualization of digital earth data via hexagonal box-spline wavelets
A Lagrangian Method for Extracting Eddy Boundaries in the Red Sea and the Gulf of Aden
Visualising the dark sky IEEE SciVis contest 2015
TimeTubes: Automatic Extraction of Observable Blazar Features from Long-Term, Multi-Dimensional Datasets
Ordering Perceptions about Perceptual Order
Visualization of Uncertainty for Computationally Intensive Simulations Using High Fidelity Emulators
Cluster-Based Visualization for Merger Tree Data: The Challenge of Missing Expectations
3D superquadric glyphs for visualizing myocardial motion
Using Cinematic Effects to Visualize the Deep Water Impact Data Set
Visualizing Deep Water Asteroid Impacts: Interactive Visual Analysis of Multi-run Spatio-temporal Simulations
PathlinesExplorer - Image-based exploration of large-scale pathline fields
Color Interpolation for Non-Euclidean Color Spaces
Toward A Deep Understanding of What Makes a Scientific Visualization Memorable
Real-time uncertainty visualization for B-mode ultrasound
Interactive Visualization and Analysis of High Resolution HPC Simulation Data on a Laptop With VTK
Explicit frequency control for high-quality texture-based flow visualization
aflak: Pluggable Visual Programming Environment with Quick Feedback Loop Tuned for Multi-Spectral Astrophysical Observations
2018 IEEE Scientific Visualization Conference, SciVis 2018, Berlin, Germany, October 21-26, 2018
High performance flow field visualization with high-order access dependencies
Real-time interactive time correction on the GPU
VIS keynote address: An evolving visual language
Automated visualization workflow for simulation experiments
VIS capstone address: Architectures physical and digital
Using maximum topology matching to explore differences in species distribution models
A proposed multivariate visualization taxonomy from user data
Visualization and Analysis of Deep Water Asteroid Impacts
Cavern Halos: Exploring spatial and nonspatial cosmological data in an immersive virtual environment
An Organic Visual Metaphor for Public Understanding of Conditional Co-occurrences
VAPLI: Novel Visual Abstraction for Protein-Lipid Interactions
Inviwo - An extensible, multi-purpose visualization framework
A bottom-up scheme for user-defined feature exploration in vector field ensembles
Integrated explorer for cosmological evolution
Visualizing 3D flow through cutting planes
Auto-calibration of multi-projector displays with a single handheld camera
Interactive Visual Exploration and Comparison on the Effect of Asteroid Impacts
FTLE Ridge Lines for Long Integration Times
Ocean Current Segmentation at Different Depths and Correlation with Temperature in a MPAS-Ocean Simulation
Comparative Visualization of Deep Water Asteroid Impacts on Ultra-high-resolution Wall Displays with Seawall
2015 IEEE Scientific Visualization Conference, SciVis 2015, Chicago, IL, USA, October 25-30, 2015
Halos in a dark sky: Interactively exploring the structure of dark matter halo merger trees
Feature-based tensor field visualization for fiber reinforced polymers
A visual voting framework for weather forecast calibration
Visualizing the life and anatomy of dark matter
Better Verification Through Symmetry
VHDL Description and Formal Verification of Systolic Multipliers
An Efficient Data-Path Synthesis Based on Algorithmic Description under the Constraints of Time and Area
HW/SW Co-Design with PRAMs Using CoDES
Automatic VHDL Model Generation System
The Modeler's Assistant: A CAD Tool for Behavioral Model Development
System-Level Specification and Design Using VHDL: A Case Study
Prevail-DM: A Framework-Based Environment for Formal Hardware Verification
UDL/I version Two: A New Horizon of HDL Standards
The Backward Walk Approach in FSM Verification
A Visual Hardware Description Language
Automatic Synthesis of Sequential Synchronizations
A Denotational Definition of the VHDL Simulation Kernel
Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL '93, sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993
Insulin: An Instruction Set Simulation Environment
ESP: An Executable Specification Language for Mixed Timing Control Circuits
Toward a Basis for Protocol Specification and Process Decomposition
Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models
Hardware-Verification using First Order BDDs
Integrating SDL and VHDL for System-Level Hardware Design
Verilog HDL Modeling Styles for Formal Verification
Reasoning about the VHDL Standard Logic Package Signal Data Type
Verification of the Futurebus+ Cache Coherence Protocol
HML: A Hardware Description Language Based on Standard ML
Real Time Distributed Systems
Automatic Verification of Sequential Circuit Designs
Automated High-level Verification Against Clocked Algorithmic Specifications
Integrating Boolean Verification with Formal Derivation
Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation
An Efficient Object-Oriented Variation of the Statecharts Formalism for Distributed Real-Time Systems
A Representation for the Binding of RT-Component Functionality to HDL Behavior
A Rewriting Based Method for the Formal Verification of Microprocessors
Integrating Behavior and Timing in Executable Specifications
Parameterized VHDL Entities for the Simulation of Hybrid Circuits
Textual/Graphical Design Concept-Level Synthesis
Transformational Rewriting with Ruby
Checking DFT Rules with a VHDL Simulator
Reasoning about Array Structure Using a Dependently Typed Logic
Linking System Design Tools and Hardware Design Tools
Specifying Hardware Systems in LOTOS
Performance Specification and Measurement
Specification Languages for Communication Protocols
Analog-VHDL: As an Application, a Real Example
An Intelligent Image Processing System for Enhancing Blood Vessel Segmentation on Low-Power SoC
Enabling indoor object localization through Bluetooth beacons on the RADIO robot platform
The challenge of multi-operand adders in CNNs on FPGAs: how not to solve it!
Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications
Characterization of HPC workloads on an ARMv8 based server under relaxed DRAM refresh and thermal stress
System modeling and multicore simulation using transactions
High-Bandwidth Address Generation Unit
Realizing reconfigurable mesh algorithms on softcore arrays
Software-controlled processor stalls for time and energy efficient data locality optimization
Efficient Reed-Solomon Iterative Decoder Using Galois Field Instruction Set
Pareto-Based Application Specification for MP-SoC Customized Run-Time Management
OpenCL code generation for low energy wide SIMD architectures with explicit datapath
Physical design aware system level synthesis of hardware
Modeling NoC Architectures by Means of Deterministic and Stochastic Petri Nets
Mitigating the Effects of RRAM Process Variation on the Accuracy of Artificial Neural Networks
Learning-based analytical cross-platform performance prediction
From High-Level Synthesis to Bundled-Data Circuits
Flux Caches: What Are They and Are They Useful?
SIMD performance in software based mobile video coding
Power aware heterogeneous MPSoC with dynamic task scheduling and increased data locality for multiple applications
Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings
Micro-architecture Performance Estimation by Formula
RV-VP 2 : Unlocking the Potential of RISC-V Packed-SIMD for Embedded Processing
Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study
Experiences in speeding up computer vision applications on mobile computing platforms
A 2D Addressing Mode for Multimedia Applications
DVB-DSNG Modem High Level Synthesis in an Optimized Latency Insensitive System Context
Special session on "What's next for ESL"
Hardware-efficient index mapping for mixed radix-2/3/4/5 FFTs
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 17-20, 2006
Session details: Security threats caused by novel technologies
An FPGA-based probability-aware fault simulator
DIF: An Interchange Format for Dataflow-Based Design Tools
DARSA: a dataflow analysis tool for reconfigurable platforms
Design Issues in Parallel Array Languages for Shared Memory
Synchronous Transfer Architecture (STA)
Performance Improvements in Microprocessor Systems Utilizing a Copressor Data-Path
Exploiting the Cell/BE Architecture with the StarPU Unified Runtime System
Introduction to Mastering Cell BE and GPU Execution Platforms
Improving memory subsystem performance in network processors with smart packet segmentation
Comparison of Exponentially Decreasing Vs. Polynomially Decreasing Objective Functions for Making Quantum Circuits Nearest Neighbour Compliant
Accelerating Depthwise Separable Convolutions on Ultra-Low-Power Devices
High-bandwidth, high-capacity, low-power memory systems
SystemQ: A Queuing-Based Approach to Architecture Performance Evaluation with SystemC
Micro-architecture and Control Electronics Simulation of Modular Color Center-Based Quantum Computers
RiBoSOM: rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform
An effective model extraction method with state space compression for model checking SystemC TLM designs
Modeling the Scalability of the EuroExa Reconfigurable Accelerators - Preliminary Results - Invited Paper
Message Passing Interface support for the runtime adaptive multi-processor system-on-chip RAMPSoC
TrueFloat: A Templatized Arithmetic Library for HLS Floating-Point Operators
Scalable and Modular Scheduling
RACOS: Transparent access and virtualization of reconfigurable hardware accelerators
Definition of an embedded driver model for driving behavior prediction within the DESERVE platform
A Case for Visualization-Integrated System-Level Design Space Exploration
Potential future research in computing: Heterogeneous systems, memory subsystems - Process-in-storage, or not to process-in-storage? That is the question
Efficient dual-ISA support in a retargetable, asynchronous Dynamic Binary Translator
On the scalability of SIMD processing for software defined radio algorithms
An Embrace-and-Extend Approach to Managing the Complexity of Future Heterogeneous Systems
Integrated Microsystems in Industrial Applications
Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs
Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms
Programmable Accelerators for Reconfigurable Video Decoder
Analysis of Dataflow Programs with Interval-Limited Data-Rates
Hardware Deceleration of Kvazaar HEVC Encoder
BLonD++: performance analysis and optimizations for enabling complex, accurate and fast beam dynamics studies
Flexibility/Cost-Tradeoffs of Platform-Based Systems
$\mathrm {DD\text {-}MPU}$: Dynamic and Distributed Memory Protection Unit for Embedded System-on-Chips
Interleaving methods for hybrid system-level MPSoC design space exploration
Fast Performance Estimation and Design Space Exploration of SSD Using AI Techniques
From Scilab to multicore embedded systems: Algorithms and methodologies
Memory Architecture Evaluation for Video Encoding on Enhanced Embedded Processors
EXTRA: an open platform for reconfigurable architectures
FLUX Networks: Interconnects on Demand
An Automatically-Retargetable Time-Constraint-Driven Instruction Scheduler for Post-compiling Optimization of Embedded Code
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2010), Samos, Greece, July 19-22, 2010
I2DS: FPGA-Based Deep Learning Industrial Intrusion Detection System
VLSI challenges to more energy efficient devices
SIMD made explicit
Accelerating collective communication in message passing on manycore System-on-Chip
An event-based Network-on-Chip debugging system for FPGA-based MPSoCs
Crack me if you can: hardware acceleration bridging the gap between practical and theoretical cryptanalysis?: a Survey
NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core Systems
A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing
ROCKY: Rotation Countermeasure for the Protection of Keys and Other Sensitive Data
SHARQ: Software-Defined Hardware-Managed Queues for Tile-Based Manycore Architectures
HIBI v.2 Communication Network for System-on-Chip
Run-Time Detection of Malicious Behavior Based on Exploit Decomposition Using Deep Learning: A Feasibility Study on SysJoker
CHIPS-AHOy: a predictable holistic cyber-physical hypervisor for MPSoCs
Application Runtime Estimation for AURIX Embedded MCU Using Deep Learning
XIVth International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2014, Agios Konstantinos, Samos, Greece, July 14-17, 2014
SPynq: Acceleration of machine learning applications over Spark on Pynq
HEVC in-loop filters GPU parallelization in embedded systems
Design space exploration for fair resource-allocated NoC architectures
Embedded Computer Systems: Architectures, Modeling, and Simulation - 24th International Conference, SAMOS 2024, Samos, Greece, June 29 - July 4, 2024, Proceedings, Part II
On the Calibration of Abstract Performance Models for System-level Design Space Exploration
A light-weight Network-on-Chip architecture for dynamically reconfigurable systems
Reconfigurable Multithreading Architectures: A Survey
A Hardware Accelerator for Controlling Access to Multiple-Unit Resources in Safety/Time-Critical Systems
Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism
On-Chip Memory Access Reduction for Energy-Efficient Dilated Convolution Processing
Energy efficiency of mobile video decoding
Embedded Computer Systems: Architectures, Modeling, and Simulation - 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, Proceedings
A system-level synthesis approach from formal application models to generic bus-based MPSoCs
Maximum performance computing for exascale applications
Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs
Instruction-Level Fault Tolerance Configurability
An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs
Signature-Based Calibration of Analytical System-Level Performance Models
Real-time stereo vision system using semi-global matching disparity estimation: Architecture and FPGA-implementation
Sharing-Aware Data Mapping in Software Transactional Memory
Embedded Computer Systems: Architectures, Modeling, and Simulation - 21st International Conference, SAMOS 2021, Virtual Event, July 4-8, 2021, Proceedings
European Research in Embedded Systems
Reducing Execution Unit Leakage Power in Embedded Processors
Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management
Imposing coarse-grained reconfiguration to general purpose processors
Adaptive reinforcement learning method for networks-on-chip
DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator
Towards self-adaptive MPSoC systems with adaptivity throttling
A new state model for DRAMs using Petri Nets
Devices and Architectures for Efficient Computing In-Memory (CIM) Design
Architectural considerations for FPGA acceleration of machine learning applications in MapReduce
An ESL timing & power estimation and simulation framework for heterogeneous socs
Self-loop Pipelining and Reconfigurable Dataflow Arrays
A hardware accelerated configurable ASIP architecture for embedded real-time video-based driver assistance applications
The Challenge of Classification Confidence Estimation in Dynamically-Adaptive Neural Networks
Monitoring of Environmentally Hazardous Exhaust Emissions from Cars Using Optical Fibre Sensors
Parallelism extraction in embedded software for android devices
A run-time modulo scheduling by using a binary translation mechanism
Evaluation of message passing synchronization algorithms in embedded systems
Effects of Program Compression
Implications of non-volatile memory as primary storage for database management systems
System on chip generation for multi-sensor and sensor fusion applications
It's All About PR - Smart Benchmarking AI Accelerators Using Performance Representatives
Rigorous design of cyber-physical systems
Formal Specification of a Protocol Processor
Pre-architectural performance estimation for ASIP design based on abstract processor models
System Simulation of Memristor Based Computation in Memory Platforms
A Multiprocessor Architecture with an Omega Network for the Massively Parallel Model GCA
Introduction to System Level Design for Heterogeneous Systems
on-Demand system reliability: The DeSyRe project
Transforming nanodevices to next generation nanosystems
Stochastic modeling and performance analysis of multimedia SoCs
Loading rho-µ-Code: Design Considerations
A generic processing in memory cycle accurate simulator under hybrid memory cube architecture
Performance Estimation of Streaming Media Applications for Reconfigurable Platforms
A Case for Partial Co-allocation Constraints in Compressed Caches
NoGAP: A Micro Architecture Construction Framework
SEC-Learn: Sensor Edge Cloud for Federated Learning - Invited Paper
Performance evaluation of concurrently executing parallel applications on multi-processor systems
Performance evaluation of the Intel Xeon Phi manycore architecture using parallel video-based driver assistance algorithms
Energy efficient stream-based configurable architecture for embedded platforms
Design of a Low Power Pre-synchronization ASIP for Multimode SDR Terminals
Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph
A Parallel Synchronous Execution Engine and Target Language for Digital Microfluidics
Just-in-Time Verification in ADL-based processor design
Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor
Scalable Architecture for Prefix Preserving Anonymization of IP Addresses
Hiding side-channel leakage through hardware randomization: A comprehensive overview
2013 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2013, Agios Konstantinos, Samos Island, Greece, July 15-18, 2013
Reconfigurable miniature sensor nodes for condition monitoring
Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI
An Optimization Methodology for Memory Allocation and Task Scheduling in SoCs Via Linear Programming
Analyzing the trade-off between power consumption and beamforming algorithm performance using a hearing aid ASIP
Compiler Optimizations for Safe Insertion of Checkpoints in Intermittently Powered Systems
Exploring the unified design-space of custom-instruction selection and resource sharing
Hybrid Functional and Instruction Level Power Modeling for Embedded Processors
Dynamic-vector execution on a general purpose EDGE chip multiprocessor
VULDAT: Automated Vulnerability Detection from Cyberattack Text
Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting
Towards scalable I/O on a many-core architecture
Early ISS Integration into Network-on-Chip Designs
Pulse-length determination techniques in the rectangular single event transient fault model
Experimental Assessment and Biaffine Modeling of the Impact of Ambient Temperature on SoC Power Requirements
Fast transaction-level dynamic power consumption modelling in priority preemptive wormhole switching networks on chip
K-Periodic schedules for evaluating the maximum throughput of a Synchronous Dataflow graph
Obfuscating the Hierarchy of a Digital IP
Fast Huffman decoding by exploiting data level parallelism
Development and design of a platform for arbitration and sharing control applications
802.15.3 Transmitter: A Fast Design Cycle Using OFDM Framework in Bluespec
Modeling the temperature bias of power consumption for nanometer-scale CPUs in application processors
Automated Power Gating of Registers Using CoDeL and FSM Branch Prediction
Scalable multi-core simulation using parallel dynamic binary translation
Dynamic task mapping onto multi-core architectures through stream rewriting
Characterizing communication behavior of dataflow programs using trace analysis
Network/system co-simulation for design space exploration of IoT applications
Interface Overheads in Embedded Multimedia Software