yusuke1997/dblp-id-title huggingface dataset:
Code cache management in managed language VMs to reduce memory consumption for embedded systems
Elastic computing: a framework for transparent, portable, and adaptive multi-core heterogeneous computing
Compiler-directed cache polymorphism
Compiler driven data layout optimization for regular/irregular array access patterns
WoCA: Avoiding Intermittent Execution in Embedded Systems by Worst-Case Analyses with Device States
Lightweight and block-level concurrent sweeping for javascript garbage collection
Design and evaluation of a compiler for embedded stream programs
Auto-vectorization for image processing DSLs
Feedback driven instruction-set extension
Annotate once - analyze anywhere: context-aware WCET analysis by user-defined abstractions
Improving Data Access Efficiency by Using Context-Aware Loads and Stores
Efficient memory-reference checks for real-time java
An old friend is better than two new ones: dual-screen Android
Complementing software pipelining with software thread integration
reUpNix: Reconfigurable and Updateable Embedded Systems
Pluggable abstract domains for analyzing embedded software
Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache
Generation of permutations for SIMD processors
Cross-Kernel Control-Flow-Graph Analysis for Event-Driven Real-Time Systems
SetMP: Set Associative Mapping Management for Multi-plane Optimization in SSDs
Issues and challenges in compiling for the CBEA
Scheduling of stream-based real-time applications for heterogeneous systems
A dictionary construction technique for code compression systems with echo instructions
Procrastination scheduling in fixed priority real-time systems
Cache vulnerability equations for protecting data in embedded processor caches from soft errors
Proceedings of the 25th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES 2024, Copenhagen, Denmark, 24 June 2024
Loop-oriented array- and field-sensitive pointer analysis for automatic SIMD vectorization
Supporting User-Friendly Analysis of Timing Constraints
LCTES '22: 23rd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, San Diego, CA, USA, 14 June 2022
Finding effective compilation sequences
Dynamic translation of structured Loads/Stores and register mapping for architectures with SIMD extensions
LCTES '21: 22nd ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, Virtual Event, Canada, 22 June, 2021
Mapping a data-flow programming model onto heterogeneous platforms
Compiling java for low-end embedded systems
An open-source realtime computational platform (short WIP paper)
Free Rider: A Tool for Retargeting Platform-Specific Intrinsic Functions
ApproxSymate: path sensitive program approximation using symbolic execution
Quick piping: a fast, high-level model for describing processor pipelines
Automated kernel fusion for GPU based on code motion
The role of C in the dark ages of multi-core
Exploiting the Trust Between Boundaries: Discovering Memory Corruptions in Printers via Driver-Assisted Testing
Power-efficient prefetching via bit-differential offset assignment on embedded processors
Tamper-resistant whole program partitioning
Sampling-based program execution monitoring
Performance Optimization on big.LITTLE Architectures: A Memory-latency Aware Approach
Scalable size inliner for mobile applications (WIP)
Time-triggered garbage collection: robust and adaptive real-time GC scheduling for embedded systems
A Tool to Assist in Fine-Tuning and Debugging Embedded Real-Time Systems
Using Inferno TM to Execute Java TM on Small Devices
JAX based parallel inference for reactive probabilistic programming
From Java to real-time Java: a model-driven methodology with automated toolchain (invited paper)
Predicting the Worst-Case Execution Time of the Concurrent Execution of Instructions and Cycle-Stealing DMA I/O Operations
TIC: a scalable model checking based approach to WCET estimation
System-wide compaction and specialization of the linux kernel
Generic control flow reconstruction from assembly code
Beyond Base-2 Logarithmic Number Systems (WiP Paper)
Static Timing Analysis of Real-Time Systems
WCET analysis of instruction caches with prefetching
A Uniform Reliable Multicast Protocol with Guaranteed Response Times
A domain specific interconnect for reconfigurable computing
Compiler-directed thermal management for VLIW functional units
On Predicting Data Cache Behavior for Real-Time Systems
Profiling tools for hardware/software partitioning of embedded applications
SCCharts Twelve Years Later: A Reflection on Sequential Constructiveness and Text-First Modeling (Keynote)
Hierarchical real-time garbage collection
Robustness analysis of avionics embedded systems
From simulink to SCADE/lustre to TTA: a layered approach for distributed embedded applications
Transparent distribution of real-time components based on logical execution time
Static determination of allocation rates to support real-time garbage collection
Compiler 2.0: Using Machine Learning to Modernize Compiler Technology
Efficient application migration under compiler guidance
Preventing interrupt overload
Mapping an Embedded Hard Real-Time Systems SDL Specification to an Analyzable Task Network - A Case Study
Spinach: a liberty-based simulator for programmable network interface architectures
Enabling compiler flow for embedded VLIW DSP processors with distributed register files
Advanced control flow in Java card programming
Specification and verification of time requirements with CCSL and Esterel
Feedback EDF scheduling exploiting hardware-assisted asynchronous dynamic voltage scaling
Look into details: the benefits of fine-grain streaming buffer analysis
SWL: a search-while-load demand paging scheme with NAND flash memory
Time weaver: a software-through-models framework for embedded real-time systems
Optimizing scientific application loops on stream processors
Energy-balanced task allocation for collaborative processing in networked embedded systems
JSCore: architectural support for accelerating JavaScript execution (short WIP paper)
Co-mining: a processing-in-memory assisted framework for memory-intensive PoW acceleration
Towards Real-time CNN Inference from a Video Stream on a Mobile GPU (WiP Paper)
Loop fusion for clustered VLIW architectures
Generating fast code from concurrent program dependence graphs
Crash recoverable ARMv8-oriented B+-tree for byte-addressable persistent memory
Compositional static instruction cache simulation
Storage assignment optimizations through variable coalescence for embedded processors
MaPHeA: a lightweight memory hierarchy-aware profile-guided heap allocation framework
A framework to schedule parametric dataflow applications on many-core platforms
PROPAN: A Retargetable System for Postpass Optimisations and Analyses
Combined WCET analysis of bitcode and machine code using control-flow relation graphs
Integrating hardware and software information flow analyses
DVSleak: combining leakage reduction and voltage scaling in feedback EDF scheduling
Optimizing Function Layout for Mobile Applications
Embedded systems in the wild: ZebraNet software, hardware, and deployment experiences
ACME: adaptive compilation made efficient
Addressing instruction fetch bottlenecks by using an instruction register file
Towards device emulation code generation
Integrated IoT programming with selective abstraction
Tiling for DMA-Based Hardware Accelerators (WIP)
Efficient User-Level I/O in the ARX Real-Time Operating System
Approximation of Worst-Case Execution Time for Preemptive Multitasking Systems
Input data reuse in compiling window operations onto reconfigurable hardware
Combinatorial spill code optimization and ultimate coalescing
Task-level analysis for a language with async/finish parallelism
Portable mapping of openMP to multicore embedded systems using MCA APIs
Compiling for memory emergency
Optimizing tensor contractions for embedded devices with racetrack memory scratch-pads
Robust I/O-compute concurrency for machine learning pipelines in constrained cyber-physical devices
RollBin: reducing code-size via loop rerolling at binary level
Improving processor efficiency by statically pipelining instructions
Cache-Sensitive Pre-runtime Scheduling
An approach to improving the structure of error-handling code in the linux kernel
SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2013, LCTES '13, Seattle, WA, USA, June 20-21, 2013
WCET-Aware Dynamic D-cache Locking for A Single Task
Stream execution on wide-issue clustered VLIW architectures
Automatic Validation of Code-Improving Transformations
Exploration of compiler optimization sequences using clustering-based selection
Modulo Scheduling for the TMS320C6x VLIW DSP Architecture
When to use a compilation service?
Intermittent Computing with Peripherals, Formally Verified
Upper bound for defragmenting buddy heaps
Automatic formal verification for scheduled VLIW code
Integrating safety analysis into the model-based development toolchain of automotive embedded systems
Improving the Performance of WCET Analysis in the Presence of Variable Latencies
Bee+Cl@k: an implementation of lattice-based array contraction in the source-to-source translator rose
A Design and Implementation of a Remote Debugging Environment for Embedded Internet Software
OpenMP-RT: Native Pragma Support for Real-Time Tasks and Synchronization with LLVM under Linux
Fractional rate dataflow model and efficient code synthesis for multimedia applications
Non-intrusive program tracing and debugging of deployed embedded systems through side-channel analysis
WasmAndroid: a cross-platform runtime for native programming languages on Android (WIP paper)
Implicit state machines
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
A type system for the automatic distribution of higher-order synchronous dataflow programs
An operational semantics for Simulink's simulation engine
Energy-conscious compilation based on voltage scaling
Code generation criteria for buffered exposed datapath architectures from dataflow graphs
A graph-based iterative compiler pass selection and phase ordering approach
Impact of JVM superoperators on energy consumption in resource-constrained embedded systems
Optimistic coalescing for heterogeneous register architectures
Proceedings of the 26th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES 2025, Seoul, Republic of Korea, June 16-17, 2025
1+1>2: variation-aware lifetime enhancement for embedded 3D NAND flash systems
IA-graph based inter-app conflicts detection in open IoT systems
Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002
Dependence-based multi-level tracing and replay for wireless sensor networks debugging
An efficient code update scheme for DSP applications in mobile embedded systems
On the complexity of spill everywhere under SSA form
TCPS: a task and cache-aware partitioned scheduler for hard real-time multi-core systems
Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor
WCET-aware data selection and allocation for scratchpad memory
On intermittence bugs in the battery-less internet of things (WIP paper)
Towards Automated Identification of Layering Violations in Embedded Applications (WIP)
Compiler-directed application mapping for NoC based chip multiprocessors
On systematic design of globally consistent executable assertions in embedded software
Trace-and-brace (TAB): bespoke software countermeasures against soft errors
Robust and sustainable schedulability analysis of embedded software
Composable code generation for distributed giotto
Automating the generation of hardware component knowledge bases
Proceedings of the 24th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES 2023, Orlando, FL, USA, 18 June 2023
Synchronous objects with scheduling policies: introducing safe shared memory in lustre
Effective thread management on network processors with compiler analysis
Better atomic writes by exposing the flash out-of-band area to file systems
rtesbench: A Multi-core Benchmark Framework for Real-Time Embedded Systems
Non-local Instruction Scheduling with Limited Code Growth
Adaptive optimization for OpenCL programs on embedded heterogeneous systems
Path Sensitive Signatures for Control Flow Error Detection
Optimizing software cache performance of packet processing applications
VOBLA: a vehicle for optimized basic linear algebra
Table-based QoS Control for Embedded Real-Time Systems
TrilobiteG: A programming architecture for autonomous underwater vehicles
Reordering Memory Bus Transactions for Reduced Power Consumption
Debugging FPGA-based packet processing systems through transaction-level communication-centric monitoring
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
AOT vs. JIT: impact of profile data on code quality
How to compute worst-case execution time by optimization modulo theory and a clever encoding of program semantics
Facilitating the Bootstrapping of a New ISA
EVMBT: A Binary Translation Scheme for Upgrading EVM Smart Contracts to WASM
Languages, Compilers, and Tools for Embedded Systems, ACM SIGPLAN Workshop LCTES 2000, Vancouver, BC, Canada, June 18, 2000, Proceedings
Compiling a gesture recognition application for a low-power spatial architecture
A JVM for soft-error-prone embedded systems
Proceedings of the ACM SIGPLAN 1999 Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES'99), Atlanta, Georgia, USA, May 5, 1999
LUCI: Lightweight UI Command Interface
Phased scheduling of stream programs
Program performance spectrum
Energy-efficient policies for embedded clusters
Deriving abstract transfer functions for analyzing embedded software
Compiler Support for Software-Based Cache Partitioning
A sample-based cache mapping scheme
Why SpecInt95 Should Not Be Used to Benchmark Embedded Systems Tools
OSEK-V: application-specific RTOS instantiation in hardware
Creating portable, repeatable, realistic benchmarks for embedded systems and the challenges thereof
Dynamic data scratchpad memory management for a memory subsystem with an MMU
SPECTRUM: a software defined predictable many-core architecture for LTE baseband processing
Rapid design space exploration of heterogeneous embedded systems using symbolic search and multi-granular simulation
BLog : block-level log -block management for NAND flash memorystorage systems
DSPs: why don't they just go away!
WCRT analysis for a uniprocessor with a unified prioritized cache
Effective Exploitation of a Zero Overhead Loop Buffer
Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures
Pipeline Behavior Prediction for Superscalar Processors by Abstract Interpretation
FORMLESS: scalable utilization of embedded manycores in streaming applications
Compiling with code-size constraints
CodeExtract: Enhancing Binary Code Similarity Detection with Code Extraction Techniques
The Cluster Compiler - A Tool for the Design of Time-Triggered Real-Time Systems
Link-time optimization of ARM binaries
Predictable task migration for locked caches in multi-core systems
A memory-bounded, deterministic and terminating semantics for the synchronous programming language Céu
Enhanced hot spot detection heuristics for embedded java just-in-time compilers
Targeting complex embedded architectures by combining the multicore communications API (mcapi) with compile-time virtualisation
A formal concurrency model based architecture description language for synthesis of software development tools
RTsynchronizer: Language Support for Real-Time Specifications in Distributed Systems
A Collaborative Filtering Approach for the Automatic Tuning of Compiler Optimisations
Partitioning data-parallel programs for heterogeneous MPSoCs: time and energy design space exploration
Modulo scheduling without overlapped lifetimes
Graphitron: A Domain Specific Language for FPGA-Based Graph Processing Accelerator Generation
Operation and data mapping for CGRAs with multi-bank memory
FaCSim: a fast and cycle-accurate architecture simulator for embedded systems
Clock-directed modular code generation for synchronous data-flow languages
A Flexible-Granularity Task Graph Representation and Its Generation from C Applications (WIP)
Scheduling of Hard Aperiodic Tasks in Hybrid Static/Dynamic Priority Systems
Efficient code generation from SHIM models
Live Memory Analysis for Garbage Collection in Embedded Systems
LUNAR: A Native Table Engine for Embedded Devices
An EDF schedulability test for periodic tasks on reconfigurable hardware devices
Symbolic consistency checking of OpenMp parallel programs
A type system for preventing data races and deadlocks in the java virtual machine language: 1
Exploiting function similarity for code size reduction
SPARQ: An Accelerator Architecture for Large Language Models with Joint Sparsity and Quantization Techniques
A Software Synthesis Tool for Distributed Embedded System Design
Enhancing the performance of 16-bit code using augmenting instructions
Software debugging and testing using the abstract diagnosis theory
Buffer minimization in earliest-deadline first scheduling of dataflow graphs
Cache-related preemption delay analysis for FIFO caches
Deep neural networks compiler for a trace-based accelerator (short WIP paper)
Zoozve: A Strip-Mining-Free RISC-V Vector Extension with Arbitrary Register Grouping Compilation Support (WIP)
Generalizing parametric timing analysis
R-Visor: An Extensible Dynamic Binary Instrumentation and Analysis Framework for Open Instruction Set Architectures
Accelerating Shared Library Execution in a DBT
Versatile system-level memory-aware platform description approach for embedded MPSoCs
Relative competitive analysis of cache replacement policies
Efficient intermittent computing with differential checkpointing
Proceedings of the 21st ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES 2020, London, UK, June 16, 2020
Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems, LCTES 2016, Santa Barbara, CA, USA, June 13 - 14, 2016
Application specific compiler/architecture codesign: a case study
Measuring the cache interference cost in preemptive real-time systems
Imprecision in WCET estimates due to library calls and how to reduce it (WIP paper)
On efficient program synthesis from statecharts
Syncopation: generational real-time garbage collection in the metronome
EMBARC: an efficient memory bank assignment algorithm for retargetable compilers
On the design of the local variable cache in a hardware translation-based java virtual machine
A machine learning approach to mapping streaming workloads to dynamic multicore processors
An instruction-scheduling-aware data partitioning technique for coarse-grained reconfigurable architectures
Proceedings of the 19th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES 2018, Philadelphia, PA, USA, June 19-20, 2018
Automatic generation of embedded communication SW for heterogeneous MPSoC platforms
Symbolic execution for memory consumption analysis
RNFTL: a reuse-aware NAND flash translation layer for flash memory
Software Synthesis for Real-Time Information Processing Systems
Boosting efficiency of fault detection and recovery throughapplication-specific comparison and checkpointing
Using UML for Modeling Complex Real-Time Systems
WCET: aware dynamic instruction cache locking
Perfecting preemption threshold scheduling for object-oriented real-time system design: from the perspective of real-time synchronization
Divide and recycle: types and compilation for a hybrid synchronous language
A Tool for Simulation and Fast Prototyping of Embedded Control Systems
CHaNAS: coordinated search for network architecture and scheduling policy
Rethinking Java call stack design for tiny embedded devices
On the side-effects of code abstraction
NDL: a domain-specific language for device drivers
Energy-conserving feedback EDF scheduling for embedded systems with real-time constraints
Modeling and simulating electronic textile applications
Proxy compilation of dynamically loaded Java classes with MoJo
Lowering overhead in sampling-based execution monitoring and tracing
Proceedings of the ACM SIGPLAN/SIGBED 2011 conference on Languages, compilers, and tools for embedded systems, LCTES 2011, Chicago, IL, USA, April 11-14, 2011
Efficient code generation in a region-based dynamic binary translator
TinySeg: Model Optimizing Framework for Image Segmentation on Tiny Embedded Systems
CASM: optimized compilation of abstract state machines
Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'05), Chicago, Illinois, USA, June 15-17, 2005
End-to-End Optimization in Heterogeneous Distributed Real-Time Systems
Efficient Implementation of Neural Networks Usual Layers on Fixed-Point Architectures
Unmasking the Lurking: Malicious Behavior Detection for IoT Malware with Multi-label Classification
Selective path-sensitive interval analysis (WIP paper)
Optimizing for space and time usage with speculative partial redundancy elimination
Precise and efficient parametric path analysis
Implementation-Aware Model Analysis: The Case of Buffer-Throughput Tradeoff in Streaming Applications
ARINC 653-inspired regularity-based resource partitioning on xen
PinIt: Influencing OS Scheduling via Compiler-Induced Affinities
Towards Energy-Aware Iteration Space Tiling
An open, transparent, industry-driven approach to AV safety (keynote)
Effective compiler generation by architecture description
Optimistic and Scalable Global Function Merging
Profile-guided deployment of stream programs on multicores
New models and methods for programming cyber-physical systems (keynote)
Speculative software management of datapath-width for energy optimization
Static strands: safely collapsing dependence chains for increasing embedded power efficiency
VISTA: a system for interactive code improvement
Live-range unsplitting for faster optimal coalescing
Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES 2019, Phoenix, AZ, USA, June 23-23, 2019
Efficient asynchronous interrupt handling in a full-system instruction set simulator
SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2014, LCTES '14, Edinburgh, United Kingdom - June 12 - 13, 2014
Tracing interrupts in embedded software
ASAC: automatic sensitivity analysis for approximate computing
Code and data partitioning for fine-grain parallelism
Resilience analysis: tightening the CRPD bound for set-associative caches
Software transactional memory for multicore embedded systems
A modular memory optimization for synchronous data-flow languages: application to arrays in a lustre compiler
Grouptuner: Efficient Group-Aware Compiler Auto-tuning
The ControlShell Component-Based Real-Time Programming System, and its Application to the Marsokhod Martian Rover
Frequency-aware energy optimization for real-time periodic and aperiodic tasks
Generalized instruction selection using SSA -graphs
Practical speculative parallelization of variable-length decompression algorithms
An Integrated Push/Pull Buffer Management Method in Multimedia Communication Environments
Push-assisted migration of real-time tasks in multi-core processors
Inter-task register-allocation for static operating systems
Flexible task graphs: a unified restricted thread programming model for java
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007
Proceedings of The Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES 2001), June 22-23, 2001 / The Workshop on Optimization of Middleware and Distributed Systems (OM 2001), June 18, 2001, Snowbird, Utah, USA