yusuke1997/dblp-id-title huggingface dataset:
Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study of Application and Implementation
Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture
Power-Constrained Embedded Memory BIST Architecture
Special Session: Architecture-Level DCIM Technologies for Edge AI Computing Applications
Side channel attacks on STTRAM and low-overhead countermeasures
Improving small-delay fault coverage for on-chip delay measurement
On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars
Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models
Function-Based Dynamic Compaction and its Impact on Test Set Sizes
A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access Memory
Calibration of Open Interconnect Yield Models
Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing Systems
System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology
Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes
Clock Glitch versus SIFA
Dependence of SEUs in Digital Cameras on Pixel size and Elevation
Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE
Built-In Proactive Tuning System for Circuit Aging Resilience
CNT-count Failure Characteristics of Carbon Nanotube FETs under Process Variations
A heuristic path selection method for small delay defects test
Fault Injection Framework for embedded memories
Approximate simulation of circuits with probabilistic behavior
An Automated and Effective Approach for SBST Generation Targeting RISC-V CPUs
Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits
A Scalable Framework for Defect Isolation of DNA Self-assemlbled Networks
State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration
An Interactive Yield Estimator as a VLSI CAD Tool
LMS-based RF BIST architecture for multistandard transmitters
Tradeoffs in Imager Design with Respect to Pixel Defect Rates
15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, Proceedings
Critical area extraction of extra material soft faults
Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs
Dependable routing in multi-chip NoC platforms for automotive applications
A Structural Testing Approach for SRAM Address Decoders Using Cell-Aware Methodology
High-Level BIST Synthesis for Delay Testing
Unintrusive aging analysis based on offline learning
On Fractal Yield Models: A Statistical Paradox
Preventing Soft Errors and Hardware Trojans in RISC-V Cores
A Multi-dimensional Iddq Testing Method Using Mahalanobis Distance
An Approach for Selection of Test Points for Analog Fault Diagnosis
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies
Testing of programmable logic devices (PLD) with faulty resources
A Soft Error Tolerance Estimation Method for Sequential Circuits
Comparison and Application of Different VHDL-Based Fault Injection Techniques
VLSI Implementation of a Fault-Tolerant Distributed Clock Generation
Combining Hardware- and Software-Based Self-Repair Methods for Statically Scheduled Data Paths
The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, October 27-29, 1993, Venice, Italy, Proceedings
Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction
Effect of Process Variation on the Performance of Phase Frequency Detector
14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings
Decreasing FIT with diverse triple modular redundancy in SRAM-based FPGAs
Low-Cost Test for Large Analog IC's
X-Stacking - A Method for Reducing Control Data for Output Compaction
Characterization of data retention faults in DRAM devices
2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD)
On the development of Software-Based Self-Test methods for VLIW processors
Detection of Defective Media in Disks
Hardening a memory cell for low power operation by gate leakage reduction
Fault-Tolerant Routing Algorithm for Network on Chip without Virtual Channels
Test Compaction by Using Linear-Matrix Driven Scan Chains
Beyond the Black Box: Advancing Transparency, Explainability, and Trust in AI for Space
Synthesis of Efficient Linear Test Pattern Generators
A Two-Phase Reconfiguration Strategy for Extracting Linear Arrays Out of Two-Dimensional Architectures
BIST Based Fault Diagnosis Using Ambiguous Test Set
Preliminary Validation of an Approach Dealing with Processor Obsolescence
Multiple Transient Faults in Logic: An Issue for Next Generation ICs
Reliable System Co-Design: The FIR Case Study
Design of Cover Circuits for Monitoring the Output of a MISA
Inserting Test Points to Control Peak Power During Scan Testing
A Fault-Tolerant Associative Approach to On-Line Memory Repair
Application of a Survey Sampling Critical Area Computation Tool in a Manufacturing Environment
Detecting SEUs in Noisy Digital Imagers with small pixels
Challenges of Built-In Current Sensor Designs
An On-Line Reconfigurable FPGA Architecture
Malware Detection on Linux Using Runtime Opcode Tracing
A Silicon Compiler for Fault-Tolerant ROMs
On-Chip Jitter Measurement for Phase Locked Loops
Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICs
An Architecture to Enable Life Cycle Testing in CMPs
Comparing fail-safe microcontroller architectures in light of IEC 61508
Reducing Power Dissipation during At-Speed Test Application
Failure Tests on 64 Mb SDRAM in Radiation Environment
A method to protect Bloom filters from soft errors
Analytic reliability evaluation for fault-tolerant circuit structures on FPGAs
Analysing degradation effects in charge-redistribution SAR ADCs
Dependability Analysis of CAN Networks: An Emulation-Based Approach
Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating Logic
Towards Biology-Inspired Fault Tolerance of Neuromorphic Hardware for Space Applications
Idle Cycles Based Concurrent Error Detection of RC6 Encryption
A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies
A Neural Network-Based Classifier for Glitch Detection in Clock Traces
Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines
An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals
MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories
An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring
Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis
CFBLT: A Closed Feed Back Loop Type Queuing System; Modeling and Analysis
Soft Errors induced by single heavy ions in Floating Gate memory arrays
Spare sharing network enhancement for scalable systems
Testing of In-Memory-Computing 8T SRAMs
Impact of Physical Defects on the Electrical Working of Embedded DRAM with 0.35B5m Design Rules
A Fault Tolerant Hierarchical Network on Chip Router Architecture
Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction
A New Algorithm for Post-Silicon Clock Measurement and Tuning
Orphan Metal Removal as an Element of DFM
Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator
Manufacturability Analysis of Analog CMOS ICs through Examination of Multiple Layout Solutions
A Simple via Duplication Tool for Yield Enhancement
Fault Recovery Based on Checkpointing for Hard Real-Time Embedded Systems
Functional Testing and Reconfiguration of MIMD Machines
An Application-Level Dependability Analysis Framework for Embedded Systems
JÄNES: A NAS Framework for ML-based EDA Applications
Partial Triple Modular Redundancy Method for Fault-Tolerant Circuit based on HITS Algorithm
INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling
Online hardening of programs against SEUs and SETs
Approximate compressors for error-resilient multiplier design
Modeling Quality Reduction of Multichip Module Systems due to Uneven Fault-Coverage and Imperfect Diagnosis
Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure
Permanent Fault Repair for FPGAs with Limited Redundant Area
Online Testable Reversible Logic Circuit Design using NAND Blocks
X-Ray Fault Injection: Reviewing Defensive Approaches from a Security Perspective
Bit-modular defect/fault-tolerant convolvers
Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems
Software-only based Diverse Redundancy for ASIL-D Automotive Applications on Embedded HPC Platforms
An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer Level
Preventing scan-based side-channel attacks through key masking
Delay Test Generation with All Reachable Output Propagation and Multiple Excitations
Test Generation for Stuck-at and Gate-Delay Faults in Sequential Circuits: A Mixed Functional/Structural Method
Realization of L2 Cache Defect Tolerance Using Multi-bit ECC
APSS Metrics for Fault Detection: Area, Position, Symmetry, and Shape in Image Segmentation
On the Testability of CMOS Feedback Amplifiers
An Integrated HW and SW Fault Injection Environment for Real-Time Systems
Layer assignment for yield enhancement
Robust Low-Cost Analog Signal Acquisition with Self-Test Capabilities
Adaptive Test Scheduling in SoC's by Dynamic Partitioning
REPAIR: Hard-error recovery via re-execution
Data Dependent Jitter (DDJ) Characterization Methodology
A Low-Cost Hardware Accelerator for CCSDS 123 Lossless Hyperspectral Image Compression
Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs
A runtime manager for gracefully degrading SoCs
Enhancing embedded SRAM security and error tolerance with hardware CRC and obfuscation
Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode
Error Control Coding for Multilevel Cell Flash Memories Using Nonbinary Low-Density Parity-Check Codes
Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections
Error Detection in Signed Digit Arithmetic Circuit with Parity Checker
Effects of Heavy Ion and Proton Irradiation on a SLC NAND Flash Memory
An Improved Reconfiguration Method for Degradable Processor Arrays Using Genetic Algorithm
Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses
Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits
A Framework to Evaluate the Trade-off among AVF Performance and Area of Soft Error Tolerant Microprocessors
Biased Voting for Improved Yield in Nanoscale Fabrics
A Unified Error Control Coding Scheme to Enhance the Reliability of a Hybrid Wireless Network-on-Chip
Control-Flow Recovery Validation Using Microarchitectural Invariants
SEU-Hardened Dual Data Rate Flip-Flop Using C-Elements
A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips
Multiple fault detection in logic resources of FPGAs
A Dual-Layer Fault Manager for systems based on Xilinx Virtex FPGAs
Error Identification and Data Recovery in MISR-based Data Compaction
Dynamic Input Match Correction in RF Low Noise Amplifiers
Reducing Test Power for Embedded Memories
Digital Generation of RF Phase-Modulated Test Stimuli: Application to BPSK Modulation Scheme
Coupling Different Methodologies to Validate Obsolete Microprocessors
Low-power LDPC decoder design exploiting memory error statistics
Logic Gate Failure Characterization for Nanoelectronic EDA Tools
Fault Tolerant Source Routing for Network-on-Chip
Design of Compact and High speed, Totally Self Checking CMOS Checkers for m-out-of-n Codes
Security analysis of logic encryption against the most effective side-channel attack: DPA
Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar Architecture
Prognosis of NBTI aging using a machine learning scheme
A Strategy for Interconnect Testing in Stacked Mesh Network-on-Chip
Incorporating parameter variations in BTI impact on nano-scale logical gates analysis
Optimizing Parametric BIST Using Bio-inspired Computing Algorithms
Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing
Built-in Self-Reconfiguring Systems for Fault Tolerant Mesh-Connected Processor Arrays by Direct Spare Replacement
Implementation of a Gracefully Degradable Binary Tree in Programmable
On-Line Periodic Self-Testing of High-Speed Floating-Point Units in Microprocessors
Impact of Aging Phenomena on Soft Error Susceptibility
CFEDR: Control-flow error detection and recovery using encoded signatures monitoring
Exploring Total Ionizing Dose Radiation Effects Across Generations of NVIDIA Jetson Devices: A Comparative Analysis
Delay Fault Testability on Two-Rail Logic Circuits
Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations
Some Results on Yield and Local Design Rule Relaxation
Design and implementation of a self-healing processor on SRAM-based FPGAs
Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols
A Design of Reliable Linear FSMs with Equivalent States in Stochastic Computing
An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing
A Flexible FPGA-Based Test Equipment for Enabling Out-of-Production Manufacturing Test Flow of Digital Systems
A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis
Defect and Fault Tolerance FPGAs by Shifting the Configuration Data
Efficient critical area estimation for arbitrary defect shapes
Single Event Upsets and Hot Pixels in digital imagers
Reconfiguration of Two-Dimensional Meshes Embedded in Faulty Hypercubes
A Multi-Modal Attention-Based Framework for Good Die in Bad Neighborhood Methodology
An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement
Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPU
Soft Error Modeling and Protection for Sequential Elements
High-energy neutrons characterization of a safety critical computing system
Computing at the Nanoscale
ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction
Embedded Core Testing Using Broadcast Test Architecture
In-place LUT polarity inVersion to mitigate soft errors for FPGAs
Online Missing/Repeated Gate Faults Detection in Reversible Circuits
A Case Study of ATPG Delay Path Performance Based on Measured Power Rail Integrity
Multiple Fault Detection in Nano Programmable Logic Arrays
Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA Platform
AI in space: applications examples and challenges
An Efficient Perfect Algorithm for Memory Repair Problems
Selective Hardening of CNNs based on Layer Vulnerability Estimation
Crosstalk Minimization in Three-Layer HVH Channel Routing
Automated formal approach for debugging dividers using dynamic specification
FPGA SEE Test with Ultra-High Energy Heavy Ions
An Analytical Error Model for Pattern Clipping in DNA Self-Assembly
Error Detection and Correction in Content Addressable Memories
Efficient time redundancy for error correcting inner-product units and convolvers
High Performance Memory Repair
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2020, Frascati, Italy, October 19-21, 2020
Construction of a soft error (SEU) hardened Latch with high critical charge
Hardware and software innovations in energy-efficient system-reliability monitoring
A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type
Transient pulse propagation using the Weibull distribution function
Reliability Estimation Model of ICs Interconnect Based on Uniform Distribution of Defects on a Chip
Detection of Yield Trends
A Software Methodology for Detecting Hardware Faults in VLIW Data Paths
Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention
Reliability Evaluation of Polyphase-filter based Decimators Implemented on SRAM-FPGAs
Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core
2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016, Storrs, CT, USA, September 19-20, 2016
BayWatch: Leveraging Bayesian Neural Networks for Hardware Fault Tolerance and Monitoring
Massively Deployable Intelligent Sensors for the Smart Power Grid
A novel method for SEE validation of complex SoCs using Low-Energy Proton beams
High-yield design of high-density SRAM for low-voltage and low-leakage operations
A Highly Robust Double Node Upset Tolerant latch
Software-Based Self-Test for Pipelined Processors: A Case Study
Design and Analysis of Self-Repairable MEMS Accelerometer
NBTI Monitoring and Design for Reliability in Nanoscale Circuits
Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems
Implementation of Concurrent Checking Circuits by Independent Sub-circuits
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation
Mixed structural-functional path delay test generation and compaction
Fine-Grained Software-Based Self-Repair of VLIW Processors
Error Identification and Data Retrieval in Signature Analysis based Data Compaction
Clock Calibration Faults and their Impact on Quality of High Performance Microprocessors
Self-checking FSMs based on a constant distance state encoding
Laser Processes for Defect Correction in Large Area VLSI Systems
Using value similarity of registers for soft error mitigation
A Fading Algorithm For Sequential Fault Diagnosis
Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study
Use of a Segmentation Technique to Analyze the Variability of the Yield of a Mature CMOS SRAM
A Fault Model to Detect Design Errors in Combinational Circuits
An Efficient Hardware-Based Fault Diagnosis Scheme for AES: Performances and Cost
Graceful Degradation in Synthesis of VLSI ICs
Fast Error-Correcting Newton-Raphson Dividers Using Time Shared TMR
Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors
2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2018, Chicago, IL, USA, October 8-10, 2018
Making defect avoidance nearly invisible to the user in wafer scale field programmable gate arrays
Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes
Coping with Obsolescence of Processor Cores in Critical Applications
Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems
Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis
Timing Failure Analysis of Commercial CPUs Under Operating Stress
Using Fourier Analysis to Enhance IC Testability
Reliability Enhancement of Analog-to-Digital Converters (ADCs)
Fault Detection in Sequential Circuits through Functional Testing
Predicting Pixel Defect Rates Based on Image Sensor Parameters
Efficient Error-Tolerant Quantized Neural Network Accelerators
SmartInjector: Exploiting intelligent fault injection for SDC rate analysis
Technology-aware system failure analysis in the presence of soft errors by Mixture Importance Sampling
Implementation and Reliability Evaluation of a RISC-V Vector Extension Unit
Functional Synchronization for Online Testing of Identical Logic Blocks
Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors
Templated-Based Asynchronous Design for Testable and Fail-Safe Operation
A novel Network-on-Chip security algorithm for tolerating Byzantine faults
On the Delay Analysis of Defective CNTFETs with Undeposited CNTs
Soft Core Embedded Processor Based Built-In Self-Test of FPGAs
Highly Reliable Systems with Differential Built-In Current Sensors
Characterizing soft error vulnerability of cache coherence protocols for chip-multiprocessors
Classes of difficult-to-diagnose transition fault clusters
Maximum Likelihood Estimation for Yield Analysis
A system-level scheme for resistance drift tolerance of a multilevel phase change memory
Fault-Tolerant CAM Architectures: A Design Framework
Scatter Scrubbing: A Method to Reduce SEU Repair Time in FPGA Configuration Memory
Testing Reversible One-Dimensional QCA Arrays for Multiple Faults
Dependable Systems and AI in Critical Infrastructures: A Case Study in European Earth Observation Missions
A Defect-Tolerant Molecular-Based Memory Architecture
Characterizing System-Level Vulnerability for Instruction Caches against Soft Errors
On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs
On the Impact of Electrical Masking and Timing Analysis on Soft Error Rate Estimation in Deep Submicron Technologies
Harvesting Through Array Partitioning: A Solution to Achieve Defect Tolerance
Multi-Dimensional Subsystem-Dividing for Yield Enhancement in Defect-Tolerant WSI Systems
Automatic Data Redundancy in Safety-Critical Applications Using Trait-Based Code Transformation
Thermal Driven Test Access Routing in Hyper-interconnected Three-Dimensional System-on-Chip
Learning Based on Fault Injection and Weight Restriction for Fault-Tolerant Hopfield Neural Networks
'BOND': An Interposition Agents Based Fault Injector for Windows NT
Reliability-aware synthesis and fault test of fully programmable valve arrays (FPVAs)
Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block
Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates
CMOS Standard Cells Characterization for IDDQ Testing
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains
A Systematic Approach for Diagnosing Multiple Delay Faults
The Effect of Placement on Yield for Standard Cell Designs
2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2011, Vancouver, BC, Canada, October 3-5, 2011
Modeling and analysis of repair and maintenance processes in Fault Tolerant Systems
Embedded Compact Deterministic Test for IP-Protected Cores
An improved approach to fault tolerant rank order filtering on a SIMD mesh processor
Network Fault Model for Dependability Assessment of Networked Embedded Systems
8-Bit Multiplier Simulation Experiments Investigating the Use of Power Supply Transient Signals for the Detection of CMOS Defects
Data Integrity Evaluations of Reed Solomon Codes for Storage Systems
A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube
On-Line Error Detectable Carry-Free Adder Design
Special Session: Impact of Compiler Optimizations on the Reliability of a RISC-V-Based Core
Memory Dynamic Faults and Array-Level Faults Detector in Digital Test Environment
20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA
Special Session Paper: FeMFET-Based High Performance, Ultra-Low Power Memory Cells for Reliable State Retention of Dataflow Networks
Coded DNA Self-Assembly for Error Detection/Location
Energy-efficient concurrent testing approach for many-core systems in the dark silicon age
Analysis of Defect to Yield Correlation on Memories: Method, Algorithms and Limits
A Self-Reconfiguration Architecture for Mesh Arrays
Analyzing the Single Event Upset Vulnerability of Binarized Neural Networks on SRAM FPGAs
EnSAFe: Enabling Sustainable SoC Security Auditing using eFPGA-based Accelerators
Region based containers - A new paradigm for the analysis of fault tolerant networks