yusuke1997/dblp-id-title huggingface dataset:
Using source-to-source compilation to instrument circuits for debug with High Level Synthesis
Live Migration for OpenCL FPGA Accelerators
Blokus Duo engine on a Zynq
Fine-grain fault diagnosis for FPGA logic blocks
Dynamic Intellectual Property Protection for Reconfigurable Devices
A Nearest Neighbor Search Engine Using Distance-Based Hashing
An Implementation of Trax player using programmable SoC
Secure Hardware Kernels Execution in CPU+FPGA Heterogeneous Cloud
HW/SW Interface Synthesis Based on Avalon Bus Specification for Nios-Oriented SoC Design
Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations
Acceleration of real-time Proximity Query for dynamic active constraints
A novel memory architecture for elliptic curve cryptography with parallel modular multipliers
Hardware-Accelerated Index Construction for Semantic Web
Deflection routing for multi-level FPGA overlay NoCs
A System-Level Transprecision FPGA Accelerator for BLSTM Using On-chip Memory Reshaping
ASKAP beamformer
Summarizing a time-sensitive control-flow checking monitoring for multitask systems-on-chip
An acceleration of a random forest classification using Altera SDK for OpenCL
Multiplier-less FIR digital filters using programmable sum-of-power-of-two (SOPOT) coefficients
Field-Programmable Dynamic Deep Learning
A new hardware coprocessor for accelerating Notification-Oriented applications
Variable pipeline structure for Coarse Grained Reconfigurable Array CMA
Hardware TCP Offload Engine based on 10-Gbps Ethernet for low-latency network communication
Evaluating power and energy consumption of FPGA-based custom computing machines for scientific floating-point computation
Integrating FPGA-based processing elements into a runtime for parallel heterogeneous computing
Implementation of a flexible RAKE receiver in heterogeneous reconfigurable hardware
FPGA based hardware accelerator for KAZE feature extraction algorithm
A co-simulation study of adaptive EPIC computing
Optimizing DNN Accelerator Compression Using Tolerable Accuracy Loss
Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing
Efficient management of custom instructions for run-time reconfigurable instruction set processors
Performance optimization of an FPGA-based configurable multiprocessor for matrix operations
Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs
GRAFT: GNN-based Adaptive Framework for Efficient CGRA Mapping
A Novel Network Architecture Support for Fast Reconfiguration
High-throughput IP-lookup supporting dynamic routing tables using FPGA
ReFiRe: Efficient Deployment of Remote Fine-Grained Reconfigurable Accelerators
GridGAS: An I/O-Efficient Heterogeneous FPGA+CPU Computing Platform for Very Large-Scale Graph Analytics
Graph minor approach for application mapping on CGRAs
FPGA-accelerated key search for cold-boot attacks against AES
A methodology for design of run-time reconfigurable systems
hCODE: An open-source platform for FPGA accelerators
The Egret platform for reconfigurable system on chip
A custom instruction approach for hardware and software implementations of finite field arithmetic over F 2 63 using Gaussian normal bases
FPGA Cluster Computing in the ETA Radio Telescope
Convex models for accelerating applications on FPGA-based clusters
A unified accelerator design for LiDAR SLAM algorithms for low-end FPGAs
2013 International Conference on Field-Programmable Technology, FPT 2013, Kyoto, Japan, December 9-11, 2013
FPGA implementation of a fuzzy controller for automobile DC-DC converters
A high speed open source controller for FPGA Partial Reconfiguration
Analyzing the divide between FPGA academic and commercial results
Delay evaluation of 90nm CMOS multi-context FPGA with shift-register-type temporal communication module for large-scale circuit emulation
The architecture and placement algorithm for a uni-directional routing based 3D FPGA
Dynamic Stencil: Effective exploitation of run-time resources in reconfigurable clusters
A scalable network port scan detection system on FPGA
A new flexible PR domain model to replace the fixed multi-PR region model for DPR systems
A Hardware-Friendly Rotation Convolution Neural Network and its FPGA Implementation for Remote Sensing Scene Classification
FPGA implementation of reconfigurable ADPLL network for distributed clock generation
Investigation of aging effects in different implementations and structures of programmable routing resources of FPGAs
Alternatives in FPGA-based SAD implementations
Exponential sine sweep measurement implementation targeting FPGA platforms
The Impact of Hardware Folding on Dependability in Spaceborne FPGA-based Neural Networks
A Table Look-Up Based Quantum Simulation Accelerator on an FPGA
A Lane Detection Hardware Algorithm Based on Helmholtz Principle and Its Application to Unmanned Mobile Vehicles
An on-chip testbed that emulates runtime traffic and reduces design verification time for FPGA designs
On the placement and granularity of FPGA configurations
High-level synthesis - the right side of history
FPGA-acceleration of cone-beam reconstruction for the X-ray CT
Population based ant colony optimization on FPGA
Accelerating hardware simulation: Testbench code emulation
Secure Partial Reconfiguration of FPGAs
Reconfiguration requirements for high speed wireless communication systems
Implementation of parallel medical ultrasound imaging algorithm on CAPI-enabled FPGA
The Design of Scalable Stochastic Biochemical Simulator on FPGA
VIB: A Versatile Interconnection Block for FPGA Routing Architecture
Formulation-level design space exploration for partially reconfigurable FPGAs
Invited Keynote 2: Applications of programmable logic in modern particle physics experiments
Switch-box design for synthesizable coarse-grain arrays for system-on-chip applications
A parallel look-up logarithmic number system addition/subtraction scheme for FPGA
Flexible hierarchy ray tracing on FPGAs
A Dynamic Partial Reconfigurable CGRA Framework for Multi-Kernel Applications
A fast, energy efficient, field programmable threshold-logic array
FPGA Implementation of a Statically Reconfigurable Java Environment for Embedded Systems
Custom-sized caches in application-specific memory hierarchies
FFPU: Fractured floating point unit for FPGA soft processors
Hardware acceleration of approximate palindromes searching
DaCO: A High-Performance Token Dataflow Coprocessor Overlay for FPGAs
A low power technology mapping method for Adaptive Logic Module
A Portable Co-Verification System Which Generates Testbench Automatically
An optically differential reconfigurable gate array and its power consumption estimation
FPGA-based Streaming Computation for Lattice Boltzmann Method
Hardware Trojan detection acceleration based on word-level statistical properties management
Enabling Overclocking Through Algorithm-Level Error Detection
Performance of Sorting Algorithms on the SRC 6 Reconfigurable Computer
Accelerating FPGA design space exploration using circuit similarity-based placement
byteman: A Bitstream Manipulation Framework
Efficient execution of augmented reality applications on mobile programmable accelerators
Debugging processors with advanced features by reprogramming LUTs on FPGA
Model-based hardware design based on compatible sets of isomorphic subgraphs
High Performance Hardware Implementation of SpikeProp Learning: Potential and Tradeoffs
A high-speed ray tracing engine built on a field-programmable system
ULP-SRP: Ultra low power Samsung Reconfigurable Processor for biomedical applications
A parameterizable HandelC divider generator for FPGAs with embedded hardware multipliers
FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks
Stream applications on the dynamically reconfigurable processor
Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes
Design space exploration and implementation of a high performance and low area Coarse Grained Reconfigurable Processor
High-Radix Systolic Modular Multiplication on Reconfigurable Hardware
Semantics-directed machine architecture in ReWire
Design Multi-Model Accelerators via Automatically Extracting Computational Graph Similarities
Desgin and Implementation of ROS2-based Autonomous Tiny Robot Car with Integration of Multiple ROS2 FPGA Nodes
Optimizing the critical loop in the H.264/AVC CABAC decoder
Automatic circuit design and modelling for heterogeneous FPGAs
Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture
Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks
Re-visiting the challenges of programmable concurrent architectures
Profiling-Based Control-Flow Reduction in High-Level Synthesis
Efficient and High-Throughput Implementations of AES-GCM on FPGAs
Reconfigurable hardware implementation of mesh routing in number field sieve factorization
Structured ASIC: Methodology and comparison
Adaptive range reduction for hardware function evaluation
Efficient Physical Page Migrations in Shared Virtual Memory Reconfigurable Computing Systems
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, FPT 2002, Hong Kong, China, December 16-18, 2002
AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-based Lightweight PQC
Development productivity in implementing a complex heterogeneous computing application
An implementation of the Rijndael on Async-WASMII
NICFlex: A Functional Verification Accelerator for An RTL NIC Design
Implementation of a foveal vision mapping
Real-time and low power embedded ℓ1-optimization solver design
All binarized convolutional neural network and its implementation on an FPGA
Stream-Based ORB Feature Extractor with Dynamic Power Optimization
Assuring Netlist-to-Bitstream Equivalence using Physical Netlist Generation and Structural Comparison
Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays
An efficient RTL buffering scheme for an FPGA-accelerated simulation of diffuse radiative transfer
Energy minimization in the time-space continuum
FPGA implementation of tabu search for the quadratic assignment problem
FPGA-based ORB feature extraction for real-time visual SLAM
On-chip communication architectures for reconfigurable System-on-Chip
A novel three phase parallel genetic approach to routing for field programmable gate arrays
Partially reconfigurable system-on-chips for adaptive fault tolerance
Placement and routing for non-rectangular embedded programmable logic cores in SoC design
LUTNet-RC: Look-Up Tables Networks for Reservoir Computing on an FPGA
PowerBit - power aware arithmetic bit-width optimization
Network recorder and player: FPGA-based network traffic capture and replay
Architecture template with dynamic buffering for runtime reconfiguration of adaptive embedded communication systems
Transparent Acceleration of Image Processing Kernels on FPGA-Attached Hybrid Memory Cube Computers
A Lightweight FPGA-based IDS-ECU Architecture for Automotive CAN
International Conference on Field Programmable Technology, ICFPT 2023, Yokohama, Japan, December 12-14, 2023
Development of Autonomous Driving System based on Image Recognition using Programmable SoCs
Area-Efficient Memory Scheduling for Dynamically Scheduled High-Level Synthesis
A high-throughput FPGA architecture for parallel connected components analysis based on label reuse
Seed-based genomic sequence comparison using a FPGA/FLASH accelerator
An FPGA-based processor for training convolutional neural networks
Reconfigurable implementation of bit-parallel multipliers over GF(2 m ) for two classes of finite fields
FPGA implementation and analysis of random delay insertion countermeasure against DPA
An energy-efficient near/sub-threshold FPGA interconnect architecture using dynamic voltage scaling and power-gating
Partial character decoding for improved regular expression matching in FPGAs
Estimation of sample mean and variance for Monte-Carlo simulations
DRESC: a retargetable compiler for coarse-grained reconfigurable architectures
SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs
An adaptive cross-layer fault recovery solution for reconfigurable SoCs
A many processing element framework for the Discrete Fourier Transform
An FPGA-cluster-accelerated match engine for content-based image retrieval
MERCURY: An Automated Remote Side-channel Attack to Nvidia Deep Learning Accelerator
FPGA Accelerated HPC and Data Analytics
Placement and routing for FPGA architectures supporting wide shallow memories
MultiMQC: A Multilevel Message Queuing Cache Combining In-NIC and In-Kernel Memories
Parallel-Pipeline Fast Walsh-Hadamard Transform Implementation Using HLS
Quality & Generality: A Flexible FPGA Re-Clustering Technique to Improve Packing and Placement
Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGA
Load Balanced Sparse Bundle Adjustment Accelerator for CNN-Based Visual-Inertial Odometry on FPGA
Implementation of Elliptic Curve Cryptosystems on a reconfigurable computer
PipeCNN: An OpenCL-based open-source FPGA accelerator for convolution neural networks
The diversity study of AES on FPGA application
An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guarantee
Floating-Point Matrix Multiplication in a Polymorphic Processor
A novel three-dimensional FPGA architecture with high-speed serial communication links
Cryptographic techniques in redundant number systems
Memory-efficient RMT Matching Optimization Based on MBitTree
High level quantitative interconnect estimation for Early Design Space Exploration
FPGA acceleration of reference-based compression for genomic data
Novel Neural Network Applications on New Python Enabled Platforms
A scalable hardware architecture for prime number validation
A comparison of 2-D discrete wavelet transform computation schedules on FPGAs
P3Net: PointNet-based Path Planning on FPGA
Dataflow Systolic Array Implementations of Exploring Dual-Triangular Structure in QR Decomposition Using High-Level Synthesis
Memory specification for reconfigurable computing synthesis tools
A configurable framework for investigating workload execution
Efficient Stride 2 Winograd Convolution Method Using Unified Transformation Matrices on FPGA
A dataflow system for anomaly detection and analysis
An FPGA Implementation of Robust Matting
FSLAM: an Efficient and Accurate SLAM Accelerator on SoC FPGAs
Accelerating on-line training of LS-SVM with run-time reconfiguration
FPGA-Based 3-D engine for high-speed 3-D measurement based on light-section method
An FPGA implementation of the simplex algorithm
Reconfigurable Number Theoretic Transform architectures for cryptographic applications
A Programmable Configuration Controller for fault-tolerant applications
A method of implementing bit-serial LDI ladder filters in FPGAs using JBits
Image fusion for uninhabited airborne vehicles
Application debug in FPGAs in the presence of multiple asynchronous clocks
A new coarse-grained FPGA architecture exploration environment
Low-latency option pricing using systolic binomial trees
Performance evaluations of ReconfigME
Streamed high dynamic range imaging
Offloading Image Recognition Processing for Care Robots to FPGA on Multi-access Edge Computing
An FPGA based coprocessor for 3D affine transformations
Datapath fault tolerance for parallel accelerators
Enabling high level design of adaptive systems with partial reconfiguration
EXPRESS: CNN EXecution Time PREdiction for DPU DeSign Space Exploration
Synthesis of program binaries into FPGA accelerators with runtime dependence validation
Rapid design space exploration for soft core processor customization and selection
hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds
Tatum: Parallel Timing Analysis for Faster Design Cycles and Improved Optimization
Performance Estimation for Exascale Reconfigurable Dataflow Platforms
Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis
RTOS acceleration on soft-core processors using instruction set customization
FPGA-accelerated Monte-Carlo integration using stratified sampling and Brownian bridges
Quantum FPGA architecture design
Why Put FPGAs in your CPU socket?
A connection-based router for FPGAs
Boosting Domain-Specific Debug Through Inter-frame Compression
Option space exploration using distributed computing for efficient benchmarking of FPGA cryptographic modules
High-performance pipeline architecture for packet classification accelerator in DPU
Collaborative processing of Least-Square Monte Carlo for American options
An FPGA-GPU Heterogeneous System and Implementation for On-Board Remote Sensing Data Processing
Network-attached FPGAs for data center applications
CGRA-HD: An Efficient Reconfigurable Accelerator for Hyperdimensional Computing: (PhD Forum Paper)
Design and implementation of a novel architecture for symmetric FIR filters with boundary handling on Xilinx Virtex FPGAs
Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities
Verification of streaming hardware and software codesigns
Compiling run-time parametrisable designs
Real-time high-quality stereo vision system in FPGA
Design and implementation of open-source SATA III core for Stratix V FPGAs
Correction to "Graph Minor Approach for Application Mapping on CGRAs"
Beyond performance: secure and fair memory management for multiple systems on a chip
A low power reconfigurable accelerator using a back-gate bias control technique
On the Malicious Potential of Xilinx' Internal Configuration Access Port (ICAP)
HGBO-DSE: Hierarchical GNN and Bayesian Optimization based HLS Design Space Exploration
Online scheduling for FPGA computation in the Cloud
Lightweight DPA resistant solution on FPGA to counteract power models
Towards automatic partial reconfiguration in FPGAs
Random stimuli generation based on a stochastic context-free grammar
An FPGA with power-gated switch blocks
The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator
FPGA-based system-level design framework based on the IRIS synthesis tool and System Generator
FLiMS: Fast Lightweight Merge Sorter
GVE: Godson-T Verification Engine for many-core architecture rapid prototyping and debugging
Hardware/software co-design architecture for Blokus Duo solver
A gate-level model for morphogenetic evolvable hardware
A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis
Reconfigurable Hardware Module Sequencer - A Tradeoff Between Networked and Data Flow Architectures
Routing optimizations for component-based system design and partial run-time reconfiguration on FPGAs
An FPGA-Based Image Recognition with Remote Update Functions for Autonomous Driving on "ad-refkit"
A Fast and Efficient FPGA-Based Implementation for Solving a System of Linear Interval Equations
Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters
Advanced Bayer demosaicing on FPGAs
High Performance Software-Hardware Network Intrusion Detection System
Self-characterization of Combinatorial Circuit Delays in FPGAs
Automating customized computing
FPGA-based Accelerator Design for RankBoost in Web Search Engines
Interface adaptor logic - a new model for interfacing peripherals in IP based designs
High performance serial ATA Gen3 controllers on FPGA devices
Technology issues facing the world's largest integrated circuits
A Reconfigurable Architecture for Implementing Multiple Cipher Algorithms
Area and time efficient implementations of matrix multiplication on FPGAs
Constant power reconfigurable computing
An analysis of ring oscillator PUF behavior on FPGAs
Application Acceleration on FPGAs with OmpSs@FPGA
Hardware-Efficient FPGA-Based Approximate Multipliers for Error-Tolerant Computing
FINN-T: Compiling Custom Dataflow Accelerators for Quantized Transformers
Networking on chip with platform FPGAs
Dynamic Loading of Peripherals on Reconfigurable System-on-Chip
A 62.5 ns holographic reconfiguration of an optically differential reconfigurable gate array
Perturber: semi-synthetic circuit generation using ancestor control for testing incremental place and route
A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks
Design considerations of real-time adaptive beamformer for medical ultrasound research using FPGA and GPU
Rapid prototyping tools for FPGA designs: RapidSmith
Random projections for scaling machine learning on FPGAs
S5: The Architecture and Development Flow of a Software Configurable Processor
Histogram-based probability density function estimation on FPGAs
The next big leap in reconfigurable systems
An open-source SATA core for Virtex-4 FPGAs
Spiking neural network-based auto-associative memory using FPGA interconnect delays
A Tri-State Weight Convolutional Neural Network for an FPGA: Applied to YOLOv2 Object Detector
Area efficient floating-point adder and multiplier with IEEE-754 compatible semantics
An FPGA-based text search engine for approximate regular expression matching
Optimisation of Convolution of Multiple Different Sized Filters in SKA Pulsar Search Engine
3D graphics accelerator platform for mobile devices
Synthesizable Heterogeneous FPGA Fabrics
Efficient methods for out-of-order load/store execution for high-performance soft processors
An FPGA-based tree crown detection approach for remote sensing images
FPGA based soft-core SIMD processing: A MIMO-OFDM Fixed-Complexity Sphere Decoder case study
Optimal temporal partitioning based on slowdown and retiming
Retiming aware clustering for sequential circuits
Time-independent discrete Gaussian sampling for post-quantum cryptography
Invited Keynote 1: Closing the gap between FPGAs and ASICs
Makespan minimization in automatic synthesis of multiprocessor systems from parallel programs
Programmable parallel coprocessor architectures for reconfigurable system-on-chip
An area-efficient FPGA realisation of a codebook-based image compression method
Memory optimisations for high-resolution imaging
From TLM to FPGA: Rapid Prototyping with SystemC and Transaction Level Modeling
Phase-change-memory-based storage elements for configurable logic
HEPPO: Hardware-Efficient Proximal Policy Optimization a Universal Pipelined Architecture for Generalized Advantage Estimation
Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures
FPGA-based MSB-first bit-serial variable block size motion estimation processor
Scalable and Flexible High-Performance In-Network Processing of Hash Joins in Distributed Databases
Efficient implementation of CIOQ switches with sequential iterative matching algorithms
Improving Bounds for FPGA Logic Minimization
AMG: Automated Efficient Approximate Multiplier Generator for FPGAs via Bayesian Optimization
Performance characterization of Altera and Xilinx 28 nm FPGAs at cryogenic temperatures
Netlist-level IP protection by watermarking for LUT-based FPGAs
A scalable memory interface for multicore reconfigurable computing systems
Cloning the Unclonable: Physically Cloning an FPGA Ring-Oscillator PUF
A high-performance and high-programmability reconfigurable wireless development platform
FPGA implementation of an interior point solver for linear model predictive control
Custom Hardware Architectures for Posture Analysis
Directional and single-driver wires in FPGA interconnect
Othello Solver based on a soft-core MIMD processor array
Net Power Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs
Combined run-time area allocation and long line re-routing for reconfigurable computing
Exploring Inter-tile Connectivity for HPC-oriented CGRA with Lower Resource Usage
Accelerated cell imaging and classification on FPGAs for quantitative-phase asymmetric-detection time-stretch optical microscopy
Evolution-based automated reconfiguration of field programmable analog devices
Application-specific hardware accelerator for implementing recursive sorting algorithms
Autonomous driving system with feature extraction using a binarized autoencoder
The challenges of using an embedded MPI for hardware-based processing nodes