yusuke1997/dblp-id-title huggingface dataset:
A Method for Test System Diagnostics Based on the Principles of Artificial Intelligence
Low cost characterization of RF transceivers through IQ data analysis
Testing High Frequency ADCs and DACs with a Low Frequency Analog Bus
Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment?
A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic
Asian Test Symposium - Past, Present and Future -
Stuck-fault tests vs. actual defects
Boolean and current detection of MOS transistor with gate oxide short
Combinational Logic Soft Error Correction
Data learning techniques and methodology for Fmax prediction
Professional Aspects of Test Engineering
A practical built-in current sensor for I_DDQ testing
Representative critical-path selection for aging-induced delay monitoring
Pattern Pruner: Automatic Pattern Size Reduction Method that Uses Computational Intelligence-Based Testing
Bit Error Rate Estimation for Improving Jitter Testing of High-Speed Serial Links
Estimating the Quality of Manufactured Digital Sequential Circuits
Handling wrong mapping: A new direction towards better diagnosis with low pin convolution compressors
Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion
A Unified Method of Designing Signature Analyzers for Digital and Mixed-Signal Circuits Testing
Feature engineering with canonical analysis for effective statistical tests screening test escapes
The implementation and application of a protocol aware architecture
Cost-effective designs of field service for electronic systems
High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips
A New Test Generation Approach for Embedded Analogue Cores in SoC
Progressive random access scan: a simultaneous solution to test power, test data volume and test time
Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions
i DD Pulse Response Testing of Analog and Digital CMOS Circuits
Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count
Characterization of High-Speed (Above 50 MHz) Devices Using Advance ATE-Techniques, Results and Device Problems
Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing
What's So Different about Deep-Submicron Test?
Unsafe board states during PC-based boundary-scan testing
Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions
Accumulator based deterministic BIST
"Real Life" System Testing of Networking Equipment
Applying Quality Curves for Economic Comparison of Alternative Test Strategies
A layout-based approach for ordering scan chain flip-flops
Improving Volume Diagnosis and Debug with Test Failure Clustering and Reorganization
Preparation of Product Test Plans
FPGA Bitstream Security: A Day in the Life
Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor
Design rule check on the clock gating logic for testability and beyond
The case for outsourcing DFT
MUST: multiple-stem analysis for identifying sequentially untestable faults
A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs
Cost Effective Frequency Measurement for Production Testing
Increasing PRPG-based compression by delayed justification
A High-Resolution Waveform Analysis Tool
Logic characterization vehicle design reflection via layout rewiring
On Random Pattern Test Length
Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology
Layout-aware 2-step window-based pattern reordering for fast bridge/open test generation
Needs fabless yield ramp foundry partnership to be most successful
Efficient Built-In Self-Test Scheme for Inter-Die Interconnects of Chiplet-Based Chips
An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test
Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA
New tools and methodology for advanced parametric and defect structure test
Embedded X86 testing methodology
Deploying A Machine Learning Solution As A Surrogate
Sure You Can Get to 100 DPPM in Deep Submicron, But It'll Cost Ya
Required - A Portable Test Standard
Concurrent Checking of Program Flow in VLSI Processors
Analyzing a PowerPC TM 620 Microprocessor Silicon Failure Using Model Checking
Achieving high transition delay fault coverage with partial DTSFF scan chains
Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery
Transfer Function Estimation Part II : Some Experimental Results
Board Test Session I
Beyond the Byzantine Generals: Unexpected Behaviour and Bridging Fault Diagnosis
Integrating CrossCheck Technology into the Raytheon Test Environment
Defect-Directed Stress Testing Based on Inline Inspection Results
A Method of Improving In-Circuit Test Effectiveness
Fault Resilience Techniques for Flash Memory of DNN Accelerators
Experience in Diagnosing a Remote, Tele-Controlled Unit Using the AITEST Expert System
Scan chain securization though Open-Circuit Deadlocks
A new path-oriented effect-cause methodology to diagnose delay failures
A Framework and Method for Hierarchical Test Generation
Timing Accuracy and Yield Estimation
A Study of the Error Behavior of a 32-bit RISC Subjected to Simulated Transient Fault Injection
ATE Test Head Requirements for Low-Cost VLSI Testing
Various Architectures of Systems for Measuring Early-Life Failure Rates of Semiconductor Components
Automated Assertion Generation from Natural Language Specifications
Parallel pattern fault simulation based on stem faults in combinational circuits
A New Approach to On-Board Microprocessor-Based Self-Test
Don't forget to lock your SIB: Hiding instruments using P16871
IC Defects-Based Testability Analysis
End-to-end testing for boards and systems using boundary scan
Towards 100% Testable FIR Digital Filters
The Process and Challenges of a High-Speed DUT Board Project
Combinational test generation for various classes of acyclic sequential circuits
Recycled FPGA detection using exhaustive LUT path delay characterization
Scan Strategies for High Quality Latch Array Testing
Testability-Enhancing Resynthesis of Reconfigurable Scan Networks
A method of serial data jitter analysis using one-shot time interval measurements
TAMED: Transitional Approaches for LFI Resilient State Machine Encoding
Test cost reduction for the AMD™ Athlon processor using test partitioning
FIFO Test Program Development
Open Architecture ATE and 250 Consecutive UIs
1149.1 Scan Control Transport Levels
A Vote in Favor of Fault Simulation
Keynote address tuesday: Challenges in mobile devices: Process, design and manufacturing
Reliability Study of 14 nm Scan Chains and Its Application to Hardware Security
Transient Fault Pruning for Effective Candidate Reduction in Functional Debugging
Challenges and Solutions for Multi-Gigahertz Testing
Board-Level Diagnosis by Signature Analysis
Experiences with non-intrusive sensors for RF built-in test
A vector-based approach for power supply noise analysis in test compaction
AgentDiag: An agent-assisted diagnostic framework for board-level functional failures
Variation-Aware Hardware Trojan Detection through Power Side-channel
Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks
Wafer Level Chip Scale Package copper pillar probing
Steering Committee and Subcommittees
A selt-testing BOST for high-frequency PLLs, DLLs, and SerDes
IC Quality and Test Transparency
A Study of Outlier Analysis Techniques for Delay Testing
Electrical Troubleshooting, Diagnostics, and Repair of Multichip Modules
Finding I/O Faults on In-Circuit ICs Using Parasitic Transistor Tests
Digital Design Techniques for Dependable High Performance Computing
LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency
Analog Fault Simulation: Need it? No. It is already done
On Combining Design for Testability Techniques
Self-Testing and Self-Healing via Mobile Agents
An empirical study on the effects of test type ordering on overall test efficiency
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs
Identification of crosstalk switch failures in domino CMOS circuits
Visualizing Quality
HITEST : Intelligent Test Generation
Diversified Testing
Sequentially Untestable Faults Identified Without Search ("Simple Implications Beat Exhaustive Search!")
Modifying User-Defined Logic for Test Access to Embedded Cores
Considerations for implementing IEEE 1149.1 on system-on-a-chip integrated circuits
Intra-die process variation aware anomaly detection in FPGAs
Testing A/D Converters on Microcomputers
Hardware-Based Weighted Random Pattern Generation for Boundary Scan
Scan Based Testing of Dual/Multi Core Processors for Small Delay Defects
17th IEEE East-West Design and Test Symposium
Statistical outlier screening as a test solution health monitor
CIM , Electronics Manufacturing and ATE
Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests
Full-scan LBIST with capture-per-cycle hybrid test points
Hierarchical test assembly for macro based VLSI design
Re-Using DFT Logic for Functional and Silicon Debugging Test
Is Burn-In Burned-Out - Part 2
Board Test Is NOT Mature
Post-production performance calibration in analog/RF devices
ISDN Device Testing Demands a New Level of Performance for Automatic Test Equipment
Designing for scan test of high performance embedded memories
Modeling facet roughening errors in self-assembly by snake tile sets
Overview of the IEEE P1500 Standard
Universal Tests Detecting Input/Output Faults in Almost All Devices
A design flow to maximize yield/area of physical devices via redundancy
A Comprehensive Approach to Test Program Debugging for High Performance VLSI Test Systems
Using Simulation in the Design Process - A Case Study
Integration of Hardware Assertions in Systems-on-Chip
Optimal conditions for Boolean and current detection of floating gate faults
Cell-Based Test Design Method
Practical scan test generation and application for embedded FIFOs
Matching Models to Real Life for Defect Reduction
High level test bench generation using software engineering concepts
Towards a standard approach for controlling board-level test functions
A 16-bit resistor string DAC with full-calibration at final test
Panel: Increasing test coverage in a VLSI desgin course
Fault Tolerance for RRAM-Based Matrix Operations
IC Failure Analysis Tools and Techniques - Macig, Mystery, and Science
ASIC Yield Estimation at Early Design Cycle
CMOS bridging fault detection
Overview of a High Speed Top Side Socket Solution
Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks
Is Analog Fault Simulation a Key to Product Quality? Practical Considerations
Wafer-Level Defect-Based Testing Using Enhanced Voltage Stress and Statistical Test Data Evaluation
Optimizing the Timing Architecture of a Digital LSI Test System
The Autopal Test Process
A Computer Architecture for High Pin Count Testers
Real-Time Automatic Calibration of Analog Test Systems
Improvement of the tolerated raw bit error rate in NAND flash-based SSDs with the help of embedded statistics
Backdrive Stress-Testing of CMOS Gate Array Circuits
Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling
Jitter Testing for Multi-Gigabit Backplane SerDes - Techniques to Decompose and Combine Various Types of Jitter
MINiature Interactive Offset Networks (MINIONs) for Wafer Map Classification
High Speed IO Access for Test forms the foundation for Silicon Lifecycle Management
Dynamic Testing of ADCs Using Wavelet Transforms
Are the IC guys helping or hindering board test?
A New Method for Partial Scan Design Based on Propagation and Justification Requirements of Faults
Device-Aware Test: A New Test Approach Towards DPPB Level
A method to improve SFDR with random interleaved sampling method
A Multi-Level Test Pattern Generation and Validation Environment
A distributed, reconfigurable, and reusable bist infrastructure for 3D-stacked ICs
Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model
Tree-Structured Linear Cellular Automata and Their Applications as PRPGs
Comparison of AC Self-Testing Procedures
A deterministic BIST scheme based on EDT-compressed test patterns
Itelligent Agents and BIST/BISR - Working Together in Distributed Systems
Test Data Encryption with a New Stream Cipher
A Case Study of Using IEEE P1687 (IJTAG) for High-Speed Serial I/O Characterization and Testing
Fast test generation for circuits with RTL and gate-level views
X-Masking During Logic BIST and Its Impact on Defect Coverage
Testing of Vega2, a chip multi-processor with spare processors
Board Test: Wanted Dead or Alive
A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation
A Mixed Functional/IDDQ Testing Methodology for CMOS Transistor Faults
A method to improve the performance of high-speed waveform digitizing
Improving the Quality of Test Education
Visual Programming for Analog/Hybrid ATE
Novel Transient Fault Hardened Static Latch
Experimental Results for High-Speed Jitter Measurement Technique
Fundamental Limits to Timing Accuracy
A BIST Scheme for an SNR Test of a Sigma-Delta ADC
Value of Testability Standards in Testing Commercial Products
IEEE P1581 can solve your board level memory cluster test problems
ASIC CAD system based on hierarchical design-for-testability
Limited access testing: IEEE 1149.4-instrumentation and methods
Contactors for Testing at High Frequencies
PC manufacturing test in a high volume environment
Isolating and Removing Sources of Variation in Test Data
Performance enhancement of a WCDMA/HSDPA+ receiver via minimizing error vector magnitude
An evaluation of defect-oriented test: WELL-controlled low voltage test
Timing Measurements on CMOS VLSI Devices Designed to Drive TTL Loads
Random Pattern Testing for Data-Line Faults in an Embedded Multiport Memory
Circuit Pack BIST from System to Factory - The MCERT Chip
MBIST-based MRAM defect screening for safety-critical applications
Location and Identification for Single and Multiple Faults in Testable Redundant PLAs for Yield Enhancement
Structure and Metrology for a Single-wire Analog
On the generation of compact test sets
A Strategy for Generating Functional Tests from Device Simulations
Is Burn-In Burned Out?
Calculation of Greatest Lower Bounds Obtainable by the Cutting Algorithm
Testability Features of AMD-K6 TM Microprocessor
Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing
A new probing technique for high-speed/high-density printed circuit boards
User Application of Statistical Process Monitor Techniques to ASIC Critical Parameters
A Full-Stack Approach for Side-Channel Secure ML Hardware
STAR-ATPG: a high speed test pattern generator for large scan designs
Diagnosis and characterization of timing-related defects by time-dependent light emission
A Design for Complete Testability of Programmable Logic Arrays
Unsupervised Learning-based Early Anomaly Detection in AMS Circuits of Automotive SoCs
Programming of flash with ICT rights and responsibilities
Clustering based techniques for I_DDQ testing
DFM - An Industry Paradigm Shift
Self-checking scheme for very fast clocks' skew correction
Test Requirements for Embedded Core-Based Systems and IEEE P1500
The P1149.4 Mixed Signal Test Bus: Costs and Benefits
Panel Statement: Increasing test coverage in a VLSI design course
The case for analyzing system level failures using structural patterns
Test Challenges of Intel IA Cores
Early Soft Error Reliability Assessment of Convolutional Neural Networks Executing on Resource-constrained IoT Edge Devices
Test and repair of large embedded DRAMs. I
A Framework for Boundary-Scan Based System Test Diagnosis
Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on automotive designs
Rapid Data Acquisition for E-Beam Testing
Boundary-scan adoption - an industry snapshot with emphasis on the semiconductor industry
Crosstalk test generation on pseudo industrial circuits: a case study
probe card-a solution for at-speed, high density, wafer probing
Signature Analysis: Yet Another Perspective
Efficient Analog Defect Simulation
Sigma-delta ADC characterization using noise transfer function pole-zero tracking
Biochip-PUF: Physically Unclonable Function for Microfluidic Biochips
Testing an MCM for high-energy physics experiments: a case study
Diagnosis of Defects on Global Signals
Proposal to Simplify Development of a Mixed-Signal Test Standard
System Level Fault Dictionary Generation
X-canceling MISR - An X-tolerant methodology for compacting output responses with unknowns using a MISR
A Logic Analyzer Tool That Cuts E-Beam Prober Acquisition Times
Spatial estimation of wafer measurement parameters using Gaussian process models
Analog and Mixed-Signal Benchmark Circuits-First Release
SiPROBE - A New Technology for Wafer Probing
Non-intrusive detection of defects in mixed-signal integrated circuits using light activation
Fail Memory Configuration Set for RA Estimation
BIST for 1149.1-Compatible Boards: A Low-Cost and Maximum-Flexibility Solution
Defects, Fault Coverage, Yield and Cost in Board Manufacturing
Structural tests for jitter tolerance in SerDes receivers
A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories
Proceedings International Test Conference 1986, Washington, D.C., USA, September 1986
An Approach to Functional Level Testability Analysis
Static component interconnection test technology in practice
On-Chip Toggle Generators to Provide Realistic Conditions during Test of Digital 2D-SoCs and 3D-SICs
The IEEE P1149.5 MTM-Bus, A Backplane Test and Initialization Interface
Generating interconnect models from prototype hardware
On the Design of Self-Checking Boundary Scannable Boards
Testability Emphasis in the General Electric A/VLSI Program
Tradeoff Decisions Made for P11149.1 Controller Design
A New Approach for Low Power Scan Testing
Resistive bridge fault modeling, simulation and test generation
A mixed mode BIST scheme based on reseeding of folding counters
Characteristic Impedance and Coupling Coefficients for Multilayer PC Boards
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms
Design for Test Approaches to Mixed-Signal Testing
Real-Time Product Characterization by Fault Modeling and Pattern Recognitions
Measuring Thermal Rises Due to Digital Device Overdriving
Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges
A roaming memory test bench for detecting particle induced SEUs
An Overview of the International Verification and Security Workshop (IVSW)
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy
Accounting for the unexpected: fault diagnosis out of the ivory tower
Very-Low Voltage (VLV) and VLV Ratio (VLVR) Testing for Quality, Reliability, and Outlier Detection
Artificial Neural Network Based Test Escape Screening Using Generative Model
Shmoo Plots - the Black Art of IC Test
Counterfeit electronics: A rising threat in the semiconductor manufacturing industry
At-speed DfT Architecture for Bundled-data Design
Design for Manufacturability - or the meaning of 'subtle'
On-chip power supply noise measurement using Time Resolved Emission (TRE) waveforms of Light Emission from Off-State Leakage Current (LEOSLC)
CONCAT: CONflict Driven Learning in ATPG for Industrial designs
Concerns over predictability of supply and quality
Modeling the unknown! Towards model-independent fault and error diagnosis
Toward Fault-Tolerant Applications on Reconfigurable Systems-on-Chip
A multiple seed linear feedback shift register
Boundary Scan with Cellular-Based Built-In Self-Test
Generalization of an outlier model into a "global" perspective
A probe scheduling algorithm for MCM substrates
Production-oriented interface testing for PCI-Express by enhanced loop-back technique
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis
ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults
Output bit selection methodology for test response compaction
Production Test and Repair of 256K Dynamic RAMS with Redundancy
On Efficiently and Reliably Achieving Low Defective Part Levels
Logical Modeling of Physical Failures and Their Inherent Syndrome Testability in MOS LSI/VLSI Networks
Fault simulation for analog test coverage
E-SCOUT: Efficient-Spatial Clustering-based Outlier Detection through Telemetry
Optimal manufacturing flow to determine minumum operating voltage
Correlation of Capacitive Load Delay
Exact path delay grading with fundamental BDD operations
Skewed-Load Transition Test: Part 1, Calculus
Linearity testing issues of analog to digital converters
Electronic Chip-In-Place Test
FAT: Training Neural Networks for Reliable Inference Under Hardware Faults
On the Effect of I SSQ Testing in Reducing Early Failure Rate
A Functional Test Program Generator
Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills
Challenges in Low Cost Test Approach for ARM9TM Core Based Mixed-Signal SoC DragonBallTM-MX1
A circular pipeline processing based deterministic parallel test pattern generator
A Robust, Self-Tuning CMOS Circuit for Built-in Go/No-Go Testing of Synthesizer Phase Noise
A Fast and Low Cost Embedded Test Solution for CMOS Image Sensors
Efficient simulation of parametric faults for multi-stage analog circuits
Defect Classes - An Overdue Paradigm for CMOS IC
BIST Techniques for ASIC Design
Testability Analysis of MOS VLSI Circuits
On efficient error diagnosis of digital circuits
Analysis and Characterization of Defects in FeFETs
Concurrent Fault Detection Using a Watchdog Processor and Assertions
An almost full-scan BIST solution-higher fault coverage and shorter test application time
BIST: required for embedded DRAM
Accurate and robust spectral testing with relaxed instrumentation requirements
Re-examining the Needs of the Mixed-Signal Test
Test Synthesis from a User Perspective
Fault Diagnosis in Analogue Circuits Using AI Techniques
RADPro: Automatic RF analyzer and diagnostic program generation tool
Implementing 1149.1 on CMOS Microprocessors
Detection and Diagnosis of Static Scan Cell Internal Defect
ECL Board Testing: An In-Circuit Point of View
Glamorous Analog Testability - We Already Test them and Ship Them - So What is the Problem?
A complete test set to diagnose scan chain failures
A built-in self-test scheme for 3D RAMs
Reducing high-speed/RF test cost - guaranteed by design or guaranteed to fail?
Leveraging new standards in ATE software
Methodology for early and accurate test power estimation at RTL
Quality in Test Education?
ISI Injection Filter Designs Using PIN and Varactor Diodes for SerDes Testing on ATE
A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation
Transforming Behavioral Specifications to Facilitate Synthesis of Testable Designs
Concurrent Testing of Droplet-Based Microfluidic Systems for Multiplexed Biomedical Assays
New Paradigm for Signal Paths in ATE Pin Electronics are Needed for Serialcom Device Testing
Manufacturing Productivity: Automated vs. Manual Test-Data-Management Systems
Knowledge-Based Testing
Detecting Multiple Faults in CMOS Circuits
A comparison of bridging fault simulation methods
Hybrid Multisite Testing at Manufacturing
Reliability Testing by Precise Electrical Measurement
Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques
Skewed-Load Transition Test: Part 2, Coverage
Design for test features of the ARM clock control macro
Parameterizable Testing Scheme for FIR Filters
Minimized power consumption for scan-based BIST
Real-time signal processing - a new PLL test approach
Testing 3G-controlled systems: time to rejoice or time to feel pain?
Perfect data reconstruction algorithm of time interleaved ADCs
An Overview of CMOS VLSI Failure Analysis and the Importance of Test and Diagnostics
How to Bridge the Gap Between Simulationand Test