yusuke1997/dblp-id-title huggingface dataset:
Astraea: towards QoS-aware and resource-efficient multi-stage GPU services
How low can you go?: recommendations for hardware-supported minimal TCB code execution
The Scalable Heterogeneous Computing (SHOC) benchmark suite
Unbounded page-based transactional memory
Compiling Distributed System Models with PGo
Kinetic Dependence Graphs
UniZK: Accelerating Zero-Knowledge Proof with Unified Hardware and Flexible Kernel Mapping
Analyzing Behavior Specialized Acceleration
NVWAL: Exploiting NVRAM in Write-Ahead Logging
Scaling Up Memory Disaggregated Applications with SMART
Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2008, Seattle, WA, USA, March 1-5, 2008
TensorTEE: Unifying Heterogeneous TEE Granularity for Efficient Secure Collaborative Tensor Computing
Persistent Memory Disaggregation for Cloud-Native Relational Databases
Cooperative Shared Memory: Software and Hardware Support for Scalable Multiprocesors
Enclosure: language-based restriction of untrusted libraries
Concurrency control with data coloring
Accelerating simulation of agent-based models on heterogeneous architectures
Understanding modern device drivers
MemScale: active low-power modes for main memory
What Scalable Programs Need from Transactional Memory
HSM: A Hybrid Slowdown Model for Multitasking GPUs
EVT: Accelerating Deep Learning Training with Epilogue Visitor Tree
Kimbap: A Node-Property Map System for Distributed Graph Analytics
Cool-Mem: combining statically speculative memory accessing with selective address translation for energy efficiency
Not All Qubits Are Created Equal: A Case for Variability-Aware Policies for NISQ-Era Quantum Computers
Scalable selective re-execution for EDGE architectures
CPS: A Cooperative Para-virtualized Scheduling Framework for Manycore Machines
Squeezing Operator Performance Potential for the Ascend Architecture
Integrated 3D-stacked server designs for increasing physical density of key-value stores
ZRAID: Leveraging Zone Random Write Area (ZRWA) for Alleviating Partial Parity Tax in ZNS RAID
AMNESIAC: Amnesic Automatic Computer
3DGates: An Instruction-Level Energy Analysis and Optimization of 3D Printers
CRUISE: cache replacement and utility-aware scheduling
Request behavior variations
Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers
Overlap Communication with Dependent Computation via Decomposition in Large Deep Learning Models
uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures
Societal infrastructure in the age of Artificial General Intelligence
Expanding Datacenter Capacity with DVFS Boosting: A safe and scalable deployment experience
Treelet Accelerated Ray Tracing on GPUs
Spindle: Efficient Distributed Training of Multi-Task Large Models via Wavefront Scheduling
NUBA: Non-Uniform Bandwidth GPUs
Heet: Accelerating Elastic Training in Heterogeneous Deep Learning Clusters
Proceedings of the 12th Workshop on General Purpose Processing Using GPUs, GPGPU@ASPLOS 2019, Providence, RI, USA, April 13, 2019
Limits of Instruction-Level Parallelism
The case for simple, visible cache coherency
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2017, Xi'an, China, April 8-12, 2017
LDX: Causality Inference by Lightweight Dual Execution
SmoothOperator: Reducing Power Fragmentation and Improving Power Utilization in Large-scale Datacenters
Volition: scalable and precise sequential consistency violation detection
TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs
COATCheck: Verifying Memory Ordering at the Hardware-OS Interface
Hardbound: architectural support for spatial safety of the C programming language
Software Overhead in Messaging Layers: Where Does the Time Go?
GPU-Initiated On-Demand High-Throughput Storage Access in the BaM System Architecture
Supporting nested transactional memory in logTM
ByteFS: System Support for (CXL-based) Memory-Semantic Solid-State Drives
Capuchin: Tensor-based GPU Memory Management for Deep Learning
Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation
SIMD defragmenter: efficient ILP realization on data-parallel architectures
Warp size impact in GPUs: large or small?
A Multi-Microprocessor Architecture with Hardware Support for Communication and Scheduling
Nested Kernel: An Operating System Architecture for Intra-Kernel Privilege Separation
Kendo: efficient deterministic multithreading in software
Hierarchical Prefetching: A Software-Hardware Instruction Prefetcher for Server Applications
Bottleneck identification and scheduling in multithreaded applications
Fine-Grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine
Nightcore: efficient and scalable serverless computing for latency-sensitive, interactive microservices
Bridge the Gap between Neural Networks and Neuromorphic Hardware with a Neural Network Compiler
Scalable Kernel TCP Design and Implementation for Short-Lived Connections
Application-Controlled Physical Memory using External Page-Cache Management
Sponge: portable stream programming on graphics engines
Heron: Automatically Constrained High-Performance Library Generation for Deep Learning Accelerators
Has Machine Learning for Systems Reached an Inflection Point?
ARC: Warp-level Adaptive Atomic Reduction in GPUs to Accelerate Differentiable Rendering
Safer Program Behavior Sharing Through Trace Wringing
Control Logic Synthesis: Drawing the Rest of the OWL
An Architecture Supporting Formal and Compositional Binary Analysis
Improving the performance of object-oriented languages with dynamic predication of indirect jumps
TANGRAM: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators
A Message Driven Or-Parallel Machine
Optimized Compilation of Aggregated Instructions for Realistic Quantum Computers
Better bug reporting with better privacy
Reflex: using low-power processors in smartphones without knowing them
PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor
Explainable Port Mapping Inference with Sparse Performance Counters for AMD's Zen Architectures
SysObjC: C extension for development of object-oriented operating systems
Instruction-Aware Cooperative TLB and Cache Replacement Policies
Real-Time Image Recognition Using Collaborative IoT Devices
Hermes: A Fast, Fault-Tolerant and Linearizable Replication Protocol
Adelie: continuous address space layout re-randomization for Linux drivers
ProbeGuard: Mitigating Probing Attacks Through Reactive Program Transformations
Accelerator: using data parallelism to program GPUs for general-purpose uses
FCatch: Automatically Detecting Time-of-fault Bugs in Cloud Systems
Using Analytical Performance/Power Model and Fine-Grained DVFS to Enhance AI Accelerator Energy Efficiency
Logical abstractions for noisy variational Quantum algorithm simulation
Issues in holistic system design
Low-level detection of language-level data races with LARD
TxRace: Efficient Data Race Detection Using Commodity Hardware Transactional Memory
Judging a type by its pointer: optimizing GPU virtual functions
Saving Energy with Per-Variable Bitwidth Speculation
OSEK/VDX API for Java
STABILIZER: statistically sound performance evaluation
PMEM-spec: persistent memory speculation (strict persistency can trump relaxed persistency)
Slapo: A Schedule Language for Progressive Optimization of Large Deep Learning Model Training
Virtualizing FPGAs in the Cloud
Dimensionality-Aware Redundant SIMT Instruction Elimination
Performance Prediction of On-NIC Network Functions with Multi-Resource Contention and Traffic Awareness
VertexSurge: Variable Length Graph Pattern Match on Billion-edge Graphs
Lightweight Fault Isolation: Practical, Efficient, and Secure Software Sandboxing
DiAG: a dataflow-inspired architecture for general-purpose processors
GPU-based Private Information Retrieval for On-Device Machine Learning Inference
An asymmetric distributed shared memory model for heterogeneous parallel systems
FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design
AxGames: Towards Crowdsourcing Quality Target Determination in Approximate Computing
A Framework for Memory Oversubscription Management in Graphics Processing Units
OpenPiton: An Open Source Manycore Research Framework
Investigating Optimal Local Memory Performance
AtoMig: Automatically Migrating Millions Lines of Code from TSO to WMM
NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing
Towards a Machine Learning-Assisted Kernel with LAKE
PDIP: Priority Directed Instruction Prefetching
CloudSeer: Workflow Monitoring of Cloud Infrastructures via Interleaved Logs
DOTA: detect and omit weak attentions for scalable transformer acceleration
VLSI Assist For a Multiprocessor
A compiler infrastructure for accelerator generators
Whole-Program Optimization for Time and Space Efficient Threads
Effective simulation and debugging for a high-level hardware language using software compilers
Fine-Grain Checkpointing with In-Cache-Line Logging
Applying transactional memory to concurrency bugs
Vector instruction selection for digital signal processors using program synthesis
Best-effort semantic document search on GPUs
PIM-DL: Expanding the Applicability of Commodity DRAM-PIMs for Deep Learning via Algorithm-System Co-Optimization
RainbowCake: Mitigating Cold-starts in Serverless with Layer-wise Container Caching and Sharing
Mercury and freon: temperature emulation and management for server systems
A distributed data-parallel framework for analysis and visualization algorithm development
TMO: transparent memory offloading in datacenters
The mapping collector: virtual memory support for generational, parallel, and concurrent compaction
Probabilistic job symbiosis modeling for SMT processor scheduling
Design and Operation of Shared Machine Learning Clusters on Campus
Accelerating Legacy String Kernels via Bounded Automata Learning
Providing safe, user space access to fast, solid state disks
HiWayLib: A Software Framework for Enabling High Performance Communications for Heterogeneous Pipeline Computations
High Performance Packet Processing with FlexNIC
Eliminating the Address Translation Bottleneck for Physical Address Cache
Forecasting GPU Performance for Deep Learning Training and Inference
DianNao: a small-footprint high-throughput accelerator for ubiquitous machine-learning
PipeLLM: Fast and Confidential Large Language Model Services with Speculative Pipelined Encryption
Hyperscale Hardware Optimized Neural Architecture Search
FlexTensor: An Automatic Schedule Exploration and Optimization Framework for Tensor Computation on Heterogeneous System
A Case Study of VAX-11 Instruction Set Usage for Compiler Execution
PARTIES: QoS-Aware Resource Partitioning for Multiple Interactive Services
Locality-Aware CTA Clustering for Modern GPUs
Graspan: A Single-machine Disk-based Graph System for Interprocedural Static Analyses of Large-scale Systems Code
Memory Errors in Modern Systems: The Good, The Bad, and The Ugly
Linguistic support for modern operating systems workshop on programming languages and operating systems 2006 (PLOS 2006)
Exploiting GPU Hardware Saturation for Fast Compiler Optimization
When application-specific ISA meets FPGAs: a multi-layer virtualization framework for heterogeneous cloud FPGAs
PMFuzz: test case generation for persistent memory programs
X-Containers: Breaking Down Barriers to Improve Performance and Isolation of Cloud-Native Containers
Variable Length Path Branch Prediction
Anomaly-based bug prediction, isolation, and validation: an automated approach for software debugging
PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development
Design Tradeoffs to Support the C Programming Language in the CRISP Microprocessor
RepCut: Superlinear Parallel RTL Simulation with Replication-Aided Partitioning
Register Allocation for Free: The C Machine Stack Cache
SoftSig: software-exposed hardware signatures for code analysis and optimization
Cooperative Concurrency Control for Write-Intensive Key-Value Workloads
Bootstrapping: Using SMT Hardware to Improve Single-Thread Performance
Hidet: Task-Mapping Programming Paradigm for Deep Learning Tensor Programs
Ratte: Fuzzing for Miscompilations in Multi-Level Compilers Using Composable Semantics
Accelerating LLM Serving for Multi-turn Dialogues with Efficient Resource Management
Mind mappings: enabling efficient algorithm-accelerator mapping space search
Zoomie: A Software-like Debugging Tool for FPGAs
CAFQA: A Classical Simulation Bootstrap for Variational Quantum Algorithms
Synchronization and Communication in the T3E Multiprocessor
A new idiom recognition framework for exploiting hardware-assist instructions
Automatic Hierarchical Parallelization of Linear Recurrences
A Benchmark Suite for Evaluating Caches' Vulnerability to Timing Attacks
Dependance Based Prefetching for Linked Data Structures
IncBricks: Toward In-Network Computation with an In-Network Cache
Embracing Imbalance: Dynamic Load Shifting among Microservice Containers in Shared Clusters
Designing computer systems with MEMS-based storage
Efficiently detecting concurrency bugs in persistent memory programs
Compiler optimization of scalar value communication between speculative threads
Keynote: Developing our Quantum Future
MorphQPV: Exploiting Isomorphism in Quantum Programs to Facilitate Confident Verification
Orchestration by approximation: mapping stream programs onto multicore architectures
Hardware Sentinel: Protecting Software Applications from Hardware Silent Data Corruptions
Exploring circuit timing-aware language and compilation
Controlled Preemption: Amplifying Side-Channel Attacks from Userspace
Flame: A Centralized Cache Controller for Serverless Computing
Operating System Support for Improving Data Locality on CC-NUMA Compute Servers
Nazar: Monitoring and Adapting ML Models on Mobile Devices
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling
Dynamic knobs for responsive power-aware computing
The ZS-1 Central Processor
Achieving Sub-second Pairwise Query over Evolving Graphs
Real-time rendering and dynamic updating of 3-d volumetric data
WiSync: An Architecture for Fast Synchronization through On-Chip Wireless Communication
Temporally Bounding TSO for Fence-Free Asymmetric Synchronization
A Study of FPGA Virtualization and Accelerator Scheduling
Programming language optimizations for modular router configurations
High-Bandwidth Data Memory Systems for Superscalar Processors
Direct Mind-Machine Teaming (Keynote)
AStitch: enabling a new multi-dimensional optimization space for memory-intensive ML training and inference on modern SIMT architectures
An Energy-interference-free Hardware-Software Debugger for Intermittent Energy-harvesting Systems
FLAT: a GPU programming framework to provide embedded MPI
Veil: A Protected Services Framework for Confidential Virtual Machines
Tarazu: optimizing MapReduce on heterogeneous clusters
Archipelago: trading address space for reliability and security
High-performance sparse matrix-vector multiplication on GPUs for structured grid computations
A Quantitative Analysis of Loop Nest Locality
A case for neuromorphic ISAs
Detailed Characterization of Deep Neural Networks on GPUs and FPGAs
GIANTSAN: Efficient Memory Sanitization with Segment Folding
DySel: Lightweight Dynamic Selection for Kernel-based Data-parallel Programming Model
Power Modeling for Heterogeneous Processors
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2015, Istanbul, Turkey, March 14-18, 2015
HuffDuff: Stealing Pruned DNNs from Sparse Accelerators
TCCL: Discovering Better Communication Paths for PCIe GPU Clusters
HOIST: a system for automatically deriving static analyzers for embedded systems
A Generic Service to Provide In-Network Aggregation for Key-Value Streams
A randomized scheduler with probabilistic guarantees of finding bugs
Kaleidoscope: Precise Invariant-Guided Pointer Analysis
Streamline: a fast, flushless cache covert-channel attack by enabling asynchronous collusion
Occamy: Elastically Sharing a SIMD Co-processor across Multiple CPU Cores
DEUCE: Write-Efficient Encryption for Non-Volatile Memories
DCG: An Efficient, Retargetable Dynamic Code Generation System
Hoard: A Scalable Memory Allocator for Multithreaded Applications
AsyncClock: Scalable Inference of Asynchronous Event Causality
Hunting Trojan Horses
Hardware-Software Trade-Offs in a Direct Rambus Implementation of the RAMpage Memory Hierarchy
Looking back on the language and hardware revolutions: measured power, performance, and scaling
RASSM: Residue-based Acceleration of Single Sparse Matrix Computation via Adaptive Tiling
Space-Efficient TREC for Enabling Deep Learning on Microcontrollers
NVAlloc: rethinking heap metadata management in persistent memory allocators
Shoestring: probabilistic soft error reliability on the cheap
NV-Heaps: making persistent objects fast and safe with next-generation, non-volatile memories
Predicting Conditional Branch Directions From Previous Runs of a Program
Efficient and Flexible Value Sampling
Marple: Scalable Spike Sorting for Untethered Brain-Machine Interfacing
Iago attacks: why the system call API is a bad untrusted RPC interface
Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators
Thesaurus: Efficient Cache Compression via Dynamic Clustering
Direct Memory Translation for Virtualized Clouds
GMT: GPU Orchestrated Memory Tiering for the Big Data Era
Parallelizing data race detection
Greybox Fuzzing for Concurrency Testing
1st International Workshop on Computing in Heterogeneous, Autonomous 'N' Goal-Oriented Environments, CHANGE 2011, Newport Beach, CA, USA, March 6, 2011
Fast Instruction Selection for Fast Digital Signal Processing
CSR: Core Surprise Removal in Commodity Operating Systems
Training Job Placement in Clusters with Statistical In-Network Aggregation
COGENT: Adaptable Compiler Toolchain for Tagging RISC-V Binaries
Early Termination for Hyperdimensional Computing Using Inferential Statistics
A comparative study of arbitration algorithms for the Alpha 21364 pipelined router
Debugging in the brave new world of reconfigurable hardware
In-Memory Data Parallel Processor
Slim NoC: A Low-Diameter On-Chip Network Topology for High Energy Efficiency and Scalability
Locality-Aware Request Distribution in Cluster-based Network Servers
Memory-harvesting VMs in cloud platforms
CoGENT: Verifying High-Assurance File System Implementations
PhasePrint: Exposing Cloud FPGA Fingerprints by Inducing Timing Faults at Runtime
Rethinking software runtimes for disaggregated memory
SherLog: error diagnosis by connecting clues from run-time logs
Register packing for cyclic reduction: a case study
Efficient Implementation of High Level Parallel Programs
WASP: Workload-Aware Self-Replicating Page-Tables for NUMA Servers
ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface Combinators
Data races vs. data race bugs: telling the difference with portend
MaxEmbed: Maximizing SSD bandwidth utilization for huge embedding models serving
Watching for Software Inefficiencies with Witch
Black-box Concurrent Data Structures for NUMA Architectures
A Tightly-Coupled Processor-Network Interface
Architectural Support for Software-Defined Metadata Processing
Serverless computing on heterogeneous computers
IWannaBit!
DPACS: Hardware Accelerated Dynamic Neural Network Pruning through Algorithm-Architecture Co-design
Sleuth: A Trace-Based Root Cause Analysis System for Large-Scale Microservices with Graph Neural Networks
Direct Execution of Lisp on a List-Directed Architecture
BaCO: A Fast and Portable Bayesian Compiler Optimization Framework
SaberLDA: Sparsity-Aware Learning of Topic Models on GPUs
Qraft: reverse your Quantum circuit and know the correct program output
COMET: Towards Practical W4A4KV4 LLMs Serving
PAPI: Exploiting Dynamic Parallelism in Large Language Model Decoding with a Processing-In-Memory-Enabled Computing System
Lynx: A SmartNIC-driven Accelerator-centric Architecture for Network Servers
Reducing divergence in GPGPU programs with loop merging
CINM (Cinnamon): A Compilation Infrastructure for Heterogeneous Compute In-Memory and Compute Near-Memory Paradigms
Data-parallel finite-state machines
Challenging Sequential Bitstream Processing via Principled Bitwise Speculation
AP1000+: Architectural Support of PUT/GET Interface for Parallelizing Compiler
Where is Time Spent in Message-Passing and Shared-Memory Programs?
Big Data of the Past, from Venice to Europe
Proactive Control of Approximate Programs
Watson and the Era of Cognitive Computing
MemorIES: A Programmable, Real-Time Hardware Emulation Tool for Multiprocessor Server Design
Hacky Racers: Exploiting Instruction-Level Parallelism to Generate Stealthy Fine-Grained Timers
Frequent Value Locality and Value-Centric Data Cache Design
λFS: A Scalable and Elastic Distributed File System Metadata Service using Serverless Functions
AvA: Accelerated Virtualization of Accelerators
λ-trim: Optimizing Function Initialization in Serverless Applications With Cost-driven Debloating
More is Less, Less is More: Molecular-Scale Photonic NoC Power Topologies
Determining Application-specific Peak Power and Energy Requirements for Ultra-low Power Processors
GMLake: Efficient and Transparent GPU Memory Defragmentation for Large-scale DNN Training with Virtual Memory Stitching
Paravirtual Remote I/O
GRIFFIN: Guarding Control Flows Using Intel Processor Trace
Wave: Offloading Resource Management to SmartNIC Cores
DIABLO: A Warehouse-Scale Computer Network Simulator using FPGAs
Inter-core cooperative TLB for chip multiprocessors
TiLT: A Time-Centric Approach for Stream Query Optimization and Parallelization
Hailstorm: Disaggregated Compute and Storage for Distributed LSM-based Databases
DejaVuzz: Disclosing Transient Execution Bugs with Dynamic Swappable Memory and Differential Information Flow Tracking Assisted Processor Fuzzing
BVAP: Energy and Memory Efficient Automata Processing for Regular Expressions with Bounded Repetitions
Litmus: Fair Pricing for Serverless Computing
Performance Consequences of Parity Placement in Disk Arrays
Enforcing C/C++ Type and Scope at Runtime for Control-Flow and Data-Flow Integrity
Unconventional Parallelization of Nondeterministic Applications
ValueExpert: exploring value patterns in GPU-accelerated applications
AnyKey: A Key-Value SSD for All Workload Types
Cooperative empirical failure avoidance for multithreaded programs
Introspective 3D chips
Finding trojan message vulnerabilities in distributed systems
Efficient virtualization on embedded power architecture® platforms
Self-aware adaptation via implementation hot-swap for heterogeneous computing
CTrigger: exposing atomicity violation bugs from their hiding places
Defensive approximation: securing CNNs using approximate computing
Improving the Accuracy of Static Branch Prediction Using Branch Correlation
SpecPIM: Accelerating Speculative Inference on PIM-Enabled System via Architecture-Dataflow Co-Exploration
Klotski: Efficient Mixture-of-Expert Inference via Expert-Aware Multi-Batch Pipeline
Production-run software failure diagnosis via hardware performance counters
Translation-Triggered Prefetching
Accelerating two-dimensional page walks for virtualized systems
Cosmic rays don't strike twice: understanding the nature of DRAM errors and the implications for system design
Towards Practical Default-On Multi-Core Record/Replay
Using Meta-level Compilation to Check FLASH Protocol Code
Communication Scheduling
Conservation cores: reducing the energy of mature computations
High-performance fractal coherence
Mondrian memory protection
Accurate Disassembly of Complex Binaries Without Use of Compiler Metadata
KickStarter: Fast and Accurate Computations on Streaming Graphs via Trimmed Approximations
ApproxHadoop: Bringing Approximations to MapReduce Frameworks
Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism
Flexible Non-intrusive Dynamic Instrumentation for WebAssembly