yusuke1997/dblp-id-title huggingface dataset:
Intuitive Representations for Temporal Logic Formulas
Identifying bottlenecks in manufacturing systems using stochastic criticality analysis
An automatic communication synthesis for high level SOC desing using transaction level modelling (poster)
Proceedings of the 2010 Forum on specification & Design Languages, FDL 2010, September 14-16, 2010, Southampton, UK
A novel modeling framework for time-triggered safety-critical embedded systems
Digital Twin and Digital Thread for System Security and Performance applied to an Electrical Vehicle Charging Use Case
VIR2EM: VIrtualization and Remotization for Resilient and Efficient Manufacturing: Project-Dissemination Paper
Formal Verification of SUBLEQ Microcode implementing the RV32I ISA
Fault Analysis in Analog Circuits Through Language Manipulation and Abstraction
SystemC-AMS Extension Library for Modeling Conservative Nonlinear Dynamic Systems
A multi-view and programming language agnostic framework for model-driven engineering
Autometic Generation of SystemC Transactors from AsmL Specification
VHDL-AMS Implementation of a Numerical Ballistic CNT Model
A SystemC-based Framework of Communication Architecture
Granularity Issues in Transaction Level Modelling Digital Signal Processing Applications
Forum on specification and Design Languages, FDL 2004, September 14-17, 2004, Lille, France, Proceedings
Interface-Centric Abstraction Level for Rapid HW/SW Integration
System model of an inertial navigation system using SystemC-AMS
C-model integration and software development using system-level simulation at TLM in a SystemC-based desing flow
Automating the translation of assertions using natural language processing techniques
Modelling Alternatives for Cycle Approximate Bus TLMs
The Performance of Combining Multiway Decision Graphs and HOL Theorem Prover
Analog assertion-based verification on partial state space representations using ASL
sciPROVE: C++ Based Verification Environment for IP and SoC Design1
Assertion support in high-level synthesis design flow
Enabling Automated Code Transformation and Variable Tracing
Improving IP core reuse through the application of the meta-language xHDL
Exploiting Dataflow Models for Parallel Simulation of Discrete Timed Systems
Proposal to extend frequency domain analysis in VHDL-AMS
VHDL-AMS virtual prototyping in power electronics
Logical Time at Work: Capturing Data Dependencies and Platform Constraints
Compositional timing-aware semantics for synchronous programming
VHDL-AMS Model of Ferroelectric Liquid Crystals
A Formal Verification Approach for IP-based Designs
Automatic integration of SystemC in the FMI standard for Software-defined Vehicle design
Efficient Monte Carlo Simulation Using SystemC
A hardware/software codesign framework for developing complex embedded systems using formal model refinement
Automating Transformation Strategy via Attributed Graphs for Process Network Parallelization
Proposal for a Bond Graph Based Model of Computation in SystemC-AMS
Application of formal methods for design space exploration and refinement
SystemC Modeling and Validation of A RISC Processor System
Integrating Model-Checking with UML-based SoC Development
Designing NOCs with a parallel extension of c
Comprehensive non-functional analysis of combinational circuits vulnerability to single event transients
Synchronised Shared Memory and Model Checking: A Proof of Concept
Design Structure Analysis and Transaction Recording in SystemC
Design Structure Analysis and Transaction-based Co-Verification
An Advanced Simulink Verification Flow Using SystemC
Towards Assertion Based Verification of Analog and Mixed Signal Designs Using PSL
Automatic High Level Assertion Generation and Synthesis for Embedded System Design
Improving PSS Test Generation Using Model Checking and Conformance Testing
Power and Energy Estimations in Model-Based Design
Localizing features of ESL models for design understanding
A Method for Terminal Platform Architecture Development
Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2017 [Verona, Italy, September 18-20, 2017]
OSSS-Channels: Modelling and Synthesis of Communication
Virtual Prototyping of Open Source Heterogeneous Systems with an Open Source Framework Featuring SystemC MDVP Extensions
Formal Methods-Based Optimization of Dataflow Models with Translation to Synchronous Models
Overcoming issues to reach full adoption and benefit of C/C++based system design methodologies in real System-on-Chip projects
A New Ageing-Aware Approach Via Path Isolation
Towards a UML Profile for Real-Time Modelling
Enhancing Split Computing and Early Exit Applications through Predefined Sparsity
Enhancing Compiler-Driven HDL Design with Automatic Waveform Analysis
Symbolic Scheduling of SystemC Dataflow Designs
Formal Specification Level: Towards verification-driven design based on natural language processing
Integrated Requirement Evaluation of Non-Functional System-on-Chip Properties
Efficient Representation and Simulation of Model-Based Designs
RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow
SDL and Timed Petri Nets versus UPPAAL for the validation of embedded architecture in automotive
Transactor-based Formal Verification of Real-time Embedded Systems
Interoperability between Design and Simulation Tools using Model Transformation Techniques
Extending the RASSP model for Verification
Language and hardware acceleration backend for graph processing
Security Driven Design Space Exploration for Embedded Systems
Case Study on Transaction Level Modeling
Forum on Specification & Design Languages, FDL 2024, Stockholm, Sweden, September 4-6, 2024
Multi-paradigm semantics for simulating SysML models using SystemC-AMS
MODEST - A unified language for quantitative models
SystemC-WMS modeling of control techniques for switching amplifiers targeting polar RF transmitters
Towards High-Level Executable Specifications of Heterogeneous Systems with SystemC-AMS: Application to a Manycore PCR-CE Lab on Chip for DNA Sequencing
Graph-based approach for software allocation in automotive networked embedded systems: A partition-and-map algorithm
Mapping of Concurrent Object-Oriented Models to Extended Real-Time Task Networks
Open-Source Timing-Monitor Co-Processor in RISC-V Safety Infrastructure
Simulation analysis and validation
Architecture description in related standards
SystemC AMS power electronic modeling with ideal instantaneous switches
A SystemC Language Extension for High-Level Reconfiguration Modelling
Forum on Specification & Design Languages, FDL 2022, Linz, Austria, September 14-16, 2022
Model Transformations from a Data Parallel Formalism towards Synchronous Languages
24th Forum on specification & Design Languages, FDL 2021, Antibes, France, September 8-10, 2021
Early Prediction of Conducted-Mode Emission of complex IC's
Heterogeneous System-Level Specification in SystemC
Modelling Environment for Heterogeneous Systems based on MoCs
Maintenance of specification models in industry using Edapt
The Sparse Synchronous Model
Secure Programming Platform for Edge-Based IoT: Wild-and-Crazy-Idea Paper
Debugging Contradictory Constraints in Constraint-Based Random Simulation
Standard compliant co-simulation models for verification of automotive embedded systems
VerilogAMS language used in the Top-Down Methodology for wireless integrated circuit designs
Requirements and Verifications through an extension of VHDL-AMS
Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification
An efficient refinement strategy exploiting component properties in a cegar process
Meta Modelling of Embedded Systems using Active Databases
Syntax-Guided Enumeration of Temporal Properties
Architectural system modeling for correct-by-construction RTL design
Traceability and Interoperability in Models Transformations
Mixed-Level Simulation of Wireless Sensor Networks
Change impact analysis for hardware designs from natural language to system level
From IEC 61131-3 Function Block Diagrams to Sequentially Constructive Statecharts
Scenario-based Validation of Embedded Systems
A new assertion property language for analog/mixed-signal circuits
Applying Communication Patterns to Actor-Oriented Models
A generic hardware / software communication middleware for streaming applications on shared memory multi processor systems-on-chip
UML/XML based approach to hierarchical AMS Synthesis
Metamodel-based Methodology for Real-Time Embedded Design
An Algebra of Deterministic Propositional Acceptance Automata (DPAA)
An Architecture for Deploying Model Based Testing in Embedded Systems
Functional Verification Environment for Object-oriented Hardware Designs
Leveraging the efficiency of C-Based Design with Catapult-C
Formal Design, Co-Simulation and Validation of a Radar Signal Processing System
A Heterogeneous Co-simulation Environment for Complex Embedded Telecommunication Systems
Modeling of signal integrity in bus communications with timed data flow SystemC-AMS
Formal Verification of Timed VHDL Programs
Hardware Definition Based on Standard C-language Source Code
A VHDL-AMS modeling methodology for top-down/bottom-up design of RF systems
Semi-formal refinement of heterogeneous embedded systems by foreign model integration
Extending SystemC Clocks to Model SoC
SystemC TLM Transaction Modelling and Dispatch for Active Object
Transaction Level Modelling: A reflection on what TLM is and how TLMs may be classified
VHDL-AMS model of RF-Interconnect System for Global On-Chip Communication
SCandal: SystemC Analysis for Nondeterminism Anomalies
RTL Assertion Mining with Automated RTL-to-TLM Abstraction
A Methodology for Embedded System Design supporting Layered Platforms
Model generation for embedded analog/mixed-signal systems
A Solution to the Lack of Multiple Inheritance in SystemVerilog
A language to desing generators of analog functions (poster)
Systemc refinement of abstract adaptive processes for implementation into Dynamically Reconfigurable Hardware
Systemc infrastructure and extensions
UML User Interface to a Proof-based Hardware Design Flow
A general approach to the interoperability of HetSC and SystemC-AMS
Scade 6: From a Kahn Semantics to a Kahn Implementation for Multicore
Contradiction Analysis for Constraint-based Random Simulation
Refinement of Perfectly Synchronous Communication Model
Formal Foundations for MARTE-SystemC Interoperability
A Case Study on Automated Generation of Integration Tests
Formal Transformation of a KPN Specification to a GALS Implementation
A methodology to compute long-term fault resilience of NoCs under fault-tolerant routing algorithms
Exploring Multidomain Faults in Digital Twin: A Gaming Engine Perspective : Wild-and-Crazy-Idea Paper
Toward seamless top-down of A/MS systems
From Low-Power to No-Power: Adaptive Clocking for Event-Driven Systems
Methodologies for High-Level Modelling and Evaluation in the Automotive Domain (invited)
LAERTE++: an Object Oriented High-level TPG for SystemC Designs
Functional Coverage-Driven Characterization of RF Amplifiers
VHDL-AMS Implementation of a Numerical Ballistic CNT Model for Logic Circuit Simulation
Statistical Modeling with SystemC-AMS for Automotive Systems
Fine grained adaptive simulation with application to NoCs
Leveraging Piecewise Composition to Infer Environment Constraints for Hardware Designs
Combinatorial Dependencies in Transaction Level Models
SystemCmantic: A high level Modelling and Co-Design Framework
Reconstructing Line References from Optimized Binary Code for Source-Level Annotation
Formal Specification Level
A re-use methodology for formal SoC protocol compliance verification
Optical Network On-chip Multi-Domain modeling using SystemC
Genetic-Based High-Level Synthesis of Sigma-Delta Modulator in SystemC-A
IP-XACT and marte based approach for partially reconfigurable systems-on-chip
An Accelerated Mixed-Signal Simulation Kernel for SystemC
Mixing Synchronous Reactive and Untimed Models of Computation
Adaptive Metrics for System-Level Functional Partitioning
FAst optimization of analog amplifier architecture using simulated annealing
IpPROCESS: a Development Process for Soft IP-Cord
A SystemC AMS extension for controlled modules and dynamic step sizes
A Model-driven Co-design Flow for Embedded Systems
A behavioural description with VHDL-AMS of a piezo-ceramic ultrasound transducer based on the Redwood's model
Generating MARTE Allocation Models from Activity Threads
Range Arithmetics to Speed up Reachability Analysis of Analog Systems
Simulation-based Holistic Functional Safety Assessment for Networked Cyber-Physical Systems
Compact Modeling of Emerging Technologies with VHDL-AMS
A comparison of parallel systemc simulation approaches at RTL
Runtime task mapping for lifetime budgeting in many-core systems
MDA Based, SystemC Code Generation, Applied to Intensive Signal Processing Applications
The Unified Models Methodology: Applications to Inkjet Printing
MARTE vs. AADL for Discrete-Event and Discrete-Time Domains
Semi-automated Hw/Sw Co-design for embedded systems: from MARTE models to SystemC simulators
Model-based Design Space Exploration for RTES with SysML and MARTE
Design and implementation of a safety-critical domain specific language for on-board train control
Automated Suggestions Framework for Processing Hardware Specifications Written in English
Code generation alternatives to reduce heterogeneous embedded systems to homogeneity
VHDL-AMS Modelling and System Verification Flow
Predictability in Real-time System Development (2) A Case Study
Dynamic Inside-Out Verification Using Inverse Transactions in TLM
Enabling SystemC Verification using Abstract State Machines
Toolchain integration of runtime variability and aging awareness in multicore platforms
Unified and comprehensive electronic system level, network and physics simulation for wirelessly networked cyber physical systems
Understanding physical models in VHDL-AMS
Modeling languages extensions and best practices
A framework for the generation from UML/MARTE models of IPXACT HW platform descriptions for multi-level performance estimation
Temporal Property-Based Testing of a Timed C Compiler using Time-Flow Graph Semantics
In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes
UML-based Specifications of an Embedded System oriented to HW/SW partitioning: a case study
Reachability Analysis of Deep Neural Networks Using Affine Arithmetic Decision Diagrams
Hybrid PTX Analysis for GPU accelerated CNN inferencing aiding Computer Architecture Design
The Formal Simulation Semantics of SystemVerilog
Tool Support for Precise Assessment of Software Security/Performance Tradeoffs
Wide-Band Sigma-Delta ADC Design in Superconducting Technology
Performance Analysis and Automated C++ Modularization Using Module-Adapters for SystemC
WiSeBat: accurate energy benchmarking of wireless sensor networks
A special-purpose language for implementing pipelined FPGA-based accelerators
Proceedings of the 2013 Forum on specification and Design Languages, FDL 2013, Paris, France, September 24-26, 2013
How to survive the verification of the latest generation of automotive system on chip
A Tool-Set for Table Based Direct Behavioral Configuration of C++ Models
A Language for Deterministic Coordination Across Multiple Timelines
A Bitwidth-aware HDL Extension
Token-based OSCI SystemC Simulator for Architecture Dimensioning
A Model Driven Development Approach for Implementing Reactive Systems in Hardware
ComPy-Learn: A toolbox for exploring machine learning representations for compilers
Formal Evaluation of Quality of Service for Data Acquisition
Comparison of ASCET and UML - Preparations for an Abstract Software Architecture
Dependable task and communication migration in tiled manycore system-on-chip
SystemC-A Modeling of an Automotive Seating Vibration Isolation System
Design of Experiments for Reliable Operation of Electronics in Automotive Applications
Automatic generation of cycle-accurate Simulink blocks from hdl ips
Traversing the Fundamental System-Level Design Gap Using Modeling Patterns
VHDL-AMS Behavioural Modelling of a Switched Current Sigma-Delta Modulator
Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures
UML-Based Co-Design for Run-Time Reconfigurable Architectures
High Level System desing using HiLes Designer
Towards High-Level Synthesis of Analog and Mixed-Signal Systems from VHDL-AMS Specifications
A complete SystemC UML profile with dynamic features for behavioral descriptions
Automated Redirection of Hardware Accesses for Host-Compiled Software Simulation
Fault-effect analysis on system-level hardware modeling using virtual prototypes
SystemC-AMS Steps towards an Implementation
Early Robustness Evaluation of Digital Integrated Systems
Development of VHDL-AMS Libraries for Automative Applications
DOHMO: Embedded Computer Vision in Co-Housing Scenarios
Adaptive Interconnect Models for Transaction-Level Simulation
FIST - a VHDL-AMS based architectural synthesis strategy for integrated high-frequency analogue filters
Virtual Prototype Driven Application Specific Hardware Optimization
Asynchronous online-monitoring of logical and temporal assertions
Robustness with Respect to Error Specifications
ENIAC & ARTEMIS Technology Platforms
CSP with Synthesisable SystemC(tm) and OSSS
Derivation of SystemC code from abstract system models
Transaction Level Modeling in Java
Synthesizing Software Defined Radio Components from Rosetta (invited)
Automatic synthesis of the Hardware/Software Interface
Forum on Specification & Design Languages, FDL 2025, St. Goar, Germany, September 10-12, 2025
Analyzing dependability measures at the Electronic System Level
CorePerfDSL: A Flexible Processor Description Language for Software Performance Simulation
SPACE: A Hardware/Software SystemC Modeling Platform Including an RTOS
A UML based framework for efficient validation of TLM 2 models
Automatic generation of self-adaptive transactors from PSL assertions
MARTE: UML-based Hardware Design from Modelling to Simulation
Synthesis for Unified Control- and Data-Oriented Models
Complete Verification of Weakly Programmable IPs against Their Operational ISA Model
An Intermediate Level HDL for System Level Design
A Quantitative Type Approach to Formal Component-Based System Design
ModelLib: A Web-Based Platform for Collecting Behavioural Models
VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes
Linearly graded behavioural analogue performance models
HSPICE implementation of a numerically efficient model of CNT transistor
Baseband Modeling Using Multidimensional Networks in VHDL-AMS
Synthesizing code for GPGPUs from abstract formal models
Compiling UML State Diagrams into VHDL: An Experiment in Using Model Driven Development
Case Study: SystemC-Based Design of an Industrial Exposure Control Unit1
SystemC Modeling of a Dynamic Power Management Architecture
A Domain Specific Language for Cryptography
SystemC and OCAPI-xl Based System-Level Design for Reconfigurable Systems-on-Chip
HetMoC: Heterogeneous Modelling in SystemC
Execution of heterogeneous models for thermal analysis with a multi-view approach
Comprehensive Platform and Component Modeling of Heterogeneous Interconnected Systems (invited)
Hardware performance estimation by dynamic scheduling
Forum on Specification & Design Languages, FDL 2023, Turin, Italy, September 13-15, 2023
VHDL-AMS Modeling and Simulation
Real-Time Operating System Services for Realistic SystemC Simulation Models of Embedded Systems
SpecScribe Analog - A Specification Tool Extension for Heterogeneous Systems
SystemC-WMS: A Wave Mixed Signal Simulator
An Application of Generalized Supervisor Synthesis to the Control of a Call Center
From Lustre to Graphical Models and SCCharts
A SystemC superset for high-level synthesis
Towards satisfaction checking of power contracts in Uppaal
Modeling and Performance Estimation of Robotic Systems using ROS: Application to drone-based Services
Feature-Oriented Refactoring Proposal for Transaction Level Models in SoCLib
Process Algebraic Specification, Refinement, and Verification of Embedded Systems
An HW/SW Co-design Environment based on UML and SystemC
Timing Performances of Automatically Generated Code Using MDA Approaches
Temporal validation of Real Time multitasking applications based on communicating timed automata
Systemc transaction level modeling with transaction events
Hardware Synthesis of Parallel Machines from SystemC
Tolerance Models in Hardware Description Languages
A VHDL-AMS Configuration for Active Pixel Sensors
Equivalence checking on ESL utilizing a priori knowledge
Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checking
SMT-based stimuli generation in the SystemC Verification library
Simple Models for Complex Systems : A-FSM Template
Model-Driven System Validation by Scenarios
Error-free near-threshold adiabatic CMOS logic in presence of process variation
UML and SystemC - Comparison and Mapping Rules for Automatic Code Generation
Semi-Symbolic Modeling and Analysis of Noise in Heterogeneous Systems
Verification-Oriented Behavioral Modeling of Non-Linear Analog
Mixed-Level Modeling Using Configurable MOS Transistor Models
Platform-independent Design for Embedded Real-time Systems
Real-time ticks for synchronous programming
Reuse of SML module system for the B language
Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device
An Integrated SystemC Debugging Environment
Overview of the ICODES Project
SystemC workload model generation from UML for performance simulation
Transaction Level Modeling in Communication Engine Design
Semi-Symbolic Analysis of Accuracy at System Level
Synchronization of analogue and digital solvers in mixed-signal simulation on a SystemC platform
Improvement of Assertion-Based Verification through the generation of proper test sequences
Compiled and Synthesized UML, a practical Approach for Codesign
Modelling Technologies for Disruptive Communication System Design
RAT-based formal verification of QDI asynchronous controllers
A modular design space exploration framework for multiprocessor real-time systems
Mixed Nets, Conversion Models, and VHDL-AMS
Modelling and Simulation of an I2C Bus Controller in SystemC-AMS
Efficient and Customizable Integration of Temporal Properties
SystemC Simulation of Continuous-Time $Sigma-Delta$ Analog-Digital Converters in the Presence of Non-linearities
SystemC - a powerful system-level modelling platform for digital and mixed-signal hardware/software co-design
TCTL-Based Verification of Industrial Processes
Error Estimation in Model-Driven Development for Real-Time Software
Modeling of immediate vs. delayed data communications: from AADL to UML Marte
Towards a Common HW/SW Interface-Centric and Component-Oriented Specification and Design Methodology
Beyond real number modeling: Comparison of analog modeling approaches
Modeling legacy code with BIP: how to reduce the gap between formal description and real-time implementation
Debugging and Verification Tools for Lingua Franca in Gemoc Studio
Generating JML Specifications from UML State Diagrams
Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interface
Reliability annotations to formal specifications of context-sensitive safety properties in embedded systems
Efficient Modelling and Simulation of Embedded Software Multi-Tasking using SystemC and OSSS
On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study
GREEN HOME: The Concept and Study of Grid Responsiveness
IP-XACT components with abstract time characterization
PLiNIO: A User-Friendly Library of Gradient-Based Methods for Complexity-Aware DNN Optimization
Chatbot-based assertion generation from natural language specifications
A Functional Programming Framework of Heterogeneous Model of Computation for System Design
Powermonitor: a versatile API for automated power-aware ESL design
Towards Behavioural Hierarchy Extensions for SystemC