yusuke1997/dblp-id-title huggingface dataset:
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering
Debug Support for Scalable System-on-Chip
14th International Workshop on Microprocessor Test and Verification, MTV 2013, Austin, TX, USA, December 11-13, 2013
Definition of a systematic method for the generation of software test programs allowing the functional verification of System On Chip (SoC)
Application of Lifting in Partial Design Analysis
An Introduction to the Plasma Language
A Case Study: Pre-Silicon SoC RAS Validation for NoC Server Processor
TiGeR, the Transmeta Instruction GEneratoR: A Production Based, Pseudo Random Instruction x86 Test Generator
A Case Study of Multiprocessor Bugs Found Using RIS Generators and Memory Usage Techniques
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking
2018 FPGA Functional Verification Trends
An Investigation of Excitation Balance and Additional Mandatory Conditions for the Diagnosis of Fortuitously Detected Defects
A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores
Fast Cycle-Accurate Interpreted Simulation
Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets
Identification of Gates for Covering all Critical Paths
Automatic Formal Correspondence Checking of ISA and RTL Microprocessor Description
A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits
Challenges in System on Chip Verification
SequenceLanguage: A Constraint Random MP-RIS Generation Framework
A Topological Approach to Hardware Bug Triage
Localization of Bugs in Processor Designs Using zamiaCAD Framework
Hardware and Software Co-Verification from Security Perspective
Automatic RTL-to-Formal Code Converter for IP Security Formal Verification
Overview on ATE Test and Debugging Methods for Asynchronous Circuits
Directed Test Case Generation for x86 Instruction Decoding
Multilayer Camouflaged Secure Boot for SoCs
Post-Verification Debugging of Hierarchical Designs
Abstraction and Refinement Techniques in Automated Design Debugging
iPUF: Interconnect PUF with Self-Masking Circuit for Performance Enhancement
Applying Verification Collaterals for Accurate Power Estimation
Ultra-Fast DMAC TLM Model for High Speed Virtual Platform Simulation
Testing Memory Models
Automatic Generation of On-Line Test Programs through a Cooperation Scheme
Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs
Continuous Linting with Automatic Debug
Energy Awareness through Software Optimisation as a Performance Estimate Case Study of the MC68HC908GP32 Microcontroller
On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design
Mixing Simulated and Actual Hardware Devices to Validate Device Drivers in a Complex Embedded Platform
Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments
Runtime Verification of k-Mutual Exclusion for SoCs
Switch-Level Test Calculation for CMOS Circuits
Abstraction as a Practical Debugging Tool
Schedulability Analysis for MultiCore Global Scheduling with Model Checking
High Coverage Power Integrity Verification in PSO Domains Employing Distributed PSO Switches
Optimized Simulation Acceleration with Partial Testbench Evaluation
Search-Space Optimizations for High-Level ATPG
DeepTrans - A Model-based Approach to Functional Verification of Address Translation Mechanisms
Verification Methodology of Heterogeneous DSP+ARM Multicore Processors for Multi-core System on Chip
Automatic UVM Environment Generation for Assertion-Based and Functional Verification of SystemC Designs
Reusing of Properties after Discretization of Hybrid Automata
A Methodology for Power-aware Pipelining via High-Level Performance Model Evaluations
Automatic Generation of Software-based Functional Failing Test for Speed Debug and On-silicon Timing Verification
Fake CPU: A Flexible and Simulation Cost-Effective UVC for Testing Shared Caches
Performance of a SystemVerilog Sudoku Solver with VCS
Proving QBF-hardness in Bounded Model Checking for Incomplete Designs
Chico: An On-chip Hardware Checker for Pipeline Control Logic
Communication Alternatives Exploration in Model-Driven Design of Networked Embedded Systems
Micro-Architecture Verification for Microprocessors
Automatic Network Protocol Synthesis from UML Sequence Diagrams
Fast Reliable Verification Methodology for RISC-V Without a Reference Model
Test Calculation for Logic and Delay Faults in Digital Circuits
Test Program Generator MicroTESK for RISC-V
Automatic Testbench Generation for Rearchitected Designs
Techniques for Debug of Low Power SoCs
A Robust and Scalable Technique for the Constraints Solving Problem in High-Level Verification
Test Generation for Precise Interrupts on Out-of-Order Microprocessors
Maintaining ISA Specifications in MicroTESK Test Program Generator
On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction
Early Models for System-Level Power Estimation
Towards Unifying Localization and Explanation for Automated Debugging
Application of Combinatorial Test (CT) Algorithm for Protocol and Hardware Feature Validation
On SAT-based Bounded Invariant Checking of Blackbox Designs
Fast Simulation of Pipeline in ASIP Simulators
Functional Verification of Pipelined Processors: A Case Study
Model Checking Bluespec Specified Hardware Designs
Deep vs. Shallow, Kernel vs. Language--What is Better for Heterogeneous Modeling in {SystemC}?
Formal Specification of an Asynchronous Processor via Action Refinement
A Methodology for Validation of Microprocessors using Equivalence Checking
IP Testing for Heterogeneous SOCs
17th International Workshop on Microprocessor and SOC Test and Verification, MTV 2016, Austin, TX, USA, December 12-13, 2016
Functional Validation of a New Network Switch Architecture Using Rapid Prototyping Techniques
Case Study: SoC Performance Verification and Static Verification of RTL Parameters
Improve the Verification Productivity: Some Best Practices from SoC and Processor Projects
An ADL for Functional Specification of IA32
A SystemC-based Framework for Properties Incompleteness Evaluation
On the Mutation Analysis of SystemC TLM-2.0 Standard
19th International Workshop on Microprocessor and SOC Test and Verification, MTV 2018, Austin, TX, USA, December 9-10, 2018
Modeling IP Responses in Testcase Generation for Systems-on-Chip Verification
Scalable, Constrained Random Software Driven Verification
How to Close Coverage 10x Faster using Portable Stimulus Standard - A Case Study
Advanced Regression Management for Post-Silicon Validation of Automotive SOCs
A Perceptron-Inspired Technique for Hardware Obfuscation
The importance of full target environment simulation tests for architecture validation
Design Space Exploration for Hotspot Detection
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study
12th International Workshop on Microprocessor Test and Verification, MTV 2011, Austin, TX, USA, December 5-7, 2011
Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA
Overview of Applying Reachability Analysis to Verifying a Physical Microprocessor
Simulation Data Mining for Functional Test Pattern Justification
Dynamic Exerciser Template Weighting in x86 Processor Verification
Hardware-Assisted Cybersecurity for IoT Devices
Tough Bugs vs. Smart Tools - L2/L3 Cache Verification Using System Verilog, UVM and Verdi Transaction Debugging
A Pseudo-Deterministic Functional ATPG based on EFSM Traversing
A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide
Specification-Based Test Program Generation for ARM VMSAv8-64 Memory Management Units
Two-Way Multicasting for Test Data Compression
Multi-Master Validation Framework for Next Generation Automotive SOCs
20th International Workshop on Microprocessor/SoC Test, Security and Verification, MTV 2019, Austin, TX, USA, December 9-10, 2019
15th International Microprocessor Test and Verification Workshop, MTV 2014, Austin, TX, USA, December 15-16, 2014
Case Study: Verification Framework of Samsung Reconfigurable Processor
TLM Based Approach for Architecture Exploration of Multicore Systems-on-Chip
Verification of CGRA Executable Code and Debugging of Memory Dependence Violation
Fault Diagnosis and Logic Debugging Using Boolean Satisfiability
Is IDDQ Test of Microprocessors Feasible?
Pre-Silicon Validation of IPF Memory Ordering for Multi-Core Processors
System Verilog Assertion Debugging Based on Visualization, Simulation Results, and Mutation
Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA
Hierarchical Verification Framework for Samsung Reconfigurable Processor Video System
Smarter Disk Space Management for Silicon Workflows
An Approach to Multi-core Functional Gate-Level Simulation Minimizing Synchronization and Communication Overheads
A Novel Approach for SVA Generation of DDR Memory Protocols Based on TDML
A Unified Formal Framework for Analyzing Functional and Speed-path Properties
Retiming Verification Using Sequential Equivalence Checking
PICHAFF 2 - A Hierarchical Parallel SAT Solver
Getting Started on Co-Emulation: Transition your Design and Testbench to an Emulator
Automatic Bug Fixing
Expediting Design Bug Discovery in Regressions of x86 Processors Using Machine Learning
TLM Virtual Platform for Fast and Accurate Power Estimation
Different Reference Models for UVM Environment to Speed Up the Verification Time
A Unified UVM Architecture for Flash-Based Memory
Circuit Profiling Mechanisms for High-Level {ATPG}
Bounded Model Checking of Incomplete Real-time Systems Using Quantified SMT Formulas
Open-Source Validation Suite for RISC-V
An ILP-Based Diagnosis Framework for Multiple Open-Segment Defects
Analyzing Efficacy of Constrained Test Program Generators - A Case Study
Secure and Trusted SoC: Challenges and Emerging Solutions
Towards Property Driven Hardware Security
Progressive-BackSpace: Efficient Predecessor Computation for Post-Silicon Debug
An Optimized Simulation-Based Fault Injection and Test Vector Generation Using VHDL to Calculate Fault Coverage
Mechanized Certification of Secure Hardware Designs
Guaranteeing Termination of Fully Symbolic Timed Forward Model Checking
Induction-Based Formal Verification of SystemC TLM Designs
Verification Tests for MCAPI
Hierarchy-Preserving Formal Verification Methods for Pre-silicon Security Assurance
Automatic Debug Quantification for Workload Balance and Progress Tracking
Modified Condition Decision Coverage: A Hardware Verification Perspective
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores
10th International Workshop on Microprocessor Test and Verification, MTV 2009, Austin, Texas, USA, 7-9 December 2009
Hardware Synthesis from Software-Oriented UML Descriptions
Ensuring Functional Closure of a Multi-core SoC through Verification Planning, Implementation and Execution
Automation of Processor Verification Using Recurrent Neural Networks
Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling
Automatic Fault Localization for SystemC TLM Designs
Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA
Mutation Based Feature Localization
PaMira - A Parallel SAT Solver with Knowledge Sharing
Modeling and Analysis of Trusted Boot Processes Based on Actor Network Procedures
Top Level SOC Interconnectivity Verification Using Formal Techniques
Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs
On the Reuse of RTL IPs for SysML Model Generation
An Automated Framework for Correction and Debug of PSL Assertions
Novel MC/DC Coverage Test Sets Generation Algorithm, and MC/DC Design Fault Detection Strength Insights
Vertical Reuse Strategy for Testbench Components Supporting Memory Consistency Checking of an SMP-Capable AMD64 Processor
A Study of Architecture Description Languages from a Model-based Perspective
Ninth International Workshop on Microprocessor Test and Verification, MTV 2008, Austin, Texas, USA, 8-10 December 2008
Constraint Management and Checking in Template-Based Circuit Designs
Workload Slicing for Characterizing New Features in High Performance Microprocessors
A Path-Oriented Timing-Aware Diagnosis Methodology of At-Speed Transition Tests
Using Graphics Processing Units for Logic Simulation of Electronic Designs
Embracing the FPGA Challenge for Processor Design Verification
18th International Workshop on Microprocessor and SOC Test and Verification, MTV 2017, Austin, TX, USA, December 11-12, 2017
Comparison of Verification Methodologies for Datapath Testing
Automotive Microcontroller End-of-Line Test via Software-Based Methodologies
Automatic Test Programs Generation Driven by Internal Performance Counters
RamGen: Moving Memories from Physical to the Logical Domain
Schmoo Data Analysis Using Machine Language Algorithms
Automated Extraction of Structural Information from SystemC-based IP for Validation
Testing the Path Delay Faults of ISCAS85 Circuit c6288
Anvil: Best in Class Multiprocessor Coherency Verification Tool
Tutorial: SoC Power Management Verification and Testing Issues
A Fault Grading Methodology for Software-Based Self-Test Programs in Systems-on-Chip
An Approach for In-House USB2.0 Electrical Compliance Testing on Nanoscale SoC
An Efficient Overlapping Event Generation Method for Symmetric System Testing
A Random Instruction Sequence Generator for ARM Based Systems
Test Generation for CMP Designs
State Retention Validation of C66X DSP Core
Harnessing Nanoscale Device Properties for Hardware Security
AMD64 Processor Front-End Verification (at Unit-Level Testbench) with Instruction Set Simulator
Identifying and Measuring Security Critical Path for Uncovering Circuit Vulnerabilities
Coverage Closure Efficient UVM Based Generic Verification Architecture for Flash Memory Controllers
Echoing the "Generality Concept" through the Bus Functional Model Architecture in Universal Verification Environments
Bounded Model Checking of Incomplete Networks of Timed Automata
Compact ATPG for Concurrent SOC Testing
Mutation Operators for Concurrent SystemC Designs
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications
Anti-counterfeit Techniques: From Design to Resign
FIES: A Fault Injection Framework for the Evaluation of Self-Tests for COTS-Based Safety-Critical Systems
An Efficient Scenario Based Testing Methodology Using UVM
Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis
A Verification Methodology for Reconfigurable Systems
Intel First Ever Converged Core Functional Validation Experience: Methodologies, Challenges, Results and Learning
Synthesizable Memory Models for Virtual Prototyping
16th International Workshop on Microprocessor and SOC Test and Verification, MTV 2015, Austin, TX, USA, December 3-4, 2015
System Verilog Assertions Synthesis Based Compiler
An Efficient Event Generation Method for Testing a SOC with Multiple Processing Elements and Associated Peripherals
Electromagnetic (EM) Crosstalk Failures and Symptoms in SoC Designs
Fourth International Workshop on Microprocessor Test and Verification, Common Challenges and Solutions (MTV 2003), May 29-30, 2003, Hyatt Town Lake Hotel, Austin, Texas, USA
Power Management Verification - An Evolving Discipline
Automatic Detection of Logic Bugs in Hardware Designs
Modeling and Analysis of Secure Processor Extensions Based on Actor Networks
A Configurable Random Instruction Sequence (RIS) Tool for Memory Coherence in Multi-processor Systems
Embedded Software Validation: Applying Formal Techniques for Coverage and Test Generation
Multi-processor Memory Scoreboard: A Multi-processor Memory Ordering and Data Consistency Checker
On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling
A Reconfigurable Five-Stage Pipelined SAT Solver
A Security-Aware Pre-partitioning Technique for 3D Integrated Circuits
A CLP-Based Functional ATPG for Extended FSMs
Dynamic Selection of Trace Signals for Post-Silicon Debug
A Test Method for Power Management of SoC-based Microprocessors
Measuring the Gain of Automatic Debug
Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores
Transaction Based Speedup for Simulation Replay
Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in {VLSI} Circuits
A Deterministic Globally Asynchronous Locally Synchronousy Microprocessor Architecture
USB Validation Challenges on C45SOI & C28NM Technology Products
Leveraging Virtual Prototype Models for Hardware Verification of an Accelerated Network Packet Processing Engine
13th International Workshop on Microprocessor Test and Verification, MTV 2012, Austin, TX, USA, December 10-13, 2012
Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors
A Verification Framework of Neural Processing Unit for Super Resolution
Efficient Methodology of Sampling UVM RAL During Simulation for SoC Functional Coverage
System-level Performance Verification of Multicore Systems-on-Chip
JTAG-AXI Debug IP with Performance Meter Mode
Standards and high tech consortia: tools the experts use to monitor and affect technology trends
The real options approach to standards for building network-based services
Standardization in the ict: towards ever closer union between SSOs and patent offices?
Standard adoption in converging technologies: The interplay between network and system
Essential patents and standard dynamics
Private standards as means of technology transfer
Innovation and standardization: Yin and Yang for policy in motion
Web service security - vulnerabilities and threats within the context of WS-security
The role of standardisation in the context of e-collaboration: a snap shot
An analysis of contribution rates in relation with funding structurization in formulating the Indonesian National Standards (SNIS)
SSO participation and the role of incremental value licensing
Gellish: an information representation language, knowledge base and ontology
Standards of quality and quality of standards for telecommunications and information technologies
On the effects of IS company standards on business process performance
Studying standardization: a review of the literature
Managing patents in standardization: lessons from ETSI's handling of UMTS
Developing an it standard in China - What lessons can we learn from this?
Firms' cooperative activities as driving factors of patent declaration on technological standards
Standards and infrastructure flexibility: Literature review
A descriptive structure to assess the maturity of a standard: application to the UNL system
Installation of an IEEE 802.11 WLAN in a large university setting
End-user participation in standards making? Taking the practical work of standards selection, configuration and use seriously
The economics of open innovation
Standardization of the early Internet: a search for socio-institutional factors
The grand coalition versus competing coalitions: trade-offs in how to standardize
The effect of standards and regulation on radically new innovations
Perilous deviations from FRAND harmony- operational pitfalls of the 2015 IEEE patent policy
Alliance formation in standard setting
Reporting on standards committee meetings: a step toward open standards
Evaluating the performance of standard setting organizations with patent data
Collaboration and competition in emerging standards: an assessment of the implications for knowledge management
Strategic maneuvering and standardization in the presence of network externalities: a simulation study of the VCR case
Gaming standards and innovation
Standardization of innovations in Russia
Toward a national strategy for Open Source Software
Factors influencing the lifetime of telecommunication and information technology standards: results of an explorative analysis of the perinorm database
Formulas for Fair, Reasonable and Non-Discriminatory royalty determination
Differences between human oriented and machine oriented information standards: Implications for design of enterprise-scale information systems
Standards and coordination in open source software
Interdependencies between intellectual property protection and standardisation strategies
Standards and Web site credibility
Interoperability and democracy: A political basis for open document standards
Patent pools-a solution to patent conflicts in standardisation and an instrument of technology transfer: the MP3 case
Engagement in ICT standardization: Pushing the patents or questing for knowledge?
ICT standardization: changing the world for a better tomorrow
Standard setting, RAND licensing and ex ante auctions: The implications of asymmetry
The role of policy in the development of Cognitive Radio systems: Co-evolutionary perspective
8th International Conference on Standardization and Innovation in Information Technology, SIIT 2013, 24-26 September 2013, European Telecommunications Standards Institute (ETSI), Sophia-Antipolis, France, 2011
Better standards to enhance European competitiveness
Making innovation happen: The role of standards and openness in an innovation-friendly ecosystem
Standardisation and innovation in mobile communication markets: the sequence of technology generations
Standardization as a knowledge game
Welcome to SIIT 2005
On standards as change agents - From a pragmatic business perspective
Standard setting abuse: The case for antitrust control
Standardization-a new discipline?
Realities of patent pools in the telecommunication sector
Standards, information and communications: a conceptual basis for a mathematical understanding of technical standards
EU commission's proposal for regulation - The view of DIN
A review of the standards making process in the telecommunications industry: challenges and potential solutions
Dealing with standardization: do you need a guru? Paradoxes and tricks of standardization management
Mass communication and the problem of standardization of space and time in the public sphere
IEC sector board 4, infrastructure of telecommunication networks: introducing the views of the market into the standardization process
The role of standardisation in inter-organisational business processes
The successes and failures of standardization in home systems
Technology substitution and standardization in telecommunication services
Extensive grantback agreements: The effects of partial termination clauses in patent pool contracts on innovation incentives and participation rates
Showcase: A database for standards and patents
The evolving role of standardisation in technological innovation: the case of photovoltaics
Driven profiling of open standards for office applications
Towards a comprehensive model to master company it standards
Internet of Things and Business Models
Experiences from implementing PDF in open source: Challenges and opportunities for standardisation processes
Interoperability as a standard-based ICT competition remedy
Convergence and harmonization of standards organizations
Success in ICT standards setting - A closer look at some influencing factors
Network effects on standard software markets: a simulation model to examine pricing strategies
What makes a killer application for the cellular telephony services?
Standards, strategy and wireless network planning
Digital enclosure: the privatization of standards and standardization
The influence of marketing communications on the dominance of standards
Testing industrall VoIP implementations: registration for SIP phones
Mobile communications and standards dynamics1
Appraisal of the current and future situation for telelearning in the field of standardization: some remarks based on experience gained from the project Telelearning for Standardization within the EU
Difficulties implementing standards
A prototype to analyze and support standardization decisions
A reference model of an instrument for quality measurement of semantic is standards
Switching costs and the choice of a standard setting process