yusuke1997/dblp-id-title huggingface dataset:
FPGA-Accelerated Decision Tree Classifier for Real-Time Supervision of Bluetooth SoC
High-performance FPGA implementations of volterra DFEs for optical fiber systems
A Hardware-Efficient Frequency Domain Correlator Architecture for Acquisition Stage in GPS
Power analysis attack on hardware implementation of MAC-Keccak on FPGAs
An architectural template for composing application specific datapaths at runtime
Improving KLT in Embedded Systems by Processing Oversampling Video Sequence in Real-Time
FPGA debugging by a device start and stop approach
Virtualization of Computing Resources in RCS for Multi-task Stream Applications
2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011
A case study of streaming storage format for sparse matrices
A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2
Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units
An implementation of 3D Electron Tomography on FPGAs
Design of Coarse-Grained Dynamically Reconfigurable Architecture for DSP Applications
2005 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2005, Puebla City, Mexico, September 28-30, 2005
Side channel attack on multiprecision multiplier used in protected ECDSA implementation
Efficient FPGA-based implementation of a CAZAC sequence generator for 3GPP LTE
Using Runtime Circuit Specialization to Accelerate Simulations of Reconfigurable Architectures
Real Time FPGA-based Architecture for Video Applications
An Architecture for Reconfigurable Multi-core Explorations
Seiba: An FPGA Overlay-Based Approach to Rapid Application Development
Bio - Inspired & Traditional Approaches to Obtain Fault Tolerance
VHDL Core for the Computation of the One-Dimensional Discrete Cosine Transform
VANNGen: a flexible CAD tool for hardware implementation of artificial neural networks
A Process-Oriented Streaming System Design Paradigm for FPGAs
Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth
Modelling and Quantitative Analysis of Coupling Mechanisms of Programmable Processor Cores and Arithmetic Oriented eFPGA Macros
An FPGA Accelerator for Embedded Microcontrollers Implementing a Ternarized Backpropagation Algorithm
On the design of two-level reconfigurable architectures
Fault Injection Results of Linux Operating on an FPGA Embedded Platform
FPGA-based Accurate Pedestrian Detection with Thermal Camera for Surveillance System
Fast generation of high throughput customized deep learning accelerators on FPGAs
Distributed execution of transmural electrophysiological imaging with CPU, GPU, and FPGA
Towards the generic reconfigurable accelerator: Algorithm development, core design, and performance analysis
Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA Platform
Towards a Generalized Reconfigurable Agent-Based Architecture: Stock Market Simulation Acceleration
A Reconfigurable Simulation Framework for Financial Computation
Spiking dynamic neural fields architectures on FPGA
Parallel Backprojector for Cone-Beam Computer Tomography
Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems
Optimizing Decomposition-Based Packet Classification Implementation on FPGAs
A hardware architecture for filtering irreducible testors
2019 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2019, Cancun, Mexico, December 9-11, 2019
Adapting communication for adaptable processors: A multi-axis reconfiguration approach
Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts of Configuration Memory Space
Characterization of OpenCL on a scalable FPGA architecture
2014 International Conference on ReConFigurable Computing and FPGAs, ReConFig14, Cancun, Mexico, December 8-10, 2014
Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations
Design Space Exploration for an Adaptive Noise Cancellation Algorithm
VHDL generator for a high performance convolutional neural network FPGA-based accelerator
RAR-NoC: A reconfigurable and adaptive routable Network-on-Chip for FPGA-based multiprocessor systems
FPGA-based Accelerators of Fully Pipelined Modular Multipliers for Homomorphic Encryption
A Runtime Profiler: Toward Virtualization of Polymorphic Computing Platforms
Post-Routing Analytical Wirelength Model for Homogeneous FPGA Architectures
FPGA Implementation of Izhikevich Spiking Neural Networks for Character Recognition
A device-agnostic tool for precomputing legal placements in modular design flows
Analysis and Preliminary Measurements of Radiated Emissions in an Asynchronous Circuit versus its Synchronous Counterpart
Isolation of behavior design from system implementation
Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study
Efficient OpenCL Accelerators for Canny Edge Detection Algorithm on a CPU-FPGA Platform
Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring applications
High-Speed Ring Oscillator based Sensors for Remote Side-Channel Attacks on FPGAs
Cascading Deep Pipelines to Achieve High Throughput in Numerical Reduction Operations
Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings
Change-driven Image Architecture on FPGA with adaptive threshold for Optical-Flow Computation
Celator: A Multi-algorithm Cryptographic Co-processor
LaKe: The Power of In-Network Computing
Empty Resource Compaction Algorithms for Real-Time Hardware Tasks Placement on Partially Reconfigurable FPGAs Subject to Fault Ocurrence
MiCAP: a custom reconfiguration controller for dynamic circuit specialization
Rapid prototyping of a self-timed ALU with FPGAs
Deriving concentrators from binary sorters using half cleaners
Hardware Pessimistic Run-Time Profiling for a Self-Reconfigurable Embedded Processor Architecture
FPGA 2 : An open source framework for FPGA-GPU PCIe communication
FPGA-Based Online Induction Motor Multiple-Fault Detection with Fused FFT and Wavelet Analysis
On the performance and energy efficiency of FPGAs and GPUs for polyphase channelization
HCrypt: A Novel Concept of Crypto-processor with Secured Key Management
An effective probability distribution SAT solver on reconfigurable hardware
Reconfigurable FPGA-Based Unit for Singular Value Decomposition of Large m x n Matrices
Digital Hardware Architectures of Kohonen's Self Organizing Feature Maps with Exponential Neighboring Function
A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances
Keynote - The past and future of FPGA soft processors
Performance-Area Improvement by Partial Reconfiguration for an Aerospace Remote Sensing Application
Can high-level synthesis compete against a hand-written code in the cryptographic domain? A case study
A generic pixel distribution architecture for parallel video processing
Snake: An Efficient Strategy for the Reuse of Circuitry and Partial Computation Results in High-Performance Reconfigurable Computing
FPGA Implementations of Radix-10 Digit Recurrence Fixed-Point and Floating-Point Dividers
Keynote 2 - "Reconfigurable Computing and Trust: Foundational technologies to enable trusted reconfigurable platforms"
An FPGA implementation of a long short-term memory neural network
Dataflow optimization for programmable embedded image preprocessing accelerators
An efficient and scalable architecture for real-time distortion removal and rectification of live camera images
Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable Architectures
Platform for intrinsic evolution of analogue neural networks
Glitch-aware variable pipeline optimization for CGRAs
Multiple contexts in a multi-ported VLIW register file implementation
A Hardware Filesystem Implementation for High-Speed Secondary Storage
A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors
A PID Controller Applied to the Gain Control of a CMOS Camera Using Reconfigurable Computing
Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture
FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting
FPGA-based acceleration of high density myoelectric signal processing
SPREX: A soft processor with Runahead execution
Robustness of different TMR granularities in shared wishbone architectures on SRAM FPGA
Timing error handling on CGRAs
Cycle-Accurate Debugging of Multi-clock Reconfigurable Systems
Low Power RTL Exploration Mechanism Based on the Cache Parameters
Approximate Adder Tree Synthesis for FPGAs
Electronic System Level Power and Performance Analysis for Multi-Processor-System-on-Chip
REoN: A protocol for reliable software-defined FPGA partial reconfiguration over network
FAUPU - A design framework for the development of programmable image processing architectures
Efficient and side-channel resistant authenticated encryption of FPGA bitstreams
Multi-channel Driving Systems for Therapeutic Applications Based-on Focused Ultrasound
Real-timerange image preprocessing on FPGAs
A software configurable and parallelized coprocessor architecture for LQR control
Smart employment of circuit redundancy to effectively counter trojans (SECRET) in third-party IP cores
An adaptive victim cache scheme
An Optimized FPGA Implementation for a Parallel Path Planning Algorithm Based on Marching Pixels
A real-time reconfigurable architecture for face detection
Keynote - SpaceCube - A family of reconfigurable hybrid on-board science data processors
A platform for secure IP integration in Xilinx Virtex FPGAs
Reconfigurable Cache Implemented on an FPGA
On FPGA-Based Implementations of the SHA-3 Candidate Grøstl
Improved method for parallel AES-GCM cores using FPGAs
A scalable latency-insensitive architecture for FPGA-accelerated semi-global matching in stereo vision applications
Synthesis and Implementation of Hierarchical Finite State Machines with Implicit Modules
Adaptive Energy-Efficient Architecture for WCDMA Channel Estimation
Performance modeling and optimization of 3-D stencil computation on a stream-based FPGA accelerator
Accurate in-situ runtime measurement of energy per operation of system-on-chip on FPGA
Dynamic and partial reconfiguration of Zynq 7000 under Linux
Merging Programming Models and On-chip Networks to Meet the Programmable and Performance Needs of Multi-core Systems on a Programmable Chip
A Coarse-Grained Reconfigurable Array for High-Performance Computing Applications
Versatile FPGA-based locomotion platform for legged robots
Robustness Analysis of Different AES Implementations on SRAM Based FPGAs
PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems
gNOSIS: A Board-Level Debugging and Verification Tool
Optimizing memory performance for FPGA implementation of pagerank
Enhancing the Productivity of Radio Designers with RapidRadio
Configuration Sharing Optimized Placment and Routing
Towards a reconfigurable distributed testbed to enable advanced research and development of timing and synchronization in cyber-physical systems
Kernel-centric acceleration of high accuracy stereo-matching
Video super resolution algorithm implemented on a low-cost NoC-based MPSoC platform
Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI
GIMME2 - an embedded system for stereo vision and processing of megapixel images with FPGA-acceleration
A Reconfigurable Platform for Frequent Pattern Mining
A universal hardware API for authenticated ciphers
Real-time pedestrian detection on a xilinx zynq using the HOG algorithm
Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation
FPGA implementation of an efficient multiplier over finite fields GF(2 m )
Reconfigurable PDA for the Visually Impaired Using FPGAs
Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices
Ant Colony Optimization based Module Footprint Selection and Placement for Lowering Power in Large FPGA Designs
Operating System Structures for Multiprocessor Systems on Programmable Chip
Accelerating the construction of BRIEF descriptors using an FPGA-based architecture
Dynamic reconfiguration of modular I/O IP cores for avionic applications
Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations
Power Consumption Calculation of AP-DCD Algorithm Using FPGA Platform
FPGA Implementation of the Generalized Hough Transform
Expediting GA-Based Evolution Using Group Testing Techniques for Reconfigurable Hardware
Parametric, Secure and Compact Implementation of RSA on FPGA
An automated test framework for experimenting with stochastic behavior in reconfigurable logic
ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings
An FPGA-based design for joint control and monitoring of permanent magnet synchronous motors
Keynote 2 - FPGA-accelerated high-performance computing - Close to breakthrough or pipedream?
A Real-Time FPGA Based Platform for Applications in Mechatronics
PoC-align: An open-source alignment accelerator using FPGAs
GIMME - A General Image Multiview Manipulation Engine
Solving large systems of linear equations over GF(2) on FPGAs
R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip
Fast fixed-point divider based on Newton-Raphson method and piecewise polynomial approximation
MiniMIPS: An 8-Bit MIPS in an FPGA for Educational Purposes
An AXI compatible cypress EZ-USB FX3 interface for USB-3.0 SuperSpeed
FPGA-based customizable systolic architecture for image processing applications
A highly parallel AES-GCM core for authenticated encryption of 400 Gb/s network protocols
The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture
Efficient Utilization of DSPs and BRAMs Revisited: New AES-GCM Recipes on FPGAs
High Efficiency Space-Based Software Radio Architectures: A Minimum Size, Weight, and Power TeraOps Processor
Spectral Method Characterization on FPGA and GPU Accelerators
Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling
Hardware OS Communication Service and Dynamic Memory Management for RSoCs
Exploring the dynamics of large-scale gene regulatory networks using hardware acceleration on a heterogeneous CPU-FPGA platform
Automating structured matrix-matrix multiplication for stream processing
A Dynamically Reconfigurable Platform for Fixed-Point FIR Filters
Robust bitstream protection in FPGA-based systems through low-overhead obfuscation
A small and adaptive coprocessor for information flow tracking in ARM SoCs
A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier
Optimized Architectural Synthesis of Fixed-Point Datapaths
Dynamic protocol stacks in smart camera networks
Evaluation of the CAESAR hardware API for lightweight implementations
2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006, San Luis Potosi, Mexico, September 20-22, 2006
FPGA-based rapid prototyping platform for MIMO-BICM design space exploration
Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard
An Optimized System for Multiple Sequence Alignment
A FPGA-based scalable architecture for URL legal filtering in 100GbE networks
Reconfigurable Hardware Implementation of Arithmetic Modulo Minimal Redundancy Cyclotomic Primes for ECC
A configurable architecture for the generalized hough transform applied to the analysis of huge aerial images and to traffic sign detection
An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures
Efficient PGA LFSR Implementation Whitens Pseudorandom Numbers
FPGA Bootstrapping on PCIe Using Partial Reconfiguration
Hardware Design of a 256-Bit Prime Field Multiplier Suitable for Computing Bilinear Pairings
Highly Parameterized K-means Clustering on FPGAs: Comparative Results with GPPs and GPUs
FPGA-based accelerator development for non-engineers
Toward All Optical Interconnections in Chip Multiprocessor (2)
Power-efficient and highly scalable parallel graph sampling using FPGAs
A scalable evolvable hardware processing array
An implementation of a directory protocol for a cache coherent system on FPGAs
Keynote 1 - The once and future FPGA: The confluence of configurable processing and reconfigurable technology
Hardware-accelerated pose estimation for embedded systems using Vivado HLS
Accuracy, cost, and performance tradeoffs for floating-point accumulation
Efficient Dual-Rail Implementations in FPGA Using Block RAMs
Optimizing register binding in FPGAs using simulated annealing
A low complexity H.264/AVC 4×4 intra prediction architecture with macroblock/block reordering
Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems
An Analysis of Implanted Antennas in Xilinx FPGAs
Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAs
A Dynamically Reconfigured Network Platform for High-Speed Malware Collection
Full-HD Accelerated and Embedded Feature Detection Video System with 63fps using ORB for FREAK
Fixed-Point Arithmetic Error Estimation in Monte-Carlo Simulations
ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 3-5 December 2008, Cancun, Mexico, Proceedings
Aging effects on ring-oscillator-based physical unclonable functions on FPGAs
Runtime Memory Allocation in a Heterogeneous Reconfigurable Platform
RALP: Reconvergence-aware layer partitioning for 3D FPGAs
Area-efficient dynamically reconfigurable protocol-processing-hardware for access network communications SoC
Performance modeling of reconfigurable distributed systems based on the opensparc FPGA board and the SIRC communication framework
Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices
Accelerating Texture Features Extraction Algorithms Using FPGA Architecture
Hardware design and implementation of a Network-on-Chip based load balancing switch fabric
Resiliency-aware Scheduling for reconfigurable VLIW processors
A Handel-C implementation of the back-propagation algorithm on field programmable gate arrays
Enhancing productivity with back-end similarity matching of digital circuits for IP reuse
Evaluating Floating-point Intensive Applications on OpenCL FPGA Platforms: A Case Study on the SimpleMOC Kernel
Genetic Algorithms and Artificial Neural Networks to Combinational Circuit Generation on Reconfigurable Hardware
Parallel Data Sort Using Networked FPGAs
FASE: An Open Run-Time Reconfigurable FPGA Architecture for Tamper-Resistant and Secure Embedded Systems
Design of High Throughput FPGA-Based Testbed for Accelerating Error Characterization of LDPC Codes
Design Space Exploration and Performance Analysis for the Modular Design of CVS in a Heterogeneous MPSoC
FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation
International Conference on ReConFigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, December 4-6, 2017
Fuzzy Control for Cyclist Robot Stability Using FPGAs
Reconfigurability-Aware Structural Mapping for LUT-Based FPGAs
Triple Line-Based Playout for Go - An Accelerator for Monte Carlo Go
A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systems
A Cost-Effective Solution to Increase System Reliability and Maintain Global Performance under Unreliable Silicon in MPSoC
Scalable analytic placement for FPGA on GPGPU
Extracting memory-level parallelism through reconfigurable hardware traces
Coarse grain reconfiguration: Power estimation and management flow for hybrid gated systems
FPGA implementation of optimized XBM specifications by transformation for AFSMs
A VLSI architecture for the K-best Sphere-Decoder in MIMO systems
Open Source Precision Timed Soft Processor for Cyber Physical System Applications
Automated design flow for no-cost configuration error detection in sram-based FPGAs
A hardware pipelined architecture of a scalable Montgomery modular multiplier over GF(2 m )
Improving memory performance in reconfigurable computing architecture through hardware-assisted dynamic graph
Investigation of DPA Resistance of Block RAMs in Cryptographic Implementations on FPGAs
Power Consumption Estimations vs Measurements for FPGA-Based Security Cores
Akers's wavefront planner - One of the fastest stencil-based path planners on FPGAs
Finite Precision Analysis of the 3GPP Standard Turbo Decoder for Fixed-Point Implementation in FPGA Devices
Reconfigurable Node Processing Unit for a Low-Power Wireless Sensor Network
An FPGA-based approach for packet deduplication in 100 gigabit-per-second networks
A single-chip solution for the secure remote configuration of FPGAs using bitstream compression
Reconfigurable Implementation of Wavelet Integer Lifting Transforms for Image Compression
FPGA Implementation of Pseudo Random Number Generators for Monte Carlo Methods in Quantitative Finance
A Physical Resource Management Approach to Minimizing FPGA Partial Reconfiguration Overhead
Efficient FPGA Cost-Performance Space Exploration using Type-Driven Program Transformations
G-DMA: improving memory access performance for hardware accelerated sparse graph computation
Runtime Temporal Partitioning Assembly to Reduce FPGA Reconfiguration Time
Adaptive Multi-client Network-on-Chip Memory
A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors
A robust and low resource FPGA-based stereoscopic vision algorithm
Issues on Building an MPI Cluster on Microblaze
Skein Tree Hashing on FPGA
EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture
Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules
A Reconfigurable Architecture for Stereo-Assisted Detection of Point-Features for Robot Mapping
The portable open-source IP core and utility library PoC
Accelerating all-pairs shortest path using a message-passing reconfigurable architecture
FPGA Implementation of ECC: Low-Cost Countermeasure against Horizontal Bus and Address-Bit SCA
FPGA-based testbed for timing behavior evaluation of the Controller Area Network (CAN)
Energy-efficient reconfiguration of flash-based FPGAs in heterogeneous wireless sensor nodes
Enumeration of Costas Arrays Using GPUs and FPGAs
Keynote 2 - Towards datacenter computing with FPGAs
FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps Networks
Module relocation in Heterogeneous Reconfigurable Systems-on-Chip using the Xilinx Isolation Design Flow
Improving Fault Tolerance of Network-on-Chip Links via Minimal Redundancy and Reconfiguration
SoC self-integration mechanism for dynamic reconfigurable systems based on collaborative macro-function units
A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems
Runtime Task Mapping Based on Hardware Configuration Reuse
Buffering strategies for ultra high-throughput stream processing
Large-scale high-dimensional nearest neighbor search using flash memory with in-store processing
Shape exploration for modules in rapid assembly workflows
New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGA
UT-OCL: an OpenCL framework for embedded systems using xilinx FPGAs
A low power configurable SoC for simulating delay-based audio effects
A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations
A Dynamically Reconfigurable Automata Processor Overlay
A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links
Base-Calling in DNA Pyrosequencing with Reconfigurable Bayesian Network
A Hybrid Router Combining SDM-Based Circuit Swictching with Packet Switching for On-chip Networks
Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays
Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime
Providing Better Multi-processor Systems-on-Chip Resources Utilization by Means of Using a Control-Loop Feedback Mechanism
Energy-efficient architecture for stride permutation on streaming data