yusuke1997/dblp-id-title huggingface dataset:
Efficient Hardware Implementation of Artificial Neural Networks on FPGA
HPPU: An Energy-Efficient Sparse DNN Training Processor with Hybrid Weight Pruning
ConvMapSim: Modeling and Simulating Convolutional Weight Mapping for PIM Arrays
SNN Architecture for Differential Time Encoding Using Decoupled Processing Time
EdgeDRNN: Enabling Low-latency Recurrent Neural Network Edge Inference
AdaQAT: Adaptive Bit-Width Quantization-Aware Training
Bin-Specific Quantization in Spectral-Domain Convolutional Neural Network Accelerators
RSPE: A High Energy Efficient SNN Inference Processor with RISC-V based Dynamic Pruning Mechanism
LG-LSQ: Learned Gradient Linear Symmetric Quantization for Low-Precision Integer Hardware
Lifetime Enhancement for RRAM-based Computing-In-Memory Engine Considering Aging and Thermal Effects
Temperature Compensation Schemes for In-Memory Computing using Phase-Change Memory
A Low-power 3D Point Clouds Matching Processor with 1D-CNN Prediction and CAM-based In-memory kNN Searching
Biologically-inspired training of spiking recurrent neural networks with neuromorphic hardware
Autopiler: An AI Based Framework for Program Autotuning and Options Recommendation
NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro
Efficient MFCC Computation for Keyword Spotting on Embedded Systems: Optimization Techniques and Performance Analysis
AnalogHTM: Memristive Spatial Pooler Learning with Backpropagation
MSCA: Model-Driven Search for Optimal Configuration for SpMM Accelerators
A single-stage detector of cerebral microbleeds using 3D feature fused region proposal network (FFRP-Net)
Exploiting Memristors for Neuromorphic Reinforcement Learning
A Convolutional Spiking Network for Gesture Recognition in Brain-Computer Interfaces
Contention-aware Adaptive Model Selection for Machine Vision in Embedded Systems
Design of a Full CMOS Computer Vision Sensor with an Embedded Analog Convolutional Neural Network Processor for Human Face Recognition
Hardware Approximation of Exponential Decay for Spiking Neural Networks
Compute-in-RRAM with Limited On-chip Resources
Configurable CNN Accelerator in Speech Processing based on Vector Convolution
Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks
A low power neural network training processor with 8-bit floating point with a shared exponent bias and fused multiply add trees
Memory-Immersed Collaborative Digitization for Area-Efficient Compute-in-Memory Deep Learning
LogicCraft: LLM-Assisted Optimization of Netlist to Layout for Complex Custom Standard Cell Designs
Quality Evaluation Method for Chest X-Ray Images using the Reference Patterns
Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs
Dynamic Backdoors with Global Average Pooling
Age Estimation on Low Quality Face Images
Energy Efficient Computing with Heterogeneous DNN Accelerators
Active Dendrites Enable Efficient Continual Learning in Time-To-First-Spike Neural Networks
An Analog Neural Network for Estimating Sea State or Wave Height from Inertial Sensor Data
Energy-Efficient Deep Reinforcement Learning Accelerator Designs for Mobile Autonomous Systems
Towards Automated FPGA Compilation of Spiking Neural Networks
Kinship Verification from Text: Towards Discovering Subtitle Textual Features Shared by Family Members using Large Language Models
Configurable Texture Unit for Convolutional Neural Networks on Graphics Processing Units
Accelerated Simulation of a Neuronal Population via Mathematical Model Order Reduction
A 35x10 Charge-Trap Synaptic Memory for 57xMatrix Recognition
On-chip Pixel Reconstruction using Simple CNN for Sparsely Read CMOS Image Sensor
A 200M-Query-Vector/s Computing-in-RRAM ADC-less k-Nearest-Neighbor Accelerator with Time-Domain Winner-Takes-All Circuits
A Hybrid Heterogeneous Neural Network Accelerator based on Systolic Array
FlexBits: A Configurable Lightweight RISC-V Micro-architecture for Flexible Bit-Width Execution
Exploiting Weight Statistics for Compressed Neural Network Implementation on Hardware
MF-DSNN:An Energy-efficient High-performance Multiplication-free Deep Spiking Neural Network Accelerator
A probability-inspired normalization for fixed-precision Hyper-Dimensional Computing
Extended Bit-Plane Compression for Convolutional Neural Network Accelerators
A Learnable Unmanned Smart Logistics Prototype System Design and Implementation
Strategic Deployment of Honeypots in Blockchain-based IoT Systems
A Quality-Oriented Reconfigurable Convolution Engine Using Cross-Shaped Sparse Kernels for Highly-Parallel CNN Acceleration
Optimal Mapping of Monte Carlo Analysis for Analog Circuit Designing using Bayesian Neural Networks
ECG-TCN: Wearable Cardiac Arrhythmia Detection with a Temporal Convolutional Network
Low-current, highly linear synaptic memory device based on MoS 2 transistors for online training and inference
Hardware-Friendly Activation Function Designs and Its Efficient VLSI Implementations for Transformer-Based Applications
Neuro-PULP: A Paradigm Shift Towards Fully Programmable Platforms for Neural Interfaces
On Automatic Generation of Training Images for Machine Learning in Automotive Applications
Energy-Efficient, Nonvolatile 8T-2MTJ Ternary CAM Cell for Low Search Delay
A Full-Neuron Memory Model Designed for Neuromorphic Systems
DualNet: Efficient Integration of Artificial Neural Network and Spiking Neural Network with Equivalent Conversion
Efficient Zero-Activation-Skipping for On-Chip Low-Energy CNN Acceleration
Performance Assessment of an Extremely Energy-Efficient Binary Neural Network Using Adiabatic Superconductor Devices
Intrinsic Sparse LSTM using Structured Targeted Dropout for Efficient Hardware Inference
Echo State Networks for Accurate and Efficient Modeling of Dynamic Circuits
The Multilayer Neural Network Implementation Using SRAM-Based Reconfigurable Cognitive Computation Matrices
Q-Segment: Segmenting Images In-Sensor for Vessel-Based Medical Diagnosis
ACC: Adaptive Compression Framework for Efficient On-device CNN Training
Landmark-Based Adversarial Network for RGB-D Pose Invariant Face Recognition
A Systolic Array with Activation Stationary Dataflow for Deep Fully-Connected Networks
Heart Rate Estimation from Ballistocardiogram Using Hilbert Transform and Viterbi Decoding
Row-wise Accelerator for Vision Transformer
Fast, Efficient and Lightweight Compressed Image Super-Resolution Network for Edge Devices
A Coarse-Grained Dual-Convolver Based CNN Accelerator with High Computing Resource Utilization
Efficient FPGA Implementation of a Convolutional Neural Network for Radar Signal Processing
Reduced-Precision Floating-Point Arithmetic in Systolic Arrays with Skewed Pipelines
Convolutional Neural Network Classification of Basal Cell Carcinoma in Harmonically Generated Microscopy Images
SENeCA: Scalable Energy-efficient Neuromorphic Computer Architecture
A Flexible and Fast PyTorch Toolkit for Simulating Training and Inference on Analog Crossbar Arrays
A Hardware-Efficient EMG Decoder with an Attractor-based Neural Network for Next-Generation Hand Prostheses
A Behavior-Level Simulation Framework for RRAM-Based Deep Learning Accelerators with Flexible Architecture Configurations
7th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2025, Bordeaux, France, April 28-30, 2025
TPC-NAS: Simple and Effective Neural Architecture Search Based on Total Path Count
Dynamic Detection and Mitigation of Read-disturb for Accurate Memristor-based Neural Networks
Securing Decision Tree Inference Using Order-Preserving Cryptography
An Efficient and Fast Filter Pruning Method for Object Detection in Embedded Systems
Reconfigurable Acceleration of Graph Neural Networks for Jet Identification in Particle Physics
BiMDiM: Area efficient Bi-directional MRAM Digital in-Memory Computing
A High Performance Accelerating CNN Inference on FPGA with Arrhythmia Classification
Energy-Efficient Intelligent EPTS Device using Novel DCNN-Based Dynamic Sensor Activation
AI Processor based Data Correction for Enhancing Accuracy of Ultrasonic Sensor
Memristor-Based In-Circuit Computation for Trace-Based STDP
Sample-Specific Backdoor based Active Intellectual Property Protection for Deep Neural Networks
Optimization Strategies for Digital Compute-in-Memory from Comparative Analysis with Systolic Array
An Energy-Efficient Look-up Table Framework for Super Resolution on FPGA
Robust Learning and Recognition of Visual Patterns in Neuromorphic Electronic Agents
MRAM-based BER resilient Quantized edge-AI Networks for Harsh Industrial Conditions
PPT-KP: Pruning Point Training-based Kernel Pruning for Deep Convolutional Neural Networks
Neuromorphic Robotics on Conventional Low-Power CPU Hardware
Implementation of STDP Learning for Non-volatile Memory-based Spiking Neural Network using Comparator Metastability
Stochastic Spiking Attention: Accelerating Attention with Stochastic Computing in Spiking Networks
5th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2023, Hangzhou, China, June 11-13, 2023
Classification of Cardiac Arrhythmias Based on Artificial Neural Networks and Continuous-in-Time Discrete-in-Amplitude Signal Flow
Exploration for Efficient Depthwise Separable Convolution Networks Deployment on FPGA
Architecture-Aware Optimization of Layer Fusion for Latency-Optimal CNN Inference
Special Session: 2018 Low-Power Image Recognition Challenge and Beyond
An Efficient and Fast Softmax Hardware Architecture (EFSHA) for Deep Neural Networks
A Real-Time 3DGS-SLAM with Voxel-based Memory Management and Region of Interest-based Pixel-wise Skipping Architecture on Edge Device
Sparse Autoencoder with Attention Mechanism for Speech Emotion Recognition
EnhancePPG: Improving PPG-based Heart Rate Estimation with Self-Supervision and Augmentation
Optimizing Accelerator Configurability for Mobile Transformer Networks
Design and Implementation of an Easy-to-Deploy Energy-Efficient Inference Acceleration System for Multi-Precision Neural Networks
Piecewise NARX Behavioral Model for RF Power Amplifiers in 5G Applications
Multi-Resolution Siamese Networks for One-Shot Learning
Characterization of an Analog MAC Cell with Multi-Bit Resolution for AI Inference Accelerators
Convergent Waveform Relaxation Schemes for the Transient Analysis of Associative ReLU Arrays
A Byte Sequence is Worth an Image: CNN for File Fragment Classification Using Bit Shift and n-Gram Embeddings
Towards On-device Domain Adaptation for Noise-Robust Keyword Spotting
Low-Complexity High Speed Residual Network-Augmented Channel Estimation for mmWave Massive MIMO
A CMOS-based Resistive Crossbar Array with Pulsed Neural Network for Deep Learning Accelerator
Microarchitecture Aware Neural Architecture Search for TinyML Devices
Temporal Similarity-Based Computation Reduction for Video Transformers in Edge Camera Nodes
A General-Purpose and Configurable Planar Data Processor for Energy-Efficient Pooling Computation
SVD-based Peephole and Clustering to Enhance Trustworthiness in DNN Classifiers
Real-time Super Resolution CNN Accelerator with Constant Kernel Size Winograd Convolution
Binary is All You Need: Ultra-Efficient Arrhythmia Detection with a Binary-Only Compressive System
Deep-learning-based X-ray CT Slice Analysis for Layout Verification in Printed Circuit Boards
RNN-Based Low Complexity High Speed Channel Estimation Architectures for Vehicular Networks
A SiPM-Based Directional Gamma-Ray Spectrometer With Embedded Machine Learning
Federated Regularization Learning: an Accurate and Safe Method for Federated Learning
Efficient Algorithms for Accelerating Spiking Neural Networks on MAC Array of SpiNNaker 2
Error-triggered Three-Factor Learning Dynamics for Crossbar Arrays
EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets
Improved Memristor Control using Device Physics and Deep Reinforcement Learning
Performance Evaluation of Neuromorphic Visual Attention Based on Proto-Objects
A Hybrid Spiking Recurrent Neural Network on Hardware for Efficient Emotion Recognition
A 62.45 TOPS/W Spike-Based Convolution Neural Network Accelerator with Spatiotemporal Parallel Data Flow and Sparsity Mechanism
Enhancing Anomaly Detection with Entropy Regularization in Autoencoder-based Lightweight Compression
Low-Power HWAccelerator for AI Edge-Computing in Human Activity Recognition Systems
Classification of ECG based on Hybrid Features using CNNs for Wearable Applications
PBNNs: Plastic Bayesian Neural Networks for Bio-Inspired Bayesian Learning
Implementation of an Quantum Circuit Simulator using Classical Bits
A Hierarchically Reconfigurable SRAM-Based Compute-in-Memory Macro for Edge Computing
Effect of Process Variations in Digital Pixel Circuits on the Accuracy of DNN based Smart Sensor
Uncertainty-based Object Detector for Autonomous Driving Embedded Platforms
Optimizations of Scatter Network for Sparse CNN Accelerators
Image Frequency Separation Residual Network for End-to-end RAW to RGB Mapping
Extensible and Modularized Processing Unit Design and Implementation for AI Accelerator
Fast Detection of Objects Using a YOLOv3 Network for a Vending Machine
E-Track: Eye Tracking with Event Camera for Extended Reality (XR) Applications
Fine-Tuned Based Transfer Learning with Temporal Attention and Physics-Informed Loss for Bearing RUL Prediction
Language Modeling on a SpiNNaker2 Neuromorphic Chip
NeuronFlow: A Hybrid Neuromorphic - Dataflow Processor Architecture for AI Workloads
A Reconfigurable Event Driven Accelerator for SNN Inference
SALSA: Simulated Annealing based Loop-Ordering Scheduler for DNN Accelerators
DualPIM: A Dual-Precision and Low-Power CNN Inference Engine Using SRAM- and eDRAM-based Processing-in-Memory Arrays
A Pipeline-Based Scheduler for Optimizing Latency of Convolution Neural Network Inference over Heterogeneous Multicore Systems
Graph-Based Spatio-Temporal Backpropagation for Training Spiking Neural Networks
ILP-based Multi-Branch CNNs Mapping on Processing-in-Memory Architecture
GEMMify: A Unified Model for Layer-Wise DNN Performance Prediction on Edge GPUs
OTFC-LSTM: An Efficient Design of LSTM Accelerator based on On-The-Fly CORDIC
Real-time Language Recognition using Hyperdimensional Computing on Phase-change Memory Array
In-memory PageRank using a Crosspoint Array of Resistive Switching Memory (RRAM) devices
Edge and Fog Computing Enabled AI for IoT-An Overview
Neuromorphic Temporal Pattern Detection with Spiking Neural Networks using Synaptic Delays
Challenges and Opportunities of Edge AI for Next-Generation Implantable BMIs
An Energy-Efficient Hardware Accelerator for Hierarchical Deep Reinforcement Learning
TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network
A Low-Power Hardware Accelerator of MFCC Extraction for Keyword Spotting in 22nm FDSOI
A Survey on Side-Channel-based Reverse Engineering Attacks on Deep Neural Networks
MLFlash-CIM: Embedded Multi-Level NOR-Flash Cell based Computing in Memory Architecture for Edge AI Devices
Tunneling-based CMOS Floating Gate Synapse for Low Power Spike Timing Dependent Plasticity
A 28nm 343.5fps/W Vision Transformer Accelerator with Integer-Only Quantized Attention Block
Memory Efficient Invertible Neural Networks for Class-Incremental Learning
ViT-LCA: A Neuromorphic Approach for Vision Transformers
Low-power ECG acquisition by Compressed Sensing with Deep Neural Oracles
Vibration may Break the Conductive Filament in amorphous Germanium based Memristor
ANP-L: A 22nm 0.72pJ/SOP Asynchronous SNN-based Edge-AI Processor Enabling One/Few-shot On-chip Incremental Learning
Epilepsy Identification System with Neural Network Hardware Implementation
EILE: Efficient Incremental Learning on the Edge
A 1.15-TOPS 6.57-TOPS/W DNN Processor for Multi-Scale Object Detection
Group Vectored Absolute-Value-Subtraction Cell Array for the Efficient Acceleration of AdderNet
GaN Distributed RF Power Amplifer Automation Design with Deep Reinforcement Learning
An AutoEncoder-Based Semi-Supervised Learning for Efficient Blood Pressure Estimation with Minimal Labeled Data
Reconfigurable Dataflow and Tile Shape Optimization in SystemC-Based NoC of 1D PE Array Simulators integrated with TVM
TinyissimoYOLO: A Quantized, Low-Memory Footprint, TinyML Object Detection Network for Low Power Microcontrollers
Optimizing Vision Transformers: Leveraging Max and Min Operations for Efficient Pruning
LungHeart-AtMe: Adventitious Cardiopulmonary Sounds Classification Using MMoE with STFT and MFCCs Spectrograms
Artificial Intelligence of Things Wearable System for Cardiac Disease Detection
Flexible-width Bit-level Compressor for Convolutional Neural Network
NeuroPilot: A Cross-Platform Framework for Edge-AI
Exploring Memory Access Techniques for Efficient FPGA based 3D CNN Accelerator Design
A 26.7 TOPS/W Multiplier-Less Digital In-Memory Computing Macro with low-cost Multi-Layer Inference in 28nm FDSOI for edge AI
Optimizing and Exploring System Performance in Compact Processing-in-Memory-based Chips
On-chip Few-shot Learning with Surrogate Gradient Descent on a Neuromorphic Processor
RCPE: An Excellent Performance Training Processor with RISC-V based Compression Mechanism
Image Recovery Through Scattering Media via GAN Reconstruction and SNES Optimization
A Convolved Self-Attention Model for IMU-based Gait Detection and Human Activity Recognition
A Ternary Weight Mapping and Charge-mode Readout Scheme for Energy Efficient FeRAM Crossbar Compute-in-Memory System
A Bio-Inspired Motion Detection Circuit Model for the Computation of Optical Flow: The Spatial-Temporal Filtering Reichardt Model
Hardware-Aware Neural Architecture Search for Memory constrained Embedded Neural Networks Accelerators
HEADS: Head-Wise Efficient and Adaptive Sparsification for Transformer-Based Models
Robotic Computing on FPGAs: Current Progress, Research Challenges, and Opportunities
TRIO: a Novel 10T Ternary SRAM Cell for Area-Efficient In-memory Computing of Ternary Neural Networks
An SoC Integration Ready VLIW-Driven CNN Accelerator with High Utilization and Scalability
Integrated System-on-Module for Design-Space Exploration of Spiking Neural Networks
An Integrated CPU-GPU Frequency Scaling Governor Based on Deep Recurrent Q-Network for Partially Observable Rendering Applications
Power-Efficient Double-Cyclic Low-Precision Training for Convolutional Neural Networks
MemQuant: Towards Memory-aware Post-Training Quantization for Multimodal Transformers
2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2020, Genova, Italy, August 31 - September 2, 2020
Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture
A Real-Time Sparsity-Aware 3D-CNN Processor for Mobile Hand Gesture Recognition
Multiple-Precision Floating-Point Dot Product Unit for Efficient Convolution Computation
MARSv2: Multicore and Programmable Reconstruction Architecture SRAM CIM-Based Accelerator with Lightweight Network
HLC: A Hardware-friendly Quantization and Cache-based Accelerator for Transformer
An Edge-Optimized Incremental Learning Algorithm For Audio Classification
Configurable Multi-Precision Floating-Point Multiplier Architecture Design for Computation in Deep Learning
Early-Exit with Class Exclusion for Efficient Inference of Neural Networks
Neuromorphic Event-based Line Detection on SpiNNaker
Novel Sleep Apnea Detection Based on UWB Artificial Intelligence Mattress
A Novel Number Representation and Its Hardware Support for Accurate Low-Bit Quantization on Large Recommender Systems
Contrast Agent Removal for Brain CT Angiography Using Switchable CycleGAN with AdaIN and Histogram Equalization
SLIM-Net: Rethinking how neural networks use systolic arrays
The 2020 Low-Power Computer Vision Challenge
Fault-Tolerant-Driven Clustering for Large Scale Neuromorphic Computing Systems
Live Demonstration: Video-to-Spike Conversion Using a Real-Time Retina Cell Network Simulator
An Energy-Efficient Accelerator with Relative- Indexing Memory for Sparse Compressed Convolutional Neural Network
Explore Activation Sparsity in Recurrent LLMs for Energy-Efficient Neuromorphic Computing
Machine Learning using Logarithmic Arithmetic with Preconditioned Input to Mitchell's Method
T-EAP: Trainable Energy-Aware Pruning for NVM-based Computing-in-Memory Architecture
Memory Efficient Training using Lookup-Table-based Quantization for Neural Network
CNNP-v2: An Energy Efficient Memory-Centric Convolutional Neural Network Processor Architecture
Effect of ReRAM Neuromorphic Circuit Array Variation and Fault on Inference Accuracy
Complexity Reduction on HEVC Intra Mode Decision with modified LeNet-5
An Architecture of Sparse Length Sum Accelerator in AxDIMM
LOMA: Fast Auto-Scheduling on DNN Accelerators through Loop-Order-based Memory Allocation
Fast event-driven incremental learning of hand symbols
Computer-Aided-Prediction of Body Constitution with Efficient Cock-Tail Learning
Function-Safe Vehicular AI Processor with Nano Core-In-Memory Architecture
Neuromorphic Implementation of Spiking Relational Neural Network for Motor Control
Tradeoff between Parallel Efficiency and Coding Efficiency of HEVC: A Load Balancing Solution with Convolutional Neural Networks
Non-uniform Memory Partitioning For Low-Power Spiking Neural Networks
Towards Intelligent Noninvasive Closed-loop Neuromodulation Systems
An AI AUV Enabling Vision-based Diver-following and Obstacle Avoidance with 3D-modeling Dataset
A Novel DNN Accelerator for Light-weight Neural Networks: Concept and Design
An Ultra-Low Latency Multicast Router for Large-Scale Multi-Chip Neuromorphic Processing
Weighted Decoupling: An Effective Image Resizing Method for Binarized Neural Network
Adapting Spatial Transformer Networks Across Diverse Hardware Platforms: A Comprehensive Implementation Study
Self-Resetting Magnetic Tunnel Junction Neuron-based Spiking Neural Networks
Range Encoding: A Low-Power Spiking Neural Network Encoding Scheme for ECG Classification
Auditory Anomaly Detection using Recurrent Spiking Neural Networks
The Ouroboros of Memristors: Neural Networks Facilitating Memristor Programming
Adaptive Image Downscaling for Rate-Accuracy-Latency Optimization of Task-Target Image Compression
Hardware Feasibility Analysis of Spatial Propagation Algorithms
A Framework for Design and Implementation of Adaptive Digital Predistortion Systems
RISCV-FNT: A Fast FNT-based RISC-V Processor for CNN Acceleration
Neuromorphic networks on the SpiNNaker platform
Hardware-Aware Optimization of Large Language Models for Enhanced Throughput on Arm CPUs
Stain-free Holographic Detection of Circulating Tumor Cells Using A Deep Feature Fusion Neural Network
A Novel Transpose 2T-DRAM based Computing-in-Memory Architecture for On-chip DNN Training and Inference
A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation
A Demonstration Platform for Large-Scaled Point Cloud Network Based on 28nm 2D/3D Unified Sparse Convolution Accelerator
Self-Aware Anomaly-Detection for Epilepsy Monitoring on Low-Power Wearable Electrocardiographic Devices
Codeword Decomposition and Recoding Based Lossless Model Compression Algorithm and Its VLSI Decompressor Design
Tiny TCN model for Gesture Recognition With Multi-point Low power ToF-Sensors
Multi-stage Attention Convolutional Neural Networks for HEVC In-Loop Filtering
QoS-Nets: Adaptive Approximate Neural Networks
AI-Based Edge-Intelligent Hypoglycemia Prediction System Using Alternate Learning and Inference Method for Blood Glucose Level Data with Low-periodicity
Analyzing the Energy-Latency-Area-Accuracy Trade-off Across Contemporary Neural Networks
Elastic Neural Networks for Classification
UMS-Net: A Multi-Scale Difference Network for Cuffless Blood Pressure Estimation
Quantized ID-CNN for a Low-power PDM-to-PCM Conversion in TinyML KWS Applications
PF-Training: Parameter Freezing for Efficient On-Device Training of CNN-based Object Detectors in Low-Resource Environments
An 176.3 GOPs Object Detection CNN Accelerator Emulated in a 28nm CMOS Technology
Read-disturb Detection Methodology for RRAM-based Computation-in-Memory Architecture
Hand Gesture Recognition Using IR-UWB Radar with Spiking Neural Networks