yusuke1997/dblp-id-title huggingface dataset:
Quantum mechanical effects on the threshold voltage of the evenly doped surrounding-gate MOSFETs
Graphene Top-gated Mos2 Phototransistors
A power-constrained contrast enhancement algorithm for AMOLED display using histogram segmentation
A General-Purpose Compiler Design for Instruction-Based AI Accelerator Implementation
An Efficient Scheduling Algorithm for Stream Computing
Analysis and architecture design of aggregation in BM3D
Improving DFA on AES using all-fault ciphertexts
Automatic compilation flow for a coarse-grained reconfigurable processor
CMOS-Compatible Time-of-Flight 3D Imaging Sensors and Systems
A Common Architecture for Digital Process of Ultrasonic Imaging System after AFE
Implementation of an energy-efficient digital baseband controller compatible with EPC Class-1 Gen-2 standard
E-mode p-FET-bridge HEMT: Toward high VTH, low reverse-conduction loss and enhanced stability
Comparisons of Photodiodes Based on Bulk-Silicon and Silicon-on-Insulator Substrates
An automated design flow for image processing filter in embedded systems
System architecture of a smart binaural hearing aid using a mobile computing platform
A 58-dB SNDR 1.32-mW chopper-stabilized analog front-end for graphene hall element detecting application
Non-linear function evaluation reusing matrix-vector multipliers
PSR-enhanced low-dropout regulator using feedforward supply noise rejection technique
A 256MHz Analog Baseband Chain with tunable Bandwidth and Gain for UWB Receivers
A New Sparsity Preserving Model Order Reduction Algorithm for Multi-terminal RC Networks
A 115-325MHz Wideband Analog Baseband with 0.5dB-Step Variable Gain Amplifier and Six-order Reconfigurable Gm-C Lowpass Filter
A novel low-cost FPGA-based real-time object tracking system
An FPGA based Parallel Implementation for Point Cloud Neural Network
A 14b 1GS/s DAC with SFDR > 80 dBc across the whole nyquist band by mixed total 3-dimesional sort-and-combine and dynamic element matching
A 10Gb/s analog equalizer in 0.18um CMOS
Radiation Hardened Design of Pipeline and Register File in Processor
A wideband CMOS variable-gain low noise amplifier with novel attenuator
A Dynamic Codec with Adaptive Quantization for Convolution Neural Network
Improvement and parallel implementation of canny edge detection algorithm based on GPU
Design of a Data Transmission Control Unit in a Multi-core DSP System
A new Schmitt trigger with adjustable hysteresis using floating-gate MOS threshold inverter
A 400mV supply voltage self-start clock generator for energy harvest system
Dual band power amplifier for handset application
Standard cell design of a low-leakage flip-flop with gate-length biasing
DTCO through design space exploration by the virtual FAB range pattern matching flow
Photoelectrochemically recessed AlGaN/GaN monolithic inverter incorporating LiNbO3 ferroelectric film
Hardware Implementation of Chromatic Dispersion Compensation in Finite Fields
Residual stress study of thin films deposited by atomic layer deposition
A turbo decoder implementation for LTE downlink mapped on a multi-core processor platform
Uniform belief propagation processor for massive MIMO detection and GF(2 n ) LDPC decoding
A digitally calibrated low-power ring oscillator
CMOS compatible MEMs process for post interconnect single chip integration application
A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation
A fuel injection control SoC for Diesel Engine Management System
Design and implementation of Serial ATA pbysical layer on FPGA
A 6-bit Active Phase Shifter with Quadrature Outputs
Pseudo differential DQS receiver for eliminating channel Hi-z noise
LVDS transmitter with optimized high power-efficiency 8: 1 MUX
CPIPQ: A common platform for silicon IP qualification
A 6-bit 700-MS/s single-channel SAR ADC with low kickback noise comparator in 40-nm CMOS
A 14-bit 2-GS/s DAC with SFDR>70dB up to 1-GHz in 65-nm CMOS
Mutual Error Compensation based Area and Power efficient Approximate Multiplier
Digital calibration techniques for interstage gain nonlinearity in pipelined ADCs
A low-noise WCDMA transmitter with 25%-duty-cycle LO generator in 65nm CMOS
Design and Optimization of Ternary Inverter using Face Tunnel Field-Effect Transistor
Full-custom Design of Improved Carry Adder Circuit for CLBs
A High Precision Capacitive Isolation Amplifier for Current Sensing Applications
A Low Power 8-bit 2b/Cycle SAR ADC with Multiple Calibration Techniques
A fully differential high efficient ASK demodulator for biomedical implantable application
A 23-nA Quiescent Current Output-Capacitorless LDO Regulator for IoT Devices
Energy efficient ADC design with low voltage operation
Integrated Homodyne Receiver Chip Design with Dual-Band Antenna
ASIC implementation of an OFDM baseband transceiver for HINOC
Design and application of reusable SoC verification platform
Ultra-low noise and high PSR LDO design
A 65nm 10MHz single-inductor dual-output switching buck converter with time-multiplexing control
A wide-division-ratio 100MHz-to-5GHz multi-modulus divider chain for wide-band PLL
A High-Precision Delta Sigma ADC with Chopper in BMS
Low noise design of 32-channel snapshot X-ray readout IC
Pixel Design of Ultra-high Speed CMOS Image Sensor
A Heterogeneous HEVC Video Encoder System Based on Two-Level CPU-FPGA Computing Architecture
A new fast median filtering algorithm based on FPGA
Design and implementation of a MAC protocol for a wearable monitoring system on human body
A 1.2 V 70 mA low drop-out voltage regulator in 0.13 µm CMOS process
Parallel nonvolatile programming of power-up states of SRAM cells
Design of digital control unit for implantable stimulator chip
Low-Complexity Belief-selective Message Passing (BsMP) Detector for SCMA Systems
An optimized topology reconfiguration bidirectional searching fault-tolerant algorithm for REmesh network-on-chip
Employing the mixed FBB/RBB in the design of FinFET logic gates
Performance evaluation and influence of device parameters on threshold voltage of dual-material strained gate-all-around MOSFET
An improved voltage bandgap reference with high-order curvature compensation
A CMOS Time-of-Flight Image Sensor with High Dynamic Range Digital Pixel
A Low-Power Single-Slope based 14-bit Column-Level ADC for 384×288 Uncooled Infrared Imager
A reference-less all-digital burst-mode CDR with embedded TDC
A new device architecture based on two dimensional van der Waals heterostructures
Steeper Subthreshold Swing Attained in Ge-Source Inductive Tunneling FET via Epitaxial Tunnel Layer for Suppressed Point Tunneling
Multi-technology simulation with mixed design environments
Study on the Performance of Flexible Curved Inverted-F Antenna under Compound Deformation Condition
A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical
A 90 nm 16 Mb embedded phase-change memory macro with write current smoothing and enhanced write bandwidth
Ultra-low power consumption Spintronics Devices
A 2.4GHz low noise high linearity RF front-end design
A low-power low-noise amplifier for EEG/ECG signal recording applications
A model for energy quantization of single-electron transistor below 10nm
Adaptive Convergence Method of Notch Frequency in Noise Spread Spectrum for Pulse Coding Switching DC-DC Converter
A 20Mbps 5.8mw QPSK transmitter based on injection locking and Class-E PA for wireless biomedical applications
Architecture and design automation for application-specific processors
Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applications
A 36-40 GHz VCO with bonding inductors for millimeter wave 5G Communication
Circuit Design Challenges of ADC for the Application in Multiple Physiological Parameters Detection System
Passiveless Digitally Controlled Oscillator With Embedded PVT Detector Using 40-nm CMOS
Color image enhancement using power-constraint histogram equalization for AMOLED
A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOS
On virtual prototyping of embedded system-on-chips
Machine Learning based SET Propagation Prediction for Large Scale Integrated Circuits
Implementation of high performance hardware architecture of face recognition algorithm based on local binary pattern on FPGA
A novel high-accuracy clock stabilizer with 50% duty cycle
Design of a Low Temperature Drift High Power Supply Rejection Bandgap Reference Circuit
A dynamic reprogramming scheme to enhance the reliability of RRAM
A low power consumption and higher performance DDR5 receiver based on a direct feedback DFE and dedicated reference voltage for 1 st TAP DFE
Improved BEOL Design Rules With 45-Degree Local Interconnection
Timing and resource constrained leakage power aware scheduling in high-level synthesis
A design of subthreshold SRAM cell based on RSCE and RNCE
ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs
A novel architecture of local memory for programmable SIMD vision chip
A high PSR SOI current-mode bandgap reference
Design of resistant DPA three-valued counter based on SABL
High Parallel VLSI Architecture Design of BPC in JPEG2000
Numerical Characterization of a 5-Layer (Pt/Ta/TaO/AlO/W) RRAM Device
All-Inorganic Two-Dimensional Ruddlesden-Popper Perovskite Cs2PbI2Cl2 Nanosheet Films for Self-Powered, Visible-Blind UV Photodetectors
An Accurate Area Model for FPGA Circuits at Advanced Technologies
High-Resolution Low-Sampling-Rate Δ∑ ADC Linearity Short-Time Testing Algorithm
A lowpass/bandpass reconfigurable continuous-time ΔΣ ADC for software-defined radio
Implementation of an embedded dual-core processor for portable medical electronics applications
A layer-based structured design of CNN on FPGA
A 14-bit 2-GS/s DAC with a programmable interpolation filter
VCCS controlled LDO with small on-chip capacitor
A new full current mode sense amplifier with compensation circuit
CMOS charge pump with separated charge sharing for improved boosting ratio and relaxed timing restriction
A Fast Reduction Method for Path Process Variations Without Time-Consuming Training
Efficient early termination schemes for belief-propagation decoding of polar codes
Design of Current-Assisted Photonic Demodulator (CAPD) for Time-of-Flight CMOS Image Sensor
An on-chip signal conditioning delta-sigma ADC for micro-mechanical gyroscope applications
The timing control design of 65nm block RAM in FPGA
A low-power soft error tolerant latch scheme
The study of parameters variation of nMOSFET affected by the HCI
DRFNet: A lightweight and high accuracy network for resource-limited implementation
Recent progress in GaN devices for power and integrated circuit
Hardware Implementation of Convolutional Neural Network for Face Feature Extraction
A novel architecture scheme with adaptive pipeline coupling technique for DSP processor design
A Time Constant Estimation Method for Block RC Circuits with Application to Power Grid Analysis
RF design and technology supporting Active Safety in automotive applications
A Digital Clock and Data Recovery Architecture with Precise Voting for Multi-Gigabit/s Links
Design of a closed-loop, bi-directional brain-machine-interface integrated on-chip spike sorting
A 60 GHz Broadband Wearable Antenna for Body-to-Body Communications
A load-transient-enhanced output-capacitor-free low-dropout regulator based on an ultra-fast push-pull amplifier
A FPGA real-time stereo vision system with luminance control and projected pattern
OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
Optimization of the amplifier's input-referred noise for high resolution comparators
Power optimization with Reinforcement Learning in Logic Synthesis
Class-AB CMOS buffer with floating class-AB control
Study of 64-bit booth asynchronous multiplier based on FPGA
Complexity-Reduced Joint Calibration for Nonlinearity and I/Q Imbalance in Direct-Conversion Transmitters
Design of the admittance detecting circuit for silicon waveguides using the capacitor-integration method
Analysis inductively coupling wireless connection in 3D package
AProgrammable IP Core for LDPC Decoder Based onASIP
A novel power optimization mechanism for pipelined ADCs
A Calibration Technique for Two-Step Single-Slope Analog-to-Digital Converter
Small-sized and noise-reducing power analyzer design for low-power IoT devices
Variation Analysis of Interconnect Capacitance and Process Corner in Advanced CMOS Process with Double Patterning Technology
A 0.18µm CMOS 2.5Gbps pre-amplifier with AGC
An Always-on Ultra-Low Power Speaker Verification Accelerator based on Binary Weighted Neural Network with System Co-optimization
An Integrated System of Blood Pressure and Electrocardiograph Recordings for Smart Home Healthcare Network
Interconnection allocation between functional units and registers in High-Level Synthesis
IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, China, October 28-31, 2013
Scheduling Algorithm Based on System of Difference Constraints Using Network Flow
An Effective Detailed Routing Algorithm Considering Advanced VLSI Technologies
Quantitative performance and power analysis of LTE using high level synthesis
Challenges and future trends for embedded security in electric vehicular communications
A light-weight energy-efficient resilient circuit for variation tolerance
Reduced complexity implementation of quasi-cyclic LDPC decoders by parity-check matrix reordering
VLSI design of fuzzy-decision bit-flipping QC-LDPC decoder
A new splitting graph construction algorithm for SIAR router
A signal conditioner IC for inductive proximity sensors
Design of Smooth Mode Transition Buck-Boost Converter Based on Adaptive Offset Cancellation
A low power 1.0 GHz VCO in 65nm-CMOS LP-process
A novel vertical semi-floating gate transistor for high-density ultrafast memory
A novel linear power amplifier for 2.6GHz LTE applications
Analysis of Single Events Effects on Supply-Regulated LC-Tank Voltage-Controlled Oscillator
Ultra-low frequency P(VDF-TrFE) piezoelectric energy harvester on flexible substrate
A 1/2/4MHz multi-mode reconfigurable lowpass/complex bandpass CT ΣΔ modulator for short range wireless receiver
Optimal design on asynchronous system with gate-level pipelining
A peak power optimization scheduling algorithm for single cycle operations and multi-cycle operations
Highly-reliable integrated circuits for Gro
A Performance-driven Neural Network Compiler for Multi-core Computing-In-Memory Accelerator
Research of a reconfigurable coarse-grained cryptographic processing unit based on different operation similar structure
Optimization of Node-clustering-based DAG partition targeting NVDLA Architecture
Performance Error Evaluation of gem5 Simulator for ARM Server
High efficiency and low power multi-rate LDPC decoder design for CMMB
Ultra-low-voltage Low-power Self-adaptive Static Pulsed Latch
Integrated amorphous-Si TFT circuits for gate drivers on LCD panels
AHardware implementation of DES with combined countermeasure against DPA
A dual-mode analog baseband utilizing digital-assisted calibration for WCDMA/GSM receivers
A TSV repair method for clustered faults
A clock interpolation structure using DLL for clock distribution in ADC
Design of a UHF RFID tag baseband with the hummingbird cryptographic engine
Looking back and forward: The execution dilemma and the importance of innovation in the semiconductor industry
Gate oxide enhancement for whole chip ESD design between different power domains
A Comparator-Reused Dynamic-Amplifier for Noise-Shaping SAR ADC
Design of a reconfigurable network interface processor
A biomedical microfluidic mixer in MEMS application using inkjet
Distributed task migration for thermal hot spot reduction in many-core microprocessors
On-Chip Protection of Cryptographic ICs Against Physical Side Channel Attacks: Invited Paper
A Two-Stage Time-Division Multiplexing AFE with Input Impedance Boosting DDA for EEG Signal Acquisition
Power optimization based on dual-logic using And-Xor-Inverter Graph
OFDM synchronization implementation based on Chisel platform for 5G research
An Obfuscated Challenge Design for APUF to Resist Machine Learning Attacks
Analysis of Switching Characteristics of Wide SOA and High Reliability 100 V N-LDMOS Transistor with Dual RESURF and Grounded Field Plate Structure
An improved equivalent circuit model for antenna: Modeling and parameter extraction
Multi-channel 600V-level Driver for Piezoelectric-Electrohydrodynamic Hybrid Inkjet Printer
A low bit-width parameter representation method for hardware-oriented convolution neural networks
The next-generation brain machine interface system for neuroscience research and neuroprosthetics development
A Novel Tri-input Schottky Barrier FET Exhibiting Three-Input Series Switching Function
An Adaptive Equalization Algorithm for High Speed SerDes
A dual mode high efficiency buck DC-DC converter
Design of a dynamically reconfigurable arithmetic unit for matrix algorithms
LC-KO: A congestion-aware and area&timing-oriented placement method
Highly Reliable Physical Unclonable Function Based on ZnO-SnO2 Gas Sensor
Directional coupler design in 3G/LTE Power Amplifier Module (invited paper)
A Low Complexity DDS Based On Optimized CORDIC Algorithm
Automatic Hardware Design Tool Based on Reusing Transformation
A universal approach for signal dependent circuit reliability simulation
A 22-33 GHz Wideband CMOS LNA Using Low-k Non-inverting MCCRs for 5G mmW Communication Applications
Tutorial sessions: Electrostatic discharge protection of consumer electronics: Challenges and solutions
Circuit-Level Soft Error Rate Evaluation Approach Considering Single-Event Multiple Transient
A high throughput FPGA embedded DSP architecture design
A sixth-order Chebyshev low-pass filter for single-chip UHF RFID reader
Flat Pass-Band Method with Two RC Band-Stop Filters for 4-Stage Passive RC Polyphase Filter in Low-IF Receiver Systems
Co-design of ESD protection and LNA in RFIC
A fully pipelined hardware architecture for convolutional neural network with low memory usage and DRAM bandwidth
Effect of field implantation on off- and on-state characteristics for thin layer SOI field P-channel LDMOS
A novel symbol synchronization algorithm and low-complexity circuits design for zero-IF GFSK demodulator
Design of a high parallelism high throughput HSPA+ Turbo decoder
RRAM-based Analog-Weight Spiking Neural Network Accelerator with in-situ Learning for IoT Applications
EG-HRNet: An Efficient High-Resolution Network Using Ghost-Modules for Human Pose Estimation
A countermeasure for power analysis to scalar multiplication of ECC hardware
Dynamic characteristics and related trapping effects of GaN-based Fin-MISHEMTs
Power optimization on MUX mapped circuits
Towards an LC passive wireless sensor platform
Fast two-dimensional finite element analysis for power network DC integrity checks of PCBs
An Analog Assisted Dual Loop Hybrid LDO Based on Adaptive Clock
An overview of soft-switching technique for flyback converters
Debugging methodology and timing analysis in CDC solution
A nonlinear weighted PID controlled 12V to 1V DC-DC converter with transient suppression
A quenching-and-reset circuit with programmable hold-off time for single photon avalanche diodes in 0.18μm CMOS
A 28nm 15.09nJ/inference Neuromorphic Processor with SRAM-Based Charge Domain in-Memory-Computing
Ultra low voltage, wide tuning range voltage controlled ring oscillator
A reference spur estimation method for integer-N PLLs
Improved monitoring-path selection algorithm for suspicious timing error prediction based timing speculation
PS-BloTAM: Pre-sampling based architecture-level temperature analysis methodology
High-Speed ASIC Implementation of Paillier Cryptosystem with Homomorphism
A hybrid router combining circuit switching and packet switching with virtual channels for on-chip networks
An equalization system for 2 series-connected Li-ion batteries
Full-digital high throughput design of adaptive decision feedback equalizers using coefficient-lookahead
A novel SCR-LDMOS for high voltage ESD protection
A CMOS hysteresis undervoltage lockout with current source inverter structure
Tensor-network-based predistorter design for multiple-input multiple-output nonlinear systems
Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor
A 4th-order N-path filter in 40nm CMOS with tunable Gm-C stage and reduced center-frequency offset
CMOS 0.35μm implementation of time-domain measurement of resonator's quality factor
Efficient Search Path Reduction for NB-LDPC Codes with T-EMS Algorithm
Advanced germanium channel transistors (invited)
Ternary Multiply-Accumulate Circuit Based on Domino Structure
A low power potentiostat for implantable glucose sensor tag
Evaluation of deflection routing on various NoC topologies
Deep Analysis of the SSN at LPDDR5 IO Interface
Research on Two-dimensional MXenes Based Synaptic Devices for the Future In-memory Computing
A method to estimate cross-section of circuits at RTL levels
A 20 μW dual-channel analog front-end in 65nm CMOS for portable ECG monitoring system
Automatic Timing-Driven Top-Level Hardware Design for Digital Signal Processing
Ag dendrite formed on the Cu pyramids as SERS substrate
Modeling and design of the LDMOSFET for RF power amplifier applications
Adaptive Low-Rank Tensor Approximation for SRAM Yield Analysis using Bootstrap Resampling
Toward 5 G: An integrated CMOS wide band arbitrary waveform generator for carrier aggregation
Efficient Photometric Alignment for Around View Monitor System
Design of a voltage-tunable pre-emphasis circuit utilizing a pseudo-differential cascode architecture
Bi2O2Se/P3HT Heterotransistors for Broadband Photodetections with High Rhotoresponsivities of 10 6 A/W
High-Performance BLS12-381 Pairing Engine on FPGA
A pseudo MMSE linear equalizer for 60GHz single carrier baseband receiver
An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP
Digital quadrature IF modulator using single-bit DACs
Periodic Analysis of Adaptive LMS Filter in TIADC
Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors
Low-resistance wide-voltage-range analog switch for implantable neural stimulators
Research of segmented 8bit voltage-mode R-2R ladder DAC
Transmitter IC Enabling Magnetic Field Shaping for High-Efficiency Wireless Charging of Multiple Receivers
An energy efficiency task scheduling algorithm for streaming applications on multiprocessor SoC
Benchmarking Heterogeneous Integration with 2.5D/3D Interconnect Modeling
A High Precision CMOS Temperature Detector with Curvature Calibration Technique
Sparse basis pursuit on automatic nonlinear circuit modeling
Linearity Analysis for Charge Domain In-memory Computing
A 60GHz power amplifier using 90-nm RF-CMOS technology
Optimization of operational amplifier settling time by adjusting secondary poles based on gm/ID design
Ultra-low Power Access Strategy for Process-Voltage-Temperature Aware STT-MRAM
Transition metal dichalcogenides - A new material class for semiconductor electronics?
Design of drain-gate transformer feedback VCO with body-biasing
Design trends in smart gate driver ICs for power MOSFETs and IGBTs
Dual-Loop-Controlled AC-Coupling 100MHz Bandwidth Envelope Tracking Modulator for 5G RF Power Amplifier
Flat passband gain design algorithm for 2nd-order RC polyphase filter
A 0.18 μ m high-voltage area efficient integrated gate driver for piston engine fuel injection control SoC
A low-kickback preamplifier with offset cancellation for pipelined folding A/D Converter
Comparator circuits automation by combination of distributed genetic algorithm and HSPICE optimization
A Low-Complexity Timing Skew Mismatch Calibration Method for Time-Interleaved ADCs
Full Software Radio transceivers
A design of high performance full adder with memristors
Event-driven analog-to-digital converter for ultra low power wearable wireless biomedical sensors
A high-speed front-end circuit used in a 16bit 250MSPS pipelined ADC
Graphite planar resistive switching memory and its application in pattern recognition
A high-precision voltage regulator with dynamic load technique and overcurrent protection