yusuke1997/dblp-id-title huggingface dataset:
Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning *
Reconfigurable high performance architectures: How much are they ready for safety-critical applications?
A SystemC-AMS Development Framework for High Power IC Test-Hardware
I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems
18th IEEE European Test Symposium, ETS 2013, Avignon, France, May 27-30, 2013
A new efficiency criterion for security oriented error correcting codes
Scan Attacks and Countermeasures in Presence of Scan Response Compactors
Online Univariate Outlier Detection in Final Test: A Robust Rolling Horizon Approach
Error Detection and Correction Codes for Safe In-Memory Computations
A method for trading off test time, area and fault coverage in datapath BIST synthesis
Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics
Functional fault coverage: the chamber of secrets or an accurate estimation of gate-level coverage?
Testing of small delay faults in a clock network
Utilizing circuit structure for scan chain diagnosis
Prediction of Thermally Accelerated Aging Process at 28nm
Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs
Coupling-based resistive-open defects in TAS-MRAM architectures
Testing in the year 2024 - big changes are coming
A Dynamic Greedy Test Scheduler for Optimizing Probe Motion in In-Circuit Testers
An effective hybrid fault-tolerant architecture for pipelined cores
Confidence Driven Compact Testing of Compute-in-Memory Based Language Models
Hardware-Independent ATE Software for SLT
Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism
On the mitigation of single event transients on flash-based FPGAs
On-chip test comparison for protecting confidential data in secure ICs
A 3DIC interconnect interface test and repair scheme based on Hybrid IEEE1838 Die Wrapper Register and BIST circuit
Jitter Decomposition in High-Speed Communication Systems
Test Sequence-Optimized BIST for Automotive Applications
High-coverage analog IP block test generation methodology using low-cost signal generation and output response analysis
Improved DFT for Testing Power Switches
ReiNN: Efficient error resilience in artificial neural networks using encoded consistency checks
Structural In-Field Diagnosis for Random Logic Circuits
Coverage-driven mixed-signal verification of smart power ICs in a UVM environment
Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor
Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling
Hardening Bus-Encoders with Power-Aware Single Error Correcting Codes
Research on Path Delay with BTI Recovery Effect
Power-aware voltage tuning for STT-MRAM reliability
A Plug and Play Digital ABIST Controller for Analog Sensors in Secure Devices
A transient error tolerant self-timed asynchronous architecture
A phase locking test solution for MEMS devices
Latency Analysis for Sequential Circuits
Towards on-line testing of MEMS using electro-thermal excitation
FATE: a Functional ATPG to Traverse Unstabilized EFSMs
Testing Functional Interfaces And Complex PADs Within Multi-Die Packages With IEEE P3405
ESD-PCM: Constructing Reliable Super Dense Phase Change Memory Under Write Disturbance
High Throughput and Energy Efficient SHA-2 ASIC Design for Continuous Integrity Checking Applications
An Integrated Framework for Aging Analysis Based on an Age-Aware Cell Library
A Software-Based Self-Test methodology for on-line testing of data TLBs
Diagnostic system based on support-vector machines for board-level functional diagnosis
Contact-less near-field measurement of RF phased array antenna mismatches
A novel threshold voltage defined switch for circuit camouflaging
Confidence Estimation in Non-RF to RF Correlation-Based Specification Test Compaction
Hierarchical Code Correction and Reliability Management in Embedded nor Flash Memories
A Reliable Architecture for the Advanced Encryption Standard
WLAN Rx PER Test Implementation in ATE
A software-based self-test methodology for system peripherals
Physical Unclonable Functions (PUFs): Foundations, Evaluation, and Testing for Secure Hardware Systems
Embedded Tutorial: IC Test Cost Benchmarking
A new built-in IDDQ testing method using programmable BICS
RRAM Crossbar-Based Fault-Tolerant Binary Neural Networks (BNNs)
Impact of Atmospheric and Space Radiation on Sensitive Electronic Devices
IEEE European Test Symposium, ETS 2025, Tallinn, Estonia, May 26-30, 2025
A Two Phase Approach for Minimal Diagnostic Test Set Generation
VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers
FPGA Design Deobfuscation by Iterative LUT Modifications at Bitstream Level
Design of an automatic testing for FPGAs
Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits
Physical-aware Interconnect Testing and Repairing of Chiplets
A novel test generation and application flow for functional access to IEEE 1687 instruments
Magical thinking applied to test engineering reality (and vice versa)
Analysis of electrostatic coupling in monolithic 3D integrated circuits and its impact on delay testing
A low-cost built-in self-test scheme for an array of memories
A self-reconfiguring IEEE 1687 network for fault monitoring
Fast and Accurate DPPM Computation Using Model Based Filtering
Evaluating Security of New Locking SIB-based Architectures
Parity-based output compaction for core-based SOCs [logic testing]
Deterministic Logic BIST for Transition Fault Testing
Power constrained preemptive TAM scheduling
Stuck-open fault diagnosis with stuck-at model
Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning
Criticality Analysis of Ring Oscillators in FPGA Bitstreams *
7th European Test Workshop, ETW 2002, Corfu, Greece, May 26-29, 2002
Power Analysis Attack Against post-SAT Logic Locking schemes
Analyzing the test generation problem for an application-oriented test of FPGAs
Improving the dependability of AMR sensors used in automotive applications
Automatic Functional Stress Pattern Generation for SoC Reliability Characterization
Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring
Counteracting Rowhammer by Data Alternation
Diagnosis of full open defects in interconnect lines with fan-out
Optimization for timing-speculated circuits by redundancy addition and removal
Combining symbolic and genetic techniques for efficient sequential circuit test generation
On resistive open defect detection in DRAMs: The charge accumulation effect
PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques
Defect Characterization and Test Generation for Spintronic-based Compute-In-Memory
Test and Repair Improvements for UCIe
A packet switching communication-based test access mechanism for system chips
RTL-based functional test generation for high defects coverage in digital SOCs
Pulsed Electromagnetic Fault Injection Attack on Ring Oscillator-based PUFs in FPGAs
A Flexible and Scaleable Methodology for Testing High Speed Source Synchronous Interfaces on ATE with Multiple Fixed Phase Capture and Compare
Optimized diagnostic strategy for embedded memories of Automotive Systems-on-Chip
Fault tolerant FPGA processor based on runtime reconfigurable modules
Funding project DIANA - Integrated diagnostics for the analysis of electronic failures in vehicles
Sat-based speedpath debugging using waveforms
A Machine Learning-based Approach to Optimize Repair and Increase Yield of Embedded Flash Memories in Automotive Systems-on-Chip
Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs
Online detection and recovery of transient errors in front-end structures of microprocessors
IEEE European Test Symposium, ETS 2023, Venezia, Italy, May 22-26, 2023
On Generating Fault Diagnosis Patterns for Designs with X Sources
Assessing the Effectiveness of Software-Based Self-Test Programs for Static Cell-Aware Test
Silent Data Corruptions in Computing Systems: Early Predictions and Large-Scale Measurements
Current testing procedure for deep submicron devices
Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits
Computing detection probability of delay defects in signal line tsvs
X-Masking for In-System Deterministic Test
GPU-based timing-aware test generation for small delay defects
Built-in self-test of molecular electronics-based nanofabrics
TaintLock: Preventing IP Theft through Lightweight Dynamic Scan Encryption using Taint Bits *
A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology
Test generation for circuits with embedded memories using SMT
Path-oriented transition fault test generation considering operating conditions
Static and dynamic on-chip test response evaluation using a two-mode comparator
Algorithms for ADC Multi-site Test with Digital Input Stimulus
Innovation and Wealth Creation from Technology
ISO26262-compliant soft-error mitigation in register banks
Low power BIST by filtering non-detecting vectors
Test pattern selection to optimize delay test quality with a limited size of test set
Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation
5th European Test Workshop, ETW 2000, Cascais, Portugal, May 23-26, 2000
DOT: new deterministic defect-oriented ATPG tool
The influence of hysteresis voltage on single event transients in a 65nm CMOS high speed comparator
On Using Cell-Aware Methodology for SRAM Bit Cell Testing
Low power embedded DRAMs with high quality error correcting capabilities
M-S specification binning based on digitally coded indirect measurements
Feature Engineering for Recycled FPGA Detection Based on WID Variation Modeling
A Side-Channel Attack on a Hardware Implementation of CRYSTALS-Kyber
A Data-driven Approach for Fault Detection in the Alternator Unit of Automotive Systems
Learning-Based Cell-Aware Defect Diagnosis of Customer Returns
Automating the Generation of Functional Stress Inducing Stimuli for Burn-In Testing
4th European Test Workshop, ETW 1999, Constance, Germany, May 25-28, 1999
Hybrid Ring Generators for In-System Test Applications
Software-based repair for memories in tiny embedded systems
Tests for address decoder delay faults in RAMs due to inter-gate opens
Real-time self-learning for control law adaptation in nonlinear systems using encoded check states
Fault Sensitivity Analysis of Printed Bespoke Multilayer Perceptron Classifiers
Study of a delayed single-event effect in the Muller C-element
A Built-In Self-Test Method For MEMS Piezoresistive Sensor
Reducing the susceptibility of design-for-delay-testability structures to process- and application-induced variations
ATPG for timing-induced functional errors on trigger events in hardware-software systems
Test scheduling for modular SOCs in an abort-on-fail environment
Diagnose Multiple Stuck-at Scan Chain Faults
DEV-PIM: Dynamic Execution Validation with Processing-in-Memory
NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating
Automotive embedded software architecture in the multi-core age
STAHL: A Novel Scan-Test-Aware Hardened Latch Design
Tomographic Testing and Validation of Probabilistic Circuits
Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC
Wafer Level Reliability Screens
Adaptive multi-site testing for analog/mixed-signal circuits incorporating neighborhood information
PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community
A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager
Dependable testing of compactor MISR: an imperceptible problem?
Signal integrity loss in bus lines due to open shielding defects
Reducing test cost for mixed signal circuits "From TOETS to ELESIS"
Defect-oriented dynamic fault models for embedded-SRAMs
Test Adapted Shielding by a Multipurpose Crosstalk Avoidance Scheme
Exploring Algebraic Interpolants for Rectification of Finite Field Arithmetic Circuits with Gröbner Bases
Keynote 2 - Sustainability and the Outlook of Semiconductor Industry
Disturbance fault testing on various NAND flash memories
Failure mechanisms and test methods for the SRAM TVC write-assist technique
Bit-flip detection-driven selection of trace signals
FPGA Soft Error Recovery Mechanism with Small Hardware Overhead
Defect Filter for Alternate RF Test
Integrated circuits' characterization for non-normal data in semiconductor quality analysis
Analyzing resistive-open defects in SRAM core-cell under the effect of process variability
Hybrid 3D pre-bonding test framework design
Evaluation of concurrent error detection techniques on the Advanced Encryption Standard
Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing
A fault model for function and delay testing
The role of test protocols in testing embedded-core-based system ICs
A scalable BIST architecture for delay faults
Formal Resilience Metric Characterization in Complex Digital Systems
A distributed architecture to check global properties for post-silicon debug
Probabilistic sensitization analysis for variation-aware path delay fault test evaluation
A shared BIST optimization methodology for memory test
An efficient approach to SoC wrapper design, TAM configuration and test scheduling
PULP Fiction No More - Dependable PULP Systems for Space
On maximizing the coverage of catastrophic and parametric faults
Test Configurations for Diagnosing Faulty Links in NoC Switches
Modeling feedback bridging faults with non-zero resistance
Test-Fleet Optimization Using Machine Learning
An efficient test technique to prevent scan-based side-channel attacks
Automatic March tests generation for static and dynamic faults in SRAMs
Test planning and test resource optimization for droplet-based microfluidic systems
Power Aware Test
What Would Interactive Testing With 1687 Look Like?
On Integrating Lightweight Encryption in Reconfigurable Scan Networks
Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation
Test control for secure scan designs
MBIST-supported Trim Adjustment to Compensate Thermal Behavior of MRAM
Secure and efficient LBIST for feedback shift register-based cryptographic systems
Practices in High-Speed IO testing
Locking of biochemical assays for digital microfluidic biochips
Pin Electronics for Instrumentation and Automated Test Equipment: Challenges and Solutions
Mitigating read & write errors in STT-MRAM memories under DVS
Using Temperature as Observable of the Frequency Response of RF CMOS Amplifiers
On the impact of process variability and aging on the reliability of emerging memories (Embedded tutorial)
Extending fault-based testing to microelectromechanical systems
A new SoC test architecture with RF/wireless connectivity
Detection of Malicious FPGA Bitstreams using CNN-Based Learning
Testing of digital microfluidic biochips with arbitrary layouts
Boundary cost optimization for Alternate Test
Functional test generation for hard to detect stuck-at faults using RTL model checking
Harvesting Wasted Clock Cycles for Efficient Online Testing
Improving RO-PUF quality on FPGAs by incorporating design-dependent frequency biases
Mixed-signal BIST computation offloading using IEEE 1687
On Bypassing Blocking Bugs during Post-Silicon Validation
Evaluating the Prevalence of SFUs in the Reliability of GPUs
An FPGA-based ATE extension module for low-cost multi-GHz memory test
MBIST Support for Reliable eMRAM Sensing
Run Time Management of Faulty Data Caches
Automating test program generation in STIL - expectations and experiences using IEEE 1450 [standard test interface language]
Concurrent online BIST for sequential circuits exploiting input reduction and output space compaction
Analog Test Bus Infrastructure for RF/AMS Modules in Core-Based Design
Fault collapsing for flash memory disturb faults
PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates
A practical evaluation of I DDQ test strategies for deep submicron production test application. Experiences and targets from the field
Efficient diagnosis technique for aging defects on automotive semiconductor chips
An error-detection and self-repairing method for dynamically and partially reconfigurable systems
AVF Analysis Acceleration via Hierarchical Fault Pruning
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes
New drain current model for nano-meter MOS transistors on-chip threshold voltage test
Parallel-Check Trimming Test Approach for Selecting the Reference Resistance of STT-MRAMs
Exact stuck-at fault classification in presence of unknowns
Production test challenges for highly integrated mobile phone SOCs - A case study
Dynamic test data transformations for average and peak power reductions
RF ATE equipment benefit from advanced network analyzer technology
Graph Theory Approach for Multi-site ATE Board Parameter Extraction
Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization
Scan Design Using Unsupervised Machine Learning to Reduce Functional Timing and Area Impact
Detection of Stealthy Bitstreams in Cloud FPGAs using Graph Convolutional Networks
Post-Manufacture Criticality-Aware Gain Tuning of Timing Encoded Spiking Neural Networks for Yield Recovery
A scheduling method for hierarchical testability based on test environment generation results
TDMS Test Scheduler: An Integrated Framework for Test Scheduling of DVFS-based SoCs with Multiple Voltage Islands
Accumulator-based test-per-clock scheme for low-power on-chip application of test patterns
Multi Coefficient CPA on a Black Box Hardware Implementation of CRYSTALS-Kyber
Branch guided functional test generation at the RTL
Combining dynamic slicing and mutation operators for ESL correction
A generic and high-level model of large unreliable NoCs for fault tolerance and performance analysis
Convolutional Compactors with Variable Polynomials
Reliability and Security of AI Hardware
Cross-layer resilience
Bias Superposition - An On-Line Test Strategy for a MEMS Based Conductivity Sensor
Software development for an open architecture test system
Microfluidic very large-scale integration for biochips: Technology, testing and fault-tolerant design
Current testing: Dead or alive?
Group delay filter measurement using a chirp
Recycled IC detection through aging sensor
Convolutional Compaction-Based MRAM Fault Diagnosis
Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints
A two-layer SPICE model of the ATMEL TSTAC TM eFlash memory technology for defect injection and faulty behavior prediction
An efficient fault-tolerant valve-based microfluidic routing fabric for single-cell analysis
Efficient minimization of test frequencies for linear analog circuits
Synergistic Built-In ECC Repair (BIER) Technique for Enhancing Yield and Reliability of Flash Memory
Automated Graph-Based Fault Injection Into Virtual Prototypes for Robustness Evaluation
IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system
Attacking Memristor-Mapped Graph Neural Network by Inducing Slow-to-Write Errors
IEEE European Test Symposium, ETS 2020, Tallinn, Estonia, May 25-29, 2020
Novel Method to Measure Common Mode Transient Immunity of Isolators
Multiple fault diagnosis in crossbar nano-architectures
Algorithm-based fault tolerance for many-core architectures
Extraction of EVM from Transmitter System Parameters
Device-Aware Test for Emerging Memories: Enabling Your Test Program for DPPB Level
The impact of functional safety standards in the design and test of reliable and available integrated circuits
A mutual characterization based SAR ADC self-testing technique
Bridging the testing speed gap: design for delay testability
Doubling Test Cell Throughput by On-Loadboard Hardware- Implementation and Experience in a Production Environment
Impact of Reduced Precision in the Reliability of Deep Neural Networks for Object Detection
Arithmetic Circuit Correction by Adding Optimized Correctors Based on Groebner Basis Computation
Hierarchical Memory Diagnosis
21th IEEE European Test Symposium, ETS 2016, Amsterdam, Netherlands, May 23-27, 2016
Power Measurement and Spectral Test of ZigBee Transmitters from 1-bit Under-sampled Acquisition
On no-reference on-line error-tolerability testing for videos
Synergies Between Delay Test and Post-silicon Speed Path Validation: A Tutorial Introduction
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers
Volume diagnosis data mining
System-level test bench generation in a co-design framework
On the Evaluation of the PIPB Effect within SRAM-based FPGAs
Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm
A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST Architecture
The use of equivalent fault analysis to improve static D.C. fault diagnosis - a potentiometric DAC case study
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing
Testing of MEMS-based microsystems
Scan pattern retargeting and merging with reduced access time
BIST architecture to detect defects in tsvs during pre-bond testing
Test Encoding for Extreme Response Compaction
Component fault localization using switching current measurements
A soft-error tolerant TCAM using partial don't-care keys
A homogeneous framework for AMS languages instrumentation, abstraction and simulation
Adaptive Debug and Diagnosis without Fault Dictionaries
Validation, Verification, and Testing (VVT) of future RISC-V powered cloud infrastructures: the Vitamin-V Horizon Europe Project perspective
23rd IEEE European Test Symposium, ETS 2018, Bremen, Germany, May 28 - June 1, 2018
Automated Test Equipment Drift Characterization Based on Gauge Repeatability and Reproducibility
Risks for Signal Integrity in System in Package and Possible Remedies
QAMR: an Approximation-Based Fully Reliable TMR Alternative for Area Overhead Reduction
A compression-driven test access mechanism design approach
Evaluating the self-testing property of AES' finite field inversion units
A hybrid algorithm to conservatively check the robustness of circuits
A Concept of Provably Detected Defects for Analog Defect Simulation Campaign Improvement
Investigations for minimum invasion digital only built-in "ramp" based test techniques for charge pump PLL's
Intermittent Undefined State Fault in RRAMs
Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study
Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path
On estimation of NBTI-Induced delay degradation
On-chip signal level evaluation for mixed-signal ICs using digital window comparators
Delay fault testing and silicon debug using scan chains
Approximate computing design exploration through data lifetime metrics
Process and Runtime Variation Robustness for Spintronic-Based Neuromorphic Fabric
M-S test based on specification validation using octrees in the measure space
Generation of compact multi-cycle diagnostic test sets
A Survey and Tutorial on Security and Resilience of Quantum Computing
FINaL: Driving High-Level Fault Injection Campaigns with Natural Language
Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC Architecture
Invited talk: Self-aware wireless communication and signal processing systems: Real-time adaptation for error resilience, low power and performance
A robust metric for screening outliers from analogue product manufacturing tests responses
Data Background-Based Test Development for All Interconnect and Contact Defects in RRAMs
Power Aware Post-manufacture Tuning of Analog Nanocircuits
Diagnosis of multiple faults with highly compacted test responses
A 22n March Test for Realistic Static Linked Faults in SRAMs
High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors