yusuke1997/dblp-id-title huggingface dataset:
Applying MILS to multicore avionics systems
VectorPU: A Generic and Efficient Data-container and Component Model for Transparent Data Transfer on GPU-based Heterogeneous Systems
Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels
Compiler Techniques for Reducing Data Cache Miss Rate on a Multithreaded Architecture
Towards adaptive MILS System: Model- Based Design, Verification and Run-Time Adaptation: Slides
Speculatively vectorized bytecode
Towards Studying the Effect of Compiler Optimizations and Software Randomization on GPU Reliability
Collecting traces in dynamic binary translation based virtual prototyping platforms
Body Biasing Injection Attacks in Practice
Extended histories: improving regularity and performance in correlation prefetchers
On Boosting Energy-Efficiency of Heterogeneous Embedded Systems via Game Theory
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
Evaluation Tools for Multivariate Side-Channel Analysis
Low communication overhead dynamic mapping of multiple HEVC video stream decoding on NoCs
RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor
MIPS MT: A Multithreaded RISC Architecture for Embedded Real-Time Processing
Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays
Side-channel leakage aware instruction scheduling
Automatic DRAM Subsystem Configuration with irace
PathTracing: Raising the Level of Understanding of Processing Latency in Heterogeneous MPSoCs
Virtualization in HPC - An Enabler for Adaptive Co-Scheduling?
Improving QoS and Utilisation in modern multi-core servers with Dynamic Cache Partitioning
SRP: Symbiotic Resource Partitioning of the Memory Hierarchy in CMPs
The Impact of Precision Tuning on Embedded Systems Performance: A Case Study on Field-Oriented Control
A Model-based Approach to Certification of Adaptive MILS
Analysis of GPU Memory Allocation Characteristics
Efficient Memory Management for Modelica Simulations
Compilation of a Countermeasure Against Instruction-Skip Fault Attacks
GLOpenCL: OpenCL support on hardware- and software-managed cache multicores
Content-Dependent Security Policies in Avionics
Bringing minimal routing back to HPC through silicon photonics: a study of "flexfly" architectures with the structural simulation toolkit (SST)
Ease Standard Compliance by Technical Means via MILS
Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems
Virtual Registers: Reducing Register Pressure Without Enlarging the Register File
A Hardware Task Scheduler for Embedded Video Processing
Network-on-chip service guarantees on the kalray MPPA-256 bostan processor
Performance estimation of streaming applications for hierarchical MPSoCs
Security by Design: Introduction to MILS
A Platform Approach for Fusing Safety and Security on a Solid Foundation
Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering
ManyGUI: A Graphical Tool to Accelerate Many-core Debugging Through Communication, Memory, and Energy Profiling
Security-Informed Safety Case Approach to Analysing MILS Systems
A Reference Architecture for Integrating Safety and Security Applications on Railway Command and Control Systems
JADE: a Heterogeneous Multiprocessor System Simulation Platform Using Recorded and Statistical Application Models
Fast Bounds Checking Using Debug Register
SO(DA) 2 : End-to-end Generation of Specialized Reconfigurable Architectures (Invited Talk)
Proceedings of the First Workshop on Cryptography and Security in Computing Systems, CS2@HiPEAC 2014, Vienna, Austria, January 20, 2014
Reducing Exit Stub Memory Consumption in Code Caches
Fog Computing as Enabler for the Industrial Internet of Things / Industrie 4.0: Slides
Larrabee: A Many-Core Intel Architecture for Visual Computing
Enabling high performance rack-scale optical switching through global synchronisation
Remote cache-timing attacks against AES
Spoofing Prevention via RF Power Profiling in Wireless Network-on-Chip
Micro-architectural simulation of embedded core heterogeneity with gem5 and McPAT
Keynote: Challenges on the Road to Exascale Computing
Integrated CPU Cache Power Management in Multiple Clock Domain Processors
NBTI-aware design of NoC buffers
Scalable and Dynamic Global Power Management for Multicore Chips
A highly robust distributed fault-tolerant routing algorithm for NoCs with localized rerouting
Optimal Power Efficient Photonic SWMR Buses
Enabling Run-Time Managed Distributed Mobile Computing
Co-Scheduling: Prospects and Challenges
Gyro: A Digital Spiking Neural Network Architecture for Multi-Sensory Data Analytics
HyperLoom: A Platform for Defining and Executing Scientific Pipelines in Distributed Environments
RAVEN: Reinforcement Learning for Generating Verifiable Run-Time Requirement Enforcers for MPSoCs
Embedded Multi-Core Code Generation with Cross-Layer Parallelization
TypeCastor: demystify dynamic typing of JavaScript applications
Switch allocator for bufferless network-on-chip routers
Radar Perception for Autonomous Unmanned Aerial Vehicles: a Survey
International Workshop on MILS: Architecture and Assurance for Secure Systems, MILS@HiPEAC 2015, Amsterdam, The Netherlands, January 20, 2015
HPC Application Cloudification: The StreamFlow Toolkit (Invited Paper)
A Novel Obstacle Detection and Avoidance Dataset for Drones
Using PEGs for Automatic Extraction of Memory Access Descriptions to Support Data-Parallel Pattern Recognition
High-Level Synthesis Developments in the Context of European Space Technology Research (Invited Talk)
Exploring Cross-fusion and Curriculum Learning for Multi-modal Human Detection on Drones
Overlapping-Horizon MPC: A Novel Approach to Computational Constraints in Real-Time Predictive Control
HiPART: High-Performance Technology for Advanced Real-Time Systems
Global misrouting policies in two-level hierarchical networks
A Co-design Approach for Hardware Optimizations in Multicore Architectures Using MCAPI
Memory-efficient on-card byte code verification for Java cards
Scaling Binarized Neural Networks on Reconfigurable Logic
Impact of Vectorization Over 16-bit Data-Types on GPUs
Model-based framework for networks-on-chip design space exploration
A Single (Unified) Shader GPU Microarchitecture for Embedded Systems
Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms
Trace-Based Data Layout Optimizations for Multi-core Processors
14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2023, Toulouse, France, January 17, 2023
RVC: a mechanism for time-analyzable real-time processors with faulty caches
Secure communications in wireless network-on-chips
iFDOR: dynamic rerouting on-chip
Evidence of an information leakage between logically independent blocks
Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems
Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2017, Stockholm, Sweden, January 25, 2017
Fourth Workshop on Next Generation Real-Time Embedded Systems, NG-RES 2023, Toulouse, France, January 18, 2023
Group-signature schemes on constrained devices: the gap between theory and practice
Zero-Copy, Minimal-Blackout Virtual Machine Migrations Using Disaggregated Shared Memory
Proceedings of the Joined Workshops COSH 2017 and VisorHPC 2017, COSH/VisorHPC@HiPEAC 2017, Stockholm, Sweden, January 24, 2017
Implementation of an UWB Impulse-Radio Acquisition and Despreading Algorithm on a Low Power ASIP
Analysing Cryptographically-Masked Information Flows in MILS-AADL Specifications
Deploying and monitoring hadoop MapReduce analytics on single-chip cloud computer
Automated empirical tuning of scientific codes for performance and power consumption
Energy Efficient And Low Latency Interconnection Network For Multicast Invalidates In Shared Memory Systems
Precision Tuning in Parallel Applications
An improved algorithm for slot selection in the Æthereal network-on-chip
Fast&Furious: A Tool for Detecting Covert Racing
Exploiting Performance Counters for Energy Efficient Co-Scheduling of Mixed Workloads on Multi-Core Platforms
A Practical Method for Quickly Evaluating Program Optimizations
Energy Minimization in DAG Scheduling on MPSoCs at Run-Time: Theory and Practice
Auto-Tuning OmpSs-OpenCL Kernels Across GPU Machines
Mocasin - Rapid Prototyping of Rapid Prototyping Tools: A Framework for Exploring New Approaches in Mapping Software to Heterogeneous Multi-cores
International Workshop on MILS: Architecture and Assurance for Secure Systems, MILS@DSN 2018, Luxembourg, June 25, 2018
Efficient Sampling Startup for Sampled Processor Simulation
Streaming Sparse Matrix Compression/Decompression
FlexTiles: self adaptive heterogeneous manycore based on flexible tiles (FP7 project)
Contention-Aware Scheduling Policies for Fairness and Throughput
Compilation Strategies for Reducing Code Size on a VLIW Processor with Variable Length Instructions
Computer Generation of Efficient Software Viterbi Decoders
Static Allocation of Basic Blocks Based on Runtime and Memory Requirements in Embedded Real-Time Systems with Hierarchical Memory Layout
Automated Precision Tuning in Activity Classification Systems: A Case Study
Automatically Tuning Sparse Matrix-Vector Multiplication for GPU Architectures
MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization
Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis
A Throughput-Driven Task Creation and Mapping for Network Processors
Criticality-driven Design Space Exploration for Mixed-Criticality Heterogeneous Parallel Embedded Systems
Accelerator-Driven Data Arrangement to Minimize Transformers Run-Time on Multi-Core Architectures
Differential Fault Attack on SIMECK
AutoPar-Clava: An Automatic Parallelization source-to-source tool for C code applications
Parallel H.264 Decoding on an Embedded Multicore Processor
Multi-level Hardware Prefetching Using Low Complexity Delta Correlating Prediction Tables with Partial Matching
Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments
Automatic ILP-based Firewall Insertion for Secure Application-Specific Networks-on-Chip
Droneport: From Concept To Simulation
An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems
Combining Locality Analysis with Online Proactive Job Co-scheduling in Chip Multiprocessors
Non-Interfering Composed Evaluation
rMPI: Message Passing on Multicore Processors with On-Chip Interconnect
Initial Formulation of Why Disallowing Same Program Co-Schedules Improves Performance
In Search for a Simple Secure Protocol for Safety-Critical High-Assurance Applications
Wavelength division multiplexed photonic layer on CMOS
Remote Store Programming
HMB: Scheduling PREM-Like Real-Time Tasks at High Memory Bandwidth (Invited Paper)
Customizing the Datapath and ISA of Soft VLIW Processors
Induction Variable Analysis with Delayed Abstractions
Bio-inspired monocular drone SLAM
Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems
Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator
Low-Latency Real-Time Applications on Heterogeneous MPSoCs
BifurKTM: Approximately Consistent Distributed Transactional Memory for GPUs
Classic and Adaptive AUTOSAR in MILS terms
Cost-aware function migration in heterogeneous systems
Arbitration of many thousand flows at 100G and beyond
Resource Aware GPU Scheduling in Kubernetes Infrastructure
Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation - Methods and Tools, RAPIDO@HiPEAC 2016, Prague, Czech Republic, January 18, 2016
Automatic OpenCL Code Generation from LLVM-IR using Polyhedral Optimization
EURO-MILS: Building and certifying modular secure systems
Analysis of Task Offloading for Accelerators
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches
High Speed CPU Simulation Using LTU Dynamic Binary Translation
Partitioning in Safety and Security: Mapping to MILS Core Partitioning Mechanisms
XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs
Disallowing Same-program Co-schedules to Improve Efficiency in Quad-core Servers
Garbage Collection Hints
History-Based Run-Time Requirement Enforcement of Non-Functional Properties on MPSoCs
A feature-rich NoC switch with cross-feature optimizations for the next generation of reliable and reconfigurable embedded systems
Execution Time Modeling for CNN Inference on Embedded GPUs
Designing an Efficient MPLS-Based Switch for FAT Tree Network-on-Chip Systems
Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors
LPA: A First Approach to the Loop Processor Architecture
How elastic is your virtualized datacenter fabric?
Multi-Requirement Enforcement of Non-Functional Properties on MPSoCs Using Enforcement FSMs - A Case Study
Sparse Matrix-Dense Matrix Multiplication on Heterogeneous CPU+FPGA Embedded System
Contention-aware node allocation policy for high-performance capacity systems
Decoupling processor and memory hierarchy simulators for efficient design space exploration
An OpenMP Parallel Genetic Algorithm for Design Space Exploration of Heterogeneous Multi-processor Embedded Systems
Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture
Software Pipelining in Nested Loops with Prolog-Epilog Merging
Bao: A Lightweight Static Partitioning Hypervisor for Modern Multi-Core Embedded Systems
Efficient Abstraction of Clock Synchronization at the Operating System Level
Detailed Application Characterization and Its Use for Effective Co-Scheduling
An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE
Programming Time-Predictable Processors with Lingua Franca
MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor
A Case Study for a New Invasive Extension of Intel's Threading Building Blocks
Two Architecture Approaches for MILS Systems in Mobility Domains (Automobile, Railway and Avionik)
On Continuous After-the-Fact Leakage-Resilient Key Exchange
Impact of the Scheduling Strategy in Heterogeneous Systems That Provide Co-Scheduling
Reliable Command, Control and Communication Links for Unmanned Aircraft Systems: Towards compliance of commercial drones
A Multi-Modal Distributed Real-Time IoT System for Urban Traffic Control (Invited Paper)
Embedded Systems as Datacenters
SDN for Dynamic Reservations on Real-Time Networks (Invited Talk)
Pipelined SHA-3 Implementations on FPGA: Architecture and Performance Analysis
15th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 13th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2024, Munich, Germany, January 18, 2024
Proceedings of the 7th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 5th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, PARMA-DITAM 2016, Prague, Czech Republic, January 18, 2016
Proceedings of the 2012 Interconnection Network Architecture - On-Chip, Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January 25, 2012
Proceedings of the 3rd Workshop on Co-Scheduling of HPC Applications, COSH@HiPEAC 2018, Manchester, United Kingdom, January 23, 2018
IRQ Coloring: Mitigating Interrupt-Generated Interference on ARM Multicore Platforms
In-Network Caching for Chip Multiprocessors
Designing Drone Systems with Papyrus for Robotics
Beyond the Threaded Programming Model on Real-Time Operating Systems
Performance/Energy Optimization of DSP Transforms on the XScale Processor
Intelligent Vehicle Perception: Toward the Integration on Embedded Many-core
Quest for the ultimate network-on-chip: the NaNoC project
On using genetic algorithms for intrinsic side-channel resistance: the case of AES S-box
An efficient joint analytical and simulation-based design space exploration flow for predictable multi-core systems
Foreword by Editors / Workshop Description / TPC List
Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach
ByteNite: A New Business Model for Grid Computing (Invited Paper)
Towards bridging the gap between academic and industrial heterogeneous system architecture design space exploration
Sunflower : Full-System, Embedded Microarchitecture Evaluation
Phase Complexity Surfaces: Characterizing Time-Varying Program Behavior
Reducing Code Size in Scheduling Synchronous Dataflow Graphs on Multicore Systems
On the Applicability of Virtualization in an Industrial HPC Environment
Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2016, Prague, Czech Republic, January 18, 2016
2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, SiPhotonics@HiPEAC 2015, Amsterdam, Netherlands, January 19, 2015
Automotive Cyber Security: Lessons Learned and Research Challenges
Efficient Program Power Behavior Characterization
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, IMA-OCMC@HiPEAC 2013, Berlin, Germany, January 23, 2013
Runtime parallelization of legacy code on a transactional memory system
Unmanned Vehicles in Smart Farming: a Survey and a Glance at Future Horizons
Online allocation for contention-free-routing NoCs
Tag-Protector: An Effective and Dynamic Detection of Out-of-bound Memory Accesses
Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations
Multithread Accelerators on FPGAs: A Dataflow-Based Approach
Optimal application mapping to 2D-mesh NoCs by using a tabu-based particle swarm methodology
Modeling Multigrain Parallelism on Heterogeneous Multi-core Processors: A Case Study of the Cell BE
Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures
Low-Overhead, High-Speed Multi-core Barrier Synchronization
DDM-VM c : the data-driven multithreading virtual machine for the cell processor
High Performance Embedded Architectures and Compilers, 6th International Conference, HiPEAC 2011, Heraklion, Crete, Greece, January 24-26, 2011. Proceedings
11th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures / 9th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM@HiPEAC 2020, Bologna, Italy, January, 2020
High Performance Embedded Architectures and Compilers, First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings
A Flexible Code Compression Scheme Using Partitioned Look-Up Tables
Communication Based Proactive Link Power Management
A Comparative Evaluation of Latency-Aware Energy Optimization Approaches in Many-Core Systems (Invited Paper)
TinyWIDS: a WPM-based Intrusion Detection System for TinyOS2.x/802.15.4 Wireless Sensor Networks
High-order timing attacks
Hardening High-Assurance Systems: MILS as Software Design for Avionics
Countering type confusion and buffer overflow attacks on Java smart cards by data type sensitive obfuscation
Bringing OptoBoards to HPC-scale environments: An OptoHPC simulation engine
Hierarchical Clustering for On-Chip Networks
Fast Yet Accurate Timing and Power Prediction of Artificial Neural Networks Deployed on Clock-Gated Multi-Core Platforms
MTP-Caffe: Memory, Timing, and Power aware tool for mapping CNNs to GPUs
Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers
Adaptive entity-identifier generation for IMD emergency access
Deriving Efficient Data Movement from Decoupled Access/Execute Specifications
Abstract modelling of switching elements for optical networks-on-chip with technology platform awareness
rev.ng: A Tale of Reverse Engineering, Dynamic Analysis and Translation of Binaries Using QEMU and LLVM
RUST-Encoded Stream Ciphers on a RISC-V Parallel Ultra-Low-Power Processor (Invited Paper)
BRAM-LUT Tradeoff on a Polymorphic DES Design
Dataflow Acceleration of scikit-learn Gaussian Process Regression
GANNoC: A Framework for Automatic Generation of NoC Topologies using Generative Adversarial Networks
Aggressive Function Inlining: Preventing Loop Blockings in the Instruction Cache
A workload extraction framework for software performance model generation
On Using Blockchains for Beyond Visual Line of Sight (BVLOS) Drones Operation: An Architectural Study
Contrasting Power Efficiency of Contention Resolution vs. Avoidance Strategies in Optical Ring Interconnects for Photonically-Integrated Embedded Systems
CAERUS: an effective arbitration and ejection policy for routing in an unidirectional torus
HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches
Finding Stress Patterns in Microprocessor Workloads
Energy-Aware HEVC Software Decoding On Mobile Heterogeneous Multi-Cores Architectures
Towards High-Performance and Power-Efficient Optical NoCs Using Silicon-in-Silica Photonic Components
Detailed Characterization of HPC Applications for Co-Scheduling
High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings
A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip
Control Systems in the Presence of Computational Problems (Invited Talk)
A power-efficient network on-chip topology
Black box power estimation for digital signal processors using virtual platforms
Enabling Civil/Military Cooperation in Crisis Management
Faster Functional Warming with Cache Merging
IPC Control for Multiple Real-Time Threads on an In-Order SMT Processor
Predictive Runtime Code Scheduling for Heterogeneous Architectures
Implicit Data-Parallelism in Kahn Process Networks: Bridging the MacQueen Gap
Low-cost congestion management in networks-on-chip using edge and in-network traffic throttling
A High Speed Scalar Multiplier for Binary Edwards Curves
MonTM: Monitoring-Based Thermal Management for Mixed-Criticality Systems
Fault and Power Analysis Attack Resistant RNS based Edwards Curve Point Multiplication
Efficient Algorithms and Architectures for Double Point Multiplication on Elliptic Curves
Code Arrangement of Embedded Java Virtual Machine for NAND Flash Memory
Evaluation of Offset Assignment Heuristics
Towards Adaptive Multi-Alternative Process Network
A novel graceful degradable routing algorithm for 3D on-chip networks
A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs
COLA-Gen: Active Learning Techniques for Automatic Code Generation of Benchmarks
Predictive modeling methodology for compiler phase-ordering
Bounds Checking with Taint-Based Analysis
An ILP approach for mapping AUTOSAR runnables on multi-core architectures
Applying Decay to Reduce Dynamic Power in Set-Associative Caches
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic
Proceedings of the 5th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 3rd Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2014, Vienna, Austria, January 20, 2014
Fast modeling of shared caches in multicore systems
ReDroSe - Reconfigurable Drone Setup for Resource-Efficient SLAM
Software Defined Radio - A High Performance Embedded Challenge
BXI: designing a network for eXascale
DIEF: An Accurate Interference Feedback Mechanism for Chip Multiprocessor Memory Systems
A resource-centric Application Classification Approach
International Workshop on MILS: Architecture and Assurance for Secure Systems, MILS@HiPEAC 2016, Prague, Czech Republic, January 19, 2016
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors