yusuke1997/dblp-id-title huggingface dataset:
Predicting and Obtaining High Final Test Yields
Testability Expertise and Test Planning from High-Level Specifications
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects
PSBIST: A Partial-Scan Based Built-In Self-Test Scheme
LA-DOS: Layout-Aware-Defect-Oriented Stress UDFM & ATPG Pattern Generation for Zero Defect Automotive Designs
High sensitivity test signatures for unconventional analog circuit test paradigms
Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing
Low Energy On-Line SBST of Embedded Processors
An 18-Bit Precision DC Measurement System
Efficient and Robust Resistive Open Defect Detection Based on Unsupervised Deep Learning
On-line Detection of Faults in Carry-Select Adders
Towards a unified test process: from UML to end-of-line functional test
Analysis of Process Variations, Defects, and Design-Induced Coupling in Memristors
Global cost functions for test generation
Security Preserving Integration and Resynthesis of Reconfigurable Scan Networks
Synthesis and Optimization Procedures for Fully and Easily Testable Sequential Machines
Advancing test compression to the physical dimension
Solder Paste Inspection: Process Control for Defect Reduction
Frequency and Power Correlation between At-Speed Scan and Functional Tests
On Benchmarking Digital Testing Systems
A New Approach to the Use of Testability Analysis in Test Generation
Test Head Design Using Electro-Optic Receivers and GaAs Pin Electronics for a Gigahertz Production Test System
Modeling the Effect of Ground Bounce on Noise Margin
VINCI: Secure Test of a VLSI High-Speed Encryption System
valuating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits
Cost Impacts of Automatic Test Equipment Purchase Decisions
Defect-Finding with Timing-Partitioned Small-Delay-Defect Methodology: Silicon Practice on N2
Test generation in VLSI circuits for crosstalk noise
Assuring Security and Reliability of Emerging Non-Volatile Memories
Device interfacing: the weakest link in the chain to break into the giga bit domain?
Memory FIT Rate Mitigation Technique for Automotive SoCs
Accurate signature driven power conscious tuning of RF systems using hierarchical performance models
An update on IEEE 1149.6 - successes and issues
A Field Analysis of System-level Effects of Soft Errors Occurring in Microprocessors used in Information Systems
A Synthesis Approach to Design for Testability
On-Chip Impulse Response Generation for Analog and Mixed-Signal Testing
Bridging faults and their implication to PLAs
An on-chip ADC BIST solution and the BIST enabled calibration scheme
Robust DfT Techniques for Built-in Fault Detection in Operational Amplifiers with High Coverage
Testing a Switching Memory in a Telcommunication System
BETSY: synthesizing circuits for a specified BIST environment
A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs
Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure
Residual Charge on the Faulty Floating Gate MOS Transistor
A BIST scheme using microprogram ROM for large capacity memories
Two CMOS Metastability Sensors
High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked Loops
Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis
Logic BIST with Scan Chain Segmentation
The GENESYS-Algorithm for ATPG without Fault Simulation
UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction
Bridging the gap between Design and Test Engineering for Functional Pattern Development
Quality and Single-Stuck Faults
New Techniques for Manufacturing Test and Diagnosis of LSSD Boards
A VXI Driver-Sensor Instrument with Large Tester Architecture
Intel ® IBIST, the full vision realized
Simulation of an Integrated Design and Test Environment for Mixed-Signal Integrated Circuits
Systematic defect detection methodology for volume diagnosis: A data mining perspective
Drive only at speed functional testing; one of the techniques Intel is using to control test costs
New Automated Prober Support for High Pincount Test Heads
The AB-filling methodology for power-aware at-speed scan testing
Built-in Fault Diagnosis for Tunable Analog Systems Using an Ensemble Method
MEMS Manufacturing Testing: An Accelerometer Case Study
LIMSoft: Automated Tool for Design and Test Integration of Analog Circuits
STIL persistence [data reduction]
Test and debug features of the RTO7 chip
High Accuracy Stimulus Generation for A/D Converter BIST
An Approach for Designing Total-Dose Tolerant MCMs Based on Current Monitoring
Report on a Pilot Project Successfully Implementing a Design-to-Test Methodology
High Fault Coverage of In-Circuit IC Pin Faults with a Vectorless Test Technique Using Parasitic Transistors
RTL functional test generation using factored concolic execution
Controlled Sine Wave Fitting for ADC Test
BA-BIST: Board test from inside the IC out
A diagnostic test pattern generation algorithm
Security vs. Test Quality: Are they mutually exclusive?
A Novel Approach to the Analysis of VLSI Device Test Programs
An Accelerated Jitter Tolerance Test Technique on Ate for 1.5GB/S and 3GB/S Serial-ATA
Transfer Function Estimation Part I : Theoretical and Practical Considerations
Selecting Close-to-Functional Path Delay Faults for Test Generation
Experiences and Expectations in VLSI Testing
An STL Gate Array Reliability Test Bar
Memory built-in self-repair using redundant words
Hierarchical boundary-scan: a Scan Chip-Set solution
Signal Integrity Loss in SoC's Interconnects: A Diagnosis Approach Using Embedded Microprocessor
The new ATE: Protocol aware
High level ATPG is important and is on its way!
DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor
Software Environment for 500 MHz VLSI Test System "ULTIMATE"
Hierarchical self-test concept based on the JTAG standard
It isn't just testing anymore (REDUX)
A High Precision IDDQ Measurement System With Improved Dynamic Load Regulation
Compressed pattern diagnosis for scan chain failures
A concurrent approach for testing address decoder faults in eFlash memories
Data Critically Estimation In Software Applications
OPMISR: the foundation for compressed ATPG vectors
Asynchronous Design: Working the Fast Lane
Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs
Contactless VLSI Laser Probing
Upper-bound computation for optimal retargeting in IEEE1687 networks
Memory repair for high fault rates
Practical Issues of Failure Diagnosis and Analysis in a Fast Cycle Time Environment
Development of a Solution for Achieving Known-Good-Die
Finding Power/Ground Defects on Connectors - Case Study
"Instant On" Semiconductor Memories: Reality or Myth
Data Compression for Multiple Scan Chains Using Dictionaries with Corrections
PPA Optimization of Test Points in Automotive Designs
The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data
A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer
Random Testing for Stuck-At Storage Cells in an Embedded Memory
Third-Order Phase Lock Loop Measurement and Characterization
Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences
Diagnostic Fault Simulation of Sequential Circuits
Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die
Completely Self-Checking Checkers in PLAs
A Bulti-in Self-Test Strategy for Wireless Communication Systems
High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST
A highly testable and diagnosable fabrication process test chip
Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard
Computer-aided design of pseudoexhaustive BIST for semiregular circuits
Leveraging UCIe Interface for Silicon Health & Reliabiilty of Chiplets in a 3D Stack
A Case Study of Mixed Signal Fault Isolation: Knowledge Based vs. Decision Tree Programming
DfT and on-line test of high-performance data converters: a practical case
Constrained ATPG for functional RTL circuits using F-Scan
Future Trends in Test of Electronic Circuits With Implications tor Entry Level Test Professionals
CMOS Bridges and Resistive Transistor Faults: I DDQ versus Delay Effects
Proceedings International Test Conference 1981, Philadelphia, PA, USA, October 1981
Importance of Asynchronous Refreshing in Memory Testing
High-coverage ATPG for datapath circuits with unimplemented blocks
Testing GaAs Devices with a Digital In-Circuit Test System
Diagnose compound scan chain and system logic defects
Ethics, Professionalism and Accountability in Testing
Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation
Scan DFT: Why More Can Cost Less
On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding
A Method of Extending an 1149.1 Bus for Mixed-Signal Testing
Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area Substrates
Exploiting don't cares to enhance functional tests
Efficient power droop aware delay fault testing
Outlier Detection for DPPM Reduction
Microwave test mismatch and power de-embedding
The Effect of the Factory of the Future on Society
Improving Delta-I_DDQ-based test methods
Risks Associated with Faults within Test Pattern Compactors and Their Implications on Testing
Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model
Industry Graphic Standards and ATE Windowing Software
Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor
The Design, Implementation and Analysis of Test Experiments
Automated Electron Beam Testing of VLSI Circuits
TASTE: A Tool for Analog System Testability Evaluation
Keynote address wednesday: Compute continuum and the nonlinear validation challenge
Testing embedded-core based system chips
Test-mode-only scan attack and countermeasure for contemporary scan architectures
Ensuring System Traceability to International Standards
Embedded DRAM built in self test and methodology for test insertion
Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch
Fine-Grained Adaptive Testing Based on Quality Prediction
Future of Temperature and Humidity Testing: Highly Accelerated Temperature and Humidity Stress Test (HAST)
Application of a continuous-time level crossing quantization method for timing noise measurements
Transition Fault Simulation by Parallel Pattern Single Fault Propagation
Concurrent Engineering: Creating Designs That Are Faster, Better and Available Sooner
A Hybrid Space Compactor for Adaptive X-Handling
A Product Information Access System for the Verification, Test, Diagnosis and Repair of Electronic Assemblies
An Automated Test of a Disk Product Power System Independent of the Primary Function of the Machine
Defect Tolerance at the End of the Roadmap
Application of Sampling in Industrial Analog Defect Simulation
Sufficient Testing In A Self-Testing Environment
Root cause identification of an hard-to-find on-chip power supply coupling fail
Making predictive analog/RF alternate test strategy independent of training set size
A Fundamental Approach to SPC Implementation
Testing of latch based embedded arrays using scan tests
An Optimal Test Sequence for the JTAG/IEEE P1149.1 Test Access Port Controller
PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test
Test Vector Generation Based on Correlation Model for Ratio-Iddq
Analytical test of 3D integrated circuits
NAND Trees Accurately Diagnose Board-Level Pin Faults
Use of In-Fab Parametric Testing for Process Control of Semiconductor Manufacturing
The Cost of Quality: Reducing ASIC Defects with I DDQ At-Speed Testing and Increased Fault Coverage
SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP Counterfeits
Achieving Automotive Safety Requirements through Functional In-Field Self-Test for Deep Learning Accelerators
Increasing Test Engineering Effectivness
A jitter separation and BER estimation method for asymmetric total jitter distributions
Statistical AC Test Coverage
Embedded Power Delivery Decoupling in Small Form Factor Test Sockets
Improving wafer sort yields with radius-tip probes
Running scan test on three pins: yes we can!
Defect-Oriented vs. Schematic-Level Based Fault Simulation for Mixed-Signal ICs
Recurrent Test Patterns
Use of Pipeline Converters for ATE Applications
Digitizer Error Extraction in the Nonlinearity Test
Concurrent Error Detection for Restricted Fault Sets in Sequential Circuits and Microprogrammed Control Units Using Convolutional Codes
Dynamic Test Emulation for EDA-Based Mixed-Signal Test Development Automation
Simple and Efficient Algorithms for Functional RAM Testing
DesignTest^TM: A Solution to the Problems of ASIC Verification
Novel compensation scheme for local clocks of high performance microprocessors
Automotive IC's: less testing, more prevention
High Quality Test Methodology for Highly Reliable Devices
Supply-voltage optimization to account for process variations in high-volume manufacturing testing
On CMOS Totally Self-Checking Circuits
A Self-Test Method for Digital Circuits
Cost-Effective System-Level Test Strategies
Testing of Droplet-Based Microelectrofluidic Systems
Distributed Factory Data Management-Breaking the Network Bottleneck
Platform Independent Test Access Port Architecture
A practical approach to comprehensive system test & debug using boundary scan based test architecture
Manufacturing data: Maximizing value using component-to-system analysis
Testing for systematic defects based on DFM guidelines
Recruiting distributed resources for grid resilience: The need for transparency
TTTC: Test Technology Technical Council
A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores
Transparent Memory Testing for Pattern-Sensitive Faults
Is It Cost-Effective to Achieve Very High Fault Coverage for Testing Homogeneous SoCs with Core-Level Redundancy?
Use of MISRs for compression and diagnostics
Instruction Based BIST for Board/System Level Test of External Memories and Internconnects
Efficient combination of trace and scan signals for post silicon validation and debug
VLSI : How Much Fault Coverage Is Enough ?
Dynamic Techniques for Yield Enhancement of Field Programmable Logic Arrays
A validation fault model for timing-induced functional errors
Expert System for the Functional Test Program Generation of Digital Electronic Circuit Boards
ACT: A DFT Tool for Self-Timed Circuits
Wafer2Spike: Spiking Neural Network for Wafer Map Pattern Classification
System Perspective on Diagnostic Testing
Macro-testability and the VSP
An ILP formulation to optimize test access mechanism in system-on-chip testing
Extraction of Coupled SPICE Models for Packages and Interconnects
A Divide and Conquer Testing Strategy for Detection of Multiple Faults by SFDTS
Automatic Diagnostic Program Generation for Mixed Signal Load Board
Test Generation In Lamp2: System Overview
Signature Analyzer Design for Yield Learning Support
Variance reduction and outliers: statistical analysis of semiconductor test data
Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors
A Case Study in the Use of Scan in microSparc TM Testing and Debug
Efficiently Performing Yield Enhancements by Identifying Dominant Physical Root Cause from Test Fail Data
Accuracy requirements in at-speed functional test
Integrating Electrical Test into Final Assembly
Board security enhancement using new locking SIB-based architectures
Faults Which Challenge the In-Circuit Tester: Some Examples and Some Solutions
Factory Final Test Systems
Timing skew compensation technique using digital filter with novel linear phase condition
Testing Repairable RAMs and Mostly Good Memories
Transient current testing of 0.25 μm CMOS devices
Timing Analyzer for Embedded Testing
Parallel, multi-DUT testing in an open architecture test system
Built-in self-test for stability measurement of low dropout regulator
Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engine
FPGA Time Measurement Module: Preliminary Results
Extreme-voltage stress vector generation of analog CMOS ICs for gate-oxide reliability enhancement
Proceedings IEEE International Test Conference 1990, Washington, D.C., USA, September 10-14, 1990
A Unifying Methodology for Intellectual Property and Custom Logic Testing
A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line
Design and Implementation of IEEE 1149.6
A distributed BIST technique for diagnosis of MCM interconnections
Fault tolerant electronic system design
Fault Collapsing via Functional Dominance
Testable Designs of Sequential Circuits Under Highly Observable Condition
On-the-shelf core pattern methodology for ColdFire(R) microprocessor cores
Structural approach for built-in tests in RF devices
Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation
Application of Boundary Scan in a Fault Tolerant Computer System
Selecting target bridging faults for uniform circuit coverage
Test method evaluation experiments and data
Analysis of Retention Time Distribution of Embedded DRAM - A New Method to Characterize Across-Chip Threshold Voltage Variation
Cell-aware analysis for small-delay effects and production test results from different fault models
A System for Converter Testing Using Walsh Transform Techniques
Leveraging IEEE 1641 for Tester-Independent ATE Software
Silicon Symptoms to Solutions: Applying Design for Debug Techniques
Delay testing considering crosstalk-induced effects
A Fast Fault Grader: Analysis and Applications
A testable design of logic circuits under highly observable condition
Integrated Pin Electronics for a VLSI Test System
Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ
Test Effectiveness Metrics and CMOS Faults
Effective DC fault models and testing approach for open defects in analog circuits
On-line Testing Field Programmable Analog Array Circuits
Security vs. Test Quality: Can We Really Only Have One at a Time?
Transfer Learning for Minimum Operating Voltage Prediction in Advanced Technology Nodes: Leveraging Legacy Data and Silicon Odometer Sensing
TIDE: Telemetry-Informed Delay Testing for Silent Data Corruption *
Exact Aliasing Computation for RAM BIST
Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning
Burn-in Temperature Projections for Deep Sub-micron Technologies
High speed differential pin electronics over 6.4 Gbps
Diagnosis for MRAM write disturbance fault
Advanced Mixed Signal Testing by DSP Localized Tester
Divide and conquer diagnosis for multiple defects
Semiconductor manufacturing process monitoring using built-in self-test for embedded memories
On the Use of Neural Networks to Guide Software Testing Activities
Can we ensure reliability in the era of heterogeneous integration?
Testability access of the high speed test features in the Alpha 21264 microprocessor
A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity Memories
Automatic Visual Testing: A New, Comprehensive Element of Cost-Effective PCB Testing Strategies
Contract Manufacturing: How Much Can They Do?
Generation of Low Power Dissipation and High Fault Coverage Patterns for Scan-Based BIST
BIST Power Reduction Using Scan-Chain Disable in the Cell Processor
Tailoring ATPG for embedded testing
Integrated Test Program Development Package
Separating temperature effects from ring-oscillator readings to measure true IR-drop on a chip
: Modeling and Test Point Selection for Data Converter Testing
New and Not-So-New Test Challenges of the Next Decade
An ATE system for testing 2.4-GHz RF digital communication devices with QAM signal interfaces
Design for Board and System Level Structural Test and Diagnosis
Statistical Process Control Using the Parametric Tester
Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained
Remote boundary-scan system test control for the ATCA standard
Defect-oriented cell-internal testing
Testability implemented in the VAX 6000 model 400
The Develpment of a Tester-Per-Pin VLSI Test System Architecture
Search State Equivalence for Redundancy Identification and Test Generation
Hardware IP Protection Using Logic Encryption and Watermarking
Measurement Repeatability for RF Test Within the Load-board Constraints of High Density and Fine Pitch SOC Applications
Optimizing the Cost of Test at Intel Using per Device Data
Pseudo-Random Low Power Built In Self Test
To Test or To Inspect, What is the Coverage?
Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits
Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores
Impeccable Circuits III
GaAs Driver and Sensor for a High-Speed Test System
A Method of Reducing ATE System Error Components and Guaranteeing Subnanosecond Measurement Accuracies
Testability Measures : What Do They Tell Us ?
Finding Defects with Fault Models
Testability Features of a 32 Kbps ADPCM Transcoder
Analog Circuit Testing Based on Sensitivity Computation and New Circuit Modeling
From Hybrid to Integrated: The Evolution of DFT Integration in SoC Design at Intel
A High Level Approach to Integrating Design and Test
Compiled Code, Dynamic Worst Case Timing Simulation Tracking Multiple Causality
Improving structural coverage of functional tests with checkpoint signature computation
A comparative study of one-shot statistical calibration methods for analog / RF ICs
An Analysis of the Economics of Self Test
Test Pattern Generation for Circuits with Three-state Modules by Improved Z-algorithm
Subnanosecond Timing Measurements on MOS Devices Using Modern VLSI Test Systems
A New System Architecture for a Combined In-Circuit/Functional Tester
Achieving serendipitous N-detect mark-offs in Multi-Capture-Clock scan patterns
Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects
Multiplets, Models, and the Search for Meaning: Improving Per-Test Fault Diagnosis
A Group Probing Strategy for Testing Large Number of Chips
In-System Timing Extraction and Control Through Scan-Based, Test-Access Ports
Fault Tolerance in RRAM-based AI Accelerator with Guided Randomized Activation
Testability implications in low-cost integrated radio transceivers: a Bluetooth case study
XML And Java For Open ATE Programming Environment
BIST-Based Diagnostics of FPGA Logic Blocks
Production Test Challenges And Possible Solutions For Multiple GB/s ICs
Random Pattern Testing for Address-Line Faults in an Embedded Multiport Memory
Using Implications for Online Error Detection
Structured Logic Analysis for Manufacturing Testing
Tester Independent Problem Representation and Tester Dependent Program Generation
Quad DCVS dynamic logic fault modeling and testing
Test Strategies For a 40Gbps Framer SoC
2012 IEEE International Test Conference, ITC 2012, Anaheim, CA, USA, November 5-8, 2012
Two New Techniques for Identifying Opens on Printed Circuit Boards: Analog Junction Test, and Radio Frequency Induction Test
Telecom Test: New Challenges, Old Roots
Considerations of the Testing of RAMs with Dual Ports
The Great ATE Robbery
An Analysis of the Multiple Fault Detection Capabilities of Single Stuck-at Fault Test Sets
Evaluation ot Monitor Complexity for Concurrently Testing Microprogrammed Control Units
A new approach to RF impedance test
Where is car IC testing going?
BIST and fault insertion re-use in telecom systems
Using on-chip test pattern compression for full scan SoC designs
Formal Verification of the UltraSPARC TM Family of Processors via ATPG Methods
Concurrent engineering
Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ
Massive signal tracing using on-chip DRAM for in-system silicon debug