yusuke1997/dblp-id-title huggingface dataset:
Integrating CAD tools into a framework environment using a flexible and adaptable procedural interface
Cell Height Driven Transistor Sizing in a Cell Based Module Design
Design for verification testability
Evaluation criteria of HDLs: VHDL compared to Verilog, UDL/I & M
A new optimization driven clustering algorithm for large circuits
Timing optimization by bit-level arithmetic transformations
Tackling cost optimization in testable design by forward inferencing
Parallel algorithms for slicing based final placement
An experimental analysis of the effectiveness of the circular self-test path technique
Application-specific microelectronics for mechatronic systems
Gate-level timing verification using waveform narrowing
A memory selection algorithm for high-performance pipelines
High-level synthesis transformations for programmable architectures
Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures
MORE: an alternative implementation of BDD packages by multi-operand synthesis
A new logic minimization method for multiplexor-based FPGA synthesis
Efficient linear circuit analysis by Padé approximation via the Lanczos process
Component Selection, Scheduling and Control Schemes for High Level Synthesis
Generalized coupling as a way to improve the convergence in relaxation-based solvers
Towards a requirements definition, specification and system design environment
Embedded pin assignment for top down system design
Tests for path delay faults vs. tests for gate delay faults: how different they are
An iterative combinational logic synthesis technique using spectral information
An object-oriented persistent database interface for CAD
Cellular scan test generation for sequential circuits
CHEOPS: an integrated VLSI floor planning and chip assembly system implemented in object oriented LISP
A new knowledge-based design manager assistant for CAD frameworks
Data flow graphs: system specification with the most unrestricted semantics
Test pattern generation hardware motivated by pseudo-exhaustive test techniques
Computing binary decision diagrams for VHDL data types
Testability analysis of hierarchical finite state machines
TORSIM: An Efficient Fault Simulator for Synchronous Sequential Circuits
A fault model for VHDL descriptions at the register transfer level
A prototyping environment for control-oriented HW/SW systems using state-charts, activity-charts and FPGA's
GAUT: An architectural synthesis tool for dedicated signal processors
An intelligent design system for analogue integrated circuits
Synthesis of Application-Specific Multiprocessor Systems
A New BIST Approach for Delay Fault Testing
Cosimulation of real-time control systems
Features supporting system-level specification in HDLs
Simulation and design optimization of microsystems based on standard simulators and adaptive search techniques
Semi-dynamic scheduling of synchronization-mechanisms
PERFLEX: a performance driven module generator
MACHETE: synthesis of sequential machines for easy testability
A new technique for exploiting regularity in data path synthesis
Incremental re-encoding for symbolic traversal of product machines
State assignment for finite state machines using T flip-flops
Signature Analysis for Sequential Circuits with Reset
A novel and efficient technique for transient analysis of tightly coupled circuits: The integral equation method (IEM)
Design tool encapsulation - all problems solved?
Interface specification and synthesis for VHDL processes
A fast and efficient algorithm for determining fanout trees in large networks
1992 VHDL standardization overview
A multi level testability assistant for VLSI design
Correctness verification of concurrent controller specifications
Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning
A digital method for testing embedded switched capacitor filters
Logic and Fault Simulation by Cellular Automata
Asynchronous state machine synthesis using data driven clocks
Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling
GOSSIP: a generic system for statistical circuit design
Timing preserving interface transformations for the synthesis of behavioral VHDL
A new global routing algorithm for over-the-cell routing in standard cell layouts
Structure based methods for parallel pattern fault simulation in combinational circuits
System clock estimation based on clock slack minimization
A Method for Reducing Power Consumption of CMOS Logic Based on Signal Transition Probability
Wolverines: standard cell placement on a network of workstations
Design by similarity using transaction modeling and statistical techniques
A dynamic scheduling algorithm for the simulation of MOS and bipolar circuits using waveform relaxation
Random Testing of Interconnects in A Boundary Scan Environment
Transistor placement and interconnect algorithms for leaf cell synthesis
Software methodologies for VHDL code static analysis based on flow graphs
System-Level Modeling and Verification: a Comprehensive Design Methodology
Automatic Synthesis of BISTed Data Paths From High Level Specification
Genesis: A Behavioral Synthesis System for Hierarchical Testability
Boolean matching in logic synthesis
A combined waveform relaxation: waveform relaxation newton algorithm for efficient parallel circuit simulation
Fault tolerant and BIST design of a FIFO cell
A net-based semantics for VHDL
On the k-layer planar subset and via minimization problems
Predicting the functional complexity of combinational circuits by symbolic spectral analysis of Boolean functions
EXPLORER: an interactive floorplanner for design space exploration
Automatic module allocation in high level synthesis
A neural net based self organising scheduling algorithm
Multi-kernel simulation description within VHDL
A new flexible VHDL simulator
PEST: a tool for implementing pseudo-exhaustive self test
PROOFS: a super fast fault simulator for sequential circuits
On the architecture of a CAD framework: the NELSIS approach
A new power estimation technique with application to decomposition of Boolean functions for low power
Regular schedules for scalable design of IIR filters
A tool for processor instruction set design
Design of a tool interface for integrated CAD-environments
Static analysis for VHDL model evaluation
Testability analysis and improvement from VHDL behavioral specifications
Locally optimistic methods of concurrent simulation
Composing ActivityCharts/StateCharts, SDL and SAO specifications for codesign in avionics
Interconnect optimisation during data path allocation
A strategy for testability enhancement at layout level
Robust tests for stuck-open faults and design for testability of reconvergent fan-out CMOS logic networks
Exploration of hardware/software design space through a codesign of robot arm controller
Interface Controller Synthesis from Requirement Specifications
An iterative algorithm for the binate covering problem
The role of VHDL within the TOSCA hardware/software codesign framework
Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems
A fast and accurate characterization method for full-CMOS circuits
Test of Bridging Faults in Scan-based Sequential Circuits
An automatically verified generalized multifunction arithmetic pipeline
A gate-matrix oriented partitioning approach for multilevel logical networks
ASTA: an integrated system for bist analysis & automatic test generation
Compilation of optimized OBDD-algorithms
Technology independent boundary scan synthesis (design flow issues)
CGE: automatic generation of controllers in the CATHEDRAL-II silicon compiler
RESIST: a recursive test pattern generation algorithm for path delay faults
Towards Incorporating Device Parameter Variations in Timing Analysis
Clock optimization for high-performance pipelined design
NETHDL: abstraction of schematics to high-level HDL
Formal methods for silicon compilation
DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits
Pre-placement of VLSI blocks through learning neural networks
A high-level synthesis approach to optimum design of self-checking circuits
An effective system development environment based on VHDL prototyping
Boolean Manipulation with Free BDD's. First Experimental Results
PCUBE: A performance driven placement algorithm for low power designs
Fast fault simulation in combinational circuits: an efficient data structure, dynamic dominators and refined check-up
ANT - a test harness for the NELSIS CAD system
A new approach to pipeline optimisation
Register allocation for data flow graphs with conditional branches and loops
Fast OFDD based minimization of fixed polarity Reed-Muller expressions
Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions
BEPPO: A data model for design representation
System level design, a VHDL based approach
Path search on rectangular floorplan
CoWare - a design environment for heterogenous hardware/software systems
Redesign using state splitting
Minimal area merger of finite state machine controllers
Channel routing with non-terminal doglegs
A self-checking PLA automatic generator tool based on unordered codes encoding
Area and performance optimizations in path-based scheduling
An approach to the analysis and test of crosstalk faults in digital VLSI circuits
GAFPGA: Genetic algorithm for FPGA technology mapping
Automatic layout generation for CMOS analog transistors
Rapid prototyping using high density interconnects
Partitioning approach to find an exact solution to the fitting problem in an application-specific EPLD device
An Optimizable Model for Process Independent Symbolic Design
Instruction-Set Matching and Selection for DSP and ASIP Code Generation
Monitoring BIST by covers
TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator
TAS: an accurate timing analyser for CMOS VLSI
Harmonic scheduling of linear recurrences for digital filter design
An efficient placement method for large standard-cell and sea-of-gates designs
Generating VHDL models from natural language descriptions
An incremental functional simulator implemented on a network of transputers
Rapid performance estimation for system design
An approach to CAD database support of design consistency control
Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path
Timing constraint specification and synthesis in behavioral VHDL
Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis
The automatic diagnosis of faults in analogue and mixed-signal circuits
VHDL intermediate format standardization activity: status and trends
Incorporating the Controller Effects During Register Transfer Level Synthesis
A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis
Design verification considering manufacturing tolerances by using worst-caste distances
Semantics and synthesis of signals in behavioral VHDL
Efficient constrained encoding for VLSI sequential logic synthesis
An efficient tool for system-level verification of behaviors and temporal properties
A new decomposition method for multilevel circuit design
A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning
Restructuring VLSI layout representations for efficiency
A classification of design steps and their verification
Evaluation of function blocks for asynchronous design
Integration of VHDL into a system design environment
A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions
Formal method for self-timed design
Comparison of implementations of real arithmetic in ELLA and VHDL
100-hour design cycle: a test case
Matching system and component behaviour in MIMOLA synthesis tools
False path exclusion in delay analysis of RTL-based datapath-controller designs
Nondeterministic finite-state machines and sequential don't cares
A global router for sea-of-gates circuits
The use of single and multiple seed architectures with a natural based micro-architecture exploration algorithm
A dynamic programming approach to the power supply net sizing problem
VHDL analog extensions: process, issues and status
Generating VHDL-A - like models using ABSynth
Decomposed symbolic forward traversals of large finite state machines
Fuzzy specification of finite state machines
Synthesis of complex VHDL operators
VHDL-based communication and synchronization synthesis
Crossing distribution
Specification and design of electronic control units
PLATO: a CAD tool for logic synthesis based on decomposition
Automatic workflow generation
Design support of printed circuit boards concerning radiation and irradiation effects (EMI): using an extended EMC-Workbench
A distributed routing system for multilayer SOG
A tightly coupled approach to design and data management
A new concept for accurate modeling of VLSI interconnections and its application for timing simulation
A Study of Undetectable Non-Feedback Shorts for the Purpose of Physical-DFT
An extendable MIPS-I processor kernel in VHDL for hardware/software co-design
Detection of PLA multiple crosspoint faults
Compiled-code-based simulation with timing verification
VHDL for high speed desktop video ICs: experience with replacement of other simulator
A proposed hardware fault simulation engine
SHARP-looking geometric partitioning
Hierarchical layout verification for submicron designs
An Overview of Analogue Optimisation Using "AD-OPT"
VHDL and fuzzy logic if-then rules
Why to incorporate a data definition language into a CAD frameworks extension language
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
DESB, a functional abstractor for CMOS VLSI circuits
A performance analysis tool for performance-driven micro-cell generation
Performance-driven interconnection optimization for microarchitecture synthesis
A Suggestion for Accelerating the Analog Fault Simulation
Modeling of Broken Connections Faults in CMOS ICs
Automatic knowledge acquisition in a digital circuit design system
GASP: a Genetic Algorithm for Standard cell Placement
Event-driven behavioural simulation of analogue transfer functions
Formal sizing rules of CMOS circuits
Temporal verification of behavioral descriptions in VHDL
Synthesis from mixed specifications
Parallel switch-level simulation for VLSI
Overall thermal simulation of electronic equipment
Challenges for CAD in computer development in the 1990s
Representing the hardware design process by a common data schema
Design data management in a distributed hardware environment
Optimization techniques for multiple output function synthesis
Synthesis of functions and procedures in behavioral VHDL
A flexible access control mechanism for CAD frameworks
Formal boolean manipulations for the verification of sequential machines
An Efficient Yield Optimization Method Using A Two Step Linear Approximation of Circuit Performance
Timing Analysis of Combinational Circuits using ADD's
SPADES: a simulator for path delay faults in sequential circuits
Variable Accuracy Device Modeling for Event-Driven Circuit Simulation
Signal Transition Graph Transformations for Initializability
Self Testable Boards with Standard IEEE 1149.5 Module Test and Maintenance (MTM) Bus Interface
On generating compact test sequences for synchronous sequential circuits
On implementation choices for iterative improvement partitioning algorithms
Towards a common RT-level subset of VHDL
The effectiveness of different test sets for PLAs
Experiments with autonomous test of PLAs
Correctness proofs of parameterized hardware modules in the CATHEDRAL-II synthesis environment
A Generalized Signal Transition Graph Model for Specification of Complex Interfaces
Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment
Clock independent timing verification of level-sensitive latches
On the minimal test set for single fault location
Generating Synchronous Timed Descriptions of Digital Receivers from Dynamic Data Flow System Level Configurations
VHDL 1076.1 - analog and mixed signal extensions to VHDL
Tool communication in an integrated synthesis environment
CIRCE: a program for parasitic parameter extraction
Formal specification and simulation of instruction-level parallelism
Multilevel generalization of relaxation algorithms for circuit simulation
Library based technology mapping using multiple domain representations
A fast multilayer general area router for MCM designs
Automatic partitioning for deterministic test
Combined topological and functionality based delay estimation using a layout-driven approach for high level applications
Logic synthesis for reliability - an early start to controlling electromigration and hot carrier effects
A database interface for phased tool integration
Selected aspects of component modeling
A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability
Datapath optimization using feedback
Computer-aided technique for optimal design of defect-tolerant VLSI with built-in redundancy
Efficent suboptimal state assignment for large sequential machines
Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations
Generation of deterministic test patterns by minimal basic test sets
Testability of Circuits Derived from Functional Decision Diagrams
P.SIZE: a sizing aid for optimized designs
Fast functional evaluation of candidate OBDD variable orderings
A quantitative measure of robustness for delay fault testing
A refinement calculus for VHDL
Optimal equivalent circuits for interconnect delay calculations using moments
Synchronous design in VHDL
High level test generation using data flow descriptions
Development of test programs with the aid of a testeroriented pattern language
A formal non-heuristic ATPG approach
(V)HDL-based verification of heterogeneous synchronous/asynchronous systems
A portable and extendible testbed for distributed logic simulation
NAUTILE: a safe environment for silicon compilation
Functional-level analog macromodeling with piecewise linear signals
An approach to guided incremental specification
A Functionality Fault Model: Feasibility and Applications
On modeling integrated design environments
VHDL based design methodology for hierarchy and component re-use
Efficient Implementations of Self-Checking Multiply and Divide Arrays
Timing influenced force directed floorplanning
Bug Identification of a Real Chip Design by Symbolic Model Checking
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
Delay Reduction by Segment Substitution
BDD-based testability estimation of VHDL designs
A macro-cell global router based on two genetic algorithms
A system level HW/SW partitioning and optimization tool
Delay modelling improvement for low voltage applications
A graphical data management system for HDL-based ASIC design projects
Post-analysis-based clustering dramatically improves the Fiduccia-Mattheyses algorithm
Modeling ASIC memories in VHDL
Scheduling with Environmental Constraints based on Automata Representations
Derivation of signal flow for switch-level simulation
An appreciation of simulated annealing to maze routing
A core information model of VHDL
An Efficient Router for 2-D Field Programmable Gate Arrays
Post routing performance optimization via tapered link insertion and wiresizing
A framework for hierarchical performance analysis
The NMP-CADLAB framework: a common framework for tool integration and development
Calculation of the Rademacher-Walsh spectrum from a reduced representation of Boolean functions
Quantifying design productivity: an effort distribution analysis
Address Generation for array access based on modulus m counters
A method for partitioning UNITY language in hardware and software
BRASIL: the Braunschweig mixed-mode-simulator for integrated circuits
Mapping statechart models onto an FPGA-based ASIP architecture
Flexible timing specification in a VHDL synthesis subset
Test generation based on synthesizable VHDL descriptions
Efficient random testing with global weights
Eldo-XL: a software accelerator for the analysis of digital MOS circuits by an analog simulator
Synthesis of System-Level Bus Interfaces
A native process algebra for VHDL
A consistent nonlinear simulation environment based on improved harmonic balance techniques
PDAS: Processor design automation system
Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis
Hardware/software partitioning of VHDL system specifications
Optimal slicing of plane point placements
Automatic synthesis of extended burst-mode circuits using generalized C-elements
A system for compiling and debugging structured data processing controllers
Open-ended system for high-level synthesis of flexible signal processors
A hierarchical approach to timing verification in CMOS VLSI design
Issues in low-power design for telecom
Implementation of a CORDIC Processor for CFFT Computation in Gallium Arsenide Technology
How to efficiently build VHDL testbenches
Conditional and unconditional hardware sharing in pipeline synthesis
Hardware-software-codesign of application specific microcontrollers with the ASM environment
Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits
Testable path delay fault cover for sequential circuits
A hardware environment for prototyping and partitioning based on multiple FPGAs
System synthesis using behavioural descriptions
Transmission gate delay models for circuit optimization
An efficient methodology for symbolic compaction of analog IC's with multiple symmetry constraints
A Graphical Approach to Analogue Behavioural Modelling
Maximal reduction of lookup-table based FPGAs
Verification of a production cell controller using symbolic timing diagrams
ALU synthesis from HDL descriptions to optimized multi-level logic
On variable ordering of binary decision diagrams for the application of multi-level logic synthesis
Beyond VHDL: textual formalisms, visual techniques, or both?
Re-engineering hardware specifications by exploiting design semantics
CACTUS: a symbolic CMOS two-dimensional compactor
Modeling shared variables in VHDL
The VLSI-programming language tangram and its translation into handshake circuits
Hierarchical test generation: Where we are, and where we should be going
MOLE: a sea-of-gates detailed router
VHD e LDO: A new mixed mode simulation
Design management requirements for hardware description languages
PAR-APLAC: Parallel Circuit Analysis and Optimization
State machine abstraction from circuit layouts using BDD's: applications in verification and synthesis
Toward a formal semantics of IEEE Std. VHDL 1076
Non-Tree Routing
An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits
High-level modeling using extended timing diagrams - A formalism for the behavioral specification of digital hardware
An approach to design flow management in CAD frameworks
Logic systems for path delay test generation
ROM-based finite state machines with PLA address modifiers
A neural network based algorithm for the scheduling problem in high-level synthesis
Fast Boolean matching for field-programmable gate arrays
Module assignment for low power
Test function embedding algorithms with application to interconnected finite state machines
Model generation of test logic for macrocell based designs
Delay macromodels for the timing analysis of GaAs DCFL
A practical approach to EMC for printed circuit board (PCB) and multichip module (MCM) design
LibQA - library quality assurance for VHDL synthesis and simulation
Procedure exlining: a new system-level specification transformation
Transforming Linear Systems for Joint Latency and Throughout Optimization
VHDL intermediate form standardization: process, issues and status
Next generation environment for extremely fast test pattern generation
Tools and devices supporting the pseudo-exhaustive test
An exact analytic technique for simulating uniform RC lines
Synthesis of Self-Testable Controllers
Design of delay insensitive circuits using multi-ring structures
TONIC: A timing database for VLSI design
On the intrinsic rent parameter and spectra-based partitioning methodologies