yusuke1997/dblp-id-title huggingface dataset:
A cost model for partial dynamic reconfiguration
Embedded Computer Systems: Architectures, Modeling, and Simulation, 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008. Proceedings
Empirical evaluation of data transformations for network infrastructure applications
Compressed Swapping for NAND Flash Memory Based Embedded Systems
Preamble Sense Multiple Access (PSMA) for Impulse Radio Ultra Wideband Sensor Networks
Design Space Expoloration Chip Size Estimation for SOC Design Space Exploration
Fully Distributed Deep Learning Inference on Resource-Constrained Edge Devices
Is time predictability quantifiable?
Evaluation of ASIPs Design with LISATek
FPL-3E: Towards Language Support for Reconfigurable Packet Processing
Multi-Domain SystemC model of 128-channel time-multiplexed neural interface front-end
Parallel Memory Implementation for Arbitrary Stride Accesses
2017 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2017, Pythagorion, Greece, July 17-20, 2017
Supervised testing of concurrent software in embedded systems
Interprocedural Optimization for Dynamic Hardware Configurations
Performance and energy evaluation of spark applications on low-power SoCs
Design Methodology for Software Radio Systems
On-Chip Communication in Run-Time Assembled Reconfigurable Systems
Racetrack memory-based encoder/decoder for low-power interconnect architectures
Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri Nets
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques
Faster unicores are still needed
Modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow Graphs
Stream Image Processing on a Dual-Core Embedded System
A Java-Enabled DSP
Analyzing the performance and energy impact of 3D memory integration on embedded DSPs
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2009), Samos, Greece, July 20-23, 2009
Customizing wide-SIMD architectures for H.264
PIMP My Many-Core: Pipeline-Integrated Message Passing
Perceptual feature based music classification - A DSP perspective for a new type of application
RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs
Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations
A kernel interleaved scheduling method for streaming applications on soft-core vector processors
EDRA: A Hardware-Assisted Decoupled Access/Execute Framework on the Digital Market - Invited Paper
Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture
A Unifying logic encryption security metric
Architecture-level fault-tolerance for biomedical implants
Towards Efficient HW Acceleration in Edge-Cloud Infrastructures: The SERRANO Approach - Invited Paper
Rethinking memory system design for data-intensive computing
A Multi-objective and Hierarchical Exploration Tool for SoC Performance Estimation
Software fault tolerance for FPUs via vectorization
A novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors
IDF Models for Trace Transformations: A Case Study in Computational Refinement
Coarse grained reconfigurable architectures in the past 25 years: Overview and classification
Efficient end-to-end latency distribution analysis for probabilistic time-triggered systems
ONNX-To-Hardware Design Flow for Adaptive Neural-Network Inference on FPGAs
Task-based parallel H.264 video encoding for explicit communication architectures
The DESERVE project: Towards future ADAS functions
Dynamic Hardware Reconfigurations: Performance Impact for MPEG2
Exploring different execution paradigms in exposed datapath architectures with buffered processing units
Accelerating Automotive Analytics: The M2DC Appliance Approach
Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture
NanoSoftController: A Minimal Soft Processor for System State Control in FPGA Systems
Evaluating System Identification Methods for Predicting Thermal Dissipation of Heterogeneous SoCs
HW/SW Acceleration of Multiple Workloads Within the SERRANO's Computing Continuum - Invited Paper
Evaluating private vs. shared last-level caches for energy efficiency in asymmetric multi-cores
Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme
Data-Driven Regular Reconfigurable Arrays: Design Space Exploration and Mapping
Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems
Improving performance in VLIW soft-core processors through software-controlled scratchpads
Experiences with Cell-BE and GPU for Tomography
Efficient Automated Clock Gating Using CoDeL
NanoStreams: Codesigned microservers for edge analytics in real time
Design space exploration of instruction set customizable MPSoCs for multimedia applications
The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors
TREAM: A Tool for Evaluating Error Resilience of Tree-Based Models Using Approximate Memory
Skeleton-based automatic parallelization of image processing algorithms for GPUs
A Latency-Optimized Hash-Based Digital Signature Accelerator for the Tactile Internet
Special session on "3D chips: Challenges and opportunities"
PoCL-R: A Scalable Low Latency Distributed OpenCL Runtime
3D specific systems design and CAD
BADCO: Behavioral Application-Dependent Superscalar Core model
HyRPF: Hybrid RRAM Prototyping on FPGA
Efficient Post-training Augmentation for Adaptive Inference in Heterogeneous and Distributed IoT Environments
Hardware Cost Estimation for Application-Specific Processor Design
An efficient asymmetric distributed lock for embedded multiprocessor systems
Scalable Instruction-Level Parallelism.
Challenges in automotive cyber-physical systems design
Reconfigurable Platform for Digital Convergence Terminals
An Interrupt Controller for FPGA-based Multiprocessors
A scriptable, standards-compliant reporting and logging extension for SystemC
Dynamic re-vectorization of binary code
Systematic design space exploration for customisable multi-processor architectures
Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units
Reliable Basic Block Energy Accounting
Exploring Multi-core Systems with Lifetime Reliability and Power Consumption Trade-offs
A Data-Driven Approach to Lightweight DVFS-Aware Counter-Based Power Modeling for Heterogeneous Platforms
A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design
Evaluating physically unclonable functions on a large set of FPGAs
Software Passports for Automated Performance Anomaly Detection of Cyber-Physical Systems
Exploiting partial reconfiguration for flexible software debugging
SIDAM: A Design Space Exploration Framework for Multi-sensor Embedded Systems Powered by Energy Harvesting
Compiler-aided methodology for low overhead on-line testing
System-on-Chip deployment with MCAPI abstraction and IP-XACT metadata
A centralized cache miss driven technique to improve processor power dissipation
Admission control and self-configuration in the EPOC framework
A Study of Energy Saving in Customizable Processors
Scalable ASIP implementation and parallelization of a MIMO sphere detector
Real-Time Embedded System for Rear-View Mirror Overtaking Car Monitoring
A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme
A Novel JAVA Processor for Embedded Devices
The Weight-Watcher Service and its Lightweight Implementation
Deep Learning Techniques for Side-Channel Analysis on AES Datasets Collected from Hardware and Software Platforms
Designing and validating access policies to reconfigurable resources in Multiprocessor Systems on chip
Design of Cam-E-leon, a Run-Time Reconfigurable Web Camera
RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors
Embeddings of Task Mappings to Multicore Systems
A GPU implementation for two MIMO-OFDM detectors
Dynamic Network Selection for the Object Detection Task: Why It Matters and What We (Didn't) Achieve
A parameterized dataflow language extension for embedded streaming systems
2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2015, Samos, Greece, July 19-23, 2015
Ranking software components using a modified PageRank algorithm including safety aspects
"Slower than you think" - The evolution of processor and SoC architectures
CLI-based compilation flows for the C language
Energy-aware design space exploration of registerfile for extensible processors
TaBit: A framework for task graph to bitstream generation
Simultaneous reconfiguration of issue-width and instruction cache for a VLIW processor
Generation of Distributed Loop Control
Automatic recognition of computational kernels for platform-dependent code optimizations
Novel energy-efficient scalable soft-output SSFE MIMO detector architectures
Special session on "Fault-tolerant techniques for computer systems, architectures and processors"
Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster
OSR-Lite: Fast and deadlock-free NoC reconfiguration framework
Efficient hardware implementation of data-flow parallel embedded systems
A Process-based Reconfigurable SystemC Module for simulation speedup
k + Neigh : An Energy Efficient Topology Control for Wireless Sensor Networks
TCEMC: A co-design flow for application-specific multicores
ADL-based specification of implementation styles for functional simulators
Structured Scheduling of Recurrence Equations: Theory and Practice
Throughput optimization via cache partitioning for embedded multiprocessors
An instruction set extension for java bytecodes translation acceleration
Identifying communication models in Process Networks derived from Weakly Dynamic Programs
MPSoCBench: A toolset for MPSoC system level evaluation
Tool Integration and Interoperability Challenges of a System-Level Design Flow: A Case Study
ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs
Special session on "aspects of Cyber-Physical Systems"
An analysis of dynamics of CA3b in Hippocampus
Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems
BEE technology overview
Access Interval Prediction for Tightly Coupled Memory Systems
Location-based leakages: New directions in modeling and exploiting
Fault-Tolerant Bus System for Airbag Sensors and Actuators
A template-based methodology for efficient microprocessor and FPGA accelerator co-design
Embedded Context Aware Hardware Component Generation for Dataflow System Exploration
Modeling Scalable SIMD DSPs in LISA
Design space exploration of systolic realization of QR factorization on a runtime reconfigurable platform
Highly-parallel special-purpose multicore architecture for SystemC/TLM simulations
The TEXTAROSSA Approach to Thermal Control of Future HPC Systems
Cobra: A comprehensive bundle-based reliable architecture
Dead-Ends in FPGAs for Database Acceleration
A new generic HLS approach for heterogeneous computing: on the feasibility of high-level synthesis in HSA-compatible systems
Security in Wireless Sensor Networks: Considerations and Experiments
Integrating VLIW Processors with a Network on Chip
FNOCEE: A framework for NoC evaluation by FPGA-based emulation
Exploiting Intra-function Correlation with the Global History Stack
A general model of concurrency and its implementation as many-core dynamic RISC processors
Automatic Search-Space Compression in System-Level Design Space Exploration Using Deep Generative Models
HNOCS: Modular open-source simulator for Heterogeneous NoCs
2012 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XII, Samos, Greece, July 16-19, 2012
High-Radix Addition and Multiplication in the Electron Counting Paradigm Using Single Electron Tunneling Technology
A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs
Breaking the bandwidth wall in chip multiprocessors
FPGA Design Methodology for a Wavelet-Based Scalable Video Decoder
Ultra Fast Cycle-Accurate Compiled Emulation of Inorder Pipelined Architectures
CARROT - A Tool for Fast and Accurate Soft Error Rate Estimation
System Architecture Modeling of an UWB Receiver for Wireless Sensor Network
WhiskEras 2.0: Fast and Accurate Whisker Tracking in Rodents
Extended performance analysis of the time predictable on-demand coherent data cache for multi- and many-core systems
Combining application adaptivity and system-wide Resource Management on multi-core platforms
Processes and actors: Translating Kahn processes to dataflow with firing
Efficient Dynamic Device Placement for Deep Neural Network Training on Heterogeneous Systems
A performance estimation flow for embedded systems with mixed software/hardware modeling
Hardware accelerators for financial applications in HDL and High Level Synthesis
Trends in Low Power Handset Software Defined Radio
Task graph mapping and scheduling on heterogeneous architectures under communication constraints
On-chip dynamic programming networks using 3D-TSV integration
An Embedded Platform with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor Networks
General purpose computing on low-power embedded GPUs: Has it come of age?
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case
A Flash File System to Support Fast Mounting for NAND Flash Memory Based Embedded Systems
Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning Techniques
Instruction-based reuse-distance prediction for effective cache management
LV * : A low complexity lazy versioning HTM infrastructure
Exploiting Locality on the Cell/B.E. through Bypassing
Vehicle-Hardware-In-The-Loop system for ADAS prototyping and validation
DDM-CMP: Data-Driven Multithreading on a Chip Multiprocessor
Closing the Capacity Gap: A Transforming Technique for ReRAM-Friendly NNs
CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey
Scalable Optimal Greedy Scheduler for Asymmetric Multi-/Many-Core Processors
Compiler and System Techniques for soc Distributed Reconfigurable Accelerators
A trace-based scenario database for high-level simulation of multimedia MP-SoCs
Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems
High-level synthesis for the design of FPGA-based signal processing systems
A scalable FFT processor architecture for OFDM based communication systems
Efficient resource management for data centers: the ACTiCLOUD approach
A Hybrid Performance Prediction Approach for Fully-Connected Artificial Neural Networks on Multi-core Platforms
SparseMAX: Accelerating Quantum Neural Networks on GPU Clusters Using Sparse-Matrix Kernels
Mobile visual computing
Phase-Aware CPU Workload Forecasting
Prediction in Dynamic SDRAM Controller Policies
Basic OS Support for Distributed Reconfigurable Hardware
Vector processor customization for FFT
Travel Time-Based Task Mapping for NoC-Based DNN Accelerator
Energy-efficient scheduling of throughput-constrained streaming applications by periodic mode switching
parti-gem5: gem5's Timing Mode Parallelised
A Smart HW-Accelerator for Non-uniform Linear Interpolation of ML-Activation Functions
Area Efficient Fully Programmable Baseband Processors
Improving accuracy of source level timing simulation for GPUs using a probabilistic resource model
QCEDA: Using Quantum Computers for EDA
Post Quantum Cryptography Research Lines in the Italian Center for Security and Rights in Cyberspace
Balanced application-specific processor system for efficient SIFT-feature detection
VGM-Bench: FPU Benchmark Suite for Computer Vision, Computer Graphics and Machine Learning Applications
Efficient runtime support for embedded MPSoCs
Improving TLB energy for java applications on JVM
(When) Do Multiple Passes Save Energy?
Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures
An Overview of Methodologies and Tools in the Field of System-Level Design
FlexCore: Utilizing Exposed Datapath Control for Efficient Computing
CORDIC-based LMMSE equalizer for Software Defined Radio
Design of a unified transport triggered processor for LDPC/turbo decoder
Modeling Loop Unrolling: Approaches and Open Issues
A Cost-Efficient RISC Processor Platform for Real Time Audio Applications
On-Chip Bus Modeling for Power and Performance Estimation
Performance Evaluation of Memory Management Configurations in Linux for an OS-Level Design Space Exploration
Evaluating Large System-on-Chip on Multi-FPGA Platform
The Molen Programming Paradigm
Intellectual Property Protection for Embedded Sensor Nodes
Efficient system design using the Statistical Analysis of Architectural Bottlenecks methodology
Towards power management verification of time-triggered systems using virtual platforms
Automatic port and bus sizing in NoGap
A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size
Transport Triggered Array Processor for Vision Applications
Special session on "programming paradigms for reconfigurable multi-core embedded systems"
SafeDX: Standalone Modules Providing Diverse Redundancy for Safety-Critical Applications
Design of Asynchronous Embedded Processor with New Ternary Data Encoding Scheme
Towards Multi-application Workload Modeling in Sesame for System-Level Design Space Exploration
Programmable and Scalable Architecture for Graphics Processing Units
RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters
The CAPH Language, Ten Years After
FAA+RTS: Designing Fault-Aware Adaptive Real-Time Systems - From Specification to Execution -
Special session on multicore architectures for embedded systems
Pilot design of data-aided carrier synchronization for short burst transmission
Speech enhancement based on a few shapes of speech spectrum
A sidelobes/grating lobes suppression method for ultrawindeband ultrasparse array through-the-wall imaging radar
Hybrid Cramér-Rao bound for joint estimation of target and ionospheric parameters using MIMO-OTH radar
Histogram-based retrieval for encrypted JPEG images
Wireless capsule endoscopy image classification based on vector sparse coding
Financing contract with adverse selection and moral hazard for spectrum trading in cognitive radio networks
Tensor product and perfect shuffling for bit matrix transpose: Bit-interleaver for SDR DVB-T2
Hyperparameter search for deep convolutional neural network using effect factors
Features extraction for PSK signals recognition using nonuniform compressive samples based on high order transformation
Hybrid DCT-Wiener-based interpolation via improved spatial filter
Toward reliable data analysis for Internet of Things by Bayesian dynamic modeling and computation
A Fishervoice based feature fusion method for short utterance speaker recognition
A distributed and virtualized infrastructure for networked multimedia services
A new ultra-wideband high-frequency channel model
An interaural electrode pairing clinical research system for bilateral cochlear implants
CASIA Image Tampering Detection Evaluation Database
A clutter suppression algorithm based on optimal waveform design for sar imaging
CS-based reliable transmission strategy for Wireless Body Area Networks
Efficient digital fingerprints tracing
Speech enhancement and features compensation algorithms for continuous speech recognition
Hashing based feature aggregating for fast image copy retrieval
Energy efficiency optimization in relay-assisted MIMO systems with statistical CSI
A topological feature constraint for nonrigid registration
Individual control of narrowband noise with disturbance
A method to build subliminal channel in streaming media with multiple steganography methods
Constrained adaptation of histogram equalization for robust speech recognition
Parallelizing computer vision algorithms on acceleration technologies: A SIFT case study
Language diarization for conversational code-switch speech with pronunciation dictionary adaptation
Forensics of blurred images based on no-reference image quality assessment
Dynamic spectrum access with goe-location database: A utility-based distributed learning approach
An investigation on DNN-derived bottleneck features for GMM-HMM based robust speech recognition
Sign-assisted precoding for joint decentralized detection and estimation in WSNs
User-friendly visual cryptography with complementary cover images
Exposing the double compression in MP3 audio by frequency vibration
Single-channel speech separation by including spectral structure information within non-negative matrix factorization
Joint detection-decoding of majority-logic decodable nonbinary LDPC coded modulation systems: An iterative noise reduction algorithm
DOA estimation under the coexistence of nonuniform noise and mutual coupling
Wideband subarray beamforming based on subband decomposition
Nonlinear convolution and fourier series coefficients estimate
A relaxation method to articulated trajectory reconstruction from monocular image sequence
An upper-bound on second-order dependency
Recent advances in perceptual H.265/HEVC video coding
OFDM imaging radars spectrum sharing
High precision magnetic ranging for Steam-Assisted Gravity Drainage system
Salient target detection in hyperspectral images using spectral saliency
A new algorithm on hierarchical sparse signal reconstruction
Privacy-preserving data collection and recovery of compressive sensing
An effective doa estimation by exploring the spatial sparse representation of the inter-sensor data ratio model
Blind method of estimating speech transmission index in room acoustics based on concept of modulation transfer function
Non-linear metric learning with multiple features for person re-identification
A geometric framework for stop sign detection
A motion tracking system for hand activity assessment
A novel prewhitening subspace channel estimation for cyclic prefixed MIMO-OFDM systems
A novel worst-case robust beamformer based on interference-plus-noise covariance reconstruction and uncertainty level estimation
Device identification based on H.264 cues
Multiclass feature selection algorithms base on R-SVM
Low-overhead content-adaptive spatial scalability for scalable video coding
Improving deep neural network acoustic models using unlabeled data
Investigation on SAR ground moving target imaging under sparse Bayesian learning framework
Generalized direction detectors in sample-starved environments
Compressive sensing multi-spectral demosaicing from single sensor architecture
Learning optimal features for music transcription
Robust adaptive beamforming for noncircular signal against array steering vector mismatch and interference nonstationarity
Improve equalization-cancellation-based sound localization in noisy reverberant environments using direct-to-reverberant energy ratio
Co-channel CCK transmission overlapped with DME in aeronautical communication
GPU accelerated MIMO ultrasonic imaging using propagation and back-propagation method
LIP movement generation using restricted Boltzmann machines for visual speech synthesis
Trajectory-based human activity recognition with hierarchical dirichlet process hidden Markov models
A new unsupervised convolutional neural network model for Chinese scene text detection
Improved (STEM) cell segmentation with histogram matching image contrast enhancement
Voice conversion using conditional restricted Boltzmann machine
Performance analysis of an enhanced two-stage detector
Detecting synthetic speech using long term magnitude and phase information
Human gesture recognition using orientation segmentation feature on random rorest
Joint non-orthogonal joint diagonalization based on LU decomposition and Jacobi scheme
Overview of AVS broadcasting standard for high definition video
Preamble overhead reduction with IAM-C for channel estimation in OQAM-OFDM systems
A high-efficiency loop delay estimator in digital predistortion subsystem