yusuke1997/dblp-id-title huggingface dataset:
A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware
A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis
Multi-channel Attacks
On Second-Order Differential Power Analysis
Towards Efficient Second-Order Power Analysis
The Simeck Family of Lightweight Block Ciphers
XBX: eXternal Benchmarking eXtension for the SUPERCOP Crypto Benchmarking Framework
Low Complexity Bit-Parallel Finite Field Arithmetic Using Polynomial Basis
Improved Higher-Order Side-Channel Attacks with FPGA Experiments
Curious Case of Rowhammer: Flipping Secret Exponent Bits Using Timing Analysis
The State-of-the-Art in IC Reverse Engineering
Get Your Hands Off My Laptop: Physical Side-Channel Key-Extraction Attacks on PCs
Success through Confidence: Evaluating the Effectiveness of a Side-Channel Attack
Secure Elliptic Curve Implementations: An Analysis of Resistance to Power-Attacks in a DSP Processor
Convolutional Neural Networks with Data Augmentation Against Jitter-Based Countermeasures - Profiling Attacks Without Pre-processing
Templates vs. Stochastic Methods
Exploiting the Power of GPUs for Asymmetric Cryptography
Strong 8-bit Sboxes with Efficient Masking in Hardware
Hardware Accelerator for the Tate Pairing in Characteristic Three Based on Karatsuba-Ofman Multipliers
Side Channel Attack to Actual Cryptanalysis: Breaking CRT-RSA with Low Weight Decryption Exponents
Hyperelliptic Curve Cryptosystems: Closing the Performance Gap to Elliptic Curves
Leak Resistant Arithmetic
A Very Compact Hardware Implementation of the MISTY1 Block Cipher
Templates as Master Keys
A New Framework for Constraint-Based Probabilistic Template Side Channel Attacks
Efficient Elliptic Curve Cryptosystems from a Scalar Multiplication Algorithm with Recovery of the y-Coordinate on a Montgomery-Form Elliptic Curve
A Low-Cost ECC Coprocessor for Smartcards
McBits Revisited
Instruction Set Extensions for Fast Arithmetic in Finite Fields GF( p) and GF(2 m )
Cryptographic Hardware and Embedded Systems - CHES 2013 - 15th International Workshop, Santa Barbara, CA, USA, August 20-23, 2013. Proceedings
Generic Side-Channel Countermeasures for Reconfigurable Devices
Fast Implementation of Elliptic Curve Defined over GF( p m ) on CalmRISC with MAC2424 Coprocessor
Superscalar Coprocessor for High-Speed Curve-Based Cryptography
Flush, Gauss, and Reload - A Cache Attack on the BLISS Lattice-Based Signature Scheme
Reducing the Number of Non-linear Multiplications in Masking Schemes
Challenges for Trusted Computing
Piccolo: An Ultra-Lightweight Blockcipher
Using an RSA Accelerator for Modular Inversion
An Offset-Compensated Oscillator-Based Random Bit Source for Security Applications
High Performance Single-Chip FPGA Rijndael Algorithm Implementations
Genus Two Hyperelliptic Curve Coprocessor
On the Security of PKCS#11
Random Sampling for Short Lattice Vectors on Graphics Cards
Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure?
Optical Fault Induction Attacks
Attacking Unbalanced RSA-CRT Using SPA
High-Speed True Random Number Generation with Logic Gates Only
PRESENT Runs Fast - Efficient and Secure Implementation in Software
New High Entropy Element for FPGA Based True Random Number Generators
Implementation of RSA Algorithm Based on RNS Montgomery Multiplication
Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology
Physical Security Devices for Computer Subsystems: A Survey of Attacks and Defences
2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis
Faster -Arithmetic for Cryptographic Pairings on Barreto-Naehrig Curves
Security Evaluation Schemas for the Public and Private Market with a Focus on Smart Card Systems
Public Key Authentication with One (Online) Single Addition
Energy-Efficient Software Implementation of Long Integer Modular Arithmetic
Symbolic Approach for Side-Channel Resistance Analysis of Masked Assembly Codes
Hardware Acceleration of the Tate Pairing in Characteristic Three
A Design for Modular Exponentiation Coprocessor in Mobile Telecommunication Terminals
Lightweight Cryptography for the Cloud: Exploit the Power of Bitslice Implementation
Smaller Keys for Code-Based Cryptography: QC-MDPC McEliece Implementations on Embedded Devices
A Differential Fault Attack Technique against SPN Structures, with Application to the AES and KHAZAD
A Scalable Architecture for Montgomery Multiplication
A Physical Approach for Stochastic Modeling of TERO-Based TRNG
Masking AES with d+1 Shares in Hardware
Automatic Generation of HCCA Resistant Scalar Multiplication Algorithm by Proper Sequencing of Field Multiplier Operands
Long Modular Multiplication for Cryptographic Applications
Protecting AES with Shamir's Secret Sharing Scheme
Accelerating AES with Vector Permute Instructions
Sliding Windows Succumbs to Big Mac Attack
When Failure Analysis Meets Side-Channel Attacks
Evaluation and Improvement of Generic-Emulating DPA Attacks
Improving SHA-2 Hardware Implementations
The Carry Leakage on the Randomized Exponent Countermeasure
NEON Crypto
Differential Computation Analysis: Hiding Your White-Box Designs is Not Enough
Cryptographic Hardware and Embedded Systems - CHES 2002, 4th International Workshop, Redwood Shores, CA, USA, August 13-15, 2002, Revised Papers
A New Attack with Side Channel Leakage During Exponent Recoding Computations
Fast Multiplication on Elliptic Curves over GF(2 m ) without Precomputation
Sliding Right into Disaster: Left-to-Right Sliding Windows Leak
ARMADILLO: A Multi-purpose Cryptographic Primitive Dedicated to Hardware
Developing a Hardware Evaluation Method for SHA-3 Candidates
A Non-Reversible Insertion Method for Hardware Trojans Based on Path Delay Faults
A Hardware Random Number Generator
PUFKY: A Fully Functional PUF-Based Cryptographic Key Generator
Security Evaluation Against Electromagnetic Analysis at Design Time
A Side-Channel Assisted Cryptanalytic Attack Against QcBits
Block Ciphers That Are Easier to Mask: How Far Can We Go?
Countermeasures against Differential Power Analysis for Hyperelliptic Curve Cryptosystems
Resistance against Differential Power Analysis for Elliptic Curve Cryptosystems
Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs
Unified Point Addition Formulæ and Side-Channel Attacks
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
Leakage Assessment Methodology - A Clear Roadmap for Side-Channel Evaluations
Reversing Stealthy Dopant-Level Circuits
Higher-Order Masking and Shuffling for Software Implementations of Block Ciphers
Compact Ring-LWE Cryptoprocessor
Mutual Information Analysis: How, When and Why?
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
Pipelined Computation of Scalar Multiplication in Elliptic Curve Cryptosystems
Pseudo-random Number Generation on the IBM 4758 Secure Crypto Coprocessor
Evaluation of the Masked Logic Style MDPL on a Prototype Chip
Attacking State-of-the-Art Software Countermeasures-A Case Study for AES
Fast Implementation of Public-Key Cryptography ona DSP TMS320C6201
Switching Blindings with a View Towards IDEA
A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis
Reconciling d+1 Masking in Hardware and Software
A New Side-Channel Attack on RSA Prime Generation
RSA-Past, Present, Future
Sleuth: Automated Verification of Software Power Analysis Countermeasures
Cryptographic Hardware and Embedded Systems - CHES 2000, Second International Workshop, Worcester, MA, USA, August 17-18, 2000, Proceedings
MAME: A Compression Function with Reduced Hardware Requirements
Practical Leakage-Resilient Symmetric Cryptography
DeKaRT: A New Paradigm for Key-Dependent Reversible Circuits
SoC It to EM: ElectroMagnetic Side-Channel Attacks on a Complex System-on-Chip
Cryptographic Hardware and Embedded Systems, First International Workshop, CHES'99, Worcester, MA, USA, August 12-13, 1999, Proceedings
Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage
NICE - New Ideal Coset Encryption
Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm
Strong Machine Learning Attack Against PUFs with No Mathematical Model
Early Propagation and Imbalanced Routing, How to Diminish in FPGAs
A Differential Fault Attack Against Early Rounds of (Triple-)DES
Nanofocused X-Ray Beam to Reprogram Secure Circuits
Fast Evaluation of Polynomials over Binary Finite Fields and Application to Side-Channel Countermeasures
PROOFS 2017, 6th International Workshop on Security Proofs for Embedded Systems, Taipei, Taiwan, September 29th, 2017
PRINTcipher: A Block Cipher for IC-Printing
Two New Techniques of Side-Channel Cryptanalysis
Aspects of Hyperelliptic Curves over Large Prime Fields in Software Implementations
Horizontal Side-Channel Attacks and Countermeasures on the ISW Masking Scheme
A Very High Speed True Random Number Generator with Entropy Assessment
Run-Time Accessible DRAM PUFs in Commodity Devices
Further Results and Considerations on Side Channel Attacks on RSA
MiniPASS: Authentication and Digital Signatures in a Constrained Environment
Fast Truncated Multiplication for Cryptographic Applications
Preventing SPA/DPA in ECC Systems Using the Jacobi Form
A 12 Gbps DES Encryptor/Decryptor Core in an FPGA
Making Password Authenticated Key Exchange Suitable for Resource-Constrained Industrial Control Devices
Hardware Design and Performance Estimation of the 128-bit Block Cipher Crypton
Three-Phase Dual-Rail Pre-charge Logic
Embedded Evaluation of Randomness in Oscillator Based Elementary TRNG
Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051µP
Secret External Encodings Do Not Prevent Transient Fault Analysis
TTS: High-Speed Signatures on a Low-Cost Smart Card
RSA with CRT: A New Cost-Effective Solution to Thwart Fault Attacks
Detection and Correction of Malicious and Natural Faults in Cryptographic Modules
Efficient Implementation of Rijndael Encryption in Reconfigurable Hardware: Improvements and Design Tradeoffs
Side-Channel Attack against RSA Key Generation Algorithms
Efficient Techniques for High-Speed Elliptic Curve Cryptography
Masking vs. Multiparty Computation: How Large Is the Gap for AES?
Fault Sensitivity Analysis
Differential Power Analysis in the Presence of Hardware Countermeasures
The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators
Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller
Hacking in the Blind: (Almost) Invisible Runtime User Interface Attacks
Read-Proof Hardware from Protective Coatings
Template Attacks
Software Implementation of Binary Elliptic Curves: Impact of the Carry-Less Multiplier on Scalar Multiplication
An Analysis of Goubin's Refined Power Analysis Attack
RF-DNA: Radio-Frequency Certificates of Authenticity
A New Bit-Serial Architecture for Field Multiplication Using Polynomial Bases
To Infinity and Beyond: Combined Attack on ECC Using Points of Low Order
Montgomery Exponentiation with no Final Subtractions: Improved Results
Ultra High Performance ECC over NIST Primes on Commercial FPGAs
Recyclable PUFs: Logically Reconfigurable PUFs
Some Security Aspects of the M IST Randomized Exponentiation Algorithm
Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers
Novel Bypass Attack and BDD-based Tradeoff Analysis Against All Known Logic Locking Attacks
An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension
Data Integrity in Hardware for Modular Arithmetic
Pushing the Limits of High-Speed GF(2 m ) Elliptic Curve Scalar Multiplication on FPGAs
Modulus Fault Attacks against RSA-CRT Signatures
On the Simplicity of Converting Leakages from Multivariate to Univariate - (Case Study of a Glitch-Resistant Masking Scheme)
DPA, Bitslicing and Masking at 1 GHz
Compiler Assisted Masking
The Gap Between Promise and Reality: On the Insecurity of XOR Arbiter PUFs
Implementing the Elliptic Curve Method of Factoring in Reconfigurable Hardware
Implementing Cryptographic Pairings on Smartcards
High Speed Cryptoprocessor for η T Pairing on 128-bit Secure Supersingular Elliptic Curves over Characteristic Two Fields
NaCl's Crypto_box in Hardware
Random Register Renaming to Foil DPA
Binary Edwards Curves
MERO: A Statistical Approach for Hardware Trojan Detection
Mutual Information Analysis
Differential Fault Analysis on DES Middle Rounds
A Sound Method for Switching between Boolean and Arithmetic Masking
Entropy Evaluation for Oscillator-Based True Random Number Generators
Who Watches the Watchmen?: Utilizing Performance Monitors for Compromising Keys of RSA on Intel Platforms
Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box
Correlated Extra-Reductions Defeat Blinded Regular Exponentiation
Protections against Differential Analysis for Elliptic Curve Cryptography
CDs Have Fingerprints Too
FPGA Implementations of SPRING - And Their Countermeasures against Side-Channel Attacks
Illusion and Dazzle: Adversarial Optical Channel Exploits Against Lidars for Automotive Applications
Cryptographic Hardware and Embedded Systems - CHES 2016 - 18th International Conference, Santa Barbara, CA, USA, August 17-19, 2016, Proceedings
A Time-Memory Tradeoff Using Distinguished Points: New Analysis & FPGA Results
Increasing the Bitlength of a Crypto-Coprocessor
Improved Cryptanalysis of the DECT Standard Cipher
Efficient Exponentiation for a Class of Finite Fields GF(2 n ) Determined by Gauss Periods
On the Implementation of Unified Arithmetic on Binary Huff Curves
Efficient Subgroup Exponentiation in Quadratic and Sixth Degree Extensions
A Real-World Attack Breaking A5/1 within Hours
Algebraic Side-Channel Attacks Beyond the Hamming Weight Leakage Model
TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks
The EM Side-Channel(s)
Efficient Power and Timing Side Channels for Physical Unclonable Functions
Algebraic Side-Channel Attacks on the AES: Why Time also Matters in DPA
XTR Implementation on Reconfigurable Hardware
Highly Regular Architectures for Finite Field Computation Using Redundant Basis
High-Performance Concurrent Error Detection Scheme for AES Hardware
How to Break Secure Boot on FPGA SoCs Through Malicious Hardware
Modelling the Crypto-Processor from Design to Synthesis
On the Power of Fault Sensitivity Analysis and Collision Side-Channel Attacks in a Combined Setting
A New Class of Invertible Mappings
Power Attack on Small RSA Public Exponent
A Hardware-Assisted Realtime Attack on A5/2 Without Precomputations
Fast Generation of Prime Numbers on Portable Devices: An Update
A Design for a Physical RNG with Robust Entropy Estimators
No Place to Hide: Contactless Probing of Secret Data on FPGAs
Assessment of Hiding the Higher-Order Leakages in Hardware - What Are the Achievements Versus Overheads?
First-Order Side-Channel Attacks on the Permutation Tables Countermeasure
KATAN and KTANTAN - A Family of Small and Efficient Hardware-Oriented Block Ciphers
On the Effectiveness of the Remanence Decay Side-Channel to Clone Memory-Based PUFs
Tradeoffs in Parallel and Serial Implementations of the International Data Encryption Algorithm IDEA
Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings
Attacking RSA-Based Sessions in SSL/TLS
A Scalable and Unified Multiplier Architecture for Finite Fields GF( p ) and GF(2 m )
Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28 - October 1, 2011. Proceedings
Elliptic Curve Scalar Multiplication Combining Yao's Algorithm and Double Bases
Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings
DPA Leakage Models for CMOS Logic Circuits
Programmable and Parallel ECC Coprocessor Architecture: Tradeoffs between Area, Speed and Security
How to Implement Cost-Effective and Secure Public Key Cryptosystems
AES on FPGA from the Fastest to the Smallest
Pushing the Limits of SHA-3 Hardware Implementations to Fit on RFID
Coordinate Blinding over Large Prime Fields
Improved Blind Side-Channel Analysis by Exploitation of Joint Distributions of Leakages
Towards Green Cryptography: A Comparison of Lightweight Ciphers from the Energy Viewpoint
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style
FPGA Design of Self-certified Signature Verification on Koblitz Curves
Hessian Elliptic Curves and Side-Channel Attacks
RFID Noisy Reader How to Prevent from Eavesdropping on the Communication?
A Differential Fault Attack on MICKEY 2.0
Exclusive Exponent Blinding May Not Suffice to Prevent Timing Attacks on RSA
A More Flexible Countermeasure against Side Channel Attacks Using Window Method
High-Speed Key Encapsulation from NTRU
Leakage-Resilient Symmetric Encryption via Re-keying
A Comparative Study of Performance of AES Final Candidates Using FPGAs
A New Low Complexity Parallel Multiplier for a Class of Finite Fields
Practical Key Recovery for Discrete-Logarithm Based Authentication Schemes from Random Nonce Bits
Elliptic Curve Scalar Multiplier Design Using FPGAs
A Low-Power Design for an Elliptic Curve Digital Signature Chip
Encryption with Statistical Self-Synchronization in Synchronous Broadband Networks
Efficient Modular Reduction Algorithm in IF q [x] and Its Application to "Left to Right" Modular Multiplication in IF 2 [x]
An Alternative to Error Correction for SRAM-Like PUFs
Crypto Engineering: Some History and Some Case Studies
Fast Multi-scalar Multiplication Methods on Elliptic Curves with Precomputation Strategy Using Montgomery Trick
Collision Attacks on AES-Based MAC: Alpha-MAC
Analysis and Improvement of the Generic Higher-Order Masking Scheme of FSE 2012
Cryptographic Hardware and Embedded Systems - CHES 2014 - 16th International Workshop, Busan, South Korea, September 23-26, 2014. Proceedings
Integer Factoring Utilizing PC Cluster
A First-Order DPA Attack Against AES in Counter Mode with Unknown Initial Counter
Faster Evaluation of SBoxes via Common Shares
An End-to-End Systems Approach to Elliptic Curve Cryptography
Enhancing Simple Power-Analysis Attacks on Elliptic Curve Cryptosystems
Improved Collision-Correlation Power Analysis on First Order Protected AES
Defeating Countermeasures Based on Randomized BSD Representations
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves
On the Design of Hardware Building Blocks for Modern Lattice-Based Encryption Schemes
Highly Efficient GF(2 8 ) Inversion Circuit Based on Redundant GF Arithmetic and Its Application to AES Design
On Tamper-Resistance from a Theoretical Viewpoint
Smartly Analyzing the Simplicity and the Power of Simple Power Analysis on Smartcards
Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings
Preventing Differential Analysis in GLV Elliptic Curve Scalar Multiplication
Very Compact FPGA Implementation of the AES Algorithm
Extractors against Side-Channel Attacks: Weak or Strong?
A Collision-Attack on AES: Combining Side Channel- and Differential-Attack
Cryptographic Hardware and Embedded Systems - CHES 2001, Third International Workshop, Paris, France, May 14-16, 2001, Proceedings
A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond
Implementation of Elliptic Curve Cryptography with Built-In Counter Measures against Side Channel Attacks
Non-invasive Spoofing Attacks for Anti-lock Braking Systems
Using Bleichenbacher"s Solution to the Hidden Number Problem to Attack Nonce Leaks in 384-Bit ECDSA
Making RSA-PSS Provably Secure against Non-random Faults
On Measurable Side-Channel Leaks Inside ASIC Design Primitives
Design and Implementation of a True Random Number Generator Based on Digital Circuit Artifacts
Hidden Markov Model Cryptanalysis
Simplified Adaptive Multiplicative Masking for AES
Bandwidth-Optimal Kleptographic Attacks
A Proposition for Correlation Power Analysis Enhancement
Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering
Towards One Cycle per Bit Asymmetric Encryption: Code-Based Cryptography on Reconfigurable Hardware
Comparing Elliptic Curve Cryptography and RSA on 8-bit CPUs
An Efficient Method for Random Delay Generation in Embedded Software
EnCounter: On Breaking the Nonce Barrier in Differential Fault Analysis with a Case-Study on PAEQ
Lightweight Coprocessor for Koblitz Curves: 283-Bit ECC Including Scalar Conversion with only 4300 Gates
Four ℚ on FPGA: New Hardware Speed Records for Elliptic Curve Cryptography over Large Prime Characteristic Fields
CHES: Past, Present, and Future
Protecting Embedded Systems - The Next Ten Years
How to Explain Side-Channel Leakage to Your Kids
Experience Using a Low-Cost FPGA Design to Crack DES Keys
An Accurate Probabilistic Reliability Model for Silicon PUFs
ICEPOLE: High-Speed, Hardware-Oriented Authenticated Encryption
Low-Power Elliptic Curve Cryptography Using Scaled Modular Arithmetic
How to Predict the Output of a Hardware Random Number Generator
A Very Compact S-Box for AES
Towards Easy Leakage Certification
A Statistical Model for DPA with Novel Algorithmic Confusion Analysis
Power-Analysis Attacks on an FPGA - First Experimental Results
Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs
Light-Weight Instruction Set Extensions for Bit-Sliced Cryptography
The Outer Limits of RFID Security
Improved Test Pattern Generation for Hardware Trojan Detection Using Genetic Algorithm and Boolean Satisfiability
FPGA Intrinsic PUFs and Their Use for IP Protection
A New Type of Timing Attack: Application to GPS
Power and EM Attacks on Passive 13.56 MHz RFID Devices
Why Attackers Lose: Design and Security Analysis of Arbitrarily Large XOR Arbiter PUFs
High-Performance Scalar Multiplication Using 8-Dimensional GLV/GLS Decomposition
Co- Z Addition Formulæ and Binary Ladders on Elliptic Curves - (Extended Abstract)
Hash Functions and RFID Tags: Mind the Gap
Fides: Lightweight Authenticated Cipher with Side-Channel Resistance for Constrained Hardware
Simple Power Analysis of Unified Code for ECC Double and Add
Improved Side-Channel Analysis of Finite-Field Multiplication
Provably Secure S-Box Implementation Based on Fourier Transform
"Ooh Aah... Just a Little Bit" : A Small Amount of Side Channel Can Go a Long Way
Solving Quadratic Equations with XL on Parallel Architectures
Efficient Implementations of MQPKS on Constrained Devices
Bitline PUF: Building Native Challenge-Response PUF Capability into Any SRAM
GCD-Free Algorithms for Computing Modular Inverses
Generalized Polynomial Decomposition for S-boxes with Application to Side-Channel Countermeasures
Template Attacks in Principal Subspaces
Hardware Implementation of Finite Fields of Characteristic Three
Cryptographic Hardware and Embedded Systems - CHES 2009, 11th International Workshop, Lausanne, Switzerland, September 6-9, 2009, Proceedings
Physical Unclonable Functions and Secure Processors
Error Detection in Polynomial Basis Multipliers over Binary Extension Fields
Breakthrough Silicon Scanning Discovers Backdoor in Military Chip
PRESENT: An Ultra-Lightweight Block Cipher
Montgomery's Multiplication Technique: How to Make It Smaller and Faster
FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control
Offline Hardware/Software Authentication for Reconfigurable Platforms
How to Disembed a Program?
Efficient Hashing Using the AES Instruction Set
Fault Analysis of Stream Ciphers
Efficient Implementation of "Large" Stream Cipher Systems
Power and Fault Analysis Resistance in Hardware through Dynamic Reconfiguration
Secure Conversion between Boolean and Arithmetic Masking of Any Order
Arithmetic Operators for Pairing-Based Cryptography
Collision Search for Elliptic Curve Discrete Logarithm over GF(2 m ) with FPGA
Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints
A DPA Attack against the Modular Reduction within a CRT Implementation of RSA