yusuke1997/dblp-id-title huggingface dataset:
Benchmarking Security Closure of Physical Layouts: ISPD 2022 Contest
RTL-MP: Toward Practical, Human-Quality Chip Planning and Macro Placement
Adding a new dimension to physical design
Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation
On convergence of switching windows computation in presence of crosstalk noise
A minimum cost path search algorithm through tile obstacles
On Ensuring Congruency with Implementation During Emulation and Prototyping
Evaluation of placer suboptimality via zero-change netlist transformations
ITOP: integrating timing optimization within placement
The coming of age of (academic) global routing
ISPD 2013 expert designer/user session (eds)
Interconnect length estimation in VLSI designs: a retrospective
Lagrangian relaxation for gate implementation selection
X-architecture placement based on effective wire models
Impact of local interconnects on timing and power in a high performance microprocessor
Cell-Based Design Methods for Directed Self-Assembly
Reality-driven physical synthesis
Timing driven placement in interaction with netlist transformations
On stress aware active area sizing, gate sizing, and repeater insertion
Coarse-grained Structural Placement for a Synthesized Parallel Multiplier
Device Layer-Aware Analytical Placement for Analog Circuits
Minimizing interconnect energy through integrated low-power placement and combinational logic synthesis
AutoDMP: Automated DREAMPlace-based Macro Placement
From design to design automation
Fast interval-valued statistical interconnect modeling and reduction
A Fast Optimal Double Row Legalization Algorithm
Grid-to-ports clock routing for high performance microprocessor designs
Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis
From 2D to Monolithic 3D: Design Possibilities, Expectations and Challenges
A robust approach to lithography friendly design implementation
Standard CAD Tool-Based Method for Simulation of Laser-Induced Faults in Large-Scale Circuits
A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation
Invited: Trailblazing the Future: Innovative Chip Design in the Era of Pervasive AI
Slicing floorplan design with boundary-constrained modules
Aggressor alignment for worst-case coupling noise
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip
TAU 2013 variation aware timing analysis contest
Physical Verification at Advanced Technology Nodes and the Road Ahead
Electromigration-Aware Interconnect Design
A Designer's Perspective on Timing Closure
Large Language Models for EDA: Future or Mirage?
Nostradamus: a floorplanner of uncertain design
Consistent floorplanning with super hierarchical constraints
Technology, performance, and computer-aided design of three-dimensional integrated circuits
A min-cost flow based min-cost rectilinear Steiner distance-preserving tree construction
Buffer minimization in pass transistor logic
Performance-driven register insertion in placement
Scalable System and Silicon Architectures to Handle the Workloads of the Post-Moore Era
Routing of analog busses with parasitic symmetry
Interconnect Physical Optimization
Thinking outside of the chip
Invited: Automation and Optimization of Heterogeneous Multi-Die Systems
FastTuner: Transferable Physical Design Parameter Optimization using Fast Reinforcement Learning
A framework for layout-level logic restructuring
Linear-time Mixed-Cell-Height Legalization for Minimizing Maximum Displacement
Optimizing the antenna area and separators in layer assignment of multi-layer global routing
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
Enterprise-wide AI-enabled Digital Transformation
Integrated structured placement design methodology in place and route flow
A Lifetime of ICs, and Cross-field Exploration: ISPD 2021 Lifetime Achievement Award Bio
Critical area computation - a new approach
Crosstalk constrained global route embedding
Technology Options for Beyond-CMOS
EWA: exact wiring-sizing algorithm
ePlace-3D: Electrostatics based Placement for 3D-ICs
mFAR: fixed-points-addition-based VLSI placement algorithm
An efficient technique for device and interconnect optimization in deep submicron designs
Commercial CAD: challenges and opportunities
VLSIR - A Modular Framework for Programming Analog & Custom Circuits & Layouts
Design platform for electrical and physical co-design of analog circuits
Combined Modeling of Electromigration, Thermal and Stress Migration in AC Interconnect Lines
Topology constrained rectilinear block packing for layout reuse
A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection
Challenges and Solutions for 3D Fabric: A Foundry Perspective
DUNE: a multi-layer gridless routing system with wire planning
PushPull: short path padding for timing error resilient circuits
DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network
iTimerM: Compact and Accurate Timing Macro Modeling for Efficient Hierarchical Timing Analysis
Physical design for debug: insurance policy for IC's
Performance study of VeSFET-based, high-density regular circuits
Will 22nm be our catch 22!: design and cad challenges
On the way to practical tools for beyond die codesign and integration
Power optimization for clock network with clock gate cloning and flip-flop merging
Advances in 3D integrated circuits
Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages
Session details: Routing in All Forms
Solving hard instances of floorplacement
Scaling Beyond 7nm: Design-Technology Co-optimization at the Rescue
LEO: Line End Optimizer for Sub-7nm Technology Nodes
Accurate power grid analysis with behavioral transistor network modeling
Maximum current estimation considering power gating
Rsyn: An Extensible Physical Synthesis Framework
ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29 - April 1, 2020, delayed to September 20-23, 2020
Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling
Analog Synthesis - The Deterministic Way
Thermal-ADI: a linear-time chip-level dynamic thermal simulation algorithm based on alternating-direction-implicit (ADI) method
Estimation of maximum current envelope for power bus analysis and design
Google Investment in Open Source Custom Hardware Development Including No-Cost Shuttle Program
Congestion and Timing Aware Macro Placement Using Machine Learning Predictions from Different Data Sources: Cross-design Model Applicability and the Discerning Ensemble
Proceedings of the 2016 on International Symposium on Physical Design, ISPD 2016, Santa Rosa, CA, USA, April 3-6, 2016
Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning
3D VLSI: A Scalable Integration Beyond 2D
Invited: How Automotive Functional Safety is Disrupting Digital Implementation
Invited: Physical Design for Advanced 3D ICs: Challenges and Solutions
The Cerebras CS-2: Designing an AI Accelerator around the World's Largest 2.6 Trillion Transistor Chip
Reinforcement Learning for Placement Optimization
Interesting Problems in Physical Synthesis
Dummy fill optimization for enhanced manufacturability
Invited: ISPD 2025 Performance-Driven Large Scale Global Routing Contest
Accelerating Physical Design from 1 to N
Gate sizing with controlled displacement
Proximity Optimization for Adaptive Circuit Design
High accurate pattern based precondition method for extremely large power/ground grid analysis
Proceedings of the 2018 International Symposium on Physical Design, ISPD 2018, Monterey, CA, USA, March 25-28, 2018
Power-aware clock tree planning
A predictive distributed congestion metric and its application to technology mapping
Concept & Research to Revenue: An Entrepreneurial Story
Closing the Gap between Global and Detailed Placement: Techniques for Improving Routability
Security Closure of IC Layouts Against Hardware Trojans
mPL6: a robust multilevel mixed-size placement engine
A Lifetime of Physical Design Automation and EDA Education: ISPD 2022 Lifetime Achievement Award Bio
RC(L) interconnect sizing with second order considerations via posynomial programming
Panel Statement: EDA Needs at Advanced Technology Nodes
Are floorplan representations important in digital design?
Machine Learning Applications in Physical Design: Recent Results and Directions
Variation and litho driven physical implementation system
An enhanced perturbing algorithm for floorplan design using the O-tree representation
Efficient on-line module-level wake-up scheduling for high performance multi-module designs
Kraftwerk: a versatile placement approach
Challenges and Opportunities for Computing-in-Memory Chips
Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees
Practical Mixed-Cell-Height Legalization Considering Vertical Cell Abutment Constraint
Physical design of biological systems
An efficent clustering algorithm for low power clock tree synthesis
Planning for local net congestion in global routing
Efficient design practices for thermal management of a TSV based 3D IC system
Quantifying academic placer performance on custom designs
Fishbone: a block-level placement and routing scheme
ROAD: Routability Analysis and Diagnosis Framework Based on SAT Techniques
Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs
Timing analysis in presence of supply voltage and temperature variations
Rectilinear block packing using O-tree representation
PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs
Towards a VLSI Design Flow Based on Logic Computation and Signal Distribution
Co-optimization of droplet routing and pin assignment in disposable digital microfluidic biochips
Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV
Timing-driven routing for FPGAs based on Lagrangian relaxation
Mapping algorithm for large-scale field programmable analog array
Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century
Introduction to the Panel on EDA Challenges at Advanced Technology Nodes
A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization
The right floorplanning formulations for future chip implementation methodologies (panel discussion - title only)
On simulated annealing in EDA
Proceedings of the 2011 International Symposium on Physical Design, ISPD 2011, Santa Barbara, California, USA, March 27-30, 2011
The Quest for The Ultimate Learning Machine
Architecture and synthesis for multi-cycle communication
Full-Chip Electro-Thermal Coupling Extraction and Analysis for Face-to-Face Bonded 3D ICs
Worst-case delay analysis considering the variability of transistors and interconnects
Timing closure based on physical hierarchy
Improved method of cell placement with symmetry constraints for analog IC layout design
Proceedings of the 2005 International Symposium on Physical Design, ISPD 2005, San Francisco, California, USA, April 3-6, 2005
Invited: Coping with Interconnects
Physical Design Automation for 3D Chip Stacks: Challenges and Solutions
Geometrically parameterized interconnect performance models for interconnect synthesis
Efficient Steiner tree construction based on spanning graphs
Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement
An architectural exploration of via patterned gate arrays
LVFGen: Efficient Liberty Variation Format (LVF) Generation Using Variational Analysis and Active Learning
Reshaping System Design in 3D Integration: Perspectives and Challenges
On pioneering nanometer-era routing problems
Invited: Innovation in Times of Technology Disruption
Physical Design Optimization, From Past to Future
3DIC Design: Challenges and Opportunities in System-of-Chips Integration
Performance driven global routing for standard cell design
Hill Climbing with Trees: Detail Placement for Large Windows
Automated design of digital microfluidic lab-on-chip under pin-count constraints
Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation
Generation of very large circuits to benchmark the partitioning of FPGA
Load-Aware Redundant Via Insertion for Electromigration Avoidance
Immersion and EUV Lithography: Two Pillars to Sustain Single-Digit Nanometer Nodes
A new algorithm for simultaneous gate sizing and threshold voltage assignment
Invited: Shaping the Future of Interconnected Physical Design
Power-driven flip-flop merging and relocation
Rules vs tools: what's the right way to address IC manufacturing complexity?
Faster minimization of linear wirelength for global placement
Hyperspherical Clustering and Sampling for Rare Event Analysis with Multiple Failure Region Coverage
Session details: FPGA Special Session: Advances in Adaptable Heterogeneous Computing and Acceleration for Big Data
Neural Operators for Solving PDEs and Inverse Design
Cross link insertion for improving tolerance to variations in clock network synthesis
An analytical placer for mixed-size 3D placement
Invited: Physical Design for Systolic Array-Based Integrated Circuits
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs
Shield count minimization in congested regions
An efficient sequential quadratic programming formulation of optimal wire spacing for cross-talk noise avoidance routing
Joint Optimization of Sizing and Layout for AMS Designs: Challenges and Opportunities
Proceedings of the 2019 International Symposium on Physical Design, ISPD 2019, San Francisco, CA, USA, April 14-17, 2019
Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs
Signal integrity management in an SoC physical design flow
Logical and physical restructuring of fan-in trees
Ispd2009 clock network synthesis contest
International Symposium on Physical Design, ISPD'14, Petaluma, CA, USA, March 30 - April 02, 2014
IncreMacro: Incremental Macro Placement Refinement
Efficient solution of systems of orientation constraints
Physical Design Challenges and Innovations to Meet Power, Speed, and Area Scaling Trend
Challenges and Opportunities in Automotive, Industrial, and IoT Physical Design
Advances in Carbon Nanotube Technologies: From Transistors to a RISC-V Microprocessor
Simulating frequency-dependent current distribution for inductance modeling of on-chip copper interconnects
Thermal via placement in 3D ICs
Partition-driven standard cell thermal placement
Incremental physical design
Interconnect coupling noise in CMOS VLSI circuits
Multilevel cooperative search: application to the circuit/hypergraph partitioning problem
Routability driven floorplanner with buffer block planning
Keep it straight: teaching placement how to better handle designs with datapaths
Interconnect characteristics of 2.5-D system integration scheme
Analog Layout Automation On Advanced Process Technologies
Ultra-fast interconnect driven cell cloning for minimizing critical path delay
DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment
Pattern sensitive placement for manufacturability
Fear, uncertainty and statistics
Twin binary sequences: a non-redundant representation for general non-slicing floorplan
Multi-scenario buffer insertion in multi-core processor designs
Physical Design Challenges and Solutions for Emerging Heterogeneous 3D Integration Technologies
A semi-persistent clustering technique for VLSI circuit placement
Challenges and Opportunities: From Near-memory Computing to In-memory Computing
Structured ASIC, evolution or revolution?
Proceedings of the 2007 International Symposium on Physical Design, ISPD 2007, Austin, Texas, USA, March 18-21, 2007
GPU/ML-Enhanced Large Scale Global Routing Contest
Skew management of NBTI impacted gated clock trees
An Interactive Physical Synthesis Methodology for High-Frequency FPGA Designs
The ISPD-2011 routability-driven placement contest and benchmark suite
Practicality on placement given by optimality of packing
3D thermal-ADI: an efficient chip-level transient thermal simulator
Proceedings of the 2001 International Symposium on Physical Design, ISPD 2001, Sonoma County, CA, USA, April 1-4, 2001
A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design
Capturing crosstalk-induced waveform for accurate static timing analysis
Theory and Algorithms of Physical Design
Network flow based datapath bit slicing
A global routing method for 2-layer ball grid array packages
Design planning trends and challenges
Force-Directed Placement of VLSI Circuits
Highly efficient gradient computation for density-constrained analytical placement methods
LEGALM: Efficient Legalization for Mixed-Cell-Height Circuits with Linearized Augmented Lagrangian Method
Routing Layer Sharing: A New Opportunity for Routing Optimization in Monolithic 3D ICs
Wot the L: Analysis of Real versus Random Placed Nets, and Implications for Steiner Tree Heuristics
Benchmarking Advanced Security Closure of Physical Layouts: ISPD 2023 Contest
Machine-Learning Enabled PPA Closure for Next-Generation Designs
DREAMPlaceFPGA-PL: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAs
Fine granularity clustering for large scale placement problems
Generating Routing-Driven Power Distribution Networks with Machine-Learning Technique
Clock Tree Construction based on Arrival Time Constraints
A faster implementation of APlace
Co-design for Heterogeneous Integration: A Failure Analysis Perspective
Proceedings of the 1998 International Symposium on Physical Design, ISPD 1998, Monterey, CA, USA, April 6-8, 1998
Floorplan assisted data rate enhancement through wire pipelining: a real assessment
Chip-level area routing
Multilevel generalized force-directed method for circuit placement
Invited: Mapping Two Decades of Innovation: Lessons from 25 Years of ISPD Research
MedPart: A Multi-Level Evolutionary Differentiable Hypergraph Partitioner
Greedy wire-sizing is linear time
Repeater insertion for concurrent setup and hold time violations with power-delay trade-off
Classical floorplanning harmful?
Network flow based multi-way partitioning with area and pin constraints
A two moment RC delay metric for performance optimization
Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints
On wirelength estimations for row-based placement
Session details: Physical Design - Where are we going?
Exact switchbox routing with search space reduction
Slicibility of rectangular graphs and floorplan optimization
Datapath routing based on a decongestion metric
Advances in Adaptable Computing
Bilinear Lithography Hotspot Detection
New strategies for gridded physical design for 32nm technologies and beyond
Geometric programming for circuit optimization
Effects of on-chip inductance on power distribution grid
Modern floorplanning based on fast simulated annealing
Physical optimization for FPGAs using post-placement topology rewriting
IC failure mechanisms yesterday, today, tomorrow: implications from test to DFM
A complete design for power methodology and flow for large ASICs
The Annealing Algorithm revisted
ML-QLS: Multilevel Quantum Layout Synthesis
FastPlace: an analytical placer for mixed-mode designs
A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction
Routability-Driven FPGA Placement Contest
Smart matter systems, an introduction through examples
Obstacle-aware length-matching bus routing
E-beam lithography stencil planning and optimization with overlapped characters
A matrix synthesis approach to thermal placement
Maze routing steiner trees with effective critical sink optimization
Design or manufacturing: which will be best for the future of the semiconductor roadmap?
Device-level early floorplanning algorithms for RF circuits
Automated placement for custom digital designs
Physical design challenges for performance
DREAM-GAN: Advancing DREAMPlace towards Commercial-Quality using Generative Adversarial Learning
100x Evolution of Video Codec Chips
FXT-Route: Efficient High-Performance PCB Routing with Crosstalk Reduction Using Spiral Delay Lines
Getting to the bottom of deep submicron II: a global wiring paradigm
Cell Selection for High-Performance Designs in an Industrial Design Flow
Physical Layout Design of Directed Self-Assembly Guiding Alphabet for IC Contact Hole/via Patterning
Automatic generation of hierarchical placement rules for analog integrated circuits
Introduction of 3D IC Thermal Analysis Flow
Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model
From academic ideas to practical physical design tools
A diagnostic method for detecting and assessing the impact of physical design optimizations on routing
A Cell-Based Row-Structure Layout Decomposer for Triple Patterning Lithography
Challenges of analog/mixed-signal SoC design and verification
Constraint-driven design: the next step towards analog design automation
RF interconnects for communications on-chip
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells
Challenges and opportunities in optimization of automotive electronics
Validating the Redundancy Assumption for HDL from Code Clone's Perspective
High performance and low power design techniques for ASIC and custom in nanometer technologies
Physical design implementation for 3D IC: methodology and tools
Computing Architecture for Large-Language Models (LLMs) and Large Multimodal Models (LMMs)
Security-aware Physical Design against Trojan Insertion, Frontside Probing, and Fault Injection Attacks
Engineering the Future of IC Design with AI
GPU-Accelerated Inverse Lithography Towards High Quality Curvy Mask Generation
Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009
NEMO: a new implicit connection graph-based gridless router with multi-layer planes and pseudo-tile propagation
Invited: Next-Generation Power Integrity Concepts and Applications for Physical Design
Design Flow Parameter Optimization with Multi-Phase Positive Nondeterministic Tuning
Mixed integer programming models for detailed placement
Building Oscillatory Neural Networks: AI Applications and Physical Design Challenges
A faster approximation scheme for timing driven minimum cost layer assignment
A DFM aware, space based router
Benchmarking for large-scale placement and beyond
Multi-project reticle floorplanning and wafer dicing
HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning
On Coloring and Colorability Analysis of Integrated Circuits with Triple and Quadruple Patterning Techniques
Session details: Detailed Routing Contest Results
Improving Chip Design Performance and Productivity Using Machine Learning
Insights and perspectives on physical synthesis
Invited: Streamlining and Automating Routing of Multi-Chiplet Technologies
Advancing Placement
NTUplace2: a hybrid placer using partitioning and analytical techniques
Multi-GHz interconnect effects in microprocessors
Interconnect Optimization Considering Multiple Critical Paths
Analysis, reduction and avoidance of crosstalk on VLSI chips
MIP-based detailed placer for mixed-size circuits
Freedom From Choice and the Power of Models: in Honor of Alberto Sangiovanni-Vincentelli
SRP: simultaneous routing and placement for congestion refinement
A metal-only-ECO solver for input-slew and output-loading violations
Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution
Delay insertion method in clock skew scheduling
Analog Placement Constraint Extraction and Exploration with the Application to Layout Retargeting
Challenges in managing timing and wiring contracts during hierarchical floorplanning and design closure
Transistor level placement for full custom datapath cell design
Optical interconnects: a viable solution for interconnection beyond 10 gbit/sec
Still Benchmarking After All These Years