yusuke1997/dblp-id-title huggingface dataset:
Sapper: a language for hardware-level security policy enforcement
QuFEM: Fast and Accurate Quantum Readout Calibration Using the Finite Element Method
Accelerating Multi-Media Processing by Implementing Memoing in Multiplication and Division Units
METAL: Caching Multi-level Indexes in Domain-Specific Architectures
Multi-objective autotuning of MobileNets across the full software/hardware stack
Dirigent: Enforcing QoS for Latency-Critical Tasks on Shared Multicore Systems
HaRMony: Heterogeneous-Reliability Memory and QoS-Aware Energy Management on Virtualized Servers
Architectural support for address translation on GPUs: designing memory management units for CPU/GPUs with unified address spaces
Software Prefetching
Dual Execution for On the Fly Fine Grained Execution Comparison
Capo: a software-hardware interface for practical deterministic multiprocessor replay
RSSD: defend against ransomware with hardware-isolated network-storage codesign and post-attack analysis
FlexDriver: a network driver for your accelerator
SlicK: slice-based locality exploitation for efficient redundant multithreading
Fingerprinting: bounding soft-error detection latency and bandwidth
Automatically generating and tuning GPU code for sparse matrix-vector multiplication from a high-level representation
Practical automatic loop specialization
Joint local and global hardware adaptations for energy
Efficient type and memory safety for tiny embedded systems
RapidMRC: approximating L2 miss rate curves on commodity systems for online optimizations
Green-Marl: a DSL for easy and efficient graph analysis
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2019, Providence, RI, USA, April 13-17, 2019
Tally: Non-Intrusive Performance Isolation for Concurrent Deep Learning Workloads
Coach: Exploiting Temporal Patterns for All-Resource Oversubscription in Cloud Platforms
Simple Compiler Algorithms to Reduce Ownership Operhead in Cache Coherence Protocols
HerQules: securing programs via hardware-enforced message queues
Architectural Support for Programming Languages and Operating Systems, ASPLOS 2014, Salt Lake City, UT, USA, March 1-5, 2014
Trap-driven Simulation with Tapeworm II
Reducing the Branch Penalty by Rearranging Instructions in Double-Width Memory
Typed Architectures: Architectural Support for Lightweight Scripting
Increasing web server throughput with network interface data caching
Phantom-BTB: a virtualized branch target buffer design
Reconfigurable interconnect infrastructure for multi-FPGA-based adaptive multiprocessing systems
NDPipe: Exploiting Near-data Processing for Scalable Inference and Continuous Training in Photo Storage
SpecInfer: Accelerating Large Language Model Serving with Tree-based Speculative Inference and Verification
Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy
Shasta: A Low Overhead, Software-Only Approach for Supporting Fine-Grain Shared Memory
RAIZN: Redundant Array of Independent Zoned Namespaces
Protecting Page Tables from RowHammer Attacks using Monotonic Pointers in DRAM True-Cells
Split tiling for GPUs: automatic parallelization using trapezoidal tiles
Interference Management for Distributed Parallel Applications in Consolidated Clusters
IANUS: Integrated Accelerator based on NPU-PIM Unified Memory System
The Sparse Abstract Machine
Client-optimized algorithms and acceleration for encrypted compute offloading
A stream compiler for communication-exposed architectures
PatDNN: Achieving Real-Time DNN Execution on Mobile Devices with Pattern-based Weight Pruning
Temporal and SFQ pulse-streams encoding for area-efficient superconducting accelerators
AdaPipe: Optimizing Pipeline Parallelism with Adaptive Recomputation and Partitioning
Empirical Analysis of the Mesa Instruction Set
ADMM-NN: An Algorithm-Hardware Co-Design Framework of DNNs Using Alternating Direction Methods of Multipliers
Computation spreading: employing hardware migration to specialize CMP cores on-the-fly
Rubix: Reducing the Overhead of Secure Rowhammer Mitigations via Randomized Line-to-Row Mapping
Current and Projected Needs for High Energy Physics Experiments (with a Particular Eye on CERN LHC)
Caracal: dynamic translation of runtime environments for GPUs
Pronto: Easy and Fast Persistence for Volatile Data Structures
VISA: Netstation's Virtual Internet SCSI Adapter
EXIST: Enabling Extremely Efficient Intra-Service Tracing Observability in Datacenters
kMVX: Detecting Kernel Information Leaks with Multi-variant Execution
Silent Shredder: Zero-Cost Shredding for Secure Non-Volatile Main Memory Controllers
Unikernels: library operating systems for the cloud
SAC: A Co-Design Cache Algorithm for Emerging SMR-based High-Density Disks
Corundum: statically-enforced persistent memory safety
MVQ: Towards Efficient DNN Compression and Acceleration with Masked Vector Quantization
DCNS: Automated Detection Of Conservative Non-Sleep Defects in the Linux Kernel
APEX: A Framework for Automated Processing Element Design Space Exploration using Frequent Subgraph Analysis
Exploiting Intra-Request Slack to Improve SSD Performance
CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators
Symbiotic Jobscheduling for a Simultaneous Multithreading Processor
Occlum: Secure and Efficient Multitasking Inside a Single Enclave of Intel SGX
Highly Efficient 8-bit Low Precision Inference of Convolutional Neural Networks with IntelCaffe
Flikker: saving DRAM refresh-power through critical data partitioning
SC-DCNN: Highly-Scalable Deep Convolutional Neural Network using Stochastic Computing
Segue & ColorGuard: Optimizing SFI Performance and Scalability on Modern Architectures
Improving software diagnosability via log enhancement
PocketWeb: instant web browsing for mobile devices
Exploring Branch Predictors for Constructing Transient Execution Trojans
Proceedings of the 6th Workshop on General Purpose Processor Using Graphics Processing Units, GPGPU-6, Houston, Texas, USA, March 16, 2013
Mapping esterel onto a multi-threaded embedded processor
Pave: Information Flow Control for Privacy-preserving Online Data Processing Services
Vector Register Design for Polycyclic Vector Scheduling
DCatch: Automatically Detecting Distributed Concurrency Bugs in Cloud Systems
Software-based instruction caching for embedded processors
One Gate Scheme to Rule Them All: Introducing a Complex Yet Reduced Instruction Set for Quantum Computing
Efficiency trends and limits from comprehensive microarchitectural adaptivity
Cascade: A Dependency-aware Efficient Training Framework for Temporal Graph Neural Network
Noise-Adaptive Compiler Mappings for Noisy Intermediate-Scale Quantum Computers
Parendi: Thousand-Way Parallel RTL Simulation
LATR: Lazy Translation Coherence
eHDL: Turning eBPF/XDP Programs into Hardware Designs for the NIC
The Effect of Context Switches on Cache Performance
Neurosurgeon: Collaborative Intelligence Between the Cloud and Mobile Edge
An Analysis of Operating System Behavior on a Simultaneous Multithreaded Architecture
Two-Face: Combining Collective and One-Sided Communication for Efficient Distributed SpMM
MVEDSUA: Higher Availability Dynamic Software Updates via Multi-Version Execution
Locality phase prediction
Proceedings of 4th Workshop on General Purpose Processing on Graphics Processing Units, GPGPU 2011, Newport Beach, CA, USA, March 5, 2011
Generating Configurable Hardware from Parallel Patterns
Pirate: No Compromise Low-Bandwidth VR Streaming for Edge Devices
TinyForge: A Design Space Exploration to Advance Energy and Silicon Area Trade-offs in tinyML Compute Architectures with Custom Latch Arrays
ρ: Relaxed Hierarchical ORAM
NetRen: Service Migration-Driven Network Renascence with Synthesizing Updated Configuration
NumaGiC: a Garbage Collector for Big Data on Big NUMA Machines
ProSE: the architecture and design of a protein discovery engine
Concerto: Automatic Communication Optimization and Scheduling for Large-Scale Deep Learning
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 1, ASPLOS 2023, Vancouver, BC, Canada, March 25-29, 2023
Betweenness centrality on GPUs and heterogeneous architectures
The Performance Advantages of Integrating Block Data Trabsfer in Cache-Coherent Multiprocessors
COIN Attacks: On Insecurity of Enclave Untrusted Interfaces in SGX
SIMDRAM: a framework for bit-serial SIMD processing using DRAM
APR: A Novel Parallel Repacking Algorithm for Efficient GPGPU Parallel Code Transformation
General and efficient locking without blocking
InkTag: secure applications on an untrusted operating system
Chronos: Efficient Speculative Parallelism for Accelerators
uGrapher: High-Performance Graph Operator Computation via Unified Abstraction for Graph Neural Networks
CMC: Video Transformer Acceleration via CODEC Assisted Matrix Condensing
Closing the Window of Vulnerability in Multiphase Memory Transactions
Time-sensitive Intermittent Computing Meets Legacy Software
Clio: a hardware-software co-designed disaggregated memory system
VARAN the Unbelievable: An Efficient N-version Execution Framework
An update-aware storage system for low-locality update-intensive workloads
An evaluation of the TRIPS computer system
Using Registers to Optimize Cross-Domain Call Performance
Q-VR: system-level design for future mobile collaborative virtual reality
CIPHERMATCH: Accelerating Homomorphic Encryption-Based String Matching via Memory-Efficient Data Packing and In-Flash Processing
OpenCL C++
The Effect of the PDP-11 Architecture on Code Generation for Chill
Region scheduling: efficiently using the cache architectures via page-level affinity
Software Profiling for Hot Path Prediction: Less is More
Approximate Storage of Compressed and Encrypted Videos
KernelGPT: Enhanced Kernel Fuzzing via Large Language Models
Power containers: an OS facility for fine-grained power and energy management on multicore servers
Ultra low-cost defect protection for microprocessor pipelines
Clearing the clouds: a study of emerging scale-out workloads on modern hardware
Computational sprinting on a hardware/software testbed
ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 3-7, 1998
Coherency for Multiprocessor Virtual Address Caches
Elastic Cuckoo Page Tables: Rethinking Virtual Memory Translation for Parallelism
Boost Linear Algebra Computation Performance via Efficient VNNI Utilization
An Overview of the Mesa Processor Architecture
LeapIO: Efficient and Portable Virtual NVMe Storage on ARM SoCs
Longnail: High-Level Synthesis of Portable Custom Instruction Set Extensions for RISC-V Processors from Descriptions in the Open-Source CoreDSL Language
Optimization of tele-immersion codes
M3: A Hardware/Operating-System Co-Design to Tame Heterogeneous Manycores
DATS - Data Containers for Web Applications
Understanding and visualizing full systems with data flow tomography
SoD 2 : Statically Optimizing Dynamic Deep Neural Network Execution
Efficient Instrumentation of GPGPU Applications Using Information Flow Analysis and Symbolic Execution
Leveraging the short-term memory of hardware to diagnose production-run software failures
RAP: Resource-aware Automated GPU Sharing for Multi-GPU Recommendation Model Training and Input Preprocessing
Grafu: Unleashing the Full Potential of Future Value Computation for Out-of-core Synchronous Graph Processing
VAULT: Reducing Paging Overheads in SGX with Efficient Integrity Verification Structures
CRUSH: A Credit-Based Approach for Functional Unit Sharing in Dynamically Scheduled HLS
Pocket cloudlets
Lazy Determinism for Faster Deterministic Multithreading
D-SPTF: decentralized request distribution in brick-based storage systems
Tapping into the fountain of CPUs: on operating system support for programmable devices
Promatch: Extending the Reach of Real-Time Quantum Error Correction with Adaptive Predecoding
CutQC: using small Quantum computers for large Quantum circuit evaluations
Neuralink: Fast on-Device LLM Inference with Neuron Co-Activation Linking
Comparison based sorting for systems with multiple GPUs
Self-aware heterogeneous MPSoC with dynamic task scheduling for battery lifetime extension
PUSHtap: PIM-based In-Memory HTAP with Unified Data Storage Format
Cache-Conscious Data Placement
Tradeoffs in transactional memory virtualization
Limoncello: Prefetchers for Scale
Safe and automatic live update for operating systems
Hardware acceleration of transactional memory on commodity systems
STI: Turbocharge NLP Inference at the Edge via Elastic Pipelining
Data Speculation Support for a Chip Multiprocessor
The 801 Minicomputer
CubicleOS: a library OS with software componentisation for practical isolation
Will We Ever have Truly Secure Operating Systems?
ReFlex: Remote Flash ≈ Local Flash
ELI: bare-metal performance for I/O virtualization
The Computational Sprinting Game
Characterizing the Caching and Synchronization Performance of a Multiprocessor Operating System
A comparison of software and hardware techniques for x86 virtualization
GPM: leveraging persistent memory from a GPU
Klotski: Efficient Obfuscated Execution against Controlled-Channel Attacks
The Floating-Point Performance of a Superscalar SPARC Processor
KMA: A Dynamic Memory Manager for OpenCL
Adapting to intermittent faults in multicore systems
Improving Datacenter Efficiency
Formalising CXL Cache Coherence
Keynote address: Sensor network research: emerging challenges for architecture, systems, and languages
Challenges and Opportunities for Systems Using CXL Memory
Snape: Reliable and Low-Cost Computing with Mixture of Spot and On-Demand VMs
Tigr: Transforming Irregular Graphs for GPU-Friendly Graph Processing
Architectural support for hypervisor-secure virtualization
Hop: Heterogeneity-aware Decentralized Training
Finding and Fixing Performance Pathologies in Persistent Memory Software Stacks
OnePerc: A Randomness-aware Compiler for Photonic Quantum Computing
Impact of virtualization on computer architecture and operating systems
Resolved: specialized architectures, languages, and system software should supplant general-purpose alternatives within a decade
TSO_ATOMICITY: efficient hardware primitive for TSO-preserving region optimizations
KNN-Joins Using a Hybrid Approach: Exploiting CPU/GPU Workload Characteristics
The Interaction of Architecture and Operating System Design
ASDR: Exploiting Adaptive Sampling and Data Reuse for CIM-based Instant Neural Rendering
High Speed Switch Scheduling for Local Area Networks
Packing Sparse Convolutional Neural Networks for Efficient Systolic Array Implementations: Column Combining Under Joint Optimization
In-fat pointer: hardware-assisted tagged-pointer spatial memory safety defense with subobject granularity protection
OceanStore: An Architecture for Global-Scale Persistent Storage
IIU: Specialized Architecture for Inverted Index Search
Timestamp snooping: an approach for extending SMPs
Rethinking Java Performance Analysis
StreamGrid: Streaming Point Cloud Analytics via Compulsory Splitting and Deterministic Termination
ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks
Faster Chaitin-like Register Allocation via Grammatical Decompositions of Control-Flow Graphs
NUMA Policies and Their Relation to Memory Architecture
Page Fault Support for Network Controllers
Prolonging 3D NAND SSD lifetime via read latency relaxation
Be CIM or Be Memory: A Dual-mode-aware DNN Compiler for CIM Accelerators
Mixed-mode multicore reliability
Compiling Smalltalk-80 to a RISC
Analysis of Branch Prediction Via Data Compression
Proceedings of the first Workshop on Emerging Technologies for software-defined and reconfigurable hardware-accelerated Cloud Datacenters, ETCD@ASPLOS 2017, Xi'an, China, April 8, 2017
A Computational Temporal Logic for Superconducting Accelerators
HetEC: Architectures for Heterogeneous Quantum Error Correction Codes
Scalable address spaces using RCU balanced trees
Concurrency-Informed Orchestration for Serverless Functions
Synchronization Using Remote-Scope Promotion
Generalizing Reuse Patterns for Efficient DNN on Microcontrollers
Hiding Communication Latency and Coherence Overhead in Software DSMs
Infinity Stream: Portable and Programmer-Friendly In-/Near-Memory Fusion
Design of Novel Analog Compute Paradigms with Ark
A probabilistic pointer analysis for speculative optimizations
GPGPU role within a 500 TFLOPS heterogeneous cluster
Architectural Support for the Efficient Generation of Code for Horizontal Architectures
Pipelining and Performance in the VAX 8800 Processor
Architecture support for disciplined approximate programming
BYOC: A "Bring Your Own Core" Framework for Heterogeneous-ISA Research
Targeting Classical Code to a Quantum Annealer
OctoCache: Caching Voxels for Accelerating 3D Occupancy Mapping in Autonomous Systems
Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs
Transactional lock-free execution of lock-based programs
Accurate and efficient regression modeling for microarchitectural performance and power prediction
A Probabilistic Graphical Model-based Approach for Minimizing Energy Under Performance Constraints
Mapping Very Large Scale Spiking Neuron Network to Neuromorphic Hardware
Performance directed energy management for main memory and disks
VELTAIR: towards high-performance multi-tenant deep learning services via adaptive compilation and scheduling
FLEXPROF: Flexible, Side-Channel-Free Memory Access
StreamBox-HBM: Stream Analytics on High Bandwidth Hybrid Memory
Composing Distributed Computations Through Task and Kernel Fusion
Supporting Descendants in SIMD-Accelerated JSONPath
Access Normalization: Loop Restructuring for NUMA Compilers
Hardware Multithreaded Transactions
An Out-of-Order Execution Technique for Runtime Binary Translators
Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2009, Washington, DC, USA, March 7-11, 2009
Software Support for Speculative Loads
SEER: Super-Optimization Explorer for High-Level Synthesis using E-graph Rewriting
Who goes first? detecting go concurrency bugs via message reordering
Optimizing CNNs on Multicores for Scalability, Performance and Goodput
Protecting Data on Smartphones and Tablets from Memory Attacks
Creating concise and efficient dynamic analyses with ALDA
True IOMMU Protection from DMA Attacks: When Copy is Faster than Zero Copy
Accelerating MATLAB Image Processing Toolbox functions on GPUs
Going Green for Less Green: Optimizing the Cost of Reducing Cloud Carbon Emissions
Performance From Architecture: Comparing a RISC and CISC with Similar Hardware Organization
Challenging the "embarrassingly sequential": parallelizing finite state machine-based computations through principled speculation
SEVeriFast: Minimizing the root of trust for fast startup of SEV microVMs
Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines
MaxK-GNN: Extremely Fast GPU Kernel Design for Accelerating Graph Neural Networks Training
Manitou: a layer-below approach to fighting malware
Evaluation of Architectural Support for Global Address-Based Communication in Large-Scale Parallel Machines
SherLock: unsupervised synchronization-operation inference
Voyager: Input-Adaptive Algebraic Transformations for High-Performance Graph Neural Networks
CommGuard: Mitigating Communication Errors in Error-Prone Parallel Execution
Red-QAOA: Efficient Variational Optimization through Circuit Reduction
ShadowLoad: Injecting State into Hardware Prefetchers
Leveraging stored energy for handling power emergencies in aggressively provisioned datacenters
Statistical Reconstruction of Class Hierarchies in Binaries
Performance Evaluation of Memory Consistency Models for Shared Memory Multiprocessors
FrozenQubits: Boosting Fidelity of QAOA by Skipping Hotspot Nodes
Lucid: A Non-intrusive, Scalable and Interpretable Scheduler for Deep Learning Training Jobs
Orion: A Fully Homomorphic Encryption Framework for Deep Learning
An Analysis of 8086 Instruction Set Usage in MS DOS Programs
Virtual ghost: protecting applications from hostile operating systems
ngAP: Non-blocking Large-scale Automata Processing on GPUs
Mosaic: Exploiting Instruction-Level Parallelism on Deep Learning Accelerators with iTex Tessellation
Virtualized and flexible ECC for main memory
ShapleyIQ: Influence Quantification by Shapley Values for Performance Debugging of Microservices
Probabilistic profiling of stateful data planes for adversarial testing
Application-aware Memory System for Fair and Efficient Execution of Concurrent GPGPU Applications
An Encoding Scheme to Enlarge Practical DNA Storage Capacity by Reducing Primer-Payload Collisions
Voltage Regulator Efficiency Aware Power Management
PowerMove: Optimizing Compilation for Neutral Atom Quantum Computers with Zoned Architecture
Bytecode fetch optimization for a Java interpreter
Catalyzer: Sub-millisecond Startup for Serverless Computing with Initialization-less Booting
KLOCs: kernel-level object contexts for heterogeneous memory systems
AcMC 2 : Accelerating Markov Chain Monte Carlo Algorithms for Probabilistic Models
Reconfigurable Virtual Memory for FPGA-Driven I/O
BOGO: Buy Spatial Memory Safety, Get Temporal Memory Safety (Almost) Free
Hybrid transactional memory
PIFT: Predictive Information-Flow Tracking
Parasol and GreenSwitch: managing datacenters powered by renewable energy
Accelerating cosmological data analysis with graphics processors
LightRidge: An End-to-end Agile Design Framework for Diffractive Optical Neural Networks
A Prediction System Service
FlexAmata: A Universal and Efficient Adaption of Applications to Spatial Automata Processing Accelerators
DoCE: Direct Extension of On-Chip Interconnects over Converged Ethernet for Rack-Scale Memory Sharing
Gloss: Seamless Live Reconfiguration and Reoptimization of Stream Programs
Suppressing ZZ crosstalk of Quantum computers through pulse and scheduling co-optimization
High-density Multi-tenant Bare-metal Cloud
Durable Transactional Memory Can Scale with Timestone
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006
Architecture-Adaptive Code Variant Tuning
Dynamic particle system for mesh extraction on the GPU
Geiger: monitoring the buffer cache in a virtual machine environment
Parallel Computers for Graphics Applications
HALO: Loop-aware Bootstrapping Management for Fully Homomorphic Encryption
Process Coordination with Fetch-and-Increment
SpecPMT: Speculative Logging for Resolving Crash Consistency Overhead of Persistent Memory
Evaluating Design Alternatives for Reliable Communication on High-Speed Networks
CirFix: automatically repairing defects in hardware design code
POD-Attention: Unlocking Full Prefill-Decode Overlap for Faster LLM Inference
The Cache Performance and Optimizations of Blocked Algorithms
Valar: a benchmark suite to study the dynamic behavior of heterogeneous systems
MiniMalloc: A Lightweight Memory Allocator for Hardware-Accelerated Machine Learning
Accelerating phase unwrapping and affine transformations for optical quadrature microscopy using CUDA
An Architecture for the Direct Execution of the Forth Programming Language
Dynamic filtering: multi-purpose architecture support for language runtime systems
Elivagar: Efficient Quantum Circuit Search for Classification
MAERI: Enabling Flexible Dataflow Mapping over DNN Accelerators via Reconfigurable Interconnects
BQSim: GPU-accelerated Batch Quantum Circuit Simulation using Decision Diagram
Energy-efficient computing for wildlife tracking: design tradeoffs and early experiences with ZebraNet
Auto-tuning interactive ray tracing using an analytical GPU architecture model
EDM: An Ultra-Low Latency Ethernet Fabric for Memory Disaggregation
Domain specific run time optimization for software data planes
Carat: Unlocking Value-Level Parallelism for Multiplier-Free GEMMs
PyTorch 2: Faster Machine Learning Through Dynamic Python Bytecode Transformation and Graph Compilation