yusuke1997/dblp-id-title huggingface dataset:
High Frequency TDDB of Reinforced Isolation Dielectric Systems
Investigation of Random Telegraph Noise Characteristics with Intentional Hot Carrier Aging
Modeling of Negative Bias Temperature Instability (NBTI) for Gate-All-Around (GAA) Stacked Nanosheet Technology
A Method to Analyze Aging Effect on ESD Protection Design
Investigation of the endurance of FE-HfO2 devices by means of TDDB studies
Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies
Managing performance-reliability tradeoffs in multicore processors
Origin of physical degradation in AlGaN/GaN on Si high electron mobility transistors under reverse bias stressing
Understanding of Incremental Step Pulse Programming (ISPP) Slope Degradation in 3D NAND and its Band-Engineered Trap Layer Solution
Ruggedness of SiC devices under extreme conditions
Effects of front-end-of line process variations and defects on retention failure of flash memory: Charge loss/gain mechanism
Characterization and Modeling of the Transient Safe Operating Area in LDMOS Transistors
The Enhancement Mechanisms of SiOx Hardness via Manipulation of Oxygen Content
Revealing stresses for plasma induced damage detection in thick oxides
Impact of via geometry and line extension on via-electromigration in nano-interconnects
Drain voltage impact on charge redistribution in GaN-on-Si E-mode MOSc-HEMTs
Experimental Study of Self-Heating Effect in InGaAs HEMTs for Quantum Technologies Down to 10K
Self-heating-aware CMOS reliability characterization using degradation maps
Modeling of Charge Failure Mechanisms during the Short Term Retention Depending on Program/Erase Cycle Counts in 3-D NAND Flash Memories
Correct Extrapolation Model for TDDB of STT-MRAM MgO Magnetic Tunnel Junctions
Advanced Multivariate Outlier Detection for Automotive Road-to-Zero Defect Strategy
Mitigating "No trouble found" component returns
Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node
Cleaved-Gate Ferroelectric FET for Reliable Multi-Level Cell Storage
Frequency dependant gate oxide TDDB model
An Accurate Device-Level Simulation Method to Estimate Cross Sections of Single Event Upsets by Silicon Thickness in Raised Layer
Cycling Induced Trap Generation and Recovery Near the Top Select Gate Transistor in 3D NAND
Sparse and Robust RRAM-based Efficient In-memory Computing for DNN Inference
Long Term NBTI Relaxation Under AC and DC Biased Stress and Recovery
A straightforward electrical method to determine screening capability of GOX extrinsics in arbitrary, commercially available SiC MOSFETs
IEEE International Reliability Physics Symposium, IRPS 2025, Monterey, CA, USA, March 30 - April 3, 2025
Impact of spacer interface charges on performance and reliability of low temperature transistors for 3D sequential integration
Comprehensive study into underlying mechanisms of anomalous gate leakage degradation in GaN high electron mobility transistors
Non-Intrusive Methodologies for Characterization of Bias Temperature Instability in SiC Power MOSFETs
Excellent Reliability performances of a truly 5V nBOXFET for Automotive and IOT applications
Optimization of SCR for High-Speed Digital and RF Applications in 45-nm SOI CMOS Technology
Recent Advances on Electromigration in Cu/SiO2 to Cu/SiO2 Hybrid Bonds for 3D Integrated Circuits
Microscopic Modeling of MgO Barrier Degradation Due to Interface Oxygen Frenkel Defects in Scaled MTJ Toward High-Density STT-MRAM
Challenges and Peculiarities in Developing New Standards for SiC
The Mysterious Bipolar Bias Temperature Stress from the Perspective of Gate-Sided Hydrogen Release
Effect of Off-State Stress on Data-Valid Window Margin for Advanced DRAM Using HK/MG Process Technology
Impact of Mechanical Stress on the Electrical Performance of 3D NAND
A Calibration-Free Synthesizable Odometer Featuring Automatic Frequency Dead Zone Escape and Start-up Glitch Removal
A Novel Approach for Assessing Impact of Temperature Hot-Spots on Chip-Package Interaction Reliability
Investigation of degradation phenomena in GaN-on-Si power MIS-HEMTs under source current and drain bias stresses
Impact of mechanical strain on wakeup of HfO2 ferroelectric memory
Comprehensive Study of SER in FDSOI-Planar: 28 nm to 18 nm Scaling Effect and Temperature Dependence
Electric Field Coupled Molecular Dynamic Insights into Anisotropic Reliability Issues of Monolayer MoS2 Based 2D FETs
Impact of electrode surface modulation on time-dependent dielectric breakdown
Multiscale Modeling and Calibration of Hot-Carrier Stress Degradation in SiGe DRAM Peripheral MOSFETs
ASM-ESD - A comprehensive physics-based compact model for ESD Diodes
Evaluation of Burn-in Technique on Gate Oxide Reliability in Commercial SiC MOSFETs
A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices
Progress and Current Topics of JEDEC JC-70.1 Power GaN Device Quality and Reliability Standards Activity: Or: What is the Avalanche capability of your GaN Transistor?
Transient Leakage Current as a Non-destructive Probe of Wire-bond Electrochemical Failures
Recombination-Driven Interface Trap Generation in SiC MOSFETs Under Constant Voltage and Constant Current Stress
EDA method to address interconnect reliability and reduce overdesign in custom analog designs
Impact of Gate Offset on PBTI of p-GaN Gate HEMTs
CPI reliability and EMI benefit for MIM CAP embedded C4 package
Insight Into HCI Reliability on I/O Nitrided Devices
Operational Workload Impact on Robust Solid-State Storage Analyzed with Interpretable Machine Learning
Comprehensive Modeling and Investigation of Intrinsic Variation Source Fluctuation in 2D-Layered Thin Film Transistors
The Effects of Process Variations and BTI in Packaged FinFET Devices
Latch-Up Over-Current Protection Design with Power Restarted Function
Towards Understanding the Physics of Gate Switching Instability in Silicon Carbide MOSFETs
Wafer-Scale TaOx Device Variability and Implications for Neuromorphic Computing Applications
Proposal to Achieve the Ultimate Holding Voltage Tunability in Silicon Controlled Rectifiers (SCRs) for a Wide Range of ESD Protection Application
Charge Trapping in Irradiated 3D Devices and ICs (Invited)
Failure mode analysis of GaN-HEMT under high temperature operation
Stress Migration Followed by Electromigration Reliability Testing
Concise Analytical Expression for Wunsch-Bell 1-D Pulsed Heating and Applications in ESD Using TLP
A fast and test-proven methodology of assessing RTN/fluctuation on deeply scaled nano pMOSFETs
Impact of RTN on stochastic BTI degradation in scaled metal gate/high-k CMOS technologies
Reliability Studies on Advanced FinFET Transistors of the Intel 4 CMOS Technology
Generation of Hot-Carrier Induced Border and Interface Traps, Investigated by Spectroscopic Charge Pumping
High Resolution Observation of Subsurface Defects at SiO2/4H-SiC Interfaces by Local Deep Level Transient Spectroscopy Based on Time-Resolved Scanning Nonlinear Dielectric Microscopy
New Insights into the Imprint Effect in FE-HfO2 and its Recovery
Reliability Assessment for an In-3D-NAND Approximate Searching Solution
Power and SER Performance of Flip-Flop Cells with Low-Leakage Options
Evolution of GaN HEMT Small-Signal Parameters During Semi-on State for RF/MM-Wave Applications
Reliability Evaluation of Silicon Interconnect Fabric Technology
Reliability-Conscious MOSFET Compact Modeling with Focus on the Defect-Screening Effect of Hot-Carrier Injection
Impact of slow and fast oxide traps on In0.53Ga0.47As device operation studied using CET maps
IEEE International Reliability Physics Symposium, IRPS 2023, Monterey, CA, USA, March 26-30, 2023
Polysilicon resistor stability under voltage stress for safe-operating area characterization
Modulating Competition between Defect Generation and Annihilation in Dielectric Breakdown Showing a Full Range of Reverse, Diminishing, and Forward Area Scaling Trends
Surface Charge Migration in SiC Power MOSFETs Induced by HVDC-H 3 TRB Testing
Analysis of The Hole Trapping Detrapping Component of NBTI Over Extended Temperature Range
A Unified Physics-Based Stochastic Model for EM-Induced Resistance Degradation in BEoL Interconnect Segments
High-temperature and high-field cycling reliability of PZT films embedded within 130 nm CMOS
Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory Computing with up to 16 parallel operations
Charge pumping source-drain current for gate oxide interface trap density in MOSFETs and LDMOS
Hot Carrier Dynamics and Electrical Breakdown Analysis in 2D Transition Metal Dichalcogenide FETs
Circuit delay variability due to wire resistance evolution under AC electromigration
Body Bias Impact on ION Degradation in SiGe-Channel pMOS without Si-Cap for DRAM Periphery
Data Retention Insights from Joint Analysis on BEOL-Integrated HZO-Based Scaled FeCAPs and 16kbit 1T-1C FeRAM Arrays
Reliability Improvement with Optimized BEOL Process in Advanced DRAM
TDDB Reliability Improvement of Low Thermal Budget RMG Stacks
Degradation Monitoring - from a Vision to Reality
Evaluation methodology for current collapse phenomenon of GaN HEMTs
Hot Carrier Reliability Improvement of Thicker Gate Oxide nFET Devices in Advanced FinFETs
A Novel Constant E-Field Methodology for Intrinsic TDDB Lifetime Projection
An Interpretable Predictive Model for Early Detection of Hardware Failure
Reliability Qualification Challenges and Flow for Analog Qualification Test Vehicle
Ambient temperature and layout impact on self-heating characterization in FinFET devices
Constant voltage electromigration for advanced BEOL copper interconnects
On the impact of buffer and GaN-channel thickness on current dispersion for GaN-on-Si RF/mmWave devices
Impact of process variability on BEOL TDDB lifetime model assessment
Introduction to Voltage-Ramping Wafer Level Electromigration Method and Current Exponent Correction Factor for Co-Capping Metal Lines
Temperature and Drift-Aware High-Level PCM-based Array Model for Reliable Hardware IMC Design
Thin-Film FD-SOI BIMOS Topologies for ESD Protection
Redundancy Effect on Electromigration Failure Time in Power Grid Networks
Electromigration Test Chip Experiments from Realistic Power Grid Structures: Failure Trend Comparison and Statistical Analysis
Large-tilt Heavy Ions Induced SEU in Multiple Radiation Hardened 22 nm FDSOI SRAMs
Combining Experiments and a Novel Small Signal Model to Investigate the Degradation Mechanisms in Ferroelectric Tunnel Junctions
Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation
Studying the Impact of Temperature Gradient on Electromigration Lifetime Using a Power Grid Test Structure with On-Chip Heaters
TSV process-induced MOS reliability degradation
eNVM RRAM reliability performance and modeling in 22FFL FinFET technology
Gate Stack Development for Next Gen High Voltage Periphery DRAM Devices
Employing transistor reliability testing as an FA tool for understanding HTOL product BIST failures
All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits
An SEU Cross Section Model Reproducing LET and Voltage Dependence in Bulk Planar and FinFET SRAMs
Hot electron and hot hole induced degradation of SiGe p-FinFETs studied by degradation maps in the entire bias space
Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging
Long-term data for BTI degradation in 32nm IBM microprocessor using HKMG technology
Drain Current Degradation Induced by Charge Trapping/De-Trapping in Fe-FET
On the ESD behavior of a-Si: H based thin film transistors: Physical insights, design and technological implications
Demonstrated Reliability of the Ideal Switch® - Glass Based MEMS Device
Decomposition of Vertical and Lateral Charge Loss in Long-term Retention of 3-D NAND Flash Memory
Nickel Silicide Electromigration on Micro Ring Modulators for Silicon Photonics Technology
Efficient Data Recovery Technique for 3D TLC NAND Flash Memory based on WL Interference
Using Partial Duplication With Compare to Detect Radiation-Induced Failure in a Commercial FPGA-Based Networking System
How to Achieve Moving Current Filament in High Voltage LDMOS Devices: Physical Insights & Design Guidelines for Self-Protected Concepts
Influence of Process Integration on pBTI Degradation in Analog SOI nMOSFETs
Reliability assessment of hafnia-based ferroelectric devices and arrays for memory and AI applications (Invited)
Comparison of variability of HCI induced drift for SiON and HKMG devices
Investigation of data pattern effects on nitride charge lateral migration in a charge trap flash memory by using a random telegraph signal method
Asymmetric Reliability and Universality of Defect Formation in Oxide-Gated Ultra-Thin In2O3Vertical FETs for Monolithic 3-D Integration
Reliability Characterization of HBM featuring $\text{HK}+\text{MG}$ Logic Chip with Multi-stacked DRAMs
How to write a compact reliability model with the Open Model Interface (OMI)
In-Product BTI Aging Sensor for Reliability Screening and Early Detection of Material at Risk
Thermal Neutron Induced Soft Errors in 7-nm Bulk FinFET Node
Cap layer and multi-work-function tuning impact on TDDB/BTI in SOI FinFET devices
Characterization and Modelling of Hot Carrier Degradation in pFETs under Vd>Vg Condition for sub-20nm DRAM Technologies
Positive-bias temperature instability (PBTI) of GaN MOSFETs
A detailed comparison of various off-state breakdown methodologies for scaled Tri-gate technologies
Role of the AlGaN Cap Layer on the Trapping Behaviour of N-Polar GaN MISHEMTs
Comparative Analysis of the Degradation Mechanisms in Logic and I/O FinFET Devices Induced by Plasma Damage
Failure Mechanisms of Cascode GaN HEMTs Under Overvoltage and Surge Energy Events
Can Emerging Computing Paradigms Help Enhancing Reliability Towards the End of Technology Roadmap?
On the Frequency Dependence of Bulk Trap Generation During AC Stress in Si and SiGe RMG P-FinFETs
Defect Spectroscopy in SiC Devices
AC TDDB extensive study for an enlargement of its impact and benefit on circuit lifetime assessment
Physical understanding of low frequency degradation of NMOS TDDB in High-k metal gate stack-based technology. Implication on lifetime assessment
Single-Event Performance of Flip Flop Designs at the 5-nm Bulk FinFET Node at Near-Threshold Supply Voltages
The Role of Materials and Defects on the Electroforming of Metal/Oxide/Metal Stacks
Permanent and Transient Effects of High-Temperature Bias Stress on Room- Temperature $V_{T}$ Drift Measurements in SiC Power MOSFETs
Assessment of critical Co electromigration parameters
New LFN and RTN analysis methodology in 28 and 14nm FD-SOI MOSFETs
Reliability Stressing Control Using Jacobian Feedback Kelvin Measurement on Intel Technologies
Analysis of SSD Acoustic Noise Generation Mechanism depending on NAND operation
Silicon based degradation model for various types of highly integrated MOL resistor devices
Modeling and spectroscopy of ovonic threshold switching defects
On How to Implement Experimentally Obtained Defect Characteristics in SiC Device Simulation
Electric Field Impact on Lateral Charge Diffusivity in Charge Trapping 3D NAND Flash Memory
Considerations in High Voltage Lateral ESD PNP Design
Negative Gate Bias TDDB evaluation of n-Channel SiC Vertical Power MOSFETs
A Novel High Voltage Drain Extended FinFET SCR for SoC Applications
A Generalized Approach to Determine the Switching Lifetime of a GaN FET
The properties, effect and extraction of localized defect profiles from degraded FET characteristics
Investigation of speed sensors accuracy for process and aging compensation
Investigation of Cryogenic Aging in 28 nm CMOS: Suppression of BTI and HCD in Circuits and SRAM
Experimental Implementation of 8.9Kgate Stress Monitor in 28nm MCU Along with Safety Software Library for IoT Device Maintenance
Impact of Sidewall Etching on the Dynamic Performance of GaN-on-Si E-Mode Transistors
Circuit Reliability of $\text{MoS}_{2}$ Channel Based 2D Transistors
Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K
A Ring-Oscillator-Based Degradation Monitor Concept with Tamper Detection Capability
Time Dependent Dielectric Breakdown of Cobalt and Ruthenium Interconnects at 36nm Pitch
Inverse Design of FinFET SRAM Cells
A Methodology to Address RF Aging of 40nm CMOS PA Cells Under 5G mmW Modulation Profiles
Recent Developments in EOTPR Towards a Fully Automated Tool for High Volume Failure Analysis
Radiation Hardened Flip-Flops with low Area, Delay and Power Overheads in a 65 nm bulk process
General Statistical Model for Dielectric Breakdown Including Reverse Area Scaling - The Role of Area-Dependent Dynamic Competition
Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects
Design and Optimization of the NAND ESD Clamp in CMOS Technology
Comparison of Analog and Noise Performance between Buried Channel versus Surface Devices in HKMG I/O Devices
Aging of Current DACs and its Impact in Equalizer Circuits
Performance & reliability of 3D architectures (πfet, Finfet, Ωfet)
Study on Avalanche Uniformity in 1.2KV GaN Vertical PIN Diode with Bevel Edge-Termination
Phase-change memory: Feasibility of reliable multilevel-cell storage and retention at elevated temperatures
Future on-chip interconnect metallization and electromigration
Study of TID effects on one row hammering using gamma in DDR4 SDRAMs
A Novel HV-NPN ESD Protection Device with Buried Floating P-Type Implant
Terrestrial SER characterization for nanoscale technologies: A comparative study
Low Temperature Characterization and Modeling of Hot Carrier Injection in 14 nm Si FinFET
Impact of Edge and Basal Plane Oxidation on the Stability of Oxygen Doped MoS2- RRAM
Silicon Reliability Characterization of Intel's Foveros 3D Integration Technology for Logic-on-Logic Die Stacking
Reliability studies of SiC vertical power MOSFETs
Threshold Voltage Instability of Commercial 1.2 kV SiC Power MOSFETs
Localized thermal effect of sub-16nm FinFET technologies and its impact on circuit reliability designs and methodologies
NanoBridge Technology for Novoaltile FPGA and Memory Applications : (Invited)
Novel Trigger Circuit & SCR Device Co-Engineering Based Local (I/O-VSS & I/O-VDD) ESD Clamp Concepts with Improved Latch-Up Susceptibility, Lower Leakage and Lower Capacitance for Ultra High Speed I/Os
Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices
A microscopic physical description of RTN current fluctuations in HfOx RRAM
Reliability benefits of a metallic liner in confined PCM
Characterization of NMOS-based ESD Protection for Wide-range Pulse Immunity
Signal duration sensitive degradation in scaled devices
Scaling Trends and the Effect of Process Variations on the Soft Error Rate of advanced FinFET SRAMs
Modeling Time and Bias Dependence of Classical HCD Mechanism (Peak ISUB Stress) in n-MOSFETs
28nm UTBB FDSOI product reliability/performance trade-off optimization through body bias operation
Use of Silicon-based Sensors for System Reliability Prediction
Improvement of IGZO BTI for DRAM Cell application by heat treatment and recovery effect
SRAM stability design comprehending 14nm FinFET reliability
Transistor aging and reliability in 14nm tri-gate technology
Understanding Correlation Between Memory Window Closure, Leakage and Read Delay Effects for FEFET Reliability Improvement: Role of IL and FE Traps
Power debug on Fully Integrated Voltage Regulators (FIVR) circuitry introduced deep low power states
Bilayer Passivation Film for Cu Interconnects on Si Interconnect Fabric
Current Scalability Issues in Multi-Bank 5V PMOS ESD structures: Root cause and Design Guideline
AC TDDB Analysis for HK/IL Gate Stack Breakdown and Frequency-dependent Oxygen Vacancy Trap Generation in Advanced nodes FinFET Devices by SILC Spectrum Methodology
Nonlinear Mixed Model and Reliability Prediction for OLED Luminance Degradation
System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents
Performing Machine Learning Based Outlier Detection for Automotive Grade Products
Statistical Analysis of Bit-Errors Distribution for Reliability of 3-D NAND Flash Memories
ESD protection clamp with active feedback and mis-trigger immunity in 28nm CMOS process
Novel methodology for temperature-aware electromigration assessment in on-chip power grid: simulations and experimental validation (Invited)
Machine Learning-Assisted Modeling of AC Stress-Induced Bias Temperature Instability in Oxide Channel Transistors for 2T Gain Cell eDRAM
Multi-Level RTN with Certain Regularities in Oxide-RRAM: Experiments, Defect Dynamics and 3D Multi-Physics Modeling
Current Filament Dynamics Under ESD Stress in High Voltage (Bidirectional) SCRs and It's Implications on Power Law Behavior
Understanding gate metal work function (mWF) impact on device reliability - A holistic approach
Scaling trends and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs
Nanosecond-scale and self-heating free characterization of advanced CMOS transistors utilizing wave reflection
Conduction and Breakdown Mechanisms in Low-k Spacer and Nitride Spacer Dielectric Stacks in Middle of Line Interconnects
Breakthrough Metal/Graphene Interface Phonon Engineering for Reliable Graphene Based-Heat Spreaders
Error elimination ECC by horizontal error detection and vertical-LDPC ECC to increase data-retention time by 230% and acceptable bit-error rate by 90% for 3D-NAND flash SSDs
High-k MIM dielectric reliability study in 65nm node
Percolation defect nucleation and growth as a description of the statistics of electrical breakdown for gate, MOL and BEOL dielectrics
Neutron and Laser Irradiation of Si and Ge Diodes
Layer-to-Layer Endurance Variation of 3D NAND Flash Memory
Reliability challenges in Forksheet Devices: (Invited Paper)
SILC and TDDB reliability of novel low thermal budget RMG gate stacks
Scenario for catastrophic failure in interconnect structures under chip package interaction
Enhanced DRAM Single Bit Characteristics from Process Control of Chlorine
Analysis of RTN Induced by Forward Gate Stress in GaN HEMTs with a Schottky p-GaN Gate
Spectroscopy of SILC trap locations and spatial correlation study of percolation path in the high-κ and interfacial layer
Four point probe ramped voltage stress as an efficient method to understand breakdown of STT-MRAM MgO tunnel junctions
Reliability Analysis of a Delay-Locked Loop Under HCI and BTI Degradation
Hot carrier effects on the RF performance degradation of nanoscale LNA SOI nFETs
Reduced Relative Humidity (RH) Enhances the Corrosion-Limited Lifetime of Self-Heated IC: Peck's equation Generalized
Investigation of Sub-20nm 4th generation DRAM cell transistor's parasitic resistance and scalable methodology for Sub-20nm era
Understanding pulsed-cycling variability and endurance in HfOx RRAM
A Study on the Origin of Dynamic Charge Loss of Next Generation DRAM Cell Array Transistor
Write-error-rate of Spin-Transfer-Torque MRAM (Invited)
Assessing the pre-breakdown carriers' multiplication in SiC power MOSFETs by soft gamma radiation and its correlation to the Terrestrial Cosmic Rays failure rate data as measured by neutron irradiation
Comprehensive device and product level reliability studies on advanced CMOS technologies featuring 7nm high-k metal gate FinFET transistors
Impact of forming gas annealing on the degradation dynamics of Ge-based MOS stacks
Voltage Acceleration of Power NLDMOS Hot Carrier Degradation
2.5D/3D Packaging and Reliability: New Frontiers, Old Paradigms, and Opportunities
Scaling Trends and Bias Dependence of SRAM SER from 16-nm to 3-nm FinFET
Machine Vision Observation, Artificial Intelligence Pattern Recognition, Protective Circuit Design, Characterization of Multiple Materials, and Nano-Structural Analysis for Investigating InGaN Green Light Emitting Diode Degradation in a Salty Water Vapor Environment
Dynamic On-State Resistance in SiC MOSFETs
Understanding and modeling transient threshold voltage instabilities in SiC MOSFETs
Investigation of Positive Bias Temperature Instability in advanced FinFET nodes