yusuke1997/dblp-id-title huggingface dataset:
Tailoring a Reconfigurable Platform to SHA-256 and HMAC through Custom Instructions and Peripherals
A reconfigurable architecture for searching optimal software code to implement block cipher permutation matrices
Microchannels for thermal management in FPGAs
Survey on and re-evaluation of wide adder architectures on FPGAs
Fast Implementation of a Bio-inspired Model for Decentralized Gathering
Keynote 2 - Past, current, and future of faster, cheaper, better
Efficient and flexible NoC-based group communication for secure MPSoCs
Keynote 3 - Extreme scale challenges: Can reconfigurable computing come to the rescue?
FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks
Decision Tree Based FPGA-Architecture for Texture Sea State Classification
An image comparison circuit design
Adaptive controller using runtime partial hardware reconfiguration for unmanned aerial vehicles (UAVs)
Fault mitigation by means of dynamic partial reconfiguration of Virtex-5 FPGAs
A flexible implementation of the PSO algorithm for fine- and coarse-grained reconfigurable embedded systems
An Application Example of a Run-Time Reconfigurable Embedded System
Acceleration of Fractal Image Compression Using the Hardware-Software Co-design Methodology
FPGA-Based Educational Platform for Wireless Transmission Using System Generator
FPGA Implementation of an Elliptic Curve Processor Using the GLV Method
Experimental Power and Performance Evaluation of CAESAR Hardware Finalists
Design space exploration of coarse-grain reconfigurable DSPs
The Impact of Global Routing on the Performance of NoCs in FPGAs
An efficient structure for run-time configuration of synthesis and channelizer filter banks
Using shadow pointers to trace C pointer values in FPGA circuits
LinkBlaze: Efficient global data movement for FPGAs
Self-Adaptive Network Interface (SANI): Local Component of a NoC Configuration Manager
An FPGA-in-the-loop approach for HDL motor controller verification
Phenox: Zynq 7000 based quadcopter robot
A Scalable and Low Power DCNN for Multimodal Data Classification
Dynamic Constant Reconfiguration for Explicit Finite Difference Option Pricing
A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures
A highly flexible reconfigurable system on a Xilinx FPGA
Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures
Keynote 1 - Education is not learning facts, but training the mind to think
Synchronized-transfer-level design methodology applied to hardware matrix multiplication
Parallelization of the estimation algorithm of the 3D structure tensor
A run-length encoding co-processor for retinal image texture analysis
Enhanced Correlation Power Analysis Using Key Screening Technique
A fault attack on a hardware-based implementation of the secure hash algorithm SHA-512
Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures
An Integrated Prime-Field ECDLP Hardware Accelerator with High-Performance Modular Arithmetic Units
Optimal weight storage improves fault tolerance of SOMs
Design and analysis of layered coarse-grained reconfigurable architecture
Multiprocessor Task Migration Implementation in a Reconfigurable Platform
DPL on Stratix II FPGA: What to Expect?
A Block-Based Open Source Approach for a Reconfigurable Virtual Instrumentation Platform Using FPGA Technology
HGum: Messaging framework for hardware accelerators
Tuning Coarse-Grained Reconfigurable Architectures towards an Application Domain
An efficient application-specific instruction-set processor for packet classification
On the Influence of the FPGA Compiler Optimization Options on the Success of the Horizontal Attack
BFLOAT MLP Training Accelerator for FPGAs
Automatic Type Inference for Resynthesis on Hardware Description Languages
A New Approach to Implement Discrete Wavelet Transform Using Collaboration of Reconfigurable Elements
A sparse VLIW instruction encoding scheme compatible with generic binaries
Statistical performance of the ARM cortex A9 accelerator coherency port in the xilinx zynq SoC for real-time applications
Accelerating Key In-memory Database Functionality with FPGA Technology
2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2013, Cancun, Mexico, December 9-11, 2013
Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area
Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling
Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems
ARM+FPGA platform to manage solid-state-smart transformer in smart grid application
Polynomial multipliers for fully homomorphic encryption on FPGA
Power modelling for saving strategies in coarse grained reconfigurable systems
An FFT/IFFT Design versus Altera and Xilinx Cores
Improving FPGA placement with a self-organizing map
Singular Value Decomposition Hardware for MIMO: State of the Art and Custom Design
Net reordering and multicommodity flow based global routing for FPGAs
Configurable-System-on-Programmable-Chip for Power Electronics Control Applications
FPGA-based CPG Robot Locomotion Modulation Using a Fuzzy Scheme and Visual Information
Integrating Logic Analyzer Functionality into VHDL Designs
Parameterised FPGA reconfigurations for efficient test set generation
VIS2SOUND on Reconfigurable Hardware
A versatile UDP/IP based PC ↔ FPGA communication platform
A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA
PAMS: Pattern Aware Memory System for embedded systems
Developing an MMX Extension for the MicroBlaze Soft Processor
A QCA Implementation of a Configurable Logic Block for an FPGA
FPGA-based design and implementation of direct torque control for induction machines
Heterogeneous computer architectures: An image processing pipeline for optical metrology
Runtime mapping and scheduling for energy efficiency in heterogeneous multi-core systems
Exploiting architecture description language for diverse IP synthesis in heterogeneous MPSoC
Low Area Overhead Custom Buffering for FFT
Improving FPGA NoC performance using virtual cut-through switching technique
Network Processing in Multi-core FPGAs with Integrated Cache-Network Interface
A novel physical defects recovery technique for FPGA-IP cores
Measuring and Predicting Temperature Distributions on FPGAs at Run-Time
Design-for-Diversity for Improved Fault-Tolerance of TMR Systems on FPGAs
Overloaded CDMA bus topology for MPSoC interconnect
Configuring Field-Programmable Robot Arrays
Modeling and Analyzing of Blocking Time Effects on Power Consumption in Network-on-Chips
Architecture Based on Array Processors for Data-Dependent Superimposed Training Channel Estimation
Enabling partial reconfiguration for coprocessors in mixed criticality multicore systems using PCI express single-root I/O virtualization
High-Speed Stochastic Processes Generator Based on Sum-of-Sinusoids for Channel Emulation
Evaluation of White-Box and Grey-Box Noekeon Implementations in FPGA
Cross-Correlation Cartography
Hardware/software infrastructure for ASIC commissioning and rapid system prototyping
Pruning the Design Space for Just-in-Time Processor Customization
A high-efficiency runtime reconfigurable IP for CNN acceleration on a mid-range all-programmable SoC
Floating point CORDIC-based architecture for powering computation
Dynamic management of a partial reconfigurable hardware architecture for pedestrian detection in regions of interest
A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using TMD-MPI
400 Gbps energy-efficient multi-field packet classification on FPGA
Parallel Processor for 3D Recovery from Optical Flow
Exploring the problems of placement and mapping in NoC-based reconfizurable systems
Hobbit - Smaller but faster than a dwarf: Revisiting lightweight SHA-3 FPGA implementations
Designing customized ISA processors using high level synthesis
VHDL core for 1024-point radix-4 FFT computation
An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases
Flexible and low-cost HSM based on non-volatile FPGAs
Full hardware implementation of the Post-Quantum Public-Key Cryptography Scheme Round5
A Pthreads-Based MPI-1 Implementation for MMU-Less Machines
FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter Search
FPGA Implementation of OFDM Transceiver for a 60GHz Wireless Mobile Radio System
Digital Talking Book Player for the Visually Impaired Using FPGAs
Dynamic Self-Rescheduling of Tasks over a Heterogeneous Platform
Comparison of direct and switch-based inter-FPGA routing interconnect for multi-FPGA systems
Accelerating low rank matrix completion on FPGA
Analysis of Parallel Sorting Algorithms in K-best Sphere-Decoder Architectures for MIMO Systems
Autotuning high-level synthesis for FPGAs using OpenTuner and LegUp
Design and implementation of hardware cache mechanism and NIC for column-oriented databases
Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs
A Novel Rekeying Message Authentication Procedure Based on Winternitz OTS and Reconfigurable Hardware Architectures
FPGA implementation of the EKF algorithm for localization in mobile robotics using a unified hardware module approach
Hardware implementation of the GPS authentication
High-level synthesis of a genomic database search engine
FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier
Stochastically computing discrete Fourier transform with reconfigurable digital fabric
Protecting the NOEKEON Cipher against SCARE Attacks in FPGAs by Using Dynamic Implementations
Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000
Energy-efficient large-scale matrix multiplication on FPGAs
Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs
ReCompAc: Reconfigurable compute accelerator
Decrypting HDCP-protected Video Streams Using Reconfigurable Hardware
A hybrid design for high performance large-scale sorting on FPGA
Mesh Mapping Exploration for Coarse-Grained Reconfigurable Array Architectures
A secure self-reconfiguring architecture based on open-source hardware
Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs
Design and implementation of a constant-time FPGA accelerator for fast elliptic curve cryptography
GF(2 m ) Arithmetic Modules for Elliptic Curve Cryptography
MARC: A Many-Core Approach to Reconfigurable Computing
Network on Chip Architectures for High Performance Digital Signal Processing Using a Configurable Core
Versatile FPGA Architecture for Skein Hashing Algorithm
NoC-based hardware function libraries for running multiple DSP algorithms
Embedding FPGA overlays into configurable Systems-on-Chip: ReconOS meets ZUMA
HW/SW co-design experimental framework using configurable SoCs
Towards a type 0 hypervisor for dynamic reconfigurable systems
Mission control: A performance metric and analysis of control logic for pipelined architectures on FPGAs
Data-rate-aware FPGA-based acceleration framework for streaming applications
On providing scalable self-healing adaptive fault-tolerance to RTR SoCs
Implementation, Simulation and Validation of Dispatching Algorithms for Elevator Systems
Implementation of a Parallel Algorithm for Protein Pairwise Alignment Using Reconfigurable Computing
Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture
Dynamic run-time hardware/software scheduling for 3D reconfigurable SoC
Scalability Studies of the BLASTn Scan and Ungapped Extension Functions
FPGA-Based Online Detection of Multiple-Combined Faults through Information Entropy and Neural Networks
Efficient Technique for the FPGA Implementation of the AES MixColumns Transformation
An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding
Breeze computing: A just in time (JIT) approach for virtualizing FPGAs in the cloud
A Reconfiguration-Aware Floorplacer for FPGAs
Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface
Observing the Randomness in RO-Based TRNG
Implementing a Protected Zone in a Reconfigurable Processor for Isolated Execution of Cryptographic Algorithms
A Framework for 2.5D NoC Exploration Using Homogeneous Networks over Heterogeneous Floorplans
Power efficiency benchmarking of a partially reconfigurable, many-tile system implemented on a Xilinx Virtex-6 FPGA
Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space Exploration
Towards the Implementation of Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture
Leveraging Firmware in Multichip Systems to Maximize FPGA Resources: An Application of Self-Partial Reconfiguration
Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing
Pragma based parallelization - Trading hardware efficiency for ease of use?
TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte traces
Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platforms
A hardware generator for factor graph applications
UCORE: Reconfigurable Platform for Educational Purposes
On how to efficiently accelerate brain network analysis on FPGA-based computing system
A hierarchical parallel evolvable hardware based on network on chip
ROS-Enabled Hardware Framework for Experimental Robotics
Towards FPGA-assisted spark: An SVM training acceleration case study
System Services for Reconfigurable Hardware Acceleration in Mobile Devices
GPU vs FPGA: Example Application on White Light Interferometry
Rotated parallel mapping: A novel approach for mapping data parallel applications on CGRAs
Run-Time Reconfiguration for Automatic Hardware/Software Partitioning
SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-Chips
Preliminary Steps Towards Protein Folding Prediction Using Reconfigurable Computing
FPGA-based reconfigurable unit for image filtering in frequency domain
FPGA Based Acceleration of Decimal Operations
Adaptive single-event effect mitigation for dependable processing systems
A Reconfigurable Computing System Based on a Cache-Coherent Fabric
Lightweight and compact solutions for secure reconfiguration of FPGAs
TURTLE: A Low-Cost Fault Injection Platform for SRAM-based FPGAs
An improved hardware design for matrix inverse based on systolic array QR decomposition and piecewise polynomial approximation
High-speed FPGA Implementation of the NIST Round 1 Rainbow Signature Scheme
High-Level Executable Models of Reactive Real-Time Systems with Logic-Labelled Finite-State Machines and FPGAs
Automatic cache partitioning and time-triggered scheduling for real-time MPSoCs
Hardware/software implementation of a discrete cosine transform algorithm using SystemC
Trusted display and input using screen overlays
Reconfigurable Block Floating Point Processing Elements in Virtex Platforms
A power-efficient real-time architecture for SURF feature extraction
Analysis and Enhancement of Ring Oscillators Based Physical Unclonable Functions in FPGAs
High-speed implementation of bcrypt password search using special-purpose hardware
Fault tolerance in neural networks: Neural design and hardware implementation
A design assembly framework for FPGA back-end acceleration
Mapping of a Real-Time Object Detection Application onto a Configurable RISC/Coprocessor Architecture at Full HD Resolution
Dynamically Reconfigurable Split Cache Architecture
Key Research Issues for Reconfigurable Network-on-Chip
Automatic Construction of Large-Scale Regular Expression Matching Engines on FPGA
dcTPM: A Generic Architecture for Dynamic Context Management
Eight ways to put your FPGA on fire - A systematic study of heat generators
Quartz: a framework for correct and efficient reconfigurable design
Realizing Arbitrary-Precision Modular Multiplication with a Fixed-Precision Multiplier Datapath
Modeling and Formal Control of Partial Dynamic Reconfiguration
Explicitly isolating data and computation in high level synthesis: the role of polyhedral framework
Very low resource table-based FPGA evaluation of elementary functions
Efficient deep neural network acceleration through FPGA-based batch processing
Efficient Congestion-Oriented Custom Network-on-Chip Topology Synthesis
Hybrid energy-aware reconfiguration management on Xilinx Zynq SoCs
Design of an attention detection system on the Zynq-7000 SoC
FPGA implementation of a reconfigurable image encryption system
Reconfigurable Systems and Flexible Programming for Hardware Design, Verification and Software Enablement for System-on-a-Chip Architectures
Design and implementation of an embedded microprocessor compatible with IL language in accordance to the norm IEC 61131-3
Identifying Merge-Beneficial Software Kernels for Hardware Implementation
Automatic Synthesis of Multiprocessor Systems from Parallel Programs under Preemptive Scheduling
Design and exploration of routing methods for NoC-based multicore systems
FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems
A Two Level Architecture for High Throughput DCT-Processor and Implementing on FPGA
Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition
Forward-Secure Content Distribution to Reconfigurable Hardware
Almost-Zero Logic Implementation of Troika Hash Function on Reconfigurable Devices
An Improved GF(2) Matrix Inverter with Linear Time Complexity
A High-Performance Reconfigurable Computing architecture using a magnetic configuration memory
IPSecco: A lightweight and reconfigurable IPSec core
The Hamiltonian-based odd-even turn model for adaptive routing in interconnection networks
Minerva: Automated hardware optimization tool
Mixed-Signal Spin/Charge Reconfigurable Array for Energy-Aware Compressive Signal Processing
Keynote 1 - Growing the ReConFig community through python, zynq and hardware overlays
Improving FPGA Design and Evaluation Productivity with a Hardware Performance Monitoring Infrastructure
PolyNOC - A polymorphic thread simulator for NoC communication based embedded systems
FPGA-based circular hough transform with graph clustering for vision-based multi-robot tracking
Enabling dynamic and partial reconfiguration in Xilinx SDSoC
A hardware-assisted proof-of-concept for secure VoIP clients on untrusted operating systems
Multi-FPGA prototyping environment: Large benchmark generation and signals routing
Keynote 2 - FPGAs in the datacenter - A software view
An FPGA Implementation of Linear Kernel Support Vector Machines
Compact trie forest: Scalable architecture for IP lookup on FPGAs
Keynote 1 - From data to information to flow
Place Reservation technique for online task placement on a multi-context heterogeneous reconfigurable architecture
Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis
Thread shadowing: On the effectiveness of error detection at the hardware thread level
Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA
Keynote - It's about time
Parallel FPGA-Based Implementation of Recursive Sorting Algorithms
Evaluation of CGRA architecture for real-time processing of biological signals on wearable devices
Reconfigurable Real-Time Video Pipelines on SRAM-based FPGAs
Fixed-Point CORDIC-Based QR Decomposition by Givens Rotations on FPGA
A framework for efficient rapid prototyping by virtually enlarging FPGA resources
Agile SMT-Based Mapping for CGRAs with Restricted Routing Networks
Implementation of Simulation Algorithms in FPGA for Real Time Simulation of Electrical Networks with Power Electronics Devices
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow
Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS
Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs
Resource Efficient Arithmetic Effects on RBM Neural Network Solution Quality Using MNIST
Linking Formal Description and Simulation of Runtime Reconfigurable Systems
Composite Look-Up Table Gaussian Pseudo-Random Number Generator
An effective window based legalization algorithm for FPGA placement
High Throughput and Low Latency LZ4 Compressor on FPGA
TCD-NPE: A Re-configurable and Efficient Neural Processing Engine, Powered by Novel Temporal-Carry-deferring MACs
A scalable array for Cellular Genetic Algorithms: TSP as case study
MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs
FPGA based nodes for sub-microsecond synchronization of cyber-physical production systems on high availability ring networks
Horizontal address-bit DPA against montgomery kP implementation
TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays
High Performance Implementation of a Public Key Block Cipher - MQQ, for FPGA Platforms
Online heavy hitter detector on FPGA
FSM merging and reduction for IP cores watermarking using Genetic Algorithms
Numerically efficient and biophysically accurate neuroprocessing platform
International Conference on ReConFigurable Computing and FPGAs, ReConFig 2016, Cancun, Mexico, November 30 - Dec. 2, 2016
Hotspot Mitigation Using Dynamic Partial Reconfiguration for Improved Performance
Complex Multiply Accumulate Cells for the Square Kilometre Array Correlators
Disparity Map Hardware Accelerator
A delay-based PUF design using multiplexer chains
Side-channel power analysis of different protection schemes against fault attacks on AES
Using type transformations to generate program variants for FPGA design space exploration
A model design of a 2560-channel neural spike detection platform
Adaptive and reconfigurable fault-tolerant routing method for 2D Networks-on-Chip
Design and Implementation of a Multi-standard Interleaver for 802.11a, 802.11n, 802.16e & DVB Standards
3D-LeukoNoC: A dynamic NoC protection
Using Partial Reconfiguration in an Embedded Message-Passing System
A lightweight speculative and predicative scheme for hardware execution
An FPGA arithmetic logic unit for computing scalar multiplication using the half-and-add method
2018 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2018, Cancun, Mexico, December 3-5, 2018
A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops
Design and Implementation of Adaptive Viterbi Decoder for Using A Dynamic Reconfigurable Processor
Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures
Hardware Task-Status Manager for an RTOS with FIFO communication
A scalable ECC processor implementation for high-speed and lightweight with side-channel countermeasures
Universal Wavelet Kernel Implementation Using Reconfigurable Hardware
Communication Interface Generation For HW/SW Architecture In The STARSoC Environment
Dual fixed-point CORDIC processor: Architecture and FPGA implementation
Scalable modular hardware platform for FPGA based industrial radar flowmeters
Reconfigurable Microkernel-based RTOS: Mechanisms and Methods for Run-Time Reconfiguration
A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests
Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA
Memory optimisation for hardware induction of axis-parallel decision tree
Loop Transformations to Reduce the Dynamic FPGA Recon?guration Overhead
Energy-efficient Median filter on FPGA
A Highly Parallel FPGA Implementation of Sparse Neural Network Training
Reconfigurable coprocessors synthesis in the MPEG-RVC domain
An a-FPGA architecture for relative timing based asynchronous designs
Exploiting hardware abstraction for hybrid parallel computing framework
The R2-D2 toolchain - Automated porting of safety-critical applications to FPGAs
Exploring Non-Traditional Hardware-Software Interaction
FPGA-based Pipeline Architecture to Transform Cartesian Images into Foveal Images by Using a new Foveation Approach