yusuke1997/dblp-id-title huggingface dataset:
Improvements in Automated IC Socket Pin Defect Detection
Using Tester Repeatability to Improve Yields
High-Resolution Analog Measurement on Mixed-Signal LSI Tester
A Densely Integrated High Performance CMOS Tester
Test and Repair of Non-Volatile Commodity and Embedded Memories (NAND Flash Memory)
Power-scan chain: design for analog testability
The Importance of Fault Simulation
Fully automated semiconductor operating condition testing
Self-repair of uncore components in robust system-on-chips: An OpenSPARC T2 case study
Test vector decompression via cyclical scan chains and its application to testing core-based designs
Hardware Dithering: A Run-Time Method for Trojan Neutralization in Wireless Cryptographic ICs
Bayesian Models of Tests : Some Practical Results
FAST Technology In-Circuit Testing Considerations
Subband filtering scheme for analog and mixed-signal circuit testing
Embedded Memory Test and Repair: Infrastructure IP for SOC Yield
ISDN, Analog or Digital Test ?
Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study
Test Generation for FET Switching Circuits
An On-Chip Sensor For Online Monitoring of HCI-Induced Aging In Integrated Analog Circuits
On-Line Testable Logic Desgin for FPGA Implementation
Automatic Multitone Alternate Test Generation For RF Circuits Using Behavioral Models
High-Voltage and High-Power PLL Diagnostics using Advanced Cooling and Emission Images
A Unified Interface for Scan Test Generation Based on STIL
Testability-Aware Low Power Controller Design with Evolutionary Learning
Testing the Tester: What Broke? Where? When? Why?
Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique
The testability features of the 3rd generation ColdFire family of microprocessors
Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study
Hierarchical Test Generation Based on Delayed Propagation
Functional Tests for Scan Chain Latches
An approach to testing 200 ps echo clock to output timing on the double data rate synchronous memory
Design and Realization of an Accurate Built-In Current Sensor for On-Line Power Dissipation Measurement and I DDQ Testing
Using STIL to describe embedded core test requirements
DART: Dependable VLSI test architecture and its implementation
Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimation
Power Side-Channel Vulnerabilities of a RISC-V Cryptography Accelerator Integrated into CVA6 via Core-V eXtension Interface (CV-X-IF)
A new procedure for weighted random built-in self-test
Pattern Recognition of Bit Fail Maps
How are failure modes, defect types and test methods changing for 32nm/28nm technologies and beyond?
Production Tests Coverage Analysis in the Simulation Environment
Application and Demonstration of a Digital Test Core: Optoelectronic Test Bed and Wafer-level Prober
HALT: Bridging the Gap Between Theory and Practice
The ITC test compression shootout
Knowledge Acquisition for ATE Diagnosis
A Fault-Driven, Comprehensive Redundancy Algorithm for Repair of Dynamic RAMs
User's Requirements for Automated Handling in Computer Manufacturing and Board Test
Low power compression of incompatible test cubes
Frequency detection-based boundary-scan testing of AC coupled nets
Learning A Wafer Feature With One Training Sample
Implementation of Parallelsite Test on an 8Bit Configurable Microcontroller
A lifecycle approach to design validation is it necessary? Is it feasible?
Keynote address Thursday: Addressing semiconductor industry needs: Defining the future through creative, exciting research
An Application of Photoconductive Switch for High-Speed Testing
Debug methodology for the McKinley processor
Predicting Test Accuracy for Analog In-Circuit Testing
Development of an ATE test cell for at-speed characterization and production testing
Efficient testing of hierarchical core-based SOCs
A New Probe Card Technology Using Compliant Microsprings TM
RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement
Influence-Directed Explanations for Deep Convolutional Networks
Delay Monitoring Under Different PVT Corners for Test and Functional Operation
Moving from mixed signal to RF test hardware development
Structural test in a board self test environment
Test Bin Entitlement: Yield Outlier Detection using Die Area and LLM based Bin-Grouping
The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits
Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-Based Proactive Defect Prediction
Clock Signal Distribution Network for High-Speed Testers
Error Detection with Latency in Sequential Circuits
Combinational logic synthesis for diversity in duplex systems
A Solution to Test Data Acquisition and Management
Interconnect open defect diagnosis with minimal physical information
A Comprehensive Learning-Based Flow for Cell-Aware Model Generation
Efficient test mode selection and insertion for RTL-BIST
Concurrent Error Detection in Linear Analog and Switched-Capacitor State Variable Systems Using Continuous Checksums
Automatic classification of bridge defects
New R&R Methodology in Semiconductor Manufacturing Electrical Testing
Open Architecture ATE: Prospects and Problems
What is DFM & DFY and Why Should I Care ?
Trouble With Scan
IS-FPGA : a new symmetric FPGA architecture with implicit scan
Digital Signal Processing Considerations in Filter-Codec Testing
Modeling and Simulation of Delay Faults in CMOS Logic Circuits
Transmission Line Simulation for Testing ISDN Devices
A Simplified Algorithm for Testing Microprocessors
On applying scan based structural test for designs with dual-edge triggered flip-flops
Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors
A Test Methodology to Support an ASEM MCM Foundry
BIST and Delay Fault Detection
On the evaluation of process-fault tolerance ability of CMOS integrated circuits
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits
Fault Simulation in a Pipelined Multiprocessor System
Using a Relational Database to Develop a Statistical Quality Control System for ATE
Robust test methods applied to functional design verification
Enabling GSM/GPRS/EDGE EVM testing on low cost multi-site testers
Test cost reduction through performance prediction using virtual probe
Detection of "Undetectable" Faults Using I DDQ Testing
Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation
Embedded Memory Diagnosis: An Industrial Workflow
Board Diagnosis: A Current Assessment and Direction for Future Improvement
SAT-based State Justification with Adaptive Mining of Invariants
Fault Modelling for Functional Primitives
Test data analytics - Exploring spatial and test-item correlations in production test data
Avionics Simulation Environment
VLSI Self-Testing Based on Syndrome Techniques
Non-scan design for testability for synchronous sequential circuits based on conflict analysis
Fault Modeling and Testing of Memristor-Based Spiking Neural Networks
Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality
Synthesis of nonintrusive concurrent error detection using an even error detecting function
Balancing Structured and Ad-hoc Design for Test: Testing of the PowerPC 603 TM Microprocessor
Language Driven Analytics for Failure Pattern Feedforward and Feedback
qFD: Coherent and Depolarizing Fault Diagnosis for Quantum Processors
Path coverage based functional test generation for processor marginality validation
The Effects of Backdriving Integrated Circuits : An Accurate Electro-Thermal Model
An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation
Tester Independent Support Software System (TISSS)
Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie
ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption
2009 IEEE International Test Conference, ITC 2009, Austin, TX, USA, November 1-6, 2009
A MEMS based device interface board
Hardware Overhead Reduction for Memory BIST
A New Testability Measure for Digital Circuits
Attainable Accuracy of Autocalibrating VLSI Test Systems
Flexible, High-Performance Pin Electronics Implementation
Device-Aware Test for Threshold Voltage Shifting in FeFET
Two-Pattern Test Capabilities of Autonomous TPG Circuits
The Advanced Test System Architecture Provides Fast and Accurate Test for a High Resolution ADC
Diagnosis method based on ΔIddq probabilistic signatures: experimental results
Incorporating Physical Design-for-Test into Routing
Low cost test point insertion without using extra registers for high performance design
Dynamic microgrids - A potential solution for enhanced resiliency in distribution systems
Workstation Based Parallel Test Generation
Issues on Test Optimization with Known Good Dies and Known Defective Dies - A Statistical Perspective
On Path-Delay Testing in a Standard Scan Environment
A Sequential Test Generator with Explicit Elimination of Easy-to-Test Faults
Functional Level Test Generation for Complex Digital Systems
Static property checking using ATPG vs. BDD techniques
Random and Systematic Defect Analysis Using IDDQ Signature Analysis for Understanding Fails and Guiding Test Decisions
On-Line Testing for VLSI
Cache-resident self-testing for I/O circuitry
System Test Cost Modelling Based on Event Rate Analysis
Practical methods for extending ATE to 40 and 50Gbps
Design for Testability of Mixed Signal Integrated Circuits
Design and Testing of the On-Ramps to the Information Superhighway
The Implementation of Pseudo-Random Memory Tests on Commercial Memory Testers
Event qualification: a gateway to at-speed system testing
CMOS Bridging Fault Detection
DFT, DFY, and DFR; Which One(s) Do You Worry About?
A Boundary Scan Test Controller for Hierarchical BIST
Future Challenges for MEMS Failure Analysis
Introduction ITC 1996 Lecture Series on Unpowered Opens Testing
I DDQ testing because 'zero defects isn't enough': a Philips perspective
Fault Modeling and Test Effectiveness Evaluation for VLSI Circuits
An analysis of the delay defect detection capability of the ECR test method
A Statistical Calculation of Fault Detection Probabilities By Fast Fault Simulation
FPGA-based universal embedded digital instrument
Localizing Open Interconnect Defects using Targeted Routing in FPGA's
A Production-Oriented Multiplexing System for Testing above 2.5 Gbps
Is the concern for soft-error overblown?
Current Signatures: Application
Modeling for Structured System Interconnect Test
Testability evaluation of sequential designs incorporating the multi-mode scannable memory element
A Self-Test Circuit for Evaluating Memory Sense-Amplifier Signal
Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures
Testing Techniques for Hardware Security
Data flow within an open architecture tester
A high density small size RF test module for high throughput multiple resource testing
Automatic test signal generation for mixed-signal integrated circuits using circuit partitioning and interval analysis
Design and Test: What Will It Take to Tie the Knot?
Can model-based and case-based expert systems operate together?
Hierarchical Test Generation Using Precomputed Tests for Modules
Avoiding Unknown States When Scanning Mutually Exclusive Latches
LFSR Reseeding as a Component of Board Level BIST
Innovative Video RAM Testing
Use models for extending IEEE 1687 to analog test
Testing silicon TV tuners on ATE without TV signal generator
Parallel Programming Significantly Improves Production NVM Wafer Sort
Optimizing Product Profitability - The Test Way
Verifying flying prober performance - fitness is survival
Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects
The Role of Pattern Recognition in VLSI Testing
Video DAC/ADC Dynamic Testing
Experimental evaluation of concurrent fault simulation algorithms on scalable, hierarchically defined test cases
Benefits of Boundary-Scan to In-Circuit Test
Deterministic Versus Random Testing
Representing Boundary Scan Tests with the EDIF Test View
Automatic Testing of Speech Synthesis Integrated Circuits
Compression-Aware ATPG
Board Testing
Demystifying automotive safety and security for semiconductor developer
Systematic approach for trim test time optimization: Case study on a multi-core RF SOC
Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing
In-Circuit Testability Factors: Shoot With a Rifle
QTAG: A Standard for Test Fixture Based I DDQ /I SSQ Monitors
Eclipse Dynamic Probe Card: A Novel Approach for Wafer-Level Photonic Testing with Automated Fiber Array Unit Alignment
Armenia: Communicating to World Community in Electronic Test and Design
A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits
Faster-than-at-speed test for increased test quality and in-field reliability
Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon
Chiplet Interconnect Test and Repair
ADWIL: A Zero-Overhead Analog Device Watermarking Using Inherent IP Features
Processing of Test Data between Design and Testing
A scalable test strategy for network-on-chip routers
TEACH: Outlier Oriented Testing of Analog/Mixed-Signal Circuits Using One-class Hyperdimensional Clustering
Changepoint-based anomaly detection in a core router system
Multiple Output Pass Networks: Design and Testing
A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead
Charge Based Transient Current Testing (CBT) for Submicron CMOS SRAMs
Using BIST Control for Pattern Generation
Designs for Diagnosability and Reliability in VLSI Systems
A New Methodology For ADC Test Flow Optimization
Fault Modeling for the Testing of Mixed Integrated Circuits
Hardware in loop testing of an insulin pump
Scan Cell Segmentation Based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs
Use of Embedded Sensors for Built-In-Test of RF Circuits
A Graph Theoretic Approach to Partial Scan Design by K-Cycle Elimination
Automatic timing margin failure location analysis by CycleStretch method
Ramp testing of ADC transition levels using finite resolution ramps
A goal tree based high-level test planning system for DSP real number models
HD 2 BIST: a hierarchical framework for BIST scheduling, data patterns delivering and diagnosis in SoCs
On Coosing a Hardware Descriptive Language for Digital Systems Testing/Verification
Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model
Reconfigurable Hardware for Pseudo-Exhaustive Test
Synthesis and Retiming for the Pseudo-Exhaustive BIST of Synchronous Sequential Circuits
Algorithmic Read Resistance Trim for Improving Yield and Reducing Test Time in MRAM
Non-Deterministic DUT Behavior During Functional Testing of High Speed Serial Busses: Challenges and Solutions
Fault Location Algorithms for Repairable Embedded
Adapting an SoC to ATE Concurrent Test Capabilities
A Flexible Approach to Data Collection for Component Test Systems
Testability, the Achilles Heel of Design
Testing a multichip package for a consumer communications application
Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information
A Symbolic Simulation-Based ANSI/IEEE Std 1149.1 Compliance Checker and BSDL Generator
A Closer Look at Testing Costs
Pre-silicon Formal Verification of JTAG Instruction Opcodes for Security
Stuck-Open and Transition Fault Testing in CMOS Complex Gates
A New Validation Methodology Combining Test and Formal Verification for PowerPC TM Microprocessor Arrays
Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic Systems Assembly Using Real-Coded Genetic Algorithms
Closing The Gap Between Process Development and Mixed Signal Design and Testing
Clock Gate Test Points
International Test Conference - Title Page
Deep Learning-based IC Monitoring
Design, Fabrications and Use of Mixed-Signal IC Testability Structures
PiRA: IC authentication utilizing intrinsic variations in pin resistance
Analog Circuit Test using Transfer Function Coe .cient Estimates
VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration
Bridging Defects Resistance Measurements in a CMOS Process
Boundary-Scan Testing of Power/Ground Pins
A software development kit for dependable applications in embedded systems
A Study of Per-Pin Timing Jitter Scope
In search of Vmin for dynamic power managmenet and reliable operation in mission mode
Arrangement of latches in scan-path design to improve delay fault coverage
Low Cost High Accuracy Stimulus Generator for On-chip Spectral Testing
On Reducing Wrapper Boundary Register Cells in Modular SOC Testing
Full-speed field-programmable memory BIST architecture
Diagnosis in Modern Design to Volume - The Tip of the Iceberg
Test Vector Generation for Linear Analog Devices
Proceedings International Test Conference 1984, Philadelphia, PA, USA, October 1984
Analysis of error-masking and X-masking probabilities for convolutional compactors
Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs
Structural Testing of High-Speed Serial Buses: A Case Study Analysis
Shadow write and read for at-speed BIST of TDM SRAMs
Test point insertion using functional flip-flops to drive control points
A Novel Approach for Testing Memories Using a Built-In Self Testing Technique
Characteristic States and Cooperative Game Based Search for Efficient Sequential ATPG and Design Validation
Simulation Requirements for Vectors in ATE Formats
Accelerated Compact Test Set Generation for Three-State Circuits
High-speed fixture interconnects for mixed-signal IC testing
An Expert System for VLSI Tester Diagnostics
Design for Testability of a 32-Bit Microprocessor, the TX1
Test and Diagnosis Solution for Functional Safety
Software Testing: Opportunity and Nightmare
Method for Diagnosing Clock Jitter Using FPGA
Test engineers role in QML
IC-PEPR: PEPR Testing Goes Intra-Cell
PROTEUS : A Logic Verification System for Combinational Circuits
On techniques for handling soft errors in digital circuits
Design Verification of a High Density Computer Using IEEE 1149.1
Predicting device performance from pass/fail transient signal analysis data
An Automated Methodology to Diagnose Geometric Defect in the EEPROM Cell
A methodology for systematic built-in self-test of phase-locked loops targeting at parametric failures
Enhancing Board Functional Self-Test by Concurrent Sampling
An Effective Methodology for Automated Diagnosis of Functional Pattern Failures to Support Silicon Debug
Two-level compression through selective reseeding
Designing State Machines for Testability
A Jitter Injection Module for Production Test of 52-Gbps PAM4 Signal Interfaces
A scalable architecture for VLSI test
A New Test Method for the Large Current Magnetic Sensors
Process-tolerant test with energy consumption ratio
MEMS Design And Verification
AAA: Automated, On-ATE AI Debug of Scan Chain Failures
2006 IEEE International Test Conference, ITC 2006, Santa Clara, CA, USA, October 22-27, 2006
A2DTest: A complete integrated solution for on-chip ADC self-test and analysis
Digital bus faults measuring techniques
Automatic Pattern Generation for Diagnosis of Wiring Interconnect Faults
Testability Enhancement for Behavioral Descriptions Containing Conditional Statements
IntegraTEST: The New Wave in Mixed-Signal Test
Delivering security by design in the Internet of Things
New Techniques for High Speed Analog Testing
How are we going to test SOC's on a board?
A Simulation-Based JTAG ATPG Optimized for MCMs
Stuck Fault and Current Testing Comparison Using CMOS Chip Test
The Growth of Application Specific Integrated Circuits: Opportunities and Challenges
A Hybrid Design of Maximum-Length Sequence Generators
Production Testing of PCM (Digital) Audio Circuits
Simulation Pattern Capturing System for Design Verification Using a Dynamic High Speed Functional Tester (DHSFT)
Testing in a high volume DSM Environment
Built-In Test Strategy for Next Generation Military Avionic Hardware
Curriculum for a Rapidly Changing Technology
A Computationally Efficient Method for Accurate Spectral Testing without Requiring Coherent Sampling
Tests of Hermetically Sealed LSI/VLSI Devices by Laser Photoexcitation Logic Analysis
Low-Cost ATE PinElectronics for Multigigabit-per-Second At-Speed Test
Cost Effective Outliers Screening with Moving Limits and Correlation Testing for Analogue ICs
A leakage control system for thermal stability during burn-in test
IC Diagnosis: Industry Issues
ASIC Verification: Second Generation Systems and Solutions
Channel Masking Synthesis for Efficient On-Chip Test Compression
Conquering Testability Problems by Combining In-Circuit and Functional Techniques
3.5Gsps MIPI C-PHY Receiver Circuit for Automatic Test Equipment
Testing Finite State Machines Based on a Structural Coverage Metric
Is ITC Bored with Board Test?
DIBPro: Automatic Diagnostic Program Generation Tool
Automated Socket Anomaly Detection through Deep Learning
Generic, orthogonal and low-cost March Element based memory BIST
Goal-Directed Vector Generation Using Sample ICs
Business constraints drive test decisions planning, partnerships and success
Techniques for Improved Testability in the IBM ES/9370 System
Test Pattern Aware Streaming Fabric-based Scan Test Methodology
Estimation of defect-free IDDQ in submicron circuits using switch level simulation
A Built-In Test Methodology for VLSI Data Paths
A New Framework for RTL Test Points Insertion Facilitating a "Shift-Left DFT" Strategy
Hardware Compression Speeds on Bitmap Fail Display
HIST: A Methodology for the Automatic Insertion of a Hierarchical Self Test
The desire-friction ratio of Adaptive test
Holistic Validation Pattern Generation for IEEE 1687 and Streaming Scan Networks
A Fast, Statistical, Machine-learning Approach for Automotive Semiconductor Test Reduction
Errors in testing
Options for High-Volume Test of Multi-GB/s Ports
An Accelerated Testing Technique for Plastic Package Devices Using a Sequential Combination of Pressure Cooker and 85/85 (PCTH)
Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach
Structuring STIL for Incremental Test Development
Multi-function multi-GHz ATE extension using state-of-the-art FPGAs
Low cost ultra-pure sine wave generation with self calibration
Self-Test Chip to System Level Approaches
Using Verilog simulation libraries for ATPG
A high-resolution jitter measurement technique using ADC sampling
Supplying Known-Good Die for MCM Applications Using Low-Cost Embedded Testing
Security solutions in the first-generation Zynq All-Programmable SoC
Prototype Testing Simplified by Scannable Buffers and Latches
"Concatenable Polydividers": Bit-Sliced LFSR Chips for Board Self-Test
A novel RF self test for a combo SoC on digital ATE with multi-site applications
Testability Features of the 68HC16Z1
SoC Yield Improvement: Redundant Architectures to the Rescue?
Rapid prototyping of time-based PDIT for substrate networks [MCM]
Test Point Insertion that Facilitates ATPG in Reducing Test Time and Data Volume
Progressive Bridge Identification
Breaking the complexity spiral in board test
DS-LFSR: A New BIST TPG for Low Heat Dissipation
The Omnitest System: A No-Generate, No-Compile, Interactive Test Methodology
Faults in Microprogrammed and Hardwired Control
Fast EVM Tuning of MIMO Wireless Systems Using Collaborative Parallel Testing and Implicit Reward Driven Learning
On the Design and Test of Asynchronous Macros Embedded in Synchronous Systems
A heuristic for thermal-safe SoC test scheduling
Successful Implementation of SPC in Semiconductor Final Test
Next-Generation Devices and Networks Bring Opportunities and Challenges
Test compression and logic BIST at your fingertips
Relating Yield Models to Burn-In Fall-Out in Time
Massively Parallel Validation of High-Speed Serial Interfaces using Compact Instrument Modules
Wave+: An easy-to-use vector generation language for compilers
Delay fault testing of IP-based designs via symbolic path modeling