yusuke1997/dblp-id-title huggingface dataset:
RF BIST and test strategy for the receive part of an RF transceiver in CMOS technology
Extension of power supply impedance emulation method on ATE for multiple power domain
Calibration-enabled scalable built-in current sensor compatible with very low cost ATE
Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries
Hardware Trojan detection using path delay order encoding with process variation tolerance
A Single-Event Latchup setup for high-precision AMS circuits
Application-aware lifetime estimation of power devices
Dependability of Future Edge-AI Processors: Pandora's Box
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
Automatic test pattern generation for resistive bridging faults
DfT support for launch and capture power reduction in launch-off-capture testing
Extending post-silicon coverage measurement using time-multiplexed FPGA overlays
Testing of High Resolution ADCs Using Lower Resolution DACs via Iterative Transfer Function Estimation
Self-Programmable Shared BIST for Testing Multiple Memories
Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults
PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information
Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates
Identification of Failing Flip-Flops with Triangular Test Response Compaction
On-chip Electromigration Sensor for Silicon Lifecycle Management of Nanoscale VLSI
Testing Scouting Logic-Based Computation-in-Memory Architectures
Applying March Tests to K-Way Set-Associative Cache Memories
DERRIC: A Tool for Unified Logic Diagnosis
Viterbi-Based Efficient Test Data Compression
Retention-Aware Test Scheduling for BISTed Embedded SRAMs
Pipelined parallel test structure for mixed-signal SoCs
Analysis and Mitigation of Radiation Effects in SRAM-based Register Files
16th European Test Symposium, ETS 2011, Trondheim, Norway, May 23-27, 2011
Learning-Based Characterization Models for Quality Assurance of Emerging Memory Technologies
Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations
Multi-conditional SAT-ATPG for power-droop testing
Two-dimensional time-division multiplexing for 3D-SoCs
Constructing augmented time compactors
Hierarchical defect-oriented fault simulation for digital circuits
10th European Test Symposium, ETS 2005, Tallinn, Estonia, May 22-25, 2005
Designing Recurrent Neural Networks for Monitoring Embedded Devices
An efficient scan tree design for test time reduction
Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs
Variability-aware aging modeling for reliability analysis of an analog neural measurement system
Digital Generation of Signals for Low Cost RF BIST
Increasing reliability of programmable mixed-signal systems by applying design diversity redundancy
LiD-CAT: A Lightweight Detector for Cache ATtacks
A novel test time reduction algorithm for test architecture design for core-based system chips
All-pass SC biquad reconfiguration scheme for oscillation based analog BIST
FP7 collaborative research project DIAMOND: Diagnosis, error modeling and correction for reliable systems design
Enabling Coverage-Based Verification in Chisel
Dual Edge Triggered Flip-Flops for Noise Aware Design
In-Field Monitoring and Preventing Read Disturb Faults in RRAMs
Reliability-aware operation chaining in high level synthesis
A fault tolerant response analyzer with self-error-correction capability
Fault-Tolerant Algebraic Architecture for radiation induced soft-errors
Impact of the switching activity on the aging of delay-PUFs
Importance of dynamic faults for new SRAM technologies
Combining the histogram method and the ultrafast segmented model identification of linearity errors algorithm for ADC linearity testing
FSMlock: Defending against Oracle-based Sequential Logic-Locking Attacks under Output-Corruption Requirements
A reconfigurable online BIST for combinational hardware using digital neural networks
SafeSU: an Extended Statistics Unit for Multicore Timing Interference
Bridge over troubled waters: Critical area based pattern generation
A high accuracy triangle-wave signal generator for on-chip ADC testing
Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation
Behavior and test of open-gate defects in FinFET based cells
Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits
Testing of Analog/Mixed Signal ICs: Past, present and future
A Resilience Framework for Synapse Weight Errors and Firing Threshold Perturbations in RRAM Spiking Neural Networks
FastGDBN: A GPU-Accelerated DNN for Identifying Good Dies in Bad Neighborhoods
An Optimized Burn-In Stress Flow targeting Interconnections logic to Embedded Memories in Automotive Systems-on-Chip
Signal integrity verification using high speed monitors
Efficient Prognostication of Pattern Count with Different Input Compression Ratios
CNN-based Data-Model Co-Design for Efficient Test-termination Prediction
Constraint-Based Automatic SBST Generation for RISC-V Processor Families
Micro-Architectural features as soft-error markers in embedded safety-critical systems: preliminary study
A new BIST architecture for low power circuits
Plenary presentations: Keynote: The product complexity and test - How product complexity impacts test industry
Pipelined test of SOC cores through test data transformations
Automatic correction of certain design errors using mutation technique
Methodology for determining the influencing factors of lifetime variation for power devices
On the selection of efficient arithmetic additive test pattern generators [logic test]
Modeling and testing comparison faults of memristive ternary content addressable memories
24th IEEE European Test Symposium, ETS 2019, Baden-Baden, Germany, May 27-31, 2019
A design-for-test solution for monolithic 3D integrated circuits
Test Pattern Generator for Majority Voter based QCA Combinational Circuits targeting MMC Defect
On-chip temperature and voltage measurement for field testing
A practical approach for logic simplification based on fault acceptability for error tolerant application
Diagnosis of failing scan cells through orthogonal response compaction
19th IEEE European Test Symposium, ETS 2014, Paderborn, Germany, May 26-30, 2014
Triple error detection for Imai-Kamiyanagi codes based on subsyndrome computations
A fast sweep-line-based failure pattern extractor for memory diagnosis
Multi-Context Execution on a RISC-V Core for Mixed-Criticality Systems
Online prevention of security violations in reconfigurable scan networks
Hierarchical Fault Simulation for Mixed-Signal Circuits Using Template Based Fault Response Modeling
A Simulator of Small-Delay Faults Caused by Resistive-Open Defects
Practical implementation of defect-oriented testing for a mixed-signal class-D amplifier
Rout3D: A lightweight adaptive routing algorithm for tolerating faulty vertical links in 3D-NoCs
Session-less based thermal-aware 3D-SIC test scheduling
Efficient fault simulation through dynamic binary translation for dependability analysis of embedded software
Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps
A new technique for low-cost phase noise production testing from 1-bit signal acquisition
Verification of the decimal floating-point square root operation
Testing and Diagnosis of Power Switches in SOCs
DfT Architecture for 3D-SICs with Multiple Towers
A Generic Fast and Low Cost BIST Solution for CMOS Image Sensors
ETS 2016 foreword
Faulty Function Extraction for Defective Circuits
Output-bit selection with X-avoidance using multiple counters for test-response compaction
Chill Out: Freezing Attacks on Capacitors and DC/DC Converters
Diagnostic Test Generation Based on Subsets of Faults
Is IoT coming to the rescue of semiconductor?
Error Resilient Transformers: A Novel Soft Error Vulnerability Guided Approach to Error Checking and Suppression
A minimum MSE sensor fusion algorithm with tolerance to multiple faults
12th European Test Symposium, ETS 2007, Freiburg, Germany, May 20, 2007
DFT Techniques For Efficient 3D IC Interconnect Test For Chiplet and Multi-Die Package
NeuroScrub: Mitigating Retention Failures Using Approximate Scrubbing in Neuromorphic Fabric Based on Resistive Memories
6th European Test Workshop, ETW 2001, Stockholm, Sweden, May 29 - June 1, 2001
Dynamic Authentication-Based Secure Access to Test Infrastructure
Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction
Automated conformance evaluation of SystemC designs using timed automata
Sensors for built-in alternate RF test
Selective Hardening in Early Design Steps
Opacity preserving Countermeasure using Finite State Machines against Differential Scan Attacks
Machine Learning-Assisted Side-Channel Analysis for Software Integrity Verification
Modified T-Flip-Flop based scan cell for RAS
Protecting caches against multi-bit errors using embedded erasure coding
MBIST-based weak bit screening method for embedded MRAM
A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points
Symmetric transparent on-line BIST of word-organized memories with binary adders
Compaction of IDDQ test sequence using reassignment method
Soft-Error Rate Testing of Deep-Submicron Integrated Circuits
Built-in Test of Frequency Modulated RF Transmitters Using Embedded Low-Pass Filters
On High-Quality Test Pattern Selection and Manipulation
Towards the formal verification of security properties of a Network-on-Chip router
Cell Aware and stuck-open tests
Post-bond test of Through-Silicon Vias with open defects
At-speed on-chip diagnosis of board-level interconnect faults
On-Line Testing of Neuromorphic Hardware
Using at-speed BIST to test LVDS serializer/deserializer function
On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores
A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors
Diagnosis of power switches with power-distribution-network consideration
Silent Data Corruption: DRAM Root Causes and Ways of Improving Test Quality Towards 0ppm
An off-line MDSI interconnect BIST incorporated in BS 1149.1
It is All About Trust: The Road to Autonomous Driving Will Connect Test, Reliability and Safety
Towards a general purpose mixed-signal instrumentation layer in the die stack of a 3D-SIC
Spotlight: An Impairing Packet Transmission Attack Targeting Specific Node in NoC-based TCMP
An Ordinal Optimization-Based Approach To Die Distribution Estimation For Massive Multi-site Testing Validation: A Case Study
Design and implementation of Automatic Test Equipment IP module
Defective behaviours of resistive opens in interconnect lines
Modeling Thermal Effects For Biasing PUFs
Full-circuit SPICE simulation based validation of dynamic delay estimation
Incremental computation of delay fault detection probability for variation-aware test generation
A Mixed-Signal Test Bus and Analog BIST with 'Unlimited' Time and Voltage Resolution
Memory Optimized Two-Stimuli INL Test Method for DAC-ADC Pairs
A Transparent based Programmable Memory BIST
Analysis and mitigation of single event effects on flash-based FPGAS
Novel Solution for the Built-in Gate Oxide Stress Test of LDMOS in Integrated Circuits for Automotive Applications
On calculating efficient LFSR seeds for built-in self test
Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs
Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits
OBT for settling error test of sampled-data systems using signal-dependent clocking
Test-architecture optimization for TSV-based 3D stacked ICs
Exploring and Comparing IEEE P1687.1 and IEEE 1687 Modeling of Non-TAP Interfaces
Online Performance Monitoring of Neuromorphic Computing Systems
Delay fault testing: choosing between random SIC and random MIC test sequences
Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution
Dynamic Voltage Scaling Aware Delay Fault Testing
Compressed bit fail maps for memory fail pattern classification
Delay chain based programmable jitter generator
Automating the device interface board modeling for virtual test
Semi-Supervised Deep Learning for Microcontroller Performance Screening
LSI aging estimation using ring oscillators
Reducing Sampling Clock Jitter to Improve SNR Measurement of A/D Converters in Production Test
F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG
Online Fault Detection and Diagnosis in RRAM
Bandwidth-aware test compression logic for SoC designs
Microprocessor fault-tolerance via on-the-fly partial reconfiguration
ADC test methods using an impure stimulus: A survey
Functional and structural testing of switched-current circuits
Adaptive quality binning for analog circuits
System-Level Access to On-Chip Instruments
Analysis and design of an on-chip retargeting engine for IEEE 1687 networks
Trustworthy computing on untrustworthy and Trojan-infected on-chip interconnects
A Novel Power Analysis Attack against CRYSTALS-Dilithium Implementation
Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values
Quantified contribution of design for manufacturing to yield at 28nm
Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis
Cell-aware diagnosis: Defective inmates exposed in their cells
Utilizing shared memory multi-cores to speed-up the ATPG process
Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs
Evaluation of impulse response-based BIST techniques for MEMS in the presence of weak nonlinearities
The impact of production defects on the soft-error tolerance of hardened latches
Exploiting an infrastructure IP to reduce memory diagnosis costs in SoCs
14th IEEE European Test Symposium, ETS 2009, Sevilla, Spain, May 25-29, 2009
IEEE Std. P1687.1 for Access Control of Reconfigurable Scan Networks
Accurate tap-delay measurements using a di .erential oscillation technique
User-constrained test architecture design for modular SOC testing
Novel approach to reduce power droop during scan-based logic BIST
Model based generation of high coverage test suites for embedded systems
On random pattern testability of cryptographic VLSI cores
Dependable Wireless Industrial IoT Networks: Recent Advances and Open Challenges
PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory
On the diagnostic analysis of IEEE 1687 networks
Challenges in Cell-Aware Test
A Low-Cost Emulation System for Fast Co-verification and Debug
Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs
ArsoNISQ: Analyzing Quantum Algorithms on Near-Term Architectures
Debug architecture for system on chip taking full advantage of the test access port
Silent Data Corruption: Test or Reliability Problem?
Online Testing of a Row-Stationary Convolution Accelerator
Variance Reduction for Supply Ramp Based Cheap RF Test Alternatives
Cost effective testing of systems on silicon: areas for optimization
Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator
Living with Failure: Lessons from Nature?
G-PUF: An Intrinsic PUF Based on GPU Error Signatures
A low-cost and scalable test architecture for multi-core chips
Testing visions
Global Tuning for System Performance Optimization of RF MIMO Radars
Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods
Detection of Rowhammer Attacks in SoCs with FPGAs
Built-In Predictors for Dynamic Crosstalk Avoidance
Interleaved scrambling technique: A novel low-power security layer for cache memories
DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs
The Future Is Low Power and Test
Multiple errors produced by single upsets in FPGA configuration memory: a possible solution
Mismatch Measurement for MIMO mm-Wave Radars via Simple Power Monitors
Addressing transient routing errors in fault-tolerant Networks-on-Chips
High-level path activation technique to speed up sequential circuit test generation
Cell-aware experiences in a high-quality automotive test suite
New test compression scheme based on low power BIST
An implementation for test-time reduction in VLIW transport-triggered architectures
A Multi-Objective Evolutionary Approach for Test Network Design
Efficient system-level aging prediction
Convolutional Coding for SEU mitigation
A SIFT-based Waveform Clustering Method for aiding analog/mixed-signal IC Verification
11th European Test Symposium, ETS 2006, Southhampton, UK, May 21-24, 2006
Study of Transistor Metrics for Room-Temperature Screening of Single Electron Transistors for Silicon Spin Qubit Applications
Understanding Permanent Hardware Failures in Deep Learning Training Accelerator Systems
Power-aware testing: The next stage
Revisiting Logic Locking for Reversible Computing
An integrated flow for the design of hardened circuits on SRAM-based FPGAs
An optical/electrical test system for 100Gb/s optical interconnection devices with high volume testing capability
Emerging Computing Devices: Challenges and Opportunities for Test and Reliability *
Heterogeneous Integration of Advanced CMOS and Emerging Devices: Challenges and Solutions
IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers
On-Chip Time Measurement Architecture with Femtosecond Timing Resolution
Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA
Homogeneous many-core processor system test distribution and execution mechanism
Robust optimization of test-architecture designs for core-based SoCs
Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation
Compact test set generation for test compression-based designs
INL systematic reduced-test technique for Pipeline ADCs
AMS Test Stimulus Generation and Response Analysis Using Hyperdimensional Clustering: Minimizing Misclassification Rate
Reducing Routing Overhead by Self-Enabling Functional Path Ring Oscillators
Logic circuit testing for transient faults
On Minimization of Peak Power for Scan Circuit during Test
Automated regression testing of CTI-systems
AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators
Simulating realistic bridging and crosstalk faults in an industrial setting
Relating entropy theory to test data compression
System-in-Package, a Combination of Challenges and Solutions
Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism
On the quality of test vectors for post-silicon characterization
Stimuli Generation for IC Design Verification using Reinforcement Learning with an Actor-Critic Model
13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008
A New Monitor Insertion Algorithm for Intermittent Fault Detection
Polynomial Formal Verification of Approximate Adders with Constant Cutwidth
On Extracting Reliability Information from Speed Binning
Safe Fault Collapsing Based on Dominance Relations
Exploiting Thread-Level Parallelism in Functional Self-Testing of CMT Processors
FPGA Architecture for RF Transceiver System and Mixed-Signal Low Cost Tests
Reducing embedded software radiation-induced failures through cache memories
DeepVigor: VulnerabIlity Value RanGes and FactORs for DNNs' Reliability Assessment
Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model
Minimal March Tests for Dynamic Faults in Random Access Memories
On the Fault Sensitivity of Natural Language Embeddings Computation
Debug facilities in the TriMedia CPU64 architecture
On test program compaction
Tackling the complexity of exact path delay fault grading for path intensive circuits
On path selection for delay fault testing considering operating conditions [logic IC testing]
Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks
Low Cost Launch-on-Shift Delay Test with Slow Scan Enable
Control-aware test architecture design for modular SOC testing
A branch-&-bound algorithm for TAM optimization in multi-Vdd SoCs
22nd IEEE European Test Symposium, ETS 2017, Limassol, Cyprus, May 22-26, 2017
Thermal Neutrons: a Possible Threat for Supercomputers and Safety Critical Applications
If It's All about Yield, Why Talk about Testing?
A Robust Metric for Screening Outliers from Analogue Product Manufacturing Tests Responses
High-Performance Diagnostic Fault Simulation on GPUs
Read path degradation analysis in SRAM
CPE: Codeword Prediction Encoder
On selecting testable paths in scan designs
On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking
Enhanced P1500 compliant wrapper suitable for delay fault testing of embedded cores
Analytical modeling for EVM in OFDM transmitters including the effects of IIP3, I/Q imbalance, noise, AM/AM and AM/PM distortion
Input test data volume reduction based on test vector chains
Bias temperature instability analysis in SRAM decoder
A distance-based test cube merging procedure for compatible and incompatible test cubes
A Novel BIST Method for Multi-Port Register Files
Expanding the boundaries of test and diagnostics: Prognostics and Health Management (PHM) for complex systems
The anatomy of nanometer timing failures
Extracting Weights of CIM-Based Neural Networks Through Power Analysis of Adder-Trees
Internal feedback bridging faults in combinational CMOS circuits: analysis and testing
Nonlinear Codes for Control Flow Checking
Characterization of the EME of integrated circuits with the help of the IEC standard 61967 [electromagnetic emission]
Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging
Functional analysis of circuits under timing variations
Improving SNR for DSM Linear Systems Using Probabilistic Error Correction and State Restoration: A Comparative Study
A Novel Approach for Online Sensor Testing Based on an Encoded Test Stimulus
Enhanced wafer matching heuristics for 3-D ICs
Speeding up Cell-Aware Library Characterization by Preceding Simulation with Structural Analysis
On avoiding undetectable faults during test generation
Reliability Under Stress: The Impact of Localized Aging on RO-PUF Architectures in FPGAs
Using the BS register for capturing and storing n-bit sequences in real-time
Dependable embedded systems: The German research foundation DFG priority program SPP 1500
On the Trustworthiness of Spiking Neural Networks and Neuromorphic Systems
Silent Data Corruption Errors in VLSI Circuits: Implications, Challenges, and Opportunities
Avoiding Mixed-Signal Field Returns by Outlier Detection of Hard-to-Detect Defects based on Multivariate Statistics
Machine learning applications in IC testing
Comparison of defect detection capabilities of current-based and voltage-based test methods
Optimizing System-Level Test Program Generation via Genetic Programming
The Role of Test in Circuits Built with Unreliable Components
Optimization of Assertion Placement in Time-Constrained Embedded Systems
RESPIN++ - deterministic embedded test
Formal verification of secure reconfigurable scan network infrastructure
Is adaptive testing the panacea for the future test problems?
Site dependencies in a multisite testing environment
Failure and Attack Detection by Digital Sensors
Counterfeit Detection by Semiconductor Process Technology Inspection
Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits
The Risk of Outsourcing: Hidden SCA Trojans in Third-Party IP-Cores Threaten Cryptographic ICs
Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation
Reducing wearout in embedded processors using proactive fine-grain dynamic runtime adaptation
Demodulation based testing of off-chip driver performance
SpinalFuzz: Coverage-Guided Fuzzing for SpinalHDL Designs
Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes?