yusuke1997/dblp-id-title huggingface dataset:
On-chip reduced-code static linearity test of V cm -based switching SAR ADCs using an incremental analog-to-digital converter
SCI-FI: a Smart, aCcurate and unIntrusive Fault-Injector for Deep Neural Networks
Data-driven fault diagnosis with missing syndromes imputation for functional test through conditional specification
Masking of X-values by Use of a Hierarchically Configurable Register
Speed-Path Debug Using At-Speed Scan Test Patterns
Semiconductor Application Fail Root Causes And Secure Test Remedy
Extended binary nonlinear codes and their application in testing and compression
Time-division multiplexing for testing SoCs with DVS and multiple voltage islands
Design Obfuscation versus Test
Design-for-Test for Intermittent Faults in STT-MRAMs
On measurement uncertainty of ADC nonlinearities in oscillation-based test
Test Compression for Neuromorphic Chips
BiSTAHL: A Built-In Self-Testable Soft-Error-Hardened Scan-Cell
Information-theoretic syndrome and root-cause analysis for guiding board-level fault diagnosis
Questioning the reliability of Monte Carlo simulation for machine learning test validation
Security Risks in AI Accelerators: Detecting RTL Vulnerabilities to Model Theft with Formal Verification
On combining alternate test with spatial correlation modeling in analog/RF ICs
Density-oriented diagnostic data compression strategy for characterization of embedded memories in Automotive Systems-on-Chip
Experimental results on BIC sensors for transient current testing
A Bayesian model for system level reliability estimation
Analog Fault Simulation - a Hot Topic!
Semiconductor failure modes and mitigation for critical systems embedded tutorial
Anomaly Detection in Embedded Systems Using Power and Memory Side Channels
BIST design for analog cell matching
CA-CSTP: a new BIST architecture for sequential circuits
A multi-mode MEMS sensor design to support system test and health & usage monitoring applications
Partial set for flip-flops based on state requirement for non-scan BIST scheme
Diagnosis of Failing Scan Cells through Orthogonal Response Compaction
Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channels
A high-level EDA environment for the automatic insertion of HD-BIST structures
Communication-Centric SoC Debug Using Transactions
Implementing model redundancy in predictive alternate test to improve test confidence
A VHDL-based virtual test concept for pre-silicon test-program debug
Symbolic Circuit Analysis under an Arc Based Timing Model
Resource-Efficient Programmable Trigger Units for Post-Silicon Validation
Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement
We Have Got Compression, What Next?
TPI for improving PR fault coverage of Boolean and three-state circuits
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
High frequency jitter estimator for SoCs
Test-per-Clock Detection, Localization and Identification of Interconnect Faults
Fast simulation based testing of anti-tearing mechanisms for small embedded systems
Early Result Capture: Racing Conditions in Pipeline due to Clock Glitches
GPU-based ATPG System by Scaling Memory Usage and Reducing Data Transfer
Degradation Monitoring Through Software-controlled On-chip Sensors for RISC-V
Adaptive test directions
Machine Learning-based Prediction of Test Power
20th IEEE European Test Symposium, ETS 2015, Cluj-Napoca, Romania, 25-29 May, 2015
How to avoid random walks in hierarchical test path identification
Property-checking based LBIST for improved diagnosability
Energy minimization for hybrid BIST in a system-on-chip test environment
Robust Pattern Generation for Small Delay Faults under the Impact of Variations
Defect-aware nanocrossbar logic mapping using Bipartite Subgraph Isomorphism & canonization
A Low Cost Alternative Method for Harmonics Estimation in a BIST Context
On coverage of timing related faults at board level
Optimization-based multiple target test generation for highly compacted test sets
A 40Gbps economic extension board and FPGA-based testing platform
8th European Test Workshop, ETW 2003, Maastricht, The Netherlands, May 25-28, 2003
PaTran: Translation Platform for Test Pattern Program
Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization
Silent Data Corruption from Timing Marginalities Due to Process Variations
Low-cost signature test of RF blocks based on envelope response analysis
New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism
An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs
A Tutorial of How to Ensure High Automotive Microcontroller Quality
Modeling and Analysis of Aging Impact on SRAM PUFs for Advanced FinFET Technology Nodes
Online Reliability Evaluation Design: Select Reliable CRPs for Arbiter PUF and Its Variants
Run-time detection of hardware Trojans: The processor protection unit
Avoiding burnt probe tips: Practical solutions for testing internally regulated power supplies
IJTAG Compatible Timing Monitor with Robust Self-Calibration for Environmental and Aging Variation
Cost and power efficient timing error tolerance in flip-flop based microprocessor cores
Accurate measurement of multi-tone power ratio (MTPR) of ADSL devices using low cost testers
Reducing power dissipation in memory repair for high defect densities
Low power probabilistic online monitoring of systematic erroneous behaviour
Automatic Test Pattern Generation for Printed Neuromorphic Circuits
A unified fault model and test generation procedure for interconnect opens and bridges
RHAT: Efficient RowHammer-Aware Test for Modern DRAM Modules
On-Chip Test Generation Using Linear Subspaces
Test-mode-only scan attack using the boundary scan chain
A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications
A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control
Security, Reliability and Test Aspects of the RISC-V Ecosystem
IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs
AMS Test Vector Generation using AMS Verification and IEEE P1687.2
Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips
Periodic Bias-Temperature Instability monitoring in SRAM cells
Exploiting STT-MRAM for approximate computing
Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic
Hardware-Based Aging Mitigation Scheme for Memory Address Decoder
Efficient system-level testing and adaptive tuning of MIMO-OFDM wireless transmitters
Reduced ATE Interface for High Test Data Compression
Hierarchical Fault Simulation of Deep Neural Networks on Multi-Core Systems
Securing Reconfigurable Scan Networks Against Data Sniffing and Data Alteration Attacks
Towards Understanding of System-Level Test Unique Fails
Minimal Witnesses for Security Weaknesses in Reconfigurable Scan Networks
Predicting dynamic specifications of ADCs with a low-quality digital input signal
Input/Output Pad for Direct Contact and Contactless Testing
Testing of resistive opens in CMOS latches and flip-flops
Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits
Trojan Insertions of Fully Programmable Valve Arrays
Advancements in diagnosis driven yield analysis (DDYA): A survey of state-of-the-art scan diagnosis and yield analysis technologies
Fault Collapsing for Transition Faults Using Extended Transition Faults
A Lightweight, Plug-and-Play and Autonomous JTAG Authentication IP for Secure Device Testing
On the detection of path delay faults by functional broadside tests
From system level to defect-oriented test: a case study
Experimental evaluation of thread distribution effects on multiple output errors in GPUs
Partial Scan Approach for Secret Information Protection
Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs
Analog test: Why still "à la mode" after more than 25 years of research?
Structural Test for Graceful Degradation of NoC Switches
Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios
Non-Uniform Error Correction for Hyperdimensional Computing Edge Accelerators
LEAP: An accurate defect-free I DDQ estimator
Non-Adaptive Pattern Reordering to Improve Scan Chain Diagnostic Resolution
Analyzing the Impact of Approximate Adders on the Reliability of FPGA Accelerators
Measuring mixed-signal test stimulus quality
On the use of standard digital ATE for the analysis of RF signals
A UCIe Compatible Repair Scheme for the Clustered Faults in the Hexagonal Array of Interconnect Lanes
Towards Variation-Aware Test Methods
Toggle-Based Masking Scheme for Clustered Unknown Response Bits
Identification of high power consuming areas with gate type and logic level information
Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns
Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs
Detection conditions for errors in self-adaptive better-than-worst-case designs
Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach
SiFFS: A Scalable in-Fault Functional Simulation Framework for Fault Criticality Analysis
Multi-voltage aware resistive open fault modeling
Recent Advances in Photonic Physical Unclonable Functions
Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories
Optimized MBIST-Based MRAM Testing for Automotive MCUs to Achieve Superior Performance and Quality Assurance
K3 TAM Optimization for Testing 3D-SoCs using Non-Regular Time-Division-Multiplexing
EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS
A new self-checking multiplier by use of a code-disjoint sum-bit duplicated adder
Built-in self-calibration of CMOS-compatible thermopile sensor with on-chip electrical stimulus
Reusing scan chains for test pattern decompression
Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead
Low Overhead Partial Enhanced Scan Technique for Compact and High Fault Coverage Transition Delay Test Patterns
Aggresive scan chain masking for improved diagnosis of multiple scan chain failures
Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs
A built-in self-test scheme for classifying refresh periods of DRAMs
Training Large Language Models for System-Level Test Program Generation Targeting Non-functional Properties
Unsupervised Learning in Test Generation for Digital Integrated Circuits
Digital Defect Based Built-in Self-Test for Low Dropout Voltage Regulators
Hybrid test application in hybrid delay scan design
17th IEEE European Test Symposium, ETS 2012, Annecy, France, May 28 - June 1 2012
An adaptive tester architecture for volume diagnosis
Two soft-error mitigation techniques for functional units of DSP processors
Introducing MEDIAN: A new COST Action on manufacturable and dependable multicore architectures at nanoscale
An Improved Algorithm to Identify the Test Stimulus in Histogram-Based A/D Converter Testing
Optimizing RO-PUFs: A Filtering Approach to Reliability and Entropy Trade-offs
A collision resistant deterministic random bit generator with fault attack detection possibilities
System level diagnosis - a comparison of two alternative approaches
Silicon technology advances and implications on test
Dependable Neuromorphic Computing-in-Memory Architectures
Improve the compression ratios for code-based test vector compressions by decomposing
Adaptive testing: Conquering process variations
A built-in method for measuring the delay of TSVs in 3D ICs
RTL design validation, DFT and test pattern generation for high defects coverage
A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256
A software reconfigurable assertion checking unit for run-time error detection
Analyzing the Structural and Operational Impact of Faults in Floating-Point and Posit Arithmetic Cores for CNN Operations
Device aging: A reliability and security concern
Automatic generation of autonomous built-in observability structures for analog circuits
Single-Event Upset Analysis and Protection in High Speed Circuits
On-Line Reliability Estimation of Ring Oscillator PUF
Fault Injection-based Reliability Evaluation of SoPCs
Design validation of behavioral VHDL descriptions for arbitrary fault models
A Game-Theoretic Approach to Branching Time Abstract-Check-Refine Process
Specifications for Free
Testing Static Analyzers with Randomly Generated Programs
Energy-Utility Quantiles
Incremental Invariant Generation Using Logic-Based Automatic Abstract Transformers
Timed Automata Learning via SMT Solving
Modifying Test Suite Composition to Enable Effective Predicate-Level Statistical Debugging
Second NASA Formal Methods Symposium - NFM 2010, Washington D.C., USA, April 13-15, 2010. Proceedings
Case Studies for Computing Density of Reachable States for Safe Autonomous Motion Planning
Run-Time Assurance for Learning-Enabled Systems
Certified Foata Normalization for Generalized Traces
A Falsification View of Success Typing
Monitorability of Expressive Verdicts
Requirements Analysis of a Quad-Redundant Flight Control System
Querying Labeled Time Series Data with Scenario Programs
A Proof Infrastructure for Binary Programs
Inferring Definite Counterexamples through Under-Approximation
Using Lightweight Theorem Proving in an Asynchronous Systems Context
Automated Conflict-Free Concurrent Implementation of Timed Component-Based Models
Composing Symmetry Propagation and Effective Symmetry Breaking for SAT Solving
Gray-Box Learning of Serial Compositions of Mealy Machines
REFINER: Towards Formal Verification of Model Transformations
Analysing Security Protocols Using Refinement in iUML-B
Verification of Design Patterns with LePUS3
Reasoning with Metric Temporal Logic and Resettable Skewed Clocks
Verifying Band Convergence for Sampled Control Systems
opaal: A Lattice Model Checker
A New Method for Incremental Testing of Finite State Machines
Formal Verification by Abstract Interpretation
Automated Assume-Guarantee Reasoning for Omega-Regular Systems and Specifications
PaRoT: A Practical Framework for Robust Deep Neural Network Training
TLA+: Whence, Wherefore, and Whither
Twenty Percent and a Few Days - Optimising a Bitcoin Majority Attack
Probabilistic Formal Verification of the SATS Concept of Operation
Warps and Atomics: Beyond Barrier Synchronization in the Verification of GPU Kernels
Improved State Space Reductions for LTL Model Checking of C and C++ Programs
Instantiation-Based Invariant Discovery
Event-Based Runtime Verification of Temporal Properties Using Time Basic Petri Nets
Assume-Guarantee Reasoning with Scheduled Components
A Verification Technique for Deterministic Parallel Programs
A Streamlined, Formal Approach to Requirements-Based Testing
Constraining Counterexamples in Hybrid System Falsification: Penalty-Based Approaches
Formalization of Asymptotic Convergence for Stationary Iterative Methods
Temporal Logic Framework for Performance Analysis of Architectures of Systems
A Hybrid Architecture for Correct-by-Construction Hybrid Planning and Control
Numerical Abstract Domain Using Support Functions
Towards Verifying SHA256 in OpenSSL with the Software Analysis Workbench
Traffic Management for Urban Air Mobility
Control Barrier Function Toolbox: An Extensible Framework for Provable Safety
Generation of Signals Under Temporal Constraints for CPS Testing
Model Checking Using SMT and Theory of Lists
Applying Atomicity and Model Decomposition to a Space Craft System in Event-B
PVS Linear Algebra Libraries for Verification of Control Software Algorithms in C/ACSL
Good Fences Make Good Neighbors - Using Formally Verified Safe Trajectories to Design a Predictive Geofence Algorithm
Vellvm: Formalizing the Informal LLVM - (Experience Report)
NASA Formal Methods - 16th International Symposium, NFM 2024, Moffett Field, CA, USA, June 4-6, 2024, Proceedings
Strategy Synthesis in Markov Decision Processes Under Limited Sampling Access
VeriFast: A Powerful, Sound, Predictable, Fast Verifier for C and Java
Strong Structural Bounds for MaxSAT: The Fine Details of Using Neuromorphic and Quantum Hardware Accelerators
A Tabular Expression Toolbox for Matlab/Simulink
Automated Test Case Generation with SMT-Solving and Abstract Interpretation
Formalized High Level Synthesis with Applications to Cryptographic Hardware
From Goal-Oriented Requirements to Event-B Specifications
NASA Formal Methods - 14th International Symposium, NFM 2022, Pasadena, CA, USA, May 24-27, 2022, Proceedings
A Brief Introduction to the PVS2C Code Generator
Towards the Formal Verification of a Distributed Real-Time Automotive System
Auto-Active Proof of Red-Black Trees in SPARK
Symbolic Execution and Reachability Analysis Using Rewriting Modulo SMT for Spatial Concurrent Constraint Systems with Extrusion
Tuning Permissiveness of Active Safety Monitors for Autonomous Systems
NASA Formal Methods - 13th International Symposium, NFM 2021, Virtual Event, May 24-28, 2021, Proceedings
Visualizing Temporal Interval Hierarchies
Tactical Synthesis of Efficient Global Search Algorithms
Operational Annotations - A New Method for Sequential Program Verification
Moving the Needle on Rigorous Floating-Point Precision Tuning
Towards Formal Verification of Neural Networks in Cyber-Physical Systems
ARSENAL: Automatic Requirements Specification Extraction from Natural Language
Incremental Construction of Realizable Choreographies
Towards Refactoring FRETish Requirements
Towards a Framework for Generating Tests to Satisfy Complex Code Coverage in Java Pathfinder
Sampling Distributed Schedulers for Resilient Space Communication
Towards Full Proof Automation in Frama-C Using Auto-active Verification
Validation of Reinforcement Learning Agents and Safety Shields with ProB
The Use of Rippling to Automate Event-B Invariant Preservation Proofs
An Efficient Rewriting Framework for Trace Coverage of Symmetric Systems
Automated Formal Methods, AFM@NFM 2017, Moffett Field, CA, USA, May 19-20, 2017
Formal Methods for Automated Diagnosis of Autosub 6000
Minimum-Violation Traffic Management for Urban Air Mobility
Phase Two Feasibility Study for Software Safety Requirements Analysis Using Model Checking
Rigorous Polynomial Approximation Using Taylor Models in Coq
Deductive Verification of Cryptographic Software
Verification of Certifying Computations through AutoCorres and Simpl
Requirements-Driven Model Checking and Test Generation for Comprehensive Verification
Verifying Hybrid Systems Involving Transcendental Functions
Enhancing the Inverse Method with State Merging
From Design Contracts to Component Requirements Verification
The comKorat Tool: Unified Combinatorial and Constraint-Based Generation of Structurally Complex Tests
A Framework for Policy Based Negotiation
Enforcing MAVLink Safety & Security Properties via Refined Multiparty Session Types
Runtime Verification with Predictive Semantics
SMT-Based Dynamic Multi-Robot Task Allocation
Proof Mate: An Interactive Proof Helper for PVS (Tool Paper)
Compositional Inductive Invariant Based Verification of Neural Network Controlled Systems
Simplifying Neural Networks Using Formal Verification
A Validation Methodology for OCaml-to-PVS Translation
Clausal Proofs of Mutilated Chessboards
Lessons Learnt from the Adoption of Formal Model-Based Development
How Formal Methods Impels Discovery: A Short History of an Air Traffic Management Project
Statistical Model Checking of Wireless Mesh Routing Protocols
Model Checking of Verilog RTL Using IC3 with Syntax-Guided Abstraction
Towards Formal Verification of HotStuff-Based Byzantine Fault Tolerant Consensus in Agda
Structuring Formal Methods into the Undergraduate Computer Science Curriculum
Benchmarking Software Model Checkers on Automotive Code
Salsa: An Automatic Tool to Improve the Numerical Accuracy of Programs
Structure-Guided Cube-and-Conquer for MaxSAT
Quantitative Timed Analysis of Interactive Markov Chains
Verifying Functional Correctness of C Programs with VCC
Using Binary Analysis Frameworks: The Case for BAP and angr
jFuzz: A Concolic Whitebox Fuzzer for Java
On the Termination of Borrow Checking in Featherweight Rust
A Synthesized Algorithm for Interactive Consistency
Automata-Based Software Model Checking of Hyperproperties
Formal Verification of a Parameterized Data Aggregation Protocol
GiNaCRA: A C++ Library for Real Algebraic Computations
Efficient Predicate Abstraction of Program Summaries
Data-flow Based Model Analysis
Reasoning over Test Specifications Using Assume-Guarantee Contracts
From the Standards to Silicon: Formally Proved Memory Controllers
Symmetry-Based Abstraction Algorithm for Accelerating Symbolic Control Synthesis
Synthesizing Predicates from Abstract Domain Losses
Verifying Relative Safety, Accuracy, and Termination for Program Approximations
Sound Black-Box Checking in the LearnLib
Towards Flight Control Verification Using Automated Theorem Proving
Providing Early Warnings of Specification Problems
Probabilistic Hyperproperties with Rewards
Floating-Point Format Inference in Mixed-Precision
Code-Level Formal Verification of Ellipsoidal Invariant Sets for Linear Parameter-Varying Systems
Language Partitioning for Mission-Time Linear Temporal Logic
Memory Efficient Data Structures for Explicit Verification of Timed Systems
Thread-Modular Model Checking with Iterative Refinement
NNLander-VeriF: A Neural Network Formal Verification Framework for Vision-Based Autonomous Aircraft Landing
NASA Formal Methods, 5th International Symposium, NFM 2013, Moffett Field, CA, USA, May 14-16, 2013. Proceedings
Polygon Merge: A Geometric Algorithm Verified Using PVS
Learning from Faults: Mutation Testing in Active Automata Learning
More Programming Than Programming: Teaching Formal Methods in a Software Engineering Programme
Comparing Techniques for Certified Static Analysis
Temporal Action Language (TAL): A Controlled Language for Consistency Checking of Natural Language Temporal Requirements - (Preliminary Results)
Assisted Coverage Closure
Robotics: A New Mission for FRET Requirements
SMT for state-based formal methods: the ASM case study
Formal Methods Applications in Air Transportation
Refinement Types for tla +
Infer: An Automatic Program Verifier for Memory Safety of C Programs
Formal Analysis of GPU Programs with Atomics via Conflict-Directed Delay-Bounding
Efficient Guiding Strategies for Testing of Temporal Properties of Hybrid Systems
An Essence of Domain Engineering - A Basis for Trustworthy Aeronautics and Space Software
Concept Design Moves
Automatically Proving Thousands of Verification Conditions Using an SMT Solver: An Empirical Study
Towards Informed Swarm Verification
A Tool for Intersecting Context-Free Grammars and Its Applications
On the Usefulness of Clause Strengthening in Parallel SAT Solving
Formal Methods for Trusted Space Autonomy: Boon or Bane?
Certified Computation of Nondeterministic Limits
JKelloy: A Proof Assistant for Relational Specifications of Java Programs
Predicting and Witnessing Data Races Using CSP
The Theory and Practice of SALT
A Little Language for Testing
Hierarchical Contract-Based Synthesis for Assurance Cases
Stuttering Mostly Speeds Up Solving Parity Games
Don't Miss the End: Preventing Unsafe End-of-File Comparisons
Obfuscator Synthesis for Privacy and Utility
NASA Formal Methods - 17th International Symposium, NFM 2025, Williamsburg, VA, USA, June 11-13, 2025, Proceedings
Tree-Based Scenario Classification - A Formal Framework for Measuring Domain Coverage When Testing Autonomous Systems
Model Checking Timed Hyperproperties in Discrete-Time Systems
Conservative Safety Monitors of Stochastic Dynamical Systems
Practical Formal Verification of Domain-Specific Language Applications
Subtropical Satisfiability for SMT Solving
Model-Based Testing for General Stochastic Time
Introduction of Virtualization Technology to Multi-Process Model Checking
Verification of Scapegoat Trees Using Dafny
ZoPE: A Fast Optimizer for ReLU Networks with Low-Dimensional Inputs
CORAL: Solving Complex Constraints for Symbolic PathFinder
Counterexample-Based Error Localization of Behavior Models
Formal Methods Assisted Training of Safe Reinforcement Learning Agents