yusuke1997/dblp-id-title huggingface dataset:
Identification of Failing Tests with Cycling Registers
Vendor-agnostic native compression engine
Do Stuck Fault Models Reflect Manufacturing Defects?
Periodic Jitter Amplitude Calibration with Walking Strobe
Testability Analysis of Programmable Array Logic
Good Scan = Good Quality Level? Well, It Depends ?
Cross-layer system reliability assessment framework for hardware faults
A Method to Generate a Very Low Distortion, High Frequency Sine Waveform Using an AWG
TAO: regular expression based high-level testability analysis and optimization
Adaptive Methods for Machine Learning-Based Testing of Integrated Circuits and Boards
A Multimode Programming Strategy for VLSI Boards
Have we overcome the challenges associated with SoC and multi-core testing?
A Case Study of IR-Drop in Structured At-Speed Testing
ERTG: A test generator for error-rate testing
A Computer System Diagnostic Strategy Based on ROM-Resident Diagnostics
Enhanced Probe Card Facilities At-Speed Wafer Probing in Very High Density Applications
Functional test generation for finite state machines
Economics Modelling for the Determination of Test Strategies for Complex VLSI Boards
TimingSAT: Decamouflaging Timing-based Logic Obfuscation
Test challenges for SONET/SDH physical layer OC3 devices and beyond
Formal Description of Test Specification and ATE Architecture for Mixed-Signal Test
Delay testing of SOI circuits: Challenges with the history effect
Unpowered Opens Test with X-Ray Laminography
Driving Forces Behind Field-Based System Testing
A Design for Test Technique for Parametric Analysis of SRAM: On-Die Low Yield Analysis
Software Verification Techniques
Design-for-Testability Using Test Design Yield and Decision Theory
VECTOR (Virtual Edge Connector Test): A Strategy to Increase TPS Fault Coverage Without Adding Test Vectors
CMOS Is Most Testable
Ultra Hi-Speed Pin-Electronics and Test Station Using GaAs IC
Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation
RIC/DICMOS - Multi-channel CMOS Formatter
Power Distribution Failure Analysis Using Transition-Delay Fault Patterns
A comprehensive approach for modeling and testing analog and mixed-signal devices
Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis
Paragons for Memory Test
Dependable clock distribution for crosstalk aware design
RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications
STARTS: Simulation Traits Assisted Random Test Selection for Multiprocessor Verification
Testing of Fault-Tolerant Clock Systems
Implementation of a Memory-Emulation Diagnostic Technique
Diagnosis with Limited Failure Information
Reducing device yield fallout at wafer level test with electrohydrodynamic (EHD) cleaning
A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM
An experiment of burn-in time reduction based on parametric test analysis
30-Gb/s optical and electrical test solution for high-volume testing
An Expert System for In-Circuit Fault Diagnosis
Achieving higher yield through diagnosis-the ASIC perspective
Position Statement: Increasing Test Coverage in a VLSI Design Course
Board assisted-BIST: Long and short term solutions for testpoint erosion - Reaching into the DFx toolbox
ASIC Manufacturing Test Cost Prediction at Early Design Stage
A self-timed structural test methodology for timing anomalies due to defects and process variations
Very-Low-Voltage testing of amorphous silicon TFT circuits
A new paradigm in test for the next millennium
Can Undergraduate Test Engineering Education Be "Faster, Better, Sooner?"
Multichip Module Testing Methodologies: What's In; What's Not
A Tightly Coupled Multiprocessor for VLSI Testing
Designed -in-diagnostics: A new optical method
On the Accuracy of Jitter Separation from Bit Error Rate Function
Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs
Dynamic tests in complex systems [automotive electronics]
Redefining and testing interconnect faults in Mesh NoCs
Tester Correlation Problem in Memory Testers Used in Production Lines
The Role of Testing in Achieving Zero Defects
A tale of two lives: Under test and in the wild
Case study: effectiveness of high-speed scan based feed forward voltage testing in reducing DPPM on a high volume ASIC
SPARTAN: a spectral and information theoretic approach to partial-scan
Making IJTAG Address Physical-World Digital and Mixed-Signal Test Challenges
Thermal Analysis of Backdriven Output Transistors
Optimal Sequencing of Scan Registers
Microprocessor Testing by Instruction Sequences Derived from Random Patterns
Implementation of a Dual-Segment Architecture for a High-Pin-Count VLSI Test System
Extending residue-based fault tolerance to encrypted computation
On Testable Design for CMOS Logic Circuits
Defect Oriented Testing for analog/mixed-signal devices
Multiple fault activation cycle tests for transistor stuck-open faults
Functional Testing of the NS32332 \muProcessor
Doing it in STIL: intelligent conversion from STIL to an ATE format
Custom VLSI Test System
Real-Time In-situ Monitoring and Characterization of Production Wafer Probing Process
Yield-Enhanced Probe Head Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test
Test time efficient group delay filter characterization technique using a discrete chirped excitation signal
Scan test of die logic in 3D ICs using TSV probing
Improved sensitivity for parallel test of substrate interconnections
Seeing Chip Testability Through a Systems Person's Eyes
BER Estimation for Serial Links Based on Jitter Spectrum and Clock Recovery Characteristics
Ultra dense SRAM Cell Test Challenges
Diagnosis for wiring interconnects
Impact of Testability Standards on University Research and Instruction
Design of Easily Testable Microprocessors : A Case Study
Requirements, Challenges, And Solutions For Testing Multiple GB/s ICs In Production
Problems Using Boundary-Scan for Memory Cluster Tests
Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects
System Monitor for Diagnostic, Calibration and System Configuration
Applying lessons learned from TDDB testing
Thermal-aware mobile SoC design and test in 14nm finfet technology
Analysis of pattern-dependent and timing-dependent failures in an experimental test chip
Tools and Techniques for Converting Simulation Models into Test Patterns
The HITEST Test Generation System Overview
Improving Diagnosis Resolution and Performance at High Compression Ratios
Design-for-test methodology for Motorola PowerPC microprocessors
H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing
Fully-Digital Time-To-Digital Converter for ATE with Autonomous Calibration
Defect-oriented testing and diagnosis of digital microfluidics-based biochips
HABIST: Histogram-Based Analog Built-In Self-Test
RF MEMS switches for Wide I/O data bus applications
ATE Value Add through Open Data Collection
The Advantages of Limiting P1687 to a Restricted Subset
Test Propagation Through Modules and Circuits
An efficient on-line-test and back-up scheme for embedded processors
A Built-in Self- Test for ADC and DAC in a Single-Chip Speech CODEC
High-Fidelity Device Tester Interface
Is test power reduction through X-filling good enough?
Design Automation for Intelligent Automotive Systems
The Importance of Functional-Like Access for Memory Test
Investment vs. Yield Relationship for Memories and IP in SOC
Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk
Rapid PLL Monitoring By A Novel min-MAX Time-to-Digital Converter
SLM Subsystem for Automotive SoC: Case Study on Path Margin Monitor
Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation
Tester retargetable patterns
A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior
Structured Functional Level Test Generation Using Binary Decision Diagrams
System-Level Test techniques for Automotive SoCs
Making the Circular Self-Test Path Technique Effective for Real Circuits
Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring
Application of Tools Developed at the University of Iowa to ITC Benchmarks
Application of a Commercial Data Base Management System to Memory Device Test Program Generation and Debugging
Improved System Design Through Proper Nesting of Test Levels
Algorithms for High-Performance Fixture Wiring
Closing the Loop: An Expanding Role for ATE in Semiconductor Manufacturing
PXI - A New Architecture for Many Testing Requirements
Non-Robust versus Robust
On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs
Development of a MEMS Testing Methodology
Variance reduction using wafer patterns in I_ddQ data
Microprocessor system failures debug and fault isolation methodology
The final D-frontier: should DFT be outsourced?
A Comparison of Defect Models for Fault Location with I DDQ Measurements
Logical Diagnosis Solutions Must Drive Yield Improvement
Design and implementation of the "G2" PowerPC 603e-embedded microprocessor core
An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes
Achieving Quality Levels of 100dpm: It's possible - but roll up your sleeves and be prepared to do some work.
IEEE P1149.6: A Boundary-Scan Standard for Advanced Digital Networks
Support for Debugging in the Alpha 21364 Microprocessor
Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression
What Do You Say When Writing a Text About Test ?
Identification of faulty processing elements by space-time compression of test responses
On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout
Delay Testing of Digital Circuits by Output Waveform Analysis
IEEE International Test Conference, ITC 2020, Washington, DC, USA, November 1-6, 2020
The enVision TM Timing Resolver
Maximizing handler thermal throughput with a rib-roughened test tray
On the Computation of Detection Probability for Multiple Faults
Speed Clustering of Integrated Circuits
Diagnostic resolution improvement through learning-guided physical failure analysis
Novel Methodology to Optimize TAT and Resource Utilization for ATPG Simulations for Large SoCs
Testing priority address encoder faults of content addressable memories
A Fast, Probabilistic Algorithm for Functional Testing of Random Access Memory Systems
Accurate Fault Modeling and Efficient Simulation of Differential CVS Circuits
Scan-Based Testing: The Only Practical Solution for Testing ASIC/Consumer Products
Testing methods for quaternary content addressable memory using charge-sharing sensing scheme
Compression mode diagnosis enables high volume monitoring diagnosis flow
An Open Modular Test Concept for the DSP KISS-16Vs
: Reducing test application time in high-level test generation
In-Field Testing using In-System Embedded Deterministic Test as a solution to alleviate Silent Data Corruption in AI designs
Test Set Embedding in a Built-In Self-Test Environment
Parallel Testing of Non-Volatile Memories
A Comparative Analysis of Input Stimuli for Testing Mixed-Signal LSIs Based on Curent Testing
Improved Match-Line Test and Repair Methodology Including Power-Supply Noise Testing for Content-Addressable Memories
A Generic Test and Maintenance Node for Embedded System Test
Transient fault characterization in dynamic noisy environments
Is IEEE 1149.1 Boundary Scan Cost Effective: A Simple Case Study
Three Different MCMs, Three Different Test Strategies
Short Paper: Bus-based Packetized Scan Architecture Trade-offs for Heterogeneous Multi-Core SoCs
Optimizing the flattened test-generation model for very large designs
Defect detection using power supply transient signal analysis
Test point insertion in hybrid test compression/LBIST architectures
A Knowledge Representation Scheme for DFT
Fast BIST of I/O Pin AC specifications and inter-chip delays
Open ATE Architecture: Key Challenges
Diagnostic test generation for transition faults using a stuck-at ATPG tool
Management of common-mode currents in semiconductor ATE
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction
2016 IEEE International Test Conference, ITC 2016, Fort Worth, TX, USA, November 15-17, 2016
Redundant core testing on the cell BE microprocessor
What a Device Interface Board Really Costs: An Evaluation of Technical Considerations for Testing Products Operating in the Gigabit Region
IPV6 Conformance Testing: Theory and Practice
Brain-Inspired Computing for Wafer Map Defect Pattern Classification
A Holistic Parallel and Hierarchical Approach towards Design-For-Test
Monitored Burn-In (A Case Study for In-Situ Testing and Reliability Studies)
Delay testing and characterization of post-bond interposer wires in 2.5-D ICs
Testing Errors: Data and Calculations in an IC Manufacturing Process
A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath
Transition Test on UltraSPARC- T2 Microprocessor
On-Chip Repair and an ATE Independent Fusing Methodology
Enhanced Delay Test Generator for High-Speed Logic LSIs
A new methodology for improved tester utilization
System to Optimize Test Quality and Efficiency for Memories and LSI
Automated die inking: A pattern recognition-based approach
A high throughput test methodology for MCM substrates
ASSIST (Allied Signal's Standardized Integrated Scan Test)
Precise test generation for resistive bridging faults of CMOS combinational circuits
Design-For-Test Techniques Utilized in an Avionics Computer MCM
An Evaluation of I DDQ Versus Conventional Testing for CMOS Sea-of-Gate IC's
Switch-level delay test of domino logic circuits
Generation and Quality Evaluation of Synthetic Process Control Monitoring Data
Darwin, thy name is system
A Simulation-Based Protocol-Driven Scan-Test-Design Rule Checker
MT-SBST: Self-test optimization in multithreaded multicore architectures
IEEE P1581: To Live or Let die?
Verification and debugging of IDDQ test of low power chips
Testing during Burn-In: Economical Alternative for Testing Memories
Highly efficient parallel ATPG based on shared memory
IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver
Digital oscillation-test method for delay and stuck-at fault testing of digital circuits
New Front-End and Line Justification Algorithm for Automatic Test Generation
Fast and effective fault simulation for path delay faults based on selected testable paths
Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring
Design, technology and yield in the post-moore era
Efficient cross-layer concurrent error detection in nonlinear control systems using mapped predictive check states
A New Probing Technique for High-Speed/High-Density Printed Circuit Boards
A Microprocessor Based Method for Testing Transition Noise in Analog to Digital Converters
A new approach to mixed-signal diagnosis
Logic Device Characterization Using Computer-Aided Test and Analysis
Effectiveness of Timing-Aware Scan Tests in Targeting Marginal Failures and Silent Data Errors in a Data Center Processor
Macro Testability: The Results of Production Device Applications
Evaluating the Effects of Transient Faults on Vehicle Dynamic Performance in Automotive Systems
Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling
Jitters in high performance microprocessors
A Technique for Making Asynchronous Sequential Circuits Readily Testable
Incorporating Test Technology into an Undergraduate Curriculum
A Demonstration IC for the P1149.4 Mixed-Signal Test Standard
Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital ICs
IC Performance Prediction System
Arbitrary-Precision Signal Generation for Bandlimited Mixed-Signal Testing
Jitter spectrum analysis using continuous time interval analyzer (CTIA)
Technology Independent Boundary Scan Synthesis (Technology and Physical Issues)
Wafer Map Pattern Recognition for Multisite Probe with Synthetic Data Augmented Training
Optimal BIST Using an Embedded Microprocessor
Adaptive test flow for mixed-signal/RF circuits using learned information from device under test
Mining-guided state justification with partitioned navigation tracks
Testing of Bit-Serial Signal Processors
Redundancies and Don't Cares in Sequential Logic Synthesis
A matched expansion MEMS probe card with low CTE LTCC substrate
A Test Generator IC for Testing Large CMOS-RAMs
Protocol requirements in an SJTAG/IJTAG environment
A Multi-Language Goal-Tree Based Functional Test Planning System
A Tester-Independent Automated Test Preparation Process for Loaded Boards
Solutions for undetected shorts on IEEE 1149.1 self-monitoring pins
FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging
XIDEN: Crosstalk Target Identification Framework
Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures
Capacitive Leadframe Testing
Concurrent Engineering with DFT in the Digital System: A Parallel Process
Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs
Defect-oriented test quality assessment using fault sampling and simulation
A novel process and hardware architecture to reduce burn-in cost
Functional test content optimization for peak-power validation - An experimental study
Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip
Automating Test-Bed Fault Detection and Diagnosis
Low cost testing of multi-GBit device pins with ATE assisted loopback instrument
An Incomplete Scan Design Approach to Test Generation for Sequential Machines
Test of Digital Transversal Filters
Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution
Analysis of pseudo-interleaving AWG
High Current DPS Architecture for Sort Test Challenge
A Test Generation Methodology for High-Performance Computer Chips and Modules
IEEE International Test Conference, ITC 2018, Phoenix, AZ, USA, October 29 - Nov. 1, 2018
Adapting CAE Design Information for In-Circuit Test Generation
Implementation Update: Logic Mapping On SPARC- Microprocessors
FALCON: Rapid statistical fault coverage estimation for complex designs
Analysis of the Switching Behavior of Combinatorial Logic Networks
Cellular automata based self-test for programmable data paths
D^3FS: A Demand Driven Deductive Fault Simulator
FAMOUS: Fault Attack Mitigation via Exploiting Invariances in Deep Neural Networks
The use of tolerance intervals in the characterization of semiconductor devices
Comparing functional and structural tests
Improve Yield and Quality Through Testability Analysis of VLSI Circuits
Efficient Latch and Clock Structures for System-on-Chip Test Flexibility
On validating data hold times for flip-flops in sequential circuits
Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up
Statistical test: A new paradigm to improve test effectiveness & efficiency
An Asynchronous Scan Path Concept for Micropipelines using the Bundled Data Convention
Structure and Metrology for an Analog Testability Bus
Automatic Functional Test Generation - A Reality
Statistical Failure Detection Methods for Linear Analog Systems
Reducing Test Program Development Time for Memory Devices
Variation and failure characterization through pattern classification of test data from multiple test stages
IEEE International Conference on Automation, Quality and Testing, Robotics (AQTR)
Towards data reliable crossbar-based memristive memories
Why Would an ASIC Foundry Accept Anything Less than Full Scan?
enVision: the inside story
Scan Path in CMOS Semicustom LSI Chips ?
Increasing IJTAG bandwidth and managing security through parallel locking-SIBs
A structured approach for the systematic test of embedded automotive communication systems
Design Assurance in a University Setting
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
CADOC : A System for Computer Aided Functional Test
Easy mixed signal test creation with test elements and procedures
Bead probes in practice
MOS Gate Oxide Quality Control and Reliability Assessment by Voltage Ramping
Across the Great Divide: Examination of Simulation Data with Actual Silicon Waveforms Improves Device Characterization and Production Test Development
Advances in Membrane Probe Technology
Probe contact resistance variations during elevated temperature wafer test
On Potential Fault Detection in Sequential Circuits
BIST for phase-locked loops in digital applications
Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM
An IDDQ Sensor Circuit for Low-Voltage ICs
Techniques to improve memory interface test quality for complex SoCs
Mixed-Signal BIST: Fact or Fiction
Using Boundary Scan Test to Test Random Access Memory Clusters
Compaction of a Functional Broadside Test Set through the Compaction of a Functional Test Sequence without Sequential Fault Simulation
Built-in self-test in a 24 bit floating point digital signal processor
Functional Characterization of Microprocessors
Tester Architecture For The Source Synchronous Bus
DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCs
Comparison of IDDQ Testing and Very-Low Voltage Testing
Practice and Theory
Functional Logic Diagnosis with Observation Points on Next-State Variables
Thermal characterization of BIST, scan design and sequential test methodologies
Adaptive multidimensional outlier analysis for analog and mixed signal circuits
Delay Test Generation for Synchronous Sequential Circuits
I/O Self-Leakage Test
Analog fault models: Back to the future?
Automatic Visual Test of Surface Mount Assemblies
Jitter and Signal Integrity Verification for Synchronous and Asynchronous I/Os at Multiple to 10 GHz/Gbps
Security keynote: Ultra-low-energy security circuit primitives for IoT platforms
Jitter Generation and Measurement for Test of Multigbps Serial IO
On the Detection of Delay Faults
Mission Impossible? Open Architecture ATE
Real-Time Data Comparison for GigaHertz Digital Test
An Efficient, Forward Fault Simulation Algorithm Based on the Parallel Pattern Single Fault Propagation
Evaluating the Limitations of High-Speed Board Testers
Yield and reliability enhancement for 3D ICs: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist
Sequential logic synthesis for testability using register-transfer level descriptions
Challenge of the 90's: Testing CoreWare TM Based ASICs
R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique
Scan Path with Look Ahead Shifting (SPLASH)
A novel test methodology based on error-rate to support error-tolerance
Exploiting path delay test generation to develop better TDF tests for small delay defects
VLSI Functional Test Pattern Generation: A Design and Implementation
Towards Automatic Failure Analysis of Complex ICs Through E-Beam Testing
Testability considerations in the design of the MC68340 Integrated Processor Unit
Detection of Hard Faults in a Combinational Circuit Using Budget Constraints
Employing Massive Parallelism in Digital ATPG Algorithms
A method to enhance the fault coverage obtained by output response comparison of identical circuits
Parity Bit Calculation and Test Signal Compaction for BIST Applications
EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arrays
On-line testing of transient and crosstalk faults affecting interconnections of FPGA-implemented systems
Diagnostic techniques for the UltraSPARC microprocessors
High Quality Testing of Embedded RAMs Using Circular Self-Test Path
Efficient Pattern Mapping for Deterministic Logic BIST
Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault
A Simulation Environment for Early Lifecycle Software Reliability Research and Prediction
What Can IC Test Teach System Test?
Cost-effective approach to improve EMI yield loss
Test compression - real issues and matching solutions
Online Scan Diagnosis : A Novel Approach to Volume Diagnosis
Test Generation for Global Delay Faults