yusuke1997/dblp-id-title huggingface dataset:
UVM based STBUS verification IP for verifying SoC architectures
A novel architecture for QPSK modulation based on time-mode signal processing
Low-Power Sequential Circuit Design Using Work-Function Engineered FinFETs
Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology - (Invited Paper)
Optimized Test Pattern Generation for Digital Circuits using SAT-Based ATPG and Scan Insertion Method
A BDD based secure hardware design method to guard against power analysis attacks
A Reconfigurable Arbiter PUF Based on VGSOT MTJ
Molecular modeling of Nano bio p-i-n FET
Low Loss Enabled Semi-superjunction 4H-SiC IGBT for High Voltage and Current Application
σLBDR: Congestion-aware logic based distributed routing for 2D NoC
A mismatch insensitive reconfigurable discrete time biosignal conditioning circuit in 180 nm MM CMOS technology
Instruction cache design space exploration for embedded software applications
Design of CMOS Based Biosensor for Implantable Medical Devices
Power aware cache miss reduction by energy efficient victim retention
On Designing Testable Reversible Circuits Using Gate Duplication
Flexible Adaptive FIR Filter Designs Using LMS Algorithm
A 82μW Mixed-Mode sub-1V Bandgap reference with 25 ppm/°C Temperature Co-efficient with Simultaneous PTAT Generation
Fault Resilient Micro-Coded Control Unit for Space-Based Digital Systems
Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis
Study of HeavyIon Irradiation Effects in FinFETs at Sub-5 nm Technology Node: Reliability Perspective
Low Power Dual-Band Current Reuse-based LC-Voltage Controlled Oscillator with Shared Inductor for IoT Applications
Low Cost Circuit Level Implementation of PRESENT-80 S-BOX
An Ultra Low Power AES Architecture for IoT
A Lifting Instruction for Performing DWT in LEON3 Processor Based System-on-Chip
FPGA-based implementation of M4RM for matrix multiplication over GF(2)
Analysis of Device Noise in Bandgap Reference Voltage Generators
Novel Configuration of Multi-mode Universal Shadow Filter Employing a New Active Block
Approximate Computing Based Adder Design for DWT Application
An Efficient High Frequency and Low Power Analog Multiplier in Current Domain
Modified low power scan based technique
A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations
A cost-optimal algorithm for guard zone computation including detection and exclusion of overlapping
Simulation and characterization of dual-gate SOI MOSFET, on-chip fabricated with ISFET
A Pre-RTL floorplanner tool for automated CMP design space exploration with thermal awareness
Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM
Design and measurement techniques for a low noise amplifier in a receiver chain for MedRadio spectrum of 401-406 MHz frequency band
Design and simulative analysis of a batteryless Teflon coated capacitive pressure sensor for glaucoma diagnosis
An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs
Design and modeling of high-Q variable width and spacing, planar and 3-D stacked spiral inductors
A Framework for Branch Predictor Selection with Aggregation on Multiple Parameters
Automated Design of Analog Circuits using Machine Learning Techniques
ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits
Multi terminal net routing for island style FPGAs using nearly-2-SAT computation
Variability and reliability aware surrogate model for sensing delay analysis of SRAM sense amplifier
Aging Resilient and Energy Efficient Ring Oscillator for PUF Design
A Novel Droplet Routing Algorithm with Behavioral Performances in Hexagonal Electrode based DMFB
An impressive approach for incorporating parallelism in designing DMFB with cross contamination avoidance
Design and simulation of magnetic logic device for next generation data processing
xMAS Based Accurate Modeling and Progress Verification of NoCs
Backward compatible MIL-STD-1553B analog transceiver upgrade for 100-Mb/s data rate
Development of Radiation Hardened by Design(RHBD) primitive gates using 0.18μm CMOS technology
On-Chip Threshold Compensated Voltage Doubler for RF Energy Harvesting
An 18 mV Offset, 193 ps Sensing Delay, and Low Static Current Sense Amplifier for SRAM
High power gain low noise amplifier design for next generation 1-7GHz wideband RF frontend RFIC using 0.18μm CMOS
HARDWARE ACCELERATOR: IMPLEMENTATION OF CNN ON FPGA FOR DIGIT RECOGNITION
A Novel and Efficient SPI enabled RSA Crypto Accelerator for Real-Time applications
Cryptanalysis of hardware based stream ciphers and implementation of GSM stream cipher to propose a novel approach for designing n-bit LFSR stream cipher
An efficient hardware architecture for stereo disparity estimation
VLSI Design and Test - 21st International Symposium, VDAT 2017, Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers
Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology
Level-Accurate Peak Activity Estimation in Combinational Circuit Using BILP
Comprehensive Study and Photovoltaic Performance Analysis of Eco-friendly Perovskite Solar Cell
Ultrasensitive Multi-Arm-Microcantilever-Based Piezoresistive Sensor for BioMEMS Application
Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker
A 0-24mA, 1.2V/1.8V Dual Mode Low Dropout Regulator Design for Efficient Power Management in Battery-Powered Systems
On logic depth per pipelining stage with power aware flop, wave and hybrid pipelining with gate size and area constraints
>Optimization of CMOS compatible non-perovskite ferroelectric gate stack for designing low power Ferroelectric tunnel FETs
An approach for efficient FIR filter design for hearing aid application
An efficient on-chip energy processing circuit for micro-scale energy harvesting systems
Effect of Malicious Hardware Logic on Circuit Reliability
High Performance Operational Amplifier with 90dB Gain in SCL 180nm Technology
A small bandwidth microelectromechanical ring resonator-based bandpass filter
A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation
High Resolution Temperature Sensor Signal Processing ASIC for Cryo-Cooler Electronics
Study of reverse substrate bias effect of 22nm node epitaxial delta doped channel MOS transistor for low power SoC applications
Formal Verification and Analysis of a Pseudo Random Number Generator
Methodology for optimizing ESD protection for high speed LVDS based I/Os
A High Speed KECCAK Coprocessor for Partitioned NSP Architecture on FPGA Platform
High-Speed Unified Elliptic Curve Cryptosystem on FPGAs Using Binary Huff Curves
Energy-Efficient VLSI Architecture & Implementation of Bi-modal Multi-banked Register-File Organization
Analysis and design guidelines for customized logic families in CMOS
Analysis of Transient Negative Capacitance Characteristics for Stabilization and Amplification
Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective
A High Speed, Low Jitter and Fast Acquisition CMOS Phase Frequency Detector for Charge Pump PLL
Differential Multi-bit Through Glass Vias for Three-Dimensional Integrated Circuits
Performance optimization of real time control systems using variable time period
Improved Gate Modulation in Tunnel Field Effect Transistors with Non-rectangular Tapered Y-Gate Geometry
An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI
Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit
MAC based FIR filter: A novel approach for low-power real-time de-noising of ECG signals
Area compact 5T portless SRAM cell for high density cache in 65nm CMOS
A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance
An Overlap-and-Add Based Time Domain Acceleration of CNNs on FPGA-CPU Systems
Design and Optimization of a 2x2 Directional Microstrip Patch Antenna
An Efficient Test and Fault Tolerance Technique for Paper-Based DMFB
2L-2D Routing for Buffered Mesh Network-on-Chip
Radiation Hardened Area-Efficient 10T SRAM Cell for Space Applications
All-Digital CMOS On-Chip Temperature Sensor with Time-Assisted Analytical Model
SFG Based Fault Simulation of Linear Analog Circuits Using Fault Classification and Sensitivity Analysis
All optical implementation of Mach-Zehnder interferometer based reversible sequential circuit
Guided multilevel approximation of less significant bits for power reduction
A VLIW-Vector co-processor design for accelerating Basic Linear Algebraic Operations in OpenCV
Meminductor Emulator via Flux Approach for Wide Frequency Range Applications
Power analysis attack using neural networks with wavelet transform as pre-processor
Simulation Study of III-V Lateral Tunnel FETs with Gate-Drain Underlap
250mA ultra low drop out regulator with high slew rate double recycling folded cascode error amplifier
Low-leakage architecture for embedded ROM
Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications
Tag only storage for capacity optimised last level cache in chip multiprocessors
Low Cost Hardware Design of ECC Scalar Multiplication
A Calibration Technique for Current Steering DACs - Self Calibration with Capacitor Storage
Real time multisensor Laplacian fusion on FPGA
Design of coherence verification unit for CMPs realizing dragon protocol
Design and Calibration of 14-bit 10 KS/s Low Power SAR ADC for Bio-medical Applications
Low Cost Implementation of Deep Neural Network on Hardware
Timing model for two stage buffer and its application in ECSM characterization
Fabrication and LBM-Modeling of Directional Fluid Transport on Low-Cost Electro-Osmotic Flow Device
Modeling and simulation of variable thickness based stepped MEMS cantilever designs for biosensing and pull-in voltage optimization
A 31 ppm/° C Pure CMOS Bandgap Reference by Exploiting Beta-Multiplier
Low power and hardware cost STUMPS BIST
RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor
Verilog-A implementation of energy-efficient SAR ADCs for biomedical application
An offset-tolerant self-correcting sense amplifier for robust high speed SRAM
19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015
A constraint driven technique for MOS amplifier design
A Novel Symbol Estimation Algorithm for LTE Standard
Resistive Switching Behavior of TiO 2 /(PVP: MoS 2 ) Nanocomposite Bilayer Hybrid RRAM
Asynchronous Hardware Design for Floating Point Multiply-Accumulate Circuit
Low power, high speed error tolerant multiplier using approximate adders
High Speed and Power Efficient Multiplexer based Matrix Vector Multiplication for LSTM Network
VLSI Architecture for Spatial Domain Spread Spectrum Image Watermarking Using Gray-Scale Watermark
Implementation of an Efficient Charge Pump using Gate All Around Nanowire TFET for Energy Harvesting Applications
Particle Swarm Optimization guided multi-frequency power-aware System-on-Chip test scheduling using window-based peak power model
An inductorless receiver front-end for multiband wireless applications
Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cell
Enhanced Logical Locking for a Secured Hardware IP Against Key-Guessing Attacks
Thermal aware AND-OR-XOR network synthesis
FEM Modeling of Thermal Aspect of Dielectric Inserted Under Source & Drain of 5 nm Nanosheet
TID effects on retention of 0.13 μm SONOS memory cell: A device simulation approach
Improving the Design of Nearest Neighbor Quantum Circuits in 2D Space
Sensitivity and non-linearity study and performance enhancement in bossed diaphragm piezoresistive pressure sensor
Design and Analysis of a Novel Noise Cancelling Topology for Common Gate UWB LNAs
Performance-Enhanced d^2 -LBDR for 2D Mesh Network-on-Chip
Switched-capacitor circuit simulator in Q-V domain including nonidealities
A GaN Based Reverse Recovery Time Limiter Circuit Integrated with a Low Noise Amplifier
Delay and Frequency Investigations in Coupled MLGNR Interconnects
Integrated Placement and Optimization Flow for Structured and Regular Logic
Tile Serial Protocol (TSP) ASIC for Distributed Controllers of Space-Borne RADAR
Programmable output switched capacitor step-down DC-DC converter with high accuracy using Sigma-Delta Feedback Control Loop
HOAA: Hybrid Overestimating Approximate Adder for Enhanced Performance Processing Engine
Simulation Study of an Ultra Thin Body Silicon On Insulator Tunnel Field Effect Transistor
Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance
Quantum Tunnelling and Themonic Emission, Transistor Simulation
A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power
Towards a dynamic associativity enabled write prediction based hybrid cache
Design and Analysis of Ultra-Low Power Adiabatic Computational Subsystem Based on Symmetric Stacking
CORDIC on a configurable serial architecture for biomedical signal processing applications
Enhancing Performance and Scalability: A Novel Hardware Architecture for 1024-bit Miller-Rabin Primality Testing
A Novel Gate-Level On-Chip Crosstalk Noise Reduction Circuit for Deep Sub-micron Technology
Density gradient quantum corrections based performance optimization of triangular TG bulk FinFETs using ANN and GA
Power- and thermal-aware testing of VLSI circuits and systems
Indigenous Fab-Lab Hybrid Device Integration for Phase Change Memory for In-Memory Computing
Design of Current Mode Sigmoid Function and Hyperbolic Tangent Function
An Improved g m / I D Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design
Translation Validation of Loop Invariant Code Optimizations Involving False Computations
Selecting Rectification Targets for Patching Buggy Circuits
A high speed low voltage latch type sense amplifier for non-volatile memory
FFT/IFFT implementation using Vivado™ HLS
An efficient searching mechanism for dynamic NUCA in chip multiprocessors
Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard
An Efficient RF Energy Harvester with Tuned Matching Circuit
An Approach for Detection of Node Displacement Fault (NDF) in Reversible Circuit
Temperature Insensitive Low-Power Ring Oscillator Using only n-type Transistors
Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology
Defeating HaTCh: Building Malicious IP Cores
Delay Efficient All Optical Carry Lookahead Adder
A Space Efficient Greedy Droplet Routing for Digital Microfluidics Biochip
Low Power, Wideband SiGe HBT LNA Covering 57-64 GHz Band
High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications
Design and implementation of DVB-S2 transport stream for onboard processing satellite
Functional Simulation Verification of RISC-V Instruction Set Based High Level Language Modeled FPU
Intelligent Traffic Light Controller: A Solution for Smart City Traffic Problem
An Efficient Technique for Longest Prefix Matching in Network Routers
An area and performance aware ECG encoder design for wireless healthcare services
Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoC
A Novel Approach to Detect Hardware Malware Using Hamming Weight Model and One Class Support Vector Machine
A 2.47 GHz ultra NanoCrystaline diamond disk resonator with temperature compensation for RF application
Investigating the Role of Parasitic Resistance in a Class of Nanoscale Interconnects
Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder
Progress in VLSI Design and Test - 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings
A fault tolerant test hardware for L1 cache module in tile CMPs architecture
Supply and Temperature Independent Voltage Reference Circuit in Subthreshold Region
Out of order floating point coprocessor for RISC V ISA
Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL's 0.18 µm CMOS Process
Energy Efficient, Hamming Code Technique for Error Detection/Correction Using In-Memory Computation
Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin
Droplet Position Estimator for Open EWOD System Using Open Source Computer Vision
Design and Implementation of 5-Stage Pipelined RISC-V Processor on FPGA
DynRP- Non-Intrusive Profiler for Dynamic Reconfigurability
FPGA based High Frequency Clock Phase Difference Measurement and Correction
A Dependability Preserving Fluid-Level Synthesis for Reconfigurable Droplet-Based Microfluidic Biochips
A Methodology for Early and Accurate Analysis of Inrush and Latency Tradeoffs during Power-Domain Wakeup
Security Assessment of Rotation Countermeasure for Protection Against Fault Attacks
A 10-bit 0.9-GS/s Segmented Flash ADC
Data dependent spurious power reduction for fixed width multiplier
Runtime Prediction for VLSI Physical Design Processes using Machine Learning
Assessing Task-to-Data Affinity in the LLVM OpenMP Runtime
OpenMP-Q: Quantum Task Offloading in OpenMP
Parallelism and Scalability in an Image Processing Application
Beyond Loop Level Parallelism in OpenMP: Accelerators, Tasking and More, 6th Internationan Workshop on OpenMP, IWOMP 2010, Tsukuba, Japan, June 14-16, 2010, Proceedings
Just-in-Time Compilation and Link-Time Optimization for OpenMP Target Offloading
Towards Unifying OpenMP Under the Task-Parallel Paradigm - Implementation and Performance of the taskloop Construct
Suspending OpenMP Tasks on Asynchronous Events: Extending the Taskwait Construct
An Evaluation of OpenMP on Current and Emerging Multithreaded/Multicore Processors
Adaptive and Architecture-Independent Task Granularity for Recursive Applications
Multiple Target Task Sharing Support for the OpenMP Accelerator Model
Adaptive OpenMP for Large NUMA Nodes
Optimization Strategies Using Hybrid MPI+OpenMP Parallelization for Large-Scale Data Visualization on Earth Simulator
Experiences Parallelizing a Web Server with OpenMP
OpenMP 4.0 Device Support in the OMPi Compiler
Towards an OpenMP Specification for Critical Real-Time Systems
Application-Level Energy Awareness for OpenMP
MetaFork: A Framework for Concurrency Platforms Targeting Multicores
Automatic OpenMP Loop Scheduling: A Combined Compiler and Runtime Approach
Implementing an OpenMP Execution Environment on InfiniBand Clusters
Implementation of OpenMP Work-Sharing on the Cell Broadband Engine Architecture
Visualization of OpenMP* Task Dependencies Using Intel® Advisor - Flow Graph Analyzer
Expressing DOACROSS Loop Dependences in OpenMP
A Compiler-Assisted Runtime-Prefetching Scheme for Heterogeneous Platforms
An Introduction to Balder - An OpenMP Run-time Library for Clusters of SMPs
User Co-scheduling for MPI+OpenMP Applications Using OpenMP Semantics
Nested Parallelization of the Flow Solver TFS Using the ParaWise Parallelization Environment
Towards Locality-Aware Host-to-Device Offloading in OpenMP
Toward a Standard Interface for User-Defined Scheduling in OpenMP
First Experiences with Intel Cluster OpenMP
SPEC OpenMP Benchmarks on Four Generations of NEC SX Parallel Vector Systems
Developing an Interactive OpenMP Programming Book with Large Language Models
: A Profiling Tool for OpenMP
An OpenMP Free Agent Threads Implementation
Evaluating the Impact of OpenMP 4.0 Extensions on Relevant Parallel Workloads
Static Validation of Barriers and Worksharing Constructs in OpenMP Applications
Extending OpenMP Metadirective Semantics for Runtime Adaptation
On the Roles of the Programmer, the Compiler and the Runtime System When Programming Accelerators in OpenMP
The TRegion Interface and Compiler Optimizations for OpenMP Target Regions
OpenMP Implementation of SPICE3 Circuit Simulator
Leveraging OpenMP 4.5 Support in CLANG for Fortran
OpenMP Parallelization and Optimization of Graph-Based Machine Learning Algorithms
Asynchronous OpenMP Tasking with Easy Thread Context Switching and Pool Control
Evaluating OpenMP Implementations for Java Using PolyBench
Advancing OpenMP for Future Accelerators - 20th International Workshop on OpenMP, IWOMP 2024, Perth, WA, Australia, September 23-25, 2024, Proceedings
Auto-scoping for OpenMP Tasks
Unifying Barrier and Point-to-Point Synchronization in OpenMP with Phasers
Dynamic Task and Data Placement over NUMA Architectures: An OpenMP Runtime Perspective
Extending the OpenMP Standard for Thread Mapping and Grouping
OpenMP in a Modern World: From Multi-device Support to Meta Programming - 18th International Workshop on OpenMP, IWOMP 2022, Chattanooga, TN, USA, September 27-30, 2022, Proceedings
Towards Transactional Memory for OpenMP
Language-Centric Performance Analysis of OpenMP Programs with Aftermath
OpenMP: Enabling Massive Node-Level Parallelism - 17th International Workshop on OpenMP, IWOMP 2021, Bristol, UK, September 14-16, 2021, Proceedings
The OpenMP Memory Model
A Proposal for OpenMP for Java
Open Source Task Profiling by Extending the OpenMP Runtime API
OpenMP Extensions for Heterogeneous Architectures
CLOMP: Accurately Characterizing OpenMP Application Overheads
CMP Cache Architecture and the OpenMP Performance
Composing Low-Overhead Scheduling Strategies for Improving Performance of Scientific Applications
Performance and Programmability Comparison Between OpenMP and MPI Implementations of a Molecular Modeling Application
OMPSan: Static Verification of OpenMP's Data Mapping Constructs
A Comparison of Task Pool Variants in OpenMP and a Proposal for a Solution to the Busy Waiting Problem
Estimation of Round-off Errors in OpenMP Codes
Preliminary Experience with OpenMP Memory Management Implementation
OpenMP Dynamic Device Offloading in Heterogeneous Platforms
The Kokkos OpenMPTarget Backend: Implementation and Lessons Learned
Evaluating OpenMP Affinity on the POWER8 Architecture
The Secrets of the Accelerators Unveiled: Tracing Heterogeneous Executions Through OMPT
Towards Automatic OpenMP-Aware Utilization of Fast GPU Memory
Supporting Indirect Data Mapping in OpenMP
Towards a Scalable and Efficient PGAS-Based Distributed OpenMP
Evaluating OpenMP on Chip MultiThreading Platforms
Multilayer Multipurpose Caches for OpenMP Target Regions on FPGAs
The Productivity, Portability and Performance of OpenMP 4.5 for Scientific Applications Targeting Intel CPUs, IBM CPUs, and NVIDIA GPUs
FAROS: A Framework to Analyze OpenMP Compilation Through Benchmarking and Compiler Optimization Analysis
On the Benefits of Tasking with OpenMP
Use of Cluster OpenMP with the Gaussian Quantum Chemistry Code: A Preliminary Performance Analysis
On the Performance of Parallel Tasking Runtimes for an Irregular Fast Multipole Method Application
Towards Task-Parallel Reductions in OpenMP
STEP: A Distributed OpenMP for Coarse-Grain Parallelism Tool
Evaluating the Energy Consumption of OpenMP Applications on Haswell Processors
Enhancing MPI+OpenMP Task Based Applications for Heterogeneous Architectures with GPU Support
A Proposal to OpenMP for Addressing the CPU Oversubscription Challenge
An Efficient OpenMP Runtime System for Hierarchical Architectures
FOTV: A Generic Device Offloading Framework for OpenMP
Virtflex: Automatic Adaptation to NUMA Topology Change for OpenMP Applications
Characterizing the Performance of Task Reductions in OpenMP 5.X Implementations
Double Buffering for MCDRAM on Second Generation $$\hbox {Intel}^{\circledR }$$ Xeon Phi $$^{\text {TM}}$$ Processors with OpenMP
Profile Generation for GPU Targets
An OpenMP Extension Library for Memory Affinity
Experiments with WRF on Intel® Many Integrated Core (Intel MIC) Architecture
Fuzzy Application Parallelization Using OpenMP
Trade-Off of Offloading to FPGA in OpenMP Task-Based Programming
Exploring the Limits of Generic Code Execution on GPUs via Direct (OpenMP) Offload
Using OpenMP to Detect and Speculate Dynamic DOALL Loops
Evaluating OpenMP Tasking at Scale for the Computation of Graph Hyperbolicity
A Case Study of Porting HPGMG from CUDA to OpenMP Target Offload
Using OpenMP under Android