yusuke1997/dblp-id-title huggingface dataset:
How close to the CMOS voltage scaling limit for FinFET technology? - Near-threshold computing and stochastic computing
Memristor models and circuits for controlling Process-VDD-Temperature variations
A Wide-Range 12b 150MS/s P-SAR ADC with Open-Loop Residue Amplifier for Ultrasound AFE
An experimental study on the potential use of ReRAM as SSD buffer
An 8-bit 100KS/s low power successive approximation register ADC for biomedical applications
Design and development of a self-contained and non-invasive integrated system for electricity monitoring applications
A Low-Complexity Algorithm for JPEG-LS-Based RAW Domain Compression
A Low Jitter Current-Mode Multiplying Delay-Locked Loop Applied to High-Precision TDC
A hall sensor microsystem for current measurement used in watt-hour meter
Multi-physiological Parameters Integrated Medical System for Home Healthcare Application
A noise rejective VCO with build-in active LC filter
An overview of charge pumping circuits for flash memory applications
Training Adaptive Hardware for Reconfigurability: A Simplified Case Study
A thermal-aware mapping algorithm for 3D Mesh Network-on-Chip architecture
A 2.4 mW, 11.7±0.4dB, 3 to 5 GHz wide-band LNA for super-regenerative IR-UWB receiver
Network functions for characterization of elementary semiconductor nanostructures
Novel superjunction collector design of power SiGe HBTs for high fT×BVCEO×β product
An On-chip Path Delay Measurement Sensor for Aging Monitoring
Data dependency aware prefetch scheduling for Dynamic Partial reconfigurable designs
Development and characterization of TaN thin film resistor with CMOS compatible fabrication process
A novel adaptive CMOS low-dropout regulator with 3A sink/source capability
A novel configuration context cache structure of reconfigurable systems
An area efficient low power ECoG front-end chip for digitalized subdural grid
Analysis of adaptive support-weight based stereo matching for hardware realization
Photoelectron In-situ Sensing Device with embedded photodiode and interface passivation
Graphene electronics and photonics (Invited)
A Cold-Start SECE and BUCK-SECE Hybrid Rectifier for Piezoelectric Energy Harvester
Influence of nitrogen buffering on oxygen in indium-tin-oxide capped resistive random access memory with NH3 treatment
Exploration for energy-efficient ECC decoder of WBAN
A 1.2V output RF energy harvester with a harvesting-efficiency tracking circuit
System-level modeling and analysis of third order MEMS accelerometer
An 4 th -order N-path Bandpass Filter with a Tuning Range of 1-30 GHz and OOB Rejection > 30 dB in 28 nm CMOS
A harmonic-free cell-based all-digital delay-locked loop for die-to-die clock synchronization of 3-D IC
Challenges of emerging memory and memristor based circuits: Nonvolatile logics, IoT security, deep learning and neuromorphic computing
Algorithms based on all-digital phase-locked loop for fast-locking and spur free
An FPGA based verification platform for pipeline ADC digital calibration technology
A high speed reconfigurable face detection architecture
Low power shift registers for megabits CMOS image sensors
A signal noise separation method for the instant mixing linear and nonlinear circuits with MISEP algorithm
Exploring stacked main memory architecture for 3D GPGPUs
Determination of the trap states distribution in Poly-Si films using the OEMS modulation
A method to speed up VLSI hierarchical physical design in floorplanning
System modeling and analysis of the IEEE 802.15.4 physical layer design
A Multi-channel 12-bits 100MS/s SAR ADC in 65nm CMOS
A Fast-Transient Right-Half-Plane Zero-Free Hybrid Buck-Boost Converter
A 76μW, 58-dB SNDR analog front-end chip for implantable intraocular pressure detection
A deterministic optimal task migration algorithm design in NoC-based multi-core system
Waveform base clock tree delay analysis using parallel processing
A Method of Mapping Convolutional Neural Networks on Resource-limited NoC Platform
A 60-GHz wireless transceiver with dual-mode power amplifier for IEEE 802.11ad in 65nm CMOS
Optimizing Supervised Learning of Deep Spiking Neural Network towards Memristor Crossbar Implementation
Design of Analog CMOS-Memristive Neural Network Circuits for Pattern Recognition
Resistive random access memory with high selectivity and ON/OFF ratio amplification sensing
Two sides of pulse quenching effect on the single-event transient pulse width at circuit-level
A novel digital controller for boost PFC converter with high power factor and fast dynamic response
Solution Processed Metal Oxide in Emerging Electronic Devices
A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power
A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC
High-Performance Rejection Sampling Hardware Circuit Design for Kyber
An ultra low power ASK demodulator for passive UHF RFID tag
A Low-power Digital Automatic Gain Control Design in Wireless Communication Receivers
Optimizing Wirelength And Delay of FPGA Tile through Floorplanning Based on Simulated Annealing Algorithm
The write deduplication mechanism based on a novel low-power data latched sense amplifier for a magnetic tunnel junction based non-volatile memory
Simulation of SEU Response of Advanced 20 nm FDSOI SRAMs
A collision and tag number detector for UHF RFID reader conforming to EPC Gen2 protocol
A configurable distributed systolic array for QR decomposition in MIMO-OFDM systems
Arbitrary Style Transfer via Learning to Paint in the Feature Domain
An integrated stacked transformer with large inductance at 900MHz
A 12-bit 50-MSPS SHA-less opamp-sharing Analog-to-Digital converter in 65nm CMOS
An Ultra-Low Power Cycle-by-Cycle Current Limiter Suitable for Switching-Mode Power Supply with 2.2 MHz Frequency
HierSyn: Fast Synthesis for Large Hierarchical Designs
A robust frame synchronization scheme for Broadband Power-line Communication
A fully integrated 0.18 μm SiGe BiCMOS power amplifier
Digitally-controlled cell-based oscillator with multi-phase differential outputs
Data pre-emphasis based retention reliability enhance scheme for MLC NAND Flash memories
Analytical models for threshold voltage, drain induced barrier lowering effect of junctionless triple-gate FinFETs
Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits
A scalable hardware architecture for multi-layer spiking neural networks
Wireless Sensor Brain Machine Interfaces for Closed-loop Neuroscience Studies
A 16-bit Pixel-level ADC Based on Ring Oscillator for 30μm Pitch 320 ×256 LWIR FPAs
A Novel RFID Architecture supporting accurate Clock Transfer for Backscatter Communication
An Efficient Space Spatiotemporal Noise Filter for Dynamic Vision Sensor
A cluster-scalable VLIW cryptography processor with high performance and energy efficiency
A novel Operational Transconductance Amplifier with high Gm using improved differential current redistribution technique (DCRT)
CMOS 1.2V bandgap voltage reference design
A method to build reconfigurable architectures by extracting common subgraphs
A Bang-Bang Phase Detector for PAM-N Signaling
A 0.69% LED Current Error LED Driver with Hysteretic Current Control
A wide lock-range, low jitter phase-locked loop for multi-standard SerDes application
A Configurable Architecture of ANN in Hardware with Resource-Efficient Reusable Neuron
A low noise and highly linear 2.4-GHz RF front-end circuit for wireless sensor networks
Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors
A 16-bit two-step pixel-level ADC for 384∗288 infrared focal plane array
An energy-efficient microprocessor using multilevel error correction for timing error tolerance
System level performance evaluation of three-dimensional integrated circuit
A Second-Order Passive Noise-Shaping SAR ADC Using the LMS-Based Mismatch Calibration
A 2D Clock Interconnect Electromigration-Thermal Coupling Simulation Method Based on COMSOL
Ring Oscillators with identical Circuit Structure to Measure Bias Temperature Instability
Welcome to ASICON 2011
Noise analysis of a CDS circuit with offset canceling
A wide tuning range low-pass Gm-C filter for multi-mode wireless receivers with automatic frequency calibration
Design of energy efficient LDPC decoders with low-voltage strategy
Dual control mode AGC for wireless communication system
A 0.0558-mm 2 0.05-0.9GHz Low-Power Multi-phase Non-overlap Clock Generator in 40 nm CMOS
A wideband VCO with constant tuning-gain and uniform sub-band interval for single-chip UHF RFID reader
Combined-solvent engineering of HPbI3 for efficient FAPbI3 perovskite solar cells
A Multi-mode Convolution Coprocessor Based on RISC-V Instruction Set Architecture
Implementation of H.264 intra-frame encoding on clustered stream architectures
ANN Based Adaptive Successive Cancellation List Decoder for Polar Codes
Low power design for FIR filter
A High-Sensitivity, Low-Power Dual-Band RF Energy Harvesting and Managing System for Bio-Potential Acquisition
Linearity enhancement algorithms for I-Q signal generation - DWA and self-calibration techniques
FPGA logic design of SATA3.0 physical layer
A novel stack package solution of AC-DC chip for high-power density adapters
TLP evaluation of ESD protection capability of graphene micro-ribbons for ICs
A Compact 144% Fractional Bandwidth CMOS Power Amplifier With an Optimization of Synthesized High-Order Matching Network
A Polymorphic Circuit Interoperability Framework
Switching dynamics and computing applications of memristors: An overview
Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit
Characteristics of n-MOSFETs with stress effects from neighborhood devices
A Model-Guided Underwater Image Enhancement Network
An Efficient Markov Random Field Based Denoising Approach for Dynamic Vision Sensor
An 842 nW Wearable Inter-Patient Cardiac Arrhythmia Monitoring Processor with a Feature Engine-Based Artificial Neural Network
A study on HCI induced gate leakage current model used for reliability simulations in 90nm n-MOSFETs
10 Mbps high-voltage digital transciever on single die for 50 V voltage swing
Low power FIR filter design for wearable devices using frequency response masking technique
A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period
Analysis and design of a high linearity quadrature demodulator based on SiGe BiCMOS process
Fundamental design tradeoff and performance limitation of electronic circuits based on uncertainty relationships
Adaptive Weight Mapping Strategy to Address the Parasitic Effects for ReRAM-based Neural Networks
Reconfigurable Clock Tree Design Methodology for Wide Voltage Scaling Using Custom Buffer
Simulation design for continuous separating and 3D focusing of particles based on inertial microfluidics
A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique
High-speed Classification of AER Data Based on a Low-cost Hardware System
Variation-resilient voltage generation for SRAM weak cell testing
Performance analysis for matrix-multiplication based on an heterogeneous multi-core SoC
A 30GHz Bidirectional PA/LNA with Transformer-Based Switchable RC Matching Network
A new event driven testbench synthesis engine for FPGA emulation
Novel operation scheme and technological optimization for 1T bulk capacitor-less DRAM
A 0.3V-to-1.1V standard cell library in 40nm CMOS
Circuits and systems for 5G network: Massive MIMO and advanced coding
An electro-optical full-subtractor using hybrid-integrated silicon-graphene waveguides
A novel equivalent circuit model of the surge wave generator
A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight
A GHz-level ring-counter-based multi-modulus fractional LO divider with on-the-fly tunability
DSSMNeRF: Depth Self-supervised MVS NeRF
Latest Development on Non-Contact Vital Signs (NCVS) Sensor Systems Using Software Defined Radio (SDR)
A UHF Semi-Passive RFID System with Photovoltaic/Thermoelectric Energy Harvesting for Wireless Sensor Networks
Positionable wearable fall detection system for elderly assisted living applications
Hardware Acceleration Linear Matrix Solvor Based on FPGA
Design of a high throughput configurable variable-length FFT processor based on switch network architecture
A High Precision Current Sampling Circuit with Rail-to-Rail Common-Mode Input Range
Heterogeneous computing for CNN
New design for low complexity and low power partial programmable shifters
A reconfigurable linear array processor architecture for data parallel and computation intensive applications
A 100M-1.5 GHz harmonic-rejection SDR receiver front-end
An Adder-Segmentation-based FIR for High Speed Signal Processing
Multi-Thread Assembling for Fast FEM Power Delivery DC Integrity Analysis
Design of four-transistor Pixel for high speed CMOS image
Low-voltage CMOS DC-DC converters for energy harvesting applications
Demonstrate high Roff/Ron ratio and forming-free RRAM for rFPGA application based on switching layer engineering
A highly reliable lightweight PUF circuit with temperature and voltage compensated for secure chip identification
A Driver Amplifier with Configurable Transformer-Based Matching Networks in 65-nm CMOS
Design and implementation of pipelined TMVP multiplier using block recombination
Memristor-based material implication logic design for full adders
An Energy-Efficient Systolic Pipeline Architecture for Binary Convolutional Neural Network
Design of the 1.0V bandgap reference on chip
A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs
The design of face recognition system based on ARM9 embedded platform
A Dual Path Hybrid Step-Up Converter with Enhanced Drive Voltage for Low Voltage Applications
An efficient low-cost fixed-point digital down converter with modified filter bank
Design and Implementation of A High-speed Configurable 2D ML-CFAR Detector
Overcoming the challenges of ReRAM towards mass production from the perspectives of process, design and application
Design of Wideband Phase Modulator for 2.4~5.25 GHz Digital Polar Transmitter
Elliptic curve GF (p) point multiplier by dual arithmetic cores
A control scheme for a 65nm 32×32b 4-read 2-write register file
Hardware Acceleration of Elliptic-Curve based Crypto-Algorithm, ECDSA and Pairing Engines
The decimator with multiplier-free realizations for high precision ADC applications
A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder
Single event upset mitigation for FDP2008
An Ultra-Low Specific On-Resistance LDMOS With Segmented LOCOS In 0.18 μm BCD Process Platform
Exploring Machine Learning Adoption in Customisable Processor Design
14th IEEE International Conference on ASIC, ASICON 2021, Kunming, China, October 26-29, 2021
A Novel Signed Bit-serial Fixed-point Accumulator with Configurable Overflow-Protection Precision
Generation of low power testing based on novel SIC sequences
A Low-Delay Self-Interference Cancellation Chip with Embeded Channel Sounding Ability
Using Fermat number transform to accelerate convolutional neural network
An Optimized Face Recognition for Edge Computing
Hybrid LED driver for multi-channel output with high consistency
Current-mode square-wave converter with current-rectifying function employing MOCCII
Machine Learning-Assisted Single-Event Transient Model of 12nm FinFETs for Circuit-Level Simulation
A high-resolution pipeline time-to-digital converter in 0.18μm CMOS technology
Post-bond test for TSVs using voltage division
A method of automatic sizing logic driver of 16nm Fin-FET
A simulation analysis of back gate effects for FDSOI devices
Design of a high voltage gate driver module
A low-power self-calibration digital-output CMOS temperature sensor with ±0.1°C inaccuracy from -40°C to 85°C
Evaluation of Null Method for Operational Amplifier Short-Time Testing
A novel Differential fault analysis on AES-128
A voltage doubling AC-DC converter with offset-controlled comparators for piezoelectric energy harvester
A 1.5-GS/s 5-bit interpolating ADC with offset averaging and interpolating sharing resistors network
Application of cellulose triacetate as biocompatible/biodegradable dielectrics in EWOD devices
A 1.0-to-2.4GHz wideband VCO with uniform sub-band interval and constant tuning gain
Design of Majority Logic Based 4-bit Approximate Subtractors and its Application in Divider
Small Object Detection in Aerial Images
An area-efficient implementation of ΣΔ ADC multistage decimation filter
An efficient parity rearrangement coding scheme for RRAM thermal crosstalk effects
Network-coding-based distributed relay scheme for PLC networks
Analysis and characterization of process/layout impacts on the performance of high-speed analog circuits
An Accurate and Efficient Yield Analysis for SRAM dynamic metrics Using Differential Evolution Algorithm
A 6-13 GHz wide-tuning-range low-phase-noise ring oscillator utilizing frequency multiplication technique
Frame synchronization for a narrow-band power line OFDM communication system
OpenMPL: An Open Source Layout Decomposer: Invited Paper
Low power instruction cache design based on branch execution tracks
FFT implementation with Multi-operand floating point units
A 39 GHz-80 GHz millimeter-wave frequency doubler with low power consumption in 65nm CMOS tehnology
Object-recognition VLSI for pedestrian detection in automotive applications
Development and Optimization of Contact Module Process for Micro-Bridge Structure based MEMS/Sensor Application
A high-performance PWM controller with adjustable current limit
An assessment of RTN-induced threshold voltage jitter
A 100MS/s 5bit fully digital flash ADC with standard cells
A Hardware Efficient Approximate Shift Multiplier with High Accuracy
EMI reduction by analog noise spread spectrum in new ripple controlled converter
An Optimal Designed Compensator for PSR Flyback Converters Based on Genetic Algorithm
Pulse Coding Control Switching Converter with Adjustable Conversion Voltage Ratio Notch Frequency Generation in Noise Spectrum
Floorplan-driven high-level synthesis using volatile/non-volatile registers for hybrid energy-harvesting systems
A 80-dB DR, 10-MHz BW continuous-time sigma-delta modulator with low power comparators and switch drivers
A 25-Gb/s 32.1-dB CMOS limiting amplifier for integrated optical receivers
Oscillator phase noise verification accounting for process variations
Incremental layout optimization for NoC designs based on MILP formulation
Spin orbit torques for ultra-low power computing
TSV modelling in 3D IC thermoelectric simulation
Approximate Multiplier Using Reordered 4-2 Compressor with OR-based Error Compensation
A Practical High-Level Synthesis Framework
Channel Stress Engineering Through Source/Drain Recess Optimization and Its Process Variation Study for 5 nm-node FinFETs
A low-cost SoC implementation of AES algorithm for bio-signals
An Adaptive Current Source IGBT Gate Driver Based on Current and Voltage Slope Feedback to Reduce EMI
Effects of unintended dopants on I-V characteristics of the double-gate MOSFETs, a simulation study
A CMOS charge pump with dual compensation amplifiers for phase-locked loops synthesizer
Cooptimization of emerging devices and architectures for energy-efficient computing
A high conversion coefficient RF front end of ultra-low power RFID tag
Machine Learning in Nanometer AMS Design-for-Reliability : (Invited Paper)
A power-efficient reconfigurable two-step VCO-based ADC for software-defined radio
High Intensity Focused Ultrasound for Noninvasive Medical Applications
A Reusable AI acceleration Architecture based on Matrix Multiplication for Convolutional Neural Network with Digital Signal ProcessingTasks
Novel flash ion sensitive field effect transistor for chemical sensor applications
Smart Gate Driver ICs for GaN Power Transistors
Surface effect on the current-voltage characteristics of back-gated MoS2 channel MOSFET
A cost-effective method for masking transient errors in NoC flit type
Optimization of High Reliability and Wide SOA 100 V LDMOS Transistor with Low Specific On-Resistance
Research on reconfigurable multiplier unit based on GF[(2 8 )] 4 field of symmetric cryptography
Fine Time Resolution TDC Architectures -Integral and Delta-Sigma Types
Graphene nanodots with high-k dielectrics for flash memory applications
A low-power 4.224GS/s sampler in 0.13-µm CMOS for IR UWB receiver
Design of Ka band bandpass filter using silicon micromachined technology
An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing
A Charge Pump with Perfect Current Matching Applied to Phase-Locked Loop in 65nm CMOS
Fabrication of high-performance a-IGZO thin-film transistor with post-annealing treatment
An FPGA-based Hardware Accelerator of RANSAC Algorithm for Matching of Images Feature Points
A novel start-up circuit for boost DC-DC converter with synchronous power-switch current-limit
Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches
Energy-efficient sub-threshold level shifter
TSVs-aware floorplanning for 3D integrated circuit
Dynamics of Ferroelectric and Ionic Memories: Physics and Applications
A folded current-reused CMOS power amplifier for low-voltage 3.0-5.0 GHz UWB applications
An Analytical Jitter Transfer Model for Mueller-Muller Clock and Data Recovery Circuits
Numerical characterization of multi-dielectric green's function for floating random walk based capacitance extraction
Low-Dropout Regulator design with a simple structure for good high frequency PSRR performance based on Bandgap Circuit
TCAD simulations of novel Interrupted-P-Finger UV/Blue photodiode based on CMOS process
An Enhanced Packing Algorithm for FPGA Architectures without Local Crossbar
Customizing CMOS/ReRAM Hybrid Hardware Architecture for Spiking CNN
Overshoot Cancelation Based on Balanced Charge-Discharge Time Condition for Buck Converter in Mobile Applications
Energy-efficient standby current suppression with bootstrapped power-gating technique
Linear Dropout Regulator based power distribution design under worst loading
Function-based ESD protection circuit design verification for BGA pad-ring array
A two-phase floorplanning approach for Application-specific Network-on-Chip
High performance optoelectronics based on CVD Mos2
A CMOS synchronous time amplifier
A Broadband Voltage Controlled Oscillator with Multi-Band Output
New Linearization Implementations Improving IIP3 of Wideband LNTA by More than 14dB
Aluminum Nitride reconfigurable RF-MEMS front-ends
A novel routing structure of coarse-grained reconfigurable architecture for radar application
A 130-150 GHz Power Amplifier for Millimeter Wave Imaging in 65-nm CMOS
Refractory epilepsy: Localization, detection, and prediction
A Review of PPG/NIRS Acquisition ASIC and System
A Digital Receive Beamforming IC for High-Frequency Ultrasound Imaging System
Developing a design system to help reduce design cycle time
A New Ga2O3 Trench Schottky Barrier Diode with Improved Forward Conduction Characteristics
Low noise low power two-stage modulator with injection locked LO divider in 65nm CMOS
Dependency of current collapse on the device structure of GaN-based HEMTs
A self-adaptive digital calibration technique for multi-channel high resolution capacitive SAR ADCs
Investigation on effectiveness of series gate resistor in CDM ESD protection designs
An Exponential Dynamic Weighted Fair Queuing Algorithm for Task Scheduling in Chip Verification Platform
Lithography hotspot detection and mitigation in nanometer VLSI
A 3600 × 3600 large-scale ISFET sensor array for high-throughput pH sensing
Design and testing of CMOS compatible EEPROM
A novel direct digital frequency synthesizer employing complementary dual-phase latch-based architecture
A low input power charge pump for passive UHF RFID applications
A GFSK transceiver for IEEE Std. 802.15.4g used in China
A CMOS low-noise amplifier for BCC applications
Research and Implementation of TPC Coding In High Bit Rate Telemetry System
A study of second saturation effect of OPTVLD NMOS
A 7W, 2.5-5GHz Wideband GaN PA with Transformer-Based Matching Network
A Transient-Enhanced Digital-LDO With Adaptive Clock-Edge Control