yusuke1997/dblp-id-title huggingface dataset:
A Battery Powered Hybrid Dual-Path Step-Up DC-DC Converter with Output Powered Bootstrap Driver
An adaptive multi-modulus frequency divider
Barrier and low k polish with a novel alkaline barrier slurry combining with FA/O chelating agent
A Three-Stage Comparator with High Speed and Low Power
A fast and accurate fault injection platform for SRAM-based FPGAs
Energy-aware Retinaface: A Power Efficient Edge-Computing SOC for Face Detector in 40nm
Fast locking Sampling PLL Using Phase Error Eliminator
An Automatically Selective Signal Combining Algorithm and System for Low SNR ECG Signals
Reflection analysis of signal transmission in 32-bit CPU based SiP
Intra-array Non-Idealities Modeling and Algorithm Optimization for RRAM-based Computing-in-Memory Applications
A 22-40.5 GHz UWB LNA Design in 0.15um GaAs
Energy efficient SVM classifier using approximate computing
RWCap2: Advanced floating random walk solver for the capacitance extraction of VLSI interconnects
A Dual-Mode Broadband Image Sensor Based on Graphene-CMOS Integration
A Non-Centralized Routing Scheme with Phase-Caching CDR for Nanosecond-Level Optical Switching Systems
Efficient floating random walk algorithm for interconnect capacitance extraction considering multiple dielectrics
Study on maximum electric field modeling used for HCI induced degradation characteristic of LDMOS transistors
Resistive Switching Characteristics of HfOx/Al2O3 Nano-multilayers Structure Memristor Fabricated by Atomic Layer Deposition
A 13-bit non-binary weighted SAR ADC with bridge structure using digital calibration for capacitor weight error
An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture
Design and Verification of a 334-Mb/s DCO-OFDM Li-Fi Transceiver Using Integrated System Evaluation Engine
A Three-valued Adder Circuit Implemented in ZnO Memristor with Multi-resistance States
A Programmable High-Voltage Pulse Transmitter Circuit for 3-D Miniature Ultrasound Probes
Pseudo Dual Path Processing to reduce the branch misprediction penalty in embedded processors
All-digital background calibration technique of the channel-time-mismatch in a two-channel TIADC
A simple semi-analytical parameter extraction method for 40nm gatelength MOSFET
Development trends of embedded NVM technology
Mobility overlap-removal based timing-constrained scheduling
Combining Max Pooling and ReLU Activation Function in Stochastic Computing
Best polarity searching for ternary FPRM logic circuit area based on whole annealing genetic algorithm
Design and implementation of a low Power Java Coprocessor for dual-interface IC Bank Card
Monolithic Logic Units based on DCFL Structure on p-GaN platform for GaN ICs
A 40Gb/s Low Power Transmitter with 2-tap FFE and 40: 1 MUX in 28nm CMOS Technology
An Energy-Efficient Image Denoising Accelerator with Depth-wise Separable Convolution and Fused-Layer Architecture
A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters
A high-performance charge pump with improved static and dynamic matching characteristic
A Speed Up Method towards DDR Subsystem Functional Verification in SoC
High-speed FPGA implementation of orthogonal matching pursuit for analog to information converter
System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration
100MS/s 9-bit 0.43mW SAR ADC with custom capacitor array
An inclusive fault model for Network-on-Chip
High performance transistors based on two dimensional materials
Defect-Tolerant and Energy-Efficient Training of Multi-Valued and Binary Memristor Crossbars for Near-Sensor Cognitive Computing
Comprehensive electro-thermal(ET) analysis with considering ET coupling
A novel channel estimation algorithm in OFDM power line communication system
A 10-bit 40 MS/s successive approximation register analog-to-digital converter with Vcm-based method for wireless communications
Effective Register Allocation for Configurable VLIW Crypto-Processor
A 6b 2b/cycle SAR ADC beyond 1GS/s with hybrid DAC structure and low kickback noise comparators
A 57 to 66 GHz novel six-port correlator
The configurable current flattening circuit for DPA countermeasures
Ultralow-power analog front-end IC design for an implantable cardioverter defibrillator (ICD)
A novel ESD device for Whole-Chip ESD protection network of TPMS mixed signal SoC
Genetic Architecture Search for Binarized Neural Networks
Electro-thermal model extraction of power GaN HEMT using I-V pulsed and DC measurements
Circuit Design Challenges in Computing-in-Memory for AI Edge Devices
An ECG Acquisition System with Piezoelectric Energy Harvesting for Low Power Healthcare Devices
Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design
A highly linear wideband variable gain CMOS balun-LNA
An Efficient ASIC Implementation of Public Key Cryptography Algorithm SM2 Based on Module Arithmetic Logic Unit
Knowledge Distillation for U-Net Based Image Denoising
Double charge pump circuit with triple charge sharing clock scheme
A High Linearity Large Time Constants Switched-Resistor Filter for Biomedical Applications
A chain-multiplier for large scale matrix multiplication
Large-signal MOSFET modeling by means of knowledge based fuzzy logic system
DC MUX PUF: A highly reliable feed-back MUX PUF based on measuring duty cycle
An Optimized Modeling Method for Transformer Design
FPGA bitstream compression and decompression based on LZ77 algorithm and BMC technique
An ECC crypto engine based on binary edwards elliptic curve for low-cost RFID tag chip
Permutation-Based Approximate Multiplier with High Accuracy
Analysis and Evaluation Method of RC Polyphase Filter
High voltage charge pump circuit using vertical parallel plate capacitors
An automatic software/hardware verification platform prototype for reconfigurable audio algorithm in media SoC
A 5-bit High-Linearity, Binary-Recombination-Redundancy Sub-SAR ADC in 300MS/s, 14-bit Pipelined-SAR ADC
DCPG: Double-control power gating technique for a 28 nm Cortex™-A9 MPCore Quad-core processor
Low-Power Keyword Recognition Feature Extraction Circuit based on SRMFCC and Shared Multiplier for High Noise Background
Concurrent Multiband CMOS Low Noise Amplifier Design for Internet of Things Applications
A broadband power detector with temperature and process compensation
A Phased-array Optoelectronic Detector using Phase-difference Filtering Technology for Incremental Encoder Application
Design and implementation of light load energy saving current-limiting circuit
A Vernier Time-to-Digital Converter with 1.5ps Resolution for an All-Digital Phase Locked Loop in 28nm CMOS
AVCO with F-V linearization techniques for CNS application
A 24 GHz reconfigurable frequency synthesizer for 60 GHz WPAN
Lithographic Hotspot Detection Using Adaptive Squish Pattern Sampling Combined with Faster R-CNN
Soft error tolerant latch designs with low power consumption (invited paper)
A semi-auto interactive 2D-to-3D video conversion technique based on edge detection
Lagrangian relaxation based topology synthesis for Application-Specific Network-on-Chips
Investigation of line tunnel field effect transistor with Ge/Si heterojunction
A novel test scheme for NAND flash memory based on built-in oscillator ring
VLSI implementation of high-speed low power decimation filter for LTE sigma-delta A/D converter application
RF mixer design techniques using GaAs process
A 60 GHz single-to-differential LNA using slow-wave CPW and transformer coupling in 28 nm CMOS
Status and trends in Nanoelectronic devices for the ultimate integration of ICs
Balance of memory footprint and runtime for high-density routing in large-scale FPGAs
A 1.2-V 250-MS/s 8-bit pipelined ADC in 0.13-µm CMOS
A high-sensitivity ASK demodulator for passive UHF RFID tags with automatic voltage limitation and average voltage detection
Wideband power amplifier predistortion: Trends, challenges and solutions
An Enhanced DSP Block Architecture for FPGA Supporting Multi-operands Addition Operation
A deep research on the chip verification platform based on network
Highly stable data SRAM-PUF in 65nm CMOS process
Analysis of SAR ADC Quantization Error and Nonlinearity in PMCW Automotive Radar
Selective Atomic Layer Deposition to Extend Moore's Law and Beyond: Surface Kinetic Tuning for Self-Aligned Growth
Advanced Simulation of RRAM Memory Cells
A novel current-mode versatile filter employing CCCDCC and MO-OTA
A 400M-510MHz On-Chip Transformer-Based RF Power Amplifier with 22.5dBm Output Power and 48% PAE
Design of router for spiking neural networks
Enhancing Temperature Immunity of Digital Circuit Against Aging : The Standard Cell Subset Method
IZIP: In-place zero overhead interconnect protection via PIP redundancy
Method for improving energy efficiency of elliptic curve cryptography algorithm on reconfigurable symmetric cipher processor
A PSR Enhancement Scheme: An Overview of Feed-Forward Ripple Cancellation Technique
OpenILT: An Open Source Inverse Lithography Technique Framework (Invited Paper)
Multibit Sturdy MASH ΔΣ Modulator with Error-shaped Segmented DACs for Wideband Low-power Applications
A CMOS passive mixer-first receiver front-end for UHF RFID Reader
2011 IEEE 9th International Conference on ASIC, ASICON 2011, Xiamen, China, October 25-28, 2011
Comparison of 2D MESH routing algorithm in NOC
An Area-Efficient Multi-Rate Digital Decimator
New power rail ESD clamp design with current starving technology
Loop-Tiling Based Compiling Optimization for CNN Accelerators
Scheduling to timing optimization for a novel high-level synthesis approach
A Network-on-Chip simulation framework for homogeneous Multi-Processor System-on-Chip
Recess-Patterned Ohmic Contact Technology for AlGaN/GaN Heterostructures
EMI Noise Reduction and Output Ripple Cancellation for Full-Wave Type Soft-Switching Converter
A high-efficiency class e power amplifier with integrated finite DC feed inductance
A fully asynchronous QDI mesh router based on 28nm standard cells
Research on the impact of different benchmark circuits on the representative path in FPGAs
Semi-superjunction IGBT with floating p-pillar and p-ring for low losses and high breakdown voltage
Flash-based Computing in-Memory Scheme for IOT
Optimization of ADM with both restrictions of resolution and power dissipation in low supply voltage
Ultrathin flexible coils for wireless power and data link in biomedical sensors
A Novel Etch Scheme to Form Sloped Profile by Standard Anisotropic CMOS Process
A simulation study of vertical tunnel field effect transistors
A design of a wideband balanced limited low noise amplifier
A non-rectifier wireless power transmission system using on-chip inductor
An asynchronous delay line TDC for ADPLL in 0.13um CMOS
Effects of using Multi Voltage Threshold Transistors in Asynchronous Circuits
Ultrafast spintronic integrated circuits
A high-performance current sensing circuit with full-phase sampling capability
Simulation and analysis of P+/N SPAD for 3D imaging
An efficient HMAC processor based on the SHA-3 HASH function
Complementary Field-Effect Transistors: From Silicon to 2D Materials
Roles of the gate length and width of the transistors in increasing the single event upset resistance of SRAM cells
A Novel Semi-superjunction SiC Trench MOSFET with Ultra-low Specific On-resistance
DPALS: A dynamic programming-based algorithm for two-level approximate logic synthesis
Design of a hybrid reconfigurable coprocessor
A software/hardware co-debug platform for multi-core systems
Single event upset immune latch circuit design using C-element
A Variation Aware Register Clustering Methodology in Near-Threshold Region
A BIST scheme for high-speed Gain Cell eDRAM
An Active Pixel Sensor Array based on Compact Photoelectron In-situ Sensing Device (PISD)
Vertical power diodes based on bulk GaN substrates
Low-power high-speed communication with short-millimeter-wave CMOS transceivers
Remote embedded simulation system for SW/HW co-design based on dynamic partial reconfiguration
A Low-Power Comparator-Less Relaxation Oscillator
Analysis and design of energy-efficient data-dependent SRAM
Current Research Status and Future Prospect of the In-Memory Computing
A high performance parallel VLSI design of matrix inversion
A 20MHz CTIA ROIC for InGaAs focal plane array
Design of a novel high-accuracy LED driving chip
A Radiation Hardened Clock Inverter Cell with High Reliability for Mitigating SET in Clock Network
A novel clock synchronizer for low-voltage clock distribution network
A fully-pipelined hash table achieving low-latency and high throughput key-value retrieving system
A high performance VLSI architecture for integer motion estimation in HEVC
A proposed data converter for current signal with temperature-compensated sample resistor
Investigation of self-heating effect in SOI tunnel field-effect transistor
Ultrahigh-Speed One-Chip CMOS Transceiver with 300-GHz Band
Designing a 3D Graphics Processor for Mobile Applications
Low power mapping optimization of loops for dual-Vdd CGRAs
Self-recovering short-circuit protection circuit for RF class-D power amplifier
A 10-Bit, 50 MS/s, 55 fJ/conversion-step SAR ADC with split capacitor array
An NFC system with high sensitivity based on SDR
Toward real-time 3D modeling system with cubic-millimeters wireless sensor nodes
Finding All Solutions of Multi-terminal Numberlink Problem Utilizing Top-down ZDD Construction
OMI/TMI-based Modeling and Fast Simulation of Random Telegraph Noise (RTN) in Advanced Logic Devices and Circuits
Research on Area Modeling Methodology for FPGA Interconnect Circuits
A low voltage SRAM sense amplifier with offset cancelling using digitized multiple body biasing
RFIDsense: A reconfigurable RFID sensor tag platform conforming to IEEE 1451.7 standard
Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network
Design and Implementation of Full Adder in One-Transistor-One-Resistor RRAM Array
Design of an Adaptive Loop Gain Controller Based on Auto-correlation Detection Scheme in All-Digital Phase-Locked Loop
An iTFET with Control Gate for Low Power Applications in RF and Digital Circuits
A method of quadratic programming for mapping on NoC architecture
A Novel SiC Superjunction Trench MOSFET with Integrated Heterojunction Diode for Improved Performance
Mixed-signal verification methods for multi-power mixed-signal System-on-Chip (SoC) design
A Hardware Architecture for Adaptive Loop Filter in VVC Decoder
An Improved InP HEMT Small Signal Model with RC Network
Current Balancing Strategy based on Threshold Midpoint Adjustment for Interleaved Constant Frequency Hysteresis Control Buck Converter
A Compact Memory Structure based on 2T1R Against Single-Event Upset in RRAM Arrays
13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019
Buffer Sizing for Near-Threshold Clock Tree using Improved Genetic Algorithm
A SPAD Relative Address Coding for Lateral Resolution Improvement in Coincidence Detection
Interface engineering of Si1-xGex gate stacks for high performance dual channel CMOS
Performance improvement of InGaAs FinFET using NH3 treatment
Fast transistor-level circuit simulation and variational analysis via the ultra-compact virtual source model
A Fine-grained Sparse Neural Network Accelerator for Image Classification
Ultra-Low-Power Intelligent Acoustic Sensing using Cochlea-Inspired Feature Extraction and DNN Classification
High Frame Rate High Precision ROIC with Pixel-level CCO-Based ADC for Infrared FPAs
An adjustable amplitude and pulse-width laser modulation driver with active feedback for QKD experiments
Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level ESD protection
LMS-FIR based digital background calibration for the four-channel time-interleaved ADC
High-order curvature-compensated CMOS bandgap voltage reference
Automatic Correction of Current Imbalance for Multi-Phase COT Ripple-Based Control DC-DC Converter
A 32GS/s 7bit TI-SAR ADC in 28nm for 32Gb/s ADC-Based SerDes Receiver
A Viterbi decoder for UHF RFID digital baseband
Design Considerations on Integrated Rectifiers with High Efficiency and Wide Input Power Range for RF Energy Harvesting
A high linearity MOS capacitor for low voltage applications
An inductive wireless telemetry circuit with OOK modulation for implantable cardiac pacemakers
A novel method for storage architecture of pipeline FFT processor
A TIA-based interface for MEMS capacitive gyroscope
A 0.1-1.5G SDR transmitter with two-stage harmonic rejection power mixer in 65-nm CMOS
Charge and Spin Transport in Semiconductor Devices
A high utilization FPGA-based accelerator for variable-scale convolutional neural network
Ultra low power and high performance nanoelectronic devices
A 35µW Receiver Front-End with 35% wireless energy harvesting efficiency for Wearable Medical Applications
On-Chip Filter for Mitigating EMI-Related Common-Mode Noise in High-Speed PAM-4 Transmitter
A Low On-state Voltage and Large Current Capability Thin SOI-LIGBT with Trench NMOS
A Method to Design 5-Bit Burst Error Correction Code against the Multiple Bit Upset (MBU) in Memories
Classical Mathematics and Analog/Mixed-Signal IC Design
Analog routing considering min-area constraint
A SIMD multiplier-accumulator design for pairing cryptography
An ASIC for Discriminating Single Photon Detector Signal of High-Speed Quantum Key Distribution System
An area-efficient interconnection network for coarse-grain reconfigurable cryptographic array
A 68.36 dB 12 bit 100MS/s SAR ADC with a low-noise comparator in 14-nm CMOS FinFet
Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays
Reverse-Bias Stability and Reliability of Enhancement-mode GaN-based MIS-FET
A flexible HEVC intra mode decision hardware for 8kx4k real time encoder
Post-Si Nano Device Technology
A 0.8-2.5GHz wideband SiGe BiCMOS low noise amplifier with noise fiugre of 1.98-3.3dB
Divide and Conquer: Floating-Point Exponential Calculation Based on Taylor-Series Expansion
An Efficient Hash Computing Unit for Kyber Algorithm
FPGA interconnect timing library based on the statistical method
Temperature Dependent Optimization for Specific On-Resistance for 900 V Superjunction MOSFETs: Numerical Calculation and Comparison
A low power high integrated BLE transceiver
A new short-channel-effect-degraded subthreshold behavior model for elliptical gate-all-around MOSFET
Circuit simulation using matrix exponential method
A High Efficiency Re-configurable Step-down Switched Capacitor DC-DC Converter for Medical Implants Application
Effects of Charge Generation and Trapping on the X-ray Response of Strained AlGaN/GaN HEMTs
Improved unified interconnect unit for high speed and scalable FPGA
An area-efficient dual-channel RF receiver for GPS-L1/Galileo-E1/Compass-B1
Functional coverage-driven UVM-based UART IP verification
Stability Analysis of Monolithic GaN MIS-HEMT Comparator with Device PBTI and Circuit Stress Tests
Impact of Hydrogen Anneal on Peripheral PMOS NBTI and Array Transistor GIDL in DRAM
A 3.5-A buck DC-DC regulator with wire drop compensation for remote-loading applications
Improvement of adiabatic domino circuits and its application in multi-valued circuits
Low complexity and low power multiplierless FIR filter implementation
Current status and future prospect of Phase Change Memory
Analytical model of the coupling capacitance between cylindrical through silicon via and horizontal interconnect in 3D IC
Analysis and Optimal Design of a New Single-Photon Memristor
A 10bit 1.6GS/s Current-steering DAC in 40nm CMOS
A DLL based low-phase-noise clock multiplier with offset-tolerant PFD
Area-Efficient Parallel Stochastic Computing with Shared Weighted Binary Generator
A current mode sense amplifier with self-compensation circuit for SRAM application
Integration of information security chips based on System-in-Package
A Novel Trench MOSFET with p-Pillar and RSO Accumulation Layer for Improved Performance
Hardware security applications of emerging nonvolatile memories
Polarity dependent of gate oxide breakdown from measurements
A Decision-Based CORDIC Hardware for Arc Tangent Calculation
The D-band MMIC LNA circuit using 70nm InP HEMT technology
A 12bit asynchronous SAR-incremental sub-range ADC
Improved Model for ESD Failure Caused by Stressing No Connect Pin
Background calibration techniques for multistage pipelined ADCs with dynamic element matching and pseudorandom noise
Design of a single-ended cell based 65nm 32×32b 4R2W register file
Modified Minimal-Connected-Component fault block model to deal with defective links and nodes for 2D-mesh NoCs
A Fourth Order Chebyshev Complex Band-pass Filter Design with Filter Solution
Survey and statistical analysis of THz detectors
Word line boost and read SA PMOS compensation (SAPC) for ROM in 55nm CMOS
Smartphone-controlled electro-wetting on dielectric microfluidics
A behavior-based reconfigurable cache for the low-power embedded processor
An 8-12GHz Class-F3 VCO with Multi-LC Tank in 28nm CMOS
Hot carrier reliability in LDMOS devices
A new scheme for testability improvement of ECC incorporated memory
Key component designs of subthreshold baseband processors in passive RF device
Image synthesis circuit design using selector-logic-based alpha blending and its FPGA implementation
A high-resolution TDC implemented in a 90nm process FPGA
An output-capacitor-less low-dropout regulator with transient-improved technique
A timing failure tolerance design with in-field simultaneous error detection and correction
A Sinusoidal Fitting-based Digital Foreground Calibration Technique for Pipelined ADC
A Digital to Time Converter Assisted TA-TDC with High Resolution for Low Power ADPLL in 22nm CMOS
A nanopower, high PSRR full CMOS voltage reference circuit consisting of subthreshold MOSFETs
A 2D mesh NoC with self-configurable and shared-FIFOs routers
The Impact of Strain and Layout Dependent Effects on High Frequency Performance and Low Frequency Noise in Nanoscale Devices
Investigation on the immunity of microcontroller to electrical fast transients
A Streaming Feature Extraction Accelerator using DPCM Image Compression Technique for SLAM Applications
A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifier
A calibration technique for SAR ADC based on code density test
A Low-complexity Max Unpooling Achitecture for CNNs
A low-power daisy-chain controller implemention in BMS based on power mode switching
Design and implementation of a dynamic loop buffer by reusing the instruction buffer
Robustness and performance analysis on high speed ASIC design with canonical statistical timing model
An 800MS/s, 6.7b ENOB Bootstrap Switching S/H IC for Wideband Direct RF Sub-Sampling Receiver in 45 nm CMOS
A Compilation Toolchain of Neural Networks for FPGA Backend
Efficient fast convolution architectures for convolutional neural network
A novel layout automation flow to facilitate test chip design for standard cell characterization
A Novel TFET-MOSFET Hybrid SRAM for Ultra-Low-Power Applications
UVM-based Functional Coverage Driven AXI4-Stream Verification
A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded application
Enabling Monolithic Heterogeneously Integrated Si/III-V Technology Platform
A Low-Power High-Throughput In-Memory CMOS-ReRAM Accelerator for Large-Scale Deep Residual Neural Networks
Novel smart card SoC memory architecture based on embedded STT-MRAM
A high performance and low cost video processing SoC for digital HDTV systems
The enhancement mode AlGaN/GaN high electron mobility transistor based on charge storage
Performance Investigation of Uniaxially Tensile Stressed Ge n-FinFETs Formed on Biaxially Strained GeOI Substrates And Its Impact On Ge CMOS Inverters
Application of LDPC codes on PUF error correction based on code-offset construction
Research on design of a reconfigurable parallel structure targeted at LFSR
Implementation of a CRNN-based low-power keyword recognition system on FPGA
A hardware accelerator for speech recognition applications
A synchronous charge extraction piezoelectric energy harvesting circuit based on precision active control peak detection with supplement energy
An input buffer for 12bit 2GS/s ADC