yusuke1997/dblp-id-title huggingface dataset:
A New Method for Route Based Synthesis and Placement in Digital Microfluidic Biochips
Reconfigurable Hardware Design for Polynomial Galois Field Arithmetic Operations
Continuous Flow Microfluidic Channel Design for Blood Plasma Separation
Four Differential Channels, Programmable Gain, Programmable Data Rate Delta Sigma ADC
High Sensitivity and Power Efficient Heater Structure for Bulk Micromachined Thermal Accelerometer
Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power
Innovative Circuit Level Methodology for FinFET based Low-Power 6T SRAM Cell Design
A 1.25-20 GHz Wide Tuning Range Frequency Synthesis for 40-Gb/s SerDes Application
A Novel Design of SRAM Using Memristors at 45 nm Technology
Simulation based methodology for fault analysis of PCB designs
Variation Robust Subthreshold SRAM Design with Ultra Low Power Consumption
Tunnel FET based low voltage static vs dynamic logic families for energy efficiency
Optimizing Concurrent Co-Designing of ICs and Package using Multi Technology and RF Solution
Design of FPGA based Custom IP Core to Detect the Edges of Brain Tumors
Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG)
A Novel 20nm FinFET Based 10T SRAM Cell Design for Improved Performance
Reliability Aware Global Routing of Graphene Nanoribbon Based Interconnect
Modeling and Analysis of Transient Heat for 3D IC
Performance Modelling and Dynamic Scheduling on Heterogeneous-ISA Multi-core Architectures
Frequency domain analysis of on-chip power distribution network
Implications of Field Plate HEMT Towards Power Performance at Microwave X - Band
Circuit Transient Analysis Using State Space Equations
An LUT based RNS FIR filter implementation for reconfigurable applications
Design and Implementation of Mixed Parallel and Dataflow Architecture for Intra-prediction Hardware in HEVC Decoder
Implementation and Analysis of Convolution Image Filtering with RISC-V Based Architecture
An Efficient Timing and Clock Tree Aware Placement Flow with Multibit Flip-Flops for Power Reduction
Hausdorff Distance Driven L-Shape Matching Based Layout Decomposition for E-Beam Lithography
Power optimized PLL implementation in 180nm CMOS technology
Design of a Threshold Voltage Insensitive 3T1C Pixel Circuit Using a-IGZO TFT for AMOLED Displays
Characterization and Compensation Circuitry for Piezo-Resistive Pressure Sensor to Accommodate Temperature Induced Variation
Architectures and algorithms for image and video processing using FPGA-based platform
Design and Analysis of 8T Radiation Hardened SRAM using 65nm Process
On-chip CMOS temperature sensor with current calibrated accuracy of -1.1°C to +1.4°C (3σ) from -20°C to 150°C
Side channel attack resistant architecture for elliptic curve cryptography
GA based diagnostic test pattern generation for transition faults
Performance Comparison of Single Level STT and SOT MRAM Cells for Cache Applications
Design of area efficient and low power bandgap voltage reference using sub-threshold MOS transistors
Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound
On determination of instantaneous peak and cycle peak switching using ILP
A constructive heuristic for application mapping onto an express channel based Network-on-Chip
Design of fault tolerant majority voter for TMR circuit in QCA
QCA Technology Based 8-Bit TRNG Design for Cryptography Applications
Design and Implementation of Efficient Vedic Multiplier Using Reversible Logic
Opto-Radio Noise based True Random Number Generator
A Latency and Throughput Efficient Successive Cancellation Decoding of Polar Codes
SEU Tolerant Robust Latch Design
Layout-aware signal selection in reconfigurable architectures
An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array
Energy-Efficient Hardware Design for CNN-Based ECG Signal Classification in Wearable Bio-Medical Devices
Design and Implementation of chaotic nondeterministic random seed-based Hybrid True Random Number Generator
Impact of Compliance Current on the Switching Behavior in SiOx based Resistive Switching Devices
Advanced UPF based voltage-aware verification for IOs
Layout Design of X-Band Low Noise Amplifier for Radar Applications
Extending the scope of translation validation by augmenting path based equivalence checkers with SMT solvers
A Shift-left Approach in Qualification of Digital IPs for SoCs by Applying Advanced Automation and Data Analytics
Analysis of Crosstalk Deviation for Bundled MWCNT with Process Induced Height and Width Variations
Operation-aware assist circuit design for improved write performance of FinFET based SRAM
Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding
SARP: Self Aware Runtime Protection Against Integrity Attacks of Hardware Trojans
A spare link based reliable Network-on-Chip design
3D LBDR: Logic-Based Distributed Routing for 3D NoC
Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing
Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on Chip
A Novel Design Approach to Implement Multi-port Register Files Using Pulsed-Latches
FPGA implementation of high speed reconfigurable filter bank for multi-standard wireless communication receivers
Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip
Performance Analysis of Graphene Based Optical Interconnect at Nanoscale Technology
Design of coherence verification unit for heterogeneous CMPs
Design of a Power Efficient Pulse Latch Circuit as a Solution for Master Slave Flip-Flop
Fabrication and characterization of Al gate n-MOSFET, on-chip fabricated with Si3N4 ISFET
Fault masking in Quantum-dot cellular automata using prohibitive logic circuit
An Angular Steiner Tree Based Global Routing Algorithm for Graphene Nanoribbon Circuit
Design and Simulation of Bulk Micromachined Accelerometer for Avionics Application
CMOS ASIC Design of a High Performance Digital Fuzzy Processor That Can Compute on Arbitrary Membership Functions
Smart handheld platform for electrochemical bio sensors
Design and Analysis of Secure One-way Functions for the Protection of Symmetric Key Cryptosystems
A 10T Subthreshold SRAM Cell with Minimal Bitline Switching for Ultra-Low Power Applications
A Decimal Multiplier With Improved Speed Using Semi-Parallel Iterative Approach
Energy Efficient 9T SRAM With R/W Margin Enhanced for beyond Von-Neumann Computation
Analytical Partitioning: Improvement over FM
Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs
Impact of Temperature on NDR Characteristics of a Negative Capacitance FinFET: Role of Landau Parameter (α)
Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff
Novel RF MEMS Capacitive Switch for Lower Actuation Voltage
Comparison of OpAmp Based and Comparator Based Switched Capacitor Filter
Pseudo-BIST: A Novel Technique for SAR-ADC Testing
10 Gbps Current Mode Logic I/O Buffer
Delay Uncertainty in Single- and Multi-Wall Carbon Nanotube Interconnects
Radiation Hardened by Design Sense Amplifier
An All-CMOS Supply, Temperature and Process Invariant Hybrid Current Reference For Power Efficient IoT Applications
Design & Benchmark of Single Bit & Multi Bit Sequential Elements in 65nm for Low Standby Power Consumption
A PAM-4 Based Full Duplex IO with In-built Feed-Forward Equalizer and Performance Enhanced Receiver
Automatic Test Bench Generation and Connection in Modern Verification Environments: Methodology and Tool
An efficient approach for estimating the impact of SSO noise on LPDDR2 timing budget
Synthesis aware sample preparation techniques using random sample sets in DMFB
Design and Fabrication of Versatile Low Power Wireless Sensor Nodes for IoT Applications
Energy Harvester Powered On-chip Reconfigurable Switched Capacitor Converter in 0.18 μm CMOS
Dual-Edge Triggered Lightweight Implementation of AES for IoT Security
Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network
An embedded framework for accurate object localization using center of gravity measure with mean shift procedure
Defect Diagnosis of Digital Circuits Using Surrogate Faults
A 10 MHz, 73 ppm/°C, 84 µW PVT Compensated Ring Oscillator
CPK Based IO AC Timing Closure to Reduce Yield Loss and Test Time
A Combined CMOS Reference Circuit with Supply and Temperature Compensation
T-Gate: Concept of partial polarization in Quantum Dot Cellular Automata
Enhancing Retention Voltage for SRAM
Design and analysis of a touch mode MEMS capacitive pressure sensor for IUPC
Formal verification of switched capacitor DC to DC power converter using circuit simulation traces
An Adaptive Multi-Objective Optimization on CMOS Two Stage Op-Amp Circuit Synthesis
Improved supply regulation and temperature compensated current reference circuit with low process variations
Effective Method for Temperature Compensation in Dual Band Metal MEMS Resonator
Design of a new high order OTA-C filter structure and its specification based testing
VLSI implementation of novel fast confluence ICA algorithm for signal processing applications
Efficient and Failure Aware ECC for STT-MRAM Cache Memory
Computational Functions' VLSI Implementation for Compressed Sensing
Analysis of CMOS inhibitory synapse with varying neurotransmitter concentration, reuptake time and spread delay
Acetone Sensing Performance of Pristine and Gold Doped Graphene Sheet: A Comparative Analysis
Low-Voltage Dual-Gate Organic Thin Film Transistors with Distinctly Placed Source and Drain
A novel dual multiplier floating point multiply accumulate architecture
Heuristic Driven Genetic Algorithm for Priority Assignment of Real-Time Communications in NoC
Real Time Mixing Index Measurement of Microchannels Using OpenCV
Case study: Re-visiting SoC verification challenges and best practices
Comparison of SRAM Cell Layout Topologies to Estimate Improvement in SER Robustness in 28FDSOI and 40 nm Technologies
2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, July 23-25, 2020
Design of Combinational and Sequential Circuits Using Novel Feedthrough Logic
Detecting Hardware Trojans by Reducing Rarity of Transitions in ICs
Novel Method for Verification and Performance Evaluation of a Non-Blocking Level-1 Instruction Cache designed for Out-of-Order RISC-V Superscaler Processor on FPGA
A Pseudo-Deadline Based O(1) proportional share scheduler for embedded systems
A novel ROPUF for hardware security
20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016
Signal Integrity and Power Loss Analysis for Different Bump Structures in Cylindrical TSV
Dual Stage Encoding Technique to Minimize Cross Coupling across NoC Links
KARNA for a Trustable Hardware
Capacitive Nonlinearity of GFET Compact Model in Quasi-Ballistic Regime for High-Frequency Applications
Introduction to MEMS; their applications as sensors for chemical & bio sensing
Design Optimization of a Wide Band MEMS Resonator for Efficient Energy Harvesting
Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET
A Cost Effective Technique for Diagnosis of Scan Chain Faults
A Generalized Technique of Automated Pin Sharing on Hexagonal Electrode Based Digital Microfluidic Biochip Along with Its Design Methodology
New technique to improve transient response of LDO regulators without an off-chip capacitor
Comparative Analysis of Logic Gates Based on Spin Transfer Torque (STT) and Differential Spin Hall Effect (DSHE) Switching Mechanisms
Performance analysis of temperature dependent GNR interconnect
A Proactive Wash droplet routing for Digital Microfluidics Biochip
VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers
Particle swarm optimization approach for low temperature BIST
Design and Analysis of Cross-Coupled Source Degenerated Balanced OTA for Biomedical Application
Squarer design with reduced area and delay
Generic methodolgy and solution for Additive Jitter correction in Mesh based clock architectures
A FSM based approach for efficient implementation of K-means algorithm
Novel Approach for Improved Signal Integrity and Power Dissipation Using MLGNR Interconnects
Characterization of Logical Effort for Improved Delay
SOI MEMS Based Over-Sampling Accelerometer Design with ΔΣ Output
Suppression of Ambipolar current in Tunnel Field-Effect Transistor using Field-Plate
Design of Transceiver at 865-867 MHz Band using UMC 180 nm CMOS Technology
Investigation of TCADs Models for Characterization of Sub 16 nm In _0.53 Ga _0.47 As FinFET
Performance Optimization of FinFET Configurations at 14 nm Technology Using ANN-PSO
Modeling and yield estimation of SRAM sub-system for different capacities subjected to parametric variations
An 8-bit 500 MSPS segmented current steering DAC using Chinese abacus technique
A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF Applications
Behavior of LDMOS transistors at cryogenic temperature - An experiment based analysis
A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGA
Automation of Timing Quality Checks and Optimization
A Novel Countermeasure Against Differential Scan Attack in AES Algorithm
Modelling the Spiking Behaviour of Ganglion Cells
Design and Implementation of Optimized Register File for Streaming Applications
Multicore processor - Architecture and programming
SNN with Gradient-based Backpropagation algorithm for ECG arrhythmia classification with LIF neuron and AdEx neuron
Custom-IP for Gradient Descent Optimization based on Hardware/Software Co-design Paradigm
Cryptanalysis of Composite PUFs (Extended abstract-invited talk)
A methodology to reuse random IP stimuli in an SoC functional verification environment
A 2.4 GHz High Efficiency Capacitive Cross Coupled Common Gate Class-E Differential Power Amplifier
Threshold Implementation of a Low-Cost CLEFIA-128 Cipher for Power Analysis Attack Resistance
Design and development of cantilever-type MEMS based piezoelectric energy harvester
A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-T ox in CMOS VLSI Circuits
Comparative Study Of GAA-JL Transistor With And Without FE Material For Hydrogen Gas Sensing
Voltage Level Adapter Design for High Voltage Swing Applications in CMOS Differential Amplifier
Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology
Signal Integrity Assessment of Stretchable Interconnects for Flexible Electronics System
Development of Distributed Controller for Electronic Beam Steering Using Indigenous Rad-Hard ASIC
Modeling of Thermal Properties of Semiconducting Monolayer MoSe2 and WSe2
An Efficient Test Design for CMPs Cache Coherence Realizing MESI Protocol
Designing efficient combinational compression architecture for testing industrial circuits
Efficient Hardware-Software Codesigns of AES Encryptor and RS-BCH Encoder
RTQCC-14T: Radiation Tolerant Quadruple Cross Coupled Robust SRAM Design for Radiation Prone Environments
A Novel March C2RR Algorithm for Nanoelectronic Resistive Random Access Memory (RRAM) Testing
A 0.9V 64Mb 6T SRAM cell with Read and Write assist schemes in 65nm LSTP technology
PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits
VLSI design of fast fractal image encoder
Impact of SRH Lifetime on the Performance of Aluminium Gallium Nitride Based Ultraviolet -C Light Emitting Diodes
A high CMRR, high resolution bio-ASIC for ECG signals
Low-Power Switched Operational Amplifier Using a-InGaZnO TFTs
A Highly Stable and Robust 7T SRAM Cell using Memristor
Cognitive-radio wireless-sensor based on energy detection with improved accuracy: Performance and hardware perspectives
RISC-V out-of-order data conversion co-processor
Multi-mode Toggle Random Access Scan to Minimize Test Application Time
A Methodology to Design Online Testable Reversible Circuits
Design and Implementation of an FPGA-based Emulator Circuit for MLP using Memristors
A low-cost energy efficient image scaling processor for multimedia applications
An analytical delay model for CMOS Inverter-Transmission Gate structure
New Energy Efficient Reconfigurable FIR Filter Architecture and Its VLSI Implementation
Test Data Compression for NoC Based SoCs Using Binary Arithmetic Operations
Design of High Speed Vedic Multiplier for Decimal Number System
Electro-Thermal Analysis of Vertically Stacked Gate All Around Nano-sheet Transistor
BONY: An algorithm to generate large synthetic combinational benchmark circuits
Process Development for Very Deep Etching of Silicon Using Two Layer Masks for Fabrication of Mechanically Decoupled MEMS Gyroscope
FPGA Implementation of Energy Efficient Approximate Hybrid Parallel Prefix Adders for Image Processing Applications
Implementation of input data buffering and scheduling methodology for 8 parallel MDC FFT
VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers
Modeling of High Frequency Out-of-Plane Single Axis MEMS Capacitive Accelerometer
An Online Testing Technique for the Detection of Control Nodes Displacement Faults (CNDF) in Reversible Circuits
18th International Symposium on VLSI Design and Test, VDAT 2014, Coimbatore, India, July 16-18, 2014
A novel adiabatic SRAM cell implementation using split level charge recovery logic
A Heuristic Qubit Placement Strategy for Nearest Neighbor Realization in 2D Architecture
Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell
Analyzing Design Parameters of Nano-Magnetic Technology Based Converter Circuit
Behaviour of FinFET Inverter's Effective Capacitances in Low-Voltage Domain
An all digital delay lock loop architecture for high precision timing generator
Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices
Parallel two step random walk algorithm to analyze VLSI power grid networks
Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods
Variability Investigation of Double Gate JunctionLess (DG-JL) Transistor for Circuit Design Perspective
ASIC Based LVDT Signal Conditioner for High-Accuracy Measurements
A 10-bit 500 MSPS Segmented CS-DAC of > 77 dB SFDR upto the Nyquist with Hexa-decal biasing
CORDIC Based Implementation of the Softmax Activation Function
Signature analysis for synthesis of reversible circuit
Super-scale architecture enhancement of LEON3 core for DSP application
A Low-Power 10-bit SAR ADC with an Integrated CDAC and C-MOSCAP DAC for Implantable Pacemakers
A CMOS Low Noise Amplifier with Improved Gain
FEM Based Device Simulator for High Voltage Devices
Design, Simulation and Optimization of Aluminum Nitride Based Accelerometer
Area-Time Scalable High Radix Montgomery Modular Multiplier for Large Modulus
High Level Synthesis and Implementation of Cryptographic Algorithm in AHIR Platform
Analysis of stability and different speed boosting assist techniques towards the design and optimization of high speed SRAM cell
Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs
Power Problems in VLSI Circuit Testing
Performance Optimized 64b/66b Line Encoding Technique for High Speed SERDES Devices
A positive level shifter for high speed symmetric switching in flash memories
Distributed adaptive routing for spidergon NoC
Impact of Operand Ordering in Approximate Multiplication in Neural Network and Image Processing Applications
FPGA based Compressive Sensing Framework for Video Compression on Edge Devices
Utilizing NBTI for Operation Detection of Integrated Circuits
A locally reconfigurable Network-on-Chip architecture and application mapping onto it
On Disabling Prefetcher to Amplify Cache Side Channels
A framework for thermal aware reliability estimation in 2D NoC
FPGA-based real-time object tracker using modified particle filtering and SAD computation
An FPGA implementation of image signature based visual-saliency detection
A secure architecture for the design for testability structures
Defect characterization and testing of QCA devices and circuits: A survey
Clock Pulse Based Foreground Calibration of a Sub-Radix-2 Successive Approximation Register ADC
RTNA: Securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks
Automated Design and Configuration of RISC-V based NoC-MPSoC Framework on FPGA
Partitioning-based test time reduction for core-based 3DICs
Design of Push-Pull Dynamic Leaker Circuit for a Low Power Embedded Voltage Regulator
Fabrication, Optimization and Testing of Photoconductively Tuned SAW Device Using CBD Method
Energy-efficient reconfigurable framework for evaluating hybrid NoCs
FPGA Implementation of Different Stochastic Biochemical Reactions Involved in a Cell
Quantized Neural Network Architecture for Hardware Efficient Real-Time 4K Image Super-Resolution
Fully Digital, Low Energy Capacitive Sensor Interface with an Auto-calibration Unit
Compact Modeling of Drain-Extended MOS Transistor Using BSIM-BULK Model
Broadband CMOS RF Logarithmic Power Detector for sub-6 GHz 5G Applications
A New Hardware Trojan Detection Technique using Class Weighted XGBoost Classifier
Design of a fault tolerant low-order interleaved memory based on the concept of bubble-stack an image storage perspective
Deterministic Shift Power Reduction in Test Compression
A Cache-Aware Strategy for H.264 Decoding on Multi-processor Architectures
A Custom Designed RISC-V ISA Compatible Processor for SoC
A novel approach to reusable time-economized STIL based pattern development
Quantum Domain Design of Clifford+T-Based Bidirectional Barrel Shifter
A Deep Dive into CORDIC Architectures to Implement Trigonometric Functions
Transient current estimation using S3C (Standard cell current transient characterization)
Design, Threat Analysis and Countermeasure for a Cache Performance Affecting Hardware Trojan
Impact of Fin Width and Graded Channel Doping on the Performance of 22nm SOI FinFET
Scalable VLSI Architecture for Hadamard Transforms of HEVC/H.265 Video Coding Standard
Standby leakage current estimation model for multi threshold CMOS inverter circuit in deep submicron technology
A Deep Insight into Frequency and Voltage Variation Impact on Memristor Performance and Applications of Memristor-NMOS Hybrid Structure in the Digital Domain
An Adaptive Digitally Tuned Flash-based LDO with Reduced Hardware for Sensor Nodes in WBAN
A pipelined memory-efficient architecture for face detection and tracking on a multicore environment
A PVT Insensitive Low-Power Differential Ring Oscillator
Approximate conditional carry adder for error tolerant applications
A 4 bit medium speed flash ADC using inverter based comparator in 0.18μm CMOS
Investigation of Traps in AlGaN/GaN HEMT Epitaxial Structure Using Conductance Method
Low Voltage, Low Power Transconductor for Low Frequency G_m -C Filters
A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS
Low Leakage Read Write Enhanced 9T SRAM Cell
Automatic Inverse Operation Detection and its Impact in High-level Synthesis
A Comparative Exploration About Approximate Full Adders for Error Tolerant Applications
A thermal aware 3D IC partitioning technique
Design and Implementation of High Performance CMOS Cross-Coupled LCVCO for Low Phase Noise
Assessment of Emerging Graphene based Network-on-chip for Integrated Circuit Design
A Hardware Generator for Posit Arithmetic and its FPGA Prototyping
Technology scaling and its side effects
Low Latency VLSI Architecture of Histogram Equalization of Images
Enhanced Edge Detection for Image Segmentation and its Real-Time Implementation
Random-LRU: A Replacement Policy for Chip Multiprocessors
Metal-Oxide Nanostructures Designed by Glancing Angle Deposition Technique and Its Applications on Sensors and Optoelectronic Devices: A Review
Low Write Energy STT-MRAM Cell Using 2T- Hybrid Tunnel FETs Exploiting the Steep Slope and Ambipolar Characteristics