yusuke1997/dblp-id-title huggingface dataset:
Clopenness of Systems: The Interwoven Nature of Ecosystems
Optimizing for Sustainability: Product Ops and Software Waste Reduction
Anticipating Success of a Business-Critical Software Project: A Comparative Case Study of Waterfall and Agile Approaches
DevOps Challenges in Organizations: Through Professional Lens
Workshop Notes: From Start-up to SaaS Conglomerate: Life Cycles of Software Products, IW-LCSP 2013
The Importance of the Business Idea for New Venture Creation in the Software Industry
Data-Limited Continuous Experimentation (dlCE): A Literature Review
Game Development Accelerator - Initial Design and Research Approach
Differentiation in Freemium: Where Does the Line Lie?
Hybrid Work in Agile Software Development
Invited paper: EcoSysNetworks: A Method for Visualizing Software Ecosystems
Risk Exposure and Management in Software Development - A Survey of Multiple Software Startups
Impact of Enterprise System Modularity on Process Performance
Companion Proceedings of the 14th International Conference on Software Business (PhD Retreat, Posters & Demos Track), Lahti, Finland, November 27-29, 2023
Design Principles for a Crowd-Based Prototype Validation Platform
Workshop on Competencies for the Globalization of Information Systems in Knowledge-Intensive Settings
Software Ecosystem Roles Classification
Management Accounting Concepts for Inner Source Software Engineering
A Survey on the Perception of Innovation in a Large Product-Focused Software Organization
A Framework for Strategic Positioning of IT-Products
Don't Start from Scratch: A Modularized Architecture for Business Model Development Tools
Developing a Maturity Matrix for Software Product Management
A Trend Analysis of Software Business Research
Democratizing Software Development: A Systematic Multivocal Literature Review and Research Agenda on Citizen Development
Software Ecosystems: A Set of Management Practices for Platform Integrators in the Telecom Industry
Managerial Growth Challenges in Small Software Firms: A Multiple-Case Study of Growth-Oriented Enterprises
Cloud Services Pricing Models
Revenue Models of Application Developers in Android Market Ecosystem
Model-driven Design and Management of Professional Education Programmes
Gender Bias in the Recruitment Process of IT Startups in the Netherlands
A Board Game to Teach Team Composition in Software Startups
A Software Engineering Course that Promotes Entrepreneurship: Insights from a VUCA Perspective
A Framework for Software Ecosystem Governance
From Agile Software Development to Mercury Business
Startup Creation Beyond Hackathons - A Survey on Startup Development and Support
The Economic Anatomy of Paid Crowdsourcing Platforms
The Impact of DevOps Critical Success Factors and Organizational Practices
A Systematic Mapping Study on Software Ecosystems
Continuous Experimentation with Product-Led Business Models: A Comparative Case Study
Software Business - Third International Conference, ICSOB 2012, Cambridge, MA, USA, June 18-20, 2012. Proceedings
Controlling Lost Opportunity Costs in Agile Development - The Basic Lost Opportunity Estimation Model for Requirements Scoping
PDISC - Towards a Method for Software Product DISCovery - Type: Exploratory Paper
Network Analysis of Platform Ecosystems: The Case of Internet of Things Ecosystem
Lean Product Development in Early Stage Startups
Hybrid Revenue Models of Software Companies and their Relationship to Hybrid Business Models
Lahti Software City: Evidence of Regional Development in IT & Software Industry
Determinants for the Success of Software Startups: Insights from a Regional Cluster
Topics in Software Industry Transformation Research: A Topic Analysis of Major IS Conferences
The Use of Generative AI Tools in the Inception Stage of Software Startups
On hardware generation of random single input change test sequences
A new EDA flow for the mitigation of SEUs in dynamic reconfigurable FPGAs
Error detection and recovery in better-than-worst-case timing designs
Convolutional compaction-driven diagnosis of scan failures
Real-Time Control-Flow Integrity for Multicore Mixed-Criticality IoT Systems
Power Side-Channel Attacks and Countermeasures on Computation-in-Memory Architectures and Technologies
Relation Coverage: A New Paradigm for Hardware/Software Testing
Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions
Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links
Shadow-scan design with low latency overhead and in-situ slack-time monitoring
Test for low cost CMOS image sensors
15th European Test Symposium, ETS 2010, Prague, Czech Republic, May 24-28, 2010
Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology
On-Chip Training of Crosstalk Predictors to Fit Uncertainties
A new BIST scheme for 5GHz low noise amplifiers
Automated area and coverage optimization of minimal latency checkers
Local Trimming Method for Enhancing the Read Reliability of STT-MRAMs
Aging-aware coding scheme for memory arrays
Yield analysis for repairable embedded memories
Improving polynomial datapath debugging with HEDs
A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter
A new approach for the nonlinearity test of ADCs/DACs and its application for BIST
Analysis and Mitigation of Electromigration in RF Circuits: An LNA Case Study
Counteracting malicious faults in cryptographic circuits
9th European Test Symposium, ETS 2004, Ajaccio, France, May 23-26, 2004
Towards a BIST technique for noise figure evaluation
BitFREE: On Significant Speedup and Security Applications of FPGA Bitstream Format Reverse Engineering
Test, Reliability and Functional Safety Trends for Automotive System-on-Chip
Reconciling the IC test and security dichotomy
A real world application used to implement a true IDDQ based test strategy (facts and figures)
System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies
Experimental Validation of a Fully Digital BISTfor Cascaded Sigma Delta Modulators
On-Chip Evaluation, Compensation, and Storage of Scan Diagnosis Data - A Test Time Efficient Scan Diagnosis Architecture
Reconfigurable Concurrent Error Detection adaptive to dynamicity of power constraints
Systematic generation of diagnostic software-based self-test routines for processor components
Transistor stuck-on fault detection tests for digital CMOS circuits
Purely Digital BIST for Any PLL or DLL
Embedded Tutorial on Low Power Test
Indirect method for random jitter measurement on SoCs using critical path characterization
A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks
Current-based testable design of level shifters in liquid crystal display drivers
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC
Ranking of Suspect Faulty Blocks Using Dataflow Analysis and Dempster-Shafer Theory for the Diagnosis of Board-Level Functional Failures
Online Profiling for cluster-specific variable rate refreshing in high-density DRAM systems
Covering hard-to-detect defects by thermal quorum sensing
A Hardware-Based Approach for Fault Detection in RTOS-Based Embedded Systems
New Standard-under-Development for Chiplet Interconnect Test and Repair: IEEE Std P3405
Design of fault-tolerant neuromorphic computing systems
Model-driven AMS Test Setup Validation Tool prepared for IEEE P1687.2
Digital Built-in Self-Test for Phased Locked Loops to Enable Fault Detection
Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs
BISTs for post-bond test and electrical analysis of high density 3D interconnect defects
Enhancement of Clock Delay Faults Testing
ETS 2015 best paper
Smart-hopping: Highly efficient ISA-level fault injection on real hardware
A supervised machine learning application in volume diagnosis
Microprocessor cores
Embedded synthetic instruments for Board-Level testing
Electrically-induced thermal stimuli for MEMS testing
Approximate Communication: Balancing Performance, Power, Reliability, and Safety
Improving test pattern generation in presence of unknown values beyond restricted symbolic logic
Built-in Test Solutions for the Electrode Structures in Bio-Fluidic Microsystems
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Towards an ADC BIST scheme using the histogram test technique
Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries
Characterization and handling of low-cost micro-architectural signatures in MPSoCs
Compressor design for silicon debug
A very low cost and highly parallel DfT method for analog and mixed-signal circuits
Automatic generation of in-circuit tests for board assembly defects
Categorizing and Analysis of Activated Faults in the FlexRay Communication Controller Registers
Toggle-masking scheme for x-filtering
A low capture power test generation method using capture safe test vectors
Automatic testing of analog ICs for latent defects using topology modification
Design-for-Test and Calibration for Silicon Photonics using Ring Resonators and Wavelength Division Multiplexing
Built-in self-diagnosis exploiting strong diagnostic windows in mixed-mode test
A low-cost susceptibility analysis methodology to selectively harden logic circuits
Image Test Libraries for the on-line self-test of functional units in GPUs running CNNs
A Novel Collaborative SSD Test Case Clustering Method Associating I/O Workload and Function Coverage
Testing of digitally assisted adaptive analog/RF systems using tuning knob - Performance space estimation
LearnX: A Hybrid Deterministic-Statistical Defect Diagnosis Methodology
A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults
GNN-Based INC and IVC Co-Optimization for Aging Mitigation
On-chip delay measurement circuit
Detection of IJTAG attacks using LDPC-based feature reduction and machine learning
Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices
Multivariate model for test response analysis
A design methodology to realize delay testable controllers using state transition information
Lifecycle Management of Emerging Memories
VLSI Test technology: Why is the field not sexy enough?
Specification and verification of security in reconfigurable scan networks
Large Language Models (LLMs) for Verification, Testing, and Design
Automating Greybox System-Level Test Generation
Super Acceleration of Dilithium in MPSoCs Critical Environments
Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions
Application of supply current testing to analogue circuits, towards a structural analogue test methodology
Concurrent Estimation of a PLL Transfer Function by Cross-Correlation with pseudo-random Jitter
Concurrent Error Detection for LSTM Accelerators
In situ measurement of aging-induced performance degradation in digital circuits
Analyzing bridging faults impact on EEPROM cell array
harDNNing: a machine-learning-based framework for fault tolerance assessment and protection of DNNs
A novel adaptive fault tolerant flip-flop architecture based on TMR
Low-Cost Online Testing of Asynchronous Handshakes
IEEE European Test Symposium, ETS 2024, The Hague, Netherlands, May 20-24, 2024
Security in Autonomous Systems
Analysis of cell-aware test pattern effectiveness - A case study using a 32-bit automotive microcontroller
Re-using BIST for circuit aging monitoring
A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression
Computing with Printed and Flexible Electronics
Exploiting Active Learning for Microcontroller Performance Prediction
Logic simulation and fault collapsing with shared structurally synthesized bdds
Extendable E 2 I-TEST for Chiplet-based Inter-die Interconnects
Process-variability aware delay fault testing of ΔV T and weak-open defects
Coverage of formal properties based on a high-level fault model and functional ATPG
Interconnect-aware tests to complement gate-exhaustive tests
IEEE European Test Symposium, ETS 2022, Barcelona, Spain, May 23-27, 2022
Low cost concurrent test implementation for linear digital systems
Modeling Static Noise Margin for FinFET based SRAM PUFs
On-the-fly timing-aware built-in self-repair for high-speed interposer wires in 2.5-D ICs
Multiple-defect diagnosis for Logic Characterization Vehicles
26th IEEE European Test Symposium, ETS 2021, Bruges, Belgium, May 24-28, 2021
Critical Fault-Based Pattern Generation for Screening SDDs
Online Detection of Unique Faults in RRAMs
A diagnostic test generation system and a coverage metric
Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction
IoT: Source of test challenges
Configurable fault-tolerant link for inter-die communication in 3D on-chip networks
Factoring variability in the Design/Technology Co Optimisation (DTCO) in advanced CMOS
Add-on blocks and algorithms for improving stimulus compression
Accelerated Shift Registers for X-tolerant Test Data Compaction
Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories
Critical Path Selection for Delay Test Considering Coupling Noise
Test power reduction in compression-based reconfigurable scan architectures
Using dynamic shift to reduce test data volume in high-compression designs
MTMS: Age-Aware Multi-Task Multi-Layer Stacking for SSD Failure Prediction
Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches
Applying IEEE Std 1838 to the 3DIC Design Trishul - A Case Study
Alternatives to Fault Injections for Early Safety/Security Evaluations
Test-station for flexible semi-automatic wafer-level silicon photonics testing
Automatic Generation of Instructions to Robustly Test Delay Defects in Processors
AI-Assisted Framework for Real-Time Monitoring and Management of Probe Cards in Electrical Wafer Sort Applications
From embedded test to embedded diagnosis
IEEE 1838 compliant scan encryption and integrity for 2.5/3D ICs
Low Cost Parametric Failure Diagnosis of RF Transceivers
Cyber-physical systems: A security perspective
Aging guardband reduction through selective flip-flop optimization
SIC pair generation in optimal time using rotatable counters
Approximate Fault-Tolerant Neural Network Systems
A programmable time measurement architecture for embedded memory characterization
Securely connected vehicles - what it takes to make self-driving cars a reality
Extracting device-parameter variations using a single sensitivity-configurable ring oscillator
Reliability analysis for power MOSFET based on multi-physics simulation
Novel Design For Test (DFT) Concept to Check the Spectral Mask Compliance Defined in the IEEE Std. 802.15.6-2012 of Wireless-Body-Area-Network (WBAN) IC-Devices
Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs
iBoX - Jitter based Power Supply Noise sensor
Timing Vulnerability Factors of Ultra Deep-sub-micron CMOS
Modeling gate oxide short defects in CMOS minimum transistors
Compact Protection Codes for protecting memory from malicious data and address manipulations
On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits
Combining Built-In Redundancy Analysis with ECC for Memory Testing
On the Impact of Hardware Timing Errors on Stochastic Computing based Neural Networks
Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips
Error-correction schemes with erasure information for fast memories
Requirements for delay testing of look-up tables in SRAM-based FPGAs
Efficient selection of signatures for analog/RF alternate test
Major eras of Design for Test
Combining deterministic logic BIST with test point insertion
LLM-aided Test Generation for Custom Neural Network Hardware Accelerators
PPM Reduction on Embedded Memories in System on Chip
Setting test conditions for improving SRAM reliability
Derivation of the reliability metric for digital circuits
On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests
Fault-detection-strengthened method to enable the POST for very-large automotive MCU in compliance with ISO26262
Reducing analogue fault-simulation time by using high-level modelling in dotss for an industrial design
Low-Complexity Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip
Software-based self-test techniques of computational modules in dual issue embedded processors
A DFT for semi-DC fault diagnosis for switched-capacitor circuits
Self-Aware Silicon: Enhancing Lifecycle Management with Intelligent Testing and Data Insights
Online Fault-Tolerance for Memristive Neuromorphic Fabric Based on Local Approximation
Through-Silicon-Via resistive-open defect analysis
Deterministic BIST with partial scan
Computation and Application of Absolute Dominators in Industrial Designs
Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering
Test challenges in nanometer technologies
A system level boundary scan controller board for VME applications [to CERN experiments]
New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG)
Novel ATPG algorithms for transition faults
Security and trust in the analog/mixed-signal/RF domain: A survey and a perspective
Fault Masking and Diagnosis in Reversible Circuits
A parameterizable fault simulator for bridging faults
Enhancing Delay Fault Coverage through Low Power Segmented Scan
Test tool qualification through fault injection
Transit-Guard: An OS-based Defense Mechanism Against Transient Execution Attacks
Increasing autonomous fault-tolerant FPGA-based systems' lifetime
Machine learning based soft error rate estimation of pass transistor logic in high-speed communication
SiCBit-PUF: Strong in-Cache Bitflip PUF Computation for Trusted SoCs
Model-based avionic systems testing for the airbus family
Quantitative evaluation of register vulnerabilities in RTL control paths
Something I Always Wanted to Know About Test, But Was Afraid to Ask
B-open: A New Defect in Nanometer Technologies due to SADP Process
Novel built-in methodology for defect testing of capacitor oxide in SAR analog to digital converters for critical automotive applications
Robust amplitude measurement for RF BIST applications
A DFT Architecture for Asynchronous Networks-on-Chip
Linking Chip, Board, and System Test via Standards
Secrets Leaking Through Quicksand: Covert Channels in Approximate Computing
Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis
Designing area-efficient controllers for multi-cycle transient fault tolerant systems
A true random number generator with on-line testability
On-chip Built-In Self-Calibration of Thermal Variations for Mixed-Signal In-Memory Computing
Design and testing methodologies for true random number generators towards industry certification
Adaptive testing of chips with varying distributions of unknown response bits
Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters
Temperature-Variation-Aware Test Pattern Optimization
Defect analysis in power mode control logic of low-power SRAMs
System level testing of virtual switch (re-)configuration over IP
Using dummy bridging faults to define a reduced set of target faults
A software-based self test of CUDA Fermi GPUs
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing
Special Session on RF/5G Test
European Test Symposium Teams: an Anniversary Snapshot
Re-using chip level DFT at board level
An Approach for Quantifying Path Correlation in Digital Circuits without any Path or Segment Enumeration
Impact of NBTI on analog components
MBIST-guided Reliability Improvement Scheme for SRAM-based Computation in Memory
An effective distributed BIST architecture for RAMs
Design and Test Challenges in Resistive Switching RAM (ReRAM): An Electrical Model for Defect Injections
Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories
Fast error detection through efficient use of hardwired resources in FPGAs
Defect filter for alternate RF test
Design, Verification, Test and In-Field Implications of Approximate Computing Systems
A Voltage-Mode Testing Method to Detect IDDQ Defects in Digital Circuits
Code generation for functional validation of pipelined microprocessors
On the fault-injection-caused increase of the DAE-index in analogue fault simulation
ROM fault diagnosis for O(n 2 ) test algorithms
Smart Redundancy Schemes for ANNs Against Fault Attacks
Measuring defect tolerance within mixed-signal ICs
Improving Reliability in NoCs by Application-Specific Mapping Combined with Adaptive Fault-Tolerant Method in the Links
Test Data-Driven Machine Learning Models for Reliable Quantum Circuit Output
Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods
CGAN-based Automated Fault Injection
Exploration of a digital-based solution for the generation of 2.4GHz OQPSK test stimuli
Characterization of Ultra-low Random Jitter Reduction Methods up to 36 GHz
Optimization of analog fault coverage by exploiting defect-specific masking
A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing
Memory reliability improvements based on maximized error-correcting codes
Variation-Aware Defect Characterization at Cell Level
Scan chain encryption for the test, diagnosis and debug of secure circuits
SAT-based post-processing for regional capture power reduction in at-speed scan test generation
Latent Defect Screening with Visually-Enhanced Dynamic Part Average Testing
Variation-aware deterministic ATPG
Data invalidation analysis for scan-based debug on multiple-clock system chips
Monitoring of BTI and HCI Aging in SRAM Decoders
Scan based speed-path debug for a microprocessor
Design of low cost fault tolerant analog circuits using real-time learned error compensation
Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors
Outlook for many-core systems: Cloudy with a chance of virtualization
An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?
Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space
An ECC-based memory architecture with online self-repair capabilities for reliability enhancement
Mems built-in-self-test using MLS
Test of embedded analog circuits based on a built-in current sensor
BISSEL: Built-In Self Security via Embedded Sensors for Reproducible Side-Channel Leakage Assessment
Signature Testing and Diagnosis of High Precision S? ADC Dynamic Specifications Using Model Parameter Estimation
Approximate computing: An emerging paradigm for energy-efficient design
Learn to Tune: Robust Performance Tuning in Post-Silicon Validation
Power efficient scan testing by exploiting existing error tolerance circuitry in a design
Bridge Defect Diagnosis for Multiple-Voltage Design
Synthesizing 56 Gbps NRZ Test Signals Using FPGAs and SiGe Logie
Evaluation of signature-based testing of RF/analog circuits
Scan test strategy for asynchronous-synchronous interfaces [SoC testing]
System-level DFT for consumer products
Defect detection from visual abnormalities in manufacturing process using I DDQ
SET Effects on Quasi Delay Insensitive and Synchronous Circuits
FLARE: Fault Attack Leveraging Address Reconfiguration Exploits in Multi-Tenant FPGAs
BIST-Assisted Analog Fault Diagnosis
Covering undetected transition fault sites with optimistic unspecified transition faults under multicycle tests
Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks
Design of Fault-Tolerant and Thermally Stable XOR Gate in Quantum dot Cellular Automata
On-line software-based self-test of the Address Calculation Unit in RISC processors
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
Revisiting Application-Dependent Test for FPGA Devices
Structural Testing of a RRAM-based AI Accelerator Core
Electronics Design-for-Test: Past, Present and Future
Memristor-based security primitives
Transcoders: A Better Alternative To Denoising Autoencoders
Holistic Memory DFT Partitioning Using a Convolution-Based Algorithm