yusuke1997/dblp-id-title huggingface dataset:
A fully standard-cell delay measurement circuit for timing variability detection
Bridging Clock Domains by Synchronizing the Mice in the Mousetrap
Phase Space Based NBTI Model
QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis
Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels
OPENTLM and SOCKET: Creating an Open EcoSystem for Virtual Prototyping of Complex SOCs
Resonant Multistage Charging of Dominant Capacitances
Voltage Scaling and Guardband Customization of Multiple Constituent Components in SoC-FPGA
DLV (Deep Low Voltage): Circuits and Devices
A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors
Subthreshold Circuit Design for Ultra-Low-Power Applications
One-Hot Residue Logarithmic Number Systems
Static Timing Model Extraction for Combinational Circuits
SET propagation in micropipelines
Power-Aware Branch Predictor Update for High-Performance Processors
Methodology for Energy-Efficient Digital Circuit Sizing: Important Issues and Design Limitations
Fast and accurate power annotated simulation: Application to a many-core architecture
Synthesis of Hybrid CBL/CMOS Cell Using Multiobjective Evolutionary Algorithms
Power Profiling of Embedded Analog/Mixed-Signal Systems
Methodology for Dynamic Power Verification of Contactless Smartcards
A versatile and reliable glitch filter for clocks
Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits
Memristive two-ports
Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms
Approximate DIV and SQRT instructions for the RISC-V ISA: An efficiency vs. accuracy analysis
Oscillation-based technique for post-bond parallel testing and diagnosis of multiple TSVs
A Fully Digital Numerical-Controlled-Oscillator
TCP Window Based DVFS for Low Power Network Controller SoC
Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip
Rapid power-management exploration using post-processing of the system-level simulation results
Fast Calculation of Permissible Slowdown Factors for Hard Real-Time Systems
Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis
RISC-V Extensions for Bit Manipulation Instructions
A topology optimization method for low-power logic circuits with dual-threshold independent-gate FinFETs
High-throughput FPGA implementation of the CCSDS 122.0-B-1 compression standard
An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis
A Systematic Performance Comparison of Ultra Low-Power AES S-Boxes
Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology
Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT Devices
An analytical model for the CMOS inverter
Optimization of Modules for Digital Audio Processing
Synthetic Generation of Events for Address-Event-Representation Communications
Memory Compaction and Power Optimization for Wavelet-Based Coders
Write Invalidation Analysis in Chip Multiprocessors
Constructing stability-based clock gating with hierarchical clustering
Power proportional adder design for Internet of Things in a 65 nm process
VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates
Accelerating Embedded Software Power Profiling Using Run-Time Power Emulation
Memristive logic: A framework for evaluation and comparison
Mixed Radix-2 and High-Radix RNS Bases for Low-Power Multiplication
SystemC AMS Extensions: New Language - New Methods - New Applications
Reducing Energy Consumption via Low-Cost Value Prediction
Tuning software-based fault-tolerance techniques for power optimization
Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques
An assessment of software lifecycle energy
Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results
Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level
Automatic design of arbitrary-size approximate sorting networks with error guarantee
Failure probability of a FinFET-based SRAM cell utilizing the most probable failure point
Design and test of a low-power 90nm XOR/XNOR gate for cryptographic applications
Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements
A Multi-Level Power-on Reset for Fine-Grained Power Management
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering
Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders
Power Supply Net for Adiabatic Circuits
A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect
Physical description and analysis of doped carbon nanotube interconnects
Early Power Estimation in Heterogeneous Designs Using SoCLib and SystemC-AMS
A Battery-Less BLE IoT Motion Detector Supplied by 2.45-GHz Wireless Power Transfer
Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing
Modeling and Reducing EMI in GALS and Synchronous Systems
System-Level Application-Specific NoC Design for Network and Multimedia Applications
Multiscale modeling of electron-ion interactions for engineering novel electronic devices and materials
Top Verification of Low Power System with "Checkerboard" Approach
Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICs
Self-Timed SRAM for Energy Harvesting Systems
Two-Phase MOBILE Interconnection Schemes for Ultra-Grain Pipeline Applications
Low Latency Synchronization Through Speculation
Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization
Power and Timing Driven Physical Design Automation
Optimization of Digital Audio Processing Algorithms Suitable for Hearing Aids
Non-invasive Power Simulation at System-Level with SystemC
Asynchronous Functional Coupling for Low Power Sensor Network Processors
New Battery Status Checking Method for Implantable Biomedical Applications
Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design
Crosstalk Waveform Modeling Using Wave Fitting
A scalable physical model for Nano-Electro-Mechanical relays
Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform
Back Annotation in High Speed Asynchronous Design
Metastability characterization for muller C-elements
Placement-based SER estimation in the presence of multiple faults in combinational logic
Leakage in CMOS Circuits - An Introduction
A Framework for Architecture-Level Exploration of 3-D FPGA Platforms
Power Optimization of Parallel Multipliers in Systems with Variable Word-Length
State Encoding for Low-Power FSMs in FPGA
Power consumption analysis using multi-view modeling
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures
A Reliable PUF in a Dual Function SRAM
Energy Efficient Elliptic Curve Processor
Reducing Energy Consumption of Computer Display by Camera-Based User Monitoring
Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform
Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm
Modeling Time Domain Magnetic Emissions of ICs
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level
Variability and sensitivity to process parameters variations in InGaAs dual-gate ultra-thin body MOSFETs: A scaling perspective
Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits
VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design
Worst-Case Performance Analysis Under Random Telegraph Noise Induced Threshold Voltage Variability
A Synergy of a Closed-Loop DVFS Controller and CPU Hot-Plug For Run-Time Thermal Management in Multicore Systems
A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms
A 260ps Quasi-static ALU in 90nm CMOS
An Approach to Energy Consumption Modeling in RC Ladder Circuits
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits
An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips
Fast Propagation of Hamming and Signal Distances for Register-Transfer Level Datapaths
Power Consumption Estimation of a C Program for Data-Intensive Applications
Multiclass Network Attack Classifier Using CNN Tuned with Genetic Algorithms
From edge to cloud: Design and implementation of a healthcare Internet of Things infrastructure
Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic
Optical sensor process variability in a 0.18 μm high voltage CMOS technology
Instruction Level Energy Modeling for Pipelined Processors
Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations
A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus
An Adiabatic Multiplier
Compact Static Power Model of Complex CMOS Gates
Semi Custom Design: A Case Study on SIMD Shufflers
Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption
Low Level Adaptive Frequency in Synthesis of High Speed Digital Circuits
Instruction Buffering Exploration for Low Energy Embedded Processors
A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors
Evaluation of an Artificial Neural Network Approach for Timing Modeling of CMOS Gates
C-elements for Hardened Self-timed Circuits
Exploiting Temporal Misalignment to Optimize the Interconnect Performance for 3D Integration
Design of Reversible Logic Circuits by Means of Control Gates
Receiver Modeling for Static Functional Crosstalk Analysis
Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random V T Variations on Timing
Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data
Register File Energy Reduction by Operand Data Reuse
Parasitic effects on memristive logic architecture
Power Management and Its Impact on Power Supply Noise
On the origin of the fading memory effect in ReRAMs
Routing Resistance Influence in Loading Effect on Leakage Analysis
2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Karlsruhe, Germany, September 9-11, 2013
Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers
Power-efficient power-management logic
Low-Voltage Embedded RAMs - Current Status and Future Trends
Energy-Delay Space Analysis for Clocked Storage Elements Under Process Variations
A Flexible Framework for Fast Multi-objective Design Space Exploration of Embedded Systems
Fast and accurate solution for power estimation and DPA countermeasure design
A System Level Approach to Multi-core Thermal Sensors Calibration
Implementing VESA Display Stream Compression Encoder in FPGAs
Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units
Power Dissipation Impact of the Technology Mapping Synthesis on Look-Up Table Architectures
Perfect 3-Limited-Weight Code for Low Power I/O
Leakage Power Characterization Considering Process Variations
Intelligate: Scalable Dynamic Invariant Learning for Power Reduction
Quasi-Delay-Insensitive Computing Device: Methodological Aspects and Practical Implementation
Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques
Clock Network Synthesis with Concurrent Gate Insertion
Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing
A Methodology for Power-Aware Transaction-Level Models of Systems-on-Chip Using UPF Standard Concepts
A Novel Constant-Time Fault-Secure Binary Counter
A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits
Remote Power Control of Wireless Network Interfaces
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates
Static and Dynamic Power Reduction by Architecture Selection
Logarithmic Number System for Low-Power Arithmetic
Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer
Design and Industrialization Challenges of Memory Dominated SOCs
A Design Methodology for Secured ICs Using Dynamic Current Mode Logic
Process Characterization for Low VTH and Low Power Design
A methodology for scaling power dissipation values between different FPGAs
Monolithic Multi-mode DC-DC Converter with Gate Voltage Optimization
An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs
Advanced SoC virtual prototyping for system-level power planning and validation
Evaluation of hop count advantages of network-coded 2D-mesh NoCs
Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems
Calculation of worst-case execution time for multicore processors using deterministic execution
Product On-Chip Process Compensation for Low Power and Yield Enhancement
Design for Volume Manufacturing in the Deep Submicron ERA
Fast Low-Power 64-Bit Modular Hybrid Adder
A Statistic Power Model for Non-synthetic RTL Operators
Leakage Power Analysis and Comparison of Deep Submicron Logic Gates
A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits
Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates
A New Logic Transformation Method for Both Low Power and High Testability
Embedded EEPROM Speed Optimization Using System Power Supply Resources
A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application
Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation
Adaptive energy minimization of embedded heterogeneous systems using regression-based learning
3D-IC signal TSV assignment for thermal and wirelength optimization
μDMA: An autonomous I/O subsystem for IoT end-nodes
Adaptive Synchronization for DVFS Applications
Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs
Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002
Design methodology for low-power embedded microprocessors
Connecting E-Dreams to Deep-Submicron Realities
Design of variable latency adder based on present and transitional states prediction
A Cycle-Accurate Energy Estimator for CMOS Digital Circuits
Optimization on cell-library design for digital Application Specific Printed Electronics Circuits
An Improved Power Macro-Model for Arithmetic Datapath Components
RTL-Based Signal Statistics Calculation Facilitates Low Power Design Approaches
TAST Profiler and Low Energy Asynchronous Design Methodology
High-Speed and Low-Power PID Structures for Embedded Applications
Design and verification of analog CMOS circuits using the gm/ID-method with age-dependent degradation effects
Method to evaluate energy saving techniques in data buses
Hardware reliability of embedded systems: Are we there yet?
Design of Digital Filters for Low Power Applications Using Integer Quadratic Programming
Ultra Low Voltage High Speed Differential CMOS Inverter
Power and Profit: Engineering in the Envelope
Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing
Circuit Design Style for Energy Efficiency: LSDL and Compound Domino
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses
Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry
Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption
Functional Verification of Low Power Designs at RTL
An FPGA-based thermal emulation framework for multicore systems
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder
The Magic Rule of Tiles: Virtual Delay Insensitivity
The Energy Scalability of Wavelet-Based, Scalable Video Decoding
Power-Aware Scheduling for Hard Real-Time Embedded Systems Using Voltage-Scaling Enabled Architectures
Minimizing the Power Consumption of an Asynchronous Multiplier
Statistical Characterization of Library Timing Performance
Statistical Modeling and Analysis of Static Leakage and Dynamic Switching Power
Advancing Rational Exploitation of Water Irrigation Using 5G-IoT Capabilities: The AREThOU5A Project
The Optimal Wire Order for Low Power CMOS
Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings
An Energy-Tree Based Routing Algorithm in Wireless Ad-Hoc Network Environments
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives
Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems
Differential Capacitance Analysis
Leakage Reduction at the Architectural Level and Its Application to 16 Bit Multiplier Architectures
Statistical Critical Path Analysis Considering Correlations
Low Power Co-design Tool and Power Optimization of Schedules and Memory System
A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages
IR-drop Reduction Through Combinational Circuit Partitioning
Human α-thrombin detection platform using aptamers on a silicon nanowire field-effect transistor
Reliability of an Industrial Wireless Communication System using Approximate Units
Enhancing GALS Processor Performance Using Data Classification Based on Data Latency
A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design
A software framework to calculate local temperatures in CMOS processors
Towards Novel Approaches in Design Automation for FPGA Power Optimization
Pipelines in Dynamic Dual-Rail Circuits
Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor
High Level Area and Current Estimation
A Novel Methodology for Evaluating the Energy Consumption of IP Blocks in System-Level Designs
PMHLS 2.0: An automated optimization of power management during high-level synthesis
Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications
Traveling the Wild Frontier of Ultra Low-Power Design
Radix-3 low-complexity modulo-M multipliers
Empirical CPU power modelling and estimation in the gem5 simulator
An analytical delay model for ReRAM memory cells
A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation
An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers
Statistic Implementation of QDI Asynchronous Primitives
Asynchronous First-in First-out Queues
Wirelength Reduction Using 3-D Physical Design
A 40nm Critical Path Monitor for the Detection of Setup and Hold Time Violations
An Automated Framework for Power-Critical Code Region Detection and Power Peak Optimization of Embedded Software
A Clock Generator Driven by a Unified-CBiCMOS Buffer Driver for High Speed and Low Energy Operation
Energy-aware mapping for dependable virtual networks
Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses
Hardware-assisted power estimation for design-stage processors using FPGA emulation
A Holistic Approach to System Level Energy Optimization
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications
Morphological Reservoir Computing Hardware
Design of High-Speed Low-Power Parallel-Prefix VLSI Adders
A Flexible and Accurate Energy Model of an Instruction-Set Simulator for Secure Smart Card Software Design
System Level Power Estimation of System-on-Chip Interconnects in Consideration of Transition Activity and Crosstalk
An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design
Effect of Temperature Variation in Experimental DPA and DEMA Attacks
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits
Degradation Delay Model Extension to CMOS Gates
Analysis of High-Speed Logic Families
The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing
Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop
A Hardware Implementation of the User-Centric Display Energy Management
Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory
RRAM variability and its mitigation schemes
An On-Chip Flip-Flop Characterization Circuit
Effects of Temperature in Deep-Submicron Global Interconnect Optimization
Modeling of Propagation Delay of a First Order Circuit with a Ramp Input
Hardware Implementation of a Low-Power K-Best MIMO Detector Based on a Hybrid Merge Network
Robust SAT-Based Search Algorithm for Leakage Power Reduction
Rate-distortion and energy performance of HEVC video encoders
Dynamic Voltage Scheduling for Real Time Asynchronous Systems
Circuit Design Techniques for On-Chip Power Supply Noise Monitoring System
Low-Voltage, Double-Edge-Triggered Flip Flop
New GALS Technique for Datapath Architectures
The semantic of the power intent format UPF: Consistent power modeling from system level to implementation
DOE based high-performance gate-level pipelines
ASTEC: Asynchronous Technology for Low Power and Secured Embedded Systems
Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit
Logic Synthesis of Handshake Components Using Structural Clustering Techniques
A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing
Heuristic for Two-Level Cache Hierarchy Exploration Considering Energy Consumption and Performance
Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip
Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs
Hold-time violation analysis and fixing in near-threshold region
Design Methodology for Rapid Development of SoC ICs Based on an Innovative System Architecture with Emphasis to Timing Closure and Power Consumption Optimization
An Asynchronous Viterbi Decoder for Low-Power Applications
Optimization of Master-Slave Flip-Flops for High-Performance Applications
Temperature Dependency in UDSM Process
Fault-tolerant routing methodology for Networks-on-Chip
Prototyping memristors in digital system with an FPGA-based testing environment
Physical Extension of the Logical Effort Model
A unique network EDA tool to create optimized ad hoc binary to residue number system converters
FPGA-Based Platform for Fast Accurate Evaluation of Ultra Low Power SoC
A Retargetable Environment for Power-Aware Code Evaluation: An Approach Based on Coloured Petri Net
Testing Framework for in-Hardware Verification of the Hardware Modules Generated Using HLS
Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates
The Effect of Data-Reuse Transformations on Multimedia Applications for Different Processing Platforms
Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate
CMOS process transient noise simulation analysis and benchmarking
A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder
A lightweight-system-level power and area estimation methodology for application specific instruction set processors
Thermally-aware composite run-time CPU power models
Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature
Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis