yusuke1997/dblp-id-title huggingface dataset:
Atomicity Checking in Linear Time using Vector Clocks
FLASH vs. (Simulated) FLASH: Closing the Simulation Loop
Translation Lookaside Buffer Consistency: A Software Approach
MDPeek: Breaking Balanced Branches in SGX with Memory Disambiguation Unit Side Channels
Achieving Near-Zero Read Retry for 3D NAND Flash Memory
QR decomposition on GPUs
A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing
PIBE: practical kernel control-flow hardening with profile-guided indirect branch elimination
KVM/ARM: the design and implementation of the linux ARM hypervisor
Performance analysis of accelerated image registration using GPGPU
A real system evaluation of hardware atomicity for software speculation
Adaptive set pinning: managing shared caches in chip multiprocessors
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA
High performance computation and interactive display of molecular orbitals on GPUs and multi-core CPUs
MSCCLang: Microsoft Collective Communication Language
Astra: Exploiting Predictability to Optimize Deep Learning
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2, ASPLOS 2023, Vancouver, BC, Canada, March 25-29, 2023
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Fat-Tree QRAM: A High-Bandwidth Shared Quantum Random Access Memory for Parallel Queries
Bell: bit-encoding online memory leak detection
Flexible architectural support for fine-grain scheduling
LightStore: Software-defined Network-attached Key-value Drives
DNNGuard: An Elastic Heterogeneous DNN Accelerator Architecture against Adversarial Attacks
Reducing solid-state drive read latency by optimizing read-retry
Towards Sound Reassembly of Modern x86-64 Binaries
Breaking the Boundaries in Heterogeneous-ISA Datacenters
ElasticMiter: Formally Verified Dataflow Circuit Rewrites
Plankton: Reconciling Binary Code and Debug Information
Risotto: A Dynamic Binary Translator for Weak Memory Model Architectures
2ndStrike: toward manifesting hidden concurrency typestate bugs
Overlapped Loop Support in the Cydra 5
Mobius: Fine Tuning Large-Scale Models on Commodity GPU Servers
Architectural implications of nanoscale integrated sensing and computing
Exploiting the Regular Structure of Modern Quantum Architectures for Compiling and Optimizing Programs with Permutable Operators
Dynamic Memory Disambiguation Using the Memory Conflict Buffer
Maximum benefit from a minimal HTM
Crossing Guard: Mediating Host-Accelerator Coherence Interactions
IceBreaker: warming serverless functions better with heterogeneity
Evaluating the Performance of Software Cache Coherence
JUNO: Optimizing High-Dimensional Approximate Nearest Neighbour Search with Sparsity-Aware Algorithm and Ray-Tracing Core Mapping
Improving Cache Performance with Balanced Tag and Data Paths
CALOREE: Learning Control for Predictable Latency and Low Energy
Understanding prediction-based partial redundant threading for low-overhead, high- coverage fault tolerance
FaaSMem: Improving Memory Efficiency of Serverless Computing with Memory Pool Architecture
Replica: A Wireless Manycore for Communication-Intensive and Approximate Data
Architectural Support for Copy and Tamper Resistant Software
PnP: Pruning and Prediction for Point-To-Point Iterative Graph Analytics
BitPacker: Enabling High Arithmetic Efficiency in Fully Homomorphic Encryption Accelerators
ExeGPT: Constraint-Aware Resource Scheduling for LLM Inference
Fast, flexible, and comprehensive bug detection for persistent memory programs
In-Network Aggregation with Transport Transparency for Distributed Training
KIT: Testing OS-Level Virtualization for Functional Interference Bugs
Load and MLP-Aware Thread Orchestration for Recommendation Systems Inference on CPUs
EVStore: Storage and Caching Capabilities for Scaling Embedding Tables in Deep Recommendation Systems
CSSTs: A Dynamic Data Structure for Partial Orders in Concurrent Execution Analysis
JaBEE: framework for object-oriented Java bytecode compilation and execution on graphics processor units
Optimizing Dynamic-Shape Neural Networks on Accelerators via On-the-Fly Micro-Kernel Polymerization
Orchestrated trios: compiling for efficient communication in Quantum programs with 3-Qubit gates
What You Trace is What You Get: Dynamic Stack-Layout Recovery for Binary Recompilation
M5: Mastering Page Migration and Memory Management for CXL-based Tiered Memory Systems
A Study of Scalar Compilation Techniques for Pipelined Supercomputers
The rise of the expert amateur: DIY culture and the evolution of computer science
A hierarchical neural model of data prefetching
TrackFM: Far-out Compiler Support for a Far Memory World
Ziria: A DSL for Wireless Systems Programming
Failure Correction Techniques for Large Disk Arrays
IOCost: block IO control for containers in datacenters
Thermostat: Application-transparent Page Management for Two-tiered Main Memory
DeNovoND: efficient hardware support for disciplined non-determinism
Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories
The ASPLOS 2025 / EuroSys 2025 Contest on Intra-Operator Parallelism for Distributed Deep Learning
Tradeoffs in fine-grained heap memory protection
Batch-Aware Unified Memory Management in GPUs for Irregular Workloads
Commutativity analysis for software parallelization: letting program transformations see the big picture
Power routing: dynamic power provisioning in the data center
Neural architecture search as program transformation exploration
Peacenik: Architecture Support for Not Failing under Fail-Stop Memory Consistency
Stepwise Debugging for Hardware Accelerators
ASPLOS-VI Proceedings - Sixth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 4-7, 1994
Writing Solaris device drivers in Java
ConSeq: detecting concurrency bugs through sequential errors
Re-architecting I/O Caches for Emerging Fast Storage Devices
Dynamic Partial Deadlock Detection and Recovery via Garbage Collection
Gigaflow: Pipeline-Aware Sub-Traversal Caching for Modern SmartNICs
Hardware/Software Tradeoffs for Increased Performance
Overlapping Execution with Transfer Using Non-Strict Execution for Mobile Programs
Efficient Microsecond-scale Blind Scheduling with Tiny Quanta
Quantifying the NUMA Behavior of Partitioned GPGPU Applications
PIM Is All You Need: A CXL-Enabled GPU-Free System for Large Language Model Inference
Breaking the computation and communication abstraction barrier in distributed machine learning workloads
BatchZK: A Fully Pipelined GPU-Accelerated System for Batch Generation of Zero-Knowledge Proofs
An Experimental Coprocessor for Implementing Persistant Objects on an IBM 4381
FMCC: Flexible Measurement-based Quantum Computation over Cluster State
FlatFlash: Exploiting the Byte-Accessibility of SSDs within a Unified Memory-Storage Hierarchy
Bolt: I Know What You Did Last Summer... In The Cloud
Full system simulation of many-core heterogeneous SoCs using GPU and QEMU semihosting
Few-to-Many: Incremental Parallelism for Reducing Tail Latency in Interactive Services
Low-overhead memory leak detection using adaptive statistical profiling
Migrating a CISC Computer Family onto RISC via Object Code Translation
PICSEL: measuring user-perceived performance to control dynamic frequency scaling
Decker: Attack Surface Reduction via On-Demand Code Mapping
TensorIR: An Abstraction for Automatic Tensorized Program Optimization
Architectural Support for Programming Languages and Operating Systems, ASPLOS 2013, Houston, TX, USA, March 16-20, 2013
Towards End-to-End Optimization of LLM-based Applications with Ayo
Scaling up Superoptimization
MoE-Lightning: High-Throughput MoE Inference on Memory-constrained GPUs
Energy-aware Scheduling and Input Buffer Overflow Prevention for Energy-harvesting Systems
Path-sensitive and alias-aware typestate analysis for detecting OS bugs
Continual flow pipelines
OS and Compiler Considerations in the Design of the IA-64 Architecture
PICACHU: Plug-In CGRA Handling Upcoming Nonlinear Operations in LLMs
ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989
Merlin: Multi-tier Optimization of eBPF Code for Performance and Compactness
MAGIS: Memory Optimization via Coordinated Graph Transformation and Scheduling for DNN
Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn
NeuMMU: Architectural Support for Efficient Address Translations in Neural Processing Units
Hydride: A Retargetable and Extensible Synthesis-based Compiler for Modern Hardware Architectures
A one-for-all and o ( v log( v ))-cost solution for parallel merge style operations on sorted key-value arrays
A spatial path scheduling algorithm for EDGE architectures
Spada: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow
FEASTA: A Flexible and Efficient Accelerator for Sparse Tensor Algebra in Machine Learning
Randomized row-swap: mitigating Row Hammer by breaking spatial correlation between aggressor and victim rows
TaOPT: Tool-Agnostic Optimization of Parallelized Automated Mobile UI Testing
FirmUp: Precise Static Detection of Common Vulnerabilities in Firmware
Efficent Synchronization Primitives for Large-Scale Cache-Coherent Multiprocessors
Codesign of quantum error-correcting codes and modular chiplets in the presence of defects
Blink: managing server clusters on intermittent power
Identifying Security Critical Properties for the Dynamic Verification of a Processor
AfterImage: Leaking Control Flow Data and Tracking Load Operations via the Hardware Prefetcher
The Effectiveness of Multiple Hardware Contexts
GRACE: A Scalable Graph-Based Approach to Accelerating Recommendation Model Inference
Ditto: End-to-End Application Cloning for Networked Cloud Services
Formalizing address spaces with application to Cuda, OpenCL, and beyond
Automated Synthesis of Comprehensive Memory Model Litmus Test Suites
History-Based Arbitration for Fairness in Processor-Interconnect of NUMA Servers
Cider: native execution of iOS apps on android
ZENO: A Type-based Optimization Framework for Zero Knowledge Neural Network Inference
Fast Out-Of-Order Processor Simulation Using Memoization
Fine-grain Access Control for Distributed Shared Memory
Efficient and scalable core multiplexing with M³v
The sharing architecture: sub-core configurability for IaaS clouds
Enzian: an open, general, CPU/FPGA platform for systems software research
Faults in linux: ten years later
Efficient Data Breakpoints
VSwapper: a memory swapper for virtualized environments
Avoiding Conflict Misses Dynamically in Large Direct-Mapped Caches
LifeStream: a high-performance stream processing engine for periodic streams
HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis
Automatic generation of peephole superoptimizers
Fast Mersenne prime testing on the GPU
The Dragon Processor
Understanding and Auto-Adjusting Performance-Sensitive Configurations
Parallel virtualized memory translation with nested elastic cuckoo page tables
Characterizing and Optimizing End-to-End Systems for Private Inference
PuDianNao: A Polyvalent Machine Learning Accelerator
Debugging Support for Pattern-Matching Languages and Accelerators
GPU acceleration of a production molecular docking code
Lifting Micro-Update Models from RTL for Formal Security Analysis
Analysis of Cache Invalidation Patterns in Multiprocessors
Traffic management: a holistic approach to memory placement on NUMA systems
DeepSigns: An End-to-End Watermarking Framework for Ownership Protection of Deep Neural Networks
The Mutators Reloaded: Fuzzing Compilers with Large Language Model Generated Mutation Operators
GPUDet: a deterministic GPU architecture
Fermihedral: On the Optimal Compilation for Fermion-to-Qubit Encoding
Fast Fine-Grained Global Synchronization on GPUs
Mnemosyne: lightweight persistent memory
MacroSS: macro-SIMDization of streaming applications
Switches for HIRE: resource scheduling for data center in-network computing
Cinnamon: A Framework for Scale-Out Encrypted AI
High performance predictable histogramming on GPUs: exploring and evaluating algorithm trade-offs
Training for multi-resolution inference using reusable quantization terms
Demand-based coordinated scheduling for SMP VMs
rIOMMU: Efficient IOMMU for I/O Devices that Employ Ring Buffers
Micro Blossom: Accelerated Minimum-Weight Perfect Matching Decoding for Quantum Error Correction
Language Models: The Most Important Compute Challenge of Our Time (Keynote)
ReQoS: reactive static/dynamic compilation for QoS in warehouse scale computers
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 4, ASPLOS 2023, Vancouver, BC, Canada, March 25-29, 2023
Language-parametric compiler validation with application to LLVM
High performance 3-D FFT using multiple CUDA GPUs
Some Requirements for Architectural Support of Software Debugging
Prototyping symbolic execution engines for interpreted languages
Reload+Reload: Exploiting Cache and Memory Contention Side Channel on AMD SEV
Cross-Failure Bug Detection in Persistent Memory Programs
ASSURE: automatic software self-healing using rescue points
Integration of Message Passing and Shared Memory in the Stanford FLASH Multiprocessor
SRAM has no chill: exploiting power domain separation to steal on-chip secrets
Harp: Leveraging Quasi-Sequential Characteristics to Accelerate Sequence-to-Graph Mapping of Long Reads
Locality-oblivious cache organization leveraging single-cycle multi-hop NoCs
Hardware counter driven on-the-fly request signatures
Reducing Memory Latency via Non-blocking and Prefetching Caches
StreamRay: a stream filtering architecture for coherent ray tracing
Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 1, ASPLOS 2025, Rotterdam, The Netherlands, 30 March 2025 - 3 April 2025
Data Center Power Oversubscription with a Medium Voltage Power Plane and Priority-Aware Capping
The Rio File Cache: Surviving Operating System Crashes
Communication optimizations for global multi-threaded instruction scheduling
Enabling Efficient Mobile Tracing with BTrace
Iterative optimization for the data center
Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), San Jose, California, USA, October 5-9, 2002
Simplifying and Accelerating NOR Flash I/O Stack for RAM-Restricted Microcontrollers
DREAM: A Dynamic Scheduler for Dynamic Real-time Multi-model ML Workloads
Reducing off-chip memory traffic by selective cache management scheme in GPGPUs
Sugar: Secure GPU Acceleration in Web Browsers
Beating OPT with Statistical Clairvoyance and Variable Size Caching
Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks
RISCs versus CISCs for Prolog: A Case Study
Dynamic tracking of page miss ratio curve for memory management
Whirlpool: Improving Dynamic Cache Management with Static Data Classification
COMPASS: a programmable data prefetcher using idle GPU shaders
ASPLOS-VII Proceedings - Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, Massachusetts, USA, October 1-5, 1996
NosWalker: A Decoupled Architecture for Out-of-Core Random Walk Processing
Reduced Hardware NOrec: A Safe and Scalable Hybrid Transactional Memory
ReBudget: Trading Off Efficiency vs. Fairness in Market-Based Multicore Resource Allocation via Runtime Budget Reassignment
vbench: Benchmarking Video Transcoding in the Cloud
SI-TM: reducing transactional memory abort rates through snapshot isolation
Devirtualizing Memory in Heterogeneous Systems
Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud
PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference
Page Placement Strategies for GPUs within Heterogeneous Memory Systems
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 1, ASPLOS 2024, La Jolla, CA, USA, 27 April 2024- 1 May 2024
Resource Allocation in a High Clock Rate Microprocessor
Respec: efficient online multiprocessor replayvia speculation and external determinism
VeGen: a vectorizer generator for SIMD and beyond
AWS Trainium: The Journey for Designing and Optimization Full Stack ML Hardware
Disengaged scheduling for fair, protected access to fast computational accelerators
Slipstream Processors: Improving both Performance and Fault Tolerance
TempGraph: An Efficient Chain-driven Temporal Graph Computing Framework on the GPU
Betty: Enabling Large-Scale GNN Training with Batch-Level Graph Partitioning
Compiler orchestrated prefetching via speculation and predication
CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment
HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description
Cheap Hardware Support for Software Debugging and Profiling
ASC: automatically scalable computation
Just-In-Time Compilation for Verilog: A New Technique for Improving the FPGA Programming Experience
Architectural Support for Synchronous Task Communication
Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, Palo Alto, California, USA, March 1-3, 1982
C4CAM: A Compiler for CAM-based In-memory Accelerators
Finding Unstable Code via Compiler-Driven Differential Testing
ClosureX: Compiler Support for Correct Persistent Fuzzing
TCS: FaaS (FPGA as a service)
Fence-free work stealing on bounded TSO processors
Hardware Architectures for Programming Languages and Programming Languages for Hardware Architectures
Systematic CXL Memory Characterization and Performance Analysis at Scale
Verifying security invariants in ExpressOS
Protecting adaptive sampling from information leakage on low-power sensors
Maximizing Performance Under a Power Cap: A Comparison of Hardware, Software, and Hybrid Techniques
Iterative induced dipoles computation for molecular mechanics on GPUs
Vectorization for digital signal processors via equality saturation
Anomaly Detection in Clouds: Challenges and Practice
Portable performance on heterogeneous architectures
SuperNoVA: Algorithm-Hardware Co-Design for Resource-Aware SLAM
High-Density Image Storage Using Approximate Memory Cells
Harnessing the Power of Specialization for Sustainable Computing
Cohort: Software-Oriented Acceleration for Heterogeneous SoCs
The design and implementation of microdrivers
Non-Volatile Memory for Fast, Reliable File Systems
Towards Efficient Superconducting Quantum Processor Architecture Design
Multi-Dimensional and Message-Guided Fuzzing for Robotic Programs in Robot Operating System
Loupe: Driving the Development of OS Compatibility Layers
Evolving RPC for active storage
PTEMagnet: fine-grained physical memory reservation for faster page walks in public clouds
Copy-on-Pin: The Missing Piece for Correct Copy-on-Write
Sentinel Scheduling for VLIW and Superscalar Processors
Cortical architectures on a GPGPU
Triple-A: a Non-SSD based autonomic all-flash array for high performance storage systems
RPCValet: NI-Driven Tail-Aware Balancing of µs-Scale RPCs
FaaSFlow: enable efficient workflow execution for function-as-a-service
ConMem: detecting severe concurrency bugs through an effect-oriented approach
NOREBA: a compiler-informed non-speculative out-of-order commit processor
Prism: Optimizing Key-Value Store for Modern Heterogeneous Storage Devices
The 5th Annual Workshop on General Purpose Processing with Graphics Processing Units, GPGPU-5, London, United Kingdom, March 3, 2012
FastGL: A GPU-Efficient Framework for Accelerating Sampling-Based GNN Training at Large Scale
Hardware/Software Cooperation in the iAPX-423
Puddle: A Dynamic, Error-Correcting, Full-Stack Microfluidics Platform
RAPID Programming of Pattern-Recognition Processors
Paulihedral: a generalized block-wise compiler optimization framework for Quantum simulation kernels
Quantifying the design-space tradeoffs in autonomous drones
Vortex: Extreme-Performance Memory Abstractions for Data-Intensive Streaming Applications
Programming FPGAs Using OpenCL from Performance Model to Application Study
QECC-Synth: A Layout Synthesizer for Quantum Error Correction Codes on Sparse Architectures
Enhancing Cross-ISA DBT Through Automatically Learned Translation Rules
Paragon: QoS-aware scheduling for heterogeneous datacenters
CoolAir: Temperature- and Variation-Aware Management for Free-Cooled Datacenters
Towards Unified Analysis of GPU Consistency
Tandem Processor: Grappling with Emerging Operators in Neural Networks
Inter-core prefetching for multicore processors using migrating helper threads
Taurus: a data plane architecture for per-packet ML
Fleet: A Framework for Massively Parallel Streaming on FPGAs
Firmware Structure and Architectural Support for Monitors, Vertical Migration and User Microprogramming
INFless: a native serverless system for low-latency, high-throughput inference
Predictor virtualization
ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, MA, USA, November 12-15, 2000
Tackling ML-based Dynamic Mispredictions using Statically Computed Invariants for Attack Surface Reduction
Input-aware auto-tuning for directive-based GPU programming
Probabilistic Concurrency Testing for Weak Memory Programs
Architectural Support for Dynamic Linking
Improved device driver reliability through hardware verification reuse
Seer: Leveraging Big Data to Navigate the Complexity of Performance Debugging in Cloud Microservices
The Structure and Performance of Interpreters
Tartan: evaluating spatial computation for whole program execution
Architecture-aware optimization targeting multithreaded stream computing
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor
Efficient Address Translation for Architectures with Multiple Page Sizes
SPECTR: Formal Supervisory Control and Coordination for Many-core Systems Resource Management
Optimal task assignment in multithreaded processors: a statistical approach
Sage: practical and scalable ML-driven performance debugging in microservices
Automatically characterizing large scale program behavior
Fusion: An Analytics Object Store Optimized for Query Pushdown
Making Huge Pages Actually Useful
Is process or architecture the solution?
Tree traversal synthesis using domain-specific symbolic compilation
Dagger: efficient and fast RPCs in cloud microservices with near-memory reconfigurable NICs
Taurus: A Holistic Language Runtime System for Coordinating Distributed Managed-Language Applications
Automatically detecting and fixing concurrency bugs in go software systems
Wonderland: A Novel Abstraction-Based Out-Of-Core Graph Processing System
Integer Multiplication and Division on the HP Precision Architecture
Mojim: A Reliable and Highly-Available Non-Volatile Memory System
CoreDet: a compiler and runtime system for deterministic multithreaded execution
Dynamically replicated memory: building reliable systems from nanoscale resistive memories
ProxiML: Building Machine Learning Classifiers for Photonic Quantum Computing
A RISC Architecture for Symbolic Computation
Compiler Optimizations for Improving Data Locality
The benefits of general-purpose on-NIC memory
FACADE: A Compiler and Runtime for (Almost) Object-Bounded Big Data Applications
FAB: building distributed enterprise disk arrays from commodity components
Einsum Trees: An Abstraction for Optimizing the Execution of Tensor Expressions
TGLite: A Lightweight Programming Framework for Continuous-Time Temporal Graph Neural Networks
SpotServe: Serving Generative Large Language Models on Preemptible Instances
Architectural support for SWAR text processing with parallel bit streams: the inductive doubling principle
Asymmetric Memory Fences: Optimizing Both Performance and Implementability