yusuke1997/dblp-id-title huggingface dataset:
A hierarchical edge-stressing algorithm for adaptive image segmentation
An Array-based Laser Radar for UAV detection
Decomposition of speech signals into a periodic and non-periodic part based on sinusoidal models
Delay/slope budgeting for clock buffer cell design
Mismatch effects explained by the spectral model [MOS devices]
Digital Realization of Conductance-Based Adaptive Exponential Integrate-and-Fire Neuron Model
An Eight-Phase 40GHz RTWO in 28nm CMOS with Phase Noise Reduction Via Head and Tail Filtering
Reducing SoC electromagnetic emissions by design
Cascode circuits for low-voltage and low-current applications
Hardware implementation of a secure random number generator
High Performance 16K, 64K, 256K complex points VLSI Systolic FFT Architectures
Algorithmic Level Approximate Computing for Machine Learning Classifiers
Developing AI Agent with Functional Mockup Units for Car Autonomous Navigation
Variability of nanoscale triple gate FinFETs: Prediction and analysis method
A low-noise wide range delta-sigma frequency synthesizer for DTV broadband
High-Gain Observer Compensator for Rotor Resistance Variation On Induction Motor RFOC
Analysis of Spatial Temperature Distribution in ICs
14th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2007, Marrakech, Morocco, December 11-14, 2007
Compact Fully-Differential CMOS Current Driver for Bioimpedance Measurements
Information technology applications of statistical nonlinear dynamics
Simulation of intrinsic bipolar transistor mechanisms for future capacitor-less eDRAM on bulk substrate
Advanced Model and RF-CMOS Design of the Boot-Strapped Inductor
Modelling the frequency sensitivity Kvco of a ring oscillator
A 17.3-20.2 GHz Fully Integrated Linear Balanced Power Amplifier in 130nm BiCMOS Technology
In memory of Tamás Roska (1940-2014)
A mathematical model for time-domain analysis and for parametric optimization of a class of switched capacitor RF power amplifiers
Artificial Neural Network Optimization for FPGA
Chaotic Oscillator Using Coupled Memristive Pairs
An Embodied Approach for Teaching Advanced Electronics in Metaverse Environment
An integrated current sensing circuit with comparator function for a buck DC-DC converter in HV-CMOS
Area efficient and accurate CORDIC processor for motor control drive
Implementation of a reconfigurable architecture
An asymmetric basis function network for approximation of dynamical systems
Utilization of multi-bit flip-flops for clock power reduction
Maximizing bandwidth in CCII for wireless optical applications
An evolutionary algorithm for the testable allocation problem in high-level synthesis
Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001
Neural network based system for testing and diagnostics of analogue integrated circuits
System-on-chip microwave radiometer for thermal remote sensing and its application to the forest fire detection
FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks
A low noise high dynamic range analog front-end ASIC for the AGIPD XFEL detector
Texture boundary detection based on multiple and parallel cellular neural networks
High-speed CMOS switched-current D/A converters for low-power/low-voltage signal processing applications
AGC tuning of interconnected reheat thermal systems with particle swarm optimization
Flexible-length Fast Fourier Transform for COFDM
Mismatch optimization for analog circuits using the DesignAssistant
An Area efficient OTA in Standard 28nm CMOS Technology for Aerospace Applications
Tree-structured product-codebook vector quantization
Synchronous conditioning circuits for piezo- and triboelectric harvesters in CMOS technologies
1-D Convolutional Neural Networks for Touch Modalities Classification
A low-supply SI-cell using threshold control
Adaptive face space models with dynamic neural priors and sparse coding
Comparison of Charge Pumps Configurations Using First-Order Dynamics
Management of Unpredictable Harvested-Energy IoT Devices
A high speed truly IC random number source for smart card microcontrollers
MAC protocol implementation in RF-MIMO WLAN
Stochasticity in Neuromorphic Computing: Evaluating Randomness for Improved Performance
PULP-NN: A Computing Library for Quantized Neural Network inference at the edge on RISC-V Based Parallel Ultra Low Power Clusters
Robust Watermarking System Using Security Enhancement on Content Based Image Segmentation
Digital signal propagation on a wafer-scale smart active programmable interconnect
Electrical modeling of inductive links for high-efficiency energy transmission
Motion estimation and DCT pruning: a combined approach to video coding
Mathifier - Speech recognition of math equations
Neural Network Characteristics-aware Proactive Boost for Heterogeneous Computing to Improve Energy Efficiency
Decomposition of Drain Current In Weak, Moderate, and Strong Inversion Components
Reduction of color variability in color image segmentation
Stabilization of power consumption of the heater of a micromachined silicon gas flow sensor
A new 2-D exact moment recovery with application to fast frequency response estimation
Frequency analysis of linear time-varying systems
Fast signed-digit arithmetic circuits for residue number systems
Dynamics and control system design of an autonomous wind turbine
Differential tuning oscillators with reduced flicker noise upconversion
Design of low cross-talk image transceiver device and controller circuitry
DSM extraction from SPOT5 stereo-pairs
High-throughput FFT architectures using HLS tools
Activity profile driven simultaneous vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs
Linearity Issues in Dual Input Doherty-Outphasing Hybrid Power Amplifier Topology
CNN Inference Costs Estimation on Microcontrollers: the EST Primitive-based Model
A low complexity EPR-IV equalizer for hard disk read channels
Development of a vision based object classification system for an industrial robotic manipulator
On the Design of Scalable Massively Parallel CRC Circuits
Always-on motion detection with application-level error control on a near-threshold approximate computing platform
A VLSI architecture for multiple antenna eigenvalue-based spectrum sensing
Design of a low-power asynchronous elliptic curve cryptography coprocessor
WINNER: a high speed high energy efficient Neural Network implementation for image classification
A template for the construction of efficient checkers with full verification guarantees
Using a parametric filter to average brainstem auditory evoked potentials
A Broadband Frequency Tunable Diamond-Shaped Metamaterial Resonator Using Varactor Diodes
Evaluation of a couple of true random number generators with liberally licensed hardware, firmware, and drivers
New way to design active filters with corrected group delay frequency response through EDE method
Codevelopment of long haul ISDN transceiver and design methodology improves time to market
Impedance characteristics of decoupling capacitors in multi-power distribution systems
Implementation of CRYSTALS-Kyber Post-Quantum Algorithm Using RISC-V Processor
SC quadrature mixer for IF bandpass sampling
Power reduction for multimedia applications through data-reuse memory exploration
A new highly linear CMOS mixer suitable for deep submicron technologies
Novel linearizer for tangent/cotangent converter
Decoder for an enhanced serial generalized bit flipping algorithm
Deadlock detection in conditional asynchronous circuits under mismatched branch selection
A programmable 1.2V to 18V Charge Pump with an internal 500kHz clock in 55nm CMOS
Fast CMOS current driver for IrDA - applications
A 64-way VLIW/SIMD FPGA architecture and design flow
High speed and ultra low voltage CMOS latch
A tree-like amplifier architecture for large gain-bandwidth product
Asynchronous data communication with low power for GALS systems
Implementation aspects of an oversampling D/A converter for DMT-ADSL systems
Hybrid neural model for automatic test pattern generation
Two-dimensional array layout for NMOS 4-phase dynamic logic
Programmable Gain Amplifiers based on High-Linearity MOS Current Dividers
X-Aware verification: A different perspective!
Computing hexagonal Steiner trees using PCx [for VLSI]
Suitable compensation circuits for on-chip interference reduction in neural tripolar recordings
Comparing the steady-state procedures based on epsilon-algorithm and sensitivity analysis
A fast imaging indexing technique in JPEG compressed domain
A Pipelined 12-bit Analog-to-Digital Converter with Continuous On-Chip Digital Correction
8-bit Partial Magnitude Comparator for Spike Generation in the Leaky Integrate-and-Fire Neuron Model using Gate-Diffusion-Input Logic Gates
Accurate reduced RL model for frequency dependent transmission lines
A novel floating-gate multiple-valued signal to binary signal converter
UTBB-FDSOI complementary logic for high quality analog signal processing
A Compact TIA in 22nm FDSOI CMOS for Qubit Readout in Monolithic Quantum Processors
Towards a foundation for FDT-based conformance testing requirements
Experimental pilot project for automating street lighting system in Abu Dhabi using powerline communications
An Improved AI-Based Micro-Single-Event-Latchup (Micro-SEL) and SEL Detection in a COTS System Against R/C/L-Induced (Power Management) Distortions
Self-Parameterized Chaotic Map: A Hardware-efficient Scheme Providing Wide Chaotic Range
Hybrid nanoparticle biomarkers in Near-Field Optical Microscopy
FPGA Implementation of Approximate CORDIC Circuits for Energy Efficient Applications
Injection locked CMOS buffer dedicated to nanomagnetic based voltage controlled oscillator
Dead-zone free Memristor-based Phase-Frequency Detector for Duty-Cycled Transceivers
Efficient and fast SOP-based inpainting for neurological signals in resource limited systems
IC design automation from circuit level optimization to retargetable layout
Laygen - An evolutionary approach to automatic analog IC layout generation
A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS
A Hybrid Method for the Recognition of Acceptor Splice Sites
Chaotic pulse-train separation and multiplex communication
Power-aware dominating set calculations in mobile ad hoc wireless networks with unidirectional links
A high dynamic range wideband CMOS phase angle detector for bioimpedance spectroscopy
Modulated waveform measurement and engineering system
Low power sensor node processor architecture
High-speed GaAs SCFL digital test structures
NAROUTO: An open-source framework for supporting architecture-level exploration at heterogeneous FPGAS
A 14-bit 12 μV/LSB resolution A/D converter for sensors using only digital circuit with low-pass filter effect
A combined 4-bit quadrature digital to analog converter/mixer for millimeter-wave applications
Heterogeneous implementation of a rake receiver for DS-CDMA communication systems
Multirate structures for very fast narrow-band digital filtering
Incremental-ΣΔ-ADCs with dynamic conversion length adaption
Bit-error-rate analysis and mixed signal triple modular redundancy methods for data converters
Effects of analogue ACS implementation errors on the modified feedback decoding algorithm
Advances in low-voltage ultra-low-power analog circuit design
Algorithms for Compositions of Arithmetic Transforms and Their Extensions
A post-layout optimization method with automatic device type selection for BiCMOS analog circuits
Internal Vth cancellation scheme for RF to DC rectifiers used in RF energy harvesting
Multi-domain simulation as a foundation for the engineering of smart systems: Challenges and the SMAC vision
A high speed BiCMOS tristate buffer circuit
Bottom-up visual attention model based on FPGA
An analytical current, delay, and power model for the submicron CMOS inverter
Acquiring regions of interest from diffuse optical tomography measurements
On the output events in concurrent error detection schemes
Scalable mobility management in wireless ad hoc sensor systems
Holographic 3D disks
Formal verification of digital circuits by 3-valued simulation
DVFS as a Security Failure of TrustZone-enabled Heterogeneous SoC
A new mobility model for pocket implanted quarter micron n-MOSFETs and below
A CMOS voltage reference for ultra low-voltage applications
A NoC-based multi-{soft}core with 16 cores
An overview of the current steering logic (CSL): from the gate to the applications
VB-DVFS: A new algorithm for power efficiency of CMP with GALS
Nanotips characterization, modeling and simulation
A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator
Improving Software-based Techniques for Soft Error Mitigation in OoO Superscalar Processors
Influence of the real power modulation provided by a shunt compensator on damping power swings
Exploring RSA Performance up to 4096-bit for Fast Security Processing on a Flexible Instruction Set Architecture Processor
Analysis of bandpass Sigma-Delta conversion in OFDM systems
Analytical modeling of transconductance in organic thin-film transistors
An effective output-oriented algorithm for low power multipartition architecture
Improved RF CMOS active inductor with high self resonant frequency
Learning and real-time classification of hand-written digits with spiking neural networks
Approximate Sum of Absolute Transformed Differences Hardware Accelerator
Machine Learning-Based Local Sensitivity Analysis of Integrated Circuits to Process Variations
Single-inductor four-phase power-clock generator for positive-feedback adiabatic logic gates
Hardware/software codesign of an avionics protocol interface system
A compensation technique for SAR ADC comparator noise
Gross-coupled LMS for quadratic constrained filter design
Neural network arbitration for edge detection
A Low-Voltage Integrated Current-Mode Boost Converter for Portable Power Supply
Separation of convolutive mixtures of cyclo-stationary signals using a non-unitary block-diagonalization algorithm
Fast characterization of RTL power macromodels
Power optimized packet buffering in a protocol processor
Lowering the Output Resistance by Quadrature Phasing in Switched-Capacitor Power Converters
Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays
Pixel circuit design for an accumulation mode BDJ APS in a 0.18µm CMOS technology
Enhancement of the semisymbolic analysis precision using the variable-length arithmetic
Improving design efficiency by providing models for simulation of parasitic effects of passive devices
Simulation-based sequential equivalence checking of RTL VHDL
Optimized resource allocation strategy for a single-cell downlink AMC-OFDMA systems
256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V
A simplified approach for designing secure Random Number Generators in HW
Strategic placement of reliable routers for the optimization of dependable dynamic NoC
No-Handshake Asynchronous Survivor Memory Unit for a Viterbi Decoder
Design of analog and mixed circuits for resonator's Q-factor measurement
Fault-Tolerant Core Mapping for NoC based architectures with improved Performance and Energy Efficiency
A Fully-Integrated 40 nm CMOS 58.1% PAE Push-Pull Class-E/Fodd Power Amplifier for NB-IoT Applications
Comparison of static logic styles for low-voltage digital design
An approach to offline Arabic character recognition using neural networks
FPGA Implementations of Espresso Stream Cipher
Tracking method for the hybrid modulation to minimize neutral-point voltage oscillations in the three-level converter
Efficient FPGA implementation of probabilistic gallager B LDPC decoder
Assessment of seven reconstruction methods for contemporary compressive sensing
Analysis of Opamp Non-Idealities in Quadrature Bandpass Sigma-Delta Modulators
Fast block-matching motion estimation based on an improved cross-diamond search algorithm
A Masking Model of HVS for Image Watermaking in the DCT Domain
Design and linearity analysis of a M-2M DAC for very low supply voltage
Power and Cross-Section Optimization for an FPGA-Based Cosmic Radiation Sensor
Rapid Deployment of Domain-specific Hyperspectral Image Processors with Application to Autonomous Driving
Ling adders in CMOS standard cell technologies
Experimental extraction of point defects parameters needed for 2-D process modeling using reverse modeling
Design of low-power on-line reconfigurable datapaths using self-checking circuits
Nanorobotic challenges in biomedical applications, design and control
Design an infrared wireless optical mouse system and a dual-band infrared receiver
Implementation of large-integer hardware multiplier in Xilinx FPGA
Multi-application electrical stimulator architecture dedicated to waveform control by electrode-tissue impedance spectra monitoring
Low Power SPI Design Based on Relative Timing Techniques
Optimization process of power distribution for a frequency multiplexing DMT transmission
A double polarity CMOS peak-and-hold circuit for satellite radiation detection systems
LSB-first SAR ADC with bit-repeating for reduced energy consumption
Modeling of a 4×10 Gbps all-optical clock extraction system
Block subspace updating algorithms for tracking directions of coherent signals in SDMA mobile systems
Efficient symbolic analysis of analog integrated circuits using determinant decision diagrams
Design and comparison of class-C and class-D power amplifiers for remotely powered systems
Rapid layout synthesis for analog VLSI
Improved Low Power Full Scan BIST
VLSI implementation and performance of turbo decoding stopping criteria
Jitter effects in continuous-time ΣΔ modulators with delayed return-to-zero feedback
MCDM method based on improved fuzzy decision map
A Dedicated Hardware Implementation for Biometric Recognition based on Finger Veins
A 1 V second order sigma-delta modulator
New Wireless Sensors Networks: The Art of Integration
Analysis of linear system response to wide band signals with applications to filters
Robust PWVD for the analysis of polynomial FM signals in non-Gaussian noise
Analysis and Performance Comparison of a Cascade 3-1 Delta-Sigma Topology
Design of Fully-Integrated Self-Powered FM Transmitter Using On-Chip Photodiodes in 65-nm CMOS
A new scalable non-feedback ΔΣ digital-to-analog converter
Modelling and performance analysis of DOA estimation in adaptive signal processing arrays
High throughput systolic memory architecture using three directional dataflows
A 10-bit, 1.8-GS/s Time-Interleaved Pipeline ADC
A new CMOS current mode fast folding amplifier
Application specific image processor for the extension of the dynamic range of images with multiple resolutions
New design approach of Front-End Electronics for high-accuracy time measurement systems
Ultra low-power low-noise transimpedance amplifier for MEMS-based reference oscillators
A new biometric authentication system using heart sounds based on wavelet packet features
Asynchronous high throughput NoC under high process variation
Model predictive control of shell benchmark process
Lookupx: Next-Generation Quantization and Lookup Techniques for Empowering Performance and Energy Efficiency
Neural system for military target detection
Auxiliary Pulse-Extender and Current-Attenuator Circuits for Flexible Interaction with Memristive Crossbars in SNNs
Frequency lowering processing for listeners with significant hearing loss
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity
SPICE simulation of ferrite core losses and hot spot temperature estimation
Designing CT ΣΔ modulators with shaped feedback waveforms using www.sigma-delta.de
An Efficient NLMS-based VLSI Architecture for Robust FECG Extraction and FHR Processing
On algorithm for phoneme speech recognition using nonlinear signal decomposition
Performance testing of a concatenated RS-convolutional encoding scheme in AWGN and impulse noise channels
5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Surfing the Waves of Science and Technology, Lisbon, Portugal, September 7-10, 1998
Electroforming-free BiFeO3 switches for neuromorphic computing: Spike-timing dependent plasticity (STDP) and cycle-number dependent plasticity (CNDP)
Efficient implementation of parallel decision feedback decoders for broadband applications
A 2.64GHz wide range low power DLL-based frequency multiplier with CML circuits using adaptive body bias
Broadly tunable frequency division duplex transceiver: Theory and operation
Constrained piecewise polinomial approximation for hardware implementation of elementary functions
Design of Improved Rail-to-Rail Low-Distortion and Low-Stress Switches in Advanced CMOS Technologies
Modelling TrenchMOSFETs in SPICE
1.05V 10.2mW WCDMA analog baseband in 65nm digital CMOS technology
Multithreading Libraries Impact on the Soft Error Reliability of Real-Time Applications
Scan-path based testing of systems on a chip
Adaptive power reconfigurability for preventing excessive power dissipation in wireless receivers
Adaptive filtering of cyclostationary interference from speech
Convergence in reconfigurable embedded systems
Analysis of neural networks for face recognition systems with feature extraction to develop an eye localization based method
A scalable microradio receiver used in radiation pattern measurement technology
Power Optimization of Pipelined ADCs with High-Order Digital Gain Calibration
Varactor diodeless harmonic VCOs for GHz-range applications
A Generic IP Core of the Identical Forward and Inverse 12/36-Point MDCT Architecture and an Architectural Model Simulation Toolbox
Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware Architectures for Robust EEG Signal Artifacts Elimination
Dynamic Structural and Computational Resource Allocation for Self-Organizing Architectures
Extended event-driven modeling of a ΣΔ-fractional-N PLL including non-ideal effects
A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS
A novel highly linear CMOS buffer
Novel FIR approximations of IIR differentiators with applications to image edge detection
High sensitivity potentiostat system for sub-micron bio-sensors impedance measurements
Secured wireless ad-hoc network administration scheme
High Density GC-eDRAM Design in 16nm FinFET
Cell-aware MBFF utilization for clock power reduction
A switched-opamp with fast common mode feedback
Second-order TDTL with initialization process
CEMS-PG: A parametrized algorithm for balanced partitioning and wakeup of power gated circuits
Yield optimization of spintronic memristor-based memory arrays
Robust Readout Circuit with Leakage Current Cancellation Technique for Stretchable Touch Sensors
A 0.35-μm CMOS Mixer for 3.1-4.8 GHz UWB MB-OFDM Receivers
Evaluating and comparing simulation verification vs. formal verification approach on block level design
50 MHz high-speed and 5 W low-power real-time programmable video multi processor (VMP) for MPEG-2 MP@ML on 0.6 μm TLM CMOS technology
Analysis of parasitic effects of small-outline packages for high-frequency integrated circuits
VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits
Method for speeding the micropower CMOS operational amplifiers with dual-input-stages
An area-saving 3-dimensional decoder structure for ROMs
CMOS-compatible structure for voltage-mode multiple-valued logic circuits
Over-voltage on inverter fed induction motor drive system
A rail-to-rail-input chopper instrumentation amplifier in 28nm CMOS
Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores
System level simulation for TD-SCDMA using smart antennas
A jitter-resilient sampling technique for high-resolution ADCs in wideband RF receivers
10 Gb/s Line Driver in 65 nm CMOS Technology for Radiation Environments
Current conveyor based amplifier and adaptive buffer for use in an analog frontend
AEDS: a novel technique for detecting DNA bands in autoradiograph images
A Programmable Complex FIR Filter with Integrated MEMS Filter for Front-end Charge Sampling Receiver
A multi-tank LC-oscillator [microwave oscillator example]
Comparative efficiency analysis of dynamically supplied power amplifiers (PA)
Analytical probability of error in TH-PPM and TH-PAM ultra wideband systems