yusuke1997/dblp-id-title huggingface dataset:
Transaction level modeling of an adaptive multi-standard and multi-application radio communication system
A Graphical Tool for System-Level Modeling and Simulation with SystemC
A model-driven methodology for the development of SystemC executable environments
Stream Programming for FPGAs
Efficient approximately-timed performance modeling for architectural exploration of MPSoCs
Modeling Embedded Software Platforms with a UML Profile
Instruction-Level Modeling and Evaluation of a Cache-Less Grid of Processing Cells
Towards an ESL Framework for Timing and Power Aware Rapid Prototyping of HW/SW Systems
Automotive System Design with Specification and Verification of Uncertainties
Time in SCCharts
Efficient Architecture Evaluation Using Functional Mapping
On Actors and Objects - OOP in System Level Design
Model-driven development of embedded system on heterogeneous platforms
Fault analysis in analog circuits through language manipulation and abstraction
Behavioural modelling of a power amplifier in VHDL-AMS
Fast Bit-Accurate C++ Datatypes For Functional System Verification and Synthesis
A case study on message-based discrete event simulation for Transaction Level Modeling
UML2 Profile for Modeling Controlled Data Parallel Applications
Modeling of Communication Infrastructure for Design-Space Exploration
Experimenting Object-Oriented System-Level Design in the ATM domain
Towards Efficient Privacy-Preserving Federated Learning on Edge with Reconfigurable FPGA
Fine-grain adaptation for real time embedded systems using UML/MARTE profile
UML - The Emerging Hardware Description Language?
If SystemVerilog is so good, why do we need the UVM? Sharing responsibilities between libraries and the core language
Satellite Payload Design for Optimized Thermal Management Using a Distributed Processor System
Formal Modelling of Burst-Mode Specifications in a Distributed Environment
SystemVerilog: The new standard
Symbolic Simulation of SystemC AMS Without Yet Another Compiler
Model Based Testing and Refinement in MDA Based Developent
Repetitive Allocation Modelling with MARTE
Mapping Actor-Oriented Models to TLM Architectures
Compositional Proof Rules for Hierarchical Timed Automata
Introducing CPU load Analysis from AADL Models for ROS applications : a use case
Local application of simulation directed for Exhaustive Coverage of Schedulings of SystemC specifications
Leveraging the Benefits of Information Flow Tracking for Detecting Hardware Design Flaws
Language and Hardware Acceleration Backend for Graph Processing
Devices modelling in SystemC based on behaviour separation
Symbolic simulation of dataflow synchronous programs with timers
Model driven engineering at work
Synchronized Shared Memory and Procedural Abstraction: Towards a Formal Semantics of Blech
QoC-oriented efficient schedule synthesis for mixed-criticality cyber-physical systems
Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques
Connecting SystemC-AMS Models with OSCI TLM 2.0 Models using Temporal Decoupling
Transaction-level Functional Mockup Units for Cyber-Physical Virtual Platforms
UML Profile for Modeling Product Observation
Modeling power consumption at system-level for design of power integrity-aware AMS-circuits
Design of Communication Infrastructures for Reconfigurable Systems
QRML: A Component Language and Toolset for Quality and Resource Management
A Contract-based Formalism for the Specification of Heterogeneous Systems (invited)
Dynamic Power Management of an AMBA-based Platform in SystemC
Forum for Specification and Design Languages, FDL 2020, Kiel, Germany, September 15-17, 2020
Extensions to the UML profile for MARTE for distributed embedded systems
Proof-based design of a microelectronic architecture for MPEG-2 bit-rate measurement
Using feature models to automate model transformations
Designing reliable cyber-physical systems overview associated to the special session at FDL'16
2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016
Model-driven design for the development of multi-platform smartphone applications
Platform Design for Privacy-Preserving Federated Learning using Homomorphic Encryption : Wild-and-Crazy-Idea Paper
Mapping Interface Method Calls over OCP Buses
Using Rewriting-Logic Notation for Funcional Verification in Data-Stream Based Reconfigurable Computing
Practical Case Example of Inertial MEMS Modeling with VHDL-AMS
Multi-objective preference-free exact design space exploration of static DSP on multicore platforms
Towards Object-Oriented Modeling in SCCharts
Why SystemVeriog?
Automatic Parallelization of Embedded Software via Hierarchical Process Network Transformations
A Minimal RISC-V Vector Processor for Embedded Systems
Blech, Imperative Synchronous Programming!
Modeling and simulation of secure wireless sensor network
Exploring Models of Computation through Static Analysis
2018 Forum on Specification & Design Languages, FDL 2018, Garching, Germany, September 10-12, 2018
ISIS: Runtime verification of TLM platforms
Formal plausibility checks for environment constraints
A New Method for Modeling and Analysis of Accuracy and Tolerances in Mixed-Signal Systems
Using Symbolic Simulation for Bounded Property Checking
A New Time Extension to phi-Calculus based on Time Consuming Transition Semantics
DEVS2VHDL: Automatic transformation of XML-specified DEVS Model of Computation into synthesizable VHDL code
SystemVerilog: Interface Based Design
UML-based Automatic Code Generation for Hybrid CPU-FPGA
Description Languages and Tools for the Behavioural Simulation of SD Modulators: a Comparative Survey
Towards a toolchain for assertion-driven test sequence generation
VHDL & VHDL-AMS Modelling and Simulation of a CMOS Imager IP
Towards Compilation of Streaming Programs into FPGA Hardware
Mining Metadata for Composability of IPs from SystemC IP Library
OCP TLM for Architectural Modelling
Industrial Partners Expectations from the ICODES Methodology
C-based System Development of Asynchronous Distributed Systems
Flexible runtime verification based on logical clock constraints
Extended framework for system simulation with affine arithmetic
Example-driven interconnect synthesis for heterogeneous coarse-grain reconfigurable logic
MARTE-based Design of a Multimedia Application and Formal Analysis
C-Based Hardware Design for Wireless Applications
Bottom-up Verification Methodology for CMOS Photonic Linear Heterogeneous System
Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC Models
2011 Forum on Specification & Design Languages, FDL 2011, Oldenburg, Germany, September 13-15, 2011
A top-down approach for the design of low-power microsensor nodes for wireless sensor network
Implementation of a SystemC based Environment
An Abstract Communication Bus Model for Performance Estimation in SoCs with SystemC (short paper)
A SystemC-based Framework for Modeling and Simulation of Networked Embedded Systems
Forum on specification and Design Languages, FDL 2005, September 27-30, 2005, Lausanne, Switzerland, Proceedings
Time Modeling in MARTE
Actor fission transformations for executing dataflow programs on manycores
Semi-formal representation of requirements for automotive solutions using sysML
Using SystemC for an Extended MATLAB/Simulink Verification Flow
Automatic Generation of a Verification Platform
A Requirements-Driven Simulation Framework for Communication Infrastructures Design
An extensible infrastructure for modeling and time analysis of predictable embedded systems
A metamodel and semantics for transaction level modeling
Integrating virtual platforms into a heterogeneous MoC-based modeling framework
Algorithmic Test Generation - a New Approach to testbench Creation
CARES, a framework for CPS simulation : application to autonomous underwater vehicle navigation function
RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems
UML to XML-Schema Transformation: a Case Study in Managing Alternative Model Transformations in MDA
Preserving Functional Correctness of Cyber-Physical System Controllers: From Model to Code
Towards consistency checking between HDL and UPF descriptions
An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System
Design automation model for application-specific processors on reconfigurable fabric
An integrated simulation framework for invasive computing
Exact Synthesis of LTL Properties from Traces
UML 2.0 Interactions with OCL/RT Constraints
A Model-driven Approach to Configuration of TTA-based Protocol Processing Platforms
Split of composite components for distributed applications
Design and Power Analysis in SysteC of an I2C Bus Driver
2019 Forum for Specification and Design Languages, FDL 2019, Southampton, United Kingdom, September 2-4, 2019
Proceedings of the 2014 Forum on Specification and Design Languages, FDL 2014, Munich, Germany, October 14-16, 2014
Formal heterogeneous system modeling with SystemC
Does asynchronous technology bring robustness in synchronous circuit monitoring?
Event-driven (RN) modeling for AMS circuits
Bringing C++ productivity to VHDL world: From language definition to a case study
Design and Modelling of an I2C Bus Controller
Models, Methods, and Tools for Complex Chip Design - Selected Contributions from FDL 2012
Software Real-time Resource Modeling
Verification of heterogeneous systems: Theory and industrial experiences
Improving Parallelism in System Level Models by Assessing PDES Performance
Impact simulation of changes to development processes: An ESL case study
3D Visualization of Symbolic Execution Traces
Configurable Load Emulation Using FPGA and Power Amplifiers for Automotive Power ICs
Towards Abstract Analysis Techniques for Range Based System Simulations
Mixed Signal Simulation with SystemC and Saber
Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification
Building heterogeneous plaftorm simulators in C++
Forum on specification and Design Languages, FDL 2007, September 18-20, 2007, Barcelona, Spain, Proceedings
Polynomial Metamodel-Based Fast Optimization of Nanoscale PLL Components
Modeling CHP descriptions in Labeled Transitions Systems for an efficient formal validation of asynchronous circuit specifications
Languages and Formalisms to Enable EDA Techniques in the Context of Industry 4.0
WIP on a Coordination Language to Automate the Generation of Co-Simulations
A VHDL-AMS based Time-Domain Skin Depth Model
Using event-B and Modelica to evaluate thermal management strategies in many core systems
Non-Intrusive High-level SystemC Debugging
Combining Formal Refinement and Model Checking for Real-Time Systems Verification
Analysis of sense finger dynamics for accurate ΣΔ MEMS accelerometer modelling in VHDL-AMS
Symbolic Simulation of Dataflow Synchronous Programs with Timers
Functional Abstractions for UML Activity Diagrams
SOAP Based Distributed Simulation Environment for SoC Design
Application Driven Methodology for Development of Communicating Systems
Jitter Tolerance Analysis of Clock and Data Recovery Circuits
A Generic Simulation Framework for Multiprocessor Architectures
A Framework for Modeling and Concurrently Simulating Mechanical and Electrical Faults in Verilog-AMS
A Seamless Simulink Based System Desing Flow for Automotive Applications
VEST - An Intelligent Tool for Timing SoCs Verification Using UML Timing Diagrams
Heterogeneous and Non-linear Modeling in SystemC-AMS
Automated synthesis of cyber-physical systems from joint controller/architecture specifications
Minimum energy point of sub-threshold operated pass-transistor circuits
SystemC-based Simulation of the MICAS Architecture
Modelling of transient noise sources with VHDL-AMS and normative spectral interpretation
Performance Modeling and Analysis of Exposed Datapath Architectures
Statistical Modeling with VHDL-AMS
An Extension to VHDL-AMS for AMS Systems with Partial Differential Equations
Protocol Bus Modeling using inheritance with TLM2.0
A Platform for Requirement Based Formal Specification
Grid Based Fast Falsification For Bounded Property Checking
C-based Design of a Flexible Wrapper for Tiled Networks On Chip
TLM POWER3: Power estimation methodology for SystemC TLM 2.0
On Consistency and Completeness of Property-Sets
Semi-Symbollic Simulation of Nonlinear Systems
Modeling Technique for Simulation Time Speed-up of Performance Computation in Transaction Level Models
ProtoLens: Dynamic Transaction Visualization in Virtual Prototypes
Real-time system modeling with ACCORD/UML methodology: Illustration through an automotive case study
A functional language for describing reversible logic
Leveraging Model-Driven Architecture for Efficient Custom Instruction Utilization in Embedded Systems in C and Rust
A formal verification framework for Bluespec System Verilog
How Different are Esterel and SystemC?
Feature based state space coverage of analog circuits
Exploration of embedded memories in SoCs using SystemC-based functional performance models
Efficient Refinement Strategy Exploiting Component Properties in a CEGAR Process
A Tripartite System Level Design Approach for Design Space Exploration
A generic execution model for efficient performance evaluation of system architectures at transaction level
Integrated model-based approach and test framework for embedded systems
Verifying consistency between activity diagrams and their corresponding OCL contracts
On-line Monitoring of Properties Built on Regular Expressions
Towards a Conceptual Framework for UML to Hardware Description Language Mappings
APDL: A Processor Description Language For Design Space Exploration of Embedded Processors
Modelling Heterogeneous Embedded Systems in DFCarts
Modeling Switched Capacitor Sigma Delta Modulator Nonidealities in SystemC-AMS
ESL power and performance estimation for heterogeneous MPSOCS using SystemC
Application Workload and SystemC Platform Modeling for Performance Evaluation
SystemC-based power simulation of wireless sensor networks
A machine-readable specification of analog circuits for integration into a validation flow
Evaluating Debugging Algorithms from a Qualitative Perspective
Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study
Using Sequential Equations to Improve Efficiency and Robustness
Rapid prototyping of a DVB-SH turbo decoder using high-level-synthesis
Bifröst: Creating Hardware With Building Blocks
The SysML profile for embedded system modelling
Formal Specification of a 40GBit/s Sonet/SDH ASIC
Systemc-AMS model of a dynamic large-scale satellite-based AIS-like network
Extension of the SystemC Kernel for Simulation Coverage
Forum on specification and Design Languages, FDL 2009, September 22-24, 2009, Sophia Antipolis, France, Proceedings
Predictability in Real-time System Development (1) Semantics Support from Development Languages
Bridging algorithm and ESL design: Matlab/Simulink model transformation and validation
TLM POWER3: Power Estimation Methodology for SystemC TLM 2.0
Cross-domain Analog Fault Injection for Designing Robust Smart Systems
Designing for dynamic partially reconfigurable FPGAs with SystemC and OSSS
Telecommunication Application Modelling with Multi Writer Multi Reader Channels: a Case Study
Hybrid dynamical systems for memristor modelling an approach avoiding the terminal-state problem
Hierarchical synthesis of high-speed CMOS photoreceiver front-ends using a multi-domain behavioural description language
SystemC-A Modelling of Mixed-Technology Systems with Distributed Behaviour
Main Results of PROSYD - Methodologies and Tools for Writing Reusable PSL Assertions
A concept for design of embedded systems at semantic level
TLM-Based Verification of a Combined Switching Networks-on-Chip Router
Temporal independence validation of an IEC-61508 compliant mixed-criticality system based on multicore partitioning
HEAVEN: A Framework for the Refinement of Heterogeneous Systems
Modeling of the ultrasonic nonlinear propagation with VHDL-AMS
Refinement of Hybrid Systems from Formal Models to Design Languages
Deterministic Actors
SystemC Architectural Transaction Level Modelling for Large NoCs
Checkpoint and Restore for SystemC models
DSLs for Model Driven Development of Secure Interoperable Automation Systems with EdgeX Foundry
Cascading metamodels from different sources for performance analysis of a power module
Distributed, loosely-synchronized systemC/TLM simulations of many-processor platforms
BDD Meets SAT: Binary Hybrid Diagrams for Efficient Generation of Multiple Solutions
A methodology for inserting clock-management strategies in transaction-level models of systemon- chips
Randomized Simulation of Hybrid Systems For Circuit Validation
Linking GENESYS application architecture modelling with platform performance simulation
Modeling Time-Triggered Architecture Based Safety-Critical Embedded Systems Using SystemC
Formalizing TLM with Communicating State Machines
Forum on specification and Design Languages, FDL 2006, September 19-22, 2006, Darmstadt, Germany, Proceedings
Selective abstraction and stochastic methods for scalable power modelling of heterogeneous systems
Model-based progressive design and verification of an integrated CMOS magnetic sensor for automotive applications
System Description Aspects as Syntactic Sugar
Embed Scripting inside SystemC
Modeling of CSP, KPN and SR Systems with SystemC
SmaCoNat: Smart Contracts in Natural Language
A novel approach to mixed-domain behavioral modeling of ferromagnetic hysteresis in VHDL-AMS
Minimal MPI as programming interface for multicore System-on-Chips
The AutoSUN Verification Environment
SystemC Coding Guideline for Faster Out-of-order Parallel Discrete Event Simulation
Automatic Integration of HDL IPs in Simulink Using FMI and S-Function Interfaces
Efficient Automatic Visualization of SystemC Designs
Specification of Adaptive HW/SW Systems in SystemC
Synthesis of Glue Logic, Transactors, Multiplexors and Serialisors from Protocol Specifications
High Level Self-adjusted Models and VHDL-AMS; Application for a freguency synthesizer modelling
A UML Approach for Modeling the Components of a Test System for Integrated Circuits
UML Specifications Towards a Codesign Environment
Forum on specification and Design Languages, FDL 2008, September 23-25, 2008, Stuttgart, Germany, Proceedings
Fast and unified SystemC AMS - HDL simulation
Heterogeneous computing with accelerators: an overview with examples
Machine Learning in Compilers: Past, Present and Future
Assisting refinement in System-on-Chip design
Multi-level modeling of wireless embedded systems
Advanced features for industry-level logging and tracing of C-based designs
AMS Extensions for Timed/Untimed System-Level Design Language
Simulation Acceleration of Image Filtering on CMOS Vision Chips Using Many-Core Processors
Monte Carlo Simulation Using VHDL-AMS
MDA for SoC Design, Intensive Signal Processing Experiment
Deadlock Analysis in Statecharts
The application of Aspectual Feature Module in the development and verification of SystemC models
Hybrid dynamic data race detection in systemC
Configurable load emulation using FPGA and power amplifiers for automotive power ICs
Incorporating SystemC in Analog/Mixed-Signal Design Flow
On Hardware Description in ECL
Designing Highly Parameterized Hardware using xHdl
Platform based design
A Metamodeling based Framework for Architectural Modeling and Simulator Generation
Sequential Behavioral Modeling for Scalable IoT Devices and Systems
2017 Forum on Specification and Design Languages, FDL 2017, Verona, Italy, September 18-20, 2017
Regular Hardware Architecture Modeling with UML2
Abstract modelling and estimation of a high performance Tobey's PGA
Tiny-Pi: A Novel Formal Method for Specification, Analysis and Verification of Dynamic Partial Reconfiguration Processes
EmCodeSyn: A visual framework for multi-rate data flow specifications and code synthesis for embedded applications
A VHDL-AMS library of hierarchical optoelectronic device models
Temporal decoupling with error-bounded predictive quantum control
Refining Power Consumption Estimations in the Component-based AADL Design Flow
ForMAt: Formal Verification of Scalable Multiply and Accumulate Units
Optimal component selection for energy-efficient systems
Design of experiments for effective pre-silicon verification of automotive electronics
A Comparison of Virtual Platform Simulation Solutions for Timing Prediction of Small RISC-V Based SoCs
Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach
Modeling the analog circuit design feature variety
Efficient Transient Simulation of Lossy Coupled Interconnects in Digital Communication Applications
SC2 StateCharts to SystemC: Automatic Executable Models Generation
Combining analytical and simulation-based design space exploration for time-critical systems
SystemC Based Design Space Exploration for Power Aware Smart Cards
Multi-level Modeling of Hot Carrier Injection for Reliability
Evalution/Testing of Compact Device Model Implementation
Building product-lines of mixed-criticality systems
Efficient realization of control logic in reversible circuits
Time Measurement and Control Blocks for Bare-Metal C++ Applications
Application of SystemC/SystemC-AMS for the Specification of Complex Wired Telecomunication Systems
Model Based Design of Distributed Embedded Cyber Physical Systems
A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library
Aspect Orientation in System Level Design
A Dynamic Load Balancing Method for Parallel Simulation of Accuracy Adaptive TLMs
Compositional specification of functionality and timing of manufacturing systems
Verification of unit and dimensional consistencies in polychronous specifications
Modeling communication and circuit's behavior
Languages for Embedded Systems and their Applications - Selected Contributions on Specification, Design, and Verification from FDL'08, September 23-25, 2008, Stuttgart, Germany
System Behaviour Capture: from UML to SystemC
Using C# Attributes to Describe Hardware Artefacts within Kiwi
VHDL-AMS code gneration from UML structural representations
A unified platform for design and verification of mixed-signal systems based on SystemC AMS
Cyber-Physical System for Industrial Control Automation Based on the Holonic Approach and the IEC 61499 Standard
Analysis of Non-functional Properties of MPSoC Designs
Automatic refinement checking for formal system models
Combination of Assertion and HSAT Methods For Automated Test Vectors Generation
IP-XACT for smart systems design: extensions for the integration of functional and extra-functional models
A Unified Approach to Code Generation from Behavioral Diagrams
PSL-based online monitoring of digital systems
Design space exploration for cyber physical system design using constraint solving
A Container-based Design Methodology for Robotic Applications on Kubernetes Edge-Cloud architectures
A Quantitative Guide to Navigate Speed/Accuracy Tradeoffs in System Level Design of RISC-V Processor Grids
Mapping UML Descriptions to the Raven Input Language
IP Library For Temporal SystemC Assertions
Creating Virtual Prototypes of Complex Micro-Electro-Mechanical Transducers using Reduced-Order Modelling Methods and VHDL-AMS
Using UML-B and U2B for formal refinement of digital components1
From UML statecharts to FPGA - the HiCoS approach
Assertion-based verification of signal processing systems with affine arithmetic
Bridging the Gap Between SysML and Design Space Exploration
Functional Virtual Prototyping Design Flow and VHDL-AMS
GBLD: A Formal Model for Layout Description and Generation
Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach
Mixed simulation kernels for high performance virtual platforms
Virtual Prototyping in SystemC AMS for Validation of Tight Sensor/Firmware Interaction in Smart Sensors
Evaluation of SystemC-AMS modeling capabilities of RF front-end non-linearities: satellite receiver case study
The Challenge of Agriculture: Increase the Productivity in a Sustainable Way
System-Level Design Space Exploration for Matrix Multiplication using Compute-In-Memory Unit
Mapping SysML to SystemC