yusuke1997/dblp-id-title huggingface dataset:
Atomic layer deposited Hf0.5Zr0.5O2-based flexible RRAM
High-Level Synthesis: On the path to ESL design
Lagrangian relaxation based pin assignment and Through-Silicon Via planning for 3-D SoCs
Calibration for split capacitor DAC in SAR ADC
A 1.2-V 7.2-μw ECG AFE with continuous time self-calibration filters
Study and implementation of cluster hierarchical memory system of multicore cryptographic processor
Design of High-Speed Drivers for 56Gb/s PAM4 Optical Communications in CMOS
General Vector Instruction Extension for GF(2 m ) Polynomial Operation in Post-quantum Cryptography
Design and automatic generation of area-efficient ring oscillator based addressable test chips
20, 000-fps Visual Motion Magnification on Pixel-parallel Vision Chip
A timing-perspective study on the wire model in placement
A study of frequency synthesizer for AT-DMB applications
A 18 mW 12 bit 50 MS/s SHA-less pipelined ADC
A Coarse-to-fine Classification for Motion Blur Kernel Size Estimation with Cascaded Neural Networks
Modeling and analysis of injection factor based on injection-locked LC oscillator
Design Techniques of Gate Driver for SiC MOSFET's Applications
A LTE digital mixer with 25% duty quadrature 4-phase clocks
Testing and trimming methods of high-resolution and large swing for ADC based on ATE
Iterative optimization algorithm for sound localization
A 300GHz CMOS Transceiver Targeting 6G
FPGA Implementation of High Critical Sparsity Orthogonal Matching Pursuit Algorithm for Compressed Sensing Reconstruction
Electrochemical biosensor based on modified graphene oxide for tuberculosis diagnosis
An Efficient Hardware Architecture for Epileptic Seizure Detection using EEG Signals based on 1D-CNN
A Self-regulating Dynamic Reference Sensing Scheme with Balanced Trade-Off between Read Disturbance and Sensing Margin
True random number generator based on switching probability of volatile GeXSe1-X ovonic threshold switching selectors
A new topology for fully differential amplifiers that enhances their tolerance to external disturbances
Parallel Global Placement on CPU via Parallel Reduction
A routing algorithm for Network-on-Chip with self-similar traffic
Logic Synthesis for Emerging Technologies
A subthreshold MOSFET bandgap reference with ultra-low power supply voltage
A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain
Configurable Hybrid Output Driver for GPIO with Wide Supply Voltage Range of 1.05V-3.70V
A 16-bit low-power double-sampled delta sigma modulator for audio applications
A pn-Coupled Superjunction IGBT for High Switching Speed
Stochastic computing implementation of trigonometric and hyperbolic functions
A thermal-aware distribution method of TSV in 3D IC
Design of a monolithic low-power micro-sensor signal processing system
Device-Architecture Co-optimization for RRAM-based In-memory Computing
A 12-bit 800MS/s pipelined A/D converter
Design and Implement of Median Filter toward Remote Sensing Images Based on FPGA
A low noise fully-integrated readout electronic with pile-up rejector for particle detector
Comparison of decoupling resistors and capacitors for increasing the single event upset resistance of SRAM cells
Flexible and Adaptive Path Splitting of Simplified Successive Cancellation List Polar Decoding
Noncontact Remote Doping for High-performance Two-dimensional Electronics
A 10-bit pipelined ADC with improved S/H circuit for CMOS image sensor
A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals
A power efficient current-mode differential driver for FPGAs
A High Gain and Wide Bandwidth Dual-Power CMOS Op-amp for High-Speed ADCs Application
Physics based compact model of GaN HEMT with an efficient parameter extraction flow
Realization of Nanoscale Neuromorphic Memristor Array with Low Power Consumption
Architecture considerations of LTE/WCDMA wideband power amplifier for efficiency improvement
2.4/5.5GHz LNA switch designs based on high resistive substrate 0.35um SiGe BiCMOS
A CMOS PGA with DCOC and I/Q mismatch calibration
An automatic DC-Offset cancellation method and circuit for RF transceivers
Stochastic Computing Based on Volatile Ovonic Threshold Switching Devices
A low cost readout and processing circuit for integrated CMOS geomagnetic sensors
Analytical model of internal heat transfer of a power chip with through silicon via
An area-efficient 10-bit two-stage DAC for active matrix organic light-emitting diodes display drivers
A novel low-cost interface design for SystemC and SystemVerilog Co-simulation
Recent progresses of STT memory design and applications
A low ripple Frequency-Feedback PFM-PWM Buck converter with seamless mode transition
Design and Co-Simulation of QPSK and NRZ/PAM-4/PAM-8 VCSEL-Based Optical Links Utilizing an Integrated System Evaluation Engine
Area-Efficient Distributed Arithmetic Optimization via Heuristic Decomposition and In-Memroy Computing
A high-performance bandgap reference with advanced curvature-compensation
Piezoelectric force microscopy study of local bipolar diode current dependence of preferential domain orientation in BiFeO3 thin films with different thicknesses
Design of ternary pulsed reversible counter based on CNFET
A Low-power High-reliability STT-MRAM Write Scheme with Real-time Voltage Sensing Module
A 60GHz Digitally-Controlled Differential Reflection-type Phase Shifter in 65-nm CMOS with Low Phase Error
SPICE model for dual-extended memristor
Fabrication, Characterization and Modeling of CVD based Amorphous Silicon Resistor
Nanoscale Devices for the end of the Roadmap
Reusable IO technique for improved utility of IC test circuit area
A 59.99dB SNDR 1.13mW Ping-pong NS SAR ADC for 3-D Transesophageal Echocardiography
Challenges and strategies in advanced CMOS technology development
An Overview of Design, Fabrication, and Cooling Techniques of 3D-ICs
Low voltage adaptive delay clock buffer design
HV CMOS orientated variation-aware layout and robust solution
Low on-resistance power MOSFET design for automotive applications
Area efficient LDPC decoder design for parallel layered decoding
Design of High Dynamic Range and Digitalized Readout Integrated Circuit for LWIR FPAs
MMV Batch Look Ahead Orthogonal Matching Pursuit (M-BLAOMP) Algorithm for Joint Sparse Recovery
A Novel 1200-V Class SiC MOSFET With Schottky Barrier Diode for Improved third quadrant performance
Extracting statistical distributions of RTN originating from both acceptor-like and donor-like traps
An Energy-efficient Approximate DCT Design for Image Processing (Invited)
A Time- and Energy-Efficient CNN with Dense Connections on Memristor-Based Chips
Frontier Applications Research for Next-Generation Cardiovascular Health Monitoring Chip Design
Algorithm/Hardware Co-Design Configurable SAR ADC with Low Power for Computing-in-Memory in 28nm CMOS
Nanoscale register file circuit design - Challenges and opportunities
An enhanced decoder for multiple-bit error correcting BCH codes
Calibration method considering second-order error term of timing skew for a novel multi-channel ADC
A radiation resistant library based on DICE and fault-tolerant delay filtering techniques in CMOS 0.18μm technology
A low-power and high-efficiency cache design for embedded bus-based symmetric multiprocessors
A novel joint estimation and compensation algorithm for non-idealities of analog front-end in DC-OFDM system
High speed, low offset, low power differential comparator with constant common mode voltage
An analytical series resistance model for on-chip stacked inductors with inclusion of proximity effect between stacked layers
High-speed object detection based on a hierarchical parallel vision chip
A neural network circuit with associative learning and forgetting process based on memristor neuromorphic device
A CMOS THz-sensing system towards label-free DNA sequencing
Word error control algorithm through multi-reading for NAND Flash memories
Design of 13.56MHz power recovery circuit with signal transmission for contactless bank IC card
Pitch Device Design in 10nm-Class DRAM Process through DTCO
Automatic gain control algorithm with high-speed and double closed-loop in UWB system
An Enhanced SSCP for Frequency Drift Suppressing in SSPLL
A Highly Automated and Rapid Datasheet Driven Empirical Modeling Process of SiC MOSFETs with High Accuracy and Robust Convergence
A new method for demodulation of FSK signal with severe impulse interference
Advances in Continuous-time MASH ΔΣ Modulators
Efficient High-Level Synthesis of Approximate Computing Circuits via Multi-fidelity Modeling
Optical computing on silicon-on-insulator-based photonic integrated circuits
An integrated development environment for reconfigurable operators array
Through-Silicon-Via assignment for 3D ICs
An Asynchronous AER Circuits with Rotation Priority Tree Arbiter for Neuromorphic Hardware with Analog Neuron
A wide range PWM signal frequency converter with the identical duty cycle
High throughput multi-code LDPC encoder for CCSDS standard
High-parallel LDPC decoder with power gating design
Design of a signal processing circuit for quartz crystal microbalance biosensors
A 63.3ps TDC Measurement System Based on FPGA for Pulsed Laser Ranging
A novel mixed reconfigurable system on chip based on field programmable analog array
An Area-Power-Efficient Multiplier-less Processing Element Design for CNN Accelerators
Low overhead task migration mechanism in NoC-based MPSoC
Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology
Controllable Growth of P3HT Single-Crystal Films for Organic Field-Effect Transistors
Pipelined-SAR ADC Calibration Technique Based on Gain-Bit Weights
TCAD Study on Strain Engineering in Vertical Channel Gate-all-around Transistor
Inversion-Mode InGaAs FinFETs for Logic and RF Applications
Redundancy-Aided Iterative Reliability-Based Majority-Logic Decoding for NB-LDPC Codes
TCAD Simulation of Novel Semiconductor Devices
Deep Spiking Convolutional Neural Networks for Programmable Neuro-synaptic System
GaN Schottky Diode Model for THz Multiplier Design with Consideration of Self-heating Effect
A 4GS/s 3b two-way time-interleaved ADC in 0.13um CMOS
Incremental 3D NoC synthesis based on physical-aware router merging algorithm
High efficiency single-inductor dual-output DC-DC converter with ZVS-PWM control
An adaptive Q factor tuning and input impedance matching method for ultra-low power front end of UHF RFID tag
Design of a time-interleaved band-pass ΣΔ modulator for Class-S power amplifier
Development of RFCMOS Technologies in the 1990s in Toshiba
An Architecture of a Single-Event Tolerant D Flip-flop Using Full-Custom Design in 28nm Process
A Multi-conductance States Memristor-based CNN Circuit Using Quantization Method for Digital Recognition
A high-speed and area-efficient sign detector for three moduli set RNS {2n, 2n-1, 2n+1}
Folding and interpolation ADC design methodology
New DfT architectures for 3D-SICs with a wireless test port
Deep trench junction termination employing variable-K dielectric for high voltage devices
CMOS image sensor with programmable compressed sensing
A clocked differential switch logic using floating-gate MOS transistors
Analysis and Modeling of Non-ideal Effects in SAR ADC
Loop Oscillation Analysis of MEMS Resonant Pressure Sensor Readout Circuit
FFTPL: An analytic placement algorithm using fast fourier transform for density equalization
An Integrated System Evaluation Engine for Cross-Domain Simulation and Design Optimization of High-Speed 5G Millimeter-Wave Wireless SoCs
An Adaptive DFE Using Pattern-Dependent Data-Level Reference in 28 nm CMOS Technology
A High-Throughput Luma Mapping with Chroma Scaling Decoder for Versatile Video Coding
A configurable SoC design for information security
Inverse RIE micro-loading in deep etching of silicon via array
A Three-stage Analog Low-Frequency Drift Calibration and DC Offset Correction Circuit for Ultrasonic AFE
A High-precision Current Detection Circuit for Battery Management System
A 77.8dB-SNDR 25MHz-BW 2 nd -order NS Pipelined SAR ADC with 4 th -order Gain-Error-Shaping
Phase-change materials and memory devices for IoT application
Electrical Overstress (EOS): Challenges for component and system-level co-design
A low-power parallel-to-serial conversion circuit for CMOS image sensors
An inductorless CMOS LNA with single input and differential output
A 1.8-V 14-bit inverter-based incremental ΣΔ ADC for CMOS image sensor
A 5-bit, 87-fs Step, Constant-Slope, Charge-Sharing-Based Encoding Digital-to-Time Converter in 130nm CMOS
A programmable baseband processor for massive MIMO uplink multi-user detection
Adsorbates on Multilayer Graphene Surface: Morphology, Distribution and Electrical Properties
Multi-stage power gating based on controlling values of logic gates
A 14-bit 5 MS/s split non-binary SAR ADC
Controlling-value-based power gating considering controllability propagation and power-off probability
MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip support
Design of novel high speed dual-modulus prescaler based on new optimized structure
Modified Peripheral MRAM Sensing for In-memory Boolean Logic
Effective Analytical Placement for Advanced Face-to-Face-Bonded Circuit Designs
High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS
An all-digital quadrature RF transmitter with 8-bit ΣΔ modulation
A design of configurable image enhancement unit
Transparent Buffer Management: An Intra-cluster Task Scheduling Method Based on Dynamic Virtual Channel
A 16/32Gb/s NRZ/PAM4 Receiver with Dual-Loop CDR and Threshold Voltage Calibration
Sub-50mV Bootstrap Clock Booster and Integrated Cold Start for Thermoelectric Energy Harvesting
A Further Analysis of the Forbidden Pitch in Photolithography in Advanced Technology Nodes
FPGA-based efficient implementation of SURF algorithm
An Efficient Demultiplexer Design in Quantum-dot Cellular Automata
Mos2 transistor gated by PMMA-based electrolyte for sub-1 V operation
The design and verification of SEU-hardened configurable DFF
A high performance sound source localization system based on macro-pipelined architecture
A new countermeasure against side channel attack for HMAC-SM3 hardware
Characterization and Classification of Heavy Ion Induced Failures in FPGA-based Logical Circuits
A high efficiency all-PMOS charge pump for 3D NAND flash memory
A high efficient baseband transceiver for IEEE 802.15.4 LR-WPAN systems
Integrated Gm-C based PI controller for MEMS gyroscope drive loop
A low-power digital GFSK receiver with mid-value filtering frequency offset estimator and soft anti-overlap slicer
An efficient successive cancellation polar decoder based on new folding approaches
Novel high uniformity readout circuit allowing microbolometers to operate with low noise
A 20MHz BW 35fJ/conv. continuous-time ΣΔ modulator with single-opamp resonator using finite GBW compensation method
Separate projection and extended Cauer method for circuit reduction
High performance protocol converters for two phase quasi-delay insensitive system-level communication
A sample-and-hold circuit for 10-bit 100MS/s pipelined ADC
A 10Gbps High-Speed Low-Noise Optical Receiver Based on CMOS 45nm Technology
An open 45nm PD-SOI standard cell library based on verified BSIM SOI spice model with predictive technology
Design and analysis of nano-scale bulk FinFETs
A thermal model for the top layer of 3D integrated circuits considering through silicon vias
A new reading scheme for multitime programmable (MTP) memory cells
A new high performance RF LDMOS with vertical n+n-p-p+ drain structure
A Vertical Thin Layer pLDMOS with Linear doping realizing ultralow Ron, sp
Process Optimization for CMOS Compatible MEMS Capacitive Acoustic Sensor
Deeply scaled VLSI analog transistor design and optimization
A passive mixer-first receiver with negative feedback for impedance matching
Interconnect waveform calculation method with parameter variation
Design of a high-linearity RF front-end with IP2 calibration for SAW-less WCDMA receivers
An ADPLL Design Model Based on LoRa IoT Application
A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applications
A New Degeneration Technique for 60 GHz Triple Cascode Wideband Low Noise Amplifier
Joint detection and decoding for polar-coded OFDM-IDMA systems
An iterative synthesis method for timing-driven design
Adaptive OCD and ODT Control for Channel S/I Enhancement in DDR4 SDRAM
A curvature corrected bandgap reference with mismatch cancelling and noise reduction
Low-complexity synchronizer used in DC-OFDM UWB system
The manufacturing of Si base thin film solar cell modules
Influence of heat source size on thermal resistance of AlGaN/GaN HEMT
Accelerating the data shuffle operations for FFT algorithms on SIMD DSPs
PEALD Ru/RuOx films for ULSI applications and its transition control between metal and metal oxide
A novel inverse quantization algorithm based on Taylor series for digital audio codecs
A TSV alignment design for multilayer 3D IC
A test approach of combining partial scan with functional testing for high performance processors
VLSI interconnect delay analysis method for ramp input signal
Efficient Layout Pattern Matching Based on Local Information
A New Uplink Channel Estimation Architecture for Massive MIMO Systems with PDMA
Cell-based programmable phase shifter design for pulsed radar SoC
The Digital Front End with Dual-box Digital Pre-distortion in All-digital Quadrature Transmitter
A novel structure of dynamic configurable scan chain bypassing unconcerned segments on the fly
Development of TFET 0.13 μm standard cell library for ultra-low power applications
An Inductorless 5-GHz Differential Dual Regulated Cross-Cascode Transimpedance Amplifier using 40 nm CMOS
A novel energy-oriented reconfigurable on-chip unified memory architecture based on Cache Behavior Phase Graph
A low complexity MCMC algorithm for MIMO system with bias technique
A 28-Gb/s 60-GHz wireless transceiver in 65nm CMOS with 64QAM capability
Split-based 200Msps and 12 bit ADC design
Design of novel chopper stabilized rail-to-rail operational amplifier
A configurable nonlinear operation unit for neural network accelerator
The Advances of OTP Memory for Embedded Applications in HKMG Generation and Beyond
Scalable Highly Integrated Quantum Bit Error Correction System by Classical Electronics
A Low-Power 10-bit 160-MSample/s DAC in 40-nm CMOS for Baseband Wireless Transmitter
A Continuous and Closed-Form Trans-Capacitance Model for Double-Gate Junctionless Transistors
A permutation network for configurable and scalable FFT processors
The Design and Implementation of High Speed Hybrid Radices Reconfigurable FFT Processor
Large-array high-density active microelectrodes array for neural signal recording
Training, Programming, and Correction Techniques of Memristor-Crossbar Neural Networks with Non-Ideal Effects such as Defects, Variation, and Parasitic Resistance
A high-speed asynchronous array multiplier based on multi-threshold semi-static NULL convention logic pipeline
ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator
An Ultra-low Specific On-resistance SiC LDMOS Using Double RESURF and Field Plate Techniques
Design of explicit-pulse generators with CNTFET
A novel vision chip architecture for image recognition based on convolutional neural network
The Design and Performance Comparison of Wide Bandwidth LNA with Three Different Kinds of Technologies
Automated design strategy for high performance mixed signal circuits
HDDB: a High Density Digital Waveform Storage Method
Mixed-signal SoC design and low power research for tire pressure monitoring systems
Soft error immunity of subthreshold SRAM
A unipolar-CMOS with recessed source/drain load
FFT design for OFDM-based cognitive radio using a reconfigurable baseband processing architecture
A programmable divider with wide division range applied in an FMCW frequency synthesizer
A 0.06 mm2 6 dBm IB1db wideband CMOS class-AB LNTA for SAW-less applications
A bulk-driven pixel circuit with wide data voltage range for OLEDoS microdisplays
Influence of substrate coupling noise to clock and data recovery
Ultra-short length stochastic computation based on multiple partition computing
A continuous time sigma-delta modulator using time-domain quantizer and feedback element
Analysis and design of quickly starting crystal oscillator
Investigation of electrical characteristics of a novel FeFET-based relaxation oscillator
12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017
Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM)
A SFA and I/Q mismatch auto-calibration scheme for high IRR multi-mode GPS RF receiver
Cascadable current-mode multifunction filter configuration using minimum number of CCTAs and grounded capacitors
High precision low power CMOS bandgap for RFID
Not your father's stochastic computing (SC)! Efficient yet Accurate End-to-End SC Accelerator Design
A new current switch driver with improved dynamic performance used for 500MS/s, 12-bit Nyquist current-steering DAC
A low-power Gm-R-C image rejection filter for complex low-IF receiver
Optimization of Protective Layer Process for Micro-bridge Structure based MEMS/Sensors Application
Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors
Low phase noise injection-locked doubler-based quadrature CMOS VCO
Statistical simulation methods for circuit performance analysis
A digitalized RRAM-based Spiking Neuron Network system with 3-bit weight and unsupervised online learning scheme
An 8-bit 4fs-step digitally controlled delay element with two cascaded delay units
Ultralow power loss integratable high-voltage MOSFETs
16-Channel Readout Circuit for Nucleic Acid Detection Based on Graphene Electrolyte-gated Field-effect Transistors (EGFETs)
Peripheral Hardware System Design for a Neuromorphic Chip
A CNN Hardware Accelerator Designed for YOLO Algorithm Based on RISC-V SoC
High Performance Bootstrap Switch for 14 bit SAR ADC with Redundancy in SMIC 180nm
A 5.75nARMS Resolution Sigma-Delta-based Sinusoidal Current Generator for in-situ Calibration of Electrochemical Bio-sensors
Research of Scale Recurrent Generative Network on Image Inpainting
Power optimization for FPRM logic using approximate computing technique
An Improved Delay Cell with Low Power Consumption and Strong Driving Capability
Impact of Evaporated AuNP Thickness on Pseudo-MOS and Its Application in Direct MicroRNA-375 Detection
Design consideration of uni-traveling carrier photodiode: Influence of doping profile and buffer layer
Ultra-flexible organic photovoltaics for powering wearable electronics
A fast multi-core virtual platform and its application on software development
Design of low-power FinFET-based TCAMs with unevenly-segmented matchlines for routing table applications
A Implementation for Built-in Self-Testing of RapidIO by JTAG
An adaptive dynamical low-rank tensor approximation scheme for fast circuit simulation
Investigation of a GaN-on-Si HEMT optimized for the 5th-generation wireless communication
A Optimized PPD CMOS Pixel with 26.09 % Transfer Efficiency Improvement and 43.34 % Crosstalk Suppression for I-ToF Application
Performance optimization for LDO regulator based on the differential evolution
A C-Band Power Amplifier with Over-Neutralization Technique and Coupled-Line MCR Matching Methods for 5G Communication in 0.25-μm GaAs
A channel estimator for LTE downlink mapped on a multi-core processor platform
A split-gate SiC trench MOSFET with embedded unipolar diode for improved performances
Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation
Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme
LSI Testing: A Core Technology to a Successful LSI Industry
A 40-nm 202.3nJ/Classification Neuromorphic Architecture Employing In-SRAM Charge-Domain Compute
A 768 Megapixels/sec inverse transform with hybrid architecture for multi-standard decoder
A new asynchronous delay-insensitive link based on a 1-of-4 LETS code
A 15GHz Class-C VCO with Two-stage Buffer in 0.15-μm GaAs