yusuke1997/dblp-id-title huggingface dataset:
Real-time FPGA architecture of extended linear convolution for digital image scaling
Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations
Sigma-delta based clock recovery using on-chip PLL in FPGA
A tsume-shogi processor based on reconfigurable hardware
An analytical energy model to accelerate FPGA logic architecture investigation
Hierarchical segmentation schemes for function evaluation
Mapping Estimator for OpenCL Heterogeneous Accelerators
An exact MCMC accelerator under custom precision regimes
Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT 2009, Sydney, Australia, December 9-11, 2009
An efficient implementation of online arithmetic
The cost of data dependence in motion vector estimation for reconfigurable platforms
A deeply pipelined and parallel architecture for denoising medical images
FCLNN: A Flexible Framework for Fast CNN Prototyping on FPGA with OpenCL and Caffe
FPGA implementations of fast fourier transforms for real-time signal and image processing
A Hexagon-Based Honeycomb Routing Architecture for FPGA
A graphical programming and design environment for FPGA-based hardware
A universal FPGA-based floating-point matrix processor for mobile systems
Distributed-Memory Based FPGA Debug: Design Timing Impact
A C compiler for implementing FPGA based bit-serial DSP systems
FPGA based acceleration of FDAS module for Pulsar Search
Fast polynomial arithmetic for Somewhat Homomorphic Encryption operations in hardware with Karatsuba algorithm
Implementing NEF Neural Networks on Embedded FPGAs
A technology mapping algorithm for CPLD architectures
Study on column wise design compaction for reconfigurable systems
A dataset generation for object recognition and a tool for generating ROS2 FPGA node
Journal Track Paper ICFPT 2023 : Across Time and Space: Senju's Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs
Tens of gigabytes per second JSON-to-Arrow conversion with FPGA accelerators
Asymmetric multiprocessing for motion control based on Zynq SoC
Accelerating Top-k ListNet Training for Ranking Using FPGA
Design tradeoffs for hard and soft FPGA-based Networks-on-Chip
Self-recovery experiments in extreme environments using a field programmable transistor array
Optimal Buffering of FPGA Interconnect for Expected Delay Optimization
Scalable radio processor architecture for modern wireless communications
FPGA-based high-speed emulator of quantum computing
A unified reconfigurable floating-point arithmetic architecture based on CORDIC algorithm
Evaluation of network topologies for a run time re-routable network on a programmable chip
Real-time packet editing using reconfigurable hardware for active networking
Multi-dimensional packet classification on FPGA: 100 Gbps and beyond
Unifying FPGA Hardware Development
Deep and narrow binary content-addressable memories using FPGA-based BRAMs
E 2 -ACE: An Energy-Efficient Reconfigurable Crypto-Accelerator with Agile End-to-End Toolchain
Accelerating iterative algorithms with asynchronous accumulative updates on FPGAs
Pipelining designs with loop-carried dependencies
Reconfigurable Functional Units for Scientific Superscalar Processors
AUGER: A Multi-Objective Design Space Exploration Framework for CGRAs
A new approach for reconfigurable massively parallel computers
The hot decade of field programmable technologies
A tiled programmable fabric using QCA
Small virtual channel routers on FPGAs through block RAM sharing
FastCGRA: A Modeling, Evaluation, and Exploration Platform for Large-Scale Coarse-Grained Reconfigurable Arrays
Migrating software to hardware on FPGAs
Hypervisor mechanisms to manage FPGA reconfigurable accelerators
Hardware acceleration of biomedical models with OpenCMISS and CellML
A detailed delay path model for FPGAs
Automatic wire modeling to explore novel FPGA architectures
Increasing the Scalability of Graph Convolution for FPGA-Implemented Event-Based Vision: (PhD Forum Paper)
High Performance High-Precision Floating-Point Operations on FPGAs Using OpenCL
Exploring the optimal size for multicasting configuration data of dynamically reconfigurable processors
Design space exploration for FPGA-based hybrid multicore architecture
Pre-silicon prototyping of a unified hardware architecture for cryptographic manipulation detection codes
Is high level synthesis ready for business? A computational finance case study
Augmenting general purpose processors for network processing
A Case for Soft Vector Processors in FPGAs
A scalable and pipelined FPGA implementation of an OC192 WF scheduler
2006 IEEE International Conference on Field Programmable Technology, FPT 2006, Bangkok, Thailand, December 13-15, 2006
Real-time ray tracing on coarse-grained reconfigurable processor
Automated multi-device placement, I/O voltage supply assignment, and pin assignment in circuit board design
Trax player implementation on FPGA using high level synthesis tool
Efficient Reinforcement Learning Framework for Automated Logic Synthesis Exploration
Product-term based synthesizable embedded programmable logic cores
Accelerating FPGA development through the automatic parallel application of standard implementation tools
System on programmable chip for real-time control implementations
Granularity aspects for the design of multi-level reconfigurable architectures
Liquid: High quality scalable placement for large heterogeneous FPGAs
Single window stream aggregation using reconfigurable hardware
A multiported register file with register renaming for configurable softcore VLIW processors
Hardware acceleration for the banded Smith-Waterman algorithm with the cycled systolic array
Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters
Software-managed automatic data sharing for Coarse-Grained Reconfigurable coprocessors
Balanced allocation of compute time in hardware-accelerated systems
Managing mutex variables in a cache-coherent shared-memory system for FPGAs
SSiMD: Supporting Six Signed Multiplications in a DSP Block for Low-Precision CNN on FPGAs
JIT trace-based verification for high-level synthesis
Performance Modeling and Scalability Analysis of Stream Computing in ESSPER FPGA Clusters
Exploring hard and soft networks-on-chip for FPGAs
Calling hardware procedures in a reconfigurable accelerator using RPC-FPGA
An efficient architecture for zero overhead data en-/decryption using reconfigurable cryptographic engine
Regular expression matching for reconfigurable packet inspection
Low-latency double-precision floating-point division for FPGAs
OD-REM: On-Demand Regular Expression Matching on FPGAs for Efficient Deep Packet Inspection
A Parallel-Trial Double-Update Annealing Processor for Enabling Highly-Effective Solution Search of Constrained Combinatorial Optimization Problems
FPGA implementation of low-power and high-PSNR DCT/IDCT architecture based on adaptive recoding CORDIC
Achieving wide frequency range in an analog FPGA
High speed low complexity FPGA-based FIR filters using pipelined adder graphs
A case for hardened multiplexers in FPGAs
Enhancing Memory Bandwidth in a Single Stream Computation with Multiple FPGAs
An FPGA-based scalable platform for high-speed malware collection in large IP networks
An efficient FPGA-based implementation of Pollard's (ρ - 1) factorization algorithm
NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture
An FPGA-based spectral anomaly detection system
Design evaluation of OpenCL compiler framework for Coarse-Grained Reconfigurable Arrays
Synthesis of efficiently reconfigurable datapaths for reconfigurable computing
2008 International Conference on Field-Programmable Technology, FPT 2008, Taipei, Taiwan, December 7-10, 2008
Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSI
FPGA-based cloud detection for real-time onboard remote sensing
Lens Distortion Self-Calibration Using the Hough Transform
Wavelet spectral dimension reduction of hyperspectral imagery on a reconfigurable computer
Accelerating FPGA Routing Using Architecture-Adaptive A* Techniques
Cool Mega-Array: A highly energy efficient reconfigurable accelerator
DIMES: an iterative emulation platform for Multiprocessor-System-On-Chip designs
FPGA Implementation of an Excitatory and Inhibitory Connectionist Model for Motion Perception
A Framework for Implementing a Network-Based Stochastic Biochemical Simulator on an FPGA
Simultaneous Inference and Training Using On-FPGA Weight Perturbation Techniques
The Multiplier Tree FIR filter architecture
A framework for verifying functional correctness in Odin II
Pipeline frequency boosting: Hiding dual-ported block RAM latency using intentional clock skew
Implementation of a Reverse Time Migration kernel using the HCE High Level Synthesis tool
Efficient algorithm for functional scheduling in hardware/software co-design
Runtime rule-reconfigurable high throughput NIPS on FPGA
Highly scalable, shared-memory, Monte-Carlo tree search based Blokus Duo Solver on FPGA
Resiliency-aware scheduling: Resource allocation for hardened computation on configurable devices
Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs
Comparison of thread signatures for error detection in hybrid multi-cores
A high-performance architecture for training Viola-Jones object detectors
Field modifiable architecture with FPGAs and its design methodology
Efficient FPGA elliptic curve cryptographic processor over GF(2 m )
Implementation of an FPGA based accelerator for virtual private networks
High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAs
Using integer linear programming for correctly rounded multipartite architectures
FPGA design of HECC coprocessors
A non-intrusive portable fault injection framework to assess reliability of FPGA-based designs
Use of embedded FPGA resources in implementations of 14 round 2 SHA-3 candidates
Zero latency encryption with FPGAs for secure time-triggered automotive networks
An Automated FPGA-Based Fault Injection Platform for Granularly-Pipelined Fault Tolerant CORDIC
Mapping computation kernels to clustered programmable-reconfigurable processors
Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction
FLOWER: A comprehensive dataflow compiler for high-level synthesis
An adaptive frequency control method using thermal feedback for reconfigurable hardware applications
Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designs
FPGA-based video processing for a vision prosthesis
SEU tolerant SRAM for FPGA applications
International Conference on Field Programmable Technology, FPT 2017, Melbourne, Australia, December 11-13, 2017
An FPGA-based real-time simultaneous localization and mapping system
High level synthesis of stereo matching: Productivity, performance, and software constraints
Using Round-Robin Tracepoints to debug multithreaded HLS circuits on FPGAs
Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA
Minimizing DSP block usage through multi-pumping
Automatic code generation of convolutional neural networks in FPGA implementation
A new reconfigurable architecture with smart data-transfer subsystems for the intelligent image processing
NnCore: A parameterized non-linear function generator for machine learning applications in FPGAs
A pattern-matching co-processor for network intrusion detection systems
Selection of an error-correcting code for FPGA-based physical unclonable functions
A framework for FPGA acceleration of large graph problems: Graphlet counting case study
Solving the Minimum Dominating Set Problem with Instance-Specific Hardware on FPGAs
Automated design space exploration of FPGA-based FFT architectures based on area and power estimation
Recursive Variable Expansion: A Loop Transformation for Reconfigurable Systems
Improving Confidentiality in Virtualized FPGAs
Implementation of LS-SVM with HLS on Zynq
Color configuration method for an optically reconfigurable gate array
An Empirically Guided Optimization Framework for FPGA OpenCL
QuickRoute: a fast routing algorithm for pipelined architectures
Rule-based data communication optimization using quantitative communication profiling
Journal Track Paper ICFPT 2023 : HyBNN: Quantifying and Optimizing Hardware Efficiency of Binary Neural Networks
A low cost FPGA system for high speed face detection and tracking
Comparing floating-point and logarithmic number representations for reconfigurable acceleration
A profiler for a heterogeneous multi-core multi-FPGA system
Efficient nested loop pipelining in high level synthesis using polyhedral bubble insertion
Direct virtual memory access from FPGA for high-productivity heterogeneous computing
Provably Correct Development of reconfigurable hardware designs via equational reasoning
Memory-Efficient Sketch Acceleration for Handling Large Network Flows on FPGAs
R3SGM: Real-Time Raster-Respecting Semi-Global Matching for Power-Constrained Systems
A Zero-Overhead Dynamic Optically Reconfigurable Gate Array
Bitstream Decompression for High Speed FPGA Configuration from Slow Memories
Arbitrary function approximation in HDLs with application to the N-body problem
Hardware-Accelerated SSH on Self-Reconfigurable Systems
Application Specific Instruction-Set Processors for Machine Learning Applications
Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture
Lossless data compression programmable hardware for high-speed data networks
A 66.1 Gbps single-pipeline AES on FPGA
Implementation of a volume rendering on coarse-grained reconfigurable multiprocessor
A debugging method for repairing post-silicon bugs of high performance processors in the fields
Seamless top-down flow for quick trial of HW/SW co-design
FPGA-based computation of free-form deformations
SMCFA: A Zynq-based stacked multi CPU-FPGA architecture
An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDIC
An IP core integration tool-flow for prototyping software-defined radios using static dataflow with access patterns
ZHW: A Numerical CODEC for Big Data Scientific Computation
HETRIS: Adaptive floorplanning for heterogeneous FPGAs
Efficient performance scaling of future CGRAs for mobile applications
Maximizing system performance: using reconfigurability to monitor system communications
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect
Parallelizing sparse LU decomposition on FPGAs
Accelerated evaluation of SEU failure-in-time using frame-based partial reconfiguration
Designing an FPGA SoC Using a Standardized IP Block Interface
An FPGA Based Travelling-Wave Fault Location System
GraFF: A Multi-FPGA System with Memory Semantic Fabric for Scalable Graph Processing
Communications infrastructure generation for modular FPGA reconfiguration
On the Performance Effect of Loop Trace Window Size on Scheduling for Configurable Coarse Grain Loop Accelerators
From dynamic reconfiguration to self-reconfiguration: Invasive algorithms and architectures
Discrete event system specification, synthesis, and optimization of low-power FPGA-based embedded systems
A Cautionary Note on Building Multi-tenant Cloud-FPGA as a Secure Infrastructure
Tessellation-based multi-block memory mapping scheme for high-level synthesis with FPGA
VMATCH: Using logical variation to counteract physical variation in bottom-up, nanoscale systems
Towards an embedded biologically-inspired machine vision processor
A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors
Hardware Join Java: a high level language for reconfigurable hardware development
EMA-FPRMs: An efficient minimization algorithm for fixed polarity Reed-Muller expressions
Exploiting system-level parallelism in the application development on a reconfigurable computer
HPIPE NX: Boosting CNN Inference Acceleration Performance with AI-Optimized FPGAs
Energy efficiency of FPGAs and programmable processors for matrix multiplication
M4BRAM: Mixed-Precision Matrix-Matrix Multiplication in FPGA Block RAMs
High-level synthesis of resource-shared microarchitectures from irregular complex C-code
High performance and memory efficient implementation of matrix multiplication on FPGAs
Net Length based Routability Driven Packing
SCC based modulo scheduling for coarse-grained reconfigurable processors
The effect of cluster packing and node duplication control in delay driven clustering
A Framework for Dynamic Resource Assignment and Scheduling on Reconfigurable Mixed-Mode On-Chip Multiprocessors
On identifying and optimizing instruction sequences for dynamic compilation
Implementation of high performance hardware architecture of OpenSURF algorithm on FPGA
Windows CE for a reconfigurable system-on-a-chip processor
Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse Lasers
PD-XML: extensible markup language for processor description
FPGA implementation of an invasive computing architecture
TROJANUS: An ultra-lightweight side-channel leakage generator for FPGAs
Leftmost longest regular expression matching in reconfigurable logic
Dual-Triangular QR Decomposition with Global Acceleration and Partially Q-Rotation Skipping
Fast architectures for FPGA-based implementation of RSA encryption algorithm
Parallel image processing field programmable gate array for real time image processing system
Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory
Programmed solutions: the step beyond programmed logic [computer architecture]
Floating-point bitwidth analysis via automatic differentiation
FPGA-based accelerator for losslessly quantized convolutional neural networks
VersaPower: Power estimation for diverse FPGA architectures
Dynamic reconfiguration for the common key encryption using FPGA
FPGA implementation of a strong Reversi player
LCAM: Low-Cost Approximate Multiplier Design on FPGA
Speedup analysis in simulation-emulation co-operation
FPGA Blokus Duo Solver using a massively parallel architecture
A systolic regular expression pattern matching engine and its application to network intrusion detection
Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting
Memory-Efficient Architecture for Accelerating Generative Networks on FPGA
Integer computations with soft GPGPU on FPGAs
High-order reconfigurable FIR filter design based on statistical analysis of CSD coefficients
LeFlow: Automatic Compilation of TensorFlow Machine Learning Applications to FPGAs
An Agile Tile-based Platform for Adaptive Heterogeneous Many-Core Systems
PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess
An FPGA-accelerated high-throughput data optimization system for high-speed transfer via wide area network
From C to Blokus Duo with LegUp high-level synthesis
A real time programmable encoder for low density parity check code targeting a reconfigurable instruction cell architecture
OpenCL library of stream memory components targeting FPGAs
Reconfigurable real-time address trace compressor for embedded microprocessors
Sharing FPUs in many-soft-cores
Integration of PSoC technology with educational robotics
Automatic generation of decomposition based matrix inversion architectures
Design and optimization of heterogeneous tree-based FPGA using 3D technology
Area-time estimation of C-based functions for design space exploration
An OpenCL optimizing compiler for reconfigurable processors
An FPGA-based processor for shogi mating problems
Extending Booth algorithm to multiplications of three numbers on FPGAs
A hardware cache memcpy accelerator
FADEC: FPGA-based Acceleration of Video Depth Estimation by HW/SW Co-design
Architectures for ICT on FPGA
Design methodology for FPGA implementation of lattice piecewise-affine functions
Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures
A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os
CAPI-Precis: Towards a Compute-Centric Interface for Coherent Shared Memory Accelerators
Multisensor inversion with high-performance FPGA computation
Compound Uniform Random Number Generators with On-Chhip Correlation and Distribution Measurements
An efficient architecture for an improved watershed algorithm and its FPGA implementation
An FPGA architecture supporting dynamically controlled power gating
2015 International Conference on Field Programmable Technology, FPT 2015, Queenstown, New Zealand, December 7-9, 2015
Impact of reconfigurable hardware on accelerating MPI_Reduce
Lossy Multiport Memory
FPGA-based computation of free-form deformations in medical image registration
Compact iterative FPGA Camellia algorithm implementations
uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology
Improve memory access for achieving both performance and energy efficiencies on heterogeneous systems
Face-off Between the CAESAR Lightweight Finalists: ACORN vs. Ascon
Exploiting partially defective LUTs: Why you don't need perfect fabrication
Reconfigurable architecture for probabilistic neural network system
Analysis and optimization of a deeply pipelined FPGA soft processor
FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example
Exploring automated space/time tradeoffs for OpenVX compute graphs
OpenTitan based Multi-Level Security in FPGA System-on-Chips
SALIENT: Ultra-Fast FPGA-based Short Read Alignment
Making domain-specific hardware synthesis tools cost-efficient
Design & development of soft-core processor based remote terminal units for nuclear reactors
FPGA accelerated tate pairing based cryptosystems over binary fields
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, Tokyo, Japan, FPT 2003, December 15-17, 2003
Architectural synthesis of computational pipelines with decoupled memory access
Reconfigurable parallel comparation architecture and its application to IP packet filters
Traffic Flow Optimization using a Chaotic Boltzmann Machine Annealer on an FPGA
Teaching FPGA security
Implementation of a real-time multiple input multiple output channel estimator on the smart antenna software radio test system platform using the Xilinx Virtex 2 Pro Field Programmable Gate Array
A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm
A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA
F-TFM: Accelerating Total Focusing Method for Ultrasonic Array Imaging on FPGA
Performance estimation framework for FPGA-based processors
Portable and scalable FPGA-based acceleration of a direct linear system solver
FPGA-based training of convolutional neural networks with a reduced precision floating-point library
Compact Area and Performance Modelling for CGRA Architecture Evaluation
Efficient region allocation for adaptive partial reconfiguration
A Secure Digital Content Delivery System Based on Partially Reconfigurable Hardware
An architecture of optimised SIFT feature detection for an FPGA implementation of an image matcher
Efficient single-chip implementation of SHA-384 and SHA-512
Debugging framework for FPGA-based soft processors
Fine-grained module-based error recovery in FPGA-based TMR systems
FPGA Architecture for Standby Power Management
FPGA implementation for an iris biometric processor
Real-time Implementation of Cyclostationary Analysis using FPGAs
Accelerating RavÆn for Real-Time Satellite Image Change Detection
Spatio-Temporally-Shared Reconfigurable Fast Fourier Transform architecture design
Memory support design for LU decomposition on the starbridge hyper-computer
General switch box modeling and optimization for FPGA routing architectures
COFFE: Fully-automated transistor sizing for FPGAs
A scalable architecture for elliptic curve point multiplication
Reconfigurable hardware control software using anonymous libraries
Modular exponentiation using parallel multipliers
Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA
A modular RFSoC-based approach to interface superconducting quantum bits