yusuke1997/dblp-id-title huggingface dataset:
Multi-Purpose Digital Test Core Utilizing Programmable Logic
LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation
Electron Beam Tester Integrated into a VLSI Tester
Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflections
Methodology of Generating Timing-Slack-Based Cell-Aware Tests
The value of tester accuracy
Potential Solutions for Benchmarking Issues
Multi-Gigahertz Testing of Wafer-Level Packaged Devices
CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test system
Contactless gigahertz testing
WCDMA Testing with a Baseband/IF Range AWG
Stress Aware Quiescent Current Test Optimization
Testability Analysis will not Replace Fault Simulation
A Fault Detection and Isolation Technique for Microcomputers
Testing of critical paths for delay faults
Automated Logic Synthesis of Random-Pattern-Testable Circuits
Interconnect and Delay Testing with a 4800-Pin Board Tester
Estimating Error Rate during Self-Test via One's Counting
Advanced Burn-In - An Optimized Product Stress and Test Flow for Automotive Microcontrollers
The Design and Validation of IP for DFM/DFY Assurance
Testing High Speed Drams
SmartScan - Hierarchical test compression for pin-limited low power designs
Transient Power Supply Voltage (V DDT ) Analysis for Detecting IC Defects
Rapid FPGA delay characterization using clock synthesis and sparse sampling
Using Scan Technology for Debug and Diagnostics in a Workstation Environment
Applications of semiconductor test economics, and multisite testing to lower cost of test
Diagnosis with convolutional compactors in presence of unknown states
Experiences with Concurrent Fault Simulation of Diagnostic Programs
Simplified Microprocessor Test Generation
X-filter: filtering unknowns from compacted test responses
Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection
Exact At-speed Delay Fault Grading in Sequential Circuits
Technique to improve the performance of time-interleaved A-D converters
A built-in self-repair analyzer (CRESTA) for embedded DRAMs
Simulation of non-classical Faults on the Gate Level - The Fault Simulator COMISM -
Reusing IEEE 1687-Compatible Instruments and Sub-Networks over a System Bus
An efficient SAT-based path delay fault ATPG with an unified sensitization model
A Test-Clock Reduction Method for Scan-Designed Circuits
Evaluation of System BIST Using Computational Performance Measures
Improving In-Circuit Diagnosis of Analog Networks with Expert Systems Techniques
Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICs
Seamless Integration of SER in Rewiring-Based Design Space Exploration
Evaluation of the Quality of N-Detect Scan ATPG Patterns on a Processor
Optimal Scan for Pipelined Testing: An Asynchronous Foundation
Designing a High-Speed Vector Bust to Meet the Requirements of Analog LSI Testing
Standard Test Interface Language (STIL): A New Language for Patterns and Waveforms
Manufacturing Test of Fiber Channel Communications Cards and Optical Subassemblies
Test Technology In a University Setting
SSC applied serial ATA signal generation and analysis by analog tester resources
An Information-Rich ATE Architecture
An algorithmic approach to optimizing fault coverage for BIST logic synthesis
Automated Test Instrumentation for Low-Current Testing
Test Cost Reduction Through A Reconfigurable Scan Architecture
Core-Based Scan Architecture for Silicon Debug
Test Economics - What can a Board/System Test Engineer do to Influence Supply Operation Metrics
IC Characteristic Matching for Optimal System Performance
Case Study: ATE Networking Using Peripheral Emulation
Efficient SAT-based combinational ATPG using multi-level don't-cares
Test of Supply Noise for Emerging Non-Volatile Memory
The Need for Real-Time Intelligence When Testing VLSI
An Analysis of the Cost and Quality Impact of LSI/VLSI Technology on PCB Test Strategies
Hazard-aware statistical timing simulation and its applications in screening frequency-dependent defects
DIP : A Diagnostics Processor
Too much delay fault coverage is a bad thing
Test Set Reduction Using the Subscripted D-Algorithm
Designing "Dual-Personality" IEEE 1149.1-Compliant Multi-Chip Modules
NeuralTPG: GPU-Accelerated Neural Twin-Based Test Pattern Generation for Transition Delay Faults in Safety-Critical Applications
IEEE International Test Conference, ITC 2024, San Diego, CA, USA, November 3-8, 2024
Future ATE: Perspectives & Requirements
Cross-Layer Reliability Evaluation of In-Memory Similarity Computation
Software Regression Testing Success Story
Calibration Techniques for a Gigahertz Test System
Defect screening challenges in the Gigahertz/Nanometer age: keeping up with the tails of defect behaviors
Physical defect modeling for fault insertion in system reliability test
Neural Fault Analysis for SAT-based ATPG
THD and SNR Tests Using the Simplified Volterra Series with Adaptive Algorithms
A general purpose 1149.4 IC with HF analog test capabilities
Design for diagnostics views and experiences
On applying non-classical defect models to automated diagnosis
Tools and Techniques for Failure Analysis and Qualification of MEMS
A Parity Bit Signature for Exhaustive Testing
Low power programmable PRPG with enhanced fault coverage gradient
On Reduction of Deterministic Test Pattern Sets
Transition test bring-up and diagnosis on UltraSPARC TM processors
Chiplets' Die-to-Die Interconnect Repair Language (IRL)
Switch-level delay test
IMEMS accelerometer testing-test laboratory development and usage
Test cost reduction by at-speed BISR for embedded DRAMs
External Loopback Testing Experiences with High Speed Serial Interfaces
Wafer-View Defect-Pattern-Prominent GDBN Method Using MetaFormer Variant
Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk
Functional Test Vector Generation for Digital LSI/VLSI Devices
How we test Siemens Embedded DRAM Cores
TAPS All Over My Chips
Predictive analysis for projecting test compression levels
Test System Architecture for Testing Advanced Mixed-Signal Devices
Scan Synthesis for One-Hot Signals
Electronic circuit comprising a secret sub-module
IJTAG: The path to organized instrument connectivity
A highly-efficient transparent online memory test
Using SCAN TM Bridge as an IEEE 1149.1 Protocol Addressable, Multi-Drop, Backplane Test Bus
A Real-Time Jitter Measurement Board for High-Performance Computer and Communication Systems
Analog Fault Diagnosis for Unpowered Circuit Boards
From Specification Validation to Hardware Testing: A Unified Method
Generated in Real-time Instant Process Statistics ("GRIPS"): Immediate, Tester-computed Test Statistics, Eliminating the Post-processing of Datalogs
Functional Testing of Microprocessor-like Architectures
Multi-Step Stress Test for Yield Improvement of 16Mbit EPROMs with Redundancy Scheme
A Novel Functional Test Generation Method for Processors Using Commercial ATPG
Test Mode Entry and Exit Methods for IEEE P1581 compliant devices
A Pragmatic Approach to the Design of Self-Testing Circuits
How are we going to test SoC's on a PCB?
Test Pattern Compaction in VLSI Testers
500-MHz Testing on a 100-MHz Tester
Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits
Study on High-Accuracy and Low-Cost Recycled FPGA Detection
Calculating the Effects of Linear Dependencies in m-Sequences Used as Test Stimuli
High-Bandwidth IJTAG over SSN
A Designer's View of Chip Test
Analyzing and Mitigating Sensing Failures in Spintronic-based Computing in Memory
SIA Roadmap: test must not limit future technologies
Design for failure analysis inserting replacement-type observation points for LVP
IEEE International Test Conference, ITC 2022, Anaheim, CA, USA, September 23-30, 2022
LLM-Aided In-Field Workload Generation for Detecting Silent Data Corruptions at Scale
Testing gigabit multilane SerDes interfaces with passive jitter injection filters
Managing in the ATE Business - Postcards from the Past, Lessons for the Future
Deterministic partitioning techniques for fault diagnosis in scan-based BIST
A Computerized Solution to the Fixture-Wiring Problem
Cost Containment for High-Volume Test of Multi-GB/s Ports
Maximizing scan pin and bandwidth utilization with a scan routing fabric
Maximization of power dissipation under random excitation for burn-in testing
Low Capture Power At-Speed Test with Local Hot Spot Analysis to Reduce Over-Test
Testing Computer Hardware through Data Compression in Space and Time
Boundary scan BIST methodology for reconfigurable systems
Linking Design Tools to In-Circuit Test Systems
Dedicated Autonomous Scan-Based Testing (DAST) for Embedded Cores
IEEE International Test Conference, ITC 2021, Anaheim, CA, USA, October 10-15, 2021
Multi-GHz interface devices should be tested using external test resources
Managing signal, power and thermal integrity for 3D integration
Design validation of RTL circuits using evolutionary swarm intelligence
A non-enumerative path delay fault simulator for sequential circuits
Improving Software Testability with Assertion Insertion
Energy-secure computer architectures
Automated Fault Diagnostic EB Tester and Its Application to a 40K-Gate VLSI Circuit
Impact of Negative Bias Temperature Instability on Product Parametric Drift
Defect tolerance for CNFET-based SRAMs
Integrating Automated Diagnosis into the Testing and Failure Analysis Operations
Improving the Accuracy of Test Compaction through Adaptive Test Update
Knowledge Representation in an In-Circuit Test Program Generator
Delay Testing Quality in Timing-Optimized Designs
An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited
High-Speed Pattern Generator and GaAs Pin : Electronics for a Gigahertz Production Test System
A Precision Measurement Technique for High Frequency Repetitive Signals
Efficient RAS support for die-stacked DRAM
Information and Material Flow Within a Production Test Cell
On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations
A diagnostic test generation system
Diagnosing CMOS bridging faults with stuck-at fault dictionaries
Hardware IP Trust Validation: Learn (the Untrustworthy), and Verify
IEA-Plugin: An AI Agent Reasoner for Test Data Analytics
A New Technique to Generate Test Sequences for Reconfigurable Scan Networks
Integrating boundary scan test into an ASIC design flow
Built-in constraint resolution
Marginal fault diagnosis based on e-beam static fault imaging with CAD interface
TRS and DTS : IC Test Result Standards
Low-Cost Fault Simulation: Why, When and How
Design-for-secure-test for crypto cores
DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors
Automatic Test Pattern Generation for Asynchronous Networks
Transforming an $n$-Detection Test Set into a Test Set for a Variety of Fault Models
Output in still, input in still
Multi-Frequency, Multi-Phase Scan Chain
EEPROM Memory: Threshold Voltage Built In Self Diagnosis
Outsourcing DFT: it can be done but it isn't easy
Analytical Testing of Data Processing Sections of Integrated CPUs
Sequential Circuit Diagnosis Based on Formal Verification Techniques
The concern for soft errors is not overblown
The Effectiveness of I DDQ , Functional and Scan Tests: How Many Fault Coverages Do We Need?
Test cycle power optimization for scan-based designs
Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level
Measurement ratio testing for improved quality and outlier detection
Low cost multisite testing of quadruple band GSM transceivers
Knowledge discovery and knowledge transfer in board-level functional fault diagnosis
Synthesizing for Scan Dependence in Built-In Self-Testable Desings
Rapid-response temperature control provides new defect screening opportunities
Low cost high-speed test data acquisition: Accurate period estimation driven signal reconstruction using incoherent subsampling
On-chip Programmable Capture for Accurate Path Delay Test and Characterization
Analyzing the Electromigration Challenges of Computation in Resistive Memories
Parametric Relationships for Self-Contained Test for Digital Avionics Functions
A Test and Maintenance Controller for a Module Containing Testable Chips
Scan array solution for testing power and testing time
RF Test 101: Defining the Problem, Finding Solutions
microSPARC TM : A Case Study of Scan-Based Debug
Testing and programming flash memories on assemblies during high volume production
Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis
Failing Frequency Signature Analysis
Why is Rigorous PCIe LTSSM Testing a Key to Robust and Reliable Systems?
Channel Card Architecture for Multimode Board Test Systems
Benchmarking an Expert System for Electronic Diagnosis
The Economics of Guardband Placement
Delay test of chip I/Os using LSSD boundary scan
Membrane Prove Technology for MCM Known-Good-Die
A study of faulty signatures using a matrix formulation
Testing Two Generations of HDTV Decoders - The Impact of Boundary-Scan
PBX System Test: Fast Functional Testing Without System Assembly
On Multiple Path Propagating Tests for Path Delay Faults
A rapid dither algorithm advances A/D converter testing
Design of integrated circuits fully testable for delay-faults and multifaults
Test generation for ultra-high-speed asynchronous pipelines
The Challenge of Configurable Logic Array Testing
A static noise impact analysis methodology for evaluating transient error effects in digital VLSI circuits
The Challenge of Testing the ARM CORTEX-A8 TM Microprocessor Core
Adaptive Self-Test for a Microprocessor
Testing CMOS Logic Gates for Realistic Shorts
AFS : An Approximate Fault Simulator
Automatic Test Generation for Generic Scan Designs
Cell Signal Measurement for High-Density DRAMs
Diagnosis Meets Physical Failure Analysis: How Long can we Succeed?
On generating high quality tests based on cell functions
Comparison of Delay Tests on Silicon
Logic Design Verification Using Automated Test Generation
Tackling test trade-offs from design, manufacturing to market using economic modeling
Testability, Debuggability, and Manufacturability Features of the UltraSPARC TM -I Microprocessor
Semiconductor Perspective on Test Standards
Built-In Self Test of CMOS-MEMS Accelerometers
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer Returns
Automatic Verification of Mixed-Signal ATE Test Programs using Device Variation
A Comparison of Test Requirements, Methods, and Results for Seven MCM Products
A Unified Approach to Test Generation and Test Data Volume Reduction
Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints
On diagnosable and tunable 3D clock network design for lifetime reliability enhancement
On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits
Testing Microprocessor Boards and Systems: A New Approach
AI-Enabled Board Level Vibration Testing: Unveiling The Physics of Degradation
Cross-layer refresh mitigation for efficient and reliable DRAM systems: A comparative study
Functionally-Possible Gate-Exhaustive Bridging Faults
The Case of Partial Scan
Search Strategy Switching: An Alternative to Increased Backtracking
Selective Optimization of Test for Embedded Flash Memory
Isolating Failures within VLSI Chips That Incorporate Signature Analysis and Set/Scan Techniques
Silicon evaluation of longest path avoidance testing for small delay defects
A Coherent and Efficient Approach to LSI Modeling and Testing for Integrated Circuit Users
What do you mean my Board Test stinks?
Oscillation Built-In Self Test (OBIST) Scheme for Functional and Structural Testing of Analog and Mixed-Signal Integrated Circuits
DE-LOC: Design validation and debugging under limited observation and control, pre- and post-silicon for mixed-signal systems
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
ATPG issues for board designs implementing boundary scan
Diagnosis and analysis of an analog circuit failure using time resolved emission microscopy
Asynchronous FIFO's Require Special Attention
RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST
Efficiency Measurement Method for Fully Integrated Voltage Regulators used in 4 th and 5 th Generation Intel® Core™ Microprocessors
Defining a Standard for Fault Simulator Evaluation
Accurate, Cost Effective Performance Screening of VLSI Circuit Designs
Optimizing Test Strategies for SONET/SDH/ATM Network Element Manufacturing
TAPs All Over My Chips
Automatic Scan Insertion and Test Generation for Asynchronous Circuits
Scan SerDes * for Multi-die Packages
Bridging Fault Diagnosis in the Absence of Physical Information
Are industrial test problems real problems? I thought research has resolved them all!
Test pattern generation in presence of unknown values based on restricted symbolic logic
A CCD Imager Test System
MHz Frequency Counting with VLSI Testers 420
A novel test flow for one-time-programming applications of NROM technology
The Case for Contract Manufacturing
CMOS Circuit Technology for Precise GHz Timing Generator
Parity prediction synthesis for nano-electronic gate designs
Backplane Test Bus Selection Criteria
IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future
Experimental Evaluation of Scan Tests for Bridges
In-field Data Collection System through Logic BIST for large Automotive Systems-on-Chip
Standard test interface language (STIL), extending the standard
Enhanced reduced pin-count test for full-scan design
Built-in Self-Calibration of On-chip DAC and ADC
Modular logic built-in self-test for IP cores
Coupling Electron-Beam Probing with Knowledge-Based Fault Localization
SCITT: Back to Basics in Mass Production Testing
Hardware Test Pattern Generation for Built-In Testing
Method for Diagnosing Channel Damage Using FPGA Transceiver
On-line testing of scalable signal processing architectures using a software test method
Warning: 100% Fault Coverage May Be Misleading!!
STIL P1450.4: A standard for test flow specification
An Exact Non-Enumerative Fault Simulator for Path-Delay Faults
High Time for Higher Level BIST
Empirical failure analysis and validation of fault models in CMOS VLSI
Networking verification process and environments: an extension of the product realization process for new network capabilities
A New Approach for PLL Characterization on Mixed Signal ATE
VLSI Package Reliability Risk Due to Accelerated Environmental Testing
A stereo audio Σ∑ ADC architecture with embedded SNDR self-test
Statistical Delay Fault Coverage and Defect Level for Delay Faults
A programmable BIST architecture for clusters of multiple-port SRAMs
Stuck-at Faults, PPMs Rejects or? What doe the SIA Roadmaps Say?
Test Length for Pseudo Random Testing
Secure design-for-debug for Systems-on-Chip
Very-Low-Voltage Testing for Weak CMOS Logic ICs
DELTEST: Deterministic Test Generation for Gate-Delay Faults
Test Width Compression for Built-In Self Testing
Aliasing-free Signature Analysis for RAM BIST
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment
An Application of Statistical Methods for System Failure Prediction
: A Testable PLA Design with Minimal Hardware and Test Set
Compression-aware pseudo-functional testing
On modeling faults in FinFET logic circuits
Managing the ASIC Design to Test Process
Boundary Scan Testing for Multichip Modules
Design for Testability and Test Generation for Static Redundancy System Level Fault-Tolerant Circuits
Look Who's Refueling the Technology Race
High throughput non-contact SiP testing
On-Line Testing Scheme for Clock's Faults
Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs
On-line Failure Detection in Memory Order Buffers
High Resolution, High Linearity Interpolating A/D Converter
Cutting the Cost of Test; the Value-added Way
Engineering Test Coverage on Complex Sockets
Testing clock distribution circuits using an analytic signal method
An IEEE 1149.1 Based Logic/Signature Analyzer in a Chip
High Quality ATPG for Delay Defects
Efficient compression of deterministic patterns into multiple PRPG seeds
Quasi-Oscillation Based Test for Improved Prediction of Analog Performance Parameters
Defect Analysis and Fault Modeling in MOS Technology
Eliminating product infant mortality failures using prognostic analysis
Functional testing of digital microfluidic biochips
Automated Generation of Device Test Software
Programmable At-Speed Array and Functional BIST for Embedded DRAM LSI
Low cost AM/AM and AM/PM distortion measurement using distortion-to-amplitude transformations
High-Speed Sampling Capability for a VLSI Mixed-Signal Tester
Machine Learning for Circuit Aging Estimation under Workload Dependency
Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains
A Novel Protection Technique for Embedded Memories with Optimized PPA
A comprehensive approach to the partial scan problem using implicit state enumeration
Computer-aided fault to defect mapping (CAFDM) for defect diagnosis
Mitigating the Effects of The DUT Interface board and Test System Parasitics in Gigabit-Plus Measurements
Very High Density Probing
POIROT: a logic fault diagnosis tool and its applications
Does Object-Oriented Programming Fit in the Real World of ATE?
IEEE P1687.1: Extending the Network Boundaries for Test
A new approach for massive parallel scan design
Advanced test methodology for complex SoCs
A Universal Technique for Accelerating Simulation of Scan Test Patterns
Fast Signature Computation for Linear Compactors
An Experiment on Intermittent-Failure Mechanisms
Arbitrary Waveform Generation with Absolute Duration Control
QED: Quick Error Detection tests for effective post-silicon validation
Can IC Test Learn from How a Tester is Tested
Using Target Faults To Detect Non-Tartget Defects
Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach
Testing bridges to nowhere - combining Boundary Scan and capacitive sensing
Understanding NTF components from the field
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
Inductive Contamination Analysis (ICA) with SRAM Application
Test Teaching
Machine Learning-Based DFT Recommendation System for ATPG QOR
Low-cost phase noise testing of complex RF ICs using standard digital ATE
Parallel Pseudorandom Sequences for Built-In Test
Integrating Emulation Techniques into General Purpose ATE
Digital serial communication device testing and its implications on automatic test equipment architecture
IEEE 1500 utilization in SOC design and test
Environmental Stress Testing with Boundary-Scan
Design of signature circuits based on weight distributions of error-correcting codes
Optimal analog trim techniques for improving the linearity of pipeline ADCs
Case study of a low power MTCMOS based ARM926 SoC : Design, analysis and test challenges
Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs
Engineering Curricula for "Meeting the Tests of Time"
Design of Cache Test Hardware on the HP PA8500
Virtual Memory Structures Facilitating Memory BIST Insertion In Complex SoCs
Low Contact-Force Fritting Probe Card Using Buckling Microcantilevers
NAND flash testing: A preliminary study on actual defects
"DFY and DFR are more important than DFT"
Testable Design for Adaptive Linear Equalizer in High-Speed Serial Links
On simultaneous shift- and capture-power reduction in linear decompressor-based test compression environment
Extending binary searches to two and three dimensions [IC testing]
Evolution of IEEE 1149.1 Addressable Shadow Protocol Devices
Improving Diagnosis Efficiency via Machine Learning
Built-In Verification Test
Detecting resistive shorts for CMOS domino circuits
Using a Synchronous High-Speed Sensor System to Diagnose Microprocessor Boards
Big data and test
A Fast and Efficient Graph-Based Methodology for Cell-Aware Model Generation
Analysis and mitigation or IR-Drop induced scan shift-errors
The Parallel-Test-Detect Fault Simulation Algorithm
Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications
Deterministic IDDQ diagnosis using a net activation based model