yusuke1997/dblp-id-title huggingface dataset:
An ATE architecture for implementing very high efficiency concurrent testing
Fault sharing in a copy-on-write based ATPG system
Packet-based JTAG for remote testing
Embedded Deterministic Test for Low-Cost Manufacturing Test
Manufacturing Pattern Development for the Alpha 21164 Microprocessor
OATT: Outlier Oriented Alternative Testing and Post-Manufacture Tuning of Mixed-Signal/RF Circuits and Systems
, An Efficient Test Vector Generation and Reduction Method for an LSI Digital Filter Circuit Using an Adaptive Search Technique
Optimization of burn-in test for many-core processors through adaptive spatiotemporal power migration
IEEE European Test Symposium (ETS)
Cognitive approach to support dynamic aging compensation
Introduction to Quantum Computation Reliability
Integration into the CAD Environment
Algorithm level recomputing with allocation diversity: a register transfer level time redundancy based concurrent error detection technique
Implementation of Model-Based Testing for Medium to High-Resolution Nyquist-Rate ADCs
MEMS fault model generation using CARAMEL
A Calculus of Testability Measure at the Functional Level
Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism
Design of High-Level Test Language for Digital LSI
A Software-Based Self-Test methodology for on-line testing of processor caches
When two worlds merge [test issues for system-level ICs]
Methods for improving test compression
Proceedings IEEE International Test Conference 1992, Discover the New World of Test and Design, Baltimore, Maryland, USA, September 20-24, 1992
Design of scan-testable CMOS sequential circuits
Lead Free Through Hole Technology (THT) and Contact Repeatability in In-Circuit Test
Harnessing process variations for optimizing wafer-level probe-test flow
An Accurate Bridging Fault Test Pattern Generator
Some New Techniques in Waveshape Capture and Analysis
DC_IATP : An Iterative Analog Circuit Test Generation Program for Generating DC Single Pattern Tests
A performance analysis system for MEMS using automated imaging methods
The Return of Asynchronous Logic
Multi-Gigahertz Digital Test Challenges and Techniques
Node sensitivity analysis for soft errors in CMOS logic
The Test Features of the Quad-Core AMD Opteron- Microprocessor
Quality Testing Requires Quality Thinking
Automated Measurement of 12 to 16-Bit Converters
VIVED : A Visual Vector Editor
Layering of the STIL extensions
A DFT technique for high performance circuit testing
Practical, non-invasive optical probing for flip-chip devices
Fault Model Extension for Diagnosing Custom Cell Fails
Embedded Test for a new Memory-Card Architecture
Practical application of energy consumption ratio test
Reducing Power Consumption in Memory ECC Checkers
A self-tuning architecture for buck converters based on alternative test
Novel crosstalk evaluation method for high-density signal traces using clock waveform conversion technique
Multi-output one-digitizer measurement
Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits
Application of Joint Time-Frequency Analysis in Mixed-Signal Testing
A 20 Bit Waveform Source for a Mixed Signal Automatic Test System
Low-Power Mode and IEEE 1149.1 Compliance - A Low-Power Solution
Overall Strategy for Online Clock System Checking Supporting Heterogeneous Integration
Built-In Checking of the Correct Self-Test Signature
Panel: "Board Test and ITC: What Does the Future Hold?"
An Organized Firmware Verification Environment for the Programmable Image DSP
What is the Path to Fast Fault Simulation?
DSP Measurement of Frequency
An Address Maskable Parallel Testing for Ultra High Density DRAMs
Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains
Generating March Tests Automatically
"Plug & Test" at System Level via Testable TLM Primitives
Case study of scan chain diagnosis and PFA on a low yield wafer
Explanation Capabilities in DEFT : A Design-For-Testability Expert System
Improving Total IC Design Quality Using Application Mode Testing
Predicting the Resolution of Scan Diagnosis
Artificial Intelligence and Testing
Low Power Scan Shift and Capture in the EDT Environment
BIST-Based Diagnosis of FPGA Interconnect
For Test Automation, Silicon is Free
Simulation Results of an Efficient Defect-Analysis Procedure
A distributed-multicore hybrid ATPG system
A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx
Deterministic Stellar BIST for In-System Automotive Test
On-chip Test and Repair of Memories for Static and Dynamic Faults
Test Equipment and Methods II
Double-Tree Scan: A Novel Low-Power Scan-Path Architecture
BIST scheme for RF VCOs allowing the self-correction of the cut
Functional Criticality Classification of Structural Faults in AI Accelerators
What we know after twelve years developing and deploying test data analytics solutions
Use of DFT Techniques In Speed Grading a 1GHz+ Microprocessor
A BIST Design of Structured Arrays with Fault-Tolerant Layout
X-Tolerant Tunable Compactor for In-System Test
Ultra-Pure High-Resolution Waveform Generation Using Low-Cost Data Converters with Dithering
Embedded self-testing checkers for low-cost arithmetic codes
A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects
Homegrown Tools and Equipment versus EDA and ATE Vendors: The Future of Design to Test Product Lines
Detecting Bridging Faults with Stuck-at Test Sets
An Implementation of IEEE 1149.1 to Avoid Timing Violations and Other Practical In-Compliance Improvements
Correlation of logical failures to a suspect process step
A General Purpose I DDQ Measurement Circuit
Observations of Supply-Voltage-Noise Dispersion in Sub-nsec
A structured approach to post-silicon validation and debug using symbolic quick error detection
Comparison of Aliasing Errors for Primitive and Non-Primitive Polynomials
Dynamic arbitrary jitter injection method for ≫6.5Gb/s SerDes testing
"Driver on a floppy" delivery of ATE instrumentation software
A High-Resolution Flash Time-to-Digital Converter and Calibration Scheme
Final Test of an LSI Populated System: A Pragmatic Approach
Delay fault simulation with bounded gate delay mode
A 250 MHz Shared-Resource VLSI Test System with High Pin Count and Memory Test Capability
Benchmarking DAT with the ITC'99 ATPG Benchmarks
Knowledge Transfer for Diagnosis Outcome Preview with Limited Data
Verification on Port Connections
ACCE: Automatic correction of control-flow errors
Bridging fault extraction from physical design data for manufacturing test development
Fault Modeling and Detection for Drowsy SRAM Caches
Benefits of ATE and Host Computer Networking
FPGA-based synthetic instrumentation for board test
A study of test quality/tester scan memory trade-offs using the SEMATECH test methods data
A run-pause-resume silicon debug technique with cycle granularity for multiple clock domain systems
"ATG" Test Generation Software
Fault Diagnosis in Designs with Convolutional Compactors
ITC Technical Paper Evaluation and Selection Process
Manufacturing-Test Simulator: A Concurrent-Engineering Tool for Boards and MCMs
Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults
Towards Machine-Learning-based Oracle-Guided Analog Circuit Deobfuscation
Detection of Low Power Trojans in Standard Cell Designs using Built-in Current Sensors
Improving Power, Performance and Area with Test: A Case Study
Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times
Testability Using Random Access Test Register
Synthesis of pattern generators based on cellular automata with phase shifters
Testability Features of the MC68HC11
Trouble-Shooting: A Key to Process Improvement
Removing JTAG Bottlenecks in System Interconnect Test
An Analysis of the Die Testing Process Using Taguchi Techniques and Circuit Diagnostics
Software Testing - The State of the Practice
Process defect trends and strategic test gaps
Virtual Test Development Using Pre-Silicon Verification Environment
Generating Test Signals for Noise-Based NPR/ACPR Type Tests in Production
Process-Aggravated Noise (PAN): New Validation and Test Problems
SIA Roadmaps: Sunset Boulevard for l_DDQ
Application of Statistical Techniques to Critical System Parameters
Theory, model, and applications of non-Gaussian probability density functions for random jitter/noise with non-white power spectral densities
Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs
IDA: A Tool for Computer-Aided Failure Analysis
Integrated Functional/Structural Timing for Digital Simulation
On-line testing and recovery in TMR systems for real-time applications
On the Testable Design of Bilateral Bit-Level Systolic Arrays
Classifying Bad Chips and Ordering Test Sets
An Algorithm to Generate Tests for MOS Circuits at the Switch Level
Digital Scan and ATPG for Analog Circuits
How are we going to test socs on a board? the users viewpoint
Testing the Enterprise IBM System/390 TM Multi Processor
Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations
Panel Synopsis - How (In)Adequate is One Time Testing?
March AB, March AB1: new March tests for unlinked dynamic memory faults
Production I DDQ Testing with Passive Current Compensation
Configuring Flip-Flops to BIST Registers
A Novel Pattern Generation Framework for Inducing Maximum Crosstalk Effects on Delay-Sensitive Paths
Access time minimization in IEEE 1687 networks
Low cost at-speed testing using On-Product Clock Generation compatible with test compression
Testing the 400-MHz IBM Generation-4 CMOS Chip
Semi-supervised Wafer Map Pattern Recognition using Domain-Specific Data Augmentation and Contrastive Learning
Technique to Detect RF Interface and Contact Issues During Production Testing
Reducing Measurement Uncertainty in a DSP-Based Mixed-Signal Test Environment without Increasing Test Time
Minimizing outlier delay test cost in the presence of systematic variability
Testing and Characterizing Jitter in 100BASE-TX and 155.52 Mbit/S ATM Devices with a 1 Gsample/s AWG in an ATE System
Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networks
DSP Calibration for Accurate Time Waveform Reconstruction
Debug of the CELL Processor: Moving the Lab into Silicon
Wrapper design for embedded core test
A high accuracy high throughput jitter test solution on ATE for 3GBPS and 6gbps serial-ata
Application of Cell-Aware Test on an Advanced 3nm CMOS Technology Library
Board Test Coverage: The Value of Prediction and How to Compare Numbers
Scan Path and Beyond : The Road to Improved ASIC Testability
Low-cost wideband periodic signal reconstruction using incoherent undersampling and back-end cost optimization
The Increasing Importance of On-line Testing to Ensure High-Reliability Products
Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ
Test data compression for IP embedded cores using selective encoding of scan slices
Fault grading the Intel 80486
Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor
Transient Thermal Characteristics of VLSI Devices : Evaluation and Application
Modeling the probability of defect excitation for a commercial IC with implications for stuck-at fault-based ATPG strategies
An effort-minimized logic BIST implementation method
A Test Generation Method for Sequential Circuits Based on Maximum Utilization of Internal States
Navigating Test Access in Systems
Improved Workstation/Tester Interface Is the Key to the Quality of Test-Program Generation
GLFSR - A New Test Pattern Generator for Built-In Self-Test
Fault Coverage of DC Parametric Tests for Embedded Analog Amplifiers
ACE-Pro: Reduction of Functional Errors with ACE Propagation Graph
Efficient Logic Verification and Test Validation for MOS LSI Circuits
A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator
Octal-Site EVM Tests for WLAN Transceivers on "Very" Low-Cost ATE Platforms
Hierarchical Functional-Fault Simulation for High-Level Synthesis
An ATPG Driver Selection Algorithm for Interconnect Test with Boundary Scan
Analysis and Detection of Timing Failures in an Experimental Test Chip
Test Compression for FPGAs
A Hierarchical Environment for Interactive Test Engineering
Chasing Front-End-Of-Line Defects with Cell-Aware Diagnostics in High-Volume Manufacturing
Concurrent hardware Trojan detection in wireless cryptographic ICs
OCTANE: On-Chip Telemetry-based Anomaly Notification Engine
In-Circuit Analog Component Testing at High Frequencies
Testing of Neuromorphic Circuits: Structural vs Functional
Realization of an efficient design verification test used on a microinstruction controlled self test
BIST of I/O circuit parameters via standard boundary scan
BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study
Algorithms for Cost Optimised Test Strategy Selection
A memory yield improvement scheme combining built-in self-repair and error correction codes
Mining AC delay measurements for understanding speed-limiting paths
Built-In Self-Test for High-Speed Data-Path Circuitry
Test-Access Solutions for Three-Dimensional SOCs
Power-Aware Test Scheduling for Memory BIST
Increasing Test Throughput Through the Implementation of Parallel Test on a 16-Bit Multimedia Audio CODEC
An Electronic Module for 12.8 Gbps Multiplexing and Loopback Test
The path to one-picosecond accuracy
Triggering and clocking architecture for mixed signal test
A Low-Cost Massively-Parallel Interconnect Test Method for MCM Substrates
A Picosecond Accuracy Timing Error Compensation Technique in TDR Measurement
'Shifting-left' Zero Defect Scan Test Development to Launch Automotive PPM-ready Products
Achieving Board-Level BIST Using the Boundary-Scan Master
A new method for jitter decomposition through its distribution tail fitting
CVT-FERT : Automatic Generator of Analytical Faults at Register Transfer Level from Electrical and Topological Descriptions
Industry Evaluation of Reversible Scan Chain Diagnosis
Hybrid Static Learning for ATPG
A Benchmark Suite to Evaluate DNN's Resilience
IC Mixed-Signal BIST: Separating Facts from Fiction
An Information Processing Software System for ATE
Structured CBIST in ASICs
A robust method for identifying a deterministic jitter model in a total jitter distribution
Design Rewiring Using ATPG
Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register
Toward understanding "Iddq-only" fails
RNA: Advanced phase tracking method for digital waveform reconstruction
Challenges for High Volume Testing of Embedded IO Interfaces in Disaggregated Microprocessor Products
Fault Simulation at the Architectural Level
Car IC test changing but the same quality goal
Why, I DDQ ? [CMOS IC testing]
Documentation for Testability : The Supplier's Responsibility to the User
A general testing method for digital microfluidic biochips under physical constraints
Logic characterization vehicle design for maximal information extraction for yield learning
Testing the Configurable Analog Blocks of Field Programmable Analog Arrays
Advantages of High-Level Test Synthesis over Design for Test
A low cost test data compression technique for high n-detection fault coverage
The Self-Assist Test Approach to Embedded Arrays
Efficient Design of System Test: A Layered Architecture
Package test interface fixture considering low cost solution, high electrical performance, and compatibility with fine pitch packages
When "almost" is good enough: a fresh look at DSP clock rates
Performance Driven BIST Technique for Random Logic
Built-in Testing of Memory Using On-chip Compact Testing Scheme
Optical Communication Channel Test Using BIST Approaches
The Use of Linear Models for the Efficient and Accurate Testing of A/D Converters
Word line pulsing technique for stability fault detection in SRAM cells
A Cell-aware Transistor State Stress Model and its Application for Quality Measurement
Software Testing, the State of the Practice
Test Access Mechanism for Multiple Identical Cores
Low Overhead Delay Testing of ASICS
Electron-Beam Testing of VLSI Dyrnamic RAMs
Data Analysis Techniques for CMOS Technology Characterization and Product Impact Assessment
A Test-System Architecture to Reduce Transmission Line Effects During High-Speed Testing
HITEST Test Generation System Interfaces
Minimal Supervision, Maximum Accuracy: TabPFN for Microcontroller Performance Prediction
COM (Cost Oriented Memory) Testing
Logic proximity bridges
Intel and the Myths of Test
On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction
Online timing variation tolerance for digital integrated circuits
Flying probe test systems: capabilities for effective testing
Panel synopsis: reducing high-speed/RF test cost: guaranteed by design or guaranteed to fail?
Integration of Design, Manufacturing and Testing
Power integrity control of ATE for emulating power supply fluctuations on customer environment
Using timing flexibility of automatic test equipment to complement X-tolerant test compression techniques
The Cost and Speed Barriers in LSI/VLSI Testing : Can They Be Overcome By Testability Design ?
Concurrent Control of Multiple BIT Structures
A Routing Testing of a VLSI Massively Parallel Machine Based on IEEE 1149.1
Logical Models of Physical Failures
Fault-Tolerant Neuromorphic Computing Systems
A high-speed pin-memory architecture using multiport dynamic RAMs
A tester architecture suitable for MEMS calibration and testing
Addressable test ports an approach to testing embedded cores
Using the Right Tools and Techniques leads to Successful Testing of MCMs
Multiple path sensitization for hierarchical circuit testing
Optical and Electrical Testing of Latchup in I/O Interface Circuits
An Enhanced Analog/Digital GPIB Based PCB Test System
Evaluation techniques of frequency-dependent I/Q imbalances in wideband quadrature mixers
Board Test Coverage Needs to be Standardized
TGEN: Flexible Timing Generator Architecture
An On-Chip Double-Bit Error-Correcting Code for Three-Dimensional Dynamic Random-Access Memory
A New Fault Model and Testing Technique for CMOS Devices
A Unified Test Plan for LSI or VLSI Components
An improved procedure to test CMOS ICs for latch-up
Application-Dependent Diagnosis of FPGAs
Integrating Scan into Hierarchical Synthesis Methodologies
Burn-in reduction using principal component analysis
Consideration While Introducing a Test Data Management System to the Factory Floor
Memory Interconnection Test at Board Level
Driver/Sensor Design for High-Performance ATE
On pinpoint capture power management in at-speed scan test generation
Behavioral-Test Generation using Mixed-Integer Non-linear Programming
The evolution of a system test process [for Motorola GSM products]
Internal Diagnostics for Tektronix Graphics Terminals
Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICs
Low power multi-chains encoding scheme for SoC in low-cost environment
Transformation of multiple fault models to a unified model for ATPG efficiency enhancement
A PVT-Resilient No-Touch DFT Methodology for Prebond TSV Testing
On Multiple Fault Coverage and Aliasing Probability Measures
A structured test re-use methodology for core-based system chips
A comprehensive production test solution for 1.5Gb/s and 3Gb/s serial-ATA - based on AWG and undersampling techniques
Self-Testing of Multichip Logic Modules
A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms
Pattern generation tools for the development of memory core test patterns for Rambus devices
Parity-Based Concurrent Error Detection in Symmetric Block Ciphers
DFT Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs
Why is less information from logic simulation more useful in fault simulation?
An Algorithmic Branch and Bound Method for PLA Test Pattern Generation
Automated Effective-Bit Characterization of Waveform Digitizers
JTAG system test in a MicroTCA world
Making cause-effect cost effective: low-resolution fault dictionaries
On Synthesizing Circuits With Implicit Testability Constraints
A Testing Methodology for New-Generation Specialty Memory Devices
Coupling Coefficients for Signal Lines Separated by Ground Lines on PC Boards
Developing a Testing Maturity Model for Software Test Process Evaluation and Improvement
Analysis of Gate Array Failures Using Functional ATE
A Framework for Design of Self-Repairing Digital Systems
A New Technique for Testing Settling Time in a Production Environment
ICTEST : A Unified System for Functional Testing and Simulation of Digital ICs
Testability Strategy of the ALPHA AXP 21164 Microprocessor
Buying time for the stuck-at fault model
A functional test of 2-GHz/4-GHz RF digital communication device using digital tester
qATG: Automatic Test Generation for Quantum Circuits
Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction
Terabit-per-second automated digital testing
The Economics of Parallel Testing
X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction
Identification of systematic yield limiters in complex ASICS through volume structural test fail data visualization and analysis
Optimal Space Compaction of Test Responses
Test Outsourcing - A Subcontract Manufacturer's Perspective
Functional Testing of Current Microprocessors (applied to the Intel i860 TM )
Low cost dynamic error detection in linearity testing of SAR ADCs
High Time For High Level ATPG
A Proposed Method of Accessing 1149.1 in a Backplane Environment
Built-In Self-Test Considerations in a High-Performance, General-Purpose Processor
A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis
Test Generation for MOS Circuits
New Testing Equipment for SMT PC Boards
Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing
Creating A Mixed-Signal Simulation Capability for Concurrent IC Design and Test Program Development
Mixed-mode ATPG under input constraints
Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers
Automated 1.5 GHz Sonet Characterization
Use of BIST in Sun Fire TM servers
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm
Realistic-Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits
Proposed Test Method to Prove Software Having a Vector Space Behavior
An Architecture for a Reconfigurable IEEE 1149.n Master Controller Board
Deception by design: fooling ourselves with gate-level models
Efficient observation-point insertion for diagnosability enhancement in digital circuits
RF (gigahertz) ATE production testing on wafer: options and tradeoffs
An advanced test system architecture for synchronous and asynchronous control of mixed signal device testing
Performance Assurance of Memories Embedded in VLSI Chips
The Manic Depression of Microprocessor Debug
Using Boundary Scan Description Language in Design
Testing Resistive Memories: Where are We and What is Missing?
Low hardware overhead scan based 3-weight weighted random BIST
SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts
Selecting PXI Architecture for Board (System) Functional Test
VICTOR : A Fast VLSI Testability Analysis Program
Physical DFT for High Coverage of Realistic Faults
Test Equipment and Methods I
Design Verification Problems: Test To The Rescue?
Defects, Fault Modeling, and Test Development Framework for FeFETs
Cell-aware Production test results from a 32-nm notebook processor
Delay testing considering power supply noise effects
Self-Test of Random Access Memories
A development platform and electronic modules for automated test up to 20 Gbps
Trace signal selection for debugging electrical errors in post-silicon validation
Modeling Challenge Covariances and Design Dependency for Efficient Attacks on Strong PUFs
Test Synthesis: From Wishful Thinking to Reality
Fast and accurate linearity test for DACs with various architectures using segmented models
From Hardware to Software Testability
Scan Power Reduction Through Test Data Transition Frequency Analysis
Issues in Optimizing the Test Process - A Telecom Case Study