yusuke1997/dblp-id-title huggingface dataset:
NeuroEngine: a hardware-based event-driven simulation system for advanced brain-inspired computing
Optimizing Quantum Circuits, Fast and Slow
Untangle: A Principled Framework to Design Low-Leakage, High-Performance Dynamic Partitioning Schemes
Proceedings of the 1st Workshop on Architectural and System Support for Improving Software Dependability, ASID 2006, San Jose, California, USA, October 21, 2006
DejaVu: accelerating resource allocation in virtualized environments
ad-heap: an Efficient Heap Data Structure for Asymmetric Multicore Processors
Discerning the dominant out-of-order performance advantage: is it speculation or dynamism?
Accelerating Number Theoretic Transform with Multi-GPU Systems for Efficient Zero Knowledge Proof
CryoCache: A Fast, Large, and Cost-Effective Cache Architecture for Cryogenic Computing
Speculative synchronization: applying thread-level speculation to explicitly parallel applications
ASPLOS-V Proceedings - Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, October 12-15, 1992
Toward molecular programming with DNA
TaintEMU: Decoupling Tracking from Functional Domains for Architecture-Agnostic and Efficient Whole-System Taint Tracking
Virgo: Cluster-level Matrix Unit Integration in GPUs for Scalability and Energy Efficiency
Energy-efficient work-stealing language runtimes
ParallelJS: An Execution Framework for JavaScript on Heterogeneous Systems
Quantifying NUMA and contention effects in multi-GPU systems
MOD: Minimally Ordered Durable Datastructures for Persistent Memory
Context-Sensitive Fencing: Securing Speculative Execution via Microcode Customization
TPC: Target-Driven Parallelism Combining Prediction and Correction to Reduce Tail Latency in Interactive Services
Atomicity and visibility in tiny embedded systems
Selectively Uniform Concurrency Testing
Micro-Optimization of Floating Point Operations
TAPAS: Thermal- and Power-Aware Scheduling for LLM Inference in Cloud Platforms
RPG 2 : Robust Profile-Guided Runtime Prefetch Generation
Aikido: accelerating shared data dynamic analyses
Compiler-Controlled Memory
Proceedings of 3rd Workshop on General Purpose Processing on Graphics Processing Units, GPGPU 2010, Pittsburgh, Pennsylvania, USA, March 14, 2010
Hopps: Leveraging Sparsity to Accelerate Automata Processing
Q100: the architecture and design of a database processing unit
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
SoftFLASH: Analyzing the Performance of Clustered Distributed Virtual Shared Memory
FLAT: An Optimized Dataflow for Mitigating Attention Bottlenecks
VSync: push-button verification and optimization for synchronization primitives on weak memory models
REF: resource elasticity fairness with sharing incentives for multiprocessors
Joint optimization of idle and cooling power in data centers while maintaining response time
Surpassing the TLB Performance of Superpages with Less Operating System Support
Hardware and Software Support for Efficient Exception Handling
RecShard: statistical feature-based memory optimization for industry-scale neural recommendation
SmartMem: Layout Transformation Elimination and Adaptation for Efficient DNN Execution on Mobile
Exploiting Human Color Discrimination for Memory- and Energy-Efficient Image Encoding in Virtual Reality
StrongBox: Confidentiality, Integrity, and Performance using Stream Ciphers for Full Drive Encryption
An Analysis of a Mesa Instruction Set Using Dynamic Instruction Frequencies
pulse: Accelerating Distributed Pointer-Traversals on Disaggregated Memory
Virtuoso: Enabling Fast and Accurate Virtual Memory Research via an Imitation-based Operating System Simulation Methodology
SmoothE: Differentiable E-Graph Extraction
K2: a mobile operating system for heterogeneous coherence domains
Amanda: Unified Instrumentation Framework for Deep Neural Networks
Characterizing processor thermal behavior
Hurdle: Securing Jump Instructions Against Code Reuse Attacks
Transparent mutable replay for multicore debugging and patch validation
MV-RLU: Scaling Read-Log-Update with Multi-Versioning
Mallacc: Accelerating Memory Allocation
Architectural Support for Fast Symmetric-Key Cryptography
A VLIW Architecture for a Trace Scheduling Compiler
Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing
LCM: Memory System Support for Parallel Language Implementation
Felix: Optimizing Tensor Programs with Gradient Descent
RANGE-BLOCKS: A Synchronization Facility for Domain-Specific Architectures
The Operating System and Language Support Features of the BELLMAC-32 Microprocessor
Automated OS-level Device Runtime Power Management
Architectural Support for Containment-based Security
A Reconfigurable Energy Storage Architecture for Energy-harvesting Devices
Atalanta: A Bit is Worth a "Thousand" Tensor Values
Earth+: On-Board Satellite Imagery Compression Leveraging Historical Earth Observations
Consistency Management for Virtually Indexed Caches
Kard: lightweight data race detection with per-thread memory protection
Coding Guidelines for Pipelined Processors
Performance and Architectural Evaluation of the PSI Machine
SparseCore: stream ISA and processor specialization for sparse computation
A Software Caching Runtime for Embedded NVRAM Systems
Ensuring operating system kernel integrity with OSck
Analyzing multicore dumps to facilitate concurrency bug reproduction
Secure program execution via dynamic information flow tracking
A Real-Time Support Processor for Ada Tasking
Programming with transactional coherence and consistency (TCC)
uBFT: Microsecond-Scale BFT using Disaggregated Memory
Comprehending performance from real-world execution traces: a device-driver case
Introducing 'Bones': a parallelizing source-to-source compiler based on algorithmic skeletons
Paragon: collaborative speculative loop execution on GPU and CPU
Pruner: A Draft-then-Verify Exploration Mechanism to Accelerate Tensor Program Tuning
The Effect of Sharing on the Cache and Bus Performance of Parallel Programs
Lazy Release Persistency
Locality Transformations for Nested Recursive Iteration Spaces
Liquid Silicon-Monona: A Reconfigurable Memory-Oriented Computing Fabric with Scalable Multi-Context Support
Customized Architecture Technology for High Performance Computing
A Midsummer Night's Tree: Efficient and High Performance Secure SCM
BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge
JSONSki: streaming semi-structured data with bit-parallel fast-forwarding
Pythia: Compiler-Guided Defense Against Non-Control Data Attacks
GPUfs: integrating a file system with GPUs
Scalable Processing of Contemporary Semi-Structured Data on Commodity Parallel Processors - A Compilation-based Approach
Unstructured grid applications on GPU: performance analysis and improvement
DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings
Khuzdul: Efficient and Scalable Distributed Graph Pattern Mining Engine
Parallel multiclass classification using SVMs on GPUs
TaxDC: A Taxonomy of Non-Deterministic Concurrency Bugs in Datacenter Distributed Systems
TaskStream: accelerating task-parallel workloads by recovering program structure
Data Buffering: Run-Time Versus Compile-Time Support
S2E: a platform for in-vivo multi-path analysis of software systems
Improving the performance of trace-based systems by false loop filtering
HAMMER: boosting fidelity of noisy Quantum circuits by exploiting Hamming behavior of erroneous outcomes
Limits on Multiple Instruction Issue
PIM-STM: Software Transactional Memory for Processing-In-Memory Systems
Precise Miss Analysis for Program Transformations with Caches of Arbitrary Associativity
FreePart: Hardening Data Processing Software via Framework-based Partitioning and Isolation
Firefly: A Multiprocessor Workstation
The Architectural Implications of Autonomous Driving: Constraints and Acceleration
SD-PCM: Constructing Reliable Super Dense Phase Change Memory under Write Disturbance
Software Mitigation of Crosstalk on Noisy Intermediate-Scale Quantum Computers
CTXNL: A Software-Hardware Co-designed Solution for Efficient CXL-Based Transaction Processing
D-VSync: Decoupled Rendering and Displaying for Smartphone Graphics
Parity Declustering for Continuous Operation in Redundant Disk Arrays
Dynamic dead-instruction detection and elimination
Livia: Data-Centric Computing Throughout the Memory Hierarchy
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance
Don't Repeat Yourself! Coarse-Grained Circuit Deduplication to Accelerate RTL Simulation
Everywhere All at Once: Co-Location Attacks on Public Cloud FaaS
TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory
Hardware support for fine-grained event-driven computation in Anton 2
VarSaw: Application-tailored Measurement Error Mitigation for Variational Quantum Algorithms
FINGERS: exploiting fine-grained parallelism in graph mining accelerators
The TrieJax Architecture: Accelerating Graph Operations Through Relational Joins
eNVy: A Non-Volatile, Main Memory Storage System
Affinity-based Optimizations for TFHE on Processing-in-DRAM
Static memory management within bytecode languages on multicore systems
Hassert: Hardware Assertion-Based Verification Framework with FPGA Acceleration
Integrated network interfaces for high-bandwidth TCP/IP
EnCore: exploiting system environment and correlation information for misconfiguration detection
TelaMalloc: Efficient On-Chip Memory Allocation for Production Machine Learning Accelerators
Transactionalizing legacy code: an experience report using GCC and Memcached
Thread Level Parallelism and Interactive Performance of Desktop Applications
Data Cache for Intermittent Computing Systems with Non-Volatile Main Memory
FlexOS: towards flexible OS isolation
SecCMP: a secure chip-multiprocessor architecture
The Mahler Experience: Using and Intermediate Language as the Machine Description
Minnow: Lightweight Offload Engines for Worklist Management and Worklist-Directed Prefetching
Better Than Worst-Case Decoding for Quantum Error Correction
On-Line Data Compression in a Log-Structured File System
Characterizing a Memory Allocator at Warehouse Scale
Scatter-and-Gather Revisited: High-Performance Side-Channel-Resistant AES on GPUs
Palantir: Hierarchical Similarity Detection for Post-Deduplication Delta Compression
Rhythmic pixel regions: multi-resolution visual sensing system towards high-precision visual computing at low power
Big Data Analytics and Intelligence at Alibaba Cloud
Specifying and checking semantic atomicity for multithreaded programs
Recording shared memory dependencies using strata
ECOSystem: managing energy as a first class operating system resource
MineSweeper: a "clean sweep" for drop-in use-after-free prevention
RTL-Repair: Fast Symbolic Repair of Hardware Design Code
DeepSniffer: A DNN Model Extraction Framework Based on Learning Architectural Hints
QUEST: systematically approximating Quantum circuits for higher output fidelity
Efficient Superscalar Performance Through Boosting
Energy Efficient Convolutions with Temporal Arithmetic
Proceedings of the 3rd Workshop on Programming Languages and Operating Systems: Linguistic Support for Modern Operating Systems, PLOS 2006, San Jose, California, USA, October 22, 2006
Computing with time: microarchitectural weird machines
Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines
Accelerating financial applications on the GPU
Synchronization without Contention
AnA: An Attentive Autonomous Driving System
An Architectural Alternative to Optimizing Compilers
CARAT CAKE: replacing paging via compiler/kernel cooperation
MicroVSA: An Ultra-Lightweight Vector Symbolic Architecture-based Classifier Library for Always-On Inference on Tiny Microcontrollers
CrossPrefetch: Accelerating I/O Prefetching for Modern Storage
Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures
Fast and Scalable VMM Live Upgrade in Large Cloud Infrastructure
SDF: software-defined flash for web-scale internet storage systems
Failure-Atomic Persistent Memory Updates via JUSTDO Logging
SparseTIR: Composable Abstractions for Sparse Compilation in Deep Learning
Architectural Support for Multilanguage Parallel Programming on Heterogeneous Systems
Which Graph Representation to Select for Static Graph-Algorithms on a CUDA-capable GPU
A Hypervisor for Shared-Memory FPGA Platforms
Virtual Memory Primitives for User Programs
Mementos: system support for long-running computation on RFID-scale devices
ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, March 16-20, 2020
Implementing the PGI Accelerator model
Paraprox: pattern-based approximation for data parallel applications
A CPU: GPU Hybrid Implementation and Model-Driven Scheduling of the Fast Multipole Method
Statistical robustness of Markov chain Monte Carlo accelerators
Past-Future Scheduler for LLM Serving under SLA Guarantees
iThreads: A Threading Library for Parallel Incremental Computation
Speculative hardware/software co-designed floating-point multiply-add fusion
Towards "Full Containerization" in Containerized Network Function Virtualization
Accelerating SQL database operations on a GPU with CUDA
A Formal Analysis of the NVIDIA PTX Memory Consistency Model
Parallelizing security checks on commodity hardware
Accurate and efficient filtering for the Intel thread checker race detector
High-Performance Transactions for Persistent Memories
Protecting Cryptographic Code Against Spectre-RSB: (and, in Fact, All Known Spectre Variants)
Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2016, Atlanta, GA, USA, April 2-6, 2016
MetaSapiens: Real-Time Neural Rendering with Efficiency-Aware Pruning and Accelerated Foveated Rendering
Addressing shared resource contention in multicore processors via scheduling
Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign
Active Disks: Programming Model, Algorithms and Evaluation
Capturing Dynamic Memory Reference Behavior with Adaptive Cache Topology
Speculative interference attacks: breaking invisible speculation schemes
8-bit Transformer Inference and Fine-tuning for Edge Accelerators
NeuPIMs: NPU-PIM Heterogeneous Acceleration for Batched LLM Inferencing
VDom: Fast and Unlimited Virtual Domains on Multiple Architectures
Efficient Lossless Compression of Scientific Floating-Point Data on CPUs and GPUs
Seventh Workshop on General Purpose Processing Using GPUs, GPGPU-7, Salt Lake City, UT, USA, March 1, 2014
DrGPUM: Guiding Memory Optimization for GPU-Accelerated Applications
Design and evaluation of compiler algorithms for pre-execution
Using ARM trustzone to build a trusted language runtime for mobile applications
The Fuzzy Barrier: A Mechanism for High Speed Synchronization of Processors
TLP: A Deep Learning-Based Cost Model for Tensor Program Tuning
Quantum Circuits for Dynamic Runtime Assertions in Quantum Computation
Efficient online validation with delta execution
Distributed SAR Image Change Detection with OpenCL-Enabled Spark
Leak pruning
DDOS: taming nondeterminism in distributed systems
ViK: practical mitigation of temporal memory safety violations through object ID inspection
Atomic-free irregular computations on GPUs
WSMeter: A Performance Evaluation Methodology for Google's Production Warehouse-Scale Computers
LeaFTL: A Learning-Based Flash Translation Layer for Solid-State Drives
BCD deduplication: effective memory compression using partial cache-line deduplication
T3: Transparent Tracking & Triggering for Fine-grained Overlap of Compute & Collectives
RESCQ: Realtime Scheduling for Continuous Angle Quantum Error Correction Architectures
Characterizing Power Management Opportunities for LLMs in the Cloud
Performance Counters and State Sharing Annotations: a Unified Approach to Thread Locality
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2018, Williamsburg, VA, USA, March 24-28, 2018
FaaSGraph: Enabling Scalable, Efficient, and Cost-Effective Graph Processing with Serverless Computing
Coyote: A Compiler for Vectorizing Encrypted Arithmetic Circuits
An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors
Efficient processor support for DRFx, a memory model with exceptions
No "power" struggles: coordinated multi-level power management for the data center
hi CUDA: a high-level directive-based language for GPU programming
Modeling GPU-CPU workloads and systems
ElasticFlow: An Elastic Serverless Training Platform for Distributed Deep Learning
SOML Read: Rethinking the Read Operation Granularity of 3D NAND SSDs
Noise-Aware Dynamical System Compilation for Analog Devices with Legno
DreamWeaver: architectural support for deep sleep
Petal: Distributed Virtual Disks
Hardware Support for Fast Capability-based Addressing
A Software Instruction Counter
Accelerating linpack with CUDA on heterogenous clusters
Integration of Compression and Caching for a Two-Level File System
A full-stack search technique for domain optimized deep learning accelerators
A Variable Instruction Stream Extension to the VLIW Architecture
FUYAO: DPU-enabled Direct Data Transfer for Serverless Computing
Syno: Structured Synthesis for Neural Operators
Navigating the Dynamic Noise Landscape of Variational Quantum Algorithms with QISMET
An Experimental Comparison Between Genetic Algorithm and Particle Swarm Optimization in Spark Performance Tuning
Fast On-device LLM Inference with NPUs
An Empirical Analysis of Instruction Repetition
Dependable != unaffordable
Specifying and dynamically verifying address translation-aware memory consistency
CoolEdge: hotspot-relievable warm water cooling for energy-efficient edge datacenters
Time-optimal Qubit mapping
Enabling task-level scheduling on heterogeneous platforms
Hardware Support for Dynamic Management of Compiler-Directed Computation Reuse
Debugger Toolchain Validation via Cross-Level Debugging
Performance Evaluation and Optimization Mechanisms for Inter-operable Graphics and Computation on GPUs
Cyrus: unintrusive application-level record-replay for replay parallelism
Compiler-driven FPGA virtualization with SYNERGY
BypassD: Enabling fast userspace access to shared SSDs
Vela: A Virtualized LLM Training System with GPU Direct RoCE
Marionette: A RowHammer Attack via Row Coupling
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
A mapping path for multi-GPGPU accelerated computers from a portable high level programming abstraction
Tags and Type Checking in Lisp: Hardware and Software Approaches
Skip It: Take Control of Your Cache!
Program Optimization for Instruction Caches
Pallas: Semantic-Aware Checking for Finding Deep Bugs in Fast Path
ORIANNA: An Accelerator Generation Framework for Optimization-based Robotic Applications
Minotaur: Adapting Software Testing Techniques for Hardware Errors
TAROT: A CXL SmartNIC-Based Defense Against Multi-bit Errors by Row-Hammer Attacks
ReCA: Integrated Acceleration for Real-Time and Efficient Cooperative Embodied Autonomous Agents
TeraHeap: Reducing Memory Pressure in Managed Big Data Frameworks
Relyzer: exploiting application-level fault equivalence to analyze application resiliency to transient faults
Targeted Automatic Integer Overflow Discovery Using Goal-Directed Conditional Branch Enforcement
Sheaved Memory: Architectural Support for State Saving and Restoration in Paged Systems
Aqua: Network-Accelerated Memory Offloading for LLMs in Scale-Up GPU Domains
GPU Concurrency: Weak Behaviours and Programming Assumptions
EagleEye: Nanosatellite constellation design for high-coverage, high-resolution sensing
Automatic Tracing in Task-Based Runtime Systems
Fine-grained fault tolerance using device checkpoints
HERA: Hardware evolution over reconfigurable architectures
Qompress: Efficient Compilation for Ququarts Exploiting Partial and Mixed Radix Operations for Communication Reduction
Streamware: programming general-purpose multicore processors using streams
Hybrid NOrec: a case study in the effectiveness of best effort hardware transactional memory
Toleo: Scaling Freshness to Tera-scale Memory Using CXL and PIM
Skyway: Connecting Managed Heaps in Distributed Big Data Systems
In-Storage Domain-Specific Acceleration for Serverless Computing
The Effect of Instruction Set Complexity on Program Size and Memory Performance
HawkEye: Efficient Fine-grained OS Support for Huge Pages
Medusa: Accelerating Serverless LLM Inference with Materialization
Performance Isolation: Sharing and Isolation in Shared-Memory Multiprocessors
Fractal: Joint Multi-Level Sparse Pattern Tuning of Accuracy and Performance for DNN Pruning
Moonwalk: NRE Optimization in ASIC Clouds
ProRace: Practical Data Race Detection for Production Use
LimitLESS Directories: A Scalable Cache Coherence Scheme
Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2011, Newport Beach, CA, USA, March 5-11, 2011
The Case for a Single-Chip Multiprocessor
Evanesco: Architectural Support for Efficient Data Sanitization in Modern Flash-Based Storage Systems
Benchmarking, analysis, and optimization of serverless function snapshots
Dynamic prediction of collection yield for managed runtimes
FleetIO: Managing Multi-Tenant Cloud Storage with Multi-Agent Reinforcement Learning
DataFlower: Exploiting the Data-flow Paradigm for Serverless Workflow Orchestration
Stramash: A Fused-Kernel Operating System For Cache-Coherent, Heterogeneous-ISA Platforms
Rethinking the SDN Abstraction
RelaxReplay: record and replay for relaxed-consistency multiprocessors
MASK: Redesigning the GPU Memory Hierarchy to Support Multi-Application Concurrency
Chimera: Collaborative Preemption for Multitasking on a Shared GPU
Game of Threads: Enabling Asynchronous Poisoning Attacks
Fast Mutual Exclusion for Uniprocessors
The cloud will change everything
Post-compiler software optimization for reducing energy
Hardware Support for Memory Protection: Capability Implementations
Neuromorphic processing: a new frontier in scaling computer architecture
A new method for GPU based irregular reductions and its application to k-means clustering
ReSBM: Region-based Scale and Minimal-Level Bootstrapping Management for FHE via Min-Cut
A Quantitative Analysis and Guidelines of Data Streaming Accelerator in Modern Intel Xeon Scalable Processors
TwinDrivers: semi-automatic derivation of fast and safe hypervisor network drivers from guest OS drivers
The benefit of SMT in the multi-core era: flexibility towards degrees of thread-level parallelism
Time Dilation and Contraction for Programmable Analog Devices with Jaunt
A Portable Interface for On-the-Fly Instruction Space Modifiction
Intelligence Beyond the Edge: Inference on Intermittent Embedded Systems
Regularities considered harmful: forcing randomness to memory accesses to reduce row buffer conflicts for multi-core, multi-bank systems
CryoWire: wire-driven microarchitecture designs for cryogenic computing
Understanding and improving operating system effects in control flow prediction
How to Build Static Checking Systems Using Orders of Magnitude Less Code
On-the-fly elimination of dynamic irregularities for GPU computing
The Run-Time Environment for Screme, A Scheme Implementation on the 88000
More Apps, Faster Hot-Launch on Mobile Devices via Fore/Background-aware GC-Swap Co-design
Enhancing software reliability with speculative threads
Salus: A Practical Trusted Execution Environment for CPU-FPGA Heterogeneous Cloud Platforms
Going beyond the Limits of SFI: Flexible and Secure Hardware-Assisted In-Process Isolation with HFI
An ultra low-power processor for sensor networks
Combinatorial sketching for finite programs
CHERI JNI: Sinking the Java Security Model into the C
Sigma: Compiling Einstein Summations to Locality-Aware Dataflow
C11Tester: a race detector for C/C++ atomics