yusuke1997/dblp-id-title huggingface dataset:
Seamless Research Between Academia And Industry To Facilitate Test Of Integrated High-Speed Wireless Systems: Is This An Illusion?
Test path simulation and characterisation
A Model for Analyzing Test Capacity, Cost, and Productivity
The stuck-at fault: it ain't over 'til it's over
POSTT: Path-oriented static test compaction for transition faults in scan circuits
Fault modeling and diagnosis for nanometric analog circuits
Boost CPU Turbo Yield Utilizing Explainable Artificial Intelligence
Screening MinVDD Outliers Using Feed-Forward Voltage Testing
Monitoring the delay of long interconnects via distributed TDC
System-Level Testability of Hardware/Software Systems
SoC Test Architecture Design and Optimization Considering Power Supply Noise Effects
Selectable Length Partial Scan: A Method to Reduce Vector Length
Outsourcing DFT: the right mix
A Test Data Collection System for Uniform Data Analysis
Test and Calibration Methods for Process Variation of ReRAM-based Spiking Neural Networks
FAT-RABBIT: Fault-Aware Training towards Robustness AgainstBit-flip Based Attacks in Deep Neural Networks
A New Maximal Diagnosis Algorithm for Bus-structured Systems
Forward prediction based on wafer sort data - A case study
Expediting ramp-to-volume production
Testing of Precision DACs Using Low-Resolution ADCs with Dithering
BIST vs. ATE for testing system-on-a-chip
Native mode functional test generation for processors with applications to self test and design validation
Feasibility Study of Smart Substrate Multichip Modules
Diagnostics Based on Fault Signature
Automated test program generation for automotive devices
Design-for-Test for Silicon Photonic Circuits
A graph-theoretic approach for minimizing the number of wrapper cells for pre-bond testing of 3D-stacked ICs
Linear Error Modeling of Analog and Mixed-Signal Devices
High volume microprocessor test escapes, an analysis of defects our tests are missing
Adapting scan architectures for low power operation
Error Model (EM) - A New Way of Doing Fault Simulation
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits
Estimating defect-type distributions through volume diagnosis and defect behavior attribution
A universal DC to logic performance correlation
BIST vs. ATE: need a different vehicle?
Testing CrossTalk Induced Delay Faults in Static CMOS Circuits Through Dynamic Timing Analysis
Accurate measurement of small delay defect coverage of test patterns
Individual Signal Path Calibration for Maximum Timing Accuracy in a High Pincount VLSI Test System
Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin ∗
On-chip timing uncertainty measurements on IBM microprocessors
Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains
Test session oriented built-in self-testable data path synthesis
Mainstream ATE: To Reduce LSI and VLSI Test Cost
Standards Based Wireless Device Testing
An Effective Diagnosis Method to Support Yield Improvement
An Adaptable Emulation Support Environment for Microprocessor Systems
A Method for Reducing the Search Space in Test Pattern Generation
A New Timing Calibration Method for High Speed Memory Test
Mixed-Mode Simulation for Time-Domain Fault Analysis
The importance of DFX, a foundry perspective
Board and system test with SoC DFT
Custom Pin Electronics for VLSI Automatic Test Equipment
A novel architecture for on-chip path delay measurement
1149.5: Now It's a Standard, So What?
On-Chip Mixed-Signal Test Structures Re-used for Board Test
SERDES external loopback test using production parametric-test hardware
A Framework of High-quality Transition Fault ATPG for Scan Circuits
Software-based online self-testing of network-on-chip using bounded model checking
Universal Signal Routing Card
Calibration of Systematic Errors in Precision Time-Interval Counters
Thoughts on Core Integration and Test
Design of a test simulation environment for test program development
Making a Test System Diagnostic Usable
A Global Algorithm for the Partial Scan Design Problem Using Circuit State Information
Plug & Play I DDQ Monitoring with QTAG
AC product defect level and yield loss
Accurate ADC testing with significantly relaxed instrumentation including large cumulative jitter
The effects of test compaction on fault diagnosis
Techniques to Reduce Data Volume and Application Time for Transition Test
A Knowledge Based Diagnostic System for Automatic Test Equipment
Multi-GB/s IC Test Challenges and Solutions
Improved Techniques for Estimating Signal Probabilities
On using address scrambling to implement defect tolerance in SRAMs
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices
EMFORCED: EM-based Fingerprinting Framework for Counterfeit Detection with Demonstration on Remarked and Cloned ICs
Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs
A Stressed Eye Testing Module for Production Test of 30-Gbps NRZ Signal Interfaces
Multi Strobe Circuit for 2.133GHz Memory Test System
Implementing 1149.1 in the PowerPC TM RISC Microprocessor Family
Power, programmability, and granularity: The challenges of ExaScale computing
Testing MRAM for Write Disturbance Fault
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
EEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips
Hardware trojan detection through information flow security verification
A methodology for detecting performance faults in microprocessors via performance monitoring hardware
Analyzing the risk of timing modeling based on path delay tests
The Role of ATPG Fault Diagnostics in Driving Physical Analysis
Functional Testing Folklore and Fact
Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST
State of the art low capture power methodology
Test program synthesis for path delay faults in microprocessor cores
Inexpensive Microprocessor Testing of Custom Integrated Circuits on Wafers, Packages, and Boards
AI-Driven Assurance of Hardware IP against Reverse Engineering Attacks
Quickly Developing Effective Codec Tests on an In-Circuit Board Test System
Hardware hooks for transition scan characterization
Testing strategies for a 9T sub-threshold SRAM
Accessing general IEEE Std. 1687 networks via functional ports
Testing Wireless Local Area Network Transceiver ICs at 5 GHz
Should Nanometer Circuits be Periodically Tested in the Field?
Novel optical probing technique for flip chip packaged microprocessors
Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models
Testing throughput computing interconnect topologies with Tbits/sec bandwidth in manufacturing and in field
Increasing the IDDQ test resolution using current prediction
High Performance Pin Electronics Employing GaAs IC and Hybrid Circuit Packaging Technology
Orthogonal Scan: Low-Overhead Scan for Data Paths
Open Microphone - My DFT is better than yours ..
Technical Paper Reviewers
Effectively Using Machine Learning to Expedite System Level Test Failure Debug
An Interactive Descrambler Program for RAMs with Redundancy
Universal test generation using fault tuples
Testing of Glue Logic Interconnects Using Boundary Scan Architecture
System Level Fault Simulation
A self-compensating built-in self-test solution for RF phased array mismatch
Microprocessor Modeling for Logic Simulation
Tolerance analysis of fixture fabrication, from drilling holes to pointing accuracy
Software Integration in a Workstation-Based F-Beam Tester
Device-Aware Test for Ion Depletion Defects in RRAMs
System-Level Boundary-Scan in a Highly Integrated Switch
Technique for transfer of analog prototypes (DV's) to production
Recycling Functional Test Vectors: Techniques and Tools for Pattern Conversion
Achieving extreme scan compression for SoC Designs
An Approach to Accelerate Scan Testing in IEEE 1149.1 Architectures
IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores
Functional Test and Speed/Power Sorting of the IBM POWER6 and Z10 Processors
Minimum Testing Requirements to Screen Temperature Dependent Defects
A DDJ calibration methodology for high-speed test and measurement equipments
Market opportunities and testing challenges for millimeter-wave radios and radars
Statistical threshold formulation for dynamic I_dd test
Test and Repair of Embedded Flash Memories
An MC68020 Users Test Program
Evaluating Waveform-Generation Capabilities of VLSI Test Systems
Fault modeling of suspended thermal MEMS
Digital Signal Processing for Production Testing of Analog LSI Devices
Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis Efficiency
Technique for testing a very high speed mixed signal read channel design
Automated Design for Testability of Semicustom Integrated Circuits
DRAM-Specific Space of Memory Tests
System Manufacturing Test Cost Model
Designing Testable Control Paths with Multiple and Feedback Scan-Paths
Overview of PowerPC TM 620 Multiprocessor Verification Strategy
Putting wasted clock cycles to use: Enhancing fortuitous cell-aware fault detection with scan shift capture
Techniques for Testing Hexagonally Connected Systolic Arrays
Vision Inspection: Meeting the Promise?
Machine Learning-Based Automatic Generation of eFuse Configuration in NAND Flash Chip
Encounter test OPMISR + on-chip compression
Integrated probe card/interface solutions for specific test applications
Identifying Undetectable Defects Using Equivalence Checking
Non-invasive RF built-in testing using on-chip temperature sensors
Auto-calibrating analog timer for on-chip testing
A New Wafer Level Latent Defect Screening Methodology for Highly Reliable DRAM Using a Response Surface Method
On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips
An algorithm to evaluate wide-band quadrature mixers
BART: A Bridging Fault Test Generation for Sequential Circuits
Optical Testing of Printed Circuit Boards
How to ensure zero defects from the beginning with semiconductor test methods
Is It Rocket Science?
A Low-Cost Programmable Memory BIST Design for Multiple Memory Instances
Soft error resiliency characterization and improvement on IBM BlueGene/Q processor using accelerated proton irradiation
High-performance ADC linearity test using low-precision signals in non-stationary environments
Self-Testing in Bit Serial VLSI Parts: High Coverage at Low Cost
Accurate path delay fault coverage is feasible
Diagnosis meets Physical Failure Analysis: What is needed to succeed?
Adaptive testing - Cost reduction through test pattern sampling
ITC'99 Benchmark Circuits - Preliminary Results
High-Yield Multichip Modules Based on Minimal IC Pretest
Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects
Concurrent Error Detection in Embedded Digital Control of Nonlinear Autonomous Systems Using Adaptive State Space Checks
A Study of Implication Based Pseudo Functional Testing
New approach to integrate LSI design databases with e-beam tester
Mutation-Based Testing of Concurrent Programs
At-Speed Interconnect Test and Diagnosis of External Memories on a System
A Rational Basis for Setting Burn-In Yield Criteria
The Role of the Engineering Work Station in Test Program Development
Design of compactors for signature-analyzers in built-in self-test
Configuration free SoC interconnect BIST methodology
Comparing the effectiveness of cache-resident tests against cycleaccurate deterministic functional patterns
"Resistive Shorts" Within CMOS Gates
Testing and debugging delay faults in dynamic circuits
IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores
Financial Impact of Tester Reliability Improvements
Linearity Test Time Reduction for Analog-to-Digital Converters Using the Kalman Filter with Experimental Parameter Estimation
A Study of I DDQ Subset Selection Algorithms for Bridging Faults
Automated translation of legacy code for ATE
2005 Call for Papers
Low-power SRAMs power mode control logic: Failure analysis and test solutions
Systems Testing Why ?
Forming N-detection test sets from one-detection test sets without test generation
On Hazard-free Patterns for Fine-delay Fault Testing
A case study: Leverage IEEE 1687 based method to automate modeling, verification, and test access for embedded instruments in a server processor
Syndrome Testable Design of Combinational Networks for Detecting Stuck-At and Bridging Faults
A dynamic programming solution for optimizing test delivery in multicore SOCs
A Workstation Environment for Boundary Scan Interconnect Testing
Integrated optimization of semiconductor manufacturing: A machine learning approach
On Built-In Testing of VLSI Chips
Minimal Test Sets for Combinatorial Circuits
Fault Recovery in Micro-Electrode-Dot-Array Digital Microfluidic Biochips Using an IJTAG NetworkBehaviors
Testing reusable IP-a case study
A Waveform Digitizer for Dynamic Testing of High Speed Data Conversion Components
Verifying Properties Using Sequential ATPG
Is "Design to Production" The Ultimate Answer For Jitter, Noise, and BER Challenges For Multi GB/s ICs?
A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS
Laser Fault Injection Vulnerability Assessment and Mitigation with Case Study on PG-TVD Logic Cells
On-Line Self-Monitoring Using Signatured Instruction Streams
Maintaining Simulation Accuracy through Physical Device Models
A Generic Framework for Scan Capture Power Reduction in Test Compression Environment
A New Hardware Architecture for Digital In-Circuit Testing
Quality Control for Production Testing
A Test Process Optimization and Cost Modeling Tool
Surviving state disruptions caused by test: The "Lobotomy Problem"
The Application of Novel Failure Analysis Techniques for Advanced Multi-Layered CMOS Devices
Configurable BISR Chain For Fast Repair Data Loading
Functional Test Program Generation Through interactive Graphics
Fault Isolation in Grey Systems
Optimal Scheduling of Signature Analysis for VLSI Testing
Intel 386 TM EX Embedded Processor I DDQ Testing
Statistical Product Monitoring: A Powerful Tool for Quality Improvement
An on-line BISTed SRAM IP core
Advanced Uniformed Test Approach For Automotive SoCs
A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST
Statistical Fault Sampling and Full Fault Simulation
Minimizing Test Time by Exploiting Parallelism in Macro Test
Early Reliability Estimation in Hardware Accelerators using Improved Colored Petri Nets
Partitioning Hierarchical Designs for Testability
Optimal Order Polynomial Transformation for Calibrating Systematic Errors in Multisite Testing
Intelligent Fault Localization in Software
In-Process Inspection Technique for Active-Matrix LCD Panels
DFM: The Real 90nm Hurdle
Single Testability Figure of Merit
Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling
The value of statistical testing for quality, yield and test cost improvement
SymbA: Symbolic Execution at C-level for Hardware Trojan Activation
A Tester for Design TM (TFD)
Power and thermal constrained test scheduling
High time for high level ATPG
Design-for-debug layout adjustment for FIB probing and circuit editing
Hypercompression of Test Patterns
Test generation for path-delay faults in one-dimensional iterative logic arrays
Wafer-Level Characterization of Probecards using NAC Probing
A New Software Tool for Detecting Problems Caused by Inductively-Generated Switching Noise
Diagnostic Test Generation for Arbitrary Faults
High Test Quality in Low Pin Count Applications
New Algorithm for Fast and Accurate Linearity Testing of High-Resolution SAR ADCs
Parallel Pattern Fast Fault Simulation for Three-State Circuits and Bidirectional I/O
Test time reduction of successive approximation register A/D converter by selective code measurement
Built-in self-test for micro-electrode-dot-array digital microfluidic biochips
Characterize Predicted vs Actual IR Drop in a Chip Using Scan Clocks
A programmable BIST for DRAM testing and diagnosis
Design for Primitive Delay Fault Testability
Core test connectivity, communication, and control
Yield and performance improvement through technology-design co-optimization in advanced technology nodes
Efficient Sequential ATPG for Functional RTL Circuits
Partial Scan Design Based on State Transition Modeling
Automated Wafer Lot Approval: A Statistically Based Implementation
Dual Port Static RAM Testing
Analog fault coverage improvement using final-test dynamic part average testing
An Intelligent Software-Integrated Environment of IC Testing
The Confluence of Manufacturing Test and Design Validation
A strategy for board level in-system programmable built-in assisted test and built-in self test
Programmable memory BIST
Automated measurement of defect tolerance in mixed-signal ICs
Test-Based Model Generation For Legacy Systems
A timestamping method using reduced cost ADC hardware
Run-time hardware trojan detection using performance counters
Estimating the integral non-linearity of A/D-converters via the frequency domain
How much testing is enough
New modeling methods for bounded Gaussian jitter (BGJ)/noise (BGN) and their applications in jitter/noise estimation/testing
Built-In Self-Diagnosis and Fault-Tolerant Daisy-Chain Design in MEDA Biochips
Systematic Yield Improvement in Board Testing Practice
: A Parallel Algorithm for Fault Simulation on the Connection Machine
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS
A Test Analysis Program for Memory Testing
8Gbps CMOS pin electronics hardware macro with simultaneous bi-directional capability
99% AC test coverage using only LBIST on the 1 GHz IBM S/390 zSeries 900 Microprocessor
Fault Diagnosis in an LSSD Environment
An Efficient Secure Scan Design for an SoC Embedding AES Core
Automatic Failure-Analysis System for High-Density DRAM
A New Method for Measuring Aperture Jitter in ADC Output and Its Application to ENOB Testing
An approach to consistent jitter modeling for various jitter aspects and measurement methods
A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current
System issues in boundary-scan board test
On-line Boundary-Scan Testing in Service of Extended Products
Global Failure Localization: We Have To, But on What and How?
Test Strategy for a 32-Bit Microprocessor Module with Memory Management
An analysis of ATE computational architecture
A Test Retrospection and a Quest for Direction
A high speed and area efficient on-chip analog waveform extractor
Analyzing and addressing the impact of test fixture relays for multi-gigabit ATE I/O characterization applications
A Flexible Approach to Test Program Cross Compilers
A Data Management System for Testing Memory Devices
Business constraints drive test decisions - not vice versa
Motherboard testing using the PCI bus
ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits
Concurrent System-Level Error Detection Using a Watchdog Processor
Development of a new standard for test
Qualification and Quantification of Process-Induced Product-Related Defects
Reusable, Low-cost, and Flexible Multidrop System JTAG Architecture
Practical Test Methods for Verification of the EDRAM
Defect Coverage Analysis of Partitioned Testing
Test Generation with High Coverages for Quiescent Current Test of Bridging Faults in Combinational Circuits
Fault diagnosis of TSV-based interconnects in 3-D stacked designs
Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs
High Frequency Wafer Probing and Power Supply Resonance Effects
Built-in self-test and self-calibration for analog and mixed signal circuits
Position statement: "have we overcome the challenges associated with SoC and multi-core testing?"
Correct by construction is guaranteed to fail
Proceedings International Test Conference 1983, Philadelphia, PA, USA, October 1983
Low Power Test
System Architecture for Optimum DC Parameter Measurements
Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis
i DD Pulse Response Testing Applied to Complex CMOS ICs
Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips
Built-in Self-Test and Fault Diagnosis for Lab-on-Chip Using Digital Microfluidic Logic Gates
EEODM: An effective BIST scheme for ROMs
DFT, test lifecycles and the product lifecycle
On Selecting Flip-Flops for Partial Reset
Concurrent Error Detection in Linear Analog Circuits Using State Estimation
Design and test of latch-based circuits to maximize performance, yield, and delay test quality
Low cost production scan chain test for compression based designs
Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores
Practical partitioning for testability with time-shared boundary scan
The gap: Test challenges in Asia manufacturing field
An Efficient Method for Compressing Test Data
Zero Trust Approach to IC Manufacturing and Testing
AN SRAM Weak Cell Fault Model and a DFT Technique with a Programmable Detection Threshold
A High-Performance Integrated Analog/Digital Test and Characterization Test System
Board-Level Boundary-Scan: Regaining Observability with an Additional IC
The Yield of Test Outsourcing
The integration of boundary-scan test methods to a mixed-signal environment
DEFCON: Defect Acceleration through Content Optimization
Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages
Testing The Tester
Software Testing: Theory and Practice
Fault simulation acceleration for TRAX dictionary construction using GPUs
Testability Analysis: What Role Should it Play in IC Design ?
Integrating Core Selection in the SOC Test Solution Design-Flow
DFT is all I can afford, who cares about Design for Yield or Design for Reliability!
On Concurrently Testable Microprogrammed Control Units
A fourth generation analog incircuit program generator
A study of the optimization of DC parametric tests
Information-theoretic and statistical methods of failure log selection for improved diagnosis
PAL and Logic Array In-Circuit Testing Considerations
Real-time testing method for 16 Gbps 4-PAM signal interface
Functional Test Generation of Digital LSI/VLSI Systems Using Machine Symbolic Execution Technique
A domain coverage metric for the validation of behavioral VHDL descriptions
Managing Test in the End-to-End, Mega Supply Chain
Fault Modeling and Test Algorithm Development
Detecting and diagnosing open defects
Verification of Device Interface Hardware Interconnections Prior to the Start of Testing
Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain
Business constraints drive test decisions
An Efficient Linear Time Algorithm for Scan Chain Optimization and Repartitioning
Model for Delay Faults Based upon Paths
Deterministic BIST with multiple scan chains
Die-level adaptive test: Real-time test reordering and elimination
AC-JTAG: empowering JTAG beyond testing DC nets
CAEN-BIST: Testing the NanoFabric
Eliminating the Ouija board: automatic thresholds and probabilistic I_DDQ diagnosis
Composite Electro-Optical Testing of Surface-Mount Device Boards-One Manufacturer's Experience
Built-In Current Sensor for I DDQ Test in CMOS
A comparative study of continuous sampling plans for functional board testing
Fault Diagnosis of Flash ADC using DNL Test
Stuck-at fault: a fault model for the next millennium
Detection of Resistive Shorts in Deep Sub-micron Technologies
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination
IRIDIUM tm Satellite: A Large System Application of Design for Testability
In-system constrained-random stimuli generation for post-silicon validation
The Power of Exhaustive Bridge Diagnosis using IDDQ Speed, Confidence, and Resolution
TDRC-a symbolic simulation based design for testability rules checker
Amdahl Corporation Board Delay Test System
Test access mechanism for multiple identical cores
Programmable deterministic Built-In Self-Test
Panel: business constraints drive test decisions
Counterfeit IC detection using light emission