yusuke1997/dblp-id-title huggingface dataset:
Proceedings of the 2nd International Workshop on Multimodal and Responsible Affective Computing, MRAC 2024, Melbourne VIC, Australia, 28 October 2024- 1 November 2024
Early Joint Learning of Emotion Information Makes MultiModal Model Understand You Better
W-TDL: Window-Based Temporal Deepfake Localization
Improving Multimodal Emotion Recognition by Leveraging Acoustic Adaptation and Visual Alignment
FEENN: The Feature Enhancement Embedded Neural Network for Robust Multimodal Emotion Recognition
Multimodal Emotion Captioning Using Large Language Model with Prompt Engineering
CLIP-based Model for Effective and Explainable Apparent Personality Perception
Proceedings of the 1st International Workshop on Multimodal and Responsible Affective Computing, MRAC 2023, Ottawa, ON, Canada, 29 October 2023
Open Vocabulary Emotion Prediction Based on Large Multimodal Models
SZTU-CMU at MER2024: Improving Emotion-LLaMA with Conv-Attention for Multimodal Emotion Recognition
Sentiments and Bias in Automated Decision Making
Multimodal Blockwise Transformer for Robust Sentiment Recognition
Robust Representation Learning for Multimodal Emotion Recognition with Contrastive Learning and Mixup
Label Distribution Adaptation for Multimodal Emotion Recognition with Multi-label Learning
MRAC'24 Track 2: 2nd International Workshop on Multimodal and Responsible Affective Computing
MER 2024: Semi-Supervised Learning, Noise Robustness, and Open-Vocabulary Multimodal Emotion Recognition
EfficienTransNet: An Automated Chest X-ray Report Generation Paradigm
Multimodal Emotion Recognition with Vision-language Prompting and Modality Dropout
Learning Noise-Robust Joint Representation for Multimodal Emotion Recognition under Incomplete Data Scenarios
Learning Aligned Audiovisual Representations for Multimodal Sentiment Analysis
Wearable Sensing for Longitudinal Automatic Task Analysis
An Improved Method for Enhancing Robustness of Multimodal Sentiment Classification Models via Utilizing Modality Latent Information
Audio-Guided Fusion Techniques for Multimodal Emotion Analysis
Facial Physiological and Emotional Analysis
Fairness for Affective and Wellbeing Computing
Leveraging Contrastive Learning and Self-Training for Multimodal Emotion Recognition with Limited Labeled Samples
THE-FD: Task Hierarchical Emotion-aware for Fake Detection
MicroEmo: Time-Sensitive Multimodal Emotion Recognition with Subtle Clue Dynamics in Video Dialogues
Generalised Bias Mitigation for Personality Computing
Semi-supervised Multimodal Emotion Recognition with Consensus Decision-making and Label Correction
Numerische Strömungssimulation - Augenblicklicher Stand und zukünftige Entwicklungen
A new Generation of Highly Parallel General Purpose Computer
An Introduction to the Connection Machine System CM-5
Parallele Optimierung großer Fachwerkstrukturen auf einem Transputersystem
Der Supercomputer als Werkzeug der numerischen Wettervorhersage
Hochgradiger Parallelismus
Anwendungen auf der CM-5
Proceedings of the Fifteenth Conference on Supercomputers and Applications, 1991, Bochum, Germany
MIMD Parallelverarbeitung in der Anwendung - Der neue Supercomputer CRAY Y-MP-90 (Folien)
Automatic toolset for fault tolerant design: results demonstration on a running industrial application
3D Integration: Another Dimension Toward Hardware Security
Error Correction in Arithmetic Operations by I/O Inversion
On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation
Flexible in-silicon checking of run-time programmable assertions
DRAM Characterization under Relaxed Refresh Period Considering System Level Effects within a Commodity Server
Internal model control for a self-tuning Delay-Locked Loop in UWB communication systems
SBanTEM: A Novel Methodology for Sparse Band Tensors as Soft-Error Mitigation in Sparse Convolutional Neural Networks
A Software Approach Towards Defeating Power Management Side Channel Leakage
A Statistical Sampler for a New On-line Analog Test Method
Mitigating Soft Errors to Prevent a Hard Threat to Dependable Computing
Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing
16th IEEE International On-Line Testing Symposium (IOLTS 2010), 5-7 July, 2010, Corfu, Greece
The Challenge of Reliability in Future Complex Systems
Exploiting the debug interface to support on-line test of control flow errors
Concurrent Test of Reconfigurable Scan Networks for Self-Aware Systems
Scrubbing Away Transients and Jiggling Around the Permanent: Long Survival of FPGA Systems Through Evolutionary Self-Repair
Exploiting FPGA for Accelerating Fault Injection Experiments
ZOBNN: Zero-Overhead Dependable Design of Binary Neural Networks with Deliberately Quantized Parameters
On-Line Error Detecting Constant Delay Adder
A hybrid self-diagnosis mechanism with defective nodes locating and attack detection for parallel computing systems
MUGEN: A high-performance fault-tolerant routing algorithm for unreliable Networks-on-Chip
10th IEEE International On-Line Testing Symposium (IOLTS 2004), 12-14 July 2004, Funchal, Madeira Island, Portugal
Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells
Low Cost On-Line Testing of RF Circuits
Hardware Accelerator for FIPS 202 Hash Functions in Post-Quantum Ready SoCs
SHIELD: PSO-Based Hardware Trojan Detection for Efficient and Low-Cost Defense
Investigating the Feasibility of eFPGA-based Hardware Patching
Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement
The Problem of On-Line Testing Methods In Approximate Data Processing
A verification strategy for fault-detection and fault-tolerance circuits
Analytic models for crossbar read operation
Self-checking test circuits for latches and flip-flops
Automatic High Functional Coverage Stimuli Generation for Assertion-based Verification
A Comparative Study of the Design of Synchronous and Asynchronous Self-Checking RISC Processors
Design of Embedded m-out-of-n Code Checkers Using Complete Parallel Counters
On-line Monitoring Capabilities of Oscillation Test Techniques: Results Demonstration in an OTA
Scalable FPGA graph model to detect routing faults
Checkpointing virtual machines against transient errors
Thermal laser attack and high temperature heating on HfO2-based OxRAM cells
Analysis of the extra delay on interconnects caused by resistive opens and shorts
A Test Generation Method Based on k-Cycle Testing for Finite State Machines
Parity check for m-of-n delay insensitive codes
Designing Robust Checkers in the Presence of Massive Timing Errors
A failure triage engine based on error trace signature extraction
Towards an automatic approach for hardware verification according to ISO 26262 functional safety standard
On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study
Fast power overhead prediction for hardware redundancy-based fault tolerance
Error resilient logic circuits under dynamic variations
Critical charge characterization in 6-T SRAMs during read mode
Automated Derivation of Application-aware Error Detectors using Static Analysis
Crosstalk Effect Minimization for Encoded Busses
Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield
Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent Testing
Code-Disjoint Carry-Dependent Sum Adder with Partial Look-Ahead
Through-silicon-via built-in self-repair for aggressive 3D integration
Reliability analysis of MTJ-based functional module for neuromorphic computing
On the Probability of Detecting Data Errors Generated by Permanent Faults Using Time Redundancy
On Evaluating the Security of Dynamic Scan Obfuscation Scheme
Power analysis attacks on ARX: An application to Salsa20
HealthLog Monitor: A Flexible System-Monitoring Linux Service
Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard
Variability and reliability-aware application tasks scheduling and power control (Voltage and Frequency Scaling) in the future nanoscale multiprocessors system on chip
JTAG: A Multifaceted Tool for Cyber Security
A Low-Cost Accumulator-Based Test Pattern Generation Architecture
A new solution to on-line detection of Control Flow Errors
Test Generation Methodology for High-Speed Floating Point Adders
Integrating an Interconnect BIST with Crosstalk Avoidance Hardware
Recent Trends and Perspectives on Defect-Oriented Testing
Accurate alpha soft error rate evaluation in SRAM memories
Aging-aware critical paths in deep submicron
A Pragmatic Approach to On-Line Testing
Spiking Neuron Hardware-Level Fault Modeling
Error correction encoding for multi-threshold capture mechanism
Enhancing the Reliability of Split Computing Deep Neural Networks
From an analytic NBTI device model to reliability assessment of complex digital circuits
A Hierarchical Self Test Scheme for SoCs
Development of FF Circuits for Measures Against Power Supply Noise
Redesign for untrusted gate-level netlists
About the functional test of the GPGPU scheduler
Emulation-based Fault Injection in Circuits with Embedded Memories
A Capture Safe Static Test Compaction Method Based on Don't Cares
Aggressively voltage overscaled adaptive RF systems using error control at the bit and symbol levels
Architectural Trade-Offs for Fault Tolerant Multi-Core Systems
Hardware Trojan detection and classification based on steady state learning
REVOLVER: A Zero-Step Execution Emulation Framework for Mitigating Power Side-Channel Attacks on ARM64
Key randomization using a power analysis resistant deterministic random bit generator
PASCAL: Timing SCA Resistant Design and Verification Flow
Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy?
Real Time Fault Injection Using a Modified Debugging Infrastructure
Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths
A post-deployment IC trust evaluation architecture
Memory BIST with address programmability
Highly-reliable integer matrix multiplication via numerical packing
Automated Die Inking through On-line Machine Learning
Error Resilient Machine Learning for Safety-Critical Systems: Position Paper
A Novel Simulation-Based Approach for ISO 26262 Hazard Analysis and Risk Assessment
Microarchitecture-Aware Timing Error Prediction via Deep Neural Networks
Self-Stabilization Testing of LUT-Based FPGA Designs by Fault Injection
Approximate computing: Energy-efficient computing with good-enough results
Efficient Fault Injection for Embedded Systems: As Fast as Possible but as Accurate as Necessary
Real time cross-layer adaptation for minimum energy wireless image transport using bit error rate control
Reliability of AI in Predicting the State of Health of Li-Ion Batteries *
Self-Monitoring, Self-Healing Biomorphic Sensor Technology
Generic BIST architecture for testing of content addressable memories
HLS-based sensitivity-inductive soft error mitigation for satellite communication systems
Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits
Minimum SRAM Retention Voltage: Insight about optimizing Power Efficiency across Temperature Profile, Process Variation and Aging
Reusing logic masking to facilitate path-delay-based hardware Trojan detection
Accumulator-Based Weighted Pattern Generation
Reliability Issues for Embedded SRAM at 90nm and Below
A Fault Injection Tool for SRAM-based FPGAs
Transformation Based Insertion of On-Line Testing Resources in a High-Level Synthesis Environment
On-line Testing of Embedded Systems Using Optical Probes: System Modeling and Probing Technology
Adaptive healing procedure for lifetime improvement in Wireless Sensor Networks
An Experimentally Tuned Compact Electrical Model for Laser Fault Injection Simulation
Mining simulation metrics for failure triage in regression testing
Modeling and Simulation of Circuit Aging in Scaled CMOS Design
EDA support for functional safety - How static and dynamic failure analysis can improve productivity in the assessment of functional safety
A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories
A smart test controller for scan chains in secure circuits
Temporal redundancy latch-based architecture for soft error mitigation
Logic Optimization of Unidirectional Circuits with Structural Methods
ICT: Interface software for the characterization and test of mixed-signal power cores
Totally Self-Checking FSM Design Based on Multilevel Synthesis Methods and FPGA Implemetation
SET response of a SEL protection switch for 130 and 250 nm CMOS technologies
30th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2024, Rennes, France, July 3-5, 2024
Faster Time-to-Market, Lower Cost of Development and Test for Standard Analog IC
GPD: Predictive Control Flow Error Detection Leveraging Data Flow Error Detection Methods
A Novel Fault-Tolerant Logic Style with Self-Checking Capability
Trends and Trade-Offs in Designing Highly Robust Throughput Computing Oriented Chips and Systems
Tackling long duration transients in sequential logic
On Attacking IJTAG Architecture based on Locking SIB with Security LFSR
An On-Line Testing Approach Using Code-Perturbation
New High Speed CMOS Self-Checking Voter
28th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2022, Torino, Italy, September 12-14, 2022
A Secure Scan Controller for Protecting Logic Locking
An Anomalous Behavior Detection Method for IoT Devices Based on Power Waveform Shapes
Leveraging CMOS Aging for Efficient Microelectronics Design
Hardware Security Vulnerability Assessment to Identify the Potential Risks in A Critical Embedded Application
Selective fault tolerance for finite state machines
The influence of clock-gating on NBTI-induced delay degradation
27th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2021, Torino, Italy, June 28-30, 2021
Improving fault handling software techniques
Assessing Robustness of Smart Systems via Multi-domain Analog Fault Simulation
On graceful degradation of microprocessors in presence of faults via resource banking
Configurable serial fault-tolerant link for communication in 3D integrated systems
Building Resilient AI: Strengthening Data, Security, and Robustness in Neural Networks
Error-tolerance evaluation and design techniques for motion estimation computing arrays
Embedded Scan Test with Diagnostic Features for Self-Testing SoCs
SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation
A Novel Approach to Error Resilience in Online Reinforcement Learning
A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths
Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Contro
An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets
NBTI aging evaluation of PUF-based differential architectures
Designing a High Speed Decoder for Cyclic Codes
Control-flow error recovery using commodity multi-core architecture features
Can Multi-Layer Microfluidic Design Methods Aid Bio-Intellectual Property Protection?
Operating System Function Reuse to Achieve Low-Cost Fault Tolerance
Identification of Failure Modes for Circuit Samples with Confounded Causes of Failure
Comparative study of defect-tolerant multiplexers for FPGAs
Envelope Detection Based Transition Time Supervision for Online Testing of RF MEMS Switches
Space Shuttle: A Test Vehicle for the Reliability of the SkyWater 130nm PDK for Future Space Processors
An RT-level Concurrent Error Detection Technique for Data Dominated Systems
Exploiting Parametric Power Supply and/or Temperature Variations to Improve Fault Tolerance in Digital Circuits
An efficient probability framework for error propagation and correlation estimation
A Study of the Effects of Transient Fault Injection into the VHDL Model of a Fault-Tolerant Microcomputer System
Linear and nonlinear MISR operations for safety and security in automotive applications
Asynchronous Design: Fault Robustness and Security Characteristics
Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts
VANDOR: Mitigating SEUs into Quantized Neural Networks
A comprehensive soft error analysis methodology for SoCs/ASICs memory instances
CMOS Differential and Absolute Thermal Sensors
Lightweight Concurrent Out-of-Distribution Detection in Hyperdimensional Computing Hardware
Bloom Filters for Soft Error Detection: Neutron and Fault Injection Validation
A Method for Measuring Process Variations in the FPGA Chip Considering the Effect of Wire Delay
A Family of Self-Repair SRAM Cores
3D integration: Circuit design, test, and reliability challenges
Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test
A Closer Look at Evaluating the Bit-Flip Attack Against Deep Neural Networks
On-line write margin estimator to monitor performance degradation in SRAM cores
CEDA: Control-flow Error Detection through Assertions
Open-Set Recognition: an Inexpensive Strategy to Increase DNN Reliability
Asynchronous Circuits Sensitivity to Fault Injection
Safety-Relevant AI-Based System Robustification with Neural Network Ensembles
False Error Study of On-line Soft Error Detection Mechanisms
Fault Grading Techniques for Evaluating Software-Based Self-Test with Respect to Small Delay Defects
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing
Defect Analysis for Delay-Fault BIST in FPGAs
Hardware Trojans classification for gate-level netlists using multi-layer neural networks
Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor
Hardware and Software Techniques for Heterogeneous Fault-Tolerance
SpikingJET: Enhancing Fault Injection for Fully and Convolutional Spiking Neural Networks
How to flip a bit?
Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices
Methodology for Tradeoffs between Performance and Lifetimes of Integrated Circuits
Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection
Analysis of SEU Effects in a Pipelined Processor
Design-time reliability evaluation for digital circuits
About the Correlation between Logical Identified Faulty Gates and their Layout Characteristics
An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors
An Efficient BIST scheme for High-Speed Adders
Real-Time Validation of Fault-Tolerant Mixed-Criticality Systems
Pre-bond testing of weak defects in TSVs
Gatewaying IEEE 1149.1 and IEEE 1149.7 test access ports
Test-per-Clock Testing of the Circuits with Scan
On-line characterization and reconfiguration for single event upset variations
Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study
TRACS-TRansient Activity Checking with Scan Cells
Human-Artificial Intelligent Threat Modelling in the Automotive Domain
Improving the significance of probabilistic circuit fault emulations
Qualification and relifing testing for space applications applied to the agilent G-Link components
A Digital SRAM Modeling for Cell-Aware Testing and Test Algorithms Evaluation
Secure and Flexible WebAssembly Deployment Infrastructure for Automotive Cyber-Physical Systems
Online monitoring of NBTI and HCD in beta-multiplier circuits
Multivariate outlier modeling for capturing customer returns - How simple it can be
An Input Vector Monitoring Concurrent BIST scheme exploiting
Protecting GPU's Microarchitectural Vulnerabilities via Effective Selective Hardening
A Model for Transient Fault Propagation in Combinatorial Logic
An on-line test strategy and analysis for a 1T1R crossbar memory
Fault missing rate analysis of the arithmetic residue codes based fault-tolerant FIR filter design
Keytone: Silent Data Corruptions at Scale
New approaches for synthesis of redundant combinatorial logic for selective fault tolerance
Fault modeling and testing of through silicon via interconnections
HHC: Hierarchical hardware checkpointing to accelerate fault recovery for SRAM-based FPGAs
Architectural vulnerability aware checkpoint placement in a multicore processor
Filtering-based error-tolerability evaluation of image processing circuits
A Functional Self-Test Approach for Peripheral Cores in Processor-Based SoCs
An On-Line Fault Detection Scheme for SBoxes in Secure Circuits
Finding False Paths for Sequential Circuits Using Operations on ROBDDs
An Anomalous Behavior Detection Method for IoT Devices by Extracting Application-Specific Power Behaviors
Temperature- and aging-resistant inverter for robust and reliable time to digital circuit designs in a 65nm bulk CMOS process
On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity
Challenges of RF and mixed signal design under process variability
Detectability analysis of small delays due to resistive opens considering process variations
Evaluating transient-fault effects on traditional C-element's implementations
Fault Tolerant System Design Method Based on Self-Checking Circuits
Online error detection and correction of erratic bits in register files
Online time interference detection in mixed-criticality applications on multicore architectures using performance counters
A Matlab Based On-Chip Signal Generation and Analysis Environment for Mixed Signal Circuits
A BIST scheme for testing and repair of multi-mode power switches
Transparent structural online test for reconfigurable systems
Probabilistic error detection and correction in switched capacitor circuits using checksum codes
Checkers for RF Matching Networks on an Automatic Test Board
On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs
Software-based control flow error detection and correction using branch triplication
A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory
Special Session 2: Benchmarking and Standardization in Software-Based SER Characterization: Towards an IEEE Task Force?
Reliability issues in RRAM ternary memories affected by variability and aging mechanisms
Physical Demonstration of Polymorphic Self-Checking Circuits
Ray-Spect: Local Parametric Degradation for Secure Designs: An application to X-Ray Fault Injection
Modern Hardware Margins: CPUs, GPUs, FPGAs Recent System-Level Studies
Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injection
Avoiding Soft Error-Induced Illegal Memory Accesses in GPU with Inter-Thread Communication
Analyzing and alleviating the impact of errors on an SRAM-based FPGA cluster
Evaluating One-Hot Encoding Finite State Machines for SEU Reliability in SRAM-based FPGAs
Cache-aware reliability evaluation through LLVM-based analysis and fault injection
An I-IP based approach for the monitoring of NBTI effects in SoCs
Increasing the robustness of CUDA Fermi GPU-based systems
Framework for economical error recovery in embedded cores
Development of a Testbench for Validation of DMT and DT2 Fault-Tolerant Architectures on SOI PowerPC7448
A Review of DASIE Code Family: Contribution to SEU/MBU Understanding
Increasing fault coverage during functional test in the operational phase
A Note on Error Detection in an RSA Architecture by Means of Residue Codes
Countermeasures against fault attacks: The good, the bad, and the ugly
Fault Tolerance Implementation within SRAM Based FPGA Design Based upon the Increased Level of Single Event Upset Susceptibility
Online Fast Detection and Diagnosis of Power Grid Security Attacks Using State Checksums
FPGA-based testing strategy for cryptographic chips: A case study on Elliptic Curve Processor for RFID tags
An accurate soft error propagation analysis technique considering temporal masking disablement
Fault Tolerant ICs by Area-Optimized Error Correcting Codes
Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories
High-level synthesis for multi-cycle transient fault tolerant datapaths
Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults