yusuke1997/dblp-id-title huggingface dataset:
IEEE 21st Annual Symposium on High-Performance Interconnects, HOTI 2013, Santa Clara, CA, USA, August 21-23, 2013
Polarized routing: an efficient and versatile algorithm for large direct networks
An Analysis of 10-Gigabit Ethernet Protocol Stacks in Multicore Environments
An implementable parallel scheduler for input-queued switches
High-Speed Networking: A Systematic Approach to High-Bandwidth Low-Latency Communications
Analysis and avoidance of cross-talk in on-chip buses
Weighted Differential Scheduler
Distributed-and-Split Data-Control Extension to SCSI for Scalable Storage Area Networks
Exploiting Offload Enabled Network Interfaces
ParaSplit: A Scalable Architecture on FPGA for Terabit Packet Classification
Tutorial 1: Optical Networking: Recent Developments, Issues, and Trends
Characterizing Communication in Distributed Parameter-Efficient Fine-Tuning for Large Language Models
Thinking across Layers: What Do We Want Out of a Network?
The Tofu Interconnect
Optimizing Packet Dropping by Efficient Congesting-Flow Isolation in Lossy Data-Center Networks
WaveLight: A Monolithic Low Latency Silicon-Photonics Communication Platform for the Next-Generation Disaggregated Cloud Data Centers
Deferred segmentation for wire-speed transmission of large TCP frames over standard GbE networks
Impact of RoCE Congestion Control Policies on Distributed Training of DNNs
Caliper: Precise and Responsive Traffic Generator
Efficient exploitation of kernel access to Infiniband: a software DSM example
Level 4 Autonomous Driving SoC, leveraging chiplet, advanced package and UCIe
Hybrid Cache Architecture for High Speed Packet Processing
Backlog Aware Low Complexity Schedulers for Input Queued Packet Switches
Hands-on with the NetFPGA to build a Gigabit-rate Router
An architecture for the future internet
IEEE Symposium on High-Performance Interconnects, HOTI 2025, San Jose, CA, USA, August 20-22, 2025
Designing packet buffers with statistical guarantees
Host Software Stack Optimizations to Maximize Aggregate Fabric Throughput
10th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2002), August 21 - 23, 2002, Stanford, CA, USA
Efficient multi-match packet classification with TCAM
A Scalable, Self-Routed, Terabit Capacity, Photonic Interconnection Network
Heterogeneous Multi-processor Coherent Interconnect
Zero Copy Sockets Direct Protocol over InfiniBand - Preliminary Implementation and Performance Analysis
What are the future trends in high-performance inter.connects for parallel computers? [Panel 1]
IEEE Symposium on High-Performance Interconnects, HOTI 2023, Virtual Conference, USA, August 23-25, 2023
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics
A Bunch of Wires (BoW) Interface for Inter-Chiplet Communication
The Case for Domain-Specific Networks
Architectures for the Future Networks and the Next Generation Internet
Exploring Wireless Technology for Off-Chip Memory Access
Design of optical burst switches based on dual shuffle-exchange network and deflection routing
MPI Process and Network Device Affinitization for Optimal HPC Application Performance
Higher Performance and Capacity with OMI Near Memory
Optical interconnection as an IP macro of a CMOS library
Designing Next Generation Clusters: Evaluation of InfiniBand DDR/QDR on Intel Computing Platforms
PCI express and advanced switching: evolutionary path to building next generation interconnects
Innovating in Your Network with OpenFlow: A Hands-on Tutorial
Keynote: The Need for Speed in Trading Environments
Scheduling Traffic Matrices On General Switch Fabrics
IBRMP: A Reliable Multicast Protocol for InfiniBand
Understanding Power Efficiency of TCP/IP Packet Processing over 10GbE
The First Supercomputer with HyperX Topology: A Viable Alternative to Fat-Trees?
Configuring a load-balanced switch in hardware
End-to-End Adaptive Packet Aggregation for High-Throughput I/O Bus Network Using Ethernet
A Nanophotonic Interconnect for High-Performance Many-Core Computation
Communication Profiling and Characterization of Deep Learning Workloads on Clusters with High-Performance Interconnects
Rail-only: A Low-Cost High-Performance Network for Training LLMs with Trillion Parameters
R3C2: Reactive Route and Rate Control for CEE
Hardware SYN Attack Protection For High Performance Load Balancers
Deterministic Multiplexing of NoC on Grid CMPs
Scalable Distributed Training of Recommendation Models: An ASTRA-SIM + NS3 case-study with TCP/IP transport
Hot Interconnects 10 Committees
Low Latency Scheduling Algorithm for Shared Memory Communications over Optical Networks
Modeling and Evaluation of Chip-to-Chip Scale Silicon Photonic Networks
OmniXtend: Direct to Caches Over Commodity Fabric
Throughput Models of Interconnection Networks: The Good, the Bad, and the Ugly
FPGA Accelerated Low-Latency Market Data Feed Processing
Fulcrum's FocalPoint FM4000: A Scalable, Low-Latency 10GigE Switch for High-Performance Data Centers
Quality of Service in Global Grid Computing
Bursting Data between Data Centers: Case for Transport SDN
nCUBE3 communications architecture
A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT)
Buffer Management for Lossless Service in Network Processors
Flexible network attached storage using remote DMA
Fast Networks and Slow Memories: A Mechanism for Mitigating Bandwidth Mismatches
Initial end-to-end performance evaluation of 10-Gigabit Ethernet
Stable Round-Robin Scheduling Algorithms for High-Performance Input Queued Switches
A Memory-Balanced Linear Pipeline Architecture for Trie-based IP Lookup
Routing Keys
Optical Networking for Data Center Interconnects Across Wide Area Networks
Proceedings. 12th Annual IEEE Symposium on High Performance Interconnects
Designing Scalable and High-Performance MPI Libraries on Amazon Elastic Fabric Adapter
Express Virtual Channels with Taps (EVC-T): A Flow Control Technique for Network-on-Chip (NoC) in Manycore Systems
The Gemini System Interconnect
Demystifying the Communication Characteristics for Distributed Transformer Models
Implementation of Dynamic Bandwidth Re-allocation in Optical Interconnects using Microring Resonators
The Open Domain-Specific Architecture
Subchannel Scheduling for Shared Optical On-chip Buses
Performance evaluation of the Cray X1 distributed shared memory architecture
Stream Handlers: Application-Specific Message Services on Attached Network Processors
Worms vs. perimeters: the case for hard-LANs
Interconnection Network for Tightly Coupled Accelerators Architecture
Evaluation of SCSI over TCP/IP and SCSI over fibre channel connections
Efficient Multi-Path NVLink/PCIe-Aware UCX based Collective Communication for Deep Learning
An Efficient Hardware-Based Multi-hash Scheme for High Speed IP Lookup
Characterizing Communication Patterns in Distributed Large Language Model Inference
IEEE Symposium on High-Performance Interconnects, HOTI 2020, Piscataway, NJ, USA, August 19-21, 2020
Lightweight, Packet-Centric Monitoring of Network Traffic and Congestion Implemented in P4
Keynote: High-Speed Networking and the Race to Zero
AF-QCN: Approximate Fairness with Quantized Congestion Notification for Multi-tenanted Data Centers
24th IEEE Annual Symposium on High-Performance Interconnects, HOTI 2016, Santa Clara, CA, USA, August 24-26, 2016
Quality-of-Service Provision for BXI3-Based Interconnection Networks
ETA: experience with an Intel® Xeon™ processor as a packet processing engine
Evaluation of an Integrated PCI Express IO Expansion and Clustering Fabric
Characterizing Traffic Locality in 3D NoC-Based CMPs Using a Path-Based Partitioning Method
Network I/O Acceleration in Heterogeneous Multicore Processors
Sp2 high-performance switch architecture
Can Parallel Replication Benefit Hadoop Distributed File System for High Performance Interconnects?
Highly Integrated 4 Tbps Silicon Photonic IC for Compute Fabric Connectivity
Tnet: a reliable system area network for I/O and IPC
A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers
NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication
Scalability Port: A Coherent Interface for Shared Memory Multiprocessors
Demystifying NCCL: An In-Depth Analysis of GPU Communication Protocols and Algorithms
Loosely Coupled TCP Acceleration Architecture
COnfigurable Network Protocol Accelerator (COPA) † : An Integrated Networking/Accelerator Hardware/Software Framework
Stonehenge: a fault-tolerant real-time network-attached storage device
Designing low cost gigabit FC-2 silicon
Path2SL: Optimizing Head-of-Line Blocking Reduction in InfiniBand-Based Fat-Tree Networks
IEEE 19th Annual Symposium on High Performance Interconnects, HOTI 2011, Santa Clara, CA, USA, August 24-26, 2011
Addressing Queuing Bottlenecks at High Speeds
Deadlock-Free Routing for Full-Mesh Networks Without Using Virtual Channels
Design of Interconnection Networks
bittide: Control Time, Not Flows
13th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2005), 17-19 August 2005, Stanford, CA, USA
Optics in Future Data Center Networks
Coherency Hub Design for Multi-Node Victoria Falls Server Systems
A High Speed Hardware Scheduler for 1000-Port Optical Packet Switches to Enable Scalable Data Centers
Scalable collective communication on the ASCI Q machine
A Middle Ground between CAMs and DAGs for High-Speed Packet Classification
A dual-level matching algorithm for 3-stage Clos-network packet switches
A Clos-Network Switch Architecture Based on Partially-Buffered Crossbar Fabrics
The Impact of Optics on HPC System Interconnects
Two virtual memory mapped network interface designs
Architecture and Hardware for Scheduling Gigabit Packet Streams
The Alpha 21364 network architecture
Silicon Nanophotonic Network-on-Chip Using TDM Arbitration
Efficient multicast on a terabit router
RHiNET-3/SW: an 80-Gbit/s high-speed network switch for distributed parallel computing
TCP Pacing in Data Center Networks
Performance Measurement of an Integrated NIC Architecture with 10GbE
2019 IEEE Symposium on High-Performance Interconnects, HOTI 2019, Santa Clara, CA, USA, August 14-16, 2019
TCP switching: exposing circuits to IP
Panel: HotI 2025
FPsPIN: An FPGA-Based Open-Hardware Research Platform for Processing in the Network
Optics for Enabling Future HPC Systems
Design Exploration of Optical Interconnection Networks for Chip Multiprocessors
22nd IEEE Annual Symposium on High-Performance Interconnects, HOTI 2014, Mountain View, CA, USA, August 26-28, 2014
Dynamic scheduling of optical data bursts in time-domain wavelength interleaved networks
Cost-Effective Optics: Enabling the Exascale Roadmap
A New Mechanism to Identify Congesting Packets in High-Performance Interconnection Networks
Resilient network infrastructures for global grid computing
Isolated Trees in Multi-Tenant Fat Tree Datacenters for In-Network Computing
Accelerating Frontier MoE Training with 3D Integrated Optics
Simple Fairness Protocols for Daisy Chain Interconnects
Versal Network-on-Chip (NoC)
Quasi Fat Trees for HPC Clouds and Their Fault-Resilient Closed-Form Routing
iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture
15th Annual IEEE Symposium on High-Performance Interconnects, HOTI 2007, Stanford, CA, USA, August 22-24, 2007
The Ninth Symposium on High Performance Interconnects, HOTI '01, Stanford, CA, USA, August 22-24, 2001
Compute Express Link®: An open industry-standard interconnect enabling heterogeneous data-centric computing
Optimised Global Reduction on QsNet II
High-Speed, Short-Latency Multipath Ethernet Transport for Interconnections
Micro-benchmark level performance comparison of high-speed cluster interconnects
Rx Stack Accelerator for 10 GbE Integrated NIC
A Single-Cycle Multi-Match Packet Classification Engine Using TCAMs
PCI Express® 6.0 Specification at 64.0 GT/s with PAM-4 signaling: a low latency, high bandwidth, high reliability and cost-effective interconnect
Evaluation of a wireless enterprise backbone network architecture
Congestion Control in InfiniBand Networks
Message from the General Chairs HOTI 2024
Low-latency communication over ATM networks using active messages
Scaling Optical Interconnects in Datacenter Networks Opportunities and Challenges for WDM
Short and Fat: TCP Performance in CEE Datacenter Networks
Clocking Links in Multi-chip Packages: A Case Study
Virtualizing the Net - a strategy for enabling network innovation [Keynote 2]
Amon: An Advanced Mesh-like Optical NoC
Multi-root Share of Single-Root I/O Virtualization (SR-IOV) Compliant PCI Express Device
Implementation and Evaluation of Network Interface and Message Passing Services for TianHe-1A Supercomputer
Exploring Data Vortex Network Architectures
The Quadrics network (QsNet): high-performance clustering technology
Breaking the Connection: RDMA Deconstructed
Layered protocol wrappers for Internet packet processing in reconfigurable hardware
Intel® Omni-path Architecture: Enabling Scalable, High Performance Fabrics
Design of a system for real-time worm detection
Telecentric Optics for Free-Space Optical Link
WDM Optical Interconnect Architectures Under Two Connection Models
Silicon Photonic Accelerated Memory Pooling for Efficient Compute Resource Allocation
Ensuring Deadlock-Freedom in Low-Diameter InfiniBand Networks
Traffic Optimization in Multi-layered WANs Using SDN
Reuse Distance Based Circuit Replacement in Silicon Photonic Interconnection Networks for HPC
Network Processing on an SPE Core in Cell Broadband Engine
Improving Non-minimal and Adaptive Routing Algorithms in Slim Fly Networks
TCP-Splitter: A TCP/IP Flow Monitor in Reconfigurable Hardware
Network Assisted Non-Contiguous Transfers for GPU-Aware MPI Libraries
17th IEEE Symposium on High Performance Interconnects, HOTI 2009, New York, New York, USA, August 25-27, 2009
Performance Analysis and Evaluation of PCIe 2.0 and Quad-Data Rate InfiniBand
Winning with Pinning in NoC
Scalable Opto-Electronic Network (SOENet)
Network substrate for parallel processing on a workstation cluster
In-Network Compression for Accelerating IoT Analytics at Scale
Control Path Implementation for a Low-Latency Optical HPC Switch
Message from the TPC Chairs: HOTI 2024
Interconnect Challenges in a Many Core Compute Environment
High-speed Host Interfaces to ATM Networks
On the Impact of Routing Algorithms in the Effectiveness of Queuing Schemes in High-Performance Interconnection Networks
Leveraging Performance of Multiroot Data Center Networks by Reactive Reroute
New World Campus networking
Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects
14th IEEE Symposium on High-Performance Interconnects, HOTI'06, Stanford, CA, USA, August 23-25, 2006
The Sun Fireplane SMP interconnect in the Sun Fire 3800-6800
Efficient Implementation of Security Applications in OpenFlow Controller with FleXam
Optimized Routing for Large-Scale InfiniBand Networks
Internet infrastructure security
A family of ASIC devices for next generation distributed packet switches with QoS support for IP and ATM
Low Power Passive Equalizer Design for Computer Memory Links
Latency Critical Operation in Network Processors
Optical Interconnects in the Data Center
16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 26-28 August 2008, Stanford, CA, USA
Quality of service guarantee on 802.11 networks
Designing Optimized MPI Broadcast and Allreduce for Many Integrated Core (MIC) InfiniBand Clusters
Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-Scale Computer with Proximity Communication
Backlog-Aware Crossbar Schedulers: A New Algorithm and its Efficient Hardware Implementation
Race Cars vs. Trailer Trucks: Switch Buffers Sizing vs. Latency Trade-Offs in Data Center Networks
Scalable High-Radix Modular Crossbar Switches
PCI for multimedia applications
A low latency approach to delivering alternate protocols with coherency and memory semantics using PCI Express® 6.0 PHY at 64.0 GT/s
Enhanced Overloaded CDMA Interconnect (OCI) Bus Architecture for On-Chip Communication
25th IEEE Annual Symposium on High-Performance Interconnects, HOTI 2017, Santa Clara, CA, USA, August 28-30, 2017
Photonic NoC for DMA Communications in Chip Multiprocessors
Belief-Propagation Assisted Scheduling in Input-Queued Switches
SIFT: Snort Intrusion Filter for TCP
Accelerating Spark with RDMA for Big Data Processing: Early Experiences
Unified Collective Communication (UCC): An Unified Library for CPU, GPU, and DPU Collectives
Battle of the BlueFields: An In-Depth Comparison of the BlueField-2 and BlueField-3 SmartNICs
CMOS Photonics - Bringing Moore's Law to Optical Interconnect
Placement of Virtual Network Functions in Hybrid Data Center Networks
Sorting and Searching Using Ternary CAMs
Hotpads - macro-dells for gigabit I/O
A Flow Table-Based Design to Approximate Fairness
Reliable and Time-efficient Virtualized Function Placement
High Capacity On-Package Physical Link Considerations
In-network reductions on multi-dimensional HyperX
A Case Study in I/O Disaggregation using PCI Express Advanced Switching Interconnect (ASI)
Implementing Ultra Low Latency Data Center Services with Programmable Logic
Synfinity II-a high-speed interconnect with 2 GBytes/sec self-configurable physical link
Impact of InfiniBand DC Transport Protocol on Energy Consumption of All-to-All Collective Algorithms
Demonstration of a Single-Lane 80 Gbps PAM-4 Full-Duplex Serial Link
Remote Direct Memory Access over the Converged Enhanced Ethernet Fabric: Evaluating the Options
A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support
Performance Analysis and Evaluation of Mellanox ConnectX InfiniBand Architecture with Multi-Core Platforms
Bandwidth Scaling for AI Interconnect - More Wavelengths versusMore Fiber?
Internet Infrastructure Security
Tutorial: Designing High-End Computing Systems with Infiniband and 10-Gigabit Ethernet
Performance Characterization of Large Language Models on High-Speed Interconnects
High-Speed and Low-Power Network Search Engine Using Adaptive Block-Selection Scheme
Tutorial 4: Mobile Ad Hoc Networking: Medium Access Control and Routing Protocols
An FPGA Platform for Hyperscalers
Performance Characterization of a 10-Gigabit Ethernet TOE
A Scalable Switch for Service Guarantees
Tutorial: Infiniband and 10-Gigabit Ethernet for Dummies
Architecture and implementation of the reliable router
23rd IEEE Annual Symposium on High-Performance Interconnects, HOTI 2015, Santa Clara, CA, USA, August 26-28, 2015
A Multilevel NOSQL Cache Design Combining In-NIC and In-Kernel Caches
A wave-pipelined on-chip interconnect structure for networks-on-chips
Proceedings of the 11th Annual IEEE Symposium on High Performance Interconnects, HOTIC 2003, August 20-22, 2003, Stanford, CA, USA
On-Die Interconnect and Other Challenges for Chip-Level Multi-Processing
A high speed, metropolitan are, ATM network
Occupancy Sampling for Terabit CEE Switches
Reducing the complexity of ATM Host Interfaces
Optimized Upstream Scheduling in Broadband Cable Networks
Network processors as building blocks in overlay networks
Programmable FPGA-based Memory Controller
Memory Scalability Evaluation of the Next-Generation Intel Bensley Platform with InfiniBand
Can Memory-Less Network Adapters Benefit Next-Generation InfiniBand Systems?
EtherNET vs. EtherNOT
Strategies for Mitigating TCAM Space Bottlenecks
Tutorial 3: High-Speed Networking: A Systematic Approach to High-Bandwidth Low-Latency Communication
A rule grouping technique for weight-based TCAM coprocessors [packet classification application]
Myrinet-a gigabit-per-second local-area network
Leveraging Optical Interconnects in Future Supercomputers and Servers
Utilizing HPC Network Technologies in High Energy Physics Experiments
HPP Switch: A Novel High Performance Switch for HPC
Power Aware Management of Packet Switches
Adaptive Routing Strategies for Modern High Performance Networks
Optical Interconnects for Present and Future High-Performance Computing Systems
160Gb/s Serial Line Rates in a Monolithic Optoelectronic Multistage Interconnection Network
Using an ATM interconnect as a high performance I/O backplanet
Constraint Repetition Inspection for Regular Expression on FPGA
The BXI Interconnect Architecture
Data Center Switch Architecture in the Age of Merchant Silicon
Measured performance of an-in-building cellular radio network
Designing Energy-Efficient Low-Diameter On-Chip Networks with Equalized Interconnects
A case for NOW (networks-of-workstations)
On-Package Memory with Universal Chiplet Interconnect Express (UCIe): A Low Power, High Bandwidth, Low Latency and Low Cost Approach
Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing
Clustered Linked List Forest for IPv6 Lookup
Wireless Wars: Wi-Fi vs. GPRS vs. 3G
A High-Speed Optical Multi-Drop Bus for Computer Interconnections
Design of a high-speed optical interconnect for scalable shared memory multiprocessors
Design of Randomized Multichannel Packet Storage for High Performance Routers
Minimizing Delay in Shared Pipelines
OWN: Optical and Wireless Network-on-Chip for Kilo-core Architectures
A Reconfigurable Architecture for Multi-Gigabit Speed Content-Based Routing
Delay Tolerant Networking
IEEE 20th Annual Symposium on High-Performance Interconnects, HOTI 2012, Santa Clara, CA, USA, August 22-24, 2012
High-Quality Fault-Resiliency in Fat-Tree Networks (Extended Abstract)
Panel - Ethernet vs. HPC: Can the hyperscale ethernet data center handle all workloads?
On the techniques of clock extraction and oversampling
General Chairs' Message
Introduction to Programming High Performance Applications on the CELL Broadband Engine
Centralized and Distributed Topology Discovery Service Implementations
PathScale InfiniPath: A First Look
Impact of Inter-application Contention in Current and Future HPC Systems
OC-3072 packet classification using BDDs and pipelined SRAMs
Csrgan: Medical Image Super-Resolution Using A Generative Adversarial Network
Radiomic Feature Stability Analysis Based on Probabilistic Segmentations
LaSCL-PLC: Lesion-Aware Supervised Contrastive Learning for Patient-Level Classification of Brainstem and Cerebellar Hemangioblastomas
DTI registration with exact finite-strain differential
Unsupervised Learning-Based Large Deformation Diffeomorphic Metric Mapping for Fast Image Registration
Sparse Representation of Deformable 3D Organs
Triplet-Constraint Transformer with Multi-Scale Refinement for Dose Prediction in Radiotherapy
MRI Reconstruction Via Cascaded Channel-Wise Attention Network
Cell segmentation and tracking in phase contrast images using graph cut with asymmetric boundary costs
Quantitative Analysis of Volumetric TPLSM Data
High resolution T1 estimation from multiple low resolution magnetic resonance images
Sosegformer: A Cross-Scale Feature Correlated Network For Small Medical Object Segmentation
Automated Actin Filament Segmentation, Tracking and TIP Elongation Measurements Based on Open Active Contour Models
Elastic Registration of Gel Electrophoresis Images Based on Landmarks and Intensities
Diffusion Smoothing on Brain Surface via Finite Element Method
Cortical Foldingprints for Infant Identification
Joint Reconstruction of Dynamic PET Activity and Kinetic Parametric Images Using Learnable Descent Framework
Classification of tumor histopathology via sparse feature learning
Semantic Segmentation, Detection AND Localisation of Mucosal Lesions from Gastrointestinal Endoscopic Images Using SUMNET
High-order concept discovery in functional brain imaging
Computer-Aided Detection of Colonic Diverticular Disease
A box spline calculus for computed tomography
Focusnet++: Attentive Aggregated Transformations For Efficient And Accurate Medical Image Segmentation
NeuroSoL: Automated classification of neurons using the sorted Laplacian of a graph
Multiscale distribution preserving autoencoders for plaque detection in intravascular optical coherence tomography
A vector momenta formulation of diffeomorphisms for improved geodesic regression and atlas construction
Rapid semi-automated segmentation and analysis of neuronal morphology and function from confocal image data
Automated identification of neuronal activity from calcium imaging by sparse dictionary learning