yusuke1997/dblp-id-title huggingface dataset:
An FFT Accelerator Using Deeply-coupled RISC-V Instruction Set Extension for Arbitrary Number of Points
A modular systolic 2-D torus for the general knapsack problem
Fast Radix-4 Retimed Division with Selection by Comparisons
A Linear Array Parallel Image Processor: SliM-II
Matrix-matrix multiplications and fault tolerance on hypercube multiprocessors
Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications
Parallelized Architecture of Multiple Classifiers for Face Detection
Reconfigurable hardware for molecular biology computing systems
Techniques for Yield Enhancement of VLSI Adders
A Scalable FPGA Design for Cloud N-Body Simulation
An application-aware approach to systems support for big data
Application-set driven exploration for custom processor architectures
Number Theoretic Transform Architecture suitable to Lattice-based Fully-Homomorphic Encryption
Refining Instruction Set Architecture for High-Performance Multimedia Processing in Constrained Environments
RETROSPECTIVE: Table-Based Polynomials for Fast Hardware Function Evaluation
xTern: Energy-Efficient Ternary Neural Network Inference on RISC-V-Based Edge Systems
Run-Time Error Detection in Polynomial Basis Multiplication Using Linear Codes
An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators
Massive spatial query on the Kepler architecture
An Improved Systolic Architecture for LU Decomposition
FusedGCN: A Systolic Three-Matrix Multiplication Architecture for Graph Convolutional Networks
Reconfigurable Computing and Electronic Nanotechnology
Color Space Conversion for MPEG decoding on FPGA-augmented TriMedia Processor
On the performance of code block segmentation for LTE-advanced
Architecture and realization of a multi signal processor system
Unifying CORDIC and Box-Muller algorithms: An accurate and efficient Gaussian Random Number generator
PVMC: Programmable Vector Memory Controller
BWOLF: Bit-Width Optimization for Statistical Divergence with -Logarithmic Functions
Fault-tolerant array processors using N-and-half-track switches
LP-BNN: Ultra-low-Latency BNN Inference with Layer Parallelism
The Denormal Logarithmic Number System
Reduced Delay BCD Adder
Architectural Support for Arithmetic in Optimal Extension Fields
Fast Energy Estimation Through Partial Execution of HPC Applications
A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design
Efficient systolization of cyclic convolution for systolic implementation of sinusoidal transforms
Double-Pumping the Interconnect for Area Reduction in Coarse-Grained Reconfigurable Arrays
Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware
Adaptive scalable SVD unit for fast processing of large LSE problems
Mapping different node types of dependence graphs into the same processing element
Array Processing Using Alternate Arithmetic - A 20 Year Legacy
Architectures for Green routers
Recent Developments in Configurable and Extensible Processors
A Novel Pipelined Threads Architecture for AES Encryption Algorithm
Affine Nested Loop Programs and their Binary Parameterized Dataflow Graph Counterparts
On core and more: a design perspective for systems-on-a-chip
FPGA-based frequency estimation of a DFB laser using Rb spectroscopy for space missions
Data Alignments for Modular Time-Space Mappings of BLAS-like Algorithms
Describing Quantum Circuits with Systolic Arrays
A Digit-Serial Algorithm for the Discrete Logarithm Modulo 2 k
Explicit SIMD Programming for Asynchronous Applications
Enhancing RISC-V Vector Extension for Efficient Application of Post-Quantum Cryptography
On the computation of the reciprocal of floating point expansions using an adapted Newton-Raphson iteration
New arithmetic coder/decoder architectures based on pipelining
A systolic algorithm for the triangular Stein equation
From Tensor Algebra to Hardware Accelerators: Generating Streaming Architectures for Solving Partial Differential Equations
An Application Mapping Algorithm for Mesh-Based Hybrid Optical Network-on-Chip Architecture
Private configuration environments (PCE) for efficient reconfiguration, in CGRAs
Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers
An Area-Efficient LDPC Decoder Architecture and Implementation for CMMB Systems
An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform
Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration
More than 50 years of parallel processing and still no easy path to speedup
Design Space Exploration for Energy-Efficient Secure Sensor Network
An optimisation methodology for array mapping of affine recurrence equations in video and image processing
Dual-purpose custom instruction identification algorithm based on Particle Swarm Optimization
A compression-based morphable PCM architecture for improving resistance drift tolerance
Pipelined FPGA implementation of numerical integration of the Hodgkin-Huxley model
High-Performance, Area-Efficient and Predictable Matrix Multiplication for ASIC
Minimizing memory requirements in rate-optimal schedules
A Vector Multiprocessor for Real-Time Multi-User Detection in Spread-Spectrum Communication
Parameterized Looped Schedules for Compact Representationof Execution Sequences
Linear arrays for residue mappers
Hardware acceleration of Private Information Retrieval protocols using GPUs
Instruction Set Extension for Fast Elliptic Curve Cryptography over Binary Finite Fields GF(2m)
A comparison of correntropy-based feature tracking on FPGAs and GPUs
Reconfigurable computing middleware for application portability and productivity
High-performance FPGA implementation of equivariant adaptive separation via independence algorithm for Independent Component Analysis
Convergence of design and fabrication technologies, a key enabler for HW-SW integration
RFC-HyPGCN: A Runtime Sparse Feature Compress Accelerator for Skeleton-Based GCNs Action Recognition Model with Hybrid Pruning
Node merging: A transformation on bit-level dependence graphs for efficient VLSI array design
A high-speed and large-scale dictionary matching engine for Information Extraction systems
Transforming a linear algebra core to an FFT accelerator
Microkernel hypervisor for a hybrid ARM-FPGA platform
Faults, Error Bounds and Reliability of Nanoelectronic Circuits
High-speed VLSI architectures for soft-output Viterbi decoding
Does arithmetic logic dominate data movement? a systematic comparison of energy-efficiency for FFT accelerators
Context-Aware Process Networks
Systolic-based computing machinery for radar signal processing studies
Efficient FeFET Crossbar Accelerator for Binary Neural Networks
Real-time H/W Implementation of the Approximate Discrete Radon Transform
Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics
Efficient architecture of a programmable block matching processor
Power dissipation challenges in multicore floating-point units
FPGA-Based Acceleration for EMT Simulation of Electrical Distribution Network
BiSME: A Hardware Coprocessor to Perform Signature Matching at Multi-Gigabit Rates
Tradeoffs Between Quality of Results and Resource Consumption in a Recognition System
Extensions to linear mapping for regular arrays with complex processing elements
Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields
Implications for Hardware Acceleration of Malware Detection
Design and Implementation of an Efficient and Power-Aware Architecture for Skin Segmentation in Color Video Stream
Maestro: A Memory-on-Logic Architecture for Coordinated Parallel Use of Many Systolic Arrays
SHA-3 Instruction Set Extension for A 32-bit RISC processor architecture
iKnowFirst: An Efficient DPU-Assisted Compaction for LSM-Tree-Based Key-Value Stores
Accelerating HAC estimation for multivariate time series
Data compiling for systems of affine recurrence equations
High Performance VLSI Architecture Design for H.264 CAVLC Decoder
A scalable and compact systolic architecture for linear solvers
MSA-CUDA: Multiple Sequence Alignment on Graphics Processing Units with CUDA
A Decomposition Method For Efficient Use Of Distributed Supercomputers For Finite Element Applications
Efficient implementation of structured long block-length LDPC codes
A FPGA-HBM-Based Hardware Streaming Accelerator for GNN Sampling
31st IEEE International Conference on Application-specific Systems, Architectures and Processors , ASAP 2020, Manchester, United Kingdom, July 6-8, 2020
A parallel hardware architecture for connected component labeling based on fast label merging
Concurrent systolic architecture for high-throughput implementation of 3-dimensional discrete wavelet transform
Digit systolic algorithms for fine-grain architectures
Security processor with quantum key distribution
Application specific VLSI architectures based on De Bruijn graphs
An Efficient Convolution Engine based on the À-trous Spatial Pyramid Pooling
27th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2016, London, United Kingdom, July 6-8, 2016
Answer Fast: Accelerating BERT on the Tensor Streaming Processor
Graphic processors to speed-up simulations for the design of high performance solar receptors
Accelerating MRI Uncertainty Estimation with Mask-Based Bayesian Neural Network
High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension
Out-of-Order and Recursive RAS: A Return Address Stack Design on High Performance Processor
RO-SVD: A Reconfigurable Hardware Copyright Protection Framework for AIGC Applications
Operation shuffling over cycle boundaries for low energy L0 clustering
Array Aware Training/Pruning: Methods for Efficient Forward Propagation on Array-based Neural Network Accelerators
CHARMED: A Multi-Objective Co-Synthesis Framework for Multi-Mode Embedded Systems
SLATE: Managing Heterogeneous Cloud Functions
A compact and scalable RNS architecture
Regular array synthesis using ALPHA
A dynamically reconfigurable wavefront array architecture for evaluation of expressions
The light at the end of the CMOS tunnel
A defect tolerant systolic array implementation for real time image processing
Low energy motion estimation via selective aproximations
F-CNN: An FPGA-based framework for training Convolutional Neural Networks
OpenCL-based design pattern for line rate packet processing
CoNAX: Towards Comprehensive Co-Design Neural Architecture Search Using HW Abstractions
Interfacing FPGA/VLSI Processor Arrays
A Datapath Generator for Full-Custom Macros of Iterative Logic Arrays
The Molen FemtoJava Engine
29th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2018, Milano, Italy, July 10-12, 2018
Constant-time triangulation problems on reconfigurable meshes
Long Live Small Fan-in Majority Gates Their Reign Looks Like Coming!
An efficient algorithm for image-template product on SIMD mesh connected computers
Unleashing the performance potential of CPU-GPU platforms for the 3D atmospheric Euler solver
Partitioning Conditional Data Flow Graphs for Embedded System Design
Multicore processors as Array Processors: Research Opportunities
From Bit Level Systolic Arrays to HDTV Processor Chips
On the characterization of OpenCL dwarfs on fixed and reconfigurable platforms
Parallel Discrete Event Simulation of Molecular Dynamics Through Event-Based Decomposition
SpDCache: Region-Based Reduction Cache for Outer-Product Sparse Matrix Kernels
A logical framework to prove properties of Alpha programs
FPGA Based Particle Identification in High Energy Physics Experiments
The Systolic Design of a Block Regularised Parameter Estimator using Hierarchical Signal Flow Graphs
Accurate Function Approximations by Symmetric Table Lookup and Addition
Diagnosis Algorithm for Mobility-Oriented System
A database machine based on surrogate files
Mapping arbitrary projections for volume rendering onto an array processor
Sum-of-product architectures computing just right
Memoryless RNS-to-binary converters for the {2 n+1 - 1, 2 n , 2 n - 1} moduli set
Designing systolic arrays for integer GCD computation
Efficient Synchronization for NR-REDCAP Implemented on a Vector DSP
Dynamic systolic associative memory chip
F-E3D: FPGA-based Acceleration of an Efficient 3D Convolutional Neural Network for Human Action Recognition
Linear scheduling is close to optimality
An Adaptable And Scalable Asymmetric Cryptographic Processor
SMPTE ST 2110 Compliant Scalable Architecture on FPGA for end to end Uncompressed Professional Video Transport Over IP Networks
New insights on Ling adders
A Unified Backend for Targeting FPGAs from DSLs
Performance Evaluation of a Novel Direct Table Lookup Method and Architecture with Application to 16-bit Integer Functions
Design space exploration for reliable mm-wave wireless NoC architectures
Integrated Design of AES (Advanced Encryption Standard) Encrypter and Decrypter
A Family of Parallel-Pre.x Modulo 2n - 1 Adders
Fast and Accurate Training of Ensemble Models with FPGA-based Switch
Zodiac: System architecture implementation for a high-performance Network Security Processor
Minimizing Synchronization Overhead in Statically Scheduled Multiprocessor Systems
Algorithmic mapping of neural network models onto parallel SIMD machines
A Configurable Framework for Hough-Transform-Based Embedded Object Recognition Systems
A scalable bit-sequential SIMD array for nearest-neighbor classification using the city-block metric
Configurable computing: the catalyst for high-performance architectures
Reduce, Reuse, Recycle (R 3 ): A design methodology for Sparse Matrix Vector Multiplication on reconfigurable platforms
FPGA-Based Network Microburst Analysis System with Flow Specification and Efficient Packet Capturing
Parametric Analysis of Polyhedral Iteration Spaces
An efficient embedded multi-ported memory architecture for next-generation FPGAs
SIMD/MIMD Dynamically-Reconfigurable Architecture for High-Performance Embedded Vision Systems
Reconfigurable Processing With Field Programmable Gate Arrays
Next-generation massively parallel short-read mapping on FPGAs
LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks
Analyzing GPU Energy Consumption in Data Movement and Storage
A practical measure of FPGA floating point acceleration for High Performance Computing
Scalar Processing Overhead on SIMD-Only Architectures
Application Specific Processing: A Tools Approach
A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing
Accelerating Recurrent Neural Networks for Gravitational Wave Experiments
Systolic design of a new finite field division/inverse algorithm
Energy efficient canonical huffman encoding
22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011
Accelerating a Virtual Ecology Model with FPGAs
CORDIC-based computation of arccos and arcsin
Automatic Synthesis of Customized Local Memories for Multicluster Application Accelerators
Input buffering requirements of a Systolic Array for the Inverse Discrete Wavelet Transform
Pipelining: just another transformation
16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece
Synthesis of a class of data format converters with specified delays
Parallel Sequence Comparison and Alignment
Fast multivariate signature generation in hardware: The case of rainbow
A New Hardware Approach to Self-Organizing Maps
ASBNN: Acceleration of Bayesian Convolutional Neural Networks by Algorithm-hardware Co-design
A Mesh-of-Trees Interconnection Network for Single-Chip Parallel Processing
The UCSC Kestrel Application-Unspecific Processor
A VLSI Architecture for Advanced Video Coding Motion Estimation
A Self-Reconfigurable Implementation of the JPEG Encoder
Image caption generation method based on an interaction mechanism and scene concept selection module
Compositional Technique for Synthesising Multi-Phase Regular Arrays
Preface ASAP 2023
HW/SW co-design based implementation of Gas discrimination
An Efficient Hardware Support for Control Data Validation
NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm
Unified FPGA Design of Kyber and Dilithium with Provable Fault Tolerance
Transparent Heterogeneous Cloud Acceleration
Calculus of space-optimal mappings of systolic algorithms on processor arrays
Transaction Specific Virtual Channel Allocation in QoS Supported On-chip Communication
Fast Heterogeneous Task Mapping for Reducing Edge DNN Latency
A reconfigurable processor array with routing LSIs and general purpose DSPs
Sparse matrix-vector multiply on the Texas Instruments C6678 Digital Signal Processor
Highly scalable on-the-fly interleaved address generation for UMTS/HSPA+ parallel turbo decoder
On Supernode Transformation with Minimized Total Running Time
Analysis and Optimization of Block LU Decomposition for Execution on Tightly Coupled Processor Arrays
Extreme scale computer architecture: Energy efficiency from the ground up
Fast Bit Compression and Expansion with Parallel Extract and Parallel Deposit Instructions
Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms
Memory copies in multi-level memory systems
Hierarchical Dataflow Model for efficient programming of clustered manycore processors
256-State Rate 1/2 Viterbi Decoder on TTA Processor
Function-Level Processor (FLP): Raising efficiency by operating at function granularity for market-oriented MPSoC
COIN: Combinational Intelligent Networks
Implementing and Parallelizing Real-time Lane Detection on Heterogeneous Platforms
A Methodology for User-Oriented Scalability Analysis
Subband filtering: Cordic modulation and systolic quadrature mirror filter tree
Real-Time Order Book Building and Snapshot Generating for High Frequency Trading on FPGA
Design of a VLSI circuit for on-line evaluation of several elementary functions using their Taylor expansions
Audio DSP to FPGA Compilation
Fully static multiprocessor realization for real-time recursive DSP algorithms
Parallel processing of complex data using quaternion and pseudo-quaternion CORDIC algorithms
An approach of processor core customization for stencil computation
Building blocks for a new generation of application specific computing systems
An Efficient Application Specific Instruction Set Processor (ASIP) for Tensor Computation
Hardware design and analysis of efficient loop coarsening and border handling for image processing
An integrated development toolset and implementation methodology for partially reconfigurable system-on-chips
Systolic VLSI compiler (SVC) for high performance vector quantisation chips
A wavefront array processor for on the fly processing of digital video streams
An effective New CRT based reverse converter for a novel moduli set {2 2n+1 - 1, 2 2n+1 , 2 2n - 1}
Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems
Oikonomos: An Opportunistic, Deep-Learning, Resource-Recommendation System for Cloud HPC
Systolic two-port adaptor for high performance wave digital filtering
An optimal algo-tech-cuit for the knapsack problem
Design of throughput-optimized arrays from recurrence abstractions
30th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2019, New York, NY, USA, July 15-17, 2019
A parallel sorting algorithm on an eight-neighbor processor array
Recomputing by Operand Exchanging: A Time-redundancy Approach for Fault-tolerant Neural Networks
A Domain Specific Language for accelerated Multilevel Monte Carlo simulations
A systolic rank revealing QR algorithm
IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2014, Zurich, Switzerland, June 18-20, 2014
An efficient computation model for coarse grained reconfigurable architectures and its applications to a reconfigurable computer
CusComNet: A customisable network for reconfigurable heterogeneous clusters
Compilation of narrowband spectral detection systems for linear MIMD machines
A Virtual Image Accelerator for Graph Cuts Inference on FPGA
Parallel Multi Channel convolution using General Matrix Multiplication
Oolong: A Baseband processor extension to the RISC-V ISA
Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis
Looking Back 25 Years to the HP Labs ASIC Synthesis Project, PICO
A VLSI Architecture for Object Recognition Using Tree Matching
Reconfigurable SWP Operator for Multimedia Processing
A Convolutional Spiking Neural Network Accelerator with the Sparsity-Aware Memory and Compressed Weights
Energy-efficient floating-point arithmetic for software-defined radio architectures
Architecture for quadruple precision floating point division with multi-precision support
Accelerating NoC-Based MPI Primitives via Communication Architecture Customization
On the performance of GPU public-key cryptography
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers
A Fault-Tolerant Modulus Replication Complex FIR Filter
Evaluating Products of Non Linear Functions by Indirect Bipartite Table Lookup
Advances in Bit Width Selection Methodology
The Design of a Novel Object-oriented Processor : OOMIPS
A Multiprocessor System for Real Time High Resolution Image Correlation
Dynamic pipeline-partitioned video decoding on symmetric stream multiprocessors
A high efficient memory architecture for H.264/AVC motion compensation
Efficient pointer management of stack data for software managed multicores
Managing Computation Offloading from Edge Devices to a Reconfigurable Edge Cloud
A scalable RC architecture for mean-shift clustering
Hardware Implementation of an Elliptic Curve Processor over GF(p)
SONA: An Accelerator for Transform-Domain Neural Networks with Sparse-Orthogonal Weights
Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations
An analog VLSI array processor for classical and connectionist AI
Unified Radix-4 Multiplier for GF(p) and GF(2^n)
The design of a high-performance scalable architecture for image processing applications
A new formulation of the mapping conditions for the synthesis of linear systolic arrays
Power6 Decimal Divide
An interpolation-based approach to multi-parameter performance modeling for heterogeneous systems
A Massively Parallel Coprocessor for Convolutional Neural Networks
A processor-time minimal systolic array for transitive closure
Recursive algorithms for AR spectral estimation and their array realizations
Modelling communication overhead for accessing local memories in hardware accelerators
IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2007, Montréal, Québec, Canada, July 8-11, 2007
Randomized windows for secure scalar multiplication on elliptic curves
Discrete wavelet transforms in VLSI
Parallel architecture for a pel-recursive motion estimation algorithm
Elliptic Curve point multiplication on GPUs
SieveMem: A Computation-in-Memory Architecture for Fast and Accurate Pre-Alignment
Determination of the Processor Functionality in the Design of Processor Arrays
Discrete Lagrangian Method for Optimizing the Design of Multiplierless QMF Filter Banks
Low latency word serial CORDIC
Condensing an overload of parallel computing ingredients into a single architecture recipe
ReaLLM: A Trace-Driven Framework for Rapid Simulation of Large-Scale LLM Inference
Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit
A reconfigurable network-on-chip architecture for heterogeneous CMPs in the dark-silicon era
New Results on Array Contraction
Using shared library interposing for transparent application acceleration in systems with heterogeneous hardware accelerators
Fine-grain system architectures for systolic emulation of neural algorithms
Spacetime-minimal systolic architectures for Gaussian elimination and the algebraic path problem
A strategy for determining a Jacobi specific dataflow processor