yusuke1997/dblp-id-title huggingface dataset:
Dragon2006: blockage-aware congestion-controlling mixed-size placer
Learning from the Implicit Functional Hierarchy in an Analog Netlist
Multi-bend bus driven floorplanning
An effective congestion driven placement framework
Physical synthesis of bus matrix for high bandwidth low power on-chip communications
3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications
Physical Design Considerations of One-level RRAM-based Routing Multiplexers
Issues in global routing
Post-routing timing optimization with routing characterization
Case study for placement solutions in ispd11 and dac12 routability-driven placement contests
Novel pulsed-latch replacement based on time borrowing and spiral clustering
Is your layout density verification exact?: a fast exact algorithm for density calculation
Optimal post-routing redundant via insertion
Efficient Runtime Power Modeling with On-Chip Power Meters
Advanced routing in changing technology landscape
Noise driven in-package decoupling capacitor optimization for power integrity
Self-aligned double patterning aware pin access and standard cell layout co-optimization
An 8-core, 64-thread, 64-bit power efficient sparc soc (niagara2)
Proceedings of the 2006 International Symposium on Physical Design, ISPD 2006, San Jose, California, USA, April 9-12, 2006
Net cluster: a net-reduction based clustering preprocessing algorithm
Robust interconnect communication capacity algorithm by geometric programming
Delay-driven layer assignment in global routing under multi-tier interconnect structure
Construction of Latency-Bounded Clock Trees
A new era for CAD
ISPD 2024 Lifetime Achievement Award Bio
Layout impact of resolution enhancement techniques: impediment or opportunity?
Invited: Scaling Standard Cell Layout Using Track Height Compression and Design Technology Co-optimization
Capo: robust and scalable open-source min-cut floorplacer
Utilizing 2D and 3D rectilinear blocks for efficient IP reuse and floorplanning of 3D-integrated systems
How Deep Learning Can Drive Physical Synthesis Towards More Predictable Legalization
Software-driven Design for Domain-specific Compute
Analytical Mixed-Cell-Height Legalization Considering Average and Maximum Movement Minimization
An O ( n log n ) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane
Timing metrics for physical design of deep submicron technologies
Concurrent Guiding Template Assignment and Redundant via Insertion for DSA-MP Hybrid Lithography
RegularRoute: an efficient detailed router with regular routing patterns
A high-performance droplet router for digital microfluidic biochips
Tree Structures and Algorithms for Physical Design
Novel Transformer Model Based Clustering Method for Standard Cell Design Automation
Physical Design Challenges in the Chip Power Distribution Network
Floorplan and power/ground network co-synthesis for fast design convergence
To do or not to do hierarchical timing?
Open Cell Library in 15nm FreePDK Technology
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
Scalable CFET Cell Library Synthesis with A DRC-Aware Lookup Table to Optimize Valid Pin Access
ML-Based Wire RC Prediction in Monolithic 3D ICs with an Application to Full-Chip Optimization
Research directions for coevolution of rules and routers
Proceedings of the 2008 International Symposium on Physical Design, ISPD 2008, Portland, Oregon, USA, April 13-16, 2008
Pin Accessibility-Driven Detailed Placement Refinement
Buffered Steiner trees for difficult instances
Timing-driven, over-the-block rectilinear steiner tree construction with pre-buffering and slew constraints
Proceedings of the 1997 International Symposium on Physical Design, ISPD 1997, Napa Valley, California, USA, April 14-16, 1997
Learning Point Clouds in EDA
Physical design methodology for analog circuitsin a system-on-a-chip environment
The Pressing Need for Electromigration-Aware Physical Design
Bryan Preas: broad contributions to system engineering in the 2000's
Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs
Subwavelength optical lithography: challenges and impact on physical design
A practical clock tree synthesis for semi-synchronous circuits
Proceedings of the 2017 ACM on International Symposium on Physical Design, ISDP 2017, Portland, OR, USA, March 19-22, 2017
Integrating LR Gate Sizing in an Industrial Place-and-Route Flow
NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model
VLSI/PCB placement with obstacles based on sequence-pair
B-escape: a simultaneous escape routing algorithm based on boundary routing
Going with the flow: bridging the gap between theory and practice in physical design
ISPD 2006 Placement Contest: Benchmark Suite and Results
Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors
A regularity-driven fast gridless detailed router for high frequency datapath designs
An improved benchmark suite for the ISPD-2013 discrete cell sizing contest
Unified 3D-IC Multi-Chiplet System Design Solution
Switch-matrix architecture and routing for FPDs
Physical design: reminiscing and looking ahead
Solving hard instances of FPGA routing with a congestion-optimal restrained-norm path search space
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
Optimized is Not Always Optimal - The Dilemma of Analog Design Automation
Filling and slotting: analysis and algorithms
Optimizing for Power, Speed, Cost and Emissions in Automotive Drivetrains
Min-max placement for large-scale timing optimization
Towards a new benchmarking paradigm in EDA: analysis of equivalence class mutant circuit distributions
Placement challenges for structured ASICs
Litho and design: moore close than ever
A roadmap of CAD tool changes for sub-micron interconnect problems
SRC physical design top ten problem
Towards synthetic benchmark circuits for evaluating timing-driven CAD tools
CAD Opportunities with Hyper-Pipelining
Density gradient minimization with coupling-constrained dummy fill for CMP control
Multi-Stage CSM Timing Waveform Propagation Accelerated by NLDM Assistance
There is life left in ASICs
Clockless IC design using handshake technology
Congestion estimation during top-down placement
The scaling challenge: can correct-by-construction design help?
Multilevel routing with antenna avoidance
Leveling Up: A Trajectory of OpenROAD, TILOS and Beyond
Minimal skew clock embedding considering time variant temperature gradient
PANEL: EDA Challenges at Advanced Technology Nodes A
Transforming Global Routing Report into DRC Violation Map with Convolutional Neural Network
Kernel Mapping Techniques for Deep Learning Neural Network Accelerators
ISPD 2020 Physical Mapping of Neural Networks on a Wafer-Scale Deep Learning Accelerator
Design considerations for regular fabrics
Efficient multilayer routing based on obstacle-avoiding preferred direction steiner tree
On two-step routing for FPGAS
Indoor localization technology and algorithm issues
Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits
Metal-density driven placement for cmp variation and routability
ISPD placement contest updates and ISPD 2007 global routing contest
Completing high-quality global routes
An area-optimality study of floorplanning
SRAM dynamic stability verification by reachability analysis with consideration of threshold voltage variation
Efficient decoupling capacitor planning via convex programming methods
Deep Learning in the Enhanced Cloud
Power optimization for FPGA look-up tables
An enhanced global router with consideration of general layer directives
Multi-voltage floorplan design with optimal voltage assignment
SMT-Based Layout Synthesis Approaches for Quantum Circuits
3-D floorplanning using labeled tree and dual sequences
Physical design tools for hierarchy
Simultaneous clock and data gate sizing algorithm with common global objective
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs
PANEL: EDA Challenges at Advanced Technology Nodes C
Improved algorithms for link-based non-tree clock networks for skew variability reduction
I attended the nineteenth design automation conference
Cell architecture: key physical design features and methodology
Activity and register placement aware gated clock network design
Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects
Requirements for models of achievable routing
Reinforcement Learning Guided Detailed Routing for Custom Circuits
Probabilistic evaluation of solutions in variability-driven optimization
Solving the Physical Challenges for the Next Generation of Safety Critical & High Reliability Systems
Clock tree design challenges for robust and low power design
Common-Centroid FinFET Placement Considering the Impact of Gate Misalignment
A polynomial time exact algorithm for self-aligned double patterning layout decomposition
Trailblazing Physical Design Flows: Ralph Otten's Impact on Design Automation
Overcoming wireload model uncertainty during physical design
An efficient tile-based ECO router with routing graph reduction and enhanced global routing flow
Invited: AI-assisted Routing
Physical hierarchy generation with routing congestion control
Construction of realistic gate sizing benchmarks with known optimal solutions
Discrete buffer and wire sizing for link-based non-tree clock networks
Placement-Aware 3D Net-to-Pad Assignment for Array-Style Hybrid Bonding 3D ICs
Buffer insertion with adaptive blockage avoidance
Innovate or perish: FPGA physical design
Constrained "Modern" Floorplanning
Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure
Graphene based transistors: physics, status and future perspectives
TEG: a new post-layout optimization method
LiDAR: Automated Curvy Waveguide Detailed Routing for Large-Scale Photonic Integrated Circuits
Placement Initialization via Sequential Subspace Optimization with Sphere Constraints
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29 - April 1, 2015
Hardware Security For and Beyond CMOS Technology: An Overview on Fundamentals, Applications, and Challenges
The good, the bad, and the statistical
Recursive bisection placement: feng shui 5.0 implementation details
TSV-constrained micro-channel infrastructure design for cooling stacked 3D-ICs
Proceedings of the 2003 International Symposium on Physical Design, ISPD 2003, Monterey, CA, USA, April 6-9, 2003
Cypress: VLSI-Inspired PCB Placement with GPU Acceleration
Via Pillar-aware Detailed Placement
An exact algorithm for coupling-free routing
Mixed-size placement with fixed macrocells using grid-warping
Closing the smoothness and uniformity gap in area fill synthesis
Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor
Concurrent transistor sizing and buffer insertion by considering cost-delay tradeoffs
Parallel and Heterogeneous Timing Analysis: Partition, Algorithm, and System
Advanced Design Methodologies for Directed Self-Assembly
The Slow Start of Fast Spice: A Brief History of Timing
Global Placement Exploiting Soft 2D Regularity
MAPLE: multilevel adaptive placement for mixed-size designs
Snap-3D: A Constrained Placement-Driven Physical Design Methodology for Face-to-Face-Bonded 3D ICs
A comparative study of two Boolean formulations of FPGA detailed routing constraints
3DICs for tera-scale computing: a case study
TEMPO: Fast Mask Topography Effect Modeling with Deep Learning
Making a difference in EDA: a thank you to Bryan Preas for his contributions to the profession
Physical-aware system-level design for tiled hierarchical chip multiprocessors
Enabling System Design in 3D Integration: Technologies and Methodologies
Research Challenges in Security-Aware Physical Design
Prediction and reduction of routing congestion
Novel Methodology for Assessing Chip-Package Interaction Effects onChip Performance
Seeing the forest and the trees: Steiner wirelength optimization in placemen
Accurate clock mesh sizing via sequential quadraticprogramming
Learning from Experience: Applying ML to Analog Circuit Design
Automation of Analog IC Layout: Challenges and Solutions
Early analysis for power distribution networks
Analog/Mixed-Signal Layout Optimization using Optimal Well Taps
Partitioning with terminals: a "new" problem and new benchmarks
Scheduling and Physical Design
The ISPD global routing benchmark suite
A size scaling approach for mixed-size placement
The ISPD-2012 discrete cell sizing contest and benchmark suite
How Game Engines Can Inspire EDA Tools Development: A use case for an open-source physical design library
Early Days of Automatic Floorplan Design
Algorithms for automatic length compensation of busses in analog integrated circuits
Implementation and extensibility of an analytic placer
Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC Routing
A pattern matching algorithm for verification and analysis of very large IC layouts
Analytical Clustering Score with Application to Post-Placement Multi-Bit Flip-Flop Merging
Design of robust global power and ground networks
Escape routing of mixed-pattern signals based on staggered-pin-array PCBs
Robust layer assignment for via optimization in multi-layer global routing
Design Automation Challenges for Automotive Systems
Vertical slit transistor based integrated circuits (veSTICs): feasibility study
Statistical clock tree routing for robustness to process variations
Timing-Driven Analytical Placement According to Expected Cell Distribution Range
On Legalization of Die Bonding Bumps and Pads for 3D ICs
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique
An efficient technology mapping algorithm targeting routing congestion under delay constraints
AI for EDA/Physical Design: Driving the AI Revolution: The Crucial Role of 3D-IC
Hardware cyber security
Diffusion-driven congestion reduction for substrate topological routing
My 50-Year Journey from Punched Cards to Swarm Systems
Standard cell placement for even on-chip thermal distribution
Consistent placement of macro-blocks using floorplanning and standard-cell placement
Floorplanning of pipelined array modules using sequence pairs
Leakage-tolerant design techniques for high performance processors
Analysis and optimization of thermal issues in high-performance VLSI
ECBL: an extended corner block list with solution space including optimum placement
A fast algorithm for power grid design
FAR: fixed-points addition & relaxation based placement
On Resilient System Performance Binning
sub-SAT: a formulation for relaxed boolean satisfiability with applications in routing
Power Optimization of FPGA Interconnect Via Circuit and CAD Techniques
Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts
Layout Verification Using Open-Source Software
Optimal slack-driven block shaping algorithm in fixed-outline floorplanning
Assessment of Reinforcement Learning for Macro Placement
Wire shaping is practical
FuILT: Full Chip ILT System With Boundary Healing
A fast estimation of SRAM failure rate using probability collectives
Buffer insertion for clock delay and skew minimization
FPGA place & route challenges
Rectilinear block placement using sequence-pair
Professor Ernest Kuh's talk
INTEGRA: fast multi-bit flip-flop clustering for clock power saving based on interval graphs
Basic and Advanced Researches in Logic Synthesis and their Industrial Contributions
Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach
Global clustering-based performance-driven circuit partitioning
What is a floorplan?
Dummy fill density analysis with coupling constraints
The death of logic synthesis
ART-3D: Analytical 3D Placement with Reinforced Parameter Tuning for Monolithic 3D ICs
Early research experience with OpenAccess gear: an open source development environment for physical design
Invited: The Future of Functional ECO Automation and Logical Equivalence Checking for Advanced Digital Design Flows
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation
Local merges for effective redundancy in clock networks
International Symposium on Physical Design, ISPD'12, Napa, CA, USA, March 25-28, 2012
Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations
Fast interconnect synthesis with layer assignment
Efficient generation of short and fast repeater tree topologies
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results
Calibration-Based Differentiable Timing Optimization in Non-linear Global Placement
The Spirit of in-house CAD Achieved by the Legend of Master "Prof. Goto" and his Apprentices
The ISPD98 circuit benchmark suite
GOALPlace: Begin with the End in Mind
Robust design of power-efficient VLSI circuits
LIBRA - a library-independent framework for post-layout performance optimization
Of Brains and Computers
Temporal logic replication for dynamically reconfigurable FPGA partitioning
Fast buffer insertion considering process variations
Challenges for Automating Package Routing
Declarative Language for Geometric Pattern Matching in VLSI Process Rule Modeling
Partitioning-based standard-cell global placement with an exact objective
Physical design and FinFETs
The economics of segregated and integrated systems in data communication with geometrically distributed message lengths
A 10-wire interface for data communications
A unified algorithm for designing multidrop teleprocessing networks
Modeling an experimental computer communication network
Reliability issues in the ARPA network
A design model for teleprocessing systems
Simulation of centralized computer communications systems
Simulation of packet-switching networks controlled on isarithmic principles
Three level subscriber signaling for data network
The ARPA network terminal system a new approach to network access
A loop network for general purpose data communications in a heterogeneous world
On the packet interleaved interface between packet switched network and computers
Traffic considerations in switched data networks
Proceedings of the third ACM Symposium on Data Communications and Data Networks - Analysis and Design, DATACOMM 1973, USA, 1973
Providing reliable networks with unreliable components
Design considerations of a proposed local area computer network emphasizing the needs of the health sciences
Packet arrival and buffer statistics in a packet switching node
A compatible multiplexing technique for anisochronous and isochronous digital data traffic
Reliability techniques applicable to message processors
Deterministic and adaptive routing policies in packet-switched computer networks
Presentation and major design aspects of the CYCLADES computer network
Dynamic buffer management for computer communications
An analysis of traffic handling capacity of packet switched and circuit switched networks
A database system for the management and design of telecommunication networks
UArizona at the MADE1.0 NLP Challenge
Bidirectional LSTM-CRF for Adverse Drug Event Tagging in Electronic Health Records
Proceedings of the 1st International Workshop on Medication and Adverse Drug Event Detection, 4 May 2018
Knowledge-based Feature Engineering for Detecting Medication and Adverse Drug Events from Electronic Health Records
IBM Research System at MADE 2018: Detecting Adverse Drug Events from Electronic Health Records
Named Entity Recognition using Neural Networks for Clinical Notes
Detecting Medications and Adverse Drug Events in Clinical Notes Using Recurrent Neural Networks
Hybrid system for adverse drug event detection
Clinical NER and Relation Extraction using Bi-Char-LSTMs and Random Forest Classifiers
NVD: the Network Virtual Device for HA-SonD
Design of a Secure Network Mirroring System for Data Sharing
Caching Personalized and Database-related Dynamic Web Pages
Formal Proof of the IDOP_SP Protocol Based on the Petri Net
Comparisons of Three Kalman Filter Tracking Algorithms in Sensor Network
Design and Analysis of a Third-Party Security Protocol for Storage System
Resilient P2P Anonymous Routing by Using Redu
A Network Memory Architecture Model and Performance Analysis
Research of Integrating Military Storage Resources Based on Storage Virtualization
An Improved Direct Digital Frequency Synthesis System Design
Accurate Performance Modeling and Guidance to the Adoption of an Inconsistency Detection Framework
A Dynamic Congestion Control Based Multipath Routing Protocol for Video Transmission over Ad Hoc Networks
P2P Traffic Identification by TCP Flow Analysis
Towards More Reliable Source Routing in Wireless Networks
A Pollution Alleviative L2 Cache Replacement Policy for Chip Multiprocessor Architecture
Event-based Trust Framework Model in Wireless Sensor Networks
A Loop Optimization Technique for Speculative Chip Multiprocessors
Storage Aware Resource Allocation for Grid Data Streaming Pipelines
Self-Similarity in Data Traffic for Object-Based Storage System
A Fast Read/Write Process to Reduce RDMA Communication Latency
TEA: Transmission Error Approximation for Distance Estimation between Two Zigbee Devices
A Dynamic Interface Activation Scheme for Vertical Handoffs
Design and Implement of Snapshots in Linux Block Level
Design and Implementation of Reconfigurable Gateway Array of Multiple Fabrics (RGAMF)
A Two-Way Selective Encryption Algorithm for MPEG Video
A Precise Interrupts Mechanism Based on Micro-Operation Tracing of Instruction Boundary for Embedded Processor
Design and Analysis of a Scalable Third-Party Storage Security Protocol
An Analytical Model for Scheduling Policies in Storage Networks
Microkernel of Embedded Operating System in SRAM
Applications of Bloom Filters in Peer-to-peer Systems: Issues and Questions
Secure Remote Storage through Authenticated Encryption
Hint-based Routing in WSNs using Scope Decay Bloom Filters
Research on Trust Evaluation Model of Grid Services
A Distributed Object Tracing System
A New Dynamic Multicast Routing Model and Its Immune Optimization Algorithm in Integrated Network
A Trace-Driven Simulation Study of Load Balancing on Distributed NIDS
Spatial-Locality-Aware Virtual Storage Devices with Tangible QoS Expressions
A Framework for Accessing General Object Storage
Dynamic Route Diversion in Connectionless Mobile Ad Hoc Networks
An Analytical Performance Model of IP-SAN
Fibre Channel Arbitrated Loop - Performance Analysis of Loop Tenancy Overhead
Enabling RDMA Capability of InfiniBand Network for Java Applications
An Evaluation of Transport Protocols in Peer-to-Peer Media Streaming
An e-Learning Services Discovery Algorithm Based on User Satisfaction
Towards a More Accurate Availability Evaluation
Intrusion Detection Based on Density Level Sets Estimation
An Ontology-based Virtual Storage System
VDMS: A Vector Data Management System for GIS Applications
Performance Characterization of a Dual Quad-Core Based Application Oriented Networking System
POND: The Power of Zone Overlapping in DHT Networks
An Energy-Efficient Clustering Technique for Wireless Sensor Networks
Efficient Event Matching in Publish/subscribe: Based on Routing Destination and Matching History
Creation of a Java-based Interactive Modeling Environment with Tape Library Model Example
A Novel Adaptive Failure Detector for Distributed Systems
Hierarchical MESH Architecture: Toward Practical Applications
Joint Topology-Transparent Scheduling and QoS Routing in Mobile Ad Hoc Networks
Assigning Program To Cache-Aware Scratchpad Concerning The Influence Of The Whole Embedded System
IncFS: An Integrated High-Performance Distributed File System Based on NFS
Component-based Network Protocol Architecture for Multi-core
A Real-Time Scheduling Algorithm for Embedded Systems With Various Resource Requirements
Adaptive Consistency Guarantees for Large-Scale Replicated Services
A Novel Embedded Accelerator for Online Detection of Shrew DDoS Attacks
A Domain-Based Storage Management Framework for the WAN