yusuke1997/dblp-id-title huggingface dataset:
Design of Light-Weight Encryption Algorithm Based on RISC-V Platform: (PhD Forum Paper)
Design of Radix-4 SRT Dividers in 65 Nanometer CMOS Technology
Impact of Loop Tiling on the Controller Logic of Acceleration Engines
An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams
Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip
Real time all intra HEVC HD encoder on FPGA
Performance Comparison of SIMD Implementations of the Discrete Wavelet Transform
Aggressive Performance Improvement on Processing-in-Memory Devices by Adopting Hugepages
Radix-4 Vectoring Cordic Algorithm And Architectures
A 3-D wafer scale architecture for early vision processing
Highly efficient mapping of the Smith-Waterman algorithm on CUDA-compatible GPUs
MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products
Clean the Scratch Registers: A Way to Mitigate Return-Oriented Programming Attacks
A FPGA-based Implementation of an Intravenous Infusion Controller System
BioBlaze: Multi-core SIMD ASIP for DNA sequence alignment
A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter
Modeling and Scheduling Parallel Data Flow Systems using Structured Systems of Recurrence Equations
On systolic mapping of multi-stage algorithms
Loop transformation methodology for fixed-rate video, image and telecom processing applications
Implementation of a VLSI polynomial evaluator for real-time applications
DoSGuard: Protecting pipelined MPSoCs against hardware Trojan based DoS attacks
Design of Low Power On-chip Processor Arrays
Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system
Design Space Exploration of Semantic Segmentation CNN SalsaNext for Constrained Architectures
A message from the general chair and program chair
Implementation of a 32-bit RISC Processor for the Data-Intensive Architecture Processing-In-Memory Chip
Power and performance trade-offs for Space Time Adaptive Processing
Implementation of Orthogonal Wavelet Transforms and their Applications
Hardware/Software Interface for Multi-Dimensional Processor Arrays
MUSE-a systolic array for adaptive nulling with 64 degrees of freedom, using Givens transformations and wafer scale integration
Automated Instruction-Set Extension of Embedded Processors with Application to MPEG-4 Video Encoding
Photonic Processor for Fully Discretized Neural Networks
ZeroVex: A Scalable and High-performance RISC-V Vector Processor Core for Embedded Systems
A 16-context Optically Reconfigurable Gate Array
A Soft Dual-Processor System with a Partially Run-Time Reconfigurable Shared 128-Bit SIMD Engine
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards
CRbS: A Code Reordering Based Speeding-up Method of Irregular Loops on CMP
Message from the Conference Chairs - ASAP 2020
Time-optimal visibility-related algorithms on meshes with multiple broadcasting
Implementing a Highly Parameterized Digital PIV System on Reconfigurable Hardware
A data path array with shared memory as core of a high performance DSP
Digit-serial VLSI microarchitecture
Efficient Conversion From Binary to Multi-Digit Multi-Dimensional Logarithmic Number Systems Using Arrays of Range Addressable Look-Up Tables
Context-Aware Number Generator for Deterministic Bit-stream Computing
Supervised and unsupervised machine learning for side-channel based Trojan detection
A Coalescing-Partitioning Algorithm for Optimizing Processor Specification and Task Allocation
OpenMP device offloading to FPGA accelerators
MSCA: A Multi-Grained Sparse Convolution Accelerator for DNN Training
PFSI.sw: A programming framework for sea ice model algorithms based on Sunway many-core processor
Windowed FIFOs for FPGA-based Multiprocessor Systems
A New approach in on-line task scheduling for reconfigurable computing systems
International Conference on Application Specific Array Processors, ASAP 1994, Proceedings, San Francisco, CA, USA, 22-24 August, 1994
Massively parallel architecture: application to neural net emulation and image reconstruction
An FPGA-based Parallel Hardware Architecture for Real-Time Face Detection Using a Face Certainty Map
Resource-efficient Reconfigurable Computer-on-Module for Embedded Vision Applications
Compressed L1 data cache and L2 cache in GPGPUs
A soft-core processor array for relational operators
EU Collaborative Research on Application-Specific Systems
Switched Memory Architectures-Moving Beyond Systolic Arrays
A Design Tool for the Specification and the Simulation of Array Processors Architectures - Application to Image Processing: The Extraction of Regions of Interests
A multi-beam Scan Mode Synthetic Aperture Radar processor suitable for satellite operation
Accelerating vision and navigation applications on a customizable platform
Design and Evaluation of a Multimedia Computing Architecture Based on a 3D Graphics Pipeline
A Run-Time Reconfigurable Fabric for 3D Texture Filtering
Integrated Security Mechanisms for Weight Protection in Memristive Crossbar Arrays
Buffer size optimization for full-search block matching algorithms
ELLIE: Energy-Efficient LLM Inference at the Edge Via Prefill-Decode Splitting
X-pSRAM: A Photonic SRAM with Embedded XOR Logic for Ultra-Fast in-Memory Computing
Design of a Hardware Accelerator for Density Based Clustering Applications
Biological information signal processor
High Level Synthesis for Peak Power Minimization Using ILP
Persistent Fault Analysis of Neural Networks on FPGA-based Acceleration System
Touch-based Smartphone Authentication Using Import Vector Domain Description
A SW/Configware Codesign Methodology for Control Dominated Applications
Polar baseband receiver for low-end WLAN
Improving the Throughput of On-line Addition for Data Streams
Floating point multiplication rounding schemes for interval arithmetic
A customized GPU acceleration of the princeton ocean model
An efficient method for evaluating polynomial and rational function approximations
System-level design space exploration for dedicated heterogeneous multi-processor systems
Resource-Constrained Encryption: Extending Ibex with a QARMA Hardware Accelerator
24th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2013, Washington, DC, USA, June 5-7, 2013
Using Media Processors for Low-Memory AES Implementation
A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming
Reconfigurable Universal Adder
High-Level Synthesis of Nonprogrammable Hardware Accelerators
A Power-Scalable Switch-Based Multi-processor FFT
On Estimations for Compiling Software to FPGA-based Systems
Partitioning schemes for circuit simulation on a multiprocessor array
Quadratic Control Signals in Linear Systolic Arrays
Processor Elements for the Standard Cell Implementation of Residue Number Systems
A Cryptograhpic Processor for Arbitrary Elliptic Curves over
An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis
Multiplier Design Addressing Area-Delay Trade-offs by using DSP and Logic resources on FPGAs
A case against small data types in GPGPUs
Hierarchical Static Analysis Of Structured Systems Of Affine Recurrence Equations
Digit On-line Large Radix CORDIC Rotator
High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology
The Xor embedding: An embedding of hypercubes onto rings and toruses
Pipelined reconfigurable accelerator for ordinal pattern encoding
A Programmable DSP Architecture for Wireless Communication Systems
Virtual Floating-Point Units for Low-Power Embedded Processors
Implementing a family of high performance, micrograined architectures
Detecting Faults in Four Symmetric Key Block Ciphers
MLIR-to-CGRA: A Versatile MLIR-Based Compiler Framework for CGRAs
Temperature-Aware Submesh Allocation Scheme for Heat Balancing on Chip-Multiprocessors
Latency-constrained Resynchronization for Multiprocessor DSP Implementation
Array-Aware Neural Architecture Search
Termination detection for fine-grained message-passing architectures
Performance Modeling and Tradeoff Analysis During Rapid Prototyping
Parallel Processing Based Power Reduction in a 256 State Viterbi Decoder
Implementation of large neural associative memories by massively parallel array processors
A methodology for performance prediction of Sphinx I in multi-computer architectures
A sparse knapsack algo-tech-cuit and its synthesis
Synthesis of application accelerators on Runtime Reconfigurable Hardware
A subsampling pulsed UWB demodulator based on a flexible complex SVD
Identification of Application Specific Instructions Based on Sub-Graph Isomorphism Constraints
An Optimized Coefficient Update Processor for High-Throughput Adaptive Equalizers
Deoxys: Defensive Approximate Computing for Secure Graph Neural Networks
Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality
Efficient Implementation of Rotation Operations for High Performance QRD-RLS Filtering
Coordinated and adaptive power gating and dynamic voltage scaling for energy minimization
Extension Of The Alpha Language To Recurrences On Sparse Periodic Domains
Voltage Assignment and Loop Scheduling for Energy Minimization while Satisfying Timing Constraint with Guaranteed Probability
Automatic formal verification of systolic array designs
IP-XACT extensions for Reconfigurable Computing
Implications of Programmable General Purpose Processors for Compression/Encryption Applications
Fast lossless image compression with Radiation Hardening by hardware/software co-design on platform FPGAs
Labidus: RISC-V Overlay with Streaming Asynchronous Custom Instructions
Area - Time - Power and Design effort: the basic tradeoffs in Application Specific Systems
Co-Design of Algorithm and FPGA Accelerator for Conditional Independence Test
Reconfigurable Viterbi Decoding Using a New ACS Pipelining Technique
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip
Systolic FFT Processors: Past, Present and Future
REMAP: Remote mEmory Manager for disAggregated Platforms
Message from the ASAP 2016 chairs
Towards Real Time Radiotherapy Simulation
Parallel Implementation of the Full Search Block Matching Algorithm for Motion Estimation
Automatic data mapping of signal processing applications
Smart Rabbit - A Wearable Device As An Intelligent Pacer for Marathon Runners
Parallel processing architectures for rank order and stack filters
Newton-Raphson algorithms for floating-point division using an FMA
Reconfigurable Stream-based Tensor Unit with Variable-Precision Posit Arithmetic
Configurable Loop Shuffling via Instruction Set Extensions
Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement Multiplication Algorithms for Radix-2 RN-Codings and Two's Complement
Mixed-signal implementation of differential decoding using binary message passing algorithms
36th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2025, Vancouver, BC, Canada, July 28-30, 2025
Stochastic circuit design and performance evaluation of vector quantization
An MPSoC architecture for the Multiple Target Tracking application in driver assistant system
Towards secure cryptographic software implementation against side-channel power analysis attacks
Algorithms and architectures for high performance recursive filtering
Design of High-Performance while Energy-Efficient Microprocessor with Novel Asynchronous Techniques: (PhD Forum Paper)
A method to synthesize modular systolic arrays with local broadcast facility
The bit-serial systolic back-projection engine (BSSBPE)
Lightweight Extension of RISC-V Core for NTT-like Algorithms: (PhD Forum Paper)
Scheduling in Co-Partitioned Array Architectures
Parallel floating-point expansions for extended-precision GPU computations
Generating Efficient Custom FPGA Soft-Cores for Control-Dominated Applications
Automated design of DSP array processor chips
A novel framework for multi-rate scheduling in DSP applications
LNS Subtraction Using Novel Cotransformation and/or Interpolation
Talos: A Weighted Speedup-Aware Device Placement of Deep Learning Models
Enabling Automatic Pipeline Utilization Improvement in Polyhedral Process Network Implementations
METAL: A Memory-Efficient Transformer Architecture for Long-Context Inference on FPGA
13th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2002), 17-19 July 2002, San Jose, CA, USA
Performance-Scalable Array Architectures for Modular Multiplication
Buffer allocation for advanced packet segmentation in Network Processors
Parallel Construction of Independent Spanning Trees on Folded Crossed Cubes
A 40 megasample IIR filter chip
Some low power implementations of DSP algorithms
Accelerating bootstrapping in FHEW using GPUs
He-P2012: Architectural heterogeneity exploration on a scalable many-core platform
1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA
Base64 Encoding on Heterogeneous Computing Platforms
Leveraging Energy Cycle Regularity to Predict Adaptive Mode for Non-volatile Processors
Refine and Recycle: A Method to Increase Decompression Parallelism
Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing
Consistency in dataflow graphs
M 3 : A high performance signal processor for RADAR applications
An End-to-End Agile Design Framework to Improve Energy Efficiency on CGRAs
Latency Reduction of Global Traffic in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing
Control for High-Speed PE Arrays
Asynchronous relaxation of locally-coupled automata networks, with application to parallel VLSI implementation of iterative image processing algorithms
Zippy - A coarse-grained reconfigurable array with support for hardware virtualization
Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application
LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models
Memory Operation Inclusive Instruction-Set Extensions and Data Path Generation
An application-specific array architecture for feedforward with backpropagation ANNs
Design-for-adaptivity of microarchitectures
Speeding Up AES By Extending a 32 bit Processor Instruction Set
SLICE Matrix: A Memory Access Scheduling Policy for Multicore Network Processors
Improving Inference Lifetime of Neuromorphic Systems via Intelligent Synapse Mapping
ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache
A Speed Area Optimized Embedded Co-processor for McEliece Cryptosystem
34th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2023, Porto, Portugal, July 19-21, 2023
Accelerating persistent scatterer pixel selection for InSAR processing
Efficient exploration of nonuniform space-time transformations for optimal systolic array synthesis
Resource efficient generators for the floating-point uniform and exponential distributions
Synthesizing systolic arrays: some recent developments
Flexible multistandard FEC processor design with ASIP methodology
FPGA Implementation of Beamforming Receivers Based on MRC and NC-LMS for DS-CDMA System
A Hardware-Oriented Method for Evaluating Complex Polynomials
On the Propagation of Faults and Their Detection in a Hardware Implementation of the Advanced Encryption Standard
An Efficient Hardware Architecture for Sparse Convolution using Linear Feedback Shift Registers
Reconfigurable Cluster-Based Networks-on-Chip for Application-Specific MPSoCs
Precise Tiling for Uniform Loop Nests
2D-VLIW: An Architecture Based on the Geometry of Computation
A Staged Memory Resource Management Method for CMP systems
Era of customization and specialization
A practical network intrusion detection system for inline FPGAs on 10GbE network adapters
Temporized data prefetching algorithm for NoC-based multiprocessor systems
CMOS VLSI Lukasiewicz logic arrays
A 550 Mb/s Radix-4 Bit-level Pipelined 16-State 0.25-mu m CMOS Viterbi Decoder
Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays
Virtual semi-concurrent self-checking for heterogeneous MPSoC architectures
Leveraging MLIR for Efficient Irregular-Shaped CGRA Overlay Design: (PhD Forum Paper)
A Model-Based Methodology for Application Specific Energy Efficient Data Path Design Using FPGAs
A Booth Multiplier Accepting Both a Redundant or a Non-Redundant Input with No Additional Delay
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield
An Explicitly Parallel Architecture for Packet Parsing in Software Defined Networks
Reconfigurable Hardware and Software Architectural Constructs for the Enablement of Resilient Computing Systems
TimeTrial: A low-impact performance profiler for streaming data applications
GFS: An Efficient Implementation of Fair Scheduling for Mult-Gigabit Packet Networks
Systolic architectures for finite-state vector quantization
Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation
Parametrized system level design: Real-time X-Ray image processing case study
An algorithm for accurate data dependence test
Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics
Efficient Processing of Color Image Sequences Using a Color-Aware Instruction Set on Mobile Systems
Bandwidth compression of multiple numerical data streams for high performance custom computing
CONAN - A Design Exploration Framework for Reliable Nano-Electronics
An array-processor based architecture for classification problems
Analytical approach to massively parallel architectures for nanotechnologies
Design Space Exploration for the Implementation of a Predictive Current Controller Based on FPGA
Accelerating the performance of stochastic encoding-based computations by sharing bits in consecutive bit streams
Volume rendering by wavefront architecture
Symbolic parallelization of loop programs for massively parallel processor arrays
Families of FPGA-Based Algorithms for Approximate String Matching
A Mid-Texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors
Model checking cloud rendering system for the QoS evaluation
Design Space Exploration of FFT Accelerators for IEEE 802.11ax using High-Level Synthesis
An efficient implementation of a phase unwrapping kernel on reconfigurable hardware
12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA
Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor
Real Time Iris Segmentation on FPGA
Loop coarsening in C-based High-Level Synthesis
Fault-tolerant DAG Scheduling with Runtime Reconfiguration on Multicore Real-Time Systems
Reliability-Aware Co-Synthesis for Embedded Systems
FarSlayer: Turnkey Acceleration of Legacy Software on Commodity FPGA Cards
International Conference on Application-Specific Array Processors, ASAP 1993, Proceedings, Venice, Italy, 25-27 October, 1993
Low-Cost DNN Hardware Accelerator for Wearable, High-Quality Cardiac Arrythmia Detection
A flexible data-interlacing architecture for full-search block-matching algorithm
Boomerang: Physical-Aware Design Space Exploration Framework on RISC-V SonicBOOM Microarchitecture
Casablanca II: Implementation of a Real-Time RISC
Programmable RNS lattice-based parallel cryptographic decryption
Systematic Register Bypass Customization for Application-Specific Processors
Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources
GFLOPS: a general flexible linearly organized parallel structure for images
Simultaneous Floating-Point Sine and Cosine for VLIW Integer Processors
An Efficient SIMD Architecture with Parallel Memory for 2D Cosine Transforms of Video Coding
TwinStep Network (TwNet): a Neuron-Centric Architecture Achieving Rapid Training
A systolic array for 2-D DFT and 2-D DCT
Formal descriptions, semantics and verification of VLSI array processors
High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder
Secure interrupts on low-end microcontrollers
A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor
Systolic Filter for Fast DNA Similarity Search
Map-reduce processing of k-means algorithm with FPGA-accelerated computer cluster
Combined scheduling and instruction selection for processors with reconfigurable cell fabric
Conception and design of a RISC CPU for the use as embedded controller within a parallel multimedia architecture
Customizing controller instruction sets for application-specific architectures
Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths
FieldHAR: A Fully Integrated End-to-End RTL Framework for Human Activity Recognition with Neural Networks from Heterogeneous Sensors
Exploring hardware support for scaling irregular applications on multi-node multi-core architectures
Accelerating AP3M-Based Computational Astrophysics Simulations with Reconfigurable Clusters
An Algorithm and Hardware Architecture for Integrated Modular Division and Multiplication in GF(p) and GF(2 n )
Jacobi-Specific Processor Arrays
MAMACG: a tool for automatic mapping of matrix algorithms onto mesh array computational graphs
Implementation of ANN on RISC processor array
Synthesis of VLSI Architectures for Two-Dimensional Discrete Wavelet Transforms
Advanced technology for improved signal processor efficiency
The Rise and Fall of Automatic Instruction-Set Extensions
Scalable Malware Detection Framework Using Performance Counters and Gradient Boosting
Application Specific Array Processors, ASAP 1992, Proceedings of the International Conference on, Berkeley, CA, USA, 4-7 August, 1992
Algorithm and architecture-level design space exploration using hierarchical data flows
Full-BNN: A Low Storage and Power Consumption Time-Domain Architecture based on FPGA
Code generation for hardware accelerated AES
Response-pipelined CAM chips - Building blocks for large associated arrays
SPERT: a VLIW/SIMD microprocessor for artificial neural network computations
Design of a systolic coprocessor for rational addition
An Architectural Design For Parallel Fractal Compression
Bit Level Block Matching Systolic Arrays
A Cost Effective Pipelined Divider for Double Precision Floating Point Number
Application-Specific Computing with Adaptive Register File Architectures
An Image Processor for Digital Film
Speeding up graph-based SLAM algorithm: A GPU-based heterogeneous architecture study
An architecture for tree search based vector quantization for single chip implementation
Hardware acceleration for Just-In-Time compilation on heterogeneous embedded systems
On the high-throughput implementation of RIPEMD-160 hash algorithm
A unified software approach to specify pipeline and spatial parallelism in FPGA hardware
Computing Digit Selection Regions for Digit Recurrences
The RAP: a ring array processor for layered network calculations
Run-time thread sorting to expose data-level parallelism
Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures
RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router
Reviewing 4-to-2 Adders for Multi-Operand Addition
An IEEE 754 double-precision floating-point multiplier for denormalized and normalized floating-point numbers
SPNC: Accelerating Sum-Product Network Inference on CPUs and GPUs
GPU kernels for high-speed 4-bit astrophysical data processing
Pseudo-constant logic optimization
High speed bit-level pipelined architectures for redundant CORDIC implementation
Linux synchronization barrier on MPSoC: Hardware/software accurate study and optimization
High Speed Channel Coding Architectures for the Uncoordinated OR Channel
A transformative approach to the partitioning of processor arrays
Resource-efficient regular expression matching architecture for text analytics