yusuke1997/dblp-id-title huggingface dataset:
D-band down conversion chipset with I-Q outputs using 0.13μm SiGe BiCMOS technology
A 12-bit 200-MS/s sample-and-hold amplifier with a hybrid Miller-Feedforward compensation technique
A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi
The Impact of Incident Wavelength and Incident Intensity on Light-modulated Subthreshold Swing Effect
Hardware-Specific Optimization for Mapping of Convolutional Neural Networks to Memristor Crossbars
Latency-aware mapping for 3D NoC using rank-based multi-objective genetic algorithm
Integer linear programming based fault-tolerant topology synthesis for application-specific NoC
Theory and hardware implementation of an analog-to-Information Converter based on Compressive Sensing
Design for testability of FFT/IFFT IP core for UWB systems
Comprehensive Comparison of Temperature Performances for SiC Trench MOSFET with Integrated Side-wall Schottky Diode and Heterojunction
15th IEEE International Conference on ASIC, ASICON 2023, Nanjing, China, October 24-27, 2023
Parameter and UVM, making a layered testbench powerful
Efficient algorithms for resistance and capacitance calculation problems in the design of flat panel display: [Invited paper]
Design of Chip-to-PCB Matching Network for Millimeter-Wave On-Chip Transmitter and On-PCB Antenna
Design of a novel ternary SRAM sense amplifier using CNFET
Design of a novel all-CMOS low power voltage reference circuit
Exploring 3D power distribution network physics
A dual-band frequency tunable complex filter with stable quality-factor in different temperatures
A 0.07-ppm/step differential digitally controlled crystal oscillator with guaranteed monotonicity
Designing hardware trojans and their detection based on a SVM-based approach
A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process
Output Voltage Ripple Reduction with Nosie Spread Spectrum for Dual-Phase LLC Resonant Converter
A VLSI global placement solver based on proximal alternating direction method
A single branch charge pump without overstress for RFID tag
Enhanced Recursive Residual Network for Single Image Super-Resolution
A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface
Using GIDL mechanism for low-power consumption and data retention time improvement in a double-gate nanowire TFT 1T-DRAM with Fin-Gate and Pillar-Body structure
A 800nW high-accuracy RC oscillator with resistor calibration for RFID
A High-speed Dynamic Domino Full Adder Based on DICG Positive Feedback
A Sub-1dB NF Receiver for 1.5T Magnetic Resonance Imaging
Characterization of single-crystalline graphene ESD interconnects
An Optimized Dataflow Based Accelerator for Sparse Convolutional Neural Networks
A Novel High-speed FPGA-based True Random Number Generator Based on Chaotic Ring Oscillator
A new figure of Merit of LC oscilators considering frequency tuning range
A novel equalizer for the high-loss backplane at Nyquist frequency
FlsGraph: A Parallel Architecture for Large-scale Graph Processing
A 79GHz 5-bit Phase Shifter With π-Network in 28-nm CMOS
A 1.8-V 12-bit self-calibrating SAR ADC with a novel comparator
Dual frequency based Real Time Location System using passive UHF RFID
A 320MS/s 7-b flash-SAR ADC with preamplifier sharing technique
Superjunction MOSFET with Trench Schottky Contact and Embedded High-k Insulator for Excellent Reverse Recovery
An improved FFT architecture optimized for reconfigurable application specified processor
Power and resource aware scheduling with multiple voltages
A 1.0-7.0 GHz inductorless RF mixer with multiple feedback and active load in 40-nm CMOS
BATMANN: A Binarized-All-Through Memory-Augmented Neural Network for Efficient In-Memory Computing
RRA-based multi-objective optimization to mitigate the worst cases of placement
Improved GAI-BP Detection for MIMO Systems Based on Message Post-Processing
An Efficient Accelerator for Sparse Convolutional Neural Networks
A 8.1 mW 0.1∼2 GHz inductorless CMOS LNTA for software-defined radio applications
H.264 video parallel decoder on a 24-core processor
A low-power continuous-time comparator with enhanced bias current at the flip point
Humidity sensor with graphene oxide as sensing material
An Input Buffer for 4 GS/s 14-b Time-Interleaved ADC
A Pattern Cancel DAC system design methodology for FMCW radar
Efficient Belief Propagation List Decoding of Polar Codes
Short path padding with multiple-Vt cells for wide-pulsed-latch based circuits at ultra-low voltage
High-voltage bidirectional current sensor
Impacts of external magnetic field and high temperature disturbance on MRAM reliability based on FPGA test platform
Characterization and analysis of pattern dependent variation-aware interconnects for a 65nm technology
Development of high-voltage ESD protection devices on smart power technologies for automotive applications
Development and Characterization of High Temperature Plasma Nitridation Process for Advanced CMOS Technology Application
Switching of 3300V Scaled IGBT by 5V Gate Drive
An on-line debug method for FPGAs
A high performance switched-capacitor programmable gain amplifier design in 0.18μm CMOS technology
An input-powered 1.1-μA Iq 13.56 MHz RF energy harvesting system for biomedical implantable devices
Receiver Characterization with On-Die Eye Monitor (ODEM) in LPDDR5 and DDR5 SDRAM
An efficient solver for statistical capacitance extraction considering random process variations
Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation
Exploiting Dynamic Bit Sparsity in Activation for Deep Neural Network Acceleration
125KHz wake-up receiver and 433MHz data transmitter for battery-less TPMS
One-channel Zero-IF Multi-mode GNSS Receiver with Self-adaptive Digitally-assisted Calibration
A SRAM-saving two-stage storage strategy for the coefficients memories in HEVC encoders
Variation-aware subthreshold logic circuit design
Secure systolic architecture for montgomery modular multiplication algorithm
Design and realization of a X-band graphene amplifier MMIC
Reconfigurable RF Power Amplifier in 5G/4G with RF-SOI CMOS
Using NOC technology to improve photoelectric encoder system for LAMOST spectroscopes
A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications
A hardware/software co-design approach for multiple-standard video bitstream parsing
A Double-Latch Comparator for Multi-GS/s SAR ADCs in 28nm CMOS
Reliability concerns on time-to-digital converter due to bias temperature instability in nanometer era
Mitigating Non-ideality Issues of Analog Computing-In-Memory in DNN-based designs
A new error masking flip-flop with one cycle correction penalty
Advanced Reliability-Aware Verification for Robust Circuit Design
A wide range and high resolution two-step TDC for millimeter-wave band ADPLL
Monolithically Integrated PWM Circuit Based on AlGaN/GaN MIS-HMETs for All-GaN Smart Power System
One-shot Read Processing to Enhance Cold Data Retention in Charge-trap TLC 3D NAND Flash
Self-powered Electrochromic Windows for Smart Homes Realized by Hybridizing Enhanced Perovskite Solar Cells
An interference miss isolation mechanism based on skewed mapping for shared cache in Chip Multiprocessors
A novel transimpedance amplifier for 10 Gbit/s optical communication system
Cut redistribution and DSA template assignment for unidirectional design
A noise-shaping SAR ADC with dual error-feedback paths and alternate DACs
A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise Coupling
High-Bandwidth Wide-Output-Swing Linear Amplifier for LTE-100MHz Envelope Tracking
RF Transceiver System Design: From Protocols to Specifications
A new intrinsic parameter extraction approach for small-signal model of AlGaN/GaN devices
Delay and area optimization for FPRM circuits based on MSPSO algorithm
Genetic Algorithm based pipeline scheduling in high-level synthesis
Research of reusability based on UVM verification
High-Dimensional Bayesian Optimization for Automated Analog Circuit Design via Add-Graph Structure
A proved dither-injection method for memory effect in double sampling pipelined ADC
Scalable Compact Model for High-frequency GaN-HEMTs
A high precision positive temperature circuit using DEM technique
Motion artifact removal based on ICA for ambulatory ECG monitoring
Challenges in the design of self-powered wearable wireless sensors for healthcare Internet-of-Things
Near-threshold processor design techniques for power-constrained computing devices
A 2.4 GHz two-point Δ-Σ modulator with gain calibration and AFC for WPAN/BAN applications
Addressing fault tolerance in 4-PAM signaling by using block codes for on/off-chip communication
Rabbit: An Efficient Verification Platform Base on Virtual Peripherals
Enhanced error correction against multiple-bit-upset based on BCH code for SRAM
Improved algorithm for Pareto front computation for CMOS OpAmp based on multi-objective genetic optimization
A 5kV ESD-protected 2.4GHz PA in 180nm RFCMOS optimized by ESD-PA co-design technique
A 0.5 V 60 nW fully-differential log-domain band-pass filter with tunable cutoff frequency for biosensor applications
A parallel sparse linear system solver for large-scale circuit simulation based on Schur Complement
A High-Linear Digital-to-Phase Converter in 40nm CMOS
3D hybrid modeling of substrate coupling noise in lightly doped mixed-signal ICs
A high input impendence AC-coupled SoC suitable for wearable ExG monitor
A finite gain bandwidth compensation method for low power continuous-time ΣΔ modulator
Design and implementation of RSA for dual interface bank IC card
Scan-based attack against Trivium stream cipher independent of scan structure
A 2-stage with 3-stack 1-tap DFE Sense Amplifier based on Dual Reference for High Speed & Low Power DRAM Interface
A dynamic and low latency wireless NoC architecture
A high performance clock precharge SEU hardened flip-flop
A 6-bit, 1GS/s Digital to Analog Converter for Automotive Ethernet PHY
A Single-Event Upset Evaluation Approach Using Ion-Induced Sensitive Area
ReRAM write circuit with dynamic uniform and small overshoot compliance current under PVT variations
Implementation and optimization of A5-1 algorithm on coarse-grained reconfigurable cryptographic logic array
Design and implementation of precise measuring method for the access time of embedded memory
Ultra-Low-Power CMOS Temperature Sensor for UHF RFID Systems
A low power TDC with 0.5ps resolution for ADPLL in 40nm CMOS
Extraction of circuit transfer functions with SuTra analyses
System-level design solutions: Enabling the IoT explosion
A low cost and high speed CSD-based symmetric transpose block FIR implementation
Adaptive semiblind background calibration of timing mismatches in an M-channel time-interleaved analog-to-digital converter
Pmm: A Matlab toolbox for passive macromodeling in RF/mm-wave circuit design
A new all-in-one bandgap reference and robust zero temperature coefficient (TC) point current reference circuit
An analytical model for SOI triple RESURF devices
5G mm-Wave front-end-module design with advanced SOI process
A High Speed, Low Power and Low Phase Noise Divider for Wideband Application
A high-efficient floating point coprocessor for SPARC Leon2 embedded processor
Active ego-noise control based on metamaterial in small-size robot
Wideband spectrum sensing using the all-phase FFT
ROIC with adaptive reset control for improving dynamic range of IR FPAs
High-Input-Impedance Amplifiers Design for Dry-Electrode Biopotential Acquisition: A Review
Design of 2-3 mixed-valued/six-valued adiabatic asynchronous up-down counter
A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology
A Pseudo Short-circuit Adaptive Zero Current Detection Method for SIBTO in AMOLED Driver
Integrated silicon RF front-end solutions for mobile communications
Mini-HOG: An Area-efficient and Low-power HOG Accelerator with SW/HW co-design for Real-time Pedestrian Detection
A Precise Block-Based Statistical Timing Analysis with MAX Approximation Using Multivariate Adaptive Regression Splines
A low-voltage differential injection locked divider with forward body bias
A Web-based Waveform Viewer for BR0101 Chip Testing Platform
Design for EMI Immunity and ESD Protection for Wearable and Flexible ICs (Invited)
A metastability-based true random number generator on FPGA
Dynamic temperature-aware reliability modeling for multi-branch interconnect trees
Oxygen-plasma-based digital etching for GaN/AlGaN high electron mobility transistors
An ECG Automatic Detection System with Baseline Drift Removal Based on SG Filter
A 16-channel electrode driver with precise calibration for electrical neural stimulation
A 0.25dB gain step high linear programmable gain amplifier
A fast 8×8 IDCT algorithm for HEVC
Controlled domain wall directions within nanodevices integrated on the surface of LiNbO3 single crystals
A dual 12bit 80MSPS 3.3V Current-Steering DAC for HINOC
Tradeoff Between the Breakdown Voltage and Specific On-Resistance of SOI RESURF LDMOS
The compact Vth model for biaxial strained Si NMOSFET
A study of dual-Vt configurations of an 8T SRAM cell in 45nm
New 2-D quadrantal- and diagonal-symmetry filter architectures using delta operator
A 2.4GHz T/R switch with ESD protection for WLAN 802.11 b/g/n applications
A hybrid fault model for differential fault attack on AES
Simulation Study of Trench IGBT with Diode-Clamped P-Well for High dI/dt and dV/dt Controllability
A 30 nA, 6.6 ppm/°C, high PSRR subthreshold CMOS voltage reference
High speed negative capacitance ferroelectric memory
Low-power and high-frequency ring oscillator design in 65nm CMOS technology
Influences of the Source and Drain Resistance of the MOSFETs on the Single Event Upset Hardness of SRAM cells
Ultra-sensitive and responsive capacitive humidity sensor based on graphene oxide
Flash-based Computing-in-memory Architectures with High-accuracy and Robust Reliabilities for General-purpose Applications
A Readout Circuit of Microchannel Plate Light Detector in 0.13um CMOS Technology
A novel RSD correction for pipeline ADC
A 0.87 mW 7MHz-BW 76dB-SNDR passive noise-shaping modulator based on a SAR ADC
Digital RF transmitter architectures exploiting FIRDACs in various configurations
Weight-based FPGA placement algorithm with wire effect considered
Processes of p-GaN Gate HEMTs for High-efficiency and High-reliability Applications
A sigma-delta modulator with a novel chopper correlated double sampled integrator
Novel RRAM programming technology for instant-on and high-security FPGAs
A LVTSCR-Based Compact Structure for Latch-up Immune
Low Power Readout Integrated Circuit with PFM-based ADCs Employing Residue Quantization for Uncooled Infrared Imagers
High-Performance Genomic Analysis Heterogeneous System Using OpenCL
Toward microwave integrated circuits on flexible substrates (invited)
Analytic models for electric potential and subthreshold swing of the dual-material double-gate MOSFET
NMOS LSI Development from 1970's to the beginning of 1980's
An Analytical Model for Domain-Specific Accelerator Deploying Sparse LU Factorization
General lattice wave digital filter with phase compensation scheme
A 3.7ppm/°C piece-wise compensated bandgap reference
An Efficient Module Arithmetic Logic Unit in Dual Field for Internet of Things Applications
Novel High-Performance and Cost Effective Soft Error Hardened Flip-Flop Design for Nanoscale CMOS Technology
A 27-to-65-GHz CMOS Amplifier with Tunable Frequency Response
Self-heating Induced Variability and Reliability in Advanced Logic Devices and Circuits
BNReLU: Combine Batch Normalization and Rectified Linear Unit to Reduce Hardware Overhead
A low complexity algorithm and architecture for MIMO detection without QR decomposition
A CPU-FPGA Based Heterogeneous Accelerator for RepVGG
Development of MEMS Capacitive Mirror Structure with CMOS Compatible Process
Design automation of analog circuit considering the process variations
Overshoot stress impact on HfO2 high-κ layer dynamic SILC
Overview of high-efficiency ant colony optimization (ACO)-based adaptive routings for traffic balancing in network-on-chip systems
Dual-Threshold Independent-Gate TFET with Tri-side Tunneling
An improved analytical series resistance model for on-chip stacked inductors
Highly Efficient Modulo Loop Pipeline For High Level Synthesis
A small-area low-power ADC array for image sensor applications
A low-offset dynamic comparator with input offset-cancellation
An auto-calibrating I/Q mismatch scheme for high image rejection GPS RF receiver
A near threshold error resilient processor based on dynamic timing error prediction and within-a-cycle timing error correction
Low frequency noise characteristics in p-Type MOSFET with multilayer WSe2 channel and Al2O3 back gate dielectric
An optimized hardware architecture for intra prediction in H.264 decoder
An FPGA Implementation of GCN with Sparse Adjacency Matrix
Application space exploration of a multi-fabric reconfigurable system
An automatic translation and parallelization system for general purpose reconfigurable processor
Robust current-mode on-chip interconnect signaling scheme in deep submicron
A three-stage LDO with active feedback frequency compensation and slew-rate enhancement
Transform-based fast mode and depth decision algorithm for HEVC intra prediction
NiGe metal source/drain Ge pMOSFETs for future high performance VLSI circuits applications
A 0.8-3GHz 40dB dynamic range CMOS variable-gain amplifier
Circuit design techniques for multimedia wireline communications
A 6bit 4GS/s current-steering digital-to-analog converter in 40nm CMOS with adjustable bias and DfT block
A High Linearity and Low Noise Anti-Aliasing Filter for ADCs
A Reliable Multi-information Entropy Glitch PUF Using Schmitt Trigger Sampling Method for IoT Security
E/D Mode Logic Cells and Series-to-Parallel Interface with Less Transistors and Better Structure Consistence in GaAs Process
Nonlinear modeling of MIMO antenna array power amplifiers based on time-delay neural network
Design of Asynchronous High Throughput SHA-256 Hardware Accelerator in 40nm CMOS
A high reliability synchronous boost converter with spike suppression circuit
A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network
A digital-assistant time-to-amplitude converter with dynamic range improvement
A Fast Aging-aware Static Timing Analysis Prediction Frame of Digital Integrated Circuits
An integrated method for extracting the statistical distribution of RTN time constants
Nanosecond-order fast switching and ultra-multilevel storage in lateral GeTe and Ge1Sb4Te7-based phase-change memories
High Precision AFE Design Methodology for Wearable EEG Acquisition
Auxiliary testability design schemes for CMOS DACs with ultrahigh sampling rates
A temperature sensing front-end using CMOS substrate PNP transistors
A multi-level arbitration and topology free streaming network for chip multiprocessor
A Low Power Real-Time DC Removal Circuit for PPG Readout
A self-powered supply circuit for switching mode power supply
Capacitor-free, fast transient response CMOS low-dropout regulator with multiple-loop control
An Automatic Slope-Calibrated Ramp Generator for Single-Slope ADCs
An all-n-type dynamic adder for ultra-low-leakage IoT devices
An analysis on a pseudo-differential dynamic comparator with load capacitance calibration
An automated test framework for SRAM-based FPGA
A Dynamic-Texture-Guided Fast Algorithm for Geometric Partitioning Mode of VVC
32-Channel ROIC for X-ray imaging system
A 14bit 320MS/s pipelined-SAR ADC based on multiplexing of dynamic amplifier
An adaptive voltage scaling circuit based on dominate pole compensation
A Lightweight Slave-Module Interface Core to Implement IEEE 1149.5 MTM-Bus Based on FPGA
An improved packing tool based on a dual-output basic logic element
A 0.6 ppm/°C current-mode bandgap with second-order temperature compensation
3D resist modeling for OPC correction and verification
An efficient layered ABV methodology for vision system on chip based on heterogeneous parallel processors
SVM Based Network Intrusion Detection for the UNSW-NB15 Dataset
Quantitative analysis for high speed interpolated/averaging ADC
A low power 10-bit 100-MS/s SAR ADC in 65nm CMOS
CongestNN: An Bi-Directional Congestion Prediction Framework for Large-Scale Heterogeneous FPGAs
A 7.9-fJ/conversion-step 8-b 400-MS/s 2-b-per-cycle SAR ADC with A preset capacitive DAC
A radiation-hard waffle layout for BCD power MOSFET
Low-cost resilient radiation hardened flip-flop design
Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections
Reconfigurable low pass filter with Automatic Frequency Tuning for WCDMA and GSM application
Design of a low-power low-phase-noise multi-mode divider with 25%-duty-cycle outputs in 0.13µm CMOS
A low-power ternary content-addressable memory using pulse current based match-line sense amplifiers
Parallel sparse LU decomposition using FPGA with an efficient cache architecture
A security processor based on MIPS 4KE architecture
A 125KHz low frequency power recovery circuit for battery-less TPMS SoC
A new channel emulator for low voltage broadband power line communication
A High-Performance YOLOV5 Accelerator for Object Detection with Near Sensor Intelligence
3D Vertical RRAM Array and Device Co-design with Physics-based Spice Model
An NoC-based CNN Accelerator for Edge Computing
Design of a Bandgap Reference Circuit with Ultra-low Temperature Coefficient
A process optimization method for carrier stored trench bipolar transistor (CSTBT) device
Design of Multi-core Spiking Neural Network Chip Based on Butterfly Network
A reconfigurable analog baseband for low-power Wi-Fi receiver
An FPGA acceleration system of exact helical CBCT image reconstruction
Graph Steiner tree construction and its routing applications
A Novel Power PiN Diode with p-type Schottky Anode and Trench Oxide for Improving Reverse Recovery
Design of Crosstalk NAND Gate Circuit Based on Interconnect Coupling Capacitance
Device parameter variations of n-MOSFETS with dog-bone layouts in 65nm and 40nm technologies
Efficient FPGA Routing Architecture Exploration Based on Two-Stage MUXes
A highly linear voltage-to-time converter with variable conversion gain for time-based ADCs
A practical method for auto-design and optimization of DC-DC buck converter
An accurate physics-based method for calculating DC inductance of on-chip square multi-layer inductors
A network components insertion method for 3D application-specific Network-on-Chip
A 1.26-ps-FoM Output-Capacitorless LDO with Dual-Path Active-Feedback Frequency Compensation and Current-Reused Dynamic Biasing in 65-nm CMOS Technology
Lateral asynchronous and vertical synchronous 3D Network on Chip with double pumped vertical links
Comprehensive Understanding of Negative Capacitance FET From the Perspective of Transient Ferroelectric Model
Improvement of the charge pump for Maneatis PLLs
The design of low leakage SRAM cell with high SNM
A NoC-based multi-core architecture for IEEE 802.11i CCMP
High Frame Rate High Linearity Low Power DROIC for 30μm-Pitch Cryogenic Infrared FPAs
A Deep Q Network Hardware Accelerator Based on Heterogeneous Computing
Design of Aging Detection Sensor Based on Voltage Comparison
Neural networks: Efficient implementations and applications
Energy-Efficient Approximate Floating-Point Multiplier Based on Radix-8 Booth Encoding
Ultra-low-power and High-accuracy CMOS Temperature Sensor
CoDRAM: A Novel Near Memory Computing Framework with Computational DRAM
A 23.5 μA Ultra-Low Standby Power Microphone ASIC with the Voice Activity Detection Based on A Level-Crossing ADC
An inductorless noise-cancelling CMOS LNA using wideband linearization technique
A Hardware-efficient Accelerator for Encoding Stage of Text-to-speech Synthesis
The implement of digital front end in all-digital quadrature RF transmitter
Improvement on branch scheduling for VLIW architecture
A new nonlinear parameterized model order reduction technique combining the interpolation method and Proper Orthogonal Decomposition
Coupled Data Prefetch and Cache Partitioning Scheme for CPU-Accelerator System