yusuke1997/dblp-id-title huggingface dataset:
Interconnect delay fault testing with IEEE 1149.1
The Final Barriers to Widespread Use of I DDQ Testing
An Enhanced EDAC Methodology for Low Power PSRAM
An optimization based approach to the partial scan design problem
Instability : A CAD Dilemma
Test Access of TAP'ed & Non-TAP'ed Cores
Circular BIST testing the digital logic within a high speed Serdes
Power conscious test synthesis and scheduling for BIST RTL data paths
AC Dynamic Testing of 20Bit Sigma-Delta Over-Sampling D/A Converter on a Mixed Signal Test System
Improved Digital I/O Ports Enhance Testability of Interconnections
On Using Machine Learning for Logic BIST
The Modern Fault Dictionary
Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs
Interposer test: Testing PCBs that have shrunk 100x
Reliability Threats in VDSM - Shortcomings in Conventional Test and Fault-Tolerance Alternatives
Digital Signal Processing Test Techniques for Telecommunications Integrated Circuits
Modeling Scan Chain Modifications For Scan-in Test Power Minimization
Test vector encoding using partial LFSR reseeding
Automatic Behavioral Test Generation
IJTAG Integrity Checking with Chained Hashing
Formal Verification of a System-on-Chip Using Computation Slicing
Test and repair of large embedded DRAMs. 2
Synthetic DSP approach for novel FPGA-based measurement of error vector magnitude
Board manufacturing test correlation to IC manufacturing test
Successful implementation of structured testing
Essential: An Efficient Self-Learning Test Pattern Generation Algorithm for Sequential Circuits
International Test Conference - Cover
A novel stuck-at based method for transistor stuck-open fault diagnosis
Redundancy architectures for channel-based 3D DRAM yield improvement
Systematic defect identification through layout snippet clustering
Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D
Managing the Multi-Gbit/s Test Challenges
Fault models and test methods for subthreshold SRAMs
Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002
Let's Grade ALL the Faults
Register-transfer level fault modeling and test evaluation techniques for VLSI circuits
DFM aware bridge pair extraction for manufacturing test development
Comprehensive Power-Aware ATPG Methodology for Complex Low-Power Designs
Hierarchical Specification-Driven Analog Fault Modeling for Efficient Fault Simulation and Diagnosis
GRAAL: a tool for highly dependable SRAMs generation
A Cost Analysis Framework for Multi-core Systems with Spares
Can We Eliminate Fault Escape in Self-Testing by Polynomial Division (Signature Analysis) ?
Stimulus generation for built-in self-test of charge-pump phase-locked loops
Power scan: DFT for power switches in VLSI designs
Test Pattern Portability for Microprocessors
Effect of lead free solders on in-circuit test process
Diagonal Test and Diagnostic Schemes for Flash Memorie
A Programmable Bus Emulation Technique for Processor Based and Peripheral Printed Circuit Boards
Algorithm for dramatically improved efficiency in ADC linearity test
An Architecture for Testable VLSI Processors
Multi-gigahertz arbitrary timing generator and data pattern serializer/formatter
The Reality of Object Oriented Solutions for ATE
Rapid UHF RFID silicon debug and production testing
A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC TM Chip Multi-Processors
Proceedings IEEE International Test Conference 1996, Test and Design Validity, Washington, DC, USA, October 20-25, 1996
A novel diagnostic test generation methodology and its application in production failure isolation
Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells
The Need for Complete System Level Test Standardization
Fault Modeling and Testing of GaAs Static Random Access Memories
Complexity, Test, and the Productivity Challenge of the 90s
A Frequency Mixing and Sub-Sampling Based RF-Measurement Apparatus for IEEE 1149.4
Using context based methods for test data compression
Logic BIST silicon debug and volume diagnosis methodology
A Microprocessor Test Approach Allowing Fault Localization
Emulative Testing at the Bus Speed Limit
A Prober/Handler Interface for High Pin-Count ASIC Devices
ATE test time reduction using asynchronous clock period
Built-In Self-Test of the Macrolan Chip
Constructive Pattern Generation Heuristic for Meeting SSO Limits
Test infrastructures evaluation at transaction level
Towards a standardized procedure for automatic test equipment timing accuracy evaluation
Delay Test Generation 2: Algebra and Algorithms
Pin electronics IC for high speed differential devices
A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs
Design-for-test and test time optimization for 3D SOCs
Testing Computation-in-Memory Architectures Based on Emerging Memories
Keynote address thursday: Efficient resilience in future systems: Design and modeling challenges
Defect coverage of non-intrusive board tests (NBT): What does it mean when a non-intrusive board test passes?
LAMBDA: LLM-Assisted Malicious Bug Detection and Analysis in Hardware Designs
Recognition of Sensitized Longest Paths in Transition Delay Test
Advanced method to refine waveform smeared by jitter in waveform sampler measurement
X-Tolerant Signature Analysis
Integrated RF-CMOS Transceivers challenge RF Test
Weighted random test program generation for a per-pin tester
Analysis of Experimental Results on Functional Testing and Diagnosis of Complex Circuits
Data Management for Large Memory Device Characterization
Adaptive test selection for post-silicon timing validation: A data mining approach
All Tests for a Fault Are Not Equally Valuable for Defect Detection
Efficient Generation of Test Patterns Using Boolean Difference
Capture power reduction using clock gating aware test generation
Power supply transient signal integration circuit
In-Circuit Test Techniques Applied to Complex Digital Assemblies
Supervisors for Testing Non-Deterministically Specified Systems
"Managing process variance in analog designs"
Optimal Logic Synthesis and Testability : Two Sides of the Same Coin
Towards reducing "functional only" fails for the UltraSPARC microprocessors
Peak Power Reduction Through Dynamic Partitioning of Scan Chains
An Economic Analysis and ROI Model for Nanometer Test
An ETHERNET Based Solution to ATE Networking
Deterministic BIST Based on a Reconfigurable Interconnection Network
Test and debug strategy of the PNX8525 Nexperia TM digital video platform system chip
A Secure Data Transmission Scheme for 1149.1 Backplane Test Bus
Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores
Lowering the cost of test with a scalable ATE custom processor and timing IC containing 400 high-linearity timing verniers
GHz Testing and Its Fuzzy Targets
Hysteresis of Intrinsic IDDQ Currents
Proceedings International Test Conference 1982, Philadelphia, PA, USA, November 1982
Test clock domain optimization for peak power supply noise reduction during scan
Test Considerations for Components with Redundant Elements
A practical guide to combining ICT & boundary scan testing
Testing Video Processors
Synthesis-for-Initializability of Asynchronous Sequential Machines
A Totally Universal Reset, Initialization (and) Nodal Observation Circuit
Low cost back end signal processing driven bandwidth interleaved signal acquisition using free running undersampling clocks and mixing signals
The Leading Edge of Production Wafer Probe Test Technology
Fault Simulation and Test Pattern Generation at the Multiple-Valued Switch Level
Power Driven Chaining of Flip-Flops in Scan Architectures
IEEE International Test Conference, ITC 2023, Anaheim, CA, USA, October 7-15, 2023
Application of High-Quality Built-In Test to Industrial Designs
Integrating DFT in the Physical Synthesis Flow
ATPG for Heat Dissipation Minimization During Test Application
Machine Learning for Yield Learning and Optimization
CODEC Testing Using Synchronized Analog and Digital Signals
A new method for measuring alias-free aperture jitter in an ADC output
Design for Testability of a Modular, Mixed Signal Family of VLSI Devices
Efficient High-Speed Interface Verification and Fault Analysis
Test Time and Area Optimized BrST Scheme for Automotive ICs
A novel test methodology for core-based system LSIs and a testing time minimization problem
Built-in self-test of FPGA interconnect
ABNER : A Burn-In Monitor and Error Reporting System for PBX Systems Test
Process Monitoring Oriented IC Testing
Run-Time Program for Self-Checking Single Board Computer
Extraction Error Diagnosis and Correction in High-Performance Designs
High-Volume Production Testing and Its Impact on the Development of Microprocessor Prototyping Tools
Analog Boundary-Scan Description Language (ABSDL) for Mixed-Signal Board Test
eRNA: Refining of reconstructed digital waveform
Mixed Signal BIST: Fact or Fiction
A methodology for testing one-hot transmission gate multiplexers
Low power compression utilizing clock-gating
Automating Design For Yield: Silicon Learning to Predictive Models and Design Optimization
A study of bridging defect probabilities on a Pentium (TM) 4 CPU
Testing a High Performance Modem Filter
An ant colony optimization technique for abstraction-guided state justification
Full-Symbolic ATPG for Large Circuits
A fully cell-based design for timing measurement of memory
Fault diagnosis in scan-based BIST using both time and space information
Static component interconnect test technology (SCITT) a new technology for assembly testing
CMOS VLSI Challenges to Test
"In System" Transparent Autodiagnostics of Rams
A Testability Strategy for Silicon Compilers
A transparent solution for providing remote wired or wireless communication to board and system level boundary-scan architectures
Terminating Transmission lines in the Test Environment
The Non-Linear Feedback Shift-Register as a Built-In Self-Test (BIST) Resource
Test Point Insertion for an Area Efficient BIST
IBM's VLSI Logic Test System
Testing Conventional Logic and Memory Clusters Using Boundary Scan Devices as Virtual ATE Channels
Access Time Evaluation of Fast Static MOS Memories
Multiple Stuck-At Fault Coverage of Single Stuck-At Fault Test Sets
Sequential Test Generation with Advanced Illegal State Search
VLSI testing based security metric for IC camouflaging
A novel test structure for measuring the threshold voltage variance in MOSFETs
Impact of Quad Flat No Lead package (QFN) on automated X-ray inspection (AXI)
Issues for Mixed-Signal CAD-Tester Interface
LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution
Generating pseudo-exhaustive vectors for external testing
Pylon: Towards an integrated customizable volume diagnosis infrastructure
IEEE 1500 Core Wrapper Optimization Techniques and Implementation
Clock Faults? Impact on Manufacturing Testing and Their Possible Detection Through On-Line Testing
A building block BIST methodology for SOC designs: a case study
Evaluating and Improving Transient Error Tolerance of CMOS Digital VLSI Circuits
A Survey of Test Problems and Solutions
Fault Macromodeling for Analog/Mixed-Signal Circuits
Test Data Compression of 100x for Scan-Based BIST
IEEE Std. P1687.1: Translator and Protocol
Generation Technique of 500MHz Ultra-High Speed Algorithmic Pattern
MFBIST: A BIST Method for Random Pattern Resistant Circuits
TPG2 : An Automatic Test Program Generator for Custom ICs
Panel 9 - Diagnostics vs. Failure Analysis
Efficient Test Generation Algorithms
On the Use of k-tuples for SoC Test Schedule Representation
A design-for-test methodology for active analog filters
IBM's Cost Performance Array Tester Architecture for the 80's
Scan Insertion at the Behavioral Level
DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management
Issues That Arise in Translating VLSI Test Programs Between Testers
Fault Tuples in Diagnosis of Deep-Submicron Circuits
ATPD: An Automatic Test Pattern Generator for Path Delay Faults
DIST: Deterministic In-System Test with X-masking
Self-Testing by Polynomial Division
On the Design for Testability of Communication Software
IC diagnosis: preventing wars and war stories
A new method for estimating spectral performance of ADC from INL
Signature Based Diagnosis for Logic BIST
4.5 Gsps MIPI D-PHY Receiver Circuit for Automatic Test Equipment
Novel Test Pattern Generators for Pseudo-Exhaustive Testing
Key Technologies for 500 MHz VLSI Test System "ULTIMATE"
Elimination of Incoming Test Based Upon In-Process Failure and Repair Costs
A Mixed Signal Analog Test Bus Framework
Using built-in self-test and adaptive recovery for defect tolerance in molecular electronics-based nanofabrics
An empirical relationship between test transparency and fault coverage
Safety-Guided Test Generation for Structural Faults
Routability and Fault Tolerance of FPGA Interconnect Architectures
Maximizing Stress Coverage by Novel DFT Techniques and Relaxed Timing Closure
Is Board Test Worth Talking About?
Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects
Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability
Synthesis of Pseudo-Random Pattern Testable Designs
Switch-level bridging fault simulation in the presence of feedbacks
Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints
Addressing Early Design-For-Test Synthesis in a Production Environment
Fault Location in Repairable Programmable Logic Arrays
Fabrication Defects and Fault Models for DNA Self-Assembled Nanoelectronics
Leave the Wires to Last - Funcitonal Evaluation of the IEEE Std 1149.5 Module Test and Maintenance Bus
DC temperature measurements for power gain monitoring in RF power amplifiers
Automatic Structural Test Generation for Analog Circuits using Neural Twins
Flexible Inspection Systems (FIS) for Printed Circuit Board Production: ATE Finds a Quality Partner
Increasing test coverage in a VLSI design course
Testability Analysis of Synchronous Sequential Circuits Based on Structural Data
Transmission Problems Encountered When Testing Memory Devices in Parallel on Memory ATE
Converting Device Test Vectors to an In-Circuit Board Test Environment
Cost evaluation of coverage directed test generation for the IBM mainframe
It's DFT, Boundary Scan and Life Cycle Benefits
End-to-End Performance Measurement for Interactive Multimedia Television
International Symposium on Design and Diagnostics of Electronic Circuits and Systems
A Concurrent Test Architecture for Massively-Parallel Computers and its Error Detection Capability
Modeling Novel Non-JTAG IEEE 1687-Like Architectures
An Analog Multi-Tone Signal Generator for Built-In Self-Test Applications
Calculating VOH for LSI 10K ECL
ATPG and Simulation Systems : The State of the Art
Minimal overhead modification of iterative logic arrays for C-testability
Test Scheduling for Network-on-Chip with BIST and Precedence Constraints
Split timing mode (STM)-answer to dual frequency domain testing
Driver sharing challenges for DDR4 high-volume testing with ATE
An Automated Menu Screen Generation Software Tool for VLSI ATE Programming and Operation
Distributed Embedded Logic Analysis for Post-Silicon Validation of SOCs
Electron Beam Tester with 10 ps Time Resolution
A Design-for-Testability Architecture for Multichip Modules
Refined Bounds on Signature Analysis Aliasing for Random Testing
Testing a Board Loaded with Leaded and Surface Mounted Components
Adaptive High Voltage Stress Methodology to Enable Automotive Quality on FinFET Technologies
Rapid prototyping and test before silicon of integrated pressure sensors
Radic: A standard-cell-based sensor for on-chip aging and flip-flop metastability measurements
Testing 256k Word x 16 Bit Cache DRAM (CDRAM)
Design for Testability Using Architectural Descriptions
Testable Programmable Digital Clock Pulse Control Elements
Improving Test Chip Design Efficiency via Machine Learning
Variable Supply Voltage Testing for Analogue CMOS and Bipolar Circuits
High Speed I/O Test Cable Assembly Interfaces for Next Generation Multi-Gigabit Serial Protocols
Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs
Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface
Infrastructure IP for Back-End Yield Improvement
Test generation for crosstalk-induced delay in integrated circuits
Failure coverage of functional test methods: a comparative experimental evaluation
An Embedded Core for Sub-Picosecond Timing Measurements
Test In the Era of "What You see Is NOT What You Get"
DFT Architecture for Automotive Microprocessors using On-Chip Scan Compression supporting Dual Vendor ATPG
Improving DSP-Based Measurements with Spectral Interpolation
Memory Test : An International Art
Panel discussion for "have we overcome the challenges associated with SoC and multi-core testing?"
Surviving state disruptions caused by test: A case study
Roadmap for Extending IEEE 1149.1 for Hierarchical Control of Locally-Stored, Standardized-Command-Set Test Programs
Circuit failure prediction to overcome scaled CMOS reliability challenges
Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000
A Fault Model and a Test Method for Analog Fuzzy Logic Circuits
A Method for Delay Fault Self-Testing of Macrocells
Multi-Level Access Protection for Future IEEE P1687.1 IJTAG Networks
Local Transformations and Robust Dependent Path Delay
Testing and Structured Design
How long can we succeed using the OBIRCH and its derivatives?
A Real-time Executive for a Distributed Processing System
Parallel Testing of Random Logic LSIs
A Wavelet-Based Timing Parameter Extraction Method
Temperature control of a handler test interface
DFT advances in Motorola's Next-Generation 74xx PowerPC TM microprocessor
Multiple-Fault Detection in Iterative Logic Arrays
Physically-aware analysis of systematic defects in integrated circuits
Read disturb fault detection in STT-MRAM
A New Parallel Test Approach for Large Memories
Quality and Reliability
Behavioral Test Economics
Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique
A built-in self-test circuit for jitter tolerance measurement in high-speed wireline receivers
Test Coverage Models for System Test?
DfST: Design for secure testability
Analogue Fault Simulation Based on Layout-Dependent Fault Models
BISTLock: Efficient IP Piracy Protection using BIST
A token scan architecture for low power testing
Achieving +/-30ps Accuracy in the ATE Environment
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint
DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks
Deformations of IC Structure in Test and Yield Learning
Practical Production Testing of ISDN Circuit Boards
Hierarchically Accessing 1149.1 Applications in a System Environment
Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL
Hierarchy Based Statistical Fault Simulation of Mixed-Signal ICs
Streaming fast access to ADCs and DACs for mixed-signal ATPG
Summing Node and False Summing Node Methods: Accurate Operational Amplifier AC Characteristics Testing without Audio Analyzer
Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics - Join Them, Baltimore, Maryland, USA, October 17-21, 1993
Fast Accurate and Complete ADC Testing
Delay defect diagnosis using segment network faults
On the Possible Limits of External Testing
An Approach to Memory Testing, Diagnostics and Analysis
A DSP-Based Feedback Loop for Mixed-Signal VLSI Testing
A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns
Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors
Reconfigurable systems self-healing using mobile hardware agents
Proceedings IEEE International Test Conference 1999, Atlantic City, NJ, USA, 27-30 September 1999
Diagnosis of intermittent faults and corresponding algorithm development beyond 5nm technologies
Failure probability algorithm for test systems to reduce false alarms
Modelling the Unmodellable: Algorithmic Fault Diagnosis
Test Data Compaction Techniques with Improved Diagnostic Capabilities and Reduced Tester Time
CMP3F: a high speed fault simulator for the Connection Machine
Transition Fault Simulation for Sequential Circuits
The Effect on Quality of Non-Uniform Fault Coverage and Fault Probability
Circuits for Pseudo-Exhaustive Test Pattern Generation
Predicting system-level test and in-field customer failures using data mining
Off-shore outsource DFT vs. build off-shore branch offices
Testing for tunneling opens
Comparative study of CA with phase shifters and GLFSRs
Diagnosis framework for locating failed segments of path delay faults
Can Redundancy Enhance Testability?
Extending STIL 1450 Standard for Test Program Flow
BIST-based delay path testing in FPGA architectures
Increased CMOS IC stuck-at fault coverage with reduced I DDQ test sets
Predictive Testing for Aging in SRAMs and Mitigation
Test wrapper and test access mechanism co-optimization for system-on-chip
A language for describing boundary-scan devices
An FFT-based jitter separation method for high-frequency jitter testing with a 10x reduction in test time
Non-Stuck-At Fault Detection in nMOS Circuits by Region Analysis
Functional State Extraction using Scan DFT
An Effective and Flexible Multiple Defect Diagnosis Methodology Using Error Propagation Analysis
Using Limited Dependence Sequential Expansion for Decompressing Test Vectors
Fault Detection of Combinational Circuits Based on Supply Current
Cost of test reduction
RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators
Automating Functional Programming for Micro-Based Boards
Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure
Impact of back side circuit edit on active device performance in bulk silicon ICs
Burn-in Elimination of a High Volume Microprocessor Using I DDQ
Efficient Embedded Memory Testing with APG
The Push for Test in Universities
Concept Recognition in Production Yield Data Analytics
An Artificial Intelligence Based Implementation of the P-Algorithm for Test Generation
Implications of Board Testing at Speed
Practical Test Strategies for Users of 100 PPM ICs
Multiple Fault Diagnosis in Printed Circuit Boards
Wireless SOC Testing: Can RF Testing Costs Be Reduced?
Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data
Simplifying Analog Device Test Program Generation
I DDQ Test: Sensitivity Analysis of Scaling
Characterization of Edge Placement Accuracy in High-Speed Digital Pin Electronics
An Automated, Complete, Structural Test Solution for SERDES
ML-Assisted Bug Emulation Experiments for Post-Silicon Multi-Debug of AMS Circuits
Exploratory Data Analysis Makes Testing More Valuable for Semiconductor Manufacturing
Higher Yields, Lower Costs
Testability Features of the MC68332 Modular Microcontroller
Simultaneous Switching Noise Evaluation of Advanced CMOS Logic (ACL)
DeltaI vs. DeltaY : A Quantitative Analysis of the Trade-offs Between Higher Capital Investment and Higher Yield in PCB Testing
Fixturing for Surface-Mounted Devices
Parasitic Effect Removal for Analog Measurement in P1149.4 Environment
Inevitable Use of TAP Domains in SOCs
Optimized reasoning-based diagnosis for non-random, board-level, production defects
Obstacles and an approach towards concurrent engineering
SiP-test: Predicting delivery quality
Techniques for Characterizing DRAMs With a 500-MHz Interface
An ATPG-Based Framework for Verifying Sequential Equivalence
An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded Cores
Principles and results of some test cost reduction methods for ASICs
Diagnosis and Layout Aware (DLA) scan chain stitching
Improved IDDQ Testing with Empirical Linear Prediction
Partial state monitoring for fault detection estimation
Test Strategy Sensitivity to Defect Parameters
Delay Testing for Non-Robust Untestable Circuits
An Integrated Analog Test Simulation Environment
Evaluating ATE-equipment for volume diagnosis
Transitioning eMRAM from Pilot Project to Volume Production