yusuke1997/dblp-id-title huggingface dataset:
Statistical analysis and comparison of 2T and 3T1D e-DRAM minimum energy operation
SDRAM Architecture & Single Event Effects Revealed with Laser
Analysis on Retention Time and Adaptive Refresh in Embedded DRAMs with Aging Benefits
Trends and Trade-offs in Designing Highly Robust Throughput on Chip Communication Network
Aging test strategy and adaptive test scheduling for SoC failure prediction
Fault Diagnosis for Linear Analog Circuits with Symbolic Analysis and Reduced Observable Point Set
Effective fault simulation of GPU's permanent faults for reliability estimation of CNNs
Contribution of Communications to Dependability in Massively-Defective General-Purpose Nanoarchitectures
Explainability and Dependability Analysis of Learning Automata based AI Hardware
An Analog Checker With Input-Relative Tolerance for Duplicate Signals
A New Approach to Design Reliable Real-Time Speech Recognition Systems
A Hybrid Approach to the Test of Cache Memory Controllers Embedded in SoCs
Error Correction Coding of Stochastic Numbers Using BER Measurement
A Crosstalk Sensor Implementation for Measuring Interferences in Digital CMOS VLSI Circuits
Online monitoring of FPGA-based co-processing engines embedded in dependable workstations
Self-checking arithmetic logic unit with duplicated outputs
A Low-Cost Single-Event Latchup Mitigation Sscheme
Testing permanent faults in pipeline registers of GPGPUs: A multi-kernel approach
A multi-objective optimization for memory BIST sharing using a genetic algorithm
A Graph-Based Methodology for Speeding up Cell-Aware Model Generation
Estimating Circuit Fault-Tolerance by Means of Transient-Fault Injection in VHDL
On-Line Testing of Lab-on-Chip Using Digital Microfluidic Compactors
Metallic Ratio Equivalent-Time Sampling: A Highly Efficient Waveform Acquisition Method
Soft error immune latch under SEU related double-node charge collection
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults
Latchup effect in CMOS IC: a solution for crypto-processors protection against fault injection attacks?
Essential Fault-Tolerance Metrics for NoC Infrastructures
Minimal exercise vector generation for reliability improvement
Relation between HCI-induced performance degradation and applications in a RISC processor
Hardware Reconfiguration Scheme for High Availability Systems
On-line monitoring of system health using on-chip SRAMs as a wearout sensor
Flip Flop Weighting: A technique for estimation of safety metrics in Automotive Designs
Enabling Cross-Layer Reliability and Functional Safety Assessment Through ML-Based Compact Models
Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory
Resistive Switching Behavior seen from the Energy Point of View
A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System
Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip
Characterizing Laser-Induced Pulses in ICs: Methodology and Results
Benchmarking the Capabilities and Limitations of SAT Solvers in Defeating Obfuscation Schemes
Power Reduction in Test-Per-Scan BIST
Programmable restricted SEC codes to mask permanent faults in semiconductor memories
Variability-aware task mapping strategies for many-cores processor chips
A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns
Meeting the Conflicting Goals of Low-Power and Resiliency Using Emerging Memories : (Invited Paper)
Evaluation of the Quality of Testing Path Delay Faults under Restricted Input Assumption
Design of efficient error resilience in signal processing and control systems: From algorithms to circuits
A BIST-based Charge Analysis for Embedded Memories
New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability
CANDoSA: A Hardware Performance Counter-Based Intrusion Detection System for DoS Attacks on Automotive CAN Bus
Automated Dysfunctional Model Extraction for Model Based Safety Assessment of Digital Systems
Effective Hardware-Trojan Feature Extraction Against Adversarial Attacks at Gate-Level Netlists
Built-in Self Repair by Reconfiguration of FPGAs
Design of Real-Number Checksum Codes Using Shared Partial Computation for CED in Linear DSP Systems
An analytical model for the calculation of the Expected Miss Ratio in faulty caches
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure
On line monitoring of RF power amplifiers with embedded temperature sensors
On Approaching Multivariate IC Pre-silicon Verification Using ML-based Adaptive Algorithms
Single Event Effects in 1Gbit 90nm NAND Flash Memories under Operating Conditions
Leveraging reuse and endurance by efficient mapping and placement for NVM-based FPGAs
Software-only Diverse Redundancy on GPUs for Autonomous Driving Platforms
DMT and DT2: Two Fault-Tolerant Architectures developed by CNES for COTs-based Spacecraft Supercomputers
Special Session 3 - Panel: SER in Automotive: what is the impact of the AEC Q100-G spec?
Resiliency Demands on Next Generation Critical Embedded Systems
RIIF - Reliability information interchange format
Body Bias Injection on the FLASH Memory Accelerator of a 32-Bit Microcontroller
2013 IEEE 19th International On-Line Testing Symposium (IOLTS), Chania, Crete, Greece, July 8-10, 2013
System-Level Test: State of the Art and Challenges
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register
Power Consumption of Fault Tolerant Codes: the Active Elements
Next-Generation Quantum Neural Networks: Enhancing Efficiency, Security, and Privacy
A call for cross-layer and cross-domain reliability analysis and management
Efficacy and efficiency of algorithm-based fault-tolerance on GPUs
Totally Fault Tolerant RNS Based FIR Filters
Low-cost functional test of a 2.4 GHz OQPSK transmitter using standard digital ATE
Failure mitigation in linear, sesquilinear and bijective operations on integer data streams via numerical entanglement
Advanced ECC solution for automotive SoCs
On the Fine Tuning of RRAM Resistance Under Variability Using Current Pulses at SET
On-Line Testable Decimation Filter Design for AMS Systems
Camo-DNN: Layer Camouflaging to Protect DNNs against Timing Side-Channel Attacks
Timing-resilient Network-on-Chip architectures
Fuse: A Technique to Anticipate Failures due to Degradation in ALUs
A New Code with Reduced EMI and Partial EC Possibilities
Micro-Checkpointing: Checkpointing for Multithreaded Applications
When Silicon Fails Silently: Characterizing Hardware-Induced Corruption in LLM Training
Emulation of an ASIC Power, Temperature and Aging Monitor System for FPGA Prototyping
DFT Assisted Built-In Soft Error Resilience
Software Product Reliability Based on Basic Block Metrics Recomposition
Analytical Semi-Empirical Model for SER Sensitivity Estimation of Deep-Submicron CMOS Circuits
Power-Balanced Self Checking Circuits for Cryptographic Chips
Autoencoder-Based Detection of Physical-Layer Anomalies in Automotive CAN Networks
Unidirectional error detection, localization and correction for DRAMs: Application to on-line DRAM repair strategies
Empirical Evaluation on Anomaly Behavior Detection for Low-Cost Micro-Controllers Utilizing Accurate Power Analysis
Challenges and Opportunities for FPGA Programmable System Platforms
An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding
Error Resilient Neuromorphic Networks Using Checker Neurons
On-Line Testing for Secure Implementations: Design and Validation
Effectiveness and Limitations of Various Software Techniques for "Soft Error" Detection: A Comparative Study
Fault-tolerance assessment and enhancement in SoCWire interface: A system-on-chip wire
Do more camera pixels result in a better picture?
Robustness of circuits under delay-induced faults : test of AES with the PAFI tool
A high performance scan flip-flop design for serial and mixed mode scan test
Modeling and mitigating NBTI in nanoscale circuits
Fault coverage of a timing and control flow checker for hard real-time systems
Reliability in Application Specific Mesh-Based NoC Architectures
Towards Scalable Lifetime Reliability Management for Dark Silicon Manycore Systems
DRAFT: An On-Line Fault Detection Method for Dynamic and Partially Reconfigurable FPGAs
AMS-RF test quality: Assessing defect severity
Transient-Fault-Aware Design and Training to Enhance DNNs Reliability with Zero-Overhead
Scan attack in presence of mode-reset countermeasure
Side-Channel Attack Detection Using gem5 and Machine Learning: A Case Study on Fault-Based Attacks in RISC-V
Security Testing for Hardware Products: The Security Evaluations Practice
Experimental validation of a Bulk Built-In Current Sensor for detecting laser-induced currents
Fast Configurable Polynomial Division for Error Control Coding Applications
Process Variation Tolerant Online Current Monitor for Robust Systems
Hierarchical Check Based Detection and Diagnosis of Sensor-Actuator Malfunction in Autonomous Systems: A Quadcopter Study
Algorithm transformation methods to reduce software-only fault tolerance techniques' overhead
On-line Fault Detection and Location for NoC Interconnects
Fault-Independent Test-Generation for Software-Based Self-Testing
Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding
Hardware Trojans classification for gate-level netlists based on machine learning
Characterizing fault propagation in safety-critical processor designs
Soft-Error Vulnerability of Sub-100-nm Flip-Flops
An effective embedded test & diagnosis solution for external memories
SafeLS: An Open Source Implementation of a Lockstep NOEL-V RISC-V Core
Robust Data Compression for Analogue Test Outputs
Control Loop of Image Correction based on Detection and Self-Healing of Defective Pixels
On Compaction-Based Concurrent Error Detection
Proton Evaluation of Single Event Effects in the NVIDIA GPU Orin SoM: Understanding Radiation Vulnerabilities Beyond the SoC
ReDiM: An Efficient Strategy for Read Disturb Mitigation in RRAM-Based Accelerators
Investigating the limits of AVF analysis in the presence of multiple bit errors
31st IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2025, Ischia, Italy, July 7-9, 2025
Test access mechanism for chips with spare identical cores
Does It Mean Less Testing for Self Calibrating Design?
Automated Synthesis of SEU Tolerant Architectures from OO Descriptions
Temperature dependence of NBTI induced delay
A New DEC/TED Code for Fast Correction of 2-Bit-Errors
Error detection in addition chain based ECC Point Multiplication
High-level Modeling of Manufacturing Faults in Deep Neural Network Accelerators
On-Line Detection of Short Circuits in Digital Devices and Systems
Sequential n -Detection Criteria: Keep It Simple
8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France
Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory Blocks
Accelerating Yield Ramp through Real-Time Testing
Predicting the Impact of Functional Approximation: from Component- to Application-Level
Defect Characterization of Spintronic-based Neuromorphic Circuits
New reliability mechanisms in memory design for sub-22nm technologies
Investigating the Use of BICS to detect resistive-open defects in SRAMs
Industrial Practices in Low-Power Robust Design
Soft Error Tolerance of Power-Supply-Noise Hardened Latches
Electrical Modeling for Laser Testing with Different Pulse Durations
Bayesian models for early cross-layer reliability analysis and design space exploration
Resistive and Spintronic RAMs: Device, Simulation, and Applications
Improved circuitry for soft error correction in combinational logic in pipelined designs
An Approach for Designing On-Line Testable State Machines
Temporary Laser Fault Injection into Flash Memory: Calibration, Enhanced Attacks, and Countermeasures
Fault injection and fault handling: An MPSoC demonstrator using IEEE P1687
Low-Area On-Chip Circuit for Jitter Measurement in a Phase-Locked Loop
Statistical Device Variability and its Impact on Yield and Performance
Multi-level secure JTAG architecture
A Technique to Reduce Power and Test Application Time in BIST
Dependable reconfigurable space systems: Challenges, new trends and case studies
How to Characterize the Problem of SEU in Processors and Representative Errors Observed on Flight
Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm
29th International Symposium on On-Line Testing and Robust System Design, IOLTS 2023, Crete, Greece, July 3-5, 2023
STDP-Trained Spiking Neural Network Reliability Assessment Through Fault Injections
Event-driven on-line co-simulation with fault diagnostic
Trusted and Secure Design of Analog/RF ICs: Recent Developments
Fault-Resilient Topology Planning and Traffic Configuration for IEEE 802.1Qbv TSN Networks
MOZART: Masking Outputs with Zeros for Architectural Robustness and Testing of DNN Accelerators
Efficient observation point selection for aging monitoring
Multilinear codes for robust error detection
ATPG-based grading of strong fault-secureness
Guided Probabilistic Checksums for Error Control in Low Power Digital-Filters
Relation between Fault Tolerance and Reconfiguration in Cellular Systems
On the test of a COTS-based system for space applications
Collective-Aware System-on-Chips for Dependable IoT Applications
Algorithmic techniques for robust applications
Radiation Induced Single-Word Multiple-Bit Upsets Correction in SRAM
A Compact Built-In Current Sensor for IDDQ Testing
Power-aware Reliable Communication for the IoT
Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs
Matrix control-flow algorithm-based fault tolerance
Special Session 1: Radiation Hardening Techniques
Concepts for fault tolerant sensor systems
A Design for Testability Method for k-Cycle Capture Test Generation
An Automatic Approach to Perform FMEDA Safety Assessment on Hardware Designs
In-situ Fmax/Vmin tracking for energy efficiency and reliability optimization
All Digital Low-Cost Built-in Defect Testing Strategy for Operational Amplifiers with High Coverage
NBTI aging tolerance in pipeline based designs NBTI
Propagation of Transients Along Sensitizable Paths
On the Reliability of Clock Monitoring Units for Safety Critical Applications' Microcontrollers
Efficient multilevel formal analysis and estimation of design vulnerability to Single Event Transients
A cost-efficient dependability management framework for self-aware system-on-chips based on IEEE 1687
On-line testing of bundled-data asynchronous handshake protocols
Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes
Injecting Multiple Upsets in a SEU Tolerant 8051 Micro-Controller
Timing error tolerance in nanometer ICs
An ECC-Based Repair Approach with an Offset-Repair CAM for Mitigating the MBUs Affecting Repair CAM
6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain
A new IP core for fast error detection and fault tolerance in COTS-based solid state mass memories
On-Line Monitor Design of Finite-State Machines
A Study of the Experimental Validation of Fault-Tolerant Systems Using Different VHDL-Based Fault Injection Techniques
Invariant checkers: An efficient low cost technique for run-time transient errors detection
Online Testing by Protocol Decomposition
On-line testing of sensor networks: A case study
Radiation-Induced Errors in the Software Level of Real-Time Soft Processing System
Cross-level protection of circuits against faults and malicious attacks
SEU-X: A SEu un-excitability prover for SRAM-FPGAs
Concurrent error detection in nonlinear digital filters using checksum linearization and residue prediction
On Transistor Level Gate Sizing for Increased Robustness to Transient Faults
Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits
Double Adjacent Error Correction in RRAM Matrix Multiplication using Weighted Checksums
Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique
Design of a Robust 8-Bit Microprocessor to Soft Errors
BTI and leakage aware dynamic voltage scaling for reliable low power cache memories
Distributed online software monitoring of manycore architectures
High-level synthesis for security and trust
Concurrent Detection of Soft Errors Based on Current Monitoring
On the Encryption of the Challenge in Physically Unclonable Functions
Infant Mortality--The Lesser Known Reliability Issue
SEU tolerant robust memory cell design
Mitigation of fail-stop failures in integer matrix products via numerical packing
Soft error analysis of MTJ-based logic-in-memory full adder: Threats and solution
On-Line Failure Detection and Confinement in Caches
A systematic approach for Failure Modes and Effects Analysis of System-On-Chips
BPPT - Bulk potential protection technique for hardened sequentials
A side channel attack countermeasure using system-on-chip power profile scrambling
Leakage mitigation for low power microcontroller design in 40nm for Internet-of-Things (IoT)
Robust cryptographic ciphers with on-line statistical properties validation
From Nuclear Reaction to System Failures: Can We Address All Levels of Soft Errors Accurately?
A New Approach to Threshold Voltage Measurements of Transistors
A Stamping Technique to Increase the Error Correction Capacity of the (127, k, d) RS Code
Evaluation of test algorithms stress effect on SRAMs under neutron radiation
Dynamic Testing of an SRAM-Based FPGA by Time-Resolved Laser Fault Injection
Testing of Hard Faults in Simultaneous Multithreaded Processors
A Learning-Based Approach for Single Event Transient Analysis in Pass Transistor Logic
Cost-effective Resilient FPGA-based LDPC Decoder Architecture
Neural Network Quantisation for Faster Homomorphic Encryption
Simulation and Mitigation of Single Event Effects
Effect of ionizing radiation on TRNGs for safe telecommunications: Robustness and randomness
Reliability/yield trade-off in mitigating "no trouble found" field returns
Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability
Evaluation of concurrent error detection techniques on the advanced encryption standard
On-line detection of random voltage perturbations in buses with multiple-threshold receivers
A synergistic fault tolerance framework for Mbit 28nm embedded RRAM
Towards Dependable RISC-V Cores for Edge Computing Devices
Single Output Distributed Two-Rail Checker with Diagnosing Capabilities for Bus Based Self-Checking Architectures
Yield Estimation of a Memristive Sensor Array
On-line testing for differential fault attacks in cryptographic circuits
On the Effect of Aging in Detecting Hardware Trojan Horses with Template Analysis
A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features
Cost-efficient of a cluster in a mesh SRAM-based FPGA
Investigation of multi cell upset in sequential logic and validity of redundancy technique
Reliability Estimations of Large Circuits in Massively-Parallel GPU-SPICE
A Software Based Online Memory Test for Highly Available Systems
Prediction of Transient Induced by Neutron/Proton in CMOS Combinational Logic Cells
A 32-Bit COTS-Based Fault-Tolerant Embedded System
Multi-abstraction level signature generation and comparison based on radiation single event upset
On-Chip Self-Calibration of RF Circuits Using Specification-Driven Built-In Self Test (S-BIST)
Quantum AI: Harnessing the Power of Quantum Computing for Scalable and Adaptive Learning
On the functional test of L2 caches
Perturbation-immune radiation-hardened PLL with a switchable DMR structure
Modem Gain-Cell Memories in Advanced Technologies
On a Redundant Diversified Steering Angle
A Configurable Modular Test Processor and Scan Controller Architecture
Improving Error Correction with Weak-Bit Information in Resistive Memories
Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs
ShapeShifter: Protecting FPGAs from Side-Channel Attacks with Isofunctional Heterogeneous Modules
Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate Computing
A Very Flexible DSP-Based Controller for On-Line Test and Control of Industrial Processes
Data Augmentation for Machine Learning-Based Hardware Trojan Detection at Gate-Level Netlists
Efficient Concurrent Error Detection for SEC-DAEC Encoders
Use of Nuclear Codes for Neutron-Induced Nuclear Reactions in Microelectronics
A radiation tolerant and self-repair memory cell
Dual Detection of Heating and Photocurrent attacks (DDHP) Sensor using Hybrid CMOS/STT-MRAM
The Consequences of Variability in Software
An effective methodology for on-line testing of embedded microprocessors
Exploiting the Error Resilience of the Preconditioned Conjugate Gradient Method for Energy and Delay Optimization
Test Compression Using Extended Nonlinear Binary Codes
ERrOR: Improving Performance and Fault Tolerance Using Early Execution
Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs
Timing for virtual TMR in logic circuits
Novel Fault-Tolerant Adder Design for FPGA-Based Systems
Coding Scheme for Low Energy Consumption Fault-Tolerant Bus
Error-Injection-Based Failure Characterization of the IEEE 1394 Bus
Methodology and Tools Developed for Validation of COTS-based Fault-Tolerant Spacecraft Supercomputers
Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology
Power supply glitch induced faults on FPGA: An in-depth analysis of the injection mechanism
Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA
Analysis of the Equivalences and Dominances of Transient Faults at the RT Level
Robust FSMs for cryptographic devices resilient to strong fault injection attacks
RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip
From on-chip self-healing to self-adaptivity in analog/RF ICs: challenges and opportunities
A partitioning approach to improve reconfigurable neuron-inspired online BIST
Probabilistic methods for the impact of an SET in combinational logic
Simulation-based analysis of FF behavior in presence of power supply noise
Securing Scan through Plain-text Restriction
Adaptive-HMD: Accurate and Cost-Efficient Machine Learning-Driven Malware Detection using Microarchitectural Events
Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment
Special Session 4: Reliability and Circuit Simulation
Control Signal Protection For High Performance Processors
On-Chip Sensor to Monitor Aging Evolution in FinFET-Based Memories
Logic masking for SET Mitigation Using Approximate Logic Circuits
Hardening of serial communication protocols for potentially critical systems in automotive applications: LIN bus
Low-Cost, On-Line Software-Based Self-Testing of Embedded Processor Cores
Hybrid Soft Error Detection by Means of Infrastructure IP Cores
Comparison of RTL fault models for the robustness evaluation of aerospace FPGA devices
Survey of the Algorithms in the Column-Matching BIST Method
A software-based self-test strategy for on-line testing of the scan chain circuitries in embedded microprocessors
Side-Channel Extraction of Dataflow AI Accelerator Hardware Parameters
Energy-efficient and error-resilient iterative solvers for approximate computing
On-Line Error Detection and BIST for the AES Encryption Algorithm with Different S-Box Implementations
Resilient random modulo cache memories for probabilistically-analyzable real-time systems
ISA-independent post-silicon validation for the address translation mechanisms of modern microprocessors
A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation
Susceptible workload driven selective fault tolerance using a probabilistic fault model
Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set
Optimization of SEU emulation on SRAM FPGAs based on sensitiveness analysis
A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations
Development flow of on-line Software Test Libraries for asynchronous processor cores