yusuke1997/dblp-id-title huggingface dataset:
Minimal Path, Fault Tolerant, QoS Aware Routing with Node and Link Failure in 2-D Mesh NoC
Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis Information
Analysis of Specified Bit Handling Capability of Combinational Expander Networks
Relating digital imager defect rates to pixel size, sensor area and ISO
Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments
An examination of empirically derived within-die local probabilities of failure
Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms
Testing Layered Interconnection Networks
An AI-Assisted Connection Weight Prediction for Regression Testing of Integrated Circuits
Fault tolerant Newton-Raphson dividers using time shared TMR
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
An Enhanced Fault Injection Framework for FPGA-Based Soft-Cores
A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAs
Improving DNN Fault Tolerance in Semantic Segmentation Applications
Simulation Methodology for Assessing X-Ray Effects on Digital Circuits
Flexible Software-Only Diverse Redundancy on COTS GPUs for Safety-Related Kernels
The Impact of Manufacturing Defects on the Fault Tolerance of TMR-Systems
Debug Aware AXI-based Network Interface
A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing
Is RISC-V ready for Space? A Security Perspective
A Modelling Attack Resistant Low Overhead Memristive Physical Unclonable Function
Built-in Self-Repair in a 3D die stack using programmable logic
An Effective TMR Approach for Low-Latency Configurable-Accuracy Adders
Fault-Tolerant Modular Convolves
Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost
A Defect and Fault Tolerant Interconnection Network Strategy for WASP Devices
Study and Comparison of QDI Pipeline Components' Sensitivity to Permanent Faults
Reconfiguration Algorithm for Degradable Processor Arrays Based on Row and Column Rerouting
Safe Satellite Electronics Design Utilizing COTS Components, FDIR Techniques, LCL Protections, and Thorough Qualifications
Power Characterization of LFSRs
Fault Detection of Bloom Filters for Defect Maps
Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters
Can Functional Test Achieve Low-cost Full Coverage of NoC Faults?
Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells
Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with h-hot Addressing Scheme
Control Constrained Resource Partitioning for Complex SoCs
FPGA oriented design of parity sharing RS codecs
A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs
Scan attack on Elliptic Curve Cryptosystem
A built-in calibration system with a reduced FFT engine for linearity optimization of low power LNA
Fault Tolerant Active Pixel Sensors in 0.18 and 0.35 Micron Technologies
A data recomputation approach for reliability improvement of scratchpad memory in embedded systems
Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits
A System for Evaluating On-Line Testability at the RT-level
Fault Tolerant Photovoltaic Array: A Repair Circuit Based on Memristor Sensing
Image Degradation due to Interacting Adjacent Hot Pixels
Optimal Vector Selection for Low Power BIST
Low power and high speed current-mode memristor-based TLGs
Adaptive Design for Performance-Optimized Robustness
VLSI Yield Optimization Based on the Sub-Processing-Element Level Redundancy
Yield-Reliability Modeling for Fault Tolerant Integrated Circuits
Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms
A CMOS Fault Tolerant Architecture for Swith-Level Faults
Efficient algorithms for analyzing and synthesizing fault-tolerant datapaths
Fault detection and repair of DSC arrays through memristor sensing
Characterization and analysis of errors in circuit test
Hierarchical critical area extraction with the EYE tool
Hardware Trojans of Computing-In-Memories: Issues and Methods
2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2019, Noordwijk, Netherlands, October 2-4, 2019
On the Modeling of Gate Delay Faults by Means of Transition Delay Faults
The Teramac Custom Computer: Extending the Limits with Defect Tolerance
Detection of an antenna effect in VLSI designs
SET Hardened Derivatives of QDI Buffer Template
A cross-layer fault-tolerant design method for high manufacturing yield and system reliability
2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2014, Amsterdam, The Netherlands, October 1-3, 2014
On-Line Mapping of In-Field Defects in Image Sensor Arrays
Bilateral Testing of Nano-scale Fault-tolerant Circuits
Semi-Concurrent Error Detection in Data Paths
Special Session: Security and RAS in the Computing Continuum
A Study of Side-Channel Effects in Reliability-Enhancing Techniques
Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations
Non-Intrusive Test Compression for SOC Using Embedded FPGA Core
An Approximate Soft Error Reliability Sorting Approach Based on State Analysis of Sequential Circuits
Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems
BIST for logic and local interconnect resources in a novel mesh of cluster FPGA
Error Control Coding for Semiconductor Memory Systems in the Space Radiation Environment
Does the Floorplan of a Chip Affect Its Yield?
Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories
Synthesis of On-Line Testing Control Units: Flow Graph Coding/Monitoring Approach
An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing
Image Degradation due to Interacting Hot Pixels and SEUs
A BIST Technique for Crosstalk Noise Detection in FPGAs
Fault-aware sensitivity analysis for probabilistic real-time systems
Scalable and Configurable Multi-Chip SRAM in a Package for Space Applications
Modeling SRAM start-up behavior for Physical Unclonable Functions
A model of soft error effects in generic IP processors
Noise Analysis of Fault Tolerant Active Pixel Sensors
Developing a Configurable Fault Tolerant Multicore System for Optimized Sensor Processing
Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata Adder
Analyzing the Reliability of Alternative Convolution Implementations for Deep Learning Applications
A Channel-Constrained Reconfiguration Approach for Processing Arrays
Efficient Parity Prediction in FPGA
Power droop reduction during Launch-On-Shift scan-based logic BIST
SASL-JTAG: A Light-Weight Dependable JTAG
Preventing Scan Attack through Test Response Encryption
Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems
Reliability and Performance Analysis of FPGA-Based Fault Tolerant System
A-Diagnosis: A Complement to Z-Diagnosis
Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing
Incorporating Signature-Monitoring Technique in VLIW Processors
Protecting cryptographic hardware against malicious attacks by nonlinear robust codes
22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy
An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications
16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings
Design-for-testability for paper-based digital microfluidic biochips
A Single Error Correcting and Double Error Detecting Coding Scheme for Computer Memory Systems
The T9000 Transputer: A Practical Example of the Application of Standard Test Techniques
Enhanced Defect Tolerance through Matrixed Deployment of Intelligent Sensors for the Smart Power Grid
Reliability Assessment of Memristor based Gas Sensor Array
Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling
You can detect but you cannot hide: Fault Assisted Side Channel Analysis on Protected Software-based Block Ciphers
A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits
The Effect of Wire Length Minimization on Yield
Gate Failures Effectively Shape Multiplexing
On-line error detection for finite field multipliers
A Design of Self-Defect-Compensatable Hardware Neuron for Multi-layer Neural Networks
"Victim Gate" Crosstalk Fault Model
Realizing strong PUF from weak PUF via neural computing
Accurate yield estimation of circuits with redundancy
KITE: a behavioural approach to fault-tolerance in FPGA-based systems
Compact SER Models for Line-Source-Induced Charge Collection Using Model Order Reduction
Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems
A Novel Self-Repair Mechanism for Tiled Matrix Multiplication Unit
Efficient Non-Binary Hamming Codes for Limited Magnitude Errors in MLC PCMs
3DSDM: A 3 Data-Source Diagnostic Method
A dynamic test compaction method on low power test generation based on capture safe test vectors
Diagnosis of Scan Chain Failures
Fast Multi-Layer Critical Area Computation
Augmenting Scan Path SRLs with an XOR Network to Enhance Delay Fault Testing
Low Overhead Self-Correction in Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flops for Space Applications
Minimization of Trojan footprint by reducing Delay/Area impact
Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique
Analysis and Evaluation of the Effects of Single Event Upsets (SEU s) on Memories in Polar Decoders
Hierarchical Embedded Logic Analyzer for Accurate Root-Cause Analysis
Online Multiple Fault Detection in Reversible Circuits
Applying efficient fault tolerance to enable the preconditioned conjugate gradient solver on approximate computing hardware
RC-IJTAG: A Methodology for Designing Remotely-Controlled IEEE 1687 Scan Networks
Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?
Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGs
A Logistic Regression Yield Model for SRAM Bit Fail Patterns
Designs for Reducing Test Time of Distributed Small Embedded SRAMs
13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings
A Fault-Tolerant Voter Circuit in NEM Technology
Special Session: Software-Based Self-Test Generation for RISC-V - Stuck-At Generation, Functional Cell-Aware Untestability, and FPGA Demonstration -
Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes
Design of defect-tolerant scan chains for MCMs with an active substrate
Time/Temperature Degradation of Solar Cells under the Single Diode Model
Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging
Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress
Dual-Modular-Redundancy Voting Circuits for Single-Event-Transient Mitigation
Reusing the IEEE 1500 design for test infrastructure for security monitoring of Systems-on-Chip
CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level
Does Fault Tolerance Safeguard DNNs Against Bitfiip Attacks? A Case Study
On the in-field functional testing of decode units in pipelined RISC processors
Fault Tolerance for Islandable-Microgrid Sensors
Mixed Loopback BiST for RF Digital Transceivers
The Prediction of Circuit Performance Variations for Deep Submicron CMOS Processes
Analysis of the Floating Gate Defect in CMOS
Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template
Characterization of a Fault-Tolerant RISC-V System-on-Chip for Space Environments
System Level Testing via TLM 2.0 Debug Transport Interface
Limitations to Estimating Yield Based on In-Line Defect Measurements
Optimizing Waveform Accurate Fault Attacks Using Formal Methods
Towards an adaptable bit-width NMR voter for multiple error masking
Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits
A Low-Power Safety Mode for Variation Tolerant Systems-on-Chip
Efficient compression of x-masking control data via dynamic channel allocation
Fault Tolerant Multi-Layer Neural Networks with GA Training
A Digital and Wide Power Bandwidth H-Field Generator for Automatic Test Equipment
Efficient LDPC Encoder Designs for Magnetic Recording Media
Design of encoders and self-testing checkers for some systematic unidirectional error detecting codes
Fabrication Variations and Defect Tolerance for Nanomagnet-Based QCA
Novel Approaches for Fault Detection in Two-Dimensional Combinational Arrays
Influence of triple-well technology on laser fault injection and laser sensor efficiency
A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits
BRAINS: A BIST Compiler for Embedded Memories
Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code
Parallel Testing of Multi-port Static Random Access Memories for BIST
Statistical analysis of Particle/Defect Data Experiments Using Poisson and Logistic Regression
Reconfiguration-Based Defect Tolerance for Microfluidic Biochips
Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs
Timing-Aware Diagnosis for Small Delay Defects
Soft Error Tolerant BILBO FF
Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration
An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems
A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks
Detecting and Locating Faults in VLSI Implementations of the Advanced Encryption Standard
Aging analysis for recycled FPGA detection
RAPPER: Robust and APProximate ERror Tolerating Communication
Error Detection and Tolerance for Scaled Electronic Technologies
A Parametric Design of a Built-in Self-Test FIFO Embedded Memory
Determination of Yield Bounds Prior to Routing
Understanding of GPU Architectural Vulnerability for Deep Learning Workloads
On the optimization of SBST test program compaction
Cross-Correlation Approach to Detecting Issue Test Sites in Massive Parallel Testing
SAM: A comprehensive mechanism for accessing embedded sensors in modern SoCs
A Low Power Oriented Multiple Target Test Generation Method for 2-Cycle Gate-Exhaustive Faults
Fault Tolerant Hopfield Associative Memory on Torus
Lazy Error Detection for Microprocessor Functional Units
A Methodology for Efficient Simulation and Diagnosis of Mixed-Signal Systems Using Error Waveforms
Reduction of Fault Latency in Sequential Circuits by using Decomposition
High-Performance Cluster-Fault Tolerance Scheme for Hybrid Nanoelectronic Memories
Exploring soft errors (SEUs) with digital imager pixels ranging from 7 to 1.3 μm
Oxide based resistive RAM: ON/OFF resistance analysis versus circuit variability
A non-conservative software-based approach for detecting illegal CFEs caused by transient faults
Efficient utilization of hierarchical iJTAG networks for interrupts management
Chip Level Power Supply Partitioning for IDDQ Testing Using Built-In Current Sensors
Analysis of Repair Structures for Chiplet Interfaces
Testing of switch blocks in TSV-reduced Three-Dimensional FPGA
Exploiting Instruction Redundancy for Transient Fault Tolerance
Testing and Reliability Enhancement of Security Primitives
Cost analysis of a new algorithmic-based soft-error tolerant architecture
Erasure Error Correction with Hardware Detection
Hybrid BIST Using an Incrementally Guided LFSR
The 2nd Order Analysis of IDDQ Test Data
Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability
Evaluating the Impact of Aging on Path-Delay Self-Test Libraries
An Area Effective Parity-Based Fault Detection Technique for FPGAs
Survivable Self-Checking Sequential Circuits
Modeling Soft-Error Reliability Under Variability
Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip
Low cost resilient regular expression matching on FPGAs
Functional Verification Coverage vs. Physical Stuck-at Fault Coverage
A systematic methodology to improve yield per area of highly-parallel CMPs
Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments
Yield Estimation of VLSI Circuits with Downscaled Layouts
Repair algorithms for mirrored disk systems
Comprehensive Modeling of VLSI Test
Estimating the effect of single-event upsets on microprocessors
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
LFSR/SR Pseudo-Exhaustive TPG in Fewer Test Cycles
Warning Prediction Sequential for Transient Error Prevention
24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, Chicago, Illinois, USA, October 7-9, 2009
Industrial best practice: cases of study by automotive chip- makers
Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method
Analysis of Resistive Open Defects in a Synchronizer
Domino effect protection on dataflow error detection and recovery
Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits
Resilience Challenges for Exascale Systems
On the Current Behavior of Faulty and Fault-Free ICs and the Impact on Diagnosis
A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies
A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques
Low-overhead fault-tolerance for the preconditioned conjugate gradient solver
Exploring hardware transaction processing for reliable computing in chip-multiprocessors against soft errors
Constructions of the SbEC-DbED and DbEC codes, and their applications
CORE-VR: A Coherence and Reusability Aware Low Voltage Fault Tolerant Cache in Multicore
Low Cost Convolutional Code Based Concurrent Error Detection in FSMs
Radiation Effects on NVIDIA Jetson SoCs: Insights from Heavy Ion Irradiation
Simulating Wear-out Effects of Asymmetric Multicores at the Architecture Level
An Approach to the Development of a IDDQ Testable Cell Library
Errors in DNA Self-Assembly by Synthesized Tile Sets
Using partial masking in X-chains to increase output compaction for an X-canceling MISR
Rescuing healthy cores against disabled routers
Equivalent IDDQ Tests for Systems with Regulated Power Supply
Reconfiguration of One-Time Programmable FPGAs with Faulty Logic Resources
A New Method for Testing EEPLA's
Synthesis of workload monitors for on-line stress prediction
Circuit Failure Prediction by Field Test - A New Task of Testing
Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard
On-Line Fault Tolerance for FPGA Interconnect with Roving STARs
Defect Characterization for Scaling of QCA Devices
Analyzing and improving delay defect tolerance in pipelined combinational circuits
Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI
Path-delay fingerprinting for identification of recovered ICs
Framework for dynamic estimation of power-supply noise and path delay
Asymmetric ECC organization in 3D-memory via spare column utilization
Module Grouping for Defect Tolerance in Nanoscale Memory
An XOR Based Reed-Solomon Algorithm for Advanced RAID Systems
PBO-Based Pattern Replacement for Compacting Diagnostic Patterns to Achieve Complete Diagnostic Resolution
Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus Fragments
Single event upset tolerance in flip-flop based microprocessor cores
Using defect density modelling to drive the optimisation of circuit layout, maximising yield
An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors
Arbitrary Error Detection in Combinational Circuits by Using Partitioning
Detecting errors in instructions with bloom filters
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM
Modeling QCA Defects at Molecular-level in Combinational Circuits
Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories
The Evolving Role of Test ... it is now a "Value Add" Operation
Incorporating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Performance
Reconfigurable TAP controllers with embedded compression for large test data volume
Testing of Inter-Word Coupling Faults in Word-Oriented SRAMs
High Level Synthesis Techniques for Efficient Built-In-Self Repair
Markov Chain-based Modeling and Analysis of Checkpointing with Rollback Recovery for Efficient DSE in Soft Real-time Systems
Gradient Descent Iterative Correction Unit for Fixed Point Parity Based Codes
A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs
Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points
Synthesis of Multi-level Self-Checking Logic
Automatic Detection of In-field eld Defect Growth in Image Sensors
Reliability Evaluation of Repairable/Reconfigurable FPGAs
CMOS Self Checking Circuits with Faulty Sequential Functional Block
A Fault-Tolerant MPSoC For CubeSats
RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation Hardening
Exploration of System-on-Chip Secure-Boot Vulnerability to Fault-Injection by Side-Channel Analysis
A Low-Cost Hardware Approach to Dependability Validation of Ips
Generating Burst-Error Correcting Codes from Orthogonal Latin Square Codes - A Graph Theoretic Approach
Transient Error Detection and Recovery in Processor Pipelines
A Generalized Approach for the Use of Convolutional Coding in SEU Mitigation
A low cost reliable architecture for S-Boxes in AES processors
21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA
#SAT-based vulnerability analysis of security components - A case study
Maintaining proximity to functional operation conditions under enhanced-scan tests based on functional broadside tests
On-line Testing for Autonomous Systems driven by RISC-V Processor Design Verification
Hardware Trojan Detection and Isolation Using Current Integration and Localized Current Analysis
High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations
On Soft Switch Programming for Reconfigurable Array Systems
A Reconfigurable ADC Circuit with Online-Testing Capability and Enhanced Fault Tolerance
Self-Configuration of a Large Area Integrated Multiprocessor System for Video Applications
Delay Fault Detection Problems in Circuits Featuring a Low Combinational Depth
A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses
Annotated Bit Flip Fault Model
Eliminating a hidden error source in stochastic circuits
Mitigation of the impact of across chip systematic process variation using a novel system level design
A Synthesis Methodology Aimed at Improving the Quality of TSC Devices
Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique
Route-Aware Task Mapping Method for Fault-Tolerant 2D-Mesh Network-on-Chips
Inferred Fault Models for RISC-V and Arm: A Comparative Study
On-chip Generation of the Second Primary Input Vectors of Broadside Tests
A High Speed Reed-Solomon Encoder-Decoder for Fault Tolerant Solid State Disks
Improved Encoding and Decoding of Optimal $m$-Out-of-$n$ Codes
Using TMR Architectures for Yield Improvement
Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment
Neutron Irradiation Testing and Analysis of a Fault-Tolerant RISC-V System-on-Chip
Unifying scan compression
Fault Tolerant Schemes for QCA Systems
A Test-Vector Generation Methodology for Crosstalk Noise Faults
Reconfigurable distributed fault tolerant routing algorithm for on-chip networks