yusuke1997/dblp-id-title huggingface dataset:
A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package
A battery-connected 24-ratio switched capacitor PMIC achieving 95.5%-efficiency
A 94GHz duobinary keying wireless transceiver in 65nm CMOS
Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS
16MB High Density Embedded PCM macrocell for automotive-grade microcontroller in 28nm FD-SOI, featuring extension to 24MB for Over-The-Air software update
A peripheral switchable 3D stacked CMOS image sensor
An on-die all-digital delay measurement circuit with 250fs accuracy
A UWB IR timed-array radar using time-shifted direct-sampling architecture
A ± 36A integrated current-sensing system with 0.3% gain error and 400µA offset from -55°C to +85°C
A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS
Integrated Power Management and Microcontroller for Ultra-Wide Power Adaptation down to nW
A 0.6V 2.9µW mixed-signal front-end for ECG monitoring
A shorted global clock design for multi-GHz 3D stacked chips
A 1.32 TOPS/W Energy Efficient Deep Neural Network Learning Processor with Direct Feedback Alignment based Heterogeneous Core Architecture
A 32.4 ppm/°C 3.2-1.6V self-chopped relaxation oscillator with adaptive supply generation
A 4.7T/11.1T NMR compliant wirelessly programmable implant for bio-artificial pancreas in vivo monitoring
A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier
Innovative system on chip platform for Smart Grids and internet of energy applications
A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme
A 61-dB SNDR 700 µm 2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops
14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation
A 0.26% BER, 10 28 Challenge-Response Machine-Learning Resistant Strong-PUF in 14nm CMOS Featuring Stability-Aware Adversarial Challenge Selection
An N-path filter enhanced low phase noise ring VCO
A 0.6V 86.5dB-DR 40kHz-BW Inverter-Based Continuous-Time Delta-Sigma Modulator with PVT-Robust Body-Biasing Technique
A 5G New Radio SAW-less RF Transmitter with a 100MHz Envelope Tracking HPUE n77 Power Amplifier Module
Application-aware solid-state drives (SSDs) with adaptive coding
A 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS
A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET
An 8Ω, 1.4W, 0.0024% THD+N Class-D Audio Amplifier with Bridge-Tied Load Half-Side Switching Mode Achieving Low Standby Quiescent Current of 660μA
A Hybrid Dual-Path Step-Down Converter with 96.2% Peak Efficiency Using a $250\text{m}$ μ Large-DCR Inductor
A 180 mW multistandard TV tuner in 28 nm CMOS
A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS
PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators
A 28-Gb/s/pin PAM-4 Single-Ended Transmitter with High-Linearity and Impedance-Matched Driver and 3-Point ZQ Calibration for Memory Interfaces
A 2.3GHz Fully Integrated DC-DC Converter based on Electromagnetically Coupled Class-D LC Oscillators achieving 78.1% Efficiency in 22nm FDSOI CMOS
An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors
A 1S Direct-Battery-Attach Integrated Buck Voltage Regulator with 5-Stack Thin-Gate 22nm FinFET CMOS Featuring Active Voltage Balancing and Cascaded Self-Turn-ON Drivers
15 dB Conversion gain, 20 MHz carrier frequency AM receiver in flexible a-IGZO TFT technology with textile antennas
Profiting from IoT: The key is very-large-scale happiness integration
Broadwell: A family of IA 14nm processors
A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS
A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process
A linear response single exposure CMOS image sensor with 0.5e - readout noise and 76ke - full well capacity
A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL
A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low VMIN applications
EQZ-LDO: A Near-Zero EDP Overhead, >10M-Attack-Resilient, Secure Digital LDO featuring Attack-Detection and Detection-Driven Protection for a Correlation-Power-Analysis-Resilient IoT Device
A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction
A 10-bit 1-GHz 33-mW CMOS ADC
Spoken vowel classification using synchronization of phase transition nano-oscillators
A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur
112 Gb/s PAM4 ADC Based SERDES Receiver for Long-Reach Channels in 10nm Process
A 13.3 mW 60 MHz bandwidth, 76 dB DR 6 GS/s CTΔΣM with time interleaved FIR feedback
A CMOS Temperature Stabilized 2-Dimensional Mechanical Stress Sensor with 11-bit Resolution
A Proactive Voltage-Droop-Mitigation System in a 7nm Hexagon™ Processor
Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array
A 640×640 Fully Dynamic CMOS Image Sensor for Always-On Object Recognition
Automotive LIDAR Technology
A 700µW 8-channel EEG/contact-impedance acquisition system for dry-electrodes
A 7.11mJ/Gb/query data-driven machine learning processor (D 2 MLP) for big data analysis and applications
A 4.5-mW 8-b 750-MS/s 2-b/step asynchronous subranged SAR ADC in 28-nm CMOS technology
1024-Electrode Hybrid Voltage/Current-Clamp Neural Interface System-on-Chip with Dynamic Incremental-SAR Acquisition
A robust -40 to 120°C all-digital true random number generator in 40nm CMOS
An ASIC for readout of post-processed thin-film MEMS resonators by employing capacitive interfacing and active parasitic cancellation
Manufacturable 300mm platform solution for Field-Free Switching SOT-MRAM
A 2PJ/Pixel/Direction MIMO Processing Based CMOS Image Sensor for Omnidirectional Local Binary Pattern Extraction and Edge Detection
Motor Control used to be boring
Highly reliable TaOx ReRAM with centralized filament for 28-nm embedded application
A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS
An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation
A 0.5V 560kHz 18.8fJ/Cycle Ultra-Low Energy Oscillator in 65nm CMOS with 96.1ppm/°C Stability using a Duty-Cycled Digital Frequency-Locked Loop
A -106dBm 33nW Bit-Level Duty-Cycled Tuned RF Wake-up Receiver
VOTA: A 2.45TFLOPS/W Heterogeneous Multi-Core Visual Object Tracking Accelerator Based on Correlation Filters
A 5MHz BW 70.7dB SNDR noise-shaped two-step quantizer based ΔΣ ADC
An 8MHz 31.25kS/s Impedance-Monitoring IC Based on IF-Sampling Architecture with a Band-Pass Delta-Sigma ADC
An AMLED microdisplay driver SoC with built-in 1.25-Mb/s VLC transmitter
An impedance and multi-wavelength near-infrared spectroscopy IC for non-invasive blood glucose estimation
A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET
A 16-bit 10Gsps current steering RF DAC in 65nm CMOS achieving 65dBc ACLR multi-carrier performance at 4.5GHz Fout
AMASS PLL: An Active-Mixer-Adopted Sub-Sampling PLL Achieving an FOM of -255.5DB and a Reference Spur of -66.6DBC
Fully Integrated OOK-Powered Pad-Less Deep Sub-Wavelength-Sized 5-GHz RFID with On-Chip Antenna Using Adiabatic Logic in 0.18μM CMOS
A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead
A 32A 5V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN NMOS Power Transistors
A standard cell compatible bidirectional repeater with thyristor assist
92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillator
A 10-MHz 14.3W/mm 2 DAB Hysteretic Control Power Converter Achieving 2.5W/247ns Full Load Power Flipping and above 80% Efficiency in 99.9% Power Range for 5G IoTs
A Reference Oversampling Digital Phase-Locked Loop with -240 dB FOM and -80 dBc Reference Spur
A New Era of Tailored Computing
A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET
A 60Gb/s 173mW receiver frontend in 65nm CMOS technology
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS
A 19-GHz PLL with 20.3-fs Jitter
A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges
A 4.68Gb/s belief propagation polar decoder with bit-splitting register file
A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit
Record-High Performance Trantenna Based On Asymmetric Nano-Ring Fet For Polarization-Independent Large-Scale/Real-Time Thz Imaging
Navion: A Fully Integrated Energy-Efficient Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones
A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration
A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET
A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response
A 71. 4dB SNDR 30MHz BW Continuous-Time Delta-sigma Modulator Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm CMOS
A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET
A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing
An Autonomous Reconfigurable Power Delivery Network (RPDN) for Many-Core SoCs Featuring Dynamic Current Steering
System challenges and hardware requirements for future consumer devices: From wearable to ChromeBooks and devices in-between
A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold
A 1.5nJ/cls Unsupervised Online Learning Classifier for Seizure Detection
A 2.2 NEF Neural-Recording Amplifier Using Discrete-Time Parametric Amplification
A fully-differential capacitive touch controller with input common-mode feedback for symmetric display noise cancellation
A fully integrated GaN-based power IC including gate drivers for high-efficiency DC-DC Converters
A 3D-Stacked Cortex-M0 SoC with 20.3Gbps/mm 2 7.1mW/mm 2 Simultaneous Wireless Inter-Tier Data and Power Transfer
Reconfigurable Germanium Quantum-Dot Arrays for CMOS Integratable Quantum Electronic Devices
Reconstruction of multiple-user voice commands using a hybrid system based on thin-film electronics and CMOS
A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme
An Always-on 4× Compressive VGA CMOS Imager with 51pJ/Pixel and >32dB PSNR
An 8-PPM, 45 pJ/bit UWB transmitter with reduced number of PA elements
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference
A Pressure Sensing System with ±0.75 mmHg (3σ) Inaccuracy for Battery-Powered Low Power IoT Applications
A 1Gb/s energy efficient triple-channel UWB-based cognitive radio
1.74-µW/ch, 95.3%-accurate spike-sorting hardware based on Bayesian decision
56Gb/s PAM4 and NRZ SerDes transceivers in 40nm CMOS
A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS
A Compact 14 GS/s 8-Bit Switched-Capacitor DAC in 16 nm FinFET CMOS
A 0.66e - rms temporal-readout-noise 3D-stacked CMOS image sensor with conditional correlated multiple sampling (CCMS) technique
Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time
A 7nm 4GHz Arm ® -core-based CoWoS ® Chiplet Design for High Performance Computing
A Single-Topology Continuously-Scalable-Conversion-Ratio Fully Integrated Switched-Capacitor DC-DC Converter with 0-to-2.22V Output and 93% Peak-Efficiency
A 3.25Gb/s, 13.2pJ/b, 0.64mm 2 Configurable Successive-Cancellation List Polar Decoder using Split-Tree Architecture in 40nm CMOS
A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems
Circuit And Systems Based on Advanced MRAM for Near Future Computing Applications
An Aptamer-based Electrochemical-Sensing Implant for Continuous Therapeutic- Drug Monitoring in vivo
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm
A 14 µM × 26 µM 20-GB/S 3-MW CDR Circuit with High Jitter Tolerance
A 0.4-6 GHz Receiver for LTE and WiFi
A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS
A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems
An 8.3M-pixel 480fps global-shutter CMOS image sensor with gain-adaptive column ADCs and 2-on-1 stacked device structure
Fully Integrated Coherent LiDAR in 3D-Integrated Silicon Photonics/65nm CMOS
A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM
A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation
Breakthrough technologies and reference designs for new IoT applications
A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS
Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core
A 252 × 144 SPAD Pixel Flash Lidar with 1728 Dual-Clock 48.8 PS TDCs, Integrated Histogramming and 14.9-to-1 Compression in 180NM CMOS Technology
A 7NM Double-Pumped 6R6W Register File for Machine Learning Memory
A Performance-Flexible Energy-Optimized Automotive-Grade Cortex-R4F SoC through Combined AVS/ABB/Bias-in-Memory-Array Closed-Loop Regulation in 28nm FD-SOI
A Sub-mW Dual-Engine ML Inference System-on-Chip for Complete End-to-End Face-Analysis at the Edge
A 47.5nJ Resistor-to-Digital Converter for Detecting BTEX with 0.06ppb-Resolution
A 224 PW 260 PPM/°C Gate-Leakage-Based Timer for Ultra-Low Power Sensor Nodes with Second-Order Temperature Dependency Cancellation
A 28-mW 32-Gb/s/pin 16-QAM Single-Ended Transceiver for High-Speed Memory Interface
Computational memory-based inference and training of deep neural networks
A 300MHz-BW 38mW 37dB/40dB SNDR/DR Frequency-Interleaving Continuous-Time Bandpass Delta-Sigma ADC in 28nm CMOS
80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity
A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW
A 2.3-MW, 950-MHz, 8-Bit Fully-Time-Based Subranging ADC Using Highly-Linear Dynamic VTC
Fully Row/Column-Parallel In-memory Computing SRAM Macro employing Capacitor-based Mixed-signal Computation with 5-b Inputs
A microcontroller with 96% power-conversion efficiency using stacked voltage domains
A 0.72 nW, 1 Sample/s Fully Integrated pH Sensor with 65.8 LSB/pH Sensitivity
Enabling future progress in machine-learning
New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE
A 0.07mm 2 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation
2 nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology
A reconfigurable mostly-digital ΔΣ ADC with a worst-case FOM of 160dB
A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer
A 220pJ/pixel/frame CMOS image sensor with partial settling readout architecture
A 0.5-1.1V 10B Adaptive Bypassing SAR ADC Utilizing Oscillation Cycle Information of VCO-Based Comparator
An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range
A ±2A/15A Current Sensor with 1.4 μA Supply Current and ±0.35%/0.6% Gain Error From -40 to 85°C using an Analog Temperature-Compensation Scheme
A Fully Integrated Switched-Capacitor Voltage Regulator with Multi-Rate Successive Approximation Achieving 190 ps Transient FoM and 83.7% Conversion Efficiency
A 50MHz 5V 3W 90% efficiency 3-level buck converter with real-time calibration and wide output range for fast-DVS in 65nm CMOS
A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method
A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW
A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm
A 179-Lux Energy-Autonomous Fully-Encapsulated 17-mm 3 Sensor Node with Initial Charge Delay Circuit for Battery Protection
A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS
A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers
A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC
A 450mV timing-margin-free waveform sorter based on body swapping error correction
A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS
A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier and Integrated MPPT Achieving 417% Energy-Extraction Improvement and 97% Tracking Efficiency
A 10/20/30/40 MHz feed-forward FIR DAC continuous-time ΔΣ ADC with robust blocker performance for radio receivers
A 1.6-mm 2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM
A 14.7Mb/mm 2 28nm FDSOI STT-MRAM with Current Starved Read Path, 52Ω/Sigma Offset Voltage Sense Amplifier and Fully Trimmable CTAT Reference
Low VMIN 20nm embedded SRAM with multi-voltage wordline control based read and write assist techniques
An Amplifier-Less Calibration-Free SAR ADC Achieving >100dB SNDR for Multi-Channel ECG Acquisition with 667mVpp Linear Input Range
A Bidirectional High-Voltage Dual-Input Buck Converter for Triboelectric Energy-Harvesting Interface Achieving 70.72% End-to-End Efficiency
A Ka-band Switched-Capacitor RFDAC Using Edge-Combining in 22nm FD-SOI
Analog In-memory Computing in FeFET-based 1T1R Array for Edge AI Applications
A -105dB THD 88dB-SNDR VCO-Based Sensor Front-End Enabled by Background-Calibrated Differential Pulse Code Modulation
An on-chip 72×60 angle-sensitive single photon image sensor array for lens-less time-resolved 3-D fluorescence lifetime imaging
A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier
A 58.6mW real-time programmable object detector with multi-scale multi-object support using deformable parts model on 1920×1080 video at 30fps
MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor using 1.4zJ/op Superconductor Josephson Junction Devices
Challenges for high-density 16Gb ReRAM with 27nm technology
2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS
An FPGA-accelerated partial image matching engine for massive media data searching systems
A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique
Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability
Low-Power and ppm-Level Detection of Gas Molecules by Integrated Metal Nanosheets
An all 0.5V, 1Mbps, 315MHz OOK transceiver with 38-µW career-frequency-free intermittent sampling receiver and 52-µW class-F transmitter in 40-nm CMOS
A 76- to 81-GHz, 0.6° rms Phase Error Multi-channel Transmitter with a Novel Phase Detector and Compensation Technique
Memory Expansion Technology for Large-Scale Data Processing Using Software-Controlled SSD
A 900mA 93% efficient 50µA quiescent current fixed frequency hysteretic buck converter using a highly digital hybrid voltage- and current-mode control
IEEE Symposium on VLSI Circuits, VLSI Circuits 2020, Honolulu, HI, USA, June 16-19, 2020
A 3nV/vHz programmable gain/BW mixed-signal 4th order Chebyshev high-pass filter for ADSL/VDSL analog front end in 28nm CMOS
A sub-100µW multi-functional cardiac signal processor for mobile healthcare applications
A Fast Triple-Interferer Sensor (Detector and Digital Encoder) with In-Situ Reference Frequency Acquisition at 2.7-to-3.7GHz in 0.13μM CMOS
A Compact 8-bit, 8 GS/s 8×TI SAR ADC in 16nm with 45dB SNDR and 5 GHz ERBW
A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF
A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS
A 97.99 dB SNDR, 2 kHz BW, 37.1 µW noise-shaping SAR ADC with dynamic element matching and modulation dither effect
An Automatic Ear Detection Technique in Capacitive Sensing Readout IC Using Cascaded Classifiers and Hovering function
2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016
A 6.5/11/17.5/30-GHz high throughput interferometer-based reactance sensors using injection-locked oscillators and ping-pong nested chopping
A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process
A Probabilistic Self-Annealing Compute Fabric Based on 560 Hexagonally Coupled Ring Oscillators for Solving Combinatorial Optimization Problems
A 100Mb/s Galvanically-Coupled Body-Channel-Communication Transceiver with 4.75pJ/b TX and 26.8 pJ/b RX for Bionic Arms
A 25-Gb/s, -10.8-dBm input sensitivity, PD-bandwidth tolerant CMOS optical receiver
Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM
A 1-5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving -43dB EVM at 1024 QAM
A 2.048 Mb/s full-duplex free-space optical transceiver IC for a real-time in vivo neurofeedback mouse experiment under social interaction
The evolution of next-generation data center networks for high capacity computing
A 64×64 APD-Based ToF Image Sensor with Background Light Suppression up to 200 klx Using In-Pixel Auto-Zeroing and Chopping
A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur
Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS
A Reconfigurable High-Bandwidth CMOS-MEMS Capacitive Accelerometer Array with High-g Measurement Capability and Low Bias Instability
Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS
A 0.25-V, 5.3-pW Voltage Reference with 25-μV/°C Temperature Coefficient, 140-μV/V Line Sensitivity and 2, 200-μm 2 Area in 180nm
2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage
A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS
Enabling closed-loop neural interface: A bi-directional interface circuit with stimulation artifact cancellation and cross-channel CM noise suppression
A 1.53 mm 3 crystal-less standards-compliant Bluetooth Low Energy module for volume constrained wireless sensors
A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disorders
A 4.45 ms Low-Latency 3D Point-Cloud-Based Neural Network Processor for Hand Pose Estimation in Immersive Wearable Devices
Industrial IoT with Crystal-Free Mote-on-Chip
Active-lite interposer for 2.5 & 3D integration
A 5.8 pJ/Op 115 billion ops/sec, to 1.78 trillion ops/sec 32nm 1000-processor array
A 1.2V 8.3nJ energy-efficient CMOS humidity sensor for RFID applications
6.5µW 92.3DB-DR Biopotential-Recording Front-End with 360MVPP Linear Input Range