yusuke1997/dblp-id-title huggingface dataset:
Reliability-Aware Task Allocation Latency Optimization in Edge Computing
Controllability and observability in mixed signal cores
Measuring the performance impact of permanent faults in modern microprocessor architectures
Encoded Check Driven Concurrent Error Detection in Particle Filters for Nonlinear State Estimation
A New Self-Checking Code-Disjoint Carry-Skip Adder
Automated Logic SER Analysis and On-Line SER reduction
Fault-tolerant system for catastrophic faults in AMR sensors
Efficient Optimized Testing of Resistive RAM Based Convolutional Neural Networks
On Derating Soft Error Probability Based on Strength Filtering
Effective Control Flow Integrity Checks for Intrusion Detection
HCD-Induced GIDL Increase and Circuit Implications
A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs
CDF Distance Based Statistical Parameter Extraction Using Nonlinear Delay Variation Models
DFx for massively multiprocessors
Stop & Go BIST
Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits
Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit
On the maximization of the sustained switching activity in a processor
A New Approach for Transient Fault Injection Using Symbolic Simulation
Variation-Resilient Design Techniques for Energy-Constrained Systems
Voltage margins identification on commercial x86-64 multicore microprocessors
Experimental Evaluation of Master/Checker Architecture Using Power Supply- and Software-Based Fault Injection
RIIF-2: Toward the next generation reliability information interchange format
Design for Resilience to Soft Errors and Variations
Low Power embedded DRAM caches using BCH code partitioning
Efficient Fault Injection based on Dynamic HDL Slicing Technique
Combining Fault Simulation and Beam Data for CNN Error Rate Estimation on RISC-V Commercial Platforms
On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits
Novel self-test methods to reduce on-chip memory requirements and improved test coverage
Error Rate Estimation for a Flight Application Using the CEU Fault Injection Approach
Anomalous IoT Behavior Detection Based on SARIMA Reference Waveform
On a Side Channel and Fault Attack Concurrent Countermeasure Methodology for MCU-based Byte-sliced Cipher Implementations
Test pattern generation to detect multiple faults in ROBDD based combinational circuits
Built-In Self Test for Low Cost Testing of a 60 MHz Synchronous Flash Memory
Flight Safety Certification Implications for Complex Multi-Core Processor based Avionics Systems
Detecting Errors in Convolutional Neural Networks Using Inter Frame Spatio-Temporal Correlation
26th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2020, Napoli, Italy, July 13-15, 2020
Detecting Hardware Faults in Approximate Adders via Minimum Redundancy
Adaptive Block Error Correction for Memristive Crossbars
FAUST: FAUlt-injection Script-based Tool
A Systematical Method of Quantifying SEU FIT
An innovative standard cells remapping method for in-circuit critical parameters monitoring
Path (Min) Delay Faults and Their Impact on Self-Checking Circuits' Operation
22nd IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2016, Sant Feliu de Guixols, Spain, July 4-6, 2016
Real-time on-chip supply voltage sensor and its application to trace-based timing error localization
Lightweight Protection of Cryptographic Hardware Accelerators against Differential Fault Analysis
Low leakage radiation tolerant CAM/TCAM cell
Soft error detection and correction for FFT based convolution using different block lengths
Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits
Tolerance to Small Delay Defects by Adaptive Clock Stretching
Aging analysis of circuit timing considering NBTI and HCI
Heavy Ion Effects on Configuration Logic of Virtex FPGAs
A Low Capture Power Oriented X-Identification-Filling Co-Optimization Method
A New Decoding Method for Double Error Correcting Cross Parity Codes
Hardware-in-the-Loop-Based Dependability Analysis of Automotive Systems
Highly Reliable Power Aware Memory Design
Variations of fault manifestation during Burn-In - A case study on industrial SRAM test results
Estimation of oxide breakdown effects by fault injection
Separate Dual-Transistor Registers - A Circuit Solution for On-line Testing of Transient Error in UDSM-IC
Microcontroller Performance Screening: Optimizing the Characterization in the Presence of Anomalous and Noisy Data
Sizing CMOS Circuits for Increased Transient Error Tolerance
A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits
Recovering Information on the CVA6 RISC-V CPU with a Baremetal Micro-Architectural Covert Channel
24th IEEE International Symposium on On-Line Testing And Robust System Design, IOLTS 2018, Platja D'Aro, Spain, July 2-4, 2018
On the Design of Long-Life Reliable Systems for Ground-Based Applications
Application dependent FPGA testing method using compressed deterministic test vectors
A New Domains-based Isolation Design Flow for Reconfigurable SoCs
Towards improved survivability in safety-critical systems
A self-consistent model to estimate NBTI degradation and a comprehensive on-line system lifetime enhancement technique
On the in-field test of embedded memories
The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks
Towards optimized functional evaluation of SEE-induced failures in complex designs
An Integrated Testbed for Trojans in Printed Circuit Boards with Fuzzing Capabilities
Recipes to build-up a rad-hard CMOS memory
Optimization of the Theory of FDD of DES for Alleviation of the State Explosion Problem and Development of CAD Tools for On-line Testing of Digital VLSI Circuits
Sequential Circuits Applicable for Detecting Different Types of Faults
Reduced overhead soft error mitigation using error control coding techniques
Comparative Analysis of TID Effects in a 65 nm FD-SOI Process Under Gamma-Ray and Alpha-Ray Irradiation
New Self-Checking Circuits by Use of Berger-Codes
EM Fault Injection-Induced Clock Glitches: From Mechanism Analysis to Novel Sensor Design
A generic embedded sequence generator for constrained-random validation with weighted distributions
Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip
A Memristive Architecture for Process Variation Aware Gas Sensing and Logic Operations
A Vulnerability Factor for ECC-protected Memory
Designing Reliable Embedded Systems Based on 32 Bit Microprocessors
Coding Techniques for Low Switching Noise in Fault Tolerant Busses
A novel methodology to increase fault tolerance in autonomous FPGA-based systems
Field profiling & monitoring of payload transistors in FPGAs
On the Facilitation of Voltage Over-Scaling and Minimization of Timing Errors in Floating-Point Multipliers
Experimental evaluation of neutron-induced errors on a multicore RISC-V platform
A real-case application of a synergetic design-flow-oriented SER analysis
Towards automated fault pruning with Petri Nets
On-Line Multiple-Fault-Detection of Fuzzy Controllers
Comparing transient-fault effects on synchronous and on asynchronous circuits
Modified DEC BCH codes for parallel correction of 3-bit errors comprising a pair of adjacent errors
Should Logic SER be Solved at the Circuit Level?
A Fuzzy Logic-Based System for Detecting Trustable Physical Unclonable Functions
On-Line Method to Limit Unreliability and Bit-Aliasing in RO-PUF
An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing
A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace Applications
Automatic Insertion of Fault-Tolerant Structures at the RT Level
Feasibility of software-based repair for program memories
Real-time transient error and induced noise cancellation in linear analog filters using learning-assisted adaptive analog checksums
Feedback-Tuned Fuzzing for Accelerating Quality Verification of Approximate Computing Design
Variation of SRAM Alpha-Induced Soft Error Rate with Technology Node
Exploiting application resiliency for energy-efficient and adequately-reliable operation
Spread in Alpha-Particle-Induced Soft-Error Rate of 90-nm Embedded SRAMs
A New Method for Concurrent Checking by Use of a 1-out-of-4 Code
Global and Local Process Variation Simulations in Design for Reliability approach
A single chip dependable and adaptable payload Data Processing Unit
Real-time checking of linear control systems using analog checksums
17th IEEE International On-Line Testing Symposium (IOLTS 2011), 13-15 July, 2011, Athens, Greece
An Improved Markov Source Design for Scan BIST
Theoretical Performance Bounds of a Probability of Bit Error Estimator Used in Digital Links Employing Binary Block Codes
Double node charge sharing SEU tolerant latch design
A fault attack robust TRNG
Introduction to the Special Session on Secure Implementations
A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities
Checker No-Harm Alarm Robustness
11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France
A Silicon-Based Yiel Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios
The functional and performance tolerance of GPUs to permanent faults in registers
An odd-even scheme to prevent a packet from being corrupted and dropped in fault tolerant NoCs
Concurrent error detection and tolerance in Kalman filters using encoded state and statistical covariance checks
Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm
A fault-tolerant sequential circuit design for SAFs and PDFs soft errors
A bit level area aware cache-based architecture for memory repairs
A Study of High Temperature Effects on Ring Oscillator Based Physical Unclonable Functions
Fault attack resistant deterministic random bit generator usable for key randomization
On-Line Test of Fully Integrated Voltage Regulators for High Performance Microprocessors of Autonomous Systems
Error Modeling for Image Processing Filters accelerated onto SRAM-based FPGAs
SENAS: Security driven ENergy Aware Scheduler for Real Time Approximate Computing Tasks on Multi-Processor Systems
An Analytical Model for Reliability Evaluation of NoC Architectures
A high throughput configurable parallel encoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes
Exploiting Reconfigurable Intelligent Surfaces to Achieve Multi-Receiver Physical Layer Security
Online error detection and recovery in dataflow execution
Fail-safety in core-based system design
Learning-Based On-Line Testing in Feedforward Neural Networks
Trojan circuits preventing and masking in sequential circuits
Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods
A reliable fault classifier for dependable systems on SRAM-based FPGAs
Hardening Techniques against Transient Faults for Asynchronous Circuits
Logic Insertion to Speed-Up Logic Verification: A Recent Development
A Fault-Tolerant Attitude Determination System Based on COTS Devices
Robust Machine Learning Systems: Reliability and Security for Deep Neural Networks
Detecting the Existence of Malfunctions in Microcontrollers Utilizing Power Analysis
Scrubbing and Partitioning for Protection of Memory Systems
Integrating Scan Design and Soft Error Correction in Low-Power Applications
Transient Bitflip Injection in Microprocessor Embedded Applications
Single Phase Clock Based Radiation Tolerant D Flip-flop Circuit
Design flows for resilient energy-efficient systems
MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors
Fast, Parallel Two-Rail Code Checker with Enhanced Testability
An Enhanced Logic BIST Architecture for Online Testing
An Off-Chip Sensor Circuit for On-Line Transient Current Testing
Identifying aging-aware representative paths in processors
Built-in performance monitoring of mixed-signal/RF front ends using real-time parameter estimation
Noise margin, critical charge and power-delay tradeoffs for SRAM design
Blurring the Layers of Abstractions: Time to Take a Step Back?
Assessment of the amplitude-duration criterion for SET/SEU robustness evaluation
Analyzing SEU Effects in SRAM-based FPGAs
Detection of Trojan HW by using hidden information on the system
Studying Aging and Soft Error Mitigation Jointly under Constrained Scenarios in Multi-Cores
Integrating embedded test infrastructure in SRAM cores to detect aging
Functional and Timing Implications of Transient Faults in Critical Systems
Novel DRAM mitigation technique
Detecting Hardware Trojans in Microprocessors via Hardware Error Correction Code-based Modules
Briefing power/reliability optimization in embedded software design
Using Low Pass Filters in Mitigation Techniques against Single-Event Transients in 45nm Technology LSIs
25th IEEE International Symposium on On-Line Testing and Robust System Design, IOLTS 2019, Rhodes, Greece, July 1-3, 2019
Generalized parity-check matrices for SEC-DED codes with fixed parity
Probabilistic Concurrent Error Compensation in Nonlinear Digital Filters Using Linearized Checksums
Adaptive Testing of Compute-in-Memory Based CNNs Using Probabilistic Test Acceptance Limits
State-aware single event analysis for sequential logic
2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014, Platja d'Aro, Girona, Spain, July 7-9, 2014
Highs and lows of radiation testing
Fault-Secure Interface Between Fault-Tolerant RAM and Transmission Channel Using Systematic Cyclic Codes
A low-cost input vector monitoring concurrent BIST scheme
Estimation of component criticality in early design steps
A self-scrubbing scheme for embedded systems in radiation environments
Life-Time Prognostics of Dependable VLSI-SoCs using Machine-learning
A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits
A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST
NAVIgator: Exploring the Voltage Limits of AMD NAVI GPUs for Energy Efficient Computing
Effective Application-level Error Modeling of Permanent Faults on AI Accelerators
Compact Modeling of NBTI Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement
Toward efficient check-pointing and rollback under on-demand SBST in chip multi-processors
Built-In-Self-Test of Analogue Circuits Using Optimised Fault Sets and Transient Response Testing
Low-Cost On-Line Fault Detection Using Control Flow Assertions
Fully distributed initialization procedure for a 2D-Mesh NoC, including off-line BIST and partial deactivation of faulty components
Analysis of BTI aging of level shifters
Fine-grain analysis of the parameters involved in aging of digital circuits
Smart Temperature Sensor for On-Line Monitoring in Automotive Applications
Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers
A BISR Architecture for Embedded Memories
Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies
Evaluating large grain TMR and selective partial reconfiguration for soft error mitigation in SRAM-based FPGAs
Single-Output Embedded Checkers for Systematic Unordered Codes
Reliability of computing systems: From flip flops to variables
Recovering Sequential Circuits from Temporary Faults: The Survival Capability of Scan-Cells
Silent Data Corruptions in Computing: Understand and Quantify
A low-cost solution for developing reliable Linux-based space computers for on-board data handling
Identification of Critical Errors in Imaging Applications
13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece
Innovative Design Platforms for Reliable SoCs in Advanced Nanometer Technologies
SRAM Cell Design Protected from SEU Upsets
A High Speed Encoder for Recursive Systematic Convolutive Codes
Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout
Muon-Ra: Quantum random number generation from cosmic rays
I-V Fast IDDQ Current Sensor for On-Line Mixed-Signal/Analog Test
7th IEEE International On-Line Testing Workshop (IOLTW 2001), 9-11 July 2001, Taormina, Italy
Shielding Performance Monitor Counters: a double edged weapon for safety and security
Precise fault-injections using voltage and temperature manipulation for differential cryptanalysis
Near-Optimal Node Selection Procedure for Aging Monitor Placement
Robustness in automotive electronics: An industrial overview of major concerns
Evaluating Alpha-induced soft errors in embedded microprocessors
Functional level embedded self testing for Walsh transform based adaptive hardware
Analysis of FinFET technology on memories
Efficient Software-Based Partitioning for Commercial-off-the-Shelf NoC-based MPSoCs for Mixed-Criticality Systems
A Hybrid Approach to Fault Detection and Correction in SoCs
Detecting Functional Safety Violations in Online AI Accelerators
SETTOFF: A fault tolerant flip-flop for building Cost-efficient Reliable Systems
Relaxing DRAM refresh rate through access pattern scheduling: A case study on stencil-based algorithms
Security and Reliability Evaluation of Countermeasures implemented using High-Level Synthesis
A framework to support the design of COTS-based reliable space computers for on-board data handling
SRAM cell design using tri-state devices for SEU protection
A hybrid reliability assessment method and its support of sequential logic modelling
Neuromorphic Computing for Embodied Intelligence in Autonomous Systems: Current Trends, Challenges, and Future Directions
A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing
Silent Data Corruption and Reliability Risks due to Faults Affecting High Performance Microprocessors' Caches
A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans
On Line Testing of Single Feedback Bridging Fault in Cluster Based FPGA by Using Asynchronous Element
Reliability Properties Assessment at System Level: A Co-design Framework
Evaluation of SET and SEU Effects at Multiple Abstraction Levels
Neutron-induced soft error rate estimation for SRAM using PHITS
Resilience, Production Yield and Self-Configuration in the Future Massively Defective Nanochips
Combinational Logic Soft Error Analysis and Protection
A fully-automated flow for ITAR-free rad-hard Atmel FPGAs
Design techniques and tradeoffs in implementing non-destructive field test using logic BIST self-test
VPUF: Voter based physical unclonable function with high reliability and modeling attack resistance
High-Level Synthesis Methodology for On-Line Testability Optimization
iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack
Fast BCH 1-Bit Error Correction Combined with Fast Multi-Bit Error Detection
Loopback output router for reliable Network on Chip
SLM ISA and Hardware Extensions for RISC-V Processors
Embedded high-precision frequency-based capacitor measurement system
Controller augmentation and test point insertion at RTL for concurrent operational unit testing
A-SOFT-AES: Self-adaptive software-implemented fault-tolerance for AES
How to Cope with SEU/SET at Chip Level? The Example of a Microprocessor Family
An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits
Online fault testing of reversible logic using dual rail coding
Analysis of on-line self-testing policies for real-time embedded multiprocessors in DSM technologies
A Robust Fault Detection Scheme for Concurrent Testing of Linear Digital Systems
Neuron-PUF: Physical Unclonable Function Based on a Single Spiking Neuron
Cost-Effective Fault Tolerance for CNNs Using Parameter Vulnerability Based Hardening and Pruning
Novel BTI Robust Ring-Oscillator-Based Physically Unclonable Function
Solutions for the self-adaptation of communicating systems in operation
Reduced-code static linearity test of SAR ADCs using a built-in incremental ∑Δ converter
An intellectual property core to detect task schedulling-related faults in RTOS-based embedded systems
LED Alert: Supply Chain Threats for Stealthy Data Exfiltration in Industrial Control Systems
A fault tolerant journalized stack processor architecture
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
PISA: Power-robust Multiprocessor Design for Space Applications
Reliable and secure memories based on algebraic manipulation correction codes
Jamming resistant encoding for non-uniformly distributed information
AKARI-X: A pseudorandom number generator for secure lightweight systems
Towards Error Resilient and Power-Efficient Adaptive Multiprocessor System using Highly Configurable and Flexible Cross-Layer Framework
Improving Fault Coverage in System Tests
Time-Sensitive Control-Flow Checking for Multitask Operating System-Based SoCs
Variability-aware and fault-tolerant self-adaptive applications for many-core chips
Fault injection in GPGPU cores to validate and debug robust parallel applications
An Anomalous Behavior Detection Method Based on Power Analysis Utilizing Steady State Power Waveform Predicted by LSTM
Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading
Cross-Layer Control Adaptation for Autonomous System Resilience
ESIFT: Efficient System for Error Injection
A low-cost fault-tolerant technique for Carry Look-Ahead adder
New Techniques for Accelerating Fault Injection in VHDL Descriptions
Error masking with approximate logic circuits using dynamic probability estimations
Technology Scaling Trends and Accelerated Testing for Soft Errors in Commercial Silicon Devices
Design of embedded constant weight code checkers based on averaging operations
Self-Stabilizing High-Speed Communication in Multi-Synchronous GALS Architectures
Hardware-Trojan Classification based on the Structure of Trigger Circuits Utilizing Random Forests
Revisiting random access scan for effective enhancement of post-silicon observability
Pushing the limits: How fault tolerance extends the scope of approximate computing
Machine Learning-Based Parametric Fault Detection in Analog and Mixed-Signal Circuits
Factors That Impact the Critical Charge of Memory Elements
On-Line Error Detection in Wireless RF Transmitters Using Real-time Streaming Data
Advanced double-sampling architectures
Dependable Deep Learning: Towards Cost-Efficient Resilience of Deep Neural Network Accelerators against Soft Errors and Permanent Faults
On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization
Application Specific True Critical Paths Identification in Sequential Circuits
Embedding test patterns into Low-Power BIST sequences
CMOS Characterization and Compact Modelling for Circuit Reliability Simulation
Error detection in 2-D Discrete Wavelet lifting transforms
An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems
Developing Fault Injection Environment for Complex Experiments
HATE: a HArdware Trojan Emulation Environment for Microprocessor-based Systems
EnSuRe: Energy & Accuracy Aware Fault-tolerant Scheduling on Real-time Heterogeneous Systems
$\text{MP}\ell\circ \mathrm{C}$: Privacy-Preserving IP Verification Using Logic Locking and Secure Multiparty Computation
Soft-errors resilient logic optimization for low power
Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features
Variation-aware Fault Modeling and Test Generation for STT-MRAM
Integrated Test Structures for Reliability Investigation under Dynamic Stimuli
On the Design of Self-Testing Checkers for Modified Berger Codes
On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check
Hierarchical RTL-based combinatorial SER estimation
Analyzing Fault Effects in Fault Insertion Experiments
An on-line fault detection technique based on embedded debug features
A New On-Line Robust Approach to Design Noise Immune Speech Recognition Systems
The positive effect on IC yield of embedded Fault Tolerance for SEUs