yusuke1997/dblp-id-title huggingface dataset:
Qualcomm Hexagon DSP: An architecture optimized for mobile multimedia and communications
Adaptive energy management features of the POWER7TM processor
RNGD - Tensor Contraction Processor for Sustainable AI Computing
The ΛNTON 3 ASIC: a Fire-Breathing Monster for Molecular Dynamics Simulations
TeraOPS hardware: A new massively-parallel MIMD computing fabric IC
2019 IEEE Hot Chips 31 Symposium (HCS), Cupertino, CA, USA, August 18-20, 2019
Hot Chips 2020 Posters
Co-Packaged Silicon Photonics Switches for Gigawatt AI Factories
The Intel® Quick Sync Video technology in the 2nd-generation Intel Core processor family
Automatic number plate recognition system on an ARM-DSP and FPGA heterogeneous SoC platforms
2014 IEEE Hot Chips 26 Symposium (HCS), Cupertino, CA, USA, August 10-12, 2014
Hot Chips 2014 Nvidia's denver processor
AMD Next Generation "Zen 4" Core and 4th Gen AMD EPYC™ 9004 Server CPU
Hot ChipsKeynote
Picasso: An Area/Energy-Efficient End-to-End Diffusion Accelerator with Hyper-Precision Data Type
UB-mesh: An New Interconnection Technology for Large AI SuperNode
Comparison of Key/Value Store (KVS) in software and programmable hardware
The chip design game at the end of Moore's law
Niagara-2: A highly threaded server-on-a-chip
1TOPS/W software programmable media processor
Passage M1000 : A 3D Photonic Interposer for AI
AI Research at Scale-Opportunities on the Road Ahead
PCI express 3.0 overview
HNPU-V2: A 46.6 FPS DNN Training Processor for Real-World Environmental Adaptation based Robust Object Detection on Mobile Devices
UltraScale+ MPSoC and FPGA families
OpenCL*, heterogeneous computing, and the CPU
VTA-NIC: Deep Learning Inference Serving in Network Interface Cards
A Scalable Multi-Chiplet Deep Learning Accelerator with Hub-Side 2.5D Heterogeneous Integration
Accelerating ML Recommendation with over a Thousand RISC-V/Tensor Processors on Esperanto's ET-SoC-1 Chip
Bandwidth engine® serial memory chip breaks 2 billion accesses/sec
Game developer's perspective on OpenCL
Transactional memory introduction
T4: A highly threaded server-on-a-chip with native support for heterogeneous computing
Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond
Silicon Photonics Technology Platform for integration of optical IOs with ASICs
LightOn Optical Processing Unit : Scaling-up AI and HPC with a Non von Neumann co-processor
DOJO: The Microarchitecture of Tesla's Exa-Scale Computer
Next Generation "Zen 3" Core
TILE-Gx100 ManyCore processor: Acceleration interfaces and architecture
SK Hynix AI-Specific Computing Memory Solution: From AiM Device to Heterogeneous AiMX-xPU System for Comprehensive LLM Inference
QORIQ ® LS1012A: Big things in small packages: 64-bit core in a sub-10mm package
A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology
Helio X20: The first tri-gear mobile SoC with CorePilot™ 3.0 technology
The future of wireless networking
ARMv8-A next-generation vector architecture for HPC
ESESC: A fast performance, power, and temperature multicore simulator
Second generation bandwidth Engine® IC breaks 4.5 billion accesses/sec
Stratix® 10: 14nm FPGA delivering 1GHz
Looking at transportation in new ways
A Machine Learning Supercomputer with an Optically Reconfigurable Interconnect and Embeddings Support
SPARC M6 Oracle's next generation processor for enterprise systems
NVIDIA'S Tegra K1 system-on-chip
Encoder logic for reducing serial I/O power in sensors and sensor hubs
FPGA augmented ASICs: The time has come
A Heterogeneous SoC for Bluetooth LE in 28nm
HyperAccel Latency Processing Unit (LPU TM ) Accelerating Hyperscale Models for Generative AI
Kraken: A Direct Event/Frame-Based Multi-sensor Fusion SoC for Ultra-Efficient Visual Processing in Nano-UAVs
TeraPHY: A Chiplet Technology for Low-Power, High-Bandwidth in-Package Optical I/O
MvEcho - acoustic response modelling for auralisation
X e HPC Ponte Vecchio
HotChips security tutorial
ARM next-generation IP supporting Avago high-end networking
OpenPOWER: Reengineering a server ecosystem for large-scale data centers
NVIDIA A100 GPU: Performance & Innovation for GPU Computing
Flexible video processing platform for 8K UHD TV
Innovation envelope: Hot chips in blades
VENICE: A compact vector processor for FPGA applications
PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications
The Journey to AI Pervasiveness
The utility of fast active messages on many-core chips: Efficient supercomputing project
AMD Radeon™ HD 7970 with graphics core next (GCN) architecture
Exciting Directions for ML Models and the Implications for Computing Hardware
POWER9: Processor for the cognitive era
Architecture of the Hexagon™ 680 DSP for mobile imaging and computer vision
Software transactional memory
Semiconductors Run the World : Hot Chips 2022
Nvidia Data Center Processing Unit (DPU) Architecture
Intel® 5520 chipset: An I / O hub chipset for server, workstation, and high end desktop
Fully integrated switched-capacitor DC-DC conversion
100Gbit/s, 120km, PAM 4 based switch to switch, layer 2 silicon photonics based optical interconnects for datacenters
Building a 40 Gbps next generation virtualized security processor: HOT CHIPS 23 - August 2011
Panel session Asia: Partner or competitor?
Power management architecture of the 2nd generation Intel® Core microarchitecture, formerly codenamed Sandy Bridge
SambaNova SN40L RDU: Breaking the Barrier of Trillion+ Parameter Scale Gen AI Computing
2009 IEEE Hot Chips 21 Symposium (HCS), Stanford, CA, USA, August 23-25, 2009
Basilisk: A 34mm² End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS : Integrated Systems Laboratory (ETH Zürich)
Design and development of a an ultra-low power Intel architecture MCU class SoCs
The Maven vector-thread architecture
High-density Multi-tenant Bare-metal Cloud with Memory Expansion SoC and Power Management
Hybrid on-chip data networks
Current trends for hardware and software developers
Pascal GPU with NVLink
The Blue Gene/Q Compute chip
High capacity and high performance 20nm FPGAs
Hummingbird™ Low-Latency Computing Engine
Hot Chips 2012 AMD "Trinity" APU
Swizzle Switch: A self-arbitrating high-radix crossbar for NoC systems
FABRIC8LABS: Electrochemical Additive Manufacturing (ECAM) For Cooling High Performance ICs
Mitigating exploits, rootkits and advanced persistent threats
Makers from Hobbyists to professionals
Hot chips 18 industry panel: Who owns the living room?
EveractiveSelf-Powered SoC with Energy Harvesting, Wakeup Receiver, and Energy-Aware Subsystem
Bixby: The scalability and coherence directory ASIC in Oracle's highly scalable enterprise systems
CYW89459: High Performance and Low Power Wi-Fi and Bluetooth 5.1 Combo Chip for IoT and Automotive
Silicon MEMS oscillators for high speed digital systems
Computer and Redundancy Solution for the Full Self-Driving Computer
Memory processing units
2006 IEEE Hot Chips 18 Symposium (HCS), Stanford, CA, USA, August 20-22, 2006
Up and Running with Rapidus : How Japan and Cutting-Edge Technologies are Transforming Semiconductor Manufacturing
MIAOW: An open source GPGPU
The Nvlink-Network Switch: Nvidia's Switch Chip for High Communication-Bandwidth Superpods
IC Technology - What Will the Next Node Offer Us?
Research accelerator for multiple processors
Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor
One billion packet per second frame processing pipeline
Adelia: A 4nm LLM Processor for Efficient Generative Al Inference
Facebook: Server board design
7NM "NAVI" GPU - A GPU Built for Performance and Efficiency
A Plug-and-Play Universal Photonic Processor for Quantum Information Processing
Ultra-low power design approaches for IoT
System Architecture and Software Stack for GDDR6-AiM
Modularizing the microprocessor core to outperform traditional out-of-order
3D reconstruction with tango
New Value Creation by Nano-Tactile Sensor Chip Exceeding our Fingertip Discrimination Ability
A scalable heterogeneous multicore architecture for ADAS: Presented at HOT CHIPS: A symposium on high performance chips Flint Center, Cupertino, CA
IBM zEnterprise 196 processor
MEGA.mini: A NPU with Novel Heterogeneous AI Processing Architecture Balancing Efficiency, Performance, and Intelligence for the Era of Generative AI
Scaling of Memory Performance and Capacity with CXL Memory Expander
Connecting the internet of everything
Video Coding Unit (VCU) : Hot Chips 2021
A Photonic Neural Network Using < 1 Photon per Scalar Multiplication
Graphcore
Photonic co-processors in HPC: Using LightOn OPUs for Randomized Numerical Linear Algebra
HSA memory model
EdgeDiff: Multi-modal Few-step Diffusion Model Accelerator with Mixed-Precision and Reordered Group-Quantization for On-device Generative AI Motivation
Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor
IoT device development challenges and solutions
An Energy-efficient Floating-Point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory
Technology scaling at an inflexion point: What next? (FPGA perspective)
A low-latency, high-bandwidth ethernet switch chip
Xbox Series X System Architecture
The Groq Software-defined Scale-out Tensor Streaming Multiprocessor : From chips-to-systems architectural overview
ML Benchmark Design Challenges
Welcome from general chairs
Next Generation "Zen 5" Core
AMD'S "LLANO" Fusion APU
Next Gen MTIA -Recommendation Inference Accelerator
Optical backplanes with 3D integrated photonics?
CogniVision: A mW Power envelope SoC for Always-on Smart Vision in 40nm
Toward accelerating deep learning at scale using specialized hardware in the datacenter
CMOS biochips for point-of-care molecular diagnostics
Low power and high performance 3-D multimedia platform
A Technical Overview of Cortex-M55 and Ethos-U55: Arm's Most Capable Processors for Endpoint AI
Arm Neoverse N1 Cloud-to-Edge Infrastructure SoCs
Distributed Services Architecture
A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode
The next generation 65-nm FPGA
RTX 5090: Designed for the Age of Neural Rendering
Medfield smartphone SOC Intel® Atom Z2460 processor
The X e GPU Architecture
AMD Versal ™ AI Edge Series Gen 2 for Vision and Automotive
Architectural challenges: AI Chips, Decision Support and High Performance Computing
Compute substrate for Software 2.0
The RISC-V instruction set
Blackford: A duall processor chipset for servers and workstatiions
Exynos 1080 High-performance, low-power CPU and GPU with AMIGO
High performance and efficient single-chip small cell base station SoC
A CORDIC-based Trigonometric Hardware Accelerator with Custom Instruction in 32-bit RISC-V System-on-Chip
Xilinx Virtex-6 and Spartan-6 FPGA families
Heterogeneous system architecture overview
Google's Training Chips Revealed: TPUv2 and TPUv3
The stanford pervasive parallelism lab
Power management of the third generation intel core micro architecture formerly codenamed ivy bridge
LSPU: A 20.7 ms Low-Latency Point Neural Network-Based 3D Perception and Semantic LiDAR SLAM System-on-Chip for Autonomous Driving System
SeaMicro SM10000-64 server: Building datacenter servers using cell phone chips
Surviving the end of scaling of traditional micro processors in HPC
What a fast FPU means for algorithms: A story of vector elementary functions
NVIDIA® Ion
Security basics
2015 IEEE Hot Chips 27 Symposium (HCS), Cupertino, CA, USA, August 22-25, 2015
Gen-Z Chipsetfor Exascale Fabrics
Roadmap for design and EDA infrastructure for 3D products
DOJO: Super-Compute System Scaling for ML Training
NOSQL hardware appliance with multiple data structure
Hotchips 2013: Clovertrail+ Smartphone SoC platform
Real-time AI for Enterprise Workloads: the IBM Telum Processor
AnyCore-1: A comprehensively adaptive 4-way superscalar processor
Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra Acceleration
Programming the Nallatech Xeon + multi-FPGA heterogeneous platform
Mojo Lens - AR Contact Lenses for Real People
Nvidia Hopper GPU: Scaling Performance
Nvidia Grace
A 40-nm 13.88-TOPS/W FC-DNN Engine for 16-bit Intelligent Audio Processing Featuring Weight-Sharing and Approximate Computing
Wafer-Scale AI: GPU Impossible Performance
An IA-32 processor with a wide voltage operating range in 32nm CMOS
AMD Ryzen™ 6000 Series for Mobile : Technology Overview
Towards "True" GPU Performance Scaling for OpenGPU
PNX8535 hybrid television processor
AMD "kabini" APU SOC
Overview of the UC Berkeley Par Lab
Hybrid memory cube (HMC)
The road to 5G: Providing the connectivity fabric for everything
Piton: A 25-core academic manycore research processor
Sensor fusion mobile platform challenges and future directions
ACF-S: An 8-Terabit / Sec SuperNIC for High-Performance Data Movement in AI & Accelerated Compute Networks
AMD's next generation GPU and high bandwidth memory architecture: FURY
Arm Morello Evaluation Platform -Validating CHERI-based Security in a High-performance System
Clearwater Forest the Next Generation Intel ® Xeon ® Processor with Efficiency Cores
Silicon at the Heart of HoloLens 2
Clo-HDnn: Continual On-Device Learning Accelerator with Hyperdimensional Computing via Progressive Search
RISC-V-Based System-on-Chips for IoT Applications
Sun's 3rd generation on-chip UltraSPARC security accelerator
FABRIC8LABS Electrochemical Additive Manufacturing ECAM Enabled Thermal Solutions for the Al Data Center
Oracle's Sonoma processor: Advanced low-cost SPARC processor for enterprise workloads
SPARC64™ VIIIfx: Fujitsu's new generation octo core processor for PETA scale computing
OpenCL for NVIDIA GPUs
Arm Neoverse N2: Arm's 2 nd generation high performance infrastructure CPUs and system IPs
MLSoC ™ - An Overview
IMAPCAR2: A dynamic SIMD/MIMD mode switching processor for embedded systems
Touch-free technology
Cuzco: A High-Performance RISC-V RVA23 Compatible CPU IP
Task parallel programming model + hardware acceleration = performance advantage
IBM's Power11 Processor
Design of a reusable 1GHz, superscalar ARM processor
SambaNova SN10 RDU: Accelerating Software 2.0 with Dataflow
Fermi GF100 graphics processing unit (GPU)
The IBM power edge of Network™ processor: A wire-speed system-on-a-chip with 16 Power™ cores / 64 threads and optimized HW acceleration
RDNA™ 2 Gaming Architecture
OpenCL in handheld devices
A novel processor architecture for high-performance stream processing
The internet of everything
NVIDIA's Resource Transmutable Network Processing ASIC
The Intel® Xeon® processor E5 family architecture, power efficiency, and performance
DSPU: A 281.6mW Real-Time Deep Learning-Based Dense RGB-D Data Acquisition with Sensor Fusion and 3D Perception System-on-Chip
A silicon anti-virus engine
Flash in an enterprise storage array - 10x performance for less than disk
2012 IEEE Hot Chips 24 Symposium (HCS), Cupertino, CA, USA, August 27-29, 2012
Embedded deep neural networks: "The cost of everything and the value of nothing"
IBM zEC12 processor subsystem
SH-MobileG1: A single-chip application and dual-mode baseband processor
Lunar Lake Architecture Session
AMD Instinct ™ MI200 Series Accelerator and Node Architectures
Intel's Hyperscale-Ready Infrastructure Processing Unit (IPU)
Mars: A 64-core ARMv8 processor
PULP: A parallel ultra low power platform for next generation IoT applications
The world's fastest DSP core: Breaking the 100 GMAC/s barrier
An FPGA-based in-line accelerator for Memcached
Inside Tiger Lake: Intel's Next Generation Mobile Client CPU
Microsoft microsoft in the living room
Ultra low power FPGA fuels faster feature evolution in mobile applications
Hot Chips 2019
The Metric-aware Kernel-width Choice for LIME
ConformaSight: Conformal Prediction-Based Global and Model-Agnostic Explainability Framework
AutoXplain: Towards Automated Interpretable Model Selection
Democratizing Advanced Attribution Analyses of Generative Language Models with the Inseq Toolkit
Joint Proceedings of the xAI 2024 Late-breaking Work, Demos and Doctoral Consortium co-located with the 2nd World Conference on eXplainable Artificial Intelligence (xAI-2024), Valletta, Malta, July 17-19, 2024
Explainable AI as a Crucial Factor for Improving Human-AI Decision-Making Processes
Comprehensive Reinforcement Learning Explanations Using Queries
A Logic of Weighted Reasons for Explainable Inference in AI
Deep Clustering as a Unified Method for Representation Learning and Clustering of EEG Data for Microstate Theory
Towards Ensemble Explanation Strategies and Solving the Disagreement Problem in XAI
CountARFactuals - Generating Plausible Model-Agnostic Counterfactual Explanations with Adversarial Random Forests
Learning Interpretable Rules from Neural Networks: Neurosymbolic AI for Radar Hand Gesture Recognition
SRFAMap: A Method for Mapping Integrated Gradients of a CNN Trained with Statistical Radiomic Features to Medical Image Saliency Maps
Mediating Explainer for Human Autonomy Teaming
Dialogue-based XAI for Predictive Policing: a Field Study
Sanity Checks for Saliency Methods Explaining Object Detectors
Explainable Artificial Intelligence - Second World Conference, xAI 2024, Valletta, Malta, July 17-19, 2024, Proceedings, Part III
Benchmarking Trust: A Metric for Trustworthy Machine Learning
Speeding Things Up. Can Explainability Improve Human Learning?
Explaining AI Decisions: Towards Achieving Human-Centered Explainability in Smart Home Environments
Causal-Based Spatio-Temporal Graph Neural Networks for Industrial Internet of Things Multivariate Time Series Forecasting
An XAI-Based Analysis of Shortcut Learning in Neural Networks
Low-Impact Feature Reduction Regularization Term: How to Improve Artificial Intelligence with Explainability
Explainable Artificial Intelligence - First World Conference, xAI 2023, Lisbon, Portugal, July 26-28, 2023, Proceedings, Part III
Evaluation of Explainable AI methods for Classification Tasks in Visual Inspection
Designing an Evaluation Framework for eXplainable AI in the Healthcare Domain
How to Explain in XAI? - Investigating Explanation Protocols in Decision Support Systems
Precision Medicine for Student Health: Insights from Tsetlin Machines into Chronic Pain and Psychological Distress
Concept Distillation in Graph Neural Networks
Here Comes the Explanation: A Shapley Perspective on Multi-contrast Medical Image Segmentation
Interactive xAI-dashboard for Semantic Segmentation
Mitigating Text Toxicity with Counterfactual Generation
Explainable Fairness in Mortgage Lending
Global Interpretability for ProtoPNet Using Rule-Based Explanations
Safe and Efficient Social Navigation Through Explainable Safety Regions Based on Topological Features
Enhancing the analysis of the P300 event-related potential with integrated gradients on a convolutional neural network trained with superlets
Blockchain for Ethical and Transparent Generative AI Utilization by Banking and Finance Lawyers
Explainable Artificial Intelligence Beyond Feature Attributions: The Validity and Reliability of Feature Selection Explanations
Explainable Artificial Intelligence - Third World Conference, xAI 2025, Istanbul, Turkey, July 9-11, 2025, Proceedings, Part III
From Colors to Classes: Emergence of Concepts in Vision Transformers
A Guide to Feature Importance Methods for Scientific Inference
Interpretable Link Prediction via Neural-Symbolic Reasoning
Explainability, Quantified: Benchmarking XAI Techniques
Improving Counterfactual Truthfulness for Molecular Property Prediction Through Uncertainty Quantification
XInsight: Revealing Model Insights for GNNs with Flow-Based Explanations
Generating Rationales Based on Human Explanations for Constrained Optimization
Scalable Concept Extraction in Industry 4.0
Human-in-the-Loop Personalized Counterfactual Recourse
Explainable Automated Anomaly Recognition in Failure Analysis: is Deep Learning Doing it Correctly?
Explainable Emotion Decoding for Human and Computer Vision
User-Driven Counterfactual Generator: A Human Centered Exploration
Communicating Uncertainty in Machine Learning Explanations: A Visualization Analytics Approach for Predictive Process Monitoring
Interpretable Deepfake Voice Detection: A Hybrid Deep-Learning Model and Explanation Evaluation
Application of the Representative Measure Approach to Assess the Reliability of Decision Trees in Dealing with Unseen Vehicle Collision Data
Human-Computer Interaction and Explainability: Intersection and Terminology
The Importance of Distrust in AI
Shapley values and fairness
Explanations Considered Harmful: The Impact of Misleading Explanations on Accuracy in Hybrid Human-AI Decision Making
Faithful Attention Explainer: Verbalizing Decisions Based on Discriminative Features
A Study on the Faithfulness of Feature Attribution Explanations in Pruned Vision-Based Multi-Task Learning
Large Language Models as Attribution Regularizers for Efficient Model Training
Concepts Guide and Explain Diffusion Visual Counterfactuals
The Dynamics of Trust in XAI: Assessing Perceived and Demonstrated Trust Across Interaction Modes and Risk Treatments
Joint Proceedings of the xAI 2025 Late-breaking Work, Demos and Doctoral Consortium co-located with the 3rd World Conference on eXplainable Artificial Intelligence (xAI 2025), Istanbul, Turkey, July 9-11, 2025
Interpretable Vital Sign Forecasting with Model Agnostic Attention Maps
Human-in-the-loop testing of the explainability of robot navigation algorithms in extended reality
This Part Looks Alike This: Tdentifying Important Parts of Explained Instances and Prototypes
Explainable Artificial Intelligence - Third World Conference, xAI 2025, Istanbul, Turkey, July 9-11, 2025, Proceedings, Part II
PsyLingXAV: A Psycholinguistics Design Framework for XAI in Automated Vehicles
An Interpretable Data-Driven Approach for Modeling Toxic Users via Feature Extraction
Toward Inclusive Online Environments: Counterfactual-Inspired XAI for Detecting and Interpreting Hateful and Offensive Tweets
Explainable Artificial Intelligence - Second World Conference, xAI 2024, Valletta, Malta, July 17-19, 2024, Proceedings, Part IV
Assessing Reliability of Explanations in Unbalanced Datasets: a Use-case on the Occurrence of Frost Events
Knowledge Graphs for Empirical Concept Retrieval
A Nexus of Explainability and Anthropomorphism in AI-Chatbots
Explainable Artificial Intelligence - Second World Conference, xAI 2024, Valletta, Malta, July 17-19, 2024, Proceedings, Part II
Hardness of Deceptive Certificate Selection
XpertAI: Uncovering Regression Model Strategies for Sub-manifolds
Uncertainty Propagation in XAI: A Comparison of Analytical and Empirical Estimators
Investigating Calibrated Classification Scores Through the Lens of Interpretability
Understanding Interpretability: Explainable AI Approaches for Hate Speech Classifiers
Why Industry 5.0 Needs XAI 2.0?
Interpretable Neural System Dynamics: Combining Deep Learning with System Dynamics Modeling to Support Critical Applications
Use Bag-of-Patterns Approach to Explore Learned Behaviors of Reinforcement Learning
SignalGrad-CAM: Beyond Image Explanation
FCAS Ethical AI Demonstrator
Investigating Poor Performance Regions of Black Boxes: LIME-based Exploration in Sepsis Detection
A Human-in-the-Loop Approach to Learning Social Norms and Behavioural Policies
Explaining Black-Boxes in Federated Learning
Meta-evaluating Stability Measures: MAX-Sensitivity and AVG-Sensitivity
Explainable Artificial Intelligence - Third World Conference, xAI 2025, Istanbul, Turkey, July 9-11, 2025, Proceedings, Part IV
Predicting Satisfaction of Counterfactual Explanations from Human Ratings of Explanatory Qualities
mlr3summary: Concise and interpretable summaries for machine learning models
A Guided Tour of Post-hoc XAI Techniques in Image Segmentation
Strengthening of the Italian Research Infrastructure for Metrology and Open Access Data in support to the Agrifood (METROFOOD-IT)
Sub-SpaCE: Subsequence-Based Sparse Counterfactual Explanations for Time Series Classification Problems
Explainable Artificial Intelligence - First World Conference, xAI 2023, Lisbon, Portugal, July 26-28, 2023, Proceedings, Part II
Increasing Explainability in Time Series Classification by Functional Decomposition