yusuke1997/dblp-id-title huggingface dataset:
A 1.2V 200-MS/s 10-bit folding and interpolating ADC in 0.13-μm CMOS
100-MS/s 14-b track-and-hold amplifier in 0.18-μm CMOS
A 23pW, 780ppm/°C resistor-less current reference using subthreshold MOSFETs
FDDAC-based Transmitter with 2 GHz Modulation Bandwidth and 8 Gbit/s Data Rate
A 24-to-44 GHz Compact Linear 5G Power Amplifier with Open-Terminated Balun in 65nm Bulk CMOS
A 1.8-V 12-bit 250-MS/s 25-mW self-calibrated DAC
Antenna and input stages of a 470-710 MHz silicon TV tuner for portable applications
A cyclic A/D converter with pixel noise and column-wise offset canceling for CMOS image sensors
A low-voltage fully-monolithic ΔΣ-based class-D audio amplifier
All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter
FDSOI: From substrate to devices and circuit applications
A 3-12.5 Gb/s Reference-Less CDR for an Eye-Opening Monitor
A 12b 180MS/s 0.068mm 2 pipelined-SAR ADC with merged-residue DAC for noise reduction
A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link
An 80-MHz 0.4V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation
A low-cost and low-power single-chip DAB+/DAB/FM receiver
A monolithically-integrated optical receiver in standard 45-nm SOI
A 12-bit, 30-MS/s, 2.95-mW pipelined ADC using single-stage class-AB amplifiers and deterministic background calibration
An integrated inductive VR with a 250MHz all-digital multisampled compensator and on-chip auto-tuning of coefficients in 130nm CMOS
A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 up to 1GHz Using Constant-Activity Element Switching
A 0.13µm CMOS 0.1-20MHz bandwidth 86-70dB DR multi-mode DT ΔΣ ADC for IMT-Advanced
Reduction of VCO phase noise through forward substrate biasing of switched MOSFETs
A chopped Hall sensor with programmable "true power-on" function
4-Mb MOSFET-selected phase-change memory experimental chip
An integrated optical receiver with wide-range timing discrimination characteristics
A 200GHz downconverter in 90nm CMOS
Multi-Gate FD-SOI Single Electron Transistor for hybrid SET-MOSFET quantum computing
A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator
Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node
A real-time image recognition system using a global directional-edge-feature extraction VLSI processor
An 85-mV input, 50-µs startup fully integrated voltage multiplier with passive clock boost using on-chip transformers for energy harvesting
An all-digital A/D converter TAD with 4-shift-clock construction for sensor interface in 0.65-μm CMOS
Low power UWB pulse radio transceiver front-end
Multi-Code Multi-Rate Universal Maximum Likelihood Decoder using GRAND
A 78 pW 1 b/s 2.4 GHz radio transmitter for near-zero-power sensing applications
A 110µW single bit audio continuous-time oversampled converter with 92.5 db dynamic range
A 0.47-1.6mW 5bit 0.5-1GS/s time-interleaved SAR ADC for low-power UWB radios
A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities
Current status on GaN-based RF-power devices
A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC
Suppression of VCO pulling effects using even-harmonic quiet transmitting circuits
Efficiency enhanced Single-Inductor Boost-Inverting Flyback converter with Dual Hybrid Energy transfer media and a Bifurcation Free Comparator
A 30-MHz, 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop
A Wireless Multimodal Physiological Monitoring ASIC for Injectable Implants
A 0.5V 20fJ/conversion-step rail-to-rail SAR ADC with programmable time-delayed control units for low-power biomedical application
A 50V high-speed level shifter with high dv/dt immunity for multi-MHz DCDC converters
60GHz quadrature doppler radar transceiver in a 0.25μm SiGe BiCMOS technology
On ambient intelligence, needful things and process technologies
A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS
An eddy-current displacement-to-digital converter based on a ratio-metric delta-sigma ADC
iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS
A 0.1 MHz to 200 MHz high-voltage CMOS transceiver for portable NMR systems with a maximum output current of 2.0 App
A 94.3-dB SFDR, 91.5-dB DR, and 200-kS/s CT Incremental Delta-Sigma Modulator With Differentially Reset FIR Feedback
Hybrid buck-linear (HBL) technique for enhanced dip voltage and transient response in load-preparation buck (LPB) converter
A 9.6 GS/s 112 mW 58 dB DR 150 MHz bandwidth RF bandpass transmission line ΣΔ modulator
A K-band Gilbert-Cell Frequency Doubler with Self-Adjusted 25% LO Duty-Cycle in SiGe BiCMOS Technology
A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os
Complex IF harmonic rejection mixer for non-contiguous dual carrier reception in 65 nm CMOS
A 135 GHz 24 Gb/s Direct-Digital Demodulation 16-QAM Receiver in 28 nm CMOS
Third-order ΣΔ modulator with 61-dB SNR and 6-MHz bandwidth consuming 6 mW
A 0.0106 mm 2 8nW Resistor-Less BJT Bandgap Reference in 65nm
Minimizing inductive noise in system-on-a-chip with multiple power gating structures
Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR
A 3-10 GHz flexible CMOS LO generator for MB-OFDM UWB application using wide tunable VCOs
A 1.2V receiver front-end for multi-standard wireless applications in 65 nm CMOS LP
A 2.2 fA/√Hz, 120 dB Dynamic Range, 12 GΩ Hybrid Readout Interface for Various Ionic Spectroscopy Applications
Intelligent task scheduler with high throughput NoC for real-time mobile object recognition SoC
Oxide electronics for imaging and displays
An 8Gbps 2.5mW on-chip pulsed-current-mode transmission line interconnect with a stacked-switch Tx
A 0.1-mm 2 3-channel area-optimized ΣΔ ADC in 0.16-µm CMOS with 20-kHz BW and 86-dB DR
A 900 MHz RF energy harvesting system in 40 nm CMOS technology with efficiency peaking at 47% and higher than 30% over a 22dB wide input power range
A fully integrated 74% efficiency 3.6V to 1.5V 150mW capacitive point-of-load DC/DC-converter
A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter
A 6-bit 6-GS/s 95mW background calibrated flash ADC with integrating preamplifiers and half-rate comparators in 32nm LP CMOS
A 13.2fJ/step 74.3-dB SNDR Pipelined Noise-shaping SAR+VCO ADC
Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET
The sense amplifier common mode effect on a switching current-mode power staged based on sigma-delta modulation
A 491.52 MHz 840 uW crystal oscillator in 28 nm FD-SOI CMOS for 5G applications
2.6 Gb/s over a four-drop bus using an adaptive 12-tap DFE
A 6.5 GHz Arbitrary Digital Waveform Generator
Digital associative memory for word-parrallel Manhattan-distance-based vector quantization
Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies
Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS technologies
Design and phase noise analysis of a multiphase 6 to 11 GHz PLL
Improving DPA security by using globally-asynchronous locally-synchronous systems
A low noise, high gain, highly linear mixer for 77 GHz automotive radar applications in SiGe: C bipolar technology
CMOS unclonable system for secure authentication based on device variability
A low-jitter 1.5-GHz and 350-ppm spread-spectrum serial ATA PHY using reference clock with 400-ppm production-frequency tolerance
30% static power improvement on ARM Cortex ® -A53 using static biasing-anticipation
A 50-Gb/s Quarter-Rate Voltage-Mode Transmitter with Three-Tap FFE in 40-nm CMOS
Offset calibrating comparator array for 1.2-V, 6bit, 4-Gsample/s flash ADCs using 0.13μm generic CMOS technology
A 28nm 6.5-8.1GHz 1.16mW/qubit Cryo-CMOS System-an-Chip for Superconducting Qubit Readout
High temperature analog circuit design in PD-SOI CMOS technology using reverse body biasing
A low-power compact IEEE 802.15.6 compatible human body communication transceiver with digital sigma-delta IIR mask shaping
A precision high voltage wave-shaper for multi-Gbit source side injection MLC NOR flash memory
Performance, reliability, radiation effects, and aging issues in microelectronics - from atomic-scale physics to engineering-level modeling
A Multi-Overloading-Factor Sparse Code Multiple Access Decoder for 5G Communications
A sub 10 pJ/Cycle Over a 2 to 200 MHz Performance Range RISC- V Microprocessor in 28 nm FDSOI
A 93.1-dB SFDR, 90.3-dB DR, and 1-MS/s CT Incremental Sigma-Delta Modulator Incorporating a Resistive Dual-RTZ FIR DAC
An energy-scalable accelerator for blind image deblurring
A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic
Direct-Conversion I-Q Transmitter Front-End for 180 GHz with 80 GHz Bandwidth in 130 nm SiGe
A 28-GHz CMOS Broadband Single-Path Power Amplifier with 17.4-dBm P1dB for 5G Phased-Array
A power amplifier driver using self-oscillating pulse-width modulators
A highly accurate spike sorting processor with reconfigurable embedded frames for unsupervised and adaptive analysis of neural signals
Photonics - Electronics integration on CMOS
From Less Batteries to Battery-Less: Enabling A Greener World through Ultra-Wide Power-Performance Adaptation down to pWs
A 0.11mm 2 164dB-FOM 0.18μm CMOS pipelined ADC with novel passive amplification
ESSCIRC Conference 2016: 42 nd European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016
Autonomous Vehicles Sensor Needs
A neural recorder IC with HV input multiplexer for voltage and current stimulation with 18V compliance
A 1.2V 62.2dB SNDR SAR-Assisted Event-Driven Clockless Level-Crossing ADC for Time-Sparse Signal Acquisition
Current reference scheme for multilevel phase-change memory sensing
A 4.1 pJ/b 25.6 Gb/s 4-PAM reduced-state sliding-block Viterbi detector in 14 nm CMOS
Configurable Energy-Efficient Lattice-Based Post-Quantum Cryptography Processor for IoT Devices
A 1.8-V wide-band CMOS LNA for multiband multistandard front-end receiver
Super-regenerative UWB impulse detector with synchronized quenching mechanism
A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% -1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio
A Low Power, 3.5-20GHz Tunable LNA with Out-Of-Band Blocker Filtering Based on Compact, Tunable Transmission Line (CTTL) Resonators in 65nm CMOS
10 Gb/s single-ended laser driver in 0.35μm SiGe BiCMOS technology
A 5.0mW 0dBm FSK transmitter for 315/433 MHz ISM applications in 0.25 μm CMOS
A 1.2-0.55V general-purpose biomedical processor with configurable machine-learning accelerators for high-order, patient-adaptive monitoring
A 54-64.8 GHz subharmonically injection-locked frequency synthesizer with transmitter EVM between -26.5 dB and -28.8 dB in 28 nm CMOS
A 5mW multi-standard Bluetooth LE/IEEE 802.15.6 SoC for WBAN applications
A linearity improvement technique for overcoming signal-dependent induced switching time mismatch in DAC-Based transmitters
Overview of 5G requirements and future wireless networks
Low voltage and low power aspects of data converter design
A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, With Fast Locking and Low Power Characteristics
A 0.02-mm2 9-bit 100-MS/s Charge-Injection Cell Based SAR-ADC in 65-nm LP CMOS
FDSOI Circuit Design for High Energy Efficiency: Wide Operating Range and ULP Applications - a 7-Year Experience
Spectral PLL built-in self-test for integrated cellular transceivers
Digital communication systems: the problem of analog interface circuits
A 40µW CMOS temperature sensor with an inaccuracy of ±0.4°C (3σ) from -55°C to 200°C
A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training
A 24V Thin-Film Ultrasonic Driver for Haptic Feedback in Metal-Oxide Thin-Film Technology using Hybrid DLL Locking Architecture
Adaptive frequency control technique for enhancing transient performance of DC-DC converters
Compute-MLROM: Compute-in-Multi Level Read Only Memory for Energy Efficient Edge AI Inference Engines
44th IEEE European Solid State Circuits Conference, ESSCIRC 2018, Dresden, Germany, September 3-6, 2018
A digital fractional-N PLL with a 3mW 0.004mm 2 6-bit PVT and mismatch insensitive TDC
A Chopper Biopotential Instrumentation Amplifier With DSL-Embedded Input Stage Achieving 109 dB CMRR and 400 mV DC Offset Tolerance
Integrated sensor for light source position measurement applicable in SOI technology
High speed, high accuracy fractional-N frequency synthesizer using nested mixed-radix digital Δ-Σ modulators
A 55-70GHz two-stage tunable polyphase filter with feedback control for quadrature generation with <2° and <0.32dB phase/amplitude imbalance in 28nm CMOS process
A Cellular Multiband DTC-Based Digital Polar Transmitter With -153 dBc/Hz Noise in 14-nm FinFET
A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS
Pulsed time-of-flight 3D-CMOS imaging using photogate-based active pixel sensors
A <25 μW CMOS monolithic photoplethysmographic sensor with distributed 1b delta-sigma light-to-digital convertor
A 6.4mW, 1-3.5GHz current-mode receiver front-end with noise cancellation
Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept
A 10-core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing over a Wide Voltage and Temperature Range
Gb/s CDR circuit for large synchronous networks
High performance pipelining method for static circuits using heterogeneous pipelining elements
A low-power wide-band digital frequency synthesizer for cognitive radio sensor units
A 12b 320 MSample/s current-steering CMOS D/A converter in 0.44mm 2
High efficiency multi-mode outphasing RF power amplifier in 45nm CMOS
An automatic frequency calibration technique for fractional-N frequency synthesizers
A 3-V, 6-bit C-2C digital-to-analog converter using complementary organic thin-film transistors on glass
A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation
2-Mb Embedded Phase Change Memory With 16-ns Read Access Time and 5-Mb/s Write Throughput in 90-nm BCD Technology for Automotive Applications
On-chip jitter and oscilloscope circuits using an asynchronous sample clock
Model and verification of triple-well shielding on substrate noise in mixed-signal CMOS ICs
A 55fJ/conv-step hybrid SAR-VCO ΔΣ capacitance-to-digital converter in 40nm CMOS
LC-oscillators above 100 GHz in silicon-based technology
A Self-Adaptive 4 th -Order Filter Based on Tunable N-Path Filters
A 45nm single power supply SRAM supporting low voltage operation down to 0.6V
A Highly Integrated Crosspoint Array Using Self-rectifying FTJ for Dual-mode Operations: CAM and PUF
Silicon bipolar circuits for wideband FM CATV transmission
Reconfigurable Intelligent Surfaces Enabled by Silicon Chips for Secure and Robust mmWave and THz Wireless Communication
A 3-channel true-time delay transmitter for 60GHz radar-beamforming applications
A dual vertical Hall latch with direction detection
A 9 pW/Hz adjustable clock generator with 3-decade tuning range for dynamic power management in subthreshold SCL systems
A 256-kb Fully Row/Column-parallel 22nm MRAM In-Memory-Computing Macro with Differential Readout for Robust Parallelization and Scale-up
A flexible, ultra-low power 35pJ/pulse digital back-end for a QAC UWB receiver
L1/L2 dual-band CMOS GPS receiver
A 12-48 V wide-vin 9-15 MHz soft-switching controlled resonant DCDC converter
A ratiometric readout circuit for thermal-conductivity-based resistive gas sensors
A 50V, 1.45ns, 4.1pJ High-Speed Low-Power Level Shifter for High-Voltage DCDC Converters
Development of high sensitivity CMOS-MEMS inertia sensor and its application to early-stage diagnosis of Parkinson's disease
FD-SOI Enabled mmWave Telecommunication Applications and System Architectures
A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS
Area and latency optimized high-throughput Min-Sum based LDPC decoder architectures
An 800-mA Time-Based Boost Converter in 0.18µm BCD with Right-Half-Plane Zero Elimination and 96% Power Efficiency
Simpler, more efficient design
A 64GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOS
A 28nm FDSOI integrated reconfigurable switched-capacitor based step-up DC-DC converter with 88% peak efficiency
High precision optical angle measuring method applicable in standard CMOS technology
6GS/s 8-channel CIC SAR TI-ADC with Neural Network Calibration
A Highly Efficient Combo Transceiver for 802.11b/g/n/ax and BT/BLE in 22nm CMOS
RF spectrum sensing technique for cognitive UWB radio network
Analog design trends and challenges in 28 and 20nm CMOS technology
Transistor operation and circuit performance in organic electronics
A Cryogenic Active Router for Qubit Array Biasing from DC to 320 MHz at 100 nm Gate Pitch
The Switched-Capacitor Power Amplifier: A Key Enabler for Future Communications Systems
A PAM4 Dielectric Waveguide Link in 28 nm CMOS
A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS
A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs
A monolithic 0.77W/mm 2 power dense capacitive DC-DC step-down converter in 90nm Bulk CMOS
Assessment of the merits of CMOS technology scaling for analog circuit design
Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting
An Integrated Optical Transceiver Circuit for Power Delivery and Bi-directional Data Communication in a Medical Catheter Device
An 8T SRAM with BTI-Aware Stability Monitor and two-phase write operation for cell stability improvement in 28-nm FDSOI
A 28-GHz Switched-Filter Phase Shifter with Fine Phase-Tuning Capability Using Back-Gate Biasing in 22-nm FD-SOI CMOS
Analysis of low noise three-phase asynchronous data transmission
Low-power SAR ADCs: trends, examples and future
A 36V voltage-to-current converter with dynamic element matching and auto-calibration for AC ripple reduction
A 13-16 GHz Low-Noise Oscillator with Enhanced Tank Energy in 22-nm FDSOI
A 8mW-RX/113mW-TX, Sub-GHz SoC with time-dithered PA ramping for LPWAN applications
A dual-band enhanced harmonic rejection filter for modulators in GSM and DCS transmitters
94.6% peak efficiency DCM buck converter with fast adaptive dead-time control
A 0.18-µm CMOS 1.25-Gbps front-end receiver for low-cost short reach optical communications
A Benchmark of Cryo-CMOS 40-nm Embedded SRAM/DRAMs for Quantum Computing
A 2 GHz 3.1 mW type-I digital ring-based PLL
A 3.2-GHz 1.3-mW ILO phase rotator for burst-mode mobile memory I/O in 28-nm low-leakage CMOS
A 13.56/402 MHz autonomous wireless sensor node with -18.2 dBm sensitivity and temperature monitoring in 0.18 /im CMOS
A Periodically Time-Varying Inductor Applied to The Class-D VCO for Phase Noise Improvement
Variable gain amplifier in polar loop modulation transmitter for EDGE
Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS
Thermoelectric energy harvesting with 1mV low input voltage and 390nA quiescent current for 99.6% maximum power point tracking
A 6bit, 1.2GSps low-power flash-ADC in 0.13μm digital CMOS
The Monte Carlo approach to transport modeling in deca-nanometer MOSFETs
A low power highly linear 2.4 GHz CMOS receiver front-end using current amplifier
A 2.6mm 2 0.19nJ/pixel VP9 and multi-standard decoder LSI for Android 4K TV applications
A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS
Proceedings of the 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, Sept. 12-16, 2011
Notice of Violation of IEEE Publication PrinciplesA 10GHz SiGe OC192 frequency synthesizer using a passive feed-forward loop filter and a half rate oscillator
Offset and dynamic gain-mismatch reduction techniques for 10b 200ms/s parallel pipeline ADCs
A low-noise differential front-end and its controller for capacitive touch screen panels
A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC ΣΔ modulator in 1.2-V 90-nm CMOS
A frequency-selective nested dual-loop broadband low-noise amplifier in 90 nm CMOS
A 0.98-nW/kHz 33-kHz Fully Integrated Subthreshold-Region Operation RC Oscillator With Forward-Body-Biasing
A high-swing complementary class-C VCO
A Low Power Bluetooth Low-Energy Transmitter with a 10.5nJ Startup-Energy Crystal Oscillator
Operating-margin-improved SRAM with column-at-a-time body-bias control technique
A fully integrated Class-D amplifier in 40nm CMOS with dynamic cascode bias and load current sensing
A compact, low-power low-jitter digital PLL
A fast response integrated current-sensing circuit for peak-current-mode buck regulator
Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005
A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR
248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting
Presentation "Automotive electronics and energy efficiency"
On the Noise Contribution of Dielectric Interfaces in Biochemical CMOS Sensor Chips
A novel hierarchical multi-port cache
A 36V 48MHz JFET-Input Bipolar Operational Amplifier with 150µV Maximum Offset and Overload Supply Current Control
Approximate 32-bit floating-point unit design with 53% power-area product reduction
Electrical measurement of alignment for 3D stacked chips
The Future of Short Reach Interconnect
A 125 pJ/hit 5 mW 28 GHz Superregenerative Receiver with Automatic Gain Control and Energy Efficient Startup for Burst Mode IoE Applications
A 4.27TFLOPS/W FP4/FP8 Hybrid-Precision Neural Network Training Processor Using Shift-Add MAC and Reconfigurable PE Array
A CMOS-based tactile sensor for continuous blood pressure monitoring
A high energy-efficiency SAR ADC based on partial floating capacitor switching technique
Exploiting FDSOI Towards Minimum Energy Point Operation in Processors and Machine Learning Accelerators
A 13.2-dBm, 138-GHz I/Q RF-DAC with 64-QAM and OFDM free-space constellation formation
A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits
An easily extendable FFT based four-channel, four-beam receiver with progressive partial spatial filtering in 65nm
An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H
A 19.2GOPS, 20mW adaptive FIR filter
Low voltage error resilient SRAM using run-time error detection and correction
A 650 V, 3 A three-phase fully-integrated BLDC motor driver with charge pump and level shifters
Suppressing start-up time variation versus load current - Adaptive soft-start in boost LED drivers
A 10Gb/s NRZ receiver with feedforward equalizer and glitch-free phase-frequency detector
Single chip, low supply voltage piezoelectric transformer controller
Design considerations for 50G+ backplane links
Design of low noise CMOS OEIC for blu-ray disc optical storage systems
A 470µW -92.5dBm OOK/FSK Receiver for IEEE 802.11 WiFi LP-WUR
3D Integration technology: Status and application development
A multi-frequency bioimpedance measurement ASIC for electrical impedance tomography
A Compact 2.5-nJ Energy/Conversion NPN-Based Temperature-to-Digital Converter with a Fully Current-Mode Processing Architecture
Power efficient 4.5Gbit/s optical receiver in 130nm CMOS with integrated photodiode
A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration
A 91.6% Peak Efficiency Time-Domain-Controlled Single-Inductor Triple-Output Step-Up Converter with ±7.5 to ±12V Bipolar Output Voltages
A 183F 2 Gate Leakage-Based Physically Unclonable Function With Area Efficient Current Tilting-Based Masking Scheme