yusuke1997/dblp-id-title huggingface dataset:
Evaluation of Digital Volunteers using a Design Approach: Motivations and Contributions in Disaster Response
Interaction design for web emergency management information systems
Taxonomy of post-impact volunteerism types to improve citizen integration into crisis response
Restoring the Medical Supply Chain from Below: The Role of Social Entrepreneurship in the Production of Face Masks during the Covid-19 Crisis
Effect of Daytime on the Efficiency of Population Alerts via Short Messages and E-Mails
Testing a motion estimator array
Binary Multiplication based on Single Electron Tunneling
Data-flow Aware CNN Accelerator with Hybrid Wireless Interconnection
Implementing 1, 024-Bit RSA Exponentiation on a 32-Bit Processor Core
Toward a fast stochastic simulation processor for biochemical reaction networks
On-line Decimal Adder with RBCD Representation
The missing dimension in real-time signal processing architectures
Hardware Compilation of Deep Neural Networks: An Overview
GPU-based multifrontal optimizing method in sparse Cholesky factorization
The International Conference on Application Specific Array Processors (ASAP'95), July 24-26, 1995, Strasbourg, France
Energy-efficient gear-shift LDPC decoders
A Dynamic Allocation Scheme for Adaptive Shared-Memory Mapping on Kilo-Core RV Clusters for Attention-Based Model Deployment
A MPSoC cache design space exploration approach based on ABC algorithm to optimize energy consumption and performance
Low-power polygon renderer for computer graphics
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
A simple array processor for binary prefix sums
FPGA Architectures for Real-time Dense SLAM
Design space exploration and constrained multiobjective optimization for digital predistortion systems
21st IEEE International Conference on Application-specific Systems Architectures and Processors, ASAP 2010, Rennes, France, 7-9 July 2010
High-Performance Front-End Embedded Signal Processors for Adaptive Sensor Arrays
Rapid Prototyping of Reconfigurable Coprocessors
Acceleration of video stabilization using embedded GPU
Nanotechnology in the Development of Future Computing Systems
Novel Application of Genetic Sequencing Algorithms to Optimization of Hardware Resource Sharing for DSP
Mapping multirate dataflow to complex RT level hardware models
Parallel implementations of discrete relaxation technique on fixed size processor arrays
PAPA - Packed Arithmetic on a Prefix Adder for Multimedia Applications
A flexible VLSI architecture for variable block size segment matching with luminance correction
Side-channel aware design: Algorithms and Architectures for Elliptic Curve Cryptography over GF(2 n )
Reconfigurable Motion Estimation Architecture for Multi-standard Video Compression
Parallel strong orientation on a mesh connected computer
Standard deviation of CPI: A new metric to evaluate architectural time predictability
Multi-rate transformation of directional affine recurrence equations
Compressive Sensing on Storage Data: An Effective Solution to Alleviate I/0 Bottleneck in Data- Intensive Workloads
On partitioning of multistage algorithms and design of intermediate memories
An efficient architecture for the in place fast cosine transform
ISP2DLA: Automated Deep Learning Accelerator Design for On-Sensor Image Signal Processing
Optical Network Reconfiguration for Signal Processing Applications
ARREST: an interactive graphic analysis tool for VLSI arrays
Low-precision logarithmic arithmetic for neural network accelerators
Low-cost hardware profiling of run-time and energy in FPGA embedded processors
15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), 27-29 September 2004, Galveston, TX, USA
A processor for calorimetry at the Large Hadron Collider in the FERMI project
A CORBA-Based GIS-T for Ambulance Assignment
Tiling with limited resources
CGRA-ME: A unified framework for CGRA modelling and exploration
A LLC-Friendly LSM-tree
Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs
Reconfigurable Design Automation by High-Level Exploration
An improved systolic extended Euclidean algorithm for Reed-Solomon decoding: design and implementation
Complex Division with Prescaling of Operands
A low-power Content-Addressable Memory based on clustered-sparse networks
Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis
A Phase-Coupled Compiler Backend for a New VLIW Processor Architecture Using Two-step Register Allocation
Customizable coarse-grained energy-efficient reconfigurable packet processing architecture
Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort
Three-dimensional orthogonal tile sizing problem: mathematical programming approach
A decimal floating-point fused multiply-add unit with a novel decimal leading-zero anticipator
Understanding Performance Gains of Accelerator-Rich Architectures
A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architectures
Trimming Down Large Spiking Vision Transformers Via Heterogeneous Quantization Search
Biosequence Similarity Search on the Mercury System
Anytime Floating-Point Addition and Multiplication-Concepts and Implementations
Instruction Set Extensions for Reed-Solomon Encoding and Decoding
NEMO-CNN: An Efficient Near-Memory Accelerator for Convolutional Neural Networks
An FPGA architecture for solving the Table Maker's Dilemma
Design of run-time fault-tolerant arrays of self-checking processing elements
A Hierarchical Classification Scheme to Derive Interprocess Communication in Process Networks
Fused floating-point two-term sum-of-squares unit
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
Extending the RISC-V Instruction Set for High Performance Data Compression Hardware Acceleration
Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS
Deadlock-avoidance for streaming applications with split-join structure: Two case studies
Fooling AI with AI: An Accelerator for Adversarial Attacks on Deep Learning Visual Classification
Bridging the FPGA programmability-portability Gap via automatic OpenCL code generation and tuning
General-purpose FPGA platform for efficient encryption and hashing
A Parallel Automaton String Matching with Pre-Hashing and Root-Indexing Techniques for Content Filtering Coprocessor
Power optimization of sum-of-products design for signal processing applications
A Novel Ring-based Small-World NoC for Neuromorphic Processor
Pipelined Range Reduction for Floating Point Numbers
A Common Architecture For The DWT and IDWT
Three Computationally Demanding Problems in Search of ASAP Solutions
Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutiosnal Neural Networks
A Modular Element for Shared Buffer ATM Switch Fabrics
Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications
VLSI Algorithms for Compressed Pattern Search Using Tree Based Codes
Mayalok: A Cyber-Deception Hardware Using Runtime Instruction Infusion
Virtual finite-state-machine architectures for fast compilation and portability
Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformations
Design methodology for digital signal processing
Accelerating data centers with reconfigurable logic
Wireless health: Challenges and opportunities
A System for Generating Non-Uniform Random Variates using Graphene Field-Effect Transistors
Mask-Net: A Hardware-efficient Object Detection Network with Masked Region Proposals
PRDSE: A Prior-Driven Design Space Exploration Method
Design and comparative evaluation of GPGPU- and FPGA-based MPSoC ECU architectures for secure, dependable, and real-time automotive CPS
FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers
Variable Radix Real and Complex Digit-Recurrence Division
WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs
An Abstract Model for a Low Cost SIMD Architecture
Robust Adders Based on Quantum-Dot Cellular Automata
On Computing With Locally-Interconnected Architectures in Atomic/Nanoelectronic Systems
A systolic array chip for robot inverse dynamics computation
Ahead of Time Generation for GPSA Protection in RISC-V Embedded Cores
Implementation of systolic algorithms using pipelined functional units
The Arithmetic Cube: error analysis and simulation
A Heterogeneous Computer Architecture Accelerating Reinforcement Learning-based Design for Silicon Photonic Devices
A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applications
Correctly rounded architectures for Floating-Point multi-operand addition and dot-product computation
Exploring Design Space of VLIW Architectures
Instruction set extension for high throughput disparity estimation in stereo image processing
Design Space Exploration for Memory-Oriented Approximate Computing Techniques
GPU Acceleration of Multi-Object Tracking with Motion Vector Interpolation and Affine Transformation
Distributed synchronization for message-passing based embedded multiprocessors
MultiExplorer: A tool set for multicore system-on-chip design exploration
A pipelined camellia architecture for compact hardware implementation
Storage Management in Process Networks using the Lexicographically Maximal Preimage
Parallel architectures for computing the Hough transform and CT image reconstruction
Improved Side-Channel Resistance by Dynamic Fault-Injection Countermeasures
A parallel DSP-based neural network emulator with CMOS VLSI packet switching hardware
A Novel Processor Architecture for McEliece Cryptosystem and FPGA Platforms
Reconfigurable vector register windows for fast matrix computation on the orthogonal multiprocessor
Decimal Multiplication Via Carry-Save Addition
Quality-aware video decoding on thermally-constrained MPSoC platforms
Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study
Predictable Instruction Caching for Media Processors
Digit-serial DSP architectures
An FPGA-based real-time nonuniformity correction system for Infrared Focal Plane Arrays
Multi-Level Prototyping of a Vertical Vector AI Processing System
A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
Efficient Implementation of Carry-Save Adders in FPGAs
Hardware-assisted middleware: Acceleration of garbage collection operations
Realization of a real time phasecorrelation chipset used in a hierarchical two step HDTV motion vector estimator
Investigating the Feasibility of FPGA-based Network Switches
Design Space Exploration for Orlando Ultra Low-Power Convolutional Neural Network SoC
A CAD tool for electromagnetic simulation on the associative string processor
New non-uniform segmentation technique for software function evaluation
Data alignment of loop nests without nonlocal communications
Secure Communication Protocol for Network-on-Chip with Authenticated Encryption and Recovery Mechanism
Five-point algorithm: An efficient cloud-based FPGA implementation
COLUMNUS - An SIMD architecture for pattern recognition and simulations of statistical physics
Hierarchical scheduling of DSP programs onto multiprocessors for maximum throughput
Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study
CORDIC Architectures with Parallel Compensation of the Scale Factor
A systolic array for nonlinear adaptive filtering and pattern recognition
An efficient architecture solution for low-power real-time background subtraction
Architectural Support on Object-Oriented Programming in a JAVA Processor
A DRL-Based Multi-Priority Task Division Scheduling Strategy in IIoT
Managing multi-core soft-error reliability through utility-driven cross domain optimization
Distributed control synthesis for data-dependent iterative algorithms
Scheduling affine parameterized recurrences by means of Variable Dependent Timing Functions
Parallel algorithm for traveling salesman problem on SIMD machines using simulated annealing
Automatic generation of polynomial-based hardware architectures for function evaluation
35th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2024, Hong Kong, July 24-26, 2024
Mapping and Topology Customization Approaches for Application-Specific STNoC Designs
GENES IV: A bit-serial processing element for a built-model neural-network accelerator
A period-processor-time-minimal schedule for cubical mesh algorithms
Low Power CORDIC Implementation Using Redundant Number Representation
Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking
Mapping Parallel FFT Algorithm onto SmartCell Coarse-Grained Reconfigurable Architecture
Longest Prefix Match and updates in Range Tries
Efficient Weight Reuse for Large LSTMs
Static Communication Scheduling for Minimizing Collisions in Application Specific Parallel Systems
Energy Aware Register File Implementation through Instruction Predecode
Architecture for Wavelet Packet Transform with Best Tree Searching
An area-Efficient LDPC decoder for multi-standard with conflict resolution
Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture
33rd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2022, Gothenburg, Sweden, July 12-14, 2022
An efficient & reconfigurable FPGA and ASIC implementation of a spectral Doppler ultrasound imaging system
Mapping FIR filtering on systolic rings
External Referees
KV-FTL: A novel key-value based FTL scheme for large scale SSDs
DeltaNet: Differential Binary Neural Network
A GPU-based correlator X-engine implemented on the CHIME Pathfinder
32nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2021, Virtual Conference, USA, July 7-9, 2021
High Performance Parallel JPEG2000 Streaming Decoder Using GPGPU-CPU Heterogeneous System
Efficient Group KeyManagement with Tamper-resistant ISA Extensions
PART: a partitioning tool for efficient use of distributed systems
Noxim: An open, extensible and cycle-accurate network on chip simulator
Pipelined modular multiplier supporting multiple standard prime fields
Parallel digital implementations of neural networks
Design Space Exploration for Softmax Implementations
Virtual science on the move: Interactive access to simulations on supercomputers
Real-time object detection in software with custom vector instructions and algorithm changes
GAP-8: A RISC-V SoC for AI at the Edge of the IoT
Array Placement for Storage Size Reduction in Embedded Multimedia Systems
A Rapid Prototyping Platform for Wireless Medium Access Control Protocols
A 108 Gbps, 1.5 GHz 1D-DCT Architecture
A Combined Interval and Floating-Point Comparator/Selector
Design and implementation of adaptive signal processing systems using Markov decision processes
Multilayer Cellular Algorithm for Complex Number Multiplication
Variable-Length Instruction Compression for Area Minimization
OCP: Offload Co-Processor for energy efficiency in embedded mobile systems
A Framework for Generating Accelerators for Homomorphic Encryption Operations on FPGAs
Energy efficient deeply fused dot-product multiplication architecture
Supporting RISC-V Performance Counters Through Linux Performance Analysis Tools
Using Residue Number Systems to Accelerate Deterministic Bit-stream Multiplication
Reconfigurable Shuffle Network Design in LDPC Decoders
Application-specific processors for web-browsing: An exploration and evaluation of the design space
Reconfiguration of FFT arrays: a flow-driven approach
Specialization of the Cell SPE for Media Applications
Error Analysis of the Square Root Operation for the Purpose of Precision Tuning: A Case Study on K-means
End-to-end Dynamic Stream Processing on Maxeler HLS Platforms
A fast, storage-efficient parallel sorting algorithm
A Performance Model for Memory Bandwidth Constrained Applications on Graphics Engines
An FPGA-Based Application-Specific Processor for Efficient Reduction of Multiple Variable-Length Floating-Point Data Sets
Understanding the design space of DRAM-optimized hardware FFT accelerators
Design of a 2D graphics front-end rendering processor
CASPER: An Integrated Energy-Driven Approach for Task Graph Scheduling on Distributed Embedded Systems
Design and implementation of a surface peak thermal detector algorithm
An efficient digital circuit for implementing Sequence Alignment algorithm in an extended processor
Custom FPGA-based soft-processors for sparse graph acceleration
A wave digital filter three-port adaptor with fine grained pipelining
FAWS: FPGA Acceleration of Large-Scale Wave Simulations
Bit matrix multiplication in commodity processors
Towards the automated design of application specific array processors (ASAPs)
A lightweight ISE for ChaCha on RISC-V
A design methodology for fixed-size systolic arrays
Generic Tool-Set for SoC Mulitiprocessor Debugging and Synchronization
Low-Cost Elliptic Curve Digital Signature Coprocessor for Smart Cards
Temporal Motionless Analysis of Video using CNN in MPSoC
A Simple Central Processing Unit with Multi-Dimensional Logarithmic Number System Extensions
A Scalable Halftoning Coprocessor Architecture
An Efficient Accelerator for Nonlinear Model Predictive Control
Stride Permutation Networks for Array Processors
Edge Intelligence: Challenges and Opportunities of Near-Sensor Machine Learning Applications
Application and packaging of the AT&T DSP3 parallel signal processor
Combined Multiplication and Sum-of-Squares Units
Analysis of a Fully-Scalable Digital Fractional Clock Divider
Processor clustering for the design of optimal fixed-size systolic arrays
Binary Complex Neural Network Acceleration on FPGA : (Invited Paper)
An Application Specific Memory Characterization Technique for Co-processor Accelerators
Hardware Synthesis for Multi-Dimensional Time
A Novel Matching Criterion And Low Power Architecture For Real-Time Block Based Motion Estimation
NULL Convention Logic TM : A Complete And Consistent Logic For Asynchronous Digital Circuit Synthesis
Time-optimal ranking algorithms on sorted matrices
Stack data management for Limited Local Memory (LLM) multi-core processors
Automated Synthesis of FSMD-Based Accelerators for Hardware Compilation
A Novel FPGA-Based Circuit Simulator for Accelerating Reinforcement Learning-Based Design of Power Converters
AccMER: Accelerating Multi-Agent Experience Replay with Cache Locality-Aware Prioritization
Accelerating the photon mapping algorithm and its hardware implementation
Cross Layer Design to Multi-thread a Data-Pipelining Application on a Multi-processor on Chip
Hybrid SPM-cache architectures to achieve high time predictability and performance
Column Compression Pipelined Multipliers
How can Garbage Collection be energy efficient by dynamic offloading?
Reduced area multipliers
Low-power Design of a Gravity Rotation Module for HAR Systems Based on Inertial Sensors
High level software synthesis for signal processing systems
Improving Emulation of Quantum Algorithms using Space-Efficient Hardware Architectures
High-Speed Viterbi Decoder: An Efficient Scheduling Method to Exploit the Pipelining
Circuit Characteristics of Molecular Electronic Components
Channel complexity analysis for reconfigurable VLSI/WSI processor arrays
Architecture of an Image Rendering Co-Processor for MPEG-4 Systems
FAV-NSS: An HIL Framework for Accelerating Validation of Automotive Network Security Strategies
SWAPHI: Smith-waterman protein database search on Xeon Phi coprocessors
The Mythical CCM: In Search of Usable (and Resuable) FPGA-Based General Computing Machines
An integrated system for rapid prototyping of high performance algorithm specific data paths
A FPGA-based Parallel Architecture for Scalable High-Speed Packet Classification
Implementation of Parallel Arithmetic in a Cellular Automaton
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding
Exploring algorithmic trading in reconfigurable hardware
CAPMA: a content-addressable pattern match architecture for production systems
Cache partitioning and scheduling for energy optimization of real-time MPSoCs
A processor-time-minimal schedule for the standard tensor product algorithm
NeMo: A Platform for Neural Modelling of Spiking Neurons Using GPUs
GRAPE: a special-purpose computer for N-body problems
From green computing to big-data learning: A kernel learning perspective
A Novel Low-Power Motion Estimation Design for H.264
Deterministic Boltzmann machine VLSI can be scaled using multi-chip modules
Performance model of the Argonne Voyager multimedia server
Comparative analysis of OpenCL vs. HDL with image-processing kernels on Stratix-V FPGA
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation
Customising Application-Speci.c Multiprocessor Systems: a Case Study
A fast pipelined FFT unit
CFStore: Boosting Hybrid storage performance by device crossfire
A Public-Key Cryptographic Processor for RSA and ECC
A Multiplication-Free Parallel Architecture for Affine Transformation
Reducing power consumption of embedded processors through register file partitioning and compiler support
Architecture for fractal dimension estimation based on Minkowski-Bouligand method using integer distances
Pipelining and transposing heterogeneous array circuits
POSTER: GPUs Pipeline Latency Analysis
Reconfigurable acceleration of microphone array algorithms for speech enhancement
A systolic array programming language
Automatic design of domain-specific instructions for low-power processors
Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects
Atomic stream computation unit based on micro-thread level parallelism
Architecture Support for FPGA Multi-tenancy in the Cloud
FPGA based singular value decomposition for image processing applications
Block-Update Parallel Processing QRD-RLS Algorithm for Throughput Improvement with Low Power Consumption
Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS tool
Low-cost implementations of NTRU for pervasive security
A GALS FFT processor with clock modulation for low-EMI applications
Programming environment for a line processor-SYMPATI-2
PPAC: A Versatile In-Memory Accelerator for Matrix-Vector-Product-Like Operations
Dynamic Coherent Cluster: A Scalable Sharing Set Management Approach
Entropy Coding on a Programmable Processor Array for Multimedia SoC
Byte-serial convolvers
Systolic Formulation for Low-Complexity Serial-Parallel Implementation of Unified Finite Field Multiplication over GF(2 m )
Hardware Acceleration of Large Scale GCN Inference
Balance power leakage to fight against side-channel analysis at gate level in FPGAs
Overcoming chip-to-chip delays and clock skews
Design space exploration of a cooperative MIMO receiver for reconfigurable architectures
Parallel Prefix Ling Structures for Modulo 2^n-1 Addition
To Buffer, or Not to Buffer? A Case Study on FFT Accelerators for Ultra-Low-Power Multicore Clusters
VLIW Based Runtime Reconfigurable Machine Vision Coprocessor Architecture for Edge Computing
Exploring DMA-assisted prefetching strategies for software caches on multicore clusters
Using TLM for Exploring Bus-based SoC Communication Architectures
Incorporating temperature-leakage interdependency into dynamic voltage scaling for real-time systems
A Reconfigurable Application-specific Instruction-set Processor for Fast Fourier Transform processing
Programming systolic arrays
Automatic Instruction Set Extension and Utilization for Embedded Processors
A compact FPGA-based architecture for elliptic curve cryptography over prime fields
Cryptonite: Scalable Accelerator Design for Cryptographic Primitives and Algorithms
Area-Efficient Parallel FIR Digital Filter Implementations
Associative information processing: algorithms and system