yusuke1997/dblp-id-title huggingface dataset:
A Spike-Sorting-Assisted Compressed Sensing Processor for High-Density Neural Interfaces
A 4.7-to-18-GHz Ultra-Wideband Variable-Gain Balun-LNA Using 3 rd -Order-Band-Pass Input Matching in 40-nm CMOS
Design philosophy of hysteretic controller for DC-DC switching converters
A process variation insensitive bandgap reference with self-calibration technique
An FPGA-based log-structure Flash memory system for space exploration
Zero-crossing distortion analysis in one cycle controlled boost PFC for Low THD
A 4x folding voltage-to-time converter with adjustable conversion gain and offset for time-based ADC
Coefficient adjustment matrix inversion approach and architecture for massive MIMO systems
A two-way parallel CAVLC encoder for 4K×2K H.264/AVC
A novel programmable pulse-broadening time amplifier controlled by node capacitance
Transaction level model of HDMI transmitter based on System Verilog
A digital sliding mode controller for switching power supply converters
A Unifying Tensor View for Lightweight CNNs
Micro-LED arrays for display and communication: Device structure and driver architecture
Origin of high on-state current for dopant-segregated schottky MOSFET
A universal framework of dual-use model for both performance and functionality based on the abstract state machine
Distinguishing dynamic bridging faults and transition delay faults
A 24/48 Gb/s NRZ/PAM-4 Dual-Mode Transmitter with 3-tap FFE in 28 nm CMOS
Power amplifier driver for SDR transmitter with high gain tuning range and dynamic power control
An efficient ASIC Implementation of QARMA Lightweight Algorithm
A 1.0-3.0GHz LTE transmitter with CIM enhancement
A sorting-based IO connection assignment for flip-chip designs
A CMOS transceiver RFIC for China geo-radio standard
Self-synchronous circuit designs, SSFPGA and SSRSA for low voltage autonomous control and tamper resistivity
Hot carrier reliability in ultra-scaled sige channel p-FinFETs
Low-power high-yield SRAM design with VSS adaptive boosting and BL capacitance variation sensing
Performance analysis of on-chip bufferless router with multi-ejection ports
SiGe HBT Power Amplifier design using 0.35 µm BiCMOS technology with through-silicon-via
A 2-V 40-MS/s 14-bit pipelined ADC for CMOS image sensor
1T2R: A novel memory cell design to resolve single-event upset in RRAM arrays
Compact and portable chemiluminescence detector for glucose
Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications
A single inductor tri-input dual-output buck-boost DC-DC converter with MPPT for multi-source energy harvesting
Optimization compensation for primary-side-regulated flyback converters in continuous-conduction-mode and discontinuous conduction mode
A Fast Signal Integrity Design Model of Printed Circuit Board based on Monte-Carlo Tree
A 55nm logic process compatible p-flash memory array fully demonstrated with high reliability
A 0.9V 0.1-4GHz LNTA in 28-nm CMOS Achieving +11.3dBm IIP3 With Self-loaded Linearization Technique
A state recovery design against single-event transient in high-speed phase interpolation clock and data recovery circuit
FPGA-based convolution neural network for traffic sign recognition
SPICE Modeling and Simulation of High-Performance Wafer-Scale MoS2 Transistors
SAR+ΔΣ ADC with open-loop integrator using dynamic amplifier
PDK design of 0.13um SOI process
0.5W X-Band SOI 4-Channel Beamforming TR IC
A high-speed analog front-end circuit used in a 12bit 1GSps pipeline ADC
A realizable reconstruction filter for sampled data systems
Towards the next generation of low-power test technologies
A Wideband Inductorless LNA Employing Dual-Loop Feedback for Low-Power Applications
Implementation of a configurable MIMO detector with complex K-best algorithm
Opportunities and challenges: Ultra-low voltage digital IC design techniques
Novel CMOS technology compatible nonvolatile on-chip hybrid memory
A crosstalk avoidance scheme based on re-layout of signal TSV
An Improved Frequency Compensation Scheme for a Low Quiescent Current Low Dropout Voltage Regulator with Wide Input Voltage and Load Current Range
Simulation Study on Novel High Voltage Transient Voltage Suppression Diodes
Multi-Phase Full/Half Wave Type Resonant Converters with Automatic Current Balance against Element Variation
Conduction mechanism of self-rectifying n + Si-HfO2-Ni RRAM
Realization of intelligent optimization algorithm on IP cores partition for NoC testing
Genetic algorithm based on divide-and-conquer strategy for defect-tolerant CMOL mapping
A Simple Steady Timing Resilient Sample Based on Delay Data Sense Detection
I/Q imbalance estimation in OFDM systems
Design of dual-wideband low noise amplifier base on common gate topology
Scalable Systolic Array Multiplier Optimized by Sparse Matrix
A Domain-Specific DMA Structure for Per-channel Processing-based CNN Accelerator
Suppression of Reflections and Elimination of Transmission Disparities in Differential Crossover Line Junctions
An efficient design algorithm for exploring flexible topologies in custom adaptive 3D NoCs for high performance and low power
An Ultra-Low-Power Temperature Sensor with an Accuracy of +0.6/-1 °C from-30 °C to 90 °C
An outlier detection method and its application to multicore-chip power estimation
An 8Kb 40-nm 2T2MTJ STT-MRAM Design with 2.6ns Access Time and Time-Adjustable Writing Process
A35.2 dBm CMOS RF Power Amplifier Using an 8-Way Current-Voltage Combining Transformer with Harmonic Control
Incremental symbolic construction for topological modeling of analog circuits
MMV Subspace Pursuit (M-SP) Algorithm for Joint Sparse Multiple Measurement Vectors Recovery
A study on channel polarization and polar coding
Fabrication of 3.1kV/10A 4H-SiC Junction Barrier Schottky Diodes
A Micro Power High Precision Sigma-Delta ADC with Adjustable Decimation Ratio
A 10-bit DAC with 2.9 μν low frequency noise for high performance MEMS capacitive accelerometer application
Frequency Estimation Sampling Circuit Using Analog Hilbert Filter and Residue Number System
Design and Analysis of high robustness dual- direction SCR with heavily doping in N-Type Well
A low power and high speed CAM design using pulsed voltage for search-line
A novel dynamic element match technique in current-steering DAC
The annealing effect of chemical vapor deposited graphene
A 20 Gb/s Limiting Amplifier in 65nm CMOS technology
Graphene Biosensor for Saliva Protein Adsorption
FNSim: A Device-Circuit-Algorithm Codesigned Simulator for Flash based Neural Network
Back to the Analog Neural Network and Linear Circuit Theory
Ultra low loss and high linearity RF switch using 130nm SOI CMOS process
Backscattering in multicycle Q-modulation for bio-implants wireless power transfer
Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing
TSV based 3D IC wire length calculation algorithm
A 64×64 active and passive imaging readout circuit based on HgCdTe-LMAPD
A radiation hardened low-noise voltage-controlled-oscillator using negative feedback based multipath- current-releasing technology
Design of frequency synthesizer in frequency-hopping transceiver
A stacked-packaged 16-channel ADC for ultrasound application
Auto-assign method for large scale flip-chip package design
Integration Of Micro Surface Mount Components On Printed Circuit Board By micro-Transfer Printing
A String-in-string-out 256 Bits eFuse Using Full-custom Design in 55nm Process
Improve DRAM Leakage Issue During RAS Operational Phase Through TCAD Simulation
A 293-to-303 GHz Fundamental VCO with -4dBm Peak Output Power in 40nm CMOS
A programmable divider with extended division range for 24GHz FMCW frequency synthesizer
CCASM: A Computation- and Communication-Aware Scheduling and Mapping Algorithm for NoC-Based DNN Accelerators
Glass Wet Deep Etching for Fabricating Biomimetic Devices in Biosensing
A 0.4V 53dB SNDR 250 MS/s time-based CT ΔΣ analog to digital converter
High-frequency low-distortion signal generation algorithm with arbitrary waveform generator
A study of high-level synthesis: Promises and challenges
Sampling Rate Enhancement for SAR-ADCs Using Adaptive Reset Approach for FOG Systems
Tunable voltage-mode four inputs universal biquad using three DVCCs
InAlN/GaN HEMTs on Si with 0.18-Ω•mm Contact Resistance and 2.1-A/mm Drain Current Density
A precision 2.5V bandgap voltage reference with excellent initial accuracy of 0.25% for high resolution ADCs
A matrix approach to low-voltage low-power log-domain CMOS current-mode adjustable-bandwidth step-gain filter design
Latency Minimal Scheduling with Maximum Instruction Parallelism
0.5 VDD digitally controlled oscillators design with compensation techniques for PVT variations
A 1-V 2.5-ppm/°C second-order compensated bandgap reference
A high performance massive MIMO detector based on log-domain belief-propagation
An On-Time Generator with Zero Quiescent Power Consumption Suitable for AOT Buck Converters
A 0.8ps minimum-resolution sub-exponent TDC for ADPLL in 0.13µm CMOS
Design and implementation of homogeneous multi-core system
A Modeling Study: Applying Carbon-Based Interconnects to BS-PDN Architecture
2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015
FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp
Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design
A JTAG-based configuration circuit applied in SerDes chip
A 65nm Reliable Near-Subthreshold Standard Cells Design Using Schmitt Trigger
An automatic peak-valley current mode step-up/step-down DC-DC converter with smooth transition
A time-domain flash ADC immune to voltage controlled delay line non-linearity
Layer thinning of MoS2 flakes by thermal annealing in air
A low gain error two-stage dB-linear variable gain amplifier in 0.35μm CMOS process
Performance evaluation modeling for reconfigurable processor
A 40V monolithic ultrasonic motor driver
Optimal design of short circuit robustness for high voltage and high power IGBTs
Meshim: A high-level performance simulation platform for three-dimensional network-on-chip
A DC Offset Cancellation Circuit Using Digital Assistance Technique and Self-Calibrating Comparator for RF Transceiver
A coarse-grained reconfigurable computing unit
Evaluation of Cyanoethyl Pullulan material as the dielectric layer for EWOD devices
A Review and Perspective on Electrode Patch-Based Fetal ECG Monitoring ASIC
Learning Sparse Patterns in Deep Neural Networks
A Novel Programmable Risistance and Capacitance Network for High-Precision Analog Design
A novel oscillator-based TRNG for smart IC card
A Single-Slope PWM Imaging Method for Multi-Mode Dynamic Vision Sensor
Hardware Design of Gaussian Kernel Function for Non-Linear SVM Classification
Soft-Error Tolerance Depending on Supply Voltage by Heavy Ions on Radiation-Hardened Flip Flops in a 65 nm Bulk Process
Integrating operation scheduling and binding for functional unit power-gating in high-level synthesis
Low jitter clock driver for high-performance pipeline ADC
An empirical model for static I-V characteristics of double gate tunneling field effect transistor
Building-in reliability in BCD (Bipolar-CMOS-DMOS) technologies
Cost-Efficient Soft Error Detection and Correction Flip-Flop Design for Nanoscale Technology
A Grain-Adaptive Computing Structure for FPGA CNN Acceleration
Design of power-up and arbiter hybrid physical unclonable functions in 65nm CMOS
A High-Efficient and Configurable Hardware Accelerator for Convolutional Neural Network
Networking industry trends in ESD protection for high speed IOs
A 2.5V supply low noise CMOS amplifier using noise reduction technique of Chopper stabilization
An efficient optimization method of RF passive components using RBF model
Joint detection and decoding for non-binary LDPC coded MIMO systems
Minimum Output Ripple and Fixed Operating Frequency Based on Modulation Injection for COT Ripple Control Converter
A Low-delay Configurable Register for FPGA
Compensator design for digital controlled switched-mode power supplies
A novel adaptive general current drive circuit
Dual-pulse nonlinear photoacoustic imaging: Physics, sensing and imaging system design
A 55nm ultra high density two-port register file compiler with improved write replica technique
Advanced FinFET technologies for boosting SRAM performance
An acceleration method by GPGPU for analytical placement using quasi-Newton method
Power grid simulation using matrix exponential method with rational Krylov subspaces
Physical Coding Sublayer For 32Gbps SerDes Based On JESD204C
CMOS low-power subthreshold reference voltage utilizing self-biased body effect
Design and verification of an application-specific PLD using VHDL and SystemVerilog
A reconfigurable floating-point FFT architecture
Driver circuit system for temperature control of micro-hotplates: Measurement and strategy
A novel positive-feedback read scheme with tail current source of STT-MRAM
A high performance real-time edge detection system with NEON
Addressing Aging Issues in Heterogeneous Three-Dimensional Integrated Circuits
Battery state of charge estimation using adaptive subspace identification method
Fp 2 arithmetic acceleration based on modified Barrett modular multiplication algorithm
A distributive on-chip voltage regulation scheme for power supply in AMOLED driver ICs
Evaluating the Energy Efficiency of STT-MRAMs Based on Perpendicular MTJs with Double Reference Layers
Low-Complexity GAI-BP Detection for MIMO Systems with Threshold-Updating Strategy
Ultra low power circuits design based on III-V group heterojunction tunnel field effect transistor
Selectable notch frequencies of EMI spread spectrum using pulse modulation in switching converter
UACT: A Unified Energy-efficient Computing Architecture for CNN and TCNN
The data retention improvement with 2T structure OTP on 0.18um CMOS technology
Primal-dual method based simultaneous functional unit and register binding
A 128-electrodes Neural Probe with 30*55 µm 2 Channel Area Low-power CCO-based ADC
Full-Chip Voltage Prediction via Graph Attention Based Neural Networks
An APWM controlled LLC resonant converter for a wide input range and different load conditions
A Fast-Lock DLL with Prediction-Based Fast-Track FDL Structure for DDR5 SDRAMs
A reference signal phase independent high precision timing skew mismatch estimation scheme for time interleaved ADC
A 1-V 5.2-5.7 GHz low noise sub-sampling phase locked loop in 0.18 μm CMOS
Research on testing of 32-bit CPU based SiP
Comprehensive study on higher order radix RSA cryptography engine
Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU
Intelligent Multimodal Sensors Based on Novel Electronic-Ionic Bi2O2Se Semiconductors
A 300MHz 10b time-interleaved pipelined-SAR ADC
A low power 1.5GHz Gm-C filter with 0-40dB variable gain in 65-nm CMOS technology
A GaSb/In0.4Ga0.6As Heterojunction Z-Shaped Tunnel Field-Effect Transistor with High Performance
A 2Mb ReRAM with two bits error correction codes circuit for high reliability application
Low noise design and measurement of 32-channel X-ray ROIC
A new low power symmetric folded cascode amplifier by recycling current in 65nm CMOS technology
A Multiplier-less Transform Architecture with the Diagonal Data Mapping Transpose Memory for The AVS3 Standard
Automatic layout generator for embedded FPGA cores
A new method to improve the unconditional stability of InGaP/GaAs heterojunction bipolar transistor
Compact modeling of the diode reverse recovery effect for leading developments of power electronic applications
Design of Lightweight Strong Arbiter PUF Circuit Based on MOSFET Threshold Loss
A 1.8V 100MS/s 10-bit pipelined folding A/D converter with 9.49 ENOB at Nyquist frequency
MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5
Synthesis and optimization of asynchronous dual rail encoded circuits based on partial acknowledgement
A CMOS Half-Bridge GaN Driver with 6-30V Input Voltage Range and 5.4ns Propagation Delay
Adaptive DLL Update Scheme for Power Fluctuation Immunity Using Phase Error Detector
A 1-V 23-μW 88-dB DR Sigma-Delta ADC for high-accuracy and low-power applications
A ReRAM-based 10T2R SRAM Using Power-off Recovery Function for Reducing Power
Design of A Reference Buffer with Ultralow Output Resistance for High-speed ADCs
A CMOS Random Number Generator with Noise-Coupled Voltage-Controlled Oscillators
Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm
Three-dimensional on-chip inductor design based on through-silicon vias
Rapid Growth of SiO2 on SiC with Low Ditusing High Pressure Microwave Oxygen Plasma
A Novel Hybrid Nonvolatile SRAM for Suppressing Leakage Power Using Tunnel FET
A FT Trimming Circuit Based on EPROM and Pin Multiplexing
A 300MS/s 57.6dB SNDR Single-Channel SAR ADC with Accelerated SAR Logic
Design and optimization of asynchronous circuits with gate-level pipelining
High reliable digital signal processor for automotive application
Scalable Modeling for the CPW Gap Discontinuity at Frequency up to 150 GHz
A force directed partitioning algorithm for 3D floorplanning
A High-Performance Mel-scale Frequency Cepstral Coefficients Digital Circuit Used on Keyword-Spotting Chip
Analytical models for channel potential and drain current in AlGaN/GaN HEMT devices
High Reliability GaN FET Gate Drivers for Next-generation Power Electronics Technology
Sample-hold circuit and stage circuits in a traditional 12-b 80-Msample/s pipelined A/D converter
A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology
A Dual-Core Quad_Mode VCO with Reconfigurable Magnetic Coupling Mode and Negative-Resistive Mode Switch
Type-3 2-D multimode IIR filter architecture and the corresponding symmetry filter's error analysis
A Low-Temperature-Coefficient and High-PSRR Bandgap Reference for Readout Circuit of SPAD
A novel multi-finger layout strategy for GGnMOS ESD protection device
A Four Modes and Smooth Transition Non-inverting Buck-Boost Converter
Design and implementation of transaction level processor based on UVM
An effecient level-shifter floorplanning method for Multi-voltage design
Mutli-level Regression Anchor-free Object Detection
Don't let the X-bugs bite: Conquer elusive X-propagation issues early! Get them before they get you!
Polarity optimization of XNOR/OR circuit area and power based on weighted sum method
A 20GS/s Track-and-Hold Amplifier based on InP DHBT Process
A 96kb, 0.36V, Energy-Efficient 8T-SRAM with Column-Selection and Shared Buffer-Foot Techniques for EEG Processor
Monolithic Co-integration of III-V Materials into Foundry Si-CMOS in a Single Chip for Novel Integrated Circuits
A linearized VBE bandgap voltage reference with wide temperature range
The VLSI architecture for channel estimation based on ADMA
Research on electromechanical model of micro-accelerometer based on SOI technology
Fabrication of silicon-based MEMS capacitive microphone structure with thin starting wafer
Analog / Mixed-Signal / RF Circuits for Complex Signal Processing
A 6-Gb/s Wireline Transmitter Design with 3-Tap FFE in 28nm CMOS Technology
A Bandgap Voltage Reference with Low Temperature Coefficient and High PSRR Designed for LDO
Design and Implementation of High-speed Reconfigurable Multi-core Network Security Protocol Analyse Processor
A Segmented and Linear Frequency Controller for Flyback Converters
Optimization of mixed polarity Reed-Muller expressions based on Whole Annealing Genetic Algorithm
Future low-noise technologies for RF, analog and mixed-signal integrated circuits
A Timing Mismatch Background Calibration Technique with High-Precision Skew Estimation
Keynote speech: Data converters for mobile and autonomous applications
A 256-channel 11-bit OLED Source Driver IC with Unit Current Calibration
A Cost-efficient Hybrid Gate Driver For SiC MOSFETs and IGBTs
Signal Generation Technologies for Analog/Mixed-Signal IC Testing
Memory-Efficient Compression Based on Least-Squares Fitting in Convolutional Neural Network Accelerators
A Compact 7-10 GHz GaN Low Noise Amplifier MMIC with Sub 0.3 dB Gain flatness
A low cost and high reliability true random number generator based on resistive random access memory
A fast HDL model for full-custom FPGA verification
Fault detection and redundancy design for TSVs in 3D ICs
Effect of structural parameters on the performance and variations of nanosizes PNIN tunneling field effect transistor
Low power design for SoC with power management unit
Dual code channel hybrid readout circuit based on high precision Photoelectric encoders
A CT DSM with DAC Scaling Technique for Direct Neural Recording Front-End
A 7nm-Based Decodable Self-Resetting Regfile Circuit
Terahertz CMOS transceiver for tera-bps wireless link
Analytical Global Placement for Heterogenous FPGAs Based on the eDensity Model
An integrated zigbee transmitter and DC-DC converter on 0.18μm HV RF CMOS technology
An on-chip circuit for timing measurement of SRAM IP
Droplet generating with accurate volume for EWOD digital microfluidics
ZnO Wheatstone bridge for UV light detection
A 110-dBΩ, 113-MHz variable-gain transimpedance amplifier for flash 3D imaging systems
A novel low THD 4-quadrant analog multiplier using feedforward compensation for PFC
A novel scaling theory for fully-depleted omega-gate (ΩG) MOSFETs
A Platform with Exquisite Film Profile Engineering in Oxide-Based Thin-Film Transistors for More-than-Moore Applications
TCAD simulation of trench-gate IGBTs for prediction of carrier lifetime requirements for future scaled devices
Area Optimization of MPRM Circuits Using Approximate Computing
Challenges of electrostatic discharge (ESD) protection in emerging silicon nanowire technology
A Class-F3 VCO with 104% Ultra-Wide Band Tuning Range and -125dBc/Hz Phase Noise
A single-inductor MIMO buck-boost converter with inductor-peak-current PFM control for multiple energy harvesting
Design of CMOS integrated circuits for radiation hardening and its application to space electronics
Simulation of carrier transport in quantum cascade lasers
A low-power on-chip calibration technique for pipelined ADCs
A charge-pump circuit to restrain reference spurs in the PLL
Low noise coupling techniques for multi-phase oscillators
AlGaN/GaN HEMTs with electric field modulation effect: a comprehensive study
Research on Transparent Resistive Random Memory Based on Lanthanum-based High-k Medium
Deploying and Optimizing Convolutional Neural Networks on Heterogeneous Architecture
Novel 15T SRAM Cell for Low Voltage High Reliability Application
Study for NOR Flash cell burn out failure improvement in the advanced node below 65nm
Design and test of an SRAM chip
An Automatic Optimization Method of Combinational Logic Loops in CGRA
Finite aperture time effects in sampling circuit
Highly flexible WBAN transmit-receive system based on USRP
Design of an optimized low-latency interrupt controller for IMS-DPU
Automatic classification of leukocytes using deep neural network
Compact modeling approach for electro-mechanical system simulation
Hot carrier aging of nano-scale devices: Characterization method, statistical variation, and their impact on use voltage
Security Analysis and Modeling Attacks on Duty Cycle Multiplexer PUF
A fast vector reuse verification method for standard cell library
High Linear Ring Amplifier Design with Analysis on Settling Procedures
Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis
Power grid sizing via convex programming
NBTI prediction and its induced time dependent variation
A Hierarchical Fault Injection System for RISC-V Processors Targeting Single Event Upsets in Flip-Flops
A gain factor controlled SUMPLE algorithm and system
A power-efficient network-on-chip for multi-core stream processors
Parallel structure of GF (2 14 ) and GF (2 16 ) multipliers based on composite finite fields
An effective analytical 3D placer in monolithic 3D IC designs
A low-power 433MHz transmitter for battery-less Tire Pressure Monitoring System
A fast and accurate automatic frequency calibration scheme for frequency synthesizer