yusuke1997/dblp-id-title huggingface dataset:
Special session on architectures and design tools for secure embedded systems
Using Frame Similarity for Low Energy Software-Only IoT Video Recognition
Exact Partitioning of Affine Dependence Algorithms
Software defined radio implementation of K-best list sphere detector algorithm
Introduction to the Future of Reconfigurable Computing and Processor Architectures
MGSim - A simulation environment for multi-core research and education
SensorOS: A New Operating System for Time Critical WSN Applications
Power proportional characteristics of an energy manager for web clusters
Design and Implementation of a WLAN Terminal Using UML 2.0 Based Design Flow
Combining Task- and Data-Level Parallelism for High-Throughput CNN Inference on Embedded CPUs-GPUs MPSoCs
Multi-processor system-on-chip Design Space Exploration based on multi-level modeling techniques
Embedded Computer Systems: Architectures, Modeling, and Simulation - 20th International Conference, SAMOS 2020, Samos, Greece, July 5-9, 2020, Proceedings
Hybrid code description for developing fast and resource efficient image processing architectures
Variable length instruction compression on Transport Triggered Architectures
XL-STaGe: A cross-layer scalable tool for graph generation, evaluation and implementation
Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow
TULIPP: Towards ubiquitous low-power image processing platforms
Reduction of Energy Consumption in Processors by Early Detection and Bypassing of Trivial Operations
Key Research Challenges for Successfully Applying MDD Within Real-Time Embedded Software Development
High-level synthesizable dataflow MapReduce accelerator for FPGA-coupled data centers
Optimal mapping of inferior olive neuron simulations on the Single-Chip Cloud Computer
Area-Aware Optimizations for Resource Contrained Branch Predictors Exploited in Embedded Processors
Configurable Computing for High-Security/High-Performance Ambient Systems
An embedded hardware-efficient architecture for real-time cascade Support Vector Machine classification
Architecture exploration of a programmable neural network processor for embedded systems
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2016, Agios Konstantinos, Samos Island, Greece, July 17-21, 2016
Composable power management with energy and power budgets per application
CORDIC-Augmented Sandbridge Processor for Channel Equalization
Evaluation of approximate operators case study: sobel filter application executed on an approximate RISC-V platform
Virtual environment for developing real-time image processing for vehicle control
A Scheduling Strategy for a Real-Time Dependable Organic Middleware
An application-specific Network-on-Chip for control architectures in RF transceivers
Deterministic event-based control of Virtual Platforms for MPSoC software debugging
Manycore performance analysis using timed configuration graphs
Accurate LLVM IR to Binary CFGs Mapping for Simulation of Optimized Embedded Software
A Case for Genome Analysis Where Genomes Reside
A Fine-Granularity Image Pyramid Accelerator for Embedded Processors
Register-Based Permutation Networks for Stride Permutations
Adaptive processor architecture - invited paper
Efficient distribution of Triggered Synchronous Block Diagrams on asynchronous platforms
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Pythagorion, Greece, July 15-19, 2018
A fully programmable FSM-based Processing Engine for Gigabytes/s header parsing
The Known Unknowns: Discovering Trade-Offs Between Heterogeneous Code Changes - Invited Paper
EPIC-Q: Equivalent-Policy Invariant Comparison Enhanced Transfer Q-learning for Run-Time SoC Performance-Power Optimization
Programming multi-core architectures using Data-Flow techniques
Unlocking the Potential of RISC-V Heterogeneous MPSoC: A PANACA-Based Approach to Simulation and Modeling
Trust-Based Adaptive Routing for NoCs
Power models supporting energy-efficient co-design on ultra-low power embedded systems
Design and Optimization of an ARM Cortex-M Based SoC for TCP/IP Communication in High Temperature Applications
Clustering method for the identification of convex disconnected Multiple Input Multiple Output instructions
Pipelined FPGA coprocessor for elliptic curve cryptography based on residue number system
Exploring system performance using elastic traces: Fast, accurate and portable
Streaming Systems in FPGAs
Multi-Constraint multi-processor Resource Allocation
Exploiting Similarity in Evolutionary Product Design for Improved Design Space Exploration
Hardware task migration module for improved fault tolerance and predictability
SC2SCFL: Automated SystemC to SystemC FL Translation
Smart cache: A self adaptive cache architecture for energy efficiency
Split'n'Cover: ISO 26262 Hardware Safety Analysis with SystemC
Communication-aware scheduling algorithms for synchronous dataflow graphs on multicore systems
Multicore Communications API (MCAPI) implementation on an FPGA multiprocessor
A Programming Model for an Embedded Media Processing Architecture
TimeCube: A manycore embedded processor with interference-agnostic progress tracking
Verilog-based simulation of hardware support for data-flow concurrency on multicore systems
Rec2Poly: Converting Recursions to Polyhedral Optimized Loops Using an Inspector-Executor Strategy
Robustness analysis of multiprocessor schedules
Caches with Compositional Performance
Low-Power Twiddle Factor Unit for FFT Computation
High-Level Simulation of Embedded Software Vulnerabilities to EM Side-Channel Attacks
Embedded multicore architectures for LDPC decoding
Automatic Memory-Efficient Scheduling of CNNs
Evaluation of Different Multithreaded and Multicore Processor Configurations for SoPC
FlexCore: Implementing an exposed datapath processor
Extraction of recursion level parallelism for embedded multicore systems
What Else Is Broken? Can We Fix It?
An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systems
Using SDRAMs for two-dimensional accesses of long 2 n × 2 m -point FFTs and transposing
Radar Object Detection on a Vector Processor Using Sparse Convolutional Neural Networks
A Real-Time Programming Model for Heterogeneous MPSoCs
Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems
Domain-Specific Modeling of Power Aware Distributed Real-Time Embedded Systems
Power Efficient Co-simulation Framework for a Wireless Application Using Platform Based SoC
Simulator calibration for accelerator-rich architecture studies
A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures
Technical Debt Management and Energy Consumption Evaluation in Implantable Medical Devices: The SDK4ED Approach
Efficient management of speculative data in hardware transactional memory systems
An intermediate format for automatic generation of MPSoC virtual prototypes
Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, 2005, Proceedings
CHASM: Security Evaluation of Cache Mapping Schemes
A Comparison of NoTA and GENESYS
RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM
Visual processing sparks a new class of processors
Dataflow computing with Polymorphic Registers
iVault: Architectural Code Concealing Techniques to Protect Cryptographic Keys
A comprehensive ASIC/FPGA prototyping environment for exploring embedded processing systems for advanced driver assistance applications
Special session on software defined radio (SDR) and Cognitive Radio (CR)
Application autotuning to support runtime adaptivity in multicore architectures
A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study
An adaptive bloom filter cache partitioning scheme for multicore architectures
LSTM Acceleration with FPGA and GPU Devices for Edge Computing Applications in B5G MEC
An emulation-based real-time power profiling unit for embedded software
Neuromorphic self-organizing map design for classification of bioelectric-timescale signals
A library of dual-clock FIFOs for cost-effective and flexible MPSoC design
Optimizing QAM Demodulation with NEON SIMD and Algorithmic Approximation Techniques
Massively parallel signal processing challenges within a driver assistant prototype framework first case study results with a novel MIMO-radar
Design, Implementation, and Experiments on Outdoor Deployment of Wireless Sensor Network for Environmental Monitoring
Exploration of Distributed Shared Memory Architectures for NoC-based Multiprocessors
A Hardware/Software Architecture for Tool Path Computation. An Application to Turning Lathe Machining
Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs
Massively parallel computation of linear recurrence equations with graphics processing units
Platform-Agnostic Learning-Based Scheduling
Functional unit sharing between stacked processors in 3D integrated systems
Bard: A unified framework for managing soft timing and power constraints
Applying Data Mapping Techniques to Vector DSPs
DVFS-enabled power-performance trade-off in MPSoC SW application mapping
Automatic FPGA synthesis of memory intensive C-based kernels
High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP
On-demand thread-level fault detection in a concurrent programming environment
Can a reconfigurable architecture beat ASIC as a CNN accelerator?
Preventing Denial-of-Service Attacks in Shared CMP Caches
Embedded Computer Systems: Architectures, Modeling, and Simulation - 19th International Conference, SAMOS 2019, Samos, Greece, July 7-11, 2019, Proceedings
Introduction to Instruction-Set Customization
PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning
AEGLE: A big bio-data analytics framework for integrated health-care services
Exposed datapath optimizations for loop scheduling
Experimental Evaluation of Probabilistic Execution-Time Modeling and Analysis Methods for SDF Applications on MPSoCs
The Heterogeneous System Architecture: It's beyond the GPU
A priority-expression-based burst scheduling of memory reordering access
System simulation with gem5 and SystemC: The keystone for full interoperability
High-Level Energy Estimation for ARM-Based SOCs
Parallel SystemC simulation for ESL design using flexible time decoupling
Customising Hardware Designs for Elliptic Curve Cryptography
The ARISE Reconfigurable Instruction Set Extensions Framework
Chip-independent Error Correction in main memories
Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform
On Security of PAN Wireless Systems
Consistency Analysis of Reconfigurable Dataflow Specifications
Compile-time GPU memory access optimizations
On the Benefit of Caching Traffic Flow Data in the Link Buffer
GPGPU workload characteristics and performance analysis
Review of Hardware Architectures for Advanced Encryption Standard Implementations Considering Wireless Sensor Networks
FPGA based application specific processing for sensor nodes
Implementing Blocked Sparse Matrix-Vector Multiplication on NVIDIA GPUs
Pattern Matching Acceleration for Network Intrusion Detection Systems
Co-design of many-accelerator heterogeneous systems exploiting virtual platforms
Mining Dynamic Document Spaces with Massively Parallel Embedded Processors
Scenario-aware dataflow: Modeling, analysis and implementation of dynamic applications
ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration
Embedded Computer Systems: Architectures, Modeling, and Simulation, 7th International Workshop, SAMOS 2007, Samos, Greece, July 16-19, 2007, Proceedings
Using a genetic algorithm approach to reduce register file pressure during instruction scheduling
RattlesnakeJake: A Fast and Accurate Pre-alignment Filter Suitable for Computation-in-Memory
High speed cycle approximate simulation for cache-incoherent MPSoCs
A quasi-cycle accurate timing model for binary translation based instruction set simulators
Simplifying HW/SW integration to deploy multiple accelerators for CPU-FPGA heterogeneous platforms
Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform
Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box
Algorithmic and memory optimizations on multiple application mapping onto FPGAs
A framework for reducing the modeling and simulation complexity of Cyberphysical Systems
On the Problem of Minimizing Workload Execution Time in SMT Processors
Access-aware DRAM failure-rate estimation under relaxed refresh operations
Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration
Fast Real-Time Job Selection with Resource Constraints Under Earliest Deadline First
Virtual prototyping for efficient multi-core ECU development of driver assistance systems
Reconfigurable Multiple Operation Array
GLoRia: An Energy-Efficient GPU-RRAM System Stack for Large Neural Networks
Plan Your Defense: A Comparative Analysis of Leakage Detection Methods on RISC-V Cores
Runtime support for adaptive power capping on heterogeneous SoCs
AccuRA: Accurate alignment of short reads on scalable reconfigurable accelerators
Real-Time Stereo Vision on a Reconfigurable System
The Next Generation Challenge for Software Defined Radio
Adaptive resource allocation for streaming applications
Empowering OpenMP with automatically generated hardware
Multicore enablement for Cyber Physical Systems
Comparison of Data Dependence Analysis Tests
System-Level Design Space Exploration of Dynamic Reconfigurable Architectures
Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata
Introduction to Programming Multicores
On the (Re-)Use of IP-Components in Re-configurable Platforms
3D-stacked many-core architecture for biological sequence analysis problems
A virtual platform for exploring hierarchical interconnection for many-accelerator systems
Neuronal connectivity assessment for epileptic seizure prevention: Parallelizing the generalized partial directed coherence on many-core platforms
Prototyping Efficient Interprocessor Communication Mechanisms
Automated Distribution of UML 2.0 Designed Applications to a Configurable Multiprocessor Platform
A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors
METASAT: Modular Model-Based Design and Testing for Applications in Satellites
High level quantitative hardware prediction modeling using statistical methods
Static Energy Saving Through Multi-Bank Memory Architecture
An Approach for the Reduction of Power Consumption in Sensor Nodes of Wireless Sensor Networks: Case Analysis of Mica2
A software-defined architecture and prototype for disaggregated memory rack scale systems
On the impact of dynamic task scheduling in heterogeneous MPSoCs
Image Quantisation on a Massively Parallel Embedded Processor
A Streaming Machine Description and Programming Model
Relaxed subgraph execution model for the throughput evaluation of IBSDF graphs
A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA
Arithmetic Design on Quantum-Dot Cellular Automata Nanotechnology
Design and Implementation of an Open Source OpenGL SC 2.0.1 Installable Client Driver and Offline Compiler
Software Is the Answer But What Is the Question?
An Architecture and Protocol for the Management of Resources in Ubiquitous and Heterogeneous Systems Based on the SVP Model of Concurrency
On Enhancing SIMD-Controlled DSPs for Performing Recursive Filtering
GEMBench: A Platform for Collaborative Development of GPU Accelerated Embedded Markov Decision Systems
GPU implementation of an anisotropic Huber-L1 dense optical flow algorithm using OpenCL
A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures
Skipping CNN Convolutions Through Efficient Memoization
Technologies for reducing power
Rethinking computer architecture for throughput computing
Energy-Efficient BLAS L1 Routines for FPGA-Supported HPC Applications
Systematic Data Structure Exploration of Multimedia and Network Applications realized Embedded Systems
Generation and calibration of compositional performance analysis models for multi-processor systems
A Memory-Efficient Reconfigurable Aho-Corasick FSM Implementation for Intrusion Detection Systems
An interval algebra for multiprocessor resource allocation
On the Characterization of Data Cache Vulnerability in High-Performance Embedded Microprocessors
Evaluation of fine-grained parallelism in AUTOSAR applications
Autonomous Construction Technology of Community for Achieving High Assurance Service
A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs)
A Low-Power Multithreaded Processor for Baseband Communication Systems
An IP Core for Embedded Java Systems
Probabilistic Modelling and Evaluation of Soft Real-Time Embedded Systems
ViPES 2015 - Preface
Deploying OpenMP on an embedded multicore accelerator
Design Space Exploration of Configuration Manager for Network Processing Applications
Tagged Geometric History Length Access Interval Prediction for Tightly Coupled Memory Systems
Heterogeneous Design in Functional DIF
Maximum and Sorted Cache Occupation Using Array Padding
Intermediate Level Components for Reconfigurable Platforms
A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models
Approximate Similarity Search with FAISS Framework Using FPGAs on the Cloud
Counting stream registers: An efficient and effective snoop filter architecture
S-NET: A Confusion Based Countermeasure Against Power Attacks for SBOX
Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platforms
A Scalable Embedded JPEG2000 Architecture
The VINEYARD integrated framework for hardware accelerators in the cloud
Open Source Software Randomisation Framework for Probabilistic WCET Prediction on Multicore CPUs, GPUs and Accelerators
Decision Support Systems to Promote Health and Well-Being of People During Their Working Age: The Case of the WorkingAge EU Project
Genesys: Automatically generating representative training sets for predictive benchmarking
From reversible logic to quantum circuits: Logic design for an emerging technology
Enabling an Isolated and Energy-Aware Deployment of Computationally Intensive Kernels on Multi-tenant Environments
PicoServer - building a compact energy efficient multiprocessor
A Design Space Exploration Methodology for Enabling Tensor Train Decomposition in Edge Devices
A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability
Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings
On the Effectiveness of True Random Number Generators Implemented on FPGAs
ImpBench revisited: An extended characterization of implant-processor benchmarks
High Level Loop Transformations for Systematic Signal Processing Embedded Applications
Framework for parameter analysis of FPGA-based image processing architectures
Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA
A hybrid approach for mapping and scheduling on heterogeneous multicore systems
Video chain demonstrator on Xilinx Kintex7 FPGA with EdkDSP floating point accelerators
PATARA: Extension of a Verification Framework for RISC-V Instruction Set Implementations
An accurate energy model for streaming applications mapped on MPSoC platforms
Performance-power exploration of software-defined big data analytics: The AEGLE cloud backend
CoPTA: Contiguous Pattern Speculating TLB Architecture
Initial Evaluation of Multimedia Extensions on VLIW Architectures
Interleaving granularity on high bandwidth memory architecture for CMPs
On the modeling of error functions as high dimensional landscapes for weight initialization in learning networks
SAD Prefetching for MPEG4 Using Flux Caches
A Novel Data-Path for Accelerating DSP Kernels
MORA: A New Coarse-Grain Reconfigurable Array for High Throughput Multimedia Processing
Transparent sampling
First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption
Energy-Efficient and High-Throughput CNN Inference on Embedded CPUs-GPUs MPSoCs
A Fast Heuristic to Pipeline SDF Graphs
An automotive specific MILP model targeting power-aware function partitioning
A quantitative analysis of fixed-point LDPC-decoder implementations using hardware-accelerated HDL emulations
MPSoCSim extension: An OVP simulator for the evaluation of cluster-based multi and many-core architectures
Memory Bandwidth Requirements of Tile-Based Rendering
Area Reliability Trade-Off in Improved Reed Muller Coding
Model-driven robot-software design using integrated models and co-simulation
Run-time mapping algorithm for dynamic workloads using process merging transformations
Evaluating the memory system behavior of smartphone workloads
Accelerating RTL Simulation by Several Orders of Magnitude Using Clock Suppression
Fully-automatic derivation of exact program-flow constraints for a tighter worst-case execution-time analysis
Tool-Aided Design and Implementation of Indoor Surveillance Wireless Sensor Network
Preliminary Analysis of the Cell BE Processor Limitations for Sequence Alignment Applications
Evaluating the Impact of Racetrack Memory Misalignment Faults on BNNs Performance
Pooling On-the-Go for NoC-Based Convolutional Neural Network Accelerator
PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration
The design space of the number theoretic transform: A survey
Customising Processors: Design-Time and Run-Time Opportunities
Comparative architectural characterization of SPEC CPU2000 and CPU2006 benchmarks on the intel® Core TM 2 Duo processor
Out-Of-order execution of synchronous data-flow networks
Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance Requirements
A tightly-coupled multi-core cluster with shared-memory HW accelerators
Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings
Runtime Adaptive Extensible Embedded Processors - A Survey
A high-level DRAM timing, power and area exploration tool
High-speed FPGA-based implementations of a Genetic Algorithm
Supporting composition in symbolic system synthesis
Towards real-time whisker tracking in rodents for studying sensorimotor disorders
Power Efficient Instruction Caches for Embedded Systems
ELAION: ML-Based System for Olive Classification with Edge Devices
RISC-V Accelerators, Enablement and Applications for Automotive and Smart Home in the ISOLDE Project
Tuning a Protocol Processor Architecture Towards DSP Operations
Challenges in embedded system simulation
Throughput driven transformations of Synchronous Data Flows for mapping to heterogeneous MPSoCs
Instruction scheduling for VLIW processors under variation scenario
An efficient design space exploration methodology for multiprocessor SoC architectures based on response surface methods
A Critical Assessment of DRAM-PIM Architectures - Trends, Challenges and Solutions
A Quantitative Study of Locality in GPU Caches
A Polymorphic Register File for matrix operations
Can They Be Fixed: Some Thoughts After 40 Years in the Business
High Performance Instruction Fetch Structure within a RISC-V Processor for Use in Harsh Environments
Multi-Objective Topology Optimization for Networked Embedded Systems
Lessons learned on which applications benefit when implemented on CPU-FPGA heterogeneous system
Abstraction of polychronous dataflow specifications into mode-automata
RETHROTTLE: Execution throttling in the REDEFINE SoC architecture
Power optimizations for transport triggered SIMD processors
Fine-Grained Power Modeling of Multicore Processors Using FFNNs
Inter-task communication via overlapping read and write windows for deadlock-free execution of cyclic task graphs