yusuke1997/dblp-id-title huggingface dataset:
Exploiting error control approaches for Hardware Trojans on Network-on-Chip links
Low-Cost Hardening of Image Processing Applications Against Soft Errors
Fast and area-time efficient Berger code checkers
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols
Transient and Intermittent Fault Recovery without Rollback
Adaptive De-noising Filter Algorithm for CMOS Image Sensor Testing Applications
Deletion/Insertion/Reversal Error Correcting Codes for Bit-Patterned Media Recording
Nonvolatile Repair Caches Repair Embedded SRAM and New Nonvolatile Memories
Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment
A Comprehensive Evaluation of the Effects of Input Data on the Resilience of GPU Applications
A novel scheme for concurrent error detection of OLS parallel decoders
A resilient scheduler for dataflow execution
Good Processor Identification in Two-Dimensional Grids
SET Emulation Under a Quantized Delay Model
On enhancing the debug architecture of a system-on-chip (SoC) to detect software attacks
Evaluation of the Effects of SEUs on Configuration Memories in FPGA Implemented QC-LDPC Decoders
Novel High Speed Robust Latch
Lightweight Fault Detection and Management for Image Restoration
Parametric counterfeit IC detection via Support Vector Machines
The effect of spot defects on the parametric yield of long interconnection lines
Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures
Fault-Tolerant High-Performance Cordic Processors
Compact and low power on-line self-testing voting scheme
A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells
Some Results on Improving the Code Length of SbEC-DED Codes
A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures
BiST Model for IC RF-Transceiver Front-End
Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model
Estimating Error Propagation Probabilities with Bounded Variances
Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element
Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning
A novel pseudonoise tester for transmission line fault location and identification using pseudorandom binary sequences
Soft Error Hardened FF Capable of Detecting Wide Error Pulse
A View from the Bottom: Nanometer Technology AC Parametric Failures -- Why, Where, and How to Detect
Layout-driven detection of bridge faults in interconnects
Evaluation of TMR effectiveness for soft error mitigation in SHyLoC compression IP core implemented on Zynq SoC under heavy ion radiation
Exploiting dynamic partial reconfiguration for on-line on-demand testing of permanent faults in reconfigurable systems
Diagnosis of Analog Circuits by Using Multiple Transistors and Data Sampling
A New Functional Fault Model for FPGA Application-Oriented Testing
Power-aware Test Scheduling for IEEE 1687 Networks with Multiple Power Domains
Error Tolerance of DNA Self-Healing Assemblies by Puncturing
Shortest path reduction in a class of uniform fault tolerant networks
SAT-based code synthesis for fault-secure circuits
Creating Defect Tolerance in Microfluidic Capacitive/Photonic Biosensors
Charge Sharing Fault Detection for CMOS Domino Logic Circuits
Fatal Fault Probability Prediction for Array Based Designs
Increasing Current Testing Resolution
Test Pattern Decompression Using a Scan Chain
System-Level Dependability Analysis with RT-Level Fault Injection Accuracy
Spare Parts in Analog Circuits: A Filter Example
On meta-obfuscation of physical layouts to conceal design characteristics
Challenges Facing Practical DFT for MEMS
On Variable-Shift-Based Fault Compensation of Fuzzy Controllers
Testable and Fault Tolerant Design for FFT Networks
Using High-Level Profiling Data to Early Assess the Robustness of Digital Systems
TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip
A configurable board-level adaptive incremental diagnosis technique based on decision trees
A Region-Based Bit-Shuffling Approach Trading Hardware Cost and Fault Mitigation Efficiency
Error-Resilient Test Data Compression Using Tunstall Codes
Implementation and Reliability Evaluation of a ChaCha20 Stream Cipher Hardware Accelerator
Error-Correcting Goldschmidt Dividers Using Time Shared TMR
Alternative Approaches to Fault Detection in FSMs
Dependability Analysis and Assessment of Approximate Membership Query XOR Filters
ABL-Tree: A Constant Diameter Interconnection Network for Reconfigurable Processor Arrays Capable of Distributed Communication
Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits
Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level
Experimental study and analysis of soft and permanent errors in digital cameras
Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes
DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture
Methodologies and Algorithms for Testing Switch-Based NoC Interconnects
An energy-efficient and robust millimeter-wave Wireless Network-on-Chip architecture
A Fault-Tolerance Strategy for an FPGA-Based Multi-stage Interconnection Network in a Multi-sensor System for Space Application
Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator
Analysis and Improvement of Resilience for Long Short-Term Memory Neural Networks
Implementing Fault Injection and Tolerance Mechanisms in Multiprocessor Systems
Analyzing circuit vulnerability to hardware Trojan insertion at the behavioral level
Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm
A Statistical Approach To Identify Semiconductor Process Equipment Related Yield Problems
A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits
An adaptive routing algorithm to improve lifetime reliability in NoCs architecture
A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test
Optimization of Wafer Scale H-Tree Clock Distribution Network Based on a New Statistical Skew Model
Variation-tolerant cache by two-layer error control codes
A row-based FPGA for single and multiple stuck-at fault detection
Fault Secure Encoder and Decoder for Memory Applications
Improved Yield Model for Submicron Domain
Yield Enhancement by Multi-level Linear Modeling of Non-Idealities in an Interpolated Flash ADCs
A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault Coverage
Towards a Comprehensive SET Analysis Flow for VLSI Circuits using Static Timing Analysis
Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance
Design Space Exploration for the Design of Reliable
AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout
Implementing a Self-Checking Neural System for Photon Event Identification by SRAM-Based FPGAs
A Technique for Modular Design of Self-Checking Carry-Select Adder
Fault Diagnosis of Analog Circuits Based on Adaptive Test and Output Characteristics
A New Test Methodology For DNL Error In Flash ADC's
Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs
A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT
Triggering Trojans in SRAM circuits with X-propagation
Fault tolerant and highly adaptive routing for 2D NoCs
Recovery During Concurrent On-Line Testing of Identical Circuits
An On-Chip Detection Circuit for the Verification of IC Supply Connections
Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches
Low-level error recovery mechanism for self-checking sequential circuits
Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis
Reconfigurable architectures for mesh-arrays with PE and link faults
Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits
Laser Fault Injection on RO-Based PUFs Implemented on FPGA
Fast single-FPGA fault injection platform
Dual-edge-triggered FF with timing error detection capability
Design Scan Test Strategy for Single Phase Dynamic Circuits
Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences
Single Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory Systems
Automatic Detection of Spatial Signature on Wafermaps in a High Volume Production
Special Session: SE-UVM, an Integrated Simulation Environment for Single Event Induced Failures Characterization and its Application to the CV32E40P Processor
Trade-offs between yield and reliability enhancement [VLSI]
Fast, Minimal Decoding Complexity, System Level, Binary Systematic (41, 32) Single-Error-Correcting Codes for On-Chip DRAM Applications
Analyzing BIST Robustness
Single fault masking logic designs with error correcting codes
Experimental Results from Iddf Testing
Preemptive multi-bit IJTAG testing with reconfigurable infrastructure
Characterization of Gain Enhanced In-Field Defects in Digital Imagers
A Fault-Tolerant Active Pixel Sensor to Correct In-Field Hot Pixel Defects
Improved image accuracy in Hot Pixel degraded digital cameras
A Probabilistic Approach to Diagnose SETs
Improving the Detectability of Resistive Open Faults in Scan Cells
Combined software and hardware techniques for the design of reliable IP processors
Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks
Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities
FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip
A Sharable Built-in Self-Repair for Semiconductor Memories with 2-D Redundancy Schema
Cross-layer fault-tolerant design of real-time systems
Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs
Highly Efficient Layered Syndrome-based Double Error Correction Utilizing Current Summing in RRAM Cells to Simplify Decoder
Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits
Lifetime reliability characterization of N/MEMS used in power gating of digital integrated circuits
Systematic AUED Codes for Self-Checking Architectures
Testing and Reliability of Spiking Neural Networks: A Review of the State-of-the-Art
Non-invasive I2C Hardware Trojan Attack Vector
Evaluations of Burst Error Recovery for VF Arithmetic Coding
System-Level Analysis of Fault Effects in an Automotive Environment
Fault-Tolerant Wormhole Switching with Backtracking Capability
Reconfiguration in 3D Meshes
High performance fault tolerance through predictive instruction re-execution
Analyzing the Sensitivity to Faults of Synchronization Primitives
A Cost Model for VLSI / MCM Systems
Data Compression for System-on-Chip Testing Using ATE
SIED: Software Implemented Error Detection
Exploiting Intel TSX for fault-tolerant execution in safety-critical systems
Approximation of critical area of ICs with simple parameters extracted from the layout
Optimizing Software Self-Test Pattern Generation for Specific Components
Improving X-tolerant combinational output compaction via input rotation
Impact of mid-bond testing in 3D stacked ICs
Self-Repairing in a Micro-Programmed Processor for Dependable Applications
Complementary Resistive Switch Sensing
Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders
The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, October 17-19, 1994, Montréal, Quebec, Canada, Proceedings
Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits
Latest Trends in Hardware Security and Privacy
A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-on-Chip
Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography
SET Fault Tolerant Combinational Circuits Based on Majority Logic
Error recovery through partial value similarity
A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor design
Performance-Based and Aging-Aware Resource Allocation for Concurrent GPU Applications
Postprocessing Procedure for Reducing the Faulty Switching Activity of a Low-Power Test Set
Duplication Based One-to-Many Coding for Trojan HW Detection
A Reliable Reconfiguration Controller for Fault-Tolerant Embedded Systems on Multi-FPGA Platforms
Investigating the effects of process variations and system workloads on endurance of non-volatile caches
Volume management for fault-tolerant continuous-flow microfluidics
Application-Dependent Testing of FPGA Interconnects
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell
An Incremental Approach to Functional Diagnosis
Quantitative Analysis of In-Field Defects in Image Sensor Arrays
Test of Interconnection Opens Considering Coupling Signals
A Reconfigurable WSI Massively Data-Parallel Processing Device for Cost-Effective 3D Sensor Data Processing
Checkpointing of Rectilinear Growth in DNA Self-Assembly
Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs
A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems
RADPlace: A Timing-aware RAdiation-Hardening Detailed Placement Scheme Satisfying TMR Spacing Constraints
Quality-Effective Repair of Multichip Module Systems
A Step Response Based Mixed-Signal BIST Approach
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
Totally defect-tolerant arrays capable of quick broadcasting
2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2013, New York City, NY, USA, October 2-4, 2013
A Practical Approach to Single Event Transients Analysis for Highly Complex Designs
Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories
A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy
Reliability Analysis of a Low-Cost CCSDS 123 Hyperspectral Image Compressor
On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter
A Novel Error Detection and Correction Technique for RNS Based FIR Filters
A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuit
Spatial and Temporal Data Path Remapping for Fault-Tolerant Coarse-Grained Reconfigurable Architectures
Recovery Mechanisms for Dual Core Architectures
Effective Post-BIST Fault Diagnosis for Multiple Faults
An Experimental Comparison of RISC-V Processors: Performance, Power, Area and Security - Special Session Paper-
Design of a Self-Correcting Active Pixel Sensor
A Novel Methodology for Functional Test Data Compression
Analog Test Interface for IEEE 1687 Employing Split SAR Architecture to Support Embedded Instrument Dependability Applications
Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs
Soft-Error Detection through Software Fault-Tolerance Techniques
Detecting intermittent resistive faults in digital CMOS circuits
System Reliabilities When Using Triple Modular Redundancy in Quantum-Dot Cellular Automata
An Emulation Platform for Evaluating the Reliability of Deep Neural Networks
Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test Configurations
Complementary Formal Approaches for Dependability Analysis
The Filter Checker: An Active Verification Management Approach
Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System
Concurrent testing of VLSI digital signal processors using mutation based testing
BIST Module for Mixed-Signal Circuits
Simulation-based evaluation of frequency upscaled operation of exact/approximate ripple carry adders
An efficient High-Volume Production Performance Screening using On-Chip Ring Oscillators
Fast Dynamic Device Authentication Based on Lorenz Chaotic Systems
Design for Testability to Achieve High Test Coverage - A Case Study
Fault Injection in VHDL Descriptions and Emulation
Modeling Yield of Self-Healing Carbon Nanotubes/Silicon-Nanowire FET-based Nanoarray
A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip
QuardTropy: Detecting and Quantifying Unauthorized Information Leakage in Hardware Designs using g-entropy
Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOS
Noise Effects on Performance of Low Power Design Schemes in Deep Submicron Regime
Single Event Induced Double Node Upset Tolerant Latch
Special Session: Exploring the Potential of Versal ACAP: Advancing Onboard Edge AI for Spacecraft
Error Detect Logic Resulting in Faster Address Generate and Decode for Caches
An Exploration of Microprocessor Self-Test Optimisation Based On Safe Faults
Partially Duplicated Code-Disjoint Carry-Skip Adder
On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits
Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures
A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network
Fault detection and fault tolerance issues at CMOS level through AUED encoding
A New Soft-Error Resilient Voltage-Mode Quaternary Latch
Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model
Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis
Reliable Logic Circuits with Byte Error Control Codes: A Feasibility Study
Machine learning-based techniques for incremental functional diagnosis: A comparative analysis
SEU sensitivity and modeling using pico-second pulsed laser stimulation of a D Flip-Flop in 40 nm CMOS technology
Secure Split-Test for preventing IC piracy by untrusted foundry and assembly
Toggle-Masking for Test-per-Scan VLSI Circuits
Specification-Driven Test Design for Analog Circuits
Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs
Reliability Assessment of AMD MicroBlaze-V TMR Architecture Using Fault Injection
Neural Networks for Multiple Fault Diagnosis in Analog Circuits
Block Implementation of Fault-Tolerant LMS Adaptive FIR Filters
On-Line Analysis and Perturbation of CAN Networks
NoC Interconnect Yield Improvement Using Crosspoint Redundancy
Complete Tests in Algorithm-Based Fault-Tolerant Matrix Operations on Processor Arrays
Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field
A Probabilistic Method to Detect Anomalies in Embedded Systems
Low pin count DfT technique for RFID ICs
Compression of VLSI Test Data by Arithmetic Coding
IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration
Design and analysis of an approximate 2D convolver
Operational Age Estimation of ICs using Gaussian Process Regression
On the Analysis of Real-time Operating System Reliability in Embedded Systems
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2025, Barcelona, Spain, October 21-23, 2025
On Generating Tests to Cover Diverse Worst-Case Timing Corners
Power Consumption in Fast Dividers Using Time Shared TMR
Faults affecting the control blocks of PV arrays and techniques for their concurrent detection
CSST: Preventing distribution of unlicensed and rejected ICs by untrusted foundry and assembly
Soft Error Hardening for Asynchronous Circuits
45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control
Error Correction Codes for SEU and SEFI Tolerant Memory Systems
Reliability and Performance Evaluation of a Fault-Tolerant MPSoC Interconnection Architecture
A dynamic reliability management framework for heterogeneous multicore systems
Performance sensor for tolerance and predictive detection of delay-faults
Combining Cluster Sampling and ACE analysis to improve fault-injection based reliability evaluation of GPU-based systems
Reliability Modeling and Assurance of Clockless Wave Pipeline
Injecting Bit Flip Faults by Means of a Purely Software Approach: A Case Studied
Online TSV health monitoring and built-in self-repair to overcome aging
17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings
Defect Characterization and Tolerance of QCA Sequential Devices and Circuits
Designing Self-Checking FPGAs through Error Detection Codes
Evaluating CLB designs under multiple SETs in SRAM-based FPGAs
Special Session: Reliability and Performance Evaluation of a RISC-V Vector Extension Unit for Vector Multiplication
Concurrent Error Detection in Sequential Circuits Implemented Using Embedded Memory of LUT-Based FPGAs
Validation Challenges in Recent Trends of Power Management in Microprocessors
A Reliability-Aware Partitioner for Multi-FPGA Platforms
Effects of online fault detection mechanisms on Probabilistic Timing Analysis
A Defect-Tolerant WSI File Memory System Using Address Permutation Scheme for Spare Allocation
Programmable MBIST Merging FSM and Microcode Techniques Using Macro Commands
Analog BIST Generator for ADC Testing
1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 1996, Boston, MA, USA, November 6-8, 1996
The Future of Test - Product Integration and its Impact on Test
Evaluating Data Encryption Effects on the Resilience of an Artificial Neural Network
Concurrent Error Detection of Polynomial Basis Multiplication over Extension Fields using a Multiple-bit Parity Scheme
An Efficient Security Closure Methodology for EM-based Attacks on Power Grid Structures
Process Variations and their Impact on Circuit Operation
Efficient Function Mapping in Nanoscale Crossbar Architecture
Procedure Call Duplication: Minimization of Energy Consumption with Constrained Error Detection Latency
Sensitivity and Reliability Evaluation for Mixed-Signal ICs under Electromigration and Hot-Carrier Effects
A Study of eSRAM Testability
Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits
Reliable hash trees for post-quantum stateless cryptographic hash-based signatures
Impact of test compression on power supply noise control
Optimal choice of arithmetic compactors for mixed-signal systems
C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications
A Novel Pulse Echo Correlation Tool for Transmission Path Testing and Fault Finding using Pseudorandom Binary Sequences
CoBRA: Low cost compensation of TSV failures in 3D-NoC
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023, Juan-Les-Pins, France, October 3-5, 2023
Stratified Testing of Multichip Module Systems under Uneven Known-Good-Yield
Zero-Overhead Protection for CNN Weights
Dirty data vulnerability mitigation by means of sharing management in cache coherence protocols
Highly Testable and Compact 1-out-of-n CMOS Checkers
Prediction of gate delay variation for CNFET under CNT density variation
A Tile-Based Error Model for Forward Growth of DNA Self-Assembly
Early estimation of aging in the design flow of integrated circuits through a programmable hardware module
A smart Trojan circuit and smart attack method in AES encryption circuits
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Analyzing the Impact of Fault Tolerant BIST for VLSI Design
A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SET
A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard
HPMA-NTRU: High-Performance Polynomial Multiplication Accelerator for NTRU
Redundant Faults in TSC Networks: Definition and Removal
On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits
Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power
Configuration-Specific Test Pattern Extraction for Field Programmable Gate Arrays